diff options
Diffstat (limited to 'test/CodeGen/AArch64/GlobalISel')
69 files changed, 0 insertions, 10198 deletions
diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll deleted file mode 100644 index a70cee0efcb6..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - -target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" -target triple = "aarch64-apple-ios9.0" - -; CHECK-LABEL: name: test_varargs -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00 -; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12 -; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3 -; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1 -; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4 -; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00 -; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00 - -; CHECK: %w0 = COPY [[ANSWER]] -; CHECK: %d0 = COPY [[D_ONE]] -; CHECK: %x1 = COPY [[TWELVE]] -; CHECK: G_STORE [[THREE]](s8), {{%[0-9]+}}(p0) :: (store 1 into stack, align 0) -; CHECK: G_STORE [[ONE]](s16), {{%[0-9]+}}(p0) :: (store 2 into stack + 8, align 0) -; CHECK: G_STORE [[FOUR]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 16, align 0) -; CHECK: G_STORE [[F_ONE]](s32), {{%[0-9]+}}(p0) :: (store 4 into stack + 24, align 0) -; CHECK: G_STORE [[TWO]](s64), {{%[0-9]+}}(p0) :: (store 8 into stack + 32, align 0) -declare void @varargs(i32, double, i64, ...) -define void @test_varargs() { - call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0) - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll deleted file mode 100644 index 59b9bb49f0ee..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll +++ /dev/null @@ -1,96 +0,0 @@ -; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - -target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" -target triple = "aarch64-linux-gnu" - -; CHECK-LABEL: name: args_i32 -; CHECK: %[[ARG0:[0-9]+]](s32) = COPY %w0 -; CHECK: %{{[0-9]+}}(s32) = COPY %w1 -; CHECK: %{{[0-9]+}}(s32) = COPY %w2 -; CHECK: %{{[0-9]+}}(s32) = COPY %w3 -; CHECK: %{{[0-9]+}}(s32) = COPY %w4 -; CHECK: %{{[0-9]+}}(s32) = COPY %w5 -; CHECK: %{{[0-9]+}}(s32) = COPY %w6 -; CHECK: %{{[0-9]+}}(s32) = COPY %w7 -; CHECK: %w0 = COPY %[[ARG0]] - -define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3, - i32 %w4, i32 %w5, i32 %w6, i32 %w7) { - ret i32 %w0 -} - -; CHECK-LABEL: name: args_i64 -; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %x0 -; CHECK: %{{[0-9]+}}(s64) = COPY %x1 -; CHECK: %{{[0-9]+}}(s64) = COPY %x2 -; CHECK: %{{[0-9]+}}(s64) = COPY %x3 -; CHECK: %{{[0-9]+}}(s64) = COPY %x4 -; CHECK: %{{[0-9]+}}(s64) = COPY %x5 -; CHECK: %{{[0-9]+}}(s64) = COPY %x6 -; CHECK: %{{[0-9]+}}(s64) = COPY %x7 -; CHECK: %x0 = COPY %[[ARG0]] -define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3, - i64 %x4, i64 %x5, i64 %x6, i64 %x7) { - ret i64 %x0 -} - - -; CHECK-LABEL: name: args_ptrs -; CHECK: %[[ARG0:[0-9]+]](p0) = COPY %x0 -; CHECK: %{{[0-9]+}}(p0) = COPY %x1 -; CHECK: %{{[0-9]+}}(p0) = COPY %x2 -; CHECK: %{{[0-9]+}}(p0) = COPY %x3 -; CHECK: %{{[0-9]+}}(p0) = COPY %x4 -; CHECK: %{{[0-9]+}}(p0) = COPY %x5 -; CHECK: %{{[0-9]+}}(p0) = COPY %x6 -; CHECK: %{{[0-9]+}}(p0) = COPY %x7 -; CHECK: %x0 = COPY %[[ARG0]] -define i8* @args_ptrs(i8* %x0, i16* %x1, <2 x i8>* %x2, {i8, i16, i32}* %x3, - [3 x float]* %x4, double* %x5, i8* %x6, i8* %x7) { - ret i8* %x0 -} - -; CHECK-LABEL: name: args_arr -; CHECK: %[[ARG0:[0-9]+]](s64) = COPY %d0 -; CHECK: %d0 = COPY %[[ARG0]] -define [1 x double] @args_arr([1 x double] %d0) { - ret [1 x double] %d0 -} - -; CHECK-LABEL: name: test_varargs -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: [[D_ONE:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00 -; CHECK: [[TWELVE:%[0-9]+]](s64) = G_CONSTANT i64 12 -; CHECK: [[THREE:%[0-9]+]](s8) = G_CONSTANT i8 3 -; CHECK: [[ONE:%[0-9]+]](s16) = G_CONSTANT i16 1 -; CHECK: [[FOUR:%[0-9]+]](s32) = G_CONSTANT i32 4 -; CHECK: [[F_ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00 -; CHECK: [[TWO:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00 - -; CHECK: %w0 = COPY [[ANSWER]] -; CHECK: %d0 = COPY [[D_ONE]] -; CHECK: %x1 = COPY [[TWELVE]] -; CHECK: %w2 = COPY [[THREE]](s8) -; CHECK: %w3 = COPY [[ONE]](s16) -; CHECK: %w4 = COPY [[FOUR]](s32) -; CHECK: %s1 = COPY [[F_ONE]](s32) -; CHECK: %d2 = COPY [[TWO]](s64) -declare void @varargs(i32, double, i64, ...) -define void @test_varargs() { - call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0) - ret void -} - -; signext/zeroext parameters on the stack: not part of any real ABI as far as I -; know, but ELF currently allocates 8 bytes for a signext parameter on the -; stack. The ADJCALLSTACK ops should reflect this, even if the difference is -; theoretical. -declare void @stack_ext_needed([8 x i64], i8 signext %in) -; CHECK-LABEL: name: test_stack_ext_needed -; CHECK: ADJCALLSTACKDOWN 8 -; CHECK: BL @stack_ext_needed -; CHECK: ADJCALLSTACKUP 8 -define void @test_stack_ext_needed() { - call void @stack_ext_needed([8 x i64] undef, i8 signext 42) - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll deleted file mode 100644 index 71ea9d54f647..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ /dev/null @@ -1,172 +0,0 @@ -; RUN: not llc -O0 -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR -; RUN: llc -O0 -global-isel -global-isel-abort=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=FALLBACK -; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err -; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out -; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err -; This file checks that the fallback path to selection dag works. -; The test is fragile in the sense that it must be updated to expose -; something that fails with global-isel. -; When we cannot produce a test case anymore, that means we can remove -; the fallback path. - -target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" -target triple = "aarch64--" - -; We use __fixunstfti as the common denominator for __fixunstfti on Linux and -; ___fixunstfti on iOS -; ERROR: unable to lower arguments: i128 (i128)* (in function: ABIi128) -; FALLBACK: ldr q0, -; FALLBACK-NEXT: bl __fixunstfti -; -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower arguments: i128 (i128)* (in function: ABIi128) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for ABIi128 -; FALLBACK-WITH-REPORT-OUT-LABEL: ABIi128: -; FALLBACK-WITH-REPORT-OUT: ldr q0, -; FALLBACK-WITH-REPORT-OUT-NEXT: bl __fixunstfti -define i128 @ABIi128(i128 %arg1) { - %farg1 = bitcast i128 %arg1 to fp128 - %res = fptoui fp128 %farg1 to i128 - ret i128 %res -} - -; It happens that we don't handle ConstantArray instances yet during -; translation. Any other constant would be fine too. - -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate constant: [1 x double] (in function: constant) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for constant -; FALLBACK-WITH-REPORT-OUT-LABEL: constant: -; FALLBACK-WITH-REPORT-OUT: fmov d0, #1.0 -define [1 x double] @constant() { - ret [1 x double] [double 1.0] -} - - ; The key problem here is that we may fail to create an MBB referenced by a - ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things - ; happen. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: G_STORE %vreg4, %vreg2; mem:ST4[%addr] GPR:%vreg4,%vreg2 (in function: pending_phis) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis -; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis: -define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) { - br i1 %tst, label %true, label %false - -end: - %res = phi i32 [%val, %true], [42, %false] - ret i32 %res - -true: - store atomic i32 42, i32* %addr seq_cst, align 4 - br label %end - -false: - br label %end - -} - - ; General legalizer inability to handle types whose size wasn't a power of 2. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(s42) = G_LOAD %vreg0; mem:LD6[%addr](align=8) (in function: odd_type) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type -; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type: -define void @odd_type(i42* %addr) { - %val42 = load i42, i42* %addr - ret void -} - -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector -; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector: -define void @odd_vector(<7 x i32>* %addr) { - %vec = load <7 x i32>, <7 x i32>* %addr - ret void -} - - ; RegBankSelect crashed when given invalid mappings, and AArch64's - ; implementation produce valid-but-nonsense mappings for G_SEQUENCE. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping -; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping: -define void @sequence_mapping([2 x i64] %in) { - ret void -} - - ; Legalizer was asserting when it enountered an unexpected default action. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default -; FALLBACK-WITH-REPORT-LABEL: legal_default: -define void @legal_default([8 x i8] %in) { - insertvalue { [4 x i8], [8 x i8], [4 x i8] } undef, [8 x i8] %in, 1 - ret void -} - - ; AArch64 was asserting instead of returning an invalid mapping for unknown - ; sizes. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: ret: ' ret i128 undef' (in function: sequence_sizes) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_sizes -; FALLBACK-WITH-REPORT-LABEL: sequence_sizes: -define i128 @sequence_sizes([8 x i8] %in) { - ret i128 undef -} - -; Just to make sure we don't accidentally emit a normal load/store. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: %vreg2<def>(s64) = G_LOAD %vreg0; mem:LD8[%addr] GPR:%vreg2,%vreg0 (in function: atomic_ops) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops -; FALLBACK-WITH-REPORT-LABEL: atomic_ops: -define i64 @atomic_ops(i64* %addr) { - store atomic i64 0, i64* %addr unordered, align 8 - %res = load atomic i64, i64* %addr seq_cst, align 8 - ret i64 %res -} - -; Make sure we don't mess up metadata arguments. -declare void @llvm.write_register.i64(metadata, i64) - -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call: ' call void @llvm.write_register.i64(metadata !0, i64 0)' (in function: test_write_register_intrin) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin -; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin: -define void @test_write_register_intrin() { - call void @llvm.write_register.i64(metadata !{!"sp"}, i64 0) - ret void -} - -@_ZTIi = external global i8* -declare i32 @__gxx_personality_v0(...) - -; Check that we fallback on invoke translation failures. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: invoke: ' invoke void %callee(i128 0) -; FALLBACK-WITH-REPORT-NEXT: to label %continue unwind label %broken' (in function: invoke_weird_type) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for invoke_weird_type -; FALLBACK-WITH-REPORT-OUT-LABEL: invoke_weird_type: -define void @invoke_weird_type(void(i128)* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { - invoke void %callee(i128 0) - to label %continue unwind label %broken - -broken: - landingpad { i8*, i32 } catch i8* bitcast(i8** @_ZTIi to i8*) - ret void - -continue: - ret void -} - -; Check that we fallback on invoke translation failures. -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(s128) = G_FCONSTANT quad 2 -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump -; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump: -define fp128 @test_quad_dump() { - ret fp128 0xL00000000000000004000000000000000 -} - -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(p0) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg2; (in function: vector_of_pointers_extractelement) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: -define void @vector_of_pointers_extractelement() { - %dummy = extractelement <2 x i16*> undef, i32 0 - ret void -} - -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(<2 x p0>) = G_INSERT_VECTOR_ELT %vreg1, %vreg2, %vreg3; (in function: vector_of_pointers_insertelement -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: -define void @vector_of_pointers_insertelement() { - %dummy = insertelement <2 x i16*> undef, i16* null, i32 0 - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll deleted file mode 100644 index 006308641184..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios %s -stop-after=irtranslator -o - -global-isel | FileCheck %s - - -; CHECK: name: test_stack_guard - -; CHECK: stack: -; CHECK: - { id: 0, name: StackGuardSlot, offset: 0, size: 8, alignment: 8 } -; CHECK-NOT: id: 1 - -; CHECK: [[GUARD_SLOT:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.StackGuardSlot -; CHECK: [[GUARD:%[0-9]+]](p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__stack_chk_guard) -; CHECK: G_STORE [[GUARD]](p0), [[GUARD_SLOT]](p0) :: (volatile store 8 into %stack.0.StackGuardSlot) -declare void @llvm.stackprotector(i8*, i8**) -define void @test_stack_guard_remat2() { - %StackGuardSlot = alloca i8* - call void @llvm.stackprotector(i8* undef, i8** %StackGuardSlot) - ret void -} - -@__stack_chk_guard = external global i64* diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll deleted file mode 100644 index 02848021dbc0..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ /dev/null @@ -1,1543 +0,0 @@ -; RUN: llc -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - -; This file checks that the translation from llvm IR to generic MachineInstr -; is correct. -target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" -target triple = "aarch64--" - -; Tests for add. -; CHECK-LABEL: name: addi64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_ADD [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @addi64(i64 %arg1, i64 %arg2) { - %res = add i64 %arg1, %arg2 - ret i64 %res -} - -; CHECK-LABEL: name: muli64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_MUL [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @muli64(i64 %arg1, i64 %arg2) { - %res = mul i64 %arg1, %arg2 - ret i64 %res -} - -; Tests for alloca -; CHECK-LABEL: name: allocai64 -; CHECK: stack: -; CHECK-NEXT: - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 } -; CHECK-NEXT: - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 } -; CHECK-NEXT: - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 } -; CHECK-NEXT: - { id: 3, name: ptr4, offset: 0, size: 1, alignment: 8 } -; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.0.ptr1 -; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.1.ptr2 -; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.2.ptr3 -; CHECK: %{{[0-9]+}}(p0) = G_FRAME_INDEX %stack.3.ptr4 -define void @allocai64() { - %ptr1 = alloca i64 - %ptr2 = alloca i64, align 1 - %ptr3 = alloca i64, i32 16 - %ptr4 = alloca [0 x i64] - ret void -} - -; Tests for br. -; CHECK-LABEL: name: uncondbr -; CHECK: body: -; -; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+}}.entry: -; -; Make sure we have one successor and only one. -; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+.bb2]](0x80000000) -; -; Check that we emit the correct branch. -; CHECK: G_BR %[[BB2]] -; -; Check that end contains the return instruction. -; CHECK: [[END:bb.[0-9]+.end]]: -; CHECK-NEXT: RET_ReallyLR -; -; CHECK: {{bb.[0-9]+}}.bb2: -; CHECK-NEXT: successors: %[[END]](0x80000000) -; CHECK: G_BR %[[END]] -define void @uncondbr() { -entry: - br label %bb2 -end: - ret void -bb2: - br label %end -} - -; CHECK-LABEL: name: uncondbr_fallthrough -; CHECK: body: -; CHECK: {{bb.[0-9]+}}.entry: -; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000) -; We don't emit a branch here, as we can fallthrough to the successor. -; CHECK-NOT: G_BR -; CHECK: [[END]]: -; CHECK-NEXT: RET_ReallyLR -define void @uncondbr_fallthrough() { -entry: - br label %end -end: - ret void -} - -; Tests for conditional br. -; CHECK-LABEL: name: condbr -; CHECK: body: -; -; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}): -; Make sure we have two successors -; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000), -; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000) -; -; CHECK: [[ADDR:%.*]](p0) = COPY %x0 -; -; Check that we emit the correct branch. -; CHECK: [[TST:%.*]](s1) = G_LOAD [[ADDR]](p0) -; CHECK: G_BRCOND [[TST]](s1), %[[TRUE]] -; CHECK: G_BR %[[FALSE]] -; -; Check that each successor contains the return instruction. -; CHECK: [[TRUE]]: -; CHECK-NEXT: RET_ReallyLR -; CHECK: [[FALSE]]: -; CHECK-NEXT: RET_ReallyLR -define void @condbr(i1* %tstaddr) { - %tst = load i1, i1* %tstaddr - br i1 %tst, label %true, label %false -true: - ret void -false: - ret void -} - -; Tests for switch. -; This gets lowered to a very straightforward sequence of comparisons for now. -; CHECK-LABEL: name: switch -; CHECK: body: -; -; CHECK: {{bb.[0-9]+.entry}}: -; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) -; CHECK: %0(s32) = COPY %w0 -; CHECK: %[[reg100:[0-9]+]](s32) = G_CONSTANT i32 100 -; CHECK: %[[reg200:[0-9]+]](s32) = G_CONSTANT i32 200 -; CHECK: %[[reg0:[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: %[[reg1:[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: %[[reg2:[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: %[[regicmp100:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg100]](s32), %0 -; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]] -; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]] -; -; CHECK: [[BB_NOTCASE100_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) -; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0 -; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]] -; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]] -; -; CHECK: [[BB_NOTCASE200_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000) -; CHECK: G_BR %[[BB_DEFAULT]] -; -; CHECK: [[BB_DEFAULT]]: -; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000) -; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]] -; CHECK: G_BR %[[BB_RET]] -; -; CHECK: [[BB_CASE100]]: -; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000) -; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]] -; CHECK: G_BR %[[BB_RET]] -; -; CHECK: [[BB_CASE200]]: -; CHECK-NEXT: successors: %[[BB_RET]](0x80000000) -; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]] -; -; CHECK: [[BB_RET]]: -; CHECK-NEXT: %[[regret:[0-9]+]](s32) = PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]] -; CHECK: %w0 = COPY %[[regret]](s32) -; CHECK: RET_ReallyLR implicit %w0 -; -define i32 @switch(i32 %argc) { -entry: - switch i32 %argc, label %default [ - i32 100, label %case100 - i32 200, label %case200 - ] - -default: - %tmp0 = add i32 %argc, 0 - br label %return - -case100: - %tmp1 = add i32 %argc, 1 - br label %return - -case200: - %tmp2 = add i32 %argc, 2 - br label %return - -return: - %res = phi i32 [ %tmp0, %default ], [ %tmp1, %case100 ], [ %tmp2, %case200 ] - ret i32 %res -} - - ; The switch lowering code changes the CFG, which means that the original - ; %entry block is no longer a predecessor for the phi instruction. We need to - ; use the correct lowered MachineBasicBlock instead. -; CHECK-LABEL: name: test_cfg_remap -; CHECK: {{bb.[0-9]+.entry}}: -; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000) -; CHECK: [[NOTCASE1_BLOCK]]: -; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000) -; CHECK: [[NOTCASE57_BLOCK]]: -; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000) -; CHECK: G_BR %[[PHI_BLOCK]] -; -; CHECK: [[PHI_BLOCK]]: -; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32), -; -define i32 @test_cfg_remap(i32 %in) { -entry: - switch i32 %in, label %phi.block [i32 1, label %next - i32 57, label %other] - -next: - br label %phi.block - -other: - ret i32 undef - -phi.block: - %res = phi i32 [1, %entry], [42, %next] - ret i32 %res -} - -; CHECK-LABEL: name: test_cfg_remap_multiple_preds -; CHECK: PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}.entry, [[ENTRY]](s32), %bb.{{[0-9]+}}.entry -define i32 @test_cfg_remap_multiple_preds(i32 %in) { -entry: - switch i32 %in, label %odd [i32 1, label %next - i32 57, label %other - i32 128, label %phi.block - i32 256, label %phi.block] -odd: - unreachable - -next: - br label %phi.block - -other: - ret i32 undef - -phi.block: - %res = phi i32 [1, %entry], [1, %entry], [42, %next] - ret i32 12 -} - -; Tests for indirect br. -; CHECK-LABEL: name: indirectbr -; CHECK: body: -; -; ABI/constant lowering and IR-level entry basic block. -; CHECK: {{bb.[0-9]+.entry}}: -; Make sure we have one successor -; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000) -; CHECK-NOT: G_BR -; -; Check basic block L1 has 2 successors: BBL1 and BBL2 -; CHECK: [[BB_L1]] (address-taken): -; CHECK-NEXT: successors: %[[BB_L1]](0x40000000), -; CHECK: %[[BB_L2:bb.[0-9]+.L2]](0x40000000) -; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0) -; -; Check basic block L2 is the return basic block -; CHECK: [[BB_L2]] (address-taken): -; CHECK-NEXT: RET_ReallyLR - -@indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8 - -define void @indirectbr() { -entry: - br label %L1 -L1: ; preds = %entry, %L1 - %i = phi i32 [ 0, %entry ], [ %inc, %L1 ] - %inc = add i32 %i, 1 - %idxprom = zext i32 %i to i64 - %arrayidx = getelementptr inbounds [3 x i8*], [3 x i8*]* @indirectbr.L, i64 0, i64 %idxprom - %brtarget = load i8*, i8** %arrayidx, align 8 - indirectbr i8* %brtarget, [label %L1, label %L2] -L2: ; preds = %L1 - ret void -} - -; Tests for or. -; CHECK-LABEL: name: ori64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_OR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @ori64(i64 %arg1, i64 %arg2) { - %res = or i64 %arg1, %arg2 - ret i64 %res -} - -; CHECK-LABEL: name: ori32 -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_OR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @ori32(i32 %arg1, i32 %arg2) { - %res = or i32 %arg1, %arg2 - ret i32 %res -} - -; Tests for xor. -; CHECK-LABEL: name: xori64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_XOR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @xori64(i64 %arg1, i64 %arg2) { - %res = xor i64 %arg1, %arg2 - ret i64 %res -} - -; CHECK-LABEL: name: xori32 -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_XOR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @xori32(i32 %arg1, i32 %arg2) { - %res = xor i32 %arg1, %arg2 - ret i32 %res -} - -; Tests for and. -; CHECK-LABEL: name: andi64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_AND [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @andi64(i64 %arg1, i64 %arg2) { - %res = and i64 %arg1, %arg2 - ret i64 %res -} - -; CHECK-LABEL: name: andi32 -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_AND [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @andi32(i32 %arg1, i32 %arg2) { - %res = and i32 %arg1, %arg2 - ret i32 %res -} - -; Tests for sub. -; CHECK-LABEL: name: subi64 -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s64) = COPY %x1 -; CHECK-NEXT: [[RES:%[0-9]+]](s64) = G_SUB [[ARG1]], [[ARG2]] -; CHECK-NEXT: %x0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %x0 -define i64 @subi64(i64 %arg1, i64 %arg2) { - %res = sub i64 %arg1, %arg2 - ret i64 %res -} - -; CHECK-LABEL: name: subi32 -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SUB [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @subi32(i32 %arg1, i32 %arg2) { - %res = sub i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: ptrtoint -; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[ARG1]] -; CHECK: %x0 = COPY [[RES]] -; CHECK: RET_ReallyLR implicit %x0 -define i64 @ptrtoint(i64* %a) { - %val = ptrtoint i64* %a to i64 - ret i64 %val -} - -; CHECK-LABEL: name: inttoptr -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[RES:%[0-9]+]](p0) = G_INTTOPTR [[ARG1]] -; CHECK: %x0 = COPY [[RES]] -; CHECK: RET_ReallyLR implicit %x0 -define i64* @inttoptr(i64 %a) { - %val = inttoptr i64 %a to i64* - ret i64* %val -} - -; CHECK-LABEL: name: trivial_bitcast -; CHECK: [[ARG1:%[0-9]+]](p0) = COPY %x0 -; CHECK: %x0 = COPY [[ARG1]] -; CHECK: RET_ReallyLR implicit %x0 -define i64* @trivial_bitcast(i8* %a) { - %val = bitcast i8* %a to i64* - ret i64* %val -} - -; CHECK-LABEL: name: trivial_bitcast_with_copy -; CHECK: [[A:%[0-9]+]](p0) = COPY %x0 -; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]] - -; CHECK: [[END:bb\.[0-9]+.end]]: - -; CHECK: [[CAST]]: -; CHECK: {{%[0-9]+}}(p0) = COPY [[A]] -; CHECK: G_BR %[[END]] -define i64* @trivial_bitcast_with_copy(i8* %a) { - br label %cast - -end: - ret i64* %val - -cast: - %val = bitcast i8* %a to i64* - br label %end -} - -; CHECK-LABEL: name: bitcast -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[RES1:%[0-9]+]](<2 x s32>) = G_BITCAST [[ARG1]] -; CHECK: [[RES2:%[0-9]+]](s64) = G_BITCAST [[RES1]] -; CHECK: %x0 = COPY [[RES2]] -; CHECK: RET_ReallyLR implicit %x0 -define i64 @bitcast(i64 %a) { - %res1 = bitcast i64 %a to <2 x i32> - %res2 = bitcast <2 x i32> %res1 to i64 - ret i64 %res2 -} - -; CHECK-LABEL: name: trunc -; CHECK: [[ARG1:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_LOAD -; CHECK: [[RES1:%[0-9]+]](s8) = G_TRUNC [[ARG1]] -; CHECK: [[RES2:%[0-9]+]](<4 x s16>) = G_TRUNC [[VEC]] -define void @trunc(i64 %a) { - %vecptr = alloca <4 x i32> - %vec = load <4 x i32>, <4 x i32>* %vecptr - %res1 = trunc i64 %a to i8 - %res2 = trunc <4 x i32> %vec to <4 x i16> - ret void -} - -; CHECK-LABEL: name: load -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1 -; CHECK: [[VAL1:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 16) -; CHECK: [[VAL2:%[0-9]+]](s64) = G_LOAD [[ADDR42]](p42) :: (load 8 from %ir.addr42) -; CHECK: [[SUM2:%.*]](s64) = G_ADD [[VAL1]], [[VAL2]] -; CHECK: [[VAL3:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (volatile load 8 from %ir.addr) -; CHECK: [[SUM3:%[0-9]+]](s64) = G_ADD [[SUM2]], [[VAL3]] -; CHECK: %x0 = COPY [[SUM3]] -; CHECK: RET_ReallyLR implicit %x0 -define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) { - %val1 = load i64, i64* %addr, align 16 - - %val2 = load i64, i64 addrspace(42)* %addr42 - %sum2 = add i64 %val1, %val2 - - %val3 = load volatile i64, i64* %addr - %sum3 = add i64 %sum2, %val3 - ret i64 %sum3 -} - -; CHECK-LABEL: name: store -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[ADDR42:%[0-9]+]](p42) = COPY %x1 -; CHECK: [[VAL1:%[0-9]+]](s64) = COPY %x2 -; CHECK: [[VAL2:%[0-9]+]](s64) = COPY %x3 -; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 16) -; CHECK: G_STORE [[VAL2]](s64), [[ADDR42]](p42) :: (store 8 into %ir.addr42) -; CHECK: G_STORE [[VAL1]](s64), [[ADDR]](p0) :: (volatile store 8 into %ir.addr) -; CHECK: RET_ReallyLR -define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2) { - store i64 %val1, i64* %addr, align 16 - store i64 %val2, i64 addrspace(42)* %addr42 - store volatile i64 %val1, i64* %addr - %sum = add i64 %val1, %val2 - ret void -} - -; CHECK-LABEL: name: intrinsics -; CHECK: [[CUR:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[BITS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[CREG:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[PTR:%[0-9]+]](p0) = G_INTRINSIC intrinsic(@llvm.returnaddress), [[CREG]] -; CHECK: [[PTR_VEC:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr.vec -; CHECK: [[VEC:%[0-9]+]](<8 x s8>) = G_LOAD [[PTR_VEC]] -; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), [[VEC]](<8 x s8>), [[VEC]](<8 x s8>), [[PTR]](p0) -; CHECK: RET_ReallyLR -declare i8* @llvm.returnaddress(i32) -declare void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*) -declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>*) -define void @intrinsics(i32 %cur, i32 %bits) { - %ptr = call i8* @llvm.returnaddress(i32 0) - %ptr.vec = alloca <8 x i8> - %vec = load <8 x i8>, <8 x i8>* %ptr.vec - call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec, <8 x i8> %vec, i8* %ptr) - ret void -} - -; CHECK-LABEL: name: test_phi -; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]] -; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]] - -; CHECK: [[TRUE]]: -; CHECK: [[RES1:%[0-9]+]](s32) = G_LOAD - -; CHECK: [[FALSE]]: -; CHECK: [[RES2:%[0-9]+]](s32) = G_LOAD - -; CHECK: [[RES:%[0-9]+]](s32) = PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]] -; CHECK: %w0 = COPY [[RES]] -define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) { - br i1 %tst, label %true, label %false - -true: - %res1 = load i32, i32* %addr1 - br label %end - -false: - %res2 = load i32, i32* %addr2 - br label %end - -end: - %res = phi i32 [%res1, %true], [%res2, %false] - ret i32 %res -} - -; CHECK-LABEL: name: unreachable -; CHECK: G_ADD -; CHECK-NEXT: {{^$}} -; CHECK-NEXT: ... -define void @unreachable(i32 %a) { - %sum = add i32 %a, %a - unreachable -} - - ; It's important that constants are after argument passing, but before the - ; rest of the entry block. -; CHECK-LABEL: name: constant_int -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[ONE:%[0-9]+]](s32) = G_CONSTANT i32 1 - -; CHECK: {{bb.[0-9]+}}.next: -; CHECK: [[SUM1:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]] -; CHECK: [[SUM2:%[0-9]+]](s32) = G_ADD [[IN]], [[ONE]] -; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[SUM1]], [[SUM2]] -; CHECK: %w0 = COPY [[RES]] - -define i32 @constant_int(i32 %in) { - br label %next - -next: - %sum1 = add i32 %in, 1 - %sum2 = add i32 %in, 1 - %res = add i32 %sum1, %sum2 - ret i32 %res -} - -; CHECK-LABEL: name: constant_int_start -; CHECK: [[TWO:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: [[RES:%[0-9]+]](s32) = G_ADD [[TWO]], [[ANSWER]] -define i32 @constant_int_start() { - %res = add i32 2, 42 - ret i32 %res -} - -; CHECK-LABEL: name: test_undef -; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF -; CHECK: %w0 = COPY [[UNDEF]] -define i32 @test_undef() { - ret i32 undef -} - -; CHECK-LABEL: name: test_constant_inttoptr -; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1 -; CHECK: [[PTR:%[0-9]+]](p0) = G_INTTOPTR [[ONE]] -; CHECK: %x0 = COPY [[PTR]] -define i8* @test_constant_inttoptr() { - ret i8* inttoptr(i64 1 to i8*) -} - - ; This failed purely because the Constant -> VReg map was kept across - ; functions, so reuse the "i64 1" from above. -; CHECK-LABEL: name: test_reused_constant -; CHECK: [[ONE:%[0-9]+]](s64) = G_CONSTANT i64 1 -; CHECK: %x0 = COPY [[ONE]] -define i64 @test_reused_constant() { - ret i64 1 -} - -; CHECK-LABEL: name: test_sext -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RES:%[0-9]+]](s64) = G_SEXT [[IN]] -; CHECK: %x0 = COPY [[RES]] -define i64 @test_sext(i32 %in) { - %res = sext i32 %in to i64 - ret i64 %res -} - -; CHECK-LABEL: name: test_zext -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RES:%[0-9]+]](s64) = G_ZEXT [[IN]] -; CHECK: %x0 = COPY [[RES]] -define i64 @test_zext(i32 %in) { - %res = zext i32 %in to i64 - ret i64 %res -} - -; CHECK-LABEL: name: test_shl -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SHL [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_shl(i32 %arg1, i32 %arg2) { - %res = shl i32 %arg1, %arg2 - ret i32 %res -} - - -; CHECK-LABEL: name: test_lshr -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_LSHR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_lshr(i32 %arg1, i32 %arg2) { - %res = lshr i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_ashr -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_ASHR [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_ashr(i32 %arg1, i32 %arg2) { - %res = ashr i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_sdiv -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SDIV [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_sdiv(i32 %arg1, i32 %arg2) { - %res = sdiv i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_udiv -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UDIV [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_udiv(i32 %arg1, i32 %arg2) { - %res = udiv i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_srem -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_SREM [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_srem(i32 %arg1, i32 %arg2) { - %res = srem i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_urem -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %w1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_UREM [[ARG1]], [[ARG2]] -; CHECK-NEXT: %w0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %w0 -define i32 @test_urem(i32 %arg1, i32 %arg2) { - %res = urem i32 %arg1, %arg2 - ret i32 %res -} - -; CHECK-LABEL: name: test_constant_null -; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0 -; CHECK: %x0 = COPY [[NULL]] -define i8* @test_constant_null() { - ret i8* null -} - -; CHECK-LABEL: name: test_struct_memops -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](s64) = G_LOAD [[ADDR]](p0) :: (load 8 from %ir.addr, align 4) -; CHECK: G_STORE [[VAL]](s64), [[ADDR]](p0) :: (store 8 into %ir.addr, align 4) -define void @test_struct_memops({ i8, i32 }* %addr) { - %val = load { i8, i32 }, { i8, i32 }* %addr - store { i8, i32 } %val, { i8, i32 }* %addr - ret void -} - -; CHECK-LABEL: name: test_i1_memops -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](s1) = G_LOAD [[ADDR]](p0) :: (load 1 from %ir.addr) -; CHECK: G_STORE [[VAL]](s1), [[ADDR]](p0) :: (store 1 into %ir.addr) -define void @test_i1_memops(i1* %addr) { - %val = load i1, i1* %addr - store i1 %val, i1* %addr - ret void -} - -; CHECK-LABEL: name: int_comparison -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(ne), [[LHS]](s32), [[RHS]] -; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0) -define void @int_comparison(i32 %a, i32 %b, i1* %addr) { - %res = icmp ne i32 %a, %b - store i1 %res, i1* %addr - ret void -} - -; CHECK-LABEL: name: ptr_comparison -; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[TST:%[0-9]+]](s1) = G_ICMP intpred(eq), [[LHS]](p0), [[RHS]] -; CHECK: G_STORE [[TST]](s1), [[ADDR]](p0) -define void @ptr_comparison(i8* %a, i8* %b, i1* %addr) { - %res = icmp eq i8* %a, %b - store i1 %res, i1* %addr - ret void -} - -; CHECK-LABEL: name: test_fadd -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FADD [[ARG1]], [[ARG2]] -; CHECK-NEXT: %s0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %s0 -define float @test_fadd(float %arg1, float %arg2) { - %res = fadd float %arg1, %arg2 - ret float %res -} - -; CHECK-LABEL: name: test_fsub -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FSUB [[ARG1]], [[ARG2]] -; CHECK-NEXT: %s0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %s0 -define float @test_fsub(float %arg1, float %arg2) { - %res = fsub float %arg1, %arg2 - ret float %res -} - -; CHECK-LABEL: name: test_fmul -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FMUL [[ARG1]], [[ARG2]] -; CHECK-NEXT: %s0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %s0 -define float @test_fmul(float %arg1, float %arg2) { - %res = fmul float %arg1, %arg2 - ret float %res -} - -; CHECK-LABEL: name: test_fdiv -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FDIV [[ARG1]], [[ARG2]] -; CHECK-NEXT: %s0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %s0 -define float @test_fdiv(float %arg1, float %arg2) { - %res = fdiv float %arg1, %arg2 - ret float %res -} - -; CHECK-LABEL: name: test_frem -; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %s0 -; CHECK-NEXT: [[ARG2:%[0-9]+]](s32) = COPY %s1 -; CHECK-NEXT: [[RES:%[0-9]+]](s32) = G_FREM [[ARG1]], [[ARG2]] -; CHECK-NEXT: %s0 = COPY [[RES]] -; CHECK-NEXT: RET_ReallyLR implicit %s0 -define float @test_frem(float %arg1, float %arg2) { - %res = frem float %arg1, %arg2 - ret float %res -} - -; CHECK-LABEL: name: test_sadd_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SADDO [[LHS]], [[RHS]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) -define void @test_sadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) { - %res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %addr - ret void -} - -; CHECK-LABEL: name: test_uadd_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UADDE [[LHS]], [[RHS]], [[ZERO]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) -define void @test_uadd_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) { - %res = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %addr - ret void -} - -; CHECK-LABEL: name: test_ssub_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SSUBO [[LHS]], [[RHS]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) -define void @test_ssub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) { - %res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %subr - ret void -} - -; CHECK-LABEL: name: test_usub_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[ZERO:%[0-9]+]](s1) = G_CONSTANT i1 false -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_USUBE [[LHS]], [[RHS]], [[ZERO]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) -define void @test_usub_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %subr) { - %res = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %subr - ret void -} - -; CHECK-LABEL: name: test_smul_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_SMULO [[LHS]], [[RHS]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) -define void @test_smul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) { - %res = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %addr - ret void -} - -; CHECK-LABEL: name: test_umul_overflow -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[VAL:%[0-9]+]](s32), [[OVERFLOW:%[0-9]+]](s1) = G_UMULO [[LHS]], [[RHS]] -; CHECK: [[RES:%[0-9]+]](s64) = G_SEQUENCE [[VAL]](s32), 0, [[OVERFLOW]](s1), 32 -; CHECK: G_STORE [[RES]](s64), [[ADDR]](p0) -declare { i32, i1 } @llvm.umul.with.overflow.i32(i32, i32) -define void @test_umul_overflow(i32 %lhs, i32 %rhs, { i32, i1 }* %addr) { - %res = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %lhs, i32 %rhs) - store { i32, i1 } %res, { i32, i1 }* %addr - ret void -} - -; CHECK-LABEL: name: test_extractvalue -; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD -; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT [[STRUCT]](s128), 64 -; CHECK: %w0 = COPY [[RES]] -%struct.nested = type {i8, { i8, i32 }, i32} -define i32 @test_extractvalue(%struct.nested* %addr) { - %struct = load %struct.nested, %struct.nested* %addr - %res = extractvalue %struct.nested %struct, 1, 1 - ret i32 %res -} - -; CHECK-LABEL: name: test_extractvalue_agg -; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD -; CHECK: [[RES:%[0-9]+]](s64) = G_EXTRACT [[STRUCT]](s128), 32 -; CHECK: G_STORE [[RES]] -define void @test_extractvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) { - %struct = load %struct.nested, %struct.nested* %addr - %res = extractvalue %struct.nested %struct, 1 - store {i8, i32} %res, {i8, i32}* %addr2 - ret void -} - -; CHECK-LABEL: name: test_insertvalue -; CHECK: [[VAL:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD -; CHECK: [[NEWSTRUCT:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[VAL]](s32), 64 -; CHECK: G_STORE [[NEWSTRUCT]](s128), -define void @test_insertvalue(%struct.nested* %addr, i32 %val) { - %struct = load %struct.nested, %struct.nested* %addr - %newstruct = insertvalue %struct.nested %struct, i32 %val, 1, 1 - store %struct.nested %newstruct, %struct.nested* %addr - ret void -} - -define [1 x i64] @test_trivial_insert([1 x i64] %s, i64 %val) { -; CHECK-LABEL: name: test_trivial_insert -; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](s64) = COPY %x1 -; CHECK: [[RES:%[0-9]+]](s64) = COPY [[VAL]](s64) -; CHECK: %x0 = COPY [[RES]] - %res = insertvalue [1 x i64] %s, i64 %val, 0 - ret [1 x i64] %res -} - -define [1 x i8*] @test_trivial_insert_ptr([1 x i8*] %s, i8* %val) { -; CHECK-LABEL: name: test_trivial_insert_ptr -; CHECK: [[STRUCT:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[RES:%[0-9]+]](s64) = G_PTRTOINT [[VAL]](p0) -; CHECK: %x0 = COPY [[RES]] - %res = insertvalue [1 x i8*] %s, i8* %val, 0 - ret [1 x i8*] %res -} - -; CHECK-LABEL: name: test_insertvalue_agg -; CHECK: [[SMALLSTRUCT:%[0-9]+]](s64) = G_LOAD -; CHECK: [[STRUCT:%[0-9]+]](s128) = G_LOAD -; CHECK: [[RES:%[0-9]+]](s128) = G_INSERT [[STRUCT]], [[SMALLSTRUCT]](s64), 32 -; CHECK: G_STORE [[RES]](s128) -define void @test_insertvalue_agg(%struct.nested* %addr, {i8, i32}* %addr2) { - %smallstruct = load {i8, i32}, {i8, i32}* %addr2 - %struct = load %struct.nested, %struct.nested* %addr - %res = insertvalue %struct.nested %struct, {i8, i32} %smallstruct, 1 - store %struct.nested %res, %struct.nested* %addr - ret void -} - -; CHECK-LABEL: name: test_select -; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0 -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %w2 -; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]] -; CHECK: %w0 = COPY [[RES]] -define i32 @test_select(i1 %tst, i32 %lhs, i32 %rhs) { - %res = select i1 %tst, i32 %lhs, i32 %rhs - ret i32 %res -} - -; CHECK-LABEL: name: test_select_ptr -; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0 -; CHECK: [[LHS:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[RHS:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[RES:%[0-9]+]](p0) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]] -; CHECK: %x0 = COPY [[RES]] -define i8* @test_select_ptr(i1 %tst, i8* %lhs, i8* %rhs) { - %res = select i1 %tst, i8* %lhs, i8* %rhs - ret i8* %res -} - -; CHECK-LABEL: name: test_select_vec -; CHECK: [[TST:%[0-9]+]](s1) = COPY %w0 -; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q0 -; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q1 -; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](s1), [[LHS]], [[RHS]] -; CHECK: %q0 = COPY [[RES]] -define <4 x i32> @test_select_vec(i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs) { - %res = select i1 %tst, <4 x i32> %lhs, <4 x i32> %rhs - ret <4 x i32> %res -} - -; CHECK-LABEL: name: test_vselect_vec -; CHECK: [[TST32:%[0-9]+]](<4 x s32>) = COPY %q0 -; CHECK: [[LHS:%[0-9]+]](<4 x s32>) = COPY %q1 -; CHECK: [[RHS:%[0-9]+]](<4 x s32>) = COPY %q2 -; CHECK: [[TST:%[0-9]+]](<4 x s1>) = G_TRUNC [[TST32]](<4 x s32>) -; CHECK: [[RES:%[0-9]+]](<4 x s32>) = G_SELECT [[TST]](<4 x s1>), [[LHS]], [[RHS]] -; CHECK: %q0 = COPY [[RES]] -define <4 x i32> @test_vselect_vec(<4 x i32> %tst32, <4 x i32> %lhs, <4 x i32> %rhs) { - %tst = trunc <4 x i32> %tst32 to <4 x i1> - %res = select <4 x i1> %tst, <4 x i32> %lhs, <4 x i32> %rhs - ret <4 x i32> %res -} - -; CHECK-LABEL: name: test_fptosi -; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0) -; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOSI [[FP]](s32) -; CHECK: %x0 = COPY [[RES]] -define i64 @test_fptosi(float* %fp.addr) { - %fp = load float, float* %fp.addr - %res = fptosi float %fp to i64 - ret i64 %res -} - -; CHECK-LABEL: name: test_fptoui -; CHECK: [[FPADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[FP:%[0-9]+]](s32) = G_LOAD [[FPADDR]](p0) -; CHECK: [[RES:%[0-9]+]](s64) = G_FPTOUI [[FP]](s32) -; CHECK: %x0 = COPY [[RES]] -define i64 @test_fptoui(float* %fp.addr) { - %fp = load float, float* %fp.addr - %res = fptoui float %fp to i64 - ret i64 %res -} - -; CHECK-LABEL: name: test_sitofp -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[FP:%[0-9]+]](s64) = G_SITOFP [[IN]](s32) -; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0) -define void @test_sitofp(double* %addr, i32 %in) { - %fp = sitofp i32 %in to double - store double %fp, double* %addr - ret void -} - -; CHECK-LABEL: name: test_uitofp -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[FP:%[0-9]+]](s64) = G_UITOFP [[IN]](s32) -; CHECK: G_STORE [[FP]](s64), [[ADDR]](p0) -define void @test_uitofp(double* %addr, i32 %in) { - %fp = uitofp i32 %in to double - store double %fp, double* %addr - ret void -} - -; CHECK-LABEL: name: test_fpext -; CHECK: [[IN:%[0-9]+]](s32) = COPY %s0 -; CHECK: [[RES:%[0-9]+]](s64) = G_FPEXT [[IN]](s32) -; CHECK: %d0 = COPY [[RES]] -define double @test_fpext(float %in) { - %res = fpext float %in to double - ret double %res -} - -; CHECK-LABEL: name: test_fptrunc -; CHECK: [[IN:%[0-9]+]](s64) = COPY %d0 -; CHECK: [[RES:%[0-9]+]](s32) = G_FPTRUNC [[IN]](s64) -; CHECK: %s0 = COPY [[RES]] -define float @test_fptrunc(double %in) { - %res = fptrunc double %in to float - ret float %res -} - -; CHECK-LABEL: name: test_constant_float -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT float 1.500000e+00 -; CHECK: G_STORE [[TMP]](s32), [[ADDR]](p0) -define void @test_constant_float(float* %addr) { - store float 1.5, float* %addr - ret void -} - -; CHECK-LABEL: name: float_comparison -; CHECK: [[LHSADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[RHSADDR:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[BOOLADDR:%[0-9]+]](p0) = COPY %x2 -; CHECK: [[LHS:%[0-9]+]](s32) = G_LOAD [[LHSADDR]](p0) -; CHECK: [[RHS:%[0-9]+]](s32) = G_LOAD [[RHSADDR]](p0) -; CHECK: [[TST:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[LHS]](s32), [[RHS]] -; CHECK: G_STORE [[TST]](s1), [[BOOLADDR]](p0) -define void @float_comparison(float* %a.addr, float* %b.addr, i1* %bool.addr) { - %a = load float, float* %a.addr - %b = load float, float* %b.addr - %res = fcmp oge float %a, %b - store i1 %res, i1* %bool.addr - ret void -} - -; CHECK-LABEL: name: trivial_float_comparison -; CHECK: [[ENTRY_R1:%[0-9]+]](s1) = G_CONSTANT i1 false -; CHECK: [[ENTRY_R2:%[0-9]+]](s1) = G_CONSTANT i1 true -; CHECK: [[R1:%[0-9]+]](s1) = COPY [[ENTRY_R1]](s1) -; CHECK: [[R2:%[0-9]+]](s1) = COPY [[ENTRY_R2]](s1) -; CHECK: G_ADD [[R1]], [[R2]] -define i1 @trivial_float_comparison(double %a, double %b) { - %r1 = fcmp false double %a, %b - %r2 = fcmp true double %a, %b - %sum = add i1 %r1, %r2 - ret i1 %sum -} - -@var = global i32 0 - -define i32* @test_global() { -; CHECK-LABEL: name: test_global -; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @var{{$}} -; CHECK: %x0 = COPY [[TMP]](p0) - - ret i32* @var -} - -@var1 = addrspace(42) global i32 0 -define i32 addrspace(42)* @test_global_addrspace() { -; CHECK-LABEL: name: test_global -; CHECK: [[TMP:%[0-9]+]](p42) = G_GLOBAL_VALUE @var1{{$}} -; CHECK: %x0 = COPY [[TMP]](p42) - - ret i32 addrspace(42)* @var1 -} - - -define void()* @test_global_func() { -; CHECK-LABEL: name: test_global_func -; CHECK: [[TMP:%[0-9]+]](p0) = G_GLOBAL_VALUE @allocai64{{$}} -; CHECK: %x0 = COPY [[TMP]](p0) - - ret void()* @allocai64 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile) -define void @test_memcpy(i8* %dst, i8* %src, i64 %size) { -; CHECK-LABEL: name: test_memcpy -; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2 -; CHECK: %x0 = COPY [[DST]] -; CHECK: %x1 = COPY [[SRC]] -; CHECK: %x2 = COPY [[SIZE]] -; CHECK: BL $memcpy, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i32 1, i1 0) - ret void -} - -declare void @llvm.memmove.p0i8.p0i8.i64(i8*, i8*, i64, i32 %align, i1 %volatile) -define void @test_memmove(i8* %dst, i8* %src, i64 %size) { -; CHECK-LABEL: name: test_memmove -; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[SRC:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2 -; CHECK: %x0 = COPY [[DST]] -; CHECK: %x1 = COPY [[SRC]] -; CHECK: %x2 = COPY [[SIZE]] -; CHECK: BL $memmove, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2 - call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %size, i32 1, i1 0) - ret void -} - -declare void @llvm.memset.p0i8.i64(i8*, i8, i64, i32 %align, i1 %volatile) -define void @test_memset(i8* %dst, i8 %val, i64 %size) { -; CHECK-LABEL: name: test_memset -; CHECK: [[DST:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[SRC:%[0-9]+]](s8) = COPY %w1 -; CHECK: [[SIZE:%[0-9]+]](s64) = COPY %x2 -; CHECK: %x0 = COPY [[DST]] -; CHECK: %w1 = COPY [[SRC]] -; CHECK: %x2 = COPY [[SIZE]] -; CHECK: BL $memset, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %w1, implicit %x2 - call void @llvm.memset.p0i8.i64(i8* %dst, i8 %val, i64 %size, i32 1, i1 0) - ret void -} - -declare i64 @llvm.objectsize.i64(i8*, i1) -declare i32 @llvm.objectsize.i32(i8*, i1) -define void @test_objectsize(i8* %addr0, i8* %addr1) { -; CHECK-LABEL: name: test_objectsize -; CHECK: [[ADDR0:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[ADDR1:%[0-9]+]](p0) = COPY %x1 -; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 -1 -; CHECK: {{%[0-9]+}}(s64) = G_CONSTANT i64 0 -; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 -1 -; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT i32 0 - %size64.0 = call i64 @llvm.objectsize.i64(i8* %addr0, i1 0) - %size64.intmin = call i64 @llvm.objectsize.i64(i8* %addr0, i1 1) - %size32.0 = call i32 @llvm.objectsize.i32(i8* %addr0, i1 0) - %size32.intmin = call i32 @llvm.objectsize.i32(i8* %addr0, i1 1) - ret void -} - -define void @test_large_const(i128* %addr) { -; CHECK-LABEL: name: test_large_const -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](s128) = G_CONSTANT i128 42 -; CHECK: G_STORE [[VAL]](s128), [[ADDR]](p0) - store i128 42, i128* %addr - ret void -} - -; When there was no formal argument handling (so the first BB was empty) we used -; to insert the constants at the end of the block, even if they were encountered -; after the block's terminators had been emitted. Also make sure the order is -; correct. -define i8* @test_const_placement() { -; CHECK-LABEL: name: test_const_placement -; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}): -; CHECK: [[VAL_INT:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: [[VAL:%[0-9]+]](p0) = G_INTTOPTR [[VAL_INT]](s32) -; CHECK: {{bb.[0-9]+}}.next: - br label %next - -next: - ret i8* inttoptr(i32 42 to i8*) -} - -declare void @llvm.va_end(i8*) -define void @test_va_end(i8* %list) { -; CHECK-LABEL: name: test_va_end -; CHECK-NOT: va_end -; CHECK-NOT: INTRINSIC -; CHECK: RET_ReallyLR - call void @llvm.va_end(i8* %list) - ret void -} - -define void @test_va_arg(i8* %list) { -; CHECK-LABEL: test_va_arg -; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0 -; CHECK: G_VAARG [[LIST]](p0), 8 -; CHECK: G_VAARG [[LIST]](p0), 1 -; CHECK: G_VAARG [[LIST]](p0), 16 - - %v0 = va_arg i8* %list, i64 - %v1 = va_arg i8* %list, i8 - %v2 = va_arg i8* %list, i128 - ret void -} - -declare float @llvm.pow.f32(float, float) -define float @test_pow_intrin(float %l, float %r) { -; CHECK-LABEL: name: test_pow_intrin -; CHECK: [[LHS:%[0-9]+]](s32) = COPY %s0 -; CHECK: [[RHS:%[0-9]+]](s32) = COPY %s1 -; CHECK: [[RES:%[0-9]+]](s32) = G_FPOW [[LHS]], [[RHS]] -; CHECK: %s0 = COPY [[RES]] - %res = call float @llvm.pow.f32(float %l, float %r) - ret float %res -} - -declare void @llvm.lifetime.start.p0i8(i64, i8*) -declare void @llvm.lifetime.end.p0i8(i64, i8*) -define void @test_lifetime_intrin() { -; CHECK-LABEL: name: test_lifetime_intrin -; CHECK: RET_ReallyLR - %slot = alloca i8, i32 4 - call void @llvm.lifetime.start.p0i8(i64 0, i8* %slot) - call void @llvm.lifetime.end.p0i8(i64 0, i8* %slot) - ret void -} - -define void @test_load_store_atomics(i8* %addr) { -; CHECK-LABEL: name: test_load_store_atomics -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[V0:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load unordered 1 from %ir.addr) -; CHECK: G_STORE [[V0]](s8), [[ADDR]](p0) :: (store monotonic 1 into %ir.addr) -; CHECK: [[V1:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load acquire 1 from %ir.addr) -; CHECK: G_STORE [[V1]](s8), [[ADDR]](p0) :: (store release 1 into %ir.addr) -; CHECK: [[V2:%[0-9]+]](s8) = G_LOAD [[ADDR]](p0) :: (load singlethread seq_cst 1 from %ir.addr) -; CHECK: G_STORE [[V2]](s8), [[ADDR]](p0) :: (store singlethread monotonic 1 into %ir.addr) - %v0 = load atomic i8, i8* %addr unordered, align 1 - store atomic i8 %v0, i8* %addr monotonic, align 1 - - %v1 = load atomic i8, i8* %addr acquire, align 1 - store atomic i8 %v1, i8* %addr release, align 1 - - %v2 = load atomic i8, i8* %addr singlethread seq_cst, align 1 - store atomic i8 %v2, i8* %addr singlethread monotonic, align 1 - - ret void -} - -define float @test_fneg_f32(float %x) { -; CHECK-LABEL: name: test_fneg_f32 -; CHECK: [[ARG:%[0-9]+]](s32) = COPY %s0 -; CHECK: [[RES:%[0-9]+]](s32) = G_FNEG [[ARG]] -; CHECK: %s0 = COPY [[RES]](s32) - %neg = fsub float -0.000000e+00, %x - ret float %neg -} - -define double @test_fneg_f64(double %x) { -; CHECK-LABEL: name: test_fneg_f64 -; CHECK: [[ARG:%[0-9]+]](s64) = COPY %d0 -; CHECK: [[RES:%[0-9]+]](s64) = G_FNEG [[ARG]] -; CHECK: %d0 = COPY [[RES]](s64) - %neg = fsub double -0.000000e+00, %x - ret double %neg -} - -define void @test_trivial_inlineasm() { -; CHECK-LABEL: name: test_trivial_inlineasm -; CHECK: INLINEASM $wibble, 1 -; CHECK: INLINEASM $wibble, 0 - call void asm sideeffect "wibble", ""() - call void asm "wibble", ""() - ret void -} - -define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){ -; CHECK-LABEL: name: test_insertelement -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[RES:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32) -; CHECK: %d0 = COPY [[RES]](<2 x s32>) - %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx - ret <2 x i32> %res -} - -define i32 @test_extractelement(<2 x i32> %vec, i32 %idx) { -; CHECK-LABEL: name: test_extractelement -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK: [[IDX:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[RES:%[0-9]+]](s32) = G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>), [[IDX]](s32) -; CHECK: %w0 = COPY [[RES]](s32) - %res = extractelement <2 x i32> %vec, i32 %idx - ret i32 %res -} - -define i32 @test_singleelementvector(i32 %elt){ -; CHECK-LABEL: name: test_singleelementvector -; CHECK: [[ELT:%[0-9]+]](s32) = COPY %w0 -; CHECK-NOT: G_INSERT_VECTOR_ELT -; CHECK-NOT: G_EXTRACT_VECTOR_ELT -; CHECK: %w0 = COPY [[ELT]](s32) - %vec = insertelement <1 x i32> undef, i32 %elt, i32 0 - %res = extractelement <1 x i32> %vec, i32 0 - ret i32 %res -} - -define <2 x i32> @test_constantaggzerovector_v2i32() { -; CHECK-LABEL: name: test_constantaggzerovector_v2i32 -; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - ret <2 x i32> zeroinitializer -} - -define <2 x float> @test_constantaggzerovector_v2f32() { -; CHECK-LABEL: name: test_constantaggzerovector_v2f32 -; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float 0.000000e+00 -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - ret <2 x float> zeroinitializer -} - -define i32 @test_constantaggzerovector_v3i32() { -; CHECK-LABEL: name: test_constantaggzerovector_v3i32 -; CHECK: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[ZERO]](s32), [[ZERO]](s32), [[ZERO]](s32) -; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>) - %elt = extractelement <3 x i32> zeroinitializer, i32 1 - ret i32 %elt -} - -define <2 x i32> @test_constantdatavector_v2i32() { -; CHECK-LABEL: name: test_constantdatavector_v2i32 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - ret <2 x i32> <i32 1, i32 2> -} - -define i32 @test_constantdatavector_v3i32() { -; CHECK-LABEL: name: test_constantdatavector_v3i32 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3 -; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32) -; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>) - %elt = extractelement <3 x i32> <i32 1, i32 2, i32 3>, i32 1 - ret i32 %elt -} - -define <4 x i32> @test_constantdatavector_v4i32() { -; CHECK-LABEL: name: test_constantdatavector_v4i32 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3 -; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4 -; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32) -; CHECK: %q0 = COPY [[VEC]](<4 x s32>) - ret <4 x i32> <i32 1, i32 2, i32 3, i32 4> -} - -define <2 x double> @test_constantdatavector_v2f64() { -; CHECK-LABEL: name: test_constantdatavector_v2f64 -; CHECK: [[FC1:%[0-9]+]](s64) = G_FCONSTANT double 1.000000e+00 -; CHECK: [[FC2:%[0-9]+]](s64) = G_FCONSTANT double 2.000000e+00 -; CHECK: [[VEC:%[0-9]+]](<2 x s64>) = G_MERGE_VALUES [[FC1]](s64), [[FC2]](s64) -; CHECK: %q0 = COPY [[VEC]](<2 x s64>) - ret <2 x double> <double 1.0, double 2.0> -} - -define i32 @test_constantaggzerovector_v1s32(i32 %arg){ -; CHECK-LABEL: name: test_constantaggzerovector_v1s32 -; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK-NOT: G_MERGE_VALUES -; CHECK: G_ADD [[ARG]], [[C0]] - %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 - %add = add <1 x i32> %vec, zeroinitializer - %res = extractelement <1 x i32> %add, i32 0 - ret i32 %res -} - -define i32 @test_constantdatavector_v1s32(i32 %arg){ -; CHECK-LABEL: name: test_constantdatavector_v1s32 -; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK-NOT: G_MERGE_VALUES -; CHECK: G_ADD [[ARG]], [[C1]] - %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 - %add = add <1 x i32> %vec, <i32 1> - %res = extractelement <1 x i32> %add, i32 0 - ret i32 %res -} - -declare ghccc float @different_call_conv_target(float %x) -define float @test_different_call_conv_target(float %x) { -; CHECK-LABEL: name: test_different_call_conv -; CHECK: [[X:%[0-9]+]](s32) = COPY %s0 -; CHECK: %s8 = COPY [[X]] -; CHECK: BL @different_call_conv_target, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s8, implicit-def %s0 - %res = call ghccc float @different_call_conv_target(float %x) - ret float %res -} - -define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) { -; CHECK-LABEL: name: test_shufflevector_s32_v2s32 -; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0 -; CHECK-DAG: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF -; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32) -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 - %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer - ret <2 x i32> %res -} - -define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) { -; CHECK-LABEL: name: test_shufflevector_v2s32_s32 -; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32) -; CHECK: %w0 = COPY [[RES]](s32) - %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1> - %res = extractelement <1 x i32> %vec, i32 0 - ret i32 %res -} - -define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) { -; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32 -; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32) -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0> - ret <2 x i32> %res -} - -define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) { -; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32 -; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK-DAG: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32) -; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>) -; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>) - %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1> - %res = extractelement <3 x i32> %vec, i32 0 - ret i32 %res -} - -define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) { -; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32 -; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0 -; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1 -; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3 -; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32) -; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>) -; CHECK: %q0 = COPY [[VEC]](<4 x s32>) - %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - ret <4 x i32> %res -} - -define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) { -; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32 -; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0 -; CHECK-DAG: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3 -; CHECK-DAG: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32) -; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>) -; CHECK: %d0 = COPY [[VEC]](<2 x s32>) - %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3> - ret <2 x i32> %res -} - - -define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) { -; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8 -; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0 -; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1 -; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8 -; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9 -; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2 -; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10 -; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3 -; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11 -; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4 -; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12 -; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5 -; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13 -; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6 -; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14 -; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7 -; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15 -; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32) -; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>) -; CHECK: %q0 = COPY [[VEC]](<16 x s8>) - %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> - ret <16 x i8> %res -} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir deleted file mode 100644 index 739fdd5cb4c5..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ /dev/null @@ -1,652 +0,0 @@ -# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=FAST -# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -regbankselect-greedy -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY - ---- | - ; ModuleID = 'generic-virtual-registers-type-error.mir' - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @defaultMapping() { - entry: - ret void - } - define void @defaultMappingVector() { - entry: - ret void - } - define void @defaultMapping1Repair() { - entry: - ret void - } - define void @defaultMapping2Repairs() { - entry: - ret void - } - define void @defaultMappingDefRepair() { - entry: - ret void - } - define void @phiPropagation(i32* %src, i32* %dst, i1 %cond) { - entry: - %srcVal = load i32, i32* %src - br i1 %cond, label %end, label %then - then: - %res = add i32 %srcVal, 36 - br label %end - end: - %toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ] - store i32 %toStore, i32* %dst - ret void - } - define void @defaultMappingUseRepairPhysReg() { - entry: - ret void - } - define void @defaultMappingDefRepairPhysReg() { - entry: - ret void - } - define void @greedyMappingOr() { - entry: - ret void - } - define void @greedyMappingOrWithConstraints() { - entry: - ret void - } - - define void @ignoreTargetSpecificInst() { ret void } - - define void @regBankSelected_property() { ret void } - - define void @bitcast_s32_gpr() { ret void } - define void @bitcast_s32_fpr() { ret void } - define void @bitcast_s32_gpr_fpr() { ret void } - define void @bitcast_s32_fpr_gpr() { ret void } - define void @bitcast_s64_gpr() { ret void } - define void @bitcast_s64_fpr() { ret void } - define void @bitcast_s64_gpr_fpr() { ret void } - define void @bitcast_s64_fpr_gpr() { ret void } - - define i64 @greedyWithChainOfComputation(i64 %arg1, <2 x i32>* %addr) { - %varg1 = bitcast i64 %arg1 to <2 x i32> - %varg2 = load <2 x i32>, <2 x i32>* %addr - %vres = or <2 x i32> %varg1, %varg2 - %res = bitcast <2 x i32> %vres to i64 - ret i64 %res - } -... - ---- -# Check that we assign a relevant register bank for %0. -# Based on the type i32, this should be gpr. -name: defaultMapping -legalized: true -# CHECK-LABEL: name: defaultMapping -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0.entry: - liveins: %x0 - ; CHECK: %1(s32) = G_ADD %0 - %0(s32) = COPY %w0 - %1(s32) = G_ADD %0, %0 -... - ---- -# Check that we assign a relevant register bank for %0. -# Based on the type <2 x i32>, this should be fpr. -# FPR is used for both floating point and vector registers. -name: defaultMappingVector -legalized: true -# CHECK-LABEL: name: defaultMappingVector -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0.entry: - liveins: %d0 - ; CHECK: %0(<2 x s32>) = COPY %d0 - ; CHECK: %1(<2 x s32>) = G_ADD %0 - %0(<2 x s32>) = COPY %d0 - %1(<2 x s32>) = G_ADD %0, %0 -... - ---- -# Check that we repair the assignment for %0. -# Indeed based on the source of the copy it should live -# in FPR, but at the use, it should be GPR. -name: defaultMapping1Repair -legalized: true -# CHECK-LABEL: name: defaultMapping1Repair -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0.entry: - liveins: %s0, %x0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK-NEXT: %1(s32) = COPY %w0 - ; CHECK-NEXT: %3(s32) = COPY %0 - ; CHECK-NEXT: %2(s32) = G_ADD %3, %1 - %0(s32) = COPY %s0 - %1(s32) = COPY %w0 - %2(s32) = G_ADD %0, %1 -... - -# Check that we repair the assignment for %0 differently for both uses. -name: defaultMapping2Repairs -legalized: true -# CHECK-LABEL: name: defaultMapping2Repairs -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0.entry: - liveins: %s0, %x0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK-NEXT: %2(s32) = COPY %0 - ; CHECK-NEXT: %3(s32) = COPY %0 - ; CHECK-NEXT: %1(s32) = G_ADD %2, %3 - %0(s32) = COPY %s0 - %1(s32) = G_ADD %0, %0 -... - ---- -# Check that we repair the definition of %1. -# %1 is forced to be into FPR, but its definition actually -# requires that it lives in GPR. Make sure regbankselect -# fixes that. -name: defaultMappingDefRepair -legalized: true -# CHECK-LABEL: name: defaultMappingDefRepair -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: fpr } -# CHECK-NEXT: - { id: 2, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: fpr } -body: | - bb.0.entry: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK-NEXT: %2(s32) = G_ADD %0, %0 - ; CHECK-NEXT: %1(s32) = COPY %2 - %0(s32) = COPY %w0 - %1(s32) = G_ADD %0, %0 -... - ---- -# Check that we are able to propagate register banks from phis. -name: phiPropagation -legalized: true -tracksRegLiveness: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr64sp } -# CHECK-NEXT: - { id: 2, class: gpr32 } -# CHECK-NEXT: - { id: 3, class: gpr } -# CHECK-NEXT: - { id: 4, class: gpr } -registers: - - { id: 0, class: gpr32 } - - { id: 1, class: gpr64sp } - - { id: 2, class: gpr32 } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - successors: %bb.2.end, %bb.1.then - liveins: %x0, %x1, %w2 - - %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src) - %5(s32) = COPY %0 - %1(p0) = COPY %x1 - %2 = COPY %w2 - TBNZW killed %2, 0, %bb.2.end - - bb.1.then: - successors: %bb.2.end - %3(s32) = G_ADD %5, %5 - - bb.2.end: - %4(s32) = PHI %0, %bb.0.entry, %3, %bb.1.then - G_STORE killed %4, killed %1 :: (store 4 into %ir.dst) - RET_ReallyLR -... - ---- -# Make sure we can repair physical register uses as well. -name: defaultMappingUseRepairPhysReg -legalized: true -# CHECK-LABEL: name: defaultMappingUseRepairPhysReg -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: fpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0.entry: - liveins: %w0, %s0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK-NEXT: %1(s32) = COPY %s0 - ; CHECK-NEXT: %3(s32) = COPY %1 - ; CHECK-NEXT: %2(s32) = G_ADD %0, %3 - %0(s32) = COPY %w0 - %1(s32) = COPY %s0 - %2(s32) = G_ADD %0, %1 -... - ---- -# Make sure we can repair physical register defs. -name: defaultMappingDefRepairPhysReg -legalized: true -# CHECK-LABEL: name: defaultMappingDefRepairPhysReg -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0.entry: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK-NEXT: %1(s32) = G_ADD %0, %0 - ; CHECK-NEXT: %s0 = COPY %1 - %0(s32) = COPY %w0 - %1(s32) = G_ADD %0, %0 - %s0 = COPY %1 -... - ---- -# Check that the greedy mode is able to switch the -# G_OR instruction from fpr to gpr. -name: greedyMappingOr -legalized: true -# CHECK-LABEL: name: greedyMappingOr -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } - -# Fast mode maps vector instruction on FPR. -# FAST-NEXT: - { id: 2, class: fpr } -# Fast mode needs two extra copies. -# FAST-NEXT: - { id: 3, class: fpr } -# FAST-NEXT: - { id: 4, class: fpr } - -# Greedy mode coalesce the computation on the GPR register -# because it is the cheapest. -# GREEDY-NEXT: - { id: 2, class: gpr } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1 - ; CHECK: %0(<2 x s32>) = COPY %x0 - ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1 - - - ; Fast mode tries to reuse the source of the copy for the destination. - ; Now, the default mapping says that %0 and %1 need to be in FPR. - ; The repairing code insert two copies to materialize that. - ; FAST-NEXT: %3(<2 x s32>) = COPY %0 - ; FAST-NEXT: %4(<2 x s32>) = COPY %1 - ; The mapping of G_OR is on FPR. - ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4 - - ; Greedy mode remapped the instruction on the GPR bank. - ; GREEDY-NEXT: %2(<2 x s32>) = G_OR %0, %1 - %0(<2 x s32>) = COPY %x0 - %1(<2 x s32>) = COPY %x1 - %2(<2 x s32>) = G_OR %0, %1 -... - ---- -# Check that the greedy mode is able to switch the -# G_OR instruction from fpr to gpr, while still honoring -# %2 constraint. -name: greedyMappingOrWithConstraints -legalized: true -# CHECK-LABEL: name: greedyMappingOrWithConstraints -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: fpr } - -# Fast mode maps vector instruction on FPR. -# Fast mode needs two extra copies. -# FAST-NEXT: - { id: 3, class: fpr } -# FAST-NEXT: - { id: 4, class: fpr } - -# Greedy mode coalesce the computation on the GPR register because it -# is the cheapest, but will need one extra copy to materialize %2 into a FPR. -# GREEDY-NEXT: - { id: 3, class: gpr } - -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: fpr } -body: | - bb.0.entry: - liveins: %x0, %x1 - ; CHECK: %0(<2 x s32>) = COPY %x0 - ; CHECK-NEXT: %1(<2 x s32>) = COPY %x1 - - - ; Fast mode tries to reuse the source of the copy for the destination. - ; Now, the default mapping says that %0 and %1 need to be in FPR. - ; The repairing code insert two copies to materialize that. - ; FAST-NEXT: %3(<2 x s32>) = COPY %0 - ; FAST-NEXT: %4(<2 x s32>) = COPY %1 - ; The mapping of G_OR is on FPR. - ; FAST-NEXT: %2(<2 x s32>) = G_OR %3, %4 - - ; Greedy mode remapped the instruction on the GPR bank. - ; GREEDY-NEXT: %3(<2 x s32>) = G_OR %0, %1 - ; We need to keep %2 into FPR because we do not know anything about it. - ; GREEDY-NEXT: %2(<2 x s32>) = COPY %3 - %0(<2 x s32>) = COPY %x0 - %1(<2 x s32>) = COPY %x1 - %2(<2 x s32>) = G_OR %0, %1 -... - ---- -# CHECK-LABEL: name: ignoreTargetSpecificInst -name: ignoreTargetSpecificInst -legalized: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: gpr64 } - - { id: 1, class: gpr64 } -body: | - bb.0: - liveins: %x0 - - ; CHECK: %0 = COPY %x0 - ; CHECK-NEXT: %1 = ADDXrr %0, %0 - ; CHECK-NEXT: %x0 = COPY %1 - ; CHECK-NEXT: RET_ReallyLR implicit %x0 - - %0 = COPY %x0 - %1 = ADDXrr %0, %0 - %x0 = COPY %1 - RET_ReallyLR implicit %x0 -... - ---- -# Check that we set the "regBankSelected" property. -# CHECK-LABEL: name: regBankSelected_property -# CHECK: legalized: true -# CHECK: regBankSelected: true -name: regBankSelected_property -legalized: true -regBankSelected: false -body: | - bb.0: -... - ---- -# CHECK-LABEL: name: bitcast_s32_gpr -name: bitcast_s32_gpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(s32) = COPY %w0 -# CHECK: %1(s32) = G_BITCAST %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s32_fpr -name: bitcast_s32_fpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# CHECK-NEXT: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(<2 x s16>) = COPY %s0 -# CHECK: %1(<2 x s16>) = G_BITCAST %0 -body: | - bb.0: - liveins: %s0 - - %0(<2 x s16>) = COPY %s0 - %1(<2 x s16>) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s32_gpr_fpr -name: bitcast_s32_gpr_fpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# FAST-NEXT: - { id: 1, class: fpr } -# GREEDY-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(s32) = COPY %w0 -# CHECK: %1(<2 x s16>) = G_BITCAST %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(<2 x s16>) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s32_fpr_gpr -name: bitcast_s32_fpr_gpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# FAST-NEXT: - { id: 1, class: gpr } -# GREEDY-NEXT: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(<2 x s16>) = COPY %s0 -# CHECK: %1(s32) = G_BITCAST %0 -body: | - bb.0: - liveins: %s0 - - %0(<2 x s16>) = COPY %s0 - %1(s32) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s64_gpr -name: bitcast_s64_gpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(s64) = COPY %x0 -# CHECK: %1(s64) = G_BITCAST %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s64_fpr -name: bitcast_s64_fpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# CHECK-NEXT: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(<2 x s32>) = COPY %d0 -# CHECK: %1(<2 x s32>) = G_BITCAST %0 -body: | - bb.0: - liveins: %d0 - - %0(<2 x s32>) = COPY %d0 - %1(<2 x s32>) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s64_gpr_fpr -name: bitcast_s64_gpr_fpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# FAST-NEXT: - { id: 1, class: fpr } -# GREEDY-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -# CHECK: body: -# CHECK: %0(s64) = COPY %x0 -# CHECK: %1(<2 x s32>) = G_BITCAST %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(<2 x s32>) = G_BITCAST %0 -... - ---- -# CHECK-LABEL: name: bitcast_s64_fpr_gpr -name: bitcast_s64_fpr_gpr -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr } -# FAST-NEXT: - { id: 1, class: gpr } -# GREEDY-NEXT: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - -# CHECK: body: -# CHECK: %0(<2 x s32>) = COPY %d0 -# CHECK: %1(s64) = G_BITCAST %0 -body: | - bb.0: - liveins: %d0 - - %0(<2 x s32>) = COPY %d0 - %1(s64) = G_BITCAST %0 -... - ---- -# Make sure the greedy mode is able to take advantage of the -# alternative mappings of G_LOAD to coalesce the whole chain -# of computation on GPR. -# CHECK-LABEL: name: greedyWithChainOfComputation -name: greedyWithChainOfComputation -legalized: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr } -# FAST-NEXT: - { id: 2, class: fpr } -# FAST-NEXT: - { id: 3, class: fpr } -# FAST-NEXT: - { id: 4, class: fpr } -# GREEDY-NEXT: - { id: 2, class: gpr } -# GREEDY-NEXT: - { id: 3, class: gpr } -# GREEDY-NEXT: - { id: 4, class: gpr } -# CHECK-NEXT: - { id: 5, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - -# No repairing should be necessary for both modes. -# CHECK: %0(s64) = COPY %x0 -# CHECK-NEXT: %1(p0) = COPY %x1 -# CHECK-NEXT: %2(<2 x s32>) = G_BITCAST %0(s64) -# CHECK-NEXT: %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr) -# CHECK-NEXT: %4(<2 x s32>) = G_OR %2, %3 -# CHECK-NEXT: %5(s64) = G_BITCAST %4(<2 x s32>) -# CHECK-NEXT: %x0 = COPY %5(s64) -# CHECK-NEXT: RET_ReallyLR implicit %x0 - -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(p0) = COPY %x1 - %2(<2 x s32>) = G_BITCAST %0(s64) - %3(<2 x s32>) = G_LOAD %1(p0) :: (load 8 from %ir.addr) - %4(<2 x s32>) = G_OR %2, %3 - %5(s64) = G_BITCAST %4(<2 x s32>) - %x0 = COPY %5(s64) - RET_ReallyLR implicit %x0 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll b/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll deleted file mode 100644 index 4e6b9cad4c3d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: llc -mtriple=aarch64-apple-ios -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - - -; CHECK-LABEL: name: test_stack_slots -; CHECK: fixedStack: -; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 1 -; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 1, size: 1 -; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; CHECK: [[LHS:%[0-9]+]](s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 0) -; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; CHECK: [[RHS:%[0-9]+]](s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]], align 0) -; CHECK: [[SUM:%[0-9]+]](s8) = G_ADD [[LHS]], [[RHS]] -; CHECK: [[SUM32:%[0-9]+]](s32) = G_SEXT [[SUM]](s8) -; CHECK: %w0 = COPY [[SUM32]](s32) -define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) { - %sum = add i8 %lhs, %rhs - ret i8 %sum -} - -; CHECK-LABEL: name: test_call_stack -; CHECK: [[C42:%[0-9]+]](s8) = G_CONSTANT i8 42 -; CHECK: [[C12:%[0-9]+]](s8) = G_CONSTANT i8 12 -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0 -; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64) -; CHECK: G_STORE [[C42]](s8), [[C42_LOC]](p0) :: (store 1 into stack, align 0) -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 1 -; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64) -; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1, align 0) -; CHECK: BL @test_stack_slots -define void @test_call_stack() { - call signext i8 @test_stack_slots([8 x i64] undef, i8 signext 42, i8 signext 12) - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/test/CodeGen/AArch64/GlobalISel/call-translator.ll deleted file mode 100644 index f8d95c88cc8f..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/call-translator.ll +++ /dev/null @@ -1,216 +0,0 @@ -; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - -; CHECK-LABEL: name: test_trivial_call -; CHECK: ADJCALLSTACKDOWN 0, implicit-def %sp, implicit %sp -; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def %lr -; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp -declare void @trivial_callee() -define void @test_trivial_call() { - call void @trivial_callee() - ret void -} - -; CHECK-LABEL: name: test_simple_return -; CHECK: BL @simple_return_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit-def %x0 -; CHECK: [[RES:%[0-9]+]](s64) = COPY %x0 -; CHECK: %x0 = COPY [[RES]] -; CHECK: RET_ReallyLR implicit %x0 -declare i64 @simple_return_callee() -define i64 @test_simple_return() { - %res = call i64 @simple_return_callee() - ret i64 %res -} - -; CHECK-LABEL: name: test_simple_arg -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 -; CHECK: %w0 = COPY [[IN]] -; CHECK: BL @simple_arg_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0 -; CHECK: RET_ReallyLR -declare void @simple_arg_callee(i32 %in) -define void @test_simple_arg(i32 %in) { - call void @simple_arg_callee(i32 %in) - ret void -} - -; CHECK-LABEL: name: test_indirect_call -; CHECK: registers: -; Make sure the register feeding the indirect call is properly constrained. -; CHECK: - { id: [[FUNC:[0-9]+]], class: gpr64 } -; CHECK: %[[FUNC]](p0) = COPY %x0 -; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def %lr, implicit %sp -; CHECK: RET_ReallyLR -define void @test_indirect_call(void()* %func) { - call void %func() - ret void -} - -; CHECK-LABEL: name: test_multiple_args -; CHECK: [[IN:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: %w0 = COPY [[ANSWER]] -; CHECK: %x1 = COPY [[IN]] -; CHECK: BL @multiple_args_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit %x1 -; CHECK: RET_ReallyLR -declare void @multiple_args_callee(i32, i64) -define void @test_multiple_args(i64 %in) { - call void @multiple_args_callee(i32 42, i64 %in) - ret void -} - - -; CHECK-LABEL: name: test_struct_formal -; CHECK: [[DBL:%[0-9]+]](s64) = COPY %d0 -; CHECK: [[I64:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[I8:%[0-9]+]](s8) = COPY %w1 -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x2 - -; CHECK: [[UNDEF:%[0-9]+]](s192) = IMPLICIT_DEF -; CHECK: [[ARG0:%[0-9]+]](s192) = G_INSERT [[UNDEF]], [[DBL]](s64), 0 -; CHECK: [[ARG1:%[0-9]+]](s192) = G_INSERT [[ARG0]], [[I64]](s64), 64 -; CHECK: [[ARG2:%[0-9]+]](s192) = G_INSERT [[ARG1]], [[I8]](s8), 128 -; CHECK: [[ARG:%[0-9]+]](s192) = COPY [[ARG2]] - -; CHECK: G_STORE [[ARG]](s192), [[ADDR]](p0) -; CHECK: RET_ReallyLR -define void @test_struct_formal({double, i64, i8} %in, {double, i64, i8}* %addr) { - store {double, i64, i8} %in, {double, i64, i8}* %addr - ret void -} - - -; CHECK-LABEL: name: test_struct_return -; CHECK: [[ADDR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[VAL:%[0-9]+]](s192) = G_LOAD [[ADDR]](p0) - -; CHECK: [[DBL:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 0 -; CHECK: [[I64:%[0-9]+]](s64) = G_EXTRACT [[VAL]](s192), 64 -; CHECK: [[I32:%[0-9]+]](s32) = G_EXTRACT [[VAL]](s192), 128 - -; CHECK: %d0 = COPY [[DBL]](s64) -; CHECK: %x0 = COPY [[I64]](s64) -; CHECK: %w1 = COPY [[I32]](s32) -; CHECK: RET_ReallyLR implicit %d0, implicit %x0, implicit %w1 -define {double, i64, i32} @test_struct_return({double, i64, i32}* %addr) { - %val = load {double, i64, i32}, {double, i64, i32}* %addr - ret {double, i64, i32} %val -} - -; CHECK-LABEL: name: test_arr_call -; CHECK: hasCalls: true -; CHECK: [[ARG:%[0-9]+]](s256) = G_LOAD - -; CHECK: [[E0:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 0 -; CHECK: [[E1:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 64 -; CHECK: [[E2:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 128 -; CHECK: [[E3:%[0-9]+]](s64) = G_EXTRACT [[ARG]](s256), 192 - -; CHECK: %x0 = COPY [[E0]](s64) -; CHECK: %x1 = COPY [[E1]](s64) -; CHECK: %x2 = COPY [[E2]](s64) -; CHECK: %x3 = COPY [[E3]](s64) -; CHECK: BL @arr_callee, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit %x1, implicit %x2, implicit %x3, implicit-def %x0, implicit-def %x1, implicit-def %x2, implicit-def %x3 -; CHECK: [[E0:%[0-9]+]](s64) = COPY %x0 -; CHECK: [[E1:%[0-9]+]](s64) = COPY %x1 -; CHECK: [[E2:%[0-9]+]](s64) = COPY %x2 -; CHECK: [[E3:%[0-9]+]](s64) = COPY %x3 -; CHECK: [[RES:%[0-9]+]](s256) = G_SEQUENCE [[E0]](s64), 0, [[E1]](s64), 64, [[E2]](s64), 128, [[E3]](s64), 192 -; CHECK: G_EXTRACT [[RES]](s256), 64 -declare [4 x i64] @arr_callee([4 x i64]) -define i64 @test_arr_call([4 x i64]* %addr) { - %arg = load [4 x i64], [4 x i64]* %addr - %res = call [4 x i64] @arr_callee([4 x i64] %arg) - %val = extractvalue [4 x i64] %res, 1 - ret i64 %val -} - - -; CHECK-LABEL: name: test_abi_exts_call -; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD -; CHECK: %w0 = COPY [[VAL]] -; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0 -; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8) -; CHECK: %w0 = COPY [[SVAL]](s32) -; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0 -; CHECK: [[ZVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8) -; CHECK: %w0 = COPY [[ZVAL]](s32) -; CHECK: BL @take_char, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0 -declare void @take_char(i8) -define void @test_abi_exts_call(i8* %addr) { - %val = load i8, i8* %addr - call void @take_char(i8 %val) - call void @take_char(i8 signext %val) - call void @take_char(i8 zeroext %val) - ret void -} - -; CHECK-LABEL: name: test_abi_sext_ret -; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD -; CHECK: [[SVAL:%[0-9]+]](s32) = G_SEXT [[VAL]](s8) -; CHECK: %w0 = COPY [[SVAL]](s32) -; CHECK: RET_ReallyLR implicit %w0 -define signext i8 @test_abi_sext_ret(i8* %addr) { - %val = load i8, i8* %addr - ret i8 %val -} - -; CHECK-LABEL: name: test_abi_zext_ret -; CHECK: [[VAL:%[0-9]+]](s8) = G_LOAD -; CHECK: [[SVAL:%[0-9]+]](s32) = G_ZEXT [[VAL]](s8) -; CHECK: %w0 = COPY [[SVAL]](s32) -; CHECK: RET_ReallyLR implicit %w0 -define zeroext i8 @test_abi_zext_ret(i8* %addr) { - %val = load i8, i8* %addr - ret i8 %val -} - -; CHECK-LABEL: name: test_stack_slots -; CHECK: fixedStack: -; CHECK-DAG: - { id: [[STACK0:[0-9]+]], offset: 0, size: 8 -; CHECK-DAG: - { id: [[STACK8:[0-9]+]], offset: 8, size: 8 -; CHECK-DAG: - { id: [[STACK16:[0-9]+]], offset: 16, size: 8 -; CHECK: [[LHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]] -; CHECK: [[LHS:%[0-9]+]](s64) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK0]], align 0) -; CHECK: [[RHS_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]] -; CHECK: [[RHS:%[0-9]+]](s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK8]], align 0) -; CHECK: [[ADDR_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]] -; CHECK: [[ADDR:%[0-9]+]](p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load 8 from %fixed-stack.[[STACK16]], align 0) -; CHECK: [[SUM:%[0-9]+]](s64) = G_ADD [[LHS]], [[RHS]] -; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0) -define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) { - %sum = add i64 %lhs, %rhs - store i64 %sum, i64* %addr - ret void -} - -; CHECK-LABEL: name: test_call_stack -; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42 -; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12 -; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0 -; CHECK: ADJCALLSTACKDOWN 24, implicit-def %sp, implicit %sp -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0 -; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64) -; CHECK: G_STORE [[C42]](s64), [[C42_LOC]](p0) :: (store 8 into stack, align 0) -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[C12_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 8 -; CHECK: [[C12_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C12_OFFS]](s64) -; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 0) -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[PTR_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 16 -; CHECK: [[PTR_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[PTR_OFFS]](s64) -; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store 8 into stack + 16, align 0) -; CHECK: BL @test_stack_slots -; CHECK: ADJCALLSTACKUP 24, 0, implicit-def %sp, implicit %sp -define void @test_call_stack() { - call void @test_stack_slots([8 x i64] undef, i64 42, i64 12, i64* null) - ret void -} - -; CHECK-LABEL: name: test_mem_i1 -; CHECK: fixedStack: -; CHECK-NEXT: - { id: [[SLOT:[0-9]+]], offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false } -; CHECK: [[ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[SLOT]] -; CHECK: {{%[0-9]+}}(s1) = G_LOAD [[ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[SLOT]], align 0) -define void @test_mem_i1([8 x i64], i1 %in) { - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll b/test/CodeGen/AArch64/GlobalISel/debug-insts.ll deleted file mode 100644 index 5a76661180f2..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/debug-insts.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: llc -global-isel -mtriple=aarch64 %s -stop-after=irtranslator -o - | FileCheck %s -; RUN: llc -mtriple=aarch64 -global-isel --global-isel-abort=0 -o /dev/null - -; CHECK-LABEL: name: debug_declare -; CHECK: stack: -; CHECK: - { id: {{.*}}, name: in.addr, offset: {{.*}}, size: {{.*}}, alignment: {{.*}}, di-variable: '!11', -; CHECK-NEXT: di-expression: '!12', di-location: '!13' } -; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !11, !12, debug-location !13 -define void @debug_declare(i32 %in) #0 !dbg !7 { -entry: - %in.addr = alloca i32, align 4 - store i32 %in, i32* %in.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %in.addr, metadata !11, metadata !12), !dbg !13 - call void @llvm.dbg.declare(metadata i32 %in, metadata !11, metadata !12), !dbg !13 - ret void, !dbg !14 -} - -; CHECK-LABEL: name: debug_declare_vla -; CHECK: DBG_VALUE debug-use %{{[0-9]+}}(p0), debug-use _, !11, !12, debug-location !13 -define void @debug_declare_vla(i32 %in) #0 !dbg !7 { -entry: - %vla.addr = alloca i32, i32 %in - call void @llvm.dbg.declare(metadata i32* %vla.addr, metadata !11, metadata !12), !dbg !13 - ret void, !dbg !14 -} - -; CHECK-LABEL: name: debug_value -; CHECK: [[IN:%[0-9]+]](s32) = COPY %w0 -define void @debug_value(i32 %in) #0 !dbg !7 { - %addr = alloca i32 -; CHECK: DBG_VALUE debug-use [[IN]](s32), debug-use _, !11, !12, debug-location !13 - call void @llvm.dbg.value(metadata i32 %in, i64 0, metadata !11, metadata !12), !dbg !13 - store i32 %in, i32* %addr -; CHECK: DBG_VALUE debug-use %1(p0), debug-use _, !11, !15, debug-location !13 - call void @llvm.dbg.value(metadata i32* %addr, i64 0, metadata !11, metadata !15), !dbg !13 -; CHECK: DBG_VALUE 123, 0, !11, !12, debug-location !13 - call void @llvm.dbg.value(metadata i32 123, i64 0, metadata !11, metadata !12), !dbg !13 -; CHECK: DBG_VALUE float 1.000000e+00, 0, !11, !12, debug-location !13 - call void @llvm.dbg.value(metadata float 1.000000e+00, i64 0, metadata !11, metadata !12), !dbg !13 -; CHECK: DBG_VALUE _, 0, !11, !12, debug-location !13 - call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !12), !dbg !13 - ret void -} - -; Function Attrs: nounwind readnone -declare void @llvm.dbg.declare(metadata, metadata, metadata) -declare void @llvm.dbg.value(metadata, i64, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!3, !4, !5} -!llvm.ident = !{!6} - -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 289075) (llvm/trunk 289080)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) -!1 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") -!2 = !{} -!3 = !{i32 2, !"Dwarf Version", i32 4} -!4 = !{i32 2, !"Debug Info Version", i32 3} -!5 = !{i32 1, !"PIC Level", i32 2} -!6 = !{!"clang version 4.0.0 (trunk 289075) (llvm/trunk 289080)"} -!7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) -!8 = !DISubroutineType(types: !9) -!9 = !{null, !10} -!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!11 = !DILocalVariable(name: "in", arg: 1, scope: !7, file: !1, line: 1, type: !10) -!12 = !DIExpression() -!13 = !DILocation(line: 1, column: 14, scope: !7) -!14 = !DILocation(line: 2, column: 1, scope: !7) -!15 = !DIExpression(DW_OP_deref) diff --git a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll b/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll deleted file mode 100644 index 196910e96ce3..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/dynamic-alloca.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc -mtriple=aarch64 -global-isel %s -o - -stop-after=irtranslator | FileCheck %s - -; CHECK-LABEL: name: test_simple_alloca -; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1 -; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32) -; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]] -; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]] -; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 4 -; CHECK: %sp = COPY [[ALIGNED_ALLOC]] -; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]] -; CHECK: %x0 = COPY [[ALLOC]] -define i8* @test_simple_alloca(i32 %numelts) { - %addr = alloca i8, i32 %numelts - ret i8* %addr -} - -; CHECK-LABEL: name: test_aligned_alloca -; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -1 -; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32) -; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]] -; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]] -; CHECK: [[ALIGNED_ALLOC:%[0-9]+]](p0) = G_PTR_MASK [[ALLOC]], 5 -; CHECK: %sp = COPY [[ALIGNED_ALLOC]] -; CHECK: [[ALLOC:%[0-9]+]](p0) = COPY [[ALIGNED_ALLOC]] -; CHECK: %x0 = COPY [[ALLOC]] -define i8* @test_aligned_alloca(i32 %numelts) { - %addr = alloca i8, i32 %numelts, align 32 - ret i8* %addr -} - -; CHECK-LABEL: name: test_natural_alloca -; CHECK: [[NUMELTS:%[0-9]+]](s32) = COPY %w0 -; CHECK: [[TYPE_SIZE:%[0-9]+]](s64) = G_CONSTANT i64 -16 -; CHECK: [[NUMELTS_64:%[0-9]+]](s64) = G_ZEXT [[NUMELTS]](s32) -; CHECK: [[NUMBYTES:%[0-9]+]](s64) = G_MUL [[NUMELTS_64]], [[TYPE_SIZE]] -; CHECK: [[SP_TMP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[ALLOC:%[0-9]+]](p0) = G_GEP [[SP_TMP]], [[NUMBYTES]] -; CHECK: %sp = COPY [[ALLOC]] -; CHECK: [[ALLOC_TMP:%[0-9]+]](p0) = COPY [[ALLOC]] -; CHECK: %x0 = COPY [[ALLOC_TMP]] -define i128* @test_natural_alloca(i32 %numelts) { - %addr = alloca i128, i32 %numelts - ret i128* %addr -} diff --git a/test/CodeGen/AArch64/GlobalISel/gisel-abort.ll b/test/CodeGen/AArch64/GlobalISel/gisel-abort.ll deleted file mode 100644 index a1480c46fe40..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/gisel-abort.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s - -; CHECK-NOT: fallback -; CHECK: empty -define void @empty() { - ret void -} - diff --git a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll deleted file mode 100644 index 3ecdb7bbedfb..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -O0 -aarch64-enable-global-isel-at-O=0 \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -O0 -aarch64-enable-global-isel-at-O=0 -global-isel-abort=2 \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -global-isel \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix NOFALLBACK - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -global-isel -global-isel-abort=2 \ -; RUN: | FileCheck %s --check-prefix ENABLED --check-prefix FALLBACK - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -O1 -aarch64-enable-global-isel-at-O=3 \ -; RUN: | FileCheck %s --check-prefix ENABLED - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -O1 -aarch64-enable-global-isel-at-O=0 \ -; RUN: | FileCheck %s --check-prefix DISABLED - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: -aarch64-enable-global-isel-at-O=-1 \ -; RUN: | FileCheck %s --check-prefix DISABLED - -; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \ -; RUN: | FileCheck %s --check-prefix DISABLED - -; ENABLED: IRTranslator -; ENABLED-NEXT: Legalizer -; ENABLED-NEXT: RegBankSelect -; ENABLED-NEXT: InstructionSelect -; ENABLED-NEXT: ResetMachineFunction - -; FALLBACK: AArch64 Instruction Selection -; NOFALLBACK-NOT: AArch64 Instruction Selection - -; DISABLED-NOT: IRTranslator - -; DISABLED: AArch64 Instruction Selection -; DISABLED: Expand ISel Pseudo-instructions - -define void @empty() { - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/gisel-fail-intermediate-legalizer.ll b/test/CodeGen/AArch64/GlobalISel/gisel-fail-intermediate-legalizer.ll deleted file mode 100644 index e333f742e04d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/gisel-fail-intermediate-legalizer.ll +++ /dev/null @@ -1,8 +0,0 @@ -;RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -global-isel-abort=2 %s 2>&1 | FileCheck %s -; CHECK: fallback -; CHECK-LABEL: foo -define i16 @foo(half* %p) { - %tmp0 = load half, half* %p - %tmp1 = fptoui half %tmp0 to i16 - ret i16 %tmp1 -} diff --git a/test/CodeGen/AArch64/GlobalISel/inline-asm.ll b/test/CodeGen/AArch64/GlobalISel/inline-asm.ll deleted file mode 100644 index 8ff7c4495dcc..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/inline-asm.ll +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 %s -o - | FileCheck %s - -; CHECK-LABEL: test_asm: -; CHECK: {{APP|InlineAsm Start}} -; CHECK: mov x0, {{x[0-9]+}} -; CHECK: {{NO_APP|InlineAsm End}} -define void @test_asm() { - call void asm sideeffect "mov x0, $0", "r"(i64 42) - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll deleted file mode 100644 index 8d1b02216ea7..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/irtranslator-bitcast.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s - -; Check that we don't invalidate the vreg map. -; This test is brittle: the invalidation only triggers when we grow the map. - -; CHECK-LABEL: name: test_bitcast_invalid_vreg -define i32 @test_bitcast_invalid_vreg() { - %tmp0 = add i32 1, 2 - %tmp1 = add i32 3, 4 - %tmp2 = add i32 5, 6 - %tmp3 = add i32 7, 8 - %tmp4 = add i32 9, 10 - %tmp5 = add i32 11, 12 - %tmp6 = add i32 13, 14 - %tmp7 = add i32 15, 16 - %tmp8 = add i32 17, 18 - %tmp9 = add i32 19, 20 - %tmp10 = add i32 21, 22 - %tmp11 = add i32 23, 24 - %tmp12 = add i32 25, 26 - %tmp13 = add i32 27, 28 - %tmp14 = add i32 29, 30 - %tmp15 = add i32 30, 30 - -; At this point we mapped 46 values. The 'i32 100' constant will grow the map. -; CHECK: %46(s32) = G_CONSTANT i32 100 -; CHECK: %w0 = COPY %46(s32) - %res = bitcast i32 100 to i32 - ret i32 %res -} diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll deleted file mode 100644 index ef4445111d7b..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll +++ /dev/null @@ -1,94 +0,0 @@ -; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator %s -o - | FileCheck %s - -@_ZTIi = external global i8* - -declare i32 @foo(i32) -declare i32 @__gxx_personality_v0(...) -declare i32 @llvm.eh.typeid.for(i8*) - -; CHECK-LABEL: name: bar -; CHECK: body: -; CHECK-NEXT: bb.1 (%ir-block.0): -; CHECK: successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]] -; CHECK: EH_LABEL -; CHECK: %w0 = COPY -; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0 -; CHECK: {{%[0-9]+}}(s32) = COPY %w0 -; CHECK: EH_LABEL -; CHECK: G_BR %[[GOOD]] - -; CHECK: [[BAD]] (landing-pad): -; CHECK: EH_LABEL -; CHECK: [[UNDEF:%[0-9]+]](s128) = IMPLICIT_DEF -; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[VAL_WITH_PTR:%[0-9]+]](s128) = G_INSERT [[UNDEF]], [[PTR]](p0), 0 -; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]] -; CHECK: [[PTR_SEL:%[0-9]+]](s128) = G_INSERT [[VAL_WITH_PTR]], [[SEL]](s32), 64 -; CHECK: [[PTR_RET:%[0-9]+]](s64) = G_EXTRACT [[PTR_SEL]](s128), 0 -; CHECK: [[SEL_RET:%[0-9]+]](s32) = G_EXTRACT [[PTR_SEL]](s128), 64 -; CHECK: %x0 = COPY [[PTR_RET]] -; CHECK: %w1 = COPY [[SEL_RET]] - -; CHECK: [[GOOD]]: -; CHECK: [[SEL:%[0-9]+]](s32) = G_CONSTANT i32 1 -; CHECK: {{%[0-9]+}}(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64 - -define { i8*, i32 } @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { - %res32 = invoke i32 @foo(i32 42) to label %continue unwind label %broken - - -broken: - %ptr.sel = landingpad { i8*, i32 } catch i8* bitcast(i8** @_ZTIi to i8*) - ret { i8*, i32 } %ptr.sel - -continue: - %sel.int = tail call i32 @llvm.eh.typeid.for(i8* bitcast(i8** @_ZTIi to i8*)) - %res.good = insertvalue { i8*, i32 } undef, i32 %sel.int, 1 - ret { i8*, i32 } %res.good -} - -; CHECK-LABEL: name: test_invoke_indirect -; CHECK: [[CALLEE:%[0-9]+]](p0) = COPY %x0 -; CHECK: BLR [[CALLEE]] -define void @test_invoke_indirect(void()* %callee) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { - invoke void %callee() to label %continue unwind label %broken - -broken: - landingpad { i8*, i32 } catch i8* bitcast(i8** @_ZTIi to i8*) - ret void - -continue: - ret void -} - -; CHECK-LABEL: name: test_invoke_varargs - -; CHECK: [[NULL:%[0-9]+]](p0) = G_CONSTANT i64 0 -; CHECK: [[ANSWER:%[0-9]+]](s32) = G_CONSTANT i32 42 -; CHECK: [[ONE:%[0-9]+]](s32) = G_FCONSTANT float 1.0 - -; CHECK: %x0 = COPY [[NULL]] - -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 0 -; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64) -; CHECK: G_STORE [[ANSWER]](s32), [[SLOT]] - -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 8 -; CHECK: [[SLOT:%[0-9]+]](p0) = G_GEP [[SP]], [[OFFSET]](s64) -; CHECK: G_STORE [[ONE]](s32), [[SLOT]] - -; CHECK: BL @printf -declare void @printf(i8*, ...) -define void @test_invoke_varargs() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { - invoke void(i8*, ...) @printf(i8* null, i32 42, float 1.0) to label %continue unwind label %broken - -broken: - landingpad { i8*, i32 } catch i8* bitcast(i8** @_ZTIi to i8*) - ret void - -continue: - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/test/CodeGen/AArch64/GlobalISel/legalize-add.mir deleted file mode 100644 index 9b27198b961a..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ /dev/null @@ -1,121 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_add_big() { - entry: - ret void - } - define void @test_scalar_add_small() { - entry: - ret void - } - define void @test_vector_add() { - entry: - ret void - } -... - ---- -name: test_scalar_add_big -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_add_big - ; CHECK-NOT: G_MERGE_VALUES - ; CHECK-NOT: G_UNMERGE_VALUES - ; CHECK-DAG: [[CARRY0_32:%.*]](s32) = G_CONSTANT i32 0 - ; CHECK-DAG: [[CARRY0:%[0-9]+]](s1) = G_TRUNC [[CARRY0_32]] - ; CHECK: [[RES_LO:%.*]](s64), [[CARRY:%.*]](s1) = G_UADDE %0, %2, [[CARRY0]] - ; CHECK: [[RES_HI:%.*]](s64), {{%.*}}(s1) = G_UADDE %1, %3, [[CARRY]] - ; CHECK-NOT: G_MERGE_VALUES - ; CHECK-NOT: G_UNMERGE_VALUES - ; CHECK: %x0 = COPY [[RES_LO]] - ; CHECK: %x1 = COPY [[RES_HI]] - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = COPY %x2 - %3(s64) = COPY %x3 - %4(s128) = G_MERGE_VALUES %0, %1 - %5(s128) = G_MERGE_VALUES %2, %3 - %6(s128) = G_ADD %4, %5 - %7(s64), %8(s64) = G_UNMERGE_VALUES %6 - %x0 = COPY %7 - %x1 = COPY %8 -... - ---- -name: test_scalar_add_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_add_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_ADD [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_ADD %2, %3 - %5(s64) = G_ANYEXT %4 - %x0 = COPY %5 -... - ---- -name: test_vector_add -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0.entry: - liveins: %q0, %q1, %q2, %q3 - ; CHECK-LABEL: name: test_vector_add - ; CHECK-NOT: G_EXTRACT - ; CHECK-NOT: G_SEQUENCE - ; CHECK: [[RES_LO:%.*]](<2 x s64>) = G_ADD %0, %2 - ; CHECK: [[RES_HI:%.*]](<2 x s64>) = G_ADD %1, %3 - ; CHECK-NOT: G_EXTRACT - ; CHECK-NOT: G_SEQUENCE - ; CHECK: %q0 = COPY [[RES_LO]] - ; CHECK: %q1 = COPY [[RES_HI]] - - %0(<2 x s64>) = COPY %q0 - %1(<2 x s64>) = COPY %q1 - %2(<2 x s64>) = COPY %q2 - %3(<2 x s64>) = COPY %q3 - %4(<4 x s64>) = G_MERGE_VALUES %0, %1 - %5(<4 x s64>) = G_MERGE_VALUES %2, %3 - %6(<4 x s64>) = G_ADD %4, %5 - %7(<2 x s64>), %8(<2 x s64>) = G_UNMERGE_VALUES %6 - %q0 = COPY %7 - %q1 = COPY %8 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/test/CodeGen/AArch64/GlobalISel/legalize-and.mir deleted file mode 100644 index 75e1d5163532..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-and.mir +++ /dev/null @@ -1,37 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_and_small() { - entry: - ret void - } -... - ---- -name: test_scalar_and_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_and_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_AND [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_AND %2, %3 - %5(s64) = G_ANYEXT %2 - %x0 = COPY %5 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir deleted file mode 100644 index 29f83b362895..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ /dev/null @@ -1,45 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_icmp() { - entry: - ret void - } -... - ---- -name: test_icmp -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } - - { id: 9, class: _ } - - { id: 10, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - %1(s64) = COPY %x0 - - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - - ; CHECK: %4(s1) = G_ICMP intpred(sge), %0(s64), %1 - %4(s1) = G_ICMP intpred(sge), %0, %1 - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3 - ; CHECK: %8(s1) = G_ICMP intpred(ult), [[LHS32]](s32), [[RHS32]] - %8(s1) = G_ICMP intpred(ult), %2, %3 - - %9(p0) = G_INTTOPTR %0(s64) - %10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0) -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir deleted file mode 100644 index fab6dcf43346..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir +++ /dev/null @@ -1,132 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_combines_1() { ret void } - define void @test_combines_2() { ret void } - define void @test_combines_3() { ret void } - define void @test_combines_4() { ret void } - define void @test_combines_5() { ret void } - define void @test_combines_6() { ret void } -... - ---- -name: test_combines_1 -body: | - bb.0: - liveins: %w0 - - %0:_(s32) = COPY %w0 - %1:_(s8) = G_TRUNC %0 - - ; Only one of these extracts can be eliminated, the offsets don't match - ; properly in the other cases. - ; CHECK-LABEL: name: test_combines_1 - ; CHECK: %2(s32) = G_SEQUENCE %1(s8), 1 - ; CHECK: %3(s8) = G_EXTRACT %2(s32), 0 - ; CHECK-NOT: G_EXTRACT - ; CHECK: %5(s8) = G_EXTRACT %2(s32), 2 - ; CHECK: %6(s32) = G_ZEXT %1(s8) - - %2:_(s32) = G_SEQUENCE %1, 1 - %3:_(s8) = G_EXTRACT %2, 0 - %4:_(s8) = G_EXTRACT %2, 1 - %5:_(s8) = G_EXTRACT %2, 2 - %6:_(s32) = G_ZEXT %4 -... - ---- -name: test_combines_2 -body: | - bb.0: - liveins: %w0 - - %0:_(s32) = COPY %w0 - - ; Similarly, here the types don't match. - ; CHECK-LABEL: name: test_combines_2 - ; CHECK: %2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 32 - ; CHECK: %3(s1) = G_EXTRACT %2(s64), 0 - ; CHECK: %4(s64) = G_EXTRACT %2(s64), 0 - %1:_(s32) = G_ADD %0, %0 - %2:_(s64) = G_SEQUENCE %0, 0, %1, 32 - %3:_(s1) = G_EXTRACT %2, 0 - %4:_(s64) = G_EXTRACT %2, 0 -... - ---- -name: test_combines_3 -body: | - bb.0: - liveins: %w0 - - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_combines_3 - ; CHECK: %1(s32) = G_ADD %0, %0 - ; CHECK-NOT: G_SEQUENCE - ; CHECK-NOT: G_EXTRACT - ; CHECK: %5(s32) = G_ADD %0, %1 - %1:_(s32) = G_ADD %0, %0 - %2:_(s64) = G_SEQUENCE %0, 0, %1, 32 - %3:_(s32) = G_EXTRACT %2, 0 - %4:_(s32) = G_EXTRACT %2, 32 - %5:_(s32) = G_ADD %3, %4 -... - ---- -name: test_combines_4 -body: | - bb.0: - liveins: %x0 - - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_combines_4 - ; CHECK: %2(<2 x s32>) = G_EXTRACT %1(s128), 0 - ; CHECK: %3(<2 x s32>) = G_ADD %2, %2 - %1:_(s128) = G_SEQUENCE %0, 0, %0, 64 - %2:_(<2 x s32>) = G_EXTRACT %1, 0 - %3:_(<2 x s32>) = G_ADD %2, %2 -... - ---- -name: test_combines_5 -body: | - bb.0: - liveins: %w0 - - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_combines_5 - ; CHECK-NOT: G_SEQUENCE - ; CHECK-NOT: G_EXTRACT - ; CHECK: %5(s32) = G_ADD %0, %1 - %1:_(s32) = G_ADD %0, %0 - %2:_(s64) = G_SEQUENCE %0, 0, %1, 32 - %3:_(s32) = G_EXTRACT %2, 0 - %4:_(s32) = G_EXTRACT %2, 32 - %5:_(s32) = G_ADD %3, %4 -... - ---- -name: test_combines_6 -body: | - bb.0: - liveins: %w0 - - ; CHECK-LABEL: name: test_combines_6 - ; CHECK: %0(s32) = COPY %w0 - %0:_(s32) = COPY %w0 - - ; Check that we replace all the uses of a G_EXTRACT. - ; CHECK-NOT: G_SEQUENCE - ; CHECK-NOT: G_EXTRACT - ; CHECK: %3(s32) = G_MUL %0, %0 - ; CHECK: %4(s32) = G_ADD %0, %3 - %1:_(s32) = G_SEQUENCE %0, 0 - %2:_(s32) = G_EXTRACT %1, 0 - %3:_(s32) = G_MUL %2, %2 - %4:_(s32) = G_ADD %2, %3 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir b/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir deleted file mode 100644 index 16d9e59698fe..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir +++ /dev/null @@ -1,77 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_constant() { - entry: - ret void - } - define void @test_fconstant() { - entry: - ret void - } - @var = global i8 0 - define i8* @test_global() { ret i8* undef } -... - ---- -name: test_constant -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - ; CHECK-LABEL: name: test_constant - ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 0 - ; CHECK: %0(s1) = G_TRUNC [[TMP]] - ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 42 - ; CHECK: %1(s8) = G_TRUNC [[TMP]] - ; CHECK: [[TMP:%[0-9]+]](s32) = G_CONSTANT i32 -1 - ; CHECK: %2(s16) = G_TRUNC [[TMP]] - ; CHECK: %3(s32) = G_CONSTANT i32 -1 - ; CHECK: %4(s64) = G_CONSTANT i64 1 - ; CHECK: %5(s64) = G_CONSTANT i64 0 - - %0(s1) = G_CONSTANT i1 0 - %1(s8) = G_CONSTANT i8 42 - %2(s16) = G_CONSTANT i16 65535 - %3(s32) = G_CONSTANT i32 -1 - %4(s64) = G_CONSTANT i64 1 - %5(s64) = G_CONSTANT i64 0 -... - ---- -name: test_fconstant -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } -body: | - bb.0.entry: - ; CHECK-LABEL: name: test_fconstant - ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00 - ; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00 - ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000 - ; CHECK: %2(s16) = G_FPTRUNC [[TMP]] - - %0(s32) = G_FCONSTANT float 1.0 - %1(s64) = G_FCONSTANT double 2.0 - %2(s16) = G_FCONSTANT half 0.0 -... - ---- -name: test_global -registers: - - { id: 0, class: _ } -body: | - bb.0: - ; CHECK-LABEL: name: test_global - ; CHECK: %0(p0) = G_GLOBAL_VALUE @var - - %0(p0) = G_GLOBAL_VALUE @var -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/test/CodeGen/AArch64/GlobalISel/legalize-div.mir deleted file mode 100644 index c6e0aabfd2c0..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-div.mir +++ /dev/null @@ -1,42 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_div() { - entry: - ret void - } -... - ---- -name: test_div -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3 - ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]] - ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]] - %4(s8) = G_SDIV %2, %3 - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3 - ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_UDIV [[LHS32]], [[RHS32]] - ; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]] - %5(s8) = G_UDIV %2, %3 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll deleted file mode 100644 index 23e7d5163e5a..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll +++ /dev/null @@ -1,53 +0,0 @@ -; RUN: llc -O0 -mtriple=aarch64-apple-ios -verify-machineinstrs -global-isel -stop-after=legalizer %s -o - | FileCheck %s - -@_ZTIi = external global i8* - -declare i32 @foo(i32) -declare i32 @__gxx_personality_v0(...) -declare i32 @llvm.eh.typeid.for(i8*) -declare void @_Unwind_Resume(i8*) - -; CHECK: name: bar -; CHECK: body: -; CHECK-NEXT: bb.1 (%ir-block.0): -; CHECK: successors: %{{bb.[0-9]+.continue.*}}%[[LP:bb.[0-9]+.cleanup]] - -; CHECK: [[LP]] (landing-pad): -; CHECK: EH_LABEL - -; CHECK: [[PTR:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[STRUCT_PTR:%[0-9]+]](s64) = G_PTRTOINT [[PTR]](p0) - -; CHECK: [[SEL_PTR:%[0-9]+]](p0) = COPY %x1 -; CHECK: [[SEL:%[0-9]+]](s32) = G_PTRTOINT [[SEL_PTR]] -; CHECK: [[STRUCT_SEL:%[0-9]+]](s64) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 0 - -; CHECK: [[STRUCT:%[0-9]+]](s128) = G_MERGE_VALUES [[STRUCT_PTR]](s64), [[STRUCT_SEL]] - -; CHECK: [[PTR:%[0-9]+]](p0) = G_EXTRACT [[STRUCT]](s128), 0 -; CHECK: G_STORE [[PTR]](p0), {{%[0-9]+}}(p0) - -; CHECK: [[SEL:%[0-9]+]](s32) = G_EXTRACT [[STRUCT]](s128), 64 -; CHECK: G_STORE [[SEL]](s32), {{%[0-9]+}}(p0) - -define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { - %exn.slot = alloca i8* - %ehselector.slot = alloca i32 - %1 = invoke i32 @foo(i32 42) to label %continue unwind label %cleanup - -cleanup: - %2 = landingpad { i8*, i32 } cleanup - %3 = extractvalue { i8*, i32 } %2, 0 - store i8* %3, i8** %exn.slot, align 8 - %4 = extractvalue { i8*, i32 } %2, 1 - store i32 %4, i32* %ehselector.slot, align 4 - br label %eh.resume - -continue: - ret void - -eh.resume: - %exn = load i8*, i8** %exn.slot, align 8 - call void @_Unwind_Resume(i8* %exn) - unreachable -} diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir deleted file mode 100644 index 70b55e4ebc66..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir +++ /dev/null @@ -1,79 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_ext() { - entry: - ret void - } -... - ---- -name: test_ext -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } - - { id: 9, class: _ } - - { id: 10, class: _ } - - { id: 11, class: _ } - - { id: 12, class: _ } - - { id: 13, class: _ } - - { id: 14, class: _ } - - { id: 15, class: _ } - - { id: 16, class: _ } - - { id: 17, class: _ } - - { id: 18, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - - ; CHECK: %1(s1) = G_TRUNC %0 - ; CHECK: %2(s8) = G_TRUNC %0 - ; CHECK: %3(s16) = G_TRUNC %0 - ; CHECK: %4(s32) = G_TRUNC %0 - %1(s1) = G_TRUNC %0 - %2(s8) = G_TRUNC %0 - %3(s16) = G_TRUNC %0 - %4(s32) = G_TRUNC %0 - - ; CHECK: %5(s64) = G_ANYEXT %1 - ; CHECK: %6(s64) = G_ZEXT %2 - ; CHECK: %7(s64) = G_ANYEXT %3 - ; CHECK: %8(s64) = G_SEXT %4 - %5(s64) = G_ANYEXT %1 - %6(s64) = G_ZEXT %2 - %7(s64) = G_ANYEXT %3 - %8(s64) = G_SEXT %4 - - ; CHECK: %9(s32) = G_SEXT %1 - ; CHECK: %10(s32) = G_ZEXT %2 - ; CHECK: %11(s32) = G_ANYEXT %3 - %9(s32) = G_SEXT %1 - %10(s32) = G_ZEXT %2 - %11(s32) = G_ANYEXT %3 - - ; CHECK: %12(s32) = G_ZEXT %1 - ; CHECK: %13(s32) = G_ANYEXT %2 - ; CHECK: %14(s32) = G_SEXT %3 - %12(s32) = G_ZEXT %1 - %13(s32) = G_ANYEXT %2 - %14(s32) = G_SEXT %3 - - ; CHECK: %15(s8) = G_ZEXT %1 - ; CHECK: %16(s16) = G_ANYEXT %2 - %15(s8) = G_ZEXT %1 - %16(s16) = G_ANYEXT %2 - - ; CHECK: %18(s64) = G_FPEXT %17 - %17(s32) = G_TRUNC %0 - %18(s64) = G_FPEXT %17 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir deleted file mode 100644 index 8cdc7b78b1e9..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir +++ /dev/null @@ -1,35 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_icmp() { - entry: - ret void - } -... - ---- -name: test_icmp -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - %1(s64) = COPY %x0 - - %2(s32) = G_TRUNC %0 - %3(s32) = G_TRUNC %1 - - ; CHECK: %4(s1) = G_FCMP floatpred(oge), %0(s64), %1 - %4(s1) = G_FCMP floatpred(oge), %0, %1 - - ; CHECK: %5(s1) = G_FCMP floatpred(uno), %2(s32), %3 - %5(s1) = G_FCMP floatpred(uno), %2, %3 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir deleted file mode 100644 index 8b5cbdfa55e3..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-fneg.mir +++ /dev/null @@ -1,48 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_fneg_f32() { - entry: - ret void - } - define void @test_fneg_f64() { - entry: - ret void - } -... ---- -name: test_fneg_f32 -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.1: - liveins: %s0 - ; CHECK-LABEL: name: test_fneg_f32 - ; CHECK: [[VAR:%[0-9]+]](s32) = COPY %s0 - ; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00 - ; CHECK: [[RES:%[0-9]+]](s32) = G_FSUB [[ZERO]], [[VAR]] - ; CHECK: %s0 = COPY [[RES]](s32) - %0(s32) = COPY %s0 - %1(s32) = G_FNEG %0 - %s0 = COPY %1(s32) -... ---- -name: test_fneg_f64 -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.1: - liveins: %d0 - ; CHECK-LABEL: name: test_fneg_f64 - ; CHECK: [[VAR:%[0-9]+]](s64) = COPY %d0 - ; CHECK: [[ZERO:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00 - ; CHECK: [[RES:%[0-9]+]](s64) = G_FSUB [[ZERO]], [[VAR]] - ; CHECK: %d0 = COPY [[RES]](s64) - %0(s64) = COPY %d0 - %1(s64) = G_FNEG %0 - %d0 = COPY %1(s64) -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir b/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir deleted file mode 100644 index f79d0382ea7c..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir +++ /dev/null @@ -1,201 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - - define void @test_fptosi_s32_s32() { ret void } - define void @test_fptoui_s32_s32() { ret void } - define void @test_fptosi_s32_s64() { ret void } - define void @test_fptoui_s32_s64() { ret void } - - define void @test_fptosi_s64_s32() { ret void } - define void @test_fptoui_s64_s32() { ret void } - define void @test_fptosi_s64_s64() { ret void } - define void @test_fptoui_s64_s64() { ret void } - - define void @test_fptosi_s1_s32() { ret void } - define void @test_fptoui_s1_s32() { ret void } - - define void @test_fptosi_s8_s64() { ret void } - define void @test_fptoui_s8_s64() { ret void } - - define void @test_fptosi_s16_s32() { ret void } - define void @test_fptoui_s16_s32() { ret void } -... - ---- -name: test_fptosi_s32_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptosi_s32_s32 - ; CHECK: %1(s32) = G_FPTOSI %0 - %1:_(s32) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s32_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptoui_s32_s32 - ; CHECK: %1(s32) = G_FPTOUI %0 - %1:_(s32) = G_FPTOUI %0 -... - ---- -name: test_fptosi_s32_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptosi_s32_s64 - ; CHECK: %1(s32) = G_FPTOSI %0 - %1:_(s32) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s32_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptoui_s32_s64 - ; CHECK: %1(s32) = G_FPTOUI %0 - %1:_(s32) = G_FPTOUI %0 -... - ---- -name: test_fptosi_s64_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptosi_s64_s32 - ; CHECK: %1(s64) = G_FPTOSI %0 - %1:_(s64) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s64_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptoui_s64_s32 - ; CHECK: %1(s64) = G_FPTOUI %0 - %1:_(s64) = G_FPTOUI %0 -... - ---- -name: test_fptosi_s64_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptosi_s64_s64 - ; CHECK: %1(s64) = G_FPTOSI %0 - %1:_(s64) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s64_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptoui_s64_s64 - ; CHECK: %1(s64) = G_FPTOUI %0 - %1:_(s64) = G_FPTOUI %0 -... - - - ---- -name: test_fptosi_s1_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptosi_s1_s32 - ; CHECK: %2(s32) = G_FPTOSI %0 - ; CHECK: %1(s1) = G_TRUNC %2 - %1:_(s1) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s1_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptoui_s1_s32 - ; CHECK: %2(s32) = G_FPTOUI %0 - ; CHECK: %1(s1) = G_TRUNC %2 - %1:_(s1) = G_FPTOUI %0 -... - ---- -name: test_fptosi_s8_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptosi_s8_s64 - ; CHECK: %2(s32) = G_FPTOSI %0 - ; CHECK: %1(s8) = G_TRUNC %2 - %1:_(s8) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s8_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_fptoui_s8_s64 - ; CHECK: %2(s32) = G_FPTOUI %0 - ; CHECK: %1(s8) = G_TRUNC %2 - %1:_(s8) = G_FPTOUI %0 -... - ---- -name: test_fptosi_s16_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptosi_s16_s32 - ; CHECK: %2(s32) = G_FPTOSI %0 - ; CHECK: %1(s16) = G_TRUNC %2 - %1:_(s16) = G_FPTOSI %0 -... - ---- -name: test_fptoui_s16_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_fptoui_s16_s32 - ; CHECK: %2(s32) = G_FPTOUI %0 - ; CHECK: %1(s16) = G_TRUNC %2 - %1:_(s16) = G_FPTOUI %0 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir b/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir deleted file mode 100644 index d6ec983c2067..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir +++ /dev/null @@ -1,31 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_gep_small() { - entry: - ret void - } -... - ---- -name: test_gep_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_gep_small - ; CHECK: [[OFFSET_EXT:%[0-9]+]](s64) = G_SEXT %2(s8) - ; CHECK: %3(p0) = G_GEP %0, [[OFFSET_EXT]](s64) - - %0(p0) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %1 - %3(p0) = G_GEP %0, %2(s8) - %x0 = COPY %3 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir deleted file mode 100644 index 43aa06ba3d90..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir +++ /dev/null @@ -1,33 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_copy() { ret void } - define void @test_targetspecific() { ret void } -... - ---- -name: test_copy -registers: - - { id: 0, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK-LABEL: name: test_copy - ; CHECK: %0(s64) = COPY %x0 - ; CHECK-NEXT: %x0 = COPY %0 - - %0(s64) = COPY %x0 - %x0 = COPY %0 -... - ---- -name: test_targetspecific -body: | - bb.0: - ; CHECK-LABEL: name: test_targetspecific - ; CHECK: RET_ReallyLR - - RET_ReallyLR -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir deleted file mode 100644 index 917f181099ec..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir +++ /dev/null @@ -1,141 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_inserts_1() { ret void } - define void @test_inserts_2() { ret void } - define void @test_inserts_3() { ret void } - define void @test_inserts_4() { ret void } - define void @test_inserts_5() { ret void } - define void @test_inserts_6() { ret void } -... - ---- -name: test_inserts_1 -body: | - bb.0: - liveins: %w0 - - ; Low part of insertion wipes out the old register entirely, so %0 gets - ; forwarded to the G_STORE. Hi part is unchanged so (split) G_LOAD gets - ; forwarded. - ; CHECK-LABEL: name: test_inserts_1 - ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD - ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD - ; CHECK: G_STORE %0(s64) - ; CHECK: G_STORE [[HI]] - %0:_(s64) = COPY %x0 - %1:_(s32) = COPY %w1 - %2:_(p0) = COPY %x2 - %3:_(s128) = G_LOAD %2(p0) :: (load 16) - %4:_(s128) = G_INSERT %3(s128), %0(s64), 0 - G_STORE %4(s128), %2(p0) :: (store 16) - RET_ReallyLR -... - ---- -name: test_inserts_2 -body: | - bb.0: - liveins: %w0 - - ; Low insertion wipes out the old register entirely, so %0 gets forwarded - ; to the G_STORE again. Second insertion is real. - ; CHECK-LABEL: name: test_inserts_2 - ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD - ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD - ; CHECK: [[NEWHI:%[0-9]+]](s64) = G_INSERT [[HI]], %1(s32), 0 - ; CHECK: G_STORE %0(s64) - ; CHECK: G_STORE [[NEWHI]] - %0:_(s64) = COPY %x0 - %1:_(s32) = COPY %w1 - %2:_(p0) = COPY %x2 - %3:_(s128) = G_LOAD %2(p0) :: (load 16) - %4:_(s128) = G_INSERT %3(s128), %0(s64), 0 - %5:_(s128) = G_INSERT %4(s128), %1(s32), 64 - G_STORE %5(s128), %2(p0) :: (store 16) - RET_ReallyLR -... - ---- -name: test_inserts_3 -body: | - bb.0: - liveins: %w0 - - ; I'm not entirely convinced inserting a p0 into an s64 is valid, but it's - ; certainly better than the alternative of directly forwarding the value - ; which would cause a nasty type mismatch. - ; CHECK-LABEL: name: test_inserts_3 - ; CHECK: [[LO:%[0-9]+]](s64) = G_LOAD - ; CHECK: [[HI:%[0-9]+]](s64) = G_LOAD - ; CHECK: [[NEWLO:%[0-9]+]](s64) = G_PTRTOINT %0(p0) - ; CHECK: G_STORE [[NEWLO]](s64) - ; CHECK: G_STORE [[HI]] - %0:_(p0) = COPY %x0 - %1:_(s32) = COPY %w1 - %2:_(p0) = COPY %x2 - %3:_(s128) = G_LOAD %2(p0) :: (load 16) - %4:_(s128) = G_INSERT %3(s128), %0(p0), 0 - G_STORE %4(s128), %2(p0) :: (store 16) - RET_ReallyLR -... - ---- -name: test_inserts_4 -body: | - bb.0: - liveins: %w0 - - ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair. - ; CHECK-LABEL: name: test_inserts_4 - ; CHECK: [[VALEXT:%[0-9]+]](s32) = G_ANYEXT %1(s8) - ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %0(s1), 0 - ; CHECK: %3(s8) = G_TRUNC [[VAL]](s32) - %0:_(s1) = COPY %w0 - %1:_(s8) = COPY %w1 - %2:_(p0) = COPY %x2 - %3:_(s8) = G_INSERT %1(s8), %0(s1), 0 - G_STORE %3(s8), %2(p0) :: (store 1) - RET_ReallyLR -... - ---- -name: test_inserts_5 -body: | - bb.0: - liveins: %x0, %x1, %x2 - - - ; CHECK-LABEL: name: test_inserts_5 - ; CHECK: [[INS_LO:%[0-9]+]](s32) = G_EXTRACT %2(s64), 0 - ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, [[INS_LO]](s32), 32 - ; CHECK: [[INS_HI:%[0-9]+]](s32) = G_EXTRACT %2(s64), 32 - ; CHECK: [[VAL_HI:%[0-9]+]](s64) = G_INSERT %1, [[INS_HI]](s32), 0 - ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64) - %0:_(s64) = COPY %x0 - %1:_(s64) = COPY %x1 - %2:_(s64) = COPY %x2 - %3:_(s128) = G_MERGE_VALUES %0, %1 - %4:_(s128) = G_INSERT %3, %2, 32 - RET_ReallyLR -... - ---- -name: test_inserts_6 -body: | - bb.0: - liveins: %x0, %x1, %x2 - - - ; CHECK-LABEL: name: test_inserts_6 - ; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, %2(s32), 32 - ; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), %1(s64) - %0:_(s64) = COPY %x0 - %1:_(s64) = COPY %x1 - %2:_(s32) = COPY %w2 - %3:_(s128) = G_MERGE_VALUES %0, %1 - %4:_(s128) = G_INSERT %3, %2, 32 - RET_ReallyLR -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir deleted file mode 100644 index 69e72bcb1f38..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir +++ /dev/null @@ -1,206 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - - define void @test_sitofp_s32_s32() { ret void } - define void @test_uitofp_s32_s32() { ret void } - define void @test_sitofp_s32_s64() { ret void } - define void @test_uitofp_s32_s64() { ret void } - - define void @test_sitofp_s64_s32() { ret void } - define void @test_uitofp_s64_s32() { ret void } - define void @test_sitofp_s64_s64() { ret void } - define void @test_uitofp_s64_s64() { ret void } - - define void @test_sitofp_s32_s1() { ret void } - define void @test_uitofp_s32_s1() { ret void } - - define void @test_sitofp_s64_s8() { ret void } - define void @test_uitofp_s64_s8() { ret void } - - define void @test_sitofp_s32_s16() { ret void } - define void @test_uitofp_s32_s16() { ret void } -... - ---- -name: test_sitofp_s32_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_sitofp_s32_s32 - ; CHECK: %1(s32) = G_SITOFP %0 - %1:_(s32) = G_SITOFP %0 -... - ---- -name: test_uitofp_s32_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_uitofp_s32_s32 - ; CHECK: %1(s32) = G_UITOFP %0 - %1:_(s32) = G_UITOFP %0 -... - ---- -name: test_sitofp_s32_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_sitofp_s32_s64 - ; CHECK: %1(s32) = G_SITOFP %0 - %1:_(s32) = G_SITOFP %0 -... - ---- -name: test_uitofp_s32_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_uitofp_s32_s64 - ; CHECK: %1(s32) = G_UITOFP %0 - %1:_(s32) = G_UITOFP %0 -... - ---- -name: test_sitofp_s64_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_sitofp_s64_s32 - ; CHECK: %1(s64) = G_SITOFP %0 - %1:_(s64) = G_SITOFP %0 -... - ---- -name: test_uitofp_s64_s32 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - - ; CHECK-LABEL: name: test_uitofp_s64_s32 - ; CHECK: %1(s64) = G_UITOFP %0 - %1:_(s64) = G_UITOFP %0 -... - ---- -name: test_sitofp_s64_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_sitofp_s64_s64 - ; CHECK: %1(s64) = G_SITOFP %0 - %1:_(s64) = G_SITOFP %0 -... - ---- -name: test_uitofp_s64_s64 -body: | - bb.0: - liveins: %x0 - %0:_(s64) = COPY %x0 - - ; CHECK-LABEL: name: test_uitofp_s64_s64 - ; CHECK: %1(s64) = G_UITOFP %0 - %1:_(s64) = G_UITOFP %0 -... - - ---- -name: test_sitofp_s32_s1 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s1) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_sitofp_s32_s1 - ; CHECK: %3(s32) = G_SEXT %1 - ; CHECK: %2(s32) = G_SITOFP %3 - %2:_(s32) = G_SITOFP %1 -... - ---- -name: test_uitofp_s32_s1 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s1) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_uitofp_s32_s1 - ; CHECK: %3(s32) = G_ZEXT %1 - ; CHECK: %2(s32) = G_UITOFP %3 - %2:_(s32) = G_UITOFP %1 -... - ---- -name: test_sitofp_s64_s8 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s8) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_sitofp_s64_s8 - ; CHECK: %3(s32) = G_SEXT %1 - ; CHECK: %2(s64) = G_SITOFP %3 - %2:_(s64) = G_SITOFP %1 -... - ---- -name: test_uitofp_s64_s8 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s8) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_uitofp_s64_s8 - ; CHECK: %3(s32) = G_ZEXT %1 - ; CHECK: %2(s64) = G_UITOFP %3 - %2:_(s64) = G_UITOFP %1 -... - ---- -name: test_sitofp_s32_s16 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s16) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_sitofp_s32_s16 - ; CHECK: %3(s32) = G_SEXT %1 - ; CHECK: %2(s32) = G_SITOFP %3 - %2:_(s32) = G_SITOFP %1 -... - ---- -name: test_uitofp_s32_s16 -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - %1:_(s16) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_uitofp_s32_s16 - ; CHECK: %3(s32) = G_ZEXT %1 - ; CHECK: %2(s32) = G_UITOFP %3 - %2:_(s32) = G_UITOFP %1 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir deleted file mode 100644 index c806b4a7060d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ /dev/null @@ -1,117 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_load(i8* %addr) { - entry: - ret void - } - define void @test_store(i8* %addr) { - entry: - ret void - } -... - ---- -name: test_load -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_load - %0(p0) = COPY %x0 - - ; CHECK: [[BIT8:%[0-9]+]](s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr) - ; CHECK: %1(s1) = G_TRUNC [[BIT8]] - %1(s1) = G_LOAD %0 :: (load 1 from %ir.addr) - - ; CHECK: %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr) - %2(s8) = G_LOAD %0 :: (load 1 from %ir.addr) - - ; CHECK: %3(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr) - %3(s16) = G_LOAD %0 :: (load 2 from %ir.addr) - - ; CHECK: %4(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr) - %4(s32) = G_LOAD %0 :: (load 4 from %ir.addr) - - ; CHECK: %5(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - %5(s64) = G_LOAD %0 :: (load 8 from %ir.addr) - - ; CHECK: %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - - ; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - - ; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0 - ; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64) - ; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD [[GEP0]](p0) :: (load 16 from %ir.addr) - ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8 - ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64) - ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr) - ; CHECK: %8(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64) - %8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr) -... - ---- -name: test_store -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_store - - %0(p0) = COPY %x0 - %1(s32) = COPY %w1 - - ; CHECK: [[BIT8:%[0-9]+]](s8) = G_ZEXT %2(s1) - ; CHECK: G_STORE [[BIT8]](s8), %0(p0) :: (store 1 into %ir.addr) - %2(s1) = G_TRUNC %1 - G_STORE %2, %0 :: (store 1 into %ir.addr) - - ; CHECK: G_STORE %3(s8), %0(p0) :: (store 1 into %ir.addr) - %3(s8) = G_TRUNC %1 - G_STORE %3, %0 :: (store 1 into %ir.addr) - - ; CHECK: G_STORE %4(s16), %0(p0) :: (store 2 into %ir.addr) - %4(s16) = G_TRUNC %1 - G_STORE %4, %0 :: (store 2 into %ir.addr) - - ; CHECK: G_STORE %1(s32), %0(p0) :: (store 4 into %ir.addr) - G_STORE %1, %0 :: (store 4 into %ir.addr) - - ; CHECK: G_STORE %5(s64), %0(p0) :: (store 8 into %ir.addr) - %5(s64) = G_PTRTOINT %0(p0) - G_STORE %5, %0 :: (store 8 into %ir.addr) - - ; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr) - G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr) - - ; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0 - ; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64) - ; CHECK: G_STORE %5(s64), [[GEP0]](p0) :: (store 16 into %ir.addr) - ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8 - ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64) - ; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr) - %6(s64) = G_PTRTOINT %0(p0) - %7(s128) = G_MERGE_VALUES %5, %6 - G_STORE %7, %0 :: (store 16 into %ir.addr) -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir deleted file mode 100644 index 1ea6e9c292f5..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir +++ /dev/null @@ -1,57 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_mul_small() { - entry: - ret void - } - define void @test_mul_overflow() { ret void } -... - ---- -name: test_scalar_mul_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_mul_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_MUL [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_MUL %2, %3 - %5(s64) = G_ANYEXT %2 - %x0 = COPY %5 -... - - ---- -name: test_mul_overflow -body: | - bb.0: - liveins: %x0, %x1, %w2, %w3 - - %0:_(s64) = COPY %x0 - %1:_(s64) = COPY %x1 - - ; CHECK-LABEL: name: test_mul_overflow - ; CHECK: %2(s64) = G_MUL %0, %1 - ; CHECK: [[HI:%[0-9]+]](s64) = G_SMULH %0, %1 - ; CHECK: [[ZERO:%[0-9]+]](s64) = G_CONSTANT i64 0 - ; CHECK: %3(s1) = G_ICMP intpred(ne), [[HI]](s64), [[ZERO]] - %2:_(s64), %3:_(s1) = G_SMULO %0, %1 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir b/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir deleted file mode 100644 index 9928ea54d2c9..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir +++ /dev/null @@ -1,29 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_legalize_merge_v3s32() { - ret void - } -... ---- -name: test_legalize_merge_v3s32 -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } -body: | - bb.0: - liveins: %w0, %w1, %w2 - ; CHECK-LABEL: name: test_legalize_merge_v3s32 - ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 - ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1 - ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2 - ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32) - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = COPY %w2 - %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32) -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/test/CodeGen/AArch64/GlobalISel/legalize-or.mir deleted file mode 100644 index e8b850982460..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-or.mir +++ /dev/null @@ -1,37 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_or_small() { - entry: - ret void - } -... - ---- -name: test_scalar_or_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_or_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_OR [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_OR %2, %3 - %5(s64) = G_ANYEXT %2 - %x0 = COPY %5 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir deleted file mode 100644 index 2becc2e134b5..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir +++ /dev/null @@ -1,38 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_pow() { - entry: - ret void - } -... - ---- -name: test_pow -body: | - bb.0.entry: - liveins: %d0, %d1, %s2, %s3 - - ; CHECK-LABEL: name: test_pow - ; CHECK: hasCalls: true - - %0:_(s64) = COPY %d0 - %1:_(s64) = COPY %d1 - %2:_(s32) = COPY %s2 - %3:_(s32) = COPY %s3 - - ; CHECK: %d0 = COPY %0 - ; CHECK: %d1 = COPY %1 - ; CHECK: BL $pow, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0 - ; CHECK: %4(s64) = COPY %d0 - %4:_(s64) = G_FPOW %0, %1 - - ; CHECK: %s0 = COPY %2 - ; CHECK: %s1 = COPY %3 - ; CHECK: BL $powf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0 - ; CHECK: %5(s32) = COPY %s0 - %5:_(s32) = G_FPOW %2, %3 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-property.mir b/test/CodeGen/AArch64/GlobalISel/legalize-property.mir deleted file mode 100644 index 1381484443e6..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-property.mir +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @legalized_property() { ret void } -... - ---- -# Check that we set the "legalized" property. -# CHECK-LABEL: name: legalized_property -# CHECK: legalized: true -name: legalized_property -legalized: false -body: | - bb.0: -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir deleted file mode 100644 index 50a4d93cbe20..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir +++ /dev/null @@ -1,73 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_rem() { - entry: - ret void - } -... - ---- -name: test_rem -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } - - { id: 9, class: _ } - - { id: 10, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - - ; CHECK: [[QUOT:%[0-9]+]](s64) = G_UDIV %0, %1 - ; CHECK: [[PROD:%[0-9]+]](s64) = G_MUL [[QUOT]], %1 - ; CHECK: [[RES:%[0-9]+]](s64) = G_SUB %0, [[PROD]] - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_UREM %0, %1 - - ; CHECK: [[QUOT:%[0-9]+]](s32) = G_SDIV %3, %4 - ; CHECK: [[PROD:%[0-9]+]](s32) = G_MUL [[QUOT]], %4 - ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB %3, [[PROD]] - %3(s32) = G_TRUNC %0 - %4(s32) = G_TRUNC %1 - %5(s32) = G_SREM %3, %4 - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %6 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7 - ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]] - ; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]] - - ; CHECK: [[QUOT32_2:%.*]](s32) = G_ANYEXT [[QUOT]](s8) - ; CHECK: [[RHS32_2:%.*]](s32) = G_ANYEXT %7(s8) - ; CHECK: [[PROD32:%.*]](s32) = G_MUL [[QUOT32_2]], [[RHS32_2]] - ; CHECK: [[PROD:%.*]](s8) = G_TRUNC [[PROD32]](s32) - - ; CHECK: [[LHS32_2:%.*]](s32) = G_ANYEXT %6(s8) - ; CHECK: [[PROD32_2:%.*]](s32) = G_ANYEXT [[PROD]](s8) - ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB [[LHS32_2]], [[PROD32_2]] - %6(s8) = G_TRUNC %0 - %7(s8) = G_TRUNC %1 - %8(s8) = G_SREM %6, %7 - - ; CHECK: %d0 = COPY %0 - ; CHECK: %d1 = COPY %1 - ; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0 - ; CHECK: %9(s64) = COPY %d0 - %9(s64) = G_FREM %0, %1 - - ; CHECK: %s0 = COPY %3 - ; CHECK: %s1 = COPY %4 - ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0 - ; CHECK: %10(s32) = COPY %s0 - %10(s32) = G_FREM %3, %4 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir deleted file mode 100644 index f75a2982a3f2..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir +++ /dev/null @@ -1,47 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_shift() { - entry: - ret void - } -... - ---- -name: test_shift -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3 - ; CHECK: [[RES32:%[0-9]+]](s32) = G_ASHR [[LHS32]], [[RHS32]] - ; CHECK: %4(s8) = G_TRUNC [[RES32]] - %4(s8) = G_ASHR %2, %3 - - ; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2 - ; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3 - ; CHECK: [[RES32:%[0-9]+]](s32) = G_LSHR [[LHS32]], [[RHS32]] - ; CHECK: %5(s8) = G_TRUNC [[RES32]] - %5(s8) = G_LSHR %2, %3 - - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_SHL [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - %6(s8) = G_SHL %2, %3 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir deleted file mode 100644 index cd24bccfe771..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir +++ /dev/null @@ -1,86 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_simple() { - entry: - ret void - next: - ret void - } -... - ---- -name: test_simple -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } - - { id: 9, class: _ } - - { id: 10, class: _ } - - { id: 11, class: _ } - - { id: 12, class: _ } - - { id: 13, class: _ } - - { id: 14, class: _ } - - { id: 15, class: _ } - - { id: 16, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - %0(s64) = COPY %x0 - - %1(s1) = G_TRUNC %0 - %2(s8) = G_TRUNC %0 - %3(s16) = G_TRUNC %0 - %4(s32) = G_TRUNC %0 - - ; CHECK-LABEL: name: test_simple - ; CHECK: %5(p0) = G_INTTOPTR %0 - ; CHECK: %6(s64) = G_PTRTOINT %5 - %5(p0) = G_INTTOPTR %0 - %6(s64) = G_PTRTOINT %5 - - ; CHECK: G_BRCOND %1(s1), %bb.1.next - G_BRCOND %1, %bb.1.next - - bb.1.next: - - ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %1(s1) - ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %1(s1) - ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]] - ; CHECK: %7(s1) = G_TRUNC [[RES]](s32) - %7(s1) = G_SELECT %1, %1, %1 - - ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]] - ; CHECK: %8(s8) = G_TRUNC [[RES]](s32) - %8(s8) = G_SELECT %1, %2, %2 - - ; CHECK: [[LHS:%[0-9]+]](s32) = G_ANYEXT %3(s16) - ; CHECK: [[RHS:%[0-9]+]](s32) = G_ANYEXT %3(s16) - ; CHECK: [[RES:%[0-9]+]](s32) = G_SELECT %1(s1), [[LHS]], [[RHS]] - ; CHECK: %9(s16) = G_TRUNC [[RES]](s32) - %9(s16) = G_SELECT %1, %3, %3 - - %10(s32) = G_SELECT %1, %4, %4 - %11(s64) = G_SELECT %1, %0, %0 - - ; CHECK: %12(<2 x s32>) = G_BITCAST %0 - ; CHECK: %13(s64) = G_BITCAST %12 - ; CHECK: %14(s32) = G_BITCAST %10 - ; CHECK: %15(<4 x s8>) = G_BITCAST %0 - ; CHECK: %16(<2 x s16>) = G_BITCAST %0 - %12(<2 x s32>) = G_BITCAST %0 - %13(s64) = G_BITCAST %12 - %14(s32) = G_BITCAST %10 - %15(<4 x s8>) = G_BITCAST %0 - %16(<2 x s16>) = G_BITCAST %0 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir deleted file mode 100644 index 82a1dd09c1a1..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir +++ /dev/null @@ -1,37 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_sub_small() { - entry: - ret void - } -... - ---- -name: test_scalar_sub_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_sub_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_SUB [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_SUB %2, %3 - %5(s64) = G_ANYEXT %2 - %x0 = COPY %5 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir deleted file mode 100644 index 8bda08d0a1d1..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir +++ /dev/null @@ -1,39 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_vaarg() { ret void } -... - ---- -name: test_vaarg -body: | - bb.0: - %0:_(p0) = COPY %x0 - - ; CHECK-LABEL: name: test_vaarg - ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8) - ; CHECK: %1(s8) = G_LOAD [[LIST]](p0) :: (load 1, align 8) - ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8 - ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64) - ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8) - %1:_(s8) = G_VAARG %0(p0), 1 - - ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8) - ; CHECK: %2(s64) = G_LOAD [[LIST]](p0) :: (load 8) - ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8 - ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64) - ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8) - %2:_(s64) = G_VAARG %0(p0), 8 - - ; CHECK: [[LIST:%[0-9]+]](p0) = G_LOAD %0(p0) :: (load 8) - ; CHECK: [[ALIGNM1:%[0-9]+]](s64) = G_CONSTANT i64 15 - ; CHECK: [[ALIGNTMP:%[0-9]+]](p0) = G_GEP [[LIST]], [[ALIGNM1]](s64) - ; CHECK: [[LIST:%[0-9]+]](p0) = G_PTR_MASK [[ALIGNTMP]], 4 - ; CHECK: %3(s64) = G_LOAD [[LIST]](p0) :: (load 8, align 16) - ; CHECK: [[SLOTSIZE:%[0-9]+]](s64) = G_CONSTANT i64 8 - ; CHECK: [[NEXT:%[0-9]+]](p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64) - ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8) - %3:_(s64) = G_VAARG %0(p0), 16 -... diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir deleted file mode 100644 index 460b3d16f1c0..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir +++ /dev/null @@ -1,37 +0,0 @@ -# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test_scalar_xor_small() { - entry: - ret void - } -... - ---- -name: test_scalar_xor_small -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } -body: | - bb.0.entry: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_scalar_xor_small - ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) - ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) - ; CHECK: [[RES32:%.*]](s32) = G_XOR [[OP0]], [[OP1]] - ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s8) = G_TRUNC %0 - %3(s8) = G_TRUNC %1 - %4(s8) = G_XOR %2, %3 - %5(s64) = G_ANYEXT %2 - %x0 = COPY %5 -... diff --git a/test/CodeGen/AArch64/GlobalISel/lit.local.cfg b/test/CodeGen/AArch64/GlobalISel/lit.local.cfg deleted file mode 100644 index e99d1bb8446c..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not 'global-isel' in config.root.available_features: - config.unsupported = True diff --git a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir b/test/CodeGen/AArch64/GlobalISel/no-regclass.mir deleted file mode 100644 index 6832ce0ee8bd..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/no-regclass.mir +++ /dev/null @@ -1,30 +0,0 @@ -# RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -start-before=legalizer -stop-after=instruction-select %s -o - | FileCheck %s - -# We run the legalizer to combine the trivial EXTRACT_SEQ pair, leaving %1 and -# %2 orphaned after instruction-selection (no instructions define or use -# them). This shouldn't be a problem. - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @unused_reg() { ret void } - ---- -# CHECK-LABEL: name: unused_reg -name: unused_reg -legalized: true -regBankSelected: true -tracksRegLiveness: true - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %w0 = COPY %0 - -body: | - bb.0: - liveins: %w0 - %0:gpr(s32) = COPY %w0 - %1:gpr(s32) = G_SEQUENCE %0(s32), 0 - %2:gpr(s32) = G_EXTRACT %1(s32), 0 - %w0 = COPY %2(s32) -... diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir deleted file mode 100644 index 73d4d2054729..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/regbankselect-dbg-value.mir +++ /dev/null @@ -1,45 +0,0 @@ -# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @test_dbg_value() !dbg !5 { - ; Keep the dbg metadata live by referencing it in the IR. - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10 - ret void - } - - declare void @llvm.dbg.value(metadata, i64, metadata, metadata) - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!3, !4} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) - !1 = !DIFile(filename: "test.ll", directory: "/tmp") - !2 = !{} - !3 = !{i32 2, !"Dwarf Version", i32 4} - !4 = !{i32 2, !"Debug Info Version", i32 3} - !5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) - !6 = !DISubroutineType(types: !2) - !7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8) - !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) - !9 = !DIExpression() - !10 = !DILocation(line: 1, column: 1, scope: !5) -... - ---- -# CHECK-LABEL: name: test_dbg_value -name: test_dbg_value -legalized: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -body: | - bb.0: - liveins: %w0 - %0:_(s32) = COPY %w0 - ; CHECK: DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10 - DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10 - - ; CHECK: DBG_VALUE _, 0, !7, !9, debug-location !10 - DBG_VALUE _, 0, !7, !9, debug-location !10 -... diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir deleted file mode 100644 index 14ee40c941bf..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ /dev/null @@ -1,870 +0,0 @@ -# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s - -# Check the default mappings for various instructions. - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @test_add_s32() { ret void } - define void @test_add_v4s32() { ret void } - define void @test_sub_s32() { ret void } - define void @test_sub_v4s32() { ret void } - define void @test_mul_s32() { ret void } - define void @test_mul_v4s32() { ret void } - - define void @test_and_s32() { ret void } - define void @test_and_v4s32() { ret void } - define void @test_or_s32() { ret void } - define void @test_or_v4s32() { ret void } - define void @test_xor_s32() { ret void } - define void @test_xor_v4s32() { ret void } - - define void @test_shl_s32() { ret void } - define void @test_shl_v4s32() { ret void } - define void @test_lshr_s32() { ret void } - define void @test_ashr_s32() { ret void } - - define void @test_sdiv_s32() { ret void } - define void @test_udiv_s32() { ret void } - - define void @test_anyext_s64_s32() { ret void } - define void @test_sext_s64_s32() { ret void } - define void @test_zext_s64_s32() { ret void } - define void @test_trunc_s32_s64() { ret void } - - define void @test_constant_s32() { ret void } - define void @test_constant_p0() { ret void } - - define void @test_icmp_s32() { ret void } - define void @test_icmp_p0() { ret void } - - define void @test_frame_index_p0() { - %ptr0 = alloca i64 - ret void - } - - define void @test_ptrtoint_s64_p0() { ret void } - define void @test_inttoptr_p0_s64() { ret void } - - define void @test_load_s32_p0() { ret void } - define void @test_store_s32_p0() { ret void } - - define void @test_fadd_s32() { ret void } - define void @test_fsub_s32() { ret void } - define void @test_fmul_s32() { ret void } - define void @test_fdiv_s32() { ret void } - - define void @test_fpext_s64_s32() { ret void } - define void @test_fptrunc_s32_s64() { ret void } - - define void @test_fconstant_s32() { ret void } - - define void @test_fcmp_s32() { ret void } - - define void @test_sitofp_s64_s32() { ret void } - define void @test_uitofp_s32_s64() { ret void } - - define void @test_fptosi_s64_s32() { ret void } - define void @test_fptoui_s32_s64() { ret void } -... - ---- -# CHECK-LABEL: name: test_add_s32 -name: test_add_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_ADD %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_ADD %0, %0 -... - ---- -# CHECK-LABEL: name: test_add_v4s32 -name: test_add_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_ADD %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_ADD %0, %0 -... - ---- -# CHECK-LABEL: name: test_sub_s32 -name: test_sub_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SUB %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_SUB %0, %0 -... - ---- -# CHECK-LABEL: name: test_sub_v4s32 -name: test_sub_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_SUB %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_SUB %0, %0 -... - ---- -# CHECK-LABEL: name: test_mul_s32 -name: test_mul_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_MUL %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_MUL %0, %0 -... - ---- -# CHECK-LABEL: name: test_mul_v4s32 -name: test_mul_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_MUL %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_MUL %0, %0 -... - ---- -# CHECK-LABEL: name: test_and_s32 -name: test_and_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_AND %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_AND %0, %0 -... - ---- -# CHECK-LABEL: name: test_and_v4s32 -name: test_and_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_AND %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_AND %0, %0 -... - ---- -# CHECK-LABEL: name: test_or_s32 -name: test_or_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_OR %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_OR %0, %0 -... - ---- -# CHECK-LABEL: name: test_or_v4s32 -name: test_or_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_OR %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_OR %0, %0 -... - ---- -# CHECK-LABEL: name: test_xor_s32 -name: test_xor_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_XOR %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_XOR %0, %0 -... - ---- -# CHECK-LABEL: name: test_xor_v4s32 -name: test_xor_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_XOR %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_XOR %0, %0 -... - ---- -# CHECK-LABEL: name: test_shl_s32 -name: test_shl_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SHL %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_SHL %0, %0 -... - ---- -# CHECK-LABEL: name: test_shl_v4s32 -name: test_shl_v4s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_SHL %0, %0 - %0(<4 x s32>) = COPY %q0 - %1(<4 x s32>) = G_SHL %0, %0 -... - ---- -# CHECK-LABEL: name: test_lshr_s32 -name: test_lshr_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_LSHR %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_LSHR %0, %0 -... - ---- -# CHECK-LABEL: name: test_ashr_s32 -name: test_ashr_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_ASHR %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_ASHR %0, %0 -... - ---- -# CHECK-LABEL: name: test_sdiv_s32 -name: test_sdiv_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SDIV %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_SDIV %0, %0 -... - ---- -# CHECK-LABEL: name: test_udiv_s32 -name: test_udiv_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_UDIV %0, %0 - %0(s32) = COPY %w0 - %1(s32) = G_UDIV %0, %0 -... - ---- -# CHECK-LABEL: name: test_anyext_s64_s32 -name: test_anyext_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_ANYEXT %0 - %0(s32) = COPY %w0 - %1(s64) = G_ANYEXT %0 -... - ---- -# CHECK-LABEL: name: test_sext_s64_s32 -name: test_sext_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_SEXT %0 - %0(s32) = COPY %w0 - %1(s64) = G_SEXT %0 -... - ---- -# CHECK-LABEL: name: test_zext_s64_s32 -name: test_zext_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_ZEXT %0 - %0(s32) = COPY %w0 - %1(s64) = G_ZEXT %0 -... - ---- -# CHECK-LABEL: name: test_trunc_s32_s64 -name: test_trunc_s32_s64 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(s32) = G_TRUNC %0 - %0(s64) = COPY %x0 - %1(s32) = G_TRUNC %0 -... - ---- -# CHECK-LABEL: name: test_constant_s32 -name: test_constant_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -registers: - - { id: 0, class: _ } -body: | - bb.0: - ; CHECK: %0(s32) = G_CONSTANT 123 - %0(s32) = G_CONSTANT 123 -... - ---- -# CHECK-LABEL: name: test_constant_p0 -name: test_constant_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -registers: - - { id: 0, class: _ } -body: | - bb.0: - ; CHECK: %0(p0) = G_CONSTANT 0 - %0(p0) = G_CONSTANT 0 -... - ---- -# CHECK-LABEL: name: test_icmp_s32 -name: test_icmp_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s1) = G_ICMP intpred(ne), %0(s32), %0 - %0(s32) = COPY %w0 - %1(s1) = G_ICMP intpred(ne), %0, %0 -... - ---- -# CHECK-LABEL: name: test_icmp_p0 -name: test_icmp_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s1) = G_ICMP intpred(ne), %0(p0), %0 - %0(p0) = COPY %x0 - %1(s1) = G_ICMP intpred(ne), %0, %0 -... - ---- -# CHECK-LABEL: name: test_frame_index_p0 -name: test_frame_index_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -registers: - - { id: 0, class: _ } -stack: - - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } -body: | - bb.0: - ; CHECK: %0(p0) = G_FRAME_INDEX %stack.0.ptr0 - %0(p0) = G_FRAME_INDEX %stack.0.ptr0 -... - ---- -# CHECK-LABEL: name: test_ptrtoint_s64_p0 -name: test_ptrtoint_s64_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s64) = G_PTRTOINT %0 - %0(p0) = COPY %x0 - %1(s64) = G_PTRTOINT %0 -... - ---- -# CHECK-LABEL: name: test_inttoptr_p0_s64 -name: test_inttoptr_p0_s64 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(p0) = G_INTTOPTR %0 - %0(s64) = COPY %x0 - %1(p0) = G_INTTOPTR %0 -... - ---- -# CHECK-LABEL: name: test_load_s32_p0 -name: test_load_s32_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s32) = G_LOAD %0 - %0(p0) = COPY %x0 - %1(s32) = G_LOAD %0 :: (load 4) -... - ---- -# CHECK-LABEL: name: test_store_s32_p0 -name: test_store_s32_p0 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0, %w1 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s32) = COPY %w1 - ; CHECK: G_STORE %1(s32), %0(p0) - %0(p0) = COPY %x0 - %1(s32) = COPY %w1 - G_STORE %1, %0 :: (store 4) -... - ---- -# CHECK-LABEL: name: test_fadd_s32 -name: test_fadd_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FADD %0, %0 - %0(s32) = COPY %s0 - %1(s32) = G_FADD %0, %0 -... - ---- -# CHECK-LABEL: name: test_fsub_s32 -name: test_fsub_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FSUB %0, %0 - %0(s32) = COPY %s0 - %1(s32) = G_FSUB %0, %0 -... - ---- -# CHECK-LABEL: name: test_fmul_s32 -name: test_fmul_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FMUL %0, %0 - %0(s32) = COPY %s0 - %1(s32) = G_FMUL %0, %0 -... - ---- -# CHECK-LABEL: name: test_fdiv_s32 -name: test_fdiv_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FDIV %0, %0 - %0(s32) = COPY %s0 - %1(s32) = G_FDIV %0, %0 -... - ---- -# CHECK-LABEL: name: test_fpext_s64_s32 -name: test_fpext_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s64) = G_FPEXT %0 - %0(s32) = COPY %s0 - %1(s64) = G_FPEXT %0 -... - ---- -# CHECK-LABEL: name: test_fptrunc_s32_s64 -name: test_fptrunc_s32_s64 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %d0 - ; CHECK: %0(s64) = COPY %d0 - ; CHECK: %1(s32) = G_FPTRUNC %0 - %0(s64) = COPY %d0 - %1(s32) = G_FPTRUNC %0 -... - ---- -# CHECK-LABEL: name: test_fconstant_s32 -name: test_fconstant_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -registers: - - { id: 0, class: _ } -body: | - bb.0: - ; CHECK: %0(s32) = G_FCONSTANT float 1.0 - %0(s32) = G_FCONSTANT float 1.0 -... - ---- -# CHECK-LABEL: name: test_fcmp_s32 -name: test_fcmp_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s1) = G_FCMP floatpred(olt), %0(s32), %0 - %0(s32) = COPY %s0 - %1(s1) = G_FCMP floatpred(olt), %0, %0 -... - ---- -# CHECK-LABEL: name: test_sitofp_s64_s32 -name: test_sitofp_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_SITOFP %0 - %0(s32) = COPY %w0 - %1(s64) = G_SITOFP %0 -... - ---- -# CHECK-LABEL: name: test_uitofp_s32_s64 -name: test_uitofp_s32_s64 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr } -# CHECK: - { id: 1, class: fpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(s32) = G_UITOFP %0 - %0(s64) = COPY %x0 - %1(s32) = G_UITOFP %0 -... - ---- -# CHECK-LABEL: name: test_fptosi_s64_s32 -name: test_fptosi_s64_s32 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s64) = G_FPTOSI %0 - %0(s32) = COPY %s0 - %1(s64) = G_FPTOSI %0 -... - ---- -# CHECK-LABEL: name: test_fptoui_s32_s64 -name: test_fptoui_s32_s64 -legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr } -# CHECK: - { id: 1, class: gpr } -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } -body: | - bb.0: - liveins: %d0 - ; CHECK: %0(s64) = COPY %d0 - ; CHECK: %1(s32) = G_FPTOUI %0 - %0(s64) = COPY %d0 - %1(s32) = G_FPTOUI %0 -... diff --git a/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir b/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir deleted file mode 100644 index 15ccf1f5459c..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/regbankselect-reg_sequence.mir +++ /dev/null @@ -1,25 +0,0 @@ -# RUN: llc %s -mtriple aarch64-- -o - -run-pass regbankselect | FileCheck %s ---- | - define void @foo() { ret void } -... ---- -# CHECK-LABEL: foo -# Check that we produce a valid mapping for REG_SEQUENCE. -# This used to fail the RegisterBankInfo verify because -# we were using the exclusively the type of the definition -# whereas since REG_SEQUENCE are kind of target opcode -# their definition may not have a type. -# -# CHECK: id: 0, class: dd -name: foo -legalized: true -tracksRegLiveness: true -registers: - - { id: 0, class: dd } -body: | - bb.0: - liveins: %d0, %d1 - - %0 = REG_SEQUENCE %d0, %subreg.dsub0, %d1, %subreg.dsub1 - -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/test/CodeGen/AArch64/GlobalISel/select-binop.mir deleted file mode 100644 index 8ae2e1b2eb7d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-binop.mir +++ /dev/null @@ -1,1042 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @add_s32_gpr() { ret void } - define void @add_s64_gpr() { ret void } - - define void @add_imm_s32_gpr() { ret void } - define void @add_imm_s64_gpr() { ret void } - - define void @add_imm_s32_gpr_bb() { ret void } - - define void @sub_s32_gpr() { ret void } - define void @sub_s64_gpr() { ret void } - - define void @or_s32_gpr() { ret void } - define void @or_s64_gpr() { ret void } - define void @or_v2s32_fpr() { ret void } - - define void @and_s32_gpr() { ret void } - define void @and_s64_gpr() { ret void } - - define void @shl_s32_gpr() { ret void } - define void @shl_s64_gpr() { ret void } - - define void @lshr_s32_gpr() { ret void } - define void @lshr_s64_gpr() { ret void } - - define void @ashr_s32_gpr() { ret void } - define void @ashr_s64_gpr() { ret void } - - define void @mul_s32_gpr() { ret void } - define void @mul_s64_gpr() { ret void } - - define void @mulh_s64_gpr() { ret void } - - define void @sdiv_s32_gpr() { ret void } - define void @sdiv_s64_gpr() { ret void } - - define void @udiv_s32_gpr() { ret void } - define void @udiv_s64_gpr() { ret void } - - define void @fadd_s32_fpr() { ret void } - define void @fadd_s64_fpr() { ret void } - - define void @fsub_s32_fpr() { ret void } - define void @fsub_s64_fpr() { ret void } - - define void @fmul_s32_fpr() { ret void } - define void @fmul_s64_fpr() { ret void } - - define void @fdiv_s32_fpr() { ret void } - define void @fdiv_s64_fpr() { ret void } - -... - ---- -# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. -# Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: add_s32_gpr -name: add_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ADDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_ADD %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s32_gpr, for 64-bit operations. -# CHECK-LABEL: name: add_s64_gpr -name: add_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ADDXrr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_ADD %0, %1 - %x0 = COPY %2(s64) -... - ---- -# CHECK-LABEL: name: add_imm_s32_gpr -name: add_imm_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr32sp } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ADDWri %0, 1, 0 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = G_CONSTANT i32 1 - %2(s32) = G_ADD %0, %1 - %w0 = COPY %2(s32) -... - ---- -# CHECK-LABEL: name: add_imm_s64_gpr -name: add_imm_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr64sp } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %2 = ADDXri %0, 1, 0 -body: | - bb.0: - liveins: %x0, %w1 - - %0(s64) = COPY %x0 - %1(s64) = G_CONSTANT i32 1 - %2(s64) = G_ADD %0, %1 - %x0 = COPY %2(s64) -... - ---- -# CHECK-LABEL: name: add_imm_s32_gpr_bb -name: add_imm_s32_gpr_bb -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr32sp } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: bb.1: -# CHECK: %2 = ADDWri %0, 1, 0 -body: | - bb.0: - liveins: %w0, %w1 - successors: %bb.1 - - %0(s32) = COPY %w0 - %1(s32) = G_CONSTANT i32 1 - G_BR %bb.1 - - bb.1: - %2(s32) = G_ADD %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s32_gpr, for G_SUB operations. -# CHECK-LABEL: name: sub_s32_gpr -name: sub_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SUBSWrr %0, %1, implicit-def %nzcv -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_SUB %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_SUB operations. -# CHECK-LABEL: name: sub_s64_gpr -name: sub_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SUBSXrr %0, %1, implicit-def %nzcv -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_SUB %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as add_s32_gpr, for G_OR operations. -# CHECK-LABEL: name: or_s32_gpr -name: or_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ORRWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_OR %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_OR operations. -# CHECK-LABEL: name: or_s64_gpr -name: or_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ORRXrr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_OR %0, %1 - %x0 = COPY %2(s64) -... - ---- -# 64-bit G_OR on vector registers. -# CHECK-LABEL: name: or_v2s32_fpr -name: or_v2s32_fpr -legalized: true -regBankSelected: true -# -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# The actual OR does not matter as long as it is operating -# on 64-bit width vector. -# CHECK: %2 = ORRv8i8 %0, %1 -body: | - bb.0: - liveins: %d0, %d1 - - %0(<2 x s32>) = COPY %d0 - %1(<2 x s32>) = COPY %d1 - %2(<2 x s32>) = G_OR %0, %1 - %d0 = COPY %2(<2 x s32>) -... - ---- -# Same as add_s32_gpr, for G_AND operations. -# CHECK-LABEL: name: and_s32_gpr -name: and_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ANDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_AND %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_AND operations. -# CHECK-LABEL: name: and_s64_gpr -name: and_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ANDXrr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_AND %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as add_s32_gpr, for G_SHL operations. -# CHECK-LABEL: name: shl_s32_gpr -name: shl_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSLVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_SHL %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_SHL operations. -# CHECK-LABEL: name: shl_s64_gpr -name: shl_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = LSLVXr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_SHL %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as add_s32_gpr, for G_LSHR operations. -# CHECK-LABEL: name: lshr_s32_gpr -name: lshr_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSRVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_LSHR %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_LSHR operations. -# CHECK-LABEL: name: lshr_s64_gpr -name: lshr_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = LSRVXr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_LSHR %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as add_s32_gpr, for G_ASHR operations. -# CHECK-LABEL: name: ashr_s32_gpr -name: ashr_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ASRVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_ASHR %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_ASHR operations. -# CHECK-LABEL: name: ashr_s64_gpr -name: ashr_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ASRVXr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_ASHR %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Check that we select s32 GPR G_MUL. This is trickier than other binops because -# there is only MADDWrrr, and we have to use the WZR physreg. -# CHECK-LABEL: name: mul_s32_gpr -name: mul_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = MADDWrrr %0, %1, %wzr -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_MUL %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as mul_s32_gpr for the s64 type. -# CHECK-LABEL: name: mul_s64_gpr -name: mul_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = MADDXrrr %0, %1, %xzr -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_MUL %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as mul_s32_gpr for the s64 type. -# CHECK-LABEL: name: mulh_s64_gpr -name: mulh_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -# CHECK-NEXT: - { id: 3, class: gpr64 } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SMULHrr %0, %1 -# CHECK: %3 = UMULHrr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0:gpr(s64) = COPY %x0 - %1:gpr(s64) = COPY %x1 - %2:gpr(s64) = G_SMULH %0, %1 - %3:gpr(s64) = G_UMULH %0, %1 - %x0 = COPY %2(s64) - %x0 = COPY %3(s64) -... - ---- -# Same as add_s32_gpr, for G_SDIV operations. -# CHECK-LABEL: name: sdiv_s32_gpr -name: sdiv_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SDIVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_SDIV %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_SDIV operations. -# CHECK-LABEL: name: sdiv_s64_gpr -name: sdiv_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SDIVXr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_SDIV %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Same as add_s32_gpr, for G_UDIV operations. -# CHECK-LABEL: name: udiv_s32_gpr -name: udiv_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = UDIVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_UDIV %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as add_s64_gpr, for G_UDIV operations. -# CHECK-LABEL: name: udiv_s64_gpr -name: udiv_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = UDIVXr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_UDIV %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Check that we select a s32 FPR G_FADD into FADDSrr. -# CHECK-LABEL: name: fadd_s32_fpr -name: fadd_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -# CHECK-NEXT: - { id: 2, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FADDSrr %0, %1 -body: | - bb.0: - liveins: %s0, %s1 - - %0(s32) = COPY %s0 - %1(s32) = COPY %s1 - %2(s32) = G_FADD %0, %1 - %s0 = COPY %2(s32) -... - ---- -# CHECK-LABEL: name: fadd_s64_fpr -name: fadd_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FADDDrr %0, %1 -body: | - bb.0: - liveins: %d0, %d1 - - %0(s64) = COPY %d0 - %1(s64) = COPY %d1 - %2(s64) = G_FADD %0, %1 - %d0 = COPY %2(s64) -... - ---- -# CHECK-LABEL: name: fsub_s32_fpr -name: fsub_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -# CHECK-NEXT: - { id: 2, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FSUBSrr %0, %1 -body: | - bb.0: - liveins: %s0, %s1 - - %0(s32) = COPY %s0 - %1(s32) = COPY %s1 - %2(s32) = G_FSUB %0, %1 - %s0 = COPY %2(s32) -... - ---- -# CHECK-LABEL: name: fsub_s64_fpr -name: fsub_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FSUBDrr %0, %1 -body: | - bb.0: - liveins: %d0, %d1 - - %0(s64) = COPY %d0 - %1(s64) = COPY %d1 - %2(s64) = G_FSUB %0, %1 - %d0 = COPY %2(s64) -... - ---- -# CHECK-LABEL: name: fmul_s32_fpr -name: fmul_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -# CHECK-NEXT: - { id: 2, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FMULSrr %0, %1 -body: | - bb.0: - liveins: %s0, %s1 - - %0(s32) = COPY %s0 - %1(s32) = COPY %s1 - %2(s32) = G_FMUL %0, %1 - %s0 = COPY %2(s32) -... - ---- -# CHECK-LABEL: name: fmul_s64_fpr -name: fmul_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FMULDrr %0, %1 -body: | - bb.0: - liveins: %d0, %d1 - - %0(s64) = COPY %d0 - %1(s64) = COPY %d1 - %2(s64) = G_FMUL %0, %1 - %d0 = COPY %2(s64) -... - ---- -# CHECK-LABEL: name: fdiv_s32_fpr -name: fdiv_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -# CHECK-NEXT: - { id: 2, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FDIVSrr %0, %1 -body: | - bb.0: - liveins: %s0, %s1 - - %0(s32) = COPY %s0 - %1(s32) = COPY %s1 - %2(s32) = G_FDIV %0, %1 - %s0 = COPY %2(s32) -... - ---- -# CHECK-LABEL: name: fdiv_s64_fpr -name: fdiv_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FDIVDrr %0, %1 -body: | - bb.0: - liveins: %d0, %d1 - - %0(s64) = COPY %d0 - %1(s64) = COPY %d1 - %2(s64) = G_FDIV %0, %1 - %d0 = COPY %2(s64) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir deleted file mode 100644 index 5ca63dbc214d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ /dev/null @@ -1,212 +0,0 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @bitcast_s32_gpr() { ret void } - define void @bitcast_s32_fpr() { ret void } - define void @bitcast_s32_gpr_fpr() { ret void } - define void @bitcast_s32_fpr_gpr() { ret void } - define void @bitcast_s64_gpr() { ret void } - define void @bitcast_s64_fpr() { ret void } - define void @bitcast_s64_gpr_fpr() { ret void } - define void @bitcast_s64_fpr_gpr() { ret void } -... - ---- -# CHECK-LABEL: name: bitcast_s32_gpr -name: bitcast_s32_gpr -legalized: true -regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all } -# CHECK-NEXT: - { id: 1, class: gpr32all } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_BITCAST %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: bitcast_s32_fpr -name: bitcast_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s32) = G_BITCAST %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: bitcast_s32_gpr_fpr -name: bitcast_s32_gpr_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_BITCAST %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: bitcast_s32_fpr_gpr -name: bitcast_s32_fpr_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32all } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s32) = G_BITCAST %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: bitcast_s64_gpr -name: bitcast_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all } -# CHECK-NEXT: - { id: 1, class: gpr64all } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_BITCAST %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: bitcast_s64_fpr -name: bitcast_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s64) = G_BITCAST %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: bitcast_s64_gpr_fpr -name: bitcast_s64_gpr_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_BITCAST %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: bitcast_s64_fpr_gpr -name: bitcast_s64_fpr_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64all } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s64) = G_BITCAST %0 - %x0 = COPY %1(s64) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-br.mir b/test/CodeGen/AArch64/GlobalISel/select-br.mir deleted file mode 100644 index f46f190260f6..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-br.mir +++ /dev/null @@ -1,71 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @unconditional_br() { ret void } - define void @conditional_br() { ret void } - define void @indirect_br() { ret void } -... - ---- -# CHECK-LABEL: name: unconditional_br -name: unconditional_br -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: bb.0: -# CHECK: successors: %bb.0 -# CHECK: B %bb.0 -body: | - bb.0: - successors: %bb.0 - - G_BR %bb.0 -... - ---- -# CHECK-LABEL: name: conditional_br -name: conditional_br -legalized: true -regBankSelected: true - -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# CHECK: bb.0: -# CHECK: TBNZW %0, 0, %bb.1 -# CHECK: B %bb.0 -body: | - bb.0: - successors: %bb.0, %bb.1 - %0(s1) = COPY %w0 - G_BRCOND %0(s1), %bb.1 - G_BR %bb.0 - - bb.1: -... - ---- -# CHECK-LABEL: name: indirect_br -name: indirect_br -legalized: true -regBankSelected: true - -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# CHECK: bb.0: -# CHECK: %0 = COPY %x0 -# CHECK: BR %0 -body: | - bb.0: - successors: %bb.0, %bb.1 - %0(p0) = COPY %x0 - G_BRINDIRECT %0(p0) - - bb.1: -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir b/test/CodeGen/AArch64/GlobalISel/select-cbz.mir deleted file mode 100644 index 2decb994b967..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-cbz.mir +++ /dev/null @@ -1,108 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - define void @cbz_s32() { ret void } - define void @cbz_s64() { ret void } - define void @cbnz_s32() { ret void } - define void @cbnz_s64() { ret void } -... - ---- -# CHECK-LABEL: name: cbz_s32 -name: cbz_s32 -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: bb.0: -# CHECK: %0 = COPY %w0 -# CHECK: CBZW %0, %bb.1 -# CHECK: B %bb.0 -body: | - bb.0: - liveins: %w0 - successors: %bb.0, %bb.1 - - %0:gpr(s32) = COPY %w0 - %1:gpr(s32) = G_CONSTANT i32 0 - %2:gpr(s1) = G_ICMP intpred(eq), %0, %1 - G_BRCOND %2(s1), %bb.1 - G_BR %bb.0 - - bb.1: -... - ---- -# CHECK-LABEL: name: cbz_s64 -name: cbz_s64 -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: bb.0: -# CHECK: %0 = COPY %x0 -# CHECK: CBZX %0, %bb.1 -# CHECK: B %bb.0 -body: | - bb.0: - liveins: %x0 - successors: %bb.0, %bb.1 - - %0:gpr(s64) = COPY %x0 - %1:gpr(s64) = G_CONSTANT i64 0 - %2:gpr(s1) = G_ICMP intpred(eq), %0, %1 - G_BRCOND %2(s1), %bb.1 - G_BR %bb.0 - - bb.1: -... - ---- -# CHECK-LABEL: name: cbnz_s32 -name: cbnz_s32 -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: bb.0: -# CHECK: %0 = COPY %w0 -# CHECK: CBNZW %0, %bb.1 -# CHECK: B %bb.0 -body: | - bb.0: - liveins: %w0 - successors: %bb.0, %bb.1 - - %0:gpr(s32) = COPY %w0 - %1:gpr(s32) = G_CONSTANT i32 0 - %2:gpr(s1) = G_ICMP intpred(ne), %0, %1 - G_BRCOND %2(s1), %bb.1 - G_BR %bb.0 - - bb.1: -... - ---- -# CHECK-LABEL: name: cbnz_s64 -name: cbnz_s64 -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: bb.0: -# CHECK: %0 = COPY %x0 -# CHECK: CBNZX %0, %bb.1 -# CHECK: B %bb.0 -body: | - bb.0: - liveins: %x0 - successors: %bb.0, %bb.1 - - %0:gpr(s64) = COPY %x0 - %1:gpr(s64) = G_CONSTANT i64 0 - %2:gpr(s1) = G_ICMP intpred(ne), %0, %1 - G_BRCOND %2(s1), %bb.1 - G_BR %bb.0 - - bb.1: -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-constant.mir b/test/CodeGen/AArch64/GlobalISel/select-constant.mir deleted file mode 100644 index 1a5bac9fb7d6..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-constant.mir +++ /dev/null @@ -1,77 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define i32 @const_s32() { ret i32 42 } - define i64 @const_s64() { ret i64 1234567890123 } - - define i32 @fconst_s32() { ret i32 42 } - define i64 @fconst_s64() { ret i64 1234567890123 } -... - ---- -# CHECK-LABEL: name: const_s32 -name: const_s32 -legalized: true -regBankSelected: true -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# CHECK: %0 = MOVi32imm 42 -body: | - bb.0: - %0(s32) = G_CONSTANT i32 42 - %w0 = COPY %0(s32) -... - ---- -# CHECK-LABEL: name: const_s64 -name: const_s64 -legalized: true -regBankSelected: true -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# CHECK: %0 = MOVi64imm 1234567890123 -body: | - bb.0: - %0(s64) = G_CONSTANT i64 1234567890123 - %x0 = COPY %0(s64) -... - ---- -# CHECK-LABEL: name: fconst_s32 -name: fconst_s32 -legalized: true -regBankSelected: true -registers: - - { id: 0, class: fpr } - -# CHECK: body: -# CHECK: [[TMP:%[0-9]+]] = MOVi32imm 1080033280 -# CHECK: %0 = COPY [[TMP]] -body: | - bb.0: - %0(s32) = G_FCONSTANT float 3.5 - %s0 = COPY %0(s32) -... - ---- -# CHECK-LABEL: name: fconst_s64 -name: fconst_s64 -legalized: true -regBankSelected: true -registers: - - { id: 0, class: fpr } - -# CHECK: body: -# CHECK: [[TMP:%[0-9]+]] = MOVi64imm 4607182418800017408 -# CHECK: %0 = COPY [[TMP]] -body: | - bb.0: - %0(s64) = G_FCONSTANT double 1.0 - %d0 = COPY %0(s64) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir b/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir deleted file mode 100644 index 2f36ec8d2aaa..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir +++ /dev/null @@ -1,69 +0,0 @@ -# RUN: llc -O0 -mtriple arm64-- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @test_dbg_value(i32 %a) !dbg !5 { - %tmp0 = add i32 %a, %a - call void @llvm.dbg.value(metadata i32 %tmp0, i64 0, metadata !7, metadata !9), !dbg !10 - ret void - } - - define void @test_dbg_value_dead(i32 %a) !dbg !5 { - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !7, metadata !9), !dbg !10 - ret void - } - - declare void @llvm.dbg.value(metadata, i64, metadata, metadata) - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!3, !4} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "llvm", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) - !1 = !DIFile(filename: "test.ll", directory: "/tmp") - !2 = !{} - !3 = !{i32 2, !"Dwarf Version", i32 4} - !4 = !{i32 2, !"Debug Info Version", i32 3} - !5 = distinct !DISubprogram(name: "test_dbg_value", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) - !6 = !DISubroutineType(types: !2) - !7 = !DILocalVariable(name: "in", arg: 1, scope: !5, file: !1, line: 1, type: !8) - !8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) - !9 = !DIExpression() - !10 = !DILocation(line: 1, column: 1, scope: !5) -... - ---- -# CHECK-LABEL: name: test_dbg_value -name: test_dbg_value -legalized: true -regBankSelected: true -body: | - bb.0: - liveins: %w0 - %0:gpr(s32) = COPY %w0 - %1:gpr(s32) = G_ADD %0, %0 - %w0 = COPY %1(s32) - - ; CHECK: %0 = COPY %w0 - ; CHECK-NEXT: %1 = ADDWrr %0, %0 - ; CHECK-NEXT: %w0 = COPY %1 - ; CHECK-NEXT: DBG_VALUE debug-use %1, debug-use _, !7, !9, debug-location !10 - - DBG_VALUE debug-use %1(s32), debug-use _, !7, !9, debug-location !10 -... - ---- -# CHECK-LABEL: name: test_dbg_value_dead -name: test_dbg_value_dead -legalized: true -regBankSelected: true -body: | - bb.0: - liveins: %w0 - %0:gpr(s32) = COPY %w0 - - ; CHECK-NOT: COPY - ; CHECK: DBG_VALUE debug-use _, debug-use _, !7, !9, debug-location !10 - - DBG_VALUE debug-use %0(s32), debug-use _, !7, !9, debug-location !10 -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir deleted file mode 100644 index fbb11a1c7a4c..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir +++ /dev/null @@ -1,478 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @fptrunc() { ret void } - define void @fpext() { ret void } - - define void @sitofp_s32_s32_fpr() { ret void } - define void @sitofp_s32_s64_fpr() { ret void } - define void @sitofp_s64_s32_fpr() { ret void } - define void @sitofp_s64_s64_fpr() { ret void } - - define void @uitofp_s32_s32_fpr() { ret void } - define void @uitofp_s32_s64_fpr() { ret void } - define void @uitofp_s64_s32_fpr() { ret void } - define void @uitofp_s64_s64_fpr() { ret void } - - define void @fptosi_s32_s32_gpr() { ret void } - define void @fptosi_s32_s64_gpr() { ret void } - define void @fptosi_s64_s32_gpr() { ret void } - define void @fptosi_s64_s64_gpr() { ret void } - - define void @fptoui_s32_s32_gpr() { ret void } - define void @fptoui_s32_s64_gpr() { ret void } - define void @fptoui_s64_s32_gpr() { ret void } - define void @fptoui_s64_s64_gpr() { ret void } -... - ---- -# CHECK-LABEL: name: fptrunc -name: fptrunc -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK: - { id: 0, class: fpr64 } -# CHECK: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTSDr %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s32) = G_FPTRUNC %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: fpext -name: fpext -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK: - { id: 0, class: fpr32 } -# CHECK: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTDSr %0 -body: | - bb.0: - liveins: %d0 - - %0(s32) = COPY %s0 - %1(s64) = G_FPEXT %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: sitofp_s32_s32_fpr -name: sitofp_s32_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SCVTFUWSri %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_SITOFP %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: sitofp_s32_s64_fpr -name: sitofp_s32_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = SCVTFUXSri %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s32) = G_SITOFP %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: sitofp_s64_s32_fpr -name: sitofp_s64_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SCVTFUWDri %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s64) = G_SITOFP %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: sitofp_s64_s64_fpr -name: sitofp_s64_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = SCVTFUXDri %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_SITOFP %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: uitofp_s32_s32_fpr -name: uitofp_s32_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UCVTFUWSri %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_UITOFP %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: uitofp_s32_s64_fpr -name: uitofp_s32_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = UCVTFUXSri %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s32) = G_UITOFP %0 - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: uitofp_s64_s32_fpr -name: uitofp_s64_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UCVTFUWDri %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s64) = G_UITOFP %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: uitofp_s64_s64_fpr -name: uitofp_s64_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = UCVTFUXDri %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_UITOFP %0 - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: fptosi_s32_s32_gpr -name: fptosi_s32_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZSUWSr %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s32) = G_FPTOSI %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: fptosi_s32_s64_gpr -name: fptosi_s32_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZSUWDr %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s32) = G_FPTOSI %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: fptosi_s64_s32_gpr -name: fptosi_s64_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZSUXSr %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s64) = G_FPTOSI %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: fptosi_s64_s64_gpr -name: fptosi_s64_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZSUXDr %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s64) = G_FPTOSI %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: fptoui_s32_s32_gpr -name: fptoui_s32_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZUUWSr %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s32) = G_FPTOUI %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: fptoui_s32_s64_gpr -name: fptoui_s32_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZUUWDr %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s32) = G_FPTOUI %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: fptoui_s64_s32_gpr -name: fptoui_s64_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZUUXSr %0 -body: | - bb.0: - liveins: %s0 - - %0(s32) = COPY %s0 - %1(s64) = G_FPTOUI %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: fptoui_s64_s64_gpr -name: fptoui_s64_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZUUXDr %0 -body: | - bb.0: - liveins: %d0 - - %0(s64) = COPY %d0 - %1(s64) = G_FPTOUI %0 - %x0 = COPY %1(s64) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir deleted file mode 100644 index 2ba8b7366252..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ /dev/null @@ -1,274 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @anyext_s64_from_s32() { ret void } - define void @anyext_s32_from_s8() { ret void } - - define void @zext_s64_from_s32() { ret void } - define void @zext_s32_from_s16() { ret void } - define void @zext_s32_from_s8() { ret void } - define void @zext_s16_from_s8() { ret void } - - define void @sext_s64_from_s32() { ret void } - define void @sext_s32_from_s16() { ret void } - define void @sext_s32_from_s8() { ret void } - define void @sext_s16_from_s8() { ret void } -... - ---- -# CHECK-LABEL: name: anyext_s64_from_s32 -name: anyext_s64_from_s32 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all } -# CHECK-NEXT: - { id: 1, class: gpr64all } -# CHECK-NEXT: - { id: 2, class: gpr64all } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = COPY %2 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s64) = G_ANYEXT %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: anyext_s32_from_s8 -name: anyext_s32_from_s8 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all } -# CHECK-NEXT: - { id: 1, class: gpr32all } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %w0 - - %0(s8) = COPY %w0 - %1(s32) = G_ANYEXT %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: zext_s64_from_s32 -name: zext_s64_from_s32 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = UBFMXri %2, 0, 31 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s64) = G_ZEXT %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: zext_s32_from_s16 -name: zext_s32_from_s16 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 15 -body: | - bb.0: - liveins: %w0 - - %0(s16) = COPY %w0 - %1(s32) = G_ZEXT %0 - %w0 = COPY %1 -... - ---- -# CHECK-LABEL: name: zext_s32_from_s8 -name: zext_s32_from_s8 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 7 -body: | - bb.0: - liveins: %w0 - - %0(s8) = COPY %w0 - %1(s32) = G_ZEXT %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: zext_s16_from_s8 -name: zext_s16_from_s8 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 7 -body: | - bb.0: - liveins: %w0 - - %0(s8) = COPY %w0 - %1(s16) = G_ZEXT %0 - %w0 = COPY %1(s16) -... - ---- -# CHECK-LABEL: name: sext_s64_from_s32 -name: sext_s64_from_s32 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = SBFMXri %2, 0, 31 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s64) = G_SEXT %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: sext_s32_from_s16 -name: sext_s32_from_s16 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 15 -body: | - bb.0: - liveins: %w0 - - %0(s16) = COPY %w0 - %1(s32) = G_SEXT %0 - %w0 = COPY %1 -... - ---- -# CHECK-LABEL: name: sext_s32_from_s8 -name: sext_s32_from_s8 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 7 -body: | - bb.0: - liveins: %w0 - - %0(s8) = COPY %w0 - %1(s32) = G_SEXT %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: sext_s16_from_s8 -name: sext_s16_from_s8 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 7 -body: | - bb.0: - liveins: %w0 - - %0(s8) = COPY %w0 - %1(s16) = G_SEXT %0 - %w0 = COPY %1(s16) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir deleted file mode 100644 index 6537408f6d98..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir +++ /dev/null @@ -1,150 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @inttoptr_p0_s64() { ret void } - define void @ptrtoint_s64_p0() { ret void } - define void @ptrtoint_s32_p0() { ret void } - define void @ptrtoint_s16_p0() { ret void } - define void @ptrtoint_s8_p0() { ret void } - define void @ptrtoint_s1_p0() { ret void } -... - ---- -# CHECK-LABEL: name: inttoptr_p0_s64 -name: inttoptr_p0_s64 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all } -# CHECK-NEXT: - { id: 1, class: gpr64all } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %x0 - %0(s64) = COPY %x0 - %1(p0) = G_INTTOPTR %0 - %x0 = COPY %1(p0) -... - ---- -# CHECK-LABEL: name: ptrtoint_s64_p0 -name: ptrtoint_s64_p0 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s64) = G_PTRTOINT %0 - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: ptrtoint_s32_p0 -name: ptrtoint_s32_p0 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s32) = G_PTRTOINT %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: ptrtoint_s16_p0 -name: ptrtoint_s16_p0 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s16) = G_PTRTOINT %0 - %w0 = COPY %1(s16) -... - ---- -# CHECK-LABEL: name: ptrtoint_s8_p0 -name: ptrtoint_s8_p0 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s8) = G_PTRTOINT %0 - %w0 = COPY %1(s8) -... - ---- -# CHECK-LABEL: name: ptrtoint_s1_p0 -name: ptrtoint_s1_p0 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s1) = G_PTRTOINT %0 - %w0 = COPY %1(s1) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-load.mir b/test/CodeGen/AArch64/GlobalISel/select-load.mir deleted file mode 100644 index 9188e2b0c0fc..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ /dev/null @@ -1,515 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @load_s64_gpr(i64* %addr) { ret void } - define void @load_s32_gpr(i32* %addr) { ret void } - define void @load_s16_gpr(i16* %addr) { ret void } - define void @load_s8_gpr(i8* %addr) { ret void } - - define void @load_fi_s64_gpr() { - %ptr0 = alloca i64 - ret void - } - - define void @load_gep_128_s64_gpr(i64* %addr) { ret void } - define void @load_gep_512_s32_gpr(i32* %addr) { ret void } - define void @load_gep_64_s16_gpr(i16* %addr) { ret void } - define void @load_gep_1_s8_gpr(i8* %addr) { ret void } - - define void @load_s64_fpr(i64* %addr) { ret void } - define void @load_s32_fpr(i32* %addr) { ret void } - define void @load_s16_fpr(i16* %addr) { ret void } - define void @load_s8_fpr(i8* %addr) { ret void } - - define void @load_gep_8_s64_fpr(i64* %addr) { ret void } - define void @load_gep_16_s32_fpr(i32* %addr) { ret void } - define void @load_gep_64_s16_fpr(i16* %addr) { ret void } - define void @load_gep_32_s8_fpr(i8* %addr) { ret void } - -... - ---- -# CHECK-LABEL: name: load_s64_gpr -name: load_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: load_s32_gpr -name: load_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: load_s16_gpr -name: load_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) - %w0 = COPY %1(s16) -... - ---- -# CHECK-LABEL: name: load_s8_gpr -name: load_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) - %w0 = COPY %1(s8) -... - ---- -# CHECK-LABEL: name: load_fi_s64_gpr -name: load_fi_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -stack: - - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } - -# CHECK: body: -# CHECK: %1 = LDRXui %stack.0.ptr0, 0 :: (load 8) -# CHECK: %x0 = COPY %1 -body: | - bb.0: - liveins: %x0 - - %0(p0) = G_FRAME_INDEX %stack.0.ptr0 - %1(s64) = G_LOAD %0 :: (load 8) - %x0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: load_gep_128_s64_gpr -name: load_gep_128_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRXui %0, 16 :: (load 8 from %ir.addr) -# CHECK: %x0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 128 - %2(p0) = G_GEP %0, %1 - %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) - %x0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_512_s32_gpr -name: load_gep_512_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRWui %0, 128 :: (load 4 from %ir.addr) -# CHECK: %w0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 512 - %2(p0) = G_GEP %0, %1 - %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) - %w0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_64_s16_gpr -name: load_gep_64_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRHHui %0, 32 :: (load 2 from %ir.addr) -# CHECK: %w0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 64 - %2(p0) = G_GEP %0, %1 - %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) - %w0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_1_s8_gpr -name: load_gep_1_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRBBui %0, 1 :: (load 1 from %ir.addr) -# CHECK: %w0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 1 - %2(p0) = G_GEP %0, %1 - %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) - %w0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_s64_fpr -name: load_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) - %d0 = COPY %1(s64) -... - ---- -# CHECK-LABEL: name: load_s32_fpr -name: load_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) - %s0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: load_s16_fpr -name: load_s16_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr16 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) - %h0 = COPY %1(s16) -... - ---- -# CHECK-LABEL: name: load_s8_fpr -name: load_s8_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr8 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) - %b0 = COPY %1(s8) -... - ---- -# CHECK-LABEL: name: load_gep_8_s64_fpr -name: load_gep_8_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRDui %0, 1 :: (load 8 from %ir.addr) -# CHECK: %d0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 8 - %2(p0) = G_GEP %0, %1 - %3(s64) = G_LOAD %2 :: (load 8 from %ir.addr) - %d0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_16_s32_fpr -name: load_gep_16_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRSui %0, 4 :: (load 4 from %ir.addr) -# CHECK: %s0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 16 - %2(p0) = G_GEP %0, %1 - %3(s32) = G_LOAD %2 :: (load 4 from %ir.addr) - %s0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_64_s16_fpr -name: load_gep_64_s16_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: fpr16 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRHui %0, 32 :: (load 2 from %ir.addr) -# CHECK: %h0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 64 - %2(p0) = G_GEP %0, %1 - %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr) - %h0 = COPY %3 -... - ---- -# CHECK-LABEL: name: load_gep_32_s8_fpr -name: load_gep_32_s8_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: fpr8 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRBui %0, 32 :: (load 1 from %ir.addr) -# CHECK: %b0 = COPY %3 -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 32 - %2(p0) = G_GEP %0, %1 - %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr) - %b0 = COPY %3 -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir b/test/CodeGen/AArch64/GlobalISel/select-muladd.mir deleted file mode 100644 index 7d5b43bc16d5..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-muladd.mir +++ /dev/null @@ -1,50 +0,0 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @SMADDLrrr_gpr() { ret void } -... - ---- -# CHECK-LABEL: name: SMADDLrrr_gpr -name: SMADDLrrr_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -# CHECK-NEXT: - { id: 3, class: gpr } -# CHECK-NEXT: - { id: 4, class: gpr } -# CHECK-NEXT: - { id: 5, class: gpr } -# CHECK-NEXT: - { id: 6, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - - { id: 6, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = COPY %w2 -# CHECK: %6 = SMADDLrrr %1, %2, %0 -body: | - bb.0: - liveins: %x0, %w1, %w2 - - %0(s64) = COPY %x0 - %1(s32) = COPY %w1 - %2(s32) = COPY %w2 - %3(s64) = G_SEXT %1 - %4(s64) = G_SEXT %2 - %5(s64) = G_MUL %3, %4 - %6(s64) = G_ADD %0, %5 - %x0 = COPY %6 -... - diff --git a/test/CodeGen/AArch64/GlobalISel/select-property.mir b/test/CodeGen/AArch64/GlobalISel/select-property.mir deleted file mode 100644 index 86961ac597e1..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-property.mir +++ /dev/null @@ -1,21 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @selected_property() { ret void } -... - ---- -# Check that we set the "selected" property. -# CHECK-LABEL: name: selected_property -# CHECK: legalized: true -# CHECK-NEXT: regBankSelected: true -# CHECK-NEXT: selected: true -name: selected_property -legalized: true -regBankSelected: true -selected: false -body: | - bb.0: -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-store.mir b/test/CodeGen/AArch64/GlobalISel/select-store.mir deleted file mode 100644 index 9b8f5c566ce0..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-store.mir +++ /dev/null @@ -1,463 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @store_s64_gpr(i64* %addr) { ret void } - define void @store_s32_gpr(i32* %addr) { ret void } - define void @store_s16_gpr(i16* %addr) { ret void } - define void @store_s8_gpr(i8* %addr) { ret void } - - define void @store_zero_s64_gpr(i64* %addr) { ret void } - define void @store_zero_s32_gpr(i32* %addr) { ret void } - - define void @store_fi_s64_gpr() { - %ptr0 = alloca i64 - ret void - } - - define void @store_gep_128_s64_gpr(i64* %addr) { ret void } - define void @store_gep_512_s32_gpr(i32* %addr) { ret void } - define void @store_gep_64_s16_gpr(i16* %addr) { ret void } - define void @store_gep_1_s8_gpr(i8* %addr) { ret void } - - define void @store_s64_fpr(i64* %addr) { ret void } - define void @store_s32_fpr(i32* %addr) { ret void } - - define void @store_gep_8_s64_fpr(i64* %addr) { ret void } - define void @store_gep_8_s32_fpr(i32* %addr) { ret void } -... - ---- -# CHECK-LABEL: name: store_s64_gpr -name: store_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr) -body: | - bb.0: - liveins: %x0, %x1 - - %0(p0) = COPY %x0 - %1(s64) = COPY %x1 - G_STORE %1, %0 :: (store 8 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_s32_gpr -name: store_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s32) = COPY %w1 - G_STORE %1, %0 :: (store 4 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_s16_gpr -name: store_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s16) = COPY %w1 - G_STORE %1, %0 :: (store 2 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_s8_gpr -name: store_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s8) = COPY %w1 - G_STORE %1, %0 :: (store 1 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_zero_s64_gpr -name: store_zero_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRXui %xzr, %0, 0 :: (store 8 into %ir.addr) -body: | - bb.0: - liveins: %x0, %x1 - - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 0 - G_STORE %1, %0 :: (store 8 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_zero_s32_gpr -name: store_zero_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRWui %wzr, %0, 0 :: (store 4 into %ir.addr) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(s32) = G_CONSTANT i32 0 - G_STORE %1, %0 :: (store 4 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_fi_s64_gpr -name: store_fi_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -stack: - - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRXui %0, %stack.0.ptr0, 0 :: (store 8) -body: | - bb.0: - liveins: %x0 - - %0(p0) = COPY %x0 - %1(p0) = G_FRAME_INDEX %stack.0.ptr0 - G_STORE %0, %1 :: (store 8) -... - ---- -# CHECK-LABEL: name: store_gep_128_s64_gpr -name: store_gep_128_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: STRXui %1, %0, 16 :: (store 8 into %ir.addr) -body: | - bb.0: - liveins: %x0, %x1 - - %0(p0) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_CONSTANT i64 128 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 8 into %ir.addr) -... - ---- -# CHECK-LABEL: name: store_gep_512_s32_gpr -name: store_gep_512_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRWui %1, %0, 128 :: (store 4 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s32) = COPY %w1 - %2(s64) = G_CONSTANT i64 512 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 4 into %ir.addr) -... - ---- -# CHECK-LABEL: name: store_gep_64_s16_gpr -name: store_gep_64_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRHHui %1, %0, 32 :: (store 2 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s16) = COPY %w1 - %2(s64) = G_CONSTANT i64 64 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 2 into %ir.addr) -... - ---- -# CHECK-LABEL: name: store_gep_1_s8_gpr -name: store_gep_1_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRBBui %1, %0, 1 :: (store 1 into %ir.addr) -body: | - bb.0: - liveins: %x0, %w1 - - %0(p0) = COPY %x0 - %1(s8) = COPY %w1 - %2(s64) = G_CONSTANT i64 1 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 1 into %ir.addr) -... - ---- -# CHECK-LABEL: name: store_s64_fpr -name: store_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %d1 -# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr) -body: | - bb.0: - liveins: %x0, %d1 - - %0(p0) = COPY %x0 - %1(s64) = COPY %d1 - G_STORE %1, %0 :: (store 8 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_s32_fpr -name: store_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %s1 -# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr) -body: | - bb.0: - liveins: %x0, %s1 - - %0(p0) = COPY %x0 - %1(s32) = COPY %s1 - G_STORE %1, %0 :: (store 4 into %ir.addr) - -... - ---- -# CHECK-LABEL: name: store_gep_8_s64_fpr -name: store_gep_8_s64_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr64 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %d1 -# CHECK: STRDui %1, %0, 1 :: (store 8 into %ir.addr) -body: | - bb.0: - liveins: %x0, %d1 - - %0(p0) = COPY %x0 - %1(s64) = COPY %d1 - %2(s64) = G_CONSTANT i64 8 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 8 into %ir.addr) -... - ---- -# CHECK-LABEL: name: store_gep_8_s32_fpr -name: store_gep_8_s32_fpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -# CHECK-NEXT: - { id: 1, class: fpr32 } -# CHECK-NEXT: - { id: 2, class: gpr } -# CHECK-NEXT: - { id: 3, class: gpr } -registers: - - { id: 0, class: gpr } - - { id: 1, class: fpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %s1 -# CHECK: STRSui %1, %0, 2 :: (store 4 into %ir.addr) -body: | - bb.0: - liveins: %x0, %s1 - - %0(p0) = COPY %x0 - %1(s32) = COPY %s1 - %2(s64) = G_CONSTANT i64 8 - %3(p0) = G_GEP %0, %2 - G_STORE %1, %3 :: (store 4 into %ir.addr) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/test/CodeGen/AArch64/GlobalISel/select-trunc.mir deleted file mode 100644 index fc3546e777f7..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ /dev/null @@ -1,81 +0,0 @@ -# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @trunc_s32_s64() { ret void } - define void @trunc_s8_s64() { ret void } - define void @trunc_s1_s32() { ret void } -... - ---- -# CHECK-LABEL: name: trunc_s32_s64 -name: trunc_s32_s64 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s32) = G_TRUNC %0 - %w0 = COPY %1(s32) -... - ---- -# CHECK-LABEL: name: trunc_s8_s64 -name: trunc_s8_s64 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %1 = COPY %0.sub_32 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s8) = G_TRUNC %0 - %w0 = COPY %1(s8) -... - ---- -# CHECK-LABEL: name: trunc_s1_s32 -name: trunc_s1_s32 -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - -# CHECK: body: -# CHECK: %1 = COPY %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s1) = G_TRUNC %0 - %w0 = COPY %1(s1) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/test/CodeGen/AArch64/GlobalISel/select-xor.mir deleted file mode 100644 index e787849c8d1b..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select-xor.mir +++ /dev/null @@ -1,165 +0,0 @@ -# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @xor_s32_gpr() { ret void } - define void @xor_s64_gpr() { ret void } - define void @xor_constant_n1_s32_gpr() { ret void } - define void @xor_constant_n1_s64_gpr() { ret void } - define void @xor_constant_n1_s32_gpr_2bb() { ret void } - -... - ---- -# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32. -# Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: xor_s32_gpr -name: xor_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = EORWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s32) = COPY %w0 - %1(s32) = COPY %w1 - %2(s32) = G_XOR %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as xor_s64_gpr, for 64-bit operations. -# CHECK-LABEL: name: xor_s64_gpr -name: xor_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr64 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = EORXrr %0, %1 -body: | - bb.0: - liveins: %x0, %x1 - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = G_XOR %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32. -# Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: xor_constant_n1_s32_gpr -name: xor_constant_n1_s32_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ORNWrr %wzr, %0 -body: | - bb.0: - liveins: %w0 - - %0(s32) = COPY %w0 - %1(s32) = G_CONSTANT i32 -1 - %2(s32) = G_XOR %0, %1 - %w0 = COPY %2(s32) -... - ---- -# Same as xor_constant_n1_s64_gpr, for 64-bit operations. -# CHECK-LABEL: name: xor_constant_n1_s64_gpr -name: xor_constant_n1_s64_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64 } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %2 = ORNXrr %xzr, %0 -body: | - bb.0: - liveins: %x0 - - %0(s64) = COPY %x0 - %1(s64) = G_CONSTANT i64 -1 - %2(s64) = G_XOR %0, %1 - %x0 = COPY %2(s64) -... - ---- -# Check that we can obtain constants from other basic blocks. -# CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb -name: xor_constant_n1_s32_gpr_2bb -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: B %bb.1 -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ORNWrr %wzr, %0 - -body: | - bb.0: - liveins: %w0, %w1 - successors: %bb.1 - %1(s32) = G_CONSTANT i32 -1 - G_BR %bb.1 - bb.1: - %0(s32) = COPY %w0 - %2(s32) = G_XOR %0, %1 - %w0 = COPY %2(s32) -... diff --git a/test/CodeGen/AArch64/GlobalISel/select.mir b/test/CodeGen/AArch64/GlobalISel/select.mir deleted file mode 100644 index 8bffa085fdca..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/select.mir +++ /dev/null @@ -1,311 +0,0 @@ -# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=IOS -# RUN: llc -O0 -mtriple=aarch64-linux-gnu -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-DEFAULT -# RUN: llc -O0 -mtriple=aarch64-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=LINUX-PIC - ---- | - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - - define void @frame_index() { - %ptr0 = alloca i64 - ret void - } - - define i8* @gep(i8* %in) { ret i8* undef } - - define i8* @ptr_mask(i8* %in) { ret i8* undef } - - @var_local = global i8 0 - define i8* @global_local() { ret i8* undef } - - @var_got = external global i8 - define i8* @global_got() { ret i8* undef } - - define void @icmp() { ret void } - define void @fcmp() { ret void } - - define void @phi() { ret void } - - define void @select() { ret void } -... - ---- -# CHECK-LABEL: name: frame_index -name: frame_index -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp } -registers: - - { id: 0, class: gpr } - -stack: - - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } - -# CHECK: body: -# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0 -body: | - bb.0: - %0(p0) = G_FRAME_INDEX %stack.0.ptr0 - %x0 = COPY %0(p0) -... - ---- -# CHECK-LABEL: name: gep -name: gep -legalized: true -regBankSelected: true -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %1 = MOVi64imm 42 -# CHECK: %2 = ADDXrr %0, %1 -body: | - bb.0: - liveins: %x0 - %0(p0) = COPY %x0 - %1(s64) = G_CONSTANT i64 42 - %2(p0) = G_GEP %0, %1(s64) - %x0 = COPY %2(p0) -... - ---- -# CHECK-LABEL: name: ptr_mask -name: ptr_mask -legalized: true -regBankSelected: true - -# CHECK: body: -# CHECK: %1 = ANDXri %0, 8060 -body: | - bb.0: - liveins: %x0 - %0:gpr(p0) = COPY %x0 - %1:gpr(p0) = G_PTR_MASK %0, 3 - %x0 = COPY %1(p0) -... - ---- -# Global defined in the same linkage unit so no GOT is needed -# CHECK-LABEL: name: global_local -name: global_local -legalized: true -regBankSelected: true -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# IOS: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local -# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_local, target-flags(aarch64-pageoff, aarch64-nc) @var_local -# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_local -body: | - bb.0: - %0(p0) = G_GLOBAL_VALUE @var_local - %x0 = COPY %0(p0) -... - ---- -# CHECK-LABEL: name: global_got -name: global_got -legalized: true -regBankSelected: true -registers: - - { id: 0, class: gpr } - -# CHECK: body: -# IOS: %0 = LOADgot target-flags(aarch64-got) @var_got -# LINUX-DEFAULT: %0 = MOVaddr target-flags(aarch64-page) @var_got, target-flags(aarch64-pageoff, aarch64-nc) @var_got -# LINUX-PIC: %0 = LOADgot target-flags(aarch64-got) @var_got -body: | - bb.0: - %0(p0) = G_GLOBAL_VALUE @var_got - %x0 = COPY %0(p0) -... - ---- -# CHECK-LABEL: name: icmp -name: icmp -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr64 } -# CHECK-NEXT: - { id: 3, class: gpr32 } -# CHECK-NEXT: - { id: 4, class: gpr64 } -# CHECK-NEXT: - { id: 5, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - -# CHECK: body: -# CHECK: %wzr = SUBSWrr %0, %0, implicit-def %nzcv -# CHECK: %1 = CSINCWr %wzr, %wzr, 1, implicit %nzcv - -# CHECK: %xzr = SUBSXrr %2, %2, implicit-def %nzcv -# CHECK: %3 = CSINCWr %wzr, %wzr, 3, implicit %nzcv - -# CHECK: %xzr = SUBSXrr %4, %4, implicit-def %nzcv -# CHECK: %5 = CSINCWr %wzr, %wzr, 0, implicit %nzcv - -body: | - bb.0: - liveins: %w0, %x0 - - %0(s32) = COPY %w0 - %1(s1) = G_ICMP intpred(eq), %0, %0 - %w0 = COPY %1(s1) - - %2(s64) = COPY %x0 - %3(s1) = G_ICMP intpred(uge), %2, %2 - %w0 = COPY %3(s1) - - %4(p0) = COPY %x0 - %5(s1) = G_ICMP intpred(ne), %4, %4 - %w0 = COPY %5(s1) -... - ---- -# CHECK-LABEL: name: fcmp -name: fcmp -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: fpr64 } -# CHECK-NEXT: - { id: 3, class: gpr32 } -# CHECK-NEXT: - { id: 4, class: gpr32 } -# CHECK-NEXT: - { id: 5, class: gpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - - { id: 2, class: fpr } - - { id: 3, class: gpr } - -# CHECK: body: -# CHECK: FCMPSrr %0, %0, implicit-def %nzcv -# CHECK: [[TST_MI:%[0-9]+]] = CSINCWr %wzr, %wzr, 5, implicit %nzcv -# CHECK: [[TST_GT:%[0-9]+]] = CSINCWr %wzr, %wzr, 13, implicit %nzcv -# CHECK: %1 = ORRWrr [[TST_MI]], [[TST_GT]] - -# CHECK: FCMPDrr %2, %2, implicit-def %nzcv -# CHECK: %3 = CSINCWr %wzr, %wzr, 4, implicit %nzcv - -body: | - bb.0: - liveins: %w0, %x0 - - %0(s32) = COPY %s0 - %1(s1) = G_FCMP floatpred(one), %0, %0 - %w0 = COPY %1(s1) - - %2(s64) = COPY %d0 - %3(s1) = G_FCMP floatpred(uge), %2, %2 - %w0 = COPY %3(s1) - -... - ---- -# CHECK-LABEL: name: phi -name: phi -legalized: true -regBankSelected: true -tracksRegLiveness: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: fpr32 } -registers: - - { id: 0, class: fpr } - - { id: 1, class: gpr } - - { id: 2, class: fpr } - -# CHECK: body: -# CHECK: bb.1: -# CHECK: %2 = PHI %0, %bb.0, %2, %bb.1 - -body: | - bb.0: - liveins: %s0, %w0 - successors: %bb.1 - %0(s32) = COPY %s0 - %1(s1) = COPY %w0 - - bb.1: - successors: %bb.1, %bb.2 - %2(s32) = PHI %0, %bb.0, %2, %bb.1 - G_BRCOND %1, %bb.1 - - bb.2: - %s0 = COPY %2 - RET_ReallyLR implicit %s0 -... - ---- -# CHECK-LABEL: name: select -name: select -legalized: true -regBankSelected: true -tracksRegLiveness: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -# CHECK-NEXT: - { id: 3, class: gpr32 } -# CHECK-NEXT: - { id: 4, class: gpr64 } -# CHECK-NEXT: - { id: 5, class: gpr64 } -# CHECK-NEXT: - { id: 6, class: gpr64 } -# CHECK-NEXT: - { id: 7, class: gpr64 } -# CHECK-NEXT: - { id: 8, class: gpr64 } -# CHECK-NEXT: - { id: 9, class: gpr64 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - - { id: 3, class: gpr } - - { id: 4, class: gpr } - - { id: 5, class: gpr } - - { id: 6, class: gpr } - - { id: 7, class: gpr } - - { id: 8, class: gpr } - - { id: 9, class: gpr } - -# CHECK: body: -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv -# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv -# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv -# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv -# CHECK: %9 = CSELXr %7, %8, 1, implicit %nzcv -body: | - bb.0: - liveins: %w0, %w1, %w2 - %0(s1) = COPY %w0 - - %1(s32) = COPY %w1 - %2(s32) = COPY %w2 - %3(s32) = G_SELECT %0, %1, %2 - %w0 = COPY %3(s32) - - %4(s64) = COPY %x0 - %5(s64) = COPY %x1 - %6(s64) = G_SELECT %0, %4, %5 - %x0 = COPY %6(s64) - - %7(p0) = COPY %x0 - %8(p0) = COPY %x1 - %9(p0) = G_SELECT %0, %7, %8 - %x0 = COPY %9(p0) -... diff --git a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll b/test/CodeGen/AArch64/GlobalISel/translate-gep.ll deleted file mode 100644 index e4c18757418d..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/translate-gep.ll +++ /dev/null @@ -1,85 +0,0 @@ -; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s - -%type = type [4 x {i8, i32}] - -define %type* @first_offset_const(%type* %addr) { -; CHECK-LABEL: name: first_offset_const -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[OFFSET:%[0-9]+]](s64) = G_CONSTANT i64 32 -; CHECK: [[RES:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64) -; CHECK: %x0 = COPY [[RES]](p0) - - %res = getelementptr %type, %type* %addr, i32 1 - ret %type* %res -} - -define %type* @first_offset_trivial(%type* %addr) { -; CHECK-LABEL: name: first_offset_trivial -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[TRIVIAL:%[0-9]+]](p0) = COPY [[BASE]](p0) -; CHECK: %x0 = COPY [[TRIVIAL]](p0) - - %res = getelementptr %type, %type* %addr, i32 0 - ret %type* %res -} - -define %type* @first_offset_variable(%type* %addr, i64 %idx) { -; CHECK-LABEL: name: first_offset_variable -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1 -; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32 -; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]] -; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64) -; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0) -; CHECK: %x0 = COPY [[RES]](p0) - - %res = getelementptr %type, %type* %addr, i64 %idx - ret %type* %res -} - -define %type* @first_offset_ext(%type* %addr, i32 %idx) { -; CHECK-LABEL: name: first_offset_ext -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IDX32:%[0-9]+]](s32) = COPY %w1 -; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 32 -; CHECK: [[IDX64:%[0-9]+]](s64) = G_SEXT [[IDX32]](s32) -; CHECK: [[OFFSET:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX64]] -; CHECK: [[STEP0:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET]](s64) -; CHECK: [[RES:%[0-9]+]](p0) = COPY [[STEP0]](p0) -; CHECK: %x0 = COPY [[RES]](p0) - - %res = getelementptr %type, %type* %addr, i32 %idx - ret %type* %res -} - -%type1 = type [4 x [4 x i32]] -define i32* @const_then_var(%type1* %addr, i64 %idx) { -; CHECK-LABEL: name: const_then_var -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1 -; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 272 -; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 4 -; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64) -; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]] -; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64) -; CHECK: [[RES:%[0-9]+]](p0) = COPY [[BASE2]](p0) -; CHECK: %x0 = COPY [[RES]](p0) - - %res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx - ret i32* %res -} - -define i32* @var_then_const(%type1* %addr, i64 %idx) { -; CHECK-LABEL: name: var_then_const -; CHECK: [[BASE:%[0-9]+]](p0) = COPY %x0 -; CHECK: [[IDX:%[0-9]+]](s64) = COPY %x1 -; CHECK: [[SIZE:%[0-9]+]](s64) = G_CONSTANT i64 64 -; CHECK: [[OFFSET2:%[0-9]+]](s64) = G_CONSTANT i64 40 -; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_MUL [[SIZE]], [[IDX]] -; CHECK: [[BASE1:%[0-9]+]](p0) = G_GEP [[BASE]], [[OFFSET1]](s64) -; CHECK: [[BASE2:%[0-9]+]](p0) = G_GEP [[BASE1]], [[OFFSET2]](s64) -; CHECK: %x0 = COPY [[BASE2]](p0) - - %res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2 - ret i32* %res -} diff --git a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll b/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll deleted file mode 100644 index 3bd56fa4cebc..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc -mtriple=aarch64-apple-ios -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s - -define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64, - i32, ...) { -; CHECK-LABEL: name: test_varargs_sentinel -; CHECK: fixedStack: -; CHECK: - { id: [[VARARGS_SLOT:[0-9]+]], offset: 8 -; CHECK: body: -; CHECK: [[LIST:%[0-9]+]] = COPY %x0 -; CHECK: [[VARARGS_AREA:%[0-9]+]] = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0 -; CHECK: STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store 8 into %ir.list, align 0) - call void @llvm.va_start(i8* %list) - ret void -} - -declare void @llvm.va_start(i8*) diff --git a/test/CodeGen/AArch64/GlobalISel/vastart.ll b/test/CodeGen/AArch64/GlobalISel/vastart.ll deleted file mode 100644 index ae44e8fc5dea..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/vastart.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-IOS %s -; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LINUX %s - - -declare void @llvm.va_start(i8*) -define void @test_va_start(i8* %list) { -; CHECK-LABEL: name: test_va_start -; CHECK: [[LIST:%[0-9]+]](p0) = COPY %x0 -; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store 8 into %ir.list, align 0) -; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store 32 into %ir.list, align 0) - call void @llvm.va_start(i8* %list) - ret void -} diff --git a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir deleted file mode 100644 index 9a2f7f7e54f8..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir +++ /dev/null @@ -1,22 +0,0 @@ -# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test() { ret void } - -... ---- -# CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function *** -# CHECK: instruction: %vreg0<def>(s64) = COPY -# CHECK: operand 0: %vreg0<def> -name: test -regBankSelected: true -registers: - - { id: 0, class: _ } -body: | - bb.0: - liveins: %x0 - %0(s64) = COPY %x0 -... diff --git a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir deleted file mode 100644 index 2149903d08a7..000000000000 --- a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir +++ /dev/null @@ -1,32 +0,0 @@ -# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - target triple = "aarch64--" - define void @test() { ret void } - -... - ---- -name: test -regBankSelected: true -selected: true -registers: - - { id: 0, class: gpr64 } - - { id: 1, class: gpr64 } - - { id: 2, class: gpr } -body: | - bb.0: - liveins: %x0 - %0 = COPY %x0 - - ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function *** - ; CHECK: instruction: %vreg1<def> = G_ADD - %1 = G_ADD %0, %0 - - ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function *** - ; CHECK: instruction: %vreg2<def>(s64) = COPY - ; CHECK: operand 0: %vreg2<def> - %2(s64) = COPY %x0 -... |