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Diffstat (limited to 'test/CodeGen/AArch64/arm64-anyregcc.ll')
-rw-r--r--test/CodeGen/AArch64/arm64-anyregcc.ll194
1 files changed, 142 insertions, 52 deletions
diff --git a/test/CodeGen/AArch64/arm64-anyregcc.ll b/test/CodeGen/AArch64/arm64-anyregcc.ll
index 1af310383243..10989a07990c 100644
--- a/test/CodeGen/AArch64/arm64-anyregcc.ll
+++ b/test/CodeGen/AArch64/arm64-anyregcc.ll
@@ -4,7 +4,7 @@
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
@@ -48,18 +48,24 @@
; CHECK-NEXT: .short 3
; Loc 0: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Constant 3
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 3
define i64 @test() nounwind ssp uwtable {
entry:
@@ -69,18 +75,22 @@ entry:
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-LABEL: .long L{{.*}}-_property_access1
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
entry:
@@ -91,18 +101,22 @@ entry:
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-LABEL: .long L{{.*}}-_property_access2
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access2() nounwind ssp uwtable {
entry:
@@ -114,18 +128,22 @@ entry:
; property access 3 - %obj is a frame index
; CHECK-LABEL: .long L{{.*}}-_property_access3
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Direct FP - 8
; CHECK-NEXT: .byte 2
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -8
define i64 @property_access3() nounwind ssp uwtable {
entry:
@@ -137,78 +155,106 @@ entry:
; anyreg_test1
; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 10: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 11: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 12: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 13: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -219,78 +265,106 @@ entry:
; anyreg_test2
; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 10: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 11: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 12: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 13: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -308,18 +382,24 @@ entry:
; CHECK-NEXT: .short 3
; Loc 0: Register (some register that will be spilled to the stack)
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
@@ -337,28 +417,38 @@ entry:
; CHECK-NEXT: .short 5
; Loc 0: Return a register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Arg0 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Arg1 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Arg2 spilled to FP -96
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -96
; Loc 4: Arg3 spilled to FP - 88
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -88
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 19:03:04 +0000