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-rw-r--r--test/CodeGen/ARM/Windows/read-only-data.ll2
-rw-r--r--test/CodeGen/ARM/Windows/structors.ll2
-rw-r--r--test/CodeGen/ARM/alloc-no-stack-realign.ll17
-rw-r--r--test/CodeGen/ARM/memcpy-inline.ll15
-rw-r--r--test/CodeGen/ARM/setcc-type-mismatch.ll11
-rw-r--r--test/CodeGen/ARM/sub-cmp-peephole.ll60
-rw-r--r--test/CodeGen/ARM/vector-load.ll253
-rw-r--r--test/CodeGen/ARM/vector-store.ll258
8 files changed, 92 insertions, 526 deletions
diff --git a/test/CodeGen/ARM/Windows/read-only-data.ll b/test/CodeGen/ARM/Windows/read-only-data.ll
index 0ccb5ededff2..0438d68b55c6 100644
--- a/test/CodeGen/ARM/Windows/read-only-data.ll
+++ b/test/CodeGen/ARM/Windows/read-only-data.ll
@@ -10,6 +10,6 @@ entry:
ret void
}
-; CHECK: .section .rdata,"rd"
+; CHECK: .section .rdata,"dr"
; CHECK-NOT: .section ".rodata.str1.1"
diff --git a/test/CodeGen/ARM/Windows/structors.ll b/test/CodeGen/ARM/Windows/structors.ll
index a1a90265c03a..874b5bf35b81 100644
--- a/test/CodeGen/ARM/Windows/structors.ll
+++ b/test/CodeGen/ARM/Windows/structors.ll
@@ -7,6 +7,6 @@ entry:
ret void
}
-; CHECK: .section .CRT$XCU,"rd"
+; CHECK: .section .CRT$XCU,"dr"
; CHECK: .long function
diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll
index 5ad87191efe9..24c28baff881 100644
--- a/test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -9,8 +9,8 @@
define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
entry:
; NO-REALIGN-LABEL: test1
-; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
-; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
+; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -21,14 +21,16 @@ entry:
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
+; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
+; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
%retval = alloca <16 x float>, align 16
%0 = load <16 x float>* @T3_retval, align 16
@@ -42,8 +44,8 @@ define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
entry:
; REALIGN-LABEL: test2
; REALIGN: bfc sp, #0, #6
-; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]
-; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!
+; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
+; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
@@ -63,7 +65,8 @@ entry:
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
-; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!
+; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
+; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
%retval = alloca <16 x float>, align 16
%0 = load <16 x float>* @T3_retval, align 16
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
index 33ac4e125633..84ce4a7f0e79 100644
--- a/test/CodeGen/ARM/memcpy-inline.ll
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -46,8 +46,10 @@ entry:
; CHECK: movw [[REG2:r[0-9]+]], #16716
; CHECK: movt [[REG2:r[0-9]+]], #72
; CHECK: str [[REG2]], [r0, #32]
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
+; CHECK: adds r0, #16
+; CHECK: adds r1, #16
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
@@ -57,8 +59,10 @@ entry:
define void @t3(i8* nocapture %C) nounwind {
entry:
; CHECK-LABEL: t3:
-; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
-; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]!
+; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
+; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
+; CHECK: adds r0, #16
+; CHECK: adds r1, #16
; CHECK: vld1.8 {d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}}, [r0]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
@@ -69,8 +73,7 @@ define void @t4(i8* nocapture %C) nounwind {
entry:
; CHECK-LABEL: t4:
; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
-; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]!
-; CHECK: strh [[REG5:r[0-9]+]], [r0]
+; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
ret void
}
diff --git a/test/CodeGen/ARM/setcc-type-mismatch.ll b/test/CodeGen/ARM/setcc-type-mismatch.ll
new file mode 100644
index 000000000000..2cfdba12db54
--- /dev/null
+++ b/test/CodeGen/ARM/setcc-type-mismatch.ll
@@ -0,0 +1,11 @@
+; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s
+
+define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) {
+; CHECK-LABEL: test_mismatched_setcc:
+; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}}
+; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]
+
+ %tst = icmp eq <4 x i22> %l, %r
+ store <4 x i1> %tst, <4 x i1>* %addr
+ ret void
+}
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index 19727dabf09e..f7328dc580ef 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -88,6 +88,19 @@ if.end11: ; preds = %num2long.exit
ret i32 23
}
+; When considering the producer of cmp's src as the subsuming instruction,
+; only consider that when the comparison is to 0.
+define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_src_nonzero:
+; CHECK: sub
+; CHECK: cmp
+ %sub = sub i32 %a, %b
+ %cmp = icmp eq i32 %sub, 17
+ %ret = select i1 %cmp, i32 %x, i32 %y
+ ret i32 %ret
+}
+
define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
entry:
; CHECK-LABEL: float_sel:
@@ -144,3 +157,50 @@ entry:
store i32 %sub, i32* @t
ret double %ret
}
+
+declare void @abort()
+declare void @exit(i32)
+
+; If the comparison uses the V bit (signed overflow/underflow), we can't
+; omit the comparison.
+define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_slt0
+; CHECK: sub
+; CHECK: cmp
+; CHECK: bge
+ %load = load i32* @t, align 4
+ %sub = sub i32 %load, 17
+ %cmp = icmp slt i32 %sub, 0
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+ call void @abort()
+ unreachable
+
+if.else:
+ call void @exit(i32 0)
+ unreachable
+}
+
+; Same for the C bit. (Note the ult X, 0 is trivially
+; false, so the DAG combiner may or may not optimize it).
+define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
+entry:
+; CHECK-LABEL: cmp_ult0
+; CHECK: sub
+; CHECK: cmp
+; CHECK: bhs
+ %load = load i32* @t, align 4
+ %sub = sub i32 %load, 17
+ %cmp = icmp ult i32 %sub, 0
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+ call void @abort()
+ unreachable
+
+if.else:
+ call void @exit(i32 0)
+ unreachable
+}
diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll
deleted file mode 100644
index 008bd1f6f8c8..000000000000
--- a/test/CodeGen/ARM/vector-load.ll
+++ /dev/null
@@ -1,253 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-
-target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-target triple = "thumbv7s-apple-ios8.0.0"
-
-define <8 x i8> @load_v8i8(<8 x i8>** %ptr) {
-;CHECK-LABEL: load_v8i8:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <8 x i8>** %ptr
- %lA = load <8 x i8>* %A, align 1
- ret <8 x i8> %lA
-}
-
-define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) {
-;CHECK-LABEL: load_v8i8_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i8>** %ptr
- %lA = load <8 x i8>* %A, align 1
- %inc = getelementptr <8 x i8>* %A, i38 1
- store <8 x i8>* %inc, <8 x i8>** %ptr
- ret <8 x i8> %lA
-}
-
-define <4 x i16> @load_v4i16(<4 x i16>** %ptr) {
-;CHECK-LABEL: load_v4i16:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x i16>** %ptr
- %lA = load <4 x i16>* %A, align 1
- ret <4 x i16> %lA
-}
-
-define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) {
-;CHECK-LABEL: load_v4i16_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i16>** %ptr
- %lA = load <4 x i16>* %A, align 1
- %inc = getelementptr <4 x i16>* %A, i34 1
- store <4 x i16>* %inc, <4 x i16>** %ptr
- ret <4 x i16> %lA
-}
-
-define <2 x i32> @load_v2i32(<2 x i32>** %ptr) {
-;CHECK-LABEL: load_v2i32:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x i32>** %ptr
- %lA = load <2 x i32>* %A, align 1
- ret <2 x i32> %lA
-}
-
-define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) {
-;CHECK-LABEL: load_v2i32_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i32>** %ptr
- %lA = load <2 x i32>* %A, align 1
- %inc = getelementptr <2 x i32>* %A, i32 1
- store <2 x i32>* %inc, <2 x i32>** %ptr
- ret <2 x i32> %lA
-}
-
-define <2 x float> @load_v2f32(<2 x float>** %ptr) {
-;CHECK-LABEL: load_v2f32:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x float>** %ptr
- %lA = load <2 x float>* %A, align 1
- ret <2 x float> %lA
-}
-
-define <2 x float> @load_v2f32_update(<2 x float>** %ptr) {
-;CHECK-LABEL: load_v2f32_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x float>** %ptr
- %lA = load <2 x float>* %A, align 1
- %inc = getelementptr <2 x float>* %A, i32 1
- store <2 x float>* %inc, <2 x float>** %ptr
- ret <2 x float> %lA
-}
-
-define <1 x i64> @load_v1i64(<1 x i64>** %ptr) {
-;CHECK-LABEL: load_v1i64:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <1 x i64>** %ptr
- %lA = load <1 x i64>* %A, align 1
- ret <1 x i64> %lA
-}
-
-define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) {
-;CHECK-LABEL: load_v1i64_update:
-;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <1 x i64>** %ptr
- %lA = load <1 x i64>* %A, align 1
- %inc = getelementptr <1 x i64>* %A, i31 1
- store <1 x i64>* %inc, <1 x i64>** %ptr
- ret <1 x i64> %lA
-}
-
-define <16 x i8> @load_v16i8(<16 x i8>** %ptr) {
-;CHECK-LABEL: load_v16i8:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <16 x i8>** %ptr
- %lA = load <16 x i8>* %A, align 1
- ret <16 x i8> %lA
-}
-
-define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) {
-;CHECK-LABEL: load_v16i8_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <16 x i8>** %ptr
- %lA = load <16 x i8>* %A, align 1
- %inc = getelementptr <16 x i8>* %A, i316 1
- store <16 x i8>* %inc, <16 x i8>** %ptr
- ret <16 x i8> %lA
-}
-
-define <8 x i16> @load_v8i16(<8 x i16>** %ptr) {
-;CHECK-LABEL: load_v8i16:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <8 x i16>** %ptr
- %lA = load <8 x i16>* %A, align 1
- ret <8 x i16> %lA
-}
-
-define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) {
-;CHECK-LABEL: load_v8i16_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i16>** %ptr
- %lA = load <8 x i16>* %A, align 1
- %inc = getelementptr <8 x i16>* %A, i38 1
- store <8 x i16>* %inc, <8 x i16>** %ptr
- ret <8 x i16> %lA
-}
-
-define <4 x i32> @load_v4i32(<4 x i32>** %ptr) {
-;CHECK-LABEL: load_v4i32:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x i32>** %ptr
- %lA = load <4 x i32>* %A, align 1
- ret <4 x i32> %lA
-}
-
-define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) {
-;CHECK-LABEL: load_v4i32_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i32>** %ptr
- %lA = load <4 x i32>* %A, align 1
- %inc = getelementptr <4 x i32>* %A, i34 1
- store <4 x i32>* %inc, <4 x i32>** %ptr
- ret <4 x i32> %lA
-}
-
-define <4 x float> @load_v4f32(<4 x float>** %ptr) {
-;CHECK-LABEL: load_v4f32:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x float>** %ptr
- %lA = load <4 x float>* %A, align 1
- ret <4 x float> %lA
-}
-
-define <4 x float> @load_v4f32_update(<4 x float>** %ptr) {
-;CHECK-LABEL: load_v4f32_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x float>** %ptr
- %lA = load <4 x float>* %A, align 1
- %inc = getelementptr <4 x float>* %A, i34 1
- store <4 x float>* %inc, <4 x float>** %ptr
- ret <4 x float> %lA
-}
-
-define <2 x i64> @load_v2i64(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 1
- ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update:
-;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 1
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret <2 x i64> %lA
-}
-
-; Make sure we change the type to match alignment if necessary.
-define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned2:
-;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 2
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned4:
-;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 4
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned8:
-;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 8
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret <2 x i64> %lA
-}
-
-define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) {
-;CHECK-LABEL: load_v2i64_update_aligned16:
-;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
- %A = load <2 x i64>** %ptr
- %lA = load <2 x i64>* %A, align 16
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret <2 x i64> %lA
-}
-
-; Make sure we don't break smaller-than-dreg extloads.
-define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) {
-;CHECK-LABEL: zextload_v8i8tov8i32:
-;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32]
-;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
-;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
- %A = load <4 x i8>** %ptr
- %lA = load <4 x i8>* %A, align 4
- %zlA = zext <4 x i8> %lA to <4 x i32>
- ret <4 x i32> %zlA
-}
-
-define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) {
-;CHECK-LABEL: zextload_v8i8tov8i32_fake_update:
-;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32]
-;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16
-;CHECK: str.w r[[INCREG]], [r0]
-;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}}
-;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}}
- %A = load <4 x i8>** %ptr
- %lA = load <4 x i8>* %A, align 4
- %inc = getelementptr <4 x i8>* %A, i38 4
- store <4 x i8>* %inc, <4 x i8>** %ptr
- %zlA = zext <4 x i8> %lA to <4 x i32>
- ret <4 x i32> %zlA
-}
diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll
deleted file mode 100644
index 9036a31d141d..000000000000
--- a/test/CodeGen/ARM/vector-store.ll
+++ /dev/null
@@ -1,258 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-
-target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
-target triple = "thumbv7s-apple-ios8.0.0"
-
-define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) {
-;CHECK-LABEL: store_v8i8:
-;CHECK: str r1, [r0]
- %A = load <8 x i8>** %ptr
- store <8 x i8> %val, <8 x i8>* %A, align 1
- ret void
-}
-
-define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) {
-;CHECK-LABEL: store_v8i8_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i8>** %ptr
- store <8 x i8> %val, <8 x i8>* %A, align 1
- %inc = getelementptr <8 x i8>* %A, i38 1
- store <8 x i8>* %inc, <8 x i8>** %ptr
- ret void
-}
-
-define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) {
-;CHECK-LABEL: store_v4i16:
-;CHECK: str r1, [r0]
- %A = load <4 x i16>** %ptr
- store <4 x i16> %val, <4 x i16>* %A, align 1
- ret void
-}
-
-define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) {
-;CHECK-LABEL: store_v4i16_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i16>** %ptr
- store <4 x i16> %val, <4 x i16>* %A, align 1
- %inc = getelementptr <4 x i16>* %A, i34 1
- store <4 x i16>* %inc, <4 x i16>** %ptr
- ret void
-}
-
-define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) {
-;CHECK-LABEL: store_v2i32:
-;CHECK: str r1, [r0]
- %A = load <2 x i32>** %ptr
- store <2 x i32> %val, <2 x i32>* %A, align 1
- ret void
-}
-
-define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) {
-;CHECK-LABEL: store_v2i32_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i32>** %ptr
- store <2 x i32> %val, <2 x i32>* %A, align 1
- %inc = getelementptr <2 x i32>* %A, i32 1
- store <2 x i32>* %inc, <2 x i32>** %ptr
- ret void
-}
-
-define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) {
-;CHECK-LABEL: store_v2f32:
-;CHECK: str r1, [r0]
- %A = load <2 x float>** %ptr
- store <2 x float> %val, <2 x float>* %A, align 1
- ret void
-}
-
-define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) {
-;CHECK-LABEL: store_v2f32_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x float>** %ptr
- store <2 x float> %val, <2 x float>* %A, align 1
- %inc = getelementptr <2 x float>* %A, i32 1
- store <2 x float>* %inc, <2 x float>** %ptr
- ret void
-}
-
-define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) {
-;CHECK-LABEL: store_v1i64:
-;CHECK: str r1, [r0]
- %A = load <1 x i64>** %ptr
- store <1 x i64> %val, <1 x i64>* %A, align 1
- ret void
-}
-
-define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) {
-;CHECK-LABEL: store_v1i64_update:
-;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <1 x i64>** %ptr
- store <1 x i64> %val, <1 x i64>* %A, align 1
- %inc = getelementptr <1 x i64>* %A, i31 1
- store <1 x i64>* %inc, <1 x i64>** %ptr
- ret void
-}
-
-define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) {
-;CHECK-LABEL: store_v16i8:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <16 x i8>** %ptr
- store <16 x i8> %val, <16 x i8>* %A, align 1
- ret void
-}
-
-define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) {
-;CHECK-LABEL: store_v16i8_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <16 x i8>** %ptr
- store <16 x i8> %val, <16 x i8>* %A, align 1
- %inc = getelementptr <16 x i8>* %A, i316 1
- store <16 x i8>* %inc, <16 x i8>** %ptr
- ret void
-}
-
-define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) {
-;CHECK-LABEL: store_v8i16:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <8 x i16>** %ptr
- store <8 x i16> %val, <8 x i16>* %A, align 1
- ret void
-}
-
-define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) {
-;CHECK-LABEL: store_v8i16_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <8 x i16>** %ptr
- store <8 x i16> %val, <8 x i16>* %A, align 1
- %inc = getelementptr <8 x i16>* %A, i38 1
- store <8 x i16>* %inc, <8 x i16>** %ptr
- ret void
-}
-
-define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: store_v4i32:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x i32>** %ptr
- store <4 x i32> %val, <4 x i32>* %A, align 1
- ret void
-}
-
-define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: store_v4i32_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x i32>** %ptr
- store <4 x i32> %val, <4 x i32>* %A, align 1
- %inc = getelementptr <4 x i32>* %A, i34 1
- store <4 x i32>* %inc, <4 x i32>** %ptr
- ret void
-}
-
-define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) {
-;CHECK-LABEL: store_v4f32:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <4 x float>** %ptr
- store <4 x float> %val, <4 x float>* %A, align 1
- ret void
-}
-
-define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) {
-;CHECK-LABEL: store_v4f32_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <4 x float>** %ptr
- store <4 x float> %val, <4 x float>* %A, align 1
- %inc = getelementptr <4 x float>* %A, i34 1
- store <4 x float>* %inc, <4 x float>** %ptr
- ret void
-}
-
-define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 1
- ret void
-}
-
-define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update:
-;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 1
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret void
-}
-
-define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned2:
-;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 2
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret void
-}
-
-define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned4:
-;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]!
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 4
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret void
-}
-
-define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned8:
-;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:64]!
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 8
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret void
-}
-
-define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) {
-;CHECK-LABEL: store_v2i64_update_aligned16:
-;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]!
- %A = load <2 x i64>** %ptr
- store <2 x i64> %val, <2 x i64>* %A, align 16
- %inc = getelementptr <2 x i64>* %A, i32 1
- store <2 x i64>* %inc, <2 x i64>** %ptr
- ret void
-}
-
-define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: truncstore_v4i32tov4i8:
-;CHECK: ldr.w r9, [sp]
-;CHECK: vmov {{d[0-9]+}}, r3, r9
-;CHECK: vmov {{d[0-9]+}}, r1, r2
-;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
-;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
-;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32]
- %A = load <4 x i8>** %ptr
- %trunc = trunc <4 x i32> %val to <4 x i8>
- store <4 x i8> %trunc, <4 x i8>* %A, align 4
- ret void
-}
-
-define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) {
-;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update:
-;CHECK: ldr.w r9, [sp]
-;CHECK: vmov {{d[0-9]+}}, r3, r9
-;CHECK: vmov {{d[0-9]+}}, r1, r2
-;CHECK: movs [[IMM16:r[0-9]+]], #16
-;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}}
-;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}}
-;CHECK: ldr r[[PTRREG:[0-9]+]], [r0]
-;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]]
-;CHECK: str r[[PTRREG]], [r0]
- %A = load <4 x i8>** %ptr
- %trunc = trunc <4 x i32> %val to <4 x i8>
- store <4 x i8> %trunc, <4 x i8>* %A, align 4
- %inc = getelementptr <4 x i8>* %A, i38 4
- store <4 x i8>* %inc, <4 x i8>** %ptr
- ret void
-}
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