diff options
Diffstat (limited to 'test/CodeGen/MIR/AMDGPU')
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir | 49 | ||||
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir | 709 | ||||
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/intrinsics.mir | 19 | ||||
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir | 49 | ||||
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/lit.local.cfg | 2 | ||||
| -rw-r--r-- | test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 87 |
6 files changed, 0 insertions, 915 deletions
diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir deleted file mode 100644 index 5da98fb9c2d1..000000000000 --- a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ /dev/null @@ -1,49 +0,0 @@ -# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - %struct.foo = type { float, [5 x i32] } - - @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - - define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { - entry: - %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index - %1 = load float, float addrspace(2)* %0 - store float %1, float addrspace(1)* %out - ret void - } - - attributes #0 = { nounwind } - -... ---- -name: float -liveins: - - { reg: '%sgpr0_sgpr1' } -frameInfo: - maxAlignment: 8 -body: | - bb.0.entry: - liveins: %sgpr0_sgpr1 - - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: [[@LINE+1]]:45: expected the name of the target index - %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec - S_ENDPGM -... diff --git a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir b/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir deleted file mode 100644 index 7cef01c9d12d..000000000000 --- a/test/CodeGen/MIR/AMDGPU/fold-imm-f16-f32.mir +++ /dev/null @@ -1,709 +0,0 @@ -# RUN: llc --mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-fold-operands,si-shrink-instructions %s -o - | FileCheck %s ---- | - define amdgpu_kernel void @add_f32_1.0_one_f16_use() #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f32.add = fadd float %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile float %f32.add, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f32_1.0_multi_f16_use() #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f32.add = fadd float %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile float %f32.add, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f32_1.0_one_f32_use_one_f16_use () #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f32.add = fadd float %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile float %f32.add, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f32_1.0_one_f32_use_multi_f16_use () #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f16.add1 = fadd half %f16.val1, 0xH3C00 - %f32.add = fadd float %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile half %f16.add1, half addrspace(1)* undef - store volatile float %f32.add, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_i32_1_multi_f16_use() #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH0001 - %f16.add1 = fadd half %f16.val1, 0xH0001 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile half %f16.add1,half addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_i32_m2_one_f32_use_multi_f16_use () #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xHFFFE - %f16.add1 = fadd half %f16.val1, 0xHFFFE - %f32.add = fadd float %f32.val, 0xffffffffc0000000 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile half %f16.add1, half addrspace(1)* undef - store volatile float %f32.add, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f16_1.0_multi_f32_use() #0 { - %f32.val0 = load volatile float, float addrspace(1)* undef - %f32.val1 = load volatile float, float addrspace(1)* undef - %f32.val = load volatile float, float addrspace(1)* undef - %f32.add0 = fadd float %f32.val0, 1.0 - %f32.add1 = fadd float %f32.val1, 1.0 - store volatile float %f32.add0, float addrspace(1)* undef - store volatile float %f32.add1, float addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f16_1.0_other_high_bits_multi_f16_use() #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile half, half addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f32.add = fadd half %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile half %f32.add, half addrspace(1)* undef - ret void - } - - define amdgpu_kernel void @add_f16_1.0_other_high_bits_use_f16_f32() #0 { - %f16.val0 = load volatile half, half addrspace(1)* undef - %f16.val1 = load volatile half, half addrspace(1)* undef - %f32.val = load volatile half, half addrspace(1)* undef - %f16.add0 = fadd half %f16.val0, 0xH3C00 - %f32.add = fadd half %f32.val, 1.000000e+00 - store volatile half %f16.add0, half addrspace(1)* undef - store volatile half %f32.add, half addrspace(1)* undef - ret void - } - - attributes #0 = { nounwind } - -... ---- - -# f32 1.0 with a single use should be folded as the low 32-bits of a -# literal constant. - -# CHECK-LABEL: name: add_f32_1.0_one_f16_use -# CHECK: %13 = V_ADD_F16_e32 1065353216, killed %11, implicit %exec - -name: add_f32_1.0_one_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = V_MOV_B32_e32 1065353216, implicit %exec - %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - S_ENDPGM - -... ---- -# Materialized f32 inline immediate should not be folded into the f16 -# operands - -# CHECK-LABEL: name: add_f32_1.0_multi_f16_use -# CHECK: %13 = V_MOV_B32_e32 1065353216, implicit %exec -# CHECK: %14 = V_ADD_F16_e32 %13, killed %11, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 killed %13, killed %12, implicit %exec - - -name: add_f32_1.0_multi_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %13 = V_MOV_B32_e32 1065353216, implicit %exec - %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec - %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# f32 1.0 should be folded into the single f32 use as an inline -# immediate, and folded into the single f16 use as a literal constant - -# CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use -# CHECK: %15 = V_ADD_F16_e32 1065353216, %11, implicit %exec -# CHECK: %16 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec - -name: add_f32_1.0_one_f32_use_one_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } - - { id: 16, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %14 = V_MOV_B32_e32 1065353216, implicit %exec - %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec - %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# f32 1.0 should be folded for the single f32 use as an inline -# constant, and not folded as a multi-use literal for the f16 cases - -# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use -# CHECK: %14 = V_MOV_B32_e32 1065353216, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 %14, %11, implicit %exec -# CHECK: %16 = V_ADD_F16_e32 %14, %12, implicit %exec -# CHECK: %17 = V_ADD_F32_e32 1065353216, killed %13, implicit %exec - -name: add_f32_1.0_one_f32_use_multi_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } - - { id: 16, class: vgpr_32 } - - { id: 17, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %14 = V_MOV_B32_e32 1065353216, implicit %exec - %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec - %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec - %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - S_ENDPGM - -... ---- -# CHECK-LABEL: name: add_i32_1_multi_f16_use -# CHECK: %13 = V_MOV_B32_e32 1, implicit %exec -# CHECK: %14 = V_ADD_F16_e32 1, killed %11, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 1, killed %12, implicit %exec - - -name: add_i32_1_multi_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %13 = V_MOV_B32_e32 1, implicit %exec - %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit %exec - %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use -# CHECK: %14 = V_MOV_B32_e32 -2, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 -2, %11, implicit %exec -# CHECK: %16 = V_ADD_F16_e32 -2, %12, implicit %exec -# CHECK: %17 = V_ADD_F32_e32 -2, killed %13, implicit %exec - -name: add_i32_m2_one_f32_use_multi_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } - - { id: 16, class: vgpr_32 } - - { id: 17, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %14 = V_MOV_B32_e32 -2, implicit %exec - %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit %exec - %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit %exec - %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# f32 1.0 should be folded for the single f32 use as an inline -# constant, and not folded as a multi-use literal for the f16 cases - -# CHECK-LABEL: name: add_f16_1.0_multi_f32_use -# CHECK: %13 = V_MOV_B32_e32 15360, implicit %exec -# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec -# CHECK: %15 = V_ADD_F32_e32 %13, %12, implicit %exec - -name: add_f16_1.0_multi_f32_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %13 = V_MOV_B32_e32 15360, implicit %exec - %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec - %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# The low 16-bits are an inline immediate, but the high bits are junk -# FIXME: Should be able to fold this - -# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use -# CHECK: %13 = V_MOV_B32_e32 80886784, implicit %exec -# CHECK: %14 = V_ADD_F16_e32 %13, %11, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec - -name: add_f16_1.0_other_high_bits_multi_f16_use -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %13 = V_MOV_B32_e32 80886784, implicit %exec - %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit %exec - %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec - BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - S_ENDPGM - -... ---- - -# FIXME: Should fold inline immediate into f16 and literal use into -# f32 instruction. - -# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32 -# CHECK: %13 = V_MOV_B32_e32 305413120, implicit %exec -# CHECK: %14 = V_ADD_F32_e32 %13, %11, implicit %exec -# CHECK: %15 = V_ADD_F16_e32 %13, %12, implicit %exec -name: add_f16_1.0_other_high_bits_use_f16_f32 -alignment: 0 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: sreg_64 } - - { id: 1, class: sreg_32 } - - { id: 2, class: sgpr_32 } - - { id: 3, class: vgpr_32 } - - { id: 4, class: sreg_64 } - - { id: 5, class: sreg_32 } - - { id: 6, class: sreg_64 } - - { id: 7, class: sreg_32 } - - { id: 8, class: sreg_32 } - - { id: 9, class: sreg_32 } - - { id: 10, class: sreg_128 } - - { id: 11, class: vgpr_32 } - - { id: 12, class: vgpr_32 } - - { id: 13, class: vgpr_32 } - - { id: 14, class: vgpr_32 } - - { id: 15, class: vgpr_32 } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 0 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -body: | - bb.0 (%ir-block.0): - %4 = IMPLICIT_DEF - %5 = COPY %4.sub1 - %6 = IMPLICIT_DEF - %7 = COPY %6.sub0 - %8 = S_MOV_B32 61440 - %9 = S_MOV_B32 -1 - %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4 - %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 4 from `float addrspace(1)* undef`) - %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile load 2 from `half addrspace(1)* undef`) - %13 = V_MOV_B32_e32 305413120, implicit %exec - %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit %exec - %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 4 into `float addrspace(1)* undef`) - BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, implicit %exec :: (volatile store 2 into `half addrspace(1)* undef`) - S_ENDPGM - -... diff --git a/test/CodeGen/MIR/AMDGPU/intrinsics.mir b/test/CodeGen/MIR/AMDGPU/intrinsics.mir deleted file mode 100644 index cb6e6190990b..000000000000 --- a/test/CodeGen/MIR/AMDGPU/intrinsics.mir +++ /dev/null @@ -1,19 +0,0 @@ -# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s - ---- | - - define amdgpu_kernel void @use_intrin() { - ret void - } - -... ---- -# Completely invalid code, but it checks that intrinsics round-trip properly. -# CHECK: %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe) -name: use_intrin -registers: - - { id: 0, class: _ } -body: | - bb.0: - %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32) -... diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir deleted file mode 100644 index 8cffc86373a3..000000000000 --- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ /dev/null @@ -1,49 +0,0 @@ -# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - %struct.foo = type { float, [5 x i32] } - - @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - - define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { - entry: - %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index - %1 = load float, float addrspace(2)* %0 - store float %1, float addrspace(1)* %out - ret void - } - - attributes #0 = { nounwind } - -... ---- -name: float -liveins: - - { reg: '%sgpr0_sgpr1' } -frameInfo: - maxAlignment: 8 -body: | - bb.0.entry: - liveins: %sgpr0_sgpr1 - - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start' - %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec - S_ENDPGM -... diff --git a/test/CodeGen/MIR/AMDGPU/lit.local.cfg b/test/CodeGen/MIR/AMDGPU/lit.local.cfg deleted file mode 100644 index 2a665f06be72..000000000000 --- a/test/CodeGen/MIR/AMDGPU/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not 'AMDGPU' in config.root.targets: - config.unsupported = True diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir deleted file mode 100644 index 32669de15ea3..000000000000 --- a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ /dev/null @@ -1,87 +0,0 @@ -# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s -# This test verifies that the MIR parser can parse target index operands. - ---- | - - %struct.foo = type { float, [5 x i32] } - - @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4 - - define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 { - entry: - %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index - %1 = load float, float addrspace(2)* %0 - store float %1, float addrspace(1)* %out - ret void - } - - define amdgpu_kernel void @float2(float addrspace(1)* %out, i32 %index) #0 { - entry: - %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index - %1 = load float, float addrspace(2)* %0 - store float %1, float addrspace(1)* %out - ret void - } - attributes #0 = { nounwind } - -... ---- -name: float -liveins: - - { reg: '%sgpr0_sgpr1' } -frameInfo: - maxAlignment: 8 -body: | - bb.0.entry: - liveins: %sgpr0_sgpr1 - - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc - %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec - S_ENDPGM -... ---- -name: float2 -liveins: - - { reg: '%sgpr0_sgpr1' } -frameInfo: - maxAlignment: 8 -body: | - bb.0.entry: - liveins: %sgpr0_sgpr1 - - %sgpr2_sgpr3 = S_GETPC_B64 - ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc - %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc - %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc - %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11, 0 - %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc - %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc - %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc - %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc - %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc - %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc - %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0, 0 - %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9, 0 - %sgpr7 = S_MOV_B32 61440 - %sgpr6 = S_MOV_B32 -1 - %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec - BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec - S_ENDPGM -... |