diff options
Diffstat (limited to 'test/CodeGen/Mips/Fast-ISel')
32 files changed, 0 insertions, 3019 deletions
diff --git a/test/CodeGen/Mips/Fast-ISel/br1.ll b/test/CodeGen/Mips/Fast-ISel/br1.ll deleted file mode 100644 index 2f2a33042701..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/br1.ll +++ /dev/null @@ -1,34 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@b = global i32 1, align 4 -@i = global i32 0, align 4 -@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 - -; Function Attrs: nounwind -define void @br() #0 { -entry: - %0 = load i32, i32* @b, align 4 - %tobool = icmp eq i32 %0, 0 - br i1 %tobool, label %if.end, label %if.then - -if.then: ; preds = %entry - store i32 6754, i32* @i, align 4 - br label %if.end - -if.end: ; preds = %entry, %if.then - ret void -; FIXME: This instruction is redundant. -; CHECK: xor $[[REG1:[0-9]+]], ${{[0-9]+}}, $zero -; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1 -; CHECK: bgtz $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]] -; CHECK: nop -; CHECK: addiu ${{[0-9]+}}, $zero, 6754 -; CHECK: sw ${{[0-9]+}}, 0(${{[0-9]+}}) -; CHECK: $BB[[BL]]: - -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/Fast-ISel/bswap1.ll b/test/CodeGen/Mips/Fast-ISel/bswap1.ll deleted file mode 100644 index bdbc41ce569c..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/bswap1.ll +++ /dev/null @@ -1,58 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R2 - -@a = global i16 -21829, align 2 -@b = global i32 -1430532899, align 4 -@a1 = common global i16 0, align 2 -@b1 = common global i32 0, align 4 - -declare i16 @llvm.bswap.i16(i16) -declare i32 @llvm.bswap.i32(i32) - -define void @b16() { - ; ALL-LABEL: b16: - - ; ALL: lw $[[A_ADDR:[0-9]+]], %got(a)($[[GOT_ADDR:[0-9]+]]) - ; ALL: lhu $[[A_VAL:[0-9]+]], 0($[[A_ADDR]]) - - ; 32R1: sll $[[TMP1:[0-9]+]], $[[A_VAL]], 8 - ; 32R1: srl $[[TMP2:[0-9]+]], $[[A_VAL]], 8 - ; 32R1: or $[[TMP3:[0-9]+]], $[[TMP1]], $[[TMP2]] - ; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535 - - ; 32R2: wsbh $[[RESULT:[0-9]+]], $[[A_VAL]] - - %1 = load i16, i16* @a, align 2 - %2 = call i16 @llvm.bswap.i16(i16 %1) - store i16 %2, i16* @a1, align 2 - ret void -} - -define void @b32() { - ; ALL-LABEL: b32: - - ; ALL: lw $[[B_ADDR:[0-9]+]], %got(b)($[[GOT_ADDR:[0-9]+]]) - ; ALL: lw $[[B_VAL:[0-9]+]], 0($[[B_ADDR]]) - - ; 32R1: srl $[[TMP1:[0-9]+]], $[[B_VAL]], 8 - ; 32R1: srl $[[TMP2:[0-9]+]], $[[B_VAL]], 24 - ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280 - ; 32R1: or $[[TMP4:[0-9]+]], $[[TMP2]], $[[TMP3]] - ; 32R1: andi $[[TMP5:[0-9]+]], $[[B_VAL]], 65280 - ; 32R1: sll $[[TMP6:[0-9]+]], $[[TMP5]], 8 - ; 32R1: sll $[[TMP7:[0-9]+]], $[[B_VAL]], 24 - ; 32R1: or $[[TMP8:[0-9]+]], $[[TMP4]], $[[TMP6]] - ; 32R1: or $[[RESULT:[0-9]+]], $[[TMP7]], $[[TMP8]] - - ; 32R2: wsbh $[[TMP:[0-9]+]], $[[B_VAL]] - ; 32R2: rotr $[[RESULT:[0-9]+]], $[[TMP]], 16 - - %1 = load i32, i32* @b, align 4 - %2 = call i32 @llvm.bswap.i32(i32 %1) - store i32 %2, i32* @b1, align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll deleted file mode 100644 index 417ee2cd96fa..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ /dev/null @@ -1,538 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ -; RUN: FileCheck %s -check-prefixes=ALL,32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ -; RUN: FileCheck %s -check-prefixes=ALL,32R2 - -declare void @xb(i8) - -define void @cxb() { - ; ALL-LABEL: cxb: - - ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 - - ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24 - ; 32R1: sra $4, $[[T1]], 24 - - ; 32R2: seb $4, $[[T0]] - call void @xb(i8 10) - ret void -} - -declare void @xh(i16) - -define void @cxh() { - ; ALL-LABEL: cxh: - - ; ALL: addiu $[[T0:[0-9]+]], $zero, 10 - - ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16 - ; 32R1: sra $4, $[[T1]], 16 - - ; 32R2: seh $4, $[[T0]] - call void @xh(i16 10) - ret void -} - -declare void @xi(i32) - -define void @cxi() { - ; ALL-LABEL: cxi: - - ; ALL-DAG: addiu $4, $zero, 10 - ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}}) - ; ALL: jalr $25 - call void @xi(i32 10) - ret void -} - -declare void @xbb(i8, i8) - -define void @cxbb() { - ; ALL-LABEL: cxbb: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 - - ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24 - ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24 - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 - ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24 - - ; 32R2-DAG: seb $4, $[[T0]] - ; 32R2-DAG: seb $5, $[[T1]] - call void @xbb(i8 76, i8 101) - ret void -} - -declare void @xhh(i16, i16) - -define void @cxhh() { - ; ALL-LABEL: cxhh: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101 - - ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16 - ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16 - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 - ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16 - - ; 32R2-DAG: seh $4, $[[T0]] - ; 32R2-DAG: seh $5, $[[T1]] - call void @xhh(i16 76, i16 101) - ret void -} - -declare void @xii(i32, i32) - -define void @cxii() { - ; ALL-LABEL: cxii: - - ; ALL-DAG: addiu $4, $zero, 746 - ; ALL-DAG: addiu $5, $zero, 892 - ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}}) - ; ALL: jalr $25 - call void @xii(i32 746, i32 892) - ret void -} - -declare void @xccc(i8, i8, i8) - -define void @cxccc() { - ; ALL-LABEL: cxccc: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 - ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 - - ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24 - ; 32R1-DAG: sra $4, $[[T3]], 24 - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24 - ; 32R1-DAG: sra $5, $[[T4]], 24 - ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24 - ; 32R1-DAG: sra $6, $[[T5]], 24 - - ; 32R2-DAG: seb $4, $[[T0]] - ; 32R2-DAG: seb $5, $[[T1]] - ; 32R2-DAG: seb $6, $[[T2]] - call void @xccc(i8 88, i8 44, i8 11) - ret void -} - -declare void @xhhh(i16, i16, i16) - -define void @cxhhh() { - ; ALL-LABEL: cxhhh: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 - ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 - - ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16 - ; 32R1-DAG: sra $4, $[[T3]], 16 - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16 - ; 32R1-DAG: sra $5, $[[T4]], 16 - ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16 - ; 32R1-DAG: sra $6, $[[T5]], 16 - - ; 32R2-DAG: seh $4, $[[T0]] - ; 32R2-DAG: seh $5, $[[T1]] - ; 32R2-DAG: seh $6, $[[T2]] - call void @xhhh(i16 88, i16 44, i16 11) - ret void -} - -declare void @xiii(i32, i32, i32) - -define void @cxiii() { - ; ALL-LABEL: cxiii: - - ; ALL-DAG: addiu $4, $zero, 88 - ; ALL-DAG: addiu $5, $zero, 44 - ; ALL-DAG: addiu $6, $zero, 11 - ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}}) - ; ALL: jalr $25 - call void @xiii(i32 88, i32 44, i32 11) - ret void -} - -declare void @xcccc(i8, i8, i8, i8) - -define void @cxcccc() { - ; ALL-LABEL: cxcccc: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 - ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 - ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33 - - ; FIXME: We should avoid the unnecessary spill/reload here. - - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24 - ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24 - ; 32R1-DAG: sw $4, 16($sp) - ; 32R1-DAG: move $4, $[[T5]] - ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24 - ; 32R1-DAG: sra $5, $[[T6]], 24 - ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24 - ; 32R1-DAG: sra $6, $[[T7]], 24 - ; 32R1: lw $[[T8:[0-9]+]], 16($sp) - ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24 - ; 32R1: sra $7, $[[T9]], 24 - - ; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]] - ; 32R2-DAG: sw $4, 16($sp) - ; 32R2-DAG: move $4, $[[T4]] - ; 32R2-DAG: seb $5, $[[T1]] - ; 32R2-DAG: seb $6, $[[T2]] - ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp) - ; 32R2: seb $7, $[[T5]] - call void @xcccc(i8 88, i8 44, i8 11, i8 33) - ret void -} - -declare void @xhhhh(i16, i16, i16, i16) - -define void @cxhhhh() { - ; ALL-LABEL: cxhhhh: - - ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88 - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44 - ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11 - ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33 - - ; FIXME: We should avoid the unnecessary spill/reload here. - - ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16 - ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16 - ; 32R1-DAG: sw $4, 16($sp) - ; 32R1-DAG: move $4, $[[T5]] - ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16 - ; 32R1-DAG: sra $5, $[[T6]], 16 - ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16 - ; 32R1-DAG: sra $6, $[[T7]], 16 - ; 32R1: lw $[[T8:[0-9]+]], 16($sp) - ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16 - ; 32R1: sra $7, $[[T9]], 16 - - ; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]] - ; 32R2-DAG: sw $4, 16($sp) - ; 32R2-DAG: move $4, $[[T4]] - ; 32R2-DAG: seh $5, $[[T1]] - ; 32R2-DAG: seh $6, $[[T2]] - ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp) - ; 32R2: seh $7, $[[T5]] - call void @xhhhh(i16 88, i16 44, i16 11, i16 33) - ret void -} - -declare void @xiiii(i32, i32, i32, i32) - -define void @cxiiii() { - ; ALL-LABEL: cxiiii: - - ; ALL-DAG: addiu $4, $zero, 167 - ; ALL-DAG: addiu $5, $zero, 320 - ; ALL-DAG: addiu $6, $zero, 97 - ; ALL-DAG: addiu $7, $zero, 14 - ; ALL-DAG: lw $25, %got(xiiii)(${{[0-9]+}}) - ; ALL: jalr $25 - call void @xiiii(i32 167, i32 320, i32 97, i32 14) - ret void -} - -@c1 = global i8 -45, align 1 -@uc1 = global i8 27, align 1 -@s1 = global i16 -1789, align 2 -@us1 = global i16 1256, align 2 - -define void @cxiiiiconv() { - ; ALL-LABEL: cxiiiiconv: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]]) - ; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]]) - ; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24 - ; 32R1-DAG: sra $4, $[[REG_C1_1]], 24 - ; 32R2-DAG: seb $4, $[[REG_C1]] - ; FIXME: andi is superfulous - ; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) - ; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]]) - ; ALL-DAG: andi $5, $[[REG_UC1]], 255 - ; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) - ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]]) - ; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16 - ; 32R1-DAG: sra $6, $[[REG_S1_1]], 16 - ; 32R2-DAG: seh $6, $[[REG_S1]] - ; FIXME andi is superfulous - ; ALL-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) - ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]]) - ; ALL-DAG: andi $7, $[[REG_US1]], 65535 - ; ALL: jalr $25 - %1 = load i8, i8* @c1, align 1 - %conv = sext i8 %1 to i32 - %2 = load i8, i8* @uc1, align 1 - %conv1 = zext i8 %2 to i32 - %3 = load i16, i16* @s1, align 2 - %conv2 = sext i16 %3 to i32 - %4 = load i16, i16* @us1, align 2 - %conv3 = zext i16 %4 to i32 - call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3) - ret void -} - -declare void @xf(float) - -define void @cxf() { - ; ALL-LABEL: cxf: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL: lui $[[REG_FPCONST_1:[0-9]+]], 17886 - ; ALL: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067 - ; ALL: mtc1 $[[REG_FPCONST]], $f12 - ; ALL: lw $25, %got(xf)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xf(float 0x40BBC85560000000) - ret void -} - -declare void @xff(float, float) - -define void @cxff() { - ; ALL-LABEL: cxff: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314 - ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349 - ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 - ; ALL-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593 - ; ALL-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642 - ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14 - ; ALL-DAG: lw $25, %got(xff)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000) - ret void -} - -declare void @xfi(float, i32) - -define void @cxfi() { - ; ALL-LABEL: cxfi: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540 - ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554 - ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 - ; ALL-DAG: addiu $5, $zero, 102 - ; ALL-DAG: lw $25, %got(xfi)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xfi(float 0x4013906240000000, i32 102) - ret void -} - -declare void @xfii(float, i32, i32) - -define void @cxfii() { - ; ALL-LABEL: cxfii: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142 - ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240 - ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 - ; ALL-DAG: addiu $5, $zero, 9993 - ; ALL-DAG: addiu $6, $zero, 10922 - ; ALL-DAG: lw $25, %got(xfii)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922) - ret void -} - -declare void @xfiii(float, i32, i32, i32) - -define void @cxfiii() { - ; ALL-LABEL: cxfiii: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120 - ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681 - ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12 - ; ALL-DAG: addiu $5, $zero, 3948 - ; ALL-DAG: lui $[[REG_I_1:[0-9]+]], 1 - ; ALL-DAG: ori $6, $[[REG_I_1]], 23475 - ; ALL-DAG: lui $[[REG_I_2:[0-9]+]], 1 - ; ALL-DAG: ori $7, $[[REG_I_2]], 45686 - ; ALL-DAG: lw $25, %got(xfiii)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222) - ret void -} - -declare void @xd(double) - -define void @cxd() { - ; ALL-LABEL: cxd: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514 - ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037 - ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195 - ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439 - ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 - ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 - ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 - ; ALL-DAG: lw $25, %got(xd)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xd(double 5.994560e+02) - ret void -} - -declare void @xdd(double, double) - -define void @cxdd() { - ; ALL-LABEL: cxdd: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531 - ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435 - ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078 - ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186 - ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12 - ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13 - ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 - ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629 - ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873 - ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438 - ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575 - ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f14 - ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f15 - ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14 - ; ALL-DAG: lw $25, %got(xdd)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917) - ret void -} - -declare void @xif(i32, float) - -define void @cxif() { - ; ALL-LABEL: cxif: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: addiu $4, $zero, 345 - ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17374 - ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393 - ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] - ; ALL-DAG: mfc1 $5, $f[[REGF_3]] - ; ALL-DAG: lw $25, %got(xif)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xif(i32 345, float 0x407BCE5A20000000) - ret void -} - -declare void @xiff(i32, float, float) - -define void @cxiff() { - ; ALL-LABEL: cxiff: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: addiu $4, $zero, 12239 - ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526 - ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706 - ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] - ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543 - ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326 - ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] - ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] - ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] - ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000) - ret void -} - -declare void @xifi(i32, float, i32) - -define void @cxifi() { - ; ALL-LABEL: cxifi: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: addiu $4, $zero, 887 - ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 16659 - ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759 - ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] - ; ALL-DAG: mfc1 $5, $f[[REGF_3]] - ; ALL-DAG: addiu $6, $zero, 888 - ; ALL-DAG: lw $25, %got(xifi)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xifi(i32 887, float 0x402277CEE0000000, i32 888) - ret void -} - -declare void @xifif(i32, float, i32, float) - -define void @cxifif() { - ; ALL-LABEL: cxifif: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: lui $[[REGI:[0-9]+]], 1 - ; ALL-DAG: ori $4, $[[REGI]], 2238 - ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527 - ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015 - ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] - ; ALL-DAG: addiu $6, $zero, 9991 - ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802 - ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470 - ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] - ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] - ; ALL-DAG: mfc1 $7, $f[[REGF1_3]] - ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xifif(i32 67774, float 0x408EE0FBE0000000, - i32 9991, float 0x40B15C8CC0000000) - ret void -} - -declare void @xiffi(i32, float, float, i32) - -define void @cxiffi() { - ; ALL-LABEL: cxiffi: - - ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: addiu $4, $zero, 45 - ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307 - ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107 - ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]] - ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529 - ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322 - ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]] - ; ALL-DAG: addiu $7, $zero, 234 - ; ALL-DAG: mfc1 $5, $f[[REGF0_3]] - ; ALL-DAG: mfc1 $6, $f[[REGF1_3]] - ; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xiffi(i32 45, float 0x3FF6666660000000, - float 0x408F333340000000, i32 234) - ret void -} - -declare void @xifii(i32, float, i32, i32) - -define void @cxifii() { - ; ALL-LABEL: cxifii: - - ; ALL-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} - ; ALL-DAG: addiu $4, $zero, 12239 - ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17526 - ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706 - ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] - ; ALL-DAG: mfc1 $5, $f[[REGF_3]] - ; ALL-DAG: lui $[[REGI2:[0-9]+]], 15 - ; ALL-DAG: ori $6, $[[REGI2]], 15837 - ; ALL-DAG: addiu $7, $zero, 1234 - ; ALL-DAG: lw $25, %got(xifii)($[[REG_GP]]) - ; ALL: jalr $25 - call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234) - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll deleted file mode 100644 index b8973efda179..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ /dev/null @@ -1,55 +0,0 @@ -; Targets where we should not enable FastISel. -; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s - -; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s - -; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s - -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+micromips -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s - -; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s - -; Valid targets for FastISel. -; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL -; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel <%s 2>&1 | FileCheck %s -check-prefix=FISEL - -; The CHECK prefix is being used by those targets that do not support FastISel. -; By checking that we don't emit the "FastISel missed terminator..." message, -; we ensure that we do not generate code through FastISel. - -; CHECK-NOT: FastISel missed terminator: ret i64 0 - -; The above CHECK will only be valid as long as we *do* emit the missed -; terminator message for targets that support FastISel. If we add support -; for i64 return values in the future, then the following FISEL check-prefix -; will fail and we will have to come up with a new test. - -; FISEL: FastISel missed terminator: ret i64 0 - -define i64 @foo() { -entry: - ret i64 0 -} diff --git a/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll deleted file mode 100644 index f27791a9241e..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ -; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ -; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s - -@ARR = external global [10 x i32], align 4 - -define void @foo() { -; CHECK-LABEL: foo - -; CHECK-DAG: lw $[[ARR:[0-9]+]], %got(ARR)({{.*}}) -; CHECK-DAG: addiu $[[T0:[0-9]+]], $zero, 12345 -; CHECK: sw $[[T0]], 8($[[ARR]]) - -entry: - store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/div1.ll b/test/CodeGen/Mips/Fast-ISel/div1.ll deleted file mode 100644 index f565af258f26..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/div1.ll +++ /dev/null @@ -1,55 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s - -@sj = global i32 200000, align 4 -@sk = global i32 -47, align 4 -@uj = global i32 200000, align 4 -@uk = global i32 43, align 4 -@si = common global i32 0, align 4 -@ui = common global i32 0, align 4 - -define void @divs() { - ; CHECK-LABEL: divs: - - ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp) - ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp) - ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25 - ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]]) - ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]]) - ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]]) - ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) - ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) - ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK-DAG: teq $[[K]], $zero, 7 - ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] - ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) - %1 = load i32, i32* @sj, align 4 - %2 = load i32, i32* @sk, align 4 - %div = sdiv i32 %1, %2 - store i32 %div, i32* @si, align 4 - ret void -} - -define void @divu() { - ; CHECK-LABEL: divu: - - ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp) - ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp) - ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25 - ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]]) - ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]]) - ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]]) - ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) - ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) - ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK-DAG: teq $[[K]], $zero, 7 - ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] - ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) - %1 = load i32, i32* @uj, align 4 - %2 = load i32, i32* @uk, align 4 - %div = udiv i32 %1, %2 - store i32 %div, i32* @ui, align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/test/CodeGen/Mips/Fast-ISel/double-arg.ll deleted file mode 100644 index eb592189e601..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ -; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s - -; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently -; supports AFGR64 only, which uses paired 32 bit registers. - -define zeroext i1 @f(double %value) { -entry: -; CHECK-LABEL: f: -; CHECK: sdc1 - %value.addr = alloca double, align 8 - store double %value, double* %value.addr, align 8 - ret i1 false -} diff --git a/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll deleted file mode 100644 index 24161ca82382..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ -; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s - -; Test that FastISel aborts instead of trying to lower arguments for soft-float. - -define void @__signbit(double %__x) { -entry: - %__x.addr = alloca double, align 8 - store double %__x, double* %__x.addr, align 8 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll deleted file mode 100644 index c420a0445786..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s -verify-machineinstrs | FileCheck %s - -%struct.x = type { i32 } - -@i = common global i32 0, align 4 - -define i32 @foobar(i32 signext %x) { -entry: -; CHECK-LABEL: foobar: - %retval = alloca i32, align 4 - %x.addr = alloca i32, align 4 - %a = alloca %struct.x, align 4 - %c = alloca %struct.x*, align 4 - store i32 %x, i32* %x.addr, align 4 - %x1 = getelementptr inbounds %struct.x, %struct.x* %a, i32 0, i32 0 - %0 = load i32, i32* %x.addr, align 4 - store i32 %0, i32* %x1, align 4 - store %struct.x* %a, %struct.x** %c, align 4 - %1 = load %struct.x*, %struct.x** %c, align 4 - %x2 = getelementptr inbounds %struct.x, %struct.x* %1, i32 0, i32 0 - %2 = load i32, i32* %x2, align 4 - store i32 %2, i32* @i, align 4 - %3 = load i32, i32* %retval -; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]]) -; CHECK-DAG: addiu $[[A_ADDR:[0-9]+]], $sp, 8 -; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp) -; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp) -; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]]) -; CHECK-DAG: sw $[[A_X]], 0($[[I_ADDR]]) - ret i32 %3 -} diff --git a/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll b/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll deleted file mode 100644 index 0aec8d506f77..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -pass-remarks-missed=isel 2>&1 | FileCheck %s - -; CHECK: FastISel missed call: -; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) - -define internal i32 @bar(i32 signext %a, i32 signext %b) { - %s = and i32 %a, %b - ret i32 %s -} - -define i32 @foo(i32 signext %a, i32 signext %b) { - %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) - ret i32 %call -} diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll deleted file mode 100644 index b27b20c8f719..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ /dev/null @@ -1,254 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: -verify-machineinstrs < %s | FileCheck %s - -@f1 = common global float 0.000000e+00, align 4 -@f2 = common global float 0.000000e+00, align 4 -@b1 = common global i32 0, align 4 -@d1 = common global double 0.000000e+00, align 8 -@d2 = common global double 0.000000e+00, align 8 - -; Function Attrs: nounwind -define void @feq1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp oeq float %0, %1 -; CHECK-LABEL: feq1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @fne1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp une float %0, %1 -; CHECK-LABEL: fne1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @flt1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp olt float %0, %1 -; CHECK-LABEL: flt1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @fgt1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp ogt float %0, %1 -; CHECK-LABEL: fgt1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @fle1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp ole float %0, %1 -; CHECK-LABEL: fle1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @fge1() { -entry: - %0 = load float, float* @f1, align 4 - %1 = load float, float* @f2, align 4 - %cmp = fcmp oge float %0, %1 -; CHECK-LABEL: fge1: -; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) -; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) -; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @deq1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp oeq double %0, %1 -; CHECK-LABEL: deq1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @dne1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp une double %0, %1 -; CHECK-LABEL: dne1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @dlt1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp olt double %0, %1 -; CHECK-LABEL: dlt1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @dgt1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp ogt double %0, %1 -; CHECK-LABEL: dgt1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @dle1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp ole double %0, %1 -; CHECK-LABEL: dle1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @dge1() { -entry: - %0 = load double, double* @d1, align 8 - %1 = load double, double* @d2, align 8 - %cmp = fcmp oge double %0, %1 -; CHECK-LABEL: dge1: -; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) -; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) -; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) -; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 -; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 -; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]] -; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 - ret void -} - - diff --git a/test/CodeGen/Mips/Fast-ISel/fpext.ll b/test/CodeGen/Mips/Fast-ISel/fpext.ll deleted file mode 100644 index d9637af92635..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fpext.ll +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@f = global float 0x40147E6B80000000, align 4 -@d_f = common global double 0.000000e+00, align 8 -@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 - -; Function Attrs: nounwind -define void @dv() #0 { -entry: - %0 = load float, float* @f, align 4 - %conv = fpext float %0 to double -; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}} - store double %conv, double* @d_f, align 8 - ret void -} - - -attributes #1 = { nounwind } diff --git a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll deleted file mode 100644 index 9a9570f21b3a..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - - -@f = global float 0x40D6E83280000000, align 4 -@d = global double 0x4132D68780000000, align 8 -@i_f = common global i32 0, align 4 -@i_d = common global i32 0, align 4 -@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 - -; Function Attrs: nounwind -define void @ifv() { -entry: -; CHECK-LABEL: .ent ifv - %0 = load float, float* @f, align 4 - %conv = fptosi float %0 to i32 -; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}} -; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]] - store i32 %conv, i32* @i_f, align 4 - ret void -} - -; Function Attrs: nounwind -define void @idv() { -entry: -; CHECK-LABEL: .ent idv - %0 = load double, double* @d, align 8 - %conv = fptosi double %0 to i32 -; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}} -; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]] - store i32 %conv, i32* @i_d, align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll deleted file mode 100644 index 61828737aabc..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@d = global double 0x40147E6B74DF0446, align 8 -@f = common global float 0.000000e+00, align 4 -@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 - -; Function Attrs: nounwind -define void @fv() #0 { -entry: - %0 = load double, double* @d, align 8 - %conv = fptrunc double %0 to float -; CHECK: cvt.s.d $f{{[0-9]+}}, $f{{[0-9]+}} - store float %conv, float* @f, align 4 - ret void -} - -attributes #1 = { nounwind } diff --git a/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/test/CodeGen/Mips/Fast-ISel/icmpa.ll deleted file mode 100644 index cc19beafd38d..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/icmpa.ll +++ /dev/null @@ -1,210 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@c = global i32 4, align 4 -@d = global i32 9, align 4 -@uc = global i32 4, align 4 -@ud = global i32 9, align 4 -@b1 = common global i32 0, align 4 - -; Function Attrs: nounwind -define void @eq() { -entry: -; CHECK-LABEL: .ent eq - - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp eq i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] -; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1 -; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @ne() { -entry: -; CHECK-LABEL: .ent ne - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp ne i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] -; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]] -; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @ugt() { -entry: -; CHECK-LABEL: .ent ugt - %0 = load i32, i32* @uc, align 4 - %1 = load i32, i32* @ud, align 4 - %cmp = icmp ugt i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) -; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] -; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 - - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @ult() { -entry: -; CHECK-LABEL: .ent ult - %0 = load i32, i32* @uc, align 4 - %1 = load i32, i32* @ud, align 4 - %cmp = icmp ult i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) -; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] -; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @uge() { -entry: -; CHECK-LABEL: .ent uge - %0 = load i32, i32* @uc, align 4 - %1 = load i32, i32* @ud, align 4 - %cmp = icmp uge i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) -; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] -; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 -; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @ule() { -entry: -; CHECK-LABEL: .ent ule - %0 = load i32, i32* @uc, align 4 - %1 = load i32, i32* @ud, align 4 - %cmp = icmp ule i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) -; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) -; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] -; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 -; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @sgt() { -entry: -; CHECK-LABEL: .ent sgt - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp sgt i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] -; FIXME: This instruction is redundant. The slt can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @slt() { -entry: -; CHECK-LABEL: .ent slt - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp slt i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] -; FIXME: This instruction is redundant. The slt can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} - -; Function Attrs: nounwind -define void @sge() { -entry: -; CHECK-LABEL: .ent sge - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp sge i32 %0, %1 - %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @b1, align 4 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] -; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 -; FIXME: This instruction is redundant. The slt can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - ret void -} - -; Function Attrs: nounwind -define void @sle() { -entry: -; CHECK-LABEL: .ent sle - %0 = load i32, i32* @c, align 4 - %1 = load i32, i32* @d, align 4 - %cmp = icmp sle i32 %0, %1 - %conv = zext i1 %cmp to i32 -; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) -; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) -; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] -; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 -; FIXME: This instruction is redundant. The slt can only produce 0 and 1. -; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 - store i32 %conv, i32* @b1, align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll deleted file mode 100644 index dc7be744ddc4..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ /dev/null @@ -1,85 +0,0 @@ -; ModuleID = 'loadstore2.c' -target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" -target triple = "mips--linux-gnu" - -@c2 = common global i8 0, align 1 -@c1 = common global i8 0, align 1 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@s2 = common global i16 0, align 2 -@s1 = common global i16 0, align 2 -@i2 = common global i32 0, align 4 -@i1 = common global i32 0, align 4 -@f2 = common global float 0.000000e+00, align 4 -@f1 = common global float 0.000000e+00, align 4 -@d2 = common global double 0.000000e+00, align 8 -@d1 = common global double 0.000000e+00, align 8 - -; Function Attrs: nounwind -define void @cfoo() #0 { -entry: - %0 = load i8, i8* @c2, align 1 - store i8 %0, i8* @c1, align 1 -; CHECK-LABEL: cfoo: -; CHECK: lbu $[[REGc:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: sb $[[REGc]], 0(${{[0-9]+}}) - - - ret void -} - -; Function Attrs: nounwind -define void @sfoo() #0 { -entry: - %0 = load i16, i16* @s2, align 2 - store i16 %0, i16* @s1, align 2 -; CHECK-LABEL: sfoo: -; CHECK: lhu $[[REGs:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: sh $[[REGs]], 0(${{[0-9]+}}) - - ret void -} - -; Function Attrs: nounwind -define void @ifoo() #0 { -entry: - %0 = load i32, i32* @i2, align 4 - store i32 %0, i32* @i1, align 4 -; CHECK-LABEL: ifoo: -; CHECK: lw $[[REGi:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: sw $[[REGi]], 0(${{[0-9]+}}) - - ret void -} - -; Function Attrs: nounwind -define void @ffoo() #0 { -entry: - %0 = load float, float* @f2, align 4 - store float %0, float* @f1, align 4 -; CHECK-LABEL: ffoo: -; CHECK: lwc1 $f[[REGf:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: swc1 $f[[REGf]], 0(${{[0-9]+}}) - - - ret void -} - -; Function Attrs: nounwind -define void @dfoo() #0 { -entry: - %0 = load double, double* @d2, align 8 - store double %0, double* @d1, align 8 -; CHECK-LABEL: dfoo: -; CHECK: ldc1 $f[[REGd:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: sdc1 $f[[REGd]], 0(${{[0-9]+}}) -; CHECK: .end dfoo - ret void -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - - diff --git a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll deleted file mode 100644 index 7e52fb40842a..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll +++ /dev/null @@ -1,179 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s -check-prefix=mips32 - -@b2 = global i8 0, align 1 -@b1 = global i8 1, align 1 -@uc1 = global i8 0, align 1 -@uc2 = global i8 -1, align 1 -@sc1 = global i8 -128, align 1 -@sc2 = global i8 127, align 1 -@ss1 = global i16 -32768, align 2 -@ss2 = global i16 32767, align 2 -@us1 = global i16 0, align 2 -@us2 = global i16 -1, align 2 -@ssi = global i16 0, align 2 -@ssj = global i16 0, align 2 -@i = global i32 0, align 4 -@j = global i32 0, align 4 -@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 -@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1 - -; Function Attrs: nounwind -define void @_Z3b_iv() { -entry: -; CHECK-LABEL: .ent _Z3b_iv - %0 = load i8, i8* @b1, align 1 - %tobool = trunc i8 %0 to i1 - %frombool = zext i1 %tobool to i8 - store i8 %frombool, i8* @b2, align 1 - %1 = load i8, i8* @b2, align 1 - %tobool1 = trunc i8 %1 to i1 - %conv = zext i1 %tobool1 to i32 - store i32 %conv, i32* @i, align 4 -; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1 -; CHECK: sb $[[REG2]], 0(${{[0-9]+}}) - - - - ret void -; CHECK: .end _Z3b_iv -} - -; Function Attrs: nounwind -define void @_Z4uc_iv() { -entry: -; CHECK-LABEL: .ent _Z4uc_iv - - %0 = load i8, i8* @uc1, align 1 - %conv = zext i8 %0 to i32 - store i32 %conv, i32* @i, align 4 - %1 = load i8, i8* @uc2, align 1 - %conv1 = zext i8 %1 to i32 -; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 - - store i32 %conv1, i32* @j, align 4 - ret void -; CHECK: .end _Z4uc_iv - -} - -; Function Attrs: nounwind -define void @_Z4sc_iv() { -entry: -; mips32r2-LABEL: .ent _Z4sc_iv -; mips32-LABEL: .ent _Z4sc_iv - - %0 = load i8, i8* @sc1, align 1 - %conv = sext i8 %0 to i32 - store i32 %conv, i32* @i, align 4 - %1 = load i8, i8* @sc2, align 1 - %conv1 = sext i8 %1 to i32 - store i32 %conv1, i32* @j, align 4 -; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32r2: seb ${{[0-9]+}}, $[[REG1]] -; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 -; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 - - ret void -; CHECK: .end _Z4sc_iv -} - -; Function Attrs: nounwind -define void @_Z4us_iv() { -entry: -; CHECK-LABEL: .ent _Z4us_iv - %0 = load i16, i16* @us1, align 2 - %conv = zext i16 %0 to i32 - store i32 %conv, i32* @i, align 4 - %1 = load i16, i16* @us2, align 2 - %conv1 = zext i16 %1 to i32 - store i32 %conv1, i32* @j, align 4 - ret void -; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535 -; CHECK: .end _Z4us_iv -} - -; Function Attrs: nounwind -define void @_Z4ss_iv() { -entry: -; mips32r2-LABEL: .ent _Z4ss_iv -; mips32=LABEL: .ent _Z4ss_iv - - %0 = load i16, i16* @ss1, align 2 - %conv = sext i16 %0 to i32 - store i32 %conv, i32* @i, align 4 - %1 = load i16, i16* @ss2, align 2 - %conv1 = sext i16 %1 to i32 - store i32 %conv1, i32* @j, align 4 -; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32r2: seh ${{[0-9]+}}, $[[REG1]] -; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16 -; mips32: sra ${{[0-9]+}}, $[[REG2]], 16 - - ret void -; CHECK: .end _Z4ss_iv -} - -; Function Attrs: nounwind -define void @_Z4b_ssv() { -entry: -; CHECK-LABEL: .ent _Z4b_ssv - %0 = load i8, i8* @b2, align 1 - %tobool = trunc i8 %0 to i1 - %conv = zext i1 %tobool to i16 - store i16 %conv, i16* @ssi, align 2 - ret void -; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 -; CHECK: .end _Z4b_ssv -} - -; Function Attrs: nounwind -define void @_Z5uc_ssv() { -entry: -; CHECK-LABEL: .ent _Z5uc_ssv - %0 = load i8, i8* @uc1, align 1 - %conv = zext i8 %0 to i16 - store i16 %conv, i16* @ssi, align 2 - %1 = load i8, i8* @uc2, align 1 - %conv1 = zext i8 %1 to i16 -; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 - - store i16 %conv1, i16* @ssj, align 2 - ret void -; CHECK: .end _Z5uc_ssv -} - -; Function Attrs: nounwind -define void @_Z5sc_ssv() { -entry: -; mips32r2-LABEL: .ent _Z5sc_ssv -; mips32-LABEL: .ent _Z5sc_ssv - %0 = load i8, i8* @sc1, align 1 - %conv = sext i8 %0 to i16 - store i16 %conv, i16* @ssi, align 2 - %1 = load i8, i8* @sc2, align 1 - %conv1 = sext i8 %1 to i16 - store i16 %conv1, i16* @ssj, align 2 -; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32r2: seb ${{[0-9]+}}, $[[REG1]] -; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) -; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 -; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 - - ret void -; CHECK: .end _Z5sc_ssv -} - diff --git a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll deleted file mode 100644 index 78077f7642f9..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll +++ /dev/null @@ -1,21 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 -@s = common global i8* null, align 4 - -; Function Attrs: nounwind -define void @foo() #0 { -entry: - store i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4 - ret void -; CHECK: .ent foo -; CHECK: lw $[[REG1:[0-9]+]], %got($.str)(${{[0-9]+}}) -; CHECK: addiu ${{[0-9]+}}, $[[REG1]], %lo($.str) - -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - diff --git a/test/CodeGen/Mips/Fast-ISel/logopm.ll b/test/CodeGen/Mips/Fast-ISel/logopm.ll deleted file mode 100644 index 0519c07682ed..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ /dev/null @@ -1,606 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s - -@ub1 = common global i8 0, align 1 -@ub2 = common global i8 0, align 1 -@ub3 = common global i8 0, align 1 -@uc1 = common global i8 0, align 1 -@uc2 = common global i8 0, align 1 -@uc3 = common global i8 0, align 1 -@us1 = common global i16 0, align 2 -@us2 = common global i16 0, align 2 -@us3 = common global i16 0, align 2 -@ub = common global i8 0, align 1 -@uc = common global i8 0, align 1 -@us = common global i16 0, align 2 -@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 -@ui = common global i32 0, align 4 -@ui1 = common global i32 0, align 4 -@ui2 = common global i32 0, align 4 -@ui3 = common global i32 0, align 4 - -; Function Attrs: noinline nounwind -define void @andUb() #0 { -entry: - %0 = load i8, i8* @ub1, align 1 - %1 = load i8, i8* @ub2, align 1 - %conv0 = trunc i8 %0 to i1 - %conv1 = trunc i8 %1 to i1 - %and0 = and i1 %conv1, %conv0 - %conv3 = zext i1 %and0 to i8 - store i8 %conv3, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUb -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) -; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) - ret void -} - -; Function Attrs: noinline nounwind -define void @andUb0() #0 { -entry: - %0 = load i8, i8* @ub1, align 1, !tbaa !2 - %conv = trunc i8 %0 to i1 - %and = and i1 %conv, 0 - %conv1 = zext i1 %and to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUb0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $zero -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end andUb0 - ret void -} - -; Function Attrs: noinline nounwind -define void @andUb1() #0 { -; clang uses i8 constants for booleans, so we test with an i8 1. -entry: - %x = load i8, i8* @ub1, align 1, !tbaa !2 - %and = and i8 %x, 1 - %conv = trunc i8 %and to i1 - %conv1 = zext i1 %conv to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUb1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: and $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end andUb1 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUb() #0 { -entry: - %0 = load i8, i8* @ub1, align 1 - %1 = load i8, i8* @ub2, align 1 - %conv0 = trunc i8 %0 to i1 - %conv1 = trunc i8 %1 to i1 - %or0 = or i1 %conv1, %conv0 - %conv3 = zext i1 %or0 to i8 - store i8 %conv3, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUb -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) -; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) - ret void -} - -; Function Attrs: noinline nounwind -define void @orUb0() #0 { -entry: - %0 = load i8, i8* @ub1, align 1, !tbaa !2 - %conv = trunc i8 %0 to i1 - %or = or i1 %conv, 0 - %conv1 = zext i1 %or to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUb0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK: andi $[[RES:[0-9]+]], $[[UB1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end orUb0 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUb1() #0 { -entry: - %x = load i8, i8* @ub1, align 1, !tbaa !2 - %or = or i8 %x, 1 - %conv = trunc i8 %or to i1 - %conv1 = zext i1 %conv to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUb1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: or $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end orUb1 - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUb() #0 { -entry: - %0 = load i8, i8* @ub1, align 1 - %1 = load i8, i8* @ub2, align 1 - %conv0 = trunc i8 %0 to i1 - %conv1 = trunc i8 %1 to i1 - %xor0 = xor i1 %conv1, %conv0 - %conv3 = zext i1 %xor0 to i8 - store i8 %conv3, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUb -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB2_ADDR:[0-9]+]], %got(ub2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: lbu $[[UB2:[0-9]+]], 0($[[UB2_ADDR]]) -; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB2]], $[[UB1]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUb0() #0 { -entry: - %0 = load i8, i8* @ub1, align 1, !tbaa !2 - %conv = trunc i8 %0 to i1 - %xor = xor i1 %conv, 0 - %conv1 = zext i1 %xor to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUb0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $zero -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end xorUb0 - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUb1() #0 { -entry: - %x = load i8, i8* @ub1, align 1, !tbaa !2 - %xor = xor i8 1, %x - %conv = trunc i8 %xor to i1 - %conv1 = zext i1 %conv to i8 - store i8 %conv1, i8* @ub, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUb1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UB_ADDR:[0-9]+]], %got(ub)($[[REG_GP]]) -; CHECK-DAG: addiu $[[CONST:[0-9]+]], $zero, 1 -; CHECK-DAG: lw $[[UB1_ADDR:[0-9]+]], %got(ub1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UB1:[0-9]+]], 0($[[UB1_ADDR]]) -; CHECK-DAG: xor $[[RES1:[0-9]+]], $[[UB1]], $[[CONST]] -; CHECK: andi $[[RES:[0-9]+]], $[[RES1]], 1 -; CHECK: sb $[[RES]], 0($[[UB_ADDR]]) -; CHECK: .end xorUb1 - ret void -} - -; Function Attrs: noinline nounwind -define void @andUc() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %1 = load i8, i8* @uc2, align 1, !tbaa !2 - %and3 = and i8 %1, %0 - store i8 %and3, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUc -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) -; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UB1]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) - ret void -} - -; Function Attrs: noinline nounwind -define void @andUc0() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %and = and i8 %0, 67 - store i8 %and, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUc0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_67:[0-9]+]], $zero, 67 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_67]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end andUc0 - ret void -} - -; Function Attrs: noinline nounwind -define void @andUc1() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %and = and i8 %0, 167 - store i8 %and, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent andUc1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_167:[0-9]+]], $zero, 167 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC1]], $[[CONST_167]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end andUc1 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUc() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %1 = load i8, i8* @uc2, align 1, !tbaa !2 - %or3 = or i8 %1, %0 - store i8 %or3, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUc -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) -; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC2]], $[[UC1]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end orUc - ret void -} - -; Function Attrs: noinline nounwind -define void @orUc0() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %or = or i8 %0, 69 - store i8 %or, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUc0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_69:[0-9]+]], $zero, 69 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_69]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end orUc0 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUc1() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %or = or i8 %0, 238 - store i8 %or, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent orUc1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_238:[0-9]+]], $zero, 238 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[UC1]], $[[CONST_238]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end orUc1 - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUc() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %1 = load i8, i8* @uc2, align 1, !tbaa !2 - %xor3 = xor i8 %1, %0 - store i8 %xor3, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUc -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC2_ADDR:[0-9]+]], %got(uc2)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]]) -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC2]], $[[UC1]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end xorUc - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUc0() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %xor = xor i8 %0, 23 - store i8 %xor, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUc0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_23:[0-9]+]], $zero, 23 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_23]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end xorUc0 - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUc1() #0 { -entry: - %0 = load i8, i8* @uc1, align 1, !tbaa !2 - %xor = xor i8 %0, 120 - store i8 %xor, i8* @uc, align 1, !tbaa !2 -; CHECK-LABEL: .ent xorUc1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[UC_ADDR:[0-9]+]], %got(uc)($[[REG_GP]]) -; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) -; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_120:[0-9]+]], $zero, 120 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[UC1]], $[[CONST_120]] -; CHECK: sb $[[RES]], 0($[[UC_ADDR]]) -; CHECK: .end xorUc1 - ret void -} - -; Function Attrs: noinline nounwind -define void @andUs() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %1 = load i16, i16* @us2, align 2, !tbaa !5 - %and3 = and i16 %1, %0 - store i16 %and3, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent andUs -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) -; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[UB1]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end andUs - ret void -} - -; Function Attrs: noinline nounwind -define void @andUs0() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %and = and i16 %0, 4660 - store i16 %and, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent andUs0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_4660:[0-9]+]], $zero, 4660 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_4660]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end andUs0 - ret void -} - -; Function Attrs: noinline nounwind -define void @andUs1() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %and = and i16 %0, 61351 - store i16 %and, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent andUs1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: ori $[[CONST_61351:[0-9]+]], $zero, 61351 -; CHECK-DAG: and $[[RES:[0-9]+]], $[[US1]], $[[CONST_61351]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end andUs1 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUs() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %1 = load i16, i16* @us2, align 2, !tbaa !5 - %or3 = or i16 %1, %0 - store i16 %or3, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent orUs -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) -; CHECK-DAG: or $[[RES:[0-9]+]], $[[US2]], $[[US1]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end orUs - ret void -} - -; Function Attrs: noinline nounwind -define void @orUs0() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %or = or i16 %0, 17666 - store i16 %or, i16* @us, align 2, !tbaa !5 - ret void -} - -; Function Attrs: noinline nounwind -define void @orUs1() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %or = or i16 %0, 60945 - store i16 %or, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent orUs1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: ori $[[CONST_60945:[0-9]+]], $zero, 60945 -; CHECK-DAG: or $[[RES:[0-9]+]], $[[US1]], $[[CONST_60945]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end orUs1 - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUs() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %1 = load i16, i16* @us2, align 2, !tbaa !5 - %xor3 = xor i16 %1, %0 - store i16 %xor3, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent xorUs -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US2]], $[[US1]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end xorUs - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUs0() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %xor = xor i16 %0, 6062 - store i16 %xor, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent xorUs0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: addiu $[[CONST_6062:[0-9]+]], $zero, 6062 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_6062]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end xorUs0 - - ret void -} - -; Function Attrs: noinline nounwind -define void @xorUs1() #0 { -entry: - %0 = load i16, i16* @us1, align 2, !tbaa !5 - %xor = xor i16 %0, 60024 - store i16 %xor, i16* @us, align 2, !tbaa !5 -; CHECK-LABEL: .ent xorUs1 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US_ADDR:[0-9]+]], %got(us)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: ori $[[CONST_60024:[0-9]+]], $zero, 60024 -; CHECK-DAG: xor $[[RES:[0-9]+]], $[[US1]], $[[CONST_60024]] -; CHECK: sh $[[RES]], 0($[[US_ADDR]]) -; CHECK: .end xorUs1 - ret void -} - -attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind } - -!llvm.module.flags = !{!0} -!llvm.ident = !{!1} - -!0 = !{i32 1, !"PIC Level", i32 2} -!1 = !{!"clang version 3.7.0 (trunk)"} -!2 = !{!3, !3, i64 0} -!3 = !{!"omnipotent char", !4, i64 0} -!4 = !{!"Simple C/C++ TBAA"} -!5 = !{!6, !6, i64 0} -!6 = !{!"short", !3, i64 0} diff --git a/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/test/CodeGen/Mips/Fast-ISel/memtest1.ll deleted file mode 100644 index aca6aa569bac..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ /dev/null @@ -1,74 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R2 - -@str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 -@src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4 -@i = global i32 12, align 4 -@dest = common global [50 x i8] zeroinitializer, align 1 - -declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) -declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) -declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) - -define void @cpy(i8* %src, i32 %i) { - ; ALL-LABEL: cpy: - - ; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL-DAG: sw $4, 24($sp) - ; ALL-DAG: move $4, $[[T0]] - ; ALL-DAG: sw $5, 20($sp) - ; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp) - ; ALL-DAG: move $5, $[[T1]] - ; ALL-DAG: lw $6, 20($sp) - ; ALL-DAG: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), - i8* %src, i32 %i, i32 1, i1 false) - ret void -} - -define void @mov(i8* %src, i32 %i) { - ; ALL-LABEL: mov: - - - ; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL-DAG: sw $4, 24($sp) - ; ALL-DAG: move $4, $[[T0]] - ; ALL-DAG: sw $5, 20($sp) - ; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp) - ; ALL-DAG: move $5, $[[T1]] - ; ALL-DAG: lw $6, 20($sp) - ; ALL-DAG: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} - call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), - i8* %src, i32 %i, i32 1, i1 false) - ret void -} - -define void @clear(i32 %i) { - ; ALL-LABEL: clear: - - ; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}}) - ; ALL-DAG: sw $4, 16($sp) - ; ALL-DAG: move $4, $[[T0]] - ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 42 - ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T1]], 24 - ; 32R1-DAG: sra $5, $[[T2]], 24 - ; 32R2-DAG: seb $5, $[[T1]] - ; ALL-DAG: lw $6, 16($sp) - ; ALL-DAG: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}}) - ; ALL: jalr $[[T2]] - ; ALL-NEXT: nop - ; ALL-NOT: {{.*}}$2{{.*}} - call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), - i8 42, i32 %i, i32 1, i1 false) - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/mul1.ll b/test/CodeGen/Mips/Fast-ISel/mul1.ll deleted file mode 100644 index 8713e7ef1d96..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/mul1.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic - -; The test is just to make sure it is able to allocate -; registers for this example. There was an issue with allocating AC0 -; after a mul instruction. - -declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) - -define i32 @foo(i32 %a, i32 %b) { -entry: - %0 = mul i32 %a, %b - %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b) - %2 = extractvalue { i32, i1 } %1, 0 - ret i32 %2 -} diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll deleted file mode 100644 index 617b9bb07dd9..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -; Function Attrs: nounwind -define void @foo() { -entry: - ret void -; CHECK: jr $ra -} diff --git a/test/CodeGen/Mips/Fast-ISel/overflt.ll b/test/CodeGen/Mips/Fast-ISel/overflt.ll deleted file mode 100644 index ed1dc2157355..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/overflt.ll +++ /dev/null @@ -1,64 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@x = common global [128000 x float] zeroinitializer, align 4 -@y = global float* getelementptr inbounds ([128000 x float], [128000 x float]* @x, i32 0, i32 0), align 4 -@result = common global float 0.000000e+00, align 4 -@.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1 - -; Function Attrs: nounwind -define void @foo() { -entry: -; CHECK-LABEL: .ent foo - %0 = load float*, float** @y, align 4 - %arrayidx = getelementptr inbounds float, float* %0, i32 64000 - store float 5.500000e+00, float* %arrayidx, align 4 -; CHECK: lui $[[REG_FPCONST_INT:[0-9]+]], 16560 -; CHECK: mtc1 $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]] -; CHECK: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}}) -; CHECK: lw $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]]) -; CHECK: lui $[[REG_IDX_UPPER:[0-9]+]], 3 -; CHECK: ori $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392 -; CHECK: addu $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]] -; CHECK: swc1 $f[[REG_FPCONST]], 0($[[REG_Y_IDX]]) - ret void -; CHECK-LABEL: .end foo -} - -; Function Attrs: nounwind -define void @goo() { -entry: -; CHECK-LABEL: .ent goo - %0 = load float*, float** @y, align 4 - %arrayidx = getelementptr inbounds float, float* %0, i32 64000 - %1 = load float, float* %arrayidx, align 4 - store float %1, float* @result, align 4 -; CHECK-DAG: lw $[[REG_RESULT:[0-9]+]], %got(result)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}}) -; CHECK-DAG: lw $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]]) -; CHECK-DAG: lui $[[REG_IDX_UPPER:[0-9]+]], 3 -; CHECK-DAG: ori $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392 -; CHECK-DAG: addu $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]] -; CHECK-DAG: lwc1 $f[[Y_IDX:[0-9]+]], 0($[[REG_Y_IDX]]) -; CHECK-DAG: swc1 $f[[Y_IDX]], 0($[[REG_RESULT]]) -; CHECK-LABEL: .end goo - ret void -} - -; -; Original C code for test. -; -;float x[128000]; -;float *y = x; -;float result; - - -;void foo() { -; y[64000] = 5.5; -;} - -;void goo() { -; result = y[64000]; -;} diff --git a/test/CodeGen/Mips/Fast-ISel/rem1.ll b/test/CodeGen/Mips/Fast-ISel/rem1.ll deleted file mode 100644 index c8524a5b81e1..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ /dev/null @@ -1,56 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=3 | FileCheck %s - -@sj = global i32 200, align 4 -@sk = global i32 -47, align 4 -@uj = global i32 200, align 4 -@uk = global i32 43, align 4 -@si = common global i32 0, align 4 -@ui = common global i32 0, align 4 - -define void @rems() { - ; CHECK-LABEL: rems: - - ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp) - ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp) - ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25 - ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(si)($[[GOT]]) - ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(sk)($[[GOT]]) - ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(sj)($[[GOT]]) - ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) - ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) - ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK-DAG: teq $[[K]], $zero, 7 - ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] - ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) - %1 = load i32, i32* @sj, align 4 - %2 = load i32, i32* @sk, align 4 - %rem = srem i32 %1, %2 - store i32 %rem, i32* @si, align 4 - ret void -} - -; Function Attrs: noinline nounwind -define void @remu() { - ; CHECK-LABEL: remu: - - ; CHECK: lui $[[GOT1:[0-9]+]], %hi(_gp_disp) - ; CHECK: addiu $[[GOT2:[0-9]+]], $[[GOT1]], %lo(_gp_disp) - ; CHECK: addu $[[GOT:[0-9]+]], $[[GOT2:[0-9]+]], $25 - ; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(ui)($[[GOT]]) - ; CHECK-DAG: lw $[[K_ADDR:[0-9]+]], %got(uk)($[[GOT]]) - ; CHECK-DAG: lw $[[J_ADDR:[0-9]+]], %got(uj)($[[GOT]]) - ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) - ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) - ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK-DAG: teq $[[K]], $zero, 7 - ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] - ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) - %1 = load i32, i32* @uj, align 4 - %2 = load i32, i32* @uk, align 4 - %rem = urem i32 %1, %2 - store i32 %rem, i32* @ui, align 4 - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/retabi.ll b/test/CodeGen/Mips/Fast-ISel/retabi.ll deleted file mode 100644 index d8d1222d3e3e..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/retabi.ll +++ /dev/null @@ -1,108 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s - -@i = global i32 75, align 4 -@s = global i16 -345, align 2 -@c = global i8 118, align 1 -@f = global float 0x40BE623360000000, align 4 -@d = global double 1.298330e+03, align 8 - -; Function Attrs: nounwind -define i32 @reti() { -entry: -; CHECK-LABEL: reti: - %0 = load i32, i32* @i, align 4 - ret i32 %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_I_ADDR:[0-9]+]], %got(i)($[[REG_GP]]) -; CHECK: lw $2, 0($[[REG_I_ADDR]]) -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define i16 @retus() { -entry: -; CHECK-LABEL: retus: - %0 = load i16, i16* @s, align 2 - ret i16 %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]]) -; CHECK: lhu $2, 0($[[REG_S_ADDR]]) -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define signext i16 @rets() { -entry: -; CHECK-LABEL: rets: - %0 = load i16, i16* @s, align 2 - ret i16 %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]]) -; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]]) -; CHECK: seh $2, $[[REG_S]] -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define i8 @retuc() { -entry: -; CHECK-LABEL: retuc: - %0 = load i8, i8* @c, align 1 - ret i8 %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]]) -; CHECK: lbu $2, 0($[[REG_C_ADDR]]) -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define signext i8 @retc() { -entry: -; CHECK-LABEL: retc: - %0 = load i8, i8* @c, align 1 - ret i8 %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]]) -; CHECK: lbu $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]]) -; CHECK: seb $2, $[[REG_C]] -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define float @retf() { -entry: -; CHECK-LABEL: retf: - %0 = load float, float* @f, align 4 - ret float %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_F_ADDR:[0-9]+]], %got(f)($[[REG_GP]]) -; CHECK: lwc1 $f0, 0($[[REG_F_ADDR]]) -; CHECK: jr $ra -} - -; Function Attrs: nounwind -define double @retd() { -entry: -; CHECK-LABEL: retd: - %0 = load double, double* @d, align 8 - ret double %0 -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK: lw $[[REG_D_ADDR:[0-9]+]], %got(d)($[[REG_GP]]) -; CHECK: ldc1 $f0, 0($[[REG_D_ADDR]]) -; CHECK: jr $ra -} diff --git a/test/CodeGen/Mips/Fast-ISel/sel1.ll b/test/CodeGen/Mips/Fast-ISel/sel1.ll deleted file mode 100644 index b3fc58f293af..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/sel1.ll +++ /dev/null @@ -1,126 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \ -; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s - -define i1 @sel_i1(i1 %j, i1 %k, i1 %l) { -entry: - ; CHECK-LABEL: sel_i1: - - ; FIXME: The following instruction is redundant. - ; CHECK: xor $[[T0:[0-9]+]], $4, $zero - ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK-NEXT: movn $6, $5, $[[T2]] - ; CHECK: move $2, $6 - %cond = icmp ne i1 %j, 0 - %res = select i1 %cond, i1 %k, i1 %l - ret i1 %res -} - -define i8 @sel_i8(i8 %j, i8 %k, i8 %l) { -entry: - ; CHECK-LABEL: sel_i8: - - ; CHECK-DAG: seb $[[T0:[0-9]+]], $4 - ; FIXME: The following 2 instructions are redundant. - ; CHECK-DAG: seb $[[T1:[0-9]+]], $zero - ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 - ; CHECK-NEXT: movn $6, $5, $[[T4]] - ; CHECK: move $2, $6 - %cond = icmp ne i8 %j, 0 - %res = select i1 %cond, i8 %k, i8 %l - ret i8 %res -} - -define i16 @sel_i16(i16 %j, i16 %k, i16 %l) { -entry: - ; CHECK-LABEL: sel_i16: - - ; CHECK-DAG: seh $[[T0:[0-9]+]], $4 - ; FIXME: The following 2 instructions are redundant. - ; CHECK-DAG: seh $[[T1:[0-9]+]], $zero - ; CHECK: xor $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]] - ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1 - ; CHECK-NEXT: movn $6, $5, $[[T4]] - ; CHECK: move $2, $6 - %cond = icmp ne i16 %j, 0 - %res = select i1 %cond, i16 %k, i16 %l - ret i16 %res -} - -define i32 @sel_i32(i32 %j, i32 %k, i32 %l) { -entry: - ; CHECK-LABEL: sel_i32: - - ; FIXME: The following instruction is redundant. - ; CHECK: xor $[[T0:[0-9]+]], $4, $zero - ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK-NEXT: movn $6, $5, $[[T2]] - ; CHECK: move $2, $6 - %cond = icmp ne i32 %j, 0 - %res = select i1 %cond, i32 %k, i32 %l - ret i32 %res -} - -define float @sel_float(i32 %j, float %k, float %l) { -entry: - ; CHECK-LABEL: sel_float: - - ; CHECK-DAG: mtc1 $6, $f0 - ; CHECK-DAG: mtc1 $5, $f1 - ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero - ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK: movn.s $f0, $f1, $[[T2]] - %cond = icmp ne i32 %j, 0 - %res = select i1 %cond, float %k, float %l - ret float %res -} - -define float @sel_float2(float %k, float %l, i32 %j) { -entry: - ; CHECK-LABEL: sel_float2: - - ; CHECK-DAG: xor $[[T0:[0-9]+]], $6, $zero - ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK: movn.s $f14, $f12, $[[T2]] - ; CHECK: mov.s $f0, $f14 - %cond = icmp ne i32 %j, 0 - %res = select i1 %cond, float %k, float %l - ret float %res -} - -define double @sel_double(i32 %j, double %k, double %l) { -entry: - ; CHECK-LABEL: sel_double: - - ; CHECK-DAG: mtc1 $6, $f2 - ; CHECK-DAG: mthc1 $7, $f2 - ; CHECK-DAG: ldc1 $f0, 16($sp) - ; CHECK-DAG: xor $[[T0:[0-9]+]], $4, $zero - ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK: movn.d $f0, $f2, $[[T2]] - %cond = icmp ne i32 %j, 0 - %res = select i1 %cond, double %k, double %l - ret double %res -} - -define double @sel_double2(double %k, double %l, i32 %j) { -entry: - ; CHECK-LABEL: sel_double2: - - ; CHECK-DAG: lw $[[SEL:[0-9]+]], 16($sp) - ; CHECK-DAG: xor $[[T0:[0-9]+]], $[[SEL]], $zero - ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]] - ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1 - ; CHECK: movn.d $f14, $f12, $[[T2]] - ; CHECK: mov.d $f0, $f14 - %cond = icmp ne i32 %j, 0 - %res = select i1 %cond, double %k, double %l - ret double %res -} diff --git a/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/test/CodeGen/Mips/Fast-ISel/shftopm.ll deleted file mode 100644 index 184db73ceab0..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/shftopm.ll +++ /dev/null @@ -1,122 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 \ -; RUN: -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 \ -; RUN: -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s - -@s1 = global i16 -89, align 2 -@s2 = global i16 4, align 2 -@us1 = global i16 -503, align 2 -@us2 = global i16 5, align 2 -@s3 = common global i16 0, align 2 -@us3 = common global i16 0, align 2 - -define void @sll() { -entry: - %0 = load i16, i16* @s1, align 2 - %1 = load i16, i16* @s2, align 2 - %shl = shl i16 %0, %1 - store i16 %shl, i16* @s3, align 2 -; CHECK-LABEL: sll: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) -; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]]) -; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) -; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]]) -; CHECK: sllv $[[RES:[0-9]+]], $[[S1]], $[[S2]] -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) - ret void -} - -define void @slli() { -entry: - %0 = load i16, i16* @s1, align 2 - %shl = shl i16 %0, 5 - store i16 %shl, i16* @s3, align 2 -; CHECK-LABEL: slli: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) -; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) -; CHECK: sll $[[RES:[0-9]+]], $[[S1]], 5 -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) - ret void -} - -define void @srl() { -entry: - %0 = load i16, i16* @us1, align 2 - %1 = load i16, i16* @us2, align 2 - %shr = lshr i16 %0, %1 - store i16 %shr, i16* @us3, align 2 - ret void -; CHECK-LABEL: srl: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) -; CHECK-DAG: lw $[[US2_ADDR:[0-9]+]], %got(us2)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]]) -; CHECK: srlv $[[RES:[0-9]+]], $[[US1]], $[[US2]] -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) -} - -define void @srli() { -entry: - %0 = load i16, i16* @us1, align 2 - %shr = lshr i16 %0, 4 - store i16 %shr, i16* @us3, align 2 -; CHECK-LABEL: srli: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[US3_ADDR:[0-9]+]], %got(us3)($[[REG_GP]]) -; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]]) -; CHECK: srl $[[RES:[0-9]+]], $[[US1]], 4 -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) - ret void -} - -define void @sra() { -entry: - %0 = load i16, i16* @s1, align 2 - %1 = load i16, i16* @s2, align 2 - %shr = ashr i16 %0, %1 - store i16 %shr, i16* @s3, align 2 -; CHECK-LABEL: sra: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) -; CHECK-DAG: lw $[[S2_ADDR:[0-9]+]], %got(s2)($[[REG_GP]]) -; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) -; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]]) -; CHECK: srav $[[RES:[0-9]+]], $[[S1]], $[[S2]] -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) - ret void -} - -define void @srai() { -entry: - %0 = load i16, i16* @s1, align 2 - %shr = ashr i16 %0, 2 - store i16 %shr, i16* @s3, align 2 -; CHECK-LABEL: srai: -; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp) -; CHECK-DAG: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp) -; CHECK-DAG: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25 -; CHECK-DAG: lw $[[S3_ADDR:[0-9]+]], %got(s3)($[[REG_GP]]) -; CHECK-DAG: lw $[[S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) -; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]]) -; CHECK: sra $[[RES:[0-9]+]], $[[S1]], 2 -; CHECK: sh $[[RES]], 0($[[S3_ADDR]]) - ret void -} diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll deleted file mode 100644 index 651fb6ad1f5a..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/shift.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \ -; RUN: | llvm-objdump -d - | FileCheck %s - -; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. - -%struct.s = type { [4 x i8], i32 } - -define i32 @main() nounwind uwtable { -entry: - %foo = alloca %struct.s, align 4 - %0 = bitcast %struct.s* %foo to i32* - %bf.load = load i32, i32* %0, align 4 - %bf.lshr = lshr i32 %bf.load, 2 - %cmp = icmp ne i32 %bf.lshr, 2 - br i1 %cmp, label %if.then, label %if.end - -if.then: - unreachable - -if.end: - ret i32 0 -} - -; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/test/CodeGen/Mips/Fast-ISel/simplestore.ll deleted file mode 100644 index 1379390039a7..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@abcd = external global i32 - -; Function Attrs: nounwind -define void @foo() { -entry: - store i32 12345, i32* @abcd, align 4 -; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345 -; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) - ret void -} - diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll deleted file mode 100644 index 4ee60bf5e61b..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ /dev/null @@ -1,54 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s -check-prefix=mips32 - -@f = common global float 0.000000e+00, align 4 -@de = common global double 0.000000e+00, align 8 - -; Function Attrs: nounwind -define void @f1() #0 { -entry: - store float 0x3FFA76C8C0000000, float* @f, align 4 - ret void -; CHECK: .ent f1 -; CHECK: lui $[[REG1:[0-9]+]], 16339 -; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662 -; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]] -; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}}) -; CHECK: swc1 $f[[REG3]], 0($[[REG4]]) -; CHECK: .end f1 - -} - -; Function Attrs: nounwind -define void @d1() #0 { -entry: - store double 1.234567e+00, double* @de, align 8 -; mip32r2: .ent d1 -; mips32r2: lui $[[REG1a:[0-9]+]], 16371 -; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 -; mips32r2: lui $[[REG1b:[0-9]+]], 21403 -; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 -; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] -; mips32r2: mthc1 $[[REG2a]], $f[[REG3]] -; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}}) -; mips32r2: .end d1 -; mips32: .ent d1 -; mips32: lui $[[REG1a:[0-9]+]], 16371 -; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 -; mips32: lui $[[REG1b:[0-9]+]], 21403 -; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 -; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] -; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}} -; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}}) -; mips32: .end d1 - - ret void -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll deleted file mode 100644 index c4a8e55425b8..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s - -@ijk = external global i32 - -; Function Attrs: nounwind -define void @si2_1() #0 { -entry: - store i32 32767, i32* @ijk, align 4 -; CHECK: .ent si2_1 -; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) - - ret void -} - -; Function Attrs: nounwind -define void @si2_2() #0 { -entry: - store i32 -32768, i32* @ijk, align 4 -; CHECK: .ent si2_2 -; CHECK: lui $[[REG1:[0-9]+]], 65535 -; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768 -; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG2]], 0($[[REG3]]) - ret void -} - -; Function Attrs: nounwind -define void @ui2_1() #0 { -entry: - store i32 65535, i32* @ijk, align 4 -; CHECK: .ent ui2_1 -; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) - ret void -} - -; Function Attrs: nounwind -define void @ui4_1() #0 { -entry: - store i32 983040, i32* @ijk, align 4 -; CHECK: .ent ui4_1 -; CHECK: lui $[[REG1:[0-9]+]], 15 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) - ret void -} - -; Function Attrs: nounwind -define void @ui4_2() #0 { -entry: - store i32 719566, i32* @ijk, align 4 -; CHECK: .ent ui4_2 -; CHECK: lui $[[REG1:[0-9]+]], 10 -; CHECK: ori $[[REG1]], $[[REG1]], 64206 -; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}}) -; CHECK: sw $[[REG1]], 0($[[REG2]]) - ret void -} - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - - diff --git a/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll b/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll deleted file mode 100644 index 421f8ff2dba0..000000000000 --- a/test/CodeGen/Mips/Fast-ISel/stackloadstore.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 -fast-isel -disable-fp-elim -relocation-model=pic < %s - -; Test that negative array access don't crash constant synthesis when fast isel -; generates negative offsets. - -define i16 @test() { - %a = alloca [4 x i16], align 4 - %arrayidx = getelementptr inbounds [4 x i16], [4 x i16]* %a, i32 0, i32 -2 - %b = load i16, i16* %arrayidx, align 2 - ret i16 %b -} - -define void @test2() { - %a = alloca [4 x i16], align 4 - %arrayidx = getelementptr inbounds [4 x i16], [4 x i16]* %a, i32 0, i32 -2 - store i16 2, i16* %arrayidx, align 2 - ret void -} |