diff options
Diffstat (limited to 'test/CodeGen/aarch64-inline-asm.c')
| -rw-r--r-- | test/CodeGen/aarch64-inline-asm.c | 26 |
1 files changed, 23 insertions, 3 deletions
diff --git a/test/CodeGen/aarch64-inline-asm.c b/test/CodeGen/aarch64-inline-asm.c index a1078f1bab83..0889a7157f0b 100644 --- a/test/CodeGen/aarch64-inline-asm.c +++ b/test/CodeGen/aarch64-inline-asm.c @@ -44,9 +44,9 @@ void test_constraints_immed(void) { void test_constraint_S(void) { int *addr; - asm("adrp %0, %A1\n\t" - "add %0, %0, %L1" : "=r"(addr) : "S"(&var)); -// CHECK: call i32* asm "adrp $0, ${1:A}\0A\09add $0, $0, ${1:L}", "=r,S"(i64* @var) + asm("adrp %0, %1\n\t" + "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var)); +// CHECK: call i32* asm "adrp $0, $1\0A\09add $0, $0, :lo12:$1", "=r,S"(i64* @var) } void test_constraint_Q(void) { @@ -54,3 +54,23 @@ void test_constraint_Q(void) { asm("ldxr %0, %1" : "=r"(val) : "Q"(var)); // CHECK: call i32 asm "ldxr $0, $1", "=r,*Q"(i64* @var) } + +void test_gcc_registers(void) { + register unsigned long reg0 asm("r0") = 0; + register unsigned long reg1 asm("r1") = 1; + register unsigned int reg29 asm("r29") = 2; + register unsigned int reg30 asm("r30") = 3; + + // Test remapping register names in register ... asm("rN") statments. + // rN register operands in these two inline assembly lines + // should get renamed to valid AArch64 registers. + asm volatile("hvc #0" : : "r" (reg0), "r" (reg1)); + // CHECK: call void asm sideeffect "hvc #0", "{x0},{x1}" + asm volatile("hvc #0" : : "r" (reg29), "r" (reg30)); + // CHECK: call void asm sideeffect "hvc #0", "{fp},{lr}" + + // rN registers when used without register ... asm("rN") syntax + // should not be remapped. + asm volatile("mov r0, r1\n"); + // CHECK: call void asm sideeffect "mov r0, r1\0A", ""() +} |