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* Move all sources from the llvm project into contrib/llvm-project.Dimitry Andric2019-12-201580-1052600/+0
| | | | | | | | | | | | | This uses the new layout of the upstream repository, which was recently migrated to GitHub, and converted into a "monorepo". That is, most of the earlier separate sub-projects with their own branches and tags were consolidated into one top-level directory, and are now branched and tagged together. Updating the vendor area to match this layout is next. Notes: svn path=/head/; revision=355940
* Merge commit 241cbf201 from llvm git (by Nemanja Ivanovic):Dimitry Andric2019-12-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | [PowerPC] Fix crash in peephole optimization When converting reg+reg shifts to reg+imm rotates, we neglect to consider the CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a rotate with missing operands which causes a crash. Committing this fix without review since it is non-controversial that the list of mnemonics to consider should include the 64-bit aliases for the exact mnemonics. Fixes PR44183. This should fix "Assertion failed: (idx < size()), function operator[], file /usr/src/contrib/llvm/include/llvm/ADT/SmallVector.h, line 153" when building the graphics/mesa-dri port for the PowerPC64 ELFv2 ABI. Reported by: Alfredo Dal'Ava Júnior <alfredo.junior@eldorado.org.br> MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=355397
* Merge commit bf996f761 from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-211-1/+3
| | | | | | | | | | | | | | | | | | [mips] Write `AFL_EXT_OCTEONP` flag to the `.MIPS.abiflags` section Differential Revision: https://reviews.llvm.org/D69851 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354981
* Merge commit 3718102d4 from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-211-2/+3
| | | | | | | | | | | | | | | | | | [mips] Support `octeon+` CPU in the `.set arch=` directive Differential Revision: https://reviews.llvm.org/D69850 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354980
* Merge commit 7bed381ea from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-219-6/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | [mips] Implement Octeon+ `saa` and `saad` instructions `saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849 This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354979
* Merge commit f596f4507 from llvm git (by Sam Elliott):Dimitry Andric2019-11-0710-4/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Add Custom Parser for Atomic Memory Operands Summary: GCC Accepts both (reg) and 0(reg) for atomic instruction memory operands. These instructions do not allow for an offset in their encoding, so in the latter case, the 0 is silently dropped. Due to how we have structured the RISCVAsmParser, the easiest way to add support for parsing this offset is to add a custom AsmOperand and parser. This parser drops all the parens, and just keeps the register. This commit also adds a custom printer for these operands, which matches the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: s.egerton, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65205 llvm-svn: 367553 Merge commit f596f4507 from llvm git (by Sam Elliott): [RISCV] Add FreeBSD targets Reviewers: asb Reviewed By: asb Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste, kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57795 Patch by James Clarke (jrtc27) llvm-svn: 367557 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Some fields do not need relocations even relax is enabled. In debug frame information, some fields, e.g., Length in CIE/FDE and Offset in FDE are attributes to describe the structure of CIE/FDE. They are not related to the relaxed code. However, these attributes are symbol differences. So, in current design, these attributes will be filled as zero and LLVM generates relocations for them. We only need to generate relocations for symbols in executable sections. So, if the symbols are not located in executable sections, we still evaluate their values under relaxation. Differential Revision: https://reviews.llvm.org/D61584 llvm-svn: 366531 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Don't force absolute FK_Data_X fixups to relocs The current behavior of shouldForceRelocation forces relocations for the majority of fixups when relaxation is enabled. This makes sense for fixups which incorporate symbols but is unnecessary for simple data fixups where the fixup target is already resolved to an absolute value. Differential Revision: https://reviews.llvm.org/D63404 Patch by Edward Jones. llvm-svn: 369257 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375 This series of merges will permit riscv64 kernels and riscv64sf worlds to build with clang instead of gcc (but still using the bfd linker). Requested by: jhb Obtained from: https://github.com/freebsd/freebsd/compare/master...bsdjhb:riscv_clang MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354469
* Merge commit 8e34dd941 from llvm git (by Sanjay Patel):Dimitry Andric2019-11-071-3/+5
| | | | | | | | | | | | | | | | | | | [x86] avoid crashing when splitting AVX stores with non-simple type (PR43916) The store splitting transform was assuming a simple type (MVT), but that's not necessarily the case as shown in the test. This should fix 'Assertion failed: (isSimple() && "Expected a SimpleValueType!")' when building the security/openssl111 port targeting a CPU that supports AVX, but not AVX2, such as sandybridge. PR: 241747 MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354429
* Merge commit 97e362607 from llvm git (by Nemanja Ivanovic):Dimitry Andric2019-11-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | [PowerPC] Do not emit HW loop if the body contains calls to lrint/lround These two intrinsics are lowered to calls so should prevent the formation of CTR loops. In a subsequent patch, we will handle all currently known intrinsics and prevent the formation of HW loops if any unknown intrinsics are encountered. Differential revision: https://reviews.llvm.org/D68841 This should fix an "invalid CRT loop" assertion when building the www/node port for powerpc64. Requested by: Alfredo Dal'Ava Júnior <alfredo.junior@eldorado.org.br> MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354339
* Pull in r372186 from upstream llvm trunk (by Eli Friedman):Dimitry Andric2019-10-255-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ARM] VFPv2 only supports 16 D registers. r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 Pull in r372187 from upstream clang trunk (by Eli Friedman): [ARM] Update clang for removal of vfp2d16 and vfp2d16sp Matching fix for https://reviews.llvm.org/D67375 (r372186). Differential Revision: https://reviews.llvm.org/D67467 This should fix clang generating invalid opcodes for floating point operations on armv6. Requested by: mmel MFC after: 3 days Notes: svn path=/head/; revision=354097
* Pull in r372606 from upstream llvm trunk (by Sanjay Patel):Dimitry Andric2019-09-232-5/+6
| | | | | | | | | | | | | | | | | [x86] fix assert with horizontal math + broadcast of vector (PR43402) https://bugs.llvm.org/show_bug.cgi?id=43402 This should fix 'Assertion failed: ((HOp.getValueType() == MVT::v2f64 || HOp.getValueType() == MVT::v4f64) && HOp.getValueType() == VT && "Unexpected type for h-op"), function foldShuffleOfHorizOp, file contrib/llvm/lib/Target/X86/X86ISelLowering.cpp, line 33661' when building the devel/llvm90 port with CPUTYPE=haswell. PR: 240759 Notes: svn path=/projects/clang900-import/; revision=352629
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-191-12/+17
| | | | | | | release 9.0.0 r372316, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=352536
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-075-21/+54
| | | | | | | release_90 branch r371301, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=352010
* Pull in r370426 from upstream llvm trunk (by Fāng-ruì Sòng):Dimitry Andric2019-09-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [PPC32] Emit R_PPC_GOT_TPREL16 instead R_PPC_GOT_TPREL16_LO Unlike ppc64, which has ADDISgotTprelHA+LDgotTprelL pairs, ppc32 just uses LDgotTprelL32, so it does not make lots of sense to use _LO without a paired _HA. Emit R_PPC_GOT_TPREL16 instead R_PPC_GOT_TPREL16_LO to match GCC, and get better linker relocation check. Note, R_PPC_GOT_TPREL16_{HA,LO} don't have good linker support: (a) lld does not support R_PPC_GOT_TPREL16_{HA,LO}. (b) Top of tree ld.bfd does not support R_PPC_GOT_REL16_HA Initial-Exec -> Local-Exec relaxation: // a.o addis 3, 3, tsd_tls@got@tprel@ha lwz 3, tsd_tls@got@tprel@l(3) add 3, 3, tsd_tls@tls // b.o .section .tdata,"awT"; .globl tsd_tls; tsd_tls: // ld/ld-new a.o b.o internal error, aborting at ../../bfd/elf32-ppc.c:7952 in ppc_elf_relocate_section Reviewed By: adalava Differential Revision: https://reviews.llvm.org/D66925 This allows use of LLD for linking 32-bit static binaries on FreeBSD/powerpc. Submitted by: Alfredo Dal'Ava Júnior <alfredo.junior@eldorado.org.br> Notes: svn path=/projects/clang900-import/; revision=352009
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-0211-18/+85
| | | | | | | release_90 branch r370514, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351722
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-0223-227/+536
| | | | | | | release_90 branch r369369, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351708
* Merge llvm trunk r366426, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-08-211585-42135/+96939
| | | | Notes: svn path=/projects/clang900-import/; revision=351344
* powerpc: Transition to Secure-PLT, like most other OSs (Toolchain part)Justin Hibbits2019-06-251-1/+2
| | | | | | | | | | | | | | | | Summary: Toolchain follow-up to r349350. LLVM patches will be submitted upstream for 9.0 as well. The bsd.cpu.mk change is required because GNU ld assumes BSS-PLT if it cannot determine for certain that it needs Secure-PLT, and some binaries do not compile in such a way to make it know to use Secure-PLT. Reviewed By: nwhitehorn, bdragon, pfg Differential Revision: https://reviews.freebsd.org/D20598 Notes: svn path=/head/; revision=349351
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt, libc++,Dimitry Andric2019-06-1227-171/+204
| | | | | | | | | | | libunwind and openmp to the upstream release_80 branch r363030 (effectively, 8.0.1 rc2). The 8.0.1 release should follow this within a week or so. MFC after: 2 weeks Notes: svn path=/head/; revision=349004
* Pull in r360099 from upstream llvm trunk (by Eli Friedman):Dimitry Andric2019-05-081-26/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ARM] Glue register copies to tail calls. This generally follows what other targets do. I don't completely understand why the special case for tail calls existed in the first place; even when the code was committed in r105413, call lowering didn't work in the way described in the comments. Stack protector lowering breaks if the register copies are not glued to a tail call: we have to insert the stack protector check before the tail call, and we choose the location based on the assumption that all physical register dependencies of a tail call are adjacent to the tail call. (See FindSplitPointForStackProtector.) This is sort of fragile, but I don't see any reason to break that assumption. I'm guessing nobody has seen this before just because it's hard to convince the scheduler to actually schedule the code in a way that breaks; even without the glue, the only computation that could actually be scheduled after the register copies is the computation of the call address, and the scheduler usually prefers to schedule that before the copies anyway. Fixes https://bugs.llvm.org/show_bug.cgi?id=41417 Differential Revision: https://reviews.llvm.org/D60427 This should fix several instances of "Bad machine code: Using an undefined physical register", when compiling ports such as multimedia/vlc, audio/alsa-lib and devel/avro-c for armv6, with -fstack-protector-strong. Reported by: jbeich PR: 237074, 237783, 237784 MFC after: 3 days Notes: svn path=/head/; revision=347243
* Pull in r356809 from upstream llvm trunk (by Eli Friedman):Dimitry Andric2019-03-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | [ARM] Don't form "ands" when it isn't scheduled correctly. In r322972/r323136, the iteration here was changed to catch cases at the beginning of a basic block... but we accidentally deleted an important safety check. Restore that check to the way it was. Fixes https://bugs.llvm.org/show_bug.cgi?id=41116 Differential Revision: https://reviews.llvm.org/D59680 This should fix "Assertion failed: (LiveCPSR && "CPSR liveness tracking is wrong!"), function UpdateCPSRUse" errors when building the devel/xwpe port for armv7. PR: 236062, 236568 MFC after: 1 month X-MFC-With: r344779 Notes: svn path=/head/; revision=345449
* Revert r308867 (which was originally committed in the clang390-importDimitry Andric2019-03-121-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | project branch): Work around LLVM PR30879, which is about a bad interaction between X86 Call Frame Optimization on i386 and libunwind, by disallowing the optimization for i386-freebsd12. This should fix some instances of broken exception handling when frame pointers are omitted, in particular some unittests run during the build of editors/libreoffice. This hack will be removed as soon as upstream has implemented a more permanent fix for this problem. And indeed, after r345018 and r345019, which updated LLVM libunwind to the most recent version, the above workaround is no longer needed. The upstream commit which fixed this is: https://llvm.org/viewvc/llvm-project?view=revision&revision=292723 Specifically, 32 bit (i386-freebsd) executables optimized with omitted frame pointers and Call Frame Optimization should now behave correctly when a C++ exception is thrown, and the stack is unwound. Upstream PR: https://llvm.org/bugs/show_bug.cgi?id=30879 PR: 236062 MFC after: 1 month X-MFC-With: r344779 Notes: svn path=/head/; revision=345073
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-03-045-18/+22
| | | | | | | r355313, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344774
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-251-2/+11
| | | | | | | r354799, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344548
* Merge ^/head r344178 through r344512.Dimitry Andric2019-02-251-5/+13
|\ | | | | | | Notes: svn path=/projects/clang800-import/; revision=344513
| * Pull in r354756 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-241-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Fix tls variable lowering issue with large code model Summary: The problem here is the lowering for tls variable. Below is the DAG for the code. SelectionDAG has 11 nodes: t0: ch = EntryToken t8: i64,ch = load<(load 8 from `i8 addrspace(257)* null`, addrspace 257)> t0, Constant:i64<0>, undef:i64 t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10] t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64 t12: i64 = add t8, t11 t4: i32,ch = load<(dereferenceable load 4 from @x)> t0, t12, undef:i64 t6: ch = CopyToReg t0, Register:i32 %0, t4 And when mcmodel is large, below instruction can NOT be folded. t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10] t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64 So "t11: i64,ch = load<(load 8 from got)> t0, t10, undef:i64" is lowered to " Morphed node: t11: i64,ch = MOV64rm<Mem:(load 8 from got)> t10, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i32 $noreg, t0" When llvm start to lower "t10: i64 = X86ISD::WrapperRIP TargetGlobalTLSAddress:i64<i32* @x> 0 [TF=10]", it fails. The patch is to fold the load and X86ISD::WrapperRIP. Fixes PR26906 Patch by LuoYuanke Reviewers: craig.topper, rnk, annita.zhang, wxiao3 Reviewed By: rnk Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58336 This should fix "fatal error: error in backend: Cannot select" messages when compiling <ctype.h> functions using -mcmodel=large. Reported by: phk PR: 233143 MFC after: 3 days Notes: svn path=/head/; revision=344503
| * Pull in r339734 from upstream llvm trunk (by Eli Friedman):Dimitry Andric2019-02-124-5/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly. Intentionally excluding nodes from the DAGCombine worklist is likely to lead to weird optimizations and infinite loops, so it's generally a bad idea. To avoid the infinite loops, fix DAGCombine to use the isDesirableToCommuteWithShift target hook before performing the transforms in question, and implement the target hook in the ARM backend disable the transforms in question. Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a reduced testcase for that bug. But we should have sufficient test coverage for PerformSHLSimplify given that we're not playing weird tricks with the worklist. I can try to bugpoint it if necessary, though.) Differential Revision: https://reviews.llvm.org/D50667 This should fix a possible hang when compiling sys/dev/nxge/if_nxge.c (which exists now only in the stable/11 branch) for arm. Notes: svn path=/head/; revision=344056
| * Pull in r352607 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-084-27/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Also bump __FreeBSD_cc_version, to be able to detect this in our test suite. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206 MFC after: 1 week Notes: svn path=/head/; revision=343916
* | Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-1512-149/+195
| | | | | | | | | | | | | | r354130, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344177
* | Pull in r352607 from upstream llvm trunk (by Craig Topper):Dimitry Andric2019-02-1010-105/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add FPSW as a Def on some FP instructions that were missing it. Pull in r352608 from upstream llvm trunk (by Craig Topper): [X86] Remove a couple places where we unnecessarily pass 0 to the EmitPriority of some FP instruction aliases. NFC As far as I can tell we already won't emit these aliases due to an operand count check in the tablegen code. Removing these because I couldn't make sense of the inconsistency between fadd and fmul from reading the code. I checked the AsmMatcher and AsmWriter files before and after this change and there were no differences. Pull in r353015 from upstream llvm trunk (by Craig Topper): [X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. Pull in r353061 from upstream llvm trunk (by Craig Topper): [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. Pull in r353141 from upstream llvm trunk (by Craig Topper): [X86] Connect the default fpsr and dirflag clobbers in inline assembly to the registers we have defined for them. Summary: We don't currently map these constraints to physical register numbers so they don't make it to the MachineIR representation of inline assembly. This could have problems for proper dependency tracking in the machine schedulers though I don't have a test case that shows that. Reviewers: rnk Reviewed By: rnk Subscribers: eraman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57641 Pull in r353489 from upstream llvm trunk (by Craig Topper): [X86] Add FPCW as a register and start using it as an implicit use on floating point instructions. Summary: FPCW contains the rounding mode control which we manipulate to implement fp to integer conversion by changing the roudning mode, storing the value to the stack, and then changing the rounding mode back. Because we didn't model FPCW and its dependency chain, other instructions could be scheduled into the middle of the sequence. This patch introduces the register and adds it as an implciit def of FLDCW and implicit use of the FP binary arithmetic instructions and store instructions. There are more instructions that need to be updated, but this is a good start. I believe this fixes at least the reduced test case from PR40529. Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor Subscribers: dim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57735 These should fix a problem in clang 7.0 where it would sometimes emit long double floating point instructions in a slightly wrong order, leading to failures in our libm tests. In particular, the cbrt_test test case 'cbrtl_powl' and the trig_test test case 'reduction'. Reported by: lwhsu PR: 234040 Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206 Notes: svn path=/projects/clang800-import/; revision=343955
* | Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-0518-77/+289
| | | | | | | | | | | | | | r353167, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=343806
* | Reduce diff against upstream.Dimitry Andric2019-01-221-1/+0
| | | | | | | | Notes: svn path=/projects/clang800-import/; revision=343321
* | Merge llvm release_80 branch r351543, and resolve conflicts.Dimitry Andric2019-01-2224-71/+320
| | | | | | | | Notes: svn path=/projects/clang800-import/; revision=343313
* | Merge llvm trunk r351319, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-01-20785-36467/+71214
|/ | | | Notes: svn path=/projects/clang800-import/; revision=343210
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-12-0917-142/+306
| | | | | | | | | | r348686 (effectively 7.0.1 rc3), resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=341763
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-11-043-5/+25
| | | | | | | | | | r346007 (effectively 7.0.1 rc2), resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=340125
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-09-1111-39/+63
| | | | | | | | | r341916, resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=338597
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-08-293-7/+29
| | | | | | | | | r340910, resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=338391
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-08-182-9/+21
| | | | | | | | | r339999, resolve conflicts, and bump version numbers. PR: 230240,230355 Notes: svn path=/projects/clang700-import/; revision=338014
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-08-116-81/+160
| | | | | | | r339355, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang700-import/; revision=337645
* Merge llvm release_70 branch r338892, and resolve conflicts.Dimitry Andric2018-08-044-4/+112
| | | | Notes: svn path=/projects/clang700-import/; revision=337309
* Merge llvm trunk r338150 (just before the 7.0.0 branch point), andDimitry Andric2018-08-02146-1024/+2190
| | | | | | | resolve conflicts. Notes: svn path=/projects/clang700-import/; revision=337149
* Merge llvm trunk r338150, and resolve conflicts.Dimitry Andric2018-07-301015-72342/+107678
| | | | Notes: svn path=/projects/clang700-import/; revision=336916
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-06-2935-119/+606
| | | | | | | | | | 6.0.1 release (upstream r335540). Relnotes: yes MFC after: 2 weeks Notes: svn path=/head/; revision=335799
* Pull in r329771 from upstream llvm trunk (by Craig Topper):Dimitry Andric2018-04-231-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | [X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction. Previously the code only knew how to handle setcc to a register. This should fix a crash in the chromium build. This fixes various assertion failures while building ports targeting i386: * www/firefox: isReg() && "This is not a register operand!" * www/iridium, www/qt5-webengine: (I.atEnd() || std::next(I) == def_instr_end()) && "getVRegDef assumes a single definition or no definition" * devel/powerpc64-gcc: FromReg != ToReg && "Cannot replace a reg with itself" Reported by: jbeich PR: 225330, 227686, 227698, 227699 MFC after: 1 week X-MFC-With: r332833 Notes: svn path=/head/; revision=332898
* Recommit r332501, with an additional upstream fix for "Cannot lowerDimitry Andric2018-04-2014-184/+882
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy that lives out of a basic block!" errors on i386. Pull in r325446 from upstream clang trunk (by me): [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Pull in r330264 from upstream llvm trunk (by Chandler Carruth): [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite uses across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332833
* Revert r332501 for now, as it can cause build failures on i386.Dimitry Andric2018-04-1414-839/+183
| | | | | | | | | | Reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=37133>. Reported by: emaste, ci.freebsd.org PR: 225330 Notes: svn path=/head/; revision=332503
* Pull in r325446 from upstream clang trunk (by me):Dimitry Andric2018-04-1414-183/+839
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332501
* Pull in r326882 from upstream llvm trunk (by Sjoerd Meijer):Dimitry Andric2018-03-091-8/+17
| | | | | | | | | | | | | | | | | | | | | | | [ARM] Fix for PR36577 Don't PerformSHLSimplify if the given node is used by a node that also uses a constant because we may get stuck in an infinite combine loop. bugzilla: https://bugs.llvm.org/show_bug.cgi?id=36577 Patch by Sam Parker. Differential Revision: https://reviews.llvm.org/D44097 This fixes a hang when compiling one particular file in java/openjdk8 for armv6 and armv7. Reported by: swills PR: 226388 Notes: svn path=/head/; revision=330686
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-03-042-1/+2
| | | | | | | | | | | | | | | | | 6.0.0 release (upstream r326565). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/6.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=330384
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-254-30/+106
| | | | | | | | | | | 6.0.0 (branches/release_60 r325932). This corresponds to 6.0.0 rc3. MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=329983
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