| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | x86: AMD Zen2: Zenbleed chicken bit mitigation | Olivier Certner | 2023-10-02 | 1 | -0/+3 |
| * | x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" | Olivier Certner | 2023-09-14 | 1 | -2/+3 |
| * | sys: Remove $FreeBSD$: one-line .c pattern | Warner Losh | 2023-08-16 | 1 | -2/+0 |
| * | Revert "Revert "tslog: Annotate some early boot functions"" | Colin Percival | 2023-06-05 | 1 | -0/+4 |
| * | Revert "tslog: Annotate some early boot functions" | Colin Percival | 2023-06-04 | 1 | -4/+0 |
| * | tslog: Annotate some early boot functions | Colin Percival | 2023-06-04 | 1 | -0/+4 |
| * | spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSD | Warner Losh | 2023-05-12 | 1 | -1/+1 |
| * | amd64: properly recalculate mitigations knobs after resume | Konstantin Belousov | 2023-03-18 | 1 | -1/+1 |
| * | amd64: Eliminate write only cpu_fxsr. | Dmitry Chagin | 2023-02-01 | 1 | -1/+1 |
| * | amd64: be more precise when enabling the AlderLake small core PCID workaround | Konstantin Belousov | 2023-01-05 | 1 | -13/+22 |
| * | amd64: for small cores, use (big hammer) INVPCID_CTXGLOB instead of INVLPG | Konstantin Belousov | 2022-12-31 | 1 | -0/+5 |
| * | amd64: identify small cores | Konstantin Belousov | 2022-12-31 | 1 | -0/+9 |
| * | amd64: Reload CPU ext features after resume or cr4 changes | Dmitry Chagin | 2022-06-29 | 1 | -0/+3 |
| * | Limit workaround for errata E400 to appropriate AMD cpus. | Konstantin Belousov | 2020-10-14 | 1 | -0/+17 |
| * | Add constant for the DE_CFG MSR on AMD CPUs. | John Baldwin | 2020-09-11 | 1 | -3/+3 |
| * | cpu_auxmsr: assert caller is preventing CPU migration. | Peter Grehan | 2020-08-24 | 1 | -1/+5 |
| * | Export a routine to provide the TSC_AUX MSR value and use this in vmm. | Peter Grehan | 2020-08-18 | 1 | -1/+10 |
| * | Control for Special Register Buffer Data Sampling mitigation. | Konstantin Belousov | 2020-06-12 | 1 | -0/+1 |
| * | amd64: Add a knob to flush RSB on context switches if machine has SMEP. | Konstantin Belousov | 2020-05-20 | 1 | -1/+13 |
| * | Fix IBRS for machines with IBRS_ALL capability. | Konstantin Belousov | 2020-02-25 | 1 | -1/+1 |
| * | Add support for Hygon Dhyana Family 18h processor. | Konstantin Belousov | 2020-01-21 | 1 | -1/+3 |
| * | Add a constant for the LS config MSR on AMD CPUs. | John Baldwin | 2019-05-23 | 1 | -6/+6 |
| * | Do not call hw_mds_recalculate() from initializecpu(). | Konstantin Belousov | 2019-05-21 | 1 | -1/+0 |
| * | Mitigations for Microarchitectural Data Sampling. | Konstantin Belousov | 2019-05-14 | 1 | -0/+1 |
| * | Provide deterministic (and somewhat useful) value for RDPID result, | Konstantin Belousov | 2019-03-15 | 1 | -0/+4 |
| * | Add kernel support for Intel userspace protection keys feature on | Konstantin Belousov | 2019-02-20 | 1 | -0/+3 |
| * | amd64: flush L1 data cache on syscall return with an error. | Konstantin Belousov | 2018-10-20 | 1 | -0/+1 |
| * | Use SMAP on amd64. | Konstantin Belousov | 2018-07-29 | 1 | -2/+6 |
| * | On amd64, enable workarounds for several Ryzen erratas as described in | Konstantin Belousov | 2018-07-27 | 1 | -0/+24 |
| * | Add Intel Spec Store Bypass Disable control. | Konstantin Belousov | 2018-05-21 | 1 | -0/+1 |
| * | amd64: Protect the kernel text, data, and BSS by setting the RW/NX bits | Jonathan T. Looney | 2018-03-06 | 1 | -1/+1 |
| * | IBRS support, AKA Spectre hardware mitigation. | Konstantin Belousov | 2018-01-31 | 1 | -0/+1 |
| * | sys/amd64: further adoption of SPDX licensing ID tags. | Pedro F. Giffuni | 2017-11-27 | 1 | -0/+2 |
| * | Lower the amd64 shared page, which contains the signal trampoline, | Don Lewis | 2017-08-02 | 1 | -0/+27 |
| * | work around AMD erratum 793 for family 16h, models 00h-0Fh | Andriy Gapon | 2016-09-07 | 1 | -0/+14 |
| * | remove a stray change from r302834 | Andriy Gapon | 2016-07-14 | 1 | -1/+0 |
| * | fix-up for configuration of AMD Family 10h processors borrowed from Linux | Andriy Gapon | 2016-07-14 | 1 | -0/+15 |
| * | fix missing variable in r298736 | Andriy Gapon | 2016-04-28 | 1 | -0/+1 |
| * | ensure that initial local apic id is sane on AMD 10h systems | Andriy Gapon | 2016-04-28 | 1 | -0/+13 |
| * | Move shared variables from {amd64,i386}/initcpu.c to x86/identcpu.c. | John Baldwin | 2015-12-23 | 1 | -31/+0 |
| * | Intel SDM before revision 56 described the CLFLUSH instruction as only | Konstantin Belousov | 2015-10-24 | 1 | -4/+9 |
| * | Update print_INTEL_TLB() by the tag values from the Intel SDM | Konstantin Belousov | 2015-06-06 | 1 | -0/+1 |
| * | For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Paging | Konstantin Belousov | 2015-01-12 | 1 | -0/+1 |
| * | Use an ANSI C definition of initializecpucache() to match the declaration | Brooks Davis | 2013-08-15 | 1 | -1/+1 |
| * | x86: detect mwait capabilities and extensions, when present | Andriy Gapon | 2013-07-28 | 1 | -0/+3 |
| * | Enable the new instructions for reading and writing bases for %fs, | Konstantin Belousov | 2012-11-01 | 1 | -1/+16 |
| * | Provide the reading and display of the Standard Extended Features, | Konstantin Belousov | 2012-11-01 | 1 | -0/+1 |
| * | Do not apply errata 721 workaround when under hypervisor, since | Konstantin Belousov | 2012-08-07 | 1 | -1/+7 |
| * | Work around Erratum 721 for AMD Family 10h and 12h processors. | Jung-uk Kim | 2012-03-30 | 1 | -1/+28 |
| * | Add support for the extended FPU states on amd64, both for native | Konstantin Belousov | 2012-01-21 | 1 | -0/+1 |
