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* Remake support for SMP kernel on UP cpu:Michal Meloun2017-02-021-1/+1
* Split CPU_CORTEXA into CPU_CORTEXA8, for the Cortex-A8, and CPU_CORTEXA_MP,Andrew Turner2016-10-041-1/+1
* Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machineAndrew Turner2016-04-151-3/+3
* Remove FDT specific parts from INTRNG. Change its interface to make itSvatopluk Kraus2016-04-041-1/+1
* Generalize IPI support for ARM intrng and use it for interruptSvatopluk Kraus2016-03-241-5/+8
* Move IPI related parts back to (ARM) machine specific file now, whenSvatopluk Kraus2016-02-271-0/+9
* Break out the shared bits of the arm intrng definitions into sys/intr.h;Adrian Chadd2016-02-101-87/+1
* [intrng] Migrate the intrng code from sys/arm/arm to sys/kern/subr_intr.c.Adrian Chadd2015-12-181-37/+37
* Only decode fdt data which belongs to the GIC controller.Ian Lepore2015-10-181-2/+1
* Import ARM_INTRNG, the "next generation" interrupt architecture for armIan Lepore2015-10-181-3/+100
* Rename arm_init_secondary_ic() -> arm_pic_init_secondary(). The latter isIan Lepore2015-10-181-1/+1
* Remove arm1136 support. We don't have any configs that use it, and I don'tAndrew Turner2015-03-291-1/+1
* Rename gic_init_secondary to arm_init_secondary_ic to help with the mergeAndrew Turner2015-01-111-1/+1
* Pull out the fdt mapping code into intr.c. The arm_intrng branch alsoAndrew Turner2014-12-211-0/+8
* Add a common routine for parsing FDT data describing an ARM GIC interrupt.Ian Lepore2014-09-141-0/+2
* GIC (Cortex A's interrupt controller) supports up to 1020 IRQs.Ruslan Bukin2014-08-311-1/+1
* Eliminate one of the causes of spurious interrupts on armv6. The arm weakIan Lepore2014-05-241-0/+2
* Fix arm build.Andreas Tobler2014-01-061-2/+0
* Add polarity and level support to ARM GICZbigniew Bodek2014-01-011-0/+3
* Add identification and necessary type checks for Krait CPU cores. Krait CPU i...Ganbold Tsagaankhuu2013-12-201-0/+2
* Bump max number of IRQs for Cortex-Ax family to cover Exynos5 requirement.Aleksandr Rybalko2013-06-281-1/+1
* Eliminate the need for an intermediate array of indices into the arrays ofIan Lepore2013-01-191-0/+1
* Replace generic ARM11 option with more specificOleksandr Tymoshenko2012-12-201-1/+1
* Add support for MSI in interrupt controlller.Grzegorz Bernacki2012-09-141-1/+6
* Add support for Armada XP A0.Grzegorz Bernacki2012-09-141-0/+2
* ARM11 might have more then 32 interrupts, e.g. BCM2835: 72 interruptsOleksandr Tymoshenko2012-08-251-0/+2
* Merging projects/armv6, part 1Oleksandr Tymoshenko2012-08-151-0/+5
* trim trailing whitespaceWarner Losh2012-06-131-2/+2
* Pass the previously returned IRQ back to arm_get_next_irq() so thatMarcel Moolenaar2009-06-091-1/+1
* Merge WIP from p4:Sam Leffler2008-12-131-1/+3
* Introduce basic support for Marvell families of system-on-chip ARM devices:Rafal Jaworowski2008-10-131-1/+3
* ARM interrupts improvements.Rafal Jaworowski2008-09-111-1/+1
* Support for the XScale PXA255 SoC as found on the Gumstix Basix and ConnexBenno Rice2008-06-061-0/+3
* On the AT91, we need to write on the EOI register after we handle anOlivier Houchard2008-04-201-0/+1
* The iop34x has 128 interrupts.Olivier Houchard2007-06-161-1/+3
* o break newbus api: add a new argument of type driver_filter_t toPaolo Pisati2007-02-231-2/+2
* - MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32Olivier Houchard2005-06-091-4/+4
* Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores providesOlivier Houchard2005-02-131-0/+4
* Start all license statements with /*-Warner Losh2005-01-051-1/+1
* Add new functions to know which irqs are pending, and to mask and unmaskOlivier Houchard2004-09-231-35/+4
* Import FreeBSD/arm kernel bits.Olivier Houchard2004-05-141-0/+83