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* arm: switch the BUSDMA buffers to normal uncached memoryMichal Meloun2024-11-111-1/+1
| | | | | | | | | | | | The BUSDMA buffer is treated as normal memory during compilation and compiler is free to inline/optimize basic functions (i.e. memset, memcpy) accessing buffers, including when an instruction is generated that performs a word access to unaligned data. We support this, but only if the buffer in question is mapped as normal memory (cached or not), but not to memory mapped as strongly ordered or device type. MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D47485
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
| | | | Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
* spdx: The BSD-2-Clause-FreeBSD identifier is obsolete, drop -FreeBSDWarner Losh2023-05-121-1/+1
| | | | | | | | | The SPDX folks have obsoleted the BSD-2-Clause-FreeBSD identifier. Catch up to that fact and revert to their recommended match of BSD-2-Clause. Discussed with: pfg MFC After: 3 days Sponsored by: Netflix
* Remove the pre-ARMv6 and pre-INTRNG code.Michal Meloun2020-11-291-6/+0
| | | | | | | | ARM has required ARMV6+ and INTRNg for some time now, so remove always false #ifdefs and unconditionally do always true #ifdefs. Notes: svn path=/head/; revision=368141
* sys/arm: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-271-0/+2
| | | | | | | | | | | | | | | Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Notes: svn path=/head/; revision=326258
* Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn'tIan Lepore2016-05-251-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | have ACLE support built in. The ACLE (ARM C Language Extensions) defines a set of standardized symbols which indicate the architecture version and features available. ACLE support is built in to modern compilers (both clang and gcc), but absent from gcc prior to 4.4. ARM (the company) provides the acle-compat.h header file to define the right symbols for older versions of gcc. Basically, acle-compat.h does for arm about the same thing cdefs.h does for freebsd: defines standardized macros that work no matter which compiler you use. If ARM hadn't provided this file we would have ended up with a big #ifdef __arm__ section in cdefs.h with our own compatibility shims. Remove #include <machine/acle-compat.h> from the zillion other places (an ever-growing list) that it appears. Since style(9) requires sys/types.h or sys/param.h early in the include list, and both of those lead to including cdefs.h, only a couple special cases still need to include acle-compat.h directly. Loves it: imp Notes: svn path=/head/; revision=300694
* Include pte-v6.h only where needed.Svatopluk Kraus2016-02-171-2/+0
| | | | Notes: svn path=/head/; revision=295695
* Make VM_MEMATTR_xxx definitions independent on pmap internalsSvatopluk Kraus2016-02-041-5/+5
| | | | | | | | | for __ARM_ARCH >= 6. It's TEX class number now, so it still has some meaning. Notes: svn path=/head/; revision=295257
* ARM: Rename ARM specific VM_MEMATTR_WT memory attribute to standard one.Michal Meloun2016-01-311-2/+2
| | | | Notes: svn path=/head/; revision=295091
* ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, andMichal Meloun2016-01-291-2/+6
| | | | | | | | | dual implementation is showstopper for major cleanup. This patch only removes old code from tree. Cleanups will follow asap. Notes: svn path=/head/; revision=295036
* ARM: create new memory attribute for writethrough cacheable memory.Michal Meloun2015-11-301-7/+9
| | | | | | | | | | | | | | | | - add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor) Notes: svn path=/head/; revision=291492
* New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.Ian Lepore2015-03-261-0/+14
| | | | | | | | | | | | | | | | | This is pretty much a complete rewrite based on the existing i386 code. The patches have been circulating for a couple years and have been looked at by plenty of people, but I'm not putting anybody on the hook as having reviewed this in any formal sense except myself. After this has gotten wider testing from the user community, ARM_NEW_PMAP will become the default and various dregs of the old pmap code will be removed. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz> Notes: svn path=/head/; revision=280712
* Properly implement pmap_[get|set]_memattrOlivier Houchard2012-12-191-1/+2
| | | | | | | Submitted by: Ian Lepore <freebsd@damnhippie.dyndns.org> Notes: svn path=/head/; revision=244414
* Add support to the virtual memory system for configuring machine-Alan Cox2009-07-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib) Notes: svn path=/head/; revision=195649
* Correct the #endif comment.Alan Cox2009-06-261-1/+1
| | | | | | | | Noticed by: jmallett Approved by: re (kib) Notes: svn path=/head/; revision=195060
* This change is the next step in implementing the cache control functionalityAlan Cox2009-06-261-0/+35
required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb Notes: svn path=/head/; revision=195033
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