| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Pull in the NetBSD global offset table handling code. Clang 3.5 creates | Andrew Turner | 2014-12-01 | 1 | -3/+9 |
| * | Update _ENTRY to use _EENTRY to reduce the common code. | Andrew Turner | 2014-11-29 | 1 | -14/+14 |
| * | Revert r274772: it is not valid on MIPS | Ed Maste | 2014-11-25 | 1 | -2/+2 |
| * | The arm PJ4B cpu is armv7 architecture, not v6. | Ian Lepore | 2014-11-24 | 1 | -2/+2 |
| * | Use canonical __PIC__ flag | Ed Maste | 2014-11-21 | 1 | -2/+2 |
| * | opt_global.h is included automatically in the build. No need to | Warner Losh | 2014-11-18 | 1 | -1/+0 |
| * | Add fueword(9) and casueword(9) functions. They are like fuword(9) | Konstantin Belousov | 2014-10-28 | 1 | -0/+4 |
| * | Add an elf not so kgdb detects the kernel as a FreeBSD elf file. The | Andrew Turner | 2014-10-18 | 1 | -0/+12 |
| * | Pass up the error status of minidumpsys() to its callers. | Mark Johnston | 2014-10-08 | 1 | -1/+1 |
| * | Make sure __ARM_ARCH is defined in sysreg.h by including acle-compat.h | Andrew Turner | 2014-09-30 | 1 | -0/+2 |
| * | Add machine/sysreg.h to simplify accessing the system control coprocessor | Andrew Turner | 2014-09-27 | 1 | -0/+230 |
| * | Add a common routine for parsing FDT data describing an ARM GIC interrupt. | Ian Lepore | 2014-09-14 | 1 | -0/+2 |
| * | Rename pmap_kenter_temp to pmap_kenter_temporary to be consistent with the | Andrew Turner | 2014-09-11 | 1 | -1/+1 |
| * | Unify interrupts bit definition and usage. While here remove PSR_C_bit. | Andrew Turner | 2014-09-10 | 3 | -12/+3 |
| * | Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE | Andrew Turner | 2014-09-10 | 2 | -11/+34 |
| * | Rename new to newval in inline asm code, to avoid clashes with C++ new. | Ian Lepore | 2014-09-09 | 1 | -5/+5 |
| * | Do not generate unwind info in asm functions if _STANDALONE is defined. | Ian Lepore | 2014-09-01 | 1 | -1/+1 |
| * | GIC (Cortex A's interrupt controller) supports up to 1020 IRQs. | Ruslan Bukin | 2014-08-31 | 1 | -1/+1 |
| * | The Marvell PJ4B cpu family is armv7, not armv6. | Ian Lepore | 2014-08-31 | 1 | -2/+2 |
| * | Expand the elf brandelf infrastructure to give access to the whole ELF | Warner Losh | 2014-08-18 | 1 | -0/+6 |
| * | When the initarm_* routines were renamed to platform_* and moved to their | Ian Lepore | 2014-08-17 | 1 | -0/+28 |
| * | From https://sourceware.org/ml/newlib/2014/msg00113.html | Warner Losh | 2014-08-14 | 2 | -2/+188 |
| * | Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU. | Ian Lepore | 2014-08-05 | 1 | -0/+3 |
| * | Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.c | Gleb Smirnoff | 2014-08-05 | 2 | -22/+10 |
| * | When arm 64-bit atomic ops are available, define ARM_HAVE_ATOMIC64. Use | Ian Lepore | 2014-08-02 | 1 | -0/+4 |
| * | Use atomic_load/store_64() in the arm implementation of counter(9), and | Ian Lepore | 2014-08-01 | 1 | -6/+7 |
| * | Add 64-bit atomic ops for armv4, only for kernel code, mostly so that we | Ian Lepore | 2014-08-01 | 1 | -0/+69 |
| * | Add 64-bit atomic ops for armv6. The only safe way to access a 64-bit | Ian Lepore | 2014-08-01 | 1 | -0/+248 |
| * | Fix unwind-info errors in our hand-written arm assembler code. | Ian Lepore | 2014-08-01 | 1 | -1/+18 |
| * | Add dl_unwind_find_exidx() for ARM EABI, required for C++ exception | Ian Lepore | 2014-07-19 | 1 | -0/+3 |
| * | Different versions of the ARM processor use different registers. | Michael Tuexen | 2014-06-17 | 1 | -0/+9 |
| * | Delete obsolete and unused PJ4B CPU functions | Zbigniew Bodek | 2014-05-25 | 1 | -9/+0 |
| * | Eliminate one of the causes of spurious interrupts on armv6. The arm weak | Ian Lepore | 2014-05-24 | 1 | -0/+2 |
| * | Remove NetBSD implementation details not relevant to FreeBSD. | Warner Losh | 2014-05-23 | 1 | -8/+0 |
| * | Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to use | Andrew Turner | 2014-05-17 | 1 | -15/+18 |
| * | Fix a comment s/initarm_/platform_/ | Andrew Turner | 2014-05-17 | 1 | -1/+1 |
| * | Add the start of the ARM platform code. This is based on the PowerPC | Andrew Turner | 2014-05-17 | 3 | -34/+142 |
| * | Give suitably-endowed ARMs a register similar to the x86 TSC register. | Mark Murray | 2014-05-14 | 1 | -1/+16 |
| * | Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier(). | Ian Lepore | 2014-05-11 | 1 | -0/+2 |
| * | Make the hardware memory and instruction barrier functions work on armv4 | Ian Lepore | 2014-05-11 | 1 | -3/+3 |
| * | Add a public routine to set the L2 cache ram latencies. This can be | Ian Lepore | 2014-05-06 | 1 | -0/+13 |
| * | Add defines for the bits in the PL310 debug control register. | Ian Lepore | 2014-05-06 | 1 | -0/+2 |
| * | Make this declaration into a proper function prototype. | Ian Lepore | 2014-04-29 | 1 | -1/+1 |
| * | Move duplicated code to print l2 cache config into the common code. | Ian Lepore | 2014-04-27 | 1 | -0/+2 |
| * | There is no difference between IPI_STOP and IPI_STOP_HARD on ARM, so | Ian Lepore | 2014-04-27 | 1 | -1/+1 |
| * | Remove cpu_idcache_wbinv_all() from kdb_cpu_trap(), it's no longer needed. | Ian Lepore | 2014-04-27 | 1 | -2/+0 |
| * | Provide a proper armv7 implementation of icache_sync_all rather than | Ian Lepore | 2014-04-27 | 1 | -0/+1 |
| * | Call cpu_icache_sync_range() rather than sync_all since we know the range | Ian Lepore | 2014-04-26 | 1 | -1/+1 |
| * | Tell VM we now have ARM platforms with physically discontiguous memory. | Ian Lepore | 2014-04-06 | 1 | -2/+2 |
| * | We don't support any ARM systems with an ISA bus and don't need a freelist | Ian Lepore | 2014-04-04 | 1 | -7/+2 |
