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* Add StarFive JH7110's STG clocksJari Sihvola2024-12-161-0/+204
* jh7110: Add sys clocks for STG & PCIEJari Sihvola2024-12-161-0/+7
* Replace calls to bus_generic_attach with bus_attach_childrenJohn Baldwin2024-12-063-3/+6
* riscv: Allwinner D1 clock and reset driverJulien Cassette2024-11-161-0/+1062
* jh7110: Add StarFive JH7110 clock/reset generator driversJari Sihvola2024-05-076-0/+1375
* Revert "jh7110: Add StarFive JH7110 clock/reset generator drivers"Mitchell Horne2024-05-076-1375/+0
* jh7110: Add StarFive JH7110 clock/reset generator driversMitchell Horne2024-05-076-0/+1375
* clkdom_dump(): improve output textMitchell Horne2024-03-081-4/+14
* clk_fixed: quiet by defaultMitchell Horne2024-03-081-2/+7
* clk_fixed: call clkdom_dump() for verbose bootMitchell Horne2024-03-081-3/+4
* syscon: Move syscon code in dev/sysconEmmanuel Vadot2024-01-102-2/+2
* hwreset: Move reset code in dev/hwresetEmmanuel Vadot2024-01-104-4/+4
* clk: Move clock code in dev/clkEmmanuel Vadot2024-01-1068-97/+3443
* clk: Move rockchip driver into the common directoryEmmanuel Vadot2024-01-1021-0/+9084
* clk: Move allwinner driver into the common directoryEmmanuel Vadot2024-01-1030-0/+9861
* xilinx: reset: Remove debug printfsEmmanuel Vadot2023-10-121-2/+0
* arm64: zynqmp: Add clock driverEmmanuel Vadot2023-09-1812-0/+1549
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