| Commit message (Collapse) | Author | Age | Files | Lines |
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Reduce the code executed in the DQRR dequeue loop, and move the
heavy-weight operations to post-dequeue loop.
* Batch if_input() after DQRR dispatch loop completes. Only do the
DQRR_CI_CINH write at the end of the loop, so only up to 16 entries
will be processed.
* Add software LRO per FQ. Each per-CPU RX FQ gets its own LRO tracking
structure.
Since LRO is configured at FQ initialization time, allocate the ifnet
earlier in attach to prevent a panic.
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Apply 6464974 to dTSEC, since it supports the same offload capabilities
as mEMAC.
The DPAA_CSUM_TX_OFFLOAD macro moves from if_memac.c to the shared
dpaa_eth.h since both drivers now reference it.
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Reported by: ziaee@
Fixes: fd8d34ce27 ("dpaa: Migrate from NCSW base to a home-grown driver")
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Enable the FMan hardware parser to take advantage of some offloading.
This enables receive and transmit checksum offloading for both IPv4 and
IPv6.
Additional offloading capabilities the DPAA supports include:
* vlan parsing
* Transmit rate limiting
* IEEE-1588 timestamps
* Soft parsing for custom protocol checking
* Congestion handling
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The NCSW reference base requires tuning for each target, and currently
is configured for FMANv2. This doesn't readily work on FMANv3 devices,
such as the T-series powerpc, or the LS1043 ARM. Since Freescale/NXP
abandoned the NCSW driver a decade ago, it makes sense to abandon it
ourselves as well. This new driver uses a combination of the NCSW
driver and the Linux driver (BSD/GPL dual licensed) as a reference, but
contains no actual code from them.
The DPAA (Data Path Acceleration Architecture) subsystem consists of the
following components:
* BMan -- Buffer Manager. Manages buffer pools of different sizes (one
size per pool, up to 64 pools)
* QMan -- Queue Manager. Manages the interfaces between DPAA-based
components and the CPU(s).
* FMan -- Frame Manager. Responsible for all ethernet-related
processing. Consists itself of the following components:
* Ports -- interfaces to the QMan. An ethernet interface consists of
2 ports.
Ports use "Next-invoked action" (NIA) descriptors to form a pipeline
for processing on receive and transmit.
* Parser -- performs protocol header parsing and validation. Both
hardware and software parsers are available.
* KeyGen -- Key generator, used to start the classification process
(for the Policer), generating FQIDs and other keys based on the
frame input.
* Policer -- performs traffic shaping and classification
* MAC -- SoC specific ethernet MAC (dTSEC, TGEC, mEMAC). Currently
supports dTSEC and mEMAC, along with their MDIO blocks.
Additional components not yet handled:
SEC -- Security engine (crypto)
RE -- RAID engine
RapidIO
DCE -- Decompression/Compression engine, supports ZLIB, DEFLATE, and
GZIP, as well as base64 encoding and decoding.
BMan and QMan are accessed via cache-coherent portals, using ring
buffers as I/O. The intent is for portals to be per-CPU (core/thread)
to reduce locking contention and improve performance. This driver pins
interrupt handlers to the CPU "owning" a given portal, and uses critical
sections to prevent switching while accessing the portal.
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