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* use netmap_rx_irq() / netmap_tx_irq() to handle interrupts inLuigi Rizzo2013-04-301-7/+3
| | | | | | | | | netmap mode, removing the logic from individual drivers. (note: if_lem.c not updated yet due to some other pending modifications) Notes: svn path=/head/; revision=250108
* Disable TX IP header checksum offloading on RL_HWREV_8168CP. ThePyun YongHyeon2013-03-131-2/+4
| | | | | | | | | | controller generates wrong checksummed frame if the IP packet has IP options. Submitted by: Alexander Bluhm via brad@openbsd Notes: svn path=/head/; revision=248227
* Mechanically substitute flags from historic mbuf allocator withGleb Smirnoff2012-12-041-6/+6
| | | | | | | malloc(9) flags in sys/dev. Notes: svn path=/head/; revision=243857
* Remove duplicate const specifiers in many drivers (I hope I got all ofDimitry Andric2012-11-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week Notes: svn path=/head/; revision=242625
* Switch some PCI register reads from using magic numbers to using the namesGavin Atkinson2012-09-191-2/+2
| | | | | | | | | defined in pcireg.h MFC after: 1 week Notes: svn path=/head/; revision=240693
* Align the PCI Express #defines with the style used for the PCI-XGavin Atkinson2012-09-181-4/+4
| | | | | | | | | | | | | | | | | | | | #defines. This also has the advantage that it makes the names more compact, iand also allows us to correct the non-uniform naming of the PCIM_LINK_* defines, making them all consistent amongst themselves. This is a mostly mechanical rename: s/PCIR_EXPRESS_/PCIER_/g s/PCIM_EXP_/PCIEM_/g s/PCIM_LINK_/PCIEM_LINK_/g When this is MFC'd, #defines will be added for the old names to assist out-of-tree drivers. Discussed with: jhb MFC after: 1 week Notes: svn path=/head/; revision=240680
* Use array notation for consistency.Ed Maste2012-08-131-2/+2
| | | | Notes: svn path=/head/; revision=239234
* Fix size of the bcopy when extracting ethernet addressKevin Lo2012-06-251-1/+1
| | | | | | | Obtained from: DragonFly Notes: svn path=/head/; revision=237547
* Make sure we don't dereference a null pointerKevin Lo2012-05-111-4/+5
| | | | Notes: svn path=/head/; revision=235262
* Do not toggle IFCAP_TSO4 if we would also do TSO6. Given the driver doesBjoern A. Zeeb2012-04-241-1/+1
| | | | | | | | | | | not currently announce/support TSO6 that cannot happen. Clean it up anyway for consistency. Reviewed by: yongari MFC after: 1 week Notes: svn path=/head/; revision=234643
* Prefer RL_GMEDIASTAT register to RGEPHY_MII_SSR register toPyun YongHyeon2012-02-281-13/+13
| | | | | | | | | | | | | | | | | | | | | | | extract a link status of PHY when parent driver is re(4). RGEPHY_MII_SSR register does not seem to report correct PHY status on some integrated PHYs used with re(4). Unfortunately, RealTek PHYs have no additional information to differentiate integrated PHYs from external ones so relying on PHY model number is not enough to know that. However, it seems RGEPHY_MII_SSR register exists for external RealTek PHYs so checking parent driver would be good indication to know which PHY was used. In other words, for non-re(4) controllers, the PHY is external one and its revision number is greater than or equal to 2. This change fixes intermittent link UP/DOWN messages reported on RTL8169 controller. Also, mii_attach(9) is tried after setting interface name since rgephy(4) have to know parent driver name. PR: kern/165509 Notes: svn path=/head/; revision=232246
* A bunch of netmap fixes:Luigi Rizzo2012-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USERSPACE: 1. add support for devices with different number of rx and tx queues; 2. add better support for zero-copy operation, adding an extra field to the netmap ring to indicate how many buffers we have already processed but not yet released (with help from Eddie Kohler); 3. The two changes above unfortunately require an API change, so while at it add a version field and some spares to the ioctl() argument to help detect mismatches. 4. update the manual page for the two changes above; 5. update sample applications in tools/tools/netmap KERNEL: 1. simplify the internal structures moving the global wait queues to the 'struct netmap_adapter'; 2. simplify the functions that map kring<->nic ring indexes 3. normalize device-specific code, helps mainteinance; 4. start exploring the impact of micro-optimizations (prefetch etc.) in the ixgbe driver. Use 'legacy' descriptors on the tx ring and prefetch slots gives about 20% speedup at 900 MHz. Another 7-10% would come from removing the explict calls to bus_dmamap* in the core (they are effectively NOPs in this case, but it takes expensive load of the per-buffer dma maps to figure out that they are all NULL. Rx performance not investigated. I am postponing the MFC so i can import a few more improvements before merging. Notes: svn path=/head/; revision=232238
* Use correct Config registers for RTL8139 family. Unlike RTL8168 andPyun YongHyeon2012-02-251-26/+43
| | | | | | | | | | | | | | | | RTL810x family , RTL8139 has different register map for Config registers. While here, follow the lead of re(4) in WOL configuration. - Disable WOL_UCAST and WOL_MCAST capabilities by default. - Config5 register write does not need to unlock EEPROM access on RTL8139 family but unlocking EEPROM access does not affect its operation and make it consistent with re(4). Reported by: Matt Renzelmann mjr <> cs dot wisc dot edu Notes: svn path=/head/; revision=232145
* For RTL8168/8111D controller, make sure to wake PHY from power downPyun YongHyeon2012-02-141-1/+6
| | | | | | | mode. Otherwise, PHY access times out under certain conditions. Notes: svn path=/head/; revision=231622
* Fix a logic error which resulted in putting PHY into sleep when WOLPyun YongHyeon2012-01-191-1/+1
| | | | | | | | is active. If WOL is active driver should not put PHY into sleep. This change makes WOL work on RTL8168E. Notes: svn path=/head/; revision=230336
* Free allocated jumbo buffers when controller is stopped.Pyun YongHyeon2012-01-171-2/+14
| | | | Notes: svn path=/head/; revision=230276
* Use a RX DMA tag to free loaded RX DMA maps.Pyun YongHyeon2012-01-171-1/+1
| | | | | | | Previously it used a TX DMA tag. Notes: svn path=/head/; revision=230275
* add netmap support for "em", "lem", "igb" and "re".Luigi Rizzo2011-12-051-0/+43
| | | | | | | | | | | | | | | | | On my hardware, "em" in netmap mode does about 1.388 Mpps on one card (on an Asus motherboard), and 1.1 Mpps on another card (PCIe bus). Both seem to be NIC-limited, because i have the same rate even with the CPU running at 150 MHz. On the "re" driver the tx throughput is around 420-450 Kpps on various (8111C and the like) chipsets. On the Rx side performance seems much better, and i can receive the full load generated by the "em" cards. "igb" is untested as i don't have the hardware. Notes: svn path=/head/; revision=228281
* To save more power, switch to 10/100Mbps link when controller isPyun YongHyeon2011-11-231-4/+76
| | | | | | | | | | | put into suspend/shutdown. Old PCI controllers performed that operation in firmware but for RTL8111C or newer controllers, it's responsibility of driver. It's not clear whether the firmware of RTL8111B still downgrades its speed to 10/100Mbps so leave it as it was. Notes: svn path=/head/; revision=227916
* Make sure to stop TX MAC before freeing queued TX frames.Pyun YongHyeon2011-11-231-5/+37
| | | | | | | | | For RTL8111DP, check if the TX MAC is active by reading RL_GTXSTART register. For RTL8402/8168E-VL/8168F/8411, wait until TX queue is empty. Notes: svn path=/head/; revision=227914
* Disable accepting frames in re_stop() to put RX MAC into idle state.Pyun YongHyeon2011-11-231-3/+15
| | | | | | | | | | | | | | | | | | | | | Because there is no reliable way to know whether RX MAC is in stopped state, rejecting all frames would be the only way to minimize possible races. Otherwise it's possible to receive frames while stop command execution is in progress and controller can DMA the frame to freed RX buffer during that period. This was observed on recent PCIe controllers(i.e. RTL8111F). While this change may not be required on old controllers it wouldn't make negative effects on old controllers. One side effect of this change is disabling receive so driver reprograms RL_RXCFG to receive WOL frames when it is put into suspend or shutdown. This should address occasional 'memory modified free' errors seen on recent RealTek controllers. Notes: svn path=/head/; revision=227854
* Perform media change after setting IFF_DRV_RUNNING flag. Without it,Pyun YongHyeon2011-11-221-2/+2
| | | | | | | | | driver would ignore the first link state update if controller already established a link such that it would have to take additional link state handling in re_tick(). Notes: svn path=/head/; revision=227851
* Writing access to RL_CFG5 register also requires EEPROM writePyun YongHyeon2011-11-221-5/+6
| | | | | | | | | | | | | | | | access. While I'm here, enable WOL through magic packet but disable waking up system via unicast, multicast and broadcast frames. Otherwise, multicast or unicast frame(e.g. ICMP echo request) can wake up system which is not probably wanted behavior on most environments. This was not known as problem because RL_CFG5 register access had not effect until this change. The capability to wake up system with unicast/multicast frames are still set in driver, default off, so users who need that feature can still activate it with ifconfig(8). Notes: svn path=/head/; revision=227850
* - There's no need to overwrite the default device method with the defaultMarius Strobl2011-11-221-5/+1
| | | | | | | | | | | | | one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID. Notes: svn path=/head/; revision=227843
* Add preliminary support for RTL8168/8111F PCIe Gigabit ethernet.Pyun YongHyeon2011-11-171-1/+3
| | | | | | | H/W donated by: RealTek Semiconductor Corp. Notes: svn path=/head/; revision=227639
* Add preliminary support for second generation RTL8105E PCIePyun YongHyeon2011-11-171-0/+2
| | | | | | | | | FastEthernet. H/W donated by: RealTek Semiconductor Corp. Notes: svn path=/head/; revision=227638
* Disable PCIe ASPM (Active State Power Management) for allPyun YongHyeon2011-11-161-1/+21
| | | | | | | | | | | | controllers. More and more RealTek controllers started to implement EEE feature. Vendor driver seems to load a kind of firmware for EEE with additional PHY fixups. It is known that the EEE feature may need ASPM support. Unfortunately there is no documentation for EEE of the controller so enabling ASPM may cause more problems. Notes: svn path=/head/; revision=227593
* Add missing driver lock in SIOCSIFCAP handler.Pyun YongHyeon2011-11-161-1/+3
| | | | Notes: svn path=/head/; revision=227591
* Add preliminary support for RTL8411 PCIe Gigabit ethernet withPyun YongHyeon2011-11-161-0/+2
| | | | | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp. Notes: svn path=/head/; revision=227590
* Add preliminary support for RTL8402 PCIe FastEthernet withPyun YongHyeon2011-11-161-0/+2
| | | | | | | | | integrated card reader. H/W donated by: RealTek Semiconductor Corp. Notes: svn path=/head/; revision=227587
* Sprinkle some const.Marius Strobl2011-11-021-6/+6
| | | | Notes: svn path=/head/; revision=227043
* Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.Pyun YongHyeon2011-10-171-1/+1
| | | | | | | | | | | Because driver is accessing a common MII structure in mii_pollstat(), updating user supplied structure should be done before dropping a driver lock. Reported by: Karim (fodillemlinkarimi <> gmail dot com) Notes: svn path=/head/; revision=226478
* Add new device id of D-Link DGE-530T Rev. C controller. DGE-503TPyun YongHyeon2011-07-301-0/+2
| | | | | | | | | | | Rev A1 and B1 is supported by sk(4) but the DGE-530T Rev. C controller is re-branded RealTek 8169 controller. PR: kern/159116 Approved by: re (kib) Notes: svn path=/head/; revision=224506
* Do a sweep of the tree replacing calls to pci_find_extcap() with calls toJohn Baldwin2011-03-231-4/+4
| | | | | | | pci_find_cap() instead. Notes: svn path=/head/; revision=219902
* Add initial support for RTL8401E PCIe Fast Ethernet.Pyun YongHyeon2011-02-161-1/+6
| | | | | | | PR: 154789 Notes: svn path=/head/; revision=218760
* Disable TX IP checksum offloading for RTL8168C controllers. ThePyun YongHyeon2011-02-041-4/+19
| | | | | | | | | | | | | | | | | | | controller in question generates frames with bad IP checksum value if packets contain IP options. For instance, packets generated by ping(8) with record route option have wrong IP checksum value. The controller correctly computes checksum for normal TCP/UDP packets though. There are two known RTL8168/8111C variants in market and the issue I observed happened on RL_HWREV_8168C_SPIN2. I'm not sure RL_HWREV_8168C also has the same issue but it would be better to assume it has the same issue since they shall share same core. RTL8102E which is supposed to be released at the time of RTL8168/8111C announcement does not have the issue. Tested by: Konstantin V. Krotov ( kkv <> insysnet dot ru ) Notes: svn path=/head/; revision=218289
* Add support for RTL8105E PCIe Fast Ethernet controller. It seemsPyun YongHyeon2011-01-261-1/+7
| | | | | | | | | | | | | | | | | the controller has a kind of embedded controller/memory and vendor applies a large set of magic code via undocumented PHY registers in device initialization stage. I guess it's a firmware image for the embedded controller in RTL8105E since the code is too big compared to other DSP fixups. However I have no idea what that magic code does and what's purpose of the embedded controller. Fortunately driver seems to still work without loading the firmware. While I'm here change device description of RTL810xE controller. H/W donated by: Realtek Semiconductor Corp. Notes: svn path=/head/; revision=217911
* Do not use interrupt taskqueue on controllers with MSI/MSI-XPyun YongHyeon2011-01-261-32/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | capability. One of reason using interrupt taskqueue in re(4) was to reduce number of TX/RX interrupts under load because re(4) controllers have no good TX/RX interrupt moderation mechanism. Basic TX interrupt moderation is done by hardware for most controllers but RX interrupt moderation through undocumented register showed poor RX performance so it was disabled in r215025. Using taskqueue to handle RX interrupt greatly reduced number of interrupts but re(4) consumed all available CPU cycles to run the taskqueue under high TX/RX network load. This can happen even with RTL810x fast ethernet controller and I believe this is not acceptable for most systems. To mitigate the issue, use one-shot timer register to moderate RX interrupts. The timer register provides programmable one-shot timer and can be used to suppress interrupt generation. The timer runs at 125MHZ on PCIe controllers so the minimum time allowed for the timer is 8ns. Data sheet says the register is 32 bits but experimentation shows only lower 13 bits are valid so maximum time that can be programmed is 65.528us. This yields theoretical maximum number of RX interrupts that could be generated per second is about 15260. Combined with TX completion interrupts re(4) shall generate less than 20k interrupts. This number is still slightly high compared to other intelligent ethernet controllers but system is very responsive even under high network load. Introduce sysctl variable dev.re.%d.int_rx_mod that controls amount of time to delay RX interrupt processing in units of us. Value 0 completely disables RX interrupt moderation. To provide old behavior for controllers that have MSI/MSI-X capability, introduce a new tunable hw.re.intr_filter. If the tunable is set to non-zero value, driver will use interrupt taskqueue. The default value of the tunable is 0. This tunable has no effect on controllers that has no MSI/MSI-X capability or if MSI/MSI-X is explicitly disabled by administrator. While I'm here cleanup interrupt setup/teardown since re(4) uses single MSI/MSI-X message at this moment. Notes: svn path=/head/; revision=217902
* Remove TX taskqueue and directly invoke re_start in interrupt task.Pyun YongHyeon2011-01-251-20/+13
| | | | Notes: svn path=/head/; revision=217868
* Prefer MSI-X to MSI on controllers that support MSI-X. AllPyun YongHyeon2011-01-251-11/+52
| | | | | | | | | | recent PCIe controllers(RTL8102E or later and RTL8168/8111C or later) supports either 2 or 4 MSI-X messages. Unfortunately vendor did not publicly release RSS related information yet. However switching to MSI-X is one-step forward to support RSS. Notes: svn path=/head/; revision=217857
* Disable TSO for all Realtek controllers. Experimentation showedPyun YongHyeon2011-01-251-7/+5
| | | | | | | | | | | RTL8111C generated corrupted frames where TCP option header was broken. All other sample controllers I have did not show such problem so it could be RTL8111C specific issue. Because there are too many variants it's hard to tell how many controllers have such issue. Just disable TSO by default but have user override it. Notes: svn path=/head/; revision=217832
* Apply TX interrupt moderation to all RTL810xE PCIe Fast EthernetPyun YongHyeon2011-01-241-14/+2
| | | | | | | | | | | controllers. Experimentation with RTL8102E, RTL8103E and RTL8105E showed dramatic decrement of TX completion interrupts under high TX load(e.g. from 147k interrupts/second to 10k interrupts/second) With this change, TX interrupt moderation is applied to all controllers except RTL8139C+. Notes: svn path=/head/; revision=217766
* Change model names of controller RTL_HWREV_8168_SPIN[123] to real ones.Pyun YongHyeon2011-01-181-6/+6
| | | | | | | | | | s/RL_HWREV_8168_SPIN1/RL_HWREV_8168B_SPIN1/g s/RL_HWREV_8168_SPIN2/RL_HWREV_8168B_SPIN2/g s/RL_HWREV_8168_SPIN3/RL_HWREV_8168B_SPIN3/g No functional changes. Notes: svn path=/head/; revision=217524
* Implement initial jumbo frame support for RTL8168/8111 C/D/E PCIePyun YongHyeon2011-01-171-111/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | GbE controllers. It seems these controllers no longer support multi-fragmented RX buffers such that driver have to allocate physically contiguous buffers. o Retire RL_FLAG_NOJUMBO flag and introduce RL_FLAG_JUMBOV2 to mark controllers that use new jumbo frame scheme. o Configure PCIe max read request size to 4096 for standard frames and reduce it to 512 for jumbo frames. o TSO/checksum offloading is not supported for jumbo frames on these controllers. Reflect it to ioctl handler and driver initialization. o Remove unused rl_stats_no_timeout in softc. o Embed a pointer to structure rl_hwrev into softc to keep track of controller MTU limitation and remove rl_hwrev in softc since that information is available through a pointer to structure rl_hwrev. Special thanks to Realtek for donating sample hardwares which made this possible. H/W donated by: Realtek Semiconductor Corp. Notes: svn path=/head/; revision=217499
* Add initial support for RTL8168E/8111E-VL PCIe GbE.Pyun YongHyeon2011-01-171-0/+6
| | | | | | | H/W donated by: Realtek Semiconductor Corp. Notes: svn path=/head/; revision=217498
* If driver is not able to allocate RX buffer, do not start driver.Pyun YongHyeon2011-01-131-6/+10
| | | | | | | | | While I'm here move RX buffer allocation and descriptor initialization up to not touch hardware registers in case of RX buffer allocation failure. Notes: svn path=/head/; revision=217385
* Make sure to check validity of dma maps before destroying.Pyun YongHyeon2011-01-131-6/+10
| | | | Notes: svn path=/head/; revision=217384
* re_reset() should be called only after setting device specificPyun YongHyeon2011-01-131-5/+5
| | | | | | | features. Notes: svn path=/head/; revision=217382
* Allow TX/RX checksum offloading to be configured independently.Pyun YongHyeon2011-01-131-3/+9
| | | | Notes: svn path=/head/; revision=217381
* For re(4) controllers that uses new jumbo frame scheme(RTL8168C/D/E),Pyun YongHyeon2011-01-121-2/+7
| | | | | | | | | | | | | | | | | | | | | | limit maximum RX buffer size to RE_RX_DESC_BUFLEN instead of blindly configuring it to 16KB. Due to lack of documentation, re(4) didn't allow jumbo frame on these controllers. However it seems controller is confused with jumbo frame such that it can DMA the received frame to wrong address instead of splitting it into multiple RX buffers. Of course, this caused panic. Since re(4) does not support jumbo frames on these controllers, make controller drop frame that is longer than RE_RX_DESC_BUFLEN sized frame. Fortunately RTL810x controllers, which do not support jumbo frame, have no such issues but this change also limited maximum RX buffer size allowed to RTL810x controllers. Allowing 16KB RX buffer for controllers that have no such capability is meaningless. MFC after: 3 days Notes: svn path=/head/; revision=217296
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