| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | sys: Remove $FreeBSD$: one-line .c comment pattern | Warner Losh | 2023-08-16 | 1 | -1/+0 |
| * | Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replace | Tijl Coosemans | 2012-03-19 | 1 | -627/+3 |
| * | Add definitions related to XCR0. | Konstantin Belousov | 2012-01-17 | 1 | -0/+1 |
| * | Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. | Jung-uk Kim | 2011-05-17 | 1 | -1/+12 |
| * | prepare code that does topology detection for amd cpus for bulldozer | Andriy Gapon | 2011-05-06 | 1 | -0/+2 |
| * | Define "Hypervisor Present" bit. This bit is used by several hypervisors to | Jung-uk Kim | 2011-04-28 | 1 | -0/+1 |
| * | Add definitions for CPUID instruction 6, ECX information. | Jung-uk Kim | 2011-04-12 | 1 | -0/+6 |
| * | specialreg.h: add definitions for some useful bits found in CPUID.6 EAX and ECX | Andriy Gapon | 2010-11-23 | 1 | -0/+9 |
| * | specialreg.h: add definitions for MPERF/APERF pair of MSRs | Andriy Gapon | 2010-11-19 | 1 | -0/+2 |
| * | specialreg.h: add AMD-specific "Hardware Configuration Register" MSR | Andriy Gapon | 2010-11-19 | 1 | -1/+2 |
| * | specialreg.h: add definition for AMD Core Performance Boost bit | Andriy Gapon | 2010-11-19 | 1 | -0/+1 |
| * | Display PCID capability of CPU and add CPUID define for it. | Konstantin Belousov | 2010-10-05 | 1 | -0/+1 |
| * | Improve cputemp(4) driver wrt newer Intel processors, especially | Xin LI | 2010-07-29 | 1 | -0/+1 |
| * | The corrected error count field is dependent on CMCI, not TES. | John Baldwin | 2010-07-28 | 1 | -3/+3 |
| * | Add support for corrected machine check interrupts. CMCI is a new local | John Baldwin | 2010-05-24 | 1 | -1/+1 |
| * | Add definitions for Intel AESNI CPUID bits and print the capabilities | Konstantin Belousov | 2010-05-05 | 1 | -0/+2 |
| * | Adapt r204907 and r205402, the amd64 implementation of the workaround for | Alan Cox | 2010-03-24 | 1 | -0/+1 |
| * | Remove unneeded type specifiers from 64-bit constants. The compiler | John Baldwin | 2010-03-22 | 1 | -30/+30 |
| * | - Extend the machine check record structure to include several fields useful | John Baldwin | 2010-03-16 | 1 | -0/+12 |
| * | Use unsigned long long constants for fields in 64-bit machine check | John Baldwin | 2010-03-16 | 1 | -12/+12 |
| * | x86 cpu features: add MOVBE reporting and flag | Andriy Gapon | 2009-11-30 | 1 | -0/+1 |
| * | Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce | Jung-uk Kim | 2009-09-10 | 1 | -2/+2 |
| * | Move (read|write)_cyrix_reg() inlines from specialreg.h to cpufunc.h. | John Baldwin | 2009-06-16 | 1 | -16/+0 |
| * | Implement simple machine check support for amd64 and i386. | John Baldwin | 2009-05-13 | 1 | -0/+28 |
| * | - Add support for cpuid leaf 0xb. This allows us to determine the | Jeff Roberson | 2009-04-29 | 1 | -0/+7 |
| * | Add more CPUID bits from AMD CPUID Specification Rev. 2.28. | Jung-uk Kim | 2008-12-12 | 1 | -0/+8 |
| * | Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). | Jung-uk Kim | 2008-11-26 | 1 | -2/+10 |
| * | Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher | Jung-uk Kim | 2008-10-22 | 1 | -0/+17 |
| * | Detect Advanced Power Management Information for AMD CPUs. | Jung-uk Kim | 2008-10-21 | 1 | -0/+13 |
| * | MFamd64: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB | John Baldwin | 2008-09-17 | 1 | -0/+6 |
| * | - Add cpuctl(4) pseudo-device driver to provide access to some low-level | Stanislav Sedov | 2008-08-08 | 1 | -0/+7 |
| * | The variable MTRR registers actually have variable-sized PhysBase and | John Baldwin | 2008-03-12 | 1 | -2/+2 |
| * | Add constants for the various fields in MTRR registers. | John Baldwin | 2008-03-11 | 1 | -0/+15 |
| * | Add a driver for the on-die digital thermal sensor found on Intel Core | Dag-Erling Smørgrav | 2007-08-15 | 1 | -0/+1 |
| * | Add CPUID2_PDCM | Dag-Erling Smørgrav | 2007-05-31 | 1 | -0/+1 |
| * | Add the PG_NX support for i386/PAE. | Ruslan Ermilov | 2007-04-06 | 1 | -0/+8 |
| * | - Add macros for newly added CPUID bits in the corresponding header files. | Jung-uk Kim | 2007-03-20 | 1 | -0/+2 |
| * | Add another CPUID for AMD CPUs and fix style(9) while I am here. | Jung-uk Kim | 2007-03-12 | 1 | -112/+113 |
| * | Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors. | Jung-uk Kim | 2007-01-09 | 1 | -1/+2 |
| * | Sync specialreg.h changes between amd64 and i386 with few fixes. | Jung-uk Kim | 2006-07-13 | 1 | -14/+21 |
| * | fix typo in identcpu.c and add one define to specialreg.h. | Michael Reifenberger | 2006-07-12 | 1 | -1/+4 |
| * | First step to identify and initialize the newer VIA C7 CPU | Michael Reifenberger | 2006-07-12 | 1 | -0/+32 |
| * | Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register. | Jung-uk Kim | 2006-07-12 | 1 | -0/+2 |
| * | Style fix, use low-case. | David Xu | 2006-06-19 | 1 | -1/+1 |
| * | Clear bit 22 in MSR IA32_MISC_ENABLE, according to Intel document, | David Xu | 2006-06-19 | 1 | -0/+1 |
| * | Add various constants for the PAT MSR and the PAT PTE and PDE flags. | John Baldwin | 2006-05-01 | 1 | -0/+13 |
| * | - Print number of physical/logical cores and more CPUID info. | Jung-uk Kim | 2005-10-14 | 1 | -0/+22 |
| * | Remove advertising clause from University of California Regent's | Warner Losh | 2004-04-07 | 1 | -4/+0 |
| * | Add new CPU_ENABLE_TCC option, from NOTES: | Maxim Sobolev | 2004-01-18 | 1 | -0/+3 |
| * | - Add macros describing some new MSR's in the Pentium 4 and some older | John Baldwin | 2003-08-15 | 1 | -0/+25 |
