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* Remove ia64.Marcel Moolenaar2014-07-0769-7437/+0
| | | | | | | | | | | | | | | | | | | | This includes: o All directories named *ia64* o All files named *ia64* o All ia64-specific code guarded by __ia64__ o All ia64-specific makefile logic o Mention of ia64 in comments and documentation This excludes: o Everything under contrib/ o Everything under crypto/ o sys/xen/interface o sys/sys/elf_common.h Discussed at: BSDcan Notes: svn path=/head/; revision=268351
* Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4Tijl Coosemans2014-04-011-1/+1
| | | | | | | | | -fms-extensions. MFC after: 2 weeks Notes: svn path=/head/; revision=263998
* Move ia64 efi.h to sys in preparation for amd64 UEFI supportEd Maste2014-03-271-177/+0
| | | | | | | | | | | | | Prototypes specific to ia64 have been left in this file for now, under __ia64__, rather than moving them to a new header under sys/ia64. I anticipate that (some of) the corresponding functions will be shared by the amd64, arm64, i386, and ia64 architectures, and we can adjust this as EFI support on other than ia64 continues to develop. Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=263815
* Add KTR events for the PMAP interface functionsMarcel Moolenaar2014-03-191-9/+14
| | | | | | | | | | | | | | | | | | | | | 1. move unmapped_buf_allowed to machdep.c. 2. map both pmap_mapbios() and pmap_mapdev() to pmap_mapdev_attr() and have the actual work done by pmap_mapdev_priv() (renamed from pmap_mapdev()). Use pmap_mapdev_priv() to map the I/O port space because we can't use CTR() that early. 3. add pmap_pinit_common() that's used by both pmap_pinit0() and pmap_pinit(). Previously pmap_pinit0() would call pmap_pinit(), but that would create 2 KTR events. While here, use pmap_t instead of "struct pmap *". 4. fix pmap_kenter() to use vm_paddr_t as the type for the physical. 5. various white-space adjustments for consistency. 6. use C99 and KNF for function definitions where appropriate. 7. slightly re-order prototypes and defines in <machine/pmap.h> No functional change (other than the creation of KTR_PMAP events). Notes: svn path=/head/; revision=263380
* Fix and improve exception tracing:Marcel Moolenaar2014-03-183-1/+9
| | | | | | | | | | | | | | | | | | | 1. Name the kernel option XTRACE instead of EXCEPTION_TRACING 2. Put support functions in ia64/ia64/xtrace.c 3. Make it work with SMP by giving each CPU its own buffer 4. Save 16 key registers in the buffer for every exception 5. In ia64_handle_intr() and trap() transfer the trace record to the KTR trace buffer using CTRx() and with some basic information for now 6. Use a tunable to anble tracing and stop tracing as soon as we enter the debugger Room for improvements: 1. Transferring exception-relevant information to KTR 2. Add a sysctl to enable/disable tracing Notes: svn path=/head/; revision=263323
* Move the implementation of kdb_cpu_trap() from <machine/kdb.h> toMarcel Moolenaar2014-03-161-10/+2
| | | | | | | | machdep.c. This makes it easier to add conditional code based on options. Notes: svn path=/head/; revision=263254
* Implement atomic_swap_<type>.Marcel Moolenaar2014-01-011-0/+28
| | | | | | | | | | The operation was documented and implemented partially (both from a type and architecture perspective) on 2013-08-21 and got used in ZFS with revision 260150 (zfeature.c) and since ZFS is supported on ia64, the lack of having atomic_swap became problem. Notes: svn path=/head/; revision=260175
* As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In otherAlan Cox2013-11-081-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | words, every architecture is now auto-sizing the kmem arena. This revision changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes mandatory and the definition of VM_KMEM_SIZE becomes optional. Replace or eliminate all existing definitions of VM_KMEM_SIZE. With auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling for VM_KMEM_SIZE_MIN on most architectures. Use VM_KMEM_SIZE_MIN for clarity. Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to that of setting the tunable vm.kmem_size. Whereas the macros VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size have been distinct. In particular, whereas VM_KMEM_SIZE was overridden by VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size was not. Remedy this inconsistency. Now, VM_KMEM_SIZE can be used to set the size of the kmem arena at compile-time without that value being overridden by auto-sizing. Update the nearby comments to reflect the kmem submap being replaced by the kmem arena. Stop duplicating the auto-sizing formula in every machine- dependent vmparam.h and place it in kmeminit() where auto-sizing takes place. Reviewed by: kib (an earlier version) Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=257854
* Use LOG2_ID_PAGE_SIZE again for the identity mapping in regions 6 & 7.Marcel Moolenaar2013-11-011-0/+5
| | | | | | | | | Make the default translation size the same as the PBVM page size to avoid inserting overlapping translations in the TC. That generally is very bad. Notes: svn path=/head/; revision=257487
* Purge the translation cache of APs before we unleash them. To thatMarcel Moolenaar2013-10-311-0/+1
| | | | | | | | | | | end, make pmap_invalidate_all() global and have it only handle the local CPU -- i.e. no rendezvous. We do not use pmap_invalidate_all other than during initialization. Note that the BSP already purges its TC -- it was missing for APs only. Nonetheless, this so far seems to eliminate random problems. Notes: svn path=/head/; revision=257477
* On those machines, where sf_bufs do not represent any real object, makeGleb Smirnoff2013-09-061-0/+12
| | | | | | | | | | | | sf_buf_alloc()/sf_buf_free() inlines, to save two calls to an absolutely empty functions. Reviewed by: alc, kib, scottl Sponsored by: Nginx, Inc. Sponsored by: Netflix Notes: svn path=/head/; revision=255289
* Tidy up global locks for ACPICA. There is no functional change.Jung-uk Kim2013-08-131-3/+3
| | | | Notes: svn path=/head/; revision=254300
* Revert r253748,253749Andriy Gapon2013-07-281-2/+2
| | | | | | | | | This WIP should not have been committed yet. Pointyhat to: avg Notes: svn path=/head/; revision=253750
* put contents of cpu.h under _KERNELAndriy Gapon2013-07-281-2/+2
| | | | | | | | | no userland-serviceable parts inside MFC after: 20 days Notes: svn path=/head/; revision=253748
* Fix issues with zeroing and fetching the counters, on x86 and ppc64.Konstantin Belousov2013-07-011-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues were noted by Bruce Evans and are present on all architectures. On i386, a counter fetch should use atomic read of 64bit value, otherwise carry from the increment on other CPU could be lost for the given fetch, making error of 2^32. If 64bit read (cmpxchg8b) is not available on the machine, it cannot be SMP and it is enough to disable preemption around read to avoid the split read. On x86 the counter increment is not atomic on purpose, which makes it possible for the store of the incremented result to override just zeroed per-cpu slot. The effect would be a counter going off by arbitrary value after zeroing. Perform the counter zeroing on the same processor which does the increments, making the operations mutually exclusive. On i386, same as for the fetching, if the cmpxchg8b is not available, machine is not SMP and we disable preemption for zeroing. PowerPC64 is treated the same as amd64. For other architectures, the changes made to allow the compilation to succeed, without fixing the issues with zeroing or fetching. It should be possible to handle them by using the 64bit loads and stores atomic WRT preemption (assuming the architectures also converted from using critical sections to proper asm). If architecture does not provide the facility, using global (spin) mutex would be non-optimal but working solution. Noted by: bde Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=252434
* Move definitions required by userland applications out of acpica_machdep.h.Jung-uk Kim2013-06-271-7/+2
| | | | Notes: svn path=/head/; revision=252280
* Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h inAttilio Rao2013-05-072-7/+4
| | | | | | | | | | | | order to match the MAXCPU concept. The change should also be useful for consolidation and consistency. Sponsored by: EMC / Isilon storage division Obtained from: jeff Reviewed by: alc Notes: svn path=/head/; revision=250338
* Merge from projects/counters: counter(9).Gleb Smirnoff2013-04-081-0/+54
| | | | | | | | | | | | | | | | Introduce counter(9) API, that implements fast and raceless counters, provided (but not limited to) for gathering of statistical data. See http://lists.freebsd.org/pipermail/freebsd-arch/2013-April/014204.html for more details. In collaboration with: kib Reviewed by: luigi Tested by: ae, ray Sponsored by: Nginx, Inc. Notes: svn path=/head/; revision=249268
* Merge from projects/counters:Gleb Smirnoff2013-04-081-1/+2
| | | | | | | | | | Pad struct pcpu so that its size is denominator of PAGE_SIZE. This is done to reduce memory waste in UMA_PCPU_ZONE zones. Sponsored by: Nginx, Inc. Notes: svn path=/head/; revision=249265
* kernacc() expects all KVAs to be covered in the kernel map. With theMarcel Moolenaar2013-02-251-4/+5
| | | | | | | | | | | | | | | introduction of the PBVM, this stopped being the case. Redefine the VM parameters so that the PBVM is included in the kernel map. In particular this introduces VM_INIT_KERNEL_ADDRESS to point to the base of region 5 now that VM_MIN_KERNEL_ADDRESS points to the base of region 4 to include the PBVM. While here define KERNBASE to the actual link address of the kernel as is intended. PR: 169926 Notes: svn path=/head/; revision=247251
* Eliminate padding by moving 'narg' next to 'code'. Both are 32-bitMarcel Moolenaar2013-02-121-1/+1
| | | | | | | | entities in the syscall_args structure that otherwise has 64-bit only fields. Notes: svn path=/head/; revision=246714
* Fix compilation on ia64 when page size is configured for 16KB.Konstantin Belousov2012-10-281-15/+0
| | | | | | | Reviewed by: alc, marcel Notes: svn path=/head/; revision=242218
* Port the new PV entry allocator from amd64/i386. This allocator has twoAlan Cox2012-10-261-4/+17
| | | | | | | | | | | | | | advantages. First, PV entries are roughly half the size. Second, this allocator doesn't access the paging queues, and thus it allows for the removal of the page queues lock from this pmap. Replace all uses of the page queues lock by a R/W lock that is private to this pmap. Tested by: marcel Notes: svn path=/head/; revision=242121
* Move PCPU initialization to a new function called cpu_pcpu_setup().Marcel Moolenaar2012-07-081-0/+2
| | | | | | | | This makes it easier to add additional CPU or platform information to the per-CPU structure without duplicated code. Notes: svn path=/head/; revision=238257
* Implement ia64_physmem_alloc() and use it consistently to get memoryMarcel Moolenaar2012-07-071-1/+1
| | | | | | | | | | | | | | | | before VM has been initialized. This includes: 1. Replacing pmap_steal_memory(), 2. Replace the handcrafted logic to allocate a naturally aligned VHPT, 3. Properly allocate the DPCPU for the BSP. Ad 3: Appending the DPCPU to kernend worked as long as we wouldn't cross into the next PBVM page. If we were to cross into the next page, then there wouldn't be a PTE entry on the page table for it and we would end up with a MCA following a page fault. As such, this commit fixes MCAs occasionally seen. Notes: svn path=/head/; revision=238190
* Hide the creation of phys_avail behind an API to make it easier to do itMarcel Moolenaar2012-07-072-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | correctly. We now iterate the EFI memory descriptors once and collect all the information in a single pass. This includes: 1. The I/O port base address, 2. The PAL memory region. Have the physmem API track this. 3. Memory descriptors of memory we can't use, like bad memory, runtime services code & data, etc. Have the physmem API track these. 4. memory descriptors of memory we can use or re-use, such as free memory, boot time services code & data, loader code & data, etc. These are added by the physmem API. Since the PBVM page table and pages are in memory described as loader data, inform the physmem API of chunks that need to be delated from the available physical memory. While here, remove Maxmem and replace it with the better named paddr_max. Maxmem was defined as physmem, which is generally wrong. Now, paddr_max is properly defined as the largesty physical address. The upshot of all this is that: 1. We properly determine realmem. 2. We maximize physmem by re-using memory where possible. 3. We remove complexity from ia64_init() in machdep.c. 4. Remove confusion about realmem, physmem & Maxmem. The new ia64_physmem_alloc() is to replace pmap_steal_memory() in pmap.c, as well as replace the handcrafted allocation of the VHPT for the BSP in pmap_bootstrap() in pmap.c. This is step 2 and addresses the manipulation of phys_avail after it is being created. Notes: svn path=/head/; revision=238184
* Make the wchar_t type machine dependent.Andrew Turner2012-06-242-6/+4
| | | | | | | | | | | | | | | | | This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an unsigned short with the former preferred. Because of this requirement we need to move the definition of __wchar_t to a machine dependent header. It also cleans up the macros defining the limits of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine dependent header then using them to define WCHAR_MIN and WCHAR_MAX respectively. Discussed with: bde Notes: svn path=/head/; revision=237517
* Implement mechanism to export some kernel timekeeping data toKonstantin Belousov2012-06-221-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usermode, using shared page. The structures and functions have vdso prefix, to indicate the intended location of the code in some future. The versioned per-algorithm data is exported in the format of struct vdso_timehands, which mostly repeats the content of in-kernel struct timehands. Usermode reading of the structure can be lockless. Compatibility export for 32bit processes on 64bit host is also provided. Kernel also provides usermode with indication about currently used timecounter, so that libc can fall back to syscall if configured timecounter is unknown to usermode code. The shared data updates are initiated both from the tc_windup(), where a fast task is queued to do the update, and from sysctl handlers which change timecounter. A manual override switch kern.timecounter.fast_gettime allows to turn off the mechanism. Only x86 architectures export the real algorithm data, and there, only for tsc timecounter. HPET counters page could be exported as well, but I prefer to not further glue the kernel and libc ABI there until proper vdso-based solution is developed. Minimal stubs neccessary for non-x86 architectures to still compile are provided. Discussed with: bde Reviewed by: jhb Tested by: flo MFC after: 1 month Notes: svn path=/head/; revision=237433
* Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer toKonstantin Belousov2012-06-221-0/+1
| | | | | | | | | timekeeping information. MFC after: 1 week Notes: svn path=/head/; revision=237430
* The page flag PGA_WRITEABLE is set and cleared exclusively by the pmapAlan Cox2012-06-161-0/+1
| | | | | | | | | | | | | | | | | | | layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks Notes: svn path=/head/; revision=237168
* MFp4 bz_ipv6_fast:Bjoern A. Zeeb2012-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | in_cksum.h required ip.h to be included for struct ip. To be able to use some general checksum functions like in_addword() in a non-IPv4 context, limit the (also exported to user space) IPv4 specific functions to the times, when the ip.h header is present and IPVERSION is defined (to 4). We should consider more general checksum (updating) functions to also allow easier incremental checksum updates in the L3/4 stack and firewalls, as well as ponder further requirements by certain NIC drivers needing slightly different pseudo values in offloading cases. Thinking in terms of a better "library". Sponsored by: The FreeBSD Foundation Sponsored by: iXsystems Reviewed by: gnn (as part of the whole) MFC After: 3 days Notes: svn path=/head/; revision=235941
* Add a convenience macro for the returns_twice attribute, and apply it toDimitry Andric2012-04-291-2/+2
| | | | | | | | | | the prototypes of the appropriate functions (getcontext, savectx, setjmp, sigsetjmp and vfork). MFC after: 2 weeks Notes: svn path=/head/; revision=234785
* Eliminate ia32_reg.h by moving its contents to x86 and ia64 reg.h.Tijl Coosemans2012-03-181-8/+40
| | | | | | | Reviewed by: kib Notes: svn path=/head/; revision=233125
* Add C11 macros describing subnormal numbers to float.h.David Schultz2012-01-231-0/+15
| | | | | | | Reviewed by: bde Notes: svn path=/head/; revision=230475
* Add parentheses where required. Without them, `sizeof LDBL_MAX'David Schultz2012-01-201-4/+4
| | | | | | | | is a syntax error and shouldn't be, while `1 FLT_ROUNDS' isn't a syntax error and should be. Thanks to bde for the examples. Notes: svn path=/head/; revision=230366
* Replace __signed by signed.Ed Schouten2011-12-131-1/+1
| | | | | | | | The signed keyword is an integral part of the C syntax. There's no need to use __signed. Notes: svn path=/head/; revision=228469
* People porting FreeBSD to new architectures ought not have toDavid Schultz2011-10-211-0/+9
| | | | | | | | | | | | | | | | implement a deprecated FPU control interface in addition to the standard one. To make this clearer, further deprecate ieeefp.h by not declaring the function prototypes except on architectures that implement them already. Currently i386 and amd64 implement the ieeefp.h interface for compatibility, and for fp[gs]etprec(), which doesn't exist on most other hardware. Powerpc, sparc64, and ia64 partially implement it and probably shouldn't, and other architectures don't implement it at all. Notes: svn path=/head/; revision=226607
* Remove unused define.Konstantin Belousov2011-10-071-1/+0
| | | | | | | MFC after: 1 month Notes: svn path=/head/; revision=226112
* Bump MAXCPU for amd64, ia64 and XLP mips appropriately.Attilio Rao2011-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | From now on, default values for FreeBSD will be 64 maxiumum supported CPUs on amd64 and ia64 and 128 for XLP. All the other architectures seem already capped appropriately (with the exception of sparc64 which needs further support on jalapeno flavour). Bump __FreeBSD_version in order to reflect KBI/KPI brekage introduced during the infrastructure cleanup for supporting MAXCPU > 32. This covers cpumask_t retiral too. The switch is considered completed at the present time, so for whatever bug you may experience that is reconducible to that area, please report immediately. Requested by: marcel, jchandra Tested by: pluknet, sbruno Approved by: re (kib) Notes: svn path=/head/; revision=224217
* Add the possibility to specify from kernel configs MAXCPU value.Attilio Rao2011-07-191-0/+2
| | | | | | | | | | | | | This patch is going to help in cases like mips flavours where you want a more granular support on MAXCPU. No MFC is previewed for this patch. Tested by: pluknet Approved by: re (kib) Notes: svn path=/head/; revision=224207
* Add a few more helper functions for working with memory descriptors:Marcel Moolenaar2011-07-161-0/+3
| | | | | | | | | o efi_md_find() - returns the md that covers the given address o efi_md_last() - returns the last md in the list o efi_md_prev() - returns the md that preceeds the given md. Notes: svn path=/head/; revision=224112
* Implement basic support for memory attributes. At this time we onlyMarcel Moolenaar2011-07-082-11/+15
| | | | | | | | | | | | | | | | distinguish between UC and WB memory so that we can map the page to either a region 6 address (for UC) or a region 7 address (for WB). This change is only now possible, because previously we would map regions 6 and 7 with 256MB translations and on top of that had the kernel mapped in region 7 using a wired translation. The introduction of the PBVM moved the kernel into its own region and freed up region 7 and allowed us to revert to standard page-sized translations. This commit inroduces pmap_page_to_va() that respects the attribute. Notes: svn path=/head/; revision=223873
* Switch to the event timers infrastructure. This includes:Marcel Moolenaar2011-06-252-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Setting td_intr_frame to the XIVs trap frame because it's referenced by the ET event handler. o Signal EOI to the CPU before calling the registered XIV handlers. This prevents lost ITC interrupts, which cause starvation in one-shot mode. o Adding support for IPI_HARDCLOCK with corresponding per-CPU counters. o Have the APs call cpu_initclocks() so as to limited the scattering of clock related initialization. cpu_initclocks() calls the <self>_bsp() or <self>_ap() version accordingly. o Uncomment the ET clock handling in cpu_idle(). o Update the DDB 'show pcpu' output for the new MD fields. o Entirely rewritten ia64_ih_clock(). Note that we don't create as many clock XIVs as we have CPUs, as is done on PowerPC. It doesn't scale. We can only have 240 XIVs and we can have more CPUs than that. There's a single intrcnt index for the cumulative clock ticks and we keep per CPU counts in the PCPU stats structure. o Register the ITC by hooking SI_SUB_CONFIGURE (2nd order). Open issues: o Clock interrupts can still be lost. Some tweaking is still necessary. Thanks to: mav@ for his support, feedback and explanations. ET stats while committing: eris% sysctl machdep.cpu | grep nclks machdep.cpu.0.nclks: 24007 machdep.cpu.1.nclks: 22895 machdep.cpu.2.nclks: 13523 machdep.cpu.3.nclks: 9342 machdep.cpu.4.nclks: 9103 machdep.cpu.5.nclks: 9298 machdep.cpu.6.nclks: 10039 machdep.cpu.7.nclks: 9479 eris% vmstat -i | grep clock clock 108599 50 Notes: svn path=/head/; revision=223526
* Properly serialize the global shootdown with the instructionMarcel Moolenaar2011-06-171-2/+11
| | | | | | | | | | stream of the local processor. Also explicitly invalidate the ALAT. This is done on the other CPUs in the coherence domain by virtue of the ptc.ga instruction, but does not apply to the local CPU. Notes: svn path=/head/; revision=223170
* MFCAttilio Rao2011-05-142-12/+9
|\ | | | | | | Notes: svn path=/projects/largeSMP/; revision=221910
| * Be pedantic: mark the pcpu pointer (= register r13) itself as volatile.Marcel Moolenaar2011-05-141-1/+1
| | | | | | | | Notes: svn path=/head/; revision=221890
| * Turn ia64_srlz() and ia64_srlz_i() into defines so that the code isMarcel Moolenaar2011-05-141-11/+8
| | | | | | | | | | | | | | still correct when inlining is disabled. Notes: svn path=/head/; revision=221889
* | MFCAttilio Rao2011-05-131-0/+2
|\| | | | | | | Notes: svn path=/projects/largeSMP/; revision=221858
| * Move the ZERO_REGION_SIZE to a machine-dependent file, as on manyMatthew D Fleming2011-05-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | architectures (i386, for example) the virtual memory space may be constrained enough that 2MB is a large chunk. Use 64K for arches other than amd64 and ia64, with special handling for sparc64 due to differing hardware. Also commit the comment changes to kmem_init_zero_region() that I missed due to not saving the file. (Darn the unfamiliar development environment). Arch maintainers, please feel free to adjust ZERO_REGION_SIZE as you see fit. Requested by: alc MFC after: 1 week MFC with: r221853 Notes: svn path=/head/; revision=221855
* | Commit the support for removing cpumask_t and replacing it directly withAttilio Rao2011-05-052-2/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpuset_t objects. That is going to offer the underlying support for a simple bump of MAXCPU and then support for number of cpus > 32 (as it is today). Right now, cpumask_t is an int, 32 bits on all our supported architecture. cpumask_t on the other side is implemented as an array of longs, and easilly extendible by definition. The architectures touched by this commit are the following: - amd64 - i386 - pc98 - arm - ia64 - XEN while the others are still missing. Userland is believed to be fully converted with the changes contained here. Some technical notes: - This commit may be considered an ABI nop for all the architectures different from amd64 and ia64 (and sparc64 in the future) - per-cpu members, which are now converted to cpuset_t, needs to be accessed avoiding migration, because the size of cpuset_t should be considered unknown - size of cpuset_t objects is different from kernel and userland (this is primirally done in order to leave some more space in userland to cope with KBI extensions). If you need to access kernel cpuset_t from the userland please refer to example in this patch on how to do that correctly (kgdb may be a good source, for example). - Support for other architectures is going to be added soon - Only MAXCPU for amd64 is bumped now The patch has been tested by sbruno and Nicholas Esborn on opteron 4 x 12 pack CPUs. More testing on big SMP is expected to came soon. pluknet tested the patch with his 8-ways on both amd64 and i386. Tested by: pluknet, sbruno, gianni, Nicholas Esborn Reviewed by: jeff, jhb, sbruno Notes: svn path=/projects/largeSMP/; revision=221499
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