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* sys: Automated cleanup of cdefs and other formattingWarner Losh2023-11-271-1/+0
| | | | | | | | | | | | | | | | Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
* sys: Remove $FreeBSD$: one-line .c patternWarner Losh2023-08-161-2/+0
| | | | Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
* powerpc: clean up empty lines in .c and .h filesMateusz Guzik2020-09-011-2/+1
| | | | Notes: svn path=/head/; revision=365073
* powerpc: Simplify _nodrop variants of FPU and vector register savesJustin Hibbits2020-03-131-4/+1
| | | | | | | | | No need for an extra temporary. It doesn't even help with readability. Suggested by: kib (almost 2 years ago) Notes: svn path=/head/; revision=358928
* [PowerPC] Fix SPE floating point environment manipulationBrandon Bergren2019-12-121-1/+1
| | | | | | | | | | | | | | | Fix multiple problems in the powerpcspe floating point code. * Endianness handling of the SPEFSCR in fenv.h was completely broken. * Ensure SPEFSCR synchronization requirements are being met. The __r.__d -> __r transformations were written by jhibbits. Reviewed by: jhibbits Differential Revision: https://reviews.freebsd.org/D22526 Notes: svn path=/head/; revision=355656
* [PowerPC] Use QEMU-compatible version of SPE accumulator saveBrandon Bergren2019-11-231-1/+1
| | | | | | | | | | | | | | | Switch from "evaddumiaaw 0,0" to "evmwumiaa 0,0,0" when persisting the accumulator. This has the benefit of actually being implemented in QEMU as it is the form Linux uses for the same task. Both instructions are functionally equivilent, as we are using them for their side effect of copying the accumulator to GPRs rather than for the actual math operation that they are performing. Reviewed by: jhibbits Notes: svn path=/head/; revision=355035
* powerpcspe: Don't leak kernel registers in SPE dumpsJustin Hibbits2019-11-161-4/+13
| | | | | | | | | | | save_vec_int() for SPE saves off only the high word of the register, leaving the low word as "garbage", but really containing whatever was in the kernel register at the time. This leaks into core dumps, and in a near future commit also into ptrace. Instead, save the GPR in the low word in save_vec_nodrop(), which is used only for core dumps and ptrace. Notes: svn path=/head/; revision=354776
* powerpcspe: Mark asm statement in spe_save_reg_high as clobbering memoryJustin Hibbits2019-11-161-1/+1
| | | | | | | | | | | Modern gcc errors that "'vec[0]' is used uninitialized in this function" without us telling it that vec is clobbered. Neither clang nor gcc 4.2.1 error on the existing construct. Submitted by: bdragon Notes: svn path=/head/; revision=354775
* powerpc/SPE: Enable SPV bit for EFSCFD instruction emulationJustin Hibbits2019-07-201-0/+1
| | | | | | | | | | | EFSCFD (floating point single convert from double) emulation requires saving the high word of the register, which uses SPE instructions. Enable the SPE to avoid an SPV Unavailable exception. MFC after: 1 week Notes: svn path=/head/; revision=350181
* powerpcspe: Correct SPE high-component loadingJustin Hibbits2019-01-131-2/+2
| | | | | | | | | | | | | | Don't clobber the low part of the register restoring the high component of. This could lead to very bad behavior if it's an ABI-affected register. While here, also mark the asm volatile in the SPE high save case, to match the load case. Reported by: Branden Bergren (git_bdragon.rtk0.net) MFC after: 1 week Notes: svn path=/head/; revision=342988
* powerpcspe: Fix GPR handling in SPE exception handlerJustin Hibbits2018-12-131-32/+74
| | | | | | | | | | | | | | | | Optimize the exception handler to only save and load the upper word of the GPRs used in the emulating instruction. This reduces the save/load overhead, and as a side effect does not overwrite the upper word of any temporary register. With this commit I am now able to run editors/abiword and math/gnumeric on a e500-based system. MFC after: 1 week MFC With: r341752,r341751 Notes: svn path=/head/; revision=342025
* powerpc/SPE: Copy lower part of source register to target for ↵Justin Hibbits2018-12-091-0/+3
| | | | | | | | | | efdabs/efdnabs/efdneg MFC after: 1 week MFC With: r341751 Notes: svn path=/head/; revision=341752
* powerpc/SPE: Reload vector registers after efdabs/efdnabs/efdnegJustin Hibbits2018-12-091-6/+9
| | | | | | | While here, also style(9)-adjust indents around this code. Notes: svn path=/head/; revision=341751
* powerpcspe: Implement SPE exception handlingJustin Hibbits2018-10-211-3/+454
| | | | | | | | | | | | | The Signal Processing Engine (SPE) found in Freescale e500 cores (and others) offloads IEEE-754 compliance (NaN, Inf handling, overflow, underflow) to software, most likely as a means of simplifying the APU silicon. Some software, like AbiWord, needs full IEEE-754 compliance, including NaN handling. Implement the necessary bits to enable it. Differential Revision: https://reviews.freebsd.org/D17446 Notes: svn path=/head/; revision=339514
* Create a new MACHINE_ARCH for Freescale PowerPC e500v2Justin Hibbits2016-10-221-0/+183
Summary: The Freescale e500v2 PowerPC core does not use a standard FPU. Instead, it uses a Signal Processing Engine (SPE)--a DSP-style vector processor unit, which doubles as a FPU. The PowerPC SPE ABI is incompatible with the stock powerpc ABI, so a new MACHINE_ARCH was created to deal with this. Additionaly, the SPE opcodes overlap with Altivec, so these are mutually exclusive. Taking advantage of this fact, a new file, powerpc/booke/spe.c, was created with the same function set as in powerpc/powerpc/altivec.c, so it becomes effectively a drop-in replacement. setjmp/longjmp were modified to save the upper 32-bits of the now-64-bit GPRs (upper 32-bits are only accessible by the SPE). Note: This does _not_ support the SPE in the e500v1, as the e500v1 SPE does not support double-precision floating point. Also, without a new MACHINE_ARCH it would be impossible to provide binary packages which utilize the SPE. Additionally, no work has been done to support ports, work is needed for this. This also means no newer gcc can yet be used. However, gcc's powerpc support has been refactored which would make adding a powerpcspe-freebsd target very easy. Test Plan: This was lightly tested on a RouterBoard RB800 and an AmigaOne A1222 (P1022-based) board, compiled against the new ABI. Base system utilities (/bin/sh, /bin/ls, etc) still function appropriately, the system is able to boot multiuser. Reviewed By: bdrewery, imp Relnotes: yes Differential Revision: https://reviews.freebsd.org/D5683 Notes: svn path=/head/; revision=307761
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