| Commit message (Collapse) | Author | Age | Files | Lines |
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Machine check and critical exceptions are independent of each other, and
can interrupt each other. Since they're asynchronous we cannot trust
that the existing stack pointer (%r1) is correct at time of entry, so
add a private machine check stack separate from the critical exception
stack. As part of this, switch to the STANDARD_CRIT_PROLOG() for
machine check exceptions, and overload the macro to specify the stack to
switch to. Also add a savearea argument to CRIT_SRR_RESTORE() so that
we can restore machine check exception state from the right location.
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Define __WCHAR_WIDTH in sys/_types.h and derive WCHAR_WIDTH from
that, the same way as WCHAR_MIN and WCHAR_MAX, in both <wchar.h>
and <stdint.h> as per C23 §7.31.1 and §7.22.3.4, respectively.
Reviewed by: fuz
Approved by: fuz (mentor)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D59385
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Add a new CPU-family `show pcpu` handler, cpu_db_show_mdpcpu() to dump
CPU-specific PCPU data. Only Book-E is populated for now, but AIM may
be populated later.
These new field prints: save areas, TLB miss nesting, the new critical
stack pointer. All of them have been very useful for debugging very
esoteric bugs, so make them easier to see from DDB, instead of having to
rummage through hex dumps.
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A critical exception, such as a watchdog, can trigger at any time,
including the middle of a standard exception prologue or epilogue, so
GPRs, including %r1 (the stack pointer) cannot be trusted at all.
Instead, use a private stack pointer for critical interrupts. Each CPU
now has its own critical exception stack, with the boot stack in the
bss.
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There are 4 options for e500 watchdog timeout, which may be core- or
even SoC- specific. Add support to tune the behavior via a tunable
(machdep.watchdog_mode). The tunable value is an integer 0-3.
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Reviewed by: fuz
Approved by: fuz (mentor)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D59293
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Bits [0:1] map to "B", the "Segment size selector", and are not part of
the VSID. Correct this mask.
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Reviewed by: fuz
Approved by: fuz (mentor)
MFC after: 1 month
Pull Request: https://github.com/freebsd/freebsd-src/pull/2352
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This reflects what amd64 has, and is needed for using GPUs with large
VRAM.
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Fixes: a7e483ee146a ("vm_phys: Add a sysctl to dump registered fictitious memory ranges")
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I've wanted this a couple of times in the past. Save the memattr in
the fictitious memory segment structure so that we can report it from
the sysctl handler, and add conversion routines for each platform.
Reviewed by: kib
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D58283
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e6500 core supports 14-bit TIDs (16384), while all earlier cores support
only 8 bit TIDs. Dynamically allocate the tidbusy array at bootstrap
time so that it stays in the TLB1, but is sized appropriately for the
core. With MAXCPU of 32, a e6500 tidbusy would be (8 * 32 * 16384), or
4MB for this array, while e5500 would use (8 * 32 * 256), or 64kB.
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Some Book-E cores (at least e6500) can have much larger PID fields, up
to 14 bits. Extend the PID mask space to the full space, and future
changes may take advantage of this extended space.
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Change powerpc64le's long double from 64-bit double to IEEE 754
binary128 (quad, 113-bit mantissa), matching aarch64 and riscv64.
Gated on FreeBSD 16 and powerpc64le only.
Differential Revision: https://reviews.freebsd.org/D57388
Reviewed by: adrian
Relnotes: yes
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The Book-E watchdog is effectively a state machine based around an AND
mask of the timebase register. A single bit (0-63) is watched in the
timebase register, and when it transitions (by counting *or* by
programmatically setting) an exception is triggered. The first
exception triggers a core interrupt. The second is programmable.
In our case, we panic on the first and reset on second.
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Suggested by: kib
Reviewed by: kib, andrew (arm changes)
Sponsored by: AFRL, DARPA
Pull Request: https://ron-dev.freebsd.org/FreeBSD/src/pulls/23
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This function returns a pointer to the top of the kstack.
Reviewed by: kib, andrew (arm changes)
Sponsored by: AFRL, DARPA
Pull Request: https://ron-dev.freebsd.org/FreeBSD/src/pulls/23
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Suggested by: kib
Reviewed by: imp, kib
Discussed with: emaste, jrtc27
Differential Revision: https://reviews.freebsd.org/D56783
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Refactor the common busdma tag setup code into busdma_machdep.c
Locally tested:
* qemu VM, pseries-9 / power9
* qemu VM, pseries-8 / power8
Differential Revision: https://reviews.freebsd.org/D55340
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* Implement the basic tag domain set routine
* Set the domain to the parent domain if provided
This is just plumbing for eventual work to re-allocate things into
the currently configured domain.
Differential Revision: https://reviews.freebsd.org/D55315
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This is a straight port of the code and doesn't yet handle
different implementations (which will be in a subsequent commit.)
Locally tested:
* G5 SMP (2x PPC970mp)
* power8 / power9 pseries QEMU VM
* power8 powernv
Differential Revision: https://reviews.freebsd.org/D55313
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Similar to glibc, define all the stdint.h macros such as `SIZE_MAX`,
`UINT64_C`, etc unconditionally. I.e. no longer check whether
`__STDC_CONSTANT_MACROS` or `__STDC_LIMIT_MACROS` are defined. See also
<https://sourceware.org/bugzilla/show_bug.cgi?id=15366>.
This is part of reverting base 00bee6fcd77f, which reverted an upstream
libc++ commit that eliminated libc++'s stdint.h wrapper header.
Submitted by: Nikolas Klauser <nikolasklauser@berlin.de>
MFC after: 1 week
Reviewed by: imp
Differential Revision: https://reviews.freebsd.org/D56746
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MFC after: 3 days
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Earlier work (40bcad56f - powerpc/pic: Add a PIC_AP_INIT() to
set up AP PIC info) broke booting my dual G5 powermac.
After much digging, jhibbits@ and I discovered that the openpic
implementation for the memory/bus controller used in the G5 CPUs
doesn't implement /all/ of the openpic specification.
Notably it sticks the WHOAMI register in a different location.
This is reading 0x0 back for all the PICs which is .. very not great.
So to restore the previous behaviour, use a quick for now that jhibbits@
can set appropriately to trust WHOAMI.
I've tested this on my dual G5 PPC and it boots/runs fine.
Fixes: 40bcad56f
Reviewed by: jhibbits
Differential Revision: https://reviews.freebsd.org/D56751
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The Freescale MPIC supports up to 2048 IRQs, but since we only build an
array of 768 interrupts in intr_machdep, clamp the max at 512. The most
any Freescale PowerPC chip actually supports is 452 on the T4240, so 512
is sufficient.
As part of this, increase the vector mask to the full openpic vector
mask, and use this limit as the terminator for the dispatch loop,
instead of a hard-coded 255.
Differential Revision: https://reviews.freebsd.org/D56422
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pc_cpuid may not match the PIC's idea of a given CPU. Since openpic
has a WHOAMI register, we can use that to get the PIC's idea of the CPU.
This needs to be done on each AP, so add a PIC_AP_INIT device method so
the PIC can perform any AP-specific initialization at AP bootstrap time.
This fixes SMP on e6500, which is still lacking SMT support.
Differential Revision: https://reviews.freebsd.org/D56421
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Add a new PHYS_TO_DMAP_ADDR that still returns an address for use in
places that only need an address and not a pointer.
Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Add explicit uintptr_t casts to the arguments to these macros so that
the work both with virtual addresses (e.g. vm_offset_t) and pointers.
Drop no-longer-needed casts in various invocations of DMAP_TO_PHYS.
Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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Effort: CHERI upstreaming
Reviewed by: kib
Sponsored by: AFRL, DARPA
Pull Request: https://github.com/freebsd/freebsd-src/pull/2068
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E6500 cores (MMUv2) support all powers-of-2 page sizes from 4k to 1TB,
not just powers of 4. By using the other page sizes (8k, 32k, etc) we
can save on TLB1 space, saving up to ~1/3 of used TLB1 entries.
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kgdb only uses the marked fields from dumppcb for initial frame
reconstruction.
This reverts commit 8f23665fed2fbaf4481359b4d2fcdd7b9feb40e3.
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There are programs that depend on this structure (e.g. kernel debuggers)
that breaks when the ABI changes.
Signed-off-by: Minsoo Choo <minsoochoo0122@proton.me>
Reviewed by: kib
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D55149
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There are no plans to allow multiple sizes of HPT superpages, so just use a
constant for it.
MFC after: 3 weeks
Fixes: 1bc75d77e9 ("powerpc/pmap/oea64: Make PV_LOCK superpage sized")
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Add atomic_set/clear_short/char for doing 8-bit and 16-bit operations
more efficiently on "newer" architectures (POWER7 and later).
Piggybacks on b31abc95eb.
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Signed-off-by: Minsoo Choo <minsoochoo0122@proton.me>
Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/1957
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Signed-off-by: Minsoo Choo <minsoochoo0122@proton.me>
Reviewed by: emaste
Pull Request: https://github.com/freebsd/freebsd-src/pull/1914
(cherry picked from commit 1bfae8b50814697ac12bc8879ad8013e7ffd77b2)
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Define _ALIGNBYTES using sizeof(void *) (no functional change on any
existing architecture) which will allow it to work with CHERI were we
must align things up to capability alignment.
In _ALIGN, replace integer manipulation which does not preserve pointer
provenance with a type and provenance preserving builtin. This requires
modest changes in code which assumes _ALIGN returns an integer, but
those are relatively rare.
Reviewed by: kib, markj
Effort: CHERI upstreaming
Sponsored by: Innovate UK
Differential Revision: https://reviews.freebsd.org/D53947
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On powerpc/powerpc64, sig_atomic_t is an int, but was treated as if
it was a long by <machine/_stdint.h>. This was finally caught by the
unit test added with 4a1c752 / D53831.
Reported by: kib
Reviewed by: kib, imp
Approved by: markj (mentor)
Fixes: c3e289e1ce8c9af8d14e9f727632e22b3bf901f9
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D54026
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The platform-dependent macros are added to the various
_stdint.h headers, those that are always the same are
added directly to _stdint.h.
We may want to move the definitions for WCHAR_* and
WINT_* out of the platform header files as those are
always the same.
Approved by: markj (mentor)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D53830
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For compliance with IOS/IEC 9899:2024 ("C23").
These macros define the width in bits of the basic integer types.
Another new macro, BITINT_MAXWIDTH, is not yet included as I do not
understand what it should be set to. Perhaps it is compiler-specific.
Approved by: markj (mentor)
MFC after: 1 month
Differential Revision: https://reviews.freebsd.org/D53825
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Using kobj allows implementing most PIC functions merely by inheriting
from the parent class. As there are multiple OpenPIC implementations,
this ensures all common hooks go through by default.
Note, this adds the suspend/resume functions to other PICs. This should
be harmless as suspend/resume isn't working on the devices anyway.
Reviewed by: jhibbits
MFC after: 2 weeks
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kexec hasn't been ported to these architectures, yet, so appease the
build with dummy headers.
Sponsored by: Juniper Networks, Inc.
Differential Revision: https://reviews.freebsd.org/D51625
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Reviewed by: jrtc27, markj
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D52626
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Multiple issues existed within the powerpc FP/VSX save/restore functionality,
leading to register corruption and loss of register contents in specific
scenarios involving high signal load and use of both floating point and VSX
instructions.
Issue #1
On little endian systems the PCB used the wrong location for the shadowed
FP register within the larger VSX register. This appears to have been an
attempt to correct issue #2 without understanding how the vector load/store
instructions actually operate.
Issue #2
On little endian systems, the VSX state save/restore routines swapped 32-bit
words within the 64-bit aliased double word for the associated floating point
register. This was due to the use of a word-oriented load/store vs. doubleword
oriented load/store.
Issue #3
The FPU was turned off in the PCB but not in hardware, leading to a potential
race condition if the same thread was scheduled immediately after sigreturn.
The triggering codebase for this is Go, which makes heavy use of signals and
and generates an unusual mix of floating point and VSX assembler. As a result,
when combined with th powerpc lazy FPU restore, a condition was repeatedly hit
whereby the thread was interrupted in FP+VSX mode, then restored in FP only
mode, thus reliably triggering the issues above.
Also clean up the associated asm() style issue flagged by GitHub Actions.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
MFC after: 1 week
Pull Request: https://github.com/freebsd/freebsd-src/pull/1756
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Reviewed by: markj
Sponsored by: The FreeBSD Foundation
MFC after: 1 week
Differential revision: https://reviews.freebsd.org/D47935
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