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* riscv: Use SBI shutdown call to implement RB_POWEROFFJessica Clarke2020-06-081-0/+19
* RISC-V: Check that the DTB doesn't overlap with kernelAlex Richardson2020-06-083-0/+13
* sys/riscv: Remove debug printfsAlex Richardson2020-06-081-2/+0
* RISC-V: handle DTB aligned to less than 2MBAlex Richardson2020-06-081-0/+6
* Remove remnant of arm's ELF trampolineMitchell Horne2020-05-311-21/+1
* Add macros simplifying the fake preload setupMitchell Horne2020-05-281-31/+39
* Fix entering KDB with dtrace-enabled kernel.Ruslan Bukin2020-05-261-4/+3
* copystr(9): Move to deprecate (attempt #2)Conrad Meyer2020-05-251-59/+0
* riscv: Fix pmap_protect for superpagesJessica Clarke2020-05-131-0/+1
* Revert r360944 and r360946 until reported issues can be resolvedConrad Meyer2020-05-121-0/+59
* copystr(9): Move to deprecate [2/2]Conrad Meyer2020-05-111-59/+0
* Use the HSM SBI extension to halt CPUsMitchell Horne2020-05-011-0/+7
* Use the HSM SBI extension to start APsMitchell Horne2020-05-011-1/+21
* Add support for HSM SBI extensionMitchell Horne2020-05-011-0/+25
* Make mpentry independent of _startMitchell Horne2020-05-011-7/+17
* Improve MACHINE_ARCH handling for hard vs soft-float on RISC-V.John Baldwin2020-04-271-0/+13
* RISC-V: provide the correct value for kernstartMitchell Horne2020-04-191-1/+1
* RISC-V: exclude reserved memory regionsMitchell Horne2020-04-191-0/+25
* RISC-V: use physmem to manage physical memoryMitchell Horne2020-04-192-123/+15
* riscv: Add semicolon missing from r359672Jessica Clarke2020-04-061-1/+1
* RISC-V: copy the DTB to early KVAMitchell Horne2020-04-064-23/+43
* riscv: Make sure local hart's icache is synced in pmap_sync_icacheJessica Clarke2020-04-061-2/+9
* riscv: Fix pmap_fault_fixup for L3 pagesJessica Clarke2020-04-061-1/+1
* Retire procfs-based process debugging.John Baldwin2020-04-011-1/+0
* Remove the secondary_stacks array in arm64 and riscv kernels.Mark Johnston2020-03-242-16/+48
* Fix ordering of machine includesMitchell Horne2020-03-221-5/+3
* [PowerPC][Book-E] Fix missing load base in elf_cpu_parse_dynamic().Brandon Bergren2020-03-181-1/+1
* Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many)Pawel Biernacki2020-02-262-4/+5
* Only compile clear_fpu state code when we're building with options FPE.Warner Losh2020-02-241-1/+1
* Implement vm.pmap.kernel_maps for RISC-VMitchell Horne2020-02-121-0/+168
* RISC-V: un-ifdef vm.kvm_size and vm.kvm_freeMitchell Horne2020-02-121-6/+6
* Use the context created in makectx() for stack traces.John Baldwin2020-02-062-10/+7
* Fix DDB to unwind across exception frames.John Baldwin2020-02-061-10/+32
* Use csr_read() to read sstatus instead of inline assembly.John Baldwin2020-02-051-8/+4
* Remove stale workaround for the htif console.John Baldwin2020-02-051-14/+0
* Add stricter checks on user changes to SSTATUS.John Baldwin2020-01-311-4/+15
* Reimplement stack capture of running threads on i386 and amd64.Mark Johnston2020-01-311-11/+9
* Trim duplicate CSR swaps from user exceptions.John Baldwin2020-01-301-2/+0
* Remove unused fields from struct pcb.John Baldwin2020-01-302-5/+0
* Check for invalid sstatus values in set_mcontext().John Baldwin2020-01-171-10/+8
* Save and restore floating point registers in get/set_mcontext().John Baldwin2020-01-171-5/+5
* RISC-V: fix global pointer assignment at bootMitchell Horne2020-01-171-12/+17
* Use unsigned loads in fubyte, fuword16, generic_bs_r_1, generic_bs_r_2Ruslan Bukin2020-01-172-6/+6
* RISC-V: fix global symbol lookups for mpentry with lldMitchell Horne2020-01-131-4/+4
* Replace inline assembly with rdtime macroMitchell Horne2020-01-101-4/+2
* Work around lld's inability to handle undefined weak symbols on risc-v.John Baldwin2020-01-071-10/+10
* riscv: Remove unused variableKristof Provost2019-12-311-1/+1
* riscv: Remove pointless loopKristof Provost2019-12-311-6/+1
* Don't hard-code field offsets of struct riscv_bootparams.Ruslan Bukin2019-12-302-5/+11
* Don't hard-code size of struct riscv_bootparams.Ruslan Bukin2019-12-302-1/+4
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