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* riscv: Add semicolon missing from r359672Jessica Clarke2020-04-061-1/+1
* RISC-V: copy the DTB to early KVAMitchell Horne2020-04-067-24/+80
* riscv: Make sure local hart's icache is synced in pmap_sync_icacheJessica Clarke2020-04-061-2/+9
* riscv: Fix pmap_fault_fixup for L3 pagesJessica Clarke2020-04-061-1/+1
* riscv/sifive: add FE310 Always-on driverNick O'Brien2020-04-022-0/+319
* Retire procfs-based process debugging.John Baldwin2020-04-011-1/+0
* Remove the secondary_stacks array in arm64 and riscv kernels.Mark Johnston2020-03-242-16/+48
* Fix ordering of machine includesMitchell Horne2020-03-221-5/+3
* [PowerPC][Book-E] Fix missing load base in elf_cpu_parse_dynamic().Brandon Bergren2020-03-181-1/+1
* fuspi: silence build warning, plug resource leakPhilip Paeps2020-03-091-3/+1
* riscv: Add a GENERIC-NODEBUG (copied from amd64)Brooks Davis2020-02-271-0/+42
* Better check for floating point type.Warner Losh2020-02-271-3/+10
* Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many)Pawel Biernacki2020-02-262-4/+5
* Add a soft-float riscv kernel configWarner Losh2020-02-241-0/+9
* Only compile clear_fpu state code when we're building with options FPE.Warner Losh2020-02-241-1/+1
* riscv: Set MACHINE_ARCH correctlyKristof Provost2020-02-221-0/+4
* Implement vm.pmap.kernel_maps for RISC-VMitchell Horne2020-02-121-0/+168
* RISC-V: un-ifdef vm.kvm_size and vm.kvm_freeMitchell Horne2020-02-121-6/+6
* Store offset into zpcpu allocations in the per-cpu area.Mateusz Guzik2020-02-121-1/+1
* Use the context created in makectx() for stack traces.John Baldwin2020-02-062-10/+7
* Fix DDB to unwind across exception frames.John Baldwin2020-02-061-10/+32
* Fix EXCP_MASK to include all relevant bits from scause.John Baldwin2020-02-051-2/+1
* Use csr_read() to read sstatus instead of inline assembly.John Baldwin2020-02-051-8/+4
* Remove stale workaround for the htif console.John Baldwin2020-02-051-14/+0
* Read the breakpoint instruction to determine its length in BKPT_SKIP.John Baldwin2020-02-051-2/+8
* Define MAXCPU consistently between the kernel and KLDs.Mark Johnston2020-02-051-2/+2
* prci: register tlclk as a fixed clockMitchell Horne2020-02-011-0/+22
* prci: fix up compatMitchell Horne2020-02-011-2/+9
* prci: register the DDR and GEMGX PLLsMitchell Horne2020-02-011-15/+45
* Add stricter checks on user changes to SSTATUS.John Baldwin2020-01-311-4/+15
* Fix 64-bit value of SSTATUS_SD to use an unsigned long.John Baldwin2020-01-311-3/+6
* Reimplement stack capture of running threads on i386 and amd64.Mark Johnston2020-01-311-11/+9
* Trim duplicate CSR swaps from user exceptions.John Baldwin2020-01-301-2/+0
* Remove unused fields from struct pcb.John Baldwin2020-01-304-9/+1
* Fix definition of SSTATUS_SDMitchell Horne2020-01-291-2/+5
* Include the PCI stack to the riscv GENERIC kernel.Ruslan Bukin2020-01-241-0/+3
* Enable NEW_PCIB on riscv.Ruslan Bukin2020-01-242-0/+5
* Check for invalid sstatus values in set_mcontext().John Baldwin2020-01-171-10/+8
* Save and restore floating point registers in get/set_mcontext().John Baldwin2020-01-171-5/+5
* RISC-V: fix global pointer assignment at bootMitchell Horne2020-01-171-12/+17
* Use unsigned loads in fubyte, fuword16, generic_bs_r_1, generic_bs_r_2Ruslan Bukin2020-01-172-6/+6
* RISC-V: fix global symbol lookups for mpentry with lldMitchell Horne2020-01-131-4/+4
* Replace inline assembly with rdtime macroMitchell Horne2020-01-101-4/+2
* Work around lld's inability to handle undefined weak symbols on risc-v.John Baldwin2020-01-071-10/+10
* sifive: Fix incorrect tx/rx ctrl definesKristof Provost2020-01-071-2/+2
* riscv: Remove unused variableKristof Provost2019-12-311-1/+1
* sifive: uart driverKristof Provost2019-12-312-0/+544
* riscv: Remove pointless loopKristof Provost2019-12-311-6/+1
* Don't hard-code field offsets of struct riscv_bootparams.Ruslan Bukin2019-12-302-5/+11
* Don't hard-code size of struct riscv_bootparams.Ruslan Bukin2019-12-302-1/+4