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* Remove sparc64 kernel supportWarner Losh2020-02-031-138/+0
| | | | | | | | | Remove all sparc64 specific files Remove all sparc64 ifdefs Removee indireeect sparc64 ifdefs Notes: svn path=/head/; revision=357455
* Introduce vm_page_astate.Mark Johnston2019-12-101-1/+1
| | | | | | | | | | | | | | | | | This is a 32-bit structure embedded in each vm_page, consisting mostly of page queue state. The use of a structure makes it easy to store a snapshot of a page's queue state in a stack variable and use cmpset loops to update that state without requiring the page lock. This change merely adds the structure and updates references to atomic state fields. No functional change intended. Reviewed by: alc, jeff, kib Sponsored by: Netflix, Intel Differential Revision: https://reviews.freebsd.org/D22650 Notes: svn path=/head/; revision=355586
* Port r353622 to sparc64 and arm v4.Konstantin Belousov2019-10-161-0/+1
| | | | | | | | | | Noted by: alc Reviewed by: alc, jeff, markj Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D22056 Notes: svn path=/head/; revision=353664
* Move phys_avail definition into MI code. It is consumed in the MI layer andJeff Roberson2019-08-161-1/+0
| | | | | | | | | | | doing so adds more flexibility with less redundant code. Reviewed by: jhb, markj, kib Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D21250 Notes: svn path=/head/; revision=351108
* Add kernel support for Intel userspace protection keys feature onKonstantin Belousov2019-02-201-0/+7
| | | | | | | | | | | | | | | | Skylake Xeons. See SDM rev. 68 Vol 3 4.6.2 Protection Keys and the description of the RDPKRU and WRPKRU instructions. Reviewed by: markj Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Differential revision: https://reviews.freebsd.org/D18893 Notes: svn path=/head/; revision=344353
* sys: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-201-0/+2
| | | | | | | | | | | | | | | | | Mainly focus on files that use BSD 3-Clause license. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Special thanks to Wind River for providing access to "The Duke of Highlander" tool: an older (2014) run over FreeBSD tree was useful as a starting point. Notes: svn path=/head/; revision=326023
* Renumber copyright clause 4Warner Losh2017-02-281-1/+1
| | | | | | | | | | | | Renumber cluase 4 to 3, per what everybody else did when BSD granted them permission to remove clause 3. My insistance on keeping the same numbering for legal reasons is too pedantic, so give up on that point. Submitted by: Jan Schaumann <jschauma@stevens.edu> Pull Request: https://github.com/freebsd/freebsd/pull/96 Notes: svn path=/head/; revision=314436
* Remove unused member.Attilio Rao2013-08-041-1/+0
| | | | | | | | | Sponsored by: EMC / Isilon storage division Reviewed by: alc Tested by: pho Notes: svn path=/head/; revision=253940
* Rework the known rwlock to benefit about staying on their ownAttilio Rao2012-11-031-7/+1
| | | | | | | | | | cache line in order to avoid manual frobbing but using struct rwlock_padalign. Reviewed by: alc, jimharris Notes: svn path=/head/; revision=242534
* Merge r236494 from x86:Marius Strobl2012-08-051-1/+7
| | | | | | | | | | Isolate the global TTE list lock from data and other locks to prevent false sharing within the cache. MFC after: 3 days Notes: svn path=/head/; revision=239079
* The page flag PGA_WRITEABLE is set and cleared exclusively by the pmapAlan Cox2012-06-161-0/+1
| | | | | | | | | | | | | | | | | | | layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks Notes: svn path=/head/; revision=237168
* Replace all uses of the vm page queues lock by a r/w lock that is privateAlan Cox2012-05-291-0/+2
| | | | | | | | | | | | | | | | to this pmap.c. This new r/w lock is used primarily to synchronize access to the TTE lists. However, it will be used in a somewhat unconventional way. As finer-grained TTE list locking is added to each of the pmap functions that acquire this r/w lock, its acquisition will be changed from write to read, enabling concurrent execution of the pmap functions with finer-grained locking. Reviewed by: attilio Tested by: flo MFC after: 10 days Notes: svn path=/head/; revision=236214
* - pmap_cache_remove() and pmap_protect_tte() are only used within pmap.cMarius Strobl2011-07-051-3/+0
| | | | | | | | so static'ize them. - Correct a typo. Notes: svn path=/head/; revision=223800
* Add sparc64 support.Attilio Rao2011-05-061-1/+2
| | | | | | | Compiled (and helped) by: pluknet Notes: svn path=/projects/largeSMP/; revision=221554
* Remove pmap fields that are either unused or not fully implemented.Alan Cox2011-02-171-2/+0
| | | | | | | Discussed with: kib Notes: svn path=/head/; revision=218773
* On UltraSPARC-III+ and greater take advantage of ASI_ATOMIC_QUAD_LDD_PHYS,Marius Strobl2010-12-291-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which takes an physical address instead of an virtual one, for loading TTEs of the kernel TSB so we no longer need to lock the kernel TSB into the dTLB, which only has a very limited number of lockable dTLB slots. The net result is that we now basically can handle a kernel TSB of any size and no longer need to limit the kernel address space based on the number of dTLB slots available for locked entries. Consequently, other parts of the trap handlers now also only access the the kernel TSB via its physical address in order to avoid nested traps, as does the PMAP bootstrap code as we haven't taken over the trap table at that point, yet. Apart from that the kernel TSB now is accessed via a direct mapping when we are otherwise taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS so no further code changes are needed. Most of this is implemented by extending the patching of the TSB addresses and mask as well as the ASIs used to load it into the trap table so the runtime overhead of this change is rather low. Currently the use of ASI_ATOMIC_QUAD_LDD_PHYS is not yet enabled on SPARC64 CPUs due to lack of testing and due to the fact it might require minor adjustments there. Theoretically it should be possible to use the same approach also for the user TSB, which already is not locked into the dTLB, avoiding nested traps. However, for reasons I don't understand yet OpenSolaris only does that with SPARC64 CPUs. On the other hand I think that also addressing the user TSB physically and thus avoiding nested traps would get us closer to sharing this code with sun4v, which only supports trap level 0 and 1, so eventually we could have a single kernel which runs on both sun4u and sun4v (as does Linux and OpenBSD). Developed at and committed from: 27C3 Notes: svn path=/head/; revision=216803
* Update various places that store or manipulate CPU masks to use cpumask_tJohn Baldwin2010-08-111-1/+1
| | | | | | | | instead of int or u_int. Since cpumask_t is currently u_int on all platforms this should just be a cosmetic change. Notes: svn path=/head/; revision=211197
* On Alan's advice, rather than do a wholesale conversion on a singleKip Macy2010-04-301-0/+2
| | | | | | | | | | | | | | | architecture from page queue lock to a hashed array of page locks (based on a patch by Jeff Roberson), I've implemented page lock support in the MI code and have only moved vm_page's hold_count out from under page queue mutex to page lock. This changes pmap_extract_and_hold on all pmaps. Supported by: Bitgravity Inc. Discussed with: alc, jeffr, and kib Notes: svn path=/head/; revision=207410
* Some machines can not only consist of CPUs running at different speedsMarius Strobl2010-02-201-1/+1
| | | | | | | | | | | | but also of different types, f.e. Sun Fire V890 can be equipped with a mix of UltraSPARC IV and IV+ CPUs, requiring different MMU initialization and different workarounds for model specific errata. Therefore move the CPU implementation number from a global variable to the per-CPU data. Functions which are called before the latter is available are passed the implementation number as a parameter now. Notes: svn path=/head/; revision=204152
* Add support to the virtual memory system for configuring machine-Alan Cox2009-07-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib) Notes: svn path=/head/; revision=195649
* - Work around the broken loader behavior of not demapping no longerMarius Strobl2009-06-281-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | used kernel TLB slots when unloading the kernel or modules, which results in havoc when loading a kernel and modules which take up less TLB slots afterwards as the unused but locked ones aren't accounted for in virtual_avail. Eventually this should be fixed in the loader which isn't straight forward though and the kernel should be robust against this anyway. [1] - Ensure that the addresses allocated directly from phys_avail[] by pmap_bootstrap_alloc() are always colored properly. This implicit assumption was broken in r194784 as unlike the other consumers the DPCPU area allocated for the BSP isn't a multiple of PAGE_SIZE * DCACHE_COLORS. [2] - Remove the no longer used global msgbuf_phys. - Remove the redundant ekva parameter of pmap_bootstrap_alloc(). - Correct some outdated function names in ktr(9) invocations. Requested by: jhb [1] Reported by: gavin [2] Approved by: re (kib) MFC after: 2 weeks Notes: svn path=/head/; revision=195149
* Add pmap_clear_write() to the interface between the virtual memoryAlan Cox2006-07-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | system's machine-dependent and machine-independent layers. Once pmap_clear_write() is implemented on all of our supported architectures, I intend to replace all calls to pmap_page_protect() by calls to pmap_clear_write(). Why? Both the use and implementation of pmap_page_protect() in our virtual memory system has subtle errors, specifically, the management of execute permission is broken on some architectures. The "prot" argument to pmap_page_protect() should behave differently from the "prot" argument to other pmap functions. Instead of meaning, "give the specified access rights to all of the physical page's mappings," it means "don't take away the specified access rights from all of the physical page's mappings, but do take away the ones that aren't specified." However, owing to our i386 legacy, i.e., no support for no-execute rights, all but one invocation of pmap_page_protect() specifies VM_PROT_READ only, when the intent is, in fact, to remove only write permission. Consequently, a faithful implementation of pmap_page_protect(), e.g., ia64, would remove execute permission as well as write permission. On the other hand, some architectures that support execute permission have basically ignored whether or not VM_PROT_EXECUTE is passed to pmap_page_protect(), e.g., amd64 and sparc64. This change represents the first step in replacing pmap_page_protect() by the less subtle pmap_clear_write() that is already implemented on amd64, i386, and sparc64. Discussed with: grehan@ and marcel@ Notes: svn path=/head/; revision=160525
* MFalpha/amd64/arm/ia64Alan Cox2006-05-291-9/+0
| | | | | | | | | | Retire pmap_track_modified(). We no longer need it because we do not create managed mappings within the clean submap. To prevent regressions, add assertions blocking the creation of managed mappings within the clean submap. Notes: svn path=/head/; revision=159031
* - Cleanup whitespace and extra ()s in vtophys() macros.John Baldwin2005-12-061-1/+1
| | | | | | | | | | | | | | - Move vtophys() macros next to vtopte() where vtopte() exists to match comments above vtopte(). - Remove references to the alternate address space in the comment above vtopte(). amd64 never had the alternate address space, and i386 lost it prior to PAE support being added. - s/entires/entries/ in comments. Reviewed by: alc Notes: svn path=/head/; revision=153179
* Silence witness warnings about duplicate pmap lock emitted sinceMarius Strobl2005-02-181-1/+1
| | | | | | | | | rev. 1.145 of sys/sparc64/sparc64/pmap.c. Submitted by: alc Notes: svn path=/head/; revision=142045
* /* -> /*- for license, minor formatting changesWarner Losh2005-01-071-1/+1
| | | | Notes: svn path=/head/; revision=139825
* Add pmap locking to many of the functions.Alan Cox2004-08-101-0/+14
| | | | | | | | | | | | | | | | Implement the protection check required by the pmap_extract_and_hold() specification. Remove the acquisition and release of Giant from pmap_extract_and_hold() and pmap_protect(). Many thanks to Ken Smith for resolving a sparc64-specific initialization problem in my original patch. Tested by: kensmith@ Notes: svn path=/head/; revision=133451
* Correct the implementation of pmap_page_is_mapped(): It should return TRUEAlan Cox2004-05-091-2/+1
| | | | | | | only if the page has one or more managed mappings. Notes: svn path=/head/; revision=129068
* Remove avail_end. It is not used.Alan Cox2004-04-111-1/+0
| | | | Notes: svn path=/head/; revision=128103
* Remove advertising clause from University of California Regent'sWarner Losh2004-04-071-4/+0
| | | | | | | | | | license, per letter dated July 22, 1999 and email from Peter Wemm, Alan Cox and Robert Watson. Approved by: core, peter, alc, rwatson Notes: svn path=/head/; revision=127977
* Remove avail_start on those platforms that no longer use it. (Only amd64Alan Cox2004-04-051-1/+0
| | | | | | | does anything with it beyond simple initialization.) Notes: svn path=/head/; revision=127875
* Move pmap_resident_count() from the MD pmap.h to the MI pmap.h.Bruce M Simpson2003-10-061-1/+0
| | | | | | | | | | | Add a definition of pmap_wired_count(). Add a definition of vmspace_wired_count(). Reviewed by: truckman Discussed with: peter Notes: svn path=/head/; revision=120831
* - Move the routine for flushing all user mappings from the tlb from pmap toJake Burkholder2003-04-131-1/+0
| | | | | | | | | | | | | | | the cpu dependent files. It will need to be done differently for USIII. - Simplify the logic for detecting context rollovers. Instead of dealing with it when the next context switch would cause the context numbers to rollover, deal with it when they actually do rollover. - Move some things around in cpu_switch so that we only do 1 membar #Sync when switching address space, instead of 2. - Detect kernel threads by comparing the new vm space to vmspace0, instead if checking if the tlb context is 0. - Removed some debug code. Notes: svn path=/head/; revision=113453
* Use vm_paddr_t for physical addresses.Jake Burkholder2003-04-081-7/+7
| | | | Notes: svn path=/head/; revision=113238
* Make the pmap stats writeable. It can be useful to clear them.Jake Burkholder2003-04-061-1/+1
| | | | Notes: svn path=/head/; revision=113171
* - Remove unused cache flushing routines. These will not necessary workJake Burkholder2003-03-191-7/+1
| | | | | | | | | | | | | | | | | | | | | | on future UltraSPARC cpus for which the data cache is not direct mapped. - Move UltraSPARC I and II (spitfire, blackbird, sapphire, sabre) specific functions to spitfire.c, and add cheetah.c for UltraSPARC III specific functions. Initially just cache flushing, but there are a few other functions that will need to move here. - Add an ipi handler for data cache flushing on UltraSPARC III. - Use function pointers to select the right cache flushing functions based on cpu_impl. With this it is possible to boot single user from an mfs root on UltraSPARC III systems, including spinning up secondary processors. There is currently no support for the host to pci bridge, and no documentation for it is publically available. Thanks to Oleg Derevenetz for providing access to a system with UltraSPARC III+ cpus. Notes: svn path=/head/; revision=112399
* Made the prototypes for pmap_kenter and pmap_kremove MD. These functionsJake Burkholder2003-03-161-0/+2
| | | | | | | | | | | | are machine dependent because they are not required to update the tlb when mappings are added or removed, and doing so is machine dependent. In addition, an implementation may require that pages mapped with pmap_kenter have a backing vm_page_t, which is not necessarily true of all physical pages, and so may choose to pass the vm_page_t to pmap_kenter instead of the physical address in order to make this requirement clear. Notes: svn path=/head/; revision=112312
* - Reorganize PMAP_STATS to scale a little better.Jake Burkholder2003-01-051-0/+19
| | | | | | | - Add some more stats for things that are now considered interesting. Notes: svn path=/head/; revision=108700
* - Add a pmap pointer to struct md_page, and use this to find the pmap thatJake Burkholder2002-12-211-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | a mapping belongs to by setting it in the vm_page_t structure that backs the tsb page that the tte for a mapping is in. This allows the pmap that a mapping belongs to to be found without keeping a pointer to it in the tte itself. - Remove the pmap pointer from struct tte and use the space to make the tte pv lists doubly linked (TAILQs), like on other architectures. This makes entering or removing a mapping O(1) instead of O(n) where n is the number of pmaps a page is mapped by (including kernel_pmap). - Use atomic ops for setting and clearing bits in the ttes, now that they return the old value and can be easily used for this purpose. - Use __builtin_memset for zeroing ttes instead of bzero, so that gcc will inline it (4 inline stores using %g0 instead of a function call). - Initially set the virtual colour for all the vm_page_ts to be equal to their physical colour. This will be more useful once uma_small_alloc is implemented, but basically pages with virtual colour equal to phsyical colour are easier to handle at the pmap level because they can be safely accessed through cachable direct virtual to physical mappings with that colour, without fear of causing illegal dcache aliases. In total these changes give a minor performance improvement, about 1% reduction in system time during buildworld. Notes: svn path=/head/; revision=108166
* Removed unused pmap_qenter_flags.Jake Burkholder2002-12-211-1/+0
| | | | Notes: svn path=/head/; revision=108155
* Move pmap_collect() out of the machine-dependent code, rename itAlan Cox2002-11-131-2/+0
| | | | | | | | | | | to reflect its new location, and add page queue and flag locking. Notes: (1) alpha, i386, and ia64 had identical implementations of pmap_collect() in terms of machine-independent interfaces; (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. Notes: svn path=/head/; revision=106838
* - Clear the page's PG_WRITEABLE flag in the i386's pmap_changebit()Alan Cox2002-11-111-2/+0
| | | | | | | | | if we're removing write access from the page's PTEs. - Export pmap_remove_all() on alpha, i386, and ia64. (It's already exported on sparc64.) Notes: svn path=/head/; revision=106753
* Add needed include of queue.h.Jake Burkholder2002-10-011-0/+1
| | | | Notes: svn path=/head/; revision=104265
* Minor style. Removed unused declaration.Jake Burkholder2002-08-161-2/+1
| | | | Notes: svn path=/head/; revision=101957
* o Introduce pmap_page_is_mapped(). Its purpose is to obsoleteAlan Cox2002-08-071-0/+1
| | | | | | | the PG_MAPPED flag. Notes: svn path=/head/; revision=101479
* Forgot to commit this.Jake Burkholder2002-08-011-2/+2
| | | | | | | Spotted by: scottl Notes: svn path=/head/; revision=101186
* Implement a direct mapped address region, like alpha and ia64. ThisJake Burkholder2002-07-271-0/+1
| | | | | | | | | | | | | | | | | | basically maps all of physical memory 1:1 to a range of virtual addresses outside of normal kva. The advantage of doing this instead of accessing phsyical addresses directly is that memory accesses will go through the data cache, and will participate in the normal cache coherency algorithm for invalidating lines in our own and in other cpus' data caches. So we don't have to flush the cache manually or send IPIs to do so on other cpus. Also, since the mappings never change, we don't have to flush them from the tlb manually. This makes pmap_copy_page and pmap_zero_page MP safe, allowing the idle zero proc to run outside of giant. Inspired by: ia64 Notes: svn path=/head/; revision=100771
* pmap_kremove can no longer be used to remove the magic device mappingsJake Burkholder2002-06-251-0/+1
| | | | | | | | | | installed with pmap_kenter_flags, since the physical addresses may not have an associated vm_page. Add a function to do this. Tested by: Tomi Vainio <Tomi.Vainio@Sun.COM> Notes: svn path=/head/; revision=98813
* Add an MD page flag for tracking if a page is cacheable or not, so thatJake Burkholder2002-05-291-0/+3
| | | | | | | | we don't flush all mappings of a physical page in order to make it virtually cachable again, if it is already cachable. Notes: svn path=/head/; revision=97449
* Merge the code in pv.c into pmap.c directly. Place all page mappings ontoJake Burkholder2002-05-291-0/+9
| | | | | | | | | | | | | the pv lists in the vm_page, even unmanaged kernel mappings. This is so that the virtual cachability of these mappings can be tracked when a page is mapped to more than one virtual address. All virtually cachable mappings of a physical page must have the same virtual colour, or illegal alises can be created in the data cache. This is a bit tricky because we still have to recognize managed and unmanaged mappings, even though they are all on the pv lists. Notes: svn path=/head/; revision=97447
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