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* sys: further adoption of SPDX licensing ID tags.Pedro F. Giffuni2017-11-2020-0/+40
* spdx: initial adoption of licensing ID tags.Pedro F. Giffuni2017-11-182-0/+4
* Add Intel Processor Trace registers for:Ruslan Bukin2017-11-171-0/+52
* Remove i386 XBOX support.Konstantin Belousov2017-11-161-1/+0
* Add Intel Processor Trace (PT) MSRs.Ruslan Bukin2017-11-121-0/+56
* Correct operators precedence.Konstantin Belousov2017-11-091-5/+5
* Replace manyinstances of VM_WAIT with blocking page allocation flagsJeff Roberson2017-11-081-6/+3
* Add AT_HWCAP2 ELF auxiliary vector.Michal Meloun2017-10-211-2/+4
* x86: Decode AMD "Extended Feature Extensions ID EBX" bitsConrad Meyer2017-09-203-0/+20
* MCA: Expand AMD Thresholding support to cover all banksConrad Meyer2017-09-172-55/+68
* Add AT_EHDRFLAGS and AT_HWCAP on amd64.John Baldwin2017-09-141-1/+3
* Add AT_HWCAP and AT_EHDRFLAGS on all platforms.John Baldwin2017-09-141-1/+3
* MCA: Rename AMD MISC bits/masksConrad Meyer2017-09-112-36/+36
* x86 MCA: Extract CMCI support predicate into functionConrad Meyer2017-09-111-3/+15
* Fix ioapic acpi id matching on PCI attach and rid calculation.Konstantin Belousov2017-09-111-4/+4
* Decode new AMD SVM feature bits on family 17hConrad Meyer2017-09-111-1/+19
* Enhance qpi.c to make it usable on all Core-microarchitecture Xeons.Konstantin Belousov2017-09-081-15/+27
* Use IOAPIC PCI rid as the interrupt TLP source id for DMAR interruptKonstantin Belousov2017-09-081-5/+21
* Add an ioapic_get_rid() function to obtain PCIe TLP requester-id forKonstantin Belousov2017-09-082-1/+96
* Add a constant specifying the min size of the IOAPIC registers window.Konstantin Belousov2017-09-081-0/+2
* Consistently use tabs for indent.Konstantin Belousov2017-09-081-7/+7
* mca: Fix printf types from r323289 on i386Conrad Meyer2017-09-081-3/+5
* x86 MCA: Helpfully, print why ECC thresholding is not enabled on AMDConrad Meyer2017-09-071-4/+15
* x86 MCA: Enable AMD thresholding support on 17hConrad Meyer2017-09-072-2/+15
* Store AMD RAS Capabilities cpuid value and name flagsConrad Meyer2017-09-073-0/+12
* cpufreq(4) hwpstate: Yield CPU awaiting frequency changeConrad Meyer2017-09-071-6/+8
* Fix typos. Stop claiming that two children are created.Konstantin Belousov2017-09-061-3/+3
* acpi/srat: zero the SRAT cpu arrayRoger Pau Monné2017-09-041-0/+1
* Stop masking FSGSBASE and SMEP features under monitors.Konstantin Belousov2017-08-241-7/+4
* Fix off-by-one error when parsing SRAT table.Alexander Motin2017-08-221-1/+1
* subr_smp: Clean up topology analysis, add additional layersConrad Meyer2017-08-221-17/+30
* hwpstate: Add support for family 17h pstate info from MSRsConrad Meyer2017-08-201-0/+13
* Discover CPU topology on multi-die AMD Zen systemsConrad Meyer2017-08-171-4/+29
* Fix unused varable warning in !SMP caseConrad Meyer2017-08-171-0/+2
* x86: Add dynamic interrupt rebalancingConrad Meyer2017-08-161-7/+139
* srat: use pmap_unmapbiosRoger Pau Monné2017-08-131-1/+1
* Stop calling atrtc_set() from the xen timer clock_settime() method. ThatIan Lepore2017-08-111-1/+1
* acpi/srat: fix build without DMAPRoger Pau Monné2017-08-111-1/+10
* mptable: fix i386 build failureRoger Pau Monné2017-08-102-1/+12
* x86: bump MAX_APIC_ID to 512Roger Pau Monné2017-08-104-13/+29
* x86: make the arrays that depend on MAX_APIC_ID dynamicRoger Pau Monné2017-08-106-21/+75
* apic_enumerator: only set mp_ncpus and mp_maxid at probe cpus phaseRoger Pau Monné2017-08-107-13/+83
* Split identify_cpu() into two functions for amd64 as we do for i386. ThisJung-uk Kim2017-08-092-13/+15
* Detect hypervisors early. We used to set lower hz on hypervisors by defaultJung-uk Kim2017-08-052-2/+2
* Don't trace running threads that have interrupts disabled.Mark Johnston2017-07-311-3/+4
* __pcpu: gcc -Wredundant-declsRyan Libby2017-07-211-2/+0
* Protect access to the AT realtime clock with its own mutex.Ian Lepore2017-07-121-0/+14
* Clean up MD pollution of bus_dma.h:Jason A. Harmening2017-07-015-143/+190
* Fix batched unload for DMAR busdma in qi mode.Konstantin Belousov2017-06-193-34/+25
* Don't try to assign interrupts to a CPU on single-CPU systems.John Baldwin2017-06-141-1/+5
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