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/*-
* Copyright (c) 2011 Robert N. M. Watson
* All rights reserved.
*
* This software was developed by SRI International and the University of
* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
* ("CTSRD"), as part of the DARPA CRASH research programme.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MIPS_H_
#define _MIPS_H_
/*
* 64-bit MIPS types.
*/
#if 0
typedef unsigned long register_t; /* 64-bit MIPS register */
#endif
typedef unsigned long paddr_t; /* Physical address */
typedef unsigned long vaddr_t; /* Virtual address */
#if 0
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long uint64_t;
#endif
/*
* MIPS address space layout.
*/
#define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000
#define MIPS_XKPHYS_CACHED_NC_BASE 0x9800000000000000
static inline vaddr_t
mips_phys_to_cached(paddr_t phys)
{
return (phys | MIPS_XKPHYS_CACHED_NC_BASE);
}
static inline vaddr_t
mips_phys_to_uncached(paddr_t phys)
{
return (phys | MIPS_XKPHYS_UNCACHED_BASE);
}
/*
* Endian conversion routines for use in I/O -- most Altera devices are little
* endian, but our processor is big endian.
*/
static inline uint16_t
byteswap16(uint16_t v)
{
return ((v & 0xff00) >> 8 | (v & 0xff) << 8);
}
static inline uint32_t
byteswap32(uint32_t v)
{
return ((v & 0xff000000) >> 24 | (v & 0x00ff0000) >> 8 |
(v & 0x0000ff00) << 8 | (v & 0x000000ff) << 24);
}
/*
* MIPS simple I/O routines -- arguments are virtual addresses so that the
* caller can determine required caching properties.
*/
static inline uint8_t
mips_ioread_uint8(vaddr_t vaddr)
{
uint8_t v;
__asm__ __volatile__ ("lb %0, 0(%1)" : "=r" (v) : "r" (vaddr));
return (v);
}
static inline void
mips_iowrite_uint8(vaddr_t vaddr, uint8_t v)
{
__asm__ __volatile__ ("sb %0, 0(%1)" : : "r" (v), "r" (vaddr));
}
static inline uint32_t
mips_ioread_uint32(vaddr_t vaddr)
{
uint32_t v;
__asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr));
return (v);
}
static inline void
mips_iowrite_uint32(vaddr_t vaddr, uint32_t v)
{
__asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr));
}
/*
* Little-endian versions of 32-bit I/O routines.
*/
static inline uint32_t
mips_ioread_uint32le(vaddr_t vaddr)
{
return (byteswap32(mips_ioread_uint32(vaddr)));
}
static inline void
mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v)
{
mips_iowrite_uint32(vaddr, byteswap32(v));
}
/*
* Coprocessor 0 interfaces.
*/
static inline register_t
cp0_count_get(void)
{
register_t count;
__asm__ __volatile__ ("dmfc0 %0, $9" : "=r" (count));
return (count);
}
#endif
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