1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
|
/*-
* Copyright (c) 2006 Benno Rice.
* Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
* All rights reserved.
*
* Adapted and extended to Marvell SoCs by Semihalf.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
struct mv_ic_softc {
struct resource * ic_res[1];
bus_space_tag_t ic_bst;
bus_space_handle_t ic_bsh;
int ic_high_regs;
int ic_error_regs;
};
static struct resource_spec mv_ic_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
};
static struct mv_ic_softc *mv_ic_sc = NULL;
static int mv_ic_probe(device_t);
static int mv_ic_attach(device_t);
uint32_t mv_ic_get_cause(void);
uint32_t mv_ic_get_mask(void);
void mv_ic_set_mask(uint32_t);
uint32_t mv_ic_get_cause_hi(void);
uint32_t mv_ic_get_mask_hi(void);
void mv_ic_set_mask_hi(uint32_t);
uint32_t mv_ic_get_cause_error(void);
uint32_t mv_ic_get_mask_error(void);
void mv_ic_set_mask_error(uint32_t);
static void arm_mask_irq_all(void);
static int
mv_ic_probe(device_t dev)
{
device_set_desc(dev, "Marvell Integrated Interrupt Controller");
return (0);
}
static int
mv_ic_attach(device_t dev)
{
struct mv_ic_softc *sc;
uint32_t dev_id, rev_id;
int error;
sc = (struct mv_ic_softc *)device_get_softc(dev);
if (mv_ic_sc != NULL)
return (ENXIO);
mv_ic_sc = sc;
soc_id(&dev_id, &rev_id);
sc->ic_high_regs = 0;
sc->ic_error_regs = 0;
if (dev_id == MV_DEV_88F6281 || dev_id == MV_DEV_MV78100 ||
dev_id == MV_DEV_MV78100_Z0)
sc->ic_high_regs = 1;
if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
sc->ic_error_regs = 1;
error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
/* Mask all interrupts */
arm_mask_irq_all();
return (0);
}
static device_method_t mv_ic_methods[] = {
DEVMETHOD(device_probe, mv_ic_probe),
DEVMETHOD(device_attach, mv_ic_attach),
{ 0, 0 }
};
static driver_t mv_ic_driver = {
"ic",
mv_ic_methods,
sizeof(struct mv_ic_softc),
};
static devclass_t mv_ic_devclass;
DRIVER_MODULE(ic, mbus, mv_ic_driver, mv_ic_devclass, 0, 0);
int
arm_get_next_irq(void)
{
int irq;
irq = mv_ic_get_cause() & mv_ic_get_mask();
if (irq)
return (ffs(irq) - 1);
if (mv_ic_sc->ic_high_regs) {
irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
if (irq)
return (ffs(irq) + 31);
}
if (mv_ic_sc->ic_error_regs) {
irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
if (irq)
return (ffs(irq) + 63);
}
return (-1);
}
static void
arm_mask_irq_all(void)
{
mv_ic_set_mask(0);
if (mv_ic_sc->ic_high_regs)
mv_ic_set_mask_hi(0);
if (mv_ic_sc->ic_error_regs)
mv_ic_set_mask_error(0);
}
void
arm_mask_irq(uintptr_t nb)
{
uint32_t mr;
if (nb < 32) {
mr = mv_ic_get_mask();
mr &= ~(1 << nb);
mv_ic_set_mask(mr);
} else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
mr = mv_ic_get_mask_hi();
mr &= ~(1 << (nb - 32));
mv_ic_set_mask_hi(mr);
} else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
mr = mv_ic_get_mask_error();
mr &= ~(1 << (nb - 64));
mv_ic_set_mask_error(mr);
}
}
void
arm_unmask_irq(uintptr_t nb)
{
uint32_t mr;
if (nb < 32) {
mr = mv_ic_get_mask();
mr |= (1 << nb);
mv_ic_set_mask(mr);
} else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
mr = mv_ic_get_mask_hi();
mr |= (1 << (nb - 32));
mv_ic_set_mask_hi(mr);
} else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
mr = mv_ic_get_mask_error();
mr |= (1 << (nb - 64));
mv_ic_set_mask_error(mr);
}
}
void
mv_ic_set_mask(uint32_t val)
{
bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
IRQ_MASK, val);
}
uint32_t
mv_ic_get_mask(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_MASK));
}
uint32_t
mv_ic_get_cause(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_CAUSE));
}
void
mv_ic_set_mask_hi(uint32_t val)
{
bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
IRQ_MASK_HI, val);
}
uint32_t
mv_ic_get_mask_hi(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_MASK_HI));
}
uint32_t
mv_ic_get_cause_hi(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
}
void
mv_ic_set_mask_error(uint32_t val)
{
bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
IRQ_MASK_ERROR, val);
}
uint32_t
mv_ic_get_mask_error(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
}
uint32_t
mv_ic_get_cause_error(void)
{
return (bus_space_read_4(mv_ic_sc->ic_bst,
mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));
}
|
