blob: 8d48a2c7e3813fc21b3ea5740947370828301581 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin Clock Controller
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
description:
Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
differences in features and register layout.
properties:
compatible:
enum:
- marvell,berlin2-clk
- marvell,berlin2q-clk
'#clock-cells':
const: 1
clocks:
maxItems: 1
clock-names:
items:
- enum:
- refclk
- video_ext0
required:
- compatible
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
|
