1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
|
/*
* Copyright (c) 2026 Justin Hibbits
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/resource.h>
#include <sys/socket.h>
#include <machine/bus.h>
#include <net/if.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <net/if_var.h>
#include <dev/mdio/mdio.h>
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include "fman.h"
#include "miibus_if.h"
#include "mdio_if.h"
#define MDIO_LOCK() mtx_lock(&sc->sc_lock)
#define MDIO_UNLOCK() mtx_unlock(&sc->sc_lock)
#define MDIO_WRITE4(sc, r, v) \
bus_write_4(sc->sc_res, r, v)
#define MDIO_READ4(sc, r) \
bus_read_4(sc->sc_res, r)
#define MDIO_CFG 0x30
#define CFG_ENC45 0x00000040
#define MDIO_STAT 0x30
#define STAT_BUSY 0x80000000
#define STAT_MDIO_RD_ER 0x00000002
#define MDIO_CTL 0x34
#define CTL_READ 0x00008000
#define MDIO_DATA 0x38
#define MDIO_ADDR 0x3c
static int xmdio_fdt_probe(device_t dev);
static int xmdio_fdt_attach(device_t dev);
static int xmdio_detach(device_t dev);
static const struct ofw_bus_devinfo *xmdio_fdt_get_devinfo(device_t, device_t);
static int xmdio_miibus_readreg(device_t dev, int phy, int reg);
static int xmdio_miibus_writereg(device_t dev, int phy, int reg, int value);
static int xmdio_mdio_readextreg(device_t dev, int phy, int devad, int reg);
static int xmdio_mdio_writeextreg(device_t dev, int phy, int devad, int reg,
int val);
struct xmdio_softc {
struct mtx sc_lock;
struct resource *sc_res;
};
static struct ofw_compat_data mdio_compat_data[] = {
{"fsl,fman-memac-mdio", 0},
{"fsl,fman-xmdio", 0},
{NULL, 0}
};
static device_method_t xmdio_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, xmdio_fdt_probe),
DEVMETHOD(device_attach, xmdio_fdt_attach),
DEVMETHOD(device_detach, xmdio_detach),
DEVMETHOD(bus_add_child, bus_generic_add_child),
/* MII interface */
DEVMETHOD(miibus_readreg, xmdio_miibus_readreg),
DEVMETHOD(miibus_writereg, xmdio_miibus_writereg),
/* MDIO interface */
DEVMETHOD(mdio_readreg, xmdio_miibus_readreg),
DEVMETHOD(mdio_writereg, xmdio_miibus_writereg),
DEVMETHOD(mdio_readextreg, xmdio_mdio_readextreg),
DEVMETHOD(mdio_writeextreg, xmdio_mdio_writeextreg),
/* ofw_bus interface -- expose devinfo of the FDT children we added. */
DEVMETHOD(ofw_bus_get_devinfo, xmdio_fdt_get_devinfo),
DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
DEVMETHOD_END
};
static driver_t xmdio_driver = {
"mdio",
xmdio_methods,
sizeof(struct xmdio_softc),
};
EARLY_DRIVER_MODULE(mdio, fman, xmdio_driver, 0, 0, BUS_PASS_SUPPORTDEV);
MODULE_DEPEND(mdio, miibus, 1, 1, 1);
static int
xmdio_fdt_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_search_compatible(dev, mdio_compat_data)->ocd_str)
return (ENXIO);
device_set_desc(dev, "Freescale XGMAC MDIO");
return (BUS_PROBE_DEFAULT);
}
static int
xmdio_fdt_attach(device_t dev)
{
struct xmdio_softc *sc;
struct ofw_bus_devinfo *obd;
phandle_t node, child;
device_t cdev;
sc = device_get_softc(dev);
sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 0, RF_ACTIVE);
OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
mtx_init(&sc->sc_lock, device_get_nameunit(dev), "XMDIO lock",
MTX_DEF);
node = ofw_bus_get_node(dev);
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
if (!OF_hasprop(child, "reg"))
continue;
obd = malloc(sizeof(*obd), M_DEVBUF, M_WAITOK | M_ZERO);
if (ofw_bus_gen_setup_devinfo(obd, child) != 0) {
free(obd, M_DEVBUF);
continue;
}
cdev = device_add_child(dev, NULL, DEVICE_UNIT_ANY);
if (cdev == NULL) {
ofw_bus_gen_destroy_devinfo(obd);
free(obd, M_DEVBUF);
continue;
}
device_set_ivars(cdev, obd);
}
bus_identify_children(dev);
bus_enumerate_hinted_children(dev);
bus_attach_children(dev);
return (0);
return (0);
}
static int
xmdio_detach(device_t dev)
{
struct xmdio_softc *sc;
sc = device_get_softc(dev);
mtx_destroy(&sc->sc_lock);
return (0);
}
static void
set_clause45(struct xmdio_softc *sc)
{
uint32_t reg;
reg = MDIO_READ4(sc, MDIO_CFG);
MDIO_WRITE4(sc, MDIO_CFG, reg | CFG_ENC45);
}
static void
set_clause22(struct xmdio_softc *sc)
{
uint32_t reg;
reg = MDIO_READ4(sc, MDIO_CFG);
MDIO_WRITE4(sc, MDIO_CFG, reg & ~CFG_ENC45);
}
static int
xmdio_wait_no_busy(struct xmdio_softc *sc)
{
uint32_t count, val;
for (count = 1000; count > 0; count--) {
val = MDIO_READ4(sc, MDIO_CFG);
if ((val & STAT_BUSY) == 0)
break;
DELAY(1);
}
if (count == 0)
return (0xffff);
return (0);
}
int
xmdio_miibus_readreg(device_t dev, int phy, int reg)
{
struct xmdio_softc *sc;
int rv;
uint32_t ctl;
sc = device_get_softc(dev);
MDIO_LOCK();
set_clause22(sc);
ctl = (phy << 5) | reg;
MDIO_WRITE4(sc, MDIO_CTL, ctl | CTL_READ);
MDIO_READ4(sc, MDIO_CTL);
if (xmdio_wait_no_busy(sc))
rv = 0xffff;
else
rv = MDIO_READ4(sc, MDIO_DATA);
MDIO_WRITE4(sc, MDIO_CTL, 0);
MDIO_UNLOCK();
return (rv);
}
int
xmdio_miibus_writereg(device_t dev, int phy, int reg, int value)
{
struct xmdio_softc *sc;
sc = device_get_softc(dev);
MDIO_LOCK();
set_clause22(sc);
/* Stop the MII management read cycle */
MDIO_WRITE4(sc, MDIO_CTL, (phy << 5) | reg);
MDIO_WRITE4(sc, MDIO_DATA, value);
/* Wait till MII management write is complete */
xmdio_wait_no_busy(sc);
MDIO_UNLOCK();
return (0);
}
static int
xmdio_mdio_readextreg(device_t dev, int phy, int devad, int reg)
{
struct xmdio_softc *sc;
int rv;
uint32_t ctl;
sc = device_get_softc(dev);
MDIO_LOCK();
set_clause45(sc);
ctl = (phy << 5) | devad;
MDIO_WRITE4(sc, MDIO_CTL, ctl);
MDIO_WRITE4(sc, MDIO_ADDR, reg);
xmdio_wait_no_busy(sc);
MDIO_WRITE4(sc, MDIO_CTL, ctl | CTL_READ);
MDIO_READ4(sc, MDIO_CTL);
xmdio_wait_no_busy(sc);
if (MDIO_READ4(sc, MDIO_STAT) & STAT_MDIO_RD_ER)
rv = 0xffff;
else
rv = MDIO_READ4(sc, MDIO_DATA);
MDIO_WRITE4(sc, MDIO_CTL, 0);
MDIO_UNLOCK();
return (rv);
}
static int
xmdio_mdio_writeextreg(device_t dev, int phy, int devad, int reg, int val)
{
struct xmdio_softc *sc;
sc = device_get_softc(dev);
MDIO_LOCK();
set_clause45(sc);
/* Stop the MII management read cycle */
MDIO_WRITE4(sc, MDIO_CTL, (phy << 5) | devad);
MDIO_WRITE4(sc, MDIO_DATA, val);
/* Wait till MII management write is complete */
xmdio_wait_no_busy(sc);
MDIO_UNLOCK();
return (0);
}
static const struct ofw_bus_devinfo *
xmdio_fdt_get_devinfo(device_t bus __unused, device_t child)
{
return (device_get_ivars(child));
}
|
