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| author | Dimitry Andric <dim@FreeBSD.org> | 2024-03-04 20:30:54 +0000 |
|---|---|---|
| committer | Gordon Tetlow <gordon@FreeBSD.org> | 2024-03-28 07:13:15 +0000 |
| commit | 26059a4f2c14d72d114175a05f75bebe43aa6efa (patch) | |
| tree | a1d0237cdf11545be89c4e785ed3061a16d12970 | |
| parent | f07351f90aa37d8fc1b86e96d76447eec884d237 (diff) | |
| download | src-26059a4f2c14d72d114175a05f75bebe43aa6efa.tar.gz src-26059a4f2c14d72d114175a05f75bebe43aa6efa.zip | |
Merge commit f800c1f3b207 from llvm-project (by Arthur Eubanks):
[PEI] Don't zero out noreg operands
A tail call may have $noreg operands.
Fixes a crash.
Reviewed By: xgupta
Differential Revision: https://reviews.llvm.org/D156485
This should fix an assertion failure building qemu, specifically those
parts using -fzero-call-used-regs.
Reported by: Daniel Berrangé <dan-freebsd@berrange.com>
PR: 277474
MFC after: 3 days
Approved by: so
Approved by: re (so, implicit, appease the commit-hook)
Security: FreeBSD-EN-24:07.clang
(cherry picked from commit a39b3aa463f3474fabb3aedb5aecf943b54b4357)
(cherry picked from commit 961271f952fc390396f967d50903291e3e6c59c6)
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp index e323aaaeefaf..49047719fdaa 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1285,6 +1285,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; MCRegister Reg = MO.getReg(); + if (!Reg) + continue; // This picks up sibling registers (e.q. %al -> %ah). for (MCRegUnit Unit : TRI.regunits(Reg)) @@ -1308,8 +1310,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { if (!MO.isReg()) continue; - for (const MCPhysReg &Reg : - TRI.sub_and_superregs_inclusive(MO.getReg())) + MCRegister Reg = MO.getReg(); + if (!Reg) + continue; + + for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg)) RegsToZero.reset(Reg); } } |