diff options
| -rw-r--r-- | contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp index e323aaaeefaf..49047719fdaa 100644 --- a/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/contrib/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1285,6 +1285,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { continue; MCRegister Reg = MO.getReg(); + if (!Reg) + continue; // This picks up sibling registers (e.q. %al -> %ah). for (MCRegUnit Unit : TRI.regunits(Reg)) @@ -1308,8 +1310,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) { if (!MO.isReg()) continue; - for (const MCPhysReg &Reg : - TRI.sub_and_superregs_inclusive(MO.getReg())) + MCRegister Reg = MO.getReg(); + if (!Reg) + continue; + + for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg)) RegsToZero.reset(Reg); } } |