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| author | Jimmy Olgeni <olgeni@FreeBSD.org> | 2014-06-09 11:21:52 +0000 |
|---|---|---|
| committer | Jimmy Olgeni <olgeni@FreeBSD.org> | 2014-06-09 11:21:52 +0000 |
| commit | 37e782dfbc764c70ed1489c5c828d3c9ce5e4d65 (patch) | |
| tree | 8d9caebfb388e25f19cd57fc86557a441d7cddff /cad/iverilog | |
| parent | bba40fef06a119bd90dc8b67e951957939f42e6e (diff) | |
| download | ports-37e782dfbc764c70ed1489c5c828d3c9ce5e4d65.tar.gz ports-37e782dfbc764c70ed1489c5c828d3c9ce5e4d65.zip | |
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.
CR: D196
Approved by: portmgr (bapt)
Notes
Notes:
svn path=/head/; revision=357139
Diffstat (limited to 'cad/iverilog')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index 3df1153c2968..82094e496e1a 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -9,7 +9,7 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \ DISTNAME= verilog-${PORTVERSION} MAINTAINER= zeising@FreeBSD.org -COMMENT= A Verilog simulation and synthesis tool +COMMENT= Verilog simulation and synthesis tool LICENSE= GPLv2 |