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| author | Yuri Victorovich <yuri@FreeBSD.org> | 2021-12-27 17:06:26 +0000 |
|---|---|---|
| committer | Yuri Victorovich <yuri@FreeBSD.org> | 2021-12-27 17:09:30 +0000 |
| commit | d7ee1b9f2e0aa100b4ec29a87ee9b4186999c251 (patch) | |
| tree | 111ea7a1ad7a0cb1da0661850a00d80599cc64e5 /cad/surelog/pkg-descr | |
| parent | b2310eb90e7efc127625562439ef050ff78dbe11 (diff) | |
| download | ports-d7ee1b9f2e0aa100b4ec29a87ee9b4186999c251.tar.gz ports-d7ee1b9f2e0aa100b4ec29a87ee9b4186999c251.zip | |
cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
Diffstat (limited to 'cad/surelog/pkg-descr')
| -rw-r--r-- | cad/surelog/pkg-descr | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cad/surelog/pkg-descr b/cad/surelog/pkg-descr new file mode 100644 index 000000000000..49e4c789698f --- /dev/null +++ b/cad/surelog/pkg-descr @@ -0,0 +1,4 @@ +SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides +IEEE Design/TB C/C++ VPI and Python AST API. + +WWW: https://github.com/chipsalliance/Surelog |