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| author | Eitan Adler <eadler@FreeBSD.org> | 2013-03-28 16:28:59 +0000 |
|---|---|---|
| committer | Eitan Adler <eadler@FreeBSD.org> | 2013-03-28 16:28:59 +0000 |
| commit | d1f32a3e5da5106edfaeb272ae3102f268d57a76 (patch) | |
| tree | 02d4462d3bb1265765e1fe1d3f6bc4b0ac3c771d /cad/verilog-mode.el | |
| parent | f4c9b38788d5f2338bfa1d4e4b8e6ede99d18fa9 (diff) | |
| download | ports-d1f32a3e5da5106edfaeb272ae3102f268d57a76.tar.gz ports-d1f32a3e5da5106edfaeb272ae3102f268d57a76.zip | |
Style: tab -> space.
Most contributors copy an existing port when writing their own so reduce the number of bad examples in the tree.
Notes
Notes:
svn path=/head/; revision=315487
Diffstat (limited to 'cad/verilog-mode.el')
| -rw-r--r-- | cad/verilog-mode.el/pkg-descr | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr index 204e0d263792..3b1cd432f249 100644 --- a/cad/verilog-mode.el/pkg-descr +++ b/cad/verilog-mode.el/pkg-descr @@ -7,4 +7,4 @@ interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators. Author: Michael McNamara <mac@verilog.com>, Wilson Snyder <wsnyder@wsnyder.org> -WWW: http://www.veripool.org/wiki/verilog-mode +WWW: http://www.veripool.org/wiki/verilog-mode |