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author | Mikael Urankar <mikael@FreeBSD.org> | 2023-06-09 11:36:53 +0000 |
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committer | Mikael Urankar <mikael@FreeBSD.org> | 2023-06-09 11:38:16 +0000 |
commit | e1d1045bc7a57cb26a07750a25c7b8bdd94b7175 (patch) | |
tree | 863958373c572b992b08e55055272272628ac5e0 /cad/veryl | |
parent | 0aa4d0db89007959f0571d56a6289211be9680f1 (diff) | |
download | ports-e1d1045bc7a57cb26a07750a25c7b8bdd94b7175.tar.gz ports-e1d1045bc7a57cb26a07750a25c7b8bdd94b7175.zip |
lang/rust: Bump revisions after 1.70.0
PR: 271797
Diffstat (limited to 'cad/veryl')
-rw-r--r-- | cad/veryl/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/veryl/Makefile b/cad/veryl/Makefile index b209c5041260..01787c542d70 100644 --- a/cad/veryl/Makefile +++ b/cad/veryl/Makefile @@ -1,7 +1,7 @@ PORTNAME= veryl DISTVERSIONPREFIX= veryl-v DISTVERSION= 0.5.5 -PORTREVISION= 2 +PORTREVISION= 3 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org |