www/qt5-webengine: unbreak on aarch64 and armv7 after r496989

PR:		236855
Reported by:	pkg-fallout
Submitted by:	Mikaël Urankar
Approved by:	kde (tcberner)

8 files changed, 229 insertions, 44 deletions

diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_build_config_compiler_BUILD.gn b/www/qt5-webengine/files/patch-src_3rdparty_chromium_build_config_compiler_BUILD.gn
index f7567447b0d8..18622b1deb33 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_build_config_compiler_BUILD.gn
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_build_config_compiler_BUILD.gn
@@ -27,6 +27,20 @@
      cflags += [
        # TODO(hans): Remove this once Clang generates better optimized debug info
        # by default. https://crbug.com/765793
+@@ -747,11 +747,11 @@ config("compiler_cpu_abi") {
+         ]
+       }
+     } else if (current_cpu == "arm") {
+-      if (is_clang && !is_android && !is_nacl) {
++      if (is_clang && !is_android && !is_nacl && !is_bsd) {
+         cflags += [ "--target=arm-linux-gnueabihf" ]
+         ldflags += [ "--target=arm-linux-gnueabihf" ]
+       }
+-      if (!is_nacl) {
++      if (!is_nacl && !is_bsd) {
+         cflags += [
+           "-march=$arm_arch",
+           "-mfloat-abi=$arm_float_abi",
 @@ -761,7 +761,7 @@ config("compiler_cpu_abi") {
          cflags += [ "-mtune=$arm_tune" ]
        }
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
index 7f93236f6b68..a9df631df242 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h
@@ -1,19 +1,35 @@
---- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2018-11-13 18:25:11 UTC
+--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-01-16 11:59:47 UTC
 +++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h
-@@ -29,6 +29,8 @@ extern "C" unsigned long getauxval(unsigned long type)
- namespace crc32c {
+@@ -16,6 +16,24 @@
  
- inline bool CanUseArm64Linux() {
-+return false;
-+#if 0
- #if HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
-   // From 'arch/arm64/include/uapi/asm/hwcap.h' in Linux kernel source code.
-   constexpr unsigned long kHWCAP_PMULL = 1 << 4;
-@@ -39,6 +41,7 @@ inline bool CanUseArm64Linux() {
- #else
-   return false;
- #endif  // HAVE_STRONG_GETAUXVAL || HAVE_WEAK_GETAUXVAL
-+#endif
- }
+ #if HAVE_ARM64_CRC32C
+ 
++#if defined(__FreeBSD__)
++#include <machine/armreg.h>
++#include <sys/types.h>
++namespace crc32c {
++
++inline bool CanUseArm64Linux() {
++  uint64_t id_aa64isar0;
++
++  id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
++  if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
++     (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
++    return true;
++  return false;
++}
++
++}  // namespace crc32c
++
++#elif defined(__linux__)
+ #if HAVE_STRONG_GETAUXVAL
+ #include <sys/auxv.h>
+ #elif HAVE_WEAK_GETAUXVAL
+@@ -43,6 +61,7 @@ inline bool CanUseArm64Linux() {
  
  }  // namespace crc32c
+ 
++#endif
+ #endif  // HAVE_ARM64_CRC32C
+ 
+ #endif  // CRC32C_CRC32C_ARM_LINUX_CHECK_H_
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
index 0693cd205a9a..a466707e404f 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp
@@ -1,19 +1,36 @@
---- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp.orig	2018-11-13 18:25:11 UTC
+--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp.orig	2019-01-16 10:59:47 UTC
 +++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp
-@@ -74,6 +74,8 @@
+@@ -70,6 +70,20 @@
+         return features;
+     }
+ 
++#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)
++    #include <machine/armreg.h>
++
++    static uint32_t read_cpu_features() {
++        uint32_t features = 0;
++        uint64_t id_aa64isar0;
++
++        id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
++        if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
++            features |= SkCpu::CRC32;
++        }
++        return features;
++    }
++
+ #elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)
      #include <sys/auxv.h>
  
-     static uint32_t read_cpu_features() {
-+return 0;
-+#if 0
-         const uint32_t kHWCAP_CRC32   = (1<< 7),
-                        kHWCAP_ASIMDHP = (1<<10);
+@@ -95,7 +109,12 @@
+         const uint32_t kHWCAP_VFPv4 = (1<<16);
  
-@@ -82,6 +84,7 @@
-         if (hwcaps & kHWCAP_CRC32  ) { features |= SkCpu::CRC32; }
-         if (hwcaps & kHWCAP_ASIMDHP) { features |= SkCpu::ASIMDHP; }
-         return features;
+         uint32_t features = 0;
++#if defined(__FreeBSD__)
++        uint32_t hwcaps = 0;
++        elf_aux_info(AT_HWCAP, &hwcaps, sizeof(hwcaps));
++#else
+         uint32_t hwcaps = getauxval(AT_HWCAP);
 +#endif
-     }
- 
- #elif defined(SK_CPU_ARM32) && __has_include(<sys/auxv.h>) && \
+         if (hwcaps & kHWCAP_NEON ) {
+             features |= SkCpu::NEON;
+             if (hwcaps & kHWCAP_VFPv4) { features |= SkCpu::NEON_FMA|SkCpu::VFP_FP16; }
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_opts_SkRasterPipeline__opts.h b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_opts_SkRasterPipeline__opts.h
new file mode 100644
index 000000000000..c9662db9dd99
--- /dev/null
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_opts_SkRasterPipeline__opts.h
@@ -0,0 +1,26 @@
+--- src/3rdparty/chromium/third_party/skia/src/opts/SkRasterPipeline_opts.h.orig	2019-01-16 10:59:47 UTC
++++ src/3rdparty/chromium/third_party/skia/src/opts/SkRasterPipeline_opts.h
+@@ -657,7 +657,10 @@ SI F approx_powf(F x, F y) {
+ }
+ 
+ SI F from_half(U16 h) {
+-#if defined(__ARM_FP16_FORMAT_IEEE)
++#if defined(__ARM_FP16_FORMAT_IEEE) && defined(__aarch64__)
++    return vcvt_f32_f16(h);
++
++#elif defined(__ARM_FP16_FORMAT_IEEE)
+     __fp16 fp16;
+     memcpy(&fp16, &h, sizeof(U16));
+     return float(fp16);
+@@ -679,7 +682,10 @@ SI F from_half(U16 h) {
+ }
+ 
+ SI U16 to_half(F f) {
+-#if defined(__ARM_FP16_FORMAT_IEEE)
++#if defined(__ARM_FP16_FORMAT_IEEE) && defined(__aarch64__)
++    return vcvt_f16_f32(f);
++
++#elif defined(__ARM_FP16_FORMAT_IEEE)
+     __fp16 fp16 = __fp16(f);
+     U16 u16;
+     memcpy(&u16, &fp16, sizeof(U16));
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
index e9aa60902f76..78038610a96f 100644
--- a/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c
@@ -1,29 +1,54 @@
---- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig	2018-11-13 18:25:11 UTC
+--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig	2019-01-16 11:59:47 UTC
 +++ src/3rdparty/chromium/third_party/zlib/arm_features.c
-@@ -16,12 +16,13 @@
+@@ -10,20 +10,33 @@
+ #include <pthread.h>
+ #include <stdint.h>
+ 
+-#if defined(ARMV8_OS_ANDROID)
++int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0;
++int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
++
++static pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
++
++#if defined (__FreeBSD__)
++#include <machine/armreg.h>
++#include <sys/types.h>
++static void init_arm_features(void)
++{
++#if defined (__aarch64__)
++    uint64_t id_aa64isar0;
++
++    id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
++    if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
++        arm_cpu_enable_pmull = 1;
++    if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
++        arm_cpu_enable_crc32 = 1;
++#endif
++}
++#elif defined(ARMV8_OS_ANDROID)
+ #include <cpu-features.h>
+ #elif defined(ARMV8_OS_LINUX)
  #include <asm/hwcap.h>
  #include <sys/auxv.h>
- #else
+-#else
 -#error ### No ARM CPU features detection in your platform/OS
-+/* #error ### No ARM CPU features detection in your platform/OS */
- #endif
- 
- int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0;
- int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
+-#endif
  
-+#ifdef ARMV8_OS_LINUX
- static pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
+-int ZLIB_INTERNAL arm_cpu_enable_crc32 = 0;
+-int ZLIB_INTERNAL arm_cpu_enable_pmull = 0;
  
+-static pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
+-
  static void init_arm_features(void)
-@@ -53,8 +54,11 @@ static void init_arm_features(void)
+ {
+     uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0;
+@@ -53,6 +66,9 @@ static void init_arm_features(void)
      if (capabilities & flag_pmull)
          arm_cpu_enable_pmull = 1;
  }
++#else
++#error ### No ARM CPU features detection in your platform/OS
 +#endif
  
  void ZLIB_INTERNAL arm_check_features(void)
  {
-+#ifdef ARMV8_OS_LINUX
-     pthread_once(&cpu_check_inited_once, init_arm_features);
-+#endif
- }
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_arm_cpu-arm.cc b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_arm_cpu-arm.cc
new file mode 100644
index 000000000000..c486b06c5847
--- /dev/null
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_arm_cpu-arm.cc
@@ -0,0 +1,22 @@
+--- src/3rdparty/chromium/v8/src/arm/cpu-arm.cc.orig	2019-01-16 10:59:47 UTC
++++ src/3rdparty/chromium/v8/src/arm/cpu-arm.cc
+@@ -7,6 +7,9 @@
+ #ifdef __QNXNTO__
+ #include <sys/mman.h>  // for cache flushing.
+ #undef MAP_TYPE
++#elif defined(__FreeBSD__)
++#include <sys/types.h>
++#include <machine/sysarch.h> // for cache flushing.
+ #else
+ #include <sys/syscall.h>  // for cache flushing.
+ #endif
+@@ -24,6 +27,9 @@ void CpuFeatures::FlushICache(void* start, size_t size
+ #if !defined(USE_SIMULATOR)
+ #if V8_OS_QNX
+   msync(start, size, MS_SYNC | MS_INVALIDATE_ICACHE);
++#elif defined(__FreeBSD__)
++  struct arm_sync_icache_args args = { .addr = (uintptr_t)start, .len = size };
++  sysarch(ARM_SYNC_ICACHE, (void *)&args);
+ #else
+   register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(start);
+   register uint32_t end asm("r1") = beg + size;
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_base_platform_platform-freebsd.cc b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_base_platform_platform-freebsd.cc
new file mode 100644
index 000000000000..e302331ba63e
--- /dev/null
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_base_platform_platform-freebsd.cc
@@ -0,0 +1,50 @@
+--- src/3rdparty/chromium/v8/src/base/platform/platform-freebsd.cc.orig	2019-01-16 10:59:47 UTC
++++ src/3rdparty/chromium/v8/src/base/platform/platform-freebsd.cc
+@@ -86,5 +86,47 @@ std::vector<OS::SharedLibraryAddress> OS::GetSharedLib
+ 
+ void OS::SignalCodeMovingGC() {}
+ 
++#ifdef __arm__
++
++bool OS::ArmUsingHardFloat() {
++// GCC versions 4.6 and above define __ARM_PCS or __ARM_PCS_VFP to specify
++// the Floating Point ABI used (PCS stands for Procedure Call Standard).
++// We use these as well as a couple of other defines to statically determine
++// what FP ABI used.
++// GCC versions 4.4 and below don't support hard-fp.
++// GCC versions 4.5 may support hard-fp without defining __ARM_PCS or
++// __ARM_PCS_VFP.
++
++#define GCC_VERSION \
++  (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
++#if GCC_VERSION >= 40600 && !defined(__clang__)
++#if defined(__ARM_PCS_VFP)
++  return true;
++#else
++  return false;
++#endif
++
++#elif GCC_VERSION < 40500 && !defined(__clang__)
++  return false;
++
++#else
++#if defined(__ARM_PCS_VFP)
++  return true;
++#elif defined(__ARM_PCS) || defined(__SOFTFP__) || defined(__SOFTFP) || \
++    !defined(__VFP_FP__)
++  return false;
++#else
++#error \
++    "Your version of compiler does not report the FP ABI compiled for."     \
++       "Please report it on this issue"                                        \
++       "http://code.google.com/p/v8/issues/detail?id=2140"
++
++#endif
++#endif
++#undef GCC_VERSION
++}
++
++#endif // def __arm__
++
+ }  // namespace base
+ }  // namespace v8
diff --git a/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_libsampler_sampler.cc b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_libsampler_sampler.cc
new file mode 100644
index 000000000000..9097657f2740
--- /dev/null
+++ b/www/qt5-webengine/files/patch-src_3rdparty_chromium_v8_src_libsampler_sampler.cc
@@ -0,0 +1,15 @@
+--- src/3rdparty/chromium/v8/src/libsampler/sampler.cc.orig	2019-01-16 10:59:47 UTC
++++ src/3rdparty/chromium/v8/src/libsampler/sampler.cc
+@@ -550,9 +550,9 @@ void SignalHandler::FillRegisterState(void* context, R
+   state->sp = reinterpret_cast<void*>(mcontext.mc_rsp);
+   state->fp = reinterpret_cast<void*>(mcontext.mc_rbp);
+ #elif V8_HOST_ARCH_ARM
+-  state->pc = reinterpret_cast<void*>(mcontext.mc_r15);
+-  state->sp = reinterpret_cast<void*>(mcontext.mc_r13);
+-  state->fp = reinterpret_cast<void*>(mcontext.mc_r11);
++  state->pc = reinterpret_cast<void*>(mcontext.__gregs[_REG_PC]);
++  state->sp = reinterpret_cast<void*>(mcontext.__gregs[_REG_SP]);
++  state->fp = reinterpret_cast<void*>(mcontext.__gregs[_REG_FP]);
+ #endif  // V8_HOST_ARCH_*
+ #elif V8_OS_NETBSD
+ #if V8_HOST_ARCH_IA32