diff options
Diffstat (limited to 'cad/py-cocotb')
| -rw-r--r-- | cad/py-cocotb/Makefile | 51 | ||||
| -rw-r--r-- | cad/py-cocotb/distinfo | 3 | ||||
| -rw-r--r-- | cad/py-cocotb/pkg-descr | 5 |
3 files changed, 59 insertions, 0 deletions
diff --git a/cad/py-cocotb/Makefile b/cad/py-cocotb/Makefile new file mode 100644 index 000000000000..41ae5db9cf5e --- /dev/null +++ b/cad/py-cocotb/Makefile @@ -0,0 +1,51 @@ +PORTNAME= cocotb +DISTVERSIONPREFIX= v +DISTVERSION= 1.8.1 +CATEGORIES= cad python +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog +WWW= https://www.cocotb.org/ + +LICENSE= BSD3CLAUSE +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= ${PY_SETUPTOOLS} \ + ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR} +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \ + gtkwave:cad/gtkwave +TEST_DEPENDS= ${PYTHON_PKGNAMEPREFIX}pytest>0:devel/py-pytest@${PY_FLAVOR} \ + ${PYTHON_PKGNAMEPREFIX}pytest-cov>0:devel/py-pytest-cov@${PY_FLAVOR} \ + ${PYTHON_PKGNAMEPREFIX}pytest-mock>=3.10.0:devel/py-pytest-mock@${PY_FLAVOR} + +USES= python shebangfix +USE_PYTHON= pep517 autoplist +USE_GITHUB= yes + +SHEBANG_GLOB= *.py + +TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} \ + PATH=${STAGEDIR}${LOCALBASE}/bin:${PATH} \ + LD_LIBRARY_PATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR}/cocotb/libs \ + SIM=icarus + +OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO +OPTIONS_DEFAULT= IVERILOG VERILATOR + +IVERILOG_DESC= Iverilog dependency +IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog + +VERILATOR_DESC= Verilator dependency +VERILATOR_RUN_DEPENDS= verilator:cad/verilator + +post-install: + @${STRIP_CMD} \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl + +do-test: # some tests fail, see https://github.com/cocotb/cocotb/issues/3236, https://github.com/cocotb/cocotb/issues/3435 + @cd ${TEST_WRKSRC} && ${SETENV} ${TEST_ENV} ${GMAKE} test + +.include <bsd.port.mk> diff --git a/cad/py-cocotb/distinfo b/cad/py-cocotb/distinfo new file mode 100644 index 000000000000..741fe045c408 --- /dev/null +++ b/cad/py-cocotb/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1696905738 +SHA256 (cocotb-cocotb-v1.8.1_GH0.tar.gz) = 4cfa4ac615e6ebed25e4af96e048e2dc3e808f328ac1db97f2a57c4e1142e6b0 +SIZE (cocotb-cocotb-v1.8.1_GH0.tar.gz) = 654022 diff --git a/cad/py-cocotb/pkg-descr b/cad/py-cocotb/pkg-descr new file mode 100644 index 000000000000..de72cfe264b0 --- /dev/null +++ b/cad/py-cocotb/pkg-descr @@ -0,0 +1,5 @@ +cocotb is an open source coroutine-based cosimulation testbench environment +for verifying VHDL and SystemVerilog RTL using Python. + +cocotb lets you verify chips like software: productive, simulator-agnostic, +in Python. |