diff options
Diffstat (limited to 'cad/yosys-systemverilog/pkg-plist')
-rw-r--r-- | cad/yosys-systemverilog/pkg-plist | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/cad/yosys-systemverilog/pkg-plist b/cad/yosys-systemverilog/pkg-plist new file mode 100644 index 000000000000..7ab2e58b7515 --- /dev/null +++ b/cad/yosys-systemverilog/pkg-plist @@ -0,0 +1,52 @@ +bin/sv2v +share/yosys/nexus/dsp_rules.txt +share/yosys/plugins/design_introspection.so +share/yosys/plugins/dsp-ff.so +share/yosys/plugins/fasm.so +share/yosys/plugins/fasm_extra_modules/BANK.v +share/yosys/plugins/integrateinv.so +share/yosys/plugins/params.so +share/yosys/plugins/ql-iob.so +share/yosys/plugins/ql-qlf.so +share/yosys/plugins/sdc.so +share/yosys/plugins/systemverilog.so +share/yosys/plugins/uhdm.so +share/yosys/plugins/xdc.so +share/yosys/quicklogic/pp3/abc9_map.v +share/yosys/quicklogic/pp3/abc9_model.v +share/yosys/quicklogic/pp3/abc9_unmap.v +share/yosys/quicklogic/pp3/bram_init_32.vh +share/yosys/quicklogic/pp3/bram_init_8_16.vh +share/yosys/quicklogic/pp3/brams.txt +share/yosys/quicklogic/pp3/brams_map.v +share/yosys/quicklogic/pp3/brams_sim.v +share/yosys/quicklogic/pp3/cells_map.v +share/yosys/quicklogic/pp3/cells_sim.v +share/yosys/quicklogic/pp3/ffs_map.v +share/yosys/quicklogic/pp3/latches_map.v +share/yosys/quicklogic/pp3/lut_map.v +share/yosys/quicklogic/pp3/lutdefs.txt +share/yosys/quicklogic/pp3/mult_sim.v +share/yosys/quicklogic/pp3/qlal3_sim.v +share/yosys/quicklogic/pp3/qlal4s3b_sim.v +share/yosys/quicklogic/qlf_k6n10/arith_map.v +share/yosys/quicklogic/qlf_k6n10/brams.txt +share/yosys/quicklogic/qlf_k6n10/brams_map.v +share/yosys/quicklogic/qlf_k6n10/cells_sim.v +share/yosys/quicklogic/qlf_k6n10/dsp_map.v +share/yosys/quicklogic/qlf_k6n10/ffs_map.v +share/yosys/quicklogic/qlf_k6n10/lut_map.v +share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +share/yosys/quicklogic/qlf_k6n10f/arith_map.v +share/yosys/quicklogic/qlf_k6n10f/brams.txt +share/yosys/quicklogic/qlf_k6n10f/brams_final_map.v +share/yosys/quicklogic/qlf_k6n10f/brams_map.v +share/yosys/quicklogic/qlf_k6n10f/brams_sim.v +share/yosys/quicklogic/qlf_k6n10f/cells_sim.v +share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v +share/yosys/quicklogic/qlf_k6n10f/dsp_map.v +share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v +share/yosys/quicklogic/qlf_k6n10f/ffs_map.v +share/yosys/quicklogic/qlf_k6n10f/primitives_sim.v +share/yosys/quicklogic/qlf_k6n10f/sram1024x18.v +share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v |