| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | cad/NASTRAN-95: Remove expired port: | Muhammad Moinur Rahman | 2023-03-19 | 1 | -1/+0 |
| * | cad/gdscpp: New port: C++ library to create and read GDSII file | Yuri Victorovich | 2023-03-02 | 1 | -0/+1 |
| * | cad/ghdl: Re-add port: GNU VHDL simulator | Yuri Victorovich | 2023-02-23 | 1 | -0/+1 |
| * | cad/hs-verismith: New port: Verilog fuzzer | Yuri Victorovich | 2023-02-17 | 1 | -0/+1 |
| * | cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHD... | Yuri Victorovich | 2023-02-04 | 1 | -0/+1 |
| * | cad/antimony: New port: CAD from a parallel universe | Yuri Victorovich | 2023-01-16 | 1 | -0/+1 |
| * | cad/silice: New port: Language that simplifies prototyping and writing algori... | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
| * | cad/py-edalize: New port: Library for interfacing EDA tools | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
| * | cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/Syste... | Yuri Victorovich | 2023-01-08 | 1 | -0/+1 |
| * | cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL) | Yuri Victorovich | 2023-01-06 | 1 | -0/+1 |
| * | cad/svls: New port: SystemVerilog language server | Yuri Victorovich | 2023-01-06 | 1 | -0/+1 |
| * | cad/svlint: New port: SystemVerilog linter | Yuri Victorovich | 2023-01-03 | 1 | -0/+1 |
| * | cad/basicdsp: Cleanup EXPIRED ports | Muhammad Moinur Rahman | 2022-12-31 | 1 | -1/+0 |
| * | cleanup: Remove expired ports: | Rene Ladan | 2022-12-31 | 1 | -1/+0 |
| * | cad/py-pygmsh: New port: Python frontend for Gmsh (on top of Gmsh's own binding) | Yuri Victorovich | 2022-12-20 | 1 | -0/+1 |
| * | cad/py-gmsh: New port: Automatic 3D finite element mesh generator (gmsh's own... | Yuri Victorovich | 2022-12-20 | 1 | -0/+1 |
| * | cad/libgdsii: New port: C++ library and command-line utility for reading GDSI... | Yuri Victorovich | 2022-11-20 | 1 | -0/+1 |
| * | cad/qucsator: New port: Circuit simulator of the Qucs project | Yuri Victorovich | 2022-07-09 | 1 | -0/+1 |
| * | cad/xyce: New port: Xyce electronic simulator | Yuri Victorovich | 2022-07-09 | 1 | -0/+1 |
| * | cad/qucs-s: New port: Quite Universal Circuit Simulator: GUI for circuit simu... | Yuri Victorovich | 2022-07-08 | 1 | -0/+1 |
| * | Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor | Robert Clausecker | 2022-06-05 | 1 | -0/+1 |
| * | Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor | Robert Clausecker | 2022-06-05 | 1 | -0/+1 |
| * | cad/camotics: adding CAMotics, Simulation & Computer Aided Machining | Thierry Thomas | 2022-05-21 | 1 | -0/+1 |
| * | cleanup: Remove ports depending on expired lang/gcc6-aux | Rene Ladan | 2022-02-28 | 1 | -1/+0 |
| * | cad/opencascade740: Resurrect cad/opencascade @ version 7.4.0 | Yuri Victorovich | 2022-01-30 | 1 | -0/+1 |
| * | cad/padring: New port: Padring generator for ASICs | Yuri Victorovich | 2021-12-30 | 1 | -0/+1 |
| * | cad/cvc: New port: Circuit Validity Checker | Yuri Victorovich | 2021-12-29 | 1 | -0/+1 |
| * | cad/uhdm: New port: Universal Hardware Data Model | Yuri Victorovich | 2021-12-27 | 1 | -0/+1 |
| * | cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc | Yuri Victorovich | 2021-12-27 | 1 | -0/+1 |
| * | cad/py-pymtl: New port: Python-based hardware generation, simulation, verific... | Yuri Victorovich | 2021-12-27 | 1 | -0/+1 |
| * | cad/gds3d: New port: Application for rendering IC (chip) layouts in 3D | Yuri Victorovich | 2021-10-04 | 1 | -0/+1 |
| * | cad/opentimer: New port: High-performance timing analysis tool for VLSI systems | Yuri Victorovich | 2021-09-12 | 1 | -0/+1 |
| * | cad/appcsxcad: New port: Minimal GUI Application using the QCSXCAD library | Yuri Victorovich | 2021-08-19 | 1 | -0/+1 |
| * | cad/qcsxcad: New port: Qt-GUI for CSXCAD | Yuri Victorovich | 2021-08-19 | 1 | -0/+1 |
| * | cad/csxcad: New port: C++ library to describe geometrical objects | Yuri Victorovich | 2021-08-19 | 1 | -0/+1 |
| * | cad/ldview: New port: LDraw model viewer | Yuri Victorovich | 2021-06-08 | 1 | -0/+1 |
| * | Remove expired ports: | Rene Ladan | 2021-04-07 | 1 | -2/+0 |
| * | One more small cleanup, forgotten yesterday. | Mathieu Arnold | 2021-04-07 | 1 | -1/+0 |
| * | Remove # $FreeBSD$ from Makefiles. | Mathieu Arnold | 2021-04-06 | 1 | -2/+0 |
| * | New port: cad/archimedes: Semiconductor device simulation software | Yuri Victorovich | 2020-12-10 | 1 | -0/+1 |
| * | New port: cad/stm32flash: Flash program for STM32 using the ST serial bootloader | Yuri Victorovich | 2020-11-18 | 1 | -0/+1 |
| * | New port: cad/ecpprog: Driver for FTDI based JTAG probes, to program ECP5 FPGAs | Yuri Victorovich | 2020-09-16 | 1 | -0/+1 |
| * | cad/opensta: Remove because it is now included in OpenRoad (cad/openroad) | Yuri Victorovich | 2020-09-15 | 1 | -1/+0 |
| * | New port: cad/openroad: ASIC physical design tool | Yuri Victorovich | 2020-09-14 | 1 | -0/+1 |
| * | Clean up some things | Tobias Kortkamp | 2020-08-18 | 1 | -0/+3 |
| * | New port: cad/openfpgaloader: Universal utility for programming FPGA | Yuri Victorovich | 2020-08-11 | 1 | -0/+1 |
| * | New port: cad/horizon-eda: EDA package for printed circuit board design | Yuri Victorovich | 2020-08-07 | 1 | -0/+1 |
| * | [NEW PORT] cad/py-ezdxf: Create and modify DXF drawings | Loïc Bartoletti | 2020-07-30 | 1 | -0/+1 |
| * | cad/meshlab: Resurrect, update to 2020.05 and take maintainer'ship | Loïc Bartoletti | 2020-07-18 | 1 | -0/+1 |
| * | [NEW PORT] cad/ifcopenshell: Open source IFC library and geometry engine | Loïc Bartoletti | 2020-05-23 | 1 | -0/+1 |
