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* cad/surelog: Update 1.64 → 1.66Yuri Victorovich2023-06-172-4/+4
* cad/surelog: Update 1.63 → 1.64Yuri Victorovich2023-06-112-4/+4
* cad/surelog: Update 1.61 → 1.63Yuri Victorovich2023-06-082-5/+4
* cad/surelog: Add TCMALLOC optionYuri Victorovich2023-06-061-3/+7
* cad/surelog: Update 1.60 → 1.61Yuri Victorovich2023-06-052-4/+6
* cad/surelog: Update 1.59 → 1.60Yuri Victorovich2023-05-312-5/+4
* cad/surelog: Fix PYTHON optionYuri Victorovich2023-05-272-0/+5
* cad/surelog: Update 1.58 → 1.59Yuri Victorovich2023-05-182-13/+13
* cad/surelog: Update 1.57 → 1.58Yuri Victorovich2023-05-072-6/+5
* cad/surelog: Remove Java runtime dependencyYuri Victorovich2023-04-301-0/+4
* cad/surelog: Update 1.56 → 1.57Yuri Victorovich2023-04-273-21/+29
* cad/surelog: Update 1.51 → 1.56Yuri Victorovich2023-04-163-15/+14
* cad/surelog: Remove unnecessary element from CONFLICTS_INSTALLYuri Victorovich2023-04-111-1/+1
* cad/surelog: Add commend about USE_JAVAYuri Victorovich2023-04-051-1/+1
* cad/surelog: Unbundle libuhdm and libcapnpYuri Victorovich2023-03-312-301/+5
* cad/surelog: Update 1.50 → 1.51Yuri Victorovich2023-03-302-5/+9
* cad/surelog: Update 1.49 → 1.50Yuri Victorovich2023-03-273-6/+7
* cad/surelog: Update 1.48 → 1.49Yuri Victorovich2023-03-253-6/+7
* cad/surelog: Add PORTSCOUT lineYuri Victorovich2023-03-111-0/+2
* cad/surelog: Update 1.45 → 1.48Yuri Victorovich2023-03-093-23/+30
* cad/surelog: Update 1.36 -> 1.45Yuri Victorovich2022-11-068-20/+75
* Remove WWW entries moved into port MakefilesStefan Eßer2022-09-071-2/+0
* Add WWW entries to port MakefilesStefan Eßer2022-09-071-0/+1
* cad/surelog: Broken on i386Yuri Victorovich2022-09-041-0/+1
* cad/surelog: Update 0.0-3950 -> 1.36Yuri Victorovich2022-08-285-152/+107
* cad/surelog: Broken on armv6Yuri Victorovich2022-08-061-1/+2
* cad/surelog: Broken on aarch64Yuri Victorovich2022-07-221-0/+2
* Update CONFLICTS definitions in categories a* to c*Stefan Eßer2022-02-061-0/+2
* cad/surelog: Update 0.0.3924 .> 0.0.3950Yuri Victorovich2022-01-014-12/+34
* cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etcYuri Victorovich2021-12-275-0/+476