blob: 21b72674f0cf1a49e9d200185507db3604b27e05 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
# ex:ts=8
# New ports collection makefile for: iverilog
# Date created: Feb 13, 2001
# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
#
# $FreeBSD$
#
PORTNAME= iverilog
PORTVERSION= 0.9.4
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
ftp://ftp.geda.seul.org/pub/geda/dist/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= niclas.zeising@gmail.com
COMMENT= A Verilog simulation and synthesis tool
GNU_CONFIGURE= yes
USE_BISON= build
USE_GMAKE= yes
CONFIGURE_ARGS= --disable-suffix
MAN1= iverilog-vpi.1 iverilog.1 vvp.1
.include <bsd.port.mk>
|