diff options
| author | Mateusz Guzik <mjg@FreeBSD.org> | 2020-09-01 21:29:01 +0000 |
|---|---|---|
| committer | Mateusz Guzik <mjg@FreeBSD.org> | 2020-09-01 21:29:01 +0000 |
| commit | b138e49c66e80c8f467872c365ecc0b6dd8acaae (patch) | |
| tree | 58041a73bf711acb1ce5833efacdc2882a869d34 /sys/dev | |
| parent | 378503af2e65497a3503301d51a2e96a9478ebf0 (diff) | |
| download | src-b138e49c66e80c8f467872c365ecc0b6dd8acaae.tar.gz src-b138e49c66e80c8f467872c365ecc0b6dd8acaae.zip | |
sfxge: clean up empty lines in .c and .h files
Notes
Notes:
svn path=/head/; revision=365086
Diffstat (limited to 'sys/dev')
63 files changed, 0 insertions, 843 deletions
diff --git a/sys/dev/sfxge/common/ef10_ev.c b/sys/dev/sfxge/common/ef10_ev.c index 5cf5130d1fed..523e6854623b 100644 --- a/sys/dev/sfxge/common/ef10_ev.c +++ b/sys/dev/sfxge/common/ef10_ev.c @@ -91,7 +91,6 @@ ef10_ev_mcdi( __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); - static __checkReturn efx_rc_t efx_mcdi_set_evq_tmr( __in efx_nic_t *enp, @@ -273,7 +272,6 @@ fail1: return (rc); } - static __checkReturn efx_rc_t efx_mcdi_init_evq_v2( __in efx_nic_t *enp, @@ -440,8 +438,6 @@ fail1: return (rc); } - - __checkReturn efx_rc_t ef10_ev_init( __in efx_nic_t *enp) @@ -754,7 +750,6 @@ fail1: return (rc); } - #if EFSYS_OPT_QSTATS void ef10_ev_qstats_update( diff --git a/sys/dev/sfxge/common/ef10_filter.c b/sys/dev/sfxge/common/ef10_filter.c index f07f6568cb82..58bc9b15b003 100644 --- a/sys/dev/sfxge/common/ef10_filter.c +++ b/sys/dev/sfxge/common/ef10_filter.c @@ -577,7 +577,6 @@ ef10_filter_restore( enp->en_family == EFX_FAMILY_MEDFORD2); for (tbl_id = 0; tbl_id < EFX_EF10_FILTER_TBL_ROWS; tbl_id++) { - EFSYS_LOCK(enp->en_eslp, state); spec = ef10_filter_entry_spec(eftp, tbl_id); @@ -729,7 +728,6 @@ found: /* This is a filter we are refreshing */ ef10_filter_set_entry_not_auto_old(eftp, ins_index); goto out_unlock; - } replacing = B_TRUE; } else { @@ -835,7 +833,6 @@ fail1: return (rc); } - static __checkReturn efx_rc_t ef10_filter_delete_internal( __in efx_nic_t *enp, @@ -1288,7 +1285,6 @@ ef10_filter_insert_multicast_list( /* Only stop upon failure if told to rollback */ goto rollback; } - } if (brdcst == B_TRUE) { @@ -1493,7 +1489,6 @@ ef10_filter_remove_old( } } - static __checkReturn efx_rc_t ef10_filter_get_workarounds( __in efx_nic_t *enp) @@ -1529,7 +1524,6 @@ fail1: } - /* * Reconfigure all filters. * If all_unicst and/or all mulcst filters cannot be applied then @@ -1767,7 +1761,6 @@ ef10_filter_get_default_rxq( *using_rss = table->eft_using_rss; } - void ef10_filter_default_rxq_set( __in efx_nic_t *enp, @@ -1797,7 +1790,6 @@ ef10_filter_default_rxq_clear( table->eft_using_rss = B_FALSE; } - #endif /* EFSYS_OPT_FILTER */ #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ diff --git a/sys/dev/sfxge/common/ef10_image.c b/sys/dev/sfxge/common/ef10_image.c index 5fbd6e2d1b35..10322edd23dd 100644 --- a/sys/dev/sfxge/common/ef10_image.c +++ b/sys/dev/sfxge/common/ef10_image.c @@ -67,7 +67,6 @@ typedef struct efx_asn1_cursor_s { uint32_t val_size; } efx_asn1_cursor_t; - /* Parse header of DER encoded ASN.1 TLV and match tag */ static __checkReturn efx_rc_t efx_asn1_parse_header_match_tag( @@ -305,7 +304,6 @@ fail1: return (rc); } - /* * Utility routines for parsing CMS headers (see RFC2315, PKCS#7) */ @@ -538,7 +536,6 @@ efx_check_reflash_image( void *imagep; efx_rc_t rc; - EFSYS_ASSERT(infop != NULL); if (infop == NULL) { rc = EINVAL; @@ -908,8 +905,6 @@ fail1: return (rc); } - - #endif /* EFSYS_OPT_IMAGE_LAYOUT */ #endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ diff --git a/sys/dev/sfxge/common/ef10_impl.h b/sys/dev/sfxge/common/ef10_impl.h index 06b3d6e06bb8..60bc90f5e1cf 100644 --- a/sys/dev/sfxge/common/ef10_impl.h +++ b/sys/dev/sfxge/common/ef10_impl.h @@ -37,7 +37,6 @@ extern "C" { #endif - /* Number of hardware PIO buffers (for compile-time resource dimensions) */ #define EF10_MAX_PIOBUF_NBUFS (16) @@ -57,8 +56,6 @@ extern "C" { # endif #endif /* EFSYS_OPT_MEDFORD2 */ - - /* * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could * possibly be increased, or the write size reported by newer firmware used @@ -81,7 +78,6 @@ extern "C" { /* Invalid RSS context handle */ #define EF10_RSS_CONTEXT_INVALID (0xffffffff) - /* EV */ __checkReturn efx_rc_t @@ -240,7 +236,6 @@ extern void ef10_nic_unprobe( __in efx_nic_t *enp); - /* MAC */ extern __checkReturn efx_rc_t @@ -311,7 +306,6 @@ ef10_mac_stats_update( #endif /* EFSYS_OPT_MAC_STATS */ - /* MCDI */ #if EFSYS_OPT_MCDI @@ -615,7 +609,6 @@ ef10_nvram_buffer_finish( #endif /* EFSYS_OPT_NVRAM */ - /* PHY */ typedef struct ef10_link_state_s { @@ -876,7 +869,6 @@ ef10_nic_pio_unlink( __inout efx_nic_t *enp, __in uint32_t vi_index); - /* VPD */ #if EFSYS_OPT_VPD @@ -942,7 +934,6 @@ ef10_vpd_fini( #endif /* EFSYS_OPT_VPD */ - /* RX */ extern __checkReturn efx_rc_t @@ -956,7 +947,6 @@ ef10_rx_scatter_enable( __in unsigned int buf_size); #endif /* EFSYS_OPT_RX_SCATTER */ - #if EFSYS_OPT_RX_SCALE extern __checkReturn efx_rc_t @@ -1166,7 +1156,6 @@ extern void ef10_filter_default_rxq_clear( __in efx_nic_t *enp); - #endif /* EFSYS_OPT_FILTER */ extern __checkReturn efx_rc_t @@ -1215,7 +1204,6 @@ efx_mcdi_get_clock( __out uint32_t *sys_freqp, __out uint32_t *dpcpu_freqp); - extern __checkReturn efx_rc_t efx_mcdi_get_rxdp_config( __in efx_nic_t *enp, @@ -1249,7 +1237,6 @@ efx_mcdi_set_nic_global( #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ - #if EFSYS_OPT_RX_PACKED_STREAM /* Data space per credit in packed stream mode */ diff --git a/sys/dev/sfxge/common/ef10_intr.c b/sys/dev/sfxge/common/ef10_intr.c index 228b0c4349c8..bd15068ba267 100644 --- a/sys/dev/sfxge/common/ef10_intr.c +++ b/sys/dev/sfxge/common/ef10_intr.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 __checkReturn efx_rc_t @@ -47,7 +46,6 @@ ef10_intr_init( return (0); } - void ef10_intr_enable( __in efx_nic_t *enp) @@ -55,7 +53,6 @@ ef10_intr_enable( _NOTE(ARGUNUSED(enp)) } - void ef10_intr_disable( __in efx_nic_t *enp) @@ -63,7 +60,6 @@ ef10_intr_disable( _NOTE(ARGUNUSED(enp)) } - void ef10_intr_disable_unlocked( __in efx_nic_t *enp) @@ -71,7 +67,6 @@ ef10_intr_disable_unlocked( _NOTE(ARGUNUSED(enp)) } - static __checkReturn efx_rc_t efx_mcdi_trigger_interrupt( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/ef10_mac.c b/sys/dev/sfxge/common/ef10_mac.c index 5a7d17d62c2d..b44fe469f255 100644 --- a/sys/dev/sfxge/common/ef10_mac.c +++ b/sys/dev/sfxge/common/ef10_mac.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 __checkReturn efx_rc_t @@ -442,7 +441,6 @@ ef10_mac_filter_default_rxq_clear( epp->ep_mulcst_addr_count); } - #if EFSYS_OPT_LOOPBACK __checkReturn efx_rc_t @@ -603,7 +601,6 @@ fail1: #define EF10_MAC_STAT_READ(_esmp, _field, _eqp) \ EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) - __checkReturn efx_rc_t ef10_mac_stats_update( __in efx_nic_t *enp, @@ -856,7 +853,6 @@ ef10_mac_stats_update( EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value); - /* VADAPTER RX */ EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS, &value); @@ -939,7 +935,6 @@ ef10_mac_stats_update( EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value); EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value); - if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2) goto done; diff --git a/sys/dev/sfxge/common/ef10_mcdi.c b/sys/dev/sfxge/common/ef10_mcdi.c index 11ac21204e3f..924751f23475 100644 --- a/sys/dev/sfxge/common/ef10_mcdi.c +++ b/sys/dev/sfxge/common/ef10_mcdi.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 #if EFSYS_OPT_MCDI @@ -43,7 +42,6 @@ __FBSDID("$FreeBSD$"); #error "WITH_MCDI_V2 required for EF10 MCDIv2 commands." #endif - __checkReturn efx_rc_t ef10_mcdi_init( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/ef10_nic.c b/sys/dev/sfxge/common/ef10_nic.c index 73550d537d68..d04f14b7e4cf 100644 --- a/sys/dev/sfxge/common/ef10_nic.c +++ b/sys/dev/sfxge/common/ef10_nic.c @@ -669,7 +669,6 @@ fail1: return (rc); } - static __checkReturn efx_rc_t efx_mcdi_free_vis( __in efx_nic_t *enp) @@ -702,7 +701,6 @@ fail1: return (rc); } - static __checkReturn efx_rc_t efx_mcdi_alloc_piobuf( __in efx_nic_t *enp, @@ -886,7 +884,6 @@ fail1: enp->en_arch.ef10.ena_piobuf_count = 0; } - static void ef10_nic_free_piobufs( __in efx_nic_t *enp) @@ -1075,7 +1072,6 @@ ef10_get_datapath_caps( if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0) goto fail1; - req.emr_cmd = MC_CMD_GET_CAPABILITIES; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; @@ -1416,7 +1412,6 @@ fail1: return (rc); } - #define EF10_LEGACY_PF_PRIVILEGE_MASK \ (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ @@ -1432,7 +1427,6 @@ fail1: #define EF10_LEGACY_VF_PRIVILEGE_MASK 0 - __checkReturn efx_rc_t ef10_get_privilege_mask( __in efx_nic_t *enp, @@ -1467,7 +1461,6 @@ fail1: return (rc); } - #define EFX_EXT_PORT_MAX 4 #define EFX_EXT_PORT_NA 0xFF @@ -2137,7 +2130,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t ef10_nic_reset( __in efx_nic_t *enp) @@ -2446,7 +2438,6 @@ ef10_nic_set_hw_unavailable( enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL; } - void ef10_nic_fini( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/ef10_nvram.c b/sys/dev/sfxge/common/ef10_nvram.c index e37c4131f3f9..2628d20f739c 100644 --- a/sys/dev/sfxge/common/ef10_nvram.c +++ b/sys/dev/sfxge/common/ef10_nvram.c @@ -63,12 +63,10 @@ typedef struct nvram_partition_s { tlv_cursor_t tlv_cursor; } nvram_partition_t; - static __checkReturn efx_rc_t tlv_validate_state( __inout tlv_cursor_t *cursor); - static void tlv_init_block( __out uint32_t *block) @@ -130,7 +128,6 @@ tlv_item( #define TLV_DWORD_COUNT(length) \ (1 + 1 + (((length) + sizeof (uint32_t) - 1) / sizeof (uint32_t))) - static uint32_t * tlv_next_item_ptr( __in tlv_cursor_t *cursor) @@ -375,7 +372,6 @@ tlv_last_segment_end( return (last_segment_end); } - static uint32_t * tlv_write( __in tlv_cursor_t *cursor, @@ -1168,7 +1164,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t ef10_nvram_buffer_delete_item( __in_bcount(buffer_size) @@ -1234,8 +1229,6 @@ fail1: return (rc); } - - /* * Read and validate a segment from a partition. A segment is a complete * tlv chain between PARTITION_HEADER and PARTITION_END tags. There may diff --git a/sys/dev/sfxge/common/ef10_phy.c b/sys/dev/sfxge/common/ef10_phy.c index c3afb7b2d99d..6e8346c8fe46 100644 --- a/sys/dev/sfxge/common/ef10_phy.c +++ b/sys/dev/sfxge/common/ef10_phy.c @@ -188,7 +188,6 @@ mcdi_phy_decode_link_mode( } } - void ef10_phy_link_ev( __in efx_nic_t *enp, @@ -335,7 +334,6 @@ ef10_phy_get_link( &elsp->epls.epls_ld_cap_mask); } - #if EFSYS_OPT_LOOPBACK /* * MC_CMD_LOOPBACK and EFX_LOOPBACK names are equivalent, so use the @@ -599,7 +597,6 @@ fail1: return (rc); } - #if EFSYS_OPT_PHY_STATS __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/ef10_rx.c b/sys/dev/sfxge/common/ef10_rx.c index 20c8f6067425..04d304e47f85 100644 --- a/sys/dev/sfxge/common/ef10_rx.c +++ b/sys/dev/sfxge/common/ef10_rx.c @@ -34,10 +34,8 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 - static __checkReturn efx_rc_t efx_mcdi_init_rxq( __in efx_nic_t *enp, @@ -539,7 +537,6 @@ fail1: } #endif /* EFSYS_OPT_RX_SCALE */ - __checkReturn efx_rc_t ef10_rx_init( __in efx_nic_t *enp) @@ -712,7 +709,6 @@ ef10_rx_scale_tbl_set( { efx_rc_t rc; - if (rss_context == EFX_RSS_CONTEXT_DEFAULT) { if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) { rc = ENOTSUP; @@ -736,7 +732,6 @@ fail1: } #endif /* EFSYS_OPT_RX_SCALE */ - /* * EF10 RX pseudo-header * --------------------- @@ -973,7 +968,6 @@ ef10_rx_qps_packet_info( return (pkt_start); } - #endif __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/ef10_tlv_layout.h b/sys/dev/sfxge/common/ef10_tlv_layout.h index ab724098189e..202e0a9f7b21 100644 --- a/sys/dev/sfxge/common/ef10_tlv_layout.h +++ b/sys/dev/sfxge/common/ef10_tlv_layout.h @@ -85,17 +85,14 @@ * well enough.) */ - #ifndef CI_MGMT_TLV_LAYOUT_H #define CI_MGMT_TLV_LAYOUT_H - /* ---------------------------------------------------------------------------- * General structure (defined by SF-108797-SW) * ---------------------------------------------------------------------------- */ - /* The "end" tag. * * (Note that this is *not* followed by length or value fields: anything after @@ -104,14 +101,12 @@ #define TLV_TAG_END (0xEEEEEEEE) - /* Other special reserved tag values. */ #define TLV_TAG_SKIP (0x00000000) #define TLV_TAG_INVALID (0xFFFFFFFF) - /* TLV partition header. * * In a TLV partition, this must be the first item in the sequence, at offset @@ -133,7 +128,6 @@ struct tlv_partition_header { uint32_t total_length; }; - /* TLV partition trailer. * * In a TLV partition, this must be the last item in the sequence, immediately @@ -149,7 +143,6 @@ struct tlv_partition_trailer { uint32_t checksum; }; - /* Appendable TLV partition header. * * In an appendable TLV partition, this must be the first item in the sequence, @@ -166,13 +159,11 @@ struct tlv_appendable_partition_header { uint16_t reserved; }; - /* ---------------------------------------------------------------------------- * Configuration items * ---------------------------------------------------------------------------- */ - /* NIC global capabilities. */ @@ -184,7 +175,6 @@ struct tlv_global_capabilities { uint32_t flags; }; - /* Siena-style per-port MAC address allocation. * * There are <count> addresses, starting at <base_address> and incrementing @@ -205,7 +195,6 @@ struct tlv_port_mac { uint16_t stride; }; - /* Static VPD. * * This is the portion of VPD which is set at manufacturing time and not @@ -230,7 +219,6 @@ struct tlv_global_static_vpd { uint8_t bytes[]; }; - /* Dynamic VPD. * * This is the portion of VPD which may be changed (e.g. by firmware updates). @@ -255,7 +243,6 @@ struct tlv_global_dynamic_vpd { uint8_t bytes[]; }; - /* "DBI" PCI config space changes. * * This is a set of edits made to the default PCI config space values before @@ -276,7 +263,6 @@ struct tlv_pf_dbi { } items[]; }; - #define TLV_TAG_GLOBAL_DBI (0x00210000) struct tlv_global_dbi { @@ -289,7 +275,6 @@ struct tlv_global_dbi { } items[]; }; - /* Partition subtype codes. * * A subtype may optionally be stored for each type of partition present in @@ -310,7 +295,6 @@ struct tlv_partition_subtype { uint8_t description[]; }; - /* Partition version codes. * * A version may optionally be stored for each type of partition present in @@ -366,7 +350,6 @@ struct tlv_per_pf_pcie_config { uint16_t msix_vec_base; }; - /* Development ONLY. This is a single TLV tag for all the gubbins * that can be set through the MC command-line other than the PCIe * settings. This is a temporary measure. */ @@ -411,7 +394,6 @@ struct tlv_global_port_config { uint32_t max_port_speed; }; - /* Firmware options. * * This is intended for user-configurable selection of optional firmware @@ -468,7 +450,6 @@ struct tlv_0v9_settings { uint16_t panic_high; /* In millivolts */ }; - /* Clock configuration */ #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ @@ -496,7 +477,6 @@ struct tlv_clock_config_medford { uint16_t clk_pcs; /* MHz */ }; - /* EF10-style global pool of MAC addresses. * * There are <count> addresses, starting at <base_address>, which are @@ -537,7 +517,6 @@ struct tlv_pcie_tx_amp_config { uint8_t lane_amp[16]; }; - /* Global PCIe configuration, second revision. This represents the visible PFs * by a bitmap rather than having the number of the highest visible one. As such * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG diff --git a/sys/dev/sfxge/common/ef10_tx.c b/sys/dev/sfxge/common/ef10_tx.c index 557c4c3ca448..189b9868d96c 100644 --- a/sys/dev/sfxge/common/ef10_tx.c +++ b/sys/dev/sfxge/common/ef10_tx.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 #if EFSYS_OPT_QSTATS @@ -393,7 +392,6 @@ ef10_tx_qpio_post( unsigned int added = *addedp; efx_rc_t rc; - if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) { rc = ENOSPC; goto fail1; @@ -717,7 +715,6 @@ ef10_tx_qdesc_checksum_create( (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0); } - __checkReturn efx_rc_t ef10_tx_qpace( __in efx_txq_t *etp, diff --git a/sys/dev/sfxge/common/ef10_vpd.c b/sys/dev/sfxge/common/ef10_vpd.c index 30806f44ae6c..c6facb1c4d67 100644 --- a/sys/dev/sfxge/common/ef10_vpd.c +++ b/sys/dev/sfxge/common/ef10_vpd.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_VPD #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 diff --git a/sys/dev/sfxge/common/efsys.h b/sys/dev/sfxge/common/efsys.h index 5c9a9ba82a5c..37f3deeb2fbc 100644 --- a/sys/dev/sfxge/common/efsys.h +++ b/sys/dev/sfxge/common/efsys.h @@ -159,7 +159,6 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, /* Code inclusion options */ - #define EFSYS_OPT_NAMES 1 #define EFSYS_OPT_SIENA 1 @@ -333,7 +332,6 @@ typedef struct efsys_mem_s { #define EFSYS_MEM_IS_NULL(_esmp) \ ((_esmp)->esm_base == NULL) - #define EFSYS_MEM_ZERO(_esmp, _size) \ do { \ (void) memset((_esmp)->esm_base, 0, (_size)); \ diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index 47a66784beef..383a271fb7ec 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -72,7 +72,6 @@ extern "C" { typedef __success(return == 0) int efx_rc_t; - /* Chip families */ typedef enum efx_family_e { @@ -92,7 +91,6 @@ efx_family( __out efx_family_t *efp, __out unsigned int *membarp); - #define EFX_PCI_VENID_SFC 0x1924 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ @@ -116,7 +114,6 @@ efx_family( #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ - #define EFX_MEM_BAR_SIENA 2 #define EFX_MEM_BAR_HUNTINGTON_PF 2 @@ -127,7 +124,6 @@ efx_family( #define EFX_MEM_BAR_MEDFORD2 0 - /* Error codes */ enum { @@ -153,7 +149,6 @@ efx_crc32_calculate( __in_ecount(length) uint8_t const *input, __in int length); - /* Type prototypes */ typedef struct efx_rxq_s efx_rxq_t; @@ -609,7 +604,6 @@ efx_mac_fcntl_get( __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp); - #if EFSYS_OPT_MAC_STATS #if EFSYS_OPT_NAMES @@ -645,7 +639,6 @@ efx_mac_stats_get_mask( ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) - extern __checkReturn efx_rc_t efx_mac_stats_clear( __in efx_nic_t *enp); @@ -1022,7 +1015,6 @@ typedef enum efx_phy_cap_type_e { EFX_PHY_CAP_NTYPES } efx_phy_cap_type_t; - #define EFX_PHY_CAP_CURRENT 0x00000000 #define EFX_PHY_CAP_DEFAULT 0x00000001 #define EFX_PHY_CAP_PERM 0x00000002 @@ -1097,7 +1089,6 @@ efx_phy_media_type_get( */ #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 - extern __checkReturn efx_rc_t efx_phy_module_get_info( __in efx_nic_t *enp, @@ -1180,7 +1171,6 @@ efx_phy_stats_update( #endif /* EFSYS_OPT_PHY_STATS */ - #if EFSYS_OPT_BIST typedef enum efx_bist_type_e { @@ -1512,7 +1502,6 @@ efx_nic_get_vi_pool( __out uint32_t *rxq_countp, __out uint32_t *txq_countp); - #if EFSYS_OPT_VPD typedef enum efx_vpd_tag_e { @@ -1531,7 +1520,6 @@ typedef struct efx_vpd_value_s { uint8_t evv_value[0x100]; } efx_vpd_value_t; - #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) extern __checkReturn efx_rc_t @@ -1742,7 +1730,6 @@ efx_bootcfg_write( __in_bcount(size) uint8_t *data, __in size_t size); - /* * Processing routines for buffers arranged in the DHCP/BOOTP option format * (see https://tools.ietf.org/html/rfc1533) @@ -1798,7 +1785,6 @@ efx_dhcp_find_end( __in size_t buffer_length, __deref_out uint8_t **endpp); - extern __checkReturn efx_rc_t efx_dhcp_delete_tag( __inout_bcount(buffer_length) uint8_t *bufferp, @@ -1822,7 +1808,6 @@ efx_dhcp_update_tag( __in_bcount_opt(value_length) uint8_t *valuep, __in size_t value_length); - #endif /* EFSYS_OPT_BOOTCFG */ #if EFSYS_OPT_IMAGE_LAYOUT @@ -1875,7 +1860,6 @@ typedef struct efx_image_header_s { #define EFX_IMAGE_HEADER_VERSION (4) #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) - typedef struct efx_image_trailer_s { uint32_t eit_crc; } efx_image_trailer_t; @@ -2076,7 +2060,6 @@ typedef __checkReturn boolean_t #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT - #define EFX_EV_RX_NLABELS 32 #define EFX_EV_TX_NLABELS 32 @@ -2448,7 +2431,6 @@ efx_rx_hash_default_support_get( __in efx_nic_t *enp, __out efx_rx_hash_support_t *supportp); - extern __checkReturn efx_rc_t efx_rx_scale_default_support_get( __in efx_nic_t *enp, @@ -2818,7 +2800,6 @@ extern void efx_tx_qdestroy( __in efx_txq_t *etp); - /* FILTER */ #if EFSYS_OPT_FILTER @@ -2937,7 +2918,6 @@ typedef struct efx_filter_spec_s { uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; } efx_filter_spec_t; - /* Default values for use in filter specifications */ #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff @@ -3124,7 +3104,6 @@ efx_lic_get_id( __out size_t *lengthp, __out_opt uint8_t *bufferp); - extern __checkReturn efx_rc_t efx_lic_find_start( __in efx_nic_t *enp, @@ -3314,7 +3293,6 @@ efx_phy_link_state_get( __in efx_nic_t *enp, __out efx_phy_link_state_t *eplsp); - #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/efx_bootcfg.c b/sys/dev/sfxge/common/efx_bootcfg.c index 64b8204b0afb..bbab4095d7ef 100644 --- a/sys/dev/sfxge/common/efx_bootcfg.c +++ b/sys/dev/sfxge/common/efx_bootcfg.c @@ -76,7 +76,6 @@ typedef struct efx_dhcp_tag_hdr_s { #define DHCP_CALC_TAG_LENGTH(payload_len) \ ((payload_len) + sizeof (efx_dhcp_tag_hdr_t)) - /* Report the layout of bootcfg sectors in NVRAM partition. */ __checkReturn efx_rc_t efx_bootcfg_sector_info( @@ -163,7 +162,6 @@ fail1: return (rc); } - __checkReturn uint8_t efx_dhcp_csum( __in_bcount(size) uint8_t const *data, @@ -399,7 +397,6 @@ fail1: return (rc); } - /* * Delete the given tag from anywhere in the buffer. Copes with * encapsulated tags, and updates or deletes the encapsulating opt as @@ -751,7 +748,6 @@ fail1: return (rc); } - /* * Copy bootcfg sector data to a target buffer which may differ in size. * Optionally corrects format errors in source buffer. diff --git a/sys/dev/sfxge/common/efx_ev.c b/sys/dev/sfxge/common/efx_ev.c index 6edbd96234b7..756b63d2a3df 100644 --- a/sys/dev/sfxge/common/efx_ev.c +++ b/sys/dev/sfxge/common/efx_ev.c @@ -53,8 +53,6 @@ __FBSDID("$FreeBSD$"); (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \ EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff) - - #if EFSYS_OPT_SIENA static __checkReturn efx_rc_t @@ -135,7 +133,6 @@ static const efx_ev_ops_t __efx_ev_ef10_ops = { }; #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ - __checkReturn efx_rc_t efx_ev_init( __in efx_nic_t *enp) @@ -221,7 +218,6 @@ efx_ev_fini( enp->en_mod_flags &= ~EFX_MOD_EV; } - __checkReturn efx_rc_t efx_ev_qcreate( __in efx_nic_t *enp, @@ -903,7 +899,6 @@ siena_ev_tx( EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 && EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 && EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) { - id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR); label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL); diff --git a/sys/dev/sfxge/common/efx_filter.c b/sys/dev/sfxge/common/efx_filter.c index dcfc2e6436a3..34e0c4fa36cb 100644 --- a/sys/dev/sfxge/common/efx_filter.c +++ b/sys/dev/sfxge/common/efx_filter.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_FILTER #if EFSYS_OPT_SIENA @@ -348,7 +347,6 @@ efx_filter_spec_init_tx( spec->efs_dmaq_id = (uint16_t)etp->et_index; } - /* * Specify IPv4 host, transport protocol and port in a filter specification */ @@ -461,7 +459,6 @@ efx_filter_spec_set_mc_def( return (0); } - __checkReturn efx_rc_t efx_filter_spec_set_encap_type( __inout efx_filter_spec_t *spec, @@ -888,7 +885,6 @@ siena_filter_clear_used( EFSYS_ASSERT3U(sftp->sft_used, >=, 0); } - static siena_filter_tbl_id_t siena_filter_tbl_id( __in siena_filter_type_t type) @@ -1176,7 +1172,6 @@ fail1: return (rc); } - static __checkReturn boolean_t siena_filter_equal( __in const siena_filter_spec_t *left, @@ -1186,7 +1181,6 @@ siena_filter_equal( tbl_id = siena_filter_tbl_id(left->sfs_type); - if (left->sfs_type != right->sfs_type) return (B_FALSE); @@ -1480,7 +1474,6 @@ siena_filter_add( efsys_lock_state_t state; uint32_t key; - EFSYS_ASSERT3P(spec, !=, NULL); if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0) diff --git a/sys/dev/sfxge/common/efx_hash.c b/sys/dev/sfxge/common/efx_hash.c index 808351f95e00..47d7fd488732 100644 --- a/sys/dev/sfxge/common/efx_hash.c +++ b/sys/dev/sfxge/common/efx_hash.c @@ -110,7 +110,6 @@ __FBSDID("$FreeBSD$"); _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) - /* Produce a 32-bit hash from 32-bit aligned input */ __checkReturn uint32_t efx_hash_dwords( diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h index 1cde86dc78c8..20ad63efe690 100644 --- a/sys/dev/sfxge/common/efx_impl.h +++ b/sys/dev/sfxge/common/efx_impl.h @@ -44,7 +44,6 @@ #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV #endif - #if EFSYS_OPT_SIENA #include "siena_impl.h" #endif /* EFSYS_OPT_SIENA */ @@ -402,7 +401,6 @@ typedef struct efx_nic_ops_s { #define EFX_RXQ_LIMIT_TARGET 512 #endif - #if EFSYS_OPT_FILTER #if EFSYS_OPT_SIENA @@ -768,7 +766,6 @@ struct efx_nic_s { #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ }; - #define EFX_NIC_MAGIC 0x02121996 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c index 5e4436350592..423020a59320 100644 --- a/sys/dev/sfxge/common/efx_intr.c +++ b/sys/dev/sfxge/common/efx_intr.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_SIENA static __checkReturn efx_rc_t @@ -86,10 +85,8 @@ static __checkReturn boolean_t siena_intr_check_fatal( __in efx_nic_t *enp); - #endif /* EFSYS_OPT_SIENA */ - #if EFSYS_OPT_SIENA static const efx_intr_ops_t __efx_intr_siena_ops = { siena_intr_init, /* eio_init */ @@ -245,7 +242,6 @@ efx_intr_disable_unlocked( eiop->eio_disable_unlocked(enp); } - __checkReturn efx_rc_t efx_intr_trigger( __in efx_nic_t *enp, @@ -303,7 +299,6 @@ efx_intr_fatal( eiop->eio_fatal(enp); } - /* ************************************************************************* */ /* ************************************************************************* */ /* ************************************************************************* */ @@ -523,7 +518,6 @@ siena_intr_status_message( *fatalp = B_FALSE; } - static void siena_intr_fatal( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/efx_lic.c b/sys/dev/sfxge/common/efx_lic.c index 276a35856916..1b5aac511a81 100644 --- a/sys/dev/sfxge/common/efx_lic.c +++ b/sys/dev/sfxge/common/efx_lic.c @@ -127,7 +127,6 @@ efx_lic_v1v2_finish_partition( #endif /* EFSYS_OPT_HUNTINGTON | EFSYS_OPT_SIENA */ - #if EFSYS_OPT_SIENA static __checkReturn efx_rc_t @@ -318,7 +317,6 @@ static const efx_lic_ops_t __efx_lic_v3_ops = { #endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ - /* V1 Licensing - used in Siena Modena only */ #if EFSYS_OPT_SIENA @@ -549,7 +547,6 @@ fail1: return (B_FALSE); } - __checkReturn efx_rc_t efx_lic_v1v2_read_key( __in efx_nic_t *enp, @@ -661,7 +658,6 @@ efx_lic_v1v2_create_partition( return (0); } - __checkReturn efx_rc_t efx_lic_v1v2_finish_partition( __in efx_nic_t *enp, @@ -676,7 +672,6 @@ efx_lic_v1v2_finish_partition( #endif /* EFSYS_OPT_HUNTINGTON | EFSYS_OPT_SIENA */ - /* V2 Licensing - used by Huntington family only. See SF-113611-TC */ #if EFSYS_OPT_HUNTINGTON @@ -1271,7 +1266,6 @@ fail1: return (rc); } - #endif /* EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ __checkReturn efx_rc_t @@ -1287,7 +1281,6 @@ efx_lic_init( EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_LIC)); switch (enp->en_family) { - #if EFSYS_OPT_SIENA case EFX_FAMILY_SIENA: elop = &__efx_lic_v1_ops; @@ -1359,7 +1352,6 @@ efx_lic_fini( enp->en_mod_flags &= ~EFX_MOD_LIC; } - __checkReturn efx_rc_t efx_lic_update_licenses( __in efx_nic_t *enp) @@ -1538,7 +1530,6 @@ efx_lic_find_key( startp, lengthp)); } - /* * Validate that the buffer contains a single key in a recognised format. * An empty or terminator buffer is not accepted as a valid key. @@ -1679,7 +1670,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t efx_lic_finish_partition( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c index a6b1f5454be3..b107a0311894 100644 --- a/sys/dev/sfxge/common/efx_mac.c +++ b/sys/dev/sfxge/common/efx_mac.c @@ -516,7 +516,6 @@ efx_mac_filter_default_rxq_clear( emop->emo_filter_default_rxq_clear(enp); } - #if EFSYS_OPT_MAC_STATS #if EFSYS_OPT_NAMES @@ -826,7 +825,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t efx_mac_stats_update( __in efx_nic_t *enp, @@ -907,7 +905,6 @@ fail1: return (rc); } - #if EFSYS_OPT_SIENA #define EFX_MAC_HASH_BITS (1 << 8) diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c index 0dca9f8c7ac2..05f7b3946613 100644 --- a/sys/dev/sfxge/common/efx_mcdi.c +++ b/sys/dev/sfxge/common/efx_mcdi.c @@ -57,8 +57,6 @@ __FBSDID("$FreeBSD$"); * response with ERROR=1 and DATALEN=0 until a request is seen with NOT_EPOCH=0. */ - - #if EFSYS_OPT_SIENA static const efx_mcdi_ops_t __efx_mcdi_siena_ops = { @@ -89,8 +87,6 @@ static const efx_mcdi_ops_t __efx_mcdi_ef10_ops = { #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ - - __checkReturn efx_rc_t efx_mcdi_init( __in efx_nic_t *enp, @@ -344,7 +340,6 @@ efx_mcdi_request_start( emrp->emr_in_buf, emrp->emr_in_length); } - static void efx_mcdi_read_response_header( __in efx_nic_t *enp, @@ -504,7 +499,6 @@ efx_mcdi_finish_response( #endif /* EFSYS_OPT_MCDI_LOGGING */ } - __checkReturn boolean_t efx_mcdi_request_poll( __in efx_nic_t *enp) @@ -1274,7 +1268,6 @@ fail1: return (rc); } - /* * Internal routines for for specific MCDI requests. */ @@ -1770,7 +1763,6 @@ fail1: #endif /* EFSYS_OPT_BIST */ - /* Enable logging of some events (e.g. link state changes) */ __checkReturn efx_rc_t efx_mcdi_log_ctrl( @@ -1806,7 +1798,6 @@ fail1: return (rc); } - #if EFSYS_OPT_MAC_STATS typedef enum efx_stats_action_e { @@ -2132,7 +2123,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t efx_mcdi_get_workarounds( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/efx_mcdi.h b/sys/dev/sfxge/common/efx_mcdi.h index 4f75d9c726cb..480f3f4f46fc 100644 --- a/sys/dev/sfxge/common/efx_mcdi.h +++ b/sys/dev/sfxge/common/efx_mcdi.h @@ -196,7 +196,6 @@ efx_mcdi_mac_spoofing_supported( __in efx_nic_t *enp, __out boolean_t *supportedp); - #if EFSYS_OPT_BIST #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 extern __checkReturn efx_rc_t @@ -236,7 +235,6 @@ efx_mcdi_mac_stats_periodic( __in uint16_t period_ms, __in boolean_t events); - #if EFSYS_OPT_LOOPBACK extern __checkReturn efx_rc_t efx_mcdi_get_loopback_modes( diff --git a/sys/dev/sfxge/common/efx_mon.c b/sys/dev/sfxge/common/efx_mon.c index 822bd90c1f08..9988db9545c3 100644 --- a/sys/dev/sfxge/common/efx_mon.c +++ b/sys/dev/sfxge/common/efx_mon.c @@ -73,7 +73,6 @@ static const efx_mon_ops_t __efx_mon_mcdi_ops = { }; #endif - __checkReturn efx_rc_t efx_mon_init( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/efx_nic.c b/sys/dev/sfxge/common/efx_nic.c index b2b411fc9ab1..0fe5045f73c2 100644 --- a/sys/dev/sfxge/common/efx_nic.c +++ b/sys/dev/sfxge/common/efx_nic.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - __checkReturn efx_rc_t efx_family( __in uint16_t venid, @@ -118,7 +117,6 @@ efx_family( return (ENOTSUP); } - #if EFSYS_OPT_SIENA static const efx_nic_ops_t __efx_nic_siena_ops = { @@ -203,7 +201,6 @@ static const efx_nic_ops_t __efx_nic_medford2_ops = { #endif /* EFSYS_OPT_MEDFORD2 */ - __checkReturn efx_rc_t efx_nic_create( __in efx_family_t family, @@ -442,7 +439,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t efx_nic_get_vi_pool( __in efx_nic_t *enp, @@ -482,7 +478,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t efx_nic_init( __in efx_nic_t *enp) @@ -725,7 +720,6 @@ efx_nic_set_hw_unavailable( enop->eno_set_hw_unavailable(enp); } - #if EFSYS_OPT_DIAG __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/efx_nvram.c b/sys/dev/sfxge/common/efx_nvram.c index b0bb785fe9dd..c6518ca2eac5 100644 --- a/sys/dev/sfxge/common/efx_nvram.c +++ b/sys/dev/sfxge/common/efx_nvram.c @@ -512,7 +512,6 @@ fail1: return (rc); } - void efx_nvram_fini( __in efx_nic_t *enp) @@ -948,7 +947,6 @@ fail1: return (rc); } - /* * MC_CMD_NVRAM_UPDATE_FINISH_V2 must be used to support firmware-verified * NVRAM updates. Older firmware will ignore the flags field in the request. @@ -1059,7 +1057,6 @@ efx_mcdi_nvram_test( result = MCDI_OUT_DWORD(req, NVRAM_TEST_OUT_RESULT); if (result == MC_CMD_NVRAM_TEST_FAIL) { - EFSYS_PROBE1(nvram_test_failure, int, partn); rc = (EINVAL); @@ -1080,5 +1077,4 @@ fail1: #endif /* EFSYS_OPT_DIAG */ - #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ diff --git a/sys/dev/sfxge/common/efx_phy.c b/sys/dev/sfxge/common/efx_phy.c index ad8608bf2c63..956701f1a2d8 100644 --- a/sys/dev/sfxge/common/efx_phy.c +++ b/sys/dev/sfxge/common/efx_phy.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_SIENA static const efx_phy_ops_t __efx_phy_siena_ops = { siena_phy_power, /* epo_power */ @@ -484,7 +483,6 @@ efx_phy_stats_update( #endif /* EFSYS_OPT_PHY_STATS */ - #if EFSYS_OPT_BIST __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/efx_phy_ids.h b/sys/dev/sfxge/common/efx_phy_ids.h index d3d023579b71..986be5b90ca4 100644 --- a/sys/dev/sfxge/common/efx_phy_ids.h +++ b/sys/dev/sfxge/common/efx_phy_ids.h @@ -49,5 +49,4 @@ typedef enum efx_phy_type_e { /* GENERATED BY scripts/genfwdef */ EFX_PHY_XFI_FARMI = 19, } efx_phy_type_t; - #endif /* _SYS_EFX_PHY_IDS_H */ diff --git a/sys/dev/sfxge/common/efx_regs.h b/sys/dev/sfxge/common/efx_regs.h index 62d17ec1421f..9593e3102ebd 100644 --- a/sys/dev/sfxge/common/efx_regs.h +++ b/sys/dev/sfxge/common/efx_regs.h @@ -35,12 +35,10 @@ #ifndef _SYS_EFX_REGS_H #define _SYS_EFX_REGS_H - #ifdef __cplusplus extern "C" { #endif - /************************************************************************** * * Falcon/Siena registers and descriptors @@ -94,7 +92,6 @@ extern "C" { #define FRF_AB_EE_VPD_EN_LBN 0 #define FRF_AB_EE_VPD_EN_WIDTH 1 - /* * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): * PCIE SerDes control register 0 to 3 @@ -163,7 +160,6 @@ extern "C" { #define FRF_AB_PCIE_LODRV_LBN 0 #define FRF_AB_PCIE_LODRV_WIDTH 8 - /* * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): * PCIE SerDes control register 4 and 5 @@ -210,7 +206,6 @@ extern "C" { #define FRF_AB_PCIE_DEQ0_LBN 0 #define FRF_AB_PCIE_DEQ0_WIDTH 4 - /* * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): * PCIE PCS control and status register @@ -251,7 +246,6 @@ extern "C" { #define FRF_AB_PCIE_PRBSSEL_LBN 0 #define FRF_AB_PCIE_PRBSSEL_WIDTH 8 - /* * FR_AB_HW_INIT_REG_SF(128bit): * Hardware initialization register @@ -306,7 +300,6 @@ extern "C" { #define FRF_AZ_TLP_TD_LBN 0 #define FRF_AZ_TLP_TD_WIDTH 1 - /* * FR_AB_NIC_STAT_REG_SF(128bit): * NIC status register @@ -339,7 +332,6 @@ extern "C" { #define FRF_AB_STRAP_PINS_LBN 0 #define FRF_AB_STRAP_PINS_WIDTH 3 - /* * FR_AB_GLB_CTL_REG_SF(128bit): * Global control register @@ -438,7 +430,6 @@ extern "C" { #define FRF_AB_SWRST_LBN 0 #define FRF_AB_SWRST_WIDTH 1 - /* * FR_AZ_IOM_IND_ADR_REG(32bit): * IO-mapped indirect access address register @@ -451,7 +442,6 @@ extern "C" { #define FRF_AZ_IOM_IND_ADR_LBN 0 #define FRF_AZ_IOM_IND_ADR_WIDTH 24 - /* * FR_AZ_IOM_IND_DAT_REG(32bit): * IO-mapped indirect access data register @@ -462,7 +452,6 @@ extern "C" { #define FRF_AZ_IOM_IND_DAT_LBN 0 #define FRF_AZ_IOM_IND_DAT_WIDTH 32 - /* * FR_AZ_ADR_REGION_REG(128bit): * Address region register @@ -479,7 +468,6 @@ extern "C" { #define FRF_AZ_ADR_REGION0_LBN 0 #define FRF_AZ_ADR_REGION0_WIDTH 18 - /* * FR_AZ_INT_EN_REG_KER(128bit): * Kernel driver Interrupt enable register @@ -496,7 +484,6 @@ extern "C" { #define FRF_AZ_DRV_INT_EN_KER_LBN 0 #define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 - /* * FR_AZ_INT_EN_REG_CHAR(128bit): * Char Driver interrupt enable register @@ -513,7 +500,6 @@ extern "C" { #define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 #define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 - /* * FR_AZ_INT_ADR_REG_KER(128bit): * Interrupt host address for Kernel driver @@ -530,7 +516,6 @@ extern "C" { #define FRF_AZ_INT_ADR_KER_DW1_LBN 32 #define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 - /* * FR_AZ_INT_ADR_REG_CHAR(128bit): * Interrupt host address for Char driver @@ -547,7 +532,6 @@ extern "C" { #define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 #define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 - /* * FR_AA_INT_ACK_KER(32bit): * Kernel interrupt acknowledge register @@ -558,7 +542,6 @@ extern "C" { #define FRF_AA_INT_ACK_KER_FIELD_LBN 0 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 - /* * FR_BZ_INT_ISR0_REG(128bit): * Function 0 Interrupt Acknowlege Status register @@ -573,7 +556,6 @@ extern "C" { #define FRF_BZ_INT_ISR_REG_DW1_LBN 32 #define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 - /* * FR_AB_EE_SPI_HCMD_REG(128bit): * SPI host command register @@ -598,7 +580,6 @@ extern "C" { #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 - /* * FR_CZ_USR_EV_CFG(32bit): * User Level Event Configuration register @@ -611,7 +592,6 @@ extern "C" { #define FRF_CZ_DFLT_EVQ_LBN 0 #define FRF_CZ_DFLT_EVQ_WIDTH 10 - /* * FR_AB_EE_SPI_HADR_REG(128bit): * SPI host address register @@ -624,7 +604,6 @@ extern "C" { #define FRF_AB_EE_SPI_HADR_ADR_LBN 0 #define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 - /* * FR_AB_EE_SPI_HDATA_REG(128bit): * SPI host data register @@ -641,7 +620,6 @@ extern "C" { #define FRF_AB_EE_SPI_HDATA0_LBN 0 #define FRF_AB_EE_SPI_HDATA0_WIDTH 32 - /* * FR_AB_EE_BASE_PAGE_REG(128bit): * Expansion ROM base mirror register @@ -654,7 +632,6 @@ extern "C" { #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 - /* * FR_AB_EE_VPD_SW_CNTL_REG(128bit): * VPD access SW control register @@ -669,7 +646,6 @@ extern "C" { #define FRF_AB_EE_VPD_CYC_ADR_LBN 0 #define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 - /* * FR_AB_EE_VPD_SW_DATA_REG(128bit): * VPD access SW data register @@ -680,7 +656,6 @@ extern "C" { #define FRF_AB_EE_VPD_CYC_DAT_LBN 0 #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 - /* * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): * Indirect Access to PCIE Core registers @@ -695,7 +670,6 @@ extern "C" { #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 - /* * FR_AB_GPIO_CTL_REG(128bit): * GPIO control register @@ -820,7 +794,6 @@ extern "C" { #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 - /* * FR_AZ_FATAL_INTR_REG_KER(128bit): * Fatal interrupt register for Kernel @@ -885,7 +858,6 @@ extern "C" { #define FRF_AZ_SRM_PERR_INT_KER_LBN 0 #define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 - /* * FR_AZ_FATAL_INTR_REG_CHAR(128bit): * Fatal interrupt register for Char @@ -950,7 +922,6 @@ extern "C" { #define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 #define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 - /* * FR_AZ_DP_CTRL_REG(128bit): * Datapath control register @@ -961,7 +932,6 @@ extern "C" { #define FRF_AZ_FLS_EVQ_ID_LBN 0 #define FRF_AZ_FLS_EVQ_ID_WIDTH 12 - /* * FR_AZ_MEM_STAT_REG(128bit): * Memory status register @@ -990,7 +960,6 @@ extern "C" { #define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 #define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 - /* * FR_PORT0_CS_DEBUG_REG(128bit): * Debug register @@ -1036,7 +1005,6 @@ extern "C" { #define FRF_AZ_CS_DEBUG_EN_LBN 0 #define FRF_AZ_CS_DEBUG_EN_WIDTH 1 - /* * FR_AZ_DRIVER_REG(128bit): * Driver scratch register [0-7] @@ -1049,7 +1017,6 @@ extern "C" { #define FRF_AZ_DRIVER_DW0_LBN 0 #define FRF_AZ_DRIVER_DW0_WIDTH 32 - /* * FR_AZ_ALTERA_BUILD_REG(128bit): * Altera build register @@ -1060,7 +1027,6 @@ extern "C" { #define FRF_AZ_ALTERA_BUILD_VER_LBN 0 #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 - /* * FR_AZ_CSR_SPARE_REG(128bit): * Spare register @@ -1079,7 +1045,6 @@ extern "C" { #define FRF_AZ_CSR_SPARE_BITS_LBN 0 #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 - /* * FR_BZ_DEBUG_DATA_OUT_REG(128bit): * Live Debug and Debug 2 out ports @@ -1092,7 +1057,6 @@ extern "C" { #define FRF_BZ_DEBUG1_PORT_LBN 0 #define FRF_BZ_DEBUG1_PORT_WIDTH 25 - /* * FR_BZ_EVQ_RPTR_REGP0(32bit): * Event queue read pointer register @@ -1132,7 +1096,6 @@ extern "C" { #define FRF_AZ_EVQ_RPTR_LBN 0 #define FRF_AZ_EVQ_RPTR_WIDTH 15 - /* * FR_BZ_TIMER_COMMAND_REGP0(128bit): * Timer Command Registers @@ -1175,7 +1138,6 @@ extern "C" { #define FRF_AB_TC_TIMER_VAL_LBN 0 #define FRF_AB_TC_TIMER_VAL_WIDTH 12 - /* * FR_AZ_DRV_EV_REG(128bit): * Driver generated event register @@ -1192,7 +1154,6 @@ extern "C" { #define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 #define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 - /* * FR_AZ_EVQ_CTL_REG(128bit): * Event queue control register @@ -1211,7 +1172,6 @@ extern "C" { #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 - /* * FR_AZ_EVQ_CNT1_REG(128bit): * Event counter 1 register @@ -1234,7 +1194,6 @@ extern "C" { #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 - /* * FR_AZ_EVQ_CNT2_REG(128bit): * Event counter 2 register @@ -1257,7 +1216,6 @@ extern "C" { #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 - /* * FR_CZ_USR_EV_REG(32bit): * Event mailbox register @@ -1270,7 +1228,6 @@ extern "C" { #define FRF_CZ_USR_EV_DATA_LBN 0 #define FRF_CZ_USR_EV_DATA_WIDTH 32 - /* * FR_AZ_BUF_TBL_CFG_REG(128bit): * Buffer table configuration register @@ -1281,7 +1238,6 @@ extern "C" { #define FRF_AZ_BUF_TBL_MODE_LBN 3 #define FRF_AZ_BUF_TBL_MODE_WIDTH 1 - /* * FR_AZ_SRM_RX_DC_CFG_REG(128bit): * SRAM receive descriptor cache configuration register @@ -1294,7 +1250,6 @@ extern "C" { #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 - /* * FR_AZ_SRM_TX_DC_CFG_REG(128bit): * SRAM transmit descriptor cache configuration register @@ -1305,7 +1260,6 @@ extern "C" { #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 - /* * FR_AZ_SRM_CFG_REG(128bit): * SRAM configuration register @@ -1330,7 +1284,6 @@ extern "C" { #define FRF_AZ_SRM_BANK_SIZE_LBN 0 #define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 - /* * FR_AZ_BUF_TBL_UPD_REG(128bit): * Buffer table update register @@ -1347,7 +1300,6 @@ extern "C" { #define FRF_AZ_BUF_CLR_START_ID_LBN 0 #define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 - /* * FR_AZ_SRM_UPD_EVQ_REG(128bit): * Buffer table update register @@ -1358,7 +1310,6 @@ extern "C" { #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 - /* * FR_AZ_SRAM_PARITY_REG(128bit): * SRAM parity register. @@ -1377,7 +1328,6 @@ extern "C" { #define FRF_AB_FORCE_SRAM_PERR_LBN 0 #define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 - /* * FR_AZ_RX_CFG_REG(128bit): * Receive configuration register @@ -1442,7 +1392,6 @@ extern "C" { #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 - /* * FR_AZ_RX_FILTER_CTL_REG(128bit): * Receive filter control registers @@ -1483,7 +1432,6 @@ extern "C" { #define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 - /* * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): * Receive flush descriptor queue register @@ -1496,7 +1444,6 @@ extern "C" { #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 - /* * FR_BZ_RX_DESC_UPD_REGP0(128bit): * Receive descriptor update register. @@ -1541,7 +1488,6 @@ extern "C" { #define FRF_AZ_RX_DESC_DW1_LBN 32 #define FRF_AZ_RX_DESC_DW1_WIDTH 32 - /* * FR_AZ_RX_DC_CFG_REG(128bit): * Receive descriptor cache configuration register @@ -1558,7 +1504,6 @@ extern "C" { #define FFE_AZ_RX_DC_SIZE_16 1 #define FFE_AZ_RX_DC_SIZE_8 0 - /* * FR_AZ_RX_DC_PF_WM_REG(128bit): * Receive descriptor cache pre-fetch watermark register @@ -1571,7 +1516,6 @@ extern "C" { #define FRF_AZ_RX_DC_PF_LWM_LBN 0 #define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 - /* * FR_BZ_RX_RSS_TKEY_REG(128bit): * RSS Toeplitz hash key @@ -1590,7 +1534,6 @@ extern "C" { #define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 #define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 - /* * FR_AZ_RX_NODESC_DROP_REG(128bit): * Receive dropped packet counter register @@ -1601,7 +1544,6 @@ extern "C" { #define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 #define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 - /* * FR_AZ_RX_SELF_RST_REG(128bit): * Receive self reset register @@ -1620,7 +1562,6 @@ extern "C" { #define FRF_AZ_RX_MAX_LU_LAT_LBN 0 #define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 - /* * FR_AZ_RX_DEBUG_REG(128bit): * undocumented register @@ -1635,7 +1576,6 @@ extern "C" { #define FRF_AZ_RX_DEBUG_DW1_LBN 32 #define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 - /* * FR_AZ_RX_PUSH_DROP_REG(128bit): * Receive descriptor push dropped counter register @@ -1646,7 +1586,6 @@ extern "C" { #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 - /* * FR_CZ_RX_RSS_IPV6_REG1(128bit): * IPv6 RSS Toeplitz hash key low bytes @@ -1665,7 +1604,6 @@ extern "C" { #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 - /* * FR_CZ_RX_RSS_IPV6_REG2(128bit): * IPv6 RSS Toeplitz hash key middle bytes @@ -1684,7 +1622,6 @@ extern "C" { #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 - /* * FR_CZ_RX_RSS_IPV6_REG3(128bit): * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings @@ -1705,7 +1642,6 @@ extern "C" { #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 - /* * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): * Transmit flush descriptor queue register @@ -1718,7 +1654,6 @@ extern "C" { #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 - /* * FR_BZ_TX_DESC_UPD_REGP0(128bit): * Transmit descriptor update register. @@ -1765,7 +1700,6 @@ extern "C" { #define FRF_AZ_TX_DESC_DW2_LBN 64 #define FRF_AZ_TX_DESC_DW2_WIDTH 31 - /* * FR_AZ_TX_DC_CFG_REG(128bit): * Transmit descriptor cache configuration register @@ -1779,7 +1713,6 @@ extern "C" { #define FFE_AZ_TX_DC_SIZE_16 1 #define FFE_AZ_TX_DC_SIZE_8 0 - /* * FR_AA_TX_CHKSM_CFG_REG(128bit): * Transmit checksum configuration register @@ -1796,7 +1729,6 @@ extern "C" { #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 - /* * FR_AZ_TX_CFG_REG(128bit): * Transmit configuration register @@ -1839,7 +1771,6 @@ extern "C" { #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 - /* * FR_AZ_TX_PUSH_DROP_REG(128bit): * Transmit push dropped register @@ -1850,7 +1781,6 @@ extern "C" { #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 - /* * FR_AZ_TX_RESERVED_REG(128bit): * Transmit configuration register @@ -1921,7 +1851,6 @@ extern "C" { #define FFE_AZ_TX_MAX_PREF_8 1 #define FFE_AZ_TX_MAX_PREF_OFF 0 - /* * FR_BZ_TX_PACE_REG(128bit): * Transmit pace control register @@ -1944,7 +1873,6 @@ extern "C" { #define FRF_AZ_TX_PACE_BIN_TH_LBN 0 #define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 - /* * FR_AZ_TX_PACE_DROP_QID_REG(128bit): * PACE Drop QID Counter @@ -1955,7 +1883,6 @@ extern "C" { #define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 #define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 - /* * FR_AB_TX_VLAN_REG(128bit): * Transmit VLAN tag register @@ -2014,7 +1941,6 @@ extern "C" { #define FRF_AB_TX_VLAN0_LBN 0 #define FRF_AB_TX_VLAN0_WIDTH 12 - /* * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): * Transmit filter control register @@ -2089,7 +2015,6 @@ extern "C" { #define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 #define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 - /* * FR_AB_TX_IPFIL_TBL(128bit): * Transmit IP source address filter table @@ -2108,7 +2033,6 @@ extern "C" { #define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 #define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 - /* * FR_AB_MD_TXD_REG(128bit): * PHY management transmit data register @@ -2119,7 +2043,6 @@ extern "C" { #define FRF_AB_MD_TXD_LBN 0 #define FRF_AB_MD_TXD_WIDTH 16 - /* * FR_AB_MD_RXD_REG(128bit): * PHY management receive data register @@ -2130,7 +2053,6 @@ extern "C" { #define FRF_AB_MD_RXD_LBN 0 #define FRF_AB_MD_RXD_WIDTH 16 - /* * FR_AB_MD_CS_REG(128bit): * PHY management configuration & status register @@ -2161,7 +2083,6 @@ extern "C" { #define FRF_AB_MD_WRC_LBN 0 #define FRF_AB_MD_WRC_WIDTH 1 - /* * FR_AB_MD_PHY_ADR_REG(128bit): * PHY management PHY address register @@ -2172,7 +2093,6 @@ extern "C" { #define FRF_AB_MD_PHY_ADR_LBN 0 #define FRF_AB_MD_PHY_ADR_WIDTH 16 - /* * FR_AB_MD_ID_REG(128bit): * PHY management ID register @@ -2185,7 +2105,6 @@ extern "C" { #define FRF_AB_MD_DEV_ADR_LBN 6 #define FRF_AB_MD_DEV_ADR_WIDTH 5 - /* * FR_AB_MD_STAT_REG(128bit): * PHY management status & mask register @@ -2204,7 +2123,6 @@ extern "C" { #define FRF_AB_MD_BSY_LBN 0 #define FRF_AB_MD_BSY_WIDTH 1 - /* * FR_AB_MAC_STAT_DMA_REG(128bit): * Port MAC statistical counter DMA register @@ -2221,7 +2139,6 @@ extern "C" { #define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 - /* * FR_AB_MAC_CTRL_REG(128bit): * Port MAC control register @@ -2264,7 +2181,6 @@ extern "C" { #define FRF_BB_XG_PHY_INT_MASK_LBN 0 #define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 - /* * FR_AB_MAC_MC_HASH_REG0(128bit): * Multicast address hash table @@ -2283,7 +2199,6 @@ extern "C" { #define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 #define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 - /* * FR_AB_MAC_MC_HASH_REG1(128bit): * Multicast address hash table @@ -2302,7 +2217,6 @@ extern "C" { #define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 #define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 - /* * FR_AB_GM_CFG1_REG(32bit): * GMAC configuration register 1 @@ -2337,7 +2251,6 @@ extern "C" { #define FRF_AB_GM_TX_EN_LBN 0 #define FRF_AB_GM_TX_EN_WIDTH 1 - /* * FR_AB_GM_CFG2_REG(32bit): * GMAC configuration register 2 @@ -2362,7 +2275,6 @@ extern "C" { #define FRF_AB_GM_FD_LBN 0 #define FRF_AB_GM_FD_WIDTH 1 - /* * FR_AB_GM_IPG_REG(32bit): * GMAC IPG register @@ -2379,7 +2291,6 @@ extern "C" { #define FRF_AB_GM_B2B_IPG_LBN 0 #define FRF_AB_GM_B2B_IPG_WIDTH 7 - /* * FR_AB_GM_HD_REG(32bit): * GMAC half duplex register @@ -2402,7 +2313,6 @@ extern "C" { #define FRF_AB_GM_COL_WIN_LBN 0 #define FRF_AB_GM_COL_WIN_WIDTH 10 - /* * FR_AB_GM_MAX_FLEN_REG(32bit): * GMAC maximum frame length register @@ -2413,7 +2323,6 @@ extern "C" { #define FRF_AB_GM_MAX_FLEN_LBN 0 #define FRF_AB_GM_MAX_FLEN_WIDTH 16 - /* * FR_AB_GM_TEST_REG(32bit): * GMAC test register @@ -2430,7 +2339,6 @@ extern "C" { #define FRF_AB_GM_SHORT_SLOT_LBN 0 #define FRF_AB_GM_SHORT_SLOT_WIDTH 1 - /* * FR_AB_GM_ADR1_REG(32bit): * GMAC station address register 1 @@ -2447,7 +2355,6 @@ extern "C" { #define FRF_AB_GM_ADR_B3_LBN 0 #define FRF_AB_GM_ADR_B3_WIDTH 8 - /* * FR_AB_GM_ADR2_REG(32bit): * GMAC station address register 2 @@ -2460,7 +2367,6 @@ extern "C" { #define FRF_AB_GM_ADR_B5_LBN 16 #define FRF_AB_GM_ADR_B5_WIDTH 8 - /* * FR_AB_GMF_CFG0_REG(32bit): * GMAC FIFO configuration register 0 @@ -2499,7 +2405,6 @@ extern "C" { #define FRF_AB_GMF_HSTRSTWT_LBN 0 #define FRF_AB_GMF_HSTRSTWT_WIDTH 1 - /* * FR_AB_GMF_CFG1_REG(32bit): * GMAC FIFO configuration register 1 @@ -2512,7 +2417,6 @@ extern "C" { #define FRF_AB_GMF_CFGXOFFRTX_LBN 0 #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 - /* * FR_AB_GMF_CFG2_REG(32bit): * GMAC FIFO configuration register 2 @@ -2525,7 +2429,6 @@ extern "C" { #define FRF_AB_GMF_CFGLWM_LBN 0 #define FRF_AB_GMF_CFGLWM_WIDTH 6 - /* * FR_AB_GMF_CFG3_REG(32bit): * GMAC FIFO configuration register 3 @@ -2538,7 +2441,6 @@ extern "C" { #define FRF_AB_GMF_CFGFTTH_LBN 0 #define FRF_AB_GMF_CFGFTTH_WIDTH 6 - /* * FR_AB_GMF_CFG4_REG(32bit): * GMAC FIFO configuration register 4 @@ -2549,7 +2451,6 @@ extern "C" { #define FRF_AB_GMF_HSTFLTRFRM_LBN 0 #define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 - /* * FR_AB_GMF_CFG5_REG(32bit): * GMAC FIFO configuration register 5 @@ -2570,7 +2471,6 @@ extern "C" { #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 - /* * FR_BB_TX_SRC_MAC_TBL(128bit): * Transmit IP source address filter table @@ -2593,7 +2493,6 @@ extern "C" { #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 - /* * FR_BB_TX_SRC_MAC_CTL_REG(128bit): * Transmit MAC source address filter control @@ -2610,7 +2509,6 @@ extern "C" { #define FRF_BB_TX_MAC_QID_SEL_LBN 0 #define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 - /* * FR_AB_XM_ADR_LO_REG(128bit): * XGMAC address register low @@ -2621,7 +2519,6 @@ extern "C" { #define FRF_AB_XM_ADR_LO_LBN 0 #define FRF_AB_XM_ADR_LO_WIDTH 32 - /* * FR_AB_XM_ADR_HI_REG(128bit): * XGMAC address register high @@ -2632,7 +2529,6 @@ extern "C" { #define FRF_AB_XM_ADR_HI_LBN 0 #define FRF_AB_XM_ADR_HI_WIDTH 16 - /* * FR_AB_XM_GLB_CFG_REG(128bit): * XGMAC global configuration @@ -2657,7 +2553,6 @@ extern "C" { #define FRF_AB_XM_CORE_RST_LBN 0 #define FRF_AB_XM_CORE_RST_WIDTH 1 - /* * FR_AB_XM_TX_CFG_REG(128bit): * XGMAC transmit configuration @@ -2684,7 +2579,6 @@ extern "C" { #define FRF_AB_XM_TX_RST_LBN 0 #define FRF_AB_XM_TX_RST_WIDTH 1 - /* * FR_AB_XM_RX_CFG_REG(128bit): * XGMAC receive configuration @@ -2715,7 +2609,6 @@ extern "C" { #define FRF_AB_XM_RX_RST_LBN 0 #define FRF_AB_XM_RX_RST_WIDTH 1 - /* * FR_AB_XM_MGT_INT_MASK(128bit): * documentation to be written for sum_XM_MGT_INT_MASK @@ -2736,7 +2629,6 @@ extern "C" { #define FRF_AB_XM_MSK_LCLFLT_LBN 0 #define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 - /* * FR_AB_XM_FC_REG(128bit): * XGMAC flow control register @@ -2763,7 +2655,6 @@ extern "C" { #define FRF_AB_XM_DIS_FCNTL_LBN 0 #define FRF_AB_XM_DIS_FCNTL_WIDTH 1 - /* * FR_AB_XM_PAUSE_TIME_REG(128bit): * XGMAC pause time register @@ -2776,7 +2667,6 @@ extern "C" { #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 - /* * FR_AB_XM_TX_PARAM_REG(128bit): * XGMAC transmit parameter register @@ -2793,7 +2683,6 @@ extern "C" { #define FRF_AB_XM_PAD_CHAR_LBN 0 #define FRF_AB_XM_PAD_CHAR_WIDTH 8 - /* * FR_AB_XM_RX_PARAM_REG(128bit): * XGMAC receive parameter register @@ -2806,7 +2695,6 @@ extern "C" { #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 - /* * FR_AB_XM_MGT_INT_MSK_REG(128bit): * XGMAC management interrupt mask register @@ -2825,7 +2713,6 @@ extern "C" { #define FRF_AB_XM_LCLFLT_LBN 0 #define FRF_AB_XM_LCLFLT_WIDTH 1 - /* * FR_AB_XX_PWR_RST_REG(128bit): * XGXS/XAUI powerdown/reset register @@ -2888,7 +2775,6 @@ extern "C" { #define FRF_AB_XX_RST_XX_EN_LBN 0 #define FRF_AB_XX_RST_XX_EN_WIDTH 1 - /* * FR_AB_XX_SD_CTL_REG(128bit): * XGXS/XAUI powerdown/reset control register @@ -2925,7 +2811,6 @@ extern "C" { #define FRF_AB_XX_LPBKA_LBN 0 #define FRF_AB_XX_LPBKA_WIDTH 1 - /* * FR_AB_XX_TXDRV_CTL_REG(128bit): * XAUI SerDes transmit drive control register @@ -2950,7 +2835,6 @@ extern "C" { #define FRF_AB_XX_DTXA_LBN 0 #define FRF_AB_XX_DTXA_WIDTH 4 - /* * FR_AB_XX_PRBS_CTL_REG(128bit): * documentation to be written for sum_XX_PRBS_CTL_REG @@ -3007,7 +2891,6 @@ extern "C" { #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 - /* * FR_AB_XX_PRBS_CHK_REG(128bit): * documentation to be written for sum_XX_PRBS_CHK_REG @@ -3050,7 +2933,6 @@ extern "C" { #define FRF_AB_XX_CH0_ERR_CHK_LBN 0 #define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 - /* * FR_AB_XX_PRBS_ERR_REG(128bit): * documentation to be written for sum_XX_PRBS_ERR_REG @@ -3067,7 +2949,6 @@ extern "C" { #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 - /* * FR_AB_XX_CORE_STAT_REG(128bit): * XAUI XGXS core status register @@ -3140,7 +3021,6 @@ extern "C" { #define FRF_AB_XX_DISPERR_CH0_LBN 0 #define FRF_AB_XX_DISPERR_CH0_WIDTH 1 - /* * FR_AA_RX_DESC_PTR_TBL_KER(128bit): * Receive descriptor pointer table @@ -3196,7 +3076,6 @@ extern "C" { #define FRF_AZ_RX_DESCQ_EN_LBN 0 #define FRF_AZ_RX_DESCQ_EN_WIDTH 1 - /* * FR_AA_TX_DESC_PTR_TBL_KER(128bit): * Transmit descriptor pointer @@ -3258,7 +3137,6 @@ extern "C" { #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 - /* * FR_AA_EVQ_PTR_TBL_KER(128bit): * Event queue pointer table @@ -3297,7 +3175,6 @@ extern "C" { #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 - /* * FR_AA_BUF_HALF_TBL_KER(64bit): * Buffer table in half buffer table mode direct access by driver @@ -3325,7 +3202,6 @@ extern "C" { #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 - /* * FR_AA_BUF_FULL_TBL_KER(64bit): * Buffer table in full buffer table mode direct access by driver @@ -3364,7 +3240,6 @@ extern "C" { #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 - /* * FR_AZ_RX_FILTER_TBL0(128bit): * TCP/IPv4 Receive filter table @@ -3399,7 +3274,6 @@ extern "C" { #define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 #define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 - /* * FR_CZ_RX_MAC_FILTER_TBL0(128bit): * Receive Ethernet filter table @@ -3428,7 +3302,6 @@ extern "C" { #define FRF_CZ_RMFT_VLAN_ID_LBN 0 #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 - /* * FR_AZ_TIMER_TBL(128bit): * Timer table @@ -3466,7 +3339,6 @@ extern "C" { #define FRF_AB_TIMER_VAL_LBN 0 #define FRF_AB_TIMER_VAL_WIDTH 12 - /* * FR_BZ_TX_PACE_TBL(128bit): * Transmit pacing table @@ -3488,7 +3360,6 @@ extern "C" { #define FRF_AZ_TX_PACE_LBN 0 #define FRF_AZ_TX_PACE_WIDTH 5 - /* * FR_BZ_RX_INDIRECTION_TBL(7bit): * RX Indirection Table @@ -3501,7 +3372,6 @@ extern "C" { #define FRF_BZ_IT_QUEUE_LBN 0 #define FRF_BZ_IT_QUEUE_WIDTH 6 - /* * FR_CZ_TX_FILTER_TBL0(128bit): * TCP/IPv4 Transmit filter table @@ -3524,7 +3394,6 @@ extern "C" { #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 - /* * FR_CZ_TX_MAC_FILTER_TBL0(128bit): * Transmit Ethernet filter table @@ -3547,7 +3416,6 @@ extern "C" { #define FRF_CZ_TMFT_VLAN_ID_LBN 0 #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 - /* * FR_CZ_MC_TREG_SMEM(32bit): * MC Shared Memory @@ -3560,7 +3428,6 @@ extern "C" { #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 - /* * FR_BB_MSIX_VECTOR_TABLE(128bit): * MSIX Vector Table @@ -3589,7 +3456,6 @@ extern "C" { #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 - /* * FR_BB_MSIX_PBA_TABLE(32bit): * MSIX Pending Bit Array @@ -3610,7 +3476,6 @@ extern "C" { #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 - /* * FR_AZ_SRM_DBG_REG(64bit): * SRAM debug access @@ -3629,7 +3494,6 @@ extern "C" { #define FRF_AZ_SRM_DBG_DW1_LBN 32 #define FRF_AZ_SRM_DBG_DW1_WIDTH 32 - /* * FR_AA_INT_ACK_CHAR(32bit): * CHAR interrupt acknowledge register @@ -3640,7 +3504,6 @@ extern "C" { #define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 #define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 - /* FS_DRIVER_EV */ #define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 @@ -3658,7 +3521,6 @@ extern "C" { #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 - /* FS_EVENT_ENTRY */ #define FSF_AZ_EV_CODE_LBN 60 #define FSF_AZ_EV_CODE_WIDTH 4 @@ -3675,7 +3537,6 @@ extern "C" { #define FSF_AZ_EV_DATA_DW1_LBN 32 #define FSF_AZ_EV_DATA_DW1_WIDTH 28 - /* FS_GLOBAL_EV */ #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 @@ -3688,7 +3549,6 @@ extern "C" { #define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 #define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 - /* FS_RX_EV */ #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 @@ -3756,7 +3616,6 @@ extern "C" { #define FSF_AZ_RX_EV_DESC_PTR_LBN 0 #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 - /* FS_RX_KER_DESC */ #define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 @@ -3769,14 +3628,12 @@ extern "C" { #define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 - /* FS_RX_USER_DESC */ #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 #define FSF_AZ_RX_USER_BUF_ID_LBN 0 #define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 - /* FS_TX_EV */ #define FSF_AZ_TX_EV_PKT_ERR_LBN 38 #define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 @@ -3795,7 +3652,6 @@ extern "C" { #define FSF_AZ_TX_EV_DESC_PTR_LBN 0 #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 - /* FS_TX_KER_DESC */ #define FSF_AZ_TX_KER_CONT_LBN 62 #define FSF_AZ_TX_KER_CONT_WIDTH 1 @@ -3810,7 +3666,6 @@ extern "C" { #define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 - /* FS_TX_USER_DESC */ #define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 @@ -3823,14 +3678,12 @@ extern "C" { #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 - /* FS_USER_EV */ #define FSF_CZ_USER_QID_LBN 32 #define FSF_CZ_USER_QID_WIDTH 10 #define FSF_CZ_USER_EV_REG_VALUE_LBN 0 #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 - /* FS_NET_IVEC */ #define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 @@ -3843,7 +3696,6 @@ extern "C" { #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 - /* DRIVER_EV */ /* Sub-fields of an RX flush completion event */ #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 @@ -3851,8 +3703,6 @@ extern "C" { #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 - - /************************************************************************** * * Falcon non-volatile configuration @@ -3860,15 +3710,10 @@ extern "C" { ************************************************************************** */ - #define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST - #ifdef __cplusplus } #endif - - - #endif /* _SYS_EFX_REGS_H */ diff --git a/sys/dev/sfxge/common/efx_regs_ef10.h b/sys/dev/sfxge/common/efx_regs_ef10.h index 753d33de70af..3403e50b5b66 100644 --- a/sys/dev/sfxge/common/efx_regs_ef10.h +++ b/sys/dev/sfxge/common/efx_regs_ef10.h @@ -55,11 +55,9 @@ extern "C" { /* hunta0,medforda0,medford2a0=pf_dbell_bar */ #define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face - #define ERF_DZ_HW_REV_ID_LBN 0 #define ERF_DZ_HW_REV_ID_WIDTH 32 - /* * BIU_MC_SFT_STATUS_REG(32bit): * @@ -71,11 +69,9 @@ extern "C" { #define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 #define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face - #define ERF_DZ_MC_SFT_STATUS_LBN 0 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32 - /* * BIU_INT_ISR_REG(32bit): * @@ -85,11 +81,9 @@ extern "C" { /* hunta0,medforda0,medford2a0=pf_dbell_bar */ #define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 - #define ERF_DZ_ISR_REG_LBN 0 #define ERF_DZ_ISR_REG_WIDTH 32 - /* * MC_DB_LWRD_REG(32bit): * @@ -99,11 +93,9 @@ extern "C" { /* hunta0,medforda0,medford2a0=pf_dbell_bar */ #define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 - #define ERF_DZ_MC_DOORBELL_L_LBN 0 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32 - /* * MC_DB_HWRD_REG(32bit): * @@ -113,11 +105,9 @@ extern "C" { /* hunta0,medforda0,medford2a0=pf_dbell_bar */ #define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 - #define ERF_DZ_MC_DOORBELL_H_LBN 0 #define ERF_DZ_MC_DOORBELL_H_WIDTH 32 - /* * EVQ_RPTR_REG(32bit): * @@ -129,13 +119,11 @@ extern "C" { #define ER_DZ_EVQ_RPTR_REG_ROWS 2048 #define ER_DZ_EVQ_RPTR_REG_RESET 0x0 - #define ERF_DZ_EVQ_RPTR_VLD_LBN 15 #define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 #define ERF_DZ_EVQ_RPTR_LBN 0 #define ERF_DZ_EVQ_RPTR_WIDTH 15 - /* * EVQ_RPTR_REG_64K(32bit): * @@ -147,13 +135,11 @@ extern "C" { #define ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048 #define ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0 - #define ERF_FZ_EVQ_RPTR_VLD_LBN 15 #define ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 #define ERF_FZ_EVQ_RPTR_LBN 0 #define ERF_FZ_EVQ_RPTR_WIDTH 15 - /* * EVQ_RPTR_REG_16K(32bit): * @@ -165,13 +151,11 @@ extern "C" { #define ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048 #define ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0 - /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */ /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */ /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */ /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */ - /* * EVQ_TMR_REG_64K(32bit): * @@ -183,7 +167,6 @@ extern "C" { #define ER_FZ_EVQ_TMR_REG_64K_ROWS 2048 #define ER_FZ_EVQ_TMR_REG_64K_RESET 0x0 - #define ERF_FZ_TC_TMR_REL_VAL_LBN 16 #define ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 #define ERF_FZ_TC_TIMER_MODE_LBN 14 @@ -191,7 +174,6 @@ extern "C" { #define ERF_FZ_TC_TIMER_VAL_LBN 0 #define ERF_FZ_TC_TIMER_VAL_WIDTH 14 - /* * EVQ_TMR_REG_16K(32bit): * @@ -203,7 +185,6 @@ extern "C" { #define ER_FZ_EVQ_TMR_REG_16K_ROWS 2048 #define ER_FZ_EVQ_TMR_REG_16K_RESET 0x0 - /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */ @@ -211,7 +192,6 @@ extern "C" { /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */ /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */ - /* * EVQ_TMR_REG(32bit): * @@ -223,7 +203,6 @@ extern "C" { #define ER_DZ_EVQ_TMR_REG_ROWS 2048 #define ER_DZ_EVQ_TMR_REG_RESET 0x0 - /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */ /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */ #define ERF_DZ_TC_TIMER_MODE_LBN 14 @@ -231,7 +210,6 @@ extern "C" { #define ERF_DZ_TC_TIMER_VAL_LBN 0 #define ERF_DZ_TC_TIMER_VAL_WIDTH 14 - /* * RX_DESC_UPD_REG_16K(32bit): * @@ -243,11 +221,9 @@ extern "C" { #define ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048 #define ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0 - #define ERF_FZ_RX_DESC_WPTR_LBN 0 #define ERF_FZ_RX_DESC_WPTR_WIDTH 12 - /* * RX_DESC_UPD_REG(32bit): * @@ -259,11 +235,9 @@ extern "C" { #define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 #define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 - #define ERF_DZ_RX_DESC_WPTR_LBN 0 #define ERF_DZ_RX_DESC_WPTR_WIDTH 12 - /* * RX_DESC_UPD_REG_64K(32bit): * @@ -275,11 +249,9 @@ extern "C" { #define ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048 #define ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0 - /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */ /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */ - /* * TX_DESC_UPD_REG_64K(96bit): * @@ -291,7 +263,6 @@ extern "C" { #define ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048 #define ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0 - #define ERF_FZ_RSVD_LBN 76 #define ERF_FZ_RSVD_WIDTH 20 #define ERF_FZ_TX_DESC_WPTR_LBN 64 @@ -301,7 +272,6 @@ extern "C" { #define ERF_FZ_TX_DESC_LWORD_LBN 0 #define ERF_FZ_TX_DESC_LWORD_WIDTH 32 - /* * TX_DESC_UPD_REG_16K(96bit): * @@ -313,7 +283,6 @@ extern "C" { #define ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048 #define ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0 - /* defined as ERF_FZ_RSVD_LBN 76; */ /* defined as ERF_FZ_RSVD_WIDTH 20 */ /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */ @@ -323,7 +292,6 @@ extern "C" { /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */ /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */ - /* * TX_DESC_UPD_REG(96bit): * @@ -335,7 +303,6 @@ extern "C" { #define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 #define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 - #define ERF_DZ_RSVD_LBN 76 #define ERF_DZ_RSVD_WIDTH 20 #define ERF_DZ_TX_DESC_WPTR_LBN 64 @@ -345,7 +312,6 @@ extern "C" { #define ERF_DZ_TX_DESC_LWORD_LBN 0 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 - /* ES_DRIVER_EV */ #define ESF_DZ_DRV_CODE_LBN 60 #define ESF_DZ_DRV_CODE_WIDTH 4 @@ -365,7 +331,6 @@ extern "C" { #define ESF_DZ_DRV_TMR_ID_LBN 0 #define ESF_DZ_DRV_TMR_ID_WIDTH 14 - /* ES_EVENT_ENTRY */ #define ESF_DZ_EV_CODE_LBN 60 #define ESF_DZ_EV_CODE_WIDTH 4 @@ -381,7 +346,6 @@ extern "C" { #define ESF_DZ_EV_DATA_LBN 0 #define ESF_DZ_EV_DATA_WIDTH 60 - /* ES_MC_EVENT */ #define ESF_DZ_MC_CODE_LBN 60 #define ESF_DZ_MC_CODE_WIDTH 4 @@ -396,7 +360,6 @@ extern "C" { #define ESF_DZ_MC_SOFT_LBN 0 #define ESF_DZ_MC_SOFT_WIDTH 58 - /* ES_RX_EVENT */ #define ESF_DZ_RX_CODE_LBN 60 #define ESF_DZ_RX_CODE_WIDTH 4 @@ -501,7 +464,6 @@ extern "C" { #define ESF_DZ_RX_BYTES_LBN 0 #define ESF_DZ_RX_BYTES_WIDTH 14 - /* ES_RX_KER_DESC */ #define ESF_DZ_RX_KER_RESERVED_LBN 62 #define ESF_DZ_RX_KER_RESERVED_WIDTH 2 @@ -514,7 +476,6 @@ extern "C" { #define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 - /* ES_TX_CSUM_TSTAMP_DESC */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -544,7 +505,6 @@ extern "C" { #define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 #define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 - /* ES_TX_EVENT */ #define ESF_DZ_TX_CODE_LBN 60 #define ESF_DZ_TX_CODE_WIDTH 4 @@ -573,7 +533,6 @@ extern "C" { #define ESF_DZ_TX_DESCR_INDX_LBN 0 #define ESF_DZ_TX_DESCR_INDX_WIDTH 16 - /* ES_TX_KER_DESC */ #define ESF_DZ_TX_KER_TYPE_LBN 63 #define ESF_DZ_TX_KER_TYPE_WIDTH 1 @@ -588,7 +547,6 @@ extern "C" { #define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 #define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 - /* ES_TX_PIO_DESC */ #define ESF_DZ_TX_PIO_TYPE_LBN 63 #define ESF_DZ_TX_PIO_TYPE_WIDTH 1 @@ -601,7 +559,6 @@ extern "C" { #define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 #define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 - /* ES_TX_TSO_DESC */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -623,7 +580,6 @@ extern "C" { #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 - /* ES_TX_TSO_V2_DESC_A */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -643,7 +599,6 @@ extern "C" { #define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 - /* ES_TX_TSO_V2_DESC_B */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -663,7 +618,6 @@ extern "C" { #define ESF_DZ_TX_TSO_OUTER_IPID_LBN 0 #define ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16 - /* ES_TX_VLAN_DESC */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -679,7 +633,6 @@ extern "C" { #define ESF_DZ_TX_VLAN_TAG1_LBN 0 #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 - /************************************************************************* * NOTE: the comment line above marks the end of the autogenerated section */ diff --git a/sys/dev/sfxge/common/efx_regs_mcdi.h b/sys/dev/sfxge/common/efx_regs_mcdi.h index 8387fed682a8..8656edd82830 100644 --- a/sys/dev/sfxge/common/efx_regs_mcdi.h +++ b/sys/dev/sfxge/common/efx_regs_mcdi.h @@ -30,7 +30,6 @@ #ifndef _SIENA_MC_DRIVER_PCOL_H #define _SIENA_MC_DRIVER_PCOL_H - /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ /* Power-on reset state */ #define MC_FW_STATE_POR (1) @@ -151,7 +150,6 @@ #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1 #endif - /* The MC can generate events for two reasons: * - To advance a shared memory request if XFLAGS_EVREQ was set * - As a notification (link state, i2c event), controlled @@ -194,7 +192,6 @@ */ #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc - /* Operation not permitted. */ #define MC_CMD_ERR_EPERM 1 /* Non-existent command target */ @@ -388,7 +385,6 @@ */ #define EVB_STACK_ID(n) (((n) & 0xff) << 16) - #ifdef WITH_MCDI_V2 /* Version 2 adds an optional argument to error returns: the errno value @@ -1043,7 +1039,6 @@ #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4 - /***********************************/ /* MC_CMD_READ32 * Read multiple 32byte words from MC memory. Note - this command really @@ -1071,7 +1066,6 @@ #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 - /***********************************/ /* MC_CMD_WRITE32 * Write multiple 32byte words to MC memory. @@ -1095,7 +1089,6 @@ /* MC_CMD_WRITE32_OUT msgresponse */ #define MC_CMD_WRITE32_OUT_LEN 0 - /***********************************/ /* MC_CMD_COPYCODE * Copy MC code between two locations and jump. Note - this command really @@ -1154,7 +1147,6 @@ /* MC_CMD_COPYCODE_OUT msgresponse */ #define MC_CMD_COPYCODE_OUT_LEN 0 - /***********************************/ /* MC_CMD_SET_FUNC * Select function for function-specific commands. @@ -1173,7 +1165,6 @@ /* MC_CMD_SET_FUNC_OUT msgresponse */ #define MC_CMD_SET_FUNC_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_BOOT_STATUS * Get the instruction address from which the MC booted. @@ -1202,7 +1193,6 @@ #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 - /***********************************/ /* MC_CMD_GET_ASSERTS * Get (and optionally clear) the current assertion status. Only @@ -1252,7 +1242,6 @@ #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4 - /***********************************/ /* MC_CMD_LOG_CTRL * Configure the output stream for log events such as link state changes, @@ -1279,7 +1268,6 @@ /* MC_CMD_LOG_CTRL_OUT msgresponse */ #define MC_CMD_LOG_CTRL_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_VERSION * Get version information about the MC firmware. @@ -1346,7 +1334,6 @@ #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 - /***********************************/ /* MC_CMD_PTP * Perform PTP operation @@ -2181,7 +2168,6 @@ /* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */ #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0 - /***********************************/ /* MC_CMD_CSR_READ32 * Read 32bit words from the indirect memory map. @@ -2211,7 +2197,6 @@ #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 - /***********************************/ /* MC_CMD_CSR_WRITE32 * Write 32bit dwords to the indirect memory map. @@ -2240,7 +2225,6 @@ #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4 - /***********************************/ /* MC_CMD_HP * These commands are used for HP related features. They are grouped under one @@ -2288,7 +2272,6 @@ /* enum: OCSD was already started for this card. */ #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 - /***********************************/ /* MC_CMD_STACKINFO * Get stack information. @@ -2311,7 +2294,6 @@ #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 - /***********************************/ /* MC_CMD_MDIO_READ * MDIO register read. @@ -2359,7 +2341,6 @@ /* enum: Good. */ #define MC_CMD_MDIO_STATUS_GOOD 0x8 - /***********************************/ /* MC_CMD_MDIO_WRITE * MDIO register write. @@ -2407,7 +2388,6 @@ /* enum: Good. */ /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ - /***********************************/ /* MC_CMD_DBI_WRITE * Write DBI register(s). @@ -2453,7 +2433,6 @@ #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 - /***********************************/ /* MC_CMD_PORT_READ32 * Read a 32-bit register from the indirect port register map. The port to @@ -2476,7 +2455,6 @@ #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4 - /***********************************/ /* MC_CMD_PORT_WRITE32 * Write a 32-bit register to the indirect port register map. The port to @@ -2499,7 +2477,6 @@ #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4 - /***********************************/ /* MC_CMD_PORT_READ128 * Read a 128-bit register from the indirect port register map. The port to @@ -2522,7 +2499,6 @@ #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4 - /***********************************/ /* MC_CMD_PORT_WRITE128 * Write a 128-bit register to the indirect port register map. The port to @@ -2571,7 +2547,6 @@ #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 - /***********************************/ /* MC_CMD_GET_BOARD_CFG * Returns the MC firmware configuration structure. @@ -2643,7 +2618,6 @@ #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 - /***********************************/ /* MC_CMD_DBI_READX * Read DBI register(s) -- extended functionality @@ -2692,7 +2666,6 @@ #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 - /***********************************/ /* MC_CMD_SET_RAND_SEED * Set the 16byte seed for the MC pseudo-random generator. @@ -2711,7 +2684,6 @@ /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 - /***********************************/ /* MC_CMD_LTSSM_HIST * Retrieve the history of the LTSSM, if the build supports it. @@ -2731,7 +2703,6 @@ #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 - /***********************************/ /* MC_CMD_DRV_ATTACH * Inform MCPU that this port is managed on the host (i.e. driver active). For @@ -2832,7 +2803,6 @@ */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4 - /***********************************/ /* MC_CMD_SHMUART * Route UART output to circular buffer in shared memory instead. @@ -2848,7 +2818,6 @@ /* MC_CMD_SHMUART_OUT msgresponse */ #define MC_CMD_SHMUART_OUT_LEN 0 - /***********************************/ /* MC_CMD_PORT_RESET * Generic per-port reset. There is no equivalent for per-board reset. Locks @@ -2866,7 +2835,6 @@ /* MC_CMD_PORT_RESET_OUT msgresponse */ #define MC_CMD_PORT_RESET_OUT_LEN 0 - /***********************************/ /* MC_CMD_ENTITY_RESET * Generic per-resource reset. There is no equivalent for per-board reset. @@ -2889,7 +2857,6 @@ /* MC_CMD_ENTITY_RESET_OUT msgresponse */ #define MC_CMD_ENTITY_RESET_OUT_LEN 0 - /***********************************/ /* MC_CMD_PCIE_CREDITS * Read instantaneous and minimum flow control thresholds. @@ -2924,7 +2891,6 @@ #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 - /***********************************/ /* MC_CMD_RXD_MONITOR * Get histogram of RX queue fill level. @@ -2983,7 +2949,6 @@ #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4 - /***********************************/ /* MC_CMD_PUTS * Copy the given ASCII string out onto UART and/or out of the network port. @@ -3013,7 +2978,6 @@ /* MC_CMD_PUTS_OUT msgresponse */ #define MC_CMD_PUTS_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_PHY_CFG * Report PHY configuration. This guarantees to succeed even if the PHY is in a @@ -3141,7 +3105,6 @@ #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 - /***********************************/ /* MC_CMD_START_BIST * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST @@ -3177,7 +3140,6 @@ /* MC_CMD_START_BIST_OUT msgresponse */ #define MC_CMD_START_BIST_OUT_LEN 0 - /***********************************/ /* MC_CMD_POLL_BIST * Poll for BIST completion. Returns a single status code, and optionally some @@ -3346,7 +3308,6 @@ #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4 - /***********************************/ /* MC_CMD_FLUSH_RX_QUEUES * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ @@ -3370,7 +3331,6 @@ /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_LOOPBACK_MODES * Returns a bitmask of loopback modes available at each speed. @@ -3665,7 +3625,6 @@ #define FEC_TYPE_TYPE_LBN 0 #define FEC_TYPE_TYPE_WIDTH 32 - /***********************************/ /* MC_CMD_GET_LINK * Read the unified MAC/PHY link state. Locks required: None Return code: 0, @@ -3822,7 +3781,6 @@ #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_LBN 8 #define MC_CMD_GET_LINK_OUT_V2_AN_DONE_WIDTH 1 - /***********************************/ /* MC_CMD_SET_LINK * Write the unified MAC/PHY link configuration. Locks required: None. Return @@ -3863,7 +3821,6 @@ /* MC_CMD_SET_LINK_OUT msgresponse */ #define MC_CMD_SET_LINK_OUT_LEN 0 - /***********************************/ /* MC_CMD_SET_ID_LED * Set identification LED state. Locks required: None. Return code: 0, EINVAL @@ -3885,7 +3842,6 @@ /* MC_CMD_SET_ID_LED_OUT msgresponse */ #define MC_CMD_SET_ID_LED_OUT_LEN 0 - /***********************************/ /* MC_CMD_SET_MAC * Set MAC configuration. Locks required: None. Return code: 0, EINVAL @@ -4000,7 +3956,6 @@ #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4 - /***********************************/ /* MC_CMD_PHY_STATS * Get generic PHY statistics. This call returns the statistics for a generic @@ -4080,7 +4035,6 @@ /* enum: (Last entry) */ #define MC_CMD_PHY_NSTATS 0x17 - /***********************************/ /* MC_CMD_MAC_STATS * Get generic MAC statistics. This call returns unified statistics maintained @@ -4425,7 +4379,6 @@ /* Other enum values, see field(s): */ /* MC_CMD_MAC_STATS_V3_OUT_NO_DMA/STATISTICS */ - /***********************************/ /* MC_CMD_SRIOV * to be documented @@ -4481,7 +4434,6 @@ #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 - /***********************************/ /* MC_CMD_MEMCPY * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data @@ -4517,7 +4469,6 @@ /* MC_CMD_MEMCPY_OUT msgresponse */ #define MC_CMD_MEMCPY_OUT_LEN 0 - /***********************************/ /* MC_CMD_WOL_FILTER_SET * Set a WoL filter. @@ -4630,7 +4581,6 @@ #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4 - /***********************************/ /* MC_CMD_WOL_FILTER_REMOVE * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS @@ -4648,7 +4598,6 @@ /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 - /***********************************/ /* MC_CMD_WOL_FILTER_RESET * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, @@ -4669,7 +4618,6 @@ /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 - /***********************************/ /* MC_CMD_SET_MCAST_HASH * Set the MCAST hash value without otherwise reconfiguring the MAC @@ -4686,7 +4634,6 @@ /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 - /***********************************/ /* MC_CMD_NVRAM_TYPES * Return bitfield indicating available types of virtual NVRAM partitions. @@ -4748,7 +4695,6 @@ /* enum: Additional flash on FPGA. */ #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14 - /***********************************/ /* MC_CMD_NVRAM_INFO * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, @@ -4826,7 +4772,6 @@ #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4 - /***********************************/ /* MC_CMD_NVRAM_UPDATE_START * Start a group of update operations on a virtual NVRAM partition. Locks @@ -4869,7 +4814,6 @@ /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 - /***********************************/ /* MC_CMD_NVRAM_READ * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if @@ -4937,7 +4881,6 @@ #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 - /***********************************/ /* MC_CMD_NVRAM_WRITE * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if @@ -4969,7 +4912,6 @@ /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 - /***********************************/ /* MC_CMD_NVRAM_ERASE * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if @@ -4995,7 +4937,6 @@ /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 - /***********************************/ /* MC_CMD_NVRAM_UPDATE_FINISH * Finish a group of update operations on a virtual NVRAM partition. Locks @@ -5100,7 +5041,6 @@ /* enum: The image has a lower security level than the current firmware. */ #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd - /***********************************/ /* MC_CMD_REBOOT * Reboot the MC. @@ -5133,7 +5073,6 @@ /* MC_CMD_REBOOT_OUT msgresponse */ #define MC_CMD_REBOOT_OUT_LEN 0 - /***********************************/ /* MC_CMD_SCHEDINFO * Request scheduler info. Locks required: NONE. Returns: An array of @@ -5157,7 +5096,6 @@ #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 - /***********************************/ /* MC_CMD_REBOOT_MODE * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot @@ -5188,7 +5126,6 @@ #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4 - /***********************************/ /* MC_CMD_SENSOR_INFO * Returns information about every available sensor. @@ -5466,7 +5403,6 @@ #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 - /***********************************/ /* MC_CMD_READ_SENSORS * Returns the current reading from each sensor. DMAs an array of sensor @@ -5543,7 +5479,6 @@ #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 - /***********************************/ /* MC_CMD_GET_PHY_STATE * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot @@ -5567,7 +5502,6 @@ /* enum: Faulty. */ #define MC_CMD_PHY_STATE_ZOMBIE 0x2 - /***********************************/ /* MC_CMD_SETUP_8021QBB * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to @@ -5583,7 +5517,6 @@ /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 - /***********************************/ /* MC_CMD_WOL_FILTER_GET * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS @@ -5601,7 +5534,6 @@ #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4 - /***********************************/ /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD * Add a protocol offload to NIC for lights-out state. Locks required: None. @@ -5650,7 +5582,6 @@ #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4 - /***********************************/ /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD * Remove a protocol offload from NIC for lights-out state. Locks required: @@ -5671,7 +5602,6 @@ /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 - /***********************************/ /* MC_CMD_MAC_RESET_RESTORE * Restore MAC after block reset. Locks required: None. Returns: 0. @@ -5684,7 +5614,6 @@ /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 - /***********************************/ /* MC_CMD_TESTASSERT * Deliberately trigger an assert-detonation in the firmware for testing @@ -5725,7 +5654,6 @@ /* MC_CMD_TESTASSERT_V2_OUT msgresponse */ #define MC_CMD_TESTASSERT_V2_OUT_LEN 0 - /***********************************/ /* MC_CMD_WORKAROUND * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't @@ -5786,7 +5714,6 @@ #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_WIDTH 1 - /***********************************/ /* MC_CMD_GET_PHY_MEDIA_INFO * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for @@ -5818,7 +5745,6 @@ #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248 - /***********************************/ /* MC_CMD_NVRAM_TEST * Test a particular NVRAM partition for valid contents (where "valid" depends @@ -5847,7 +5773,6 @@ /* enum: Not supported. */ #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 - /***********************************/ /* MC_CMD_MRSFP_TWEAK * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds. @@ -5890,7 +5815,6 @@ /* enum: In. */ #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 - /***********************************/ /* MC_CMD_SENSOR_SET_LIMS * Adjusts the sensor limits. This is a warranty-voiding operation. Returns: @@ -5924,7 +5848,6 @@ /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */ #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_RESOURCE_LIMITS */ @@ -5944,7 +5867,6 @@ #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4 - /***********************************/ /* MC_CMD_NVRAM_PARTITIONS * Reads the list of available virtual NVRAM partition types. Locks required: @@ -5971,7 +5893,6 @@ #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62 - /***********************************/ /* MC_CMD_NVRAM_METADATA * Reads soft metadata for a virtual NVRAM partition type. Locks required: @@ -6024,7 +5945,6 @@ #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232 - /***********************************/ /* MC_CMD_GET_MAC_ADDRESSES * Returns the base MAC, count and stride for the requesting function @@ -6052,7 +5972,6 @@ #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4 - /***********************************/ /* MC_CMD_CLP * Perform a CLP related operation @@ -6142,7 +6061,6 @@ #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_OFST 1 #define MC_CMD_CLP_OUT_GET_BOOT_RESERVED_LEN 3 - /***********************************/ /* MC_CMD_MUM * Perform a MUM operation @@ -7173,7 +7091,6 @@ #define MESSAGE_TYPE_MESSAGE_TYPE_LBN 0 #define MESSAGE_TYPE_MESSAGE_TYPE_WIDTH 32 - /***********************************/ /* MC_CMD_READ_REGS * Get a dump of the MCPU registers @@ -7198,7 +7115,6 @@ #define MC_CMD_READ_REGS_OUT_REGS_LEN 4 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73 - /***********************************/ /* MC_CMD_INIT_EVQ * Set up an event queue according to the supplied parameters. The IN arguments @@ -7426,7 +7342,6 @@ #define QUEUE_CRC_MODE_SPARE_LBN 4 #define QUEUE_CRC_MODE_SPARE_WIDTH 4 - /***********************************/ /* MC_CMD_INIT_RXQ * set up a receive queue according to the supplied parameters. The IN @@ -7694,7 +7609,6 @@ /* MC_CMD_INIT_RXQ_V3_OUT msgresponse */ #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0 - /***********************************/ /* MC_CMD_INIT_TXQ */ @@ -7831,7 +7745,6 @@ /* MC_CMD_INIT_TXQ_OUT msgresponse */ #define MC_CMD_INIT_TXQ_OUT_LEN 0 - /***********************************/ /* MC_CMD_FINI_EVQ * Teardown an EVQ. @@ -7855,7 +7768,6 @@ /* MC_CMD_FINI_EVQ_OUT msgresponse */ #define MC_CMD_FINI_EVQ_OUT_LEN 0 - /***********************************/ /* MC_CMD_FINI_RXQ * Teardown a RXQ. @@ -7874,7 +7786,6 @@ /* MC_CMD_FINI_RXQ_OUT msgresponse */ #define MC_CMD_FINI_RXQ_OUT_LEN 0 - /***********************************/ /* MC_CMD_FINI_TXQ * Teardown a TXQ. @@ -7893,7 +7804,6 @@ /* MC_CMD_FINI_TXQ_OUT msgresponse */ #define MC_CMD_FINI_TXQ_OUT_LEN 0 - /***********************************/ /* MC_CMD_DRIVER_EVENT * Generate an event on an EVQ belonging to the function issuing the command. @@ -7917,7 +7827,6 @@ /* MC_CMD_DRIVER_EVENT_OUT msgresponse */ #define MC_CMD_DRIVER_EVENT_OUT_LEN 0 - /***********************************/ /* MC_CMD_PROXY_CMD * Execute an arbitrary MCDI command on behalf of a different function, subject @@ -7985,7 +7894,6 @@ #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LBN 96 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_WIDTH 32 - /***********************************/ /* MC_CMD_PROXY_CONFIGURE * Enable/disable authorization of MCDI requests from unprivileged functions by @@ -8089,7 +7997,6 @@ /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 - /***********************************/ /* MC_CMD_PROXY_COMPLETE * Tells FW that a requested proxy operation has either been completed (by @@ -8128,7 +8035,6 @@ /* MC_CMD_PROXY_COMPLETE_OUT msgresponse */ #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0 - /***********************************/ /* MC_CMD_ALLOC_BUFTBL_CHUNK * Allocate a set of buffer table entries using the specified owner ID. This @@ -8161,7 +8067,6 @@ #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4 - /***********************************/ /* MC_CMD_PROGRAM_BUFTBL_ENTRIES * Reprogram a set of buffer table entries in the specified chunk. @@ -8194,7 +8099,6 @@ /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */ #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0 - /***********************************/ /* MC_CMD_FREE_BUFTBL_CHUNK */ @@ -8211,7 +8115,6 @@ /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */ #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0 - /***********************************/ /* MC_CMD_FILTER_OP * Multiplexed MCDI call for filter operations @@ -8918,7 +8821,6 @@ /* Enum values, see field(s): */ /* MC_CMD_FILTER_OP_OUT/HANDLE */ - /***********************************/ /* MC_CMD_GET_PARSER_DISP_INFO * Get information related to the parser-dispatcher subsystem @@ -9024,7 +8926,6 @@ #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_OFST 32 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4 - /***********************************/ /* MC_CMD_PARSER_DISP_RW * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. @@ -9119,7 +9020,6 @@ #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ - /***********************************/ /* MC_CMD_GET_PF_COUNT * Get number of PFs on the device. @@ -9138,7 +9038,6 @@ #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1 - /***********************************/ /* MC_CMD_SET_PF_COUNT * Set number of PFs on the device. @@ -9154,7 +9053,6 @@ /* MC_CMD_SET_PF_COUNT_OUT msgresponse */ #define MC_CMD_SET_PF_COUNT_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_PORT_ASSIGNMENT * Get port assignment for current PCI function. @@ -9173,7 +9071,6 @@ #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4 - /***********************************/ /* MC_CMD_SET_PORT_ASSIGNMENT * Set port assignment for current PCI function. @@ -9192,7 +9089,6 @@ /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */ #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0 - /***********************************/ /* MC_CMD_ALLOC_VIS * Allocate VIs for current PCI function. @@ -9238,7 +9134,6 @@ #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_OFST 8 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4 - /***********************************/ /* MC_CMD_FREE_VIS * Free VIs for current PCI function. Any linked PIO buffers will be unlinked, @@ -9255,7 +9150,6 @@ /* MC_CMD_FREE_VIS_OUT msgresponse */ #define MC_CMD_FREE_VIS_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_SRIOV_CFG * Get SRIOV config for this PF. @@ -9287,7 +9181,6 @@ #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4 - /***********************************/ /* MC_CMD_SET_SRIOV_CFG * Set SRIOV config for this PF. @@ -9323,7 +9216,6 @@ /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */ #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_VI_ALLOC_INFO * Get information about number of VI's and base VI number allocated to this @@ -9351,7 +9243,6 @@ #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_OFST 8 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4 - /***********************************/ /* MC_CMD_DUMP_VI_STATE * For CmdClient use. Dump pertinent information on a specific absolute VI. @@ -9465,7 +9356,6 @@ #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8 - /***********************************/ /* MC_CMD_ALLOC_PIOBUF * Allocate a push I/O buffer for later use with a tx queue. @@ -9484,7 +9374,6 @@ #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4 - /***********************************/ /* MC_CMD_FREE_PIOBUF * Free a push I/O buffer. @@ -9503,7 +9392,6 @@ /* MC_CMD_FREE_PIOBUF_OUT msgresponse */ #define MC_CMD_FREE_PIOBUF_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_VI_TLP_PROCESSING * Get TLP steering and ordering information for a VI. @@ -9542,7 +9430,6 @@ #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4 - /***********************************/ /* MC_CMD_SET_VI_TLP_PROCESSING * Set TLP steering and ordering information for a VI. @@ -9581,7 +9468,6 @@ /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */ #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_TLP_PROCESSING_GLOBALS * Get global PCIe steering and transaction processing configuration. @@ -9648,7 +9534,6 @@ #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23 - /***********************************/ /* MC_CMD_SET_TLP_PROCESSING_GLOBALS * Set global PCIe steering and transaction processing configuration. @@ -9699,7 +9584,6 @@ /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */ #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0 - /***********************************/ /* MC_CMD_SATELLITE_DOWNLOAD * Download a new set of images to the satellite CPUs from the host. @@ -9820,7 +9704,6 @@ /* enum: Checksum was incorrect */ #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300 - /***********************************/ /* MC_CMD_GET_CAPABILITIES * Get device capabilities. @@ -11438,7 +11321,6 @@ #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_OFST 80 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4 - /***********************************/ /* MC_CMD_V2_EXTN * Encapsulation for a v2 extended command @@ -11469,7 +11351,6 @@ */ #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1 - /***********************************/ /* MC_CMD_TCM_BUCKET_ALLOC * Allocate a pacer bucket (for qau rp or a snapper test) @@ -11488,7 +11369,6 @@ #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4 - /***********************************/ /* MC_CMD_TCM_BUCKET_FREE * Free a pacer bucket @@ -11507,7 +11387,6 @@ /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_TCM_BUCKET_INIT * Initialise pacer bucket with a given rate @@ -11541,7 +11420,6 @@ /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */ #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0 - /***********************************/ /* MC_CMD_TCM_TXQ_INIT * Initialise txq in pacer with given options or set options @@ -11625,7 +11503,6 @@ /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */ #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0 - /***********************************/ /* MC_CMD_LINK_PIOBUF * Link a push I/O buffer to a TxQ @@ -11647,7 +11524,6 @@ /* MC_CMD_LINK_PIOBUF_OUT msgresponse */ #define MC_CMD_LINK_PIOBUF_OUT_LEN 0 - /***********************************/ /* MC_CMD_UNLINK_PIOBUF * Unlink a push I/O buffer from a TxQ @@ -11666,7 +11542,6 @@ /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */ #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0 - /***********************************/ /* MC_CMD_VSWITCH_ALLOC * allocate and initialise a v-switch. @@ -11712,7 +11587,6 @@ /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */ #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0 - /***********************************/ /* MC_CMD_VSWITCH_FREE * de-allocate a v-switch. @@ -11731,7 +11605,6 @@ /* MC_CMD_VSWITCH_FREE_OUT msgresponse */ #define MC_CMD_VSWITCH_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_VSWITCH_QUERY * read some config of v-switch. For now this command is an empty placeholder. @@ -11752,7 +11625,6 @@ /* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 - /***********************************/ /* MC_CMD_VPORT_ALLOC * allocate a v-port. @@ -11815,7 +11687,6 @@ #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4 - /***********************************/ /* MC_CMD_VPORT_FREE * de-allocate a v-port. @@ -11834,7 +11705,6 @@ /* MC_CMD_VPORT_FREE_OUT msgresponse */ #define MC_CMD_VPORT_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_VADAPTOR_ALLOC * allocate a v-adaptor. @@ -11878,7 +11748,6 @@ /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */ #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0 - /***********************************/ /* MC_CMD_VADAPTOR_FREE * de-allocate a v-adaptor. @@ -11897,7 +11766,6 @@ /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */ #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_VADAPTOR_SET_MAC * assign a new MAC address to a v-adaptor. @@ -11919,7 +11787,6 @@ /* MC_CMD_VADAPTOR_SET_MAC_OUT msgresponse */ #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0 - /***********************************/ /* MC_CMD_VADAPTOR_GET_MAC * read the MAC address assigned to a v-adaptor. @@ -11941,7 +11808,6 @@ #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_LEN 6 - /***********************************/ /* MC_CMD_VADAPTOR_QUERY * read some config of v-adaptor. @@ -11969,7 +11835,6 @@ #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 - /***********************************/ /* MC_CMD_EVB_PORT_ASSIGN * assign a port to a PCI function. @@ -11995,7 +11860,6 @@ /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */ #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0 - /***********************************/ /* MC_CMD_RDWR_A64_REGIONS * Assign the 64 bit region addresses. @@ -12034,7 +11898,6 @@ #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4 - /***********************************/ /* MC_CMD_ONLOAD_STACK_ALLOC * Allocate an Onload stack ID. @@ -12056,7 +11919,6 @@ #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4 - /***********************************/ /* MC_CMD_ONLOAD_STACK_FREE * Free an Onload stack ID. @@ -12075,7 +11937,6 @@ /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */ #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_RSS_CONTEXT_ALLOC * Allocate an RSS context. @@ -12119,7 +11980,6 @@ /* enum: guaranteed invalid RSS context handle value */ #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff - /***********************************/ /* MC_CMD_RSS_CONTEXT_FREE * Free an RSS context. @@ -12138,7 +11998,6 @@ /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_RSS_CONTEXT_SET_KEY * Set the Toeplitz hash key for an RSS context. @@ -12160,7 +12019,6 @@ /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0 - /***********************************/ /* MC_CMD_RSS_CONTEXT_GET_KEY * Get the Toeplitz hash key for an RSS context. @@ -12182,7 +12040,6 @@ #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40 - /***********************************/ /* MC_CMD_RSS_CONTEXT_SET_TABLE * Set the indirection table for an RSS context. @@ -12204,7 +12061,6 @@ /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0 - /***********************************/ /* MC_CMD_RSS_CONTEXT_GET_TABLE * Get the indirection table for an RSS context. @@ -12226,7 +12082,6 @@ #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128 - /***********************************/ /* MC_CMD_RSS_CONTEXT_SET_FLAGS * Set various control flags for an RSS context. @@ -12281,7 +12136,6 @@ /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0 - /***********************************/ /* MC_CMD_RSS_CONTEXT_GET_FLAGS * Get various control flags for an RSS context. @@ -12337,7 +12191,6 @@ #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN 28 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4 - /***********************************/ /* MC_CMD_DOT1P_MAPPING_ALLOC * Allocate a .1p mapping. @@ -12370,7 +12223,6 @@ /* enum: guaranteed invalid .1p mapping handle value */ #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff - /***********************************/ /* MC_CMD_DOT1P_MAPPING_FREE * Free a .1p mapping. @@ -12389,7 +12241,6 @@ /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */ #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_DOT1P_MAPPING_SET_TABLE * Set the mapping table for a .1p mapping. @@ -12413,7 +12264,6 @@ /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */ #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0 - /***********************************/ /* MC_CMD_DOT1P_MAPPING_GET_TABLE * Get the mapping table for a .1p mapping. @@ -12437,7 +12287,6 @@ #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32 - /***********************************/ /* MC_CMD_GET_VECTOR_CFG * Get Interrupt Vector config for this PF. @@ -12462,7 +12311,6 @@ #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4 - /***********************************/ /* MC_CMD_SET_VECTOR_CFG * Set Interrupt Vector config for this PF. @@ -12489,7 +12337,6 @@ /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */ #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0 - /***********************************/ /* MC_CMD_VPORT_ADD_MAC_ADDRESS * Add a MAC address to a v-port @@ -12511,7 +12358,6 @@ /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */ #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0 - /***********************************/ /* MC_CMD_VPORT_DEL_MAC_ADDRESS * Delete a MAC address from a v-port @@ -12533,7 +12379,6 @@ /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */ #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0 - /***********************************/ /* MC_CMD_VPORT_GET_MAC_ADDRESSES * Delete a MAC address from a v-port @@ -12562,7 +12407,6 @@ #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41 - /***********************************/ /* MC_CMD_VPORT_RECONFIGURE * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port @@ -12614,7 +12458,6 @@ #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 - /***********************************/ /* MC_CMD_EVB_PORT_QUERY * read some config of v-port. @@ -12641,7 +12484,6 @@ #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4 - /***********************************/ /* MC_CMD_DUMP_BUFTBL_ENTRIES * Dump buffer table entries, mainly for command client debug use. Dumps @@ -12673,7 +12515,6 @@ #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21 - /***********************************/ /* MC_CMD_SET_RXDP_CONFIG * Set global RXDP configuration settings @@ -12701,7 +12542,6 @@ /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_RXDP_CONFIG * Get global RXDP configuration settings @@ -12725,7 +12565,6 @@ /* Enum values, see field(s): */ /* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ - /***********************************/ /* MC_CMD_GET_CLOCK * Return the system and PDCPU clock frequencies. @@ -12747,7 +12586,6 @@ #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4 - /***********************************/ /* MC_CMD_SET_CLOCK * Control the system and DPCPU clock frequencies. Changes are lost reboot. @@ -12833,7 +12671,6 @@ /* enum: The vswitch clock domain doesn't exist / isn't controlled */ #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0 - /***********************************/ /* MC_CMD_DPCPU_RPC * Send an arbitrary DPCPU message. @@ -12938,7 +12775,6 @@ #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4 - /***********************************/ /* MC_CMD_TRIGGER_INTERRUPT * Trigger an interrupt by prodding the BIU. @@ -12957,7 +12793,6 @@ /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */ #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0 - /***********************************/ /* MC_CMD_SHMBOOT_OP * Special operations to support (for now) shmboot. @@ -12978,7 +12813,6 @@ /* MC_CMD_SHMBOOT_OP_OUT msgresponse */ #define MC_CMD_SHMBOOT_OP_OUT_LEN 0 - /***********************************/ /* MC_CMD_CAP_BLK_READ * Read multiple 64bit words from capture block memory @@ -13008,7 +12842,6 @@ #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MINNUM 1 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_MAXNUM 31 - /***********************************/ /* MC_CMD_DUMP_DO * Take a dump of the DUT state @@ -13088,7 +12921,6 @@ #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4 - /***********************************/ /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED * Configure unsolicited dumps @@ -13155,7 +12987,6 @@ #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4 - /***********************************/ /* MC_CMD_SET_PSU * Adjusts power supply parameters. This is a warranty-voiding operation. @@ -13183,7 +13014,6 @@ /* MC_CMD_SET_PSU_OUT msgresponse */ #define MC_CMD_SET_PSU_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_FUNCTION_INFO * Get function information. PF and VF number. @@ -13203,7 +13033,6 @@ #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4 - /***********************************/ /* MC_CMD_ENABLE_OFFLINE_BIST * Enters offline BIST mode. All queues are torn down, chip enters quiescent @@ -13221,7 +13050,6 @@ /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */ #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0 - /***********************************/ /* MC_CMD_UART_SEND_DATA * Send checksummed[sic] block of data over the uart. Response is a placeholder @@ -13257,7 +13085,6 @@ /* MC_CMD_UART_SEND_DATA_IN msgresponse */ #define MC_CMD_UART_SEND_DATA_IN_LEN 0 - /***********************************/ /* MC_CMD_UART_RECV_DATA * Request checksummed[sic] block of data over the uart. Only a placeholder, @@ -13304,7 +13131,6 @@ #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0 #define MC_CMD_UART_RECV_DATA_IN_DATA_MAXNUM 236 - /***********************************/ /* MC_CMD_READ_FUSES * Read data programmed into the device One-Time-Programmable (OTP) Fuses @@ -13336,7 +13162,6 @@ #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248 - /***********************************/ /* MC_CMD_KR_TUNE * Get or set KR Serdes RXEQ and TX Driver settings @@ -13798,7 +13623,6 @@ #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_OFST 20 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4 - /***********************************/ /* MC_CMD_PCIE_TUNE * Get or set PCIE Serdes RXEQ and TX Driver settings @@ -14024,7 +13848,6 @@ /* MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT msgrequest */ #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0 - /***********************************/ /* MC_CMD_LICENSING * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition @@ -14080,7 +13903,6 @@ /* enum: licensing subsystem self-test passed */ #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1 - /***********************************/ /* MC_CMD_LICENSING_V3 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition @@ -14150,7 +13972,6 @@ #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 #define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 - /***********************************/ /* MC_CMD_LICENSING_GET_ID_V3 * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license @@ -14180,7 +14001,6 @@ #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 - /***********************************/ /* MC_CMD_MC2MC_PROXY * Execute an arbitrary MCDI command on the slave MC of a dual-core device. @@ -14197,7 +14017,6 @@ /* MC_CMD_MC2MC_PROXY_OUT msgresponse */ #define MC_CMD_MC2MC_PROXY_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_LICENSED_APP_STATE * Query the state of an individual licensed application. (Note that the actual @@ -14225,7 +14044,6 @@ /* enum: a valid license is present for the application */ #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1 - /***********************************/ /* MC_CMD_GET_LICENSED_V3_APP_STATE * Query the state of an individual licensed application. (Note that the actual @@ -14257,7 +14075,6 @@ /* enum: a valid license is present for the application */ #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 - /***********************************/ /* MC_CMD_GET_LICENSED_V3_FEATURE_STATES * Query the state of an one or more licensed features. (Note that the actual @@ -14287,7 +14104,6 @@ #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 - /***********************************/ /* MC_CMD_LICENSED_APP_OP * Perform an action for an individual licensed application - not used for V3 @@ -14364,7 +14180,6 @@ /* MC_CMD_LICENSED_APP_OP_MASK_OUT msgresponse */ #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0 - /***********************************/ /* MC_CMD_LICENSED_V3_VALIDATE_APP * Perform validation for an individual licensed application - V3 licensing @@ -14418,7 +14233,6 @@ #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_OFST 110 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_VADAPTOR_MACADDR_LEN 6 - /***********************************/ /* MC_CMD_LICENSED_V3_MASK_FEATURES * Mask features - V3 licensing (Medford) @@ -14446,7 +14260,6 @@ /* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 - /***********************************/ /* MC_CMD_LICENSING_V3_TEMPORARY * Perform operations to support installation of a single temporary license in @@ -14516,7 +14329,6 @@ #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_OFST 8 - /***********************************/ /* MC_CMD_SET_PORT_SNIFF_CONFIG * Configure RX port sniffing for the physical port associated with the calling @@ -14559,7 +14371,6 @@ /* MC_CMD_SET_PORT_SNIFF_CONFIG_OUT msgresponse */ #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_PORT_SNIFF_CONFIG * Obtain the current RX port sniffing configuration for the physical port @@ -14597,7 +14408,6 @@ #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 - /***********************************/ /* MC_CMD_SET_PARSER_DISP_CONFIG * Change configuration related to the parser-dispatcher subsystem. @@ -14639,7 +14449,6 @@ /* MC_CMD_SET_PARSER_DISP_CONFIG_OUT msgresponse */ #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_PARSER_DISP_CONFIG * Read configuration related to the parser-dispatcher subsystem. @@ -14674,7 +14483,6 @@ #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MINNUM 1 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_MAXNUM 63 - /***********************************/ /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG * Configure TX port sniffing for the physical port associated with the calling @@ -14717,7 +14525,6 @@ /* MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT msgresponse */ #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_TX_PORT_SNIFF_CONFIG * Obtain the current TX port sniffing configuration for the physical port @@ -14753,7 +14560,6 @@ #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4 - /***********************************/ /* MC_CMD_RMON_STATS_RX_ERRORS * Per queue rx error stats. @@ -14784,7 +14590,6 @@ #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_OFST 12 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4 - /***********************************/ /* MC_CMD_GET_PCIE_RESOURCE_INFO * Find out about available PCIE resources @@ -14823,7 +14628,6 @@ #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_OFST 24 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4 - /***********************************/ /* MC_CMD_GET_PORT_MODES * Find out about available port modes @@ -14848,7 +14652,6 @@ #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST 8 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4 - /***********************************/ /* MC_CMD_READ_ATB * Sample voltages on the ATB @@ -14877,7 +14680,6 @@ #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4 - /***********************************/ /* MC_CMD_GET_WORKAROUNDS * Read the list of all implemented and all currently enabled workarounds. The @@ -14915,7 +14717,6 @@ /* enum: Bug 61265 work around (broken EVQ TMR writes). */ #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80 - /***********************************/ /* MC_CMD_PRIVILEGE_MASK * Read/set privileges of an arbitrary PCIe function @@ -14989,7 +14790,6 @@ #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4 - /***********************************/ /* MC_CMD_LINK_STATE_MODE * Read/set link state mode of a VF @@ -15025,7 +14825,6 @@ #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4 - /***********************************/ /* MC_CMD_GET_SNAPSHOT_LENGTH * Obtain the current range of allowable values for the SNAPSHOT_LENGTH @@ -15048,7 +14847,6 @@ #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4 - /***********************************/ /* MC_CMD_FUSE_DIAGS * Additional fuse diagnostics @@ -15100,7 +14898,6 @@ #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_OFST 44 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4 - /***********************************/ /* MC_CMD_PRIVILEGE_MODIFY * Modify the privileges of a set of PCIe functions. Note that this operation @@ -15144,7 +14941,6 @@ /* MC_CMD_PRIVILEGE_MODIFY_OUT msgresponse */ #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_READ_BYTES * Read XPM memory @@ -15173,7 +14969,6 @@ #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MAXNUM 252 - /***********************************/ /* MC_CMD_XPM_WRITE_BYTES * Write XPM memory @@ -15202,7 +14997,6 @@ /* MC_CMD_XPM_WRITE_BYTES_OUT msgresponse */ #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_READ_SECTOR * Read XPM sector @@ -15239,7 +15033,6 @@ #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MAXNUM 32 - /***********************************/ /* MC_CMD_XPM_WRITE_SECTOR * Write XPM sector @@ -15282,7 +15075,6 @@ #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4 - /***********************************/ /* MC_CMD_XPM_INVALIDATE_SECTOR * Invalidate XPM sector @@ -15301,7 +15093,6 @@ /* MC_CMD_XPM_INVALIDATE_SECTOR_OUT msgresponse */ #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_BLANK_CHECK * Blank-check XPM memory and report bad locations @@ -15335,7 +15126,6 @@ #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MAXNUM 124 - /***********************************/ /* MC_CMD_XPM_REPAIR * Blank-check and repair XPM memory @@ -15357,7 +15147,6 @@ /* MC_CMD_XPM_REPAIR_OUT msgresponse */ #define MC_CMD_XPM_REPAIR_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_DECODER_TEST * Test XPM memory address decoders for gross manufacturing defects. Can only @@ -15374,7 +15163,6 @@ /* MC_CMD_XPM_DECODER_TEST_OUT msgresponse */ #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_WRITE_TEST * XPM memory write test. Test XPM write logic for gross manufacturing defects @@ -15394,7 +15182,6 @@ /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 - /***********************************/ /* MC_CMD_EXEC_SIGNED * Check the CMAC of the contents of IMEM and DMEM against the value supplied @@ -15427,7 +15214,6 @@ /* MC_CMD_EXEC_SIGNED_OUT msgresponse */ #define MC_CMD_EXEC_SIGNED_OUT_LEN 0 - /***********************************/ /* MC_CMD_PREPARE_SIGNED * Prepare to upload a signed image. This will scrub the specified length of @@ -15448,7 +15234,6 @@ /* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 - /***********************************/ /* MC_CMD_SET_SECURITY_RULE * Set blacklist and/or whitelist action for a particular match criteria. @@ -15623,7 +15408,6 @@ #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_OFST 28 #define MC_CMD_SET_SECURITY_RULE_OUT_COUNTER_ID_LEN 4 - /***********************************/ /* MC_CMD_RESET_SECURITY_RULES * Reset all blacklist and whitelist actions for a particular physical port, or @@ -15648,7 +15432,6 @@ /* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */ #define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_SECURITY_RULESET_VERSION * Return a large hash value representing a "version" of the complete set of @@ -15676,7 +15459,6 @@ #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MINNUM 1 #define MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION_MAXNUM 252 - /***********************************/ /* MC_CMD_SECURITY_RULE_COUNTER_ALLOC * Allocate counters for use with blacklist / whitelist rules. (Medford-only; @@ -15711,7 +15493,6 @@ #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM 0 #define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM 62 - /***********************************/ /* MC_CMD_SECURITY_RULE_COUNTER_FREE * Allocate counters for use with blacklist / whitelist rules. (Medford-only; @@ -15741,7 +15522,6 @@ /* MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT msgresponse */ #define MC_CMD_SECURITY_RULE_COUNTER_FREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_SUBNET_MAP_SET_NODE * Atomically update a trie node in the map of subnets to subnet IDs. The @@ -15793,7 +15573,6 @@ #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_LBN 16 #define PORTRANGE_TREE_ENTRY_LEAF_PORTRANGE_ID_WIDTH 16 - /***********************************/ /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE * Atomically update the entire tree mapping remote port ranges to portrange @@ -15824,7 +15603,6 @@ /* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT msgresponse */ #define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_OUT_LEN 0 - /***********************************/ /* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE * Atomically update the entire tree mapping remote port ranges to portrange @@ -15876,7 +15654,6 @@ #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16 - /***********************************/ /* MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS * Configure UDP ports for tunnel encapsulation hardware acceleration. The @@ -15918,7 +15695,6 @@ #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_WIDTH 1 - /***********************************/ /* MC_CMD_RX_BALANCING * Configure a port upconverter to distribute the packets on both RX engines. @@ -15949,7 +15725,6 @@ /* MC_CMD_RX_BALANCING_OUT msgresponse */ #define MC_CMD_RX_BALANCING_OUT_LEN 0 - /***********************************/ /* MC_CMD_TSA_BIND * TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more @@ -16481,7 +16256,6 @@ #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_OFST 0 #define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_LEN 4 - /***********************************/ /* MC_CMD_MANAGE_SECURITY_RULESET_CACHE * Manage the persistent NVRAM cache of security rules created with @@ -16543,7 +16317,6 @@ #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MINNUM 1 #define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_VERSION_MAXNUM 248 - /***********************************/ /* MC_CMD_NVRAM_PRIVATE_APPEND * Append a single TLV to the MC_USAGE_TLV partition. Returns MC_CMD_ERR_EEXIST @@ -16573,7 +16346,6 @@ /* MC_CMD_NVRAM_PRIVATE_APPEND_OUT msgresponse */ #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0 - /***********************************/ /* MC_CMD_XPM_VERIFY_CONTENTS * Verify that the contents of the XPM memory is correct (Medford only). This @@ -16610,7 +16382,6 @@ #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MAXNUM 240 - /***********************************/ /* MC_CMD_SET_EVQ_TMR * Update the timer load, timer reload and timer mode values for a given EVQ. @@ -16653,7 +16424,6 @@ #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4 - /***********************************/ /* MC_CMD_GET_EVQ_TMR_PROPERTIES * Query properties about the event queue timers. @@ -16721,7 +16491,6 @@ #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_OFST 32 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4 - /***********************************/ /* MC_CMD_ALLOCATE_TX_VFIFO_CP * When we use the TX_vFIFO_ULL mode, we can allocate common pools using the @@ -16773,7 +16542,6 @@ #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4 - /***********************************/ /* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO * When we use the TX_vFIFO_ULL mode, we can allocate vFIFOs using the @@ -16826,7 +16594,6 @@ #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4 - /***********************************/ /* MC_CMD_TEARDOWN_TX_VFIFO_VF * This interface clears the configuration of the given vFIFO and leaves it @@ -16846,7 +16613,6 @@ /* MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT msgresponse */ #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0 - /***********************************/ /* MC_CMD_DEALLOCATE_TX_VFIFO_CP * This interface clears the configuration of the given common pool and leaves @@ -16866,7 +16632,6 @@ /* MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT msgresponse */ #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0 - /***********************************/ /* MC_CMD_REKEY * This request causes the NIC to generate a new per-NIC key and program it @@ -16898,7 +16663,6 @@ /* MC_CMD_REKEY_OUT msgresponse */ #define MC_CMD_REKEY_OUT_LEN 0 - /***********************************/ /* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS * This interface allows the host to find out how many common pool buffers are @@ -16921,7 +16685,6 @@ #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4 - /***********************************/ /* MC_CMD_SET_SECURITY_FUSES * Change the security level of the adapter by setting bits in the write-once @@ -16961,7 +16724,6 @@ #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_OFST 0 #define MC_CMD_SET_SECURITY_FUSES_V2_OUT_FLAGS_LEN 4 - /***********************************/ /* MC_CMD_TSA_INFO * Messages sent from TSA adapter to TSA controller. This command is only valid @@ -17097,7 +16859,6 @@ /* MC_CMD_TSA_INFO_OUT msgresponse */ #define MC_CMD_TSA_INFO_OUT_LEN 0 - /***********************************/ /* MC_CMD_HOST_INFO * Commands to appply or retrieve host-related information from an adapter. @@ -17162,7 +16923,6 @@ /* MC_CMD_HOST_INFO_OUT_SET_UUID msgresponse */ #define MC_CMD_HOST_INFO_OUT_SET_UUID_LEN 0 - /***********************************/ /* MC_CMD_TSAN_INFO * Get TSA adapter information. TSA controllers query each TSA adapter to learn @@ -17256,7 +17016,6 @@ #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_OFST 32 #define MC_CMD_TSAN_INFO_OUT_GET_CFG_V2_STATS_WIDTH_LEN 4 - /***********************************/ /* MC_CMD_TSA_STATISTICS * TSA adapter statistics operations. @@ -17369,7 +17128,6 @@ #define MC_TSA_STATISTICS_ENTRY_RX_STAT_LBN 64 #define MC_TSA_STATISTICS_ENTRY_RX_STAT_WIDTH 64 - /***********************************/ /* MC_CMD_ERASE_INITIAL_NIC_SECRET * This request causes the NIC to find the initial NIC secret (programmed @@ -17388,7 +17146,6 @@ /* MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT msgresponse */ #define MC_CMD_ERASE_INITIAL_NIC_SECRET_OUT_LEN 0 - /***********************************/ /* MC_CMD_TSA_CONFIG * TSA adapter configuration operations. This command is used to prepare the @@ -17497,7 +17254,6 @@ #define MC_TSA_IPV4_ITEM_IPV4_ADDR_LBN 32 #define MC_TSA_IPV4_ITEM_IPV4_ADDR_WIDTH 32 - /***********************************/ /* MC_CMD_TSA_IPADDR * TSA operations relating to the monitoring and expiry of local IP addresses @@ -17585,7 +17341,6 @@ /* MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4 msgresponse */ #define MC_CMD_TSA_IPADDR_OUT_REMOVE_IPV4_LEN 0 - /***********************************/ /* MC_CMD_SECURE_NIC_INFO * Get secure NIC information. While many of the features reported by these @@ -17675,7 +17430,6 @@ #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_OFST 418 #define MC_CMD_SECURE_NIC_INFO_OUT_STATUS_FIRMWARE_VERSION_D_LEN 2 - /***********************************/ /* MC_CMD_TSA_TEST * A simple ping-pong command just to test the adapter<>controller MCDI @@ -17695,7 +17449,6 @@ /* MC_CMD_TSA_TEST_OUT msgresponse */ #define MC_CMD_TSA_TEST_OUT_LEN 0 - /***********************************/ /* MC_CMD_TSA_RULESET_OVERRIDE * Override TSA ruleset that is currently active on the adapter. This operation @@ -17731,7 +17484,6 @@ /* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */ #define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0 - /***********************************/ /* MC_CMD_TSAC_REQUEST * Generic command to send requests from a TSA controller to a TSA adapter. @@ -17756,7 +17508,6 @@ /* MC_CMD_TSAC_REQUEST_OUT msgresponse */ #define MC_CMD_TSAC_REQUEST_OUT_LEN 0 - /***********************************/ /* MC_CMD_SUC_VERSION * Get the version of the SUC @@ -17801,7 +17552,6 @@ #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4 - /***********************************/ /* MC_CMD_SUC_MANFTEST * Operations to support manftest on SUC based systems. @@ -17959,7 +17709,6 @@ /* MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT msgresponse */ #define MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0 - /***********************************/ /* MC_CMD_GET_CERTIFICATE * Request a certificate. @@ -18030,7 +17779,6 @@ #define MC_CMD_GET_CERTIFICATE_OUT_DATA_MINNUM 1 #define MC_CMD_GET_CERTIFICATE_OUT_DATA_MAXNUM 240 - /***********************************/ /* MC_CMD_GET_NIC_GLOBAL * Get a global value which applies to all PCI functions @@ -18055,7 +17803,6 @@ #define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_OFST 0 #define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_LEN 4 - /***********************************/ /* MC_CMD_SET_NIC_GLOBAL * Set a global value which applies to all PCI functions. Most global values @@ -18101,7 +17848,6 @@ */ #define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM 0x1 - /***********************************/ /* MC_CMD_LTSSM_TRACE_POLL * Medford2 hardware has support for logging all LTSSM state transitions to a diff --git a/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h b/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h index d5defc89904b..378d62aa37f3 100644 --- a/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h +++ b/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h @@ -30,8 +30,6 @@ #ifndef _SYS_EFX_REGS_MCDI_AOE_H #define _SYS_EFX_REGS_MCDI_AOE_H - - /***********************************/ /* MC_CMD_FC * Perform an FC operation @@ -2204,7 +2202,6 @@ /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 - /***********************************/ /* MC_CMD_AOE * AOE operations on MC diff --git a/sys/dev/sfxge/common/efx_regs_pci.h b/sys/dev/sfxge/common/efx_regs_pci.h index 4d63c4a84b2d..c321a38d9a2f 100644 --- a/sys/dev/sfxge/common/efx_regs_pci.h +++ b/sys/dev/sfxge/common/efx_regs_pci.h @@ -50,7 +50,6 @@ extern "C" { #define PCRF_AZ_VEND_ID_LBN 0 #define PCRF_AZ_VEND_ID_WIDTH 16 - /* * PC_DEV_ID_REG(16bit): * Device ID register @@ -62,7 +61,6 @@ extern "C" { #define PCRF_AZ_DEV_ID_LBN 0 #define PCRF_AZ_DEV_ID_WIDTH 16 - /* * PC_CMD_REG(16bit): * Command register @@ -94,7 +92,6 @@ extern "C" { #define PCRF_AZ_IO_EN_LBN 0 #define PCRF_AZ_IO_EN_WIDTH 1 - /* * PC_STAT_REG(16bit): * Status register @@ -126,7 +123,6 @@ extern "C" { #define PCRF_AZ_INTX_STAT_LBN 3 #define PCRF_AZ_INTX_STAT_WIDTH 1 - /* * PC_REV_ID_REG(8bit): * Class code & revision ID register @@ -138,7 +134,6 @@ extern "C" { #define PCRF_AZ_REV_ID_LBN 0 #define PCRF_AZ_REV_ID_WIDTH 8 - /* * PC_CC_REG(24bit): * Class code register @@ -154,7 +149,6 @@ extern "C" { #define PCRF_AZ_PROG_IF_LBN 0 #define PCRF_AZ_PROG_IF_WIDTH 8 - /* * PC_CACHE_LSIZE_REG(8bit): * Cache line size @@ -166,7 +160,6 @@ extern "C" { #define PCRF_AZ_CACHE_LSIZE_LBN 0 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 - /* * PC_MST_LAT_REG(8bit): * Master latency timer register @@ -178,7 +171,6 @@ extern "C" { #define PCRF_AZ_MST_LAT_LBN 0 #define PCRF_AZ_MST_LAT_WIDTH 8 - /* * PC_HDR_TYPE_REG(8bit): * Header type register @@ -192,7 +184,6 @@ extern "C" { #define PCRF_AZ_TYPE_LBN 0 #define PCRF_AZ_TYPE_WIDTH 7 - /* * PC_BIST_REG(8bit): * BIST register @@ -204,7 +195,6 @@ extern "C" { #define PCRF_AZ_BIST_LBN 0 #define PCRF_AZ_BIST_WIDTH 8 - /* * PC_BAR0_REG(32bit): * Primary function base address register 0 @@ -222,7 +212,6 @@ extern "C" { #define PCRF_AZ_BAR0_IOM_LBN 0 #define PCRF_AZ_BAR0_IOM_WIDTH 1 - /* * PC_BAR1_REG(32bit): * Primary function base address register 1, BAR1 is not implemented so read only. @@ -234,7 +223,6 @@ extern "C" { #define PCRF_DZ_BAR1_LBN 0 #define PCRF_DZ_BAR1_WIDTH 32 - /* * PC_BAR2_LO_REG(32bit): * Primary function base address register 2 low bits @@ -252,7 +240,6 @@ extern "C" { #define PCRF_AZ_BAR2_IOM_LBN 0 #define PCRF_AZ_BAR2_IOM_WIDTH 1 - /* * PC_BAR2_HI_REG(32bit): * Primary function base address register 2 high bits @@ -264,7 +251,6 @@ extern "C" { #define PCRF_AZ_BAR2_HI_LBN 0 #define PCRF_AZ_BAR2_HI_WIDTH 32 - /* * PC_BAR4_LO_REG(32bit): * Primary function base address register 2 low bits @@ -282,7 +268,6 @@ extern "C" { #define PCRF_CZ_BAR4_IOM_LBN 0 #define PCRF_CZ_BAR4_IOM_WIDTH 1 - /* * PC_BAR4_HI_REG(32bit): * Primary function base address register 2 high bits @@ -294,7 +279,6 @@ extern "C" { #define PCRF_CZ_BAR4_HI_LBN 0 #define PCRF_CZ_BAR4_HI_WIDTH 32 - /* * PC_SS_VEND_ID_REG(16bit): * Sub-system vendor ID register @@ -306,7 +290,6 @@ extern "C" { #define PCRF_AZ_SS_VEND_ID_LBN 0 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 - /* * PC_SS_ID_REG(16bit): * Sub-system ID register @@ -318,7 +301,6 @@ extern "C" { #define PCRF_AZ_SS_ID_LBN 0 #define PCRF_AZ_SS_ID_WIDTH 16 - /* * PC_EXPROM_BAR_REG(32bit): * Expansion ROM base address register @@ -338,7 +320,6 @@ extern "C" { #define PCRF_AZ_EXPROM_EN_LBN 0 #define PCRF_AZ_EXPROM_EN_WIDTH 1 - /* * PC_CAP_PTR_REG(8bit): * Capability pointer register @@ -350,7 +331,6 @@ extern "C" { #define PCRF_AZ_CAP_PTR_LBN 0 #define PCRF_AZ_CAP_PTR_WIDTH 8 - /* * PC_INT_LINE_REG(8bit): * Interrupt line register @@ -362,7 +342,6 @@ extern "C" { #define PCRF_AZ_INT_LINE_LBN 0 #define PCRF_AZ_INT_LINE_WIDTH 8 - /* * PC_INT_PIN_REG(8bit): * Interrupt pin register @@ -378,7 +357,6 @@ extern "C" { #define PCFE_DZ_INTPIN_INTB 2 #define PCFE_DZ_INTPIN_INTA 1 - /* * PC_PM_CAP_ID_REG(8bit): * Power management capability ID @@ -390,7 +368,6 @@ extern "C" { #define PCRF_AZ_PM_CAP_ID_LBN 0 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 - /* * PC_PM_NXT_PTR_REG(8bit): * Power management next item pointer @@ -402,7 +379,6 @@ extern "C" { #define PCRF_AZ_PM_NXT_PTR_LBN 0 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 - /* * PC_PM_CAP_REG(16bit): * Power management capabilities register @@ -426,7 +402,6 @@ extern "C" { #define PCRF_AZ_PM_PME_VER_LBN 0 #define PCRF_AZ_PM_PME_VER_WIDTH 3 - /* * PC_PM_CS_REG(16bit): * Power management control & status register @@ -448,7 +423,6 @@ extern "C" { #define PCRF_AZ_PM_PWR_ST_LBN 0 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 - /* * PC_MSI_CAP_ID_REG(8bit): * MSI capability ID @@ -460,7 +434,6 @@ extern "C" { #define PCRF_AZ_MSI_CAP_ID_LBN 0 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 - /* * PC_MSI_NXT_PTR_REG(8bit): * MSI next item pointer @@ -472,7 +445,6 @@ extern "C" { #define PCRF_AZ_MSI_NXT_PTR_LBN 0 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 - /* * PC_MSI_CTL_REG(16bit): * MSI control register @@ -490,7 +462,6 @@ extern "C" { #define PCRF_AZ_MSI_EN_LBN 0 #define PCRF_AZ_MSI_EN_WIDTH 1 - /* * PC_MSI_ADR_LO_REG(32bit): * MSI low 32 bits address register @@ -502,7 +473,6 @@ extern "C" { #define PCRF_AZ_MSI_ADR_LO_LBN 2 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 - /* * PC_MSI_ADR_HI_REG(32bit): * MSI high 32 bits address register @@ -514,7 +484,6 @@ extern "C" { #define PCRF_AZ_MSI_ADR_HI_LBN 0 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 - /* * PC_MSI_DAT_REG(16bit): * MSI data register @@ -526,7 +495,6 @@ extern "C" { #define PCRF_AZ_MSI_DAT_LBN 0 #define PCRF_AZ_MSI_DAT_WIDTH 16 - /* * PC_PCIE_CAP_LIST_REG(16bit): * PCIe capability list register @@ -543,7 +511,6 @@ extern "C" { #define PCRF_AZ_PCIE_CAP_ID_LBN 0 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 - /* * PC_PCIE_CAP_REG(16bit): * PCIe capability register @@ -564,7 +531,6 @@ extern "C" { #define PCRF_AZ_PCIE_CAP_VER_LBN 0 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 - /* * PC_DEV_CAP_REG(32bit): * PCIe device capabilities register @@ -601,7 +567,6 @@ extern "C" { #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 - /* * PC_DEV_CTL_REG(16bit): * PCIe device control register @@ -652,7 +617,6 @@ extern "C" { #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 - /* * PC_DEV_STAT_REG(16bit): * PCIe device status register @@ -677,7 +641,6 @@ extern "C" { #define PCRF_AZ_CORR_ERR_DET_LBN 0 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 - /* * PC_LNK_CAP_REG(32bit): * PCIe link capabilities register @@ -712,7 +675,6 @@ extern "C" { #define PCRF_AZ_MAX_LNK_SP_LBN 0 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 - /* * PC_LNK_CTL_REG(16bit): * PCIe link control register @@ -739,7 +701,6 @@ extern "C" { #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 - /* * PC_LNK_STAT_REG(16bit): * PCIe link status register @@ -762,7 +723,6 @@ extern "C" { #define PCRF_AZ_LNK_SP_LBN 0 #define PCRF_AZ_LNK_SP_WIDTH 4 - /* * PC_SLOT_CAP_REG(32bit): * PCIe slot capabilities register @@ -792,7 +752,6 @@ extern "C" { #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 - /* * PC_SLOT_CTL_REG(16bit): * PCIe slot control register @@ -820,7 +779,6 @@ extern "C" { #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 - /* * PC_SLOT_STAT_REG(16bit): * PCIe slot status register @@ -844,7 +802,6 @@ extern "C" { #define PCRF_AB_ATTN_BUTDET_LBN 0 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 - /* * PC_MSIX_CAP_ID_REG(8bit): * MSIX Capability ID @@ -859,7 +816,6 @@ extern "C" { #define PCRF_BZ_MSIX_CAP_ID_LBN 0 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 - /* * PC_MSIX_NXT_PTR_REG(8bit): * MSIX Capability Next Capability Ptr @@ -874,7 +830,6 @@ extern "C" { #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 - /* * PC_MSIX_CTL_REG(16bit): * MSIX control register @@ -893,7 +848,6 @@ extern "C" { #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 - /* * PC_MSIX_TBL_BASE_REG(32bit): * MSIX Capability Vector Table Base @@ -910,7 +864,6 @@ extern "C" { #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 - /* * PC_DEV_CAP2_REG(32bit): * PCIe Device Capabilities 2 @@ -941,7 +894,6 @@ extern "C" { #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 - /* * PC_DEV_CTL2_REG(16bit): * PCIe Device Control 2 @@ -963,7 +915,6 @@ extern "C" { #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 - /* * PC_MSIX_PBA_BASE_REG(32bit): * MSIX Capability PBA Base @@ -980,7 +931,6 @@ extern "C" { #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 - /* * PC_LNK_CAP2_REG(32bit): * PCIe Link Capability 2 @@ -992,7 +942,6 @@ extern "C" { #define PCRF_DZ_LNK_SPEED_SUP_LBN 1 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 - /* * PC_LNK_CTL2_REG(16bit): * PCIe Link Control 2 @@ -1021,7 +970,6 @@ extern "C" { #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 - /* * PC_LNK_STAT2_REG(16bit): * PCIe Link Status 2 @@ -1033,7 +981,6 @@ extern "C" { #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 - /* * PC_VPD_CAP_ID_REG(8bit): * VPD data register @@ -1045,7 +992,6 @@ extern "C" { #define PCRF_AB_VPD_CAP_ID_LBN 0 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 - /* * PC_VPD_NXT_PTR_REG(8bit): * VPD next item pointer @@ -1057,7 +1003,6 @@ extern "C" { #define PCRF_AB_VPD_NXT_PTR_LBN 0 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 - /* * PC_VPD_ADDR_REG(16bit): * VPD address register @@ -1071,7 +1016,6 @@ extern "C" { #define PCRF_AB_VPD_ADDR_LBN 0 #define PCRF_AB_VPD_ADDR_WIDTH 15 - /* * PC_VPD_CAP_DATA_REG(32bit): * documentation to be written for sum_PC_VPD_CAP_DATA_REG @@ -1086,7 +1030,6 @@ extern "C" { #define PCRF_AZ_VPD_DATA_LBN 0 #define PCRF_AZ_VPD_DATA_WIDTH 32 - /* * PC_VPD_CAP_CTL_REG(8bit): * VPD control and capabilities register @@ -1104,7 +1047,6 @@ extern "C" { #define PCRF_CZ_VPD_CAP_ID_LBN 0 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 - /* * PC_AER_CAP_HDR_REG(32bit): * AER capability header register @@ -1120,7 +1062,6 @@ extern "C" { #define PCRF_AZ_AERCAPHDR_ID_LBN 0 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 - /* * PC_AER_UNCORR_ERR_STAT_REG(32bit): * AER Uncorrectable error status register @@ -1152,7 +1093,6 @@ extern "C" { #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 - /* * PC_AER_UNCORR_ERR_MASK_REG(32bit): * AER Uncorrectable error mask register @@ -1188,7 +1128,6 @@ extern "C" { #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 - /* * PC_AER_UNCORR_ERR_SEV_REG(32bit): * AER Uncorrectable error severity register @@ -1220,7 +1159,6 @@ extern "C" { #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 - /* * PC_AER_CORR_ERR_STAT_REG(32bit): * AER Correctable error status register @@ -1242,7 +1180,6 @@ extern "C" { #define PCRF_AZ_RX_ERR_STAT_LBN 0 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 - /* * PC_AER_CORR_ERR_MASK_REG(32bit): * AER Correctable error status register @@ -1264,7 +1201,6 @@ extern "C" { #define PCRF_AZ_RX_ERR_MASK_LBN 0 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 - /* * PC_AER_CAP_CTL_REG(32bit): * AER capability and control register @@ -1284,7 +1220,6 @@ extern "C" { #define PCRF_AZ_1ST_ERR_PTR_LBN 0 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 - /* * PC_AER_HDR_LOG_REG(128bit): * AER Header log register @@ -1296,7 +1231,6 @@ extern "C" { #define PCRF_AZ_HDR_LOG_LBN 0 #define PCRF_AZ_HDR_LOG_WIDTH 128 - /* * PC_DEVSN_CAP_HDR_REG(32bit): * Device serial number capability header register @@ -1312,7 +1246,6 @@ extern "C" { #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 - /* * PC_DEVSN_DWORD0_REG(32bit): * Device serial number DWORD0 @@ -1324,7 +1257,6 @@ extern "C" { #define PCRF_CZ_DEVSN_DWORD0_LBN 0 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 - /* * PC_DEVSN_DWORD1_REG(32bit): * Device serial number DWORD0 @@ -1336,7 +1268,6 @@ extern "C" { #define PCRF_CZ_DEVSN_DWORD1_LBN 0 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 - /* * PC_ARI_CAP_HDR_REG(32bit): * ARI capability header register @@ -1352,7 +1283,6 @@ extern "C" { #define PCRF_CZ_ARICAPHDR_ID_LBN 0 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 - /* * PC_ARI_CAP_REG(16bit): * ARI Capabilities @@ -1368,7 +1298,6 @@ extern "C" { #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 - /* * PC_ARI_CTL_REG(16bit): * ARI Control @@ -1384,7 +1313,6 @@ extern "C" { #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 - /* * PC_SEC_PCIE_CAP_REG(32bit): * Secondary PCIE Capability Register @@ -1400,7 +1328,6 @@ extern "C" { #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 - /* * PC_SRIOV_CAP_HDR_REG(32bit): * SRIOV capability header register @@ -1419,7 +1346,6 @@ extern "C" { #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 - /* * PC_SRIOV_CAP_REG(32bit): * SRIOV Capabilities @@ -1438,7 +1364,6 @@ extern "C" { #define PCRF_CZ_VF_MIGR_CAP_LBN 0 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 - /* * PC_LINK_CONTROL3_REG(32bit): * Link Control 3. @@ -1452,7 +1377,6 @@ extern "C" { #define PCRF_DZ_PERFORM_EQL_LBN 0 #define PCRF_DZ_PERFORM_EQL_WIDTH 1 - /* * PC_LANE_ERROR_STAT_REG(32bit): * Lane Error Status Register. @@ -1464,7 +1388,6 @@ extern "C" { #define PCRF_DZ_LANE_STATUS_LBN 0 #define PCRF_DZ_LANE_STATUS_WIDTH 8 - /* * PC_SRIOV_CTL_REG(16bit): * SRIOV Control @@ -1487,7 +1410,6 @@ extern "C" { #define PCRF_CZ_VF_EN_LBN 0 #define PCRF_CZ_VF_EN_WIDTH 1 - /* * PC_SRIOV_STAT_REG(16bit): * SRIOV Status @@ -1502,7 +1424,6 @@ extern "C" { #define PCRF_CZ_VF_MIGR_STAT_LBN 0 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 - /* * PC_LANE01_EQU_CONTROL_REG(32bit): * Lanes 0,1 Equalization Control Register. @@ -1516,7 +1437,6 @@ extern "C" { #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 - /* * PC_SRIOV_INITIALVFS_REG(16bit): * SRIOV Initial VFs @@ -1531,7 +1451,6 @@ extern "C" { #define PCRF_CZ_VF_INITIALVFS_LBN 0 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 - /* * PC_SRIOV_TOTALVFS_REG(10bit): * SRIOV Total VFs @@ -1546,7 +1465,6 @@ extern "C" { #define PCRF_CZ_VF_TOTALVFS_LBN 0 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 - /* * PC_SRIOV_NUMVFS_REG(16bit): * SRIOV Number of VFs @@ -1561,7 +1479,6 @@ extern "C" { #define PCRF_CZ_VF_NUMVFS_LBN 0 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 - /* * PC_LANE23_EQU_CONTROL_REG(32bit): * Lanes 2,3 Equalization Control Register. @@ -1575,7 +1492,6 @@ extern "C" { #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 - /* * PC_SRIOV_FN_DPND_LNK_REG(16bit): * SRIOV Function dependency link @@ -1590,7 +1506,6 @@ extern "C" { #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 - /* * PC_SRIOV_1STVF_OFFSET_REG(16bit): * SRIOV First VF Offset @@ -1605,7 +1520,6 @@ extern "C" { #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 - /* * PC_LANE45_EQU_CONTROL_REG(32bit): * Lanes 4,5 Equalization Control Register. @@ -1619,7 +1533,6 @@ extern "C" { #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 - /* * PC_SRIOV_VFSTRIDE_REG(16bit): * SRIOV VF Stride @@ -1634,7 +1547,6 @@ extern "C" { #define PCRF_CZ_VF_VFSTRIDE_LBN 0 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 - /* * PC_LANE67_EQU_CONTROL_REG(32bit): * Lanes 6,7 Equalization Control Register. @@ -1648,7 +1560,6 @@ extern "C" { #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 - /* * PC_SRIOV_DEVID_REG(16bit): * SRIOV VF Device ID @@ -1663,7 +1574,6 @@ extern "C" { #define PCRF_CZ_VF_DEVID_LBN 0 #define PCRF_CZ_VF_DEVID_WIDTH 16 - /* * PC_SRIOV_SUP_PAGESZ_REG(16bit): * SRIOV Supported Page Sizes @@ -1678,7 +1588,6 @@ extern "C" { #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 - /* * PC_SRIOV_SYS_PAGESZ_REG(32bit): * SRIOV System Page Size @@ -1693,7 +1602,6 @@ extern "C" { #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 - /* * PC_SRIOV_BAR0_REG(32bit): * SRIOV VF Bar0 @@ -1716,7 +1624,6 @@ extern "C" { #define PCRF_DZ_VF_BAR0_IOM_LBN 0 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 - /* * PC_SRIOV_BAR1_REG(32bit): * SRIOV Bar1 @@ -1733,7 +1640,6 @@ extern "C" { #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 - /* * PC_SRIOV_BAR2_REG(32bit): * SRIOV Bar2 @@ -1756,7 +1662,6 @@ extern "C" { #define PCRF_DZ_VF_BAR2_IOM_LBN 0 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 - /* * PC_SRIOV_BAR3_REG(32bit): * SRIOV Bar3 @@ -1773,7 +1678,6 @@ extern "C" { #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 - /* * PC_SRIOV_BAR4_REG(32bit): * SRIOV Bar4 @@ -1790,7 +1694,6 @@ extern "C" { #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 - /* * PC_SRIOV_BAR5_REG(32bit): * SRIOV Bar5 @@ -1807,7 +1710,6 @@ extern "C" { #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 - /* * PC_SRIOV_RSVD_REG(16bit): * Reserved register @@ -1819,7 +1721,6 @@ extern "C" { #define PCRF_DZ_VF_RSVD_LBN 0 #define PCRF_DZ_VF_RSVD_WIDTH 16 - /* * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): * SRIOV VF Migration State Array Offset @@ -1836,7 +1737,6 @@ extern "C" { #define PCRF_CZ_VF_MIGR_BIR_LBN 0 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 - /* * PC_TPH_CAP_HDR_REG(32bit): * TPH Capability Header Register @@ -1852,7 +1752,6 @@ extern "C" { #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 - /* * PC_TPH_REQ_CAP_REG(32bit): * TPH Requester Capability Register @@ -1874,7 +1773,6 @@ extern "C" { #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 - /* * PC_TPH_REQ_CTL_REG(32bit): * TPH Requester Control Register @@ -1888,7 +1786,6 @@ extern "C" { #define PCRF_DZ_TPH_ST_MODE_LBN 0 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 - /* * PC_LTR_CAP_HDR_REG(32bit): * Latency Tolerance Reporting Cap Header Reg @@ -1904,7 +1801,6 @@ extern "C" { #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 - /* * PC_LTR_MAX_SNOOP_REG(32bit): * LTR Maximum Snoop/No Snoop Register @@ -1922,7 +1818,6 @@ extern "C" { #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 - /* * PC_ACK_LAT_TMR_REG(32bit): * ACK latency timer & replay timer register @@ -1936,7 +1831,6 @@ extern "C" { #define PCRF_AC_ALT_LBN 0 #define PCRF_AC_ALT_WIDTH 16 - /* * PC_OTHER_MSG_REG(32bit): * Other message register @@ -1954,7 +1848,6 @@ extern "C" { #define PCRF_AC_OM_CRPT0_LBN 0 #define PCRF_AC_OM_CRPT0_WIDTH 8 - /* * PC_FORCE_LNK_REG(24bit): * Port force link register @@ -1970,7 +1863,6 @@ extern "C" { #define PCRF_AC_LN_LBN 0 #define PCRF_AC_LN_WIDTH 8 - /* * PC_ACK_FREQ_REG(32bit): * ACK frequency register @@ -1994,7 +1886,6 @@ extern "C" { #define PCRF_AC_ACK_FREQ_LBN 0 #define PCRF_AC_ACK_FREQ_WIDTH 8 - /* * PC_PORT_LNK_CTL_REG(32bit): * Port link control register @@ -2032,7 +1923,6 @@ extern "C" { #define PCRF_AC_OMR_LBN 0 #define PCRF_AC_OMR_WIDTH 1 - /* * PC_LN_SKEW_REG(32bit): * Lane skew register @@ -2056,7 +1946,6 @@ extern "C" { #define PCRF_AC_LS0_LBN 0 #define PCRF_AC_LS0_WIDTH 8 - /* * PC_SYM_NUM_REG(16bit): * Symbol number register @@ -2084,7 +1973,6 @@ extern "C" { #define PCRF_AC_TS1_LBN 0 #define PCRF_AC_TS1_WIDTH 4 - /* * PC_SYM_TMR_FLT_MSK_REG(16bit): * Symbol timer and Filter Mask Register @@ -2104,7 +1992,6 @@ extern "C" { #define PCRF_CC_SI0_LBN 0 #define PCRF_CC_SI0_WIDTH 8 - /* * PC_SYM_TMR_REG(16bit): * Symbol timer register @@ -2120,7 +2007,6 @@ extern "C" { #define PCRF_AB_SI0_LBN 0 #define PCRF_AB_SI0_WIDTH 8 - /* * PC_FLT_MSK_REG(32bit): * Filter Mask Register 2 @@ -2132,7 +2018,6 @@ extern "C" { #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 - /* * PC_PHY_STAT_REG(32bit): * PHY status register @@ -2153,7 +2038,6 @@ extern "C" { #define PCRF_AC_SSCD_LBN 0 #define PCRF_AC_SSCD_WIDTH 1 - /* * PC_PHY_CTL_REG(32bit): * PHY control register @@ -2182,7 +2066,6 @@ extern "C" { #define PCRF_AC_FORCE_LOS_EN_LBN 0 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 - /* * PC_DEBUG0_REG(32bit): * Debug register 0 @@ -2202,7 +2085,6 @@ extern "C" { #define PCRF_AC_CDI00_LBN 0 #define PCRF_AC_CDI00_WIDTH 8 - /* * PC_DEBUG1_REG(32bit): * Debug register 1 @@ -2222,7 +2104,6 @@ extern "C" { #define PCRF_AC_CDI10_LBN 0 #define PCRF_AC_CDI10_WIDTH 8 - /* * PC_XPFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XPFCC_STAT_REG @@ -2236,7 +2117,6 @@ extern "C" { #define PCRF_AC_XPHC_LBN 0 #define PCRF_AC_XPHC_WIDTH 12 - /* * PC_XNPFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XNPFCC_STAT_REG @@ -2250,7 +2130,6 @@ extern "C" { #define PCRF_AC_XNPHC_LBN 0 #define PCRF_AC_XNPHC_WIDTH 12 - /* * PC_XCFCC_STAT_REG(24bit): * documentation to be written for sum_PC_XCFCC_STAT_REG @@ -2264,7 +2143,6 @@ extern "C" { #define PCRF_AC_XCHC_LBN 0 #define PCRF_AC_XCHC_WIDTH 12 - /* * PC_Q_STAT_REG(8bit): * documentation to be written for sum_PC_Q_STAT_REG @@ -2280,7 +2158,6 @@ extern "C" { #define PCRF_AC_RCNR_LBN 0 #define PCRF_AC_RCNR_WIDTH 1 - /* * PC_VC_XMIT_ARB1_REG(32bit): * VC Transmit Arbitration Register 1 @@ -2289,8 +2166,6 @@ extern "C" { #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 /* sienaa0=pci_f0_config */ - - /* * PC_VC_XMIT_ARB2_REG(32bit): * VC Transmit Arbitration Register 2 @@ -2299,8 +2174,6 @@ extern "C" { #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 /* sienaa0=pci_f0_config */ - - /* * PC_VC0_P_RQ_CTL_REG(32bit): * VC0 Posted Receive Queue Control @@ -2309,8 +2182,6 @@ extern "C" { #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 /* sienaa0=pci_f0_config */ - - /* * PC_VC0_NP_RQ_CTL_REG(32bit): * VC0 Non-Posted Receive Queue Control @@ -2319,8 +2190,6 @@ extern "C" { #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c /* sienaa0=pci_f0_config */ - - /* * PC_VC0_C_RQ_CTL_REG(32bit): * VC0 Completion Receive Queue Control @@ -2329,8 +2198,6 @@ extern "C" { #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 /* sienaa0=pci_f0_config */ - - /* * PC_GEN2_REG(32bit): * Gen2 Register @@ -2352,7 +2219,6 @@ extern "C" { #define PCRF_CC_NUM_FTS_LBN 0 #define PCRF_CC_NUM_FTS_WIDTH 8 - #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/efx_rx.c b/sys/dev/sfxge/common/efx_rx.c index b1185ae0b7da..b2c89199e486 100644 --- a/sys/dev/sfxge/common/efx_rx.c +++ b/sys/dev/sfxge/common/efx_rx.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_SIENA static __checkReturn efx_rc_t @@ -150,7 +149,6 @@ siena_rx_qdestroy( #endif /* EFSYS_OPT_SIENA */ - #if EFSYS_OPT_SIENA static const efx_rx_ops_t __efx_rx_siena_ops = { siena_rx_init, /* erxo_init */ @@ -209,7 +207,6 @@ static const efx_rx_ops_t __efx_rx_ef10_ops = { }; #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ - __checkReturn efx_rc_t efx_rx_init( __inout efx_nic_t *enp) @@ -955,7 +952,6 @@ fail1: #endif - void efx_rx_qdestroy( __in efx_rxq_t *erp) @@ -1081,7 +1077,6 @@ fail1: } #endif /* EFSYS_OPT_RX_SCATTER */ - #define EFX_RX_LFSR_HASH(_enp, _insert) \ do { \ efx_oword_t oword; \ @@ -1141,7 +1136,6 @@ fail1: _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) - #if EFSYS_OPT_RX_SCALE static __checkReturn efx_rc_t @@ -1456,7 +1450,6 @@ siena_rx_prefix_pktlen( return (ENOTSUP); } - static void siena_rx_qpost( __in efx_rxq_t *erp, diff --git a/sys/dev/sfxge/common/efx_sram.c b/sys/dev/sfxge/common/efx_sram.c index 587d9490f393..32007952fb2f 100644 --- a/sys/dev/sfxge/common/efx_sram.c +++ b/sys/dev/sfxge/common/efx_sram.c @@ -204,7 +204,6 @@ efx_sram_buf_tbl_clear( EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword); } - #if EFSYS_OPT_DIAG static void diff --git a/sys/dev/sfxge/common/efx_tunnel.c b/sys/dev/sfxge/common/efx_tunnel.c index a0dd75d2b2c9..21f50f3aec48 100644 --- a/sys/dev/sfxge/common/efx_tunnel.c +++ b/sys/dev/sfxge/common/efx_tunnel.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_TUNNEL #if EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON diff --git a/sys/dev/sfxge/common/efx_tx.c b/sys/dev/sfxge/common/efx_tx.c index 1b43363cb8a4..10aa7e8060ba 100644 --- a/sys/dev/sfxge/common/efx_tx.c +++ b/sys/dev/sfxge/common/efx_tx.c @@ -125,7 +125,6 @@ siena_tx_qstats_update( #endif /* EFSYS_OPT_SIENA */ - #if EFSYS_OPT_SIENA static const efx_tx_ops_t __efx_tx_siena_ops = { siena_tx_init, /* etxo_init */ @@ -234,7 +233,6 @@ static const efx_tx_ops_t __efx_tx_medford2_ops = { }; #endif /* EFSYS_OPT_MEDFORD2 */ - __checkReturn efx_rc_t efx_tx_init( __in efx_nic_t *enp) @@ -691,7 +689,6 @@ efx_tx_qdesc_checksum_create( etxop->etxo_qdesc_checksum_create(etp, flags, edp); } - #if EFSYS_OPT_QSTATS void efx_tx_qstats_update( @@ -707,7 +704,6 @@ efx_tx_qstats_update( } #endif - #if EFSYS_OPT_SIENA static __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/efx_types.h b/sys/dev/sfxge/common/efx_types.h index 8828aa230fd4..67ddd3cbad54 100644 --- a/sys/dev/sfxge/common/efx_types.h +++ b/sys/dev/sfxge/common/efx_types.h @@ -454,7 +454,6 @@ extern int fix_lint; (EFX_EXTRACT8((_byte).eb_u8[0], FIX_LINT(0), FIX_LINT(7), \ _low, _high)) - #define EFX_OWORD_FIELD64(_oword, _field) \ ((uint32_t)EFX_EXTRACT_OWORD64(_oword, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK32(_field)) @@ -483,7 +482,6 @@ extern int fix_lint; (EFX_EXTRACT_BYTE(_byte, EFX_LOW_BIT(_field), \ EFX_HIGH_BIT(_field)) & EFX_MASK8(_field)) - #define EFX_OWORD_IS_EQUAL64(_oword_a, _oword_b) \ ((_oword_a).eo_u64[0] == (_oword_b).eo_u64[0] && \ (_oword_a).eo_u64[1] == (_oword_b).eo_u64[1]) @@ -510,7 +508,6 @@ extern int fix_lint; #define EFX_BYTE_IS_EQUAL(_byte_a, _byte_b) \ ((_byte_a).eb_u8[0] == (_byte_b).eb_u8[0]) - #define EFX_OWORD_IS_ZERO64(_oword) \ (((_oword).eo_u64[0] | \ (_oword).eo_u64[1]) == 0) @@ -537,7 +534,6 @@ extern int fix_lint; #define EFX_BYTE_IS_ZERO(_byte) \ (((_byte).eb_u8[0]) == 0) - #define EFX_OWORD_IS_SET64(_oword) \ (((_oword).eo_u64[0] & \ (_oword).eo_u64[1]) == ~((uint64_t)0)) @@ -1408,7 +1404,6 @@ extern int fix_lint; ((_oword).eo_u32[3] & \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(96))))) - #define EFX_SET_QWORD_BIT64(_qword, _bit) \ do { \ _NOTE(CONSTANTCONDITION) \ @@ -1455,7 +1450,6 @@ extern int fix_lint; ((_qword).eq_u32[1] & \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(32))))) - #define EFX_SET_DWORD_BIT(_dword, _bit) \ do { \ (_dword).ed_u32[0] |= \ @@ -1474,7 +1468,6 @@ extern int fix_lint; (((_dword).ed_u32[0] & \ __CPU_TO_LE_32(EFX_SHIFT32(_bit, FIX_LINT(0)))) != 0) - #define EFX_SET_WORD_BIT(_word, _bit) \ do { \ (_word).ew_u16[0] |= \ @@ -1493,7 +1486,6 @@ extern int fix_lint; (((_word).ew_u16[0] & \ __CPU_TO_LE_16(EFX_SHIFT16(_bit, FIX_LINT(0)))) != 0) - #define EFX_SET_BYTE_BIT(_byte, _bit) \ do { \ (_byte).eb_u8[0] |= \ @@ -1512,7 +1504,6 @@ extern int fix_lint; (((_byte).eb_u8[0] & \ __NATIVE_8(EFX_SHIFT8(_bit, FIX_LINT(0)))) != 0) - #define EFX_OR_OWORD64(_oword1, _oword2) \ do { \ (_oword1).eo_u64[0] |= (_oword2).eo_u64[0]; \ diff --git a/sys/dev/sfxge/common/hunt_impl.h b/sys/dev/sfxge/common/hunt_impl.h index 06904c66fbf8..7072907d4290 100644 --- a/sys/dev/sfxge/common/hunt_impl.h +++ b/sys/dev/sfxge/common/hunt_impl.h @@ -62,7 +62,6 @@ extern "C" { #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32) - /* NIC */ extern __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/hunt_nic.c b/sys/dev/sfxge/common/hunt_nic.c index f3594710d550..82c31dd0b419 100644 --- a/sys/dev/sfxge/common/hunt_nic.c +++ b/sys/dev/sfxge/common/hunt_nic.c @@ -251,5 +251,4 @@ fail1: return (rc); } - #endif /* EFSYS_OPT_HUNTINGTON */ diff --git a/sys/dev/sfxge/common/mcdi_mon.c b/sys/dev/sfxge/common/mcdi_mon.c index 835ea210983a..adc7e0842701 100644 --- a/sys/dev/sfxge/common/mcdi_mon.c +++ b/sys/dev/sfxge/common/mcdi_mon.c @@ -210,7 +210,6 @@ fail1: return (rc); } - static __checkReturn efx_rc_t efx_mcdi_read_sensors( __in efx_nic_t *enp, @@ -408,7 +407,6 @@ efx_mcdi_sensor_info_page( /* Copy an entry for all but the highest bit set. */ while (mask_copy) { - if (mask_copy == (1U << MC_CMD_SENSOR_PAGE0_NEXT)) { /* Only next page bit set. */ mask_copy = 0; @@ -656,7 +654,6 @@ mcdi_mon_cfg_free( } } - #endif /* EFSYS_OPT_MON_STATS */ #endif /* EFSYS_OPT_MON_MCDI */ diff --git a/sys/dev/sfxge/common/mcdi_mon.h b/sys/dev/sfxge/common/mcdi_mon.h index 317ec92f035a..06d44956ef38 100644 --- a/sys/dev/sfxge/common/mcdi_mon.h +++ b/sys/dev/sfxge/common/mcdi_mon.h @@ -51,7 +51,6 @@ mcdi_mon_cfg_build( mcdi_mon_cfg_free( __in efx_nic_t *enp); - extern __checkReturn efx_rc_t mcdi_mon_ev( __in efx_nic_t *enp, diff --git a/sys/dev/sfxge/common/medford2_impl.h b/sys/dev/sfxge/common/medford2_impl.h index b7cd84096781..5d19c6bd8bf5 100644 --- a/sys/dev/sfxge/common/medford2_impl.h +++ b/sys/dev/sfxge/common/medford2_impl.h @@ -39,23 +39,19 @@ extern "C" { #endif - #ifndef ER_EZ_TX_PIOBUF_SIZE #define ER_EZ_TX_PIOBUF_SIZE 4096 #endif - #define MEDFORD2_PIOBUF_NBUFS (16) #define MEDFORD2_PIOBUF_SIZE (ER_EZ_TX_PIOBUF_SIZE) #define MEDFORD2_MIN_PIO_ALLOC_SIZE (MEDFORD2_PIOBUF_SIZE / 32) - extern __checkReturn efx_rc_t medford2_board_cfg( __in efx_nic_t *enp); - #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/medford2_nic.c b/sys/dev/sfxge/common/medford2_nic.c index 46f8c265a824..e25cbb7ff0e3 100644 --- a/sys/dev/sfxge/common/medford2_nic.c +++ b/sys/dev/sfxge/common/medford2_nic.c @@ -36,7 +36,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_MEDFORD2 static __checkReturn efx_rc_t @@ -89,7 +88,6 @@ medford2_board_cfg( * See efx_mcdi_request_errcode() for MCDI error translations. */ - if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* * Interrupt testing does not work for VFs on Medford2. diff --git a/sys/dev/sfxge/common/medford_impl.h b/sys/dev/sfxge/common/medford_impl.h index 69b8ff4c9940..711fa1776678 100644 --- a/sys/dev/sfxge/common/medford_impl.h +++ b/sys/dev/sfxge/common/medford_impl.h @@ -37,23 +37,19 @@ extern "C" { #endif - #ifndef ER_EZ_TX_PIOBUF_SIZE #define ER_EZ_TX_PIOBUF_SIZE 4096 #endif - #define MEDFORD_PIOBUF_NBUFS (16) #define MEDFORD_PIOBUF_SIZE (ER_EZ_TX_PIOBUF_SIZE) #define MEDFORD_MIN_PIO_ALLOC_SIZE (MEDFORD_PIOBUF_SIZE / 32) - extern __checkReturn efx_rc_t medford_board_cfg( __in efx_nic_t *enp); - #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/medford_nic.c b/sys/dev/sfxge/common/medford_nic.c index 9f9738f90a74..9fa3e0ff8eda 100644 --- a/sys/dev/sfxge/common/medford_nic.c +++ b/sys/dev/sfxge/common/medford_nic.c @@ -34,7 +34,6 @@ __FBSDID("$FreeBSD$"); #include "efx.h" #include "efx_impl.h" - #if EFSYS_OPT_MEDFORD static __checkReturn efx_rc_t @@ -85,7 +84,6 @@ medford_board_cfg( * See efx_mcdi_request_errcode() for MCDI error translations. */ - if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* * Interrupt testing does not work for VFs. See bug50084 and diff --git a/sys/dev/sfxge/common/siena_flash.h b/sys/dev/sfxge/common/siena_flash.h index 20db866fa339..2f800bf9d65b 100644 --- a/sys/dev/sfxge/common/siena_flash.h +++ b/sys/dev/sfxge/common/siena_flash.h @@ -55,7 +55,6 @@ #define SIENA_MC_BOOT_MAGIC (0x51E4A001) #define SIENA_MC_BOOT_VERSION (1) - /*Structures supporting an arbitrary number of binary blobs in the flash image intended to house code and tables for the satellite cpus*/ /*thanks to random.org for:*/ diff --git a/sys/dev/sfxge/common/siena_impl.h b/sys/dev/sfxge/common/siena_impl.h index 672f0d86b268..85fa4298d15a 100644 --- a/sys/dev/sfxge/common/siena_impl.h +++ b/sys/dev/sfxge/common/siena_impl.h @@ -54,7 +54,6 @@ extern "C" { #define SIENA_NVRAM_CHUNK 0x80 - extern __checkReturn efx_rc_t siena_nic_probe( __in efx_nic_t *enp); diff --git a/sys/dev/sfxge/common/siena_mcdi.c b/sys/dev/sfxge/common/siena_mcdi.c index 2cfed5d5fd4a..129549dce987 100644 --- a/sys/dev/sfxge/common/siena_mcdi.c +++ b/sys/dev/sfxge/common/siena_mcdi.c @@ -51,7 +51,6 @@ __FBSDID("$FreeBSD$"); ? MC_SMEM_P0_STATUS_OFST >> 2 \ : MC_SMEM_P1_STATUS_OFST >> 2) - void siena_mcdi_send_request( __in efx_nic_t *enp, @@ -265,5 +264,4 @@ siena_mcdi_get_timeout( *timeoutp = SIENA_MCDI_CMD_TIMEOUT_US; } - #endif /* EFSYS_OPT_SIENA && EFSYS_OPT_MCDI */ diff --git a/sys/dev/sfxge/common/siena_nic.c b/sys/dev/sfxge/common/siena_nic.c index e9a9143a3a17..01251fdf7800 100644 --- a/sys/dev/sfxge/common/siena_nic.c +++ b/sys/dev/sfxge/common/siena_nic.c @@ -749,7 +749,6 @@ fail1: return (rc); } - __checkReturn efx_rc_t siena_nic_register_test( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/siena_nvram.c b/sys/dev/sfxge/common/siena_nvram.c index a886d01883fd..c3fcd054150b 100644 --- a/sys/dev/sfxge/common/siena_nvram.c +++ b/sys/dev/sfxge/common/siena_nvram.c @@ -261,7 +261,6 @@ siena_nvram_type_to_partn( return (ENOTSUP); } - #if EFSYS_OPT_DIAG __checkReturn efx_rc_t @@ -299,7 +298,6 @@ fail1: #endif /* EFSYS_OPT_DIAG */ - #define SIENA_DYNAMIC_CFG_SIZE(_nitems) \ (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \ sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0]))) diff --git a/sys/dev/sfxge/sfxge.c b/sys/dev/sfxge/sfxge.c index b9ee63569d99..866f940a7b29 100644 --- a/sys/dev/sfxge/sfxge.c +++ b/sys/dev/sfxge/sfxge.c @@ -85,7 +85,6 @@ __FBSDID("$FreeBSD$"); MALLOC_DEFINE(M_SFXGE, "sfxge", "Solarflare 10GigE driver"); - SYSCTL_NODE(_hw, OID_AUTO, sfxge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "SFXGE driver parameters"); @@ -325,7 +324,6 @@ sfxge_stop(struct sfxge_softc *sc) sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING; } - static int sfxge_vpd_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc) { @@ -385,7 +383,6 @@ sfxge_private_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ioc) } } - static int sfxge_if_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data) { diff --git a/sys/dev/sfxge/sfxge.h b/sys/dev/sfxge/sfxge.h index 1ffac1458dc3..07e7ede97309 100644 --- a/sys/dev/sfxge/sfxge.h +++ b/sys/dev/sfxge/sfxge.h @@ -110,7 +110,6 @@ #define SFXGE_ETHERTYPE_LOOPBACK 0x9000 /* Xerox loopback */ - #define SFXGE_MAGIC_RESERVED 0x8000 #define SFXGE_MAGIC_DMAQ_LABEL_WIDTH 6 diff --git a/sys/dev/sfxge/sfxge_ev.c b/sys/dev/sfxge/sfxge_ev.c index bcc18fb31d64..9356e01efeff 100644 --- a/sys/dev/sfxge/sfxge_ev.c +++ b/sys/dev/sfxge/sfxge_ev.c @@ -675,7 +675,6 @@ static const efx_ev_callbacks_t sfxge_ev_callbacks = { .eec_link_change = sfxge_ev_link_change, }; - int sfxge_ev_qpoll(struct sfxge_evq *evq) { diff --git a/sys/dev/sfxge/sfxge_intr.c b/sys/dev/sfxge/sfxge_intr.c index ebd772ccb692..5f6b1bbcc94b 100644 --- a/sys/dev/sfxge/sfxge_intr.c +++ b/sys/dev/sfxge/sfxge_intr.c @@ -204,7 +204,6 @@ sfxge_intr_bus_enable(struct sfxge_softc *sc) #else bus_bind_intr(sc->dev, table[index].eih_res, index); #endif - } return (0); diff --git a/sys/dev/sfxge/sfxge_mcdi.c b/sys/dev/sfxge/sfxge_mcdi.c index 025bed0d73de..00aaa73027a8 100644 --- a/sys/dev/sfxge/sfxge_mcdi.c +++ b/sys/dev/sfxge/sfxge_mcdi.c @@ -280,7 +280,6 @@ sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) * Both ports will see ->emt_exception callbacks on the next MCDI poll */ if (ip->u.mcdi.cmd == MC_CMD_REBOOT) { - EFSYS_PROBE(mcdi_ioctl_mc_reboot); /* sfxge_t->s_state_lock held */ (void) sfxge_schedule_reset(sc); @@ -299,7 +298,6 @@ fail1: return (rc); } - int sfxge_mcdi_init(struct sfxge_softc *sc) { diff --git a/sys/dev/sfxge/sfxge_nvram.c b/sys/dev/sfxge/sfxge_nvram.c index d9bbc68570b5..7298cf0b2dfc 100644 --- a/sys/dev/sfxge/sfxge_nvram.c +++ b/sys/dev/sfxge/sfxge_nvram.c @@ -30,7 +30,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - #include <sys/types.h> #include <sys/malloc.h> @@ -109,7 +108,6 @@ fail1: return (rc); } - static int sfxge_nvram_erase(struct sfxge_softc *sc, efx_nvram_type_t type) { diff --git a/sys/dev/sfxge/sfxge_rx.c b/sys/dev/sfxge/sfxge_rx.c index c1fd93728594..111e1ee5b880 100644 --- a/sys/dev/sfxge/sfxge_rx.c +++ b/sys/dev/sfxge/sfxge_rx.c @@ -65,7 +65,6 @@ __FBSDID("$FreeBSD$"); #include "common/efx.h" - #include "sfxge.h" #include "sfxge_rx.h" diff --git a/sys/dev/sfxge/sfxge_tx.c b/sys/dev/sfxge/sfxge_tx.c index bdf698881301..663b4e99270f 100644 --- a/sys/dev/sfxge/sfxge_tx.c +++ b/sys/dev/sfxge/sfxge_tx.c @@ -92,7 +92,6 @@ __FBSDID("$FreeBSD$"); #include "sfxge.h" #include "sfxge_tx.h" - #define SFXGE_PARAM_TX_DPL_GET_MAX SFXGE_PARAM(tx_dpl_get_max) static int sfxge_tx_dpl_get_max = SFXGE_TX_DPL_GET_PKT_LIMIT_DEFAULT; TUNABLE_INT(SFXGE_PARAM_TX_DPL_GET_MAX, &sfxge_tx_dpl_get_max); @@ -123,7 +122,6 @@ SYSCTL_INT(_hw_sfxge, OID_AUTO, tso_fw_assisted, CTLFLAG_RDTUN, &sfxge_tso_fw_assisted, 0, "Bitmask of FW-assisted TSO allowed to use if supported by NIC firmware"); - static const struct { const char *name; size_t offset; @@ -143,7 +141,6 @@ static const struct { SFXGE_TX_STAT(tx_netdown_drops, netdown_drops), }; - /* Forward declarations. */ static void sfxge_tx_qdpl_service(struct sfxge_txq *txq); static void sfxge_tx_qlist_post(struct sfxge_txq *txq); @@ -802,7 +799,6 @@ sfxge_if_qflush(struct ifnet *ifp) * The fields are 8-bit, but it's ok, no header may be longer than 255 bytes. */ - #define TSO_MBUF_PROTO(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[0]) /* We abuse l5hlen here because PH_loc can hold only 64 bits of data */ #define TSO_MBUF_FLAGS(_mbuf) ((_mbuf)->m_pkthdr.l5hlen) @@ -991,7 +987,6 @@ static const struct tcphdr *tso_tcph(const struct sfxge_tso_state *tso) } #endif - /* Size of preallocated TSO header buffers. Larger blocks must be * allocated from the heap. */ @@ -1092,14 +1087,12 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, } #endif - if (tso->fw_assisted && __predict_false(tso->tcph_off > encp->enc_tx_tso_tcp_header_offset_limit)) { tso->fw_assisted = 0; } - #if !SFXGE_TX_PARSE_EARLY KASSERT(mbuf->m_len >= tso->tcph_off, ("network header is fragmented in mbuf")); @@ -2007,7 +2000,6 @@ sfxge_tx_fini(struct sfxge_softc *sc) sc->txq_count = 0; } - int sfxge_tx_init(struct sfxge_softc *sc) { diff --git a/sys/dev/sfxge/sfxge_tx.h b/sys/dev/sfxge/sfxge_tx.h index bb1d94aeb6e5..4446eb51a238 100644 --- a/sys/dev/sfxge/sfxge_tx.h +++ b/sys/dev/sfxge/sfxge_tx.h @@ -121,7 +121,6 @@ struct sfxge_tx_dpl { * high watermark */ }; - #define SFXGE_TX_BUFFER_SIZE 0x400 #define SFXGE_TX_HEADER_SIZE 0x100 #define SFXGE_TX_COPY_THRESHOLD 0x200 @@ -170,7 +169,6 @@ enum sfxge_txq_type { #define SFXGE_TXQ_LOCK_ASSERT_NOTOWNED(_txq) \ mtx_assert(&(_txq)->lock, MA_NOTOWNED) - struct sfxge_txq { /* The following fields should be written very rarely */ struct sfxge_softc *sc; |