810 files changed, 88884 insertions, 59472 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1723944a36e8..704e6f90d4fe 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,758 +1,1294 @@
-2006-07-19  Mat Hostetter  <mat@lcs.mit.edu>
+2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* symbols.c (report_op_error): Fix pasto.  Don't use as_bad_where
-	when file and line unknown.
+	* config/tc-m68k.c (m68k_ip): Add j & K operand types.
+	(install_operand): Add E encoding.
+	(md_begin): Check and skip initial '.' arg character.
+	(get_num): Add 0..511 case.
 
-2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
+2007-07-03  Alan Modra  <amodra@bigpond.net.au>
 
-	* po/Make-in (pdf, ps): New dummy targets.
+	PR 4713
+	* config/obj-elf.c (elf_ecoff_set_ext): Make static when OBJ_MAYBE_ELF.
+	* config/obj-elf.h (obj_ecoff_set_ext): Comment.
 
-2006-06-02  Joseph S. Myers  <joseph@codesourcery.com>
+2007-07-03  Mikkel Lauritsen  <renard@nospam.dk>
 
-	* doc/Makefile.am (TEXI2DVI): Define.
+	PR 4722
+	* app.c (do_scrub_chars <state 5>): Check for output buffer full
+	after memcpy.
+
+2007-07-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-mips.c (s_dtprelword, s_dtpreldword,
+	s_dtprel_internal): New.
+	(mips_pseudo_table): Add .dtprelword and .dtpreldword.
+	(md_apply_fix): Handle BFD_RELOC_MIPS_TLS_DTPREL32 and
+	BFD_RELOC_MIPS_TLS_DTPREL64.
+
+2007-07-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* config.in: Regenerate.
 	* doc/Makefile.in: Regenerate.
-	* doc/c-arc.texi: Fix typo.
+	* po/POTFILES.in: Regenerate.
+	* po/gas.pot: Regenerate.
 
-2006-05-30  Nick Clifton  <nickc@redhat.com>
+2007-07-02  Alan Modra  <amodra@bigpond.net.au>
 
-	* po/es.po: Updated Spanish translation.
+	* config/tc-ppc.c (ppc_pe_section): Comment out code assigning
+	coff section flag values to bfd section flag.
 
-2006-05-25  Nathan Sidwell  <nathan@codesourcery.com>
+2007-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
-	cfloat/m68881 to correct architecture before using it.
+	* aclocal.m4: Regenerated.
+	* doc/Makefile.in: Likewise.
+	* Makefile.in: Likewise.
 
-2006-05-16  Nick Clifton  <nickc@redhat.com>
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
 
-	* Import these patches from the mainline:
+	* as.c (main): Only call create_obj_attrs_section if IS_ELF.
 
-	2006-05-16  Bjoern Haase  <bjoern.m.haase@web.de>
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
 
-        * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
-	constant values.
+	* as.c (create_obj_attrs_section): New.
+	(main): Call create_obj_attrs_section for ELF.
+	* read.c (s_gnu_attribute, skip_whitespace, skip_past_char,
+	skip_past_comma, s_vendor_attribute): New.
+	(potable): Add gnu_attribute for ELF.
+	* read.h (s_vendor_attribute): Declare.
+	* config/tc-arm.c (s_arm_eabi_attribute): Replace by wrapper
+	round s_vendor_attribute.
+	(aeabi_set_public_attributes): Update for new attributes
+	interfaces.
+	(arm_md_end): Remove attributes contents setting now done
+	generically.
 
-	2006-05-05  Bjoern Haase  <bjoern.m.haase@web.de>
+2007-06-29  M R Swami Reddy  <MR.Swami.Redd@nsc.com>
 
-	* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define.  Disable fixups
-	for PMEM related expressions.
+	* Makefile.am: Add CR16 related entry.
+	* Makefile.in: Regenerate.
+	* config/tc-cr16.h: New file
+	* config/tc-cr16.c: New file
+	* doc/c-cr16.texi: New file for cr16 
+	* doc/all.texi: Entry for cr16 
+	* doc/Makefile.am: Added c-cr16.texi
+	* doc/Makefile.in: Regenerate 
+	* doc/as.texinfo: Entry for CR16 target
+	* NEWS: Announce the support for the new target.
 
-2006-05-11  Thiemo Seufer  <ths@mips.com>
+2007-06-26  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-mips.c (append_insn): Don't check the range of j or
-	jal addresses.
+	* config/tc-arm.c (parse_operands): Accept generic coprocessor regs
+	for OP_RVC.
+	(reg_names): Add fpinst, pfinst2, mvfr0 and mvfr1.
 
-2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+2007-06-25  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
-	of list rather than beginning.
+	* config/tc-i386.c (process_operands): Replace regKludge
+	with RegKludge.
 
-2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 
-	* write.c (relax_segment): Add pass count arg.  Don't error on
-	negative org/space on first two passes.
-	(relax_seg_info): New struct.
-	(relax_seg, write_object_file): Adjust.
-	* write.h (relax_segment): Update prototype.
+	* config/tc-mips.h (TC_SYMFIELD_TYPE): New.
+	* config/tc-mips.c (append_insn): Record which symbols have
+	R_MIPS16_26 relocations against them.
+	(mips_fix_adjustable): Don't reduce relocations against such symbols.
 
-2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+2007-06-22  Sterling Augustine  <sterling@tensilica.com>
 
-	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
-	here.
-	(md_apply_fix3): Multiply offset by 4 here for
-	BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+	* config/tc-xtensa.c (xg_assembly_relax): Comment termination rules.
+	(frag_format_size): Handle RELAX_IMMED_STEP3.
+	(xtensa_relax_frag, md_convert_frag): Likewise.
+	* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_IMMED_STEP3.
+	(RELAX_IMMED_MAXSTEPS): Adjust.
+	* config/xtensa-relax.c (widen_spec_list): Add transitions from
+	wide branches to branch-over-jumps.
+	(build_transition): Handle wide branches in transition patterns.
+	
+2007-06-22  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+	* config/tc-i386.c (disp_size): New.
+	(imm_size): Likewise.
+	(output_disp): Use disp_size and imm_size.
+	(output_imm): Use imm_size.
 
-	* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
-	(TEXI2POD): Use AM_MAKEINFOFLAGS.
-	(asconfig.texi): Don't set top_srcdir.
-	* doc/as.texinfo: Don't use top_srcdir.
-	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+2007-06-19  Sterling Augustine  <sterling@tensilica.com>
 
-2006-05-02  Paul Brook  <paul@codesourcery.com>
+	* config/tc-xtensa.h (struct xtensa_frag_type): Update comment about
+	use of literal_frag field.
+	* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Record frag
+	in the literal_frag field.
+	(xtensa_move_literals): Use it here instead of searching.  Update
+	literal_frag field with new value.
 
-	* config/tc-arm.c (arm_optimize_expr): New function.
-	* config/tc-arm.h (md_optimize_expr): Define
-	(arm_optimize_expr): Add prototype.
-	(TC_FORCE_RELOCATION_SUB_SAME): Define.
+2007-06-14  Paul Brook  <paul@codesourcery.com>
 
-2006-05-01  James Lemke  <jwlemke@wasabisystems.com>
+	* config/tc-arm.c (do_t_mov_cmp): Handle shift by register and
+	narrow shift by immediate.
 
-	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+2007-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* Makefile.am (ACLOCAL_AMFLAGS): Add -I ../config -I ../bfd.
 
-	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
-	syntax instead of hardcoded opcodes with ".w18" suffixes.
-	(wide_branch_opcode): New.
-	(build_transition): Use it to check for wide branch opcodes with
-	either ".w18" or ".w15" suffixes.
+	* acinclude.m4: Don't include m4 files.
+	(BFD_BINARY_FOPEN): Removed.
+	Remove libtool kludge.
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* Makefile.in: Regenerated.
+	* doc/Makefile.in: Likewise.
+	* aclocal.m4: Likewise.
+	* configure: Likewise.
 
-	* config/tc-xtensa.c (xtensa_create_literal_symbol,
-	xg_assemble_literal, xg_assemble_literal_space): Do not set the
-	frag's is_literal flag.
+2007-06-11  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+	
+	* config/tc-xtensa.c (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to...
+	(XTENSA_PROP_NO_TRANSFORM): ...this.
+	(frag_flags_struct): Move is_no_transform out of the insn sub-struct.
+	(xtensa_mark_frags_for_org): New.
+	(xtensa_handle_align): Set RELAX_ORG frag subtype for rs_org.
+	(xtensa_post_relax_hook): Call xtensa_mark_frags_for_org.
+	(get_frag_property_flags): Adjust reference to is_no_transform flag.
+	(xtensa_frag_flags_combinable): Likewise.
+	(frag_flags_to_number): Likewise.  Use XTENSA_PROP_NO_TRANSFORM.
+	* config/tc-xtensa.h (xtensa_relax_statesE): Add RELAX_ORG.
+	
+2007-06-06  Paul Brook  <paul@codesourcery.com>
 
-2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+	* config/tc-arm.c (s_align): Pad code sections appropriately.
 
-	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+2007-06-05  Paul Brook  <paul@codesourcery.com>
 
-2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
+	* config/tc-arm.c (insns): Correct Thumb-2 ldrd/strd opcodes.
 
-	* po/POTFILES.in: Regenerated.
+2007-06-05  Nick Clifton  <nickc@redhat.com>
 
-2006-04-14  Sterling Augustine  <sterling@tensilica.com>
+	PR gas/4587
+	* config/tc-sparc.c (sparc_ip): Terminate tls_ops array.
 
-	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
-	instructions when such transformations have been disabled.
+2007-06-05  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-10  Sterling Augustine  <sterling@tensilica.com>
+	* config/tc-spu.c (spu_cons): Use deferred_expression.  Handle
+	number@ppu.
+	(tc_gen_reloc): Abort if neither addsy or subsy is set.
+	(md_apply_fix): Don't attempt to resolve SPU_PPU relocs.
+	* config/tc-spu.h (md_operand): Handle @ppu without sym.
 
-	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
-	symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
-	(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
-	decoding the loop instructions.  Remove current_offset variable.
-	(xtensa_fix_short_loop_frags): Likewise.
-	(min_bytes_to_other_loop_end): Remove current_offset argument.
+2007-05-31  Paul Brook  <paul@codesourcery.com>
 
-2006-04-09  Arnold Metselaar  <arnold.metselaar@planet.nl>
+	* config/tc-arm.c (insns): Allow strex on M profile cores.
 
-	* config/tc-z80.c (z80_optimize_expr): Removed; redundant since 2006-04-04.
-	* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
+2007-05-29  David S. Miller  <davem@davemloft.net>
+	    Jakub Jelinek  <jakub@redhat.com>
 
-2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+	PR gas/4558
+	* config/tc-sparc.c (md_apply_fix): Fix relocation overflow checks
+	for BFD_RELOC_SPARC_WDISP16 and BFD_RELOC_SPARC_WDISP19.
 
-	* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
-	attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
-	attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
-	atmega644, atmega329, atmega3290, atmega649, atmega6490,
-	atmega406, atmega640, atmega1280, atmega1281, at90can32,
-	at90can64, at90usb646, at90usb647, at90usb1286 and
-	at90usb1287.
-	Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* config/tc-spu.h: Wrap in #ifndef/#endif.  Delete coff macros.
 
-	* config/tc-arm.c (parse_operands): Set default error message.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* config/tc-ppc.c: Convert to ISO C.
+	* config/tc-ppc.c: Likewise.
 
-	* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
+2007-05-29  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* write.h (EXEC_MACHINE_TYPE): Delete.
+	(string_byte_count, section_alignment): Delete.
 
-	* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
+2007-05-28  Nathan Sidwell  <nathan@codesourcery.com>
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+	* app.c (do_scrub_chars): Cope with \ at end of buffer.
 
-	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
-	(move_or_literal_pool): Handle Thumb-2 instructions.
-	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
+2007-05-26  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-07  Alan Modra  <amodra@bigpond.net.au>
+	* config/tc-ppc.c (ppc_insert_operand): Truncate sign bits in
+	top 32 bits of 64 bit value if so doing results in passing
+	range check.  Rewrite sign extension fudges similarly.  Enable
+	fudges for powerpc64 too.  Report user value if range check
+	fails rather than fudged value.  Negate PPC_OPERAND_NEGATIVE
+	range rather than value, also to report user value on failure.
 
-	PR 2512.
-	* config/tc-i386.c (match_template): Move 64-bit operand tests
-	inside loop.
+2007-03-25  Paul Brook  <paul@codesourcery.com>
 
-2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
+	* config/tc-arm.c (T2_SUBS_PC_LR): Define.
+	(do_t_add_sub): Correctly encode subs pc, lr, #const.
+	(do_t_mov_cmp): Correctly encode movs pc, lr.
 
-	* po/Make-in: Add install-html target.
-	* Makefile.am: Add install-html and install-html-recursive targets.
-	* Makefile.in: Regenerate.
-	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
+2007-05-24  Steve Ellcey  <sje@cup.hp.com>
+
+	* Makefile.in: Regnerate.
 	* configure: Regenerate.
-	* doc/Makefile.am: Add install-html and install-html-am targets.
+	* aclocal.m4: Regenerate.
 	* doc/Makefile.in: Regenerate.
 
-2006-04-06  Alan Modra  <amodra@bigpond.net.au>
+2007-05-22  Bob Wilson  <bob.wilson@acm.org>
+	
+	* doc/c-xtensa.texi (Xtensa Automatic Alignment): Remove statements
+	and index entries about automatic alignment of ENTRY instructions.
+	
+2007-05-22  Nick Clifton  <nickc@redhat.com>
+
+	* doc/as.texinfo: Use @copying around the copyright notice.
+
+2007-05-18  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-mips.c (s_mipsset): Use generic s_set for directives
+	containing a comma.
+
+2007-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/4517
+	2003-06-05  Michal Ludvig  <mludvig@suse.cz>
+	* doc/as.texinfo: Document new directives: .cfi_restore, 
+	.cfi_undefined, .cfi_same_value, .cfi_return_column, 
+	.cfi_remember_state and .cfi_restore_state.
+
+2007-05-17  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (md_apply_fix): Show value of out of range
+	fixups in error message.
+	(md_conver_frag_1): Propagate the fix source location and use
+	as_bad_where rather than fatal, for better error messages.
+
+2007-05-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (v7m_psrs): Add uppercase PSR names and xpsr.
+
+2007-05-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* app.c (do_scrub_chars): Don't damage \@ pseudo-variables.
+
+2007-05-15  Vincent Riviere  <vincent.riviere@freesbee.fr>	
+
+	PR gas/3041
+	* config/tc-m68k.c (relaxable_symbol): Make sure that the correct
+	addend is stored for relocs against weak symbols.
+	(md_apply_fix): So not loose track of addend for relocs against
+	weak symbols.
+
+2007-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_parse_option): Fix parsing of -O option.
+
+2007-05-14  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (data_op2, validate_immediate): Fix bug for
+	addri, addri.c, subi, and subi.c when immediate number is hex.
+	(score_insns): Remove subis and subis.c.
+	(do_sub_rdi16): Delete.
+	
+2007-05-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c (md_pseudo_table): Add int, long, quad.  Call
+	spu_cons for word.
+	(md_assemble): Tidy use of insn.flag.
+	(get_imm): Likewise.  Handle uppercase input too.
+	(spu_cons): New function.
+	* config/tc-spu.h (tc_fix_adjustable): Don't adjust SPU_PPU relocs.
+	(TC_FORCE_RELOCATION): Don't resolve them either.
+
+2007-05-05  Mark Shinwell  <shinwell@codesourcery.com>
+ 
+	* config/tc-arm.c (md_apply_fix): Generate more accurate
+	diagnostic when 8-bit immediate range is exceeded for
+	BFD_RELOC_ARM_OFFSET_IMM8.
+
+2007-05-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/4460
+	* config/tc-i386.c (lex_got): Don't replace the reloc token with
+	a space if we already have a space.
+
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Don't explicitly check
+	suffix for crc32 in Intel mode.
+	(process_suffix): Issue an error for crc32 if the operand size
+	is ambiguous.
+
+2007-05-03  Vincent Riviere  <vincent.riviere@freesbee.fr>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3041
+	* config/tc-m68k.c (relaxable_symbol): Do not relax weak symbols.
+	(tc_gen_reloc): Adjust the addend of relocs against weak symbols.
+	(md_apply_fix): Put zero values into the frags referencing weak
+	symbols.
+
+2007-05-02  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4448
+	* config/tc-ppc.c (ppc_insert_operand): Don't increase min for
+	PPC_OPERAND_PLUS1.
+
+2007-05-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Check suffix for crc32 in
+	Intel mdoe.
+	(process_suffix): Default the suffix of 8bit crc32 to
+	BYTE_MNEM_SUFFIX.
+	(check_byte_reg): Skip check for 8bit crc32.
+
+2007-04-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Use register_prefix in
+	error/warning message.
+	(check_byte_reg): Likewise.
+	(check_long_reg): Likewise.
+	(check_qword_reg): Likewise.
+	(check_word_reg): Likewise.
+	(process_operands): Likewise.
+
+2007-04-30  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4436
+	* config/tc-ppc.c (ppc_insert_operand): Disable range check if
+	min > max.
+
+2007-04-28  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c: Fix comment.
+
+2007-04-26  Anatoly Sokolov <aesok@post.ru>
+
+	* config/tc-avr.c (mcu_types): Add support for atmega8hva and
+	atmega16hva devices. Move at90usb82 device to 'avr5' architecture.
+	* doc/c-avr.texi: Document new devices.
+
+2007-04-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf54455_ctrl): New.
+	(HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New.
+	(m68k_archs): Add isac.
+	(m68k_cpus): Add 54455 family.
+	(m68k_ip): Split Bg into Bb, Bs, Bg.
+	(m68k_elf_final_processing): Add ISA_C.
+	* doc/c-m68k.texi (M680x0 Options): Add isac.
 
-	* frags.c (frag_offset_fixed_p): Reinitialise offset before
-	second scan.
+2007-04-22  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-05  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
+	* read.c (read_a_source_file): Skip multiple spaces to
+	cover hack in mmix md_start_line_hook which overwrites a
+	colon with a space.  Delete sermon and needless assertion.
 
-	* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
-	(GOTT_BASE, GOTT_INDEX): New.
-	(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
-	GOTT_INDEX when generating VxWorks PIC.
-	* configure.tgt (sparc*-*-vxworks*): Remove this special case;
-	use the generic *-*-vxworks* stanza instead.
+2007-04-21  Alan Modra  <amodra@bigpond.net.au>
 
-2006-04-04  Alan Modra  <amodra@bigpond.net.au>
+	* config/atof-vax.c (atof_vax_sizeof): Change return type to unsigned.
+	(md_atof): Make number_of_chars unsigned.  Revert last change.
+	* config/tc-or32.c (md_apply_fix): Delete bogus assertions.
+	* config/tc-sh.c (sh_optimize_expr): Only define for OBJ_ELF.
+	* config/tc-sh.h (md_optimize_expr): Likewise.
+	* config/tc-sh64.c (shmedia_md_pcrel_from_section): Delete bogus
+	assertion.
+	* config/tc-xtensa.c (convert_frag_immed_finish_loop): Likewise.
 
-	PR 997
-	* frags.c (frag_offset_fixed_p): New function.
-	* frags.h (frag_offset_fixed_p): Declare.
-	* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
-	(resolve_expression): Likewise.
+2007-04-21  Nick Clifton  <nickc@redhat.com>
 
-2006-04-03  Sterling Augustine  <sterling@tensilica.com>
+	* config/atof-vax.c (md_atof): Fix comparison inside know().
 
-	* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
-	of the same length but different numbers of slots.
+	* config/tc-ia64.c (emit_one_bundle): Fix typo.
 
-2006-03-30  Andreas Schwab  <schwab@suse.de>
+2007-04-21  Alan Modra  <amodra@bigpond.net.au>
 
-	* configure.in: Fix help string for --enable-targets option.
+	* expr.c (expr): Assert on rankarg, not rank which can be unsigned.
+	* read.c (read_a_source_file): Remove buffer_limit[-1] assertion.
+	Don't skip over NUL char.
+	(pseudo_set): Set X_op for registers to O_register.
+	* symbols.c (symbol_clone): Remove assertion that sym is defined.
+	(resolve_symbol_value): Resolve O_register symbols.
+	* config/tc-i386.c (parse_real_register): Don't use i386_float_regtab.
+	Instead find st(0) by hash lookup.
+	* config/tc-ppc.c (ppc_macro): Warning fix.
+
+	* as.h (ENABLE_CHECKING): Default define to 0.
+	(know): Assert if ENABLE_CHECKING.
+	(struct relax_type): Remove superfluous declaration.
+	* configure.in (--enable-checking): New.
 	* configure: Regenerate.
+	* config.in: Regenerate.
+	* config/tc-ppc.c (ppc_setup_opcodes): Do checks when ENABLE_CHECKING.
+	Check for duplicate powerpc_operands entries.
+
+2007-04-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5253_ctrl): New.
+	(mcf52223_ctrl): New.
+	(m68k_cpus): Add 5253, 52221, 52223.
+
+	* config/m68k-parse.h (RAMBAR_ALT): New.
+	* config/tc-m68k.c (mcf5206_ctrl, mcf5307_ctrl): New.
+	(mcf_ctrl, mcf5208_ctrl, mcf5210a_ctrl, mcf5213_ctrl, mcf52235_ctrl,
+	mcf5225_ctrl, mcf5235_ctrl, mcf5271_ctrl, mcf5275_ctrl,
+	mcf5282_ctrl, mcf5329_ctrl, mcf5373_ctrl, mcfv4e_ctrl,
+	mcf5475_ctrl, mcf5485_ctrl): Add RAMBAR synonym for
+	RAMBAR1.
+	(mcf5272_ctrl): Add RAMBAR0, replace add RAMBAR with RAMBAR_ALT.
+	(m68k_cpus): Adjust 5206, 5206e & 5307 entries.
+	(m68k_ip) <Case J>: Detect when RAMBAR_ALT should be used.  Add it
+	to control register mapping.
+
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* messages.c (as_internal_value_out_of_range): Fix typo in
+	error message.  Return after printing domain error.
+	* config/tc-ppc.c (ppc_insert_operand): Preserve low zero bits
+	in max when shifting right.
+
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 
-2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
-	(m68k_ip): ... here.  Use for all chips.  Protect against buffer
-	overrun and avoid excessive copying.
-
-	* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
-	m68020_control_regs, m68040_control_regs, m68060_control_regs,
-	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
-	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
-	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
-	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
-	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl, 
-	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
-	mcf5282_ctrl, mcfv4e_ctrl): ... these.
-	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
-	(struct m68k_cpu): Change chip field to control_regs.
-	(current_chip): Remove.
-	(control_regs): New.
-	(m68k_archs, m68k_extensions): Adjust.
-	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
-	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
-	(find_cf_chip): Reimplement for new organization of cpu table.
-	(select_control_regs): Remove.
-	(mri_chip): Adjust.
-	(struct save_opts): Save control regs, not chip.
-	(s_save, s_restore): Adjust.
-	(m68k_lookup_cpu): Give deprecated warning when necessary.
-	(m68k_init_arch): Adjust.
-	(md_show_usage): Adjust for new cpu table organization.
-
-2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
-
-	* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
-	* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
-	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
-	"elf/bfin.h".
-	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
-	(any_gotrel): New rule.
-	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
-	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
-	"elf/bfin.h".
-	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
-	(bfin_pic_ptr): New function.
-	(md_pseudo_table): Add it for ".picptr".
-	(OPTION_FDPIC): New macro.
-	(md_longopts): Add -mfdpic.
-	(md_parse_option): Handle it.
-	(md_begin): Set BFD flags.
-	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
-	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
-	us for GOT relocs.
-	* Makefile.am (bfin-parse.o): Update dependencies.
-	(DEPTC_bfin_elf): Likewise.
+	* messages.c (as_internal_value_out_of_range): Extend to report
+	errors for values with invalid low bits set.
+	* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
+	fields.  Check that operands and opcode fields are disjoint.
+	(ppc_insert_operand): Check operands using mask rather than bit
+	count.   Check low bits too.  Handle PPC_OPERAND_PLUS1.  Adjust
+	insertion code.
+	(md_apply_fix): Adjust for struct powerpc_operand change.
+
+2007-04-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_assemble): Only allow 16-bit instructions on
+	Thumb-1.  Add sanity check for bogus relaxations.
+
+2007-04-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Allow rsb and rsbs on Thumb-1.
+
+2007-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
 	* Makefile.in: Regenerate.
 
-2006-03-25  Richard Sandiford  <richard@codesourcery.com>
+2007-04-19  Nathan Froyd <froydnj@codesourcery.com>
 
-	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
-	mcfemac instead of mcfmac.
+	* doc/c-ppc.texi (PowerPC-Opts): Document -me500, -me500x2, -mspe.
 
-2006-03-22  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
-	    Phil Edwards  <phil@codesourcery.com>
-	    Zack Weinberg  <zack@codesourcery.com>
-	    Mark Mitchell  <mark@codesourcery.com>
-	    Nathan Sidwell  <nathan@codesourcery.com>
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* doc/c-i386.texi; Document .ssse3, .sse4.1, .sse4.2 and .sse4.
+
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .sse4.2 and .sse4.
+	(match_template): Handle operand size for crc32 in SSE4.2.
+	(process_suffix): Handle operand type for crc32 in SSE4.2.
+	(output_insn): Support SSE4.2.
+
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add .sse4.1.
+	(process_operands): Adjust implicit operand for blendvpd,
+	blendvps and pblendvb in SSE4.1.
+	(output_insn): Support SSE4.1.
+
+2007-04-18  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_t_rsb): Use 16-bit encoding when possible.
+
+2007-04-16  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c (sh_handle_align):  Call as_bad_where instead
+	of as_warn_where for misaligned data.
+
+2007-04-15  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c (align_test_frag_offset_fixed_p): Handle
+	rs_fill frags.
+
+2007-04-14  Steve Ellcey  <sje@cup.hp.com>
+
+	* Makefile.am: Add ACLOCAL_AMFLAGS.
+	* Makefile.in: Regenerate.
 
-	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
-	(md_begin): Complain about -G being used for PIC.  Don't change
-	the text, data and bss alignments on VxWorks.
-	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
-	generating VxWorks PIC.
-	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
-	(macro): Likewise, but do not treat la $25 specially for
-	VxWorks PIC, and do not handle jal.
-	(OPTION_MVXWORKS_PIC): New macro.
-	(md_longopts): Add -mvxworks-pic.
-	(md_parse_option): Don't complain about using PIC and -G together here.
-	Handle OPTION_MVXWORKS_PIC.
-	(md_estimate_size_before_relax): Always use the first relaxation
-	sequence on VxWorks.
-	* config/tc-mips.h (VXWORKS_PIC): New.
+2007-04-14  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 
-2006-03-21  Paul Brook  <paul@codesourcery.com>
+	* config/tc-sh.c (align_test_frag_offset_fixed_p): New.
+	(sh_optimize_expr): Likewise.
+	* config/tc-sh.h (md_optimize_expr): Define.
+	(sh_optimize_expr): Prototype.
 
-	* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
+2007-04-06  Matt Thomas  <matt@netbsd.org>
 
-2006-03-21  Sterling Augustine  <sterling@tensilica.com>
+	* config/tc-vax.c (vax_cons): Added to support %pcrel{8,16,32}(exp)
+	to emit pcrel relocations by DWARF2 in non-code sections.  Borrowed
+	heavily from tc-sparc.c.  (vax_cons_fix_new): Likewise.
 
-	* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
-	(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
-	(get_loop_align_size): New.
-	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
-	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
-	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
-	(get_noop_aligned_address): Use get_loop_align_size.
-	(get_aligned_diff): Likewise.
+2007-04-04  Kazu Hirata  <kazu@codesourcery.com>
 
-2006-03-21  Paul Brook  <paul@codesourcery.com>
+	* config/tc-m68k.c (HAVE_LONG_BRANCH): Add fido_a.
 
-	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
+2007-04-04  Paul Brook  <paul@codesourcery.com>
 
-2006-03-20  Paul Brook  <paul@codesourcery.com>
+	* config/tc-arm.c (do_neon_ext): Enforce immediate range.
+	(insns): Use I15 for vext.
 
-	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
-	(do_t_branch): Encode branches inside IT blocks as unconditional.
-	(do_t_cps): New function.
-	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
-	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
-	(opcode_lookup): Allow conditional suffixes on all instructions in
-	Thumb mode.
-	(md_assemble): Advance condexec state before checking for errors.
-	(insns): Use do_t_cps.
+2007-04-04  Paul Brook  <paul@codesourcery.com>
 
-2006-03-20  Paul Brook  <paul@codesourcery.com>
+	* configure.tgt: Loosen checks for arm uclinux eabi targets.
 
-	* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
-	outputting the insn.
+2007-04-02  Sterling Augustine  <sterling@tensilica.com>
 
-2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+	* config/tc-xtensa.c (xtensa_flush_pending_output): Check
+	outputting_stabs_line_debug.
 
-	* config/tc-vax.c: Update copyright year.
-	* config/tc-vax.h: Likewise.
+2007-03-26  Anatoly Sokolov <aesok@post.ru>
 
-2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+	* config/tc-avr.c (mcu_types): Add support for at90pwm1, at90usb82,
+	at90usb162, atmega325p, atmega329p, atmega3250p and atmega3290p
+	devices.
+	* doc/c-avr.texi: Document new devices.
 
-	* config/tc-vax.c (md_chars_to_number): Used only locally, so
-	make it static.
-	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
+2007-04-02  Richard Sandiford  <richard@codesourcery.com>
 
-2006-03-17  Paul Brook  <paul@codesourcery.com>
+	* doc/as.texinfo: Add -mvxworks-pic to the list of MIPS options.
+	* doc/c-mips.texi (-KPIC, -mvxworks-pic): Document.
+	* config/tc-mips.c (md_show_usage): Mention -mvxworks-pic.
 
-	* config/tc-arm.c (insns): Add ldm and stm.
+2007-03-30  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
 
-2006-03-17  Ben Elliston  <bje@au.ibm.com>
+	* config/tc-xtensa.c (xtensa_move_labels): Remove loops_ok argument.
+	Do not check is_loop_target flag.
+	(xtensa_frob_label): Adjust calls to xtensa_move_labels.
+	(xg_assemble_vliw_tokens): Likewise.  Also avoid calling
+	xtensa_move_labels for alignment of loop opcodes.
+	
+2007-03-30  H.J. Lu  <hongjiu.lu@intel.com>
 
-	PR gas/2446
-	* doc/as.texinfo (Ident): Document this directive more thoroughly.
+	* config/tc-i386.c (process_suffix): Reindent a bit.
 
-2006-03-16  Paul Brook  <paul@codesourcery.com>
+2007-03-30  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-arm.c (insns): Add "svc".
+	* config/tc-arm.c (encode_thumb2_ldmstm): New function.
+	(do_t_ldmstm): Generate 16-bit push/pop.  Use encode_thumb2_ldmstm.
+	(do_t_push_pop):  Use encode_thumb2_ldmstm.
 
-2006-03-13  Bob Wilson  <bob.wilson@acm.org>
+2007-03-29  DJ Delorie  <dj@redhat.com>
 
-	* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
-	flag and avoid double underscore prefixes.
+	* config/tc-m32c.c (rl_for, relaxable): Protect argument.
+	(md_relax_table): Add entries for ADJNZ macros.
+	(M32C_Macros): Add ADJNZ macros.
+	(subtype_mappings): Add entries for ADJNZ macros.
+	(insn_to_subtype): Check for adjnz and sbjnz insns.
+	(md_estimate_size_before_relax): Pass insn to insn_to_subtype.
+	(md_convert_frag): Convert adjnz and sbjnz.
 
-2006-03-10  Paul Brook  <paul@codesourcery.com>
+2007-03-29  Nick Clifton  <nickc@redhat.com>
 
-	* config/tc-arm.c (md_begin): Handle EABIv5.
-	(arm_eabis): Add EF_ARM_EABI_VER5.
-	* doc/c-arm.texi: Document -meabi=5.
+	* itbl-ops.c (itbl_entry): Remove unnecessary and excessively long
+	initialization.
+	* itbl-ops.h (enum e_processor): Initialise the e_nprocs field
+	using ITBL_NUMBER_OF_PROCESSORS.
+	* itbl-parse.y (yyerror): Remove use of redundant macro PARAMS.
 
-2006-03-10  Ben Elliston  <bje@au.ibm.com>
+2007-03-28  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* app.c (do_scrub_chars): Simplify string handling.
+	* config/tc-i386.c (build_modrm_byte): For instructions with 2
+	register operands, encode destination in i.rm.regmem if its
+	RegMem bit is set.
 
-2006-03-07  Richard Sandiford  <richard@codesourcery.com>
-	    Daniel Jacobowitz  <dan@codesourcery.com>
-	    Zack Weinberg  <zack@codesourcery.com>
-	    Nathan Sidwell  <nathan@codesourcery.com>
-	    Paul Brook  <paul@codesourcery.com>
-	    Ricardo Anguiano  <anguiano@codesourcery.com>
+2007-03-28  Richard Sandiford  <richard@codesourcery.com>
 	    Phil Edwards  <phil@codesourcery.com>
 
-	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
-	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
-	R_ARM_ABS12 reloc.
-	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
-	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
-	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
-
-2006-03-06  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
-	even when using the text-section-literals option.
-
-2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
-	and cf.
-	(m68k_ip): <case 'J'> Check we have some control regs.
-	(md_parse_option): Allow raw arch switch.
-	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
-	whether 68881 or cfloat was meant by -mfloat.
-	(md_show_usage): Adjust extension display.
-	(m68k_elf_final_processing): Adjust.
-
-2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
-
-	* config/tc-avr.c (avr_mod_hash_value): New function.
-	(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
-	BFD_RELOC_MS8_LDI for hlo8() and hhi8() 
-	(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
-	instead of int avr_ldi_expression: use avr_mod_hash_value instead
-	of (int).
-	(tc_gen_reloc): Handle substractions of symbols, if possible do
-	fixups, abort otherwise.	
-	* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
-	tc_fix_adjustable): Define.
+	* doc/as.texinfo: Put the contents after the title page rather
+	than at the end of the document.
+
+2007-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* NEWS: Mention ".reloc".
+
+2007-03-26  Sterling Augustine  <sterling@tensilica.com>
 	
-2006-03-02  James E Wilson  <wilson@specifix.com>
+	* config/tc-xtensa.c (xg_translate_idioms): Allow assembly idioms
+	in FLIX instructions.
+	
+2007-03-26  Julian Brown  <julian@codesourcery.com>
 
-	* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
-	change the template, then clear md.slot[curr].end_of_insn_group.
+	* config/tc-arm.c (arm_it): Add immisfloat field.
+	(parse_qfloat_immediate): Disallow integer syntax for floating-point
+	immediates. Fix hex immediates, handle 0.0 and -0.0 specially.
+	(parse_neon_mov): Set immisfloat bit for operand if it parsed as a
+	float.
+	(neon_cmode_for_move_imm): Reject non-float immediates for float
+	operands.
+	(neon_move_immediate): Pass immisfloat bit to neon_cmode_for_move_imm.
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+2007-03-26  Julian Brown  <julian@codesourcery.com>
 
-	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
+	* doc/c-arm.texi: Add documentation for .dn/.qn directives.
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+2007-03-26  Alan Modra  <amodra@bigpond.net.au>
 
-	PR/1070
-	* macro.c (getstring): Don't treat parentheses special anymore.
-	(get_any_string): Don't consider '(' and ')' as quoting anymore.
-	Special-case '(', ')', '[', and ']' when dealing with non-quoting
-	characters.
+	* doc/as.texinfo (Reloc): Document.
+	* read.c (potable): Add "reloc".
+	(s_reloc): New function.
+	* write.c (reloc_list): New global var.
+	(resolve_reloc_expr_symbols): New function.
+	(write_object_file): Call it.
+	(write_relocs): Process reloc_list.
+	* write.h (struct reloc_list): New.
+	(reloc_list): Declare.
 
-2006-02-28  Mat <mat@csail.mit.edu>
+2007-03-24  Paul Brook  <paul@codesourcery.com>
 
-	* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
+	* config/tc-arm.c (do_t_ldmstm): Error on Thumb-2 addressing modes.
 
-2006-02-27  Jakub Jelinek  <jakub@redhat.com>
+2007-03-24  Paul Brook  <paul@codesourcery.com>
+	Mark Shinwell  <shinwell@codesourcery.com>
 
-	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
-	field.
-	(CFI_signal_frame): Define.
-	(cfi_pseudo_table): Add .cfi_signal_frame.
-	(dot_cfi): Handle CFI_signal_frame.
-	(output_cie): Handle cie->signal_frame.
-	(select_cie_for_fde): Don't share CIE if signal_frame flag is
-	different.  Copy signal_frame from FDE to newly created CIE.
-	* doc/as.texinfo: Document .cfi_signal_frame.
+	* config/tc-arm.c (operand_parse_code): Add OP_oRRw.
+	(parse_operands): Don't expect comma if first operand missing.
+	Handle OP_oRRw.
+	(do_srs): Encode register number, checking it is r13.  Update comment.
+	(insns): Update SRS entries to take a register.
 
-2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
+2007-03-23  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* doc/Makefile.am: Add html target.
-	* doc/Makefile.in: Regenerate.
-	* po/Make-in: Add html target.
-
-2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
-
-	* config/tc-i386.c (output_insn): Support Intel Merom New
-	Instructions.
-
-	* config/tc-i386.h (CpuMNI): New.
-	(CpuUnknownFlags): Add CpuMNI.
-
-2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
-
-	* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
-	(hpriv_reg_table): New table for hyperprivileged registers.
-	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
-	register encoding.
-
-2006-02-24  DJ Delorie  <dj@redhat.com>
-
-	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
-	(tc_gen_reloc): Don't define.
-	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
-	(OPTION_LINKRELAX): New.
-	(md_longopts): Add it.
-	(m32c_relax): New.
-	(md_parse_options): Set it.
-	(md_assemble): Emit relaxation relocs as needed.
-	(md_convert_frag): Emit relaxation relocs as needed.
-	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
-	(m32c_apply_fix): New.
-	(tc_gen_reloc): New.
-	(m32c_force_relocation): Force out jump relocs when relaxing.
-	(m32c_fix_adjustable): Return false if relaxing.
-
-2006-02-24  Paul Brook  <paul@codesourcery.com>
-
-	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
-	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
-	(struct asm_barrier_opt): Define.
-	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
-	(parse_psr): Accept V7M psr names.
-	(parse_barrier): New function.
-	(enum operand_parse_code): Add OP_oBARRIER.
-	(parse_operands): Implement OP_oBARRIER.
-	(do_barrier): New function.
-	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
-	(do_t_cpsi): Add V7M restrictions.
-	(do_t_mrs, do_t_msr): Validate V7M variants.
-	(md_assemble): Check for NULL variants.
-	(v7m_psrs, barrier_opt_names): New tables.
-	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
-	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
-	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
-	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
-	(struct cpu_arch_ver_table): Define.
-	(cpu_arch_ver): New.
-	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
-	Tag_CPU_arch_profile.
-	* doc/c-arm.texi: Document new cpu and arch options.
-
-2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
-
-2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c: Update copyright years.
-
-2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c (specify_resource): Add the rule 17 from
-	SDM 2.2.
-
-2005-02-22  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (do_pld): Remove incorrect write to
-	inst.instruction.
-	(encode_thumb32_addr_mode): Use correct operand.
-
-2006-02-21  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
-
-2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
-            Anil Paranjape   <anilp1@kpitcummins.com>
-            Shilin Shakti    <shilins@kpitcummins.com>
-
-	* Makefile.am: Add xc16x related entry.
+	* config/tc-i386.c (md_begin): Allow '.' in mnemonic.
+
+2007-03-23  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Turn CBZ instructions that
+	attempt to jump to the next instruction into NOPs.
+
+2007-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c: Don't include opcode/spu.h.
+	(md_assemble): Set tc_fix_data.insn_tag and arg_format.
+	(md_apply_fix): Adjust.
+	* config/tc-spu.h: Include opcode/spu.h.
+	(struct tc_fix_info): New.
+	(TC_FIX_TYPE, TC_INIT_FIX_DATA): Adjust.
+	(TC_FORCE_RELOCATION): Define.
+
+2007-03-22  Joseph Myers  <joseph@codesourcery.com>
+
+	* doc/as.texinfo: Include VERSION_PACKAGE when reporting version.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_suffix): Check 0x90 instead of
+	xchg for xchg %rax,%rax.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY
+	and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4218
+	* config/tc-i386.c (match_template): Properly handle 64bit mode
+	"xchg %eax, %eax".
+
+2007-03-21  Anton Ertl  <anton@mips.complang.tuw>
+
+	PR gas/4124
+	* config/tc-alpha.c (emit_ustX): Fix ustq code generation.
+
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run dep-am.
+	* Makefile.in: Regenerated.
+
+	* config/tc-i386.c: Don't include "opcodes/i386-opc.h".
+
+	* config/tc-i386.h: Include "opcodes/i386-opc.h".
+	(NOP_OPCODE): Removed.
+	(template): Likewise.
+
+2007-03-21  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-i386.h (NOP_OPCODE): Restore.
+
+2007-03-18  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_mul): Don't warn about overlapping
+	Rd and Rm operands when assembling for v6 or above.
+	Correctly capitalize register names in the messages.
+	(do_mlas): Likewise.  Delete spurious blank line.
+
+2007-03-16  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_cpus): Add an entry for fidoa.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_begin): Use i386_regtab_size to scan 
+	i386_regtab.
+	(parse_register): Use i386_regtab_size instead of ARRAY_SIZE
+	on i386_regtab.
+
+2007-03-15  Alexandre Oliva  <aoliva@redhat.com>
+
+	PR gas/4184
+	* app.c (do_scrub_chars): PUT after setting states.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerated.
+
+	* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
+	"opcode/i386.h".
+	(md_begin): Check reg_name != NULL for the last entry in
+	i386_regtab.
+
+	* config/tc-i386.h: Move many entries to opcode/i386.h and
+	opcodes/i386-opc.h.
+
+	* configure.in (need_opcodes): Set true for i386.
+	* configure: Regenerated.
+
+2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am (REPORT_BUGS_TO): Removed.
+	(INCLUDES): Remove -DREPORT_BUGS_TO.
+	* Makefile.in: Regenerated.
+
+	* configure.in (--with-bugurl): Removed.
+	* configure: Regenerated.
+
+	* doc/Makefile.am (as_TEXINFOS): Remove gasver.texi.
+	(AM_MAKEINFOFLAGS): Add -I ../../bfd/doc.
+	(TEXI2DVI): Likewise.
+	(gasver.texi): Removed.
+	(MOSTLYCLEANFILES): Remove gasver.texi.
+	(as.1): Don't depend on gasver.texi.
+	* doc/Makefile.in: Regenerated.
+
+	* doc/as.texi: Include bfdver.texi instead of gasver.texi.
+
+2007-03-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.c (arm_copy_symbol_attributes): New.
+	* config/tc-arm.h (arm_copy_symbol_attributes): Declare.
+	(TC_COPY_SYMBOL_ATTRIBUTES): Define.
+	* gas/symbols.c (copy_symbol_attributes): Use
+	TC_COPY_SYMBOL_ATTRIBUTES.
+
+2007-03-14  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T16_32_TAB): Fix dec_sp encoding.
+
+2007-03-14  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4029
+	* write.c (relax_segment): Insert extra alignment padding
+	to break infinite relax loop when given impossible
+	gcc_except_table assembly.
+
+2007-03-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Use Opcode_XXX instead of XXX
+	on i.tm.base_opcode.
+	(match_template): Likewise.
+	(process_operands): Use ~0x3 mask to match MOV_AX_DISP32.
+
+	* config/tc-i386.h (Opcode_D): New.
+	(Opcode_FloatR): Likewise.
+	(Opcode_FloatD): Likewise.
+	(D): Redefined.
+	(W): Likewise.
+	(FloatMF): Likewise.
+	(FloatR): Likewise.
+	(FloatD): Likewise.
+
+2007-03-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	* app.c (do_scrub_chars): Recognize comments after # line "file".
+	* read.c (get_linefile_number): New.
+	(s_app_line): Accept ill-formed .linefile lines as comments.
+
+2007-03-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.h (WORKING_DOT_WORD): Define.
+
+2007-03-09  Alexandre Oliva  <aoliva@redhat.com>
+
+	* app.c (do_scrub_chars): Turn #<line>"file"flags into .linefile.
+	* as.h (new_logical_line_flags): New.
+	* input-scrub.c (new_logical_line): Turned into wrapper for...
+	(new_logical_line_flags): this.  Handle flags.
+	* read.c (potable): Add linefile.  Adjust appline argument.
+	(s_app_file): Fake .appfiles no more.
+	(s_app_line): For .linefile, accept file name and flags.
+
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (symbol_relc_make_sym): Comment typo fixes.
+
+2007-03-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
 	* Makefile.in: Regenerate.
-	* configure.in: Added xc16x related entry.
-	* configure: Regenerate.
-	* config/tc-xc16x.h: New file
-	* config/tc-xc16x.c: New file
-	* doc/c-xc16x.texi: New file for xc16x
-	* doc/all.texi: Entry for xc16x
-	* doc/Makefile.texi: Added c-xc16x.texi 
-	* NEWS: Announce the support for the new target.
+	* po/POTFILES.in: Regenerate.
 
-2006-02-16  Nick Hudson  <nick.hudson@dsl.pipex.com>
+2007-03-07  Joseph Myers  <joseph@codesourcery.com>
 
-	* configure.tgt: set emulation for mips-*-netbsd*
+	* configure.in (REPORT_BUGS_TEXI): Define to Texinfo version of
+	bug-reporting URL.
+	* doc/Makefile.am (gasver.texi): Define BUGURL.
+	* doc/as.texinfo: Use BUGURL.
+	* Makefile.in, configure, doc/Makefile.in: Regenerate.
 
-2006-02-14  Jakub Jelinek  <jakub@redhat.com>
+2007-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>
 
-	* config.in: Rebuilt.
+	* config/tc-s390.c (md_parse_option): z9-ec option added.
 
-2006-02-13  Bob Wilson  <bob.wilson@acm.org>
+2007-03-02  Paul Brook  <paul@codesourcery.com>
 
-	* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
-	from 1, not 0, in error messages.
-	(md_assemble): Simplify special-case check for ENTRY instructions.
-	(tinsn_has_invalid_symbolic_operands): Do not include opcode and
-	operand in error message.
+	* config/tc-arm.c (relax_immediate): Always return positive values.
+	(relaxed_symbol_addr): New function.
+	(relax_adr, relax_branch): Use it.
+	(arm_relax_frag): Pass strect argument.  Adjust infinite loop check.
 
-2006-02-13  Joseph S. Myers  <joseph@codesourcery.com>
+2007-03-01  Joseph Myers  <joseph@codesourcery.com>
 
-	* configure.tgt (arm-*-linux-gnueabi*): Change to
-	arm-*-linux-*eabi*.
+	* as.c (parse_args): Update copyright date.
 
-2006-02-10  Nick Clifton  <nickc@redhat.com>
+2007-02-28  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* config/tc-crx.c (check_range): Ensure that the sign bit of a
-	32-bit value is propagated into the upper bits of a 64-bit long.
+	* configure.tgt (sh-*-uclinux, sh[12]-*-uclinux): Specify as elf.
 
-	* config/tc-arc.c (init_opcode_tables): Fix cast.
-	(arc_extoper, md_operand): Likewise.
+2007-02-28  Nick Clifton  <nickc@redhat.com>
 
-2006-02-09  David Heine  <dlheine@tensilica.com>
+	PR gas/3797
+	* config/tc-d10v.c (do_assemble): Do not generate error messages,
+	just return -1 whenever a problem is encountered.
+	(md_assemble): If do_assemble returns -1 generate a non-fatal
+	error message and return.
 
-	* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
-	each relaxation step.
+	PR gas/2623
+	* config/tc-msp430.c (line_separator_char): Change to '{'.
 
-2006-02-09  Eric Botcazou  <ebotcazou@libertysurf.fr>
-	
-	* configure.in (CHECK_DECLS): Add vsnprintf.
+2007-02-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-m68hc11.c (fixup24): Correct fixup size.
+	(build_jump_insn): Likewise.
+	(build_insn): Likewise.
+	(s_m68hc11_relax): Likewise.
+
+2007-02-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-elf.c (elf_frob_file): frag_wane any new frags.
+
+2007-02-25  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_nsyn_pop): Use fldmias/fldmiad.
+
+2007-02-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-mn10300.c (md_convert_frag): Correct fixup size.
+	(md_assemble): Likewise.
+
+2007-02-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (size_seg): Always clear SEC_RELOC here.
+	(install_reloc): New function, extracted from..
+	(write_relocs): ..here.  Combine RELOC_EXPANSION_POSSIBLE code
+	with !RELOC_EXPANSION_POSSIBLE code.  Don't add fr_offset when
+	testing frag size.  Set SEC_RELOC here.
+
+2007-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4082
+	* config/tc-avr.h (TC_FX_SIZE_SLACK): Define.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+
+	* doc/c-mips.texi: Document 74kc, 74kf, 74kx.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add 74K configurations.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+            Chao-Ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
+	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
+	(macro_build): Add case '2'.
+	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
+	(validate_mips_insn): Add support for balign instruction.
+	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
+	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
+	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
+	command line options.
+	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
+	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
+	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
+	.set dspr2, .set nodspr2.
+
+2007-02-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5210a_ctrl, mcf52235_ctrl, mcf5225_ctrl): New.
+	(m68k_cpus): Add 5210a..5211a, 52230..52235 5224..5225.
+
+2007-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (TC_FX_SIZE_SLACK): Define.
+	(write_relocs): Reinstate check for fixup within frag.
+	* config/tc-bfin.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-h8300.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-mmix.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-sh.h (TC_FX_SIZE_SLACK): Define.
+	* config/tc-xstormy16.h (TC_FX_SIZE_SLACK): Define.
+
+2007-02-17  Mark Mitchell  <mark@codesourcery.com>
+            Nathan Sidwell  <nathan@codesourcery.com>
+            Vladimir Prus  <vladimir@codesourcery.com
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* configure.in (--with-bugurl): New option.
+	* configure: Regenerate.
+	* dep-in.sed: Remove bin-bugs.h.
+	* Makefile.am (REPORT_BUGS_TO): Define.
+	(INCLUDES): Define REPORT_BUGS_TO.
+	(DEP_INCLUDES): Likewise.
+	($(OBJS)): No longer depend on bin-bugs.h.
+	* Makefile.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* as.c (show_usage): Don't print empty REPORT_BUGS_TO.
+	* as.h: Remove include of bin-bugs.h.
+
+2007-02-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c: White space fixes.
+	(fixup_segment): Move symbol_mri_common_p adjustments..
+	(write_relocs): ..and symbol_equated_reloc_p adjustments..
+	(adjust_reloc_syms): ..to here.
+
+2007-02-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.c (subseg_change, subseg_get): Use xcalloc rather than
+	xmalloc, memset.  Don't bother assigning NULL to known zero mem.
+	(subseg_set_rest): Remove unnecessary cast.
+	* write.c: Include libbfd.h.  Replace PTR with void * throughout.
+	Remove unnecessary forward declarations and casts.
+	(set_symtab): Delete extern bfd_alloc.
+	(fixup_segment): Move.
+
+2007-02-15  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/m68k-parse.h (m68k_register): Add ROMBAR0, ASID.
+	* config/tc-m68k.c (mcfv4e_ctrl): Add ColdFire specific names.
+	(mcf5475_ctrl, mcf5485_ctrl): New.
+	(m68k_cpus): Use mcf5485_ctrl and mcf5485_ctrl for those families.
+	(m68k_ip): Add ASID, MMUBAR, ROMBAR0 handling.
+	(init_table): Add asid, mmubar, adjust rombar0.
+
+2007-02-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
+	* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
+	(process_operands): Move old Seg2ShortForm and Seg3ShortForm
+	code, and test for these insns using a combination of
+	opcode_modifier and operand_types.
+
+2007-02-07  Paul Brook  <paul@codesourcery.com>
+
+	* configure.tgt: Add arm*-*-uclinux-*eabi.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+	    Richard Sandiford  <rsandifo@redhat.com>
+	    DJ Delorie  <dj@redhat.com>
+	    Stan Cox  <scox@redhat.com>
+	    Jim Blandy  <jimb@redhat.com>
+	    Nick Clifton  <nickc@redhat.com>
+	    Jim Wilson  <wilson@redhat.com>
+	    Frank Ch. Eigler  <fche@redhat.com>
+	    Graydon Hoare  <graydon@redhat.com>
+	    Ben Elliston  <bje@redhat.com>
+	    John Healy  <jhealy@redhat.com>
+	    Richard Henderson  <rth@redhat.com>
+
+	* Makefile.am (CPU_TYPES): Add mep.
+	(TARGET_CPU_CFILES): Add tc-mep.c.
+	(TARGET_CPU_HFILES): Add tc-mep.h.
+	(DEPTC_mep_elf): New variable.
+	(DEPTC_mep_coff): Likewise.
+	(DEPOBJ_mep_coff, DEPOBJ_mep_elf, DEP_mep_coff, DEP_mep_elf): Likewise.
+	* configure.in: Support mep.
+	* configure.tgt: Likewise.
+	* config/tc-mep.c: New file.
+	* config/obj-elf.c: New file.
+	* config/tc-mep.c: New file.
+	* config/tc-mep.h: New file.
+	* testsuite/gas/mep: New testsuite with content.
+	* Makefile.in: Regenerate.
 	* configure: Regenerate.
-	* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
-	include/declare here, but...
-	* as.h: Move code detecting VARARGS idiom to the top.
-	(errno.h, stdarg.h, varargs.h, va_list): ...here.
-	(vsnprintf): Declare if not already declared.
-
-2006-02-08  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* as.c (close_output_file): New.
-	(main): Register close_output_file with xatexit before
-	dump_statistics. Don't call output_file_close.
-
-2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
-	mcf5329_control_regs): New.
-	(not_current_architecture, selected_arch, selected_cpu): New.
-	(m68k_archs, m68k_extensions): New.
-	(archs): Renamed to ...
-	(m68k_cpus): ... here.  Adjust.
-	(n_arches): Remove.
-	(md_pseudo_table): Add arch and cpu directives.
-	(find_cf_chip, m68k_ip): Adjust table scanning.
-	(no_68851, no_68881): Remove.
-	(md_assemble): Lazily initialize.
-	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
-	(md_init_after_args): Move functionality to m68k_init_arch.
-	(mri_chip): Adjust table scanning.
-	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
-	options with saner parsing.
-	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
-	m68k_init_arch): New.
-	(s_m68k_cpu, s_m68k_arch): New.
-	(md_show_usage): Adjust.
-	(m68k_elf_final_processing): Set CF EF flags.
-	* config/tc-m68k.h (m68k_init_after_args): Remove.
-	(tc_init_after_args): Remove.
-	* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
-	(M68k-Directives): Document .arch and .cpu directives.
-
-2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
-
-	* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as 
-	synonyms for equ and defl. 
-	(z80_cons_fix_new): New function.
-	(emit_byte): Disallow relative jumps to absolute locations.
-	(emit_data): Only handle defb, prototype changed, because defb is 
-	now handled as pseudo-op rather than an instruction.
-	(instab): Entries for defb,defw,db,dw moved from here...
-	(md_pseudo_table): ... to here, use generic cons() for defw,dw. 
-	Add entries for def24,def32,d24,d32.
-	(md_assemble): Improved error handling.
-	(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
-	* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
-	(z80_cons_fix_new): Declare.
-	* doc/c-z80.texi (defb, db): Mention warning on overflow. 
-	(def24,d24,def32,d32): New pseudo-ops.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+
+	* cgen.c (gas_cgen_install_complex_reloc): Removed.
+	(complex_reloc_installation_howto): Removed.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+	    Graydon Hoare  <graydon@redhat.com>
+	    DJ Delorie  <dj@redhat.com>
+	    Catherine Moore  <clm@redhat.com>
+	    Michael Chastain  <chastain@redhat.com>
+	    Frank Ch. Eigler  <fche@redhat.com>
+
+	* symbols.c (use_complex_relocs_for): New, to decide
+	when to use complex relocs. Add signed RELC support.
+	(resolve_symbol_value): Call use_complex_relocs_for. Unconditionally
+	encode expression symbols as mangled complex relocation symbols (when
+	compiled with -DOBJ_COMPLEX_RELOC).
+	(symbol_relc_make_sym,value,expr): New traversal/conversion routines.
+	* cgen.c (gas_cgen_md_apply_fix3):  Only set signed_p if RELC. Call
+	encode_addend with new args. Modify to get start, length from
+	ifield whenever it is set. Also change condition on which
+	self-describing relocs are encoded. Add hook into
+	gas_cgen_encode_addend.
+	(queue_fixup_recursively): Add signed RELC support. Change from masked
+	expr to trunc flag. Restore assignment of sub-field value to
+	temporary in fixups array. Reflect changed meaning of last arg to
+	queue_fixup_recursively.
+	(fixup): Add cgen_maybe_multi_ifield member.
+	(make_right_shifted_expr): New function.
+	(queue_fixup): Change to recursive function that fragments
+	fixups if operand has a multi-ifield.
+	(gas_cgen_parse_operand): Add RELC code to wrap expressions in
+	symbols, call weak_operand_overflow_check, and fragment call
+	queue_fixup with operand fields.
+	(gas_cgen_finish_insn) Modify to manage ifield pointer.
+	(weak_operand_overflow_check): New function to try to select
+	insns correctly.
+	(gas_cgen_encode_addend): New function for relc.
+	(gas_cgen_install_complex_reloc): Likewise.
+	(gas_cgen_tc_gen_reloc): Add hook into gas_cgen_install_complex_reloc.
+	* write.h (struct fix): Add msb_field_p to fx_cgen sub-struct. Add
+	cgen_maybe_multi_ifield field to fx_cgen substructure.
+	* cgen.h (GAS_CGEN_MAX_FIXUPS): Bump from 3 up to 32.
+	* symbols.h (symbol_relc_make_sym,value,expr): New prototypes.
+	
+2007-02-03  DJ Delorie  <dj@delorie.com>
+
+	* config/tc-m32c.c (m32c_cons_fix_new): New.  Added to support 3
+	byte relocs.
+	* config/tc-m32c.h (TC_CONS_FIX_NEW): Define.
+	(m32c_cons_fix_new): Prototype.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+	
+	* config/tc-xtensa.c (xg_build_to_insn): Use tinsn_init.
+	(xg_expand_assembly_insn, istack_push_space, istack_pop): Likewise.
 	
-2006-02-02  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
-
-2005-02-02  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
-	T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
-	T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
-	T2_OPCODE_RSB): Define.
-	(thumb32_negate_data_op): New function.
-	(md_apply_fix): Use it.
-
-2006-01-31  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
-	fields.
-	* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
-	* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
-	subtracted symbols.
-	(relaxation_requirements): Add pfinish_frag argument and use it to
-	replace setting tinsn->record_fix fields.
-	(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
-	and vinsn_to_insnbuf.  Remove references to record_fix and
-	slot_sub_symbols fields.
-	(xtensa_mark_narrow_branches): Delete unused code.
-	(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
-	a symbol.
-	(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
-	record_fix fields.
-	(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
-	(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
-	of the record_fix field.  Simplify error messages for unexpected
-	symbolic operands.
-	(set_expr_symbol_offset_diff): Delete.
-
-2006-01-31  Paul Brook  <paul@codesourcery.com>
-
-	* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
-
-2006-01-31  Paul Brook  <paul@codesourcery.com>
-	Richard Earnshaw <rearnsha@arm.com>
-
-	* config/tc-arm.c: Use arm_feature_set.
-	(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
-	arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
-	fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
-	New variables.
-	(insns): Use them.
-	(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
-	md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
-	arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
-	s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
-	feature flags.
-	(arm_legacy_option_table, arm_option_cpu_value_table): New types.
-	(arm_opts): Move old cpu/arch options from here...
-	(arm_legacy_opts): ... to here.
-	(md_parse_option): Search arm_legacy_opts.
-	(arm_cpus, arm_archs, arm_extensions, arm_fpus)
-	(arm_float_abis, arm_eabis): Make const.
-
-2006-01-25  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
-
-2006-01-21  Jie Zhang  <jie.zhang@analog.com>
-
-	* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
-	in load immediate intruction.
-
-2006-01-21  Jie Zhang  <jie.zhang@analog.com>
-
-	* config/bfin-parse.y (value_match): Use correct conversion
-	specifications in template string for __FILE__ and __LINE__.
-	(binary): Ditto.
-	(unary): Ditto.
-
-2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
-
-	Introduce TLS descriptors for i386 and x86_64.
-	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
-	BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
-	BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
-	(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
-	BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
-	displacement bits.
-	(build_modrm_byte): Set up zero modrm for TLS desc calls.
-	(lex_got): Handle @tlsdesc and @tlscall.
-	(md_apply_fix, tc_gen_reloc): Handle the new relocations.
-
-2006-01-11  Nick Clifton  <nickc@redhat.com>
-
-	Fixes for building on 64-bit hosts:
-	* config/tc-avr.c (mod_index): New union to allow conversion
-	between pointers and integers.
-	(md_begin, avr_ldi_expression): Use it.
-	* config/tc-i370.c (md_assemble): Add cast for argument to print
-	statement.
-	* config/tc-tic54x.c (subsym_substitute): Likewise.
-	* config/tc-mn10200.c (md_assemble): Use a union to convert the
-	opindex field of fr_cgen structure into a pointer so that it can
-	be stored in a frag.
-	* config/tc-mn10300.c (md_assemble): Likewise.
-	* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
-	types.
-	* config/tc-v850.c: Replace uses of (int) casts with correct
-	types.
-
-2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
-
-	PR gas/2117
-	* symbols.c (snapshot_symbol): Don't change a defined symbol.
-
-2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
-
-	PR gas/2101
-	* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
-	a local-label reference.
-
-For older changes see ChangeLog-2005
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (SUFFIX_MAP, suffix_relocs): New.
+	(xtensa_elf_suffix): Use suffix_relocs instead of local mapping table.
+	(map_suffix_reloc_to_operator): New.
+	(map_operator_to_reloc): New.
+	(expression_maybe_register): Fix incorrect test of return value from
+	xtensa_elf_suffix.  Rearrange to use map_suffix_reloc_to_operator.
+	(xg_assemble_literal, convert_frag_immed): Use map_operator_to_reloc.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (struct tinsn_struct): Delete fixup field.
+	(tinsn_get_tok): Delete prototype.
+	* config/tc-xtensa.c (tinsn_get_tok): Delete.
+	
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.h (struct build_instr): Delete id field.
+	* config/xtensa-relax.c (widen_spec_list): Remove zeros from LITERAL
+	and LABEL tokens.
+	(append_literal_op, append_label_op): Remove litnum/labnum arguments;
+	set op_data fields to zero.
+	(parse_id_constant): Delete.
+	(build_transition): Remove code to handle numbered literals and labels.
+
+2007-02-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (build_transition): Remove code after as_fatal.
+	(build_transition_table): Likewise.
+
+2007-02-01  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_add_opcode_fix, md_apply_fix): Delete use of
+	fx_tcbit.
+	* config/tc-xtensa.h (TC_FORCE_RELOCATION_LOCAL): Remove.
+
+2007-02-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.h (struct fix <fx_pcrel_adjust, fx_size>): Move.
+	(struct fix <fx_plt>): Rename to tcbit2.
+	* write.c (fix_new_internal): Adjust.
+	(TC_FORCE_RELOCATION_LOCAL): Don't test fx_plt.
+	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-cris.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-i960.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sh.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sh64.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-sparc.h (TC_FORCE_RELOCATION_LOCAL): Likewise.
+	* config/tc-msp430.c (msp430_force_relocation_local): Likewise.
+	* config/tc-ia64.c (emit_one_bundle): Don't set fx_plt.
+	* config/tc-ia64.h (TC_FORCE_RELOCATION_LOCAL): Don't test fx_plt.
+	Instead, compare fx_r_type.
+	* config/tc-xtensa.c (xg_add_opcode_fix, md_apply_fix): Use
+	fx_tcbit in place of fx_plt.
+	* config/tc-xtensa.h (TC_FORCE_RELOCATION_LOCAL): Define.
+	* doc/internals.texi (TC_FORCE_RELOCATION_LOCAL): Remove reference
+	to fx_plt.
+
+2007-01-30  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (main): Mark symbols created via the --defsym command line
+	option as volatile so that they can be overridden later on by a
+	.set directive.  This maintains compatibility with the behaviour
+	of earlier versions of the assembler.
+	* doc/as.texinfo (--defsym): Document that the defined symbol's
+	value can be overridden via a .set directive.
+
+2007-01-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (swap_imm_operands): Renamed to ...
+	(swap_2_operands): This.  Take 2 ints.
+	(md_assemble): Updated.
+	(swap_operands): Call swap_2_operands to swap 2 operands.
+
+2007-01-24  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_pseudo_table): Add .3byte.
+
+2007-01-22  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3871
+	* tc-score.c: Remove unnecessary uses of _().
+	Make the err_msg[] a file level local array in order to save
+	storage space.
+	Remove unnecessary sprintf()s.
+
+2007-01-18  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	PR gas/3871
+	* config/tc-score.c : Using _() for const string.
+	Do not assign inst.error with a local string pointer.
+	(md_section_align): Pad section.
+	
+2007-01-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Check number of operands
+	when procssing memory/register operand.
+
+2007-01-12  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3856
+	* macro.c (expand_irp): Do not ignore spaces inside quoted
+	strings.
+
+2007-01-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	* config/tc-m32r.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	* config/tc-mn10300.h (TC_RELOC_RTSYM_LOC_FIXUP): Delete.
+	(TC_FORCE_RELOCATION): Define.
+	(TC_FORCE_RELOCATION_LOCAL): Define.
+	* config/tc-mn10300.c (mn10300_fix_adjustable): Adjust.
+
+2007-01-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* input-file.c (input_file_open): Check fgets return.
+
+2007-01-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
+
+2007-01-11  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3707
+	* config/tc-arm.c (md_begin): Cope with an NULL mcpu_fpu_opt
+	variable.
+
+	* config/tc-mcore.c (md_number_to_chars): Use
+	number_to_chars_{big|little}endian.
+
+2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an
+	architecture by itself.
+	(m68k_ip): Don't issue a warning for tbl instructions on fido.
+	(m68k_elf_final_processing): Treat Fido as an architecture by
+	itself.
+
+2007-01-08  Kai Tietz	<kai.tietz@onevision.com>
+
+	* configure.tgt: Renamed target x86_64-*-mingw64 to x86_64-*-mingw*
+
+2007-01-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (set_intel_syntax): Update set_intel_syntax
+	depending on allow_naked_reg.
+
+2007-01-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_cpsi): Set mmod bit for 2 argument form.
+
+2007-01-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3830
+	* config/tc-i386.c (register_prefix): New.
+	(set_intel_syntax): Set set_intel_syntax to "" if register
+	prefix isn't needed.
+	(check_byte_reg): Use register_prefix for error message.
+	(check_long_reg): Likewise.
+	(check_qword_reg): Likewise.
+	(check_word_reg): Likewise.
+
+2006-01-04  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (do_neon_shl_imm): Swap rN, rM.
+	(do_neon_qshl_imm): Likewise.
+	(do_neon_rshl): New function. Handle rounding variants of
+	v{q}shl-by-register.
+	(insns): Use do_neon_rshl for vrshl, vqrshl.
+
+2007-01-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (NEON_ENC_TAB): Fix encoding of vclt, vcle, vaclt
+	and vacle.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (swap_operands): Remove branches.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Update copyright year.
+	* config/tc-i386.h: Likewise.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (smallest_imm_type): Return unsigned int
+	instead of int.
+
+2007-01-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Convert to ISO C90 formatting
+	* config/tc-i386.h: Likewise.
+
+2007-01-03  David Daney  <ddaney@avtrex.com>
+
+	* config/tc-mips.c (md_show_usage):  Clean up -mno-shared
+	documentation.
+
+For older changes see ChangeLog-2006
 
 Local Variables:
 mode: change-log
diff --git a/gas/ChangeLog-2006 b/gas/ChangeLog-2006
new file mode 100644
index 000000000000..dc933e5b0508
--- /dev/null
+++ b/gas/ChangeLog-2006
@@ -0,0 +1,2756 @@
+2006-12-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (ShiftCount): Fix a comment typo.
+
+2006-12-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_show_usage): Mention --32/--64.
+
+2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Handle shift count
+	register with 3 operands.
+
+2006-12-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_operands): Check i.reg_operands
+	and increment i.operands when adding a register operand.
+	(build_modrm_byte): Fix 4 operand instruction handling.
+
+2006-12-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (disp_expressions): Use MAX_MEMORY_OPERANDS
+	for array size instead of 2.
+	(im_expressions): Use MAX_IMMEDIATE_OPERANDS for for array size
+	instead of 2.
+	(i386_immediate): Update immediate operand overflow error
+	message.
+	(i386_displacement): Check displacement operand overflow.
+
+2006-12-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Document tc-i386.c, not i386.c.
+
+2006-12-27  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/m68k-parse.h (m68k_register): Add CAC and MBB.
+	* config/tc-m68k.c (fido_ctrl): New.
+	(m68k_archs): Use fido_ctrl for -mfidoa.
+	(m68k_cpus): Use fido_ctrl on fido-*-*.
+	(m68k_ip): Add support for CAC and MBB.
+	(init_table): Add CAC and MBB.
+
+2006-12-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (i386_immediate): Remove prototype.
+
+2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c (cpu_of_arch): Add fido.
+	(m68k_archs, m68k_cpu): Add entries for fido.
+	(m68k_elf_final_processing): Handle EF_M68K_CPU32_FIDO_A.
+
+2006-12-25  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (build_lw_pic): Rename as build_lwst_pic.
+	Delete the code handling large constant for PIC.
+	Modify some comments.
+	(score_relax_frag): Decrease insn_addr in certain situation.
+	(s_score_cprestore): Change .cprestore syntax from ".cprestore offset" 
+	to ".cprestore reg, offset".
+	
+2006-12-23  Kazu Hirata  <kazu@codesourcery.com>
+
+	* configure.tgt: Recognize fido.
+
+2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c: Add a blank line bewteen function bodies.
+
+2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Reformat to 72 columns.
+
+2006-12-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* Makefile.am (YFLAGS): Define.
+	* Makefile.in: Regenerated.
+
+2006-12-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Simplify 3 and 4 operand
+	match.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (build_modrm_byte): Set the Operand_PCrel
+	bit only.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (match_template): Use a for loop to set
+	operand_types array.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3712
+	* config/tc-i386.c (match_template): Use MAX_OPERANDS for the
+	number of operands. Issue an error if MAX_OPERANDS != 4. Add
+	the 4th operand check.
+
+2006-12-13  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_arch_option_table): Add v7-{a,r,m}.
+	* doc/c-arm.texi: Fix spelling of ARMv7 profile variants.
+
+2006-12-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (WordMem): Document it for 64 bit memory
+	reference.
+
+2006-12-12  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (as_TEXINFOS): Set.
+	(as.info as.dvi as.html): Delete rule.
+	* doc/Makefile.in: Regenerated.
+
+2006-12-11  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* configure.in: Define GENINSRC_NEVER.
+	* doc/Makefile.am (as.info): Remove srcdir prefix.
+	(MAINTAINERCLEANFILES): Add info file.
+	(DISTCLEANFILES): Pretend to add info file.
+	* po/Make-in (.po.gmo): Put gmo files in objdir.
+	* configure, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-12-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (template): Use MAX_OPERANDS instead of 4
+	for operand_types array.
+
+2006-12-08  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-z8k.c (whatreg): Add comment describing function.
+	Return NULL if symbol name characters follow the register number.
+	(parse_reg): Use NULL instead of 0 for pointer values.  Stop
+	processing if whatreg returned NULL.
+
+2006-12-07  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-m68k.c: Update uses of EF_M68K_*.
+
+2006-12-06  H.J. Lu <hjl@gnu.org>
+
+	* config/tc-i386.h: Change the prefix order to SEG_PREFIX,
+	ADDR_PREFIX, DATA_PREFIX, LOCKREP_PREFIX.
+
+2006-12-02  Jakub Jelinek  <jakub@redhat.com>
+
+	PR gas/3607
+	* subsegs.c (subseg_set_rest): Clear frch_cfi_data field.
+
+2006-12-01  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_force_relocation): Return 1 for relocs against
+	function symbols.
+
+2006-11-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_is_eabi): New function.
+	* config/tc-arm.h (arm_is_eabi): New prototype.
+	(THUMB_IS_FUNC): Use ELF function type for EABI objects.
+	* doc/c-arm.texi (.thumb_func): Update documentation.
+
+2006-11-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_sp_const, do_vfp_dp_const): Fix operans
+	encoding.
+
+2006-11-27  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xtensa_sanity_check): Check for RELAX_IMMED
+	as the first slot_subtype, not the frag subtype.
+
+2006-11-27  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (XSHAL_ABI): Add default definition.
+	(directive_state): Disable scheduling by default.
+	(xtensa_add_config_info): New.
+	(xtensa_end): Call xtensa_add_config_info.
+
+2006-11-27  Eric Botcazou  <ebotcazou@adacore.com>
+
+	* config/tc-sparc.c (tc_gen_reloc): Turn aligned relocs into
+	their unaligned counterparts in debugging sections.
+
+2006-11-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c (md_pseudo_table): Add eqv and .eqv.
+
+2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.h (md_cons_align): Define.
+	(mapping_state): New prototype.
+	* config/tc-arm.c (mapping_state): Make global.
+
+2006-11-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-elf.c (obj_elf_version): Use memcpy rather than strcpy.
+
+2006-11-16  Mei ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (score_relax_frag): If next frag contains 32 bit
+	branch instruction, handle it specially.
+	(score_insns): Modify 32 bit branch instruction.
+
+2006-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (resolve_symbol_value): Formatting.
+
+2006-11-15  Jan Beulich  <jbeulich@novell.com>
+
+	PR/3469
+	* symbols.c (symbol_clone): Mark symbol ending up not on symbol
+	chain by linking it to itself.
+	(resolve_symbol_value): Also check symbol_shadow_p().
+	(symbol_shadow_p): New.
+	* symbols.h (symbol_shadow_p): Declare.
+
+2006-11-12  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (do_t_czb): Rename to do_t_cbz.
+	(insns): Adjust accordingly.
+	(md_apply_fix): Alter comments to use CBZ instead of CZB.
+
+2006-11-10  Pedro Alves <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c (arm_fix_adjustable) [OBJ_COFF]: Delete.
+	(arm_fix_adjustable) [OBJ_ELF]: Use it on coff targets too.
+
+2006-11-10  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3456:
+	* config/obj-elf.c (obj_elf_version): Do not include the name
+	field's padding in the namesz value.
+
+2006-11-09  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c: Fix outdated comment.
+
+2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (CpuPNI): Removed.
+	(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
+	* config/tc-i386.c (md_assemble): Likewise.
+
+2006-11-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (symbol_create, symbol_clone): Don't set udata.p.
+
+2006-11-06  David Daney  <ddaney@avtrex.com>
+
+	* config/tc-mips.c (pic_need_relax): Return true for section symbols.
+
+2006-11-06  Thiemo Seufer  <ths@mips.com>
+
+	* doc/c-mips.texi (-march): Document sb1a.
+
+2006-11-06  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
+	34k always has DSP ASE.
+
+2006-11-03  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_pcrel_from_section): Disallow PC relative
+	MIPS16 instructions referencing other sections, unless they are
+	external branches.
+
+2006-11-03  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): The 25Kf is a MIPS64
+	release 1 CPU.
+
+2006-11-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* dw2gencfi.c (struct fde_entry): Add per_encoding, lsda_encoding,
+	personality and lsda.
+	(struct cie_entry): Add per_encoding, lsda_encoding and personality.
+	(alloc_fde_entry): Initialize per_encoding and lsda_encoding.
+	(cfi_pseudo_table): Handle .cfi_personality and .cfi_lsda.
+	(dot_cfi_personality, dot_cfi_lsda, encoding_size): New functions.
+	(output_cie): Output personality including its encoding and LSDA encoding.
+	(output_fde): Output LSDA.
+	(select_cie_for_fde): Don't share CIE if personality, its encoding or
+	LSDA encoding are different.  Copy the 3 fields from fde_entry to
+	cie_entry.
+	* doc/as.texinfo (.cfi_personality, .cfi_lsda): Document.
+
+	* subsegs.h (struct frchain): Add frch_cfi_data field.
+	* dw2gencfi.c: Include subsegs.h.
+	(cur_fde_data, last_address, cur_cfa_offset, cfa_save_stack): Removed.
+	(struct frch_cfi_data): New type.
+	(unused_cfi_data): New variable.
+	(alloc_fde_entry): Move cur_fde_data, last_address, cur_cfa_offset
+	and cfa_save_stack static vars into a structure pointed from
+	each frchain.
+	(alloc_cfi_insn_data, cfi_new_fde, cfi_end_fde, cfi_set_return_column,
+	cfi_add_advance_loc, cfi_add_CFA_def_cfa, cfi_add_CFA_def_cfa_offset,
+	cfi_add_CFA_remember_state, cfi_add_CFA_restore_state, dot_cfi,
+	dot_cfi_escape, dot_cfi_startproc, dot_cfi_endproc, cfi_finish):
+	Likewise.
+
+2006-11-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-h8300.c (build_bytes): Fix const warning.
+
+2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* tc-score.c (do16_rdrs): Handle not! instruction especially.
+
+2006-10-31  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Don't use STT_ARM_16BIT
+	for EABIv4.
+
+2006-10-31  Paul Brook  <paul@codesourcery.com>
+
+	gas/
+	* config/tc-arm.c (object_arch): New variable.
+	(s_arm_object_arch): New function.
+	(md_pseudo_table): Add object_arch.
+	(aeabi_set_public_attributes): Obey object_arch.
+	* doc/c-arm.texi: Document .object_arch.
+
+2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* tc-score.c (data_op2): Check invalid operands.
+	(my_get_expression): Const operand of some instructions can not be
+	symbol in assembly.
+	(get_insn_class_from_type): Handle instruction type Insn_internal.
+	(do_macro_ldst_label): Modify inst.type.
+	(Insn_PIC): Delete.
+	(data_op2): The immediate value in lw is 15 bit signed.
+
+2006-10-29  Randolph Chung  <tausq@debian.org>
+
+	* config/tc-hppa.c (hppa_cfi_frame_initial_instructions)
+	(hppa_regname_to_dw2regnum): New funcions.
+	* config/tc-hppa.h [OBJ_ELF] (TARGET_USE_CFIPOP): Define.
+	(tc_cfi_frame_initial_instructions)
+	(tc_regname_to_dw2regnum): Define.
+	(hppa_cfi_frame_initial_instructions)
+	(hppa_regname_to_dw2regnum): Declare.
+	(DWARF2_LINE_MIN_INSN_LENGTH, DWARF2_DEFAULT_RETURN_COLUMN)
+	(DWARF2_CIE_DATA_ALIGNMENT): Define.
+
+2006-10-29  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-spu.c (md_assemble): Cast printf string size parameter
+	to int in order to avoid a compiler warning.
+
+2006-10-27  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* config/tc-sh.c (md_assemble): Define size of branches.
+
+2006-10-26  Ben Elliston  <bje@au.ibm.com>
+
+	* dw2gencfi.c (cfi_add_CFA_offset):
+	Assert DWARF2_CIE_DATA_ALIGNMENT is non-zero.
+
+	* write.c (chain_frchains_together_1): Assert that this function
+	never returns a pointer to the auto variable `dummy'.
+
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+	    Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+	    Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+	    Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-spu.c: New file.
+	* config/tc-spu.h: New file.
+	* configure.tgt: Add SPU support.
+	* Makefile.am: Likewise.  Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2006-10-25  Ben Elliston  <bje@au.ibm.com>
+
+	* expr.c (expr): Replace O_add case in switch (op_left) explaining
+	why it can never occur.
+
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+	* doc/c-ppc.texi (-mcell): Document.
+	* config/tc-ppc.c (parse_cpu): Parse -mcell.
+	(md_show_usage): Document -mcell.
+
+2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+	* doc/c-i386.texi : Document amdfam10,.sse4a and .abm in cpu_type.
+
+2006-10-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-m68hc11.c (md_assemble): Quiet warning.
+
+2006-10-19  Mike Frysinger  <vapier@gentoo.org>
+
+	* config/tc-i386.c (md_parse_option): Use CONST_STRNEQ.
+	(x86_64_section_letter): Likewise.
+
+2006-10-19  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (build_relax_frag): Compute correct
+	tc_frag_data.fixp.
+
+2006-10-18  Roy Marples  <uberlord@gentoo.org>
+
+	* config/tc-sparc.c (md_parse_option): Treat any target starting with
+	elf32-sparc as a viable target for the -32 switch and any target
+	starting with elf64-sparc as a viable target for the -64 switch.
+	(sparc_target_format): For 64-bit ELF flavoured output use
+	ELF_TARGET_FORMAT64 while for 32-bit ELF flavoured output use
+	ELF_TARGET_FORMAT.
+	* config/tc-sparc.h (ELF_TARGET_FORMAT, ELF_TARGET_FORMAT64): Define.
+
+2006-10-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* configure: Regenerated.
+
+2006-10-16  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* input-scrub.c (input_scrub_next_buffer): Use TC_EOL_IN_INSN
+	in addition to testing for '\n'.
+	(TC_EOL_IN_INSN): Provide a default definition if necessary.
+
+2006-10-13  Sterling Augstine  <sterling@tensilica.com>
+
+	* dwarf2dbg.c (out_debug_info): Use TC_DWARF2_EMIT_OFFSET to emit
+	a disjoint DW_AT range.
+
+2006-10-13  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c (md_show_usage): Print -KPIC option usage.
+
+2006-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_big_immediate): 64-bit host fix.
+	(parse_operands): Use parse_big_immediate for OP_NILO.
+	(neon_cmode_for_logic_imm): Try smaller element sizes.
+	(neon_cmode_for_move_imm): Ditto.
+	(do_neon_logic): Handle .i64 pseudo-op.
+
+2006-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+
+2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (CpuMNI): Renamed to ...
+	(CpuSSSE3): This.
+	(CpuUnknownFlags): Updated.
+	(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
+	and PROCESSOR_MEROM with PROCESSOR_CORE2.
+	* config/tc-i386.c: Updated.
+	* doc/c-i386.texi: Likewise.
+
+	* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".
+
+2006-09-28  Bridge Wu  <mingqiao.wu@gmail.com>
+
+	* config/tc-arm.c (md_apply_fix): Do not clear write_back bit.
+
+2006-09-27  Nick Clifton  <nickc@redhat.com>
+
+	* output-file.c (output_file_close): Prevent an infinite loop
+	reporting that stdoutput could not be closed.
+
+2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+            Ian Lance Taylor  <ian@wasabisystems.com>
+            Ben Elliston  <bje@wasabisystems.com>
+
+	* config/tc-arm.c (arm_cext_iwmmxt2): New.
+	(enum operand_parse_code): New code OP_RIWR_I32z.
+	(parse_operands): Handle OP_RIWR_I32z.
+	(do_iwmmxt_wmerge): New function.
+	(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
+	a register.
+	(do_iwmmxt_wrwrwr_or_imm5): New function.
+	(insns): Mark instructions as RIWR_I32z as appropriate.
+	Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
+	waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
+	wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
+	wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
+	(md_begin): Handle IWMMXT2.
+	(arm_cpus): Add iwmmxt2.
+	(arm_extensions): Likewise.
+	(arm_archs): Likewise.
+
+2006-09-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo (Overview): Revise description of --keep-locals.
+	Add xref to "Symbol Names".
+	(L): Refer to "local symbols" instead of "local labels".  Move
+	definition to "Symbol Names" section; add xref to that section.
+	(Symbol Names): Use "Local Symbol Names" section to define local
+	symbols.  Add "Local Labels" heading for description of temporary
+	forward/backward labels, and refer to those as "local labels".
+
+2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/3235
+	* config/tc-i386.c (match_template): Check address size prefix
+	to turn Disp64/Disp32/Disp16 operand into Disp32/Disp16/Disp32
+	operand.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_symbol_chars): Remove '+' and '-'.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* as.h (as_perror): Delete declaration.
+	* gdbinit.in (as_perror): Delete breakpoint.
+	* messages.c (as_perror): Delete function.
+	* doc/internals.texi: Remove as_perror description.
+	* listing.c (listing_print: Don't use as_perror.
+	* output-file.c (output_file_create, output_file_close): Likewise.
+	* symbols.c (symbol_create, symbol_clone): Likewise.
+	* write.c (write_contents): Likewise.
+	* config/obj-som.c (obj_som_version, obj_som_copyright): Likewise.
+	* config/tc-tic54x.c (tic54x_mlib): Likewise.
+
+2006-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (md_section_align): Don't round up address for ELF.
+	(ppc_handle_align): New function.
+	* config/tc-ppc.h (HANDLE_ALIGN): Use ppc_handle_align.
+	(SUB_SEGMENT_ALIGN): Define as zero.
+
+2006-09-20  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo: Fix cross reference usage, typos and grammar.
+	(Overview): Skip cross reference in man page.
+
+2006-09-20  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* configure.in: Add new target x86_64-pc-mingw64.
+	* configure: Regenerate.
+	* configure.tgt: Add new target x86_64-pc-mingw64.
+	* config/obj-coff.h: Add handling for TE_PEP target specific code
+	and definitions.
+	* config/tc-i386.c: Add new targets.
+	(md_parse_option): Add targets to OPTION_64.
+	(x86_64_target_format): Add new method for setup proper default
+	target cpu mode.
+	* config/te-pep.h: Add new target definition header.
+	(TE_PEP): New macro: Identifies new target architecture.
+	(COFF_WITH_pex64): Set proper includes in bfd.
+	* NEWS: Mention new target.
+
+2006-09-18  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-parse.y (binary): Change sub of const to add of negated
+	const.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* config/tc-score.c: New file.
+	* config/tc-score.h: Newf file.
+	* configure.tgt: Add Score target.
+	* Makefile.am: Add Score files.
+	* Makefile.in: Regenerate.
+	* NEWS: Mention new target support.
+
+2006-09-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_movsp): Add offset argument.
+	* doc/c-arm.texi (movsp): Document offset argument.
+
+2006-09-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (thumb32_negate_data_op): Consistently use
+	unsigned int to avoid 64-bit host problems.
+
+2006-09-15  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-parse.y (binary): Do some more constant folding for
+	additions.
+
+2006-09-13  Jan Beulich  <jbeulich@novell.com>
+
+	* input-file.c (input_file_give_next_buffer): Demote as_bad to
+	as_warn.
+
+2006-09-13  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/3165
+	* config/tc-sh (DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number
+	in parens.
+
+2006-09-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* input-file.c (input_file_open): Replace as_perror with as_bad
+	so that gas exits with error on file errors.  Correct error
+	message.
+	(input_file_get, input_file_give_next_buffer): Likewise.
+	* input-file.h: Update comment.
+
+2006-09-11  Tomas Frydrych  <dr.tomas@yahoo.co.uk>
+
+	PR gas/3172
+	* config/tc-arm.c (parse_typed_reg_or_scalar): Accept wCg class
+	registers as a sub-class of wC registers.
+
+2006-09-11  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/3165
+	* config/tc-mips.h (enum dwarf2_format): Forward declare.
+	(DWARF2_CIE_DATA_ALIGNMENT): Wrap negative number in parens.
+	* config/tc-alpha.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
+	* config/tc-arm.h (DWARF2_CIE_DATA_ALIGNMENT): Likewise.
+
+2006-09-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3129
+	* doc/as.texinfo (Macro): Improve documentation about separating
+	macro arguments from following text.
+
+2006-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Allow ARM IT pseudo-insn on all cores.
+
+2006-09-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Mark operand as present.
+
+2006-09-04  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
+	(do_neon_dyadic_if_i_d): Avoid setting U bit.
+	(do_neon_mac_maybe_scalar): Ditto.
+	(do_neon_dyadic_narrow): Force operand type to NT_integer.
+	(insns): Remove out of date comments.
+
+2006-08-29  Nick Clifton  <nickc@redhat.com>
+
+	* read.c (s_align): Initialize the 'stopc' variable to prevent
+	compiler complaints about it being used without being
+	initialized.
+	(s_comm_internal, s_mri_common, s_fail, s_globl, s_space,
+	s_float_space, s_struct, cons_worker, equals): Likewise.
+
+2006-08-29  Malcolm Parsons  <malcolm.parsons@gmail.com>
+
+	* ecoff.c (ecoff_directive_val): Fix message typo.
+	* config/tc-ns32k.c (convert_iif): Likewise.
+	* config/tc-sh64.c (shmedia_check_limits): Likewise.
+
+2006-08-25  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_mark_literal_pool_location): Do not check
+	the state of the absolute_literals directive.  Remove align frag at
+	the start of the literal pool position.
+
+2006-08-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/c-xtensa.texi: Add @group commands in examples.
+
+2006-08-24  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (FINI_LITERAL_SECTION_NAME): Delete.
+	(INIT_LITERAL_SECTION_NAME): Delete.
+	(lit_state struct): Remove segment names, init_lit_seg, and
+	fini_lit_seg.  Add lit_prefix and current_text_seg.
+	(init_literal_head_h, init_literal_head): Delete.
+	(fini_literal_head_h, fini_literal_head): Delete.
+	(xtensa_begin_directive): Move argument parsing to
+	xtensa_literal_prefix function.
+	(xtensa_end_directive): Deallocate lit_prefix field of lit_state.
+	(xtensa_literal_prefix): Parse the directive argument here and
+	record it in the lit_prefix field.  Remove code to derive literal
+	section names.
+	(linkonce_len): New.
+	(get_is_linkonce_section): Use linkonce_len.  Check for any
+	".gnu.linkonce.*" section, not just text sections.
+	(md_begin): Remove initialization of deleted lit_state fields.
+	(xtensa_reorder_segments, xtensa_post_relax_hook): Remove references
+	to init_literal_head and fini_literal_head.
+	(xtensa_move_literals): Likewise.  Skip literals for .init and .fini
+	when traversing literal_head list.
+	(match_section_group): New.
+	(cache_literal_section): Rewrite to determine the literal section
+	name on the fly, create the section and return it.
+	(xtensa_switch_to_literal_fragment): Adjust for cache_literal_section.
+	(xtensa_switch_to_non_abs_literal_fragment): Likewise.
+	(xtensa_create_property_segments, xtensa_create_xproperty_segments):
+	Use xtensa_get_property_section from bfd.
+	(retrieve_xtensa_section): Delete.
+	* doc/c-xtensa.texi (Xtensa Options): Fix --text-section-literals
+	description to refer to plural literal sections and add xref to
+	the Literal Directive section.
+	(Literal Directive): Describe new rules for deriving literal section
+	names.  Add footnote for special case of .init/.fini with
+	--text-section-literals.
+	(Literal Prefix Directive): Replace old naming rules with xref to the
+	Literal Directive section.
+
+2006-08-21  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_save_mmxwr): Correct condition for
+	merging with previous long opcode.
+
+2006-08-22  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* Makefile.am (TARG_ENV_HFILES): Add te-wince-pe.h.
+	* Makefile.in: Regenerate.
+	* config/tc-arm.h [TARGET_FORMAT]: ARM wince bfd names were
+	renamed. Adjust.
+
+2006-08-16  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (md_assemble): Improve diagnostic when attempting
+	to use ARM instructions on non-ARM-supporting cores.
+	(autoselect_thumb_from_cpu_variant): New function. Switch on Thumb
+	mode automatically based on cpu variant.
+	(md_begin): Call above function.
+
+2006-08-16  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (opcode_lookup): Allow Neon type suffixes to be
+	recognized in non-unified syntax mode.
+
+2006-08-15  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* configure.tgt: Handle mips*-sde-elf*.
+
+2006-08-12  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c (mips16_ip): Fix argument register handling
+	for restore instruction.
+
+2006-08-08  Bob Wilson  <bob.wilson@acm.org>
+
+	* dwarf2dbg.c (DWARF2_USE_FIXED_ADVANCE_PC): New.
+	(out_sleb128): New.
+	(out_fixed_inc_line_addr): New.
+	(process_entries): Use out_fixed_inc_line_addr when
+	DWARF2_USE_FIXED_ADVANCE_PC is set.
+	* config/tc-xtensa.h (DWARF2_USE_FIXED_ADVANCE_PC): Define.
+
+2006-08-08  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-sh.c (sh_frob_section): Canonicalize pointers to local
+	vs full symbols so that we never have more than one pointer value
+	for any given symbol in our symbol table.
+
+2006-08-08  Sterling Augustine  <sterling@tensilica.com>
+
+	* dwarf2dbg.c (out_debug_info): Add new parameter ranges_seg
+	and emit DW_AT_ranges when code in compilation unit is not
+	contiguous.
+	(out_debug_abbrev): Emit DW_AT_ranges abbreviation if code in
+	is not contiguous.
+	(dwarf2_finish): Create and pass ranges_seg to out_debug_info.
+	(out_debug_ranges): New function to emit .debug_ranges section
+	when code is not contiguous.
+
+2006-08-08  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (WARN_DEPRECATED): Enable.
+
+2006-08-05  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c: Move "dwarf2dbg.h" inclusion out of OBJ_ELF
+	only block.
+	(pe_directive_secrel) [TE_PE]: New function.
+	(md_pseudo_table) [!OBJ_ELF]: Handle 2byte, 4byte, 8byte, file,
+	loc, loc_mark_labels.
+	[TE_PE]: Handle secrel32.
+	(output_relax_insn): Remove OBJ_ELF around dwarf2_emit_insn
+	call.
+	(output_inst): Remove OBJ_ELF around dwarf2_emit_insn call.
+	(arm_frob_label): Remove OBJ_ELF around dwarf2_emit_label call.
+	(md_section_align): Only round section sizes here for AOUT
+	targets.
+	(tc_arm_regname_to_dw2regnum): Move out for OBJ_ELF only block.
+	(tc_pe_dwarf2_emit_offset): New function.
+	(md_apply_fix) [TE_PE]: Handle BFD_RELOC_32_SECREL.
+	(cons_fix_new_arm): Handle O_secrel.
+	* config/tc-arm.h : Move DWARF2_LINE_MIN_INSN_LENGTH,
+	DWARF2_DEFAULT_RETURN_COLUMN and DWARF2_CIE_DATA_ALIGNMENT out
+	of OBJ_ELF only block.
+	[TE_PE]: Define O_secrel, TC_DWARF2_EMIT_OFFSET, and declare
+	tc_pe_dwarf2_emit_offset.
+
+2006-08-04  Richard Sandiford  <richard@codesourcery.com>
+
+	* config/tc-sh.c (apply_full_field_fix): New function.
+	(md_apply_fix): Use it instead of md_number_to_chars.  Do not fill
+	in fx_addnumber for BFD_RELOC_32_PLT_PCREL.
+	(tc_gen_reloc): Use fx_addnumber rather than 0 as the default case.
+	* config/tc-sh.h (TARGET_FORMAT): Override for TE_VXWORKS.
+
+2006-08-03  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2991
+	* config.in: Regenerate.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Handle invalid register name
+	for OP_RIWR_RIWC.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
+	(parse_operands): Handle it.
+	(insns): Use it for tmcr and tmrc.
+
+2006-08-02  Petr Salinger  <Petr.Salinger@seznam.cz>
+
+	PR binutils/2983
+	* config/tc-i386.c (md_parse_option): Treat any target starting
+	with elf64_x86_64 as a viable target for the -64 switch.
+	(i386_target_format): For 64-bit ELF flavoured output use
+	ELF_TARGET_FORMAT64.
+	* config/tc-i386.h (ELF_TARGET_FORMAT64): Define.
+
+2006-08-02  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2991
+	* acinclude.m4 (BFD_BINARY_FOPEN): Import this function from
+	bfd/aclocal.m4.
+	* configure.in: Run BFD_BINARY_FOPEN.
+	* configure: Regenerate.
+	* as.h: Look at USE_BINARY_FOPEN to decide which fopen-*.h header
+	file to include.
+
+2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (md_assemble): Don't update
+	cpu_arch_isa_flags.
+
+2006-08-01  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_section_align): Check ELF-ness at runtime.
+
+2006-08-01  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build_lui): Fix comment formatting.
+	(md_apply_fix): Likewise. Unify handling of BFD_RELOC_RVA,
+	BFD_RELOC_32 and BFD_RELOC_16.
+	(s_align, s_cpload, s_cplocal, s_cprestore, s_mips_stab,
+	md_convert_frag, md_obj_end): Fix comment formatting.
+
+2006-07-31  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (md_apply_fix, tc_gen_reloc): Remove special
+	handling for BFD_RELOC_MIPS16_JMP.
+
+2006-07-24  Andreas Schwab  <schwab@suse.de>
+
+	PR/2756
+	* read.c (read_a_source_file): Ignore unknown text after line
+	comment character.  Fix misleading comment.
+
+2006-07-24  Ralk Wildenhues  <Ralf.Wildenhues@gmx.de>
+
+	* doc/all.texi, doc/as.texinfo, doc/c-arc.texi, doc/c-arm.texi,
+	doc/c-avr.texi, doc/c-bfin.texi, doc/c-i386.texi,
+	doc/c-i960.texi, doc/c-m32r.texi, doc/c-m68k.texi,
+	doc/c-mmix.texi, doc/c-pdp11.texi, doc/c-ppc.texi,
+	doc/c-tic54x.texi, doc/c-v850.texi, doc/c-xtensa.texi,
+	doc/c-z80.texi, doc/internals.texi: Fix some typos.
+
+2006-07-21  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (md_longopts): Add -EL and -EB for use by the
+	linker testsuite.
+
+2006-07-20  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (md_parse_option): Don't infer optimisation
+	options from debug options.
+
+2006-07-20  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_fix_adjustable): Handle BFD_RELOC_MIPS16_JMP.
+	(tc_gen_reloc): Handle mips16 jumps to section symbol offsets.
+
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Fix rbit Arm opcode.
+
+2006-07-18  Paul Brook  <paul@codesourcery.com>
+
+	* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
+	(md_convert_frag): Use correct reloc for add_pc.  Use
+	BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
+	(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
+	(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
+
+2006-07-17  Mat Hostetter  <mat@lcs.mit.edu>
+
+	* symbols.c (report_op_error): Fix pasto.  Don't use as_bad_where
+	when file and line unknown.
+
+2006-07-17  Thiemo Seufer  <ths@mips.com>
+
+	* read.c (s_struct): Use IS_ELF.
+	* config/tc-mips.c (md_begin, mips16_mark_labels, mips_ip,
+	md_parse_option, s_change_sec, pic_need_relax, mips_fix_adjustable,
+	tc_gen_reloc, mips_frob_file_after_relocs, s_mips_end, s_mips_frame,
+	s_mips_mask): Likewise.
+
+2006-07-16  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* read.c (s_struct): Handle ELF section changing.
+	* config/tc-mips.c (s_align): Leave enabling auto-align to the
+	generic code.
+	(s_change_sec): Try section changing only if we output ELF.
+
+2006-07-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Remove Cpu086, CpuAthlon and
+	CpuAmdFam10.
+	(smallest_imm_type): Remove Cpu086.
+	(i386_target_format): Likewise.
+
+	* config/tc-i386.h: Remove Cpu086, CpuAthlon and CpuAmdFam10.
+	Update CpuXXX.
+
+2006-07-13 Dwarakanath Rajagopal	<dwarak.rajagopal@amd.com>
+	   Michael Meissner		<michael.meissner@amd.com>
+
+	* config/tc-i386.h (PROCESSOR_AMDFAM10): New processor_type.
+	(CpuSSE4a, CpuABM, CpuAmdFam10): New Cpu directives.
+	* config/tc-i386.c (cpu_arch): Add support for AmdFam10
+	architecture.
+	(i386_align_code): Ditto.
+	(md_assemble_code): Add support for insertq/extrq instructions,
+	swapping as needed for intel syntax.
+	(swap_imm_operands): New function to swap immediate operands.
+	(swap_operands): Deal with 4 operand instructions.
+	(build_modrm_byte): Add support for insertq instruction.
+
+2006-07-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (Size64): Fix a typo in comment.
+
+2006-07-12  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (md_apply_fix): Do not allow the generic code in
+	fixup_segment() to repeat a range check on a value that has
+	already been checked here.
+
+2006-07-07  James E Wilson  <wilson@specifix.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add sb1a.
+
+2006-07-06  Mohammed Adnène Trojette  <adn@diwi.org>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR binutils/2877
+	* doc/as.texi: Fix spelling typo: branchs => branches.
+	* doc/c-m68hc11.texi: Likewise.
+	* config/tc-m68hc11.c: Likewise.
+	Support old spelling of command line switch for backwards
+	compatibility.
+
+2006-07-04  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (s_is_linkonce): New function.
+	(mips16_mark_labels): Don't adjust mips16 symbol addresses for
+	weak, external, and linkonce symbols.
+	(pic_need_relax): Use s_is_linkonce.
+
+2006-06-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* doc/as.texinfo (Org): Remove space.
+	(P2align): Add "@var{abs-expr},".
+
+2006-06-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch_tune_set): New.
+	(cpu_arch_isa): Likewise.
+	(i386_align_code): Use xchg %ax,%ax for 2 byte nop. Optimize
+	nops with short or long nop sequences based on -march=/.arch
+	and -mtune=.
+	(set_cpu_arch): Set cpu_arch_isa.  If cpu_arch_tune_set is 0,
+	set cpu_arch_tune and cpu_arch_tune_flags.
+	(md_parse_option): For -march=, set cpu_arch_isa and set
+	cpu_arch_tune and cpu_arch_tune_flags if cpu_arch_tune_set is
+	0.  Set cpu_arch_tune_set to 1 for -mtune=.
+	(i386_target_format): Don't set cpu_arch_tune.
+
+2006-06-23  Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
+	generated .sbss.* and .gnu.linkonce.sb.*.
+
+2006-06-23  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.h (TC_SEGMENT_INFO_TYPE): Declare per-segment
+	label_list.
+	* config/tc-mips.c (label_list): Define per-segment label_list.
+	(mips_clear_insn_labels, mips_move_labels, mips16_mark_labels,
+	append_insn, s_align, s_cons, s_float_cons, s_gpword, s_gpdword,
+	mips_from_file_after_relocs, mips_define_label): Use per-segment
+	label_list.
+
+2006-06-22  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (ISA_SUPPORTS_MIPS16E): New macro.
+	(append_insn): Use it.
+	(md_apply_fix): Whitespace formatting.
+	(md_begin, append_insn, macro, macro2, mips16_immed, mips_align,
+	mips16_extended_frag): Remove register specifier.
+	(md_convert_frag): Likewise. Use TRUE ans FALSE instead of numeric
+	constants.
+
+2006-06-21  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New.  Parse
+	a directive saving VFP registers for ARMv6 or later.
+	(s_arm_unwind_save): Add parameter arch_v6 and call
+	s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
+	appropriate.
+	(md_pseudo_table): Add entry for new "vsave" directive.
+	* doc/c-arm.texi: Correct error in example for "save"
+	directive (fstmdf -> fstmdx).  Also document "vsave" directive.
+
+2006-06-18  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+	    Anatoly Sokolov <aesok@post.ru>
+
+	* config/tc-avr.c (mcu_types): Add support for atmega165p, atmega169p
+	and atmega644p devices. Rename atmega164/atmega324 devices to
+	atmega164p/atmega324p.
+	* doc/c-avr.texi: Document new mcu and arch options.
+
+2006-06-17  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (enum parse_operand_result): Move outside of
+	#ifdef OBJ_ELF so that non-ELF targeted ARM ports can build.
+
+2006-06-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.h (processor_type): New.
+	(arch_entry): Add type.
+
+	* config/tc-i386.c (cpu_arch_tune): New.
+	(cpu_arch_tune_flags): Likewise.
+	(cpu_arch_isa_flags): Likewise.
+	(cpu_arch): Updated.
+	(set_cpu_arch): Also update cpu_arch_isa_flags.
+	(md_assemble): Update cpu_arch_isa_flags.
+	(OPTION_MARCH): New.
+	(OPTION_MTUNE): Likewise.
+	(md_longopts): Add -march= and -mtune=.
+	(md_parse_option): Support -march= and -mtune=.
+	(md_show_usage): Add -march=CPU/-mtune=CPU.
+	(i386_target_format): Also update cpu_arch_isa_flags,
+	cpu_arch_tune and cpu_arch_tune_flags.
+
+	* doc/as.texinfo: Add -march=CPU/-mtune=CPU.
+
+	* doc/c-i386.texi: Document -march=CPU/-mtune=CPU.
+
+2006-06-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* config/tc-arm.c (enum parse_operand_result): New.
+	(struct group_reloc_table_entry): New.
+	(enum group_reloc_type): New.
+	(group_reloc_table): New array.
+	(find_group_reloc_table_entry): New function.
+	(parse_shifter_operand_group_reloc): New function.
+	(parse_address_main): New function, incorporating code
+	from the old parse_address function.  To be used via...
+	(parse_address): wrapper for parse_address_main; and
+	(parse_address_group_reloc): new function, likewise.
+	(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
+	OP_ADDRGLDRS, OP_ADDRGLDC.
+	(parse_operands): Support for these new operand codes.
+	New macro po_misc_or_fail_no_backtrack.
+	(encode_arm_cp_address): Preserve group relocations.
+	(insns): Modify to use the above operand codes where group
+	relocations are permitted.
+	(md_apply_fix): Handle the group relocations
+	ALU_PC_G0_NC through LDC_SB_G2.
+	(tc_gen_reloc): Likewise.
+	(arm_force_relocation): Leave group relocations for the linker.
+	(arm_fix_adjustable): Likewise.
+
+2006-06-15  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...
+	(do_neon_ldr_str): Always defer to VFP encoding routines, which handle
+	relocs properly.
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (process_suffix): Don't add rex64 for
+	"xchg %rax,%rax".
+
+2006-06-09  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (mips_ip): Maintain argument count.
+
+2006-06-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-iq2000.c: Include sb.h.
+
+2006-06-08  Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mips.c (mips_pseudo_table): Add "origin" and "repeat"
+	aliases for better compatibility with SGI tools.
+
+2006-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete.
+	* Makefile.am (GASLIBS): Expand @BFDLIB@.
+	(BFDVER_H): Delete.
+	(OBJS): Expand @ALL_OBJ_DEPS@.  Depend on all fopen-*.h variants.
+	(obj-aout.o): Depend on $(DEP_@target_get_type@_aout)
+	(obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly.
+	Run "make dep-am".
+	* dep-in.sed: Don't substitute bfdver.h.  Do remove symcat.h.
+	* Makefile.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* configure: Regenerate.
+
+2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* po/Make-in (pdf, ps): New dummy targets.
+
+2006-06-07  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (stdarg.h): include.
+	(arm_it): Add uncond_value field. Add isvec and issingle to operand
+	array.
+	(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
+	REG_TYPE_NSDQ (single, double or quad vector reg).
+	(reg_expected_msgs): Update.
+	(BAD_FPU): Add macro for unsupported FPU instruction error.
+	(parse_neon_type): Support 'd' as an alias for .f64.
+	(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
+	sets of registers.
+	(parse_vfp_reg_list): Don't update first arg on error.
+	(parse_neon_mov): Support extra syntax for VFP moves.
+	(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
+	OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
+	(parse_operands): Support isvec, issingle operands fields, new parse
+	codes above.
+	(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
+	msr variants.
+	(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
+	(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
+	(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
+	(NEON_SHAPE_DEF): New macro. Define table of possible instruction
+	shapes.
+	(neon_shape): Redefine in terms of above.
+	(neon_shape_class): New enumeration, table of shape classes.
+	(neon_shape_el): New enumeration. One element of a shape.
+	(neon_shape_el_size): Register widths of above, where appropriate.
+	(neon_shape_info): New struct. Info for shape table.
+	(neon_shape_tab): New array.
+	(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
+	(neon_check_shape): Rewrite as...
+	(neon_select_shape): New function to classify instruction shapes,
+	driven by new table neon_shape_tab array.
+	(neon_quad): New function. Return 1 if shape should set Q flag in
+	instructions (or equivalent), 0 otherwise.
+	(type_chk_of_el_type): Support F64.
+	(el_type_of_type_chk): Likewise.
+	(neon_check_type): Add support for VFP type checking (VFP data
+	elements fill their containing registers).
+	(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
+	in thumb mode for VFP instructions.
+	(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
+	and encode the current instruction as if it were that opcode.
+	(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
+	arguments, call function in PFN.
+	(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
+	(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
+	(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
+	(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
+	(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
+	Redirect Neon-syntax VFP instructions to VFP instruction handlers.
+	(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
+	(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
+	(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
+	(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
+	(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
+	(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
+	(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
+	(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
+	(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
+	neon_quad.
+	(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
+	between VFP and Neon turns out to belong to Neon. Perform
+	architecture check and fill in condition field if appropriate.
+	(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
+	(do_neon_cvt): Add support for VFP variants of instructions.
+	(neon_cvt_flavour): Extend to cover VFP conversions.
+	(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
+	vmov variants.
+	(do_neon_ldr_str): Handle single-precision VFP load/store.
+	(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
+	NS_NULL not NS_IGNORE.
+	(opcode_tag): Add OT_csuffixF for operands which either take a
+	conditional suffix, or have 0xF in the condition field.
+	(md_assemble): Add support for OT_csuffixF.
+	(NCE): Replace macro with...
+	(NCE_tag, NCE, NCEF): New macros.
+	(nCE): Replace macro with...
+	(nCE_tag, nCE, nCEF): New macros.
+	(insns): Add support for VFP insns or VFP versions of insns msr,
+	mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
+	vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
+	vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
+	VFP/Neon insns together.
+
+2006-06-07  Alan Modra  <amodra@bigpond.net.au>
+	    Ladislav Michl  <ladis@linux-mips.org>
+
+	* app.c: Don't include headers already included by as.h.
+	* as.c: Likewise.
+	* atof-generic.c: Likewise.
+	* cgen.c: Likewise.
+	* dwarf2dbg.c: Likewise.
+	* expr.c: Likewise.
+	* input-file.c: Likewise.
+	* input-scrub.c: Likewise.
+	* macro.c: Likewise.
+	* output-file.c: Likewise.
+	* read.c: Likewise.
+	* sb.c: Likewise.
+	* config/bfin-lex.l: Likewise.
+	* config/obj-coff.h: Likewise.
+	* config/obj-elf.h: Likewise.
+	* config/obj-som.h: Likewise.
+	* config/tc-arc.c: Likewise.
+	* config/tc-arm.c: Likewise.
+	* config/tc-avr.c: Likewise.
+	* config/tc-bfin.c: Likewise.
+	* config/tc-cris.c: Likewise.
+	* config/tc-d10v.c: Likewise.
+	* config/tc-d30v.c: Likewise.
+	* config/tc-dlx.h: Likewise.
+	* config/tc-fr30.c: Likewise.
+	* config/tc-frv.c: Likewise.
+	* config/tc-h8300.c: Likewise.
+	* config/tc-hppa.c: Likewise.
+	* config/tc-i370.c: Likewise.
+	* config/tc-i860.c: Likewise.
+	* config/tc-i960.c: Likewise.
+	* config/tc-ip2k.c: Likewise.
+	* config/tc-iq2000.c: Likewise.
+	* config/tc-m32c.c: Likewise.
+	* config/tc-m32r.c: Likewise.
+	* config/tc-maxq.c: Likewise.
+	* config/tc-mcore.c: Likewise.
+	* config/tc-mips.c: Likewise.
+	* config/tc-mmix.c: Likewise.
+	* config/tc-mn10200.c: Likewise.
+	* config/tc-mn10300.c: Likewise.
+	* config/tc-msp430.c: Likewise.
+	* config/tc-mt.c: Likewise.
+	* config/tc-ns32k.c: Likewise.
+	* config/tc-openrisc.c: Likewise.
+	* config/tc-ppc.c: Likewise.
+	* config/tc-s390.c: Likewise.
+	* config/tc-sh.c: Likewise.
+	* config/tc-sh64.c: Likewise.
+	* config/tc-sparc.c: Likewise.
+	* config/tc-tic30.c: Likewise.
+	* config/tc-tic4x.c: Likewise.
+	* config/tc-tic54x.c: Likewise.
+	* config/tc-v850.c: Likewise.
+	* config/tc-vax.c: Likewise.
+	* config/tc-xc16x.c: Likewise.
+	* config/tc-xstormy16.c: Likewise.
+	* config/tc-xtensa.c: Likewise.
+	* config/tc-z80.c: Likewise.
+	* config/tc-z8k.c: Likewise.
+	* macro.h: Don't include sb.h or ansidecl.h.
+	* sb.h: Don't include stdio.h or ansidecl.h.
+	* cond.c: Include sb.h.
+	* itbl-lex.l: Include as.h instead of other system headers.
+	* itbl-parse.y: Likewise.
+	* itbl-ops.c: Similarly.
+	* itbl-ops.h: Don't include as.h or ansidecl.h.
+	* config/bfin-defs.h: Don't include bfd.h or as.h.
+	* config/bfin-parse.y: Include as.h instead of other system headers.
+
+2006-06-06  Ben Elliston  <bje@au.ibm.com>
+	    Anton Blanchard  <anton@samba.org>
+
+	* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
+	(md_show_usage): Document it.
+	(ppc_setup_opcodes): Test power6 opcode flag bits.
+	* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
+
+2006-06-06  Thiemo Seufer  <ths@mips.com>
+            Chao-ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
+	(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
+	(macro_build): Update comment.
+	(mips_ip): Allow DSP64 instructions for MIPS64R2.
+	(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
+	CPU_HAS_MDMX.
+	(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
+	MIPS_CPU_ASE_MDMX flags for sb1.
+
+2006-06-05  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew
+	appropriate.
+	(mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate.
+	(mips_ip): Make overflowed/underflowed constant arguments in DSP
+	and MT instructions a fatal error. Use INSERT_OPERAND where
+	appropriate. Improve warnings for break and wait code overflows.
+	Use symbolic constant of OP_MASK_COPZ.
+	(mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate.
+
+2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* po/Make-in (top_builddir): Define.
+
+2006-06-02  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* doc/Makefile.am (TEXI2DVI): Define.
+	* doc/Makefile.in: Regenerate.
+	* doc/c-arc.texi: Fix typo.
+
+2006-06-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-ieee.c: Delete.
+	* config/obj-ieee.h: Delete.
+	* Makefile.am (OBJ_FORMATS): Remove ieee.
+	(OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly.
+	(obj-ieee.o): Remove rule.
+	* Makefile.in: Regenerate.
+	* configure.in (atof): Remove tahoe.
+	(OBJ_MAYBE_IEEE): Don't define.
+	* configure: Regenerate.
+	* config.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL
+	and LIBINTL_DEP everywhere.
+	(INTLLIBS): Remove.
+	(INCLUDES, DEP_INCLUDES): Use @INCINTL@.
+	* acinclude.m4: Include new gettext macros.
+	* configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
+	Remove local code for po/Makefile.
+	* Makefile.in, configure, doc/Makefile.in: Regenerated.
+
+2006-05-30  Nick Clifton  <nickc@redhat.com>
+
+	* po/es.po: Updated Spanish translation.
+
+2006-05-06  Denis Chertykov  <denisc@overta.ru>
+
+	* doc/c-avr.texi: New file.
+	* doc/Makefile.am (CPU_DOCS): Add c-avr.texi
+	* doc/all.texi: Set AVR
+	* doc/as.texinfo: Include c-avr.texi
+
+2006-05-28  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (check_macfunc): Loose the condition of
+	calling check_multiply_halfregs ().
+
+2006-05-25  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (asm_1): Better check and deal with
+	vector and scalar Multiply 16-Bit Operands instructions.
+
+2006-05-24  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-hppa.c: Convert to ISO C90 format.
+	* config/tc-hppa.h: Likewise.
+
+2006-05-24  Carlos O'Donell  <carlos@systemhalted.org>
+	    Randolph Chung  <randolph@tausq.org>
+
+	* config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff,
+	is_tls_ieoff, is_tls_leoff): Define.
+	(fix_new_hppa): Handle TLS.
+	(cons_fix_new_hppa): Likewise.
+	(pa_ip): Likewise.
+	(md_apply_fix): Handle TLS relocs.
+	* config/tc-hppa.h (hppa_fix_adjustable): Handle TLS.
+
+2006-05-24  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561.
+
+2006-05-23  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	[ gas/ChangeLog ]
+	* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename.
+	(ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS,
+	ISA_HAS_MXHC1): New macros.
+	(HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of
+	ISA_HAS_64BIT_REGS.  Formatting fixes.  Improved comments.
+	(mips_cpu_info): Change to use combined ASE/IS_ISA flag.
+	(MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP,
+	MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines.
+	(mips_after_parse_args): Change default handling of float register
+	size to account for 32bit code with 64bit FP. Better sanity checking
+	of ISA/ASE/ABI option combinations.
+	(s_mipsset): Support switching of GPR and FPR sizes via
+	.set {g,f}p={32,64,default}. Better sanity checking for .set ASE
+	options.
+	(mips_elf_final_processing): We should record the use of 64bit FP
+	registers in 32bit code but we don't, because ELF header flags are
+	a scarce ressource.
+	(mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE
+	extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef,
+	24kex, 34kc, 34kf, 34kx, 25kf CPU definitions.
+	(mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA.
+	* doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document
+	missing -march options. Document .set arch=CPU. Move .set smartmips
+	to ASE page. Use @code for .set FOO examples.
+
+2006-05-23  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/tc-bfin.c (bfin_start_line_hook): Bump line counters
+	if needed.
+
+2006-05-23  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-defs.h (bfin_equals): Remove declaration.
+	* config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr".
+	* config/tc-bfin.c (bfin_name_is_register): Remove.
+	(bfin_equals): Remove.
+	* config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1.
+	(bfin_name_is_register): Remove declaration.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define.
+	(mips_oddfpreg_ok): New function.
+	(mips_ip): Use it.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare.
+	* config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS,
+	ISA_HAS_DROR, ISA_HAS_ROR): Reformat.
+	(regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC,
+	RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK,
+	RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES,
+	FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES,
+	N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES,
+	SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES,
+	MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names,
+	reg_names_o32, reg_names_n32n64): Define register classes.
+	(reg_lookup): New function, use register classes.
+	(md_begin): Reserve register names in the symbol table. Simplify
+	OBJ_ELF defines.
+	(mips_ip): Fix comment formatting. Handle symbolic COP0 registers.
+	Use reg_lookup.
+	(mips16_ip): Use reg_lookup.
+	(tc_get_register): Likewise.
+	(tc_mips_regname_to_dw2regnum): New function.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum):
+	Un-constify string argument.
+	* config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum):
+	Likewise.
+	* config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum):
+	Likewise.
+
+2006-05-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
+	cfloat/m68881 to correct architecture before using it.
+
+2006-05-16  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
+	constant values.
+
+2006-05-15  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Use
+	bfd_is_arm_special_symbol_name.
+
+2006-05-15  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next,
+	xg_assemble_vliw_tokens, xtensa_mark_narrow_branches,
+	xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed):
+	Handle errors from calls to xtensa_opcode_is_* functions.
+
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (macro_build): Test for currently active
+	mips16 option.
+	(mips16_ip): Reject invalid opcodes.
+
+2006-05-11  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* doc/as.texinfo: Rename "Index" to "AS Index",
+	and "ABORT" to "ABORT (COFF)".
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_half): New function.
+	(operand_parse_code): Remove OP_Iffff.  Add OP_HALF.
+	(parse_operands): Ditto.
+	(do_mov16): Reject invalid relocations.
+	(do_t_mov16): Ditto.  Use Thumb reloc numbers.
+	(insns): Replace Iffff with HALF.
+	(md_apply_fix): Add MOVW and MOVT relocs.
+	(tc_gen_reloc): Ditto.
+	* doc/c-arm.texi: Document relocation operators
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols.
+
+2006-05-11  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (append_insn): Don't check the range of j or
+	jal addresses.
+
+2006-05-11  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* config/tc-arm.c (md_pcrel_from_section): Force a bias for
+	relocs against external symbols for WinCE targets.
+	(md_apply_fix): Likewise.
+
+2006-05-09  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (append_insn): Only warn about an out-of-range
+	j or jal address.
+
+2006-05-09  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups
+	against symbols which are not going to be placed into the symbol
+	table.
+
+2006-05-09  Ben Elliston  <bje@au.ibm.com>
+
+	* expr.c (operand): Remove `if (0 && ..)' statement and
+	subsequently unused target_op label.  Collapse `if (1 || ..)'
+	statement.
+	* app.c (do_scrub_chars): Remove unused case 0, as it is handled
+	separately above the switch.
+
+2006-05-08  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2623
+	* config/tc-msp430.c (line_separator_character): Define as |.
+
+2006-05-08  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (mips_set_options): Add ase_smartmips flag.
+	(mips_opts): Likewise.
+	(file_ase_smartmips): New variable.
+	(ISA_HAS_ROR): SmartMIPS implements rotate instructions.
+	(macro_build): Handle SmartMIPS instructions.
+	(mips_ip): Likewise.
+	(md_longopts): Add argument handling for smartmips.
+	(md_parse_options, mips_after_parse_args): Likewise.
+	(s_mipsset): Add .set smartmips support.
+	(md_show_usage): Document -msmartmips/-mno-smartmips.
+	* doc/as.texinfo: Document -msmartmips/-mno-smartmips and
+	.set smartmips.
+	* doc/c-mips.texi: Likewise.
+
+2006-05-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (relax_segment): Add pass count arg.  Don't error on
+	negative org/space on first two passes.
+	(relax_seg_info): New struct.
+	(relax_seg, write_object_file): Adjust.
+	* write.h (relax_segment): Update prototype.
+
+2006-05-05  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
+	checking.
+	(do_neon_mov): Enable several VMOV variants for VFP. Add suitable
+	architecture version checks.
+	(insns): Allow overlapping instructions to be used in VFP mode.
+
+2006-05-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2598
+	* config/obj-elf.c (obj_elf_change_section): Allow user
+	specified SHF_ALPHA_GPREL.
+
+2006-05-05  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define.  Disable fixups
+	for PMEM related expressions.
+
+2006-05-05  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/2582
+	* dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro.  Handles the
+	insertion of a directory separator character into a string at a
+	given offset.  Uses heuristics to decide when to use a backslash
+	character rather than a forward-slash character.
+	(dwarf2_directive_loc): Use the macro.
+	(out_debug_info): Likewise.
+
+2006-05-05  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (macro_build): Add case 'k' to handle cache
+	instruction.
+	(macro): Add new case M_CACHE_AB.
+
+2006-05-04  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated.
+	(opcode_lookup): Issue a warning for opcode with
+	OT_cinfix3_deprecated.  Otherwise treat OT_cinfix3_deprecated
+	identical to OT_cinfix3.
+	(TxC3w, TC3w, tC3w): New.
+	(insns): Use tC3w and TC3w for comparison instructions with
+	's' suffix.
+
+2006-05-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.h (struct frchain): Delete frch_seg.
+	(frchain_root): Delete.
+	(seg_info): Define as macro.
+	* subsegs.c (frchain_root): Delete.
+	(abs_seg_info, und_seg_info, absolute_frchain): Delete.
+	(subsegs_begin, subseg_change): Adjust for above.
+	(subseg_set_rest): Likewise.  Add new frchain structs to seginfo
+	rather than to one big list.
+	(subseg_get): Don't special case abs, und sections.
+	(subseg_new, subseg_force_new): Don't set frchainP here.
+	(seg_info): Delete.
+	(subsegs_print_statistics): Adjust frag chain control list traversal.
+	* debug.c (dmp_frags):  Likewise.
+	* dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag
+	at frchain_root.  Make use of known frchain ordering.
+	(last_frag_for_seg): Likewise.
+	(get_frag_fix): Likewise.  Add seg param.
+	(process_entries, out_debug_aranges): Adjust get_frag_fix calls.
+	* write.c (chain_frchains_together_1): Adjust for struct frchain.
+	(SUB_SEGMENT_ALIGN): Likewise.
+	(subsegs_finish): Adjust frchain list traversal.
+	* config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise.
+	(xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise.
+	(xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise.
+	(xtensa_fix_b_j_loop_end_frags): Likewise.
+	(xtensa_fix_close_loop_end_frags): Likewise.
+	(xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise.
+	(retrieve_segment_info): Delete frch_seg initialisation.
+
+2006-05-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* subsegs.c (subseg_get): Don't call obj_sec_set_private_data.
+	* config/obj-elf.h (obj_sec_set_private_data): Delete.
+	* config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol.
+	* config/tc-mn10300.c (tc_gen_reloc): Likewise.
+
+2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
+	here.
+	(md_apply_fix3): Multiply offset by 4 here for
+	BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2006-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+	    Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (output_invalid_buf): Change size for
+	unsigned char.
+	* config/tc-tic30.c (output_invalid_buf): Likewise.
+
+	* config/tc-i386.c (output_invalid): Cast none-ascii char to
+	unsigned char.
+	* config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
+	(TEXI2POD): Use AM_MAKEINFOFLAGS.
+	(asconfig.texi): Don't set top_srcdir.
+	* doc/as.texinfo: Don't use top_srcdir.
+	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (output_invalid_buf): Change size to 16.
+	* config/tc-tic30.c (output_invalid_buf): Likewise.
+
+	* config/tc-i386.c (output_invalid): Use snprintf instead of
+	sprintf.
+	* config/tc-ia64.c (declare_register_set): Likewise.
+	(emit_one_bundle): Likewise.
+	(check_dependencies): Likewise.
+	* config/tc-tic30.c (output_invalid): Likewise.
+
+2006-05-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_optimize_expr): New function.
+	* config/tc-arm.h (md_optimize_expr): Define
+	(arm_optimize_expr): Add prototype.
+	(TC_FORCE_RELOCATION_SUB_SAME): Define.
+
+2006-05-02  Ben Elliston  <bje@au.ibm.com>
+
+	* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit
+	field unsigned.
+
+	* sb.h (sb_list_vector): Move to sb.c.
+	* sb.c (free_list): Use type of sb_list_vector directly.
+	(sb_build): Fix off-by-one error in assertion about `size'.
+
+2006-05-01  Ben Elliston  <bje@au.ibm.com>
+
+	* listing.c (listing_listing): Remove useless loop.
+	* macro.c (macro_expand): Remove is_positional local variable.
+	* read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1
+	and simplify surrounding expressions, where possible.
+	(assign_symbol): Likewise.
+	(s_weakref): Likewise.
+	* symbols.c (colon): Likewise.
+
+2006-05-01  James Lemke  <jwlemke@wasabisystems.com>
+
+	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+
+2006-04-30  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (validate_mips_insn): Handling of udi cases.
+	(mips_immed): New table that records various handling of udi
+	instruction patterns.
+	(mips_ip): Adds udi handling.
+
+2006-04-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
+	of list rather than beginning.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to...
+	(is_quarter_float): Rename from above. Simplify slightly.
+	(parse_qfloat_immediate): Parse a "quarter precision" floating-point
+	number.
+	(parse_neon_mov): Parse floating-point constants.
+	(neon_qfloat_bits): Fix encoding.
+	(neon_cmode_for_move_imm): Tweak to use floating-point encoding in
+	preference to integer encoding when using the F32 type.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so
+	zero-initialising structures containing it will lead to invalid types).
+	(arm_it): Add vectype to each operand.
+	(NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias
+	defined field.
+	(neon_typed_alias): New structure. Extra information for typed
+	register aliases.
+	(reg_entry): Add neon type info field.
+	(arm_reg_parse): Remove RTYPE argument (revert to previous arguments).
+	Break out alternative syntax for coprocessor registers, etc. into...
+	(arm_reg_alt_syntax): New function. Alternate syntax handling broken
+	out from arm_reg_parse.
+	(parse_neon_type): Move. Return SUCCESS/FAIL.
+	(first_error): New function. Call to ensure first error which occurs is
+	reported.
+	(parse_neon_operand_type): Parse exactly one type.
+	(NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move.
+	(parse_typed_reg_or_scalar): New function. Handle core of both
+	arm_typed_reg_parse and parse_scalar.
+	(arm_typed_reg_parse): Parse a register with an optional type.
+	(NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar
+	result.
+	(parse_scalar): Parse a Neon scalar with optional type.
+	(parse_reg_list): Use first_error.
+	(parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse.
+	(neon_alias_types_same): New function. Return true if two (alias) types
+	are the same.
+	(parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type
+	of elements.
+	(insert_reg_alias): Return new reg_entry not void.
+	(insert_neon_reg_alias): New function. Insert type/index information as
+	well as register for alias.
+	(create_neon_reg_alias): New function. Parse .dn/.qn directives and
+	make typed register aliases accordingly.
+	(s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start
+	of line.
+	(s_unreq): Delete type information if present.
+	(s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls.
+	(s_arm_unwind_save_mmxwcg): Likewise.
+	(s_arm_unwind_movsp): Likewise.
+	(s_arm_unwind_setfp): Likewise.
+	(parse_shift): Likewise.
+	(parse_shifter_operand): Likewise.
+	(parse_address): Likewise.
+	(parse_tb): Likewise.
+	(tc_arm_regname_to_dw2regnum): Likewise.
+	(md_pseudo_table): Add dn, qn.
+	(parse_neon_mov): Handle typed operands.
+	(parse_operands): Likewise.
+	(neon_type_mask): Add N_SIZ.
+	(N_ALLMODS): New macro.
+	(neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error.
+	(el_type_of_type_chk): Add some safeguards.
+	(modify_types_allowed): Fix logic bug.
+	(neon_check_type): Handle operands with types.
+	(neon_three_same): Remove redundant optional arg handling.
+	(do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm)
+	(do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute)
+	(do_neon_step): Adjust accordingly.
+	(neon_cmode_for_logic_imm): Use first_error.
+	(do_neon_bitfield): Call neon_check_type.
+	(neon_dyadic): Rename to...
+	(neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield
+	to allow modification of type of the destination.
+	(do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+	(do_neon_addsub_if_i, do_neon_mul): Adjust accordingly.
+	(do_neon_compare): Make destination be an untyped bitfield.
+	(neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX.
+	(neon_mul_mac): Return early in case of errors.
+	(neon_move_immediate): Use first_error.
+	(neon_mac_reg_scalar_long): Fix type to include scalar.
+	(do_neon_dup): Likewise.
+	(do_neon_mov): Likewise (in several places).
+	(do_neon_tbl_tbx): Fix type.
+	(do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane)
+	(do_neon_ld_dup): Exit early in case of errors and/or use
+	first_error.
+	(opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL.
+	Handle .dn/.qn directives.
+	(REGDEF): Add zero for reg_entry neon field.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (limits.h): Include.
+	(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
+	(fpu_vfp_v3_or_neon_ext): Declare constants.
+	(neon_el_type): New enumeration of types for Neon vector elements.
+	(neon_type_el): New struct. Define type and size of a vector element.
+	(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
+	instruction.
+	(neon_type): Define struct. The type of an instruction.
+	(arm_it): Add 'vectype' for the current instruction.
+	(isscalar, immisalign, regisimm, isquad): New predicates for operands.
+	(vfp_sp_reg_pos): Rename to...
+	(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
+	tags.
+	(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
+	(Neon D or Q register).
+	(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D
+	register.
+	(GE_OPT_PREFIX_BIG): Define constant, for use in...
+	(my_get_expression): Allow above constant as argument to accept
+	64-bit constants with optional prefix.
+	(arm_reg_parse): Add extra argument to return the specific type of
+	register in when either a D or Q register (REG_TYPE_NDQ) is
+	requested. Can be NULL.
+	(parse_scalar): New function. Parse Neon scalar (vector reg and index).
+	(parse_reg_list): Update for new arm_reg_parse args.
+	(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
+	(parse_neon_el_struct_list): New function. Parse element/structure
+	register lists for VLD<n>/VST<n> instructions.
+	(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
+	(s_arm_unwind_save_mmxwr): Likewise.
+	(s_arm_unwind_save_mmxwcg): Likewise.
+	(s_arm_unwind_movsp): Likewise.
+	(s_arm_unwind_setfp): Likewise.
+	(parse_big_immediate): New function. Parse an immediate, which may be
+	64 bits wide. Put results in inst.operands[i].
+	(parse_shift): Update for new arm_reg_parse args.
+	(parse_address): Likewise. Add parsing of alignment specifiers.
+	(parse_neon_mov): Parse the operands of a VMOV instruction.
+	(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST,
+	OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
+	OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64,
+	OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ.
+	(parse_operands): Handle new codes above.
+	(encode_arm_vfp_sp_reg): Rename to...
+	(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
+	selected VFP version only supports D0-D15.
+	(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
+	(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
+	(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
+	(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
+	encode_arm_vfp_reg name, and allow 32 D regs.
+	(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm)
+	(do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D
+	regs.
+	(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
+	(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
+	constant-load and conversion insns introduced with VFPv3.
+	(neon_tab_entry): New struct.
+	(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
+	those which are the targets of pseudo-instructions.
+	(neon_opc): Enumerate opcodes, use as indices into...
+	(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
+	(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
+	(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
+	(NEON_ENC_DUP): Define meaningful helper macros to look up values in
+	neon_enc_tab.
+	(neon_shape): Enumerate shapes (permitted register widths, etc.) for
+	Neon instructions.
+	(neon_type_mask): New. Compact type representation for type checking.
+	(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
+	permitted type combinations.
+	(N_IGNORE_TYPE): New macro.
+	(neon_check_shape): New function. Check an instruction shape for
+	multiple alternatives. Return the specific shape for the current
+	instruction.
+	(neon_modify_type_size): New function. Modify a vector type and size,
+	depending on the bit mask in argument 1.
+	(neon_type_promote): New function. Convert a given "key" type (of an
+	operand) into the correct type for a different operand, based on a bit
+	mask.
+	(type_chk_of_el_type): New function. Convert a type and size into the
+	compact representation used for type checking.
+	(el_type_of_type_ckh): New function. Reverse of above (only when a
+	single bit is set in the bit mask).
+	(modify_types_allowed): New function. Alter a mask of allowed types
+	based on a bit mask of modifications.
+	(neon_check_type): New function. Check the type of the current
+	instruction against the variable argument list. The "key" type of the
+	instruction is returned.
+	(neon_dp_fixup): New function. Fill in and modify instruction bits for
+	a Neon data-processing instruction depending on whether we're in ARM
+	mode or Thumb-2 mode.
+	(neon_logbits): New function.
+	(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
+	(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
+	(do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes)
+	(neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits)
+	(neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size)
+	(do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su)
+	(do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d)
+	(do_neon_addsub_if_i, neon_exchange_operands, neon_compare)
+	(do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul)
+	(neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul)
+	(do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv)
+	(do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri)
+	(do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun)
+	(do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn)
+	(do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt)
+	(neon_move_immediate, do_neon_mvn, neon_mixed_length)
+	(do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long)
+	(do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull)
+	(do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov)
+	(do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp)
+	(do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est)
+	(do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx)
+	(do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave)
+	(neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup)
+	(do_neon_ldx_stx): New functions. Neon bit encoding and encoding
+	helpers.
+	(parse_neon_type): New function. Parse Neon type specifier.
+	(opcode_lookup): Allow parsing of Neon type specifiers.
+	(REGNUM2, REGSETH, REGSET2): New macros.
+	(reg_names): Add new VFPv3 and Neon registers.
+	(NUF, nUF, NCE, nCE): New macros for opcode table.
+	(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
+	fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd,
+	fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd.
+	Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl,
+	vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif,
+	vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla,
+	vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt,
+	vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr,  v{r}sra, vsli,
+	vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal,
+	vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn,
+	vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup,
+	vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe,
+	vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr,
+	vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd],
+	fto[us][lh][sd].
+	(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
+	(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
+	(arm_option_cpu_value): Add vfp3 and neon.
+	(aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix
+	VFPv1 attribute.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
+	syntax instead of hardcoded opcodes with ".w18" suffixes.
+	(wide_branch_opcode): New.
+	(build_transition): Use it to check for wide branch opcodes with
+	either ".w18" or ".w15" suffixes.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_create_literal_symbol,
+	xg_assemble_literal, xg_assemble_literal_space): Do not set the
+	frag's is_literal flag.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+
+2006-04-23  Kazu Hirata  <kazu@codesourcery.com>
+
+	* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c,
+	config/tc-cris.c, config/tc-crx.c, config/tc-i386.c,
+	config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h,
+	config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c,
+	config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.
+
+2005-04-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for
+	all targets.
+	(md_pseudo_table): Enable .arch, .cpu and .fpu for all targets.
+
+2006-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (CPU_TYPES): Add maxq and mt.  Sort.
+	(CPU_OBJ_VALID): Change sense of COFF test to default to invalid.
+	Make some cpus unsupported on ELF.  Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2006-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in (--enable-targets): Indent help message.
+	* configure: Regenerate.
+
+2006-04-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2533
+	* config/tc-i386.c (i386_immediate): Check illegal immediate
+	register operand.
+
+2006-04-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-i386.c: Formatting.
+	(output_disp, output_imm): ISO C90 params.
+
+	* frags.c (frag_offset_fixed_p): Constify args.
+	* frags.h (frag_offset_fixed_p): Ditto.
+
+	* config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete.
+	(COFF_MAGIC): Delete.
+
+	* config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.
+
+2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* po/POTFILES.in: Regenerated.
+
+2006-04-16  Mark Mitchell  <mark@codesourcery.com>
+
+	* doc/as.texinfo: Mention that some .type syntaxes are not
+	supported on all architectures.
+
+2006-04-14  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
+	instructions when such transformations have been disabled.
+
+2006-04-10  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
+	symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
+	(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
+	decoding the loop instructions.  Remove current_offset variable.
+	(xtensa_fix_short_loop_frags): Likewise.
+	(min_bytes_to_other_loop_end): Remove current_offset argument.
+
+2006-04-09  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* config/tc-z80.c (z80_optimize_expr): Removed.
+	* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
+
+2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+
+	* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
+	attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
+	attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
+	atmega644, atmega329, atmega3290, atmega649, atmega6490,
+	atmega406, atmega640, atmega1280, atmega1281, at90can32,
+	at90can64, at90usb646, at90usb647, at90usb1286 and
+	at90usb1287.
+	Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_operands): Set default error message.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
+	(move_or_literal_pool): Handle Thumb-2 instructions.
+	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
+
+2006-04-07  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 2512.
+	* config/tc-i386.c (match_template): Move 64-bit operand tests
+	inside loop.
+
+2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* po/Make-in: Add install-html target.
+	* Makefile.am: Add install-html and install-html-recursive targets.
+	* Makefile.in: Regenerate.
+	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
+	* configure: Regenerate.
+	* doc/Makefile.am: Add install-html and install-html-am targets.
+	* doc/Makefile.in: Regenerate.
+
+2006-04-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* frags.c (frag_offset_fixed_p): Reinitialise offset before
+	second scan.
+
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
+	(GOTT_BASE, GOTT_INDEX): New.
+	(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
+	GOTT_INDEX when generating VxWorks PIC.
+	* configure.tgt (sparc*-*-vxworks*): Remove this special case;
+	use the generic *-*-vxworks* stanza instead.
+
+2006-04-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 997
+	* frags.c (frag_offset_fixed_p): New function.
+	* frags.h (frag_offset_fixed_p): Declare.
+	* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
+	(resolve_expression): Likewise.
+
+2006-04-03  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
+	of the same length but different numbers of slots.
+
+2006-03-30  Andreas Schwab  <schwab@suse.de>
+
+	* configure.in: Fix help string for --enable-targets option.
+	* configure: Regenerate.
+
+2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
+	(m68k_ip): ... here.  Use for all chips.  Protect against buffer
+	overrun and avoid excessive copying.
+
+	* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
+	m68020_control_regs, m68040_control_regs, m68060_control_regs,
+	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
+	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
+	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
+	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
+	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
+	mcf5282_ctrl, mcfv4e_ctrl): ... these.
+	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
+	(struct m68k_cpu): Change chip field to control_regs.
+	(current_chip): Remove.
+	(control_regs): New.
+	(m68k_archs, m68k_extensions): Adjust.
+	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
+	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
+	(find_cf_chip): Reimplement for new organization of cpu table.
+	(select_control_regs): Remove.
+	(mri_chip): Adjust.
+	(struct save_opts): Save control regs, not chip.
+	(s_save, s_restore): Adjust.
+	(m68k_lookup_cpu): Give deprecated warning when necessary.
+	(m68k_init_arch): Adjust.
+	(md_show_usage): Adjust for new cpu table organization.
+
+2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
+	* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
+	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
+	(any_gotrel): New rule.
+	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
+	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
+	(bfin_pic_ptr): New function.
+	(md_pseudo_table): Add it for ".picptr".
+	(OPTION_FDPIC): New macro.
+	(md_longopts): Add -mfdpic.
+	(md_parse_option): Handle it.
+	(md_begin): Set BFD flags.
+	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
+	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
+	us for GOT relocs.
+	* Makefile.am (bfin-parse.o): Update dependencies.
+	(DEPTC_bfin_elf): Likewise.
+	* Makefile.in: Regenerate.
+
+2006-03-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
+	mcfemac instead of mcfmac.
+
+2006-03-23  Michael Matz  <matz@suse.de>
+
+	* config/tc-i386.c (type_names): Correct placement of 'static'.
+	(reloc): Map some more relocs to their 64 bit counterpart when
+	size is 8.
+	(output_insn): Work around breakage if DEBUG386 is defined.
+	(output_disp): A BFD_RELOC_64 with GOT_symbol as operand also
+	needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or
+	BFD_RELOC_X86_64_GOTPC32.  Also x86-64 handles pcrel addressing
+	different from i386.
+	(output_imm): Ditto.
+	(lex_got): Recognize @PLTOFF and @GOTPLT.  Make @GOT accept also
+	Imm64.
+	(md_convert_frag): Jumps can now be larger than 2GB away, error
+	out in that case.
+	(tc_gen_reloc): New relocs are passed through.  BFD_RELOC_64
+	and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64.
+
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
+	(md_begin): Complain about -G being used for PIC.  Don't change
+	the text, data and bss alignments on VxWorks.
+	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
+	generating VxWorks PIC.
+	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
+	(macro): Likewise, but do not treat la $25 specially for
+	VxWorks PIC, and do not handle jal.
+	(OPTION_MVXWORKS_PIC): New macro.
+	(md_longopts): Add -mvxworks-pic.
+	(md_parse_option): Don't complain about using PIC and -G together here.
+	Handle OPTION_MVXWORKS_PIC.
+	(md_estimate_size_before_relax): Always use the first relaxation
+	sequence on VxWorks.
+	* config/tc-mips.h (VXWORKS_PIC): New.
+
+2006-03-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
+
+2006-03-21  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
+	(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
+	(get_loop_align_size): New.
+	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
+	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
+	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
+	(get_noop_aligned_address): Use get_loop_align_size.
+	(get_aligned_diff): Likewise.
+
+2006-03-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
+
+2006-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
+	(do_t_branch): Encode branches inside IT blocks as unconditional.
+	(do_t_cps): New function.
+	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
+	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
+	(opcode_lookup): Allow conditional suffixes on all instructions in
+	Thumb mode.
+	(md_assemble): Advance condexec state before checking for errors.
+	(insns): Use do_t_cps.
+
+2006-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
+	outputting the insn.
+
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* config/tc-vax.c: Update copyright year.
+	* config/tc-vax.h: Likewise.
+
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* config/tc-vax.c (md_chars_to_number): Used only locally, so
+	make it static.
+	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
+
+2006-03-17  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Add ldm and stm.
+
+2006-03-17  Ben Elliston  <bje@au.ibm.com>
+
+	PR gas/2446
+	* doc/as.texinfo (Ident): Document this directive more thoroughly.
+
+2006-03-16  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Add "svc".
+
+2006-03-13  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
+	flag and avoid double underscore prefixes.
+
+2006-03-10  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_begin): Handle EABIv5.
+	(arm_eabis): Add EF_ARM_EABI_VER5.
+	* doc/c-arm.texi: Document -meabi=5.
+
+2006-03-10  Ben Elliston  <bje@au.ibm.com>
+
+	* app.c (do_scrub_chars): Simplify string handling.
+
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+	    Paul Brook  <paul@codesourcery.com>
+	    Ricardo Anguiano  <anguiano@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
+	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
+	R_ARM_ABS12 reloc.
+	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
+	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
+	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
+
+2006-03-06  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
+	even when using the text-section-literals option.
+
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
+	and cf.
+	(m68k_ip): <case 'J'> Check we have some control regs.
+	(md_parse_option): Allow raw arch switch.
+	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
+	whether 68881 or cfloat was meant by -mfloat.
+	(md_show_usage): Adjust extension display.
+	(m68k_elf_final_processing): Adjust.
+
+2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* config/tc-avr.c (avr_mod_hash_value): New function.
+	(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
+	BFD_RELOC_MS8_LDI for hlo8() and hhi8()
+	(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
+	instead of int avr_ldi_expression: use avr_mod_hash_value instead
+	of (int).
+	(tc_gen_reloc): Handle substractions of symbols, if possible do
+	fixups, abort otherwise.
+	* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
+	tc_fix_adjustable): Define.
+
+2006-03-02  James E Wilson  <wilson@specifix.com>
+
+	* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
+	change the template, then clear md.slot[curr].end_of_insn_group.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	PR/1070
+	* macro.c (getstring): Don't treat parentheses special anymore.
+	(get_any_string): Don't consider '(' and ')' as quoting anymore.
+	Special-case '(', ')', '[', and ']' when dealing with non-quoting
+	characters.
+
+2006-02-28  Mat <mat@csail.mit.edu>
+
+	* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
+
+2006-02-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
+	field.
+	(CFI_signal_frame): Define.
+	(cfi_pseudo_table): Add .cfi_signal_frame.
+	(dot_cfi): Handle CFI_signal_frame.
+	(output_cie): Handle cie->signal_frame.
+	(select_cie_for_fde): Don't share CIE if signal_frame flag is
+	different.  Copy signal_frame from FDE to newly created CIE.
+	* doc/as.texinfo: Document .cfi_signal_frame.
+
+2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* doc/Makefile.am: Add html target.
+	* doc/Makefile.in: Regenerate.
+	* po/Make-in: Add html target.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (output_insn): Support Intel Merom New
+	Instructions.
+
+	* config/tc-i386.h (CpuMNI): New.
+	(CpuUnknownFlags): Add CpuMNI.
+
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+	* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
+	(hpriv_reg_table): New table for hyperprivileged registers.
+	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
+	register encoding.
+
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
+	(tc_gen_reloc): Don't define.
+	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
+	(OPTION_LINKRELAX): New.
+	(md_longopts): Add it.
+	(m32c_relax): New.
+	(md_parse_options): Set it.
+	(md_assemble): Emit relaxation relocs as needed.
+	(md_convert_frag): Emit relaxation relocs as needed.
+	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
+	(m32c_apply_fix): New.
+	(tc_gen_reloc): New.
+	(m32c_force_relocation): Force out jump relocs when relaxing.
+	(m32c_fix_adjustable): Return false if relaxing.
+
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
+	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
+	(struct asm_barrier_opt): Define.
+	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
+	(parse_psr): Accept V7M psr names.
+	(parse_barrier): New function.
+	(enum operand_parse_code): Add OP_oBARRIER.
+	(parse_operands): Implement OP_oBARRIER.
+	(do_barrier): New function.
+	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
+	(do_t_cpsi): Add V7M restrictions.
+	(do_t_mrs, do_t_msr): Validate V7M variants.
+	(md_assemble): Check for NULL variants.
+	(v7m_psrs, barrier_opt_names): New tables.
+	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
+	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
+	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
+	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
+	(struct cpu_arch_ver_table): Define.
+	(cpu_arch_ver): New.
+	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
+	Tag_CPU_arch_profile.
+	* doc/c-arm.texi: Document new cpu and arch options.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c: Update copyright years.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (specify_resource): Add the rule 17 from
+	SDM 2.2.
+
+2005-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_pld): Remove incorrect write to
+	inst.instruction.
+	(encode_thumb32_addr_mode): Use correct operand.
+
+2006-02-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* Makefile.am: Add xc16x related entry.
+	* Makefile.in: Regenerate.
+	* configure.in: Added xc16x related entry.
+	* configure: Regenerate.
+	* config/tc-xc16x.h: New file
+	* config/tc-xc16x.c: New file
+	* doc/c-xc16x.texi: New file for xc16x
+	* doc/all.texi: Entry for xc16x
+	* doc/Makefile.texi: Added c-xc16x.texi
+	* NEWS: Announce the support for the new target.
+
+2006-02-16  Nick Hudson  <nick.hudson@dsl.pipex.com>
+
+	* configure.tgt: set emulation for mips-*-netbsd*
+
+2006-02-14  Jakub Jelinek  <jakub@redhat.com>
+
+	* config.in: Rebuilt.
+
+2006-02-13  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
+	from 1, not 0, in error messages.
+	(md_assemble): Simplify special-case check for ENTRY instructions.
+	(tinsn_has_invalid_symbolic_operands): Do not include opcode and
+	operand in error message.
+
+2006-02-13  Joseph S. Myers  <joseph@codesourcery.com>
+
+	* configure.tgt (arm-*-linux-gnueabi*): Change to
+	arm-*-linux-*eabi*.
+
+2006-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-crx.c (check_range): Ensure that the sign bit of a
+	32-bit value is propagated into the upper bits of a 64-bit long.
+
+	* config/tc-arc.c (init_opcode_tables): Fix cast.
+	(arc_extoper, md_operand): Likewise.
+
+2006-02-09  David Heine  <dlheine@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
+	each relaxation step.
+
+2006-02-09  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* configure.in (CHECK_DECLS): Add vsnprintf.
+	* configure: Regenerate.
+	* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
+	include/declare here, but...
+	* as.h: Move code detecting VARARGS idiom to the top.
+	(errno.h, stdarg.h, varargs.h, va_list): ...here.
+	(vsnprintf): Declare if not already declared.
+
+2006-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* as.c (close_output_file): New.
+	(main): Register close_output_file with xatexit before
+	dump_statistics. Don't call output_file_close.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs): New.
+	(not_current_architecture, selected_arch, selected_cpu): New.
+	(m68k_archs, m68k_extensions): New.
+	(archs): Renamed to ...
+	(m68k_cpus): ... here.  Adjust.
+	(n_arches): Remove.
+	(md_pseudo_table): Add arch and cpu directives.
+	(find_cf_chip, m68k_ip): Adjust table scanning.
+	(no_68851, no_68881): Remove.
+	(md_assemble): Lazily initialize.
+	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
+	(md_init_after_args): Move functionality to m68k_init_arch.
+	(mri_chip): Adjust table scanning.
+	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
+	options with saner parsing.
+	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
+	m68k_init_arch): New.
+	(s_m68k_cpu, s_m68k_arch): New.
+	(md_show_usage): Adjust.
+	(m68k_elf_final_processing): Set CF EF flags.
+	* config/tc-m68k.h (m68k_init_after_args): Remove.
+	(tc_init_after_args): Remove.
+	* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
+	(M68k-Directives): Document .arch and .cpu directives.
+
+2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as
+	synonyms for equ and defl.
+	(z80_cons_fix_new): New function.
+	(emit_byte): Disallow relative jumps to absolute locations.
+	(emit_data): Only handle defb, prototype changed, because defb is
+	now handled as pseudo-op rather than an instruction.
+	(instab): Entries for defb,defw,db,dw moved from here...
+	(md_pseudo_table): ... to here, use generic cons() for defw,dw.
+	Add entries for def24,def32,d24,d32.
+	(md_assemble): Improved error handling.
+	(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
+	* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
+	(z80_cons_fix_new): Declare.
+	* doc/c-z80.texi (defb, db): Mention warning on overflow.
+	(def24,d24,def32,d32): New pseudo-ops.
+
+2006-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
+
+2005-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
+	T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
+	T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
+	T2_OPCODE_RSB): Define.
+	(thumb32_negate_data_op): New function.
+	(md_apply_fix): Use it.
+
+2006-01-31  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
+	fields.
+	* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
+	* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
+	subtracted symbols.
+	(relaxation_requirements): Add pfinish_frag argument and use it to
+	replace setting tinsn->record_fix fields.
+	(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
+	and vinsn_to_insnbuf.  Remove references to record_fix and
+	slot_sub_symbols fields.
+	(xtensa_mark_narrow_branches): Delete unused code.
+	(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
+	a symbol.
+	(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
+	record_fix fields.
+	(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
+	(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
+	of the record_fix field.  Simplify error messages for unexpected
+	symbolic operands.
+	(set_expr_symbol_offset_diff): Delete.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+	Richard Earnshaw <rearnsha@arm.com>
+
+	* config/tc-arm.c: Use arm_feature_set.
+	(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
+	arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
+	fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
+	New variables.
+	(insns): Use them.
+	(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
+	md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
+	arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
+	s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
+	feature flags.
+	(arm_legacy_option_table, arm_option_cpu_value_table): New types.
+	(arm_opts): Move old cpu/arch options from here...
+	(arm_legacy_opts): ... to here.
+	(md_parse_option): Search arm_legacy_opts.
+	(arm_cpus, arm_archs, arm_extensions, arm_fpus)
+	(arm_float_abis, arm_eabis): Make const.
+
+2006-01-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
+	in load immediate intruction.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (value_match): Use correct conversion
+	specifications in template string for __FILE__ and __LINE__.
+	(binary): Ditto.
+	(unary): Ditto.
+
+2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce TLS descriptors for i386 and x86_64.
+	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
+	BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
+	BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
+	(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
+	BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
+	displacement bits.
+	(build_modrm_byte): Set up zero modrm for TLS desc calls.
+	(lex_got): Handle @tlsdesc and @tlscall.
+	(md_apply_fix, tc_gen_reloc): Handle the new relocations.
+
+2006-01-11  Nick Clifton  <nickc@redhat.com>
+
+	Fixes for building on 64-bit hosts:
+	* config/tc-avr.c (mod_index): New union to allow conversion
+	between pointers and integers.
+	(md_begin, avr_ldi_expression): Use it.
+	* config/tc-i370.c (md_assemble): Add cast for argument to print
+	statement.
+	* config/tc-tic54x.c (subsym_substitute): Likewise.
+	* config/tc-mn10200.c (md_assemble): Use a union to convert the
+	opindex field of fr_cgen structure into a pointer so that it can
+	be stored in a frag.
+	* config/tc-mn10300.c (md_assemble): Likewise.
+	* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
+	types.
+	* config/tc-v850.c: Replace uses of (int) casts with correct
+	types.
+
+2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2117
+	* symbols.c (snapshot_symbol): Don't change a defined symbol.
+
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR gas/2101
+	* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
+	a local-label reference.
+
+For older changes see ChangeLog-2005
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 08b9842fc6be..670423660d01 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -1,9 +1,7 @@
 ## Process this file with automake to generate Makefile.in
 
-## Work around apparent automake bug.
-INTLLIBS = @INTLLIBS@
-
 AUTOMAKE_OPTIONS = 1.8 cygnus dejagnu
+ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd
 
 SUBDIRS = doc po
 # Automake should figure this out on its own.  It doesn't, because
@@ -15,6 +13,10 @@ tooldir = $(exec_prefix)/$(target_alias)
 YACC = `if [ -f ../bison/bison ] ; then echo ../bison/bison -y -L../bison/bison ; else echo @YACC@ ; fi`
 LEX = `if [ -f ../flex/flex ] ; then echo ../flex/flex ; else echo @LEX@ ; fi`
 
+# We have to set this, because autoconf 2.59 does not substitute YFLAGS.
+# Autoconf 2.61 does, so this can be removed when we upgrade.
+YFLAGS =
+
 WARN_CFLAGS = @WARN_CFLAGS@
 NO_WERROR = @NO_WERROR@
 AM_CFLAGS = $(WARN_CFLAGS)
@@ -33,7 +35,7 @@ ATOF_TARG_C = $(srcdir)/config/atof-@atof@.c
 ATOF_TARG_O = atof-@atof@.o
 
 # use @target_cpu_type@ for refering to configured target name
-IT_HDRS=itbl-parse.h $(srcdir)/itbl-ops.h 
+IT_HDRS=itbl-parse.h $(srcdir)/itbl-ops.h
 IT_SRCS=itbl-parse.c itbl-lex.c $(srcdir)/itbl-ops.c
 IT_DEPS=$(srcdir)/itbl-parse.y $(srcdir)/itbl-lex.l $(srcdir)/config/itbl-@target_cpu_type@.h
 IT_OBJS=itbl-parse.o itbl-lex.o itbl-ops.o
@@ -46,6 +48,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -55,22 +58,25 @@ CPU_TYPES = \
 	frv \
 	h8300 \
 	hppa \
-	ia64 \
 	i370 \
 	i386 \
 	i860 \
 	i960 \
+	ia64 \
 	ip2k \
 	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
+	maxq \
 	mcore \
+	mep \
 	mips \
 	mmix \
 	mn10200 \
 	mn10300 \
 	msp430 \
+	mt \
 	ns32k \
 	openrisc \
 	or32 \
@@ -78,16 +84,18 @@ CPU_TYPES = \
 	pj \
 	ppc \
 	s390 \
+	score \
 	sh \
 	sh64 \
 	sparc \
+	spu \
 	tic30 \
 	tic4x \
 	tic54x \
-	vax \
 	v850 \
-	xstormy16 \
+	vax \
 	xc16x \
+	xstormy16 \
 	xtensa \
 	z80 \
 	z8k
@@ -100,8 +108,7 @@ OBJ_FORMATS = \
 	coff \
 	ecoff \
 	elf \
-	evax \
-	ieee
+	evax
 
 # This is an sh case which sets valid according to whether the CPU
 # type in the shell variable c and the OS type in the shell variable o
@@ -116,16 +123,20 @@ CPU_OBJ_VALID = \
 	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	coff) valid=yes; \
+	coff) \
 	  case $$c in \
-	  cris | i860 | mmix | sh64) \
-	    valid= ;; \
+	  arm | h8300 | i386 | i960 | m68k | maxq | mcore | mips | or32 \
+		| ppc | sh | sparc | tic* | xscale | z80 | z8k) \
+	    valid=yes ;; \
 	  esac ;; \
 	ecoff) \
 	  case $$c in \
 	  mips | alpha) valid=yes ;; \
 	  esac ;; \
-	elf) valid=yes ;; \
+	elf) valid=yes ; \
+	  case $$c in \
+	  maxq | ns32k | tic* | z80 | z8k) valid= ;; \
+	  esac ;; \
 	evax) \
 	  case $$c in \
 	  alpha) valid=yes ;; \
@@ -230,6 +241,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -250,6 +262,7 @@ TARGET_CPU_CFILES = \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
 	config/tc-mcore.c \
+	config/tc-mep.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
 	config/tc-mn10200.c \
@@ -262,9 +275,11 @@ TARGET_CPU_CFILES = \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
+	config/tc-score.c \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
+	config/tc-spu.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
 	config/tc-vax.c \
@@ -281,6 +296,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -301,6 +317,7 @@ TARGET_CPU_HFILES = \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
 	config/tc-mcore.h \
+	config/tc-mep.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
 	config/tc-mn10200.h \
@@ -313,9 +330,11 @@ TARGET_CPU_HFILES = \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
+	config/tc-score.h \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
+	config/tc-spu.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
 	config/tc-vax.h \
@@ -334,7 +353,6 @@ OBJ_FORMAT_CFILES = \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-ieee.c \
 	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
@@ -343,7 +361,6 @@ OBJ_FORMAT_HFILES = \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-ieee.h \
 	config/obj-som.h
 
 # Emulation header files in config
@@ -381,7 +398,8 @@ TARG_ENV_HFILES = \
 	config/te-sun3.h \
 	config/te-svr4.h \
 	config/te-symbian.h \
-	config/te-tmips.h
+	config/te-tmips.h \
+	config/te-wince-pe.h
 
 # Multi files in config
 
@@ -464,13 +482,18 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config \
+	-I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd \
+	-I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. \
+	-I$${srcdir}/../bfd @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
 
 DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
@@ -478,25 +501,22 @@ DEP_FLAGS = -DOBJ_MAYBE_ELF \
 # How to link with both our special library facilities
 # and the system's installed libraries.
 
-GASLIBS = @OPCODES_LIB@ @BFDLIB@ ../libiberty/libiberty.a
+GASLIBS = @OPCODES_LIB@ ../bfd/libbfd.la ../libiberty/libiberty.a
 
 # Files to be copied away after each stage in building.
 STAGESTUFF = *.o $(noinst_PROGRAMS)
 
-BFDVER_H = @BFDVER_H@
-
-$(OBJS): @ALL_OBJ_DEPS@
-
 as_new_SOURCES = $(GAS_CFILES)
 as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLLIBS) $(LIBM)
+	$(extra_objects) $(GASLIBS) $(LIBINTL) $(LIBM)
 as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLDEPS)
+	$(extra_objects) $(GASLIBS) $(LIBINTL_DEP)
 
 # Stuff that every object file depends upon.  If anything is removed
 # from this list, remove it from dep-in.sed as well.
-$(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-	$(INCDIR)/progress.h $(INCDIR)/fopen-same.h \
+$(OBJS): ../bfd/bfd.h $(INCDIR)/symcat.h \
+	$(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/progress.h \
+	$(INCDIR)/fopen-same.h $(INCDIR)/fopen-bin.h $(INCDIR)/fopen-vms.h \
 	$(OBJ_FORMAT_H) $(TARG_CPU_H) $(TARG_ENV_H) \
 	as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \
 	frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h
@@ -540,18 +560,16 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 # We need all these explicit rules for the multi stuff.  Because of
 # these rules, we don't need one for OBJ_FORMAT_O.
 
-obj-aout.o : $(srcdir)/config/obj-aout.c
+obj-aout.o : $(srcdir)/config/obj-aout.c $(DEP_@target_cpu_type@_aout)
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-coff.o: $(srcdir)/config/obj-coff.c
+obj-coff.o: $(srcdir)/config/obj-coff.c $(DEP_@target_cpu_type@_coff)
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
-obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
+obj-ecoff.o : $(srcdir)/config/obj-ecoff.c $(DEP_@target_cpu_type@_ecoff)
 	$(COMPILE) -c $(srcdir)/config/obj-ecoff.c
-obj-elf.o : $(srcdir)/config/obj-elf.c
+obj-elf.o : $(srcdir)/config/obj-elf.c $(DEP_@target_cpu_type@_elf)
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-ieee.o : $(srcdir)/config/obj-ieee.c
-	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
@@ -602,7 +620,7 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	  rm -f m68k-parse.y; \
 	else true; fi
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -629,12 +647,12 @@ bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
 itbl-lex.c: $(srcdir)/itbl-lex.l
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -988,582 +1006,443 @@ dep-am: DEP
 .PHONY: dep dep-in dep-am
 
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPTC_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h \
-  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
-DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h subsegs.h \
+  $(INCDIR)/obstack.h struc-symbol.h ecoff.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/elf/alpha.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
-DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
   $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h
-DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
-DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
+DEPTC_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
+DEPTC_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/avr.h
-DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
+DEPTC_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h dwarf2dbg.h
+DEPTC_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/avr.h
-DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
-  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
-  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  struc-symbol.h $(srcdir)/config/bfin-defs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
+  $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
+  dwarf2dbg.h
+DEPTC_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/cris.h dwarf2dbg.h
-DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h
-DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+DEPTC_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/crx.h \
   $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d10v.h \
   $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d10v.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d30v.h
-DEPTC_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
+DEPTC_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d30v.h
-DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/dlx.h
-DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
-DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
-DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
-DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+DEPTC_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/frv-opc.h \
   cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
-  $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
-DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
+DEPTC_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
+DEPTC_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-DEPTC_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+DEPTC_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/hppa.h \
-  dwarf2dbg.h
-DEPTC_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/i370.h
-DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h dwarf2dbg.h
+DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
-DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+DEPTC_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i960.h
-DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
-DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+DEPTC_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
+DEPTC_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h
+DEPTC_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
   $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
-DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
-  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
-  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
+DEPTC_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h ../bfd/bfd_stdint.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
+DEPTC_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
   $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h \
-  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
+DEPTC_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h
-DEPTC_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  subsegs.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
-DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+  $(srcdir)/config/m68k-parse.h
+DEPTC_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+DEPTC_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/opcode/maxq.h
+DEPTC_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/mcore-opc.h $(INCDIR)/safe-ctype.h
+DEPTC_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+DEPTC_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mep-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
+DEPTC_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
   dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+DEPTC_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h
+DEPTC_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h \
+  itbl-ops.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(srcdir)/config/obj-elf.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+DEPTC_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10200.h
-DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/obstack.h
+DEPTC_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
-DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10300.h \
-  dwarf2dbg.h
-DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h
-DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
-DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
+DEPTC_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
+DEPTC_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h
+DEPTC_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mt-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mt-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+DEPTC_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
-DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
-DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPTC_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
-DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
+DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
-  $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
-DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/pdp11.h
-DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
-DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/pj.h
-DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
-DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+DEPTC_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+DEPTC_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/ppc.h
+DEPTC_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h
-DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
+  struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
+DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
-DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
-DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h sb.h macro.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/tic54x.h
-DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h sb.h macro.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
+DEPTC_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/spu-insns.h
+DEPTC_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
+DEPTC_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
+DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h
+DEPTC_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h
-DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
-DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
+  $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h
+DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
+  dwarf2dbg.h
+DEPTC_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/vax.h
-DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
-  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+DEPTC_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
-DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h dwarf2dbg.h
-DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPTC_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h
-DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
-DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h dwarf2dbg.h \
+  $(INCDIR)/elf/xc16x.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
-DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
-DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
+DEPTC_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/tc-xtensa.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
-  dwarf2dbg.h struc-symbol.h
-DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
-DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
-DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/xtensa-config.h
+DEPTC_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPTC_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/../opcodes/z8k-opc.h
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
   $(BFDDIR)/som.h
@@ -1572,483 +1451,364 @@ DEPTC_i386_multi = $(DEPTC_i386_aout) $(DEPTC_i386_coff) \
 DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
-DEPOBJ_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
+DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
+DEPOBJ_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
-DEPOBJ_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h
-DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPOBJ_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
+DEPOBJ_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
-DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
+DEPOBJ_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
-DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/mep.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
+DEPOBJ_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
+DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+DEPOBJ_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
+DEPOBJ_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
+DEPOBJ_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
@@ -2057,354 +1817,309 @@ DEPOBJ_i386_multi = $(DEPOBJ_i386_aout) $(DEPOBJ_i386_coff) \
 DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
 DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
+DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
 DEP_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
-DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h
+DEP_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_arm_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
-DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h
-DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
+DEP_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h
-DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h
-DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
-DEP_d30v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
-DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h
-DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h
-DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
+DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
+DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
+DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
 DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h
-DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h
-DEP_ia64_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/symcat.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
-DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h
+DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h
+DEP_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h
-DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h
-DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h
-DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h
-DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h
-DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+DEP_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h
+DEP_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
-DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h
-DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h
+DEP_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h
+DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
+DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+DEP_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
-DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h
-DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h
-DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h
-DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h
+DEP_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
+DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h
-DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h
+DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+DEP_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h
-DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h
+DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h
-DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
-DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h
+DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h
+DEP_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_sh_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
-DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
+DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 DEP_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+DEP_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h
-DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h
-DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
-DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+DEP_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
+DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h
 DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
   $(DEP_i386_elf)
@@ -2413,66 +2128,52 @@ DEP_mips_multi = $(DEP_mips_coff) $(DEP_mips_ecoff) \
 DEP_cris_multi = $(DEP_cris_aout) $(DEP_cris_elf)
 BMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING ABOVE.
 #MKDEP    DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-app.o: app.c $(INCDIR)/symcat.h
-as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
-atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
-depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
-ecoff.o: ecoff.c $(INCDIR)/symcat.h ecoff.h
-ehopt.o: ehopt.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
+app.o: app.c
+as.o: as.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  sb.h macro.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  ../bfd/bfdver.h
+atof-generic.o: atof-generic.c $(INCDIR)/safe-ctype.h
+cond.o: cond.c sb.h macro.h $(INCDIR)/obstack.h
+depend.o: depend.c
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/safe-ctype.h dwarf2dbg.h \
+  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
-expr.o: expr.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-flonum-copy.o: flonum-copy.c $(INCDIR)/symcat.h
+dw2gencfi.o: dw2gencfi.c dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  subsegs.h $(INCDIR)/obstack.h
+ecoff.o: ecoff.c ecoff.h
+ehopt.o: ehopt.c subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/dwarf2.h
+expr.o: expr.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+flonum-copy.o: flonum-copy.c
 flonum-konst.o: flonum-konst.c
 flonum-mult.o: flonum-mult.c
-frags.o: frags.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-hash.o: hash.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-input-file.o: input-file.c $(INCDIR)/symcat.h input-file.h \
-  $(INCDIR)/safe-ctype.h
-input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
-  sb.h
-listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  $(INCDIR)/safe-ctype.h input-file.h subsegs.h
-literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  sb.h macro.h
-messages.o: messages.c $(INCDIR)/symcat.h
-output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
-read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h $(INCDIR)/symcat.h
-stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-symbols.o: symbols.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h struc-symbol.h
-write.o: write.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h dwarf2dbg.h
-itbl-ops.o: itbl-ops.c itbl-ops.h $(INCDIR)/symcat.h
-e-crisaout.o: $(srcdir)/config/e-crisaout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-criself.o: $(srcdir)/config/e-criself.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386aout.o: $(srcdir)/config/e-i386aout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386coff.o: $(srcdir)/config/e-i386coff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386elf.o: $(srcdir)/config/e-i386elf.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipself.o: $(srcdir)/config/e-mipself.c $(INCDIR)/symcat.h \
-  emul-target.h
+frags.o: frags.c subsegs.h $(INCDIR)/obstack.h
+hash.o: hash.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+input-file.o: input-file.c input-file.h $(INCDIR)/safe-ctype.h
+input-scrub.o: input-scrub.c input-file.h sb.h
+listing.o: listing.c $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  input-file.h subsegs.h
+literal.o: literal.c subsegs.h $(INCDIR)/obstack.h
+macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+messages.o: messages.c
+output-file.o: output-file.c output-file.h
+read.o: read.c $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  sb.h macro.h ecoff.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+sb.o: sb.c sb.h
+stabs.o: stabs.c $(INCDIR)/obstack.h subsegs.h ecoff.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
+subsegs.o: subsegs.c subsegs.h $(INCDIR)/obstack.h
+symbols.o: symbols.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  subsegs.h struc-symbol.h
+write.o: write.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  dwarf2dbg.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+itbl-ops.o: itbl-ops.c itbl-ops.h
+e-crisaout.o: $(srcdir)/config/e-crisaout.c emul-target.h
+e-criself.o: $(srcdir)/config/e-criself.c emul-target.h
+e-i386aout.o: $(srcdir)/config/e-i386aout.c emul-target.h
+e-i386coff.o: $(srcdir)/config/e-i386coff.c emul-target.h
+e-i386elf.o: $(srcdir)/config/e-i386elf.c emul-target.h
+e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c emul-target.h
+e-mipself.o: $(srcdir)/config/e-mipself.c emul-target.h
 $(OBJS): $(DEP_@target_cpu_type@_@obj_format@)
 $(TARG_CPU_O): $(DEPTC_@target_cpu_type@_@obj_format@)
 $(OBJ_FORMAT_O): $(DEPOBJ_@target_cpu_type@_@obj_format@)
diff --git a/gas/Makefile.in b/gas/Makefile.in
index 4cc485f9683a..6a43ccaeb489 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -51,9 +51,16 @@ DIST_COMMON = $(srcdir)/../config.guess $(srcdir)/../config.sub NEWS \
 	$(srcdir)/../config.sub
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
-	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../bfd/warning.m4 \
+	$(top_srcdir)/../config/depstand.m4 \
+	$(top_srcdir)/../config/gettext-sister.m4 \
+	$(top_srcdir)/../config/lead-dot.m4 \
+	$(top_srcdir)/../config/nls.m4 $(top_srcdir)/../config/po.m4 \
+	$(top_srcdir)/../config/progtest.m4 \
+	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+	$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+	$(top_srcdir)/acinclude.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
@@ -78,7 +85,7 @@ am__DEPENDENCIES_1 = tc-@target_cpu_type@.o
 am__DEPENDENCIES_2 = obj-@obj_format@.o
 am__DEPENDENCIES_3 = atof-@atof@.o
 am__DEPENDENCIES_4 =
-am__DEPENDENCIES_5 = ../libiberty/libiberty.a
+am__DEPENDENCIES_5 = ../bfd/libbfd.la ../libiberty/libiberty.a
 am_itbl_test_OBJECTS = itbl-parse.$(OBJEXT) itbl-lex.$(OBJEXT)
 itbl_test_OBJECTS = $(am_itbl_test_OBJECTS)
 itbl_test_DEPENDENCIES = itbl-tops.o itbl-test.o $(am__DEPENDENCIES_5)
@@ -88,11 +95,11 @@ depcomp =
 am__depfiles_maybe =
 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
 	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
-LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) \
+LTCOMPILE = $(LIBTOOL) --tag=CC --mode=compile $(CC) $(DEFS) \
 	$(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \
 	$(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
-LINK = $(LIBTOOL) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
+LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
 	$(AM_LDFLAGS) $(LDFLAGS) -o $@
 LEXCOMPILE = $(LEX) $(LFLAGS) $(AM_LFLAGS)
 LTLEXCOMPILE = $(LIBTOOL) --mode=compile $(LEX) $(LFLAGS) $(AM_LFLAGS)
@@ -114,16 +121,14 @@ DEJATOOL = $(PACKAGE)
 RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
 ACLOCAL = @ACLOCAL@
 ALLOCA = @ALLOCA@
-ALL_OBJ_DEPS = @ALL_OBJ_DEPS@
 AMDEP_FALSE = @AMDEP_FALSE@
 AMDEP_TRUE = @AMDEP_TRUE@
 AMTAR = @AMTAR@
+AR = @AR@
 AUTOCONF = @AUTOCONF@
 AUTOHEADER = @AUTOHEADER@
 AUTOMAKE = @AUTOMAKE@
 AWK = @AWK@
-BFDLIB = @BFDLIB@
-BFDVER_H = @BFDVER_H@
 CATALOGS = @CATALOGS@
 CATOBJEXT = @CATOBJEXT@
 CC = @CC@
@@ -135,29 +140,32 @@ CYGPATH_W = @CYGPATH_W@
 DATADIRNAME = @DATADIRNAME@
 DEFS = @DEFS@
 DEPDIR = @DEPDIR@
+DUMPBIN = @DUMPBIN@
 ECHO_C = @ECHO_C@
 ECHO_N = @ECHO_N@
 ECHO_T = @ECHO_T@
 EGREP = @EGREP@
 EXEEXT = @EXEEXT@
+FGREP = @FGREP@
 GDBINIT = @GDBINIT@
-GMOFILES = @GMOFILES@
+GENCAT = @GENCAT@
+GENINSRC_NEVER_FALSE = @GENINSRC_NEVER_FALSE@
+GENINSRC_NEVER_TRUE = @GENINSRC_NEVER_TRUE@
 GMSGFMT = @GMSGFMT@
-GT_NO = @GT_NO@
-GT_YES = @GT_YES@
-INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@
+GREP = @GREP@
+INCINTL = @INCINTL@
 INSTALL_DATA = @INSTALL_DATA@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_SCRIPT = @INSTALL_SCRIPT@
 INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
 INSTOBJEXT = @INSTOBJEXT@
-INTLDEPS = @INTLDEPS@
-INTLLIBS = @INTLLIBS@
-INTLOBJS = @INTLOBJS@
+LD = @LD@
 LDFLAGS = @LDFLAGS@
 LEX = `if [ -f ../flex/flex ] ; then echo ../flex/flex ; else echo @LEX@ ; fi`
 LEXLIB = @LEXLIB@
 LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@
+LIBINTL = @LIBINTL@
+LIBINTL_DEP = @LIBINTL_DEP@
 LIBM = @LIBM@
 LIBOBJS = @LIBOBJS@
 LIBS = @LIBS@
@@ -170,6 +178,8 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+MSGMERGE = @MSGMERGE@
+NM = @NM@
 NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
@@ -180,19 +190,20 @@ PACKAGE_STRING = @PACKAGE_STRING@
 PACKAGE_TARNAME = @PACKAGE_TARNAME@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
-POFILES = @POFILES@
 POSUB = @POSUB@
 RANLIB = @RANLIB@
+SED = @SED@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
-USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
 USE_NLS = @USE_NLS@
 VERSION = @VERSION@
 WARN_CFLAGS = @WARN_CFLAGS@
 XGETTEXT = @XGETTEXT@
 YACC = `if [ -f ../bison/bison ] ; then echo ../bison/bison -y -L../bison/bison ; else echo @YACC@ ; fi`
+ac_ct_AR = @ac_ct_AR@
 ac_ct_CC = @ac_ct_CC@
+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
 ac_ct_RANLIB = @ac_ct_RANLIB@
 ac_ct_STRIP = @ac_ct_STRIP@
 am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
@@ -225,10 +236,10 @@ includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
 install_tooldir = @install_tooldir@
-l = @l@
 libdir = @libdir@
 libexecdir = @libexecdir@
 localstatedir = @localstatedir@
+lt_ECHO = @lt_ECHO@
 mandir = @mandir@
 mkdir_p = @mkdir_p@
 obj_format = @obj_format@
@@ -246,11 +257,16 @@ target_os = @target_os@
 target_vendor = @target_vendor@
 te_file = @te_file@
 AUTOMAKE_OPTIONS = 1.8 cygnus dejagnu
+ACLOCAL_AMFLAGS = -I .. -I ../config -I ../bfd
 SUBDIRS = doc po
 # Automake should figure this out on its own.  It doesn't, because
 # of the "cygnus" option.  But distclean still wants it.
 DIST_SUBDIRS = $(SUBDIRS)
 tooldir = $(exec_prefix)/$(target_alias)
+
+# We have to set this, because autoconf 2.59 does not substitute YFLAGS.
+# Autoconf 2.61 does, so this can be removed when we upgrade.
+YFLAGS = 
 AM_CFLAGS = $(WARN_CFLAGS)
 MKDEP = gcc -MM
 TARG_CPU = @target_cpu_type@
@@ -265,7 +281,7 @@ ATOF_TARG_C = $(srcdir)/config/atof-@atof@.c
 ATOF_TARG_O = atof-@atof@.o
 
 # use @target_cpu_type@ for refering to configured target name
-IT_HDRS = itbl-parse.h $(srcdir)/itbl-ops.h 
+IT_HDRS = itbl-parse.h $(srcdir)/itbl-ops.h
 IT_SRCS = itbl-parse.c itbl-lex.c $(srcdir)/itbl-ops.c
 IT_DEPS = $(srcdir)/itbl-parse.y $(srcdir)/itbl-lex.l $(srcdir)/config/itbl-@target_cpu_type@.h
 IT_OBJS = itbl-parse.o itbl-lex.o itbl-ops.o
@@ -277,6 +293,7 @@ CPU_TYPES = \
 	arm \
 	avr \
 	bfin \
+	cr16 \
 	cris \
 	crx \
 	d10v \
@@ -286,22 +303,25 @@ CPU_TYPES = \
 	frv \
 	h8300 \
 	hppa \
-	ia64 \
 	i370 \
 	i386 \
 	i860 \
 	i960 \
+	ia64 \
 	ip2k \
 	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
+	maxq \
 	mcore \
+	mep \
 	mips \
 	mmix \
 	mn10200 \
 	mn10300 \
 	msp430 \
+	mt \
 	ns32k \
 	openrisc \
 	or32 \
@@ -309,16 +329,18 @@ CPU_TYPES = \
 	pj \
 	ppc \
 	s390 \
+	score \
 	sh \
 	sh64 \
 	sparc \
+	spu \
 	tic30 \
 	tic4x \
 	tic54x \
-	vax \
 	v850 \
-	xstormy16 \
+	vax \
 	xc16x \
+	xstormy16 \
 	xtensa \
 	z80 \
 	z8k
@@ -331,8 +353,7 @@ OBJ_FORMATS = \
 	coff \
 	ecoff \
 	elf \
-	evax \
-	ieee
+	evax
 
 
 # This is an sh case which sets valid according to whether the CPU
@@ -347,16 +368,20 @@ CPU_OBJ_VALID = \
 	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	coff) valid=yes; \
+	coff) \
 	  case $$c in \
-	  cris | i860 | mmix | sh64) \
-	    valid= ;; \
+	  arm | h8300 | i386 | i960 | m68k | maxq | mcore | mips | or32 \
+		| ppc | sh | sparc | tic* | xscale | z80 | z8k) \
+	    valid=yes ;; \
 	  esac ;; \
 	ecoff) \
 	  case $$c in \
 	  mips | alpha) valid=yes ;; \
 	  esac ;; \
-	elf) valid=yes ;; \
+	elf) valid=yes ; \
+	  case $$c in \
+	  maxq | ns32k | tic* | z80 | z8k) valid= ;; \
+	  esac ;; \
 	evax) \
 	  case $$c in \
 	  alpha) valid=yes ;; \
@@ -459,6 +484,7 @@ TARGET_CPU_CFILES = \
 	config/tc-arm.c \
 	config/tc-avr.c \
 	config/tc-bfin.c \
+	config/tc-cr16.c \
 	config/tc-cris.c \
 	config/tc-crx.c \
 	config/tc-d10v.c \
@@ -479,6 +505,7 @@ TARGET_CPU_CFILES = \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
 	config/tc-mcore.c \
+	config/tc-mep.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
 	config/tc-mn10200.c \
@@ -491,9 +518,11 @@ TARGET_CPU_CFILES = \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
+	config/tc-score.c \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
+	config/tc-spu.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
 	config/tc-vax.c \
@@ -510,6 +539,7 @@ TARGET_CPU_HFILES = \
 	config/tc-arm.h \
 	config/tc-avr.h \
 	config/tc-bfin.h \
+	config/tc-cr16.h \
 	config/tc-cris.h \
 	config/tc-crx.h \
 	config/tc-d10v.h \
@@ -530,6 +560,7 @@ TARGET_CPU_HFILES = \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
 	config/tc-mcore.h \
+	config/tc-mep.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
 	config/tc-mn10200.h \
@@ -542,9 +573,11 @@ TARGET_CPU_HFILES = \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
+	config/tc-score.h \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
+	config/tc-spu.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
 	config/tc-vax.h \
@@ -563,7 +596,6 @@ OBJ_FORMAT_CFILES = \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-ieee.c \
 	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
@@ -572,7 +604,6 @@ OBJ_FORMAT_HFILES = \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-ieee.h \
 	config/obj-som.h
 
 
@@ -610,7 +641,8 @@ TARG_ENV_HFILES = \
 	config/te-sun3.h \
 	config/te-svr4.h \
 	config/te-symbian.h \
-	config/te-tmips.h
+	config/te-tmips.h \
+	config/te-wince-pe.h
 
 
 # Multi files in config
@@ -681,29 +713,36 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config \
+	-I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
+
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd \
+	-I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. \
+	-I$${srcdir}/../bfd @INCINTL@ \
+	-DLOCALEDIR="\"$(datadir)/locale\""
+
 DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
 
 
 # How to link with both our special library facilities
 # and the system's installed libraries.
-GASLIBS = @OPCODES_LIB@ @BFDLIB@ ../libiberty/libiberty.a
+GASLIBS = @OPCODES_LIB@ ../bfd/libbfd.la ../libiberty/libiberty.a
 
 # Files to be copied away after each stage in building.
 STAGESTUFF = *.o $(noinst_PROGRAMS)
 as_new_SOURCES = $(GAS_CFILES)
 as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLLIBS) $(LIBM)
+	$(extra_objects) $(GASLIBS) $(LIBINTL) $(LIBM)
 
 as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
-	$(extra_objects) $(GASLIBS) $(INTLDEPS)
+	$(extra_objects) $(GASLIBS) $(LIBINTL_DEP)
 
 EXPECT = expect
 RUNTEST = runtest
@@ -729,687 +768,520 @@ DEP_FILE_DEPS = $(CFILES) $(HFILES) $(TARGET_CPU_CFILES) \
 
 CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+DEPTC_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+DEPTC_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h subsegs.h \
+  $(INCDIR)/obstack.h struc-symbol.h ecoff.h $(INCDIR)/coff/sym.h \
+  $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/elf/alpha.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPTC_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h \
   subsegs.h $(INCDIR)/obstack.h struc-symbol.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h $(INCDIR)/opcode/alpha.h \
-  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
-
-DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
+  $(INCDIR)/opcode/alpha.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
-DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
   $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 
-DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
 
-DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h
+DEPTC_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  dwarf2dbg.h
 
-DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
+DEPTC_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h \
+  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h dwarf2dbg.h
 
-DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPTC_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+  $(INCDIR)/opcode/avr.h
 
-DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/avr.h
+DEPTC_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  struc-symbol.h $(srcdir)/config/bfin-defs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h \
+  $(INCDIR)/elf/reloc-macros.h $(srcdir)/config/bfin-aux.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/opcode/bfin.h
+
+DEPTC_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/cr16.h \
+  $(INCDIR)/elf/cr16.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/avr.h
+DEPTC_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/cris.h \
+  dwarf2dbg.h
 
-DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
-  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-
-DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
-  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
-
-DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
+DEPTC_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/cris.h dwarf2dbg.h
 
-DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h
-
-DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
-  $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+DEPTC_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/opcode/crx.h \
   $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d10v.h \
   $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d10v.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/d30v.h
 
-DEPTC_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/d30v.h
-
-DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/dlx.h
-
-DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
-
-DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
 
-DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
 
-DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+DEPTC_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/frv-opc.h \
   cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
-  $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
+DEPTC_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/opcode/h8300.h $(INCDIR)/safe-ctype.h
 
-DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
+DEPTC_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h
-
-DEPTC_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+DEPTC_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/hppa.h \
-  dwarf2dbg.h
-
-DEPTC_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
+  subsegs.h $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h dwarf2dbg.h
 
-DEPTC_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h
-
-DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/i370.h
-
-DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
-  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
-
-DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+DEPTC_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i960.h
 
-DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+DEPTC_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
 
-DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+DEPTC_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h
+
+DEPTC_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
   $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 
-DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
-  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
-  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
+DEPTC_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
-  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
-  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
-  $(INCDIR)/safe-ctype.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h ../bfd/bfd_stdint.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h
 
-DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
-  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+DEPTC_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
   $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h \
-  $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
+DEPTC_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h
 
-DEPTC_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  subsegs.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
+DEPTC_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+  $(srcdir)/config/m68k-parse.h
 
-DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h subsegs.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
+DEPTC_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
-  $(INCDIR)/safe-ctype.h
+DEPTC_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/opcode/maxq.h
 
-DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+DEPTC_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/mcore-opc.h $(INCDIR)/safe-ctype.h
+
+DEPTC_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+DEPTC_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
-  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mep-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
 
-DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
   dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+DEPTC_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h
+
+DEPTC_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h \
+  itbl-ops.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(srcdir)/config/obj-elf.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+DEPTC_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10200.h
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h $(INCDIR)/obstack.h
 
-DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
 
-DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/mn10300.h \
-  dwarf2dbg.h
-
-DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h
-
-DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
+DEPTC_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
 
-DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
-  $(INCDIR)/safe-ctype.h
+DEPTC_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  $(INCDIR)/safe-ctype.h dwarf2dbg.h
 
-DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
+DEPTC_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mt-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/mt-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mt.h $(INCDIR)/elf/reloc-macros.h \
+  $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 
-DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
+DEPTC_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
 
-DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
-
-DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
-
-DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPTC_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
-
-DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
-  $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
 
-DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
-  $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h $(INCDIR)/opcode/or32.h $(INCDIR)/elf/or32.h \
+  $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/pdp11.h
 
-DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+DEPTC_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
 
-DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/pj.h
+DEPTC_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
 
-DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+DEPTC_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/ppc.h
 
-DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+DEPTC_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h
-
-DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 
-DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+DEPTC_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
-  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/score-inst.h $(INCDIR)/opcode/score-datadep.h \
+  struc-symbol.h $(INCDIR)/elf/score.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
 
-DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
+DEPTC_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h subsegs.h \
+  $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+
+DEPTC_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
+  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+  $(srcdir)/../opcodes/sh-opc.h $(INCDIR)/safe-ctype.h \
+  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h
+DEPTC_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/sparc.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
-DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
-
-DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
-
-DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h
 
-DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+DEPTC_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/spu-insns.h
 
-DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
+DEPTC_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
 
-DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
-  subsegs.h $(INCDIR)/obstack.h
+DEPTC_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/tic30.h
 
-DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h sb.h macro.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h $(INCDIR)/opcode/tic54x.h
+DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/opcode/tic4x.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h
 
-DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h sb.h macro.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h \
+DEPTC_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
-  $(BFDDIR)/libcoff.h
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h subsegs.h $(INCDIR)/obstack.h struc-symbol.h \
+  $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h
 
-DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
+DEPTC_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
+  dwarf2dbg.h
 
-DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+DEPTC_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
   $(INCDIR)/opcode/vax.h
 
-DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
-  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+DEPTC_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
 
-DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h dwarf2dbg.h
-
-DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPTC_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/v850.h
-
-DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h dwarf2dbg.h \
+  $(INCDIR)/elf/xc16x.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+DEPTC_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
-
-DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
 
-DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+DEPTC_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/tc-xtensa.h subsegs.h $(INCDIR)/obstack.h \
   $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
-  dwarf2dbg.h struc-symbol.h
-
-DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-
-DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/xtensa-config.h
 
-DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+DEPTC_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+DEPTC_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/../opcodes/z8k-opc.h
 
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
@@ -1422,588 +1294,439 @@ DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
 
-DEPOBJ_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
+DEPOBJ_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/aout/aout64.h
 
-DEPOBJ_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
+DEPOBJ_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
+DEPOBJ_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/alpha.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
-  $(srcdir)/config/tc-alpha.h
+DEPOBJ_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
+DEPOBJ_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
+DEPOBJ_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d10v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h \
+DEPOBJ_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_d30v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-d30v.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_d30v_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h \
+DEPOBJ_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
+DEPOBJ_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
+DEPOBJ_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
+DEPOBJ_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_hppa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
+DEPOBJ_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ia64_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
-  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_ia64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h \
+DEPOBJ_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i370.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
+DEPOBJ_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+DEPOBJ_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
+DEPOBJ_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_m68k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m68k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
+DEPOBJ_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
-  $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(BFDDIR)/libecoff.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
+DEPOBJ_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/mep.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
+DEPOBJ_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
+  $(BFDDIR)/libecoff.h
 
-DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ns32k.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+DEPOBJ_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pdp11.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+DEPOBJ_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/aout/aout64.h
+DEPOBJ_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
+DEPOBJ_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
+DEPOBJ_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-sparc.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic30.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+DEPOBJ_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+DEPOBJ_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
+DEPOBJ_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
+  subsegs.h $(INCDIR)/obstack.h
 
-DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 
-DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+DEPOBJ_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
+DEPOBJ_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
-
-DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+DEPOBJ_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
   dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/obstack.h struc-symbol.h \
+  dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
+
+DEPOBJ_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/obstack.h
 
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
@@ -2016,458 +1739,385 @@ DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
 DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
+DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h
 
 DEP_alpha_evax = $(srcdir)/config/obj-evax.h $(srcdir)/config/tc-alpha.h
-DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  dwarf2dbg.h
+DEP_arc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_arm_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_arm_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h
 
-DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  dwarf2dbg.h
+DEP_avr_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
-  dwarf2dbg.h
+DEP_cr16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cr16.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  dwarf2dbg.h
-
-DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
-  dwarf2dbg.h
-
-DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
-
-DEP_d30v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d30v.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
+DEP_cris_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  dwarf2dbg.h
+DEP_d10v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d10v.h
 
-DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_d30v_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-d30v.h
 
-DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  dwarf2dbg.h
+DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_frv_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
+DEP_frv_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h
 
 DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  dwarf2dbg.h
-
-DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h \
-  $(BFDDIR)/elf32-hppa.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
-  $(INCDIR)/elf/reloc-macros.h
-
-DEP_ia64_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/symcat.h $(INCDIR)/elf/ia64.h \
-  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h \
-  $(INCDIR)/opcode/ia64.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
+DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 
-DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_hppa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-hppa.h $(BFDDIR)/elf32-hppa.h \
+  $(BFDDIR)/elf-bfd.h $(BFDDIR)/libhppa.h $(INCDIR)/elf/hppa.h \
+  $(INCDIR)/elf/reloc-macros.h
 
-DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  dwarf2dbg.h
+DEP_i370_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i386.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(srcdir)/../opcodes/i386-opc.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  dwarf2dbg.h
+DEP_i386_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h $(srcdir)/../opcodes/i386-opc.h \
+  $(INCDIR)/opcode/i386.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/x86_64.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  dwarf2dbg.h
+DEP_i860_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  dwarf2dbg.h
-
-DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 
-DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  dwarf2dbg.h
-
-DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_i960_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h
 
-DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
-  dwarf2dbg.h
+DEP_ia64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ia64.h $(INCDIR)/opcode/ia64.h \
+  $(INCDIR)/elf/ia64.h $(INCDIR)/elf/reloc-macros.h
 
-DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  dwarf2dbg.h
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  dwarf2dbg.h
+DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
 
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
+
+DEP_maxq_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-maxq.h \
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/maxq.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  dwarf2dbg.h
+DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_mips_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-mips.h \
   ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
-DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
-
-DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  dwarf2dbg.h
-
-DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_mips_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
 
-DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  dwarf2dbg.h
+DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  dwarf2dbg.h
+DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  dwarf2dbg.h
+DEP_mt_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mt.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  dwarf2dbg.h
-
-DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  dwarf2dbg.h
+DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
 
-DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  dwarf2dbg.h
+DEP_or32_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h
 
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  dwarf2dbg.h
-
-DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  dwarf2dbg.h
+DEP_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
 
-DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  dwarf2dbg.h
+DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h
 
-DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_s390_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  dwarf2dbg.h
+DEP_score_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-score.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_sh_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
+DEP_sh_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h
 
-DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
-  $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/elf32-sh64.h
+DEP_sh64_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h $(srcdir)/config/tc-sh.h \
+  $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/elf32-sh64.h
 
 DEP_sparc_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-sparc.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  dwarf2dbg.h
+DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/sparc.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h
+
+DEP_spu_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-spu.h $(INCDIR)/opcode/spu.h \
+  $(INCDIR)/opcode/spu-insns.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic30.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
-  $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
-DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
+DEP_v850_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h \
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h $(srcdir)/config/obj-coff.h \
+  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h
 
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
-DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  dwarf2dbg.h
-
-DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
-  $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
-
-DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
+DEP_vax_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  dwarf2dbg.h
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h dwarf2dbg.h \
+  $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
+DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(srcdir)/config/obj-coff.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h
 
-DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h $(INCDIR)/xtensa-isa.h \
+  $(INCDIR)/xtensa-config.h
 
 DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  dwarf2dbg.h
+  $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
@@ -2489,15 +2139,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
 	    *$$dep*) \
-	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
-	      cd $(srcdir) && $(AUTOMAKE) --foreign  \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
+	      cd $(srcdir) && $(AUTOMAKE) --cygnus  \
 		&& exit 0; \
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --foreign  Makefile
+	  $(AUTOMAKE) --cygnus  Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -2856,12 +2506,11 @@ po/POTFILES.in: @MAINT@ Makefile
 diststuff: $(EXTRA_DIST) info
 all: info
 
-$(OBJS): @ALL_OBJ_DEPS@
-
 # Stuff that every object file depends upon.  If anything is removed
 # from this list, remove it from dep-in.sed as well.
-$(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
-	$(INCDIR)/progress.h $(INCDIR)/fopen-same.h \
+$(OBJS): ../bfd/bfd.h $(INCDIR)/symcat.h \
+	$(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h $(INCDIR)/progress.h \
+	$(INCDIR)/fopen-same.h $(INCDIR)/fopen-bin.h $(INCDIR)/fopen-vms.h \
 	$(OBJ_FORMAT_H) $(TARG_CPU_H) $(TARG_ENV_H) \
 	as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \
 	frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h
@@ -2901,18 +2550,16 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 # We need all these explicit rules for the multi stuff.  Because of
 # these rules, we don't need one for OBJ_FORMAT_O.
 
-obj-aout.o : $(srcdir)/config/obj-aout.c
+obj-aout.o : $(srcdir)/config/obj-aout.c $(DEP_@target_cpu_type@_aout)
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-coff.o: $(srcdir)/config/obj-coff.c
+obj-coff.o: $(srcdir)/config/obj-coff.c $(DEP_@target_cpu_type@_coff)
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
-obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
+obj-ecoff.o : $(srcdir)/config/obj-ecoff.c $(DEP_@target_cpu_type@_ecoff)
 	$(COMPILE) -c $(srcdir)/config/obj-ecoff.c
-obj-elf.o : $(srcdir)/config/obj-elf.c
+obj-elf.o : $(srcdir)/config/obj-elf.c $(DEP_@target_cpu_type@_elf)
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-ieee.o : $(srcdir)/config/obj-ieee.c
-	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
@@ -2959,7 +2606,7 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	  rm -f m68k-parse.y; \
 	else true; fi
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -2986,12 +2633,12 @@ bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
 itbl-lex.c: $(srcdir)/itbl-lex.l
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
 # Disable -Werror, if it has been enabled, since old versions of bison/
-# yacc will produce working code which contain compile time warnings. 
+# yacc will produce working code which contain compile time warnings.
 itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
 	$(COMPILE) -c $< $(NO_WERROR)
 
@@ -3319,66 +2966,52 @@ dep-am: DEP
 # ANYTHING CHANGED OR ADDED BETWEEN THE WARNING LINES MAY GO AWAY.
 .PHONY: dep dep-in dep-am
 #MKDEP    DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-app.o: app.c $(INCDIR)/symcat.h
-as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
-atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
-depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
+app.o: app.c
+as.o: as.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  sb.h macro.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  ../bfd/bfdver.h
+atof-generic.o: atof-generic.c $(INCDIR)/safe-ctype.h
+cond.o: cond.c sb.h macro.h $(INCDIR)/obstack.h
+depend.o: depend.c
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/safe-ctype.h dwarf2dbg.h \
+  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
-ecoff.o: ecoff.c $(INCDIR)/symcat.h ecoff.h
-ehopt.o: ehopt.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/dwarf2.h
-expr.o: expr.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-flonum-copy.o: flonum-copy.c $(INCDIR)/symcat.h
+dw2gencfi.o: dw2gencfi.c dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
+  subsegs.h $(INCDIR)/obstack.h
+ecoff.o: ecoff.c ecoff.h
+ehopt.o: ehopt.c subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/dwarf2.h
+expr.o: expr.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+flonum-copy.o: flonum-copy.c
 flonum-konst.o: flonum-konst.c
 flonum-mult.o: flonum-mult.c
-frags.o: frags.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-hash.o: hash.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h
-input-file.o: input-file.c $(INCDIR)/symcat.h input-file.h \
-  $(INCDIR)/safe-ctype.h
-input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
-  sb.h
-listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  $(INCDIR)/safe-ctype.h input-file.h subsegs.h
-literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  sb.h macro.h
-messages.o: messages.c $(INCDIR)/symcat.h
-output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
-read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
-  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h $(INCDIR)/symcat.h
-stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
-  subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-symbols.o: symbols.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h struc-symbol.h
-write.o: write.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
-  output-file.h dwarf2dbg.h
-itbl-ops.o: itbl-ops.c itbl-ops.h $(INCDIR)/symcat.h
-e-crisaout.o: $(srcdir)/config/e-crisaout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-criself.o: $(srcdir)/config/e-criself.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386aout.o: $(srcdir)/config/e-i386aout.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386coff.o: $(srcdir)/config/e-i386coff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-i386elf.o: $(srcdir)/config/e-i386elf.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c $(INCDIR)/symcat.h \
-  emul-target.h
-e-mipself.o: $(srcdir)/config/e-mipself.c $(INCDIR)/symcat.h \
-  emul-target.h
+frags.o: frags.c subsegs.h $(INCDIR)/obstack.h
+hash.o: hash.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h
+input-file.o: input-file.c input-file.h $(INCDIR)/safe-ctype.h
+input-scrub.o: input-scrub.c input-file.h sb.h
+listing.o: listing.c $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  input-file.h subsegs.h
+literal.o: literal.c subsegs.h $(INCDIR)/obstack.h
+macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+messages.o: messages.c
+output-file.o: output-file.c output-file.h
+read.o: read.c $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  sb.h macro.h ecoff.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
+sb.o: sb.c sb.h
+stabs.o: stabs.c $(INCDIR)/obstack.h subsegs.h ecoff.h \
+  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
+subsegs.o: subsegs.c subsegs.h $(INCDIR)/obstack.h
+symbols.o: symbols.c $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  subsegs.h struc-symbol.h
+write.o: write.c subsegs.h $(INCDIR)/obstack.h output-file.h \
+  dwarf2dbg.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+itbl-ops.o: itbl-ops.c itbl-ops.h
+e-crisaout.o: $(srcdir)/config/e-crisaout.c emul-target.h
+e-criself.o: $(srcdir)/config/e-criself.c emul-target.h
+e-i386aout.o: $(srcdir)/config/e-i386aout.c emul-target.h
+e-i386coff.o: $(srcdir)/config/e-i386coff.c emul-target.h
+e-i386elf.o: $(srcdir)/config/e-i386elf.c emul-target.h
+e-mipsecoff.o: $(srcdir)/config/e-mipsecoff.c emul-target.h
+e-mipself.o: $(srcdir)/config/e-mipself.c emul-target.h
 $(OBJS): $(DEP_@target_cpu_type@_@obj_format@)
 $(TARG_CPU_O): $(DEPTC_@target_cpu_type@_@obj_format@)
 $(OBJ_FORMAT_O): $(DEPOBJ_@target_cpu_type@_@obj_format@)
diff --git a/gas/NEWS b/gas/NEWS
index 4b4d029685ab..bf278ef65a88 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,4 +1,12 @@
 -*- text -*-
+* Support for the National Semiconductor CR16 target has been added.
+
+* Added gas .reloc pseudo.  This is a low-level interface for creating
+  relocations.
+
+* Add support for x86_64 PE+ target.
+
+* Add support for Score target.
 
 * Support for the Infineon XC16X has been added by KPIT Cummins Infosystems.
 
diff --git a/gas/acinclude.m4 b/gas/acinclude.m4
index 0946e724f126..fa4c1bc6e9f5 100644
--- a/gas/acinclude.m4
+++ b/gas/acinclude.m4
@@ -1,5 +1,3 @@
-sinclude(../bfd/warning.m4)
-
 dnl GAS_CHECK_DECL_NEEDED(name, typedefname, typedef, headers)
 AC_DEFUN([GAS_CHECK_DECL_NEEDED],[
 AC_MSG_CHECKING(whether declaration is required for $1)
@@ -56,19 +54,3 @@ for _gas_uniq_i in _gas_uniq_dummy [$]_gas_uniq_list ; do
 done
 $1=[$]_gas_uniq_newlist
 ])dnl
-
-sinclude(../libtool.m4)
-dnl The lines below arrange for aclocal not to bring libtool.m4
-dnl AM_PROG_LIBTOOL into aclocal.m4, while still arranging for automake
-dnl to add a definition of LIBTOOL to Makefile.in.
-ifelse(yes,no,[
-AC_DEFUN([AM_PROG_LIBTOOL],)
-AC_DEFUN([AC_CHECK_LIBM],)
-AC_SUBST(LIBTOOL)
-])
-
-sinclude(../gettext.m4)
-ifelse(yes,no,[
-AC_DEFUN([CY_WITH_NLS],)
-AC_SUBST(INTLLIBS)
-])
diff --git a/gas/aclocal.m4 b/gas/aclocal.m4
index cd4267338b72..1182e3622d19 100644
--- a/gas/aclocal.m4
+++ b/gas/aclocal.m4
@@ -480,27 +480,6 @@ AC_DEFUN([AM_PROG_INSTALL_SH],
 install_sh=${install_sh-"$am_aux_dir/install-sh"}
 AC_SUBST(install_sh)])
 
-# Copyright (C) 2003, 2005  Free Software Foundation, Inc.
-#
-# This file is free software; the Free Software Foundation
-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
-
-# serial 2
-
-# Check whether the underlying file-system supports filenames
-# with a leading dot.  For instance MS-DOS doesn't.
-AC_DEFUN([AM_SET_LEADING_DOT],
-[rm -rf .tst 2>/dev/null
-mkdir .tst 2>/dev/null
-if test -d .tst; then
-  am__leading_dot=.
-else
-  am__leading_dot=_
-fi
-rmdir .tst 2>/dev/null
-AC_SUBST([am__leading_dot])])
-
 # Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2005
 # Free Software Foundation, Inc.
 #
@@ -910,4 +889,16 @@ AC_SUBST([am__tar])
 AC_SUBST([am__untar])
 ]) # _AM_PROG_TAR
 
+m4_include([../bfd/acinclude.m4])
+m4_include([../bfd/warning.m4])
+m4_include([../config/depstand.m4])
+m4_include([../config/gettext-sister.m4])
+m4_include([../config/lead-dot.m4])
+m4_include([../config/nls.m4])
+m4_include([../config/po.m4])
+m4_include([../config/progtest.m4])
+m4_include([../libtool.m4])
+m4_include([../ltoptions.m4])
+m4_include([../ltsugar.m4])
+m4_include([../ltversion.m4])
 m4_include([acinclude.m4])
diff --git a/gas/app.c b/gas/app.c
index 275ad68ebb0b..e5f177801fdb 100644
--- a/gas/app.c
+++ b/gas/app.c
@@ -1,6 +1,6 @@
 /* This is the Assembler Pre-Processor
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -21,13 +21,12 @@
    02110-1301, USA.  */
 
 /* Modified by Allen Wirfs-Brock, Instantiations Inc 2/90.  */
-/* App, the assembler pre-processor.  This pre-processor strips out excess
-   spaces, turns single-quoted characters into a decimal constant, and turns
-   # <number> <filename> <garbage> into a .line <number>\n.file <filename>
-   pair.  This needs better error-handling.  */
+/* App, the assembler pre-processor.  This pre-processor strips out
+   excess spaces, turns single-quoted characters into a decimal
+   constant, and turns the # in # <number> <filename> <garbage> into a
+   .linefile.  This needs better error-handling.  */
 
-#include <stdio.h>
-#include "as.h"			/* For BAD_CASE() only.  */
+#include "as.h"
 
 #if (__STDC__ != 1)
 #ifndef const
@@ -352,11 +351,11 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  1: After first whitespace on line (flush more white)
 	  2: After first non-white (opcode) on line (keep 1white)
 	  3: after second white on line (into operands) (flush white)
-	  4: after putting out a .line, put out digits
+	  4: after putting out a .linefile, put out digits
 	  5: parsing a string, then go to old-state
 	  6: putting out \ escape in a "d string.
-	  7: After putting out a .appfile, put out string.
-	  8: After putting out a .appfile string, flush until newline.
+	  7: no longer used
+	  8: no longer used
 	  9: After seeing symbol char in state 3 (keep 1white after symchar)
 	 10: After seeing whitespace in state 9 (keep white before symchar)
 	 11: After seeing a symbol character in state 0 (eg a label definition)
@@ -511,14 +510,10 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		ch = GET ();
 	      if (ch == '"')
 		{
-		  UNGET (ch);
-		  if (scrub_m68k_mri)
-		    out_string = "\n\tappfile ";
-		  else
-		    out_string = "\n\t.appfile ";
-		  old_state = 7;
-		  state = -1;
-		  PUT (*out_string++);
+		  quotechar = ch;
+		  state = 5;
+		  old_state = 3;
+		  PUT (ch);
 		}
 	      else
 		{
@@ -555,6 +550,8 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		memcpy (to, from, len);
 		to += len;
 		from += len;
+		if (to >= toend)
+		  goto tofull;
 	      }
 	  }
 
@@ -639,24 +636,6 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  PUT (ch);
 	  continue;
 
-	case 7:
-	  ch = GET ();
-	  quotechar = ch;
-	  state = 5;
-	  old_state = 8;
-	  PUT (ch);
-	  continue;
-
-	case 8:
-	  do
-	    ch = GET ();
-	  while (ch != '\n' && ch != EOF);
-	  if (ch == EOF)
-	    goto fromeof;
-	  state = 0;
-	  PUT (ch);
-	  continue;
-
 #ifdef DOUBLEBAR_PARALLEL
 	case 13:
 	  ch = GET ();
@@ -888,9 +867,6 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 
 	  switch (state)
 	    {
-	    case 0:
-	      state++;
-	      goto recycle;	/* Punted leading sp */
 	    case 1:
 	      /* We can arrive here if we leave a leading whitespace
 		 character at the beginning of a line.  */
@@ -1200,9 +1176,9 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	      old_state = 4;
 	      state = -1;
 	      if (scrub_m68k_mri)
-		out_string = "\tappline ";
+		out_string = "\tlinefile ";
 	      else
-		out_string = "\t.appline ";
+		out_string = "\t.linefile ";
 	      PUT (*out_string++);
 	      break;
 	    }
@@ -1245,6 +1221,15 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  if ((symver_state != NULL) && (*symver_state == 0))
 	    goto de_fault;
 #endif
+
+#ifdef TC_ARM
+	  /* For the ARM, care is needed not to damage occurrences of \@
+	     by stripping the @ onwards.  Yuck.  */
+	  if (to > tostart && *(to - 1) == '\\')
+	    /* Do not treat the @ as a start-of-comment.  */
+	    goto de_fault;
+#endif
+
 #ifdef WARN_COMMENTS
 	  if (!found_comment)
 	    as_where (&found_comment_file, &found_comment);
@@ -1377,7 +1362,15 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 		     the space.  We don't have enough information to
 		     make the right choice, so here we are making the
 		     choice which is more likely to be correct.  */
-		  PUT (' ');
+		  if (to + 1 >= toend)
+		    {
+		      /* If we're near the end of the buffer, save the
+		         character for the next time round.  Otherwise
+		         we'll lose our state.  */
+		      UNGET (ch);
+		      goto tofull;
+		    }
+		  *to++ = ' ';
 		}
 
 	      state = 3;
diff --git a/gas/as.c b/gas/as.c
index 727a1dd40ee5..b05f9d514a30 100644
--- a/gas/as.c
+++ b/gas/as.c
@@ -1,6 +1,6 @@
 /* as.c - GAS main program.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -31,8 +31,6 @@
   	Since no-one else says they will support them in future: I
    don't support them now.  */
 
-#include "ansidecl.h"
-
 #define COMMON
 
 #include "as.h"
@@ -42,7 +40,6 @@
 #include "macro.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
-#include "hash.h"
 #include "bfdver.h"
 
 #ifdef HAVE_ITBL_CPU
@@ -352,7 +349,9 @@ Options:\n\
   md_show_usage (stream);
 
   fputc ('\n', stream);
-  fprintf (stream, _("Report bugs to %s\n"), REPORT_BUGS_TO);
+
+  if (REPORT_BUGS_TO[0] && stream == stdout)
+    fprintf (stream, _("Report bugs to %s\n"), REPORT_BUGS_TO);
 }
 
 /* Since it is easy to do here we interpret the special arg "-"
@@ -591,7 +590,7 @@ parse_args (int * pargc, char *** pargv)
 	case OPTION_VERSION:
 	  /* This output is intended to follow the GNU standards document.  */
 	  printf (_("GNU assembler %s\n"), BFD_VERSION_STRING);
-	  printf (_("Copyright 2005 Free Software Foundation, Inc.\n"));
+	  printf (_("Copyright 2007 Free Software Foundation, Inc.\n"));
 	  printf (_("\
 This program is free software; you may redistribute it under the terms of\n\
 the GNU General Public License.  This program has absolutely no warranty.\n"));
@@ -1032,6 +1031,33 @@ perform_an_assembly_pass (int argc, char ** argv)
     read_a_source_file ("");
 }
 
+#ifdef OBJ_ELF
+static void
+create_obj_attrs_section (void)
+{
+  segT s;
+  char *p;
+  addressT addr;
+  offsetT size;
+  const char *name;
+
+  size = bfd_elf_obj_attr_size (stdoutput);
+  if (size)
+    {
+      name = get_elf_backend_data (stdoutput)->obj_attrs_section;
+      if (!name)
+	name = ".gnu.attributes";
+      s = subseg_new (name, 0);
+      elf_section_type (s)
+	= get_elf_backend_data (stdoutput)->obj_attrs_section_type;
+      bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
+      addr = frag_now_fix ();
+      p = frag_more (size);
+      bfd_elf_set_obj_attr_contents (stdoutput, (bfd_byte *)p, size);
+    }
+}
+#endif
+
 
 int
 main (int argc, char ** argv)
@@ -1125,6 +1151,11 @@ main (int argc, char ** argv)
 
       sym = symbol_new (defsyms->name, absolute_section, defsyms->value,
 			&zero_address_frag);
+      /* Make symbols defined on the command line volatile, so that they
+	 can be redefined inside a source file.  This makes this assembler's
+	 behaviour compatible with earlier versions, but it may not be
+	 completely intuitive.  */
+      S_SET_VOLATILE (sym);
       symbol_table_insert (sym);
       next = defsyms->next;
       free (defsyms);
@@ -1142,6 +1173,11 @@ main (int argc, char ** argv)
   md_end ();
 #endif
 
+#ifdef OBJ_ELF
+  if (IS_ELF)
+    create_obj_attrs_section ();
+#endif
+
 #if defined OBJ_ELF || defined OBJ_MAYBE_ELF
   if ((flag_execstack || flag_noexecstack)
       && OUTPUT_FLAVOR == bfd_target_elf_flavour)
diff --git a/gas/as.h b/gas/as.h
index 2f92c2ed7748..4ea63abeea92 100644
--- a/gas/as.h
+++ b/gas/as.h
@@ -1,6 +1,6 @@
 /* as.h - global header file
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -37,7 +37,6 @@
    If TEST is #defined, then we are testing a module: #define COMMON as "".  */
 
 #include "config.h"
-#include "bin-bugs.h"
 
 /* This is the code recommended in the autoconf documentation, almost
    verbatim.  If it doesn't work for you, let me know, and notify
@@ -210,7 +209,7 @@ extern int vsnprintf(char *, size_t, const char *, va_list);
 #endif /* __FILE__ */
 
 #ifndef FOPEN_WB
-#if defined GO32 || defined __MINGW32__
+#ifdef USE_BINARY_FOPEN
 #include "fopen-bin.h"
 #else
 #include "fopen-same.h"
@@ -259,7 +258,11 @@ typedef addressT valueT;
 #endif
 /* COMMON now defined */
 
-#ifdef DEBUG
+#ifndef ENABLE_CHECKING
+#define ENABLE_CHECKING 0
+#endif
+
+#if ENABLE_CHECKING || defined (DEBUG)
 #ifndef know
 #define know(p) assert(p)	/* Verify our assumptions!  */
 #endif /* not yet defined */
@@ -544,7 +547,6 @@ void   cond_finish_check (int);
 void   cond_exit_macro (int);
 int    seen_at_least_1_file (void);
 void   app_pop (char *);
-void   as_perror (const char *, const char *);
 void   as_where (char **, unsigned int *);
 void   bump_line_counters (void);
 void   do_scrub_begin (int);
@@ -552,6 +554,7 @@ void   input_scrub_begin (void);
 void   input_scrub_close (void);
 void   input_scrub_end (void);
 int    new_logical_line (char *, int);
+int    new_logical_line_flags (char *, int, int);
 void   subsegs_begin (void);
 void   subseg_change (segT, int);
 segT   subseg_new (const char *, subsegT);
@@ -567,7 +570,6 @@ segT   subseg_get (const char *, int);
 struct expressionS;
 struct fix;
 typedef struct symbol symbolS;
-struct relax_type;
 typedef struct frag fragS;
 
 /* literal.c */
diff --git a/gas/atof-generic.c b/gas/atof-generic.c
index 6a5c2f15b3cc..3021c4c861bb 100644
--- a/gas/atof-generic.c
+++ b/gas/atof-generic.c
@@ -1,6 +1,6 @@
 /* atof_generic.c - turn a string of digits into a Flonum
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000,
-   2001, 2003, 2005 Free Software Foundation, Inc.
+   2001, 2003, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,8 +19,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <string.h>
-
 #include "as.h"
 #include "safe-ctype.h"
 
diff --git a/gas/bfin-lex.c b/gas/bfin-lex.c
deleted file mode 100644
index cfc1fe7f30c0..000000000000
--- a/gas/bfin-lex.c
+++ /dev/null
@@ -1,3368 +0,0 @@
-/* A lexical scanner generated by flex */
-
-/* Scanner skeleton version:
- * $Header: /cvs/src/src/gas/Attic/bfin-lex.c,v 1.1.2.1 2006/04/16 18:36:43 drow Exp $
- */
-
-#define FLEX_SCANNER
-#define YY_FLEX_MAJOR_VERSION 2
-#define YY_FLEX_MINOR_VERSION 5
-
-#include <stdio.h>
-#include <errno.h>
-
-/* cfront 1.2 defines "c_plusplus" instead of "__cplusplus" */
-#ifdef c_plusplus
-#ifndef __cplusplus
-#define __cplusplus
-#endif
-#endif
-
-
-#ifdef __cplusplus
-
-#include <stdlib.h>
-#ifndef _WIN32
-#include <unistd.h>
-#endif
-
-/* Use prototypes in function declarations. */
-#define YY_USE_PROTOS
-
-/* The "const" storage-class-modifier is valid. */
-#define YY_USE_CONST
-
-#else	/* ! __cplusplus */
-
-#if __STDC__
-
-#define YY_USE_PROTOS
-#define YY_USE_CONST
-
-#endif	/* __STDC__ */
-#endif	/* ! __cplusplus */
-
-#ifdef __TURBOC__
- #pragma warn -rch
- #pragma warn -use
-#include <io.h>
-#include <stdlib.h>
-#define YY_USE_CONST
-#define YY_USE_PROTOS
-#endif
-
-#ifdef YY_USE_CONST
-#define yyconst const
-#else
-#define yyconst
-#endif
-
-
-#ifdef YY_USE_PROTOS
-#define YY_PROTO(proto) proto
-#else
-#define YY_PROTO(proto) ()
-#endif
-
-
-/* Returned upon end-of-file. */
-#define YY_NULL 0
-
-/* Promotes a possibly negative, possibly signed char to an unsigned
- * integer for use as an array index.  If the signed char is negative,
- * we want to instead treat it as an 8-bit unsigned char, hence the
- * double cast.
- */
-#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
-
-/* Enter a start condition.  This macro really ought to take a parameter,
- * but we do it the disgusting crufty way forced on us by the ()-less
- * definition of BEGIN.
- */
-#define BEGIN yy_start = 1 + 2 *
-
-/* Translate the current start state into a value that can be later handed
- * to BEGIN to return to the state.  The YYSTATE alias is for lex
- * compatibility.
- */
-#define YY_START ((yy_start - 1) / 2)
-#define YYSTATE YY_START
-
-/* Action number for EOF rule of a given start state. */
-#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
-
-/* Special action meaning "start processing a new file". */
-#define YY_NEW_FILE yyrestart( yyin )
-
-#define YY_END_OF_BUFFER_CHAR 0
-
-/* Size of default input buffer. */
-#define YY_BUF_SIZE 16384
-
-typedef struct yy_buffer_state *YY_BUFFER_STATE;
-
-extern int yyleng;
-extern FILE *yyin, *yyout;
-
-#define EOB_ACT_CONTINUE_SCAN 0
-#define EOB_ACT_END_OF_FILE 1
-#define EOB_ACT_LAST_MATCH 2
-
-/* The funky do-while in the following #define is used to turn the definition
- * int a single C statement (which needs a semi-colon terminator).  This
- * avoids problems with code like:
- *
- * 	if ( condition_holds )
- *		yyless( 5 );
- *	else
- *		do_something_else();
- *
- * Prior to using the do-while the compiler would get upset at the
- * "else" because it interpreted the "if" statement as being all
- * done when it reached the ';' after the yyless() call.
- */
-
-/* Return all but the first 'n' matched characters back to the input stream. */
-
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-		*yy_cp = yy_hold_char; \
-		YY_RESTORE_YY_MORE_OFFSET \
-		yy_c_buf_p = yy_cp = yy_bp + n - YY_MORE_ADJ; \
-		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
-		} \
-	while ( 0 )
-
-#define unput(c) yyunput( c, yytext_ptr )
-
-/* The following is because we cannot portably get our hands on size_t
- * (without autoconf's help, which isn't available because we want
- * flex-generated scanners to compile on their own).
- */
-typedef unsigned int yy_size_t;
-
-
-struct yy_buffer_state
-	{
-	FILE *yy_input_file;
-
-	char *yy_ch_buf;		/* input buffer */
-	char *yy_buf_pos;		/* current position in input buffer */
-
-	/* Size of input buffer in bytes, not including room for EOB
-	 * characters.
-	 */
-	yy_size_t yy_buf_size;
-
-	/* Number of characters read into yy_ch_buf, not including EOB
-	 * characters.
-	 */
-	int yy_n_chars;
-
-	/* Whether we "own" the buffer - i.e., we know we created it,
-	 * and can realloc() it to grow it, and should free() it to
-	 * delete it.
-	 */
-	int yy_is_our_buffer;
-
-	/* Whether this is an "interactive" input source; if so, and
-	 * if we're using stdio for input, then we want to use getc()
-	 * instead of fread(), to make sure we stop fetching input after
-	 * each newline.
-	 */
-	int yy_is_interactive;
-
-	/* Whether we're considered to be at the beginning of a line.
-	 * If so, '^' rules will be active on the next match, otherwise
-	 * not.
-	 */
-	int yy_at_bol;
-
-	/* Whether to try to fill the input buffer when we reach the
-	 * end of it.
-	 */
-	int yy_fill_buffer;
-
-	int yy_buffer_status;
-#define YY_BUFFER_NEW 0
-#define YY_BUFFER_NORMAL 1
-	/* When an EOF's been seen but there's still some text to process
-	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
-	 * shouldn't try reading from the input source any more.  We might
-	 * still have a bunch of tokens to match, though, because of
-	 * possible backing-up.
-	 *
-	 * When we actually see the EOF, we change the status to "new"
-	 * (via yyrestart()), so that the user can continue scanning by
-	 * just pointing yyin at a new input file.
-	 */
-#define YY_BUFFER_EOF_PENDING 2
-	};
-
-static YY_BUFFER_STATE yy_current_buffer = 0;
-
-/* We provide macros for accessing buffer states in case in the
- * future we want to put the buffer states in a more general
- * "scanner state".
- */
-#define YY_CURRENT_BUFFER yy_current_buffer
-
-
-/* yy_hold_char holds the character lost when yytext is formed. */
-static char yy_hold_char;
-
-static int yy_n_chars;		/* number of characters read into yy_ch_buf */
-
-
-int yyleng;
-
-/* Points to current character in buffer. */
-static char *yy_c_buf_p = (char *) 0;
-static int yy_init = 1;		/* whether we need to initialize */
-static int yy_start = 0;	/* start state number */
-
-/* Flag which is used to allow yywrap()'s to do buffer switches
- * instead of setting up a fresh yyin.  A bit of a hack ...
- */
-static int yy_did_buffer_switch_on_eof;
-
-void yyrestart YY_PROTO(( FILE *input_file ));
-
-void yy_switch_to_buffer YY_PROTO(( YY_BUFFER_STATE new_buffer ));
-void yy_load_buffer_state YY_PROTO(( void ));
-YY_BUFFER_STATE yy_create_buffer YY_PROTO(( FILE *file, int size ));
-void yy_delete_buffer YY_PROTO(( YY_BUFFER_STATE b ));
-void yy_init_buffer YY_PROTO(( YY_BUFFER_STATE b, FILE *file ));
-void yy_flush_buffer YY_PROTO(( YY_BUFFER_STATE b ));
-#define YY_FLUSH_BUFFER yy_flush_buffer( yy_current_buffer )
-
-YY_BUFFER_STATE yy_scan_buffer YY_PROTO(( char *base, yy_size_t size ));
-YY_BUFFER_STATE yy_scan_string YY_PROTO(( yyconst char *yy_str ));
-YY_BUFFER_STATE yy_scan_bytes YY_PROTO(( yyconst char *bytes, int len ));
-
-static void *yy_flex_alloc YY_PROTO(( yy_size_t ));
-static void *yy_flex_realloc YY_PROTO(( void *, yy_size_t ));
-static void yy_flex_free YY_PROTO(( void * ));
-
-#define yy_new_buffer yy_create_buffer
-
-#define yy_set_interactive(is_interactive) \
-	{ \
-	if ( ! yy_current_buffer ) \
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
-	yy_current_buffer->yy_is_interactive = is_interactive; \
-	}
-
-#define yy_set_bol(at_bol) \
-	{ \
-	if ( ! yy_current_buffer ) \
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
-	yy_current_buffer->yy_at_bol = at_bol; \
-	}
-
-#define YY_AT_BOL() (yy_current_buffer->yy_at_bol)
-
-typedef unsigned char YY_CHAR;
-FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
-typedef int yy_state_type;
-extern char *yytext;
-#define yytext_ptr yytext
-
-static yy_state_type yy_get_previous_state YY_PROTO(( void ));
-static yy_state_type yy_try_NUL_trans YY_PROTO(( yy_state_type current_state ));
-static int yy_get_next_buffer YY_PROTO(( void ));
-static void yy_fatal_error YY_PROTO(( yyconst char msg[] ));
-
-/* Done after the current pattern has been matched and before the
- * corresponding action - sets up yytext.
- */
-#define YY_DO_BEFORE_ACTION \
-	yytext_ptr = yy_bp; \
-	yyleng = (int) (yy_cp - yy_bp); \
-	yy_hold_char = *yy_cp; \
-	*yy_cp = '\0'; \
-	yy_c_buf_p = yy_cp;
-
-#define YY_NUM_RULES 238
-#define YY_END_OF_BUFFER 239
-static yyconst short int yy_accept[559] =
-    {   0,
-        0,    0,    0,    0,  239,  237,  235,  235,  220,  233,
-      219,  218,  200,  201,  216,  214,  211,  210,  203,  232,
-      232,  202,  221,  199,  195,  237,  224,  233,  148,  233,
-      233,  233,  233,  233,  233,  233,  233,  233,   70,  233,
-      233,  233,   54,   19,   18,  233,   12,   10,    8,    7,
-      189,  188,  187,  233,  185,  183,  233,  233,  233,  233,
-      233,  233,  217,  215,  213,  212,    0,  209,  204,    0,
-        0,    0,  232,  234,    0,  232,  234,  198,  196,  222,
-      194,  193,  178,  175,  233,  233,  233,  150,  151,  233,
-      233,  149,    0,  147,  233,  140,  233,  233,  136,  233,
-
-      125,  233,  123,  233,  233,  233,  233,  233,  233,  233,
-      103,  102,  101,  233,  100,   99,  233,  233,   97,  233,
-       95,   94,   93,   91,  233,   85,  233,  233,   77,   86,
-      233,   71,   69,  233,  233,  233,  233,   65,  233,  233,
-      233,   59,  233,   56,  233,  233,   53,  233,  233,  233,
-      233,  233,  233,  233,  233,  233,  233,  233,  233,   25,
-      233,  233,  233,  233,  233,   15,   14,  233,  233,  159,
-      233,  186,  233,  184,  223,  233,  233,   95,  233,  233,
-      233,  205,  207,  206,  208,    0,    0,  232,  232,  232,
-      232,  197,  191,  192,  233,  233,  171,  152,  153,  233,
-
-      233,  162,  163,  233,  154,  156,  232,  233,  233,  233,
-      233,  233,  233,  124,  233,  233,  119,  233,  233,  233,
-      233,  233,  233,  233,  233,  233,  179,   98,  233,  233,
-      233,  233,  233,  233,   80,   83,   78,   81,  233,  233,
-      233,   79,   82,  233,   67,   66,  233,   63,   62,  233,
-      233,  233,  233,  233,  233,  233,  233,  233,  233,   44,
-       39,   38,   37,   36,   35,   34,  233,   32,   31,  233,
-      233,  233,  233,  233,  233,  233,   21,  233,  233,   16,
-       13,  233,    9,  233,  233,  233,  233,  233,  233,  233,
-      236,  190,  170,  168,  177,  176,  169,  167,  174,  173,
-
-      233,  233,  233,  155,  157,  146,  233,  233,  233,  233,
-      139,  138,  233,  127,  233,  233,  118,  233,  233,  233,
-      233,  111,  110,  233,  233,  233,  233,  233,  233,  233,
-      105,  104,  233,  233,  233,   96,  233,   92,   89,   84,
-       74,  233,  233,   68,   64,  233,   61,   60,   58,   57,
-      233,   55,   45,  233,   50,   47,   49,   46,   48,  233,
-      233,   43,   42,  233,  233,  233,  233,  233,   27,   24,
-       23,  233,  233,  233,  233,  233,  233,  228,  233,  227,
-      233,  233,  233,  233,  160,  233,  233,  233,  233,  233,
-      233,  233,  233,  233,  233,  122,  233,  117,  116,  233,
-
-      233,  233,  233,  233,  233,  233,  233,  108,  233,  233,
-      233,  233,  233,  233,  233,  233,  233,  233,    2,  182,
-       52,   41,   40,   33,  233,  233,  233,   30,  233,   22,
-      233,  233,  233,  172,  231,  233,  233,  233,  233,  233,
-      164,  161,  145,  144,  143,  142,  141,  233,  233,  233,
-      233,  126,  121,  233,  233,  233,  233,  233,   51,  233,
-      233,  107,  233,  233,  233,  233,  233,   88,   87,   90,
-      233,  233,   73,   72,   29,  233,  233,  233,   20,  233,
-      233,  233,  229,  233,  226,  165,  166,  233,  233,  233,
-      233,  233,  233,  120,  233,  114,  113,  233,  233,  233,
-
-        5,  106,  233,  180,  233,  233,  233,  233,   28,  233,
-      233,   17,   11,  233,  233,  233,  233,  135,  133,  134,
-      132,  129,  233,  115,  233,    6,  109,  233,  233,    3,
-      233,   76,    1,   26,  230,  225,  137,  130,  131,  233,
-      233,  233,  233,  233,  128,  233,  233,    4,   75,  233,
-      233,  112,  233,  233,  233,  233,  181,    0
-    } ;
-
-static yyconst int yy_ec[256] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    2,    4,    1,    5,    6,    7,    8,    1,    9,
-       10,   11,   12,   13,   14,   15,   16,   17,   18,   19,
-       20,   21,   22,   23,   24,   25,   26,   27,   28,   29,
-       30,   31,    1,   32,   33,   34,   35,   36,   37,   38,
-       39,   40,   41,   42,   43,   44,   45,   46,   47,   48,
-       49,   50,   51,   52,   53,   54,   55,   56,   57,   58,
-       59,    1,   60,   61,   62,    1,   63,   64,   35,   36,
-
-       37,   38,   39,   40,   41,   42,   43,   44,   45,   46,
-       65,   48,   49,   66,   51,   67,   53,   54,   55,   56,
-       57,   58,    1,   68,    1,   69,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1
-    } ;
-
-static yyconst int yy_meta[70] =
-    {   0,
-        1,    1,    2,    1,    1,    3,    1,    1,    1,    1,
-        1,    1,    1,    1,    3,    1,    4,    4,    4,    4,
-        4,    4,    4,    4,    4,    4,    1,    1,    1,    1,
-        1,    1,    5,    4,    5,    5,    5,    4,    3,    3,
-        3,    3,    3,    3,    3,    3,    3,    3,    3,    3,
-        3,    3,    3,    3,    3,    3,    3,    3,    1,    1,
-        1,    3,    5,    4,    3,    3,    3,    1,    1
-    } ;
-
-static yyconst short int yy_base[565] =
-    {   0,
-        0,    0,   32,   33,  814,  815,  815,  815,  815,    0,
-      815,  783,  815,  815,  782,   60,  815,   61,  800,  113,
-       44,  815,  815,   54,   75,  779,  815,  161,  221,   59,
-       84,   42,   92,  105,  109,  148,  756,  271,  141,   48,
-      110,  322,  372,  421,  153,  757,   60,  787,    0,    0,
-      815,  815,  776,  741,   58,  815,  141,   64,  763,   43,
-       61,    0,  815,  815,  815,  815,  105,  815,  815,  129,
-      792,  210,  225,  235,  472,  275,  815,  772,  815,  815,
-      815,  145,  786,  785,  748,  163,  757,    0,    0,  263,
-      185,    0,    0,  782,  131,    0,  759,   97,  154,  751,
-
-        0,  753,    0,  736,  757,  752,  742,   69,  736,  279,
-      773,  741,    0,  156,    0,    0,  157,  749,  770,  740,
-        0,    0,  732,    0,  737,  766,  196,  199,    0,  153,
-      226,  247,  765,  723,  732,  220,  280,    0,  221,  740,
-      170,  761,  740,    0,  250,  728,  758,  731,  252,  735,
-      257,  308,  260,  248,  269,  288,  281,  729,  730,  753,
-      710,  725,  714,  713,  710,    0,    0,  714,  298,    0,
-      742,  815,  219,  815,  815,  707,  715,  714,  711,  174,
-      712,  815,  815,  815,  815,  744,  138,  356,  408,    0,
-        0,  815,  815,  724,  312,  343,    0,    0,    0,  714,
-
-      711,    0,    0,  249,  700,  699,    0,  232,  369,  695,
-      303,  711,  703,    0,  700,  701,  375,  337,  337,  122,
-      238,  338,  378,  347,  239,  709,  725,    0,  356,  318,
-      705,  722,  692,  363,    0,    0,    0,    0,  691,  390,
-      697,    0,    0,  372,    0,    0,  689,    0,    0,  700,
-      684,  699,  403,  690,  684,  393,  436,  680,  474,  431,
-        0,    0,    0,    0,    0,    0,  684,    0,    0,  398,
-      678,  401,  690,  681,  437,  680,    0,  690,  401,    0,
-        0,  662,    0,  657,  671,  684,  667,  676,  680,  676,
-      705,  815,    0,    0,    0,    0,    0,    0,    0,    0,
-
-      669,  676,  434,    0,    0,    0,  669,  659,  674,  448,
-        0,  659,  466,  694,  673,  670,  439,  661,  411,  654,
-      660,    0,    0,  419,  422,  647,  649,  450,  665,  470,
-        0,    0,  664,  675,  462,    0,  636,    0,  682,    0,
-      634,  642,  656,    0,    0,  656,    0,    0,    0,    0,
-      657,    0,    0,  654,    0,    0,    0,    0,    0,  671,
-      672,    0,    0,  652,  652,  470,  649,  471,  470,    0,
-        0,  650,  646,  632,  637,  614,  640,  617,  627,    0,
-      640,  630,  521,  474,    0,  466,  619,  475,  630,  477,
-      633,  624,  485,  625,  614,    0,  618,    0,    0,  620,
-
-      623,  625,  626,  611,  491,  628,  611,    0,  619,  625,
-      622,  613,  622,  495,  503,  487,  608,  497,    0,    0,
-        0,    0,    0,    0,  615,  517,  603,    0,  612,    0,
-      613,  614,  519,    0,  609,  609,  501,  605,  624,  625,
-        0,    0,    0,    0,    0,    0,    0,  604,  537,  609,
-      595,    0,  623,  597,  508,  510,  594,  588,    0,  590,
-      600,    0,  511,  585,  614,  532,  597,    0,    0,    0,
-      596,  586,    0,    0,    0,  514,  594,  517,    0,  518,
-      574,  583,    0,  593,    0,    0,    0,  589,  544,  315,
-      578,  582,  538,    0,  568,    0,    0,  586,  578,  520,
-
-        0,    0,  575,    0,  551,  554,  563,  564,    0,  521,
-      548,    0,    0,  543,  556,  522,  418,    0,    0,    0,
-        0,    0,  558,    0,  535,    0,    0,  524,  528,    0,
-      424,    0,    0,    0,    0,    0,    0,    0,    0,  403,
-      388,  378,  324,  279,    0,  272,  529,    0,    0,  531,
-      538,    0,  262,  168,   82,   83,    0,  815,  603,  608,
-       92,  613,  615,  617
-    } ;
-
-static yyconst short int yy_def[565] =
-    {   0,
-      558,    1,    1,    1,  558,  558,  558,  558,  558,  559,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  560,
-      561,  558,  558,  558,  558,  558,  558,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      558,  558,  558,   28,  558,  558,  559,   36,   38,   42,
-      559,  559,  558,  558,  558,  558,  558,  558,  558,  558,
-      562,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  563,  559,  559,  559,  559,  559,  559,  559,
-
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  558,  559,  558,  558,  559,  559,  559,  559,  559,
-      559,  558,  558,  558,  558,  562,  562,  558,  558,   75,
-      564,  558,  558,  558,  559,  559,  559,  559,  559,  559,
-
-      559,  559,  559,  559,  559,  559,  563,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      562,  558,  559,  559,  559,  559,  559,  559,  559,  559,
-
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
-      559,  559,  559,  559,  559,  559,  559,    0,  558,  558,
-      558,  558,  558,  558
-    } ;
-
-static yyconst short int yy_nxt[885] =
-    {   0,
-        6,    7,    8,    9,    6,   10,   11,   12,   13,   14,
-       15,   16,   17,   18,   10,   19,   20,   21,   21,   21,
-       21,   21,   21,   21,   21,   21,   22,   23,   24,   25,
-       26,   27,   28,   29,   30,   31,   32,   33,   34,   35,
-       36,   37,   10,   38,   39,   40,   41,   42,   10,   43,
-       44,   45,   46,   47,   48,   49,   10,   50,   51,   52,
-       53,   10,   54,   29,   41,   43,   45,   55,   56,   57,
-       57,   65,   58,   58,   68,   59,   59,   77,   80,   60,
-       60,   77,   78,   79,   61,   61,  109,  174,   93,   66,
-       69,  100,  180,  101,  137,   76,   93,  110,  138,  177,
-
-      169,  178,  102,  557,   81,  103,  181,   77,  180,  104,
-      170,  168,  137,   93,   93,  105,  182,  106,  183,  219,
-      107,  100,  220,  103,  108,  175,  556,   67,   70,   73,
-       73,   73,   73,   73,   73,   73,   73,   73,   73,  111,
-      184,  113,  185,  211,  112,   93,   74,  106,  187,  116,
-       74,  114,  117,  291,  139,  140,  115,  133,  133,  133,
-      133,  211,  141,  118,  119,  119,  119,  119,   75,  114,
-      322,  115,  323,  134,  193,  194,   74,   83,   84,  198,
-      199,  135,  209,  120,  176,  121,  136,  122,  111,  164,
-      165,  555,  166,  112,   85,   86,  167,  209,  123,  239,
-
-      124,  205,  206,  134,   87,  212,   88,  227,  228,   89,
-      289,   90,  235,  236,   91,  237,  238,  239,   92,  256,
-      212,  252,  227,  228,   85,   93,  188,  188,  188,  188,
-      188,  188,  188,  188,  188,  188,  252,   94,   94,   94,
-       94,  189,  189,  189,  189,  189,  189,  189,  189,  189,
-      189,  188,  188,  188,  188,  188,  188,  188,  188,  188,
-      188,   95,  240,  242,  243,  241,  247,  250,   96,  197,
-       97,  306,  324,  325,  326,  306,   98,   99,  331,  554,
-      268,  303,  332,  284,  247,  250,   97,  126,  126,  126,
-      126,   76,   76,   76,   76,   76,   76,   76,   76,   76,
-
-       76,  255,  201,  259,  127,  128,  202,  129,  261,  267,
-      268,  303,  203,  222,  204,  269,  255,  130,  259,  550,
-      270,  131,  132,  261,  549,  267,  223,  248,  203,  204,
-      224,  249,  272,  269,  127,  130,  271,  132,  142,  142,
-      142,  142,  142,  142,  262,  224,  249,  272,  263,  282,
-      270,  293,  312,  264,  143,  294,  144,  336,  265,  519,
-      548,  336,  520,  266,  282,  145,  295,  296,  312,  321,
-      327,  146,  188,  188,  188,  188,  188,  188,  188,  188,
-      188,  188,  297,  320,  143,  328,  298,  146,  147,  147,
-      147,  147,  147,  147,  147,  147,  330,  299,  300,  321,
-
-      327,  320,  340,  307,  148,  335,  340,  317,  149,  318,
-      329,  344,  330,  308,  319,  344,  547,  150,  151,  309,
-      310,  335,  546,  152,  189,  189,  189,  189,  189,  189,
-      189,  189,  189,  189,  148,  310,  151,  317,  152,  153,
-      329,  342,  349,  401,  352,  545,  349,  365,  360,  361,
-      367,  404,  374,  154,  405,  155,  342,  156,  157,  352,
-      158,  159,  538,  365,  544,  539,  367,  374,  160,  353,
-      362,  161,  162,  401,  363,  353,  370,  163,  398,  353,
-      371,  404,  399,  154,  405,  385,  389,  162,  190,  190,
-      190,  190,  190,  190,  190,  190,  190,  190,  390,  353,
-
-      385,  408,  410,  429,  191,  191,  191,  191,  191,  191,
-      355,  413,  392,  393,  356,  443,  408,  450,  394,  357,
-      471,  426,  428,  472,  358,  442,  445,  413,  447,  359,
-      392,  443,  410,  429,  191,  191,  426,  428,  439,  440,
-      442,  445,  459,  447,  467,  441,  468,  450,  474,  476,
-      471,  481,  484,  469,  489,  490,  491,  459,  470,  496,
-      467,  497,  502,  474,  505,  509,  517,  484,  511,  512,
-      523,  527,  533,  537,  496,  551,  497,  502,  543,  476,
-      509,  481,  552,  511,  512,  542,  527,  533,  537,  553,
-      541,  518,  540,  551,  505,  536,  535,  552,  534,  532,
-
-      523,  531,  530,  529,  553,   62,   62,   62,   72,  528,
-       72,   72,   72,  186,  526,  186,  186,  186,  207,  207,
-      191,  191,  525,  524,  522,  521,  516,  515,  514,  513,
-      510,  508,  507,  506,  504,  503,  501,  500,  499,  498,
-      495,  494,  493,  492,  488,  487,  486,  485,  483,  482,
-      480,  479,  478,  477,  475,  473,  466,  465,  464,  463,
-      462,  461,  460,  458,  457,  456,  455,  454,  453,  452,
-      451,  449,  448,  446,  444,  438,  437,  436,  414,  435,
-      434,  433,  432,  431,  430,  427,  425,  424,  423,  422,
-      421,  420,  419,  418,  417,  416,  415,  414,  412,  411,
-
-      409,  407,  406,  403,  402,  400,  397,  396,  395,  391,
-      388,  387,  386,  384,  383,  187,  382,  381,  380,  379,
-      378,  377,  376,  375,  373,  372,  369,  368,  366,  364,
-      354,  351,  350,  348,  347,  346,  345,  343,  341,  339,
-      338,  337,  334,  333,  316,  315,  314,  313,  311,  305,
-      304,  302,  301,  292,  187,  290,  288,  287,  286,  285,
-      283,  281,  280,  279,  278,  277,  276,  275,  274,  273,
-      260,  258,  257,  256,  254,  253,  251,  246,  245,  244,
-      234,  233,  232,  231,  230,  229,  226,  225,  221,  218,
-      217,  216,  215,  214,  213,  210,  208,  200,  197,  196,
-
-      195,  192,  187,  179,  173,  172,  171,  168,  125,   82,
-       71,   64,   63,  558,    5,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558
-    } ;
-
-static yyconst short int yy_chk[885] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    3,
-        4,   16,    3,    4,   18,    3,    4,   21,   25,    3,
-        4,   21,   24,   24,    3,    4,   32,   55,   31,   16,
-       18,   30,   60,   30,   40,  561,   33,   32,   40,   58,
-
-       47,   58,   30,  556,   25,   30,   61,   21,   60,   30,
-       47,   61,   40,   35,   41,   30,   67,   31,   67,  108,
-       31,   30,  108,   30,   31,   55,  555,   16,   18,   20,
-       20,   20,   20,   20,   20,   20,   20,   20,   20,   33,
-       70,   34,   70,   98,   33,   57,   20,   31,  187,   35,
-       20,   34,   35,  187,   41,   41,   34,   39,   39,   39,
-       39,   98,   41,   35,   36,   36,   36,   36,   20,   34,
-      220,   34,  220,   39,   82,   82,   20,   28,   28,   86,
-       86,   39,   95,   36,   57,   36,   39,   36,   57,   45,
-       45,  554,   45,   57,   28,   28,   45,   95,   36,  130,
-
-       36,   91,   91,   39,   28,   99,   28,  114,  117,   28,
-      180,   28,  127,  127,   28,  128,  128,  130,   28,  180,
-       99,  141,  114,  117,   28,   29,   72,   72,   72,   72,
-       72,   72,   72,   72,   72,   72,  141,   29,   29,   29,
-       29,   73,   73,   73,   73,   73,   73,   73,   73,   73,
-       73,   74,   74,   74,   74,   74,   74,   74,   74,   74,
-       74,   29,  131,  132,  132,  131,  136,  139,   29,  173,
-       29,  208,  221,  221,  221,  208,   29,   29,  225,  553,
-      154,  204,  225,  173,  136,  139,   29,   38,   38,   38,
-       38,   76,   76,   76,   76,   76,   76,   76,   76,   76,
-
-       76,  145,   90,  149,   38,   38,   90,   38,  151,  153,
-      154,  204,   90,  110,   90,  155,  145,   38,  149,  546,
-      156,   38,   38,  151,  544,  153,  110,  137,   90,   90,
-      110,  137,  157,  155,   38,   38,  156,   38,   42,   42,
-       42,   42,   42,   42,  152,  110,  137,  157,  152,  169,
-      156,  195,  211,  152,   42,  195,   42,  230,  152,  490,
-      543,  230,  490,  152,  169,   42,  195,  195,  211,  219,
-      222,   42,  188,  188,  188,  188,  188,  188,  188,  188,
-      188,  188,  196,  218,   42,  222,  196,   42,   43,   43,
-       43,   43,   43,   43,   43,   43,  224,  196,  196,  219,
-
-      222,  218,  234,  209,   43,  229,  234,  217,   43,  217,
-      223,  244,  224,  209,  217,  244,  542,   43,   43,  209,
-      209,  229,  541,   43,  189,  189,  189,  189,  189,  189,
-      189,  189,  189,  189,   43,  209,   43,  217,   43,   44,
-      223,  240,  253,  319,  256,  540,  253,  270,  260,  260,
-      272,  324,  279,   44,  325,   44,  240,   44,   44,  256,
-       44,   44,  517,  270,  531,  517,  272,  279,   44,  257,
-      260,   44,   44,  319,  260,  257,  275,   44,  317,  257,
-      275,  324,  317,   44,  325,  303,  310,   44,   75,   75,
-       75,   75,   75,   75,   75,   75,   75,   75,  310,  257,
-
-      303,  328,  330,  369,   75,   75,   75,   75,   75,   75,
-      259,  335,  313,  313,  259,  386,  328,  393,  313,  259,
-      416,  366,  368,  416,  259,  384,  388,  335,  390,  259,
-      313,  386,  330,  369,   75,   75,  366,  368,  383,  383,
-      384,  388,  405,  390,  414,  383,  415,  393,  418,  426,
-      416,  433,  437,  415,  449,  449,  449,  405,  415,  455,
-      414,  456,  463,  418,  466,  476,  489,  437,  478,  480,
-      493,  500,  510,  516,  455,  547,  456,  463,  529,  426,
-      476,  433,  550,  478,  480,  528,  500,  510,  516,  551,
-      525,  489,  523,  547,  466,  515,  514,  550,  511,  508,
-
-      493,  507,  506,  505,  551,  559,  559,  559,  560,  503,
-      560,  560,  560,  562,  499,  562,  562,  562,  563,  563,
-      564,  564,  498,  495,  492,  491,  488,  484,  482,  481,
-      477,  472,  471,  467,  465,  464,  461,  460,  458,  457,
-      454,  453,  451,  450,  448,  440,  439,  438,  436,  435,
-      432,  431,  429,  427,  425,  417,  413,  412,  411,  410,
-      409,  407,  406,  404,  403,  402,  401,  400,  397,  395,
-      394,  392,  391,  389,  387,  382,  381,  379,  378,  377,
-      376,  375,  374,  373,  372,  367,  365,  364,  361,  360,
-      354,  351,  346,  343,  342,  341,  339,  337,  334,  333,
-
-      329,  327,  326,  321,  320,  318,  316,  315,  314,  312,
-      309,  308,  307,  302,  301,  291,  290,  289,  288,  287,
-      286,  285,  284,  282,  278,  276,  274,  273,  271,  267,
-      258,  255,  254,  252,  251,  250,  247,  241,  239,  233,
-      232,  231,  227,  226,  216,  215,  213,  212,  210,  206,
-      205,  201,  200,  194,  186,  181,  179,  178,  177,  176,
-      171,  168,  165,  164,  163,  162,  161,  160,  159,  158,
-      150,  148,  147,  146,  143,  142,  140,  135,  134,  133,
-      126,  125,  123,  120,  119,  118,  112,  111,  109,  107,
-      106,  105,  104,  102,  100,   97,   94,   87,   85,   84,
-
-       83,   78,   71,   59,   54,   53,   48,   46,   37,   26,
-       19,   15,   12,    5,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
-      558,  558,  558,  558
-    } ;
-
-static yy_state_type yy_last_accepting_state;
-static char *yy_last_accepting_cpos;
-
-/* The intent behind this definition is that it'll catch
- * any uses of REJECT which flex missed.
- */
-#define REJECT reject_used_but_not_detected
-#define yymore() yymore_used_but_not_detected
-#define YY_MORE_ADJ 0
-#define YY_RESTORE_YY_MORE_OFFSET
-char *yytext;
-#line 1 "bfin-lex.l"
-#define INITIAL 0
-/* bfin-lex.l  ADI Blackfin lexer
-   Copyright 2005
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-#line 22 "bfin-lex.l"
-
-#include <stdlib.h>
-#include <string.h>
-#include "bfin-defs.h"
-#include "bfin-parse.h"
-#include "as.h"
-
-static long parse_int (char **end);
-static int parse_halfreg (Register *r, int cl, char *hr);
-static int parse_reg (Register *r, int type, char *rt);
-int yylex (void);
-
-#define _REG yylval.reg
-
-
-/* Define Start States ... Actually we will use exclusion.
-   If no start state is specified it should match any state
-   and <INITIAL> would match some keyword rules only with
-   initial.  */
-#define KEYWORD 1
-
-#line 788 "bfin-lex.c"
-
-/* Macros after this point can all be overridden by user definitions in
- * section 1.
- */
-
-#ifndef YY_SKIP_YYWRAP
-#ifdef __cplusplus
-extern "C" int yywrap YY_PROTO(( void ));
-#else
-extern int yywrap YY_PROTO(( void ));
-#endif
-#endif
-
-#ifndef YY_NO_UNPUT
-static void yyunput YY_PROTO(( int c, char *buf_ptr ));
-#endif
-
-#ifndef yytext_ptr
-static void yy_flex_strncpy YY_PROTO(( char *, yyconst char *, int ));
-#endif
-
-#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen YY_PROTO(( yyconst char * ));
-#endif
-
-#ifndef YY_NO_INPUT
-#ifdef __cplusplus
-static int yyinput YY_PROTO(( void ));
-#else
-static int input YY_PROTO(( void ));
-#endif
-#endif
-
-#if YY_STACK_USED
-static int yy_start_stack_ptr = 0;
-static int yy_start_stack_depth = 0;
-static int *yy_start_stack = 0;
-#ifndef YY_NO_PUSH_STATE
-static void yy_push_state YY_PROTO(( int new_state ));
-#endif
-#ifndef YY_NO_POP_STATE
-static void yy_pop_state YY_PROTO(( void ));
-#endif
-#ifndef YY_NO_TOP_STATE
-static int yy_top_state YY_PROTO(( void ));
-#endif
-
-#else
-#define YY_NO_PUSH_STATE 1
-#define YY_NO_POP_STATE 1
-#define YY_NO_TOP_STATE 1
-#endif
-
-#ifdef YY_MALLOC_DECL
-YY_MALLOC_DECL
-#else
-#if __STDC__
-#ifndef __cplusplus
-#include <stdlib.h>
-#endif
-#else
-/* Just try to get by without declaring the routines.  This will fail
- * miserably on non-ANSI systems for which sizeof(size_t) != sizeof(int)
- * or sizeof(void*) != sizeof(int).
- */
-#endif
-#endif
-
-/* Amount of stuff to slurp up with each read. */
-#ifndef YY_READ_BUF_SIZE
-#define YY_READ_BUF_SIZE 8192
-#endif
-
-/* Copy whatever the last rule matched to the standard output. */
-
-#ifndef ECHO
-/* This used to be an fputs(), but since the string might contain NUL's,
- * we now use fwrite().
- */
-#define ECHO (void) fwrite( yytext, yyleng, 1, yyout )
-#endif
-
-/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
- * is returned in "result".
- */
-#ifndef YY_INPUT
-#define YY_INPUT(buf,result,max_size) \
-	if ( yy_current_buffer->yy_is_interactive ) \
-		{ \
-		int c = '*', n; \
-		for ( n = 0; n < max_size && \
-			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
-			buf[n] = (char) c; \
-		if ( c == '\n' ) \
-			buf[n++] = (char) c; \
-		if ( c == EOF && ferror( yyin ) ) \
-			YY_FATAL_ERROR( "input in flex scanner failed" ); \
-		result = n; \
-		} \
-	else \
-		{ \
-		errno=0; \
-		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
-			{ \
-			if( errno != EINTR) \
-				{ \
-				YY_FATAL_ERROR( "input in flex scanner failed" ); \
-				break; \
-				} \
-			errno=0; \
-			clearerr(yyin); \
-			} \
-		}
-#endif
-
-/* No semi-colon after return; correct usage is to write "yyterminate();" -
- * we don't want an extra ';' after the "return" because that will cause
- * some compilers to complain about unreachable statements.
- */
-#ifndef yyterminate
-#define yyterminate() return YY_NULL
-#endif
-
-/* Number of entries by which start-condition stack grows. */
-#ifndef YY_START_STACK_INCR
-#define YY_START_STACK_INCR 25
-#endif
-
-/* Report a fatal error. */
-#ifndef YY_FATAL_ERROR
-#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
-#endif
-
-/* Default declaration of generated scanner - a define so the user can
- * easily add parameters.
- */
-#ifndef YY_DECL
-#define YY_DECL int yylex YY_PROTO(( void ))
-#endif
-
-/* Code executed at the beginning of each rule, after yytext and yyleng
- * have been set up.
- */
-#ifndef YY_USER_ACTION
-#define YY_USER_ACTION
-#endif
-
-/* Code executed at the end of each rule. */
-#ifndef YY_BREAK
-#define YY_BREAK break;
-#endif
-
-#define YY_RULE_SETUP \
-	YY_USER_ACTION
-
-YY_DECL
-	{
-	register yy_state_type yy_current_state;
-	register char *yy_cp, *yy_bp;
-	register int yy_act;
-
-#line 45 "bfin-lex.l"
-
-#line 952 "bfin-lex.c"
-
-	if ( yy_init )
-		{
-		yy_init = 0;
-
-#ifdef YY_USER_INIT
-		YY_USER_INIT;
-#endif
-
-		if ( ! yy_start )
-			yy_start = 1;	/* first start state */
-
-		if ( ! yyin )
-			yyin = stdin;
-
-		if ( ! yyout )
-			yyout = stdout;
-
-		if ( ! yy_current_buffer )
-			yy_current_buffer =
-				yy_create_buffer( yyin, YY_BUF_SIZE );
-
-		yy_load_buffer_state();
-		}
-
-	while ( 1 )		/* loops until end-of-file is reached */
-		{
-		yy_cp = yy_c_buf_p;
-
-		/* Support of yytext. */
-		*yy_cp = yy_hold_char;
-
-		/* yy_bp points to the position in yy_ch_buf of the start of
-		 * the current run.
-		 */
-		yy_bp = yy_cp;
-
-		yy_current_state = yy_start;
-yy_match:
-		do
-			{
-			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
-			if ( yy_accept[yy_current_state] )
-				{
-				yy_last_accepting_state = yy_current_state;
-				yy_last_accepting_cpos = yy_cp;
-				}
-			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-				{
-				yy_current_state = (int) yy_def[yy_current_state];
-				if ( yy_current_state >= 559 )
-					yy_c = yy_meta[(unsigned int) yy_c];
-				}
-			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-			++yy_cp;
-			}
-		while ( yy_base[yy_current_state] != 815 );
-
-yy_find_action:
-		yy_act = yy_accept[yy_current_state];
-		if ( yy_act == 0 )
-			{ /* have to back up */
-			yy_cp = yy_last_accepting_cpos;
-			yy_current_state = yy_last_accepting_state;
-			yy_act = yy_accept[yy_current_state];
-			}
-
-		YY_DO_BEFORE_ACTION;
-
-
-do_action:	/* This label is used only to access EOF actions. */
-
-
-		switch ( yy_act )
-	{ /* beginning of action switch */
-			case 0: /* must back up */
-			/* undo the effects of YY_DO_BEFORE_ACTION */
-			*yy_cp = yy_hold_char;
-			yy_cp = yy_last_accepting_cpos;
-			yy_current_state = yy_last_accepting_state;
-			goto yy_find_action;
-
-case 1:
-YY_RULE_SETUP
-#line 46 "bfin-lex.l"
-_REG.regno = REG_sftreset;  return REG;
-	YY_BREAK
-case 2:
-YY_RULE_SETUP
-#line 47 "bfin-lex.l"
-_REG.regno = REG_omode;     return REG;
-	YY_BREAK
-case 3:
-YY_RULE_SETUP
-#line 48 "bfin-lex.l"
-_REG.regno = REG_idle_req;  return REG;
-	YY_BREAK
-case 4:
-YY_RULE_SETUP
-#line 49 "bfin-lex.l"
-_REG.regno = REG_hwerrcause; return REG;
-	YY_BREAK
-case 5:
-YY_RULE_SETUP
-#line 50 "bfin-lex.l"
-_REG.regno = REG_excause;   return REG;
-	YY_BREAK
-case 6:
-YY_RULE_SETUP
-#line 51 "bfin-lex.l"
-_REG.regno = REG_emucause;  return REG;
-	YY_BREAK
-case 7:
-YY_RULE_SETUP
-#line 52 "bfin-lex.l"
-return Z;
-	YY_BREAK
-case 8:
-YY_RULE_SETUP
-#line 53 "bfin-lex.l"
-return X;
-	YY_BREAK
-case 9:
-YY_RULE_SETUP
-#line 54 "bfin-lex.l"
-yylval.value = M_W32; return MMOD;
-	YY_BREAK
-case 10:
-YY_RULE_SETUP
-#line 55 "bfin-lex.l"
-return W;
-	YY_BREAK
-case 11:
-YY_RULE_SETUP
-#line 56 "bfin-lex.l"
-return VIT_MAX;
-	YY_BREAK
-case 12:
-YY_RULE_SETUP
-#line 57 "bfin-lex.l"
-return V; /* Special: V is a statflag and a modifier.  */
-	YY_BREAK
-case 13:
-YY_RULE_SETUP
-#line 58 "bfin-lex.l"
-_REG.regno = REG_USP; return REG;
-	YY_BREAK
-case 14:
-YY_RULE_SETUP
-#line 59 "bfin-lex.l"
-return TL;
-	YY_BREAK
-case 15:
-YY_RULE_SETUP
-#line 60 "bfin-lex.l"
-return TH;
-	YY_BREAK
-case 16:
-YY_RULE_SETUP
-#line 61 "bfin-lex.l"
-yylval.value = M_TFU; return MMOD;
-	YY_BREAK
-case 17:
-YY_RULE_SETUP
-#line 62 "bfin-lex.l"
-return TESTSET;
-	YY_BREAK
-case 18:
-YY_RULE_SETUP
-#line 63 "bfin-lex.l"
-yylval.value = M_T; return MMOD;
-	YY_BREAK
-case 19:
-YY_RULE_SETUP
-#line 64 "bfin-lex.l"
-return S;
-	YY_BREAK
-case 20:
-YY_RULE_SETUP
-#line 65 "bfin-lex.l"
-_REG.regno = REG_SYSCFG; return REG;
-	YY_BREAK
-case 21:
-YY_RULE_SETUP
-#line 66 "bfin-lex.l"
-return STI;
-	YY_BREAK
-case 22:
-YY_RULE_SETUP
-#line 67 "bfin-lex.l"
-return SSYNC;
-	YY_BREAK
-case 23:
-YY_RULE_SETUP
-#line 68 "bfin-lex.l"
-_REG.regno = REG_SP; return HALF_REG;
-	YY_BREAK
-case 24:
-YY_RULE_SETUP
-#line 69 "bfin-lex.l"
-_REG.regno = REG_SP | F_REG_HIGH; return HALF_REG;
-	YY_BREAK
-case 25:
-YY_RULE_SETUP
-#line 70 "bfin-lex.l"
-_REG.regno = REG_SP; return REG;
-	YY_BREAK
-case 26:
-YY_RULE_SETUP
-#line 71 "bfin-lex.l"
-return SIGNBITS;
-	YY_BREAK
-case 27:
-YY_RULE_SETUP
-#line 72 "bfin-lex.l"
-return SIGN;
-	YY_BREAK
-case 28:
-YY_RULE_SETUP
-#line 73 "bfin-lex.l"
-_REG.regno = REG_SEQSTAT; return REG;
-	YY_BREAK
-case 29:
-YY_RULE_SETUP
-#line 74 "bfin-lex.l"
-return SEARCH;
-	YY_BREAK
-case 30:
-YY_RULE_SETUP
-#line 75 "bfin-lex.l"
-return SHIFT;
-	YY_BREAK
-case 31:
-YY_RULE_SETUP
-#line 76 "bfin-lex.l"
-return SCO;
-	YY_BREAK
-case 32:
-YY_RULE_SETUP
-#line 78 "bfin-lex.l"
-return SAA;
-	YY_BREAK
-case 33:
-YY_RULE_SETUP
-#line 79 "bfin-lex.l"
-yylval.value = M_S2RND; return MMOD;
-	YY_BREAK
-case 34:
-YY_RULE_SETUP
-#line 80 "bfin-lex.l"
-return RTX;
-	YY_BREAK
-case 35:
-YY_RULE_SETUP
-#line 81 "bfin-lex.l"
-return RTS;
-	YY_BREAK
-case 36:
-YY_RULE_SETUP
-#line 82 "bfin-lex.l"
-return RTN;
-	YY_BREAK
-case 37:
-YY_RULE_SETUP
-#line 83 "bfin-lex.l"
-return RTI;
-	YY_BREAK
-case 38:
-YY_RULE_SETUP
-#line 84 "bfin-lex.l"
-return RTE;
-	YY_BREAK
-case 39:
-YY_RULE_SETUP
-#line 85 "bfin-lex.l"
-return ROT;
-	YY_BREAK
-case 40:
-YY_RULE_SETUP
-#line 86 "bfin-lex.l"
-return RND20;
-	YY_BREAK
-case 41:
-YY_RULE_SETUP
-#line 87 "bfin-lex.l"
-return RND12;
-	YY_BREAK
-case 42:
-YY_RULE_SETUP
-#line 88 "bfin-lex.l"
-return RNDL;
-	YY_BREAK
-case 43:
-YY_RULE_SETUP
-#line 89 "bfin-lex.l"
-return RNDH;
-	YY_BREAK
-case 44:
-YY_RULE_SETUP
-#line 90 "bfin-lex.l"
-return RND;
-	YY_BREAK
-case 45:
-YY_RULE_SETUP
-#line 92 "bfin-lex.l"
-return parse_halfreg(&yylval.reg, T_REG_R, yytext);
-	YY_BREAK
-case 46:
-YY_RULE_SETUP
-#line 94 "bfin-lex.l"
-_REG.regno = REG_RETS; return REG;
-	YY_BREAK
-case 47:
-YY_RULE_SETUP
-#line 95 "bfin-lex.l"
-_REG.regno = REG_RETI; return REG;
-	YY_BREAK
-case 48:
-YY_RULE_SETUP
-#line 96 "bfin-lex.l"
-_REG.regno = REG_RETX; return REG;
-	YY_BREAK
-case 49:
-YY_RULE_SETUP
-#line 97 "bfin-lex.l"
-_REG.regno = REG_RETN; return REG;
-	YY_BREAK
-case 50:
-YY_RULE_SETUP
-#line 98 "bfin-lex.l"
-_REG.regno = REG_RETE; return REG;
-	YY_BREAK
-case 51:
-YY_RULE_SETUP
-#line 99 "bfin-lex.l"
-_REG.regno = REG_EMUDAT; return REG;
-	YY_BREAK
-case 52:
-YY_RULE_SETUP
-#line 100 "bfin-lex.l"
-return RAISE;
-	YY_BREAK
-case 53:
-YY_RULE_SETUP
-#line 102 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_R, yytext);
-	YY_BREAK
-case 54:
-YY_RULE_SETUP
-#line 104 "bfin-lex.l"
-return R;
-	YY_BREAK
-case 55:
-YY_RULE_SETUP
-#line 105 "bfin-lex.l"
-return PRNT;
-	YY_BREAK
-case 56:
-YY_RULE_SETUP
-#line 106 "bfin-lex.l"
-return PC;
-	YY_BREAK
-case 57:
-YY_RULE_SETUP
-#line 107 "bfin-lex.l"
-return PACK;
-	YY_BREAK
-case 58:
-YY_RULE_SETUP
-#line 109 "bfin-lex.l"
-return parse_halfreg (&yylval.reg, T_REG_P, yytext);
-	YY_BREAK
-case 59:
-YY_RULE_SETUP
-#line 110 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_P, yytext);
-	YY_BREAK
-case 60:
-YY_RULE_SETUP
-#line 112 "bfin-lex.l"
-return OUTC;
-	YY_BREAK
-case 61:
-YY_RULE_SETUP
-#line 113 "bfin-lex.l"
-return ONES;
-	YY_BREAK
-case 62:
-YY_RULE_SETUP
-#line 115 "bfin-lex.l"
-return NOT;
-	YY_BREAK
-case 63:
-YY_RULE_SETUP
-#line 116 "bfin-lex.l"
-return NOP;
-	YY_BREAK
-case 64:
-YY_RULE_SETUP
-#line 117 "bfin-lex.l"
-return MNOP;
-	YY_BREAK
-case 65:
-YY_RULE_SETUP
-#line 118 "bfin-lex.l"
-return NS;
-	YY_BREAK
-case 66:
-YY_RULE_SETUP
-#line 121 "bfin-lex.l"
-return MIN;
-	YY_BREAK
-case 67:
-YY_RULE_SETUP
-#line 122 "bfin-lex.l"
-return MAX;
-	YY_BREAK
-case 68:
-YY_RULE_SETUP
-#line 124 "bfin-lex.l"
-return parse_halfreg (&yylval.reg, T_REG_M, yytext);
-	YY_BREAK
-case 69:
-YY_RULE_SETUP
-#line 125 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_M, yytext);
-	YY_BREAK
-case 70:
-YY_RULE_SETUP
-#line 127 "bfin-lex.l"
-return M;
-	YY_BREAK
-case 71:
-YY_RULE_SETUP
-#line 128 "bfin-lex.l"
-return LT;
-	YY_BREAK
-case 72:
-YY_RULE_SETUP
-#line 129 "bfin-lex.l"
-return LSHIFT;
-	YY_BREAK
-case 73:
-YY_RULE_SETUP
-#line 130 "bfin-lex.l"
-return LSETUP;
-	YY_BREAK
-case 74:
-YY_RULE_SETUP
-#line 131 "bfin-lex.l"
-return LOOP;
-	YY_BREAK
-case 75:
-YY_RULE_SETUP
-#line 132 "bfin-lex.l"
-return LOOP_BEGIN;
-	YY_BREAK
-case 76:
-YY_RULE_SETUP
-#line 133 "bfin-lex.l"
-return LOOP_END;
-	YY_BREAK
-case 77:
-YY_RULE_SETUP
-#line 135 "bfin-lex.l"
-return LE;
-	YY_BREAK
-case 78:
-YY_RULE_SETUP
-#line 136 "bfin-lex.l"
-_REG.regno = REG_LC0; return REG;
-	YY_BREAK
-case 79:
-YY_RULE_SETUP
-#line 137 "bfin-lex.l"
-_REG.regno = REG_LT0; return REG;
-	YY_BREAK
-case 80:
-YY_RULE_SETUP
-#line 138 "bfin-lex.l"
-_REG.regno = REG_LB0; return REG;
-	YY_BREAK
-case 81:
-YY_RULE_SETUP
-#line 139 "bfin-lex.l"
-_REG.regno = REG_LC1; return REG;
-	YY_BREAK
-case 82:
-YY_RULE_SETUP
-#line 140 "bfin-lex.l"
-_REG.regno = REG_LT1; return REG;
-	YY_BREAK
-case 83:
-YY_RULE_SETUP
-#line 141 "bfin-lex.l"
-_REG.regno = REG_LB1; return REG;
-	YY_BREAK
-case 84:
-YY_RULE_SETUP
-#line 143 "bfin-lex.l"
-return parse_halfreg (&yylval.reg, T_REG_L, yytext);
-	YY_BREAK
-case 85:
-YY_RULE_SETUP
-#line 144 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_L, yytext);
-	YY_BREAK
-case 86:
-YY_RULE_SETUP
-#line 145 "bfin-lex.l"
-return LO;
-	YY_BREAK
-case 87:
-YY_RULE_SETUP
-#line 146 "bfin-lex.l"
-{ BEGIN 0; return JUMP_DOT_S;}
-	YY_BREAK
-case 88:
-YY_RULE_SETUP
-#line 147 "bfin-lex.l"
-{ BEGIN 0; return JUMP_DOT_L;}
-	YY_BREAK
-case 89:
-YY_RULE_SETUP
-#line 148 "bfin-lex.l"
-{ BEGIN 0; return JUMP;}
-	YY_BREAK
-case 90:
-YY_RULE_SETUP
-#line 149 "bfin-lex.l"
-{ BEGIN 0; return JUMP_DOT_L; }
-	YY_BREAK
-case 91:
-YY_RULE_SETUP
-#line 150 "bfin-lex.l"
-yylval.value = M_IU;   return MMOD;
-	YY_BREAK
-case 92:
-YY_RULE_SETUP
-#line 151 "bfin-lex.l"
-yylval.value = M_ISS2; return MMOD;
-	YY_BREAK
-case 93:
-YY_RULE_SETUP
-#line 152 "bfin-lex.l"
-yylval.value = M_IS;   return MMOD;
-	YY_BREAK
-case 94:
-YY_RULE_SETUP
-#line 153 "bfin-lex.l"
-yylval.value = M_IH;   return MMOD;
-	YY_BREAK
-case 95:
-YY_RULE_SETUP
-#line 154 "bfin-lex.l"
-return IF;
-	YY_BREAK
-case 96:
-YY_RULE_SETUP
-#line 155 "bfin-lex.l"
-return parse_halfreg (&yylval.reg, T_REG_I, yytext);
-	YY_BREAK
-case 97:
-YY_RULE_SETUP
-#line 156 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_I, yytext);
-	YY_BREAK
-case 98:
-YY_RULE_SETUP
-#line 157 "bfin-lex.l"
-return HLT;
-	YY_BREAK
-case 99:
-YY_RULE_SETUP
-#line 158 "bfin-lex.l"
-return HI;
-	YY_BREAK
-case 100:
-YY_RULE_SETUP
-#line 159 "bfin-lex.l"
-return GT;
-	YY_BREAK
-case 101:
-YY_RULE_SETUP
-#line 160 "bfin-lex.l"
-return GE;
-	YY_BREAK
-case 102:
-YY_RULE_SETUP
-#line 161 "bfin-lex.l"
-yylval.value = M_FU; return MMOD;
-	YY_BREAK
-case 103:
-YY_RULE_SETUP
-#line 162 "bfin-lex.l"
-_REG.regno = REG_FP; return REG;
-	YY_BREAK
-case 104:
-YY_RULE_SETUP
-#line 163 "bfin-lex.l"
-_REG.regno = REG_FP; return HALF_REG;
-	YY_BREAK
-case 105:
-YY_RULE_SETUP
-#line 164 "bfin-lex.l"
-_REG.regno = REG_FP | F_REG_HIGH; return HALF_REG;
-	YY_BREAK
-case 106:
-YY_RULE_SETUP
-#line 166 "bfin-lex.l"
-return EXTRACT;
-	YY_BREAK
-case 107:
-YY_RULE_SETUP
-#line 167 "bfin-lex.l"
-return EXPADJ;
-	YY_BREAK
-case 108:
-YY_RULE_SETUP
-#line 168 "bfin-lex.l"
-return EXCPT;
-	YY_BREAK
-case 109:
-YY_RULE_SETUP
-#line 169 "bfin-lex.l"
-return EMUEXCPT;
-	YY_BREAK
-case 110:
-YY_RULE_SETUP
-#line 170 "bfin-lex.l"
-return DIVS;
-	YY_BREAK
-case 111:
-YY_RULE_SETUP
-#line 171 "bfin-lex.l"
-return DIVQ;
-	YY_BREAK
-case 112:
-YY_RULE_SETUP
-#line 172 "bfin-lex.l"
-return DISALGNEXCPT;
-	YY_BREAK
-case 113:
-YY_RULE_SETUP
-#line 173 "bfin-lex.l"
-return DEPOSIT;
-	YY_BREAK
-case 114:
-YY_RULE_SETUP
-#line 174 "bfin-lex.l"
-return DBGHALT;
-	YY_BREAK
-case 115:
-YY_RULE_SETUP
-#line 175 "bfin-lex.l"
-return DBGCMPLX;
-	YY_BREAK
-case 116:
-YY_RULE_SETUP
-#line 176 "bfin-lex.l"
-return DBGAL;
-	YY_BREAK
-case 117:
-YY_RULE_SETUP
-#line 177 "bfin-lex.l"
-return DBGAH;
-	YY_BREAK
-case 118:
-YY_RULE_SETUP
-#line 178 "bfin-lex.l"
-return DBGA;
-	YY_BREAK
-case 119:
-YY_RULE_SETUP
-#line 179 "bfin-lex.l"
-return DBG;
-	YY_BREAK
-case 120:
-YY_RULE_SETUP
-#line 180 "bfin-lex.l"
-{ _REG.regno = REG_CYCLES2; return REG; }
-	YY_BREAK
-case 121:
-YY_RULE_SETUP
-#line 181 "bfin-lex.l"
-{ _REG.regno = REG_CYCLES; return REG; }
-	YY_BREAK
-case 122:
-YY_RULE_SETUP
-#line 182 "bfin-lex.l"
-return CSYNC;
-	YY_BREAK
-case 123:
-YY_RULE_SETUP
-#line 183 "bfin-lex.l"
-return CO;
-	YY_BREAK
-case 124:
-YY_RULE_SETUP
-#line 184 "bfin-lex.l"
-return CLI;
-	YY_BREAK
-case 125:
-YY_RULE_SETUP
-#line 186 "bfin-lex.l"
-_REG.regno = REG_CC; return CCREG;
-	YY_BREAK
-case 126:
-YY_RULE_SETUP
-#line 187 "bfin-lex.l"
-{ BEGIN 0; return CALL;}
-	YY_BREAK
-case 127:
-YY_RULE_SETUP
-#line 188 "bfin-lex.l"
-{ BEGIN 0; return CALL;}
-	YY_BREAK
-case 128:
-YY_RULE_SETUP
-#line 189 "bfin-lex.l"
-return BYTEUNPACK;
-	YY_BREAK
-case 129:
-YY_RULE_SETUP
-#line 190 "bfin-lex.l"
-return BYTEPACK;
-	YY_BREAK
-case 130:
-YY_RULE_SETUP
-#line 191 "bfin-lex.l"
-return BYTEOP16M;
-	YY_BREAK
-case 131:
-YY_RULE_SETUP
-#line 192 "bfin-lex.l"
-return BYTEOP16P;
-	YY_BREAK
-case 132:
-YY_RULE_SETUP
-#line 193 "bfin-lex.l"
-return BYTEOP3P;
-	YY_BREAK
-case 133:
-YY_RULE_SETUP
-#line 194 "bfin-lex.l"
-return BYTEOP2M;
-	YY_BREAK
-case 134:
-YY_RULE_SETUP
-#line 195 "bfin-lex.l"
-return BYTEOP2P;
-	YY_BREAK
-case 135:
-YY_RULE_SETUP
-#line 196 "bfin-lex.l"
-return BYTEOP1P;
-	YY_BREAK
-case 136:
-YY_RULE_SETUP
-#line 197 "bfin-lex.l"
-return BY;
-	YY_BREAK
-case 137:
-YY_RULE_SETUP
-#line 198 "bfin-lex.l"
-return BXORSHIFT;
-	YY_BREAK
-case 138:
-YY_RULE_SETUP
-#line 199 "bfin-lex.l"
-return BXOR;
-	YY_BREAK
-case 139:
-YY_RULE_SETUP
-#line 201 "bfin-lex.l"
-return BREV;
-	YY_BREAK
-case 140:
-YY_RULE_SETUP
-#line 202 "bfin-lex.l"
-return BP;
-	YY_BREAK
-case 141:
-YY_RULE_SETUP
-#line 203 "bfin-lex.l"
-return BITTST;
-	YY_BREAK
-case 142:
-YY_RULE_SETUP
-#line 204 "bfin-lex.l"
-return BITTGL;
-	YY_BREAK
-case 143:
-YY_RULE_SETUP
-#line 205 "bfin-lex.l"
-return BITSET;
-	YY_BREAK
-case 144:
-YY_RULE_SETUP
-#line 206 "bfin-lex.l"
-return BITMUX;
-	YY_BREAK
-case 145:
-YY_RULE_SETUP
-#line 207 "bfin-lex.l"
-return BITCLR;
-	YY_BREAK
-case 146:
-YY_RULE_SETUP
-#line 208 "bfin-lex.l"
-return parse_halfreg (&yylval.reg, T_REG_B, yytext);
-	YY_BREAK
-case 147:
-YY_RULE_SETUP
-#line 209 "bfin-lex.l"
-return parse_reg (&yylval.reg, T_REG_B, yytext);
-	YY_BREAK
-case 148:
-YY_RULE_SETUP
-#line 210 "bfin-lex.l"
-return B;
-	YY_BREAK
-case 149:
-YY_RULE_SETUP
-#line 211 "bfin-lex.l"
-_REG.regno = S_AZ;   return STATUS_REG;
-	YY_BREAK
-case 150:
-YY_RULE_SETUP
-#line 212 "bfin-lex.l"
-_REG.regno = S_AN;   return STATUS_REG;
-	YY_BREAK
-case 151:
-YY_RULE_SETUP
-#line 213 "bfin-lex.l"
-_REG.regno = S_AQ;   return STATUS_REG;
-	YY_BREAK
-case 152:
-YY_RULE_SETUP
-#line 214 "bfin-lex.l"
-_REG.regno = S_AC0;  return STATUS_REG;
-	YY_BREAK
-case 153:
-YY_RULE_SETUP
-#line 215 "bfin-lex.l"
-_REG.regno = S_AC1;  return STATUS_REG;
-	YY_BREAK
-case 154:
-YY_RULE_SETUP
-#line 216 "bfin-lex.l"
-_REG.regno = S_AV0;  return STATUS_REG;
-	YY_BREAK
-case 155:
-YY_RULE_SETUP
-#line 217 "bfin-lex.l"
-_REG.regno = S_AV0S; return STATUS_REG;
-	YY_BREAK
-case 156:
-YY_RULE_SETUP
-#line 218 "bfin-lex.l"
-_REG.regno = S_AV1;  return STATUS_REG;
-	YY_BREAK
-case 157:
-YY_RULE_SETUP
-#line 219 "bfin-lex.l"
-_REG.regno = S_AV1S; return STATUS_REG;
-	YY_BREAK
-case 158:
-YY_RULE_SETUP
-#line 220 "bfin-lex.l"
-_REG.regno = S_V; return STATUS_REG;
-	YY_BREAK
-case 159:
-YY_RULE_SETUP
-#line 221 "bfin-lex.l"
-_REG.regno = S_VS;   return STATUS_REG;
-	YY_BREAK
-case 160:
-YY_RULE_SETUP
-#line 224 "bfin-lex.l"
-_REG.regno = REG_ASTAT; return REG;
-	YY_BREAK
-case 161:
-YY_RULE_SETUP
-#line 225 "bfin-lex.l"
-return ASHIFT;
-	YY_BREAK
-case 162:
-YY_RULE_SETUP
-#line 226 "bfin-lex.l"
-return ASL;
-	YY_BREAK
-case 163:
-YY_RULE_SETUP
-#line 227 "bfin-lex.l"
-return ASR;
-	YY_BREAK
-case 164:
-YY_RULE_SETUP
-#line 228 "bfin-lex.l"
-return ALIGN8;
-	YY_BREAK
-case 165:
-YY_RULE_SETUP
-#line 229 "bfin-lex.l"
-return ALIGN16;
-	YY_BREAK
-case 166:
-YY_RULE_SETUP
-#line 230 "bfin-lex.l"
-return ALIGN24;
-	YY_BREAK
-case 167:
-YY_RULE_SETUP
-#line 231 "bfin-lex.l"
-return A_ONE_DOT_L;
-	YY_BREAK
-case 168:
-YY_RULE_SETUP
-#line 232 "bfin-lex.l"
-return A_ZERO_DOT_L;
-	YY_BREAK
-case 169:
-YY_RULE_SETUP
-#line 233 "bfin-lex.l"
-return A_ONE_DOT_H;
-	YY_BREAK
-case 170:
-YY_RULE_SETUP
-#line 234 "bfin-lex.l"
-return A_ZERO_DOT_H;
-	YY_BREAK
-case 171:
-YY_RULE_SETUP
-#line 235 "bfin-lex.l"
-return ABS;
-	YY_BREAK
-case 172:
-YY_RULE_SETUP
-#line 236 "bfin-lex.l"
-return ABORT;
-	YY_BREAK
-case 173:
-YY_RULE_SETUP
-#line 237 "bfin-lex.l"
-_REG.regno = REG_A1x; return REG;
-	YY_BREAK
-case 174:
-YY_RULE_SETUP
-#line 238 "bfin-lex.l"
-_REG.regno = REG_A1w; return REG;
-	YY_BREAK
-case 175:
-YY_RULE_SETUP
-#line 239 "bfin-lex.l"
-_REG.regno = REG_A1;  return REG_A_DOUBLE_ONE;
-	YY_BREAK
-case 176:
-YY_RULE_SETUP
-#line 240 "bfin-lex.l"
-_REG.regno = REG_A0x; return REG;
-	YY_BREAK
-case 177:
-YY_RULE_SETUP
-#line 241 "bfin-lex.l"
-_REG.regno = REG_A0w; return REG;
-	YY_BREAK
-case 178:
-YY_RULE_SETUP
-#line 242 "bfin-lex.l"
-_REG.regno = REG_A0;  return REG_A_DOUBLE_ZERO;
-	YY_BREAK
-case 179:
-YY_RULE_SETUP
-#line 243 "bfin-lex.l"
-return GOT;
-	YY_BREAK
-case 180:
-YY_RULE_SETUP
-#line 244 "bfin-lex.l"
-return GOT17M4;
-	YY_BREAK
-case 181:
-YY_RULE_SETUP
-#line 245 "bfin-lex.l"
-return FUNCDESC_GOT17M4;
-	YY_BREAK
-case 182:
-YY_RULE_SETUP
-#line 246 "bfin-lex.l"
-return PLTPC;
-	YY_BREAK
-case 183:
-YY_RULE_SETUP
-#line 249 "bfin-lex.l"
-return TILDA;
-	YY_BREAK
-case 184:
-YY_RULE_SETUP
-#line 250 "bfin-lex.l"
-return _BAR_ASSIGN;
-	YY_BREAK
-case 185:
-YY_RULE_SETUP
-#line 251 "bfin-lex.l"
-return BAR;
-	YY_BREAK
-case 186:
-YY_RULE_SETUP
-#line 252 "bfin-lex.l"
-return _CARET_ASSIGN;
-	YY_BREAK
-case 187:
-YY_RULE_SETUP
-#line 253 "bfin-lex.l"
-return CARET;
-	YY_BREAK
-case 188:
-YY_RULE_SETUP
-#line 254 "bfin-lex.l"
-return RBRACK;
-	YY_BREAK
-case 189:
-YY_RULE_SETUP
-#line 255 "bfin-lex.l"
-return LBRACK;
-	YY_BREAK
-case 190:
-YY_RULE_SETUP
-#line 256 "bfin-lex.l"
-return _GREATER_GREATER_GREATER_THAN_ASSIGN;
-	YY_BREAK
-case 191:
-YY_RULE_SETUP
-#line 257 "bfin-lex.l"
-return _GREATER_GREATER_ASSIGN;
-	YY_BREAK
-case 192:
-YY_RULE_SETUP
-#line 258 "bfin-lex.l"
-return _GREATER_GREATER_GREATER;
-	YY_BREAK
-case 193:
-YY_RULE_SETUP
-#line 259 "bfin-lex.l"
-return GREATER_GREATER;
-	YY_BREAK
-case 194:
-YY_RULE_SETUP
-#line 260 "bfin-lex.l"
-return _ASSIGN_ASSIGN;
-	YY_BREAK
-case 195:
-YY_RULE_SETUP
-#line 261 "bfin-lex.l"
-return ASSIGN;
-	YY_BREAK
-case 196:
-YY_RULE_SETUP
-#line 262 "bfin-lex.l"
-return _LESS_THAN_ASSIGN;
-	YY_BREAK
-case 197:
-YY_RULE_SETUP
-#line 263 "bfin-lex.l"
-return _LESS_LESS_ASSIGN;
-	YY_BREAK
-case 198:
-YY_RULE_SETUP
-#line 264 "bfin-lex.l"
-return LESS_LESS;
-	YY_BREAK
-case 199:
-YY_RULE_SETUP
-#line 265 "bfin-lex.l"
-return LESS_THAN;
-	YY_BREAK
-case 200:
-YY_RULE_SETUP
-#line 266 "bfin-lex.l"
-return LPAREN;
-	YY_BREAK
-case 201:
-YY_RULE_SETUP
-#line 267 "bfin-lex.l"
-return RPAREN;
-	YY_BREAK
-case 202:
-YY_RULE_SETUP
-#line 268 "bfin-lex.l"
-return COLON;
-	YY_BREAK
-case 203:
-YY_RULE_SETUP
-#line 269 "bfin-lex.l"
-return SLASH;
-	YY_BREAK
-case 204:
-YY_RULE_SETUP
-#line 270 "bfin-lex.l"
-return _MINUS_ASSIGN;
-	YY_BREAK
-case 205:
-YY_RULE_SETUP
-#line 271 "bfin-lex.l"
-return _PLUS_BAR_PLUS;
-	YY_BREAK
-case 206:
-YY_RULE_SETUP
-#line 272 "bfin-lex.l"
-return _MINUS_BAR_PLUS;
-	YY_BREAK
-case 207:
-YY_RULE_SETUP
-#line 273 "bfin-lex.l"
-return _PLUS_BAR_MINUS;
-	YY_BREAK
-case 208:
-YY_RULE_SETUP
-#line 274 "bfin-lex.l"
-return _MINUS_BAR_MINUS;
-	YY_BREAK
-case 209:
-YY_RULE_SETUP
-#line 275 "bfin-lex.l"
-return _MINUS_MINUS;
-	YY_BREAK
-case 210:
-YY_RULE_SETUP
-#line 276 "bfin-lex.l"
-return MINUS;
-	YY_BREAK
-case 211:
-YY_RULE_SETUP
-#line 277 "bfin-lex.l"
-return COMMA;
-	YY_BREAK
-case 212:
-YY_RULE_SETUP
-#line 278 "bfin-lex.l"
-return _PLUS_ASSIGN;
-	YY_BREAK
-case 213:
-YY_RULE_SETUP
-#line 279 "bfin-lex.l"
-return _PLUS_PLUS;
-	YY_BREAK
-case 214:
-YY_RULE_SETUP
-#line 280 "bfin-lex.l"
-return PLUS;
-	YY_BREAK
-case 215:
-YY_RULE_SETUP
-#line 281 "bfin-lex.l"
-return _STAR_ASSIGN;
-	YY_BREAK
-case 216:
-YY_RULE_SETUP
-#line 282 "bfin-lex.l"
-return STAR;
-	YY_BREAK
-case 217:
-YY_RULE_SETUP
-#line 283 "bfin-lex.l"
-return _AMPERSAND_ASSIGN;
-	YY_BREAK
-case 218:
-YY_RULE_SETUP
-#line 284 "bfin-lex.l"
-return AMPERSAND;
-	YY_BREAK
-case 219:
-YY_RULE_SETUP
-#line 285 "bfin-lex.l"
-return PERCENT;
-	YY_BREAK
-case 220:
-YY_RULE_SETUP
-#line 286 "bfin-lex.l"
-return BANG;
-	YY_BREAK
-case 221:
-YY_RULE_SETUP
-#line 287 "bfin-lex.l"
-return SEMICOLON;
-	YY_BREAK
-case 222:
-YY_RULE_SETUP
-#line 288 "bfin-lex.l"
-return _ASSIGN_BANG;
-	YY_BREAK
-case 223:
-YY_RULE_SETUP
-#line 289 "bfin-lex.l"
-return DOUBLE_BAR;
-	YY_BREAK
-case 224:
-YY_RULE_SETUP
-#line 290 "bfin-lex.l"
-return AT;
-	YY_BREAK
-case 225:
-YY_RULE_SETUP
-#line 291 "bfin-lex.l"
-return PREFETCH;
-	YY_BREAK
-case 226:
-YY_RULE_SETUP
-#line 292 "bfin-lex.l"
-return UNLINK;
-	YY_BREAK
-case 227:
-YY_RULE_SETUP
-#line 293 "bfin-lex.l"
-return LINK;
-	YY_BREAK
-case 228:
-YY_RULE_SETUP
-#line 294 "bfin-lex.l"
-return IDLE;
-	YY_BREAK
-case 229:
-YY_RULE_SETUP
-#line 295 "bfin-lex.l"
-return IFLUSH;
-	YY_BREAK
-case 230:
-YY_RULE_SETUP
-#line 296 "bfin-lex.l"
-return FLUSHINV;
-	YY_BREAK
-case 231:
-YY_RULE_SETUP
-#line 297 "bfin-lex.l"
-return FLUSH;
-	YY_BREAK
-case 232:
-YY_RULE_SETUP
-#line 298 "bfin-lex.l"
-{
-    yylval.value = parse_int (&yytext);
-    return NUMBER;
-  }
-	YY_BREAK
-case 233:
-YY_RULE_SETUP
-#line 302 "bfin-lex.l"
-{ 
-    yylval.symbol = symbol_find_or_make (yytext);
-    symbol_mark_used (yylval.symbol);
-    return SYMBOL; 
-  }
-	YY_BREAK
-case 234:
-YY_RULE_SETUP
-#line 307 "bfin-lex.l"
-{
-    char *name;
-    char *ref = strdup (yytext);
-    if (ref[1] == 'b' || ref[1] == 'B')
-      {
-        name = fb_label_name ((int) (ref[0] - '0'), 0);
-	yylval.symbol = symbol_find (name);
-
-	if ((yylval.symbol != NULL)
-             && (S_IS_DEFINED (yylval.symbol)))
-          return SYMBOL;
-	as_bad ("backward reference to unknown label %d:", 
-						  (int) (ref[0] - '0')); 
-      }
-    else if (ref[1] == 'f' || ref[1] == 'F')
-      {
-        /* Forward reference.  Expect symbol to be undefined or
-           unknown.  undefined: seen it before.  unknown: never seen
-           it before.
-
-           Construct a local label name, then an undefined symbol.
-           Just return it as never seen before.  */
-
-        name = fb_label_name ((int) (ref[0] - '0'), 1);
-	yylval.symbol = symbol_find_or_make (name);
-	/* We have no need to check symbol properties.  */
-	return SYMBOL;
-      }                                  
-  }                                  
-	YY_BREAK
-case 235:
-YY_RULE_SETUP
-#line 336 "bfin-lex.l"
-;
-	YY_BREAK
-case 236:
-YY_RULE_SETUP
-#line 337 "bfin-lex.l"
-;
-	YY_BREAK
-case 237:
-YY_RULE_SETUP
-#line 338 "bfin-lex.l"
-return yytext[0];
-	YY_BREAK
-case 238:
-YY_RULE_SETUP
-#line 339 "bfin-lex.l"
-ECHO;
-	YY_BREAK
-#line 2260 "bfin-lex.c"
-case YY_STATE_EOF(INITIAL):
-case YY_STATE_EOF(KEYWORD):
-	yyterminate();
-
-	case YY_END_OF_BUFFER:
-		{
-		/* Amount of text matched not including the EOB char. */
-		int yy_amount_of_matched_text = (int) (yy_cp - yytext_ptr) - 1;
-
-		/* Undo the effects of YY_DO_BEFORE_ACTION. */
-		*yy_cp = yy_hold_char;
-		YY_RESTORE_YY_MORE_OFFSET
-
-		if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_NEW )
-			{
-			/* We're scanning a new file or input source.  It's
-			 * possible that this happened because the user
-			 * just pointed yyin at a new source and called
-			 * yylex().  If so, then we have to assure
-			 * consistency between yy_current_buffer and our
-			 * globals.  Here is the right place to do so, because
-			 * this is the first action (other than possibly a
-			 * back-up) that will match for the new input source.
-			 */
-			yy_n_chars = yy_current_buffer->yy_n_chars;
-			yy_current_buffer->yy_input_file = yyin;
-			yy_current_buffer->yy_buffer_status = YY_BUFFER_NORMAL;
-			}
-
-		/* Note that here we test for yy_c_buf_p "<=" to the position
-		 * of the first EOB in the buffer, since yy_c_buf_p will
-		 * already have been incremented past the NUL character
-		 * (since all states make transitions on EOB to the
-		 * end-of-buffer state).  Contrast this with the test
-		 * in input().
-		 */
-		if ( yy_c_buf_p <= &yy_current_buffer->yy_ch_buf[yy_n_chars] )
-			{ /* This was really a NUL. */
-			yy_state_type yy_next_state;
-
-			yy_c_buf_p = yytext_ptr + yy_amount_of_matched_text;
-
-			yy_current_state = yy_get_previous_state();
-
-			/* Okay, we're now positioned to make the NUL
-			 * transition.  We couldn't have
-			 * yy_get_previous_state() go ahead and do it
-			 * for us because it doesn't know how to deal
-			 * with the possibility of jamming (and we don't
-			 * want to build jamming into it because then it
-			 * will run more slowly).
-			 */
-
-			yy_next_state = yy_try_NUL_trans( yy_current_state );
-
-			yy_bp = yytext_ptr + YY_MORE_ADJ;
-
-			if ( yy_next_state )
-				{
-				/* Consume the NUL. */
-				yy_cp = ++yy_c_buf_p;
-				yy_current_state = yy_next_state;
-				goto yy_match;
-				}
-
-			else
-				{
-				yy_cp = yy_c_buf_p;
-				goto yy_find_action;
-				}
-			}
-
-		else switch ( yy_get_next_buffer() )
-			{
-			case EOB_ACT_END_OF_FILE:
-				{
-				yy_did_buffer_switch_on_eof = 0;
-
-				if ( yywrap() )
-					{
-					/* Note: because we've taken care in
-					 * yy_get_next_buffer() to have set up
-					 * yytext, we can now set up
-					 * yy_c_buf_p so that if some total
-					 * hoser (like flex itself) wants to
-					 * call the scanner after we return the
-					 * YY_NULL, it'll still work - another
-					 * YY_NULL will get returned.
-					 */
-					yy_c_buf_p = yytext_ptr + YY_MORE_ADJ;
-
-					yy_act = YY_STATE_EOF(YY_START);
-					goto do_action;
-					}
-
-				else
-					{
-					if ( ! yy_did_buffer_switch_on_eof )
-						YY_NEW_FILE;
-					}
-				break;
-				}
-
-			case EOB_ACT_CONTINUE_SCAN:
-				yy_c_buf_p =
-					yytext_ptr + yy_amount_of_matched_text;
-
-				yy_current_state = yy_get_previous_state();
-
-				yy_cp = yy_c_buf_p;
-				yy_bp = yytext_ptr + YY_MORE_ADJ;
-				goto yy_match;
-
-			case EOB_ACT_LAST_MATCH:
-				yy_c_buf_p =
-				&yy_current_buffer->yy_ch_buf[yy_n_chars];
-
-				yy_current_state = yy_get_previous_state();
-
-				yy_cp = yy_c_buf_p;
-				yy_bp = yytext_ptr + YY_MORE_ADJ;
-				goto yy_find_action;
-			}
-		break;
-		}
-
-	default:
-		YY_FATAL_ERROR(
-			"fatal flex scanner internal error--no action found" );
-	} /* end of action switch */
-		} /* end of scanning one token */
-	} /* end of yylex */
-
-
-/* yy_get_next_buffer - try to read in a new buffer
- *
- * Returns a code representing an action:
- *	EOB_ACT_LAST_MATCH -
- *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
- *	EOB_ACT_END_OF_FILE - end of file
- */
-
-static int yy_get_next_buffer()
-	{
-	register char *dest = yy_current_buffer->yy_ch_buf;
-	register char *source = yytext_ptr;
-	register int number_to_move, i;
-	int ret_val;
-
-	if ( yy_c_buf_p > &yy_current_buffer->yy_ch_buf[yy_n_chars + 1] )
-		YY_FATAL_ERROR(
-		"fatal flex scanner internal error--end of buffer missed" );
-
-	if ( yy_current_buffer->yy_fill_buffer == 0 )
-		{ /* Don't try to fill the buffer, so this is an EOF. */
-		if ( yy_c_buf_p - yytext_ptr - YY_MORE_ADJ == 1 )
-			{
-			/* We matched a single character, the EOB, so
-			 * treat this as a final EOF.
-			 */
-			return EOB_ACT_END_OF_FILE;
-			}
-
-		else
-			{
-			/* We matched some text prior to the EOB, first
-			 * process it.
-			 */
-			return EOB_ACT_LAST_MATCH;
-			}
-		}
-
-	/* Try to read more data. */
-
-	/* First move last chars to start of buffer. */
-	number_to_move = (int) (yy_c_buf_p - yytext_ptr) - 1;
-
-	for ( i = 0; i < number_to_move; ++i )
-		*(dest++) = *(source++);
-
-	if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_EOF_PENDING )
-		/* don't do the read, it's not guaranteed to return an EOF,
-		 * just force an EOF
-		 */
-		yy_current_buffer->yy_n_chars = yy_n_chars = 0;
-
-	else
-		{
-		int num_to_read =
-			yy_current_buffer->yy_buf_size - number_to_move - 1;
-
-		while ( num_to_read <= 0 )
-			{ /* Not enough room in the buffer - grow it. */
-#ifdef YY_USES_REJECT
-			YY_FATAL_ERROR(
-"input buffer overflow, can't enlarge buffer because scanner uses REJECT" );
-#else
-
-			/* just a shorter name for the current buffer */
-			YY_BUFFER_STATE b = yy_current_buffer;
-
-			int yy_c_buf_p_offset =
-				(int) (yy_c_buf_p - b->yy_ch_buf);
-
-			if ( b->yy_is_our_buffer )
-				{
-				int new_size = b->yy_buf_size * 2;
-
-				if ( new_size <= 0 )
-					b->yy_buf_size += b->yy_buf_size / 8;
-				else
-					b->yy_buf_size *= 2;
-
-				b->yy_ch_buf = (char *)
-					/* Include room in for 2 EOB chars. */
-					yy_flex_realloc( (void *) b->yy_ch_buf,
-							 b->yy_buf_size + 2 );
-				}
-			else
-				/* Can't grow it, we don't own it. */
-				b->yy_ch_buf = 0;
-
-			if ( ! b->yy_ch_buf )
-				YY_FATAL_ERROR(
-				"fatal error - scanner input buffer overflow" );
-
-			yy_c_buf_p = &b->yy_ch_buf[yy_c_buf_p_offset];
-
-			num_to_read = yy_current_buffer->yy_buf_size -
-						number_to_move - 1;
-#endif
-			}
-
-		if ( num_to_read > YY_READ_BUF_SIZE )
-			num_to_read = YY_READ_BUF_SIZE;
-
-		/* Read in more data. */
-		YY_INPUT( (&yy_current_buffer->yy_ch_buf[number_to_move]),
-			yy_n_chars, num_to_read );
-
-		yy_current_buffer->yy_n_chars = yy_n_chars;
-		}
-
-	if ( yy_n_chars == 0 )
-		{
-		if ( number_to_move == YY_MORE_ADJ )
-			{
-			ret_val = EOB_ACT_END_OF_FILE;
-			yyrestart( yyin );
-			}
-
-		else
-			{
-			ret_val = EOB_ACT_LAST_MATCH;
-			yy_current_buffer->yy_buffer_status =
-				YY_BUFFER_EOF_PENDING;
-			}
-		}
-
-	else
-		ret_val = EOB_ACT_CONTINUE_SCAN;
-
-	yy_n_chars += number_to_move;
-	yy_current_buffer->yy_ch_buf[yy_n_chars] = YY_END_OF_BUFFER_CHAR;
-	yy_current_buffer->yy_ch_buf[yy_n_chars + 1] = YY_END_OF_BUFFER_CHAR;
-
-	yytext_ptr = &yy_current_buffer->yy_ch_buf[0];
-
-	return ret_val;
-	}
-
-
-/* yy_get_previous_state - get the state just before the EOB char was reached */
-
-static yy_state_type yy_get_previous_state()
-	{
-	register yy_state_type yy_current_state;
-	register char *yy_cp;
-
-	yy_current_state = yy_start;
-
-	for ( yy_cp = yytext_ptr + YY_MORE_ADJ; yy_cp < yy_c_buf_p; ++yy_cp )
-		{
-		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
-		if ( yy_accept[yy_current_state] )
-			{
-			yy_last_accepting_state = yy_current_state;
-			yy_last_accepting_cpos = yy_cp;
-			}
-		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-			{
-			yy_current_state = (int) yy_def[yy_current_state];
-			if ( yy_current_state >= 559 )
-				yy_c = yy_meta[(unsigned int) yy_c];
-			}
-		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-		}
-
-	return yy_current_state;
-	}
-
-
-/* yy_try_NUL_trans - try to make a transition on the NUL character
- *
- * synopsis
- *	next_state = yy_try_NUL_trans( current_state );
- */
-
-#ifdef YY_USE_PROTOS
-static yy_state_type yy_try_NUL_trans( yy_state_type yy_current_state )
-#else
-static yy_state_type yy_try_NUL_trans( yy_current_state )
-yy_state_type yy_current_state;
-#endif
-	{
-	register int yy_is_jam;
-	register char *yy_cp = yy_c_buf_p;
-
-	register YY_CHAR yy_c = 1;
-	if ( yy_accept[yy_current_state] )
-		{
-		yy_last_accepting_state = yy_current_state;
-		yy_last_accepting_cpos = yy_cp;
-		}
-	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-		{
-		yy_current_state = (int) yy_def[yy_current_state];
-		if ( yy_current_state >= 559 )
-			yy_c = yy_meta[(unsigned int) yy_c];
-		}
-	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-	yy_is_jam = (yy_current_state == 558);
-
-	return yy_is_jam ? 0 : yy_current_state;
-	}
-
-
-#ifndef YY_NO_UNPUT
-#ifdef YY_USE_PROTOS
-static void yyunput( int c, register char *yy_bp )
-#else
-static void yyunput( c, yy_bp )
-int c;
-register char *yy_bp;
-#endif
-	{
-	register char *yy_cp = yy_c_buf_p;
-
-	/* undo effects of setting up yytext */
-	*yy_cp = yy_hold_char;
-
-	if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
-		{ /* need to shift things up to make room */
-		/* +2 for EOB chars. */
-		register int number_to_move = yy_n_chars + 2;
-		register char *dest = &yy_current_buffer->yy_ch_buf[
-					yy_current_buffer->yy_buf_size + 2];
-		register char *source =
-				&yy_current_buffer->yy_ch_buf[number_to_move];
-
-		while ( source > yy_current_buffer->yy_ch_buf )
-			*--dest = *--source;
-
-		yy_cp += (int) (dest - source);
-		yy_bp += (int) (dest - source);
-		yy_current_buffer->yy_n_chars =
-			yy_n_chars = yy_current_buffer->yy_buf_size;
-
-		if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
-			YY_FATAL_ERROR( "flex scanner push-back overflow" );
-		}
-
-	*--yy_cp = (char) c;
-
-
-	yytext_ptr = yy_bp;
-	yy_hold_char = *yy_cp;
-	yy_c_buf_p = yy_cp;
-	}
-#endif	/* ifndef YY_NO_UNPUT */
-
-
-#ifdef __cplusplus
-static int yyinput()
-#else
-static int input()
-#endif
-	{
-	int c;
-
-	*yy_c_buf_p = yy_hold_char;
-
-	if ( *yy_c_buf_p == YY_END_OF_BUFFER_CHAR )
-		{
-		/* yy_c_buf_p now points to the character we want to return.
-		 * If this occurs *before* the EOB characters, then it's a
-		 * valid NUL; if not, then we've hit the end of the buffer.
-		 */
-		if ( yy_c_buf_p < &yy_current_buffer->yy_ch_buf[yy_n_chars] )
-			/* This was really a NUL. */
-			*yy_c_buf_p = '\0';
-
-		else
-			{ /* need more input */
-			int offset = yy_c_buf_p - yytext_ptr;
-			++yy_c_buf_p;
-
-			switch ( yy_get_next_buffer() )
-				{
-				case EOB_ACT_LAST_MATCH:
-					/* This happens because yy_g_n_b()
-					 * sees that we've accumulated a
-					 * token and flags that we need to
-					 * try matching the token before
-					 * proceeding.  But for input(),
-					 * there's no matching to consider.
-					 * So convert the EOB_ACT_LAST_MATCH
-					 * to EOB_ACT_END_OF_FILE.
-					 */
-
-					/* Reset buffer status. */
-					yyrestart( yyin );
-
-					/* fall through */
-
-				case EOB_ACT_END_OF_FILE:
-					{
-					if ( yywrap() )
-						return EOF;
-
-					if ( ! yy_did_buffer_switch_on_eof )
-						YY_NEW_FILE;
-#ifdef __cplusplus
-					return yyinput();
-#else
-					return input();
-#endif
-					}
-
-				case EOB_ACT_CONTINUE_SCAN:
-					yy_c_buf_p = yytext_ptr + offset;
-					break;
-				}
-			}
-		}
-
-	c = *(unsigned char *) yy_c_buf_p;	/* cast for 8-bit char's */
-	*yy_c_buf_p = '\0';	/* preserve yytext */
-	yy_hold_char = *++yy_c_buf_p;
-
-
-	return c;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yyrestart( FILE *input_file )
-#else
-void yyrestart( input_file )
-FILE *input_file;
-#endif
-	{
-	if ( ! yy_current_buffer )
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE );
-
-	yy_init_buffer( yy_current_buffer, input_file );
-	yy_load_buffer_state();
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_switch_to_buffer( YY_BUFFER_STATE new_buffer )
-#else
-void yy_switch_to_buffer( new_buffer )
-YY_BUFFER_STATE new_buffer;
-#endif
-	{
-	if ( yy_current_buffer == new_buffer )
-		return;
-
-	if ( yy_current_buffer )
-		{
-		/* Flush out information for old buffer. */
-		*yy_c_buf_p = yy_hold_char;
-		yy_current_buffer->yy_buf_pos = yy_c_buf_p;
-		yy_current_buffer->yy_n_chars = yy_n_chars;
-		}
-
-	yy_current_buffer = new_buffer;
-	yy_load_buffer_state();
-
-	/* We don't actually know whether we did this switch during
-	 * EOF (yywrap()) processing, but the only time this flag
-	 * is looked at is after yywrap() is called, so it's safe
-	 * to go ahead and always set it.
-	 */
-	yy_did_buffer_switch_on_eof = 1;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_load_buffer_state( void )
-#else
-void yy_load_buffer_state()
-#endif
-	{
-	yy_n_chars = yy_current_buffer->yy_n_chars;
-	yytext_ptr = yy_c_buf_p = yy_current_buffer->yy_buf_pos;
-	yyin = yy_current_buffer->yy_input_file;
-	yy_hold_char = *yy_c_buf_p;
-	}
-
-
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_create_buffer( FILE *file, int size )
-#else
-YY_BUFFER_STATE yy_create_buffer( file, size )
-FILE *file;
-int size;
-#endif
-	{
-	YY_BUFFER_STATE b;
-
-	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_buf_size = size;
-
-	/* yy_ch_buf has to be 2 characters longer than the size given because
-	 * we need to put in 2 end-of-buffer characters.
-	 */
-	b->yy_ch_buf = (char *) yy_flex_alloc( b->yy_buf_size + 2 );
-	if ( ! b->yy_ch_buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_is_our_buffer = 1;
-
-	yy_init_buffer( b, file );
-
-	return b;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_delete_buffer( YY_BUFFER_STATE b )
-#else
-void yy_delete_buffer( b )
-YY_BUFFER_STATE b;
-#endif
-	{
-	if ( ! b )
-		return;
-
-	if ( b == yy_current_buffer )
-		yy_current_buffer = (YY_BUFFER_STATE) 0;
-
-	if ( b->yy_is_our_buffer )
-		yy_flex_free( (void *) b->yy_ch_buf );
-
-	yy_flex_free( (void *) b );
-	}
-
-
-#ifndef _WIN32
-#include <unistd.h>
-#else
-#ifndef YY_ALWAYS_INTERACTIVE
-#ifndef YY_NEVER_INTERACTIVE
-extern int isatty YY_PROTO(( int ));
-#endif
-#endif
-#endif
-
-#ifdef YY_USE_PROTOS
-void yy_init_buffer( YY_BUFFER_STATE b, FILE *file )
-#else
-void yy_init_buffer( b, file )
-YY_BUFFER_STATE b;
-FILE *file;
-#endif
-
-
-	{
-	yy_flush_buffer( b );
-
-	b->yy_input_file = file;
-	b->yy_fill_buffer = 1;
-
-#if YY_ALWAYS_INTERACTIVE
-	b->yy_is_interactive = 1;
-#else
-#if YY_NEVER_INTERACTIVE
-	b->yy_is_interactive = 0;
-#else
-	b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
-#endif
-#endif
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_flush_buffer( YY_BUFFER_STATE b )
-#else
-void yy_flush_buffer( b )
-YY_BUFFER_STATE b;
-#endif
-
-	{
-	if ( ! b )
-		return;
-
-	b->yy_n_chars = 0;
-
-	/* We always need two end-of-buffer characters.  The first causes
-	 * a transition to the end-of-buffer state.  The second causes
-	 * a jam in that state.
-	 */
-	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
-	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
-
-	b->yy_buf_pos = &b->yy_ch_buf[0];
-
-	b->yy_at_bol = 1;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	if ( b == yy_current_buffer )
-		yy_load_buffer_state();
-	}
-
-
-#ifndef YY_NO_SCAN_BUFFER
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_buffer( char *base, yy_size_t size )
-#else
-YY_BUFFER_STATE yy_scan_buffer( base, size )
-char *base;
-yy_size_t size;
-#endif
-	{
-	YY_BUFFER_STATE b;
-
-	if ( size < 2 ||
-	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
-	     base[size-1] != YY_END_OF_BUFFER_CHAR )
-		/* They forgot to leave room for the EOB's. */
-		return 0;
-
-	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
-
-	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
-	b->yy_buf_pos = b->yy_ch_buf = base;
-	b->yy_is_our_buffer = 0;
-	b->yy_input_file = 0;
-	b->yy_n_chars = b->yy_buf_size;
-	b->yy_is_interactive = 0;
-	b->yy_at_bol = 1;
-	b->yy_fill_buffer = 0;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	yy_switch_to_buffer( b );
-
-	return b;
-	}
-#endif
-
-
-#ifndef YY_NO_SCAN_STRING
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_string( yyconst char *yy_str )
-#else
-YY_BUFFER_STATE yy_scan_string( yy_str )
-yyconst char *yy_str;
-#endif
-	{
-	int len;
-	for ( len = 0; yy_str[len]; ++len )
-		;
-
-	return yy_scan_bytes( yy_str, len );
-	}
-#endif
-
-
-#ifndef YY_NO_SCAN_BYTES
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_bytes( yyconst char *bytes, int len )
-#else
-YY_BUFFER_STATE yy_scan_bytes( bytes, len )
-yyconst char *bytes;
-int len;
-#endif
-	{
-	YY_BUFFER_STATE b;
-	char *buf;
-	yy_size_t n;
-	int i;
-
-	/* Get memory for full buffer, including space for trailing EOB's. */
-	n = len + 2;
-	buf = (char *) yy_flex_alloc( n );
-	if ( ! buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
-
-	for ( i = 0; i < len; ++i )
-		buf[i] = bytes[i];
-
-	buf[len] = buf[len+1] = YY_END_OF_BUFFER_CHAR;
-
-	b = yy_scan_buffer( buf, n );
-	if ( ! b )
-		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
-
-	/* It's okay to grow etc. this buffer, and we should throw it
-	 * away when we're done.
-	 */
-	b->yy_is_our_buffer = 1;
-
-	return b;
-	}
-#endif
-
-
-#ifndef YY_NO_PUSH_STATE
-#ifdef YY_USE_PROTOS
-static void yy_push_state( int new_state )
-#else
-static void yy_push_state( new_state )
-int new_state;
-#endif
-	{
-	if ( yy_start_stack_ptr >= yy_start_stack_depth )
-		{
-		yy_size_t new_size;
-
-		yy_start_stack_depth += YY_START_STACK_INCR;
-		new_size = yy_start_stack_depth * sizeof( int );
-
-		if ( ! yy_start_stack )
-			yy_start_stack = (int *) yy_flex_alloc( new_size );
-
-		else
-			yy_start_stack = (int *) yy_flex_realloc(
-					(void *) yy_start_stack, new_size );
-
-		if ( ! yy_start_stack )
-			YY_FATAL_ERROR(
-			"out of memory expanding start-condition stack" );
-		}
-
-	yy_start_stack[yy_start_stack_ptr++] = YY_START;
-
-	BEGIN(new_state);
-	}
-#endif
-
-
-#ifndef YY_NO_POP_STATE
-static void yy_pop_state()
-	{
-	if ( --yy_start_stack_ptr < 0 )
-		YY_FATAL_ERROR( "start-condition stack underflow" );
-
-	BEGIN(yy_start_stack[yy_start_stack_ptr]);
-	}
-#endif
-
-
-#ifndef YY_NO_TOP_STATE
-static int yy_top_state()
-	{
-	return yy_start_stack[yy_start_stack_ptr - 1];
-	}
-#endif
-
-#ifndef YY_EXIT_FAILURE
-#define YY_EXIT_FAILURE 2
-#endif
-
-#ifdef YY_USE_PROTOS
-static void yy_fatal_error( yyconst char msg[] )
-#else
-static void yy_fatal_error( msg )
-char msg[];
-#endif
-	{
-	(void) fprintf( stderr, "%s\n", msg );
-	exit( YY_EXIT_FAILURE );
-	}
-
-
-
-/* Redefine yyless() so it works in section 3 code. */
-
-#undef yyless
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-		yytext[yyleng] = yy_hold_char; \
-		yy_c_buf_p = yytext + n; \
-		yy_hold_char = *yy_c_buf_p; \
-		*yy_c_buf_p = '\0'; \
-		yyleng = n; \
-		} \
-	while ( 0 )
-
-
-/* Internal utility routines. */
-
-#ifndef yytext_ptr
-#ifdef YY_USE_PROTOS
-static void yy_flex_strncpy( char *s1, yyconst char *s2, int n )
-#else
-static void yy_flex_strncpy( s1, s2, n )
-char *s1;
-yyconst char *s2;
-int n;
-#endif
-	{
-	register int i;
-	for ( i = 0; i < n; ++i )
-		s1[i] = s2[i];
-	}
-#endif
-
-#ifdef YY_NEED_STRLEN
-#ifdef YY_USE_PROTOS
-static int yy_flex_strlen( yyconst char *s )
-#else
-static int yy_flex_strlen( s )
-yyconst char *s;
-#endif
-	{
-	register int n;
-	for ( n = 0; s[n]; ++n )
-		;
-
-	return n;
-	}
-#endif
-
-
-#ifdef YY_USE_PROTOS
-static void *yy_flex_alloc( yy_size_t size )
-#else
-static void *yy_flex_alloc( size )
-yy_size_t size;
-#endif
-	{
-	return (void *) malloc( size );
-	}
-
-#ifdef YY_USE_PROTOS
-static void *yy_flex_realloc( void *ptr, yy_size_t size )
-#else
-static void *yy_flex_realloc( ptr, size )
-void *ptr;
-yy_size_t size;
-#endif
-	{
-	/* The cast to (char *) in the following accommodates both
-	 * implementations that use char* generic pointers, and those
-	 * that use void* generic pointers.  It works with the latter
-	 * because both ANSI C and C++ allow castless assignment from
-	 * any pointer type to void*, and deal with argument conversions
-	 * as though doing an assignment.
-	 */
-	return (void *) realloc( (char *) ptr, size );
-	}
-
-#ifdef YY_USE_PROTOS
-static void yy_flex_free( void *ptr )
-#else
-static void yy_flex_free( ptr )
-void *ptr;
-#endif
-	{
-	free( ptr );
-	}
-
-#if YY_MAIN
-int main()
-	{
-	yylex();
-	return 0;
-	}
-#endif
-#line 339 "bfin-lex.l"
-
-static long parse_int (char **end)
-{
-  char fmt = '\0';
-  int not_done = 1;
-  int shiftvalue = 0;
-  char * char_bag;
-  long value = 0;
-  char c;
-  char *arg = *end;
-
-  while (*arg && *arg == ' ')
-    arg++;
-
-  switch (*arg)
-    {
-      case '1':
-      case '2':
-      case '3':
-      case '4':
-      case '5':
-      case '6':
-      case '7':
-      case '8':
-      case '9':
-        fmt = 'd';
-        break;
-
-      case '0':  /* Accept different formated integers hex octal and binary. */
-        {
-	  c = *++arg;
-          arg++;
-	  if (c == 'x' || c == 'X') /* Hex input.  */
-	    fmt = 'h';
-	  else if (c == 'b' || c == 'B')
-	    fmt = 'b';
-	  else if (c == '.')
-	    fmt = 'f';
-	  else
-            {             /* Octal.  */
-	      arg--;
-	      fmt = 'o';
-	    }
-	  break;
-        }
-
-      case 'd':
-      case 'D':
-      case 'h':
-      case 'H':
-      case 'o':
-      case 'O':
-      case 'b':
-      case 'B':
-      case 'f':
-      case 'F':
-        {
-	  fmt = *arg++;
-	  if (*arg == '#')
-	    arg++;
-        }
-    }
-
-  switch (fmt)
-    {
-      case 'h':
-      case 'H':
-        shiftvalue = 4;
-        char_bag = "0123456789ABCDEFabcdef";
-        break;
-
-      case 'o':
-      case 'O':
-        shiftvalue = 3;
-        char_bag = "01234567";
-        break;
-
-      case 'b':
-      case 'B':
-        shiftvalue = 1;
-        char_bag = "01";
-        break;
-
-/* The assembler allows for fractional constants to be created
-   by either the 0.xxxx or the f#xxxx format 
-
-   i.e.   0.5 would result in 0x4000
-
-   note .5 would result in the identifier .5.
-
-   The assembler converts to fractional format 1.15 by the simple rule:
-
-             value = (short) (finput * (1 << 15)).  */
-
-      case 'f':
-      case 'F':
-        {
-          float fval = 0.0;
-          float pos = 10.0;
-          while (1)
-            {
-              int c;
-              c = *arg++;
-
-              if (c >= '0' && c <= '9')
-                {
-                  float digit = (c - '0') / pos;
-                  fval = fval + digit;
-                  pos = pos * 10.0;
-                }
-              else
-                {
-	          *--arg = c;
-                  value = (short) (fval * (1 << 15));
-                  break;
-                }
-            }
-          *end = arg+1;
-          return value;
-        }
-
-      case 'd':
-      case 'D':
-      default:
-        {
-          while (1)
-            {
-              int c;
-              c = *arg++;
-              if (c >= '0' && c <= '9')
-                value = (value * 10) + (c - '0');
-              else
-                {
-                  /* Constants that are suffixed with k|K are multiplied by 1024
-                     This suffix is only allowed on decimal constants. */
-                  if (c == 'k' || c == 'K')
-                    value *= 1024;
-                  else
-                    *--arg = c;
-                  break;
-                }
-            }
-          *end = arg+1;
-          return value;
-        }
-    }
-
-  while (not_done)
-    {
-      char c;
-      c = *arg++;
-      if (c == 0 || !index (char_bag, c))
-	{
-          not_done = 0;
-          *--arg = c;
-        }
-      else
-        {
-          if (c >= 'a' && c <= 'z')
-            c = c - ('a' - '9') + 1;
-          else if (c >= 'A' && c <= 'Z')
-            c = c - ('A' - '9') + 1;
-
-          c -= '0';
-          value = (value << shiftvalue) + c;
-        }
-    }
-  *end = arg+1;
-  return value;
-}
-
-
-static int parse_reg (Register *r, int cl, char *rt)
-{
-  r->regno = cl | (rt[1] - '0');
-  return REG;
-}
-
-static int parse_halfreg (Register *r, int cl, char *rt)
-{
-  r->regno = cl | (rt[1] - '0');
-
-  switch (rt[3])
-    {
-      case 'b':
-      case 'B':
-	return BYTE_DREG;
-
-      case 'l':
-      case 'L':
-	break;
-
-      case 'h':
-      case 'H':
-	r->regno |= F_REG_HIGH;
-	break;
-    }
-
-  return HALF_REG;
-}
-
-/* Our start state is KEYWORD as we have
-   command keywords such as PREFETCH.  */
-
-void 
-set_start_state (void)
-{
-  BEGIN KEYWORD;
-}
-
-
-#ifndef yywrap
-int
-yywrap ()
-{ 
-  return 1;
-}
-#endif
diff --git a/gas/bfin-parse.c b/gas/bfin-parse.c
deleted file mode 100644
index bc6728b659ba..000000000000
--- a/gas/bfin-parse.c
+++ /dev/null
@@ -1,7491 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.1.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Written by Richard Stallman by simplifying the original so called
-   ``semantic'' parser.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
-
-/* Identify Bison output.  */
-#define YYBISON 1
-
-/* Bison version.  */
-#define YYBISON_VERSION "2.1"
-
-/* Skeleton name.  */
-#define YYSKELETON_NAME "yacc.c"
-
-/* Pure parsers.  */
-#define YYPURE 0
-
-/* Using locations.  */
-#define YYLSP_NEEDED 0
-
-
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     BYTEOP16P = 258,
-     BYTEOP16M = 259,
-     BYTEOP1P = 260,
-     BYTEOP2P = 261,
-     BYTEOP2M = 262,
-     BYTEOP3P = 263,
-     BYTEUNPACK = 264,
-     BYTEPACK = 265,
-     PACK = 266,
-     SAA = 267,
-     ALIGN8 = 268,
-     ALIGN16 = 269,
-     ALIGN24 = 270,
-     VIT_MAX = 271,
-     EXTRACT = 272,
-     DEPOSIT = 273,
-     EXPADJ = 274,
-     SEARCH = 275,
-     ONES = 276,
-     SIGN = 277,
-     SIGNBITS = 278,
-     LINK = 279,
-     UNLINK = 280,
-     REG = 281,
-     PC = 282,
-     CCREG = 283,
-     BYTE_DREG = 284,
-     REG_A_DOUBLE_ZERO = 285,
-     REG_A_DOUBLE_ONE = 286,
-     A_ZERO_DOT_L = 287,
-     A_ZERO_DOT_H = 288,
-     A_ONE_DOT_L = 289,
-     A_ONE_DOT_H = 290,
-     HALF_REG = 291,
-     NOP = 292,
-     RTI = 293,
-     RTS = 294,
-     RTX = 295,
-     RTN = 296,
-     RTE = 297,
-     HLT = 298,
-     IDLE = 299,
-     STI = 300,
-     CLI = 301,
-     CSYNC = 302,
-     SSYNC = 303,
-     EMUEXCPT = 304,
-     RAISE = 305,
-     EXCPT = 306,
-     LSETUP = 307,
-     LOOP = 308,
-     LOOP_BEGIN = 309,
-     LOOP_END = 310,
-     DISALGNEXCPT = 311,
-     JUMP = 312,
-     JUMP_DOT_S = 313,
-     JUMP_DOT_L = 314,
-     CALL = 315,
-     ABORT = 316,
-     NOT = 317,
-     TILDA = 318,
-     BANG = 319,
-     AMPERSAND = 320,
-     BAR = 321,
-     PERCENT = 322,
-     CARET = 323,
-     BXOR = 324,
-     MINUS = 325,
-     PLUS = 326,
-     STAR = 327,
-     SLASH = 328,
-     NEG = 329,
-     MIN = 330,
-     MAX = 331,
-     ABS = 332,
-     DOUBLE_BAR = 333,
-     _PLUS_BAR_PLUS = 334,
-     _PLUS_BAR_MINUS = 335,
-     _MINUS_BAR_PLUS = 336,
-     _MINUS_BAR_MINUS = 337,
-     _MINUS_MINUS = 338,
-     _PLUS_PLUS = 339,
-     SHIFT = 340,
-     LSHIFT = 341,
-     ASHIFT = 342,
-     BXORSHIFT = 343,
-     _GREATER_GREATER_GREATER_THAN_ASSIGN = 344,
-     ROT = 345,
-     LESS_LESS = 346,
-     GREATER_GREATER = 347,
-     _GREATER_GREATER_GREATER = 348,
-     _LESS_LESS_ASSIGN = 349,
-     _GREATER_GREATER_ASSIGN = 350,
-     DIVS = 351,
-     DIVQ = 352,
-     ASSIGN = 353,
-     _STAR_ASSIGN = 354,
-     _BAR_ASSIGN = 355,
-     _CARET_ASSIGN = 356,
-     _AMPERSAND_ASSIGN = 357,
-     _MINUS_ASSIGN = 358,
-     _PLUS_ASSIGN = 359,
-     _ASSIGN_BANG = 360,
-     _LESS_THAN_ASSIGN = 361,
-     _ASSIGN_ASSIGN = 362,
-     GE = 363,
-     LT = 364,
-     LE = 365,
-     GT = 366,
-     LESS_THAN = 367,
-     FLUSHINV = 368,
-     FLUSH = 369,
-     IFLUSH = 370,
-     PREFETCH = 371,
-     PRNT = 372,
-     OUTC = 373,
-     WHATREG = 374,
-     TESTSET = 375,
-     ASL = 376,
-     ASR = 377,
-     B = 378,
-     W = 379,
-     NS = 380,
-     S = 381,
-     CO = 382,
-     SCO = 383,
-     TH = 384,
-     TL = 385,
-     BP = 386,
-     BREV = 387,
-     X = 388,
-     Z = 389,
-     M = 390,
-     MMOD = 391,
-     R = 392,
-     RND = 393,
-     RNDL = 394,
-     RNDH = 395,
-     RND12 = 396,
-     RND20 = 397,
-     V = 398,
-     LO = 399,
-     HI = 400,
-     BITTGL = 401,
-     BITCLR = 402,
-     BITSET = 403,
-     BITTST = 404,
-     BITMUX = 405,
-     DBGAL = 406,
-     DBGAH = 407,
-     DBGHALT = 408,
-     DBG = 409,
-     DBGA = 410,
-     DBGCMPLX = 411,
-     IF = 412,
-     COMMA = 413,
-     BY = 414,
-     COLON = 415,
-     SEMICOLON = 416,
-     RPAREN = 417,
-     LPAREN = 418,
-     LBRACK = 419,
-     RBRACK = 420,
-     STATUS_REG = 421,
-     MNOP = 422,
-     SYMBOL = 423,
-     NUMBER = 424,
-     GOT = 425,
-     GOT17M4 = 426,
-     FUNCDESC_GOT17M4 = 427,
-     AT = 428,
-     PLTPC = 429
-   };
-#endif
-/* Tokens.  */
-#define BYTEOP16P 258
-#define BYTEOP16M 259
-#define BYTEOP1P 260
-#define BYTEOP2P 261
-#define BYTEOP2M 262
-#define BYTEOP3P 263
-#define BYTEUNPACK 264
-#define BYTEPACK 265
-#define PACK 266
-#define SAA 267
-#define ALIGN8 268
-#define ALIGN16 269
-#define ALIGN24 270
-#define VIT_MAX 271
-#define EXTRACT 272
-#define DEPOSIT 273
-#define EXPADJ 274
-#define SEARCH 275
-#define ONES 276
-#define SIGN 277
-#define SIGNBITS 278
-#define LINK 279
-#define UNLINK 280
-#define REG 281
-#define PC 282
-#define CCREG 283
-#define BYTE_DREG 284
-#define REG_A_DOUBLE_ZERO 285
-#define REG_A_DOUBLE_ONE 286
-#define A_ZERO_DOT_L 287
-#define A_ZERO_DOT_H 288
-#define A_ONE_DOT_L 289
-#define A_ONE_DOT_H 290
-#define HALF_REG 291
-#define NOP 292
-#define RTI 293
-#define RTS 294
-#define RTX 295
-#define RTN 296
-#define RTE 297
-#define HLT 298
-#define IDLE 299
-#define STI 300
-#define CLI 301
-#define CSYNC 302
-#define SSYNC 303
-#define EMUEXCPT 304
-#define RAISE 305
-#define EXCPT 306
-#define LSETUP 307
-#define LOOP 308
-#define LOOP_BEGIN 309
-#define LOOP_END 310
-#define DISALGNEXCPT 311
-#define JUMP 312
-#define JUMP_DOT_S 313
-#define JUMP_DOT_L 314
-#define CALL 315
-#define ABORT 316
-#define NOT 317
-#define TILDA 318
-#define BANG 319
-#define AMPERSAND 320
-#define BAR 321
-#define PERCENT 322
-#define CARET 323
-#define BXOR 324
-#define MINUS 325
-#define PLUS 326
-#define STAR 327
-#define SLASH 328
-#define NEG 329
-#define MIN 330
-#define MAX 331
-#define ABS 332
-#define DOUBLE_BAR 333
-#define _PLUS_BAR_PLUS 334
-#define _PLUS_BAR_MINUS 335
-#define _MINUS_BAR_PLUS 336
-#define _MINUS_BAR_MINUS 337
-#define _MINUS_MINUS 338
-#define _PLUS_PLUS 339
-#define SHIFT 340
-#define LSHIFT 341
-#define ASHIFT 342
-#define BXORSHIFT 343
-#define _GREATER_GREATER_GREATER_THAN_ASSIGN 344
-#define ROT 345
-#define LESS_LESS 346
-#define GREATER_GREATER 347
-#define _GREATER_GREATER_GREATER 348
-#define _LESS_LESS_ASSIGN 349
-#define _GREATER_GREATER_ASSIGN 350
-#define DIVS 351
-#define DIVQ 352
-#define ASSIGN 353
-#define _STAR_ASSIGN 354
-#define _BAR_ASSIGN 355
-#define _CARET_ASSIGN 356
-#define _AMPERSAND_ASSIGN 357
-#define _MINUS_ASSIGN 358
-#define _PLUS_ASSIGN 359
-#define _ASSIGN_BANG 360
-#define _LESS_THAN_ASSIGN 361
-#define _ASSIGN_ASSIGN 362
-#define GE 363
-#define LT 364
-#define LE 365
-#define GT 366
-#define LESS_THAN 367
-#define FLUSHINV 368
-#define FLUSH 369
-#define IFLUSH 370
-#define PREFETCH 371
-#define PRNT 372
-#define OUTC 373
-#define WHATREG 374
-#define TESTSET 375
-#define ASL 376
-#define ASR 377
-#define B 378
-#define W 379
-#define NS 380
-#define S 381
-#define CO 382
-#define SCO 383
-#define TH 384
-#define TL 385
-#define BP 386
-#define BREV 387
-#define X 388
-#define Z 389
-#define M 390
-#define MMOD 391
-#define R 392
-#define RND 393
-#define RNDL 394
-#define RNDH 395
-#define RND12 396
-#define RND20 397
-#define V 398
-#define LO 399
-#define HI 400
-#define BITTGL 401
-#define BITCLR 402
-#define BITSET 403
-#define BITTST 404
-#define BITMUX 405
-#define DBGAL 406
-#define DBGAH 407
-#define DBGHALT 408
-#define DBG 409
-#define DBGA 410
-#define DBGCMPLX 411
-#define IF 412
-#define COMMA 413
-#define BY 414
-#define COLON 415
-#define SEMICOLON 416
-#define RPAREN 417
-#define LPAREN 418
-#define LBRACK 419
-#define RBRACK 420
-#define STATUS_REG 421
-#define MNOP 422
-#define SYMBOL 423
-#define NUMBER 424
-#define GOT 425
-#define GOT17M4 426
-#define FUNCDESC_GOT17M4 427
-#define AT 428
-#define PLTPC 429
-
-
-
-
-/* Copy the first part of user declarations.  */
-#line 21 "bfin-parse.y"
-
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <obstack.h>
-
-#include "bfin-aux.h"  // opcode generating auxiliaries
-#include "libbfd.h"
-#include "elf/common.h"
-#include "elf/bfin.h"
-
-#define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
-	bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
-
-#define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
-	bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
-	                   dst, src0, src1, w0)
-
-#define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
-	bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
-	                    dst, src0, src1, w0)
-
-#define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
-	bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
-
-#define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
-	bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
-
-#define LDIMMHALF_R(reg, h, s, z, hword) \
-	bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
-
-#define LDIMMHALF_R5(reg, h, s, z, hword) \
-        bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
-
-#define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
-	bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
-
-#define LDST(ptr, reg, aop, sz, z, w)  \
-	bfin_gen_ldst (ptr, reg, aop, sz, z, w)
-
-#define LDSTII(ptr, reg, offset, w, op)  \
-	bfin_gen_ldstii (ptr, reg, offset, w, op)
-
-#define DSPLDST(i, m, reg, aop, w) \
-	bfin_gen_dspldst (i, reg, aop, w, m)
-
-#define LDSTPMOD(ptr, reg, idx, aop, w) \
-	bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
-
-#define LDSTIIFP(offset, reg, w)  \
-	bfin_gen_ldstiifp (reg, offset, w)
-
-#define LOGI2OP(dst, src, opc) \
-	bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
-
-#define ALU2OP(dst, src, opc)  \
-	bfin_gen_alu2op (dst, src, opc)
-
-#define BRCC(t, b, offset) \
-	bfin_gen_brcc (t, b, offset)
-
-#define UJUMP(offset) \
-	bfin_gen_ujump (offset)
-
-#define PROGCTRL(prgfunc, poprnd) \
-	bfin_gen_progctrl (prgfunc, poprnd)
-
-#define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
-	bfin_gen_pushpopmultiple (dr, pr, d, p, w)
-
-#define PUSHPOPREG(reg, w) \
-	bfin_gen_pushpopreg (reg, w)
-
-#define CALLA(addr, s)  \
-	bfin_gen_calla (addr, s)
-
-#define LINKAGE(r, framesize) \
-	bfin_gen_linkage (r, framesize)
-
-#define COMPI2OPD(dst, src, op)  \
-	bfin_gen_compi2opd (dst, src, op)
-
-#define COMPI2OPP(dst, src, op)  \
-	bfin_gen_compi2opp (dst, src, op)
-
-#define DAGMODIK(i, op)  \
-	bfin_gen_dagmodik (i, op)
-
-#define DAGMODIM(i, m, op, br)  \
-	bfin_gen_dagmodim (i, m, op, br)
-
-#define COMP3OP(dst, src0, src1, opc)   \
-	bfin_gen_comp3op (src0, src1, dst, opc)
-
-#define PTR2OP(dst, src, opc)   \
-	bfin_gen_ptr2op (dst, src, opc)
-
-#define CCFLAG(x, y, opc, i, g)  \
-	bfin_gen_ccflag (x, y, opc, i, g)
-
-#define CCMV(src, dst, t) \
-	bfin_gen_ccmv (src, dst, t)
-
-#define CACTRL(reg, a, op) \
-	bfin_gen_cactrl (reg, a, op)
-
-#define LOOPSETUP(soffset, c, rop, eoffset, reg) \
-	bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
-
-#define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
-#define IS_RANGE(bits, expr, sign, mul)    \
-	value_match(expr, bits, sign, mul, 1)
-#define IS_URANGE(bits, expr, sign, mul)    \
-	value_match(expr, bits, sign, mul, 0)
-#define IS_CONST(expr) (expr->type == Expr_Node_Constant)
-#define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
-#define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
-#define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
-
-#define IS_PCREL4(expr) \
-	(value_match (expr, 4, 0, 2, 0))
-
-#define IS_LPPCREL10(expr) \
-	(value_match (expr, 10, 0, 2, 0))
-
-#define IS_PCREL10(expr) \
-	(value_match (expr, 10, 0, 2, 1))
-
-#define IS_PCREL12(expr) \
-	(value_match (expr, 12, 0, 2, 1))
-
-#define IS_PCREL24(expr) \
-	(value_match (expr, 24, 0, 2, 1))
-
-
-static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
-
-extern FILE *errorf;
-extern INSTR_T insn;
-
-static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
-static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
-
-static void notethat (char *format, ...);
-
-char *current_inputline;
-extern char *yytext;
-int yyerror (char *msg);
-
-void error (char *format, ...)
-{
-    va_list ap;
-    char buffer[2000];
-    
-    va_start (ap, format);
-    vsprintf (buffer, format, ap);
-    va_end (ap);
-
-    as_bad (buffer);
-}
-
-int
-yyerror (char *msg)
-{
-  if (msg[0] == '\0')
-    error ("%s", msg);
-
-  else if (yytext[0] != ';')
-    error ("%s. Input text was %s.", msg, yytext);
-  else
-    error ("%s.", msg);
-
-  return -1;
-}
-
-static int
-in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
-{
-  int val = EXPR_VALUE (expr);
-  if (expr->type != Expr_Node_Constant)
-    return 0;
-  if (val < from || val > to)
-    return 0;
-  return (val & mask) == 0;
-}
-
-extern int yylex (void);
-
-#define imm3(x) EXPR_VALUE (x)
-#define imm4(x) EXPR_VALUE (x)
-#define uimm4(x) EXPR_VALUE (x)
-#define imm5(x) EXPR_VALUE (x)
-#define uimm5(x) EXPR_VALUE (x)
-#define imm6(x) EXPR_VALUE (x)
-#define imm7(x) EXPR_VALUE (x)
-#define imm16(x) EXPR_VALUE (x)
-#define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
-#define uimm16(x) EXPR_VALUE (x)
-
-/* Return true if a value is inside a range.  */
-#define IN_RANGE(x, low, high) \
-  (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
-
-/* Auxiliary functions.  */
-
-static void
-neg_value (Expr_Node *expr)
-{
-  expr->value.i_value = -expr->value.i_value;
-}
-
-static int
-valid_dreg_pair (Register *reg1, Expr_Node *reg2)
-{
-  if (!IS_DREG (*reg1))
-    {
-      yyerror ("Dregs expected");
-      return 0;
-    }
-
-  if (reg1->regno != 1 && reg1->regno != 3)
-    {
-      yyerror ("Bad register pair");
-      return 0;
-    }
-
-  if (imm7 (reg2) != reg1->regno - 1)
-    {
-      yyerror ("Bad register pair");
-      return 0;
-    }
-
-  reg1->regno--;
-  return 1;
-}
-
-static int
-check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
-{
-  if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
-      || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
-    return yyerror ("Source multiplication register mismatch");
-
-  return 0;
-}
-
-
-/* Check (vector) mac funcs and ops.  */
-
-static int
-check_macfuncs (Macfunc *aa, Opt_mode *opa,
-		Macfunc *ab, Opt_mode *opb)
-{
-  /* Variables for swapping.  */
-  Macfunc mtmp;
-  Opt_mode otmp;
-
-  /* If a0macfunc comes before a1macfunc, swap them.  */
-	
-  if (aa->n == 0)
-    {
-      /*  (M) is not allowed here.  */
-      if (opa->MM != 0)
-	return yyerror ("(M) not allowed with A0MAC");
-      if (ab->n != 1)
-	return yyerror ("Vector AxMACs can't be same");
-
-      mtmp = *aa; *aa = *ab; *ab = mtmp;
-      otmp = *opa; *opa = *opb; *opb = otmp;
-    }
-  else
-    {
-      if (opb->MM != 0)
-	return yyerror ("(M) not allowed with A0MAC");
-      if (opa->mod != 0)
-	return yyerror ("Bad opt mode");
-      if (ab->n != 0)
-	return yyerror ("Vector AxMACs can't be same");
-    }
-
-  /*  If both ops are != 3, we have multiply_halfregs in both
-  assignment_or_macfuncs.  */
-  if (aa->op == ab->op && aa->op != 3)
-    {
-      if (check_multiply_halfregs (aa, ab) < 0)
-	return -1;
-    }
-  else
-    {
-      /*  Only one of the assign_macfuncs has a half reg multiply
-      Evil trick: Just 'OR' their source register codes:
-      We can do that, because we know they were initialized to 0
-      in the rules that don't use multiply_halfregs.  */
-      aa->s0.regno |= (ab->s0.regno & CODE_MASK);
-      aa->s1.regno |= (ab->s1.regno & CODE_MASK);
-    }
-
-  if (aa->w == ab->w  && aa->P != ab->P)
-    {
-      return yyerror ("macfuncs must differ");
-      if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
-	return yyerror ("Destination Dregs must differ by one");
-    }
-  /* We assign to full regs, thus obey even/odd rules.  */
-  else if ((aa->w && aa->P && IS_EVEN (aa->dst)) 
-	   || (ab->w && ab->P && !IS_EVEN (ab->dst)))
-    return yyerror ("Even/Odd register assignment mismatch");
-  /* We assign to half regs, thus obey hi/low rules.  */
-  else if ( (aa->w && !aa->P && !IS_H (aa->dst)) 
-	    || (ab->w && !aa->P && IS_H (ab->dst)))
-    return yyerror ("High/Low register assignment mismatch");
-
-  /* Make sure first macfunc has got both P flags ORed.  */
-  aa->P |= ab->P;
-
-  /* Make sure mod flags get ORed, too.  */
-  opb->mod |= opa->mod;
-  return 0;	
-}
-
-
-static int
-is_group1 (INSTR_T x)
-{
-  /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
-  if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
-    return 1;
-
-  return 0;
-}
-
-static int
-is_group2 (INSTR_T x)
-{
-  if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
-       && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
-       && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
-       && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
-      || (x->value == 0x0000))
-    return 1;
-  return 0;
-}
-
-
-
-/* Enabling traces.  */
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
-
-/* Enabling verbose error messages.  */
-#ifdef YYERROR_VERBOSE
-# undef YYERROR_VERBOSE
-# define YYERROR_VERBOSE 1
-#else
-# define YYERROR_VERBOSE 0
-#endif
-
-/* Enabling the token table.  */
-#ifndef YYTOKEN_TABLE
-# define YYTOKEN_TABLE 0
-#endif
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 366 "bfin-parse.y"
-typedef union YYSTYPE {
-  INSTR_T instr;
-  Expr_Node *expr;
-  SYMBOL_T symbol;
-  long value;
-  Register reg;
-  Macfunc macfunc;
-  struct { int r0; int s0; int x0; int aop; } modcodes;
-  struct { int r0; } r0;
-  Opt_mode mod;
-} YYSTYPE;
-/* Line 196 of yacc.c.  */
-#line 790 "bfin-parse.c"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-
-
-/* Copy the second part of user declarations.  */
-
-
-/* Line 219 of yacc.c.  */
-#line 802 "bfin-parse.c"
-
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
-#endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
-# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
-#endif
-
-#ifndef YY_
-# if YYENABLE_NLS
-#  if ENABLE_NLS
-#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
-#   define YY_(msgid) dgettext ("bison-runtime", msgid)
-#  endif
-# endif
-# ifndef YY_
-#  define YY_(msgid) msgid
-# endif
-#endif
-
-#if ! defined (yyoverflow) || YYERROR_VERBOSE
-
-/* The parser invokes alloca or malloc; define the necessary symbols.  */
-
-# ifdef YYSTACK_USE_ALLOCA
-#  if YYSTACK_USE_ALLOCA
-#   ifdef __GNUC__
-#    define YYSTACK_ALLOC __builtin_alloca
-#   else
-#    define YYSTACK_ALLOC alloca
-#    if defined (__STDC__) || defined (__cplusplus)
-#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     define YYINCLUDED_STDLIB_H
-#    endif
-#   endif
-#  endif
-# endif
-
-# ifdef YYSTACK_ALLOC
-   /* Pacify GCC's `empty if-body' warning. */
-#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-    /* The OS might guarantee only one guard page at the bottom of the stack,
-       and a page size can be as small as 4096 bytes.  So we cannot safely
-       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
-       to allow for a few compiler-allocated temporary stack slots.  */
-#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
-#  endif
-# else
-#  define YYSTACK_ALLOC YYMALLOC
-#  define YYSTACK_FREE YYFREE
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
-#  endif
-#  ifdef __cplusplus
-extern "C" {
-#  endif
-#  ifndef YYMALLOC
-#   define YYMALLOC malloc
-#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifndef YYFREE
-#   define YYFREE free
-#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void free (void *); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifdef __cplusplus
-}
-#  endif
-# endif
-#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
-
-
-#if (! defined (yyoverflow) \
-     && (! defined (__cplusplus) \
-	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
-
-/* A type that is properly aligned for any stack member.  */
-union yyalloc
-{
-  short int yyss;
-  YYSTYPE yyvs;
-  };
-
-/* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
-
-/* The size of an array large to enough to hold all stacks, each with
-   N elements.  */
-# define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
-      + YYSTACK_GAP_MAXIMUM)
-
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined (__GNUC__) && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)		\
-      do					\
-	{					\
-	  YYSIZE_T yyi;				\
-	  for (yyi = 0; yyi < (Count); yyi++)	\
-	    (To)[yyi] = (From)[yyi];		\
-	}					\
-      while (0)
-#  endif
-# endif
-
-/* Relocate STACK from its old location to the new one.  The
-   local variables YYSIZE and YYSTACKSIZE give the old and new number of
-   elements in the stack, and YYPTR gives the new location of the
-   stack.  Advance YYPTR to a properly aligned location for the next
-   stack.  */
-# define YYSTACK_RELOCATE(Stack)					\
-    do									\
-      {									\
-	YYSIZE_T yynewbytes;						\
-	YYCOPY (&yyptr->Stack, Stack, yysize);				\
-	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-	yyptr += yynewbytes / sizeof (*yyptr);				\
-      }									\
-    while (0)
-
-#endif
-
-#if defined (__STDC__) || defined (__cplusplus)
-   typedef signed char yysigned_char;
-#else
-   typedef short int yysigned_char;
-#endif
-
-/* YYFINAL -- State number of the termination state. */
-#define YYFINAL  149
-/* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   1315
-
-/* YYNTOKENS -- Number of terminals. */
-#define YYNTOKENS  175
-/* YYNNTS -- Number of nonterminals. */
-#define YYNNTS  47
-/* YYNRULES -- Number of rules. */
-#define YYNRULES  349
-/* YYNRULES -- Number of states. */
-#define YYNSTATES  1024
-
-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
-#define YYUNDEFTOK  2
-#define YYMAXUTOK   429
-
-#define YYTRANSLATE(YYX)						\
-  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
-static const unsigned char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
-       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
-      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
-      25,    26,    27,    28,    29,    30,    31,    32,    33,    34,
-      35,    36,    37,    38,    39,    40,    41,    42,    43,    44,
-      45,    46,    47,    48,    49,    50,    51,    52,    53,    54,
-      55,    56,    57,    58,    59,    60,    61,    62,    63,    64,
-      65,    66,    67,    68,    69,    70,    71,    72,    73,    74,
-      75,    76,    77,    78,    79,    80,    81,    82,    83,    84,
-      85,    86,    87,    88,    89,    90,    91,    92,    93,    94,
-      95,    96,    97,    98,    99,   100,   101,   102,   103,   104,
-     105,   106,   107,   108,   109,   110,   111,   112,   113,   114,
-     115,   116,   117,   118,   119,   120,   121,   122,   123,   124,
-     125,   126,   127,   128,   129,   130,   131,   132,   133,   134,
-     135,   136,   137,   138,   139,   140,   141,   142,   143,   144,
-     145,   146,   147,   148,   149,   150,   151,   152,   153,   154,
-     155,   156,   157,   158,   159,   160,   161,   162,   163,   164,
-     165,   166,   167,   168,   169,   170,   171,   172,   173,   174
-};
-
-#if YYDEBUG
-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-   YYRHS.  */
-static const unsigned short int yyprhs[] =
-{
-       0,     0,     3,     4,     6,     9,    16,    21,    23,    25,
-      28,    34,    36,    43,    50,    54,    58,    76,    94,   106,
-     118,   130,   143,   156,   169,   175,   179,   183,   187,   196,
-     210,   223,   237,   251,   265,   274,   292,   299,   309,   313,
-     320,   324,   330,   337,   346,   355,   358,   361,   366,   370,
-     373,   378,   382,   389,   394,   402,   410,   414,   418,   425,
-     429,   434,   438,   442,   446,   458,   470,   480,   486,   492,
-     502,   508,   514,   521,   528,   534,   540,   546,   553,   560,
-     566,   568,   572,   576,   580,   584,   589,   594,   604,   614,
-     620,   628,   633,   640,   646,   653,   661,   671,   680,   689,
-     701,   711,   716,   722,   729,   737,   744,   749,   756,   762,
-     769,   776,   781,   790,   801,   812,   825,   831,   838,   844,
-     851,   856,   861,   866,   874,   884,   894,   904,   911,   918,
-     925,   934,   943,   950,   956,   962,   971,   976,   984,   986,
-     988,   990,   992,   994,   996,   998,  1000,  1002,  1004,  1007,
-    1010,  1015,  1020,  1027,  1034,  1037,  1040,  1045,  1048,  1051,
-    1054,  1057,  1060,  1063,  1070,  1077,  1083,  1088,  1092,  1096,
-    1100,  1104,  1108,  1112,  1117,  1120,  1125,  1128,  1133,  1136,
-    1141,  1144,  1152,  1161,  1170,  1178,  1186,  1194,  1204,  1212,
-    1221,  1231,  1240,  1247,  1255,  1264,  1274,  1283,  1291,  1299,
-    1306,  1310,  1322,  1330,  1342,  1350,  1354,  1357,  1359,  1367,
-    1377,  1389,  1393,  1399,  1407,  1409,  1412,  1415,  1420,  1422,
-    1429,  1436,  1443,  1445,  1447,  1448,  1454,  1460,  1464,  1468,
-    1472,  1476,  1477,  1479,  1481,  1483,  1485,  1487,  1488,  1492,
-    1493,  1497,  1501,  1502,  1506,  1510,  1516,  1522,  1523,  1527,
-    1531,  1532,  1536,  1540,  1541,  1545,  1549,  1553,  1559,  1565,
-    1566,  1570,  1571,  1575,  1577,  1579,  1581,  1583,  1584,  1588,
-    1592,  1596,  1602,  1608,  1610,  1612,  1614,  1615,  1619,  1620,
-    1624,  1629,  1634,  1636,  1638,  1640,  1642,  1644,  1646,  1648,
-    1650,  1654,  1658,  1662,  1666,  1672,  1678,  1684,  1690,  1694,
-    1698,  1704,  1710,  1711,  1713,  1715,  1718,  1721,  1724,  1728,
-    1730,  1736,  1742,  1746,  1749,  1752,  1755,  1759,  1761,  1763,
-    1765,  1767,  1771,  1775,  1779,  1783,  1785,  1787,  1789,  1791,
-    1795,  1797,  1799,  1803,  1805,  1807,  1811,  1814,  1817,  1819,
-    1823,  1827,  1831,  1835,  1839,  1843,  1847,  1851,  1855,  1859
-};
-
-/* YYRHS -- A `-1'-separated list of the rules' RHS. */
-static const short int yyrhs[] =
-{
-     176,     0,    -1,    -1,   177,    -1,   178,   161,    -1,   178,
-      78,   178,    78,   178,   161,    -1,   178,    78,   178,   161,
-      -1,     1,    -1,   167,    -1,   209,   180,    -1,   209,   180,
-     158,   209,   180,    -1,    56,    -1,    26,    98,   163,   208,
-     179,   162,    -1,    36,    98,   163,   208,   179,   162,    -1,
-      33,    98,    36,    -1,    35,    98,    36,    -1,   163,    26,
-     158,    26,   162,    98,     3,   163,    26,   160,   220,   158,
-      26,   160,   220,   162,   193,    -1,   163,    26,   158,    26,
-     162,    98,     4,   163,    26,   160,   220,   158,    26,   160,
-     220,   162,   193,    -1,   163,    26,   158,    26,   162,    98,
-       9,    26,   160,   220,   193,    -1,   163,    26,   158,    26,
-     162,    98,    20,    26,   163,   192,   162,    -1,    26,    98,
-      34,    71,    35,   158,    26,    98,    32,    71,    33,    -1,
-      26,    98,   179,    71,   179,   158,    26,    98,   179,    70,
-     179,   185,    -1,    26,    98,    26,   202,    26,   158,    26,
-      98,    26,   202,    26,   185,    -1,    26,    98,    26,   201,
-      26,   158,    26,    98,    26,   201,    26,   186,    -1,    26,
-      98,    77,    26,   190,    -1,   206,    77,   179,    -1,    32,
-      98,    36,    -1,    34,    98,    36,    -1,    26,    98,   195,
-     163,    26,   158,    26,   162,    -1,    26,    98,     5,   163,
-      26,   160,   220,   158,    26,   160,   220,   162,   194,    -1,
-      26,    98,     5,   163,    26,   160,   220,   158,    26,   160,
-     220,   162,    -1,    26,    98,     6,   163,    26,   160,   220,
-     158,    26,   160,   220,   162,   203,    -1,    26,    98,     7,
-     163,    26,   160,   220,   158,    26,   160,   220,   162,   203,
-      -1,    26,    98,     8,   163,    26,   160,   220,   158,    26,
-     160,   220,   162,   204,    -1,    26,    98,    10,   163,    26,
-     158,    26,   162,    -1,    36,    98,    36,    98,    22,   163,
-      36,   162,    72,    36,    71,    22,   163,    36,   162,    72,
-      36,    -1,    26,    98,    26,   202,    26,   185,    -1,    26,
-      98,   200,   163,    26,   158,    26,   162,   190,    -1,   206,
-      70,   179,    -1,    36,    98,    36,   202,    36,   185,    -1,
-     206,   206,   220,    -1,   206,   179,   163,   126,   162,    -1,
-      36,    98,    26,   163,   138,   162,    -1,    36,    98,    26,
-     202,    26,   163,   141,   162,    -1,    36,    98,    26,   202,
-      26,   163,   142,   162,    -1,   206,   179,    -1,   206,    26,
-      -1,    26,    98,    36,   187,    -1,    36,    98,   220,    -1,
-     206,   220,    -1,    26,    98,   220,   188,    -1,    36,    98,
-      26,    -1,    26,    98,    26,   201,    26,   184,    -1,    26,
-      98,    29,   187,    -1,   206,    77,   179,   158,   206,    77,
-     179,    -1,   206,    70,   179,   158,   206,    70,   179,    -1,
-     207,   179,   196,    -1,    26,   103,   220,    -1,    26,   104,
-      26,   163,   132,   162,    -1,    26,   103,    26,    -1,   179,
-     104,   179,   196,    -1,    26,   104,    26,    -1,    26,   104,
-     220,    -1,    26,    99,    26,    -1,    12,   163,    26,   160,
-     220,   158,    26,   160,   220,   162,   193,    -1,   206,   179,
-     163,   126,   162,   158,   206,   179,   163,   126,   162,    -1,
-      26,    98,   163,    26,    71,    26,   162,    91,   220,    -1,
-      26,    98,    26,    66,    26,    -1,    26,    98,    26,    68,
-      26,    -1,    26,    98,    26,    71,   163,    26,    91,   220,
-     162,    -1,    28,    98,   179,   107,   179,    -1,    28,    98,
-     179,   112,   179,    -1,    28,    98,    26,   112,    26,   197,
-      -1,    28,    98,    26,   112,   220,   197,    -1,    28,    98,
-      26,   107,    26,    -1,    28,    98,    26,   107,   220,    -1,
-      28,    98,   179,   106,   179,    -1,    28,    98,    26,   106,
-      26,   197,    -1,    28,    98,    26,   106,   220,   197,    -1,
-      26,    98,    26,    65,    26,    -1,   213,    -1,    26,    98,
-      26,    -1,    28,    98,    26,    -1,    26,    98,    28,    -1,
-      28,   105,    28,    -1,    36,    98,   211,   180,    -1,    26,
-      98,   211,   180,    -1,    36,    98,   211,   180,   158,    36,
-      98,   211,   180,    -1,    26,    98,   211,   180,   158,    26,
-      98,   211,   180,    -1,   206,    87,   179,   159,    36,    -1,
-      36,    98,    87,    36,   159,    36,   191,    -1,   206,   179,
-      91,   220,    -1,    26,    98,    26,    91,   220,   189,    -1,
-      36,    98,    36,    91,   220,    -1,    36,    98,    36,    91,
-     220,   191,    -1,    26,    98,    87,    26,   159,    36,   189,
-      -1,    36,    98,    19,   163,    26,   158,    36,   162,   190,
-      -1,    36,    98,    19,   163,    36,   158,    36,   162,    -1,
-      26,    98,    18,   163,    26,   158,    26,   162,    -1,    26,
-      98,    18,   163,    26,   158,    26,   162,   163,   133,   162,
-      -1,    26,    98,    17,   163,    26,   158,    36,   162,   187,
-      -1,   206,   179,    93,   220,    -1,   206,    86,   179,   159,
-      36,    -1,    36,    98,    86,    36,   159,    36,    -1,    26,
-      98,    86,    26,   159,    36,   190,    -1,    26,    98,    85,
-      26,   159,    36,    -1,   206,   179,    92,   220,    -1,    26,
-      98,    26,    92,   220,   190,    -1,    36,    98,    36,    92,
-     220,    -1,    36,    98,    36,    93,   220,   191,    -1,    26,
-      98,    26,    93,   220,   189,    -1,    36,    98,    21,    26,
-      -1,    26,    98,    11,   163,    36,   158,    36,   162,    -1,
-      36,    98,    28,    98,    88,   163,   179,   158,    26,   162,
-      -1,    36,    98,    28,    98,    69,   163,   179,   158,    26,
-     162,    -1,    36,    98,    28,    98,    69,   163,   179,   158,
-     179,   158,    28,   162,    -1,   206,    90,   179,   159,    36,
-      -1,    26,    98,    90,    26,   159,    36,    -1,   206,    90,
-     179,   159,   220,    -1,    26,    98,    90,    26,   159,   220,
-      -1,    36,    98,    23,   179,    -1,    36,    98,    23,    26,
-      -1,    36,    98,    23,    36,    -1,    36,    98,    16,   163,
-      26,   162,   181,    -1,    26,    98,    16,   163,    26,   158,
-      26,   162,   181,    -1,   150,   163,    26,   158,    26,   158,
-     179,   162,   181,    -1,   206,    88,   163,   179,   158,   179,
-     158,    28,   162,    -1,   147,   163,    26,   158,   220,   162,
-      -1,   148,   163,    26,   158,   220,   162,    -1,   146,   163,
-      26,   158,   220,   162,    -1,    28,   105,   149,   163,    26,
-     158,   220,   162,    -1,    28,    98,   149,   163,    26,   158,
-     220,   162,    -1,   157,    64,    28,    26,    98,    26,    -1,
-     157,    28,    26,    98,    26,    -1,   157,    64,    28,    57,
-     220,    -1,   157,    64,    28,    57,   220,   163,   131,   162,
-      -1,   157,    28,    57,   220,    -1,   157,    28,    57,   220,
-     163,   131,   162,    -1,    37,    -1,    39,    -1,    38,    -1,
-      40,    -1,    41,    -1,    42,    -1,    44,    -1,    47,    -1,
-      48,    -1,    49,    -1,    46,    26,    -1,    45,    26,    -1,
-      57,   163,    26,   162,    -1,    60,   163,    26,   162,    -1,
-      60,   163,    27,    71,    26,   162,    -1,    57,   163,    27,
-      71,    26,   162,    -1,    50,   220,    -1,    51,   220,    -1,
-     120,   163,    26,   162,    -1,    57,   220,    -1,    58,   220,
-      -1,    59,   220,    -1,    59,   218,    -1,    60,   220,    -1,
-      60,   218,    -1,    97,   163,    26,   158,    26,   162,    -1,
-      96,   163,    26,   158,    26,   162,    -1,    26,    98,    70,
-      26,   189,    -1,    26,    98,    63,    26,    -1,    26,    95,
-      26,    -1,    26,    95,   220,    -1,    26,    89,    26,    -1,
-      26,    94,    26,    -1,    26,    94,   220,    -1,    26,    89,
-     220,    -1,   114,   164,    26,   165,    -1,   114,   199,    -1,
-     113,   164,    26,   165,    -1,   113,   199,    -1,   115,   164,
-      26,   165,    -1,   115,   199,    -1,   116,   164,    26,   165,
-      -1,   116,   199,    -1,   123,   164,    26,   205,   165,    98,
-      26,    -1,   123,   164,    26,   202,   220,   165,    98,    26,
-      -1,   124,   164,    26,   202,   220,   165,    98,    26,    -1,
-     124,   164,    26,   205,   165,    98,    26,    -1,   124,   164,
-      26,   205,   165,    98,    36,    -1,   164,    26,   202,   220,
-     165,    98,    26,    -1,    26,    98,   124,   164,    26,   202,
-     220,   165,   187,    -1,    36,    98,   124,   164,    26,   205,
-     165,    -1,    26,    98,   124,   164,    26,   205,   165,   187,
-      -1,    26,    98,   124,   164,    26,    84,    26,   165,   187,
-      -1,    36,    98,   124,   164,    26,    84,    26,   165,    -1,
-     164,    26,   205,   165,    98,    26,    -1,   164,    26,    84,
-      26,   165,    98,    26,    -1,   124,   164,    26,    84,    26,
-     165,    98,    36,    -1,    26,    98,   123,   164,    26,   202,
-     220,   165,   187,    -1,    26,    98,   123,   164,    26,   205,
-     165,   187,    -1,    26,    98,   164,    26,    84,    26,   165,
-      -1,    26,    98,   164,    26,   202,   217,   165,    -1,    26,
-      98,   164,    26,   205,   165,    -1,   220,    98,   220,    -1,
-     198,    98,   163,    26,   160,   220,   158,    26,   160,   220,
-     162,    -1,   198,    98,   163,    26,   160,   220,   162,    -1,
-     163,    26,   160,   220,   158,    26,   160,   220,   162,    98,
-     199,    -1,   163,    26,   160,   220,   162,    98,   199,    -1,
-     198,    98,    26,    -1,    24,   220,    -1,    25,    -1,    52,
-     163,   220,   158,   220,   162,    26,    -1,    52,   163,   220,
-     158,   220,   162,    26,    98,    26,    -1,    52,   163,   220,
-     158,   220,   162,    26,    98,    26,    92,   220,    -1,    53,
-     220,    26,    -1,    53,   220,    26,    98,    26,    -1,    53,
-     220,    26,    98,    26,    92,   220,    -1,   154,    -1,   154,
-     179,    -1,   154,    26,    -1,   156,   163,    26,   162,    -1,
-     153,    -1,   155,   163,    36,   158,   220,   162,    -1,   152,
-     163,    26,   158,   220,   162,    -1,   151,   163,    26,   158,
-     220,   162,    -1,    30,    -1,    31,    -1,    -1,   163,   135,
-     158,   136,   162,    -1,   163,   136,   158,   135,   162,    -1,
-     163,   136,   162,    -1,   163,   135,   162,    -1,   163,   121,
-     162,    -1,   163,   122,   162,    -1,    -1,   126,    -1,   127,
-      -1,   128,    -1,   121,    -1,   122,    -1,    -1,   163,   182,
-     162,    -1,    -1,   163,   125,   162,    -1,   163,   126,   162,
-      -1,    -1,   163,   183,   162,    -1,   163,   182,   162,    -1,
-     163,   183,   158,   182,   162,    -1,   163,   182,   158,   183,
-     162,    -1,    -1,   163,   134,   162,    -1,   163,   133,   162,
-      -1,    -1,   163,   133,   162,    -1,   163,   134,   162,    -1,
-      -1,   163,   125,   162,    -1,   163,   126,   162,    -1,   163,
-     143,   162,    -1,   163,   143,   158,   126,   162,    -1,   163,
-     126,   158,   143,   162,    -1,    -1,   163,   143,   162,    -1,
-      -1,   163,   126,   162,    -1,   108,    -1,   111,    -1,   110,
-      -1,   109,    -1,    -1,   163,   137,   162,    -1,   163,   137,
-     162,    -1,   163,   136,   162,    -1,   163,   136,   158,   137,
-     162,    -1,   163,   137,   158,   136,   162,    -1,    13,    -1,
-      14,    -1,    15,    -1,    -1,   163,   136,   162,    -1,    -1,
-     163,   136,   162,    -1,   164,    83,    26,   165,    -1,   164,
-      26,    84,   165,    -1,    75,    -1,    76,    -1,    79,    -1,
-      80,    -1,    81,    -1,    82,    -1,    71,    -1,    70,    -1,
-     163,   140,   162,    -1,   163,   129,   162,    -1,   163,   139,
-     162,    -1,   163,   130,   162,    -1,   163,   140,   158,   137,
-     162,    -1,   163,   129,   158,   137,   162,    -1,   163,   139,
-     158,   137,   162,    -1,   163,   130,   158,   137,   162,    -1,
-     163,   144,   162,    -1,   163,   145,   162,    -1,   163,   144,
-     158,   137,   162,    -1,   163,   145,   158,   137,   162,    -1,
-      -1,    84,    -1,    83,    -1,   179,    98,    -1,   179,   103,
-      -1,   179,   104,    -1,    26,    98,   179,    -1,   210,    -1,
-      26,    98,   163,   210,   162,    -1,    36,    98,   163,   210,
-     162,    -1,    36,    98,   179,    -1,   206,   211,    -1,   208,
-     211,    -1,   207,   211,    -1,    36,    72,    36,    -1,    98,
-      -1,   100,    -1,   102,    -1,   101,    -1,    28,   212,   166,
-      -1,    28,   212,   143,    -1,   166,   212,    28,    -1,   143,
-     212,    28,    -1,   168,    -1,   170,    -1,   171,    -1,   172,
-      -1,   214,   173,   215,    -1,   216,    -1,   220,    -1,   214,
-     173,   174,    -1,   169,    -1,   214,    -1,   163,   221,   162,
-      -1,    63,   221,    -1,    70,   221,    -1,   221,    -1,   221,
-      72,   221,    -1,   221,    73,   221,    -1,   221,    67,   221,
-      -1,   221,    71,   221,    -1,   221,    70,   221,    -1,   221,
-      91,   221,    -1,   221,    92,   221,    -1,   221,    65,   221,
-      -1,   221,    68,   221,    -1,   221,    66,   221,    -1,   219,
-      -1
-};
-
-/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
-static const unsigned short int yyrline[] =
-{
-       0,   567,   567,   568,   580,   582,   615,   642,   653,   657,
-     692,   712,   717,   727,   737,   742,   747,   763,   779,   791,
-     801,   814,   833,   851,   874,   896,   901,   911,   922,   933,
-     947,   962,   978,   994,  1010,  1021,  1035,  1061,  1079,  1084,
-    1090,  1102,  1113,  1124,  1135,  1146,  1157,  1168,  1194,  1208,
-    1218,  1263,  1282,  1293,  1304,  1315,  1326,  1337,  1353,  1370,
-    1386,  1397,  1408,  1439,  1450,  1463,  1474,  1513,  1523,  1533,
-    1553,  1563,  1573,  1583,  1594,  1602,  1612,  1622,  1633,  1657,
-    1668,  1674,  1685,  1696,  1707,  1715,  1736,  1761,  1788,  1822,
-    1836,  1847,  1861,  1895,  1905,  1915,  1940,  1952,  1970,  1981,
-    1992,  2003,  2016,  2027,  2038,  2049,  2060,  2071,  2104,  2114,
-    2127,  2147,  2158,  2169,  2182,  2195,  2206,  2217,  2228,  2239,
-    2249,  2260,  2271,  2283,  2294,  2305,  2316,  2329,  2341,  2353,
-    2364,  2375,  2386,  2398,  2410,  2421,  2432,  2443,  2453,  2459,
-    2465,  2471,  2477,  2483,  2489,  2495,  2501,  2507,  2513,  2524,
-    2535,  2546,  2557,  2568,  2579,  2590,  2596,  2607,  2618,  2629,
-    2640,  2651,  2661,  2674,  2682,  2690,  2714,  2725,  2736,  2747,
-    2758,  2769,  2781,  2794,  2803,  2814,  2825,  2837,  2848,  2859,
-    2870,  2884,  2896,  2911,  2930,  2941,  2959,  2993,  3011,  3028,
-    3039,  3050,  3061,  3082,  3101,  3114,  3128,  3140,  3156,  3196,
-    3229,  3237,  3253,  3272,  3286,  3305,  3321,  3329,  3338,  3349,
-    3361,  3375,  3383,  3393,  3405,  3410,  3415,  3421,  3429,  3435,
-    3441,  3447,  3460,  3464,  3474,  3478,  3483,  3488,  3493,  3500,
-    3504,  3511,  3515,  3520,  3525,  3533,  3537,  3544,  3548,  3556,
-    3561,  3567,  3576,  3581,  3587,  3593,  3599,  3608,  3611,  3615,
-    3622,  3625,  3629,  3636,  3641,  3647,  3653,  3659,  3664,  3672,
-    3675,  3682,  3685,  3692,  3696,  3700,  3704,  3711,  3714,  3721,
-    3726,  3733,  3740,  3752,  3756,  3760,  3767,  3770,  3780,  3783,
-    3792,  3798,  3807,  3811,  3818,  3822,  3826,  3830,  3837,  3841,
-    3848,  3856,  3864,  3872,  3880,  3887,  3894,  3902,  3912,  3917,
-    3922,  3927,  3935,  3938,  3942,  3951,  3958,  3965,  3972,  3987,
-    3993,  4001,  4009,  4027,  4034,  4041,  4051,  4064,  4068,  4072,
-    4076,  4083,  4089,  4095,  4101,  4111,  4120,  4122,  4124,  4128,
-    4136,  4140,  4147,  4153,  4159,  4163,  4167,  4171,  4177,  4183,
-    4187,  4191,  4195,  4199,  4203,  4207,  4211,  4215,  4219,  4223
-};
-#endif
-
-#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
-/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
-   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
-static const char *const yytname[] =
-{
-  "$end", "error", "$undefined", "BYTEOP16P", "BYTEOP16M", "BYTEOP1P",
-  "BYTEOP2P", "BYTEOP2M", "BYTEOP3P", "BYTEUNPACK", "BYTEPACK", "PACK",
-  "SAA", "ALIGN8", "ALIGN16", "ALIGN24", "VIT_MAX", "EXTRACT", "DEPOSIT",
-  "EXPADJ", "SEARCH", "ONES", "SIGN", "SIGNBITS", "LINK", "UNLINK", "REG",
-  "PC", "CCREG", "BYTE_DREG", "REG_A_DOUBLE_ZERO", "REG_A_DOUBLE_ONE",
-  "A_ZERO_DOT_L", "A_ZERO_DOT_H", "A_ONE_DOT_L", "A_ONE_DOT_H", "HALF_REG",
-  "NOP", "RTI", "RTS", "RTX", "RTN", "RTE", "HLT", "IDLE", "STI", "CLI",
-  "CSYNC", "SSYNC", "EMUEXCPT", "RAISE", "EXCPT", "LSETUP", "LOOP",
-  "LOOP_BEGIN", "LOOP_END", "DISALGNEXCPT", "JUMP", "JUMP_DOT_S",
-  "JUMP_DOT_L", "CALL", "ABORT", "NOT", "TILDA", "BANG", "AMPERSAND",
-  "BAR", "PERCENT", "CARET", "BXOR", "MINUS", "PLUS", "STAR", "SLASH",
-  "NEG", "MIN", "MAX", "ABS", "DOUBLE_BAR", "_PLUS_BAR_PLUS",
-  "_PLUS_BAR_MINUS", "_MINUS_BAR_PLUS", "_MINUS_BAR_MINUS", "_MINUS_MINUS",
-  "_PLUS_PLUS", "SHIFT", "LSHIFT", "ASHIFT", "BXORSHIFT",
-  "_GREATER_GREATER_GREATER_THAN_ASSIGN", "ROT", "LESS_LESS",
-  "GREATER_GREATER", "_GREATER_GREATER_GREATER", "_LESS_LESS_ASSIGN",
-  "_GREATER_GREATER_ASSIGN", "DIVS", "DIVQ", "ASSIGN", "_STAR_ASSIGN",
-  "_BAR_ASSIGN", "_CARET_ASSIGN", "_AMPERSAND_ASSIGN", "_MINUS_ASSIGN",
-  "_PLUS_ASSIGN", "_ASSIGN_BANG", "_LESS_THAN_ASSIGN", "_ASSIGN_ASSIGN",
-  "GE", "LT", "LE", "GT", "LESS_THAN", "FLUSHINV", "FLUSH", "IFLUSH",
-  "PREFETCH", "PRNT", "OUTC", "WHATREG", "TESTSET", "ASL", "ASR", "B", "W",
-  "NS", "S", "CO", "SCO", "TH", "TL", "BP", "BREV", "X", "Z", "M", "MMOD",
-  "R", "RND", "RNDL", "RNDH", "RND12", "RND20", "V", "LO", "HI", "BITTGL",
-  "BITCLR", "BITSET", "BITTST", "BITMUX", "DBGAL", "DBGAH", "DBGHALT",
-  "DBG", "DBGA", "DBGCMPLX", "IF", "COMMA", "BY", "COLON", "SEMICOLON",
-  "RPAREN", "LPAREN", "LBRACK", "RBRACK", "STATUS_REG", "MNOP", "SYMBOL",
-  "NUMBER", "GOT", "GOT17M4", "FUNCDESC_GOT17M4", "AT", "PLTPC", "$accept",
-  "statement", "asm", "asm_1", "REG_A", "opt_mode", "asr_asl", "sco",
-  "asr_asl_0", "amod0", "amod1", "amod2", "xpmod", "xpmod1", "vsmod",
-  "vmod", "smod", "searchmod", "aligndir", "byteop_mod", "c_align",
-  "w32_or_nothing", "iu_or_nothing", "reg_with_predec", "reg_with_postinc",
-  "min_max", "op_bar_op", "plus_minus", "rnd_op", "b3_op", "post_op",
-  "a_assign", "a_minusassign", "a_plusassign", "assign_macfunc",
-  "a_macfunc", "multiply_halfregs", "cc_op", "ccstat", "symbol",
-  "any_gotrel", "got", "got_or_expr", "pltpc", "eterm", "expr", "expr_1", 0
-};
-#endif
-
-# ifdef YYPRINT
-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-   token YYLEX-NUM.  */
-static const unsigned short int yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
-     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,
-     285,   286,   287,   288,   289,   290,   291,   292,   293,   294,
-     295,   296,   297,   298,   299,   300,   301,   302,   303,   304,
-     305,   306,   307,   308,   309,   310,   311,   312,   313,   314,
-     315,   316,   317,   318,   319,   320,   321,   322,   323,   324,
-     325,   326,   327,   328,   329,   330,   331,   332,   333,   334,
-     335,   336,   337,   338,   339,   340,   341,   342,   343,   344,
-     345,   346,   347,   348,   349,   350,   351,   352,   353,   354,
-     355,   356,   357,   358,   359,   360,   361,   362,   363,   364,
-     365,   366,   367,   368,   369,   370,   371,   372,   373,   374,
-     375,   376,   377,   378,   379,   380,   381,   382,   383,   384,
-     385,   386,   387,   388,   389,   390,   391,   392,   393,   394,
-     395,   396,   397,   398,   399,   400,   401,   402,   403,   404,
-     405,   406,   407,   408,   409,   410,   411,   412,   413,   414,
-     415,   416,   417,   418,   419,   420,   421,   422,   423,   424,
-     425,   426,   427,   428,   429
-};
-# endif
-
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
-static const unsigned char yyr1[] =
-{
-       0,   175,   176,   176,   177,   177,   177,   177,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
-     178,   178,   179,   179,   180,   180,   180,   180,   180,   181,
-     181,   182,   182,   182,   182,   183,   183,   184,   184,   185,
-     185,   185,   186,   186,   186,   186,   186,   187,   187,   187,
-     188,   188,   188,   189,   189,   189,   189,   189,   189,   190,
-     190,   191,   191,   192,   192,   192,   192,   193,   193,   194,
-     194,   194,   194,   195,   195,   195,   196,   196,   197,   197,
-     198,   199,   200,   200,   201,   201,   201,   201,   202,   202,
-     203,   203,   203,   203,   203,   203,   203,   203,   204,   204,
-     204,   204,   205,   205,   205,   206,   207,   208,   209,   209,
-     209,   209,   209,   210,   210,   210,   211,   212,   212,   212,
-     212,   213,   213,   213,   213,   214,   215,   215,   215,   216,
-     217,   217,   218,   219,   219,   219,   219,   219,   220,   221,
-     221,   221,   221,   221,   221,   221,   221,   221,   221,   221
-};
-
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
-static const unsigned char yyr2[] =
-{
-       0,     2,     0,     1,     2,     6,     4,     1,     1,     2,
-       5,     1,     6,     6,     3,     3,    17,    17,    11,    11,
-      11,    12,    12,    12,     5,     3,     3,     3,     8,    13,
-      12,    13,    13,    13,     8,    17,     6,     9,     3,     6,
-       3,     5,     6,     8,     8,     2,     2,     4,     3,     2,
-       4,     3,     6,     4,     7,     7,     3,     3,     6,     3,
-       4,     3,     3,     3,    11,    11,     9,     5,     5,     9,
-       5,     5,     6,     6,     5,     5,     5,     6,     6,     5,
-       1,     3,     3,     3,     3,     4,     4,     9,     9,     5,
-       7,     4,     6,     5,     6,     7,     9,     8,     8,    11,
-       9,     4,     5,     6,     7,     6,     4,     6,     5,     6,
-       6,     4,     8,    10,    10,    12,     5,     6,     5,     6,
-       4,     4,     4,     7,     9,     9,     9,     6,     6,     6,
-       8,     8,     6,     5,     5,     8,     4,     7,     1,     1,
-       1,     1,     1,     1,     1,     1,     1,     1,     2,     2,
-       4,     4,     6,     6,     2,     2,     4,     2,     2,     2,
-       2,     2,     2,     6,     6,     5,     4,     3,     3,     3,
-       3,     3,     3,     4,     2,     4,     2,     4,     2,     4,
-       2,     7,     8,     8,     7,     7,     7,     9,     7,     8,
-       9,     8,     6,     7,     8,     9,     8,     7,     7,     6,
-       3,    11,     7,    11,     7,     3,     2,     1,     7,     9,
-      11,     3,     5,     7,     1,     2,     2,     4,     1,     6,
-       6,     6,     1,     1,     0,     5,     5,     3,     3,     3,
-       3,     0,     1,     1,     1,     1,     1,     0,     3,     0,
-       3,     3,     0,     3,     3,     5,     5,     0,     3,     3,
-       0,     3,     3,     0,     3,     3,     3,     5,     5,     0,
-       3,     0,     3,     1,     1,     1,     1,     0,     3,     3,
-       3,     5,     5,     1,     1,     1,     0,     3,     0,     3,
-       4,     4,     1,     1,     1,     1,     1,     1,     1,     1,
-       3,     3,     3,     3,     5,     5,     5,     5,     3,     3,
-       5,     5,     0,     1,     1,     2,     2,     2,     3,     1,
-       5,     5,     3,     2,     2,     2,     3,     1,     1,     1,
-       1,     3,     3,     3,     3,     1,     1,     1,     1,     3,
-       1,     1,     3,     1,     1,     3,     2,     2,     1,     3,
-       3,     3,     3,     3,     3,     3,     3,     3,     3,     1
-};
-
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
-   means the default is an error.  */
-static const unsigned short int yydefact[] =
-{
-       0,     7,     0,     0,   207,     0,     0,   222,   223,     0,
-       0,     0,     0,     0,   138,   140,   139,   141,   142,   143,
-     144,     0,     0,   145,   146,   147,     0,     0,     0,     0,
-      11,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   218,   214,     0,     0,     0,     0,     0,
-       0,     8,   325,   333,     0,     3,     0,     0,     0,     0,
-       0,     0,   224,   309,    80,   334,   349,     0,   338,     0,
-       0,   206,     0,     0,     0,     0,     0,     0,     0,   317,
-     318,   320,   319,     0,     0,     0,     0,     0,     0,     0,
-     149,   148,   154,   155,     0,     0,     0,   157,   158,   334,
-     160,   159,     0,   162,   161,   336,   337,     0,     0,     0,
-     176,     0,   174,     0,   178,     0,   180,     0,     0,     0,
-     317,     0,     0,     0,     0,     0,     0,     0,   216,   215,
-       0,     0,     0,     0,     0,     0,   302,     0,     0,     1,
-       0,     4,   305,   306,   307,     0,    46,     0,     0,     0,
-       0,     0,     0,     0,    45,     0,   313,    49,   276,   315,
-     314,     0,     9,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,   169,   172,   170,   171,   167,
-     168,     0,     0,     0,     0,     0,     0,   273,   274,   275,
-       0,     0,     0,    81,    83,   247,     0,   247,     0,     0,
-     282,   283,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,   308,     0,     0,   224,   250,    63,    59,    57,    61,
-      62,    82,     0,     0,    84,     0,   322,   321,    26,    14,
-      27,    15,     0,     0,     0,     0,    51,     0,     0,     0,
-       0,     0,     0,   312,   224,    48,     0,   211,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-     302,   302,   324,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,   335,   289,   288,   304,
-     303,     0,     0,     0,   323,     0,   276,   205,     0,     0,
-      38,    25,     0,     0,     0,     0,     0,     0,     0,     0,
-      40,     0,    56,     0,     0,     0,   200,   346,   348,   341,
-     347,   343,   342,   339,   340,   344,   345,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-     288,   284,   285,   286,   287,     0,     0,     0,     0,     0,
-       0,    53,     0,    47,   166,   253,   259,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,   302,
-       0,     0,     0,    86,     0,    50,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,   111,   121,   122,
-     120,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,    85,     0,     0,   150,     0,   332,
-     151,     0,     0,     0,     0,   175,   173,   177,   179,   156,
-     303,     0,     0,   303,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   217,     0,   136,     0,     0,     0,     0,
-       0,     0,     0,   280,     0,     6,    60,     0,   316,     0,
-       0,     0,     0,     0,     0,    91,   106,   101,     0,     0,
-       0,   228,     0,   227,     0,     0,   224,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,    79,    67,    68,
-       0,   253,   259,   253,   237,   239,     0,     0,     0,     0,
-     165,     0,    24,     0,     0,     0,     0,   302,   302,     0,
-     307,     0,   310,   303,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   278,   278,    74,    75,   278,   278,     0,
-      76,    70,    71,     0,     0,     0,     0,     0,     0,     0,
-       0,    93,   108,   261,     0,   239,     0,     0,   302,     0,
-     311,     0,     0,   212,     0,     0,     0,     0,   281,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,   133,     0,     0,   134,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,   102,    89,     0,   116,
-     118,    41,   277,     0,     0,     0,     0,    10,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,    92,
-     107,   110,     0,   231,    52,     0,     0,    36,   249,   248,
-       0,     0,     0,     0,     0,   105,   259,   253,   117,   119,
-       0,     0,   303,     0,     0,     0,    12,     0,   334,   330,
-       0,   331,   199,     0,     0,     0,     0,   251,   252,    58,
-       0,    77,    78,    72,    73,     0,     0,     0,     0,     0,
-      42,     0,     0,     0,     0,    94,   109,     0,    39,   103,
-     261,   303,     0,    13,     0,     0,     0,   153,   152,   164,
-     163,     0,     0,     0,     0,     0,   129,   127,   128,     0,
-     221,   220,   219,     0,   132,     0,     0,     0,     0,     0,
-       0,   192,     5,     0,     0,     0,     0,     0,   225,   226,
-       0,   308,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,   232,   233,   234,     0,     0,
-       0,     0,     0,   254,     0,   255,     0,   256,   260,   104,
-      95,     0,   247,     0,     0,   247,     0,   197,     0,   198,
-       0,     0,     0,     0,     0,     0,     0,     0,   123,     0,
-       0,     0,     0,     0,     0,     0,     0,    90,     0,   188,
-       0,   208,   213,     0,   181,     0,     0,   184,   185,     0,
-     137,     0,     0,     0,     0,     0,     0,     0,   204,   193,
-     186,     0,   202,    55,    54,     0,     0,     0,     0,     0,
-       0,     0,    34,   112,     0,   247,    98,     0,     0,   238,
-       0,   240,   241,     0,     0,     0,   247,   196,   247,   247,
-     189,     0,   326,   327,   328,   329,     0,    28,   259,   224,
-     279,   131,   130,     0,     0,   259,    97,    43,    44,     0,
-       0,   262,     0,   191,   224,     0,   182,   194,   183,     0,
-     135,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,   124,   100,     0,    69,     0,
-       0,     0,   258,   257,   195,   190,   187,    66,     0,    37,
-      88,   229,   230,    96,     0,     0,     0,     0,    87,   209,
-     125,     0,     0,     0,     0,     0,     0,   126,     0,   267,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,   114,
-       0,   113,     0,     0,     0,     0,   267,   263,   266,   265,
-     264,     0,     0,     0,     0,     0,    64,     0,     0,     0,
-       0,    99,   242,   239,    20,   239,     0,     0,   210,     0,
-       0,    18,    19,   203,   201,    65,     0,    30,     0,     0,
-       0,   231,    23,    22,    21,   115,     0,     0,     0,   268,
-       0,    29,     0,    31,    32,     0,    33,   235,   236,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
-       0,     0,     0,   244,   231,   243,     0,     0,     0,     0,
-     270,     0,   269,     0,   291,     0,   293,     0,   292,     0,
-     290,     0,   298,     0,   299,     0,     0,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,   246,   245,
-       0,   267,   267,   271,   272,   295,   297,   296,   294,   300,
-     301,    35,    16,    17
-};
-
-/* YYDEFGOTO[NTERM-NUM]. */
-static const short int yydefgoto[] =
-{
-      -1,    64,    65,    66,   364,   172,   748,   718,   960,   604,
-     607,   942,   351,   375,   490,   492,   655,   911,   916,   951,
-     222,   312,   641,    68,   120,   223,   348,   291,   953,   956,
-     292,   365,   366,    71,    72,    73,   170,    94,    74,    75,
-     815,   629,   630,   110,    76,    77,    78
-};
-
-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-   STATE-NUM.  */
-#define YYPACT_NINF -903
-static const short int yypact[] =
-{
-     697,  -903,   -94,   277,  -903,   676,   315,  -903,  -903,    23,
-      32,    41,    58,    65,  -903,  -903,  -903,  -903,  -903,  -903,
-    -903,   121,   158,  -903,  -903,  -903,   277,   277,    29,   277,
-    -903,   318,   277,   277,   320,   277,   277,    94,   100,    64,
-     104,   108,   131,   137,   152,   165,   376,   160,   171,   176,
-     182,   219,   238,  -903,   566,   244,   251,    79,    96,    44,
-     376,  -903,  -903,  -903,   350,  -903,   -57,   187,   337,    63,
-     245,   394,   278,  -903,  -903,  -903,  -903,   349,   563,   436,
-     277,  -903,   146,   159,   167,   489,   438,   186,   188,    37,
-    -903,  -903,  -903,    15,  -118,   446,   462,   480,   485,    28,
-    -903,  -903,  -903,  -903,   277,   513,    50,  -903,  -903,   353,
-    -903,  -903,    85,  -903,  -903,  -903,  -903,   521,   534,   537,
-    -903,   542,  -903,   567,  -903,   575,  -903,   578,   583,   585,
-    -903,   619,   590,   598,   630,   651,   656,   680,  -903,  -903,
-     677,   693,    62,   692,   204,   470,   200,   698,   712,  -903,
-     886,  -903,  -903,  -903,   180,    -6,  -903,   419,   302,   180,
-     180,   180,   589,   180,    97,   277,  -903,  -903,   595,  -903,
-    -903,   297,   568,   277,   277,   277,   277,   277,   277,   277,
-     277,   277,   277,   277,   591,  -903,  -903,  -903,  -903,  -903,
-    -903,   599,   600,   601,   603,   605,   606,  -903,  -903,  -903,
-     609,   613,   614,   580,  -903,   615,   688,   -38,   210,   226,
-    -903,  -903,   735,   755,   756,   757,   759,   622,   623,    98,
-     762,   718,   627,   628,   278,   629,  -903,  -903,  -903,   632,
-    -903,   205,   633,   332,  -903,   634,  -903,  -903,  -903,  -903,
-    -903,  -903,   635,   636,   774,   449,   -25,   703,   227,   766,
-     768,   641,   302,  -903,   278,  -903,   648,   709,   647,   743,
-     642,   653,   747,   661,   664,   -62,   -31,   -19,    16,   662,
-     326,   372,  -903,   665,   667,   668,   669,   670,   671,   672,
-     673,   733,   277,    84,   806,   277,  -903,  -903,  -903,  -903,
-     808,   277,   674,   690,  -903,   -16,   595,  -903,   810,   801,
-     683,   684,   679,   699,   180,   700,   277,   277,   277,   730,
-    -903,   721,  -903,   -26,   116,   520,  -903,   441,   616,  -903,
-     457,   313,   313,  -903,  -903,   500,   500,   277,   836,   841,
-     842,   843,   844,   835,   846,   848,   849,   850,   851,   852,
-     716,  -903,  -903,  -903,  -903,   277,   277,   277,   855,   856,
-     316,  -903,   857,  -903,  -903,   722,   723,   725,   732,   734,
-     736,   868,   870,   826,   487,   394,   394,   245,   737,   389,
-     180,   877,   878,   748,   324,  -903,   773,   243,   268,   300,
-     881,   180,   180,   180,   882,   883,   189,  -903,  -903,  -903,
-    -903,   775,   903,   110,   277,   277,   277,   918,   905,   788,
-     789,   924,   245,   790,   793,   277,   927,  -903,   928,  -903,
-    -903,   929,   931,   932,   794,  -903,  -903,  -903,  -903,  -903,
-    -903,   277,   795,   935,   277,   797,   277,   277,   277,   937,
-     277,   277,   277,  -903,   938,   802,   869,   277,   804,   179,
-     803,   805,   871,  -903,   886,  -903,  -903,   811,  -903,   180,
-     180,   936,   940,   815,    72,  -903,  -903,  -903,   816,   817,
-     845,  -903,   853,  -903,   879,   887,   278,   822,   824,   827,
-     829,   830,   828,   833,   834,   837,   838,  -903,  -903,  -903,
-     967,   722,   723,   722,   -66,    92,   832,   854,   839,    95,
-    -903,   860,  -903,   962,   968,   969,   124,   326,   474,   981,
-    -903,   858,  -903,   982,   277,   847,   859,   861,   863,   985,
-     862,   864,   865,   867,   867,  -903,  -903,   867,   867,   873,
-    -903,  -903,  -903,   888,   866,   889,   890,   894,   872,   895,
-     896,   897,  -903,   897,   898,   899,   977,   978,   426,   901,
-    -903,   979,   902,   926,   904,   906,   907,   908,  -903,   880,
-     925,   892,   900,   946,   909,   910,   911,   893,   912,   913,
-     914,  -903,   891,   999,   915,   983,  1041,   984,   986,   987,
-    1051,   919,   277,   988,  1009,  1006,  -903,  -903,   180,  -903,
-    -903,   930,  -903,   933,   934,     2,     6,  -903,  1061,   277,
-     277,   277,   277,  1063,  1054,  1065,  1056,  1067,  1003,  -903,
-    -903,  -903,  1071,   427,  -903,  1072,   455,  -903,  -903,  -903,
-    1073,   939,   190,   209,   941,  -903,   723,   722,  -903,  -903,
-     277,   942,  1074,   277,   943,   944,  -903,   945,   947,  -903,
-     948,  -903,  -903,  1076,  1078,  1079,  1011,  -903,  -903,  -903,
-     975,  -903,  -903,  -903,  -903,   277,   277,   949,  1080,  1081,
-    -903,   497,   180,   180,   989,  -903,  -903,  1082,  -903,  -903,
-     897,  1088,   954,  -903,  1023,  1096,   277,  -903,  -903,  -903,
-    -903,  1025,  1098,  1027,  1028,   191,  -903,  -903,  -903,   180,
-    -903,  -903,  -903,   965,  -903,   997,   357,   970,   971,  1103,
-    1105,  -903,  -903,   246,   180,   180,   974,   180,  -903,  -903,
-     180,  -903,   180,   973,   976,   980,   990,   991,   992,   993,
-     994,   995,   996,   277,  1038,  -903,  -903,  -903,   998,  1039,
-    1000,  1001,  1042,  -903,  1002,  -903,  1013,  -903,  -903,  -903,
-    -903,  1004,   615,  1005,  1007,   615,  1050,  -903,   533,  -903,
-    1044,  1012,  1014,   394,  1015,  1016,  1017,   477,  -903,  1018,
-    1019,  1020,  1021,  1008,  1010,  1022,  1024,  -903,  1026,  -903,
-     394,  1045,  -903,  1118,  -903,  1110,  1121,  -903,  -903,  1030,
-    -903,  1031,  1032,  1033,  1124,  1125,   277,  1126,  -903,  -903,
-    -903,  1127,  -903,  -903,  -903,  1131,   180,   277,  1135,  1138,
-    1139,  1141,  -903,  -903,   949,   615,  1034,  1036,  1145,  -903,
-    1147,  -903,  -903,  1143,  1037,  1040,   615,  -903,   615,   615,
-    -903,   277,  -903,  -903,  -903,  -903,   180,  -903,   723,   278,
-    -903,  -903,  -903,  1043,  1046,   723,  -903,  -903,  -903,   588,
-    1159,  -903,  1115,  -903,   278,  1162,  -903,  -903,  -903,   949,
-    -903,  1163,  1164,  1047,  1048,  1052,  1116,  1049,  1053,  1055,
-    1057,  1060,  1062,  1064,  1066,  -903,  -903,  1068,  -903,   586,
-     624,  1123,  -903,  -903,  -903,  -903,  -903,  -903,  1133,  -903,
-    -903,  -903,  -903,  -903,  1059,  1058,  1069,  1168,  -903,  1114,
-    -903,  1070,  1075,   277,   582,  1112,   277,  -903,  1086,  1077,
-     277,   277,   277,   277,  1083,  1187,  1191,  1190,   180,  -903,
-    1197,  -903,  1156,   277,   277,   277,  1077,  -903,  -903,  -903,
-    -903,  1084,   971,  1085,  1087,  1091,  -903,  1089,  1090,  1092,
-    1093,  -903,  1094,   899,  -903,   899,  1097,  1207,  -903,  1095,
-    1100,  -903,  -903,  -903,  -903,  -903,  1099,  1101,  1102,  1102,
-    1104,   456,  -903,  -903,  -903,  -903,  1106,  1206,  1208,  -903,
-     579,  -903,   229,  -903,  -903,   555,  -903,  -903,  -903,   264,
-     448,  1200,  1108,  1111,   463,   464,   465,   479,   482,   516,
-     517,   518,   596,  -903,   427,  -903,  1113,   277,   277,  1107,
-    -903,  1120,  -903,  1129,  -903,  1136,  -903,  1137,  -903,  1140,
-    -903,  1142,  -903,  1144,  -903,  1122,  1128,  1161,  1130,  1132,
-    1134,  1146,  1148,  1149,  1150,  1151,  1152,  1153,  -903,  -903,
-    1201,  1077,  1077,  -903,  -903,  -903,  -903,  -903,  -903,  -903,
-    -903,  -903,  -903,  -903
-};
-
-/* YYPGOTO[NTERM-NUM].  */
-static const short int yypgoto[] =
-{
-    -903,  -903,  -903,  -134,    17,  -219,  -716,  -902,   266,  -903,
-    -520,  -903,  -201,  -903,  -443,  -472,  -478,  -903,  -788,  -903,
-    -903,   952,  -275,  -903,   -39,  -903,   380,  -196,   303,  -903,
-    -252,     4,     8,  -162,   955,  -210,   -58,    49,  -903,   -20,
-    -903,  -903,  -903,  1209,  -903,    -3,    25
-};
-
-/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
-   positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -3
-static const short int yytable[] =
-{
-      81,   122,   124,   126,    69,   373,   353,   349,    70,   368,
-     600,   166,   169,   109,   109,   658,   295,    67,   422,   425,
-     297,   150,   414,   102,   103,   236,   105,   224,   107,   108,
-     111,   114,     7,     8,   299,   404,     7,     8,   599,   959,
-     601,   254,   403,   234,   242,   287,   288,   243,   237,   244,
-     392,   245,   398,   414,   246,   656,   247,   367,     7,     8,
-     115,   116,   444,   231,   248,   414,   167,     7,     8,    79,
-     146,   139,   996,   165,   421,   424,   258,   259,   855,   186,
-     188,   190,   225,   145,   228,   230,   164,   168,   281,   156,
-     402,    35,   602,     7,     8,   131,   255,   603,    36,   157,
-     414,   256,   221,   415,   151,   145,   233,   142,   579,   148,
-     436,   261,   262,    35,   249,   250,   253,   505,   931,   282,
-      36,    95,   144,   880,   363,   350,    35,   147,     7,     8,
-      96,   145,   460,   158,   416,    35,   461,   145,   391,    97,
-     159,   437,    36,   143,   729,   445,   417,   100,    35,   160,
-     161,   162,   251,   163,    69,    36,    98,   298,    70,    35,
-     618,    35,   310,    99,   235,   700,    36,    67,    36,   702,
-     316,   296,   185,   504,   730,   300,   301,   302,   303,   529,
-     305,   418,   757,   116,   101,   187,   232,    35,   306,   307,
-     308,   252,   104,   189,    36,   152,    62,    63,   530,   317,
-     318,   319,   320,   321,   322,   323,   324,   325,   326,    35,
-       7,     8,   227,    80,   229,   525,    36,   767,    62,    63,
-     611,   612,    35,  1022,  1023,   526,    80,   768,   119,    36,
-      35,    62,    63,   115,   116,    80,   354,    36,   613,   642,
-      62,    63,   643,   644,   145,   621,   624,   587,    80,    35,
-     605,    35,   355,    62,    63,   606,    36,   117,    36,    80,
-     309,    80,   390,   118,    62,    63,    62,    63,   121,   513,
-     287,   288,   123,    35,   462,     7,     8,   145,   463,   435,
-      36,   157,   439,   289,   290,   152,   662,    80,   441,    35,
-     153,   154,    62,    63,   515,   125,    36,   287,   288,   299,
-     127,   620,   623,   455,   456,   457,    35,   166,   169,    80,
-     571,   377,   378,    36,    62,    63,   128,   379,   394,   395,
-     396,   453,    80,   132,   467,   397,   517,    62,    63,   129,
-      80,    35,     7,     8,   133,    62,    63,   566,    36,   134,
-      35,   567,   481,   482,   483,   135,   869,    36,   724,    80,
-     149,    80,   725,   873,    62,    63,    62,    63,   966,   967,
-     772,   773,   284,    35,   285,    35,   774,   726,   968,   969,
-      36,   727,    36,    80,   514,   516,   518,   775,    62,    63,
-     176,    35,   136,    35,   501,   180,   181,   506,    36,    80,
-      36,   531,   532,   533,    62,    63,   287,   288,   520,   521,
-     522,   137,   542,   943,   781,   944,    80,   140,   782,   289,
-     420,    62,    63,    89,   141,    90,    91,    92,   549,   539,
-      93,   552,   972,   554,   555,   556,   973,   558,   559,   560,
-     157,    80,   313,   314,   564,   155,    62,    63,   381,   382,
-      80,   171,   287,   288,   383,    62,    63,   173,    69,   486,
-     487,   580,    70,   574,   575,   289,   423,   510,   511,   287,
-     288,    67,   184,    80,   226,    80,   573,   573,    62,    63,
-      62,    63,   289,   503,   130,   388,    90,    91,    92,     7,
-       8,   106,   238,   112,   628,   389,    62,    63,    62,    63,
-     368,   299,   403,   619,   191,   192,   193,   194,   239,   195,
-     196,   631,   197,   198,   199,   200,   201,   202,   176,   289,
-     661,   178,   179,   180,   181,   203,   240,   204,   205,     7,
-       8,   241,   174,   206,   176,   207,   260,   178,   179,   180,
-     181,   807,   182,   183,   810,   174,   175,   176,   177,   257,
-     178,   179,   180,   181,   287,   288,   464,   263,   182,   183,
-       7,     8,   208,   715,   716,   717,   465,   289,   622,   209,
-     264,   182,   183,   265,   210,   211,   212,   176,   266,   693,
-     178,   179,   180,   181,   213,   214,   215,   957,   958,   216,
-     720,   721,   715,   716,   717,   152,   704,   705,   706,   707,
-     153,   500,   138,   267,   856,   696,     7,     8,   823,   824,
-     870,   268,   701,   253,   269,   864,   974,   865,   866,   270,
-     975,   271,   217,   218,   874,   878,   273,   731,     7,     8,
-     734,   979,   981,   983,   274,   980,   982,   984,   174,   175,
-     176,   177,   286,   178,   179,   180,   181,   985,   751,   752,
-     987,   986,   745,   746,   988,   337,   338,   272,   339,   778,
-     287,   340,   219,   220,   182,   183,   275,    62,    63,   341,
-     342,   343,   344,   762,   896,   341,   342,   343,   344,   753,
-     754,   345,   346,   347,   989,   991,   993,   276,   990,   992,
-     994,   174,   277,   176,   177,   819,   178,   179,   180,   181,
-     907,   908,   909,   910,   287,   288,   769,    -2,     1,   970,
-     971,   786,   834,   812,   813,   814,   278,   182,   183,     2,
-     797,   783,   784,   279,   573,   964,   965,   957,   958,   280,
-     283,     3,     4,     5,   293,     6,   315,     7,     8,     9,
-      10,    11,    12,    13,    14,    15,    16,    17,    18,    19,
-     294,    20,    21,    22,    23,    24,    25,    26,    27,    28,
-      29,   327,   304,    30,    31,    32,    33,    34,   311,   352,
-      35,   356,   328,   329,   330,    82,   331,    36,   332,   333,
-      83,    84,   334,   845,    85,    86,   335,   336,   350,    87,
-      88,   357,   358,   359,   850,   360,   361,   362,   369,   370,
-     371,   372,   374,    37,    38,   376,   380,   384,   385,   386,
-     387,   393,   399,   849,   400,   401,   405,   406,   867,   407,
-      39,    40,    41,    42,   408,   410,   409,    43,   411,   412,
-      44,    45,   413,   426,   419,   427,   428,   429,   430,   431,
-     432,   434,   438,   868,   440,   433,   447,   448,   451,   442,
-      46,   449,   450,    47,    48,    49,   875,    50,    51,    52,
-      53,    54,    55,    56,    57,   443,   458,   459,   452,   454,
-      58,    59,   468,    60,    61,    62,    63,   469,   470,   471,
-     472,   473,   474,   933,   475,   476,   477,   478,   479,   480,
-     906,   484,   485,   913,   493,   489,   491,   917,   918,   919,
-     920,   494,   488,   495,   497,   496,   498,   499,     2,   502,
-     928,   929,   930,   507,   508,   512,   509,   519,   523,   524,
-       3,     4,     5,   527,     6,   925,     7,     8,     9,    10,
-      11,    12,    13,    14,    15,    16,    17,    18,    19,   528,
-      20,    21,    22,    23,    24,    25,    26,    27,    28,    29,
-     534,   535,    30,    31,    32,    33,    34,   536,   537,    35,
-     538,   541,   540,   543,   544,   545,    36,   546,   547,   548,
-     550,   551,   553,   557,   561,   562,   565,   563,   568,   570,
-     569,   572,   576,   578,   998,   999,   577,   585,   581,   582,
-     588,   583,    37,    38,   589,   586,   593,   590,   584,   591,
-     592,   594,   595,   598,   608,   596,   597,   610,   615,    39,
-      40,    41,    42,   614,   616,   617,    43,   625,   627,    44,
-      45,   636,   632,   659,   660,   664,   609,   633,   666,   634,
-     626,   635,   683,   672,   637,   684,   638,   639,   647,    46,
-     640,   645,    47,    48,    49,   651,    50,    51,    52,    53,
-      54,    55,    56,    57,   675,   671,   646,   648,   649,    58,
-      59,   679,    60,    61,    62,    63,   650,   673,   652,   653,
-     654,   657,   606,   663,   665,   674,   667,   687,   668,   669,
-     670,   676,   677,   678,   680,   681,   682,   691,   685,   694,
-     692,   686,   688,   695,   689,   690,   152,   703,   697,   708,
-     709,   710,   711,   712,   713,   698,   699,   714,   719,   722,
-     733,   723,   740,   728,   741,   742,   736,   732,   735,   743,
-     737,   744,   747,   739,   758,   755,   749,   750,   756,   759,
-     738,   760,   761,   763,   764,   765,   766,   770,   771,   779,
-     776,   780,   785,   787,   788,   777,   798,   800,   789,   805,
-     803,   811,   816,   835,   836,   804,   837,   838,   790,   791,
-     843,   844,   846,   847,   792,   793,   794,   795,   796,   848,
-     799,   851,   801,   802,   852,   853,   829,   854,   830,   806,
-     808,   859,   809,   860,   817,   861,   818,   820,   821,   822,
-     825,   826,   827,   828,   831,   876,   832,   877,   879,   881,
-     882,   833,   839,   840,   897,   841,   842,   857,   858,   862,
-     414,   894,   863,   898,   902,   871,   903,   883,   872,   886,
-     912,   884,   914,   922,   885,   887,   900,   923,   888,   889,
-     890,   899,   891,   924,   892,   926,   893,   927,   936,   946,
-     904,   901,   962,  1010,   963,   905,   976,  1021,   995,   895,
-     915,     0,   954,   113,  1000,   921,   932,   934,   446,   935,
-       0,   937,   938,   947,   939,   940,  1001,   941,   948,   945,
-       0,   949,     0,     0,   950,   952,  1002,   955,   977,   961,
-     466,   978,     0,  1003,  1004,   997,     0,  1005,     0,  1006,
-       0,  1007,     0,     0,  1008,     0,     0,     0,     0,     0,
-    1009,     0,  1011,     0,  1012,     0,  1013,     0,     0,     0,
-       0,     0,     0,     0,     0,     0,     0,     0,  1014,     0,
-    1015,  1016,  1017,  1018,  1019,  1020
-};
-
-static const short int yycheck[] =
-{
-       3,    40,    41,    42,     0,   224,   207,   203,     0,   219,
-     482,    69,    70,    33,    34,   535,   150,     0,   270,   271,
-      26,    78,    84,    26,    27,   143,    29,    85,    31,    32,
-      33,    34,    30,    31,    72,   254,    30,    31,   481,   941,
-     483,    99,   252,    28,    16,    70,    71,    19,   166,    21,
-     246,    23,   248,    84,    26,   533,    28,   219,    30,    31,
-      35,    36,    78,    26,    36,    84,    69,    30,    31,   163,
-      26,    54,   974,    69,   270,   271,    26,    27,   794,    82,
-      83,    84,    85,    58,    87,    88,    69,    70,    26,    26,
-     252,    63,   158,    30,    31,    46,    99,   163,    70,    36,
-      84,   104,    85,   165,   161,    80,    89,    28,    36,    60,
-      26,    26,    27,    63,    86,    87,    99,   369,   906,    57,
-      70,    98,    26,   839,    26,   163,    63,    83,    30,    31,
-      98,   106,   158,    70,   165,    63,   162,   112,   163,    98,
-      77,    57,    70,    64,   616,   161,   165,    26,    63,    86,
-      87,    88,   124,    90,   150,    70,    98,   163,   150,    63,
-      36,    63,   165,    98,   149,   163,    70,   150,    70,   163,
-     173,   154,    26,   369,   617,   158,   159,   160,   161,    69,
-     163,   165,   660,   158,    26,    26,   149,    63,    91,    92,
-      93,   163,   163,    26,    70,    98,   168,   169,    88,   174,
-     175,   176,   177,   178,   179,   180,   181,   182,   183,    63,
-      30,    31,    26,   163,    26,    26,    70,    26,   168,   169,
-     125,   126,    63,  1011,  1012,    36,   163,    36,   164,    70,
-      63,   168,   169,   208,   209,   163,    26,    70,   143,   514,
-     168,   169,   517,   518,   219,   497,   498,   466,   163,    63,
-     158,    63,    26,   168,   169,   163,    70,   163,    70,   163,
-     163,   163,   245,   163,   168,   169,   168,   169,   164,    26,
-      70,    71,   164,    63,   158,    30,    31,   252,   162,   282,
-      70,    36,   285,    83,    84,    98,   538,   163,   291,    63,
-     103,   104,   168,   169,    26,   164,    70,    70,    71,    72,
-     163,   497,   498,   306,   307,   308,    63,   365,   366,   163,
-     444,   106,   107,    70,   168,   169,   164,   112,    91,    92,
-      93,   304,   163,   163,   327,    98,    26,   168,   169,   164,
-     163,    63,    30,    31,   163,   168,   169,   158,    70,   163,
-      63,   162,   345,   346,   347,   163,   818,    70,   158,   163,
-       0,   163,   162,   825,   168,   169,   168,   169,   129,   130,
-       3,     4,   158,    63,   160,    63,     9,   158,   139,   140,
-      70,   162,    70,   163,   377,   378,   379,    20,   168,   169,
-      67,    63,   163,    63,   367,    72,    73,   370,    70,   163,
-      70,   394,   395,   396,   168,   169,    70,    71,   381,   382,
-     383,   163,   405,   923,   158,   925,   163,   163,   162,    83,
-      84,   168,   169,    98,   163,   100,   101,   102,   421,   402,
-     105,   424,   158,   426,   427,   428,   162,   430,   431,   432,
-      36,   163,   135,   136,   437,    98,   168,   169,   106,   107,
-     163,   163,    70,    71,   112,   168,   169,    98,   444,   133,
-     134,   454,   444,   449,   450,    83,    84,   133,   134,    70,
-      71,   444,    26,   163,    26,   163,   449,   450,   168,   169,
-     168,   169,    83,    84,    98,    26,   100,   101,   102,    30,
-      31,   163,    36,   163,   504,    36,   168,   169,   168,   169,
-     700,    72,   702,   496,     5,     6,     7,     8,    36,    10,
-      11,   504,    13,    14,    15,    16,    17,    18,    67,    83,
-      84,    70,    71,    72,    73,    26,    36,    28,    29,    30,
-      31,    36,    65,    34,    67,    36,   173,    70,    71,    72,
-      73,   732,    91,    92,   735,    65,    66,    67,    68,    26,
-      70,    71,    72,    73,    70,    71,    26,    26,    91,    92,
-      30,    31,    63,   126,   127,   128,    36,    83,    84,    70,
-      26,    91,    92,    26,    75,    76,    77,    67,    26,   572,
-      70,    71,    72,    73,    85,    86,    87,   121,   122,    90,
-     125,   126,   126,   127,   128,    98,   589,   590,   591,   592,
-     103,   104,    26,    26,   795,   578,    30,    31,   121,   122,
-     819,    26,   585,   586,    26,   806,   158,   808,   809,    26,
-     162,    26,   123,   124,    26,   834,    26,   620,    30,    31,
-     623,   158,   158,   158,    26,   162,   162,   162,    65,    66,
-      67,    68,   162,    70,    71,    72,    73,   158,   141,   142,
-     158,   162,   645,   646,   162,    65,    66,    28,    68,   688,
-      70,    71,   163,   164,    91,    92,    26,   168,   169,    79,
-      80,    81,    82,   666,   860,    79,    80,    81,    82,   652,
-     653,    91,    92,    93,   158,   158,   158,    26,   162,   162,
-     162,    65,    26,    67,    68,   743,    70,    71,    72,    73,
-     108,   109,   110,   111,    70,    71,   679,     0,     1,   144,
-     145,   697,   760,   170,   171,   172,    26,    91,    92,    12,
-     713,   694,   695,    36,   697,   136,   137,   121,   122,    26,
-      28,    24,    25,    26,    26,    28,   158,    30,    31,    32,
-      33,    34,    35,    36,    37,    38,    39,    40,    41,    42,
-      28,    44,    45,    46,    47,    48,    49,    50,    51,    52,
-      53,   160,   163,    56,    57,    58,    59,    60,   163,    71,
-      63,    26,   163,   163,   163,    89,   163,    70,   163,   163,
-      94,    95,   163,   776,    98,    99,   163,   163,   163,   103,
-     104,    26,    26,    26,   787,    26,   164,   164,    26,    71,
-     163,   163,   163,    96,    97,   163,   163,   163,   163,   163,
-      26,    98,    36,   786,    36,   164,   158,    98,   811,   162,
-     113,   114,   115,   116,    71,   162,   174,   120,    71,   158,
-     123,   124,   158,   158,   162,   158,   158,   158,   158,   158,
-     158,    98,    26,   816,    26,   162,    26,    36,   159,   165,
-     143,   158,   158,   146,   147,   148,   829,   150,   151,   152,
-     153,   154,   155,   156,   157,   165,   126,   136,   159,   159,
-     163,   164,    26,   166,   167,   168,   169,    26,    26,    26,
-      26,    36,    26,   912,    26,    26,    26,    26,    26,   163,
-     883,    26,    26,   886,   159,   163,   163,   890,   891,   892,
-     893,   159,    35,   159,    26,   159,    26,    71,    12,   162,
-     903,   904,   905,    26,    26,   132,   158,    26,    26,    26,
-      24,    25,    26,   138,    28,   898,    30,    31,    32,    33,
-      34,    35,    36,    37,    38,    39,    40,    41,    42,    26,
-      44,    45,    46,    47,    48,    49,    50,    51,    52,    53,
-      22,    36,    56,    57,    58,    59,    60,   159,   159,    63,
-      26,   158,   162,    26,    26,    26,    70,    26,    26,   165,
-     165,    26,   165,    26,    26,   163,   162,    98,   165,    98,
-     165,   160,    36,   158,   977,   978,    36,    98,   162,   162,
-     158,   136,    96,    97,   160,    98,   158,   160,   135,   160,
-     160,   158,   158,    26,   162,   158,   158,   158,    36,   113,
-     114,   115,   116,   143,    36,    36,   120,    26,    26,   123,
-     124,    26,   165,    36,    36,    36,   162,   158,    92,   158,
-     162,   158,   131,    98,   162,    26,   162,   162,   162,   143,
-     163,   158,   146,   147,   148,   163,   150,   151,   152,   153,
-     154,   155,   156,   157,    98,   165,   158,   158,   158,   163,
-     164,   158,   166,   167,   168,   169,   162,   165,   163,   163,
-     163,   163,   163,   162,   162,   165,   162,    26,   162,   162,
-     162,   162,   162,   162,   162,   162,   162,    26,   163,    70,
-     161,    98,    98,    77,    98,    98,    98,    26,   158,    26,
-      36,    26,    36,    26,    91,   162,   162,    26,    26,    26,
-      26,   162,    26,   162,    26,    26,   162,   165,   165,    98,
-     165,   136,   163,   165,    26,   126,    36,    36,    36,   165,
-     173,    98,    26,    98,    26,    98,    98,   162,   131,    26,
-     160,    26,   158,   160,   158,   164,    98,    98,   158,   126,
-      98,    91,    98,    98,    26,   143,    36,    26,   158,   158,
-      26,    26,    26,    26,   162,   162,   162,   162,   162,    28,
-     162,    26,   162,   162,    26,    26,   158,    26,   158,   165,
-     165,    26,   165,    26,   162,    32,   162,   162,   162,   162,
-     162,   162,   162,   162,   162,    26,   162,    72,    26,    26,
-      26,   165,   162,   162,    71,   163,   163,   163,   162,   162,
-      84,   133,   162,    70,    36,   162,    92,   160,   162,   160,
-      98,   163,   126,    26,   162,   162,   158,    26,   163,   162,
-     160,   162,   160,    33,   160,    28,   160,    71,   137,    22,
-     160,   162,    26,    72,    26,   160,    36,    36,   972,   859,
-     163,    -1,   939,    34,   137,   162,   162,   162,   296,   162,
-      -1,   162,   162,   158,   162,   162,   136,   163,   158,   162,
-      -1,   162,    -1,    -1,   163,   163,   137,   163,   160,   163,
-     315,   160,    -1,   137,   137,   162,    -1,   137,    -1,   137,
-      -1,   137,    -1,    -1,   162,    -1,    -1,    -1,    -1,    -1,
-     162,    -1,   162,    -1,   162,    -1,   162,    -1,    -1,    -1,
-      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   162,    -1,
-     162,   162,   162,   162,   162,   162
-};
-
-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-   symbol of state STATE-NUM.  */
-static const unsigned char yystos[] =
-{
-       0,     1,    12,    24,    25,    26,    28,    30,    31,    32,
-      33,    34,    35,    36,    37,    38,    39,    40,    41,    42,
-      44,    45,    46,    47,    48,    49,    50,    51,    52,    53,
-      56,    57,    58,    59,    60,    63,    70,    96,    97,   113,
-     114,   115,   116,   120,   123,   124,   143,   146,   147,   148,
-     150,   151,   152,   153,   154,   155,   156,   157,   163,   164,
-     166,   167,   168,   169,   176,   177,   178,   179,   198,   206,
-     207,   208,   209,   210,   213,   214,   219,   220,   221,   163,
-     163,   220,    89,    94,    95,    98,    99,   103,   104,    98,
-     100,   101,   102,   105,   212,    98,    98,    98,    98,    98,
-      26,    26,   220,   220,   163,   220,   163,   220,   220,   214,
-     218,   220,   163,   218,   220,   221,   221,   163,   163,   164,
-     199,   164,   199,   164,   199,   164,   199,   163,   164,   164,
-      98,   212,   163,   163,   163,   163,   163,   163,    26,   179,
-     163,   163,    28,    64,    26,   221,    26,    83,   212,     0,
-      78,   161,    98,   103,   104,    98,    26,    36,    70,    77,
-      86,    87,    88,    90,   179,   206,   211,   220,   179,   211,
-     211,   163,   180,    98,    65,    66,    67,    68,    70,    71,
-      72,    73,    91,    92,    26,    26,   220,    26,   220,    26,
-     220,     5,     6,     7,     8,    10,    11,    13,    14,    15,
-      16,    17,    18,    26,    28,    29,    34,    36,    63,    70,
-      75,    76,    77,    85,    86,    87,    90,   123,   124,   163,
-     164,   179,   195,   200,   211,   220,    26,    26,   220,    26,
-     220,    26,   149,   179,    28,   149,   143,   166,    36,    36,
-      36,    36,    16,    19,    21,    23,    26,    28,    36,    86,
-      87,   124,   163,   179,   211,   220,   220,    26,    26,    27,
-     173,    26,    27,    26,    26,    26,    26,    26,    26,    26,
-      26,    26,    28,    26,    26,    26,    26,    26,    26,    36,
-      26,    26,    57,    28,   158,   160,   162,    70,    71,    83,
-      84,   202,   205,    26,    28,   178,   179,    26,   163,    72,
-     179,   179,   179,   179,   163,   179,    91,    92,    93,   163,
-     220,   163,   196,   135,   136,   158,   220,   221,   221,   221,
-     221,   221,   221,   221,   221,   221,   221,   160,   163,   163,
-     163,   163,   163,   163,   163,   163,   163,    65,    66,    68,
-      71,    79,    80,    81,    82,    91,    92,    93,   201,   202,
-     163,   187,    71,   187,    26,    26,    26,    26,    26,    26,
-      26,   164,   164,    26,   179,   206,   207,   208,   210,    26,
-      71,   163,   163,   180,   163,   188,   163,   106,   107,   112,
-     163,   106,   107,   112,   163,   163,   163,    26,    26,    36,
-     179,   163,   202,    98,    91,    92,    93,    98,   202,    36,
-      36,   164,   208,   210,   180,   158,    98,   162,    71,   174,
-     162,    71,   158,   158,    84,   165,   165,   165,   165,   162,
-      84,   202,   205,    84,   202,   205,   158,   158,   158,   158,
-     158,   158,   158,   162,    98,   220,    26,    57,    26,   220,
-      26,   220,   165,   165,    78,   161,   196,    26,    36,   158,
-     158,   159,   159,   179,   159,   220,   220,   220,   126,   136,
-     158,   162,   158,   162,    26,    36,   209,   220,    26,    26,
-      26,    26,    26,    36,    26,    26,    26,    26,    26,    26,
-     163,   220,   220,   220,    26,    26,   133,   134,    35,   163,
-     189,   163,   190,   159,   159,   159,   159,    26,    26,    71,
-     104,   179,   162,    84,   202,   205,   179,    26,    26,   158,
-     133,   134,   132,    26,   220,    26,   220,    26,   220,    26,
-     179,   179,   179,    26,    26,    26,    36,   138,    26,    69,
-      88,   220,   220,   220,    22,    36,   159,   159,    26,   179,
-     162,   158,   220,    26,    26,    26,    26,    26,   165,   220,
-     165,    26,   220,   165,   220,   220,   220,    26,   220,   220,
-     220,    26,   163,    98,   220,   162,   158,   162,   165,   165,
-      98,   178,   160,   179,   206,   206,    36,    36,   158,    36,
-     220,   162,   162,   136,   135,    98,    98,   180,   158,   160,
-     160,   160,   160,   158,   158,   158,   158,   158,    26,   189,
-     190,   189,   158,   163,   184,   158,   163,   185,   162,   162,
-     158,   125,   126,   143,   143,    36,    36,    36,    36,   220,
-     202,   205,    84,   202,   205,    26,   162,    26,   214,   216,
-     217,   220,   165,   158,   158,   158,    26,   162,   162,   162,
-     163,   197,   197,   197,   197,   158,   158,   162,   158,   158,
-     162,   163,   163,   163,   163,   191,   191,   163,   185,    36,
-      36,    84,   205,   162,    36,   162,    92,   162,   162,   162,
-     162,   165,    98,   165,   165,    98,   162,   162,   162,   158,
-     162,   162,   162,   131,    26,   163,    98,    26,    98,    98,
-      98,    26,   161,   220,    70,    77,   179,   158,   162,   162,
-     163,   179,   163,    26,   220,   220,   220,   220,    26,    36,
-      26,    36,    26,    91,    26,   126,   127,   128,   182,    26,
-     125,   126,    26,   162,   158,   162,   158,   162,   162,   190,
-     189,   220,   165,    26,   220,   165,   162,   165,   173,   165,
-      26,    26,    26,    98,   136,   220,   220,   163,   181,    36,
-      36,   141,   142,   179,   179,   126,    36,   191,    26,   165,
-      98,    26,   220,    98,    26,    98,    98,    26,    36,   179,
-     162,   131,     3,     4,     9,    20,   160,   164,   199,    26,
-      26,   158,   162,   179,   179,   158,   206,   160,   158,   158,
-     158,   158,   162,   162,   162,   162,   162,   220,    98,   162,
-      98,   162,   162,    98,   143,   126,   165,   187,   165,   165,
-     187,    91,   170,   171,   172,   215,    98,   162,   162,   211,
-     162,   162,   162,   121,   122,   162,   162,   162,   162,   158,
-     158,   162,   162,   165,   211,    98,    26,    36,    26,   162,
-     162,   163,   163,    26,    26,   220,    26,    26,    28,   179,
-     220,    26,    26,    26,    26,   181,   187,   163,   162,    26,
-      26,    32,   162,   162,   187,   187,   187,   220,   179,   190,
-     180,   162,   162,   190,    26,   179,    26,    72,   180,    26,
-     181,    26,    26,   160,   163,   162,   160,   162,   163,   162,
-     160,   160,   160,   160,   133,   201,   202,    71,    70,   162,
-     158,   162,    36,    92,   160,   160,   220,   108,   109,   110,
-     111,   192,    98,   220,   126,   163,   193,   220,   220,   220,
-     220,   162,    26,    26,    33,   179,    28,    71,   220,   220,
-     220,   193,   162,   199,   162,   162,   137,   162,   162,   162,
-     162,   163,   186,   185,   185,   162,    22,   158,   158,   162,
-     163,   194,   163,   203,   203,   163,   204,   121,   122,   182,
-     183,   163,    26,    26,   136,   137,   129,   130,   139,   140,
-     144,   145,   158,   162,   158,   162,    36,   160,   160,   158,
-     162,   158,   162,   158,   162,   158,   162,   158,   162,   158,
-     162,   158,   162,   158,   162,   183,   182,   162,   220,   220,
-     137,   136,   137,   137,   137,   137,   137,   137,   162,   162,
-      72,   162,   162,   162,   162,   162,   162,   162,   162,   162,
-     162,    36,   193,   193
-};
-
-#define yyerrok		(yyerrstatus = 0)
-#define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		(-2)
-#define YYEOF		0
-
-#define YYACCEPT	goto yyacceptlab
-#define YYABORT		goto yyabortlab
-#define YYERROR		goto yyerrorlab
-
-
-/* Like YYERROR except do call yyerror.  This remains here temporarily
-   to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
-
-#define YYFAIL		goto yyerrlab
-
-#define YYRECOVERING()  (!!yyerrstatus)
-
-#define YYBACKUP(Token, Value)					\
-do								\
-  if (yychar == YYEMPTY && yylen == 1)				\
-    {								\
-      yychar = (Token);						\
-      yylval = (Value);						\
-      yytoken = YYTRANSLATE (yychar);				\
-      YYPOPSTACK;						\
-      goto yybackup;						\
-    }								\
-  else								\
-    {								\
-      yyerror (YY_("syntax error: cannot back up")); \
-      YYERROR;							\
-    }								\
-while (0)
-
-
-#define YYTERROR	1
-#define YYERRCODE	256
-
-
-/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
-   If N is 0, then set CURRENT to the empty location which ends
-   the previous symbol: RHS[0] (always defined).  */
-
-#define YYRHSLOC(Rhs, K) ((Rhs)[K])
-#ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)				\
-    do									\
-      if (N)								\
-	{								\
-	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
-	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
-	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
-	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
-	}								\
-      else								\
-	{								\
-	  (Current).first_line   = (Current).last_line   =		\
-	    YYRHSLOC (Rhs, 0).last_line;				\
-	  (Current).first_column = (Current).last_column =		\
-	    YYRHSLOC (Rhs, 0).last_column;				\
-	}								\
-    while (0)
-#endif
-
-
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
-
-#ifndef YY_LOCATION_PRINT
-# if YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)			\
-     fprintf (File, "%d.%d-%d.%d",			\
-              (Loc).first_line, (Loc).first_column,	\
-              (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
-#endif
-
-
-/* YYLEX -- calling `yylex' with the right arguments.  */
-
-#ifdef YYLEX_PARAM
-# define YYLEX yylex (YYLEX_PARAM)
-#else
-# define YYLEX yylex ()
-#endif
-
-/* Enable debugging if requested.  */
-#if YYDEBUG
-
-# ifndef YYFPRINTF
-#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYFPRINTF fprintf
-# endif
-
-# define YYDPRINTF(Args)			\
-do {						\
-  if (yydebug)					\
-    YYFPRINTF Args;				\
-} while (0)
-
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
-do {								\
-  if (yydebug)							\
-    {								\
-      YYFPRINTF (stderr, "%s ", Title);				\
-      yysymprint (stderr,					\
-                  Type, Value);	\
-      YYFPRINTF (stderr, "\n");					\
-    }								\
-} while (0)
-
-/*------------------------------------------------------------------.
-| yy_stack_print -- Print the state stack from its BOTTOM up to its |
-| TOP (included).                                                   |
-`------------------------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_stack_print (short int *bottom, short int *top)
-#else
-static void
-yy_stack_print (bottom, top)
-    short int *bottom;
-    short int *top;
-#endif
-{
-  YYFPRINTF (stderr, "Stack now");
-  for (/* Nothing. */; bottom <= top; ++bottom)
-    YYFPRINTF (stderr, " %d", *bottom);
-  YYFPRINTF (stderr, "\n");
-}
-
-# define YY_STACK_PRINT(Bottom, Top)				\
-do {								\
-  if (yydebug)							\
-    yy_stack_print ((Bottom), (Top));				\
-} while (0)
-
-
-/*------------------------------------------------.
-| Report that the YYRULE is going to be reduced.  |
-`------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_reduce_print (int yyrule)
-#else
-static void
-yy_reduce_print (yyrule)
-    int yyrule;
-#endif
-{
-  int yyi;
-  unsigned long int yylno = yyrline[yyrule];
-  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
-             yyrule - 1, yylno);
-  /* Print the symbols being reduced, and their result.  */
-  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
-    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
-  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
-}
-
-# define YY_REDUCE_PRINT(Rule)		\
-do {					\
-  if (yydebug)				\
-    yy_reduce_print (Rule);		\
-} while (0)
-
-/* Nonzero means print parse trace.  It is left uninitialized so that
-   multiple parsers can coexist.  */
-int yydebug;
-#else /* !YYDEBUG */
-# define YYDPRINTF(Args)
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
-# define YY_STACK_PRINT(Bottom, Top)
-# define YY_REDUCE_PRINT(Rule)
-#endif /* !YYDEBUG */
-
-
-/* YYINITDEPTH -- initial size of the parser's stacks.  */
-#ifndef	YYINITDEPTH
-# define YYINITDEPTH 200
-#endif
-
-/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
-   if the built-in stack extension method is used).
-
-   Do not make this value too large; the results are undefined if
-   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
-   evaluated with infinite-precision integer arithmetic.  */
-
-#ifndef YYMAXDEPTH
-# define YYMAXDEPTH 10000
-#endif
-
-
-
-#if YYERROR_VERBOSE
-
-# ifndef yystrlen
-#  if defined (__GLIBC__) && defined (_STRING_H)
-#   define yystrlen strlen
-#  else
-/* Return the length of YYSTR.  */
-static YYSIZE_T
-#   if defined (__STDC__) || defined (__cplusplus)
-yystrlen (const char *yystr)
-#   else
-yystrlen (yystr)
-     const char *yystr;
-#   endif
-{
-  const char *yys = yystr;
-
-  while (*yys++ != '\0')
-    continue;
-
-  return yys - yystr - 1;
-}
-#  endif
-# endif
-
-# ifndef yystpcpy
-#  if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
-#   define yystpcpy stpcpy
-#  else
-/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
-   YYDEST.  */
-static char *
-#   if defined (__STDC__) || defined (__cplusplus)
-yystpcpy (char *yydest, const char *yysrc)
-#   else
-yystpcpy (yydest, yysrc)
-     char *yydest;
-     const char *yysrc;
-#   endif
-{
-  char *yyd = yydest;
-  const char *yys = yysrc;
-
-  while ((*yyd++ = *yys++) != '\0')
-    continue;
-
-  return yyd - 1;
-}
-#  endif
-# endif
-
-# ifndef yytnamerr
-/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
-   quotes and backslashes, so that it's suitable for yyerror.  The
-   heuristic is that double-quoting is unnecessary unless the string
-   contains an apostrophe, a comma, or backslash (other than
-   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
-   null, do not copy; instead, return the length of what the result
-   would have been.  */
-static YYSIZE_T
-yytnamerr (char *yyres, const char *yystr)
-{
-  if (*yystr == '"')
-    {
-      size_t yyn = 0;
-      char const *yyp = yystr;
-
-      for (;;)
-	switch (*++yyp)
-	  {
-	  case '\'':
-	  case ',':
-	    goto do_not_strip_quotes;
-
-	  case '\\':
-	    if (*++yyp != '\\')
-	      goto do_not_strip_quotes;
-	    /* Fall through.  */
-	  default:
-	    if (yyres)
-	      yyres[yyn] = *yyp;
-	    yyn++;
-	    break;
-
-	  case '"':
-	    if (yyres)
-	      yyres[yyn] = '\0';
-	    return yyn;
-	  }
-    do_not_strip_quotes: ;
-    }
-
-  if (! yyres)
-    return yystrlen (yystr);
-
-  return yystpcpy (yyres, yystr) - yyres;
-}
-# endif
-
-#endif /* YYERROR_VERBOSE */
-
-
-
-#if YYDEBUG
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yysymprint (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (yytype < YYNTOKENS)
-    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-  else
-    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-
-
-# ifdef YYPRINT
-  if (yytype < YYNTOKENS)
-    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
-# endif
-  switch (yytype)
-    {
-      default:
-        break;
-    }
-  YYFPRINTF (yyoutput, ")");
-}
-
-#endif /* ! YYDEBUG */
-/*-----------------------------------------------.
-| Release the memory associated to this symbol.  |
-`-----------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yydestruct (yymsg, yytype, yyvaluep)
-    const char *yymsg;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (!yymsg)
-    yymsg = "Deleting";
-  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
-
-  switch (yytype)
-    {
-
-      default:
-        break;
-    }
-}
-
-
-/* Prevent warnings from -Wmissing-prototypes.  */
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM);
-# else
-int yyparse ();
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void);
-#else
-int yyparse ();
-#endif
-#endif /* ! YYPARSE_PARAM */
-
-
-
-/* The look-ahead symbol.  */
-int yychar;
-
-/* The semantic value of the look-ahead symbol.  */
-YYSTYPE yylval;
-
-/* Number of syntax errors so far.  */
-int yynerrs;
-
-
-
-/*----------.
-| yyparse.  |
-`----------*/
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM)
-# else
-int yyparse (YYPARSE_PARAM)
-  void *YYPARSE_PARAM;
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int
-yyparse (void)
-#else
-int
-yyparse ()
-    ;
-#endif
-#endif
-{
-  
-  int yystate;
-  int yyn;
-  int yyresult;
-  /* Number of tokens to shift before error messages enabled.  */
-  int yyerrstatus;
-  /* Look-ahead token as an internal (translated) token number.  */
-  int yytoken = 0;
-
-  /* Three stacks and their tools:
-     `yyss': related to states,
-     `yyvs': related to semantic values,
-     `yyls': related to locations.
-
-     Refer to the stacks thru separate pointers, to allow yyoverflow
-     to reallocate them elsewhere.  */
-
-  /* The state stack.  */
-  short int yyssa[YYINITDEPTH];
-  short int *yyss = yyssa;
-  short int *yyssp;
-
-  /* The semantic value stack.  */
-  YYSTYPE yyvsa[YYINITDEPTH];
-  YYSTYPE *yyvs = yyvsa;
-  YYSTYPE *yyvsp;
-
-
-
-#define YYPOPSTACK   (yyvsp--, yyssp--)
-
-  YYSIZE_T yystacksize = YYINITDEPTH;
-
-  /* The variables used to return semantic value and location from the
-     action routines.  */
-  YYSTYPE yyval;
-
-
-  /* When reducing, the number of symbols on the RHS of the reduced
-     rule.  */
-  int yylen;
-
-  YYDPRINTF ((stderr, "Starting parse\n"));
-
-  yystate = 0;
-  yyerrstatus = 0;
-  yynerrs = 0;
-  yychar = YYEMPTY;		/* Cause a token to be read.  */
-
-  /* Initialize stack pointers.
-     Waste one element of value and location stack
-     so that they stay on the same level as the state stack.
-     The wasted elements are never initialized.  */
-
-  yyssp = yyss;
-  yyvsp = yyvs;
-
-  goto yysetstate;
-
-/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate.  |
-`------------------------------------------------------------*/
- yynewstate:
-  /* In all cases, when you get here, the value and location stacks
-     have just been pushed. so pushing a state here evens the stacks.
-     */
-  yyssp++;
-
- yysetstate:
-  *yyssp = yystate;
-
-  if (yyss + yystacksize - 1 <= yyssp)
-    {
-      /* Get the current used size of the three stacks, in elements.  */
-      YYSIZE_T yysize = yyssp - yyss + 1;
-
-#ifdef yyoverflow
-      {
-	/* Give user a chance to reallocate the stack. Use copies of
-	   these so that the &'s don't force the real ones into
-	   memory.  */
-	YYSTYPE *yyvs1 = yyvs;
-	short int *yyss1 = yyss;
-
-
-	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  This used to be a
-	   conditional around just the two extra args, but that might
-	   be undefined if yyoverflow is a macro.  */
-	yyoverflow (YY_("memory exhausted"),
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-
-		    &yystacksize);
-
-	yyss = yyss1;
-	yyvs = yyvs1;
-      }
-#else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
-      goto yyexhaustedlab;
-# else
-      /* Extend the stack our own way.  */
-      if (YYMAXDEPTH <= yystacksize)
-	goto yyexhaustedlab;
-      yystacksize *= 2;
-      if (YYMAXDEPTH < yystacksize)
-	yystacksize = YYMAXDEPTH;
-
-      {
-	short int *yyss1 = yyss;
-	union yyalloc *yyptr =
-	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-	if (! yyptr)
-	  goto yyexhaustedlab;
-	YYSTACK_RELOCATE (yyss);
-	YYSTACK_RELOCATE (yyvs);
-
-#  undef YYSTACK_RELOCATE
-	if (yyss1 != yyssa)
-	  YYSTACK_FREE (yyss1);
-      }
-# endif
-#endif /* no yyoverflow */
-
-      yyssp = yyss + yysize - 1;
-      yyvsp = yyvs + yysize - 1;
-
-
-      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-		  (unsigned long int) yystacksize));
-
-      if (yyss + yystacksize - 1 <= yyssp)
-	YYABORT;
-    }
-
-  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
-
-  goto yybackup;
-
-/*-----------.
-| yybackup.  |
-`-----------*/
-yybackup:
-
-/* Do appropriate processing given the current state.  */
-/* Read a look-ahead token if we need one and don't already have one.  */
-/* yyresume: */
-
-  /* First try to decide what to do without reference to look-ahead token.  */
-
-  yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
-    goto yydefault;
-
-  /* Not known => get a look-ahead token if don't already have one.  */
-
-  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
-  if (yychar == YYEMPTY)
-    {
-      YYDPRINTF ((stderr, "Reading a token: "));
-      yychar = YYLEX;
-    }
-
-  if (yychar <= YYEOF)
-    {
-      yychar = yytoken = YYEOF;
-      YYDPRINTF ((stderr, "Now at end of input.\n"));
-    }
-  else
-    {
-      yytoken = YYTRANSLATE (yychar);
-      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
-    }
-
-  /* If the proper action on seeing token YYTOKEN is to reduce or to
-     detect an error, take that action.  */
-  yyn += yytoken;
-  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
-    goto yydefault;
-  yyn = yytable[yyn];
-  if (yyn <= 0)
-    {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-	goto yyerrlab;
-      yyn = -yyn;
-      goto yyreduce;
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  /* Shift the look-ahead token.  */
-  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
-
-  /* Discard the token being shifted unless it is eof.  */
-  if (yychar != YYEOF)
-    yychar = YYEMPTY;
-
-  *++yyvsp = yylval;
-
-
-  /* Count tokens shifted since error; after three, turn off error
-     status.  */
-  if (yyerrstatus)
-    yyerrstatus--;
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-----------------------------------------------------------.
-| yydefault -- do the default action for the current state.  |
-`-----------------------------------------------------------*/
-yydefault:
-  yyn = yydefact[yystate];
-  if (yyn == 0)
-    goto yyerrlab;
-  goto yyreduce;
-
-
-/*-----------------------------.
-| yyreduce -- Do a reduction.  |
-`-----------------------------*/
-yyreduce:
-  /* yyn is the number of a rule to reduce with.  */
-  yylen = yyr2[yyn];
-
-  /* If YYLEN is nonzero, implement the default value of the action:
-     `$$ = $1'.
-
-     Otherwise, the following line sets YYVAL to garbage.
-     This behavior is undocumented and Bison
-     users should not rely upon it.  Assigning to YYVAL
-     unconditionally makes the parser a bit smaller, and it avoids a
-     GCC warning that YYVAL may be used uninitialized.  */
-  yyval = yyvsp[1-yylen];
-
-
-  YY_REDUCE_PRINT (yyn);
-  switch (yyn)
-    {
-        case 3:
-#line 569 "bfin-parse.y"
-    {
-	  insn = (yyvsp[0].instr);
-	  if (insn == (INSTR_T) 0)
-	    return NO_INSN_GENERATED;
-	  else if (insn == (INSTR_T) - 1)
-	    return SEMANTIC_ERROR;
-	  else
-	    return INSN_GENERATED;
-	}
-    break;
-
-  case 5:
-#line 583 "bfin-parse.y"
-    {
-	  if (((yyvsp[-5].instr)->value & 0xf800) == 0xc000)
-	    {
-	      if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-5].instr), (yyvsp[-3].instr), (yyvsp[-1].instr));
-	      else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-5].instr), (yyvsp[-1].instr), (yyvsp[-3].instr));
-	      else
-		return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
-	    }
-	  else if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
-	    {
-	      if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-5].instr), (yyvsp[-1].instr));
-	      else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-1].instr), (yyvsp[-5].instr));
-	      else
-		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
-	    }
-	  else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
-	    {
-	      if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-3].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-5].instr), (yyvsp[-3].instr));
-	      else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-3].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-3].instr), (yyvsp[-5].instr));
-	      else
-		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
-	    }
-	  else
-	    error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
-	}
-    break;
-
-  case 6:
-#line 616 "bfin-parse.y"
-    {
-	  if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
-	    {
-	      if (is_group1 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-1].instr), 0);
-	      else if (is_group2 ((yyvsp[-1].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), 0, (yyvsp[-1].instr));
-	      else
-		return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
-	    }
-	  else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
-	    {
-	      if (is_group1 ((yyvsp[-3].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-3].instr), 0);
-	      else if (is_group2 ((yyvsp[-3].instr)))
-		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), 0, (yyvsp[-3].instr));
-	      else
-		return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
-	    }
-	  else if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
-	      (yyval.instr) = bfin_gen_multi_instr (0, (yyvsp[-3].instr), (yyvsp[-1].instr));
-	  else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
-	    (yyval.instr) = bfin_gen_multi_instr (0, (yyvsp[-1].instr), (yyvsp[-3].instr));
-	  else
-	    return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
-	}
-    break;
-
-  case 7:
-#line 643 "bfin-parse.y"
-    {
-	(yyval.instr) = 0;
-	yyerror ("");
-	yyerrok;
-	}
-    break;
-
-  case 8:
-#line 654 "bfin-parse.y"
-    {
-	  (yyval.instr) = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
-	}
-    break;
-
-  case 9:
-#line 658 "bfin-parse.y"
-    {
-	  int op0, op1;
-	  int w0 = 0, w1 = 0;
-	  int h00, h10, h01, h11;
-
-	  if ((yyvsp[-1].macfunc).n == 0)
-	    {
-	      if ((yyvsp[0].mod).MM) 
-		return yyerror ("(m) not allowed with a0 unit");
-	      op1 = 3;
-	      op0 = (yyvsp[-1].macfunc).op;
-	      w1 = 0;
-              w0 = (yyvsp[-1].macfunc).w;
-	      h00 = IS_H ((yyvsp[-1].macfunc).s0);
-              h10 = IS_H ((yyvsp[-1].macfunc).s1);
-	      h01 = h11 = 0;
-	    }
-	  else
-	    {
-	      op1 = (yyvsp[-1].macfunc).op;
-	      op0 = 3;
-	      w1 = (yyvsp[-1].macfunc).w;
-              w0 = 0;
-	      h00 = h10 = 0;
-	      h01 = IS_H ((yyvsp[-1].macfunc).s0);
-              h11 = IS_H ((yyvsp[-1].macfunc).s1);
-	    }
-	  (yyval.instr) = DSP32MAC (op1, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, w1, (yyvsp[-1].macfunc).P, h01, h11, h00, h10,
-			 &(yyvsp[-1].macfunc).dst, op0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, w0);
-	}
-    break;
-
-  case 10:
-#line 693 "bfin-parse.y"
-    {
-	  Register *dst;
-
-	  if (check_macfuncs (&(yyvsp[-4].macfunc), &(yyvsp[-3].mod), &(yyvsp[-1].macfunc), &(yyvsp[0].mod)) < 0) 
-	    return -1;
-	  notethat ("assign_macfunc (.), assign_macfunc (.)\n");
-
-	  if ((yyvsp[-4].macfunc).w)
-	    dst = &(yyvsp[-4].macfunc).dst;
-	  else
-	    dst = &(yyvsp[-1].macfunc).dst;
-
-	  (yyval.instr) = DSP32MAC ((yyvsp[-4].macfunc).op, (yyvsp[-3].mod).MM, (yyvsp[0].mod).mod, (yyvsp[-4].macfunc).w, (yyvsp[-4].macfunc).P,
-			 IS_H ((yyvsp[-4].macfunc).s0),  IS_H ((yyvsp[-4].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
-			 dst, (yyvsp[-1].macfunc).op, &(yyvsp[-4].macfunc).s0, &(yyvsp[-4].macfunc).s1, (yyvsp[-1].macfunc).w);
-	}
-    break;
-
-  case 11:
-#line 713 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: DISALGNEXCPT\n");
-	  (yyval.instr) = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
-	}
-    break;
-
-  case 12:
-#line 718 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && !IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
-	      (yyval.instr) = DSP32ALU (11, 0, 0, &(yyvsp[-5].reg), 0, 0, 0, 0, 0);
-	    }
-	  else 
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 13:
-#line 728 "bfin-parse.y"
-    {
-	  if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
-	      (yyval.instr) = DSP32ALU (11, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), 0, 0, 0, 0, 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 14:
-#line 738 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
-	  (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
-	}
-    break;
-
-  case 15:
-#line 743 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
-	  (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
-	}
-    break;
-
-  case 16:
-#line 749 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG ((yyvsp[-13].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
-	      (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
-	    }
-	}
-    break;
-
-  case 17:
-#line 765 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG((yyvsp[-13].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
-	      (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 1);
-	    }
-	}
-    break;
-
-  case 18:
-#line 780 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
-	      (yyval.instr) = DSP32ALU (24, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, (yyvsp[0].r0).r0, 0, 1);
-	    }
-	}
-    break;
-
-  case 19:
-#line 792 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
-	      (yyval.instr) = DSP32ALU (13, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0, (yyvsp[-1].r0).r0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 20:
-#line 803 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-4].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
-	      (yyval.instr) = DSP32ALU (12, 0, &(yyvsp[-10].reg), &(yyvsp[-4].reg), 0, 0, 0, 0, 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 21:
-#line 815 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
-	      && IS_A1 ((yyvsp[-3].reg)) && !IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
-	      (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), 0, 0, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 0);
-	      
-	    }
-	  else if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
-		   && !IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
-	      (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), 0, 0, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 22:
-#line 834 "bfin-parse.y"
-    {
-	  if ((yyvsp[-8].r0).r0 == (yyvsp[-2].r0).r0) 
-	    return yyerror ("Operators must differ");
-
-	  if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg))
-	      && REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) && REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = dregs + dregs,"
-		       "dregs = dregs - dregs (amod1)\n");
-	      (yyval.instr) = DSP32ALU (4, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 2);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 23:
-#line 852 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) || !REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
-	    return yyerror ("Differing source registers");
-
-	  if (!IS_DREG ((yyvsp[-11].reg)) || !IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)) || !IS_DREG ((yyvsp[-5].reg))) 
-	    return yyerror ("Dregs expected");
-
-	
-	  if ((yyvsp[-8].r0).r0 == 1 && (yyvsp[-2].r0).r0 == 2)
-	    {
-	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
-	      (yyval.instr) = DSP32ALU (1, 1, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
-	    }
-	  else if ((yyvsp[-8].r0).r0 == 0 && (yyvsp[-2].r0).r0 == 3)
-	    {
-	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
-	      (yyval.instr) = DSP32ALU (1, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
-	    }
-	  else
-	    return yyerror ("Bar operand mismatch");
-	}
-    break;
-
-  case 24:
-#line 875 "bfin-parse.y"
-    {
-	  int op;
-
-	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      if ((yyvsp[0].r0).r0)
-		{
-		  notethat ("dsp32alu: dregs = ABS dregs (v)\n");
-		  op = 6;
-		}
-	      else
-		{
-		  /* Vector version of ABS.  */
-		  notethat ("dsp32alu: dregs = ABS dregs\n");
-		  op = 7;
-		}
-	      (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, 0, 0, 2);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 25:
-#line 897 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: Ax = ABS Ax\n");
-	  (yyval.instr) = DSP32ALU (16, IS_A1 ((yyvsp[-2].reg)), 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[0].reg)));
-	}
-    break;
-
-  case 26:
-#line 902 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32alu: A0.l = reg_half\n");
-	      (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
-	    }
-	  else
-	    return yyerror ("A0.l = Rx.l expected");
-	}
-    break;
-
-  case 27:
-#line 912 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32alu: A1.l = reg_half\n");
-	      (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
-	    }
-	  else
-	    return yyerror ("A1.l = Rx.l expected");
-	}
-    break;
-
-  case 28:
-#line 923 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
-	      (yyval.instr) = DSP32SHIFT (13, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[-5].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 29:
-#line 934 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-12].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
-	      (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, (yyvsp[0].modcodes).r0);
-	    }
-	}
-    break;
-
-  case 30:
-#line 948 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-11].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-7].reg), (yyvsp[-5].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
-	      (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-11].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0);
-	    }
-	}
-    break;
-
-  case 31:
-#line 964 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-12].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
-	      (yyval.instr) = DSP32ALU (22, (yyvsp[0].modcodes).r0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).aop);
-	    }
-	}
-    break;
-
-  case 32:
-#line 980 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-12].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
-	      (yyval.instr) = DSP32ALU (22, (yyvsp[0].modcodes).r0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, (yyvsp[0].modcodes).x0);
-	    }
-	}
-    break;
-
-  case 33:
-#line 996 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-12].reg)))
-	    return yyerror ("Dregs expected");
-	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
-	      (yyval.instr) = DSP32ALU (23, (yyvsp[0].modcodes).x0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, 0);
-	    }
-	}
-    break;
-
-  case 34:
-#line 1011 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
-	      (yyval.instr) = DSP32ALU (24, 0, 0, &(yyvsp[-7].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 0, 0, 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 35:
-#line 1023 "bfin-parse.y"
-    {
-	  if (IS_HCOMPL ((yyvsp[-16].reg), (yyvsp[-14].reg)) && IS_HCOMPL ((yyvsp[-10].reg), (yyvsp[-3].reg)) && IS_HCOMPL ((yyvsp[-7].reg), (yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32alu:	dregs_hi = dregs_lo ="
-		       "SIGN (dregs_hi) * dregs_hi + "
-		       "SIGN (dregs_lo) * dregs_lo \n");
-
-		(yyval.instr) = DSP32ALU (12, 0, 0, &(yyvsp[-16].reg), &(yyvsp[-10].reg), &(yyvsp[-7].reg), 0, 0, 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 36:
-#line 1036 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      if ((yyvsp[0].modcodes).aop == 0)
-		{
-	          /* No saturation flag specified, generate the 16 bit variant.  */
-		  notethat ("COMP3op: dregs = dregs +- dregs\n");
-		  (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[-2].r0).r0);
-		}
-	      else
-		{
-		 /* Saturation flag specified, generate the 32 bit variant.  */
-                 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
-                 (yyval.instr) = DSP32ALU (4, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
-		}
-	    }
-	  else
-	    if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)) && (yyvsp[-2].r0).r0 == 0)
-	      {
-		notethat ("COMP3op: pregs = pregs + pregs\n");
-		(yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 5);
-	      }
-	    else
-	      return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 37:
-#line 1062 "bfin-parse.y"
-    {
-	  int op;
-
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
-	    {
-	      if ((yyvsp[0].r0).r0)
-		op = 6;
-	      else
-		op = 7;
-
-	      notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
-	      (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), &(yyvsp[-2].reg), 0, 0, (yyvsp[-6].r0).r0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 38:
-#line 1080 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: Ax = - Ax\n");
-	  (yyval.instr) = DSP32ALU (14, IS_A1 ((yyvsp[-2].reg)), 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[0].reg)));
-	}
-    break;
-
-  case 39:
-#line 1085 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
-	  (yyval.instr) = DSP32ALU (2 | (yyvsp[-2].r0).r0, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg),
-			 (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)));
-	}
-    break;
-
-  case 40:
-#line 1091 "bfin-parse.y"
-    {
-	  if (EXPR_VALUE ((yyvsp[0].expr)) == 0 && !REG_SAME ((yyvsp[-2].reg), (yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: A1 = A0 = 0\n");
-	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
-	    }
-	  else
-	    return yyerror ("Bad value, 0 expected");
-	}
-    break;
-
-  case 41:
-#line 1103 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32alu: Ax = Ax (S)\n");
-	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ((yyvsp[-4].reg)));
-	    }
-	  else
-	    return yyerror ("Registers must be equal");
-	}
-    break;
-
-  case 42:
-#line 1114 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32alu: dregs_half = dregs (RND)\n");
-	      (yyval.instr) = DSP32ALU (12, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, 0, 3);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 43:
-#line 1125 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
-	      (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, (yyvsp[-4].r0).r0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 44:
-#line 1136 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
-	      (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1, (yyvsp[-4].r0).r0 | 2);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 45:
-#line 1147 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-1].reg), (yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32alu: An = Am\n");
-	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[-1].reg)), 0, 3);
-	    }
-	  else
-	    return yyerror ("Accu reg arguments must differ");
-	}
-    break;
-
-  case 46:
-#line 1158 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32alu: An = dregs\n");
-	      (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[0].reg), 0, 1, 0, IS_A1 ((yyvsp[-1].reg)) << 1);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 47:
-#line 1169 "bfin-parse.y"
-    {
-	  if (!IS_H ((yyvsp[-1].reg)))
-	    {
-	      if ((yyvsp[-3].reg).regno == REG_A0x && IS_DREG ((yyvsp[-1].reg)))
-		{
-		  notethat ("dsp32alu: A0.x = dregs_lo\n");
-		  (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 1);
-		}
-	      else if ((yyvsp[-3].reg).regno == REG_A1x && IS_DREG ((yyvsp[-1].reg)))
-		{
-		  notethat ("dsp32alu: A1.x = dregs_lo\n");
-		  (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 3);
-		}
-	      else if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-		{
-		  notethat ("ALU2op: dregs = dregs_lo\n");
-		  (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 10 | ((yyvsp[0].r0).r0 ? 0: 1));
-		}
-	      else
-	        return yyerror ("Register mismatch");
-	    }
-	  else
-	    return yyerror ("Low reg expected");
-	}
-    break;
-
-  case 48:
-#line 1195 "bfin-parse.y"
-    {
-	  notethat ("LDIMMhalf: pregs_half = imm16\n");
-
-	  if (!IS_DREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)) && !IS_IREG ((yyvsp[-2].reg))
-	      && !IS_MREG ((yyvsp[-2].reg)) && !IS_BREG ((yyvsp[-2].reg)) && !IS_LREG ((yyvsp[-2].reg)))
-	    return yyerror ("Wrong register for load immediate");
-
-	  if (!IS_IMM ((yyvsp[0].expr), 16) && !IS_UIMM ((yyvsp[0].expr), 16))
-	    return yyerror ("Constant out of range");
-
-	  (yyval.instr) = LDIMMHALF_R (&(yyvsp[-2].reg), IS_H ((yyvsp[-2].reg)), 0, 0, (yyvsp[0].expr));
-	}
-    break;
-
-  case 49:
-#line 1209 "bfin-parse.y"
-    {
-	  notethat ("dsp32alu: An = 0\n");
-
-	  if (imm7 ((yyvsp[0].expr)) != 0)
-	    return yyerror ("0 expected");
-
-	  (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[-1].reg)));
-	}
-    break;
-
-  case 50:
-#line 1219 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-3].reg)) && !IS_PREG ((yyvsp[-3].reg)) && !IS_IREG ((yyvsp[-3].reg))
-	      && !IS_MREG ((yyvsp[-3].reg)) && !IS_BREG ((yyvsp[-3].reg)) && !IS_LREG ((yyvsp[-3].reg)))
-	    return yyerror ("Wrong register for load immediate");
-
-	  if ((yyvsp[0].r0).r0 == 0)
-	    {
-	      /* 7 bit immediate value if possible.
-		 We will check for that constant value for efficiency
-		 If it goes to reloc, it will be 16 bit.  */
-	      if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_DREG ((yyvsp[-3].reg)))
-		{
-		  notethat ("COMPI2opD: dregs = imm7 (x) \n");
-		  (yyval.instr) = COMPI2OPD (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
-		}
-	      else if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_PREG ((yyvsp[-3].reg)))
-		{
-		  notethat ("COMPI2opP: pregs = imm7 (x)\n");
-		  (yyval.instr) = COMPI2OPP (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
-		}
-	      else
-		{
-		  if (IS_CONST ((yyvsp[-1].expr)) && !IS_IMM ((yyvsp[-1].expr), 16))
-		    return yyerror ("Immediate value out of range");
-
-		  notethat ("LDIMMhalf: regs = luimm16 (x)\n");
-		  /* reg, H, S, Z.   */
-		  (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 1, 0, (yyvsp[-1].expr));
-		} 
-	    }
-	  else
-	    {
-	      /* (z) There is no 7 bit zero extended instruction.
-	      If the expr is a relocation, generate it.   */
-
-	      if (IS_CONST ((yyvsp[-1].expr)) && !IS_UIMM ((yyvsp[-1].expr), 16))
-		return yyerror ("Immediate value out of range");
-
-	      notethat ("LDIMMhalf: regs = luimm16 (x)\n");
-	      /* reg, H, S, Z.  */
-	      (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 0, 1, (yyvsp[-1].expr));
-	    }
-	}
-    break;
-
-  case 51:
-#line 1264 "bfin-parse.y"
-    {
-	  if (IS_H ((yyvsp[-2].reg)))
-	    return yyerror ("Low reg expected");
-
-	  if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A0x)
-	    {
-	      notethat ("dsp32alu: dregs_lo = A0.x\n");
-	      (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), 0, 0, 0, 0, 0);
-	    }
-	  else if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A1x)
-	    {
-	      notethat ("dsp32alu: dregs_lo = A1.x\n");
-	      (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), 0, 0, 0, 0, 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 52:
-#line 1283 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
-	      (yyval.instr) = DSP32ALU (0, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 53:
-#line 1294 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ALU2op: dregs = dregs_byte\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 12 | ((yyvsp[0].r0).r0 ? 0: 1));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 54:
-#line 1305 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
-	      (yyval.instr) = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 55:
-#line 1316 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
-	      (yyval.instr) = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 56:
-#line 1327 "bfin-parse.y"
-    {
-	  if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: A0 -= A1\n");
-	      (yyval.instr) = DSP32ALU (11, 0, 0, 0, 0, 0, (yyvsp[0].r0).r0, 0, 3);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 57:
-#line 1338 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 4)
-	    {
-	      notethat ("dagMODik: iregs -= 4\n");
-	      (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 3);
-	    }
-	  else if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 2)
-	    {
-	      notethat ("dagMODik: iregs -= 2\n");
-	      (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 1);
-	    }
-	  else
-	    return yyerror ("Register or value mismatch");
-	}
-    break;
-
-  case 58:
-#line 1354 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dagMODim: iregs += mregs (opt_brev)\n");
-	      /* i, m, op, br.  */
-	      (yyval.instr) = DAGMODIM (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1);
-	    }
-	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("PTR2op: pregs += pregs (BREV )\n");
-	      (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 5);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 59:
-#line 1371 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dagMODim: iregs -= mregs\n");
-	      (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1, 0);
-	    }
-	  else if (IS_PREG ((yyvsp[-2].reg)) && IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("PTR2op: pregs -= pregs\n");
-	      (yyval.instr) = PTR2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 60:
-#line 1387 "bfin-parse.y"
-    {
-	  if (!IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32alu: A0 += A1 (W32)\n");
-	      (yyval.instr) = DSP32ALU (11, 0, 0, 0, 0, 0, (yyvsp[0].r0).r0, 0, 2);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 61:
-#line 1398 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dagMODim: iregs += mregs\n");
-	      (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0, 0);
-	    }
-	  else
-	    return yyerror ("iregs += mregs expected");
-	}
-    break;
-
-  case 62:
-#line 1409 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-2].reg)))
-	    {
-	      if (EXPR_VALUE ((yyvsp[0].expr)) == 4)
-		{
-		  notethat ("dagMODik: iregs += 4\n");
-		  (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 2);
-		}
-	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
-		{
-		  notethat ("dagMODik: iregs += 2\n");
-		  (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 0);
-		}
-	      else
-		return yyerror ("iregs += [ 2 | 4 ");
-	    }
-	  else if (IS_PREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
-	    {
-	      notethat ("COMPI2opP: pregs += imm7\n");
-	      (yyval.instr) = COMPI2OPP (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
-	    }
-	  else if (IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
-	    {
-	      notethat ("COMPI2opD: dregs += imm7\n");
-	      (yyval.instr) = COMPI2OPD (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 63:
-#line 1440 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ALU2op: dregs *= dregs\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 64:
-#line 1451 "bfin-parse.y"
-    {
-	  if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
-	    return yyerror ("Bad dreg pair");
-	  else
-	    {
-	      notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
-	      (yyval.instr) = DSP32ALU (18, 0, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
-	    }
-	}
-    break;
-
-  case 65:
-#line 1464 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-10].reg), (yyvsp[-9].reg)) && REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)) && !REG_SAME ((yyvsp[-10].reg), (yyvsp[-4].reg)))
-	    {
-	      notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
-	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 66:
-#line 1475 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg))
-	      && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
-	    {
-	      if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
-		{
-		  notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
-		  (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 4);
-		}
-	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
-		{
-		  notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
-		  (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 5);
-		}
-	      else
-		return yyerror ("Bad shift value");
-	    }
-	  else if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg))
-		   && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
-	    {
-	      if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
-		{
-		  notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
-		  (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 6);
-		}
-	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
-		{
-		  notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
-		  (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 7);
-		}
-	      else
-		return yyerror ("Bad shift value");
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 67:
-#line 1514 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("COMP3op: dregs = dregs | dregs\n");
-	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 68:
-#line 1524 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("COMP3op: dregs = dregs ^ dregs\n");
-	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 4);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 69:
-#line 1534 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
-		{
-		  notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
-		  (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 6);
-		}
-	      else if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
-		{
-		  notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
-		  (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 7);
-		}
-	      else
-		  return yyerror ("Bad shift value");
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 70:
-#line 1554 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
-	    {
-	      notethat ("CCflag: CC = A0 == A1\n");
-	      (yyval.instr) = CCFLAG (0, 0, 5, 0, 0);
-	    }
-	  else
-	    return yyerror ("CC register expected");
-	}
-    break;
-
-  case 71:
-#line 1564 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
-	    {
-	      notethat ("CCflag: CC = A0 < A1\n");
-	      (yyval.instr) = CCFLAG (0, 0, 6, 0, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 72:
-#line 1574 "bfin-parse.y"
-    {
-	  if (REG_CLASS((yyvsp[-3].reg)) == REG_CLASS((yyvsp[-1].reg)))
-	    {
-	      notethat ("CCflag: CC = dpregs < dpregs\n");
-	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
-	    }
-	  else
-	    return yyerror ("Compare only of same register class");
-	}
-    break;
-
-  case 73:
-#line 1584 "bfin-parse.y"
-    {
-	  if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
-	      || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
-	    {
-	      notethat ("CCflag: CC = dpregs < (u)imm3\n");
-	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), (yyvsp[0].r0).r0, 1, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
-	    }
-	  else
-	    return yyerror ("Bad constant value");
-	}
-    break;
-
-  case 74:
-#line 1595 "bfin-parse.y"
-    {
-	  if (REG_CLASS((yyvsp[-2].reg)) == REG_CLASS((yyvsp[0].reg)))
-	    {
-	      notethat ("CCflag: CC = dpregs == dpregs\n");
-	      (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), (yyvsp[0].reg).regno & CODE_MASK, 0, 0, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
-	    } 
-	}
-    break;
-
-  case 75:
-#line 1603 "bfin-parse.y"
-    {
-	  if (IS_IMM ((yyvsp[0].expr), 3))
-	    {
-	      notethat ("CCflag: CC = dpregs == imm3\n");
-	      (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), imm3 ((yyvsp[0].expr)), 0, 1, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
-	    }
-	  else
-	    return yyerror ("Bad constant range");
-	}
-    break;
-
-  case 76:
-#line 1613 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
-	    {
-	      notethat ("CCflag: CC = A0 <= A1\n");
-	      (yyval.instr) = CCFLAG (0, 0, 7, 0, 0);
-	    }
-	  else
-	    return yyerror ("CC register expected");
-	}
-    break;
-
-  case 77:
-#line 1623 "bfin-parse.y"
-    {
-	  if (REG_CLASS((yyvsp[-3].reg)) == REG_CLASS((yyvsp[-1].reg)))
-	    {
-	      notethat ("CCflag: CC = pregs <= pregs (..)\n");
-	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK,
-			   1 + (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
-	    }
-	  else
-	    return yyerror ("Compare only of same register class");
-	}
-    break;
-
-  case 78:
-#line 1634 "bfin-parse.y"
-    {
-	  if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
-	      || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
-	    {
-	      if (IS_DREG ((yyvsp[-3].reg)))
-		{
-		  notethat ("CCflag: CC = dregs <= (u)imm3\n");
-		  /*    x       y     opc     I     G   */
-		  (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), 1 + (yyvsp[0].r0).r0, 1, 0);
-		}
-	      else if (IS_PREG ((yyvsp[-3].reg)))
-		{
-		  notethat ("CCflag: CC = pregs <= (u)imm3\n");
-		  /*    x       y     opc     I     G   */
-		  (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), 1 + (yyvsp[0].r0).r0, 1, 1);
-		}
-	      else
-		return yyerror ("Dreg or Preg expected");
-	    }
-	  else
-	    return yyerror ("Bad constant value");
-	}
-    break;
-
-  case 79:
-#line 1658 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("COMP3op: dregs = dregs & dregs\n");
-	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 80:
-#line 1669 "bfin-parse.y"
-    {
-	  notethat ("CC2stat operation\n");
-	  (yyval.instr) = bfin_gen_cc2stat ((yyvsp[0].modcodes).r0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).s0);
-	}
-    break;
-
-  case 81:
-#line 1675 "bfin-parse.y"
-    {
-	  if (IS_ALLREG ((yyvsp[-2].reg)) && IS_ALLREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("REGMV: allregs = allregs\n");
-	      (yyval.instr) = bfin_gen_regmv (&(yyvsp[0].reg), &(yyvsp[-2].reg));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 82:
-#line 1686 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("CC2dreg: CC = dregs\n");
-	      (yyval.instr) = bfin_gen_cc2dreg (1, &(yyvsp[0].reg));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 83:
-#line 1697 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("CC2dreg: dregs = CC\n");
-	      (yyval.instr) = bfin_gen_cc2dreg (0, &(yyvsp[-2].reg));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 84:
-#line 1708 "bfin-parse.y"
-    {
-	  notethat ("CC2dreg: CC =! CC\n");
-	  (yyval.instr) = bfin_gen_cc2dreg (3, 0);
-	}
-    break;
-
-  case 85:
-#line 1716 "bfin-parse.y"
-    {
-	  notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
-
-	  if (!IS_H ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM)
-	    return yyerror ("(M) not allowed with MAC0");
-
-	  if (IS_H ((yyvsp[-3].reg)))
-	    {
-	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
-			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
-			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
-	    }
-	  else
-	    {
-	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 0,
-			      0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 
-			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
-		}	
-	}
-    break;
-
-  case 86:
-#line 1737 "bfin-parse.y"
-    {
-	  /* Odd registers can use (M).  */
-	  if (!IS_DREG ((yyvsp[-3].reg)))
-	    return yyerror ("Dreg expected");
-
-	  if (!IS_EVEN ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
-
-	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
-			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
-			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
-	    }
-	  else if ((yyvsp[0].mod).MM == 0)
-	    {
-	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
-	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 1,
-			      0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 
-			      &(yyvsp[-3].reg),  0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
-	    }
-	  else
-	    return yyerror ("Register or mode mismatch");
-	}
-    break;
-
-  case 87:
-#line 1763 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg))) 
-	    return yyerror ("Dregs expected");
-
-	  if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
-	    return -1;
-
-	  if (IS_H ((yyvsp[-8].reg)) && !IS_H ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
-		       "dregs_lo = multiply_halfregs opt_mode\n");
-	      (yyval.instr) = DSP32MULT (0, (yyvsp[-5].mod).MM, (yyvsp[0].mod).mod, 1, 0,
-			      IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
-			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
-	    }
-	  else if (!IS_H ((yyvsp[-8].reg)) && IS_H ((yyvsp[-3].reg)) && (yyvsp[-5].mod).MM == 0)
-	    {
-	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
-			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
-			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
-	    }
-	  else
-	    return yyerror ("Multfunc Register or mode mismatch");
-	}
-    break;
-
-  case 88:
-#line 1789 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg))) 
-	    return yyerror ("Dregs expected");
-
-	  if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
-	    return -1;
-
-	  notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
-		   "dregs = multiply_halfregs opt_mode\n");
-	  if (IS_EVEN ((yyvsp[-8].reg)))
-	    {
-	      if ((yyvsp[-3].reg).regno - (yyvsp[-8].reg).regno != 1 || (yyvsp[-5].mod).MM != 0)
-		return yyerror ("Dest registers or mode mismatch");
-
-	      /*   op1       MM      mmod  */
-	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 1, 1,
-			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
-			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
-	      
-	    }
-	  else
-	    {
-	      if ((yyvsp[-8].reg).regno - (yyvsp[-3].reg).regno != 1)
-		return yyerror ("Dest registers mismatch");
-	      
-	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
-			      IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
-			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
-	    }
-	}
-    break;
-
-  case 89:
-#line 1823 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)))
-	    return yyerror ("Aregs must be same");
-
-	  if (IS_DREG ((yyvsp[0].reg)) && !IS_H ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 0, IS_A1 ((yyvsp[-4].reg)));
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 90:
-#line 1837 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-6].reg), (yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 91:
-#line 1848 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
-	    return yyerror ("Aregs must be same");
-
-	  if (IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
-	      (yyval.instr) = DSP32SHIFTIMM (3, 0, imm5 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Bad shift value");
-	}
-    break;
-
-  case 92:
-#line 1862 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      if ((yyvsp[0].modcodes).r0)
-		{
-		  /*  Vector?  */
-		  notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
-		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), imm4 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
-		}
-	      else
-		{
-		  notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
-		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
-		}
-	    }
-	  else if ((yyvsp[0].modcodes).s0 == 0 && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
-		{
-		  notethat ("PTR2op: pregs = pregs << 2\n");
-		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 1);
-		}
-	      else if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
-		{
-		  notethat ("COMP3op: pregs = pregs << 1\n");
-		  (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-3].reg), 5);
-		}
-	      else
-		return yyerror ("Bad shift value");
-	    }
-	  else
-	    return yyerror ("Bad shift value or register");
-	}
-    break;
-
-  case 93:
-#line 1896 "bfin-parse.y"
-    {
-	  if (IS_UIMM ((yyvsp[0].expr), 4))
-	    {
-	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-	      (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-4].reg), imm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
-	    }
-	  else
-	    return yyerror ("Bad shift value");
-	}
-    break;
-
-  case 94:
-#line 1906 "bfin-parse.y"
-    {
-	  if (IS_UIMM ((yyvsp[-1].expr), 4))
-	    {
-	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
-	      (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Bad shift value");
-	}
-    break;
-
-  case 95:
-#line 1916 "bfin-parse.y"
-    {
-	  int op;
-
-	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
-	    {
-	      if ((yyvsp[0].modcodes).r0)
-		{
-		  op = 1;
-		  notethat ("dsp32shift: dregs = ASHIFT dregs BY "
-			   "dregs_lo (V, .)\n");
-		}
-	      else
-		{
-		  
-		  op = 2;
-		  notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
-		}
-	      (yyval.instr) = DSP32SHIFT (op, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 96:
-#line 1941 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-8].reg)) && IS_DREG_L ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
-	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Bad shift value or register");
-	}
-    break;
-
-  case 97:
-#line 1953 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
-	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
-	    }
-	  else if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_H ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
-	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 3, 0);
-	    }
-	  else
-	    return yyerror ("Bad shift value or register");
-	}
-    break;
-
-  case 98:
-#line 1971 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
-	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 99:
-#line 1982 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
-	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-10].reg), &(yyvsp[-4].reg), &(yyvsp[-6].reg), 3, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 100:
-#line 1993 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
-	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 101:
-#line 2004 "bfin-parse.y"
-    {
-	  if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
-	    return yyerror ("Aregs must be same");
-
-	  if (IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
-	      (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Shift value range error");
-	}
-    break;
-
-  case 102:
-#line 2017 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 1, IS_A1 ((yyvsp[-4].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 103:
-#line 2028 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-2].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 104:
-#line 2039 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
-	      (yyval.instr) = DSP32SHIFT ((yyvsp[0].r0).r0 ? 1: 2, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 105:
-#line 2050 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 106:
-#line 2061 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6) >= 0)
-	    {
-	      notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
-	      (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Accu register expected");
-	}
-    break;
-
-  case 107:
-#line 2072 "bfin-parse.y"
-    {
-	  if ((yyvsp[0].r0).r0 == 1)
-	    {
-	      if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-		{
-		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
-		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
-		}
-	      else
-	        return yyerror ("Register mismatch");
-	    }
-	  else
-	    {
-	      if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-		{
-		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
-		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
-		}
-	      else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 2)
-		{
-		  notethat ("PTR2op: pregs = pregs >> 2\n");
-		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 3);
-		}
-	      else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 1)
-		{
-		  notethat ("PTR2op: pregs = pregs >> 1\n");
-		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 4);
-		}
-	      else
-	        return yyerror ("Register mismatch");
-	    }
-	}
-    break;
-
-  case 108:
-#line 2105 "bfin-parse.y"
-    {
-	  if (IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
-	      (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-4].reg), -uimm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 109:
-#line 2115 "bfin-parse.y"
-    {
-	  if (IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
-	      (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg),
-				  (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
-	    }
-	  else
-	    return yyerror ("Register or modifier mismatch");
-	}
-    break;
-
-  case 110:
-#line 2128 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      if ((yyvsp[0].modcodes).r0)
-		{
-		  /* Vector?  */
-		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
-		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
-		}
-	      else
-		{
-		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
-		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
-		}
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 111:
-#line 2148 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = ONES dregs\n");
-	      (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 3, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 112:
-#line 2159 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
-	      (yyval.instr) = DSP32SHIFT (4, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 113:
-#line 2170 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-9].reg))
-	      && (yyvsp[-3].reg).regno == REG_A0
-	      && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
-	      (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 0, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 114:
-#line 2183 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-9].reg))
-	      && (yyvsp[-3].reg).regno == REG_A0
-	      && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
-	      (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 1, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 115:
-#line 2196 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-11].reg)) && !IS_H ((yyvsp[-11].reg)) && !REG_SAME ((yyvsp[-5].reg), (yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
-	      (yyval.instr) = DSP32SHIFT (12, &(yyvsp[-11].reg), 0, 0, 1, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 116:
-#line 2207 "bfin-parse.y"
-    {
-	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 2, IS_A1 ((yyvsp[-4].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 117:
-#line 2218 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 3, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 118:
-#line 2229 "bfin-parse.y"
-    {
-	  if (IS_IMM ((yyvsp[0].expr), 6))
-	    {
-	      notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
-	      (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 119:
-#line 2240 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6))
-	    {
-	      (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 120:
-#line 2250 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
-	      (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, 0, IS_A1 ((yyvsp[0].reg)), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 121:
-#line 2261 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
-	      (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 0, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 122:
-#line 2272 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
-	      (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 1 + IS_H ((yyvsp[0].reg)), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 123:
-#line 2284 "bfin-parse.y"
-    {
-	  if (IS_DREG_L ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
-	      (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-6].reg), 0, &(yyvsp[-2].reg), ((yyvsp[0].r0).r0 ? 0 : 1), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 124:
-#line 2295 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
-	      (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), 2 | ((yyvsp[0].r0).r0 ? 0 : 1), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 125:
-#line 2306 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)) && !IS_A1 ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
-	      (yyval.instr) = DSP32SHIFT (8, 0, &(yyvsp[-6].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 126:
-#line 2317 "bfin-parse.y"
-    {
-	  if (!IS_A1 ((yyvsp[-8].reg)) && !IS_A1 ((yyvsp[-5].reg)) && IS_A1 ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
-	      (yyval.instr) = DSP32SHIFT (12, 0, 0, 0, 0, 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 127:
-#line 2330 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 4);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 128:
-#line 2342 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 2);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 129:
-#line 2354 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 3);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 130:
-#line 2365 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch or value error");
-	}
-    break;
-
-  case 131:
-#line 2376 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
-	    {
-	      notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch or value error");
-	}
-    break;
-
-  case 132:
-#line 2387 "bfin-parse.y"
-    {
-	  if ((IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg)))
-	      && (IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg))))
-	    {
-	      notethat ("ccMV: IF ! CC gregs = gregs\n");
-	      (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 0);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 133:
-#line 2399 "bfin-parse.y"
-    {
-	  if ((IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg)))
-	      && (IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg))))
-	    {
-	      notethat ("ccMV: IF CC gregs = gregs\n");
-	      (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 134:
-#line 2411 "bfin-parse.y"
-    {
-	  if (IS_PCREL10 ((yyvsp[0].expr)))
-	    {
-	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
-	      (yyval.instr) = BRCC (0, 0, (yyvsp[0].expr));
-	    }
-	  else
-	    return yyerror ("Bad jump offset");
-	}
-    break;
-
-  case 135:
-#line 2422 "bfin-parse.y"
-    {
-	  if (IS_PCREL10 ((yyvsp[-3].expr)))
-	    {
-	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
-	      (yyval.instr) = BRCC (0, 1, (yyvsp[-3].expr));
-	    }
-	  else
-	    return yyerror ("Bad jump offset");
-	}
-    break;
-
-  case 136:
-#line 2433 "bfin-parse.y"
-    {
-	  if (IS_PCREL10 ((yyvsp[0].expr)))
-	    {
-	      notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
-	      (yyval.instr) = BRCC (1, 0, (yyvsp[0].expr));
-	    }
-	  else
-	    return yyerror ("Bad jump offset");
-	}
-    break;
-
-  case 137:
-#line 2444 "bfin-parse.y"
-    {
-	  if (IS_PCREL10 ((yyvsp[-3].expr)))
-	    {
-	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
-	      (yyval.instr) = BRCC (1, 1, (yyvsp[-3].expr));
-	    }
-	  else
-	    return yyerror ("Bad jump offset");
-	}
-    break;
-
-  case 138:
-#line 2454 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: NOP\n");
-	  (yyval.instr) = PROGCTRL (0, 0);
-	}
-    break;
-
-  case 139:
-#line 2460 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: RTS\n");
-	  (yyval.instr) = PROGCTRL (1, 0);
-	}
-    break;
-
-  case 140:
-#line 2466 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: RTI\n");
-	  (yyval.instr) = PROGCTRL (1, 1);
-	}
-    break;
-
-  case 141:
-#line 2472 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: RTX\n");
-	  (yyval.instr) = PROGCTRL (1, 2);
-	}
-    break;
-
-  case 142:
-#line 2478 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: RTN\n");
-	  (yyval.instr) = PROGCTRL (1, 3);
-	}
-    break;
-
-  case 143:
-#line 2484 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: RTE\n");
-	  (yyval.instr) = PROGCTRL (1, 4);
-	}
-    break;
-
-  case 144:
-#line 2490 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: IDLE\n");
-	  (yyval.instr) = PROGCTRL (2, 0);
-	}
-    break;
-
-  case 145:
-#line 2496 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: CSYNC\n");
-	  (yyval.instr) = PROGCTRL (2, 3);
-	}
-    break;
-
-  case 146:
-#line 2502 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: SSYNC\n");
-	  (yyval.instr) = PROGCTRL (2, 4);
-	}
-    break;
-
-  case 147:
-#line 2508 "bfin-parse.y"
-    {
-	  notethat ("ProgCtrl: EMUEXCPT\n");
-	  (yyval.instr) = PROGCTRL (2, 5);
-	}
-    break;
-
-  case 148:
-#line 2514 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ProgCtrl: CLI dregs\n");
-	      (yyval.instr) = PROGCTRL (3, (yyvsp[0].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Dreg expected for CLI");
-	}
-    break;
-
-  case 149:
-#line 2525 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ProgCtrl: STI dregs\n");
-	      (yyval.instr) = PROGCTRL (4, (yyvsp[0].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Dreg expected for STI");
-	}
-    break;
-
-  case 150:
-#line 2536 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ProgCtrl: JUMP (pregs )\n");
-	      (yyval.instr) = PROGCTRL (5, (yyvsp[-1].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Bad register for indirect jump");
-	}
-    break;
-
-  case 151:
-#line 2547 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ProgCtrl: CALL (pregs )\n");
-	      (yyval.instr) = PROGCTRL (6, (yyvsp[-1].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Bad register for indirect call");
-	}
-    break;
-
-  case 152:
-#line 2558 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ProgCtrl: CALL (PC + pregs )\n");
-	      (yyval.instr) = PROGCTRL (7, (yyvsp[-1].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Bad register for indirect call");
-	}
-    break;
-
-  case 153:
-#line 2569 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ProgCtrl: JUMP (PC + pregs )\n");
-	      (yyval.instr) = PROGCTRL (8, (yyvsp[-1].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Bad register for indirect jump");
-	}
-    break;
-
-  case 154:
-#line 2580 "bfin-parse.y"
-    {
-	  if (IS_UIMM ((yyvsp[0].expr), 4))
-	    {
-	      notethat ("ProgCtrl: RAISE uimm4\n");
-	      (yyval.instr) = PROGCTRL (9, uimm4 ((yyvsp[0].expr)));
-	    }
-	  else
-	    return yyerror ("Bad value for RAISE");
-	}
-    break;
-
-  case 155:
-#line 2591 "bfin-parse.y"
-    {
-		notethat ("ProgCtrl: EMUEXCPT\n");
-		(yyval.instr) = PROGCTRL (10, uimm4 ((yyvsp[0].expr)));
-	}
-    break;
-
-  case 156:
-#line 2597 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("ProgCtrl: TESTSET (pregs )\n");
-	      (yyval.instr) = PROGCTRL (11, (yyvsp[-1].reg).regno & CODE_MASK);
-	    }
-	  else
-	    return yyerror ("Preg expected");
-	}
-    break;
-
-  case 157:
-#line 2608 "bfin-parse.y"
-    {
-	  if (IS_PCREL12 ((yyvsp[0].expr)))
-	    {
-	      notethat ("UJUMP: JUMP pcrel12\n");
-	      (yyval.instr) = UJUMP ((yyvsp[0].expr));
-	    }
-	  else
-	    return yyerror ("Bad value for relative jump");
-	}
-    break;
-
-  case 158:
-#line 2619 "bfin-parse.y"
-    {
-	  if (IS_PCREL12 ((yyvsp[0].expr)))
-	    {
-	      notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
-	      (yyval.instr) = UJUMP((yyvsp[0].expr));
-	    }
-	  else
-	    return yyerror ("Bad value for relative jump");
-	}
-    break;
-
-  case 159:
-#line 2630 "bfin-parse.y"
-    {
-	  if (IS_PCREL24 ((yyvsp[0].expr)))
-	    {
-	      notethat ("CALLa: jump.l pcrel24\n");
-	      (yyval.instr) = CALLA ((yyvsp[0].expr), 0);
-	    }
-	  else
-	    return yyerror ("Bad value for long jump");
-	}
-    break;
-
-  case 160:
-#line 2641 "bfin-parse.y"
-    {
-	  if (IS_PCREL24 ((yyvsp[0].expr)))
-	    {
-	      notethat ("CALLa: jump.l pcrel24\n");
-	      (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
-	    }
-	  else
-	    return yyerror ("Bad value for long jump");
-	}
-    break;
-
-  case 161:
-#line 2652 "bfin-parse.y"
-    {
-	  if (IS_PCREL24 ((yyvsp[0].expr)))
-	    {
-	      notethat ("CALLa: CALL pcrel25m2\n");
-	      (yyval.instr) = CALLA ((yyvsp[0].expr), 1);
-	    }
-	  else
-	    return yyerror ("Bad call address");
-	}
-    break;
-
-  case 162:
-#line 2662 "bfin-parse.y"
-    {
-	  if (IS_PCREL24 ((yyvsp[0].expr)))
-	    {
-	      notethat ("CALLa: CALL pcrel25m2\n");
-	      (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
-	    }
-	  else
-	    return yyerror ("Bad call address");
-	}
-    break;
-
-  case 163:
-#line 2675 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 8);
-	  else
-	    return yyerror ("Bad registers for DIVQ");
-	}
-    break;
-
-  case 164:
-#line 2683 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 9);
-	  else
-	    return yyerror ("Bad registers for DIVS");
-	}
-    break;
-
-  case 165:
-#line 2691 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
-	    {
-	      if ((yyvsp[0].modcodes).r0 == 0 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 0)
-		{
-		  notethat ("ALU2op: dregs = - dregs\n");
-		  (yyval.instr) = ALU2OP (&(yyvsp[-4].reg), &(yyvsp[-1].reg), 14);
-		}
-	      else if ((yyvsp[0].modcodes).r0 == 1 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 3)
-		{
-		  notethat ("dsp32alu: dregs = - dregs (.)\n");
-		  (yyval.instr) = DSP32ALU (15, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
-		}
-	      else
-		{
-		  notethat ("dsp32alu: dregs = - dregs (.)\n");
-		  (yyval.instr) = DSP32ALU (7, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
-		}
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 166:
-#line 2715 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ALU2op: dregs = ~dregs\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[0].reg), 15);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 167:
-#line 2726 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ALU2op: dregs >>= dregs\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 168:
-#line 2737 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("LOGI2op: dregs >>= uimm5\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 6);
-	    }
-	  else
-	    return yyerror ("Dregs expected or value error");
-	}
-    break;
-
-  case 169:
-#line 2748 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ALU2op: dregs >>>= dregs\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 170:
-#line 2759 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("ALU2op: dregs <<= dregs\n");
-	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 171:
-#line 2770 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("LOGI2op: dregs <<= uimm5\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 7);
-	    }
-	  else
-	    return yyerror ("Dregs expected or const value error");
-	}
-    break;
-
-  case 172:
-#line 2782 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
-	    {
-	      notethat ("LOGI2op: dregs >>>= uimm5\n");
-	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 5);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 173:
-#line 2795 "bfin-parse.y"
-    {
-	  notethat ("CaCTRL: FLUSH [ pregs ]\n");
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 2);
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 174:
-#line 2804 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 2);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 175:
-#line 2815 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 1);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 176:
-#line 2826 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 1);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 177:
-#line 2838 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("CaCTRL: IFLUSH [ pregs ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 3);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 178:
-#line 2849 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 3);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for FLUSH");
-	}
-    break;
-
-  case 179:
-#line 2860 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("CaCTRL: PREFETCH [ pregs ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 0);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for PREFETCH");
-	}
-    break;
-
-  case 180:
-#line 2871 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
-	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 0);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for PREFETCH");
-	}
-    break;
-
-  case 181:
-#line 2885 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
-	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 2, 0, 1);
-	    }
-	  else
-	    return yyerror ("Register mismatch");
-	}
-    break;
-
-  case 182:
-#line 2897 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-5].reg)) && IS_RANGE(16, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 1) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
-	      if ((yyvsp[-4].r0).r0)
-		neg_value ((yyvsp[-3].expr));
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 2, 0, (yyvsp[-3].expr));
-	    }
-	  else
-	    return yyerror ("Register mismatch or const size wrong");
-	}
-    break;
-
-  case 183:
-#line 2912 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-5].reg)) && IS_URANGE (4, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 2) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
-	      (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), (yyvsp[-3].expr), 1, 1);
-	    }
-	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_RANGE(16, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 2) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
-	      if ((yyvsp[-4].r0).r0)
-		neg_value ((yyvsp[-3].expr));
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 1, 0, (yyvsp[-3].expr));
-	    }
-	  else
-	    return yyerror ("Bad register(s) or wrong constant size");
-	}
-    break;
-
-  case 184:
-#line 2931 "bfin-parse.y"
-    {
-	  if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
-	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1, 0, 1);
-	    }
-	  else
-	    return yyerror ("Bad register(s) for STORE");
-	}
-    break;
-
-  case 185:
-#line 2942 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-4].reg)))
-	    {
-	      notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
-	      (yyval.instr) = DSPLDST (&(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
-	    }
-	  else if ((yyvsp[-3].modcodes).x0 == 2 && IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[0].reg), &(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
-	      
-	    }
-	  else
-	    return yyerror ("Bad register(s) for STORE");
-	}
-    break;
-
-  case 186:
-#line 2960 "bfin-parse.y"
-    {
-	  Expr_Node *tmp = (yyvsp[-3].expr);
-	  int ispreg = IS_PREG ((yyvsp[0].reg));
-
-	  if (!IS_PREG ((yyvsp[-5].reg)))
-	    return yyerror ("Preg expected for indirect");
-
-	  if (!IS_DREG ((yyvsp[0].reg)) && !ispreg)
-	    return yyerror ("Bad source register for STORE");
-
-	  if ((yyvsp[-4].r0).r0)
-	    tmp = unary (Expr_Op_Type_NEG, tmp);
-
-	  if (in_range_p (tmp, 0, 63, 3))
-	    {
-	      notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
-	      (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), tmp, 1, ispreg ? 3 : 0);
-	    }
-	  else if ((yyvsp[-5].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
-	    {
-	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
-	      tmp = unary (Expr_Op_Type_NEG, tmp);
-	      (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[0].reg), 1);
-	    }
-	  else if (in_range_p (tmp, -131072, 131071, 3))
-	    {
-	      notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 0, ispreg ? 1: 0, tmp);
-	    }
-	  else
-	    return yyerror ("Displacement out of range for store");
-	}
-    break;
-
-  case 187:
-#line 2994 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_URANGE (4, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 2))
-	    {
-	      notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
-	      (yyval.instr) = LDSTII (&(yyvsp[-4].reg), &(yyvsp[-8].reg), (yyvsp[-2].expr), 0, 1 << (yyvsp[0].r0).r0);
-	    }
-	  else if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_RANGE(16, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 2))
-	    {
-	      notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
-	      if ((yyvsp[-3].r0).r0)
-		neg_value ((yyvsp[-2].expr));
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 1, (yyvsp[0].r0).r0, (yyvsp[-2].expr));
-	    }
-	  else
-	    return yyerror ("Bad register or constant for LOAD");
-	}
-    break;
-
-  case 188:
-#line 3012 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dspLDST: dregs_half = W [ iregs ]\n");
-	      (yyval.instr) = DSPLDST(&(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), &(yyvsp[-6].reg), (yyvsp[-1].modcodes).x0, 0);
-	    }
-	  else if ((yyvsp[-1].modcodes).x0 == 2 && IS_DREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-2].reg), &(yyvsp[-6].reg), &(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), 0);
-	    }
-	  else
-	    return yyerror ("Bad register or post_op for LOAD");
-	}
-    break;
-
-  case 189:
-#line 3029 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
-	      (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 1, (yyvsp[0].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Bad register for LOAD");
-	}
-    break;
-
-  case 190:
-#line 3040 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_PREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[-8].reg), &(yyvsp[-2].reg), 3, (yyvsp[0].r0).r0);
-	    }
-	  else
-	    return yyerror ("Bad register for LOAD");
-	}
-    break;
-
-  case 191:
-#line 3051 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-7].reg), &(yyvsp[-1].reg), 1 + IS_H ((yyvsp[-7].reg)), 0);
-	    }
-	  else
-	    return yyerror ("Bad register for LOAD");
-	}
-    break;
-
-  case 192:
-#line 3062 "bfin-parse.y"
-    {
-	  if (IS_IREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
-	      (yyval.instr) = DSPLDST(&(yyvsp[-4].reg), 0, &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
-	    }
-	  else if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDST: [ pregs <post_op> ] = dregs\n");
-	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 0, 1);
-	    }
-	  else if (IS_PREG ((yyvsp[-4].reg)) && IS_PREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LDST: [ pregs <post_op> ] = pregs\n");
-	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 1, 1);
-	    }
-	  else
-	    return yyerror ("Bad register for STORE");
-	}
-    break;
-
-  case 193:
-#line 3083 "bfin-parse.y"
-    {
-	  if (! IS_DREG ((yyvsp[0].reg)))
-	    return yyerror ("Expected Dreg for last argument");
-
-	  if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
-	      (yyval.instr) = DSPLDST(&(yyvsp[-5].reg), (yyvsp[-3].reg).regno & CODE_MASK, &(yyvsp[0].reg), 3, 1);
-	    }
-	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 0, 1);
-	    }
-	  else
-	    return yyerror ("Bad register for STORE");
-	}
-    break;
-
-  case 194:
-#line 3102 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[0].reg)))
-	    return yyerror ("Expect Dreg as last argument");
-	  if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
-	    }
-	  else
-	    return yyerror ("Bad register for STORE");
-	}
-    break;
-
-  case 195:
-#line 3115 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_RANGE(16, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 1))
-	    {
-	      notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
-		       (yyvsp[0].r0).r0 ? 'X' : 'Z');
-	      if ((yyvsp[-3].r0).r0)
-		neg_value ((yyvsp[-2].expr));
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 2, (yyvsp[0].r0).r0, (yyvsp[-2].expr));
-	    }
-	  else
-	    return yyerror ("Bad register or value for LOAD");
-	}
-    break;
-
-  case 196:
-#line 3129 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)))
-	    {
-	      notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
-		       (yyvsp[0].r0).r0 ? 'X' : 'Z');
-	      (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 2, (yyvsp[0].r0).r0, 0);
-	    }
-	  else
-	    return yyerror ("Bad register for LOAD");
-	}
-    break;
-
-  case 197:
-#line 3141 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-6].reg)) && IS_IREG ((yyvsp[-3].reg)) && IS_MREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
-	      (yyval.instr) = DSPLDST(&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, &(yyvsp[-6].reg), 3, 0);
-	    }
-	  else if (IS_DREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)))
-	    {
-	      notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
-	      (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-6].reg), &(yyvsp[-1].reg), 0, 0);
-	    }
-	  else
-	    return yyerror ("Bad register for LOAD");
-	}
-    break;
-
-  case 198:
-#line 3157 "bfin-parse.y"
-    {
-	  Expr_Node *tmp = (yyvsp[-1].expr);
-	  int ispreg = IS_PREG ((yyvsp[-6].reg));
-	  int isgot = IS_RELOC((yyvsp[-1].expr));
-
-	  if (!IS_PREG ((yyvsp[-3].reg)))
-	    return yyerror ("Preg expected for indirect");
-
-	  if (!IS_DREG ((yyvsp[-6].reg)) && !ispreg)
-	    return yyerror ("Bad destination register for LOAD");
-
-	  if ((yyvsp[-2].r0).r0)
-	    tmp = unary (Expr_Op_Type_NEG, tmp);
-
-	  if(isgot){
-	      notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1: 0, tmp);
-	  }
-	  else if (in_range_p (tmp, 0, 63, 3))
-	    {
-	      notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
-	      (yyval.instr) = LDSTII (&(yyvsp[-3].reg), &(yyvsp[-6].reg), tmp, 0, ispreg ? 3 : 0);
-	    }
-	  else if ((yyvsp[-3].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
-	    {
-	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
-	      tmp = unary (Expr_Op_Type_NEG, tmp);
-	      (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[-6].reg), 0);
-	    }
-	  else if (in_range_p (tmp, -131072, 131071, 3))
-	    {
-	      notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
-	      (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1: 0, tmp);
-	      
-	    }
-	  else
-	    return yyerror ("Displacement out of range for load");
-	}
-    break;
-
-  case 199:
-#line 3197 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-5].reg)) && IS_IREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
-	      (yyval.instr) = DSPLDST (&(yyvsp[-2].reg), 0, &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0);
-	    }
-	  else if (IS_DREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("LDST: dregs = [ pregs <post_op> ]\n");
-	      (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 0, 0);
-	    }
-	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-2].reg)))
-	    {
-	      if (REG_SAME ((yyvsp[-5].reg), (yyvsp[-2].reg)) && (yyvsp[-1].modcodes).x0 != 2)
-		return yyerror ("Pregs can't be same");
-
-	      notethat ("LDST: pregs = [ pregs <post_op> ]\n");
-	      (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 1, 0);
-	    }
-	  else if ((yyvsp[-2].reg).regno == REG_SP && IS_ALLREG ((yyvsp[-5].reg)) && (yyvsp[-1].modcodes).x0 == 0)
-	    {
-	      notethat ("PushPopReg: allregs = [ SP ++ ]\n");
-	      (yyval.instr) = PUSHPOPREG (&(yyvsp[-5].reg), 0);
-	    }
-	  else
-	    return yyerror ("Bad register or value");
-	}
-    break;
-
-  case 200:
-#line 3230 "bfin-parse.y"
-    {
-	  bfin_equals ((yyvsp[-2].expr));
-	  (yyval.instr) = 0;
-	}
-    break;
-
-  case 201:
-#line 3238 "bfin-parse.y"
-    {
-	  if ((yyvsp[-10].reg).regno != REG_SP)
-	    yyerror ("Stack Pointer expected");
-	  if ((yyvsp[-7].reg).regno == REG_R7
-	      && IN_RANGE ((yyvsp[-5].expr), 0, 7)
-	      && (yyvsp[-3].reg).regno == REG_P5
-	      && IN_RANGE ((yyvsp[-1].expr), 0, 5))
-	    {
-	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-5].expr)), imm5 ((yyvsp[-1].expr)), 1, 1, 1);
-	    }
-	  else
-	    return yyerror ("Bad register for PushPopMultiple");
-	}
-    break;
-
-  case 202:
-#line 3254 "bfin-parse.y"
-    {
-	  if ((yyvsp[-6].reg).regno != REG_SP)
-	    yyerror ("Stack Pointer expected");
-
-	  if ((yyvsp[-3].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-1].expr), 0, 7))
-	    {
-	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-1].expr)), 0, 1, 0, 1);
-	    }
-	  else if ((yyvsp[-3].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-1].expr), 0, 6))
-	    {
-	      notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-1].expr)), 0, 1, 1);
-	    }
-	  else
-	    return yyerror ("Bad register for PushPopMultiple");
-	}
-    break;
-
-  case 203:
-#line 3273 "bfin-parse.y"
-    {
-	  if ((yyvsp[0].reg).regno != REG_SP)
-	    yyerror ("Stack Pointer expected");
-	  if ((yyvsp[-9].reg).regno == REG_R7 && (IN_RANGE ((yyvsp[-7].expr), 0, 7))
-	      && (yyvsp[-5].reg).regno == REG_P5 && (IN_RANGE ((yyvsp[-3].expr), 0, 6)))
-	    {
-	      notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-7].expr)), imm5 ((yyvsp[-3].expr)), 1, 1, 0);
-	    }
-	  else
-	    return yyerror ("Bad register range for PushPopMultiple");
-	}
-    break;
-
-  case 204:
-#line 3287 "bfin-parse.y"
-    {
-	  if ((yyvsp[0].reg).regno != REG_SP)
-	    yyerror ("Stack Pointer expected");
-
-	  if ((yyvsp[-5].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-3].expr), 0, 7))
-	    {
-	      notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-3].expr)), 0, 1, 0, 0);
-	    }
-	  else if ((yyvsp[-5].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-3].expr), 0, 6))
-	    {
-	      notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
-	      (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-3].expr)), 0, 1, 0);
-	    }
-	  else
-	    return yyerror ("Bad register range for PushPopMultiple");
-	}
-    break;
-
-  case 205:
-#line 3306 "bfin-parse.y"
-    {
-	  if ((yyvsp[-2].reg).regno != REG_SP)
-	    yyerror ("Stack Pointer expected");
-
-	  if (IS_ALLREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("PushPopReg: [ -- SP ] = allregs\n");
-	      (yyval.instr) = PUSHPOPREG (&(yyvsp[0].reg), 1);
-	    }
-	  else
-	    return yyerror ("Bad register for PushPopReg");
-	}
-    break;
-
-  case 206:
-#line 3322 "bfin-parse.y"
-    {
-	  if (IS_URANGE (16, (yyvsp[0].expr), 0, 4))
-	    (yyval.instr) = LINKAGE (0, uimm16s4 ((yyvsp[0].expr)));
-	  else
-	    return yyerror ("Bad constant for LINK");
-	}
-    break;
-
-  case 207:
-#line 3330 "bfin-parse.y"
-    {
-		notethat ("linkage: UNLINK\n");
-		(yyval.instr) = LINKAGE (1, 0);
-	}
-    break;
-
-  case 208:
-#line 3339 "bfin-parse.y"
-    {
-	  if (IS_PCREL4 ((yyvsp[-4].expr)) && IS_LPPCREL10 ((yyvsp[-2].expr)) && IS_CREG ((yyvsp[0].reg)))
-	    {
-	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
-	      (yyval.instr) = LOOPSETUP ((yyvsp[-4].expr), &(yyvsp[0].reg), 0, (yyvsp[-2].expr), 0);
-	    }
-	  else
-	    return yyerror ("Bad register or values for LSETUP");
-	  
-	}
-    break;
-
-  case 209:
-#line 3350 "bfin-parse.y"
-    {
-	  if (IS_PCREL4 ((yyvsp[-6].expr)) && IS_LPPCREL10 ((yyvsp[-4].expr))
-	      && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
-	      (yyval.instr) = LOOPSETUP ((yyvsp[-6].expr), &(yyvsp[-2].reg), 1, (yyvsp[-4].expr), &(yyvsp[0].reg));
-	    }
-	  else
-	    return yyerror ("Bad register or values for LSETUP");
-	}
-    break;
-
-  case 210:
-#line 3362 "bfin-parse.y"
-    {
-	  if (IS_PCREL4 ((yyvsp[-8].expr)) && IS_LPPCREL10 ((yyvsp[-6].expr))
-	      && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg)) 
-	      && EXPR_VALUE ((yyvsp[0].expr)) == 1)
-	    {
-	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
-	      (yyval.instr) = LOOPSETUP ((yyvsp[-8].expr), &(yyvsp[-4].reg), 3, (yyvsp[-6].expr), &(yyvsp[-2].reg));
-	    }
-	  else
-	    return yyerror ("Bad register or values for LSETUP");
-	}
-    break;
-
-  case 211:
-#line 3376 "bfin-parse.y"
-    {
-	  if (!IS_RELOC ((yyvsp[-1].expr)))
-	    return yyerror ("Invalid expression in loop statement");
-	  if (!IS_CREG ((yyvsp[0].reg)))
-            return yyerror ("Invalid loop counter register");
-	(yyval.instr) = bfin_gen_loop ((yyvsp[-1].expr), &(yyvsp[0].reg), 0, 0);
-	}
-    break;
-
-  case 212:
-#line 3384 "bfin-parse.y"
-    {
-	  if (IS_RELOC ((yyvsp[-3].expr)) && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
-	    {
-	      notethat ("Loop: LOOP expr counters = pregs\n");
-	      (yyval.instr) = bfin_gen_loop ((yyvsp[-3].expr), &(yyvsp[-2].reg), 1, &(yyvsp[0].reg));
-	    }
-	  else
-	    return yyerror ("Bad register or values for LOOP");
-	}
-    break;
-
-  case 213:
-#line 3394 "bfin-parse.y"
-    {
-	  if (IS_RELOC ((yyvsp[-5].expr)) && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 1)
-	    {
-	      notethat ("Loop: LOOP expr counters = pregs >> 1\n");
-	      (yyval.instr) = bfin_gen_loop ((yyvsp[-5].expr), &(yyvsp[-4].reg), 3, &(yyvsp[-2].reg));
-	    }
-	  else
-	    return yyerror ("Bad register or values for LOOP");
-	}
-    break;
-
-  case 214:
-#line 3406 "bfin-parse.y"
-    {
-	  notethat ("pseudoDEBUG: DBG\n");
-	  (yyval.instr) = bfin_gen_pseudodbg (3, 7, 0);
-	}
-    break;
-
-  case 215:
-#line 3411 "bfin-parse.y"
-    {
-	  notethat ("pseudoDEBUG: DBG REG_A\n");
-	  (yyval.instr) = bfin_gen_pseudodbg (3, IS_A1 ((yyvsp[0].reg)), 0);
-	}
-    break;
-
-  case 216:
-#line 3416 "bfin-parse.y"
-    {
-	  notethat ("pseudoDEBUG: DBG allregs\n");
-	  (yyval.instr) = bfin_gen_pseudodbg (0, (yyvsp[0].reg).regno & CODE_MASK, (yyvsp[0].reg).regno & CLASS_MASK);
-	}
-    break;
-
-  case 217:
-#line 3422 "bfin-parse.y"
-    {
-	  if (!IS_DREG ((yyvsp[-1].reg)))
-	    return yyerror ("Dregs expected");
-	  notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
-	  (yyval.instr) = bfin_gen_pseudodbg (3, 6, (yyvsp[-1].reg).regno & CODE_MASK);
-	}
-    break;
-
-  case 218:
-#line 3430 "bfin-parse.y"
-    {
-	  notethat ("psedoDEBUG: DBGHALT\n");
-	  (yyval.instr) = bfin_gen_pseudodbg (3, 5, 0);
-	}
-    break;
-
-  case 219:
-#line 3436 "bfin-parse.y"
-    {
-	  notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
-	  (yyval.instr) = bfin_gen_pseudodbg_assert (IS_H ((yyvsp[-3].reg)), &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
-	}
-    break;
-
-  case 220:
-#line 3442 "bfin-parse.y"
-    {
-	  notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
-	  (yyval.instr) = bfin_gen_pseudodbg_assert (3, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
-	}
-    break;
-
-  case 221:
-#line 3448 "bfin-parse.y"
-    {
-	  notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
-	  (yyval.instr) = bfin_gen_pseudodbg_assert (2, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
-	}
-    break;
-
-  case 222:
-#line 3461 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[0].reg);
-	}
-    break;
-
-  case 223:
-#line 3465 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[0].reg);
-	}
-    break;
-
-  case 224:
-#line 3474 "bfin-parse.y"
-    {
-	(yyval.mod).MM = 0;
-	(yyval.mod).mod = 0;
-	}
-    break;
-
-  case 225:
-#line 3479 "bfin-parse.y"
-    {
-	(yyval.mod).MM = 1;
-	(yyval.mod).mod = (yyvsp[-1].value);
-	}
-    break;
-
-  case 226:
-#line 3484 "bfin-parse.y"
-    {
-	(yyval.mod).MM = 1;
-	(yyval.mod).mod = (yyvsp[-3].value);
-	}
-    break;
-
-  case 227:
-#line 3489 "bfin-parse.y"
-    {
-	(yyval.mod).MM = 0;
-	(yyval.mod).mod = (yyvsp[-1].value);
-	}
-    break;
-
-  case 228:
-#line 3494 "bfin-parse.y"
-    {
-	(yyval.mod).MM = 1;
-	(yyval.mod).mod = 0;
-	}
-    break;
-
-  case 229:
-#line 3501 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 230:
-#line 3505 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 231:
-#line 3511 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 232:
-#line 3516 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 1;
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 233:
-#line 3521 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 1;
-	}
-    break;
-
-  case 234:
-#line 3526 "bfin-parse.y"
-    {	
-	(yyval.modcodes).s0 = 1;
-	(yyval.modcodes).x0 = 1;
-	}
-    break;
-
-  case 235:
-#line 3534 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 236:
-#line 3538 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 237:
-#line 3544 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 238:
-#line 3549 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
-	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
-	}
-    break;
-
-  case 239:
-#line 3556 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	(yyval.modcodes).aop = 0;
-	}
-    break;
-
-  case 240:
-#line 3562 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	(yyval.modcodes).aop = 1;
-	}
-    break;
-
-  case 241:
-#line 3568 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 1;
-	(yyval.modcodes).x0 = 0;
-	(yyval.modcodes).aop = 1;
-	}
-    break;
-
-  case 242:
-#line 3576 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 243:
-#line 3582 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 244:
-#line 3588 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
-	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
-	}
-    break;
-
-  case 245:
-#line 3594 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 2 + (yyvsp[-3].r0).r0;
-	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
-	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
-	}
-    break;
-
-  case 246:
-#line 3600 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = (yyvsp[-3].modcodes).s0;
-	(yyval.modcodes).x0 = (yyvsp[-3].modcodes).x0;
-	}
-    break;
-
-  case 247:
-#line 3608 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 248:
-#line 3612 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 249:
-#line 3616 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 250:
-#line 3622 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 251:
-#line 3626 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 252:
-#line 3630 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 253:
-#line 3636 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).aop = 0;
-	}
-    break;
-
-  case 254:
-#line 3642 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).aop = 3;
-	}
-    break;
-
-  case 255:
-#line 3648 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = 1;
-	(yyval.modcodes).aop = 3;
-	}
-    break;
-
-  case 256:
-#line 3654 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 0;
-	(yyval.modcodes).aop = 3;
-	}
-    break;
-
-  case 257:
-#line 3660 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 258:
-#line 3665 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 259:
-#line 3672 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 260:
-#line 3676 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 261:
-#line 3682 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 0;
-	}
-    break;
-
-  case 262:
-#line 3686 "bfin-parse.y"
-    {
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 263:
-#line 3693 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 264:
-#line 3697 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 265:
-#line 3701 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 3;
-	}
-    break;
-
-  case 266:
-#line 3705 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 2;
-	}
-    break;
-
-  case 267:
-#line 3711 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 268:
-#line 3715 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 269:
-#line 3722 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 270:
-#line 3727 "bfin-parse.y"
-    {
-	if ((yyvsp[-1].value) != M_T)
-	  return yyerror ("Bad modifier");
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 0;
-	}
-    break;
-
-  case 271:
-#line 3734 "bfin-parse.y"
-    {
-	if ((yyvsp[-3].value) != M_T)
-	  return yyerror ("Bad modifier");
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 272:
-#line 3741 "bfin-parse.y"
-    {
-	if ((yyvsp[-1].value) != M_T)
-	  return yyerror ("Bad modifier");
-	(yyval.modcodes).r0 = 1;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 273:
-#line 3753 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 274:
-#line 3757 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 275:
-#line 3761 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 2;
-	}
-    break;
-
-  case 276:
-#line 3767 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 277:
-#line 3771 "bfin-parse.y"
-    {
-	  if ((yyvsp[-1].value) == M_W32)
-	    (yyval.r0).r0 = 1;
-	  else
-	    return yyerror ("Only (W32) allowed");
-	}
-    break;
-
-  case 278:
-#line 3780 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 279:
-#line 3784 "bfin-parse.y"
-    {
-	  if ((yyvsp[-1].value) == M_IU)
-	    (yyval.r0).r0 = 3;
-	  else
-	    return yyerror ("(IU) expected");
-	}
-    break;
-
-  case 280:
-#line 3793 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[-1].reg);
-	}
-    break;
-
-  case 281:
-#line 3799 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[-2].reg);
-	}
-    break;
-
-  case 282:
-#line 3808 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 283:
-#line 3812 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 284:
-#line 3819 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 285:
-#line 3823 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 286:
-#line 3827 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 2;
-	}
-    break;
-
-  case 287:
-#line 3831 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 3;
-	}
-    break;
-
-  case 288:
-#line 3838 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 289:
-#line 3842 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 290:
-#line 3849 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 1;	/* HL.  */
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 0;	/* aop.  */
-	}
-    break;
-
-  case 291:
-#line 3857 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 1;	/* HL.  */
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 1;	/* aop.  */
-	}
-    break;
-
-  case 292:
-#line 3865 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 0;	/* HL.  */
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 0;	/* aop.  */
-	}
-    break;
-
-  case 293:
-#line 3873 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 0;	/* HL.  */
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 1;
-	}
-    break;
-
-  case 294:
-#line 3881 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 1;	/* HL.  */
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 0;	/* aop.  */
-	}
-    break;
-
-  case 295:
-#line 3888 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 1;	/* HL.  */
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 1;	/* aop.  */
-	}
-    break;
-
-  case 296:
-#line 3895 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 0;	/* HL.  */
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 0;	/* aop.  */
-	}
-    break;
-
-  case 297:
-#line 3903 "bfin-parse.y"
-    {
-	  (yyval.modcodes).r0 = 0;	/* HL.  */
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* x.  */
-	  (yyval.modcodes).aop = 1;	/* aop.  */
-	}
-    break;
-
-  case 298:
-#line 3913 "bfin-parse.y"
-    {
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* HL.  */
-	}
-    break;
-
-  case 299:
-#line 3918 "bfin-parse.y"
-    {
-	  (yyval.modcodes).s0 = 0;	/* s.  */
-	  (yyval.modcodes).x0 = 1;	/* HL.  */
-	}
-    break;
-
-  case 300:
-#line 3923 "bfin-parse.y"
-    {
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 0;	/* HL.  */
-	}
-    break;
-
-  case 301:
-#line 3928 "bfin-parse.y"
-    {
-	  (yyval.modcodes).s0 = 1;	/* s.  */
-	  (yyval.modcodes).x0 = 1;	/* HL.  */
-	}
-    break;
-
-  case 302:
-#line 3935 "bfin-parse.y"
-    {
-	(yyval.modcodes).x0 = 2;
-	}
-    break;
-
-  case 303:
-#line 3939 "bfin-parse.y"
-    {
-	(yyval.modcodes).x0 = 0;
-	}
-    break;
-
-  case 304:
-#line 3943 "bfin-parse.y"
-    {
-	(yyval.modcodes).x0 = 1;
-	}
-    break;
-
-  case 305:
-#line 3952 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[-1].reg);
-	}
-    break;
-
-  case 306:
-#line 3959 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[-1].reg);
-	}
-    break;
-
-  case 307:
-#line 3966 "bfin-parse.y"
-    {
-	(yyval.reg) = (yyvsp[-1].reg);
-	}
-    break;
-
-  case 308:
-#line 3973 "bfin-parse.y"
-    {
-	  (yyval.macfunc).w = 1;
-          (yyval.macfunc).P = 1;
-          (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
-	  (yyval.macfunc).op = 3;
-          (yyval.macfunc).dst = (yyvsp[-2].reg);
-	  (yyval.macfunc).s0.regno = 0;
-          (yyval.macfunc).s1.regno = 0;
-
-	  if (IS_A1 ((yyvsp[0].reg)) && IS_EVEN ((yyvsp[-2].reg)))
-	    return yyerror ("Cannot move A1 to even register");
-	  else if (!IS_A1 ((yyvsp[0].reg)) && !IS_EVEN ((yyvsp[-2].reg)))
-	    return yyerror ("Cannot move A0 to odd register");
-	}
-    break;
-
-  case 309:
-#line 3988 "bfin-parse.y"
-    {
-	  (yyval.macfunc) = (yyvsp[0].macfunc);
-	  (yyval.macfunc).w = 0; (yyval.macfunc).P = 0;
-	  (yyval.macfunc).dst.regno = 0;
-	}
-    break;
-
-  case 310:
-#line 3994 "bfin-parse.y"
-    {
-	  (yyval.macfunc) = (yyvsp[-1].macfunc);
-	  (yyval.macfunc).w = 1;
-          (yyval.macfunc).P = 1;
-          (yyval.macfunc).dst = (yyvsp[-4].reg);
-	}
-    break;
-
-  case 311:
-#line 4002 "bfin-parse.y"
-    {
-	  (yyval.macfunc) = (yyvsp[-1].macfunc);
-	  (yyval.macfunc).w = 1;
-	  (yyval.macfunc).P = 0;
-          (yyval.macfunc).dst = (yyvsp[-4].reg);
-	}
-    break;
-
-  case 312:
-#line 4010 "bfin-parse.y"
-    {
-	  (yyval.macfunc).w = 1;
-	  (yyval.macfunc).P = 0;
-	  (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
-	  (yyval.macfunc).op = 3;
-          (yyval.macfunc).dst = (yyvsp[-2].reg);
-	  (yyval.macfunc).s0.regno = 0;
-          (yyval.macfunc).s1.regno = 0;
-
-	  if (IS_A1 ((yyvsp[0].reg)) && !IS_H ((yyvsp[-2].reg)))
-	    return yyerror ("Cannot move A1 to low half of register");
-	  else if (!IS_A1 ((yyvsp[0].reg)) && IS_H ((yyvsp[-2].reg)))
-	    return yyerror ("Cannot move A0 to high half of register");
-	}
-    break;
-
-  case 313:
-#line 4028 "bfin-parse.y"
-    {
-	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
-	  (yyval.macfunc).op = 0;
-	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
-	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
-	}
-    break;
-
-  case 314:
-#line 4035 "bfin-parse.y"
-    {
-	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
-	  (yyval.macfunc).op = 1;
-	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
-	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
-	}
-    break;
-
-  case 315:
-#line 4042 "bfin-parse.y"
-    {
-	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
-	  (yyval.macfunc).op = 2;
-	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
-	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
-	}
-    break;
-
-  case 316:
-#line 4052 "bfin-parse.y"
-    {
-	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
-	    {
-	      (yyval.macfunc).s0 = (yyvsp[-2].reg);
-              (yyval.macfunc).s1 = (yyvsp[0].reg);
-	    }
-	  else
-	    return yyerror ("Dregs expected");
-	}
-    break;
-
-  case 317:
-#line 4065 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 0;
-	}
-    break;
-
-  case 318:
-#line 4069 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 1;
-	}
-    break;
-
-  case 319:
-#line 4073 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 2;
-	}
-    break;
-
-  case 320:
-#line 4077 "bfin-parse.y"
-    {
-	(yyval.r0).r0 = 3;
-	}
-    break;
-
-  case 321:
-#line 4084 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = (yyvsp[0].reg).regno;
-	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = 0;
-	}
-    break;
-
-  case 322:
-#line 4090 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0x18;
-	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = 0;
-	}
-    break;
-
-  case 323:
-#line 4096 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = (yyvsp[-2].reg).regno;
-	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 324:
-#line 4102 "bfin-parse.y"
-    {
-	(yyval.modcodes).r0 = 0x18;
-	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
-	(yyval.modcodes).s0 = 1;
-	}
-    break;
-
-  case 325:
-#line 4112 "bfin-parse.y"
-    {
-	Expr_Node_Value val;
-	val.s_value = S_GET_NAME((yyvsp[0].symbol));
-	(yyval.expr) = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
-	}
-    break;
-
-  case 326:
-#line 4121 "bfin-parse.y"
-    { (yyval.value) = BFD_RELOC_BFIN_GOT; }
-    break;
-
-  case 327:
-#line 4123 "bfin-parse.y"
-    { (yyval.value) = BFD_RELOC_BFIN_GOT17M4; }
-    break;
-
-  case 328:
-#line 4125 "bfin-parse.y"
-    { (yyval.value) = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
-    break;
-
-  case 329:
-#line 4129 "bfin-parse.y"
-    {
-	Expr_Node_Value val;
-	val.i_value = (yyvsp[0].value);
-	(yyval.expr) = Expr_Node_Create (Expr_Node_GOT_Reloc, val, (yyvsp[-2].expr), NULL);
-	}
-    break;
-
-  case 330:
-#line 4137 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[0].expr);
-	}
-    break;
-
-  case 331:
-#line 4141 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[0].expr);
-	}
-    break;
-
-  case 332:
-#line 4148 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[-2].expr);
-	}
-    break;
-
-  case 333:
-#line 4154 "bfin-parse.y"
-    {
-	Expr_Node_Value val;
-	val.i_value = (yyvsp[0].value);
-	(yyval.expr) = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
-	}
-    break;
-
-  case 334:
-#line 4160 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[0].expr);
-	}
-    break;
-
-  case 335:
-#line 4164 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[-1].expr);
-	}
-    break;
-
-  case 336:
-#line 4168 "bfin-parse.y"
-    {
-	(yyval.expr) = unary (Expr_Op_Type_COMP, (yyvsp[0].expr));
-	}
-    break;
-
-  case 337:
-#line 4172 "bfin-parse.y"
-    {
-	(yyval.expr) = unary (Expr_Op_Type_NEG, (yyvsp[0].expr));
-	}
-    break;
-
-  case 338:
-#line 4178 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[0].expr);
-	}
-    break;
-
-  case 339:
-#line 4184 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Mult, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 340:
-#line 4188 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Div, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 341:
-#line 4192 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Mod, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 342:
-#line 4196 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Add, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 343:
-#line 4200 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Sub, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 344:
-#line 4204 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Lshift, (yyvsp[-2].expr), (yyvsp[0].expr));	
-	}
-    break;
-
-  case 345:
-#line 4208 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_Rshift, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 346:
-#line 4212 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_BAND, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 347:
-#line 4216 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_LOR, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 348:
-#line 4220 "bfin-parse.y"
-    {
-	(yyval.expr) = binary (Expr_Op_Type_BOR, (yyvsp[-2].expr), (yyvsp[0].expr));
-	}
-    break;
-
-  case 349:
-#line 4224 "bfin-parse.y"
-    {
-	(yyval.expr) = (yyvsp[0].expr);
-	}
-    break;
-
-
-      default: break;
-    }
-
-/* Line 1126 of yacc.c.  */
-#line 7065 "bfin-parse.c"
-
-  yyvsp -= yylen;
-  yyssp -= yylen;
-
-
-  YY_STACK_PRINT (yyss, yyssp);
-
-  *++yyvsp = yyval;
-
-
-  /* Now `shift' the result of the reduction.  Determine what state
-     that goes to, based on the state we popped back to and the rule
-     number reduced by.  */
-
-  yyn = yyr1[yyn];
-
-  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
-  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
-    yystate = yytable[yystate];
-  else
-    yystate = yydefgoto[yyn - YYNTOKENS];
-
-  goto yynewstate;
-
-
-/*------------------------------------.
-| yyerrlab -- here on detecting error |
-`------------------------------------*/
-yyerrlab:
-  /* If not already recovering from an error, report this error.  */
-  if (!yyerrstatus)
-    {
-      ++yynerrs;
-#if YYERROR_VERBOSE
-      yyn = yypact[yystate];
-
-      if (YYPACT_NINF < yyn && yyn < YYLAST)
-	{
-	  int yytype = YYTRANSLATE (yychar);
-	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-	  YYSIZE_T yysize = yysize0;
-	  YYSIZE_T yysize1;
-	  int yysize_overflow = 0;
-	  char *yymsg = 0;
-#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
-	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-	  int yyx;
-
-#if 0
-	  /* This is so xgettext sees the translatable formats that are
-	     constructed on the fly.  */
-	  YY_("syntax error, unexpected %s");
-	  YY_("syntax error, unexpected %s, expecting %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-#endif
-	  char *yyfmt;
-	  char const *yyf;
-	  static char const yyunexpected[] = "syntax error, unexpected %s";
-	  static char const yyexpecting[] = ", expecting %s";
-	  static char const yyor[] = " or %s";
-	  char yyformat[sizeof yyunexpected
-			+ sizeof yyexpecting - 1
-			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-			   * (sizeof yyor - 1))];
-	  char const *yyprefix = yyexpecting;
-
-	  /* Start YYX at -YYN if negative to avoid negative indexes in
-	     YYCHECK.  */
-	  int yyxbegin = yyn < 0 ? -yyn : 0;
-
-	  /* Stay within bounds of both yycheck and yytname.  */
-	  int yychecklim = YYLAST - yyn;
-	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-	  int yycount = 1;
-
-	  yyarg[0] = yytname[yytype];
-	  yyfmt = yystpcpy (yyformat, yyunexpected);
-
-	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-	      {
-		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-		  {
-		    yycount = 1;
-		    yysize = yysize0;
-		    yyformat[sizeof yyunexpected - 1] = '\0';
-		    break;
-		  }
-		yyarg[yycount++] = yytname[yyx];
-		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-		yysize_overflow |= yysize1 < yysize;
-		yysize = yysize1;
-		yyfmt = yystpcpy (yyfmt, yyprefix);
-		yyprefix = yyor;
-	      }
-
-	  yyf = YY_(yyformat);
-	  yysize1 = yysize + yystrlen (yyf);
-	  yysize_overflow |= yysize1 < yysize;
-	  yysize = yysize1;
-
-	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
-	    yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg)
-	    {
-	      /* Avoid sprintf, as that infringes on the user's name space.
-		 Don't have undefined behavior even if the translation
-		 produced a string with the wrong number of "%s"s.  */
-	      char *yyp = yymsg;
-	      int yyi = 0;
-	      while ((*yyp = *yyf))
-		{
-		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-		    {
-		      yyp += yytnamerr (yyp, yyarg[yyi++]);
-		      yyf += 2;
-		    }
-		  else
-		    {
-		      yyp++;
-		      yyf++;
-		    }
-		}
-	      yyerror (yymsg);
-	      YYSTACK_FREE (yymsg);
-	    }
-	  else
-	    {
-	      yyerror (YY_("syntax error"));
-	      goto yyexhaustedlab;
-	    }
-	}
-      else
-#endif /* YYERROR_VERBOSE */
-	yyerror (YY_("syntax error"));
-    }
-
-
-
-  if (yyerrstatus == 3)
-    {
-      /* If just tried and failed to reuse look-ahead token after an
-	 error, discard it.  */
-
-      if (yychar <= YYEOF)
-        {
-	  /* Return failure if at end of input.  */
-	  if (yychar == YYEOF)
-	    YYABORT;
-        }
-      else
-	{
-	  yydestruct ("Error: discarding", yytoken, &yylval);
-	  yychar = YYEMPTY;
-	}
-    }
-
-  /* Else will try to reuse look-ahead token after shifting the error
-     token.  */
-  goto yyerrlab1;
-
-
-/*---------------------------------------------------.
-| yyerrorlab -- error raised explicitly by YYERROR.  |
-`---------------------------------------------------*/
-yyerrorlab:
-
-  /* Pacify compilers like GCC when the user code never invokes
-     YYERROR and the label yyerrorlab therefore never appears in user
-     code.  */
-  if (0)
-     goto yyerrorlab;
-
-yyvsp -= yylen;
-  yyssp -= yylen;
-  yystate = *yyssp;
-  goto yyerrlab1;
-
-
-/*-------------------------------------------------------------.
-| yyerrlab1 -- common code for both syntax error and YYERROR.  |
-`-------------------------------------------------------------*/
-yyerrlab1:
-  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
-
-  for (;;)
-    {
-      yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
-	{
-	  yyn += YYTERROR;
-	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-	    {
-	      yyn = yytable[yyn];
-	      if (0 < yyn)
-		break;
-	    }
-	}
-
-      /* Pop the current state because it cannot handle the error token.  */
-      if (yyssp == yyss)
-	YYABORT;
-
-
-      yydestruct ("Error: popping", yystos[yystate], yyvsp);
-      YYPOPSTACK;
-      yystate = *yyssp;
-      YY_STACK_PRINT (yyss, yyssp);
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  *++yyvsp = yylval;
-
-
-  /* Shift the error token. */
-  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-------------------------------------.
-| yyacceptlab -- YYACCEPT comes here.  |
-`-------------------------------------*/
-yyacceptlab:
-  yyresult = 0;
-  goto yyreturn;
-
-/*-----------------------------------.
-| yyabortlab -- YYABORT comes here.  |
-`-----------------------------------*/
-yyabortlab:
-  yyresult = 1;
-  goto yyreturn;
-
-#ifndef yyoverflow
-/*-------------------------------------------------.
-| yyexhaustedlab -- memory exhaustion comes here.  |
-`-------------------------------------------------*/
-yyexhaustedlab:
-  yyerror (YY_("memory exhausted"));
-  yyresult = 2;
-  /* Fall through.  */
-#endif
-
-yyreturn:
-  if (yychar != YYEOF && yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-		 yytoken, &yylval);
-  while (yyssp != yyss)
-    {
-      yydestruct ("Cleanup: popping",
-		  yystos[*yyssp], yyvsp);
-      YYPOPSTACK;
-    }
-#ifndef yyoverflow
-  if (yyss != yyssa)
-    YYSTACK_FREE (yyss);
-#endif
-  return yyresult;
-}
-
-
-#line 4230 "bfin-parse.y"
-
-
-EXPR_T
-mkexpr (int x, SYMBOL_T s)
-{
-  EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
-  e->value = x;
-  EXPR_SYMBOL(e) = s;
-  return e;
-}
-
-static int
-value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
-{
-  long umax = (1L << sz) - 1;
-  long min = -1L << (sz - 1);
-  long max = (1L << (sz - 1)) - 1;
-	
-  long v = EXPR_VALUE (expr);
-
-  if ((v % mul) != 0)
-    {
-      error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); 
-      return 0;
-    }
-
-  v /= mul;
-
-  if (sign)
-    v = -v;
-
-  if (issigned)
-    {
-      if (v >= min && v <= max) return 1;
-
-#ifdef DEBUG
-      fprintf(stderr, "signed value %lx out of range\n", v * mul);
-#endif
-      return 0;
-    }
-  if (v <= umax && v >= 0) 
-    return 1;
-#ifdef DEBUG
-  fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
-#endif
-  return 0;
-}
-
-/* Return the expression structure that allows symbol operations.
-   If the left and right children are constants, do the operation.  */
-static Expr_Node *
-binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
-{
-  if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
-    {
-      switch (op)
-	{
-        case Expr_Op_Type_Add: 
-	  x->value.i_value += y->value.i_value;
-	  break;
-        case Expr_Op_Type_Sub: 
-	  x->value.i_value -= y->value.i_value;
-	  break;
-        case Expr_Op_Type_Mult: 
-	  x->value.i_value *= y->value.i_value;
-	  break;
-        case Expr_Op_Type_Div: 
-	  if (y->value.i_value == 0)
-	    error ("Illegal Expression:  Division by zero.");
-	  else
-	    x->value.i_value /= y->value.i_value;
-	  break;
-        case Expr_Op_Type_Mod: 
-	  x->value.i_value %= y->value.i_value;
-	  break;
-        case Expr_Op_Type_Lshift: 
-	  x->value.i_value <<= y->value.i_value;
-	  break;
-        case Expr_Op_Type_Rshift: 
-	  x->value.i_value >>= y->value.i_value;
-	  break;
-        case Expr_Op_Type_BAND: 
-	  x->value.i_value &= y->value.i_value;
-	  break;
-        case Expr_Op_Type_BOR: 
-	  x->value.i_value |= y->value.i_value;
-	  break;
-        case Expr_Op_Type_BXOR: 
-	  x->value.i_value ^= y->value.i_value;
-	  break;
-        case Expr_Op_Type_LAND: 
-	  x->value.i_value = x->value.i_value && y->value.i_value;
-	  break;
-        case Expr_Op_Type_LOR: 
-	  x->value.i_value = x->value.i_value || y->value.i_value;
-	  break;
-
-	default:
-	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
-	}
-      return x;
-    }
-  else
-    {
-    /* Create a new expression structure.  */
-    Expr_Node_Value val;
-    val.op_value = op;
-    return Expr_Node_Create (Expr_Node_Binop, val, x, y);
-  }
-}
-
-static Expr_Node *
-unary (Expr_Op_Type op, Expr_Node *x) 
-{
-  if (x->type == Expr_Node_Constant)
-    {
-      switch (op)
-	{
-	case Expr_Op_Type_NEG: 
-	  x->value.i_value = -x->value.i_value;
-	  break;
-	case Expr_Op_Type_COMP:
-	  x->value.i_value = ~x->value.i_value;
-	  break;
-	default:
-	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
-	}
-      return x;
-    }
-  else
-    {
-      /* Create a new expression structure.  */
-      Expr_Node_Value val;
-      val.op_value = op;
-      return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
-    }
-}
-
-int debug_codeselection = 0;
-static void
-notethat (char *format, ...)
-{
-  va_list ap;
-  va_start (ap, format);
-  if (debug_codeselection)
-    {
-      vfprintf (errorf, format, ap);
-    }
-  va_end (ap);
-}
-
-#ifdef TEST
-main (int argc, char **argv)
-{
-  yyparse();
-}
-#endif
-
-
diff --git a/gas/bfin-parse.h b/gas/bfin-parse.h
deleted file mode 100644
index 06403c81ec03..000000000000
--- a/gas/bfin-parse.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.1.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     BYTEOP16P = 258,
-     BYTEOP16M = 259,
-     BYTEOP1P = 260,
-     BYTEOP2P = 261,
-     BYTEOP2M = 262,
-     BYTEOP3P = 263,
-     BYTEUNPACK = 264,
-     BYTEPACK = 265,
-     PACK = 266,
-     SAA = 267,
-     ALIGN8 = 268,
-     ALIGN16 = 269,
-     ALIGN24 = 270,
-     VIT_MAX = 271,
-     EXTRACT = 272,
-     DEPOSIT = 273,
-     EXPADJ = 274,
-     SEARCH = 275,
-     ONES = 276,
-     SIGN = 277,
-     SIGNBITS = 278,
-     LINK = 279,
-     UNLINK = 280,
-     REG = 281,
-     PC = 282,
-     CCREG = 283,
-     BYTE_DREG = 284,
-     REG_A_DOUBLE_ZERO = 285,
-     REG_A_DOUBLE_ONE = 286,
-     A_ZERO_DOT_L = 287,
-     A_ZERO_DOT_H = 288,
-     A_ONE_DOT_L = 289,
-     A_ONE_DOT_H = 290,
-     HALF_REG = 291,
-     NOP = 292,
-     RTI = 293,
-     RTS = 294,
-     RTX = 295,
-     RTN = 296,
-     RTE = 297,
-     HLT = 298,
-     IDLE = 299,
-     STI = 300,
-     CLI = 301,
-     CSYNC = 302,
-     SSYNC = 303,
-     EMUEXCPT = 304,
-     RAISE = 305,
-     EXCPT = 306,
-     LSETUP = 307,
-     LOOP = 308,
-     LOOP_BEGIN = 309,
-     LOOP_END = 310,
-     DISALGNEXCPT = 311,
-     JUMP = 312,
-     JUMP_DOT_S = 313,
-     JUMP_DOT_L = 314,
-     CALL = 315,
-     ABORT = 316,
-     NOT = 317,
-     TILDA = 318,
-     BANG = 319,
-     AMPERSAND = 320,
-     BAR = 321,
-     PERCENT = 322,
-     CARET = 323,
-     BXOR = 324,
-     MINUS = 325,
-     PLUS = 326,
-     STAR = 327,
-     SLASH = 328,
-     NEG = 329,
-     MIN = 330,
-     MAX = 331,
-     ABS = 332,
-     DOUBLE_BAR = 333,
-     _PLUS_BAR_PLUS = 334,
-     _PLUS_BAR_MINUS = 335,
-     _MINUS_BAR_PLUS = 336,
-     _MINUS_BAR_MINUS = 337,
-     _MINUS_MINUS = 338,
-     _PLUS_PLUS = 339,
-     SHIFT = 340,
-     LSHIFT = 341,
-     ASHIFT = 342,
-     BXORSHIFT = 343,
-     _GREATER_GREATER_GREATER_THAN_ASSIGN = 344,
-     ROT = 345,
-     LESS_LESS = 346,
-     GREATER_GREATER = 347,
-     _GREATER_GREATER_GREATER = 348,
-     _LESS_LESS_ASSIGN = 349,
-     _GREATER_GREATER_ASSIGN = 350,
-     DIVS = 351,
-     DIVQ = 352,
-     ASSIGN = 353,
-     _STAR_ASSIGN = 354,
-     _BAR_ASSIGN = 355,
-     _CARET_ASSIGN = 356,
-     _AMPERSAND_ASSIGN = 357,
-     _MINUS_ASSIGN = 358,
-     _PLUS_ASSIGN = 359,
-     _ASSIGN_BANG = 360,
-     _LESS_THAN_ASSIGN = 361,
-     _ASSIGN_ASSIGN = 362,
-     GE = 363,
-     LT = 364,
-     LE = 365,
-     GT = 366,
-     LESS_THAN = 367,
-     FLUSHINV = 368,
-     FLUSH = 369,
-     IFLUSH = 370,
-     PREFETCH = 371,
-     PRNT = 372,
-     OUTC = 373,
-     WHATREG = 374,
-     TESTSET = 375,
-     ASL = 376,
-     ASR = 377,
-     B = 378,
-     W = 379,
-     NS = 380,
-     S = 381,
-     CO = 382,
-     SCO = 383,
-     TH = 384,
-     TL = 385,
-     BP = 386,
-     BREV = 387,
-     X = 388,
-     Z = 389,
-     M = 390,
-     MMOD = 391,
-     R = 392,
-     RND = 393,
-     RNDL = 394,
-     RNDH = 395,
-     RND12 = 396,
-     RND20 = 397,
-     V = 398,
-     LO = 399,
-     HI = 400,
-     BITTGL = 401,
-     BITCLR = 402,
-     BITSET = 403,
-     BITTST = 404,
-     BITMUX = 405,
-     DBGAL = 406,
-     DBGAH = 407,
-     DBGHALT = 408,
-     DBG = 409,
-     DBGA = 410,
-     DBGCMPLX = 411,
-     IF = 412,
-     COMMA = 413,
-     BY = 414,
-     COLON = 415,
-     SEMICOLON = 416,
-     RPAREN = 417,
-     LPAREN = 418,
-     LBRACK = 419,
-     RBRACK = 420,
-     STATUS_REG = 421,
-     MNOP = 422,
-     SYMBOL = 423,
-     NUMBER = 424,
-     GOT = 425,
-     GOT17M4 = 426,
-     FUNCDESC_GOT17M4 = 427,
-     AT = 428,
-     PLTPC = 429
-   };
-#endif
-/* Tokens.  */
-#define BYTEOP16P 258
-#define BYTEOP16M 259
-#define BYTEOP1P 260
-#define BYTEOP2P 261
-#define BYTEOP2M 262
-#define BYTEOP3P 263
-#define BYTEUNPACK 264
-#define BYTEPACK 265
-#define PACK 266
-#define SAA 267
-#define ALIGN8 268
-#define ALIGN16 269
-#define ALIGN24 270
-#define VIT_MAX 271
-#define EXTRACT 272
-#define DEPOSIT 273
-#define EXPADJ 274
-#define SEARCH 275
-#define ONES 276
-#define SIGN 277
-#define SIGNBITS 278
-#define LINK 279
-#define UNLINK 280
-#define REG 281
-#define PC 282
-#define CCREG 283
-#define BYTE_DREG 284
-#define REG_A_DOUBLE_ZERO 285
-#define REG_A_DOUBLE_ONE 286
-#define A_ZERO_DOT_L 287
-#define A_ZERO_DOT_H 288
-#define A_ONE_DOT_L 289
-#define A_ONE_DOT_H 290
-#define HALF_REG 291
-#define NOP 292
-#define RTI 293
-#define RTS 294
-#define RTX 295
-#define RTN 296
-#define RTE 297
-#define HLT 298
-#define IDLE 299
-#define STI 300
-#define CLI 301
-#define CSYNC 302
-#define SSYNC 303
-#define EMUEXCPT 304
-#define RAISE 305
-#define EXCPT 306
-#define LSETUP 307
-#define LOOP 308
-#define LOOP_BEGIN 309
-#define LOOP_END 310
-#define DISALGNEXCPT 311
-#define JUMP 312
-#define JUMP_DOT_S 313
-#define JUMP_DOT_L 314
-#define CALL 315
-#define ABORT 316
-#define NOT 317
-#define TILDA 318
-#define BANG 319
-#define AMPERSAND 320
-#define BAR 321
-#define PERCENT 322
-#define CARET 323
-#define BXOR 324
-#define MINUS 325
-#define PLUS 326
-#define STAR 327
-#define SLASH 328
-#define NEG 329
-#define MIN 330
-#define MAX 331
-#define ABS 332
-#define DOUBLE_BAR 333
-#define _PLUS_BAR_PLUS 334
-#define _PLUS_BAR_MINUS 335
-#define _MINUS_BAR_PLUS 336
-#define _MINUS_BAR_MINUS 337
-#define _MINUS_MINUS 338
-#define _PLUS_PLUS 339
-#define SHIFT 340
-#define LSHIFT 341
-#define ASHIFT 342
-#define BXORSHIFT 343
-#define _GREATER_GREATER_GREATER_THAN_ASSIGN 344
-#define ROT 345
-#define LESS_LESS 346
-#define GREATER_GREATER 347
-#define _GREATER_GREATER_GREATER 348
-#define _LESS_LESS_ASSIGN 349
-#define _GREATER_GREATER_ASSIGN 350
-#define DIVS 351
-#define DIVQ 352
-#define ASSIGN 353
-#define _STAR_ASSIGN 354
-#define _BAR_ASSIGN 355
-#define _CARET_ASSIGN 356
-#define _AMPERSAND_ASSIGN 357
-#define _MINUS_ASSIGN 358
-#define _PLUS_ASSIGN 359
-#define _ASSIGN_BANG 360
-#define _LESS_THAN_ASSIGN 361
-#define _ASSIGN_ASSIGN 362
-#define GE 363
-#define LT 364
-#define LE 365
-#define GT 366
-#define LESS_THAN 367
-#define FLUSHINV 368
-#define FLUSH 369
-#define IFLUSH 370
-#define PREFETCH 371
-#define PRNT 372
-#define OUTC 373
-#define WHATREG 374
-#define TESTSET 375
-#define ASL 376
-#define ASR 377
-#define B 378
-#define W 379
-#define NS 380
-#define S 381
-#define CO 382
-#define SCO 383
-#define TH 384
-#define TL 385
-#define BP 386
-#define BREV 387
-#define X 388
-#define Z 389
-#define M 390
-#define MMOD 391
-#define R 392
-#define RND 393
-#define RNDL 394
-#define RNDH 395
-#define RND12 396
-#define RND20 397
-#define V 398
-#define LO 399
-#define HI 400
-#define BITTGL 401
-#define BITCLR 402
-#define BITSET 403
-#define BITTST 404
-#define BITMUX 405
-#define DBGAL 406
-#define DBGAH 407
-#define DBGHALT 408
-#define DBG 409
-#define DBGA 410
-#define DBGCMPLX 411
-#define IF 412
-#define COMMA 413
-#define BY 414
-#define COLON 415
-#define SEMICOLON 416
-#define RPAREN 417
-#define LPAREN 418
-#define LBRACK 419
-#define RBRACK 420
-#define STATUS_REG 421
-#define MNOP 422
-#define SYMBOL 423
-#define NUMBER 424
-#define GOT 425
-#define GOT17M4 426
-#define FUNCDESC_GOT17M4 427
-#define AT 428
-#define PLTPC 429
-
-
-
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 366 "bfin-parse.y"
-typedef union YYSTYPE {
-  INSTR_T instr;
-  Expr_Node *expr;
-  SYMBOL_T symbol;
-  long value;
-  Register reg;
-  Macfunc macfunc;
-  struct { int r0; int s0; int x0; int aop; } modcodes;
-  struct { int r0; } r0;
-  Opt_mode mod;
-} YYSTYPE;
-/* Line 1447 of yacc.c.  */
-#line 398 "bfin-parse.h"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-extern YYSTYPE yylval;
-
-
-
diff --git a/gas/cgen.c b/gas/cgen.c
index 363c05e5318a..5b0694b03e22 100644
--- a/gas/cgen.c
+++ b/gas/cgen.c
@@ -1,6 +1,6 @@
 /* GAS interface for targets using CGEN: Cpu tools GENerator.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,16 +19,34 @@
    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <setjmp.h>
-#include "ansidecl.h"
-#include "libiberty.h"
-#include "bfd.h"
+#include "as.h"
 #include "symcat.h"
 #include "cgen-desc.h"
-#include "as.h"
 #include "subsegs.h"
 #include "cgen.h"
 #include "dwarf2dbg.h"
 
+#include "symbols.h"
+#include "struc-symbol.h"
+
+#ifdef OBJ_COMPLEX_RELC
+static expressionS * make_right_shifted_expr
+  (expressionS *, const int, const int);
+
+static unsigned long gas_cgen_encode_addend
+  (const unsigned long, const unsigned long, const unsigned long, \
+   const unsigned long, const unsigned long, const unsigned long, \
+   const unsigned long);
+
+static char * weak_operand_overflow_check
+  (const expressionS *, const CGEN_OPERAND *);
+
+static void queue_fixup_recursively
+  (const int, const int, expressionS *, \
+   const CGEN_MAYBE_MULTI_IFLD *, const int, const int);
+
+static int rightshift = 0;
+#endif
 static void queue_fixup (int, int, expressionS *);
 
 /* Opcode table descriptor, must be set by md_begin.  */
@@ -66,6 +84,8 @@ struct fixup
   int opindex;
   int opinfo;
   expressionS exp;
+  struct cgen_maybe_multi_ifield * field;
+  int msb_field_p;
 };
 
 static struct fixup fixups[GAS_CGEN_MAX_FIXUPS];
@@ -249,6 +269,8 @@ gas_cgen_record_fixup (frag, where, insn, length, operand, opinfo, symbol, offse
 		     + (int) operand->type));
   fixP->fx_cgen.insn = insn;
   fixP->fx_cgen.opinfo = opinfo;
+  fixP->fx_cgen.field = NULL;
+  fixP->fx_cgen.msb_field_p = 0;
 
   return fixP;
 }
@@ -287,10 +309,26 @@ gas_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
 			 + (int) operand->type));
   fixP->fx_cgen.insn = insn;
   fixP->fx_cgen.opinfo = opinfo;
+  fixP->fx_cgen.field = NULL;
+  fixP->fx_cgen.msb_field_p = 0;
 
   return fixP;
 }
 
+#ifdef OBJ_COMPLEX_RELC
+static symbolS *
+expr_build_binary (operatorT op, symbolS * s1, symbolS * s2)
+{
+  expressionS e;
+
+  e.X_op = op;
+  e.X_add_symbol = s1;
+  e.X_op_symbol = s2;
+  e.X_add_number = 0;
+  return make_expr_symbol (& e);
+}
+#endif
+
 /* Used for communication between the next two procedures.  */
 static jmp_buf expr_jmp_buf;
 static int expr_jmp_buf_p;
@@ -308,7 +346,12 @@ static int expr_jmp_buf_p;
 
 const char *
 gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
+
+#ifdef OBJ_COMPLEX_RELC
+     CGEN_CPU_DESC cd;
+#else
      CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+#endif
      enum cgen_parse_operand_type want;
      const char **strP;
      int opindex;
@@ -329,6 +372,13 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
   const char *errmsg;
   expressionS exp;
 
+#ifdef OBJ_COMPLEX_RELC
+  volatile int              signed_p = 0;
+  symbolS *                 stmp = NULL;
+  bfd_reloc_code_real_type  reloc_type;
+  const CGEN_OPERAND *      operand;
+  fixS                      dummy_fixup;
+#endif
   if (want == CGEN_PARSE_OPERAND_INIT)
     {
       gas_cgen_init_parse ();
@@ -386,9 +436,82 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
       break;
     de_fault:
     default:
+#ifdef OBJ_COMPLEX_RELC
+      /* Look up operand, check to see if there's an obvious
+	 overflow (this helps disambiguate some insn parses).  */
+      operand = cgen_operand_lookup_by_num (cd, opindex);
+      errmsg = weak_operand_overflow_check (& exp, operand);
+
+      if (! errmsg)
+	{
+	  /* Fragment the expression as necessary, and queue a reloc.  */
+	  memset (& dummy_fixup, 0, sizeof (fixS));
+
+	  reloc_type = md_cgen_lookup_reloc (0, operand, & dummy_fixup);
+
+	  if (exp.X_op == O_symbol
+	      && reloc_type == BFD_RELOC_RELC
+	      && exp.X_add_symbol->sy_value.X_op == O_constant
+	      && exp.X_add_symbol->bsym->section != expr_section
+	      && exp.X_add_symbol->bsym->section != absolute_section
+	      && exp.X_add_symbol->bsym->section != undefined_section)
+	    {
+	      /* Local labels will have been (eagerly) turned into constants
+		 by now, due to the inappropriately deep insight of the
+		 expression parser.  Unfortunately make_expr_symbol
+		 prematurely dives into the symbol evaluator, and in this
+		 case it gets a bad answer, so we manually create the
+		 expression symbol we want here.  */
+	      stmp = symbol_create (FAKE_LABEL_NAME, expr_section, 0,
+				    & zero_address_frag);
+	      symbol_set_value_expression (stmp, & exp);
+	    } 
+	  else 
+	    stmp = make_expr_symbol (& exp);
+
+	  /* If this is a pc-relative RELC operand, we
+	     need to subtract "." from the expression.  */	  
+ 	  if (reloc_type == BFD_RELOC_RELC
+	      && CGEN_OPERAND_ATTR_VALUE (operand, CGEN_OPERAND_PCREL_ADDR))
+ 	    stmp = expr_build_binary (O_subtract, stmp, expr_build_dot ()); 
+
+	  /* FIXME: this is not a perfect heuristic for figuring out
+	     whether an operand is signed: it only works when the operand
+	     is an immediate. it's not terribly likely that any other
+	     values will be signed relocs, but it's possible. */
+	  if (operand && (operand->hw_type == HW_H_SINT))
+	    signed_p = 1;
+	  
+	  if (stmp->bsym && (stmp->bsym->section == expr_section))
+	    {
+	      if (signed_p)
+		stmp->bsym->flags |= BSF_SRELC;
+	      else
+		stmp->bsym->flags |= BSF_RELC;
+	    }
+	  
+	  /* Now package it all up for the fixup emitter.  */
+	  exp.X_op = O_symbol;
+	  exp.X_op_symbol = 0;
+	  exp.X_add_symbol = stmp;
+	  exp.X_add_number = 0;
+	      
+	  /* Re-init rightshift quantity, just in case.  */
+	  rightshift = operand->length;
+	  queue_fixup_recursively (opindex, opinfo_1, & exp,  
+				   (reloc_type == BFD_RELOC_RELC) ?
+				   & (operand->index_fields) : 0,
+				   signed_p, -1);
+	}
+      * resultP = errmsg
+	? CGEN_PARSE_OPERAND_RESULT_ERROR
+	: CGEN_PARSE_OPERAND_RESULT_QUEUED;
+      *valueP = 0;
+#else
       queue_fixup (opindex, opinfo_1, &exp);
       *valueP = 0;
       *resultP = CGEN_PARSE_OPERAND_RESULT_QUEUED;
+#endif      
       break;
     }
 
@@ -556,6 +679,8 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
 				       insn, length, operand,
 				       fixups[i].opinfo,
 				       &fixups[i].exp);
+      fixP->fx_cgen.field = fixups[i].field;
+      fixP->fx_cgen.msb_field_p = fixups[i].msb_field_p;
       if (result)
 	result->fixups[i] = fixP;
     }
@@ -567,6 +692,167 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
     }
 }
 
+#ifdef OBJ_COMPLEX_RELC
+/* Queue many fixups, recursively. If the field is a multi-ifield,
+   repeatedly queue its sub-parts, right shifted to fit into the field (we
+   assume here multi-fields represent a left-to-right, MSB0-LSB0
+   reading). */
+
+static void
+queue_fixup_recursively (const int                      opindex,
+			 const int                      opinfo,
+			 expressionS *                  expP,
+			 const CGEN_MAYBE_MULTI_IFLD *  field,
+			 const int                      signed_p,
+			 const int                      part_of_multi)
+{
+  if (field && field->count)
+    {
+      int i;
+  
+      for (i = 0; i < field->count; ++ i)
+	queue_fixup_recursively (opindex, opinfo, expP, 
+				 & (field->val.multi[i]), signed_p, i);
+    }
+  else
+    {
+      expressionS * new_exp = expP;
+
+#ifdef DEBUG
+      printf ("queueing fixup for field %s\n",
+	      (field ? field->val.leaf->name : "??"));
+      print_symbol_value (expP->X_add_symbol);
+#endif
+      if (field && part_of_multi != -1)
+	{
+	  rightshift -= field->val.leaf->length;
+
+	  /* Shift reloc value by number of bits remaining after this
+	     field.  */
+	  if (rightshift)
+	    new_exp = make_right_shifted_expr (expP, rightshift, signed_p);	  
+	}
+      
+      /* Truncate reloc values to length, *after* leftmost one.  */
+      fixups[num_fixups].msb_field_p = (part_of_multi <= 0);
+      fixups[num_fixups].field = (CGEN_MAYBE_MULTI_IFLD *) field;
+      
+      queue_fixup (opindex, opinfo, new_exp);
+    }
+}
+
+/* Encode the self-describing RELC reloc format's addend.  */
+
+static unsigned long 
+gas_cgen_encode_addend (const unsigned long start,    /* in bits */
+			const unsigned long len,      /* in bits */
+			const unsigned long oplen,    /* in bits */
+			const unsigned long wordsz,   /* in bytes */
+			const unsigned long chunksz,  /* in bytes */
+			const unsigned long signed_p,
+			const unsigned long trunc_p)
+{
+  unsigned long res = 0L;
+
+  res |= start    & 0x3F;
+  res |= (oplen   & 0x3F) << 6;
+  res |= (len     & 0x3F) << 12;
+  res |= (wordsz  & 0xF)  << 18;
+  res |= (chunksz & 0xF)  << 22;
+  res |= (CGEN_INSN_LSB0_P ? 1 : 0) << 27;
+  res |= signed_p << 28;
+  res |= trunc_p << 29;
+
+  return res;
+}
+
+/* Purpose: make a weak check that the expression doesn't overflow the
+   operand it's to be inserted into.
+
+   Rationale: some insns used to use %operators to disambiguate during a
+   parse. when these %operators are translated to expressions by the macro
+   expander, the ambiguity returns. we attempt to disambiguate by field
+   size.
+   
+   Method: check to see if the expression's top node is an O_and operator,
+   and the mask is larger than the operand length. This would be an
+   overflow, so signal it by returning an error string. Any other case is
+   ambiguous, so we assume it's OK and return NULL.  */
+
+static char *
+weak_operand_overflow_check (const expressionS *  exp,
+			     const CGEN_OPERAND * operand)
+{
+  const unsigned long len = operand->length;
+  unsigned long mask;
+  unsigned long opmask = (((1L << (len - 1)) - 1) << 1) | 1;
+
+  if (!exp)
+    return NULL;
+
+  if (exp->X_op != O_bit_and)
+    {
+      /* Check for implicit overflow flag.  */
+      if (CGEN_OPERAND_ATTR_VALUE 
+	  (operand, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW))
+	return _("a reloc on this operand implies an overflow");
+      return NULL;
+    }
+  
+  mask = exp->X_add_number;
+
+  if (exp->X_add_symbol &&
+      exp->X_add_symbol->sy_value.X_op == O_constant)
+    mask |= exp->X_add_symbol->sy_value.X_add_number;
+
+  if (exp->X_op_symbol &&
+      exp->X_op_symbol->sy_value.X_op == O_constant)
+    mask |= exp->X_op_symbol->sy_value.X_add_number;
+
+  /* Want to know if mask covers more bits than opmask. 
+     this is the same as asking if mask has any bits not in opmask,
+     or whether (mask & ~opmask) is nonzero.  */
+  if (mask && (mask & ~opmask))
+    {
+#ifdef DEBUG
+      printf ("overflow: (mask = %8.8x, ~opmask = %8.8x, AND = %8.8x)\n",
+	      mask, ~opmask, (mask & ~opmask));
+#endif
+      return _("operand mask overflow");
+    }
+
+  return NULL;  
+}
+
+
+static expressionS *
+make_right_shifted_expr (expressionS * exp,
+			 const int     amount,
+			 const int     signed_p)
+{
+  symbolS * stmp = 0;
+  expressionS * new_exp;
+
+  stmp = expr_build_binary (O_right_shift, 
+			    make_expr_symbol (exp),
+			    expr_build_uconstant (amount));
+  
+  if (signed_p)
+    stmp->bsym->flags |= BSF_SRELC;
+  else
+    stmp->bsym->flags |= BSF_RELC;
+  
+  /* Then wrap that in a "symbol expr" for good measure.  */
+  new_exp = xmalloc (sizeof (expressionS));
+  memset (new_exp, 0, sizeof (expressionS));
+  new_exp->X_op = O_symbol;
+  new_exp->X_op_symbol = 0;
+  new_exp->X_add_symbol = stmp;
+  new_exp->X_add_number = 0;
+  
+  return new_exp;
+}
+#endif
 /* Apply a fixup to the object code.  This is called for all the
    fixups we generated by the call to fix_new_exp, above.  In the call
    above we used a reloc code which was the largest legal reloc code
@@ -605,6 +891,30 @@ gas_cgen_md_apply_fix (fixP, valP, seg)
       bfd_reloc_code_real_type reloc_type;
       CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
       const CGEN_INSN *insn = fixP->fx_cgen.insn;
+      int start;
+      int length;
+      int signed_p = 0;
+
+      if (fixP->fx_cgen.field)
+	{	      
+	  /* Use the twisty little pointer path
+	     back to the ifield if it exists.  */
+	  start = fixP->fx_cgen.field->val.leaf->start;
+	  length = fixP->fx_cgen.field->val.leaf->length;
+	}
+      else
+	{
+	  /* Or the far less useful operand-size guesstimate.  */
+	  start = operand->start;
+	  length = operand->length;
+	}
+
+      /* FIXME: this is not a perfect heuristic for figuring out
+         whether an operand is signed: it only works when the operand
+         is an immediate. it's not terribly likely that any other
+         values will be signed relocs, but it's possible. */
+      if (operand && (operand->hw_type == HW_H_SINT))
+        signed_p = 1;
 
       /* If the reloc has been fully resolved finish the operand here.  */
       /* FIXME: This duplicates the capabilities of code in BFD.  */
@@ -647,6 +957,18 @@ gas_cgen_md_apply_fix (fixP, valP, seg)
 	 partial_inplace == false.  */
 
       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+#ifdef OBJ_COMPLEX_RELC
+      if (reloc_type == BFD_RELOC_RELC)
+	{
+	  /* Change addend to "self-describing" form,
+	     for BFD to handle in the linker.  */
+	  value = gas_cgen_encode_addend (start, operand->length,
+					  length, fixP->fx_size, 
+					  cd->insn_chunk_bitsize / 8, 
+					  signed_p, 
+					  ! (fixP->fx_cgen.msb_field_p));
+	}
+#endif
 
       if (reloc_type != BFD_RELOC_NONE)
 	fixP->fx_r_type = reloc_type;
@@ -702,7 +1024,6 @@ gas_cgen_tc_gen_reloc (section, fixP)
      fixS *     fixP;
 {
   arelent *reloc;
-
   reloc = (arelent *) xmalloc (sizeof (arelent));
 
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
@@ -740,3 +1061,4 @@ gas_cgen_begin ()
   else
     cgen_clear_signed_overflow_ok (gas_cgen_cpu_desc);
 }
+
diff --git a/gas/cond.c b/gas/cond.c
index d6c32acc2532..d76e4d98d9a2 100644
--- a/gas/cond.c
+++ b/gas/cond.c
@@ -1,6 +1,6 @@
 /* cond.c - conditional assembly pseudo-ops, and .include
    Copyright 1990, 1991, 1992, 1993, 1995, 1997, 1998, 2000, 2001, 2002,
-   2003 Free Software Foundation, Inc.
+   2003, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -20,6 +20,7 @@
    02110-1301, USA.  */
 
 #include "as.h"
+#include "sb.h"
 #include "macro.h"
 
 #include "obstack.h"
diff --git a/gas/config.in b/gas/config.in
index b15d8024aba2..20d5df9a4e2f 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -29,7 +29,11 @@
 /* Supported emulations. */
 #undef EMULATIONS
 
-/* Define to 1 if NLS is requested */
+/* Define if you want run-time sanity checks. */
+#undef ENABLE_CHECKING
+
+/* Define to 1 if translation of program messages to the user's native
+   language is requested. */
 #undef ENABLE_NLS
 
 /* Define to 1 if you have `alloca', as a function or macro. */
@@ -39,12 +43,6 @@
    */
 #undef HAVE_ALLOCA_H
 
-/* Define to 1 if you have the <argz.h> header file. */
-#undef HAVE_ARGZ_H
-
-/* Define to 1 if you have the `dcgettext' function. */
-#undef HAVE_DCGETTEXT
-
 /* Is the prototype for getopt in <unistd.h> in the expected format? */
 #undef HAVE_DECL_GETOPT
 
@@ -52,60 +50,24 @@
    don't. */
 #undef HAVE_DECL_VSNPRINTF
 
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
 /* Define to 1 if you have the <errno.h> header file. */
 #undef HAVE_ERRNO_H
 
-/* Define to 1 if you have the `getcwd' function. */
-#undef HAVE_GETCWD
-
-/* Define to 1 if you have the `getpagesize' function. */
-#undef HAVE_GETPAGESIZE
-
-/* Define as 1 if you have gettext and don't want to use GNU gettext. */
-#undef HAVE_GETTEXT
-
 /* Define to 1 if you have the <inttypes.h> header file. */
 #undef HAVE_INTTYPES_H
 
-/* Define if your locale.h file contains LC_MESSAGES. */
-#undef HAVE_LC_MESSAGES
-
-/* Define to 1 if you have the <limits.h> header file. */
-#undef HAVE_LIMITS_H
-
-/* Define to 1 if you have the <locale.h> header file. */
-#undef HAVE_LOCALE_H
-
-/* Define to 1 if you have the <malloc.h> header file. */
-#undef HAVE_MALLOC_H
-
 /* Define to 1 if you have the <memory.h> header file. */
 #undef HAVE_MEMORY_H
 
-/* Define to 1 if you have a working `mmap' system call. */
-#undef HAVE_MMAP
-
-/* Define to 1 if you have the `munmap' function. */
-#undef HAVE_MUNMAP
-
-/* Define to 1 if you have the <nl_types.h> header file. */
-#undef HAVE_NL_TYPES_H
-
-/* Define to 1 if you have the `putenv' function. */
-#undef HAVE_PUTENV
-
 /* Define to 1 if you have the `remove' function. */
 #undef HAVE_REMOVE
 
 /* Define to 1 if you have the `sbrk' function. */
 #undef HAVE_SBRK
 
-/* Define to 1 if you have the `setenv' function. */
-#undef HAVE_SETENV
-
-/* Define to 1 if you have the `setlocale' function. */
-#undef HAVE_SETLOCALE
-
 /* Define to 1 if you have the <stdarg.h> header file. */
 #undef HAVE_STDARG_H
 
@@ -115,24 +77,12 @@
 /* Define to 1 if you have the <stdlib.h> header file. */
 #undef HAVE_STDLIB_H
 
-/* Define if you have the stpcpy function */
-#undef HAVE_STPCPY
-
-/* Define to 1 if you have the `strcasecmp' function. */
-#undef HAVE_STRCASECMP
-
-/* Define to 1 if you have the `strchr' function. */
-#undef HAVE_STRCHR
-
 /* Define to 1 if you have the <strings.h> header file. */
 #undef HAVE_STRINGS_H
 
 /* Define to 1 if you have the <string.h> header file. */
 #undef HAVE_STRING_H
 
-/* Define to 1 if you have the <sys/param.h> header file. */
-#undef HAVE_SYS_PARAM_H
-
 /* Define to 1 if you have the <sys/stat.h> header file. */
 #undef HAVE_SYS_STAT_H
 
@@ -145,24 +95,16 @@
 /* Define to 1 if you have the `unlink' function. */
 #undef HAVE_UNLINK
 
-/* Define to 1 if you have the <values.h> header file. */
-#undef HAVE_VALUES_H
-
 /* Define to 1 if you have the <varargs.h> header file. */
 #undef HAVE_VARARGS_H
 
-/* Define to 1 if you have the `__argz_count' function. */
-#undef HAVE___ARGZ_COUNT
-
-/* Define to 1 if you have the `__argz_next' function. */
-#undef HAVE___ARGZ_NEXT
-
-/* Define to 1 if you have the `__argz_stringify' function. */
-#undef HAVE___ARGZ_STRINGIFY
-
 /* Using i386 COFF? */
 #undef I386COFF
 
+/* Define to the sub-directory in which libtool stores uninstalled libraries.
+   */
+#undef LT_OBJDIR
+
 /* Using m68k COFF? */
 #undef M68KCOFF
 
@@ -217,9 +159,6 @@
 /* generic support? */
 #undef OBJ_MAYBE_GENERIC
 
-/* IEEE support? */
-#undef OBJ_MAYBE_IEEE
-
 /* SOM support? */
 #undef OBJ_MAYBE_SOM
 
@@ -282,6 +221,9 @@
 /* Target vendor. */
 #undef TARGET_VENDOR
 
+/* Use b modifier when opening binary files? */
+#undef USE_BINARY_FOPEN
+
 /* Use emulation support? */
 #undef USE_EMULATIONS
 
@@ -302,17 +244,8 @@
    `char[]'. */
 #undef YYTEXT_POINTER
 
-/* Define to empty if `const' does not conform to ANSI C. */
-#undef const
-
 /* Define to `__inline__' or `__inline' if that's what the C compiler
    calls it, or to nothing if 'inline' is not supported under any name.  */
 #ifndef __cplusplus
 #undef inline
 #endif
-
-/* Define to `long' if <sys/types.h> does not define. */
-#undef off_t
-
-/* Define to `unsigned' if <sys/types.h> does not define. */
-#undef size_t
diff --git a/gas/config/atof-vax.c b/gas/config/atof-vax.c
index 75756904fb89..fe9f8b9b1063 100644
--- a/gas/config/atof-vax.c
+++ b/gas/config/atof-vax.c
@@ -1,5 +1,5 @@
 /* atof_vax.c - turn a Flonum into a VAX floating point number
-   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005
+   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -35,7 +35,7 @@ int flonum_gen2vax (int, FLONUM_TYPE *, LITTLENUM_TYPE *);
 
 /* Number of chars in flonum type 'letter'.  */
 
-static int
+static unsigned int
 atof_vax_sizeof (int letter)
 {
   int return_value;
@@ -395,7 +395,7 @@ md_atof (int what_statement_type,
 {
   LITTLENUM_TYPE words[MAXIMUM_NUMBER_OF_LITTLENUMS];
   char kind_of_float;
-  int number_of_chars;
+  unsigned int number_of_chars;
   LITTLENUM_TYPE *littlenumP;
 
   switch (what_statement_type)
diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h
index 48bacb3ed7d4..f94107136cf7 100644
--- a/gas/config/bfin-defs.h
+++ b/gas/config/bfin-defs.h
@@ -1,5 +1,5 @@
 /* bfin-defs.h ADI Blackfin gas header file
-   Copyright 2005
+   Copyright 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -22,9 +22,6 @@
 #ifndef BFIN_PARSE_H
 #define BFIN_PARSE_H  
 
-#include <bfd.h>
-#include "as.h"
-
 #define PCREL	1
 #define CODE_FRAG_SIZE 4096  /* 1 page.  */  
 
@@ -374,7 +371,6 @@ void semantic_error_2 (char *syntax);
 
 EXPR_T mkexpr (int, SYMBOL_T);
 
-extern void bfin_equals (Expr_Node *sym);
 /* Defined in bfin-lex.l.  */
 void set_start_state (void);
 
diff --git a/gas/config/bfin-lex.l b/gas/config/bfin-lex.l
index 3a0077cd9854..21f284541324 100644
--- a/gas/config/bfin-lex.l
+++ b/gas/config/bfin-lex.l
@@ -1,5 +1,5 @@
 /* bfin-lex.l  ADI Blackfin lexer
-   Copyright 2005
+   Copyright 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,11 +20,9 @@
    02110-1301, USA.  */
 %{
 
-#include <stdlib.h>
-#include <string.h>
+#include "as.h"
 #include "bfin-defs.h"
 #include "bfin-parse.h"
-#include "as.h"
 
 static long parse_int (char **end);
 static int parse_halfreg (Register *r, int cl, char *hr);
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 917c2d27ba0f..b3416aa1130a 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1,5 +1,5 @@
 /* bfin-parse.y  ADI Blackfin parser
-   Copyright 2005
+   Copyright 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,8 +20,7 @@
    02110-1301, USA.  */
 %{
 
-#include <stdio.h>
-#include <stdarg.h>
+#include "as.h"
 #include <obstack.h>
 
 #include "bfin-aux.h"  // opcode generating auxiliaries
@@ -298,9 +297,10 @@ check_macfuncs (Macfunc *aa, Opt_mode *opa,
 	return yyerror ("Vector AxMACs can't be same");
     }
 
-  /*  If both ops are != 3, we have multiply_halfregs in both
+  /*  If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
   assignment_or_macfuncs.  */
-  if (aa->op == ab->op && aa->op != 3)
+  if (aa->op < 3 && aa->op >=0
+      && ab->op < 3 && ab->op >= 0)
     {
       if (check_multiply_halfregs (aa, ab) < 0)
 	return -1;
@@ -1730,7 +1730,7 @@ asm_1:
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
 			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
 			      &$1, 0, &$3.s0, &$3.s1, 1);
-		}	
+	    }
 	}
 
 	| REG ASSIGN multiply_halfregs opt_mode 
@@ -1739,6 +1739,9 @@ asm_1:
 	  if (!IS_DREG ($1))
 	    return yyerror ("Dreg expected");
 
+	  if (IS_EVEN ($1) && $4.MM)
+	    return yyerror ("(M) not allowed with MAC0");
+
 	  if (!IS_EVEN ($1))
 	    {
 	      notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
@@ -1747,15 +1750,13 @@ asm_1:
 			      IS_H ($3.s0), IS_H ($3.s1), 0, 0,
 			      &$1, 0, &$3.s0, &$3.s1, 0);
 	    }
-	  else if ($4.MM == 0)
+	  else
 	    {
 	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
 	      $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
 			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
 			      &$1,  0, &$3.s0, &$3.s1, 1);
 	    }
-	  else
-	    return yyerror ("Register or mode mismatch");
 	}
 
 	| HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
@@ -1764,57 +1765,56 @@ asm_1:
 	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
 	    return yyerror ("Dregs expected");
 
+	  if (!IS_HCOMPL($1, $6))
+	    return yyerror ("Dest registers mismatch");
+
 	  if (check_multiply_halfregs (&$3, &$8) < 0)
 	    return -1;
 
-	  if (IS_H ($1) && !IS_H ($6))
-	    {
-	      notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
-		       "dregs_lo = multiply_halfregs opt_mode\n");
-	      $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
-			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
-	  else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
-	    {
-	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
-			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
+	  if ((!IS_H ($1) && $4.MM)
+	      || (!IS_H ($6) && $9.MM))
+	    return yyerror ("(M) not allowed with MAC0");
+
+	  notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
+		    "dregs_lo = multiply_halfregs opt_mode\n");
+
+	  if (IS_H ($1))
+	    $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
+			    IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	  else
-	    return yyerror ("Multfunc Register or mode mismatch");
+	    $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
+			    IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	}
 
-	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode 
+	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
 	{
 	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
 	    return yyerror ("Dregs expected");
 
+	  if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
+	      || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
+	    return yyerror ("Dest registers mismatch");
+
 	  if (check_multiply_halfregs (&$3, &$8) < 0)
 	    return -1;
 
+	  if ((IS_EVEN ($1) && $4.MM)
+	      || (IS_EVEN ($6) && $9.MM))
+	    return yyerror ("(M) not allowed with MAC0");
+
 	  notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
 		   "dregs = multiply_halfregs opt_mode\n");
-	  if (IS_EVEN ($1))
-	    {
-	      if ($6.regno - $1.regno != 1 || $4.MM != 0)
-		return yyerror ("Dest registers or mode mismatch");
 
-	      /*   op1       MM      mmod  */
-	      $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
-			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	      
-	    }
+	  if (IS_EVEN ($1))
+	    $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
+			    IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	  else
-	    {
-	      if ($1.regno - $6.regno != 1)
-		return yyerror ("Dest registers mismatch");
-	      
-	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
-			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
-			      &$1, 0, &$3.s0, &$3.s1, 1);
-	    }
+	    $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
+			    IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			    &$1, 0, &$3.s0, &$3.s1, 1);
 	}
 
 
@@ -3223,16 +3223,6 @@ asm_1:
 	}
 
 
-
-/* Expression Assignment.  */
-
-	| expr ASSIGN expr
-	{
-	  bfin_equals ($1);
-	  $$ = 0;
-	}
-
-
 /*  PushPopMultiple.  */
 	| reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
 	{
@@ -4280,6 +4270,8 @@ value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
 static Expr_Node *
 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
 {
+  Expr_Node_Value val;
+
   if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
     {
       switch (op)
@@ -4329,13 +4321,32 @@ binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
 	}
       return x;
     }
-  else
+  /* Canonicalize order to EXPR OP CONSTANT.  */
+  if (x->type == Expr_Node_Constant)
     {
-    /* Create a new expression structure.  */
-    Expr_Node_Value val;
-    val.op_value = op;
-    return Expr_Node_Create (Expr_Node_Binop, val, x, y);
-  }
+      Expr_Node *t = x;
+      x = y;
+      y = t;
+    }
+  /* Canonicalize subtraction of const to addition of negated const.  */
+  if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
+    {
+      op = Expr_Op_Type_Add;
+      y->value.i_value = -y->value.i_value;
+    }
+  if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
+      && x->Right_Child->type == Expr_Node_Constant)
+    {
+      if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
+	{
+	  x->Right_Child->value.i_value += y->value.i_value;
+	  return x;
+	}
+    }
+
+  /* Create a new expression structure.  */
+  val.op_value = op;
+  return Expr_Node_Create (Expr_Node_Binop, val, x, y);
 }
 
 static Expr_Node *
diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h
index e7af8536a805..4351609cc38e 100644
--- a/gas/config/m68k-parse.h
+++ b/gas/config/m68k-parse.h
@@ -113,9 +113,12 @@ enum m68k_register
   BUSCR,			/* 68060 added these.  */
   PCR,
   ROMBAR,			/* mcf5200 added these.  */
+  RAMBAR_ALT,			/* Some CF chips have RAMBAR using
+				   RAMBAR0's number */
   RAMBAR0,
   RAMBAR1,
   MMUBAR,			/* mcfv4e added these.  */
+  ROMBAR0,			/* mcfv4e added these.  */
   ROMBAR1,			/* mcfv4e added these.  */
   MPCR, EDRAMBAR, SECMBAR,	/* mcfv4e added these.  */
   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
@@ -126,7 +129,10 @@ enum m68k_register
   FLASHBAR, RAMBAR,  		/* mcf528x added these.  */
   MBAR2,  		        /* mcf5249 added this.  */
   MBAR,
-#define last_movec_reg MBAR
+  ASID,				/* m5475.  */
+  CAC,  		        /* fido added this.  */
+  MBB,
+#define last_movec_reg MBB
   /* End of movec ordering constraints.  */
 
   FPI,
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index a5a76ff3da0a..1ac8a138f082 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -1026,7 +1026,7 @@ weak_name2altname (const char * name)
 }
 
 /* Return the name of the weak symbol corresponding to an
-   alterate symbol.  */
+   alternate symbol.  */
 
 static const char *
 weak_altname2name (const char * name)
@@ -1579,7 +1579,7 @@ obj_coff_section (int ignore ATTRIBUTE_UNUSED)
 		  if (! load_removed)
 		    flags |= SEC_LOAD;
 		  /* Note - the READONLY flag is set here, even for the 'x'
-		     attrbiute in order to be compatible with the MSVC
+		     attribute in order to be compatible with the MSVC
 		     linker.  */
 		  if (! readonly_removed)
 		    flags |= SEC_READONLY;
diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h
index 6fcbc9f06cbb..d2b212565ef1 100644
--- a/gas/config/obj-coff.h
+++ b/gas/config/obj-coff.h
@@ -1,6 +1,6 @@
 /* coff object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -27,8 +27,6 @@
 
 #include "targ-cpu.h"
 
-#include "bfd.h"
-
 /* This internal_lineno crap is to stop namespace pollution from the
    bfd internal coff headerfile.  */
 #define internal_lineno bfd_internal_lineno
@@ -57,16 +55,30 @@
 #endif
 
 #ifdef TC_I386
+#ifndef TE_PEP
+#include "coff/x86_64.h"
+#else
 #include "coff/i386.h"
+#endif
 
 #ifdef TE_PE
+#ifdef TE_PEP
+extern const char *   x86_64_target_format (void);
+#define TARGET_FORMAT x86_64_target_format ()
+#define COFF_TARGET_FORMAT "pe-x86-64"
+#else
 #define TARGET_FORMAT "pe-i386"
 #endif
+#endif
 
 #ifndef TARGET_FORMAT
+#ifdef TE_PEP
+#define TARGET_FORMAT "coff-x86-64"
+#else
 #define TARGET_FORMAT "coff-i386"
 #endif
 #endif
+#endif
 
 #ifdef TC_M68K
 #include "coff/m68k.h"
diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index f922149cae0d..2f93990e721d 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -1,6 +1,7 @@
 /* ELF object file format
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005, 2006, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -57,6 +58,10 @@
 #include "elf/x86-64.h"
 #endif
 
+#ifdef TC_MEP
+#include "elf/mep.h"
+#endif
+
 static void obj_elf_line (int);
 static void obj_elf_size (int);
 static void obj_elf_type (int);
@@ -632,6 +637,11 @@ obj_elf_change_section (const char *name,
 	  else if (attr == SHF_EXECINSTR
 		   && strcmp (name, ".note.GNU-stack") == 0)
 	    override = TRUE;
+#ifdef TC_ALPHA
+	  /* A section on Alpha may have SHF_ALPHA_GPREL.  */
+	  else if ((attr & ~ssect->attr) == SHF_ALPHA_GPREL)
+	    override = TRUE;
+#endif
 	  else
 	    {
 	      if (group_name == NULL)
@@ -1414,11 +1424,12 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
   Elf_Internal_Note i_note;
   Elf_External_Note e_note;
   asection *note_secp = NULL;
-  int len;
 
   SKIP_WHITESPACE ();
   if (*input_line_pointer == '\"')
     {
+      unsigned int len;
+
       ++input_line_pointer;	/* -> 1st char of string.  */
       name = input_line_pointer;
 
@@ -1429,19 +1440,19 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
       *(input_line_pointer - 1) = '\0';
       *input_line_pointer = c;
 
-      /* create the .note section */
-
+      /* Create the .note section.  */
       note_secp = subseg_new (".note", 0);
       bfd_set_section_flags (stdoutput,
 			     note_secp,
 			     SEC_HAS_CONTENTS | SEC_READONLY);
 
-      /* process the version string */
-
-      len = strlen (name);
+      /* Process the version string.  */
+      len = strlen (name) + 1;
 
-      i_note.namesz = ((len + 1) + 3) & ~3; /* round this to word boundary */
-      i_note.descsz = 0;	/* no description */
+      /* PR 3456: Although the name field is padded out to an 4-byte
+	 boundary, the namesz field should not be adjusted.  */
+      i_note.namesz = len;
+      i_note.descsz = 0;	/* No description.  */
       i_note.type = NT_VERSION;
       p = frag_more (sizeof (e_note.namesz));
       md_number_to_chars (p, i_note.namesz, sizeof (e_note.namesz));
@@ -1449,17 +1460,16 @@ obj_elf_version (int ignore ATTRIBUTE_UNUSED)
       md_number_to_chars (p, i_note.descsz, sizeof (e_note.descsz));
       p = frag_more (sizeof (e_note.type));
       md_number_to_chars (p, i_note.type, sizeof (e_note.type));
-      p = frag_more (len + 1);
-      strcpy (p, name);
+      p = frag_more (len);
+      memcpy (p, name, len);
 
       frag_align (2, 0, 0);
 
       subseg_set (seg, subseg);
     }
   else
-    {
-      as_bad (_("expected quoted string"));
-    }
+    as_bad (_("expected quoted string"));
+
   demand_empty_rest_of_line ();
 }
 
@@ -1684,6 +1694,9 @@ adjust_stab_sections (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
    this at the moment, so we do it ourselves.  We save the information
    in the symbol.  */
 
+#ifdef OBJ_MAYBE_ELF
+static
+#endif
 void
 elf_ecoff_set_ext (symbolS *sym, struct ecoff_extr *ext)
 {
@@ -1978,6 +1991,7 @@ elf_frob_file (void)
       bfd_set_section_size (stdoutput, s, size);
       s->contents = (unsigned char *) frag_more (size);
       frag_now->fr_fix = frag_now_fix_octets ();
+      frag_wane (frag_now);
     }
 
 #ifdef elf_tc_final_processing
diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h
index 7ff9ef09aa3c..29356ab3b06a 100644
--- a/gas/config/obj-elf.h
+++ b/gas/config/obj-elf.h
@@ -1,6 +1,6 @@
 /* ELF object file format.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-   2002, 2003, 2004 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -34,8 +34,6 @@
 #define OUTPUT_FLAVOR bfd_target_elf_flavour
 #endif
 
-#include "bfd.h"
-
 #define BYTES_IN_WORD 4		/* for now */
 #include "bfd/elf-bfd.h"
 
@@ -83,15 +81,13 @@ struct elf_obj_sy
 #define OBJ_SYMFIELD_TYPE struct elf_obj_sy
 
 /* Symbol fields used by the ELF back end.  */
-#define ELF_TARGET_SYMBOL_FIELDS int local:1;
+#define ELF_TARGET_SYMBOL_FIELDS unsigned int local:1;
 
 /* Don't change this; change ELF_TARGET_SYMBOL_FIELDS instead.  */
 #ifndef TARGET_SYMBOL_FIELDS
 #define TARGET_SYMBOL_FIELDS ELF_TARGET_SYMBOL_FIELDS
 #endif
 
-/* #include "targ-cpu.h" */
-
 #ifndef FALSE
 #define FALSE 0
 #define TRUE  !FALSE
@@ -134,13 +130,6 @@ int elf_s_get_other (symbolS *);
 
 extern asection *gdb_section;
 
-#ifndef obj_sec_set_private_data
-#define obj_sec_set_private_data(B, S) \
-  if (! BFD_SEND ((B), _new_section_hook, ((B), (S)))) \
-    as_fatal (_("can't allocate ELF private section data: %s"),	\
-	      bfd_errmsg (bfd_get_error ()))
-#endif
-
 #ifndef obj_frob_file
 #define obj_frob_file  elf_frob_file
 #endif
@@ -247,6 +236,7 @@ extern void elf_pop_insert (void);
 #endif
 
 #ifndef OBJ_MAYBE_ELF
+/* If OBJ_MAYBE_ELF then obj-multi.h will define obj_ecoff_set_ext.  */
 #define obj_ecoff_set_ext elf_ecoff_set_ext
 struct ecoff_extr;
 extern void elf_ecoff_set_ext (symbolS *, struct ecoff_extr *);
diff --git a/gas/config/obj-ieee.c b/gas/config/obj-ieee.c
deleted file mode 100644
index bac46757c131..000000000000
--- a/gas/config/obj-ieee.c
+++ /dev/null
@@ -1,613 +0,0 @@
-/* obj-format for ieee-695 records.
-   Copyright 1991, 1992, 1993, 1994, 1997, 2000, 2001, 2002, 2003, 2005
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-
-/* Created by Steve Chamberlain <steve@cygnus.com>.  */
-
-/* This will hopefully become the port through which bfd and gas talk,
-   for the moment, only ieee is known to work well.  */
-
-#include "bfd.h"
-#include "as.h"
-#include "subsegs.h"
-#include "output-file.h"
-#include "frags.h"
-
-bfd *abfd;
-
-/* How many addresses does the .align take?  */
-
-static relax_addressT
-relax_align (address, alignment)
-     /* Address now.  */
-     register relax_addressT address;
-
-     /* Alignment (binary).  */
-     register long alignment;
-{
-  relax_addressT mask;
-  relax_addressT new_address;
-
-  mask = ~((~0) << alignment);
-  new_address = (address + mask) & (~mask);
-  return (new_address - address);
-}
-
-/* Calculate the size of the frag chain
-   and create a bfd section to contain all of it.  */
-
-static void
-size_section (abfd, idx)
-     bfd *abfd;
-     unsigned int idx;
-{
-  asection *sec;
-  unsigned int size = 0;
-  fragS *frag = segment_info[idx].frag_root;
-
-  while (frag)
-    {
-      if (frag->fr_address != size)
-	{
-	  printf (_("Out of step\n"));
-	  size = frag->fr_address;
-	}
-      size += frag->fr_fix;
-      switch (frag->fr_type)
-	{
-	case rs_fill:
-	case rs_org:
-	  size += frag->fr_offset * frag->fr_var;
-	  break;
-	case rs_align:
-	case rs_align_code:
-	  {
-	    addressT off;
-
-	    off = relax_align (size, frag->fr_offset);
-	    if (frag->fr_subtype != 0 && off > frag->fr_subtype)
-	      off = 0;
-	    size += off;
-	  }
-	}
-      frag = frag->fr_next;
-    }
-  if (size)
-    {
-      char *name = segment_info[idx].name;
-
-      if (name == (char *) NULL)
-	name = ".data";
-
-      segment_info[idx].user_stuff =
-	(char *) (sec = bfd_make_section (abfd, name));
-      /* Make it output through itself.  */
-      sec->output_section = sec;
-      sec->flags |= SEC_HAS_CONTENTS;
-      bfd_set_section_size (abfd, sec, size);
-    }
-}
-
-/* Run through a frag chain and write out the data to go with it.  */
-
-static void
-fill_section (abfd, idx)
-     bfd *abfd;
-     unsigned int idx;
-{
-  asection *sec = segment_info[idx].user_stuff;
-
-  if (sec)
-    {
-      fragS *frag = segment_info[idx].frag_root;
-      unsigned int offset = 0;
-      while (frag)
-	{
-	  unsigned int fill_size;
-	  unsigned int count;
-	  switch (frag->fr_type)
-	    {
-	    case rs_fill:
-	    case rs_align:
-	    case rs_org:
-	      if (frag->fr_fix)
-		{
-		  bfd_set_section_contents (abfd,
-					    sec,
-					    frag->fr_literal,
-					    frag->fr_address,
-					    frag->fr_fix);
-		}
-	      offset += frag->fr_fix;
-	      fill_size = frag->fr_var;
-	      if (fill_size)
-		{
-		  unsigned int off = frag->fr_fix;
-		  for (count = frag->fr_offset; count; count--)
-		    {
-		      bfd_set_section_contents (abfd, sec,
-						frag->fr_literal +
-						frag->fr_fix,
-						frag->fr_address + off,
-						fill_size);
-		      off += fill_size;
-		    }
-		}
-	      break;
-	    default:
-	      abort ();
-	    }
-	  frag = frag->fr_next;
-	}
-    }
-}
-
-/* Count the relocations in a chain.  */
-
-static unsigned int
-count_entries_in_chain (idx)
-     unsigned int idx;
-{
-  unsigned int nrelocs;
-  fixS *fixup_ptr;
-
-  /* Count the relocations.  */
-  fixup_ptr = segment_info[idx].fix_root;
-  nrelocs = 0;
-  while (fixup_ptr != (fixS *) NULL)
-    {
-      fixup_ptr = fixup_ptr->fx_next;
-      nrelocs++;
-    }
-  return nrelocs;
-}
-
-/* Output all the relocations for a section.  */
-
-void
-do_relocs_for (idx)
-     unsigned int idx;
-{
-  unsigned int nrelocs;
-  arelent **reloc_ptr_vector;
-  arelent *reloc_vector;
-  asymbol **ptrs;
-  asection *section = (asection *) (segment_info[idx].user_stuff);
-  unsigned int i;
-  fixS *from;
-
-  if (section)
-    {
-      nrelocs = count_entries_in_chain (idx);
-
-      reloc_ptr_vector =
-	(arelent **) malloc ((nrelocs + 1) * sizeof (arelent *));
-      reloc_vector = (arelent *) malloc (nrelocs * sizeof (arelent));
-      ptrs = (asymbol **) malloc (nrelocs * sizeof (asymbol *));
-      from = segment_info[idx].fix_root;
-      for (i = 0; i < nrelocs; i++)
-	{
-	  arelent *to = reloc_vector + i;
-	  asymbol *s;
-	  reloc_ptr_vector[i] = to;
-	  to->howto = (reloc_howto_type *) (from->fx_r_type);
-
-	  s = &(from->fx_addsy->sy_symbol.sy);
-	  to->address = ((char *) (from->fx_frag->fr_address +
-				   from->fx_where))
-	    - ((char *) (&(from->fx_frag->fr_literal)));
-	  to->addend = from->fx_offset;
-	  /* If we know the symbol which we want to relocate to, turn
-	     this reloaction into a section relative.
-
-	     If this relocation is pcrelative, and we know the
-	     destination, we still want to keep the relocation - since
-	     the linker might relax some of the bytes, but it stops
-	     being pc relative and turns into an absolute relocation.  */
-	  if (s)
-	    {
-	      if ((s->flags & BSF_UNDEFINED) == 0)
-		{
-		  to->section = s->section;
-
-		  /* We can refer directly to the value field here,
-		     rather than using S_GET_VALUE, because this is
-		     only called after do_symbols, which sets up the
-		     value field.  */
-		  to->addend += s->value;
-
-		  to->sym_ptr_ptr = 0;
-		  if (to->howto->pcrel_offset)
-		    /* This is a pcrel relocation, the addend should
-		       be adjusted.  */
-		    to->addend -= to->address + 1;
-		}
-	      else
-		{
-		  to->section = 0;
-		  *ptrs = &(from->fx_addsy->sy_symbol.sy);
-		  to->sym_ptr_ptr = ptrs;
-
-		  if (to->howto->pcrel_offset)
-		    /* This is a pcrel relocation, the addend should
-		       be adjusted.  */
-		    to->addend -= to->address - 1;
-		}
-	    }
-	  else
-	    to->section = 0;
-
-	  ptrs++;
-	  from = from->fx_next;
-	}
-
-      /* Attach to the section.  */
-      section->orelocation = reloc_ptr_vector;
-      section->reloc_count = nrelocs;
-      section->flags |= SEC_LOAD;
-    }
-}
-
-/* Do the symbols.  */
-
-static void
-do_symbols (abfd)
-     bfd *abfd;
-{
-  extern symbolS *symbol_rootP;
-  symbolS *ptr;
-  asymbol **symbol_ptr_vec;
-  asymbol *symbol_vec;
-  unsigned int count = 0;
-  unsigned int index;
-
-  for (ptr = symbol_rootP;
-       ptr != (symbolS *) NULL;
-       ptr = ptr->sy_next)
-    {
-      if (SEG_NORMAL (ptr->sy_symbol.seg))
-	{
-	  ptr->sy_symbol.sy.section =
-	    (asection *) (segment_info[ptr->sy_symbol.seg].user_stuff);
-	  S_SET_VALUE (ptr, S_GET_VALUE (ptr));
-	  if (ptr->sy_symbol.sy.flags == 0)
-	    ptr->sy_symbol.sy.flags = BSF_LOCAL;
-	}
-      else
-	{
-	  switch (ptr->sy_symbol.seg)
-	    {
-	    case SEG_ABSOLUTE:
-	      ptr->sy_symbol.sy.flags |= BSF_ABSOLUTE;
-	      ptr->sy_symbol.sy.section = 0;
-	      break;
-	    case SEG_UNKNOWN:
-	      ptr->sy_symbol.sy.flags = BSF_UNDEFINED;
-	      ptr->sy_symbol.sy.section = 0;
-	      break;
-	    default:
-	      abort ();
-	    }
-	}
-      ptr->sy_symbol.sy.value = S_GET_VALUE (ptr);
-      count++;
-    }
-  symbol_ptr_vec = (asymbol **) malloc ((count + 1) * sizeof (asymbol *));
-
-  index = 0;
-  for (ptr = symbol_rootP;
-       ptr != (symbolS *) NULL;
-       ptr = ptr->sy_next)
-    {
-      symbol_ptr_vec[index] = &(ptr->sy_symbol.sy);
-      index++;
-    }
-  symbol_ptr_vec[index] = 0;
-  abfd->outsymbols = symbol_ptr_vec;
-  abfd->symcount = count;
-}
-
-/* The generic as->bfd converter. Other backends may have special case
-   code.  */
-
-void
-bfd_as_write_hook ()
-{
-  int i;
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    size_section (abfd, i);
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    fill_section (abfd, i);
-
-  do_symbols (abfd);
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    do_relocs_for (i);
-}
-
-S_SET_SEGMENT (x, y)
-     symbolS *x;
-     int y;
-{
-  x->sy_symbol.seg = y;
-}
-
-S_IS_DEFINED (x)
-     symbolS *x;
-{
-  if (SEG_NORMAL (x->sy_symbol.seg))
-    {
-      return 1;
-    }
-  switch (x->sy_symbol.seg)
-    {
-    case SEG_UNKNOWN:
-      return 0;
-    default:
-      abort ();
-    }
-}
-
-S_IS_EXTERNAL (x)
-{
-  abort ();
-}
-
-S_GET_DESC (x)
-{
-  abort ();
-}
-
-S_GET_SEGMENT (x)
-     symbolS *x;
-{
-  return x->sy_symbol.seg;
-}
-
-S_SET_EXTERNAL (x)
-     symbolS *x;
-{
-  x->sy_symbol.sy.flags |= BSF_GLOBAL | BSF_EXPORT;
-}
-
-S_SET_NAME (x, y)
-     symbolS *x;
-     char *y;
-{
-  x->sy_symbol.sy.name = y;
-}
-
-S_GET_OTHER (x)
-{
-  abort ();
-}
-
-S_IS_DEBUG (x)
-{
-  abort ();
-}
-
-#ifndef segment_name
-char *
-segment_name ()
-{
-  abort ();
-}
-#endif
-
-void
-obj_read_begin_hook ()
-{
-}
-
-static void
-obj_ieee_section (ignore)
-     int ignore;
-{
-  extern char *input_line_pointer;
-  extern char is_end_of_line[];
-  char *p = input_line_pointer;
-  char *s = p;
-  int i;
-
-  /* Look up the name, if it doesn't exist, make it.  */
-  while (*p && *p != ' ' && *p != ',' && !is_end_of_line[*p])
-    {
-      p++;
-    }
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      if (segment_info[i].hadone)
-	{
-	  if (strncmp (segment_info[i].name, s, p - s) == 0)
-	    goto ok;
-	}
-      else
-	break;
-    }
-  if (i == SEG_UNKNOWN)
-    {
-      as_bad (_("too many sections"));
-      return;
-    }
-
-  segment_info[i].hadone = 1;
-  segment_info[i].name = malloc (p - s + 1);
-  memcpy (segment_info[i].name, s, p - s);
-  segment_info[i].name[p - s] = 0;
-ok:
-  subseg_set (i, 0);
-  while (!is_end_of_line[*p])
-    p++;
-  input_line_pointer = p;
-}
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  {"section", obj_ieee_section, 0},
-  {"data.b" , cons            , 1},
-  {"data.w" , cons            , 2},
-  {"data.l" , cons            , 4},
-  {"export" , s_globl         , 0},
-  {"option" , s_ignore        , 0},
-  {"end"    , s_ignore        , 0},
-  {"import" , s_ignore        , 0},
-  {"sdata"  , stringer        , 0},
-  0,
-};
-
-void
-obj_symbol_new_hook (symbolP)
-     symbolS *symbolP;
-{
-  symbolP->sy_symbol.sy.the_bfd = abfd;
-}
-
-#if 1
-
-#ifndef SUB_SEGMENT_ALIGN
-#ifdef HANDLE_ALIGN
-/* The last subsegment gets an alignment corresponding to the alignment
-   of the section.  This allows proper nop-filling at the end of
-   code-bearing sections.  */
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)					\
-  (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
-   ? get_recorded_alignment (SEG) : 0)
-#else
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2
-#endif
-#endif
-
-extern void
-write_object_file ()
-{
-  int i;
-  struct frchain *frchain_ptr;
-  struct frag *frag_ptr;
-
-  abfd = bfd_openw (out_file_name, "ieee");
-
-  if (abfd == 0)
-    {
-      as_perror (_("FATAL: Can't create %s"), out_file_name);
-      exit (EXIT_FAILURE);
-    }
-  bfd_set_format (abfd, bfd_object);
-  bfd_set_arch_mach (abfd, bfd_arch_h8300, 0);
-  subseg_set (1, 0);
-  subseg_set (2, 0);
-  subseg_set (3, 0);
-
-  /* Run through all the sub-segments and align them up.  Also
-     close any open frags.  We tack a .fill onto the end of the
-     frag chain so that any .align's size can be worked by looking
-     at the next frag.  */
-  for (frchain_ptr = frchain_root;
-       frchain_ptr != (struct frchain *) NULL;
-       frchain_ptr = frchain_ptr->frch_next)
-    {
-      int alignment;
-
-      subseg_set (frchain_ptr->frch_seg, frchain_ptr->frch_subseg);
-
-      alignment = SUB_SEGMENT_ALIGN (now_seg, frchain_ptr)
-
-#ifdef md_do_align
-      md_do_align (alignment, (char *) NULL, 0, 0, alignment_done);
-#endif
-      if (subseg_text_p (now_seg))
-	frag_align_code (alignment, 0);
-      else
-	frag_align (alignment, 0, 0);
-
-#ifdef md_do_align
-    alignment_done:
-#endif
-
-      frag_wane (frag_now);
-      frag_now->fr_fix = 0;
-      know (frag_now->fr_next == NULL);
-    }
-
-  /* Now build one big frag chain for each segment, linked through
-     fr_next.  */
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      fragS **prev_frag_ptr_ptr;
-      struct frchain *next_frchain_ptr;
-
-      segment_info[i].frag_root = segment_info[i].frchainP->frch_root;
-    }
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    relax_segment (segment_info[i].frag_root, i);
-
-  /* Relaxation has completed.  Freeze all syms.  */
-  finalize_syms = 1;
-
-  /* Now the addresses of the frags are correct within the segment.  */
-
-  bfd_as_write_hook ();
-  bfd_close (abfd);
-}
-
-#endif
-
-H_SET_TEXT_SIZE (a, b)
-{
-  abort ();
-}
-
-H_GET_TEXT_SIZE ()
-{
-  abort ();
-}
-
-H_SET_BSS_SIZE ()
-{
-  abort ();
-}
-
-H_SET_STRING_SIZE ()
-{
-  abort ();
-}
-
-H_SET_RELOCATION_SIZE ()
-{
-  abort ();
-}
-
-H_SET_MAGIC_NUMBER ()
-{
-  abort ();
-}
-
-H_GET_FILE_SIZE ()
-{
-  abort ();
-}
-
-H_GET_TEXT_RELOCATION_SIZE ()
-{
-  abort ();
-}
diff --git a/gas/config/obj-ieee.h b/gas/config/obj-ieee.h
deleted file mode 100644
index 29654296e83f..000000000000
--- a/gas/config/obj-ieee.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* This file is obj-ieee.h
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2002, 2003
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-
-#include "bfd.h"
-
-typedef struct
-{
-  asymbol sy;
-  int seg;
-}
-obj_symbol_type;
-
-#define S_GET_NAME(s) (((s)->sy_symbol.sy.name))
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) (!SEG_NORMAL (x->sy_symbol.seg))
-
-typedef struct
-  {
-    int x;
-  }
-object_headers;
-
-int lineno_rootP;
-
-#define IEEE_STYLE
diff --git a/gas/config/obj-som.c b/gas/config/obj-som.c
index 571330efcb42..f41df58182b6 100644
--- a/gas/config/obj-som.c
+++ b/gas/config/obj-som.c
@@ -1,5 +1,5 @@
 /* SOM object file format.
-   Copyright 1993, 1994, 1998, 2000, 2002, 2003, 2004, 2005
+   Copyright 1993, 1994, 1998, 2000, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -150,12 +150,9 @@ obj_som_version (int unused ATTRIBUTE_UNUSED)
 
   version_seen = 1;
   if (!bfd_som_attach_aux_hdr (stdoutput, VERSION_AUX_ID, version))
-    {
-      bfd_perror (stdoutput->filename);
-      as_perror (_("FATAL: Attaching version header %s"),
-		 stdoutput->filename);
-      exit (EXIT_FAILURE);
-    }
+    as_fatal (_("attaching version header %s: %s"),
+	      stdoutput->filename, bfd_errmsg (bfd_get_error ()));
+
   *input_line_pointer = c;
   demand_empty_rest_of_line ();
 }
@@ -195,12 +192,9 @@ obj_som_copyright (int unused ATTRIBUTE_UNUSED)
 
   copyright_seen = 1;
   if (!bfd_som_attach_aux_hdr (stdoutput, COPYRIGHT_AUX_ID, copyright))
-    {
-      bfd_perror (stdoutput->filename);
-      as_perror (_("FATAL: Attaching copyright header %s"),
-		 stdoutput->filename);
-      exit (EXIT_FAILURE);
-    }
+    as_fatal (_("attaching copyright header %s: %s"),
+	      stdoutput->filename, bfd_errmsg (bfd_get_error ()));
+
   *input_line_pointer = c;
   demand_empty_rest_of_line ();
 }
diff --git a/gas/config/obj-som.h b/gas/config/obj-som.h
index 85f3f72bb404..16ca21e1c6e5 100644
--- a/gas/config/obj-som.h
+++ b/gas/config/obj-som.h
@@ -1,5 +1,5 @@
 /* SOM object file format.
-   Copyright 1993, 1994, 1995, 1998, 2000, 2004, 2005
+   Copyright 1993, 1994, 1995, 1998, 2000, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -27,7 +27,6 @@
 
 #define OBJ_SOM 1
 
-#include "bfd.h"
 #include "bfd/som.h"
 #include "targ-cpu.h"
 
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index 3765b08c73a5..e8f0bad55f34 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -1,6 +1,6 @@
 /* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU.
    Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
    Contributed by Carnegie Mellon University, 1993.
    Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
    Modified by Ken Raeburn for gas-2.x and ECOFF support.
@@ -2383,15 +2383,15 @@ emit_ustX (const expressionS *tok,
   newtok[2] = newtok[0];
   assemble_tokens ("or", newtok, 3, 1);
 
-  /* Emit "stq_u $t9, 0($at)".  */
-  set_tok_reg (newtok[0], AXP_REG_T9);
-  set_tok_const (newtok[1], 0);
-  set_tok_preg (newtok[2], AXP_REG_AT);
-  assemble_tokens ("stq_u", newtok, 3, 1);
-
   /* Emit "stq_u $t10, size-1($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_const (newtok[1], (1 << lgsize) - 1);
+  set_tok_preg (newtok[2], AXP_REG_AT);
+  assemble_tokens ("stq_u", newtok, 3, 1);
+
+  /* Emit "stq_u $t9, 0($at)".  */
+  set_tok_reg (newtok[0], AXP_REG_T9);
+  set_tok_const (newtok[1], 0);
   assemble_tokens ("stq_u", newtok, 3, 1);
 }
 
diff --git a/gas/config/tc-alpha.h b/gas/config/tc-alpha.h
index 42e004e41482..d28ab9ff35a5 100644
--- a/gas/config/tc-alpha.h
+++ b/gas/config/tc-alpha.h
@@ -1,6 +1,6 @@
 /* This file is tc-alpha.h
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   2005
+   2005, 2006
    Free Software Foundation, Inc.
    Written by Ken Raeburn <raeburn@cygnus.com>.
 
@@ -180,4 +180,4 @@ extern void alpha_cfi_frame_initial_instructions (void);
 
 #define DWARF2_LINE_MIN_INSN_LENGTH	4
 #define DWARF2_DEFAULT_RETURN_COLUMN	26
-#define DWARF2_CIE_DATA_ALIGNMENT	-8
+#define DWARF2_CIE_DATA_ALIGNMENT	(-8)
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 525b54083fb9..490f327efd4c 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -20,8 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
-#include "libiberty.h"
 #include "as.h"
 #include "struc-symbol.h"
 #include "safe-ctype.h"
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ae420b353471..ac88be63c458 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1,6 +1,6 @@
 /* tc-arm.c -- Assemble for the ARM
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005
+   2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -25,28 +25,24 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <string.h>
+#include <limits.h>
+#include <stdarg.h>
 #define	 NO_RELOC 0
 #include "as.h"
 #include "safe-ctype.h"
-
-/* Need TARGET_CPU.  */
-#include "config.h"
 #include "subsegs.h"
 #include "obstack.h"
-#include "symbols.h"
-#include "listing.h"
 
 #include "opcode/arm.h"
 
 #ifdef OBJ_ELF
 #include "elf/arm.h"
-#include "dwarf2dbg.h"
 #include "dw2gencfi.h"
 #endif
 
-/* XXX Set this to 1 after the next binutils release.  */
-#define WARN_DEPRECATED 0
+#include "dwarf2dbg.h"
+
+#define WARN_DEPRECATED 1
 
 #ifdef OBJ_ELF
 /* Must be at least the size of the largest unwind opcode (currently two).  */
@@ -90,6 +86,15 @@ static unsigned int marked_pr_dependency = 0;
 
 #endif /* OBJ_ELF */
 
+/* Results from operand parsing worker functions.  */
+
+typedef enum
+{
+  PARSE_OPERAND_SUCCESS,
+  PARSE_OPERAND_FAIL,
+  PARSE_OPERAND_FAIL_NO_BACKTRACK
+} parse_operand_result;
+
 enum arm_float_abi
 {
   ARM_FLOAT_ABI_HARD,
@@ -150,11 +155,14 @@ static const arm_feature_set *mcpu_fpu_opt = NULL;
 static const arm_feature_set *march_cpu_opt = NULL;
 static const arm_feature_set *march_fpu_opt = NULL;
 static const arm_feature_set *mfpu_opt = NULL;
+static const arm_feature_set *object_arch = NULL;
 
 /* Constants for known architecture features.  */
 static const arm_feature_set fpu_default = FPU_DEFAULT;
 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
+static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
+static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
@@ -194,6 +202,8 @@ static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
 
+static const arm_feature_set arm_cext_iwmmxt2 =
+  ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
 static const arm_feature_set arm_cext_iwmmxt =
   ARM_FEATURE (0, ARM_CEXT_IWMMXT);
 static const arm_feature_set arm_cext_xscale =
@@ -206,6 +216,10 @@ static const arm_feature_set fpu_vfp_ext_v1xd =
   ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
+static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
+static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
+static const arm_feature_set fpu_vfp_v3_or_neon_ext =
+  ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
 
 static int mfloat_abi_opt = -1;
 /* Record user cpu selection for object attributes.  */
@@ -218,6 +232,12 @@ static int meabi_flags = EABI_DEFAULT;
 # else
 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
 # endif
+
+bfd_boolean
+arm_is_eabi(void)
+{
+  return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
+}
 #endif
 
 #ifdef OBJ_ELF
@@ -256,6 +276,31 @@ static int thumb_mode = 0;
 
 static bfd_boolean unified_syntax = FALSE;
 
+enum neon_el_type
+{
+  NT_invtype,
+  NT_untyped,
+  NT_integer,
+  NT_float,
+  NT_poly,
+  NT_signed,
+  NT_unsigned
+};
+
+struct neon_type_el
+{
+  enum neon_el_type type;
+  unsigned size;
+};
+
+#define NEON_MAX_TYPE_ELS 4
+
+struct neon_type
+{
+  struct neon_type_el el[NEON_MAX_TYPE_ELS];
+  unsigned elems;
+};
+
 struct arm_it
 {
   const char *	error;
@@ -263,6 +308,11 @@ struct arm_it
   int		size;
   int		size_req;
   int		cond;
+  /* "uncond_value" is set to the value in place of the conditional field in
+     unconditional versions of the instruction, or -1 if nothing is
+     appropriate.  */
+  int		uncond_value;
+  struct neon_type vectype;
   /* Set to the opcode if the instruction needs relaxation.
      Zero if the instruction is not relaxed.  */
   unsigned long	relax;
@@ -277,9 +327,19 @@ struct arm_it
   {
     unsigned reg;
     signed int imm;
+    struct neon_type_el vectype;
     unsigned present	: 1;  /* Operand present.  */
     unsigned isreg	: 1;  /* Operand was a register.  */
     unsigned immisreg	: 1;  /* .imm field is a second register.  */
+    unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
+    unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
+    unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */
+    /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
+       instructions. This allows us to disambiguate ARM <-> vector insns.  */
+    unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
+    unsigned isvec      : 1;  /* Is a single, double or quad VFP/Neon reg.  */
+    unsigned isquad     : 1;  /* Operand is Neon quad-precision register.  */
+    unsigned issingle   : 1;  /* Operand is VFP single-precision register.  */
     unsigned hasreloc	: 1;  /* Operand has relocation suffix.  */
     unsigned writeback	: 1;  /* Operand has trailing !  */
     unsigned preind	: 1;  /* Preindexed address.  */
@@ -355,9 +415,10 @@ struct reloc_entry
   bfd_reloc_code_real_type reloc;
 };
 
-enum vfp_sp_reg_pos
+enum vfp_reg_pos
 {
-  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
+  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
+  VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
 };
 
 enum vfp_ldstm_type
@@ -365,6 +426,17 @@ enum vfp_ldstm_type
   VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
 };
 
+/* Bits for DEFINED field in neon_typed_alias.  */
+#define NTA_HASTYPE  1
+#define NTA_HASINDEX 2
+
+struct neon_typed_alias
+{
+  unsigned char defined;
+  unsigned char index;
+  struct neon_type_el eltype;
+};
+
 /* ARM register categories.  This includes coprocessor numbers and various
    architecture extensions' registers.	*/
 enum arm_reg_type
@@ -375,6 +447,10 @@ enum arm_reg_type
   REG_TYPE_FN,
   REG_TYPE_VFS,
   REG_TYPE_VFD,
+  REG_TYPE_NQ,
+  REG_TYPE_VFSD,
+  REG_TYPE_NDQ,
+  REG_TYPE_NSDQ,
   REG_TYPE_VFC,
   REG_TYPE_MVF,
   REG_TYPE_MVD,
@@ -388,13 +464,17 @@ enum arm_reg_type
   REG_TYPE_XSCALE,
 };
 
-/* Structure for a hash table entry for a register.  */
+/* Structure for a hash table entry for a register.
+   If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
+   information which states whether a vector type or index is specified (for a
+   register alias created with .dn or .qn). Otherwise NEON should be NULL.  */
 struct reg_entry
 {
-  const char   *name;
-  unsigned char number;
-  unsigned char type;
-  unsigned char builtin;
+  const char        *name;
+  unsigned char      number;
+  unsigned char      type;
+  unsigned char      builtin;
+  struct neon_typed_alias *neon;
 };
 
 /* Diagnostics used when we don't get a register of the expected type.	*/
@@ -405,7 +485,11 @@ const char *const reg_expected_msgs[] =
   N_("co-processor register expected"),
   N_("FPA register expected"),
   N_("VFP single precision register expected"),
-  N_("VFP double precision register expected"),
+  N_("VFP/Neon double precision register expected"),
+  N_("Neon quad precision register expected"),
+  N_("VFP single or double precision register expected"),
+  N_("Neon double or quad precision register expected"),
+  N_("VFP single, double or Neon quad precision register expected"),
   N_("VFP system register expected"),
   N_("Maverick MVF register expected"),
   N_("Maverick MVD register expected"),
@@ -465,11 +549,14 @@ struct asm_opcode
 #define INDEX_UP	0x00800000
 #define WRITE_BACK	0x00200000
 #define LDM_TYPE_2_OR_3	0x00400000
+#define CPSI_MMOD	0x00020000
 
 #define LITERAL_MASK	0xf000f000
 #define OPCODE_MASK	0xfe1fffff
 #define V4_STR_BIT	0x00000020
 
+#define T2_SUBS_PC_LR	0xf3de8f00
+
 #define DATA_OP_SHIFT	21
 
 #define T2_OPCODE_MASK	0xfe1fffff
@@ -571,6 +658,7 @@ struct asm_opcode
 #define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
 #define BAD_BRANCH	_("branch must be last instruction in IT block")
 #define BAD_NOT_IT	_("instruction not allowed in IT block")
+#define BAD_FPU		_("selected FPU does not support instruction")
 
 static struct hash_control *arm_ops_hsh;
 static struct hash_control *arm_cond_hsh;
@@ -691,6 +779,9 @@ static int in_my_get_expression = 0;
 #define GE_NO_PREFIX 0
 #define GE_IMM_PREFIX 1
 #define GE_OPT_PREFIX 2
+/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
+   immediates, as can be used in Neon VMVN and VMOV immediate instructions.  */
+#define GE_OPT_PREFIX_BIG 3
 
 static int
 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
@@ -700,7 +791,8 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
 
   /* In unified syntax, all prefixes are optional.  */
   if (unified_syntax)
-    prefix_mode = GE_OPT_PREFIX;
+    prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
+                  : GE_OPT_PREFIX;
 
   switch (prefix_mode)
     {
@@ -714,6 +806,7 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
       (*str)++;
       break;
     case GE_OPT_PREFIX:
+    case GE_OPT_PREFIX_BIG:
       if (is_immediate_prefix (**str))
 	(*str)++;
       break;
@@ -755,11 +848,12 @@ my_get_expression (expressionS * ep, char ** str, int prefix_mode)
   /* Get rid of any bignums now, so that we don't generate an error for which
      we can't establish a line number later on.	 Big numbers are never valid
      in instructions, which is where this routine is always called.  */
-  if (ep->X_op == O_big
-      || (ep->X_add_symbol
-	  && (walk_no_bignums (ep->X_add_symbol)
-	      || (ep->X_op_symbol
-		  && walk_no_bignums (ep->X_op_symbol)))))
+  if (prefix_mode != GE_OPT_PREFIX_BIG
+      && (ep->X_op == O_big
+          || (ep->X_add_symbol
+	      && (walk_no_bignums (ep->X_add_symbol)
+	          || (ep->X_op_symbol
+		      && walk_no_bignums (ep->X_op_symbol))))))
     {
       inst.error = _("invalid constant");
       *str = input_line_pointer;
@@ -939,18 +1033,10 @@ arm_reg_parse_multi (char **ccp)
   return reg;
 }
 
-/* As above, but the register must be of type TYPE, and the return
-   value is the register number or FAIL.  */
-
 static int
-arm_reg_parse (char **ccp, enum arm_reg_type type)
+arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
+                    enum arm_reg_type type)
 {
-  char *start = *ccp;
-  struct reg_entry *reg = arm_reg_parse_multi (ccp);
-
-  if (reg && reg->type == type)
-    return reg->number;
-
   /* Alternative syntaxes are accepted for a few register classes.  */
   switch (type)
     {
@@ -982,10 +1068,354 @@ arm_reg_parse (char **ccp, enum arm_reg_type type)
       break;
     }
 
+  return FAIL;
+}
+
+/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
+   return value is the register number or FAIL.  */
+
+static int
+arm_reg_parse (char **ccp, enum arm_reg_type type)
+{
+  char *start = *ccp;
+  struct reg_entry *reg = arm_reg_parse_multi (ccp);
+  int ret;
+
+  /* Do not allow a scalar (reg+index) to parse as a register.  */
+  if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
+    return FAIL;
+
+  if (reg && reg->type == type)
+    return reg->number;
+
+  if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
+    return ret;
+
   *ccp = start;
   return FAIL;
 }
 
+/* Parse a Neon type specifier. *STR should point at the leading '.'
+   character. Does no verification at this stage that the type fits the opcode
+   properly. E.g.,
+
+     .i32.i32.s16
+     .s32.f32
+     .u16
+
+   Can all be legally parsed by this function.
+
+   Fills in neon_type struct pointer with parsed information, and updates STR
+   to point after the parsed type specifier. Returns SUCCESS if this was a legal
+   type, FAIL if not.  */
+
+static int
+parse_neon_type (struct neon_type *type, char **str)
+{
+  char *ptr = *str;
+
+  if (type)
+    type->elems = 0;
+
+  while (type->elems < NEON_MAX_TYPE_ELS)
+    {
+      enum neon_el_type thistype = NT_untyped;
+      unsigned thissize = -1u;
+
+      if (*ptr != '.')
+	break;
+
+      ptr++;
+
+      /* Just a size without an explicit type.  */
+      if (ISDIGIT (*ptr))
+	goto parsesize;
+
+      switch (TOLOWER (*ptr))
+	{
+	case 'i': thistype = NT_integer; break;
+	case 'f': thistype = NT_float; break;
+	case 'p': thistype = NT_poly; break;
+	case 's': thistype = NT_signed; break;
+	case 'u': thistype = NT_unsigned; break;
+        case 'd':
+          thistype = NT_float;
+          thissize = 64;
+          ptr++;
+          goto done;
+	default:
+	  as_bad (_("unexpected character `%c' in type specifier"), *ptr);
+	  return FAIL;
+	}
+
+      ptr++;
+
+      /* .f is an abbreviation for .f32.  */
+      if (thistype == NT_float && !ISDIGIT (*ptr))
+	thissize = 32;
+      else
+	{
+	parsesize:
+	  thissize = strtoul (ptr, &ptr, 10);
+
+	  if (thissize != 8 && thissize != 16 && thissize != 32
+              && thissize != 64)
+            {
+              as_bad (_("bad size %d in type specifier"), thissize);
+	      return FAIL;
+	    }
+	}
+
+      done:
+      if (type)
+        {
+          type->el[type->elems].type = thistype;
+	  type->el[type->elems].size = thissize;
+	  type->elems++;
+	}
+    }
+
+  /* Empty/missing type is not a successful parse.  */
+  if (type->elems == 0)
+    return FAIL;
+
+  *str = ptr;
+
+  return SUCCESS;
+}
+
+/* Errors may be set multiple times during parsing or bit encoding
+   (particularly in the Neon bits), but usually the earliest error which is set
+   will be the most meaningful. Avoid overwriting it with later (cascading)
+   errors by calling this function.  */
+
+static void
+first_error (const char *err)
+{
+  if (!inst.error)
+    inst.error = err;
+}
+
+/* Parse a single type, e.g. ".s32", leading period included.  */
+static int
+parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
+{
+  char *str = *ccp;
+  struct neon_type optype;
+
+  if (*str == '.')
+    {
+      if (parse_neon_type (&optype, &str) == SUCCESS)
+        {
+          if (optype.elems == 1)
+            *vectype = optype.el[0];
+          else
+            {
+              first_error (_("only one type should be specified for operand"));
+              return FAIL;
+            }
+        }
+      else
+        {
+          first_error (_("vector type expected"));
+          return FAIL;
+        }
+    }
+  else
+    return FAIL;
+  
+  *ccp = str;
+  
+  return SUCCESS;
+}
+
+/* Special meanings for indices (which have a range of 0-7), which will fit into
+   a 4-bit integer.  */
+
+#define NEON_ALL_LANES		15
+#define NEON_INTERLEAVE_LANES	14
+
+/* Parse either a register or a scalar, with an optional type. Return the
+   register number, and optionally fill in the actual type of the register
+   when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
+   type/index information in *TYPEINFO.  */
+
+static int
+parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
+                           enum arm_reg_type *rtype,
+                           struct neon_typed_alias *typeinfo)
+{
+  char *str = *ccp;
+  struct reg_entry *reg = arm_reg_parse_multi (&str);
+  struct neon_typed_alias atype;
+  struct neon_type_el parsetype;
+
+  atype.defined = 0;
+  atype.index = -1;
+  atype.eltype.type = NT_invtype;
+  atype.eltype.size = -1;
+
+  /* Try alternate syntax for some types of register. Note these are mutually
+     exclusive with the Neon syntax extensions.  */
+  if (reg == NULL)
+    {
+      int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
+      if (altreg != FAIL)
+        *ccp = str;
+      if (typeinfo)
+        *typeinfo = atype;
+      return altreg;
+    }
+
+  /* Undo polymorphism when a set of register types may be accepted.  */
+  if ((type == REG_TYPE_NDQ
+       && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
+      || (type == REG_TYPE_VFSD
+          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
+      || (type == REG_TYPE_NSDQ
+          && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
+              || reg->type == REG_TYPE_NQ))
+      || (type == REG_TYPE_MMXWC
+	  && (reg->type == REG_TYPE_MMXWCG)))
+    type = reg->type;
+
+  if (type != reg->type)
+    return FAIL;
+
+  if (reg->neon)
+    atype = *reg->neon;
+  
+  if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
+    {
+      if ((atype.defined & NTA_HASTYPE) != 0)
+        {
+          first_error (_("can't redefine type for operand"));
+          return FAIL;
+        }
+      atype.defined |= NTA_HASTYPE;
+      atype.eltype = parsetype;
+    }
+    
+  if (skip_past_char (&str, '[') == SUCCESS)
+    {
+      if (type != REG_TYPE_VFD)
+        {
+          first_error (_("only D registers may be indexed"));
+          return FAIL;
+        }
+    
+      if ((atype.defined & NTA_HASINDEX) != 0)
+        {
+          first_error (_("can't change index for operand"));
+          return FAIL;
+        }
+
+      atype.defined |= NTA_HASINDEX;
+
+      if (skip_past_char (&str, ']') == SUCCESS)
+        atype.index = NEON_ALL_LANES;
+      else
+        {
+          expressionS exp;
+
+          my_get_expression (&exp, &str, GE_NO_PREFIX);
+
+          if (exp.X_op != O_constant)
+            {
+              first_error (_("constant expression required"));
+              return FAIL;
+            }
+
+          if (skip_past_char (&str, ']') == FAIL)
+            return FAIL;
+
+          atype.index = exp.X_add_number;
+        }
+    }
+  
+  if (typeinfo)
+    *typeinfo = atype;
+  
+  if (rtype)
+    *rtype = type;
+  
+  *ccp = str;
+  
+  return reg->number;
+}
+
+/* Like arm_reg_parse, but allow allow the following extra features:
+    - If RTYPE is non-zero, return the (possibly restricted) type of the
+      register (e.g. Neon double or quad reg when either has been requested).
+    - If this is a Neon vector type with additional type information, fill
+      in the struct pointed to by VECTYPE (if non-NULL).
+   This function will fault on encountering a scalar.
+*/
+
+static int
+arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
+                     enum arm_reg_type *rtype, struct neon_type_el *vectype)
+{
+  struct neon_typed_alias atype;
+  char *str = *ccp;
+  int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
+
+  if (reg == FAIL)
+    return FAIL;
+
+  /* Do not allow a scalar (reg+index) to parse as a register.  */
+  if ((atype.defined & NTA_HASINDEX) != 0)
+    {
+      first_error (_("register operand expected, but got scalar"));
+      return FAIL;
+    }
+
+  if (vectype)
+    *vectype = atype.eltype;
+
+  *ccp = str;
+
+  return reg;
+}
+
+#define NEON_SCALAR_REG(X)	((X) >> 4)
+#define NEON_SCALAR_INDEX(X)	((X) & 15)
+
+/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
+   have enough information to be able to do a good job bounds-checking. So, we
+   just do easy checks here, and do further checks later.  */
+
+static int
+parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
+{
+  int reg;
+  char *str = *ccp;
+  struct neon_typed_alias atype;
+  
+  reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
+  
+  if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
+    return FAIL;
+  
+  if (atype.index == NEON_ALL_LANES)
+    {
+      first_error (_("scalar must have an index"));
+      return FAIL;
+    }
+  else if (atype.index >= 64 / elsize)
+    {
+      first_error (_("scalar index out of range"));
+      return FAIL;
+    }
+  
+  if (type)
+    *type = atype.eltype;
+  
+  *ccp = str;
+  
+  return reg * 16 + atype.index;
+}
+
 /* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
 static long
 parse_reg_list (char ** strp)
@@ -1011,7 +1441,7 @@ parse_reg_list (char ** strp)
 
 	      if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
 		{
-		  inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+		  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
 		  return FAIL;
 		}
 
@@ -1021,7 +1451,7 @@ parse_reg_list (char ** strp)
 
 		  if (reg <= cur_reg)
 		    {
-		      inst.error = _("bad range in register list");
+		      first_error (_("bad range in register list"));
 		      return FAIL;
 		    }
 
@@ -1052,7 +1482,7 @@ parse_reg_list (char ** strp)
 
 	  if (*str++ != '}')
 	    {
-	      inst.error = _("missing `}'");
+	      first_error (_("missing `}'"));
 	      return FAIL;
 	    }
 	}
@@ -1111,55 +1541,117 @@ parse_reg_list (char ** strp)
   return range;
 }
 
+/* Types of registers in a list.  */
+
+enum reg_list_els
+{
+  REGLIST_VFP_S,
+  REGLIST_VFP_D,
+  REGLIST_NEON_D
+};
+
 /* Parse a VFP register list.  If the string is invalid return FAIL.
    Otherwise return the number of registers, and set PBASE to the first
-   register.  Double precision registers are matched if DP is nonzero.	*/
+   register.  Parses registers of type ETYPE.
+   If REGLIST_NEON_D is used, several syntax enhancements are enabled:
+     - Q registers can be used to specify pairs of D registers
+     - { } can be omitted from around a singleton register list
+         FIXME: This is not implemented, as it would require backtracking in
+         some cases, e.g.:
+           vtbl.8 d3,d4,d5
+         This could be done (the meaning isn't really ambiguous), but doesn't
+         fit in well with the current parsing framework.
+     - 32 D registers may be used (also true for VFPv3).
+   FIXME: Types are ignored in these register lists, which is probably a
+   bug.  */
 
 static int
-parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
+parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
 {
+  char *str = *ccp;
   int base_reg;
   int new_base;
-  int regtype;
-  int max_regs;
+  enum arm_reg_type regtype = 0;
+  int max_regs = 0;
   int count = 0;
   int warned = 0;
   unsigned long mask = 0;
   int i;
 
-  if (**str != '{')
-    return FAIL;
+  if (*str != '{')
+    {
+      inst.error = _("expecting {");
+      return FAIL;
+    }
 
-  (*str)++;
+  str++;
 
-  if (dp)
+  switch (etype)
     {
+    case REGLIST_VFP_S:
+      regtype = REG_TYPE_VFS;
+      max_regs = 32;
+      break;
+    
+    case REGLIST_VFP_D:
       regtype = REG_TYPE_VFD;
-      max_regs = 16;
+      break;
+    
+    case REGLIST_NEON_D:
+      regtype = REG_TYPE_NDQ;
+      break;
     }
-  else
+
+  if (etype != REGLIST_VFP_S)
     {
-      regtype = REG_TYPE_VFS;
-      max_regs = 32;
+      /* VFPv3 allows 32 D registers.  */
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+        {
+          max_regs = 32;
+          if (thumb_mode)
+            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+                                    fpu_vfp_ext_v3);
+          else
+            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
+                                    fpu_vfp_ext_v3);
+        }
+      else
+        max_regs = 16;
     }
 
   base_reg = max_regs;
 
   do
     {
-      new_base = arm_reg_parse (str, regtype);
+      int setmask = 1, addregs = 1;
+
+      new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
+
       if (new_base == FAIL)
 	{
-	  inst.error = gettext (reg_expected_msgs[regtype]);
+	  first_error (_(reg_expected_msgs[regtype]));
 	  return FAIL;
 	}
+ 
+      if (new_base >= max_regs)
+        {
+          first_error (_("register out of range in list"));
+          return FAIL;
+        }
+ 
+      /* Note: a value of 2 * n is returned for the register Q<n>.  */
+      if (regtype == REG_TYPE_NQ)
+        {
+          setmask = 3;
+          addregs = 2;
+        }
 
       if (new_base < base_reg)
 	base_reg = new_base;
 
-      if (mask & (1 << new_base))
+      if (mask & (setmask << new_base))
 	{
-	  inst.error = _("invalid register list");
+	  first_error (_("invalid register list"));
 	  return FAIL;
 	}
 
@@ -1169,43 +1661,53 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
 	  warned = 1;
 	}
 
-      mask |= 1 << new_base;
-      count++;
+      mask |= setmask << new_base;
+      count += addregs;
 
-      if (**str == '-') /* We have the start of a range expression */
+      if (*str == '-') /* We have the start of a range expression */
 	{
 	  int high_range;
 
-	  (*str)++;
+	  str++;
 
-	  if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
+	  if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
+              == FAIL)
 	    {
 	      inst.error = gettext (reg_expected_msgs[regtype]);
 	      return FAIL;
 	    }
 
+          if (high_range >= max_regs)
+            {
+              first_error (_("register out of range in list"));
+              return FAIL;
+            }
+
+          if (regtype == REG_TYPE_NQ)
+            high_range = high_range + 1;
+
 	  if (high_range <= new_base)
 	    {
 	      inst.error = _("register range not in ascending order");
 	      return FAIL;
 	    }
 
-	  for (new_base++; new_base <= high_range; new_base++)
+	  for (new_base += addregs; new_base <= high_range; new_base += addregs)
 	    {
-	      if (mask & (1 << new_base))
+	      if (mask & (setmask << new_base))
 		{
 		  inst.error = _("invalid register list");
 		  return FAIL;
 		}
 
-	      mask |= 1 << new_base;
-	      count++;
+	      mask |= setmask << new_base;
+	      count += addregs;
 	    }
 	}
     }
-  while (skip_past_comma (str) != FAIL);
+  while (skip_past_comma (&str) != FAIL);
 
-  (*str)++;
+  str++;
 
   /* Sanity check -- should have raised a parse error above.  */
   if (count == 0 || count > max_regs)
@@ -1224,9 +1726,204 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
 	}
     }
 
+  *ccp = str;
+
   return count;
 }
 
+/* True if two alias types are the same.  */
+
+static int
+neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
+{
+  if (!a && !b)
+    return 1;
+    
+  if (!a || !b)
+    return 0;
+
+  if (a->defined != b->defined)
+    return 0;
+  
+  if ((a->defined & NTA_HASTYPE) != 0
+      && (a->eltype.type != b->eltype.type
+          || a->eltype.size != b->eltype.size))
+    return 0;
+
+  if ((a->defined & NTA_HASINDEX) != 0
+      && (a->index != b->index))
+    return 0;
+  
+  return 1;
+}
+
+/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
+   The base register is put in *PBASE.
+   The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
+   the return value.
+   The register stride (minus one) is put in bit 4 of the return value.
+   Bits [6:5] encode the list length (minus one).
+   The type of the list elements is put in *ELTYPE, if non-NULL.  */
+
+#define NEON_LANE(X)		((X) & 0xf)
+#define NEON_REG_STRIDE(X)	((((X) >> 4) & 1) + 1)
+#define NEON_REGLIST_LENGTH(X)	((((X) >> 5) & 3) + 1)
+
+static int
+parse_neon_el_struct_list (char **str, unsigned *pbase,
+                           struct neon_type_el *eltype)
+{
+  char *ptr = *str;
+  int base_reg = -1;
+  int reg_incr = -1;
+  int count = 0;
+  int lane = -1;
+  int leading_brace = 0;
+  enum arm_reg_type rtype = REG_TYPE_NDQ;
+  int addregs = 1;
+  const char *const incr_error = "register stride must be 1 or 2";
+  const char *const type_error = "mismatched element/structure types in list";
+  struct neon_typed_alias firsttype;
+  
+  if (skip_past_char (&ptr, '{') == SUCCESS)
+    leading_brace = 1;
+  
+  do
+    {
+      struct neon_typed_alias atype;
+      int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
+
+      if (getreg == FAIL)
+        {
+          first_error (_(reg_expected_msgs[rtype]));
+          return FAIL;
+        }
+      
+      if (base_reg == -1)
+        {
+          base_reg = getreg;
+          if (rtype == REG_TYPE_NQ)
+            {
+              reg_incr = 1;
+              addregs = 2;
+            }
+          firsttype = atype;
+        }
+      else if (reg_incr == -1)
+        {
+          reg_incr = getreg - base_reg;
+          if (reg_incr < 1 || reg_incr > 2)
+            {
+              first_error (_(incr_error));
+              return FAIL;
+            }
+        }
+      else if (getreg != base_reg + reg_incr * count)
+        {
+          first_error (_(incr_error));
+          return FAIL;
+        }
+
+      if (!neon_alias_types_same (&atype, &firsttype))
+        {
+          first_error (_(type_error));
+          return FAIL;
+        }
+      
+      /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
+         modes.  */
+      if (ptr[0] == '-')
+        {
+          struct neon_typed_alias htype;
+          int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
+          if (lane == -1)
+            lane = NEON_INTERLEAVE_LANES;
+          else if (lane != NEON_INTERLEAVE_LANES)
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+          if (reg_incr == -1)
+            reg_incr = 1;
+          else if (reg_incr != 1)
+            {
+              first_error (_("don't use Rn-Rm syntax with non-unit stride"));
+              return FAIL;
+            }
+          ptr++;
+          hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
+          if (hireg == FAIL)
+            {
+              first_error (_(reg_expected_msgs[rtype]));
+              return FAIL;
+            }
+          if (!neon_alias_types_same (&htype, &firsttype))
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+          count += hireg + dregs - getreg;
+          continue;
+        }
+      
+      /* If we're using Q registers, we can't use [] or [n] syntax.  */
+      if (rtype == REG_TYPE_NQ)
+        {
+          count += 2;
+          continue;
+        }
+      
+      if ((atype.defined & NTA_HASINDEX) != 0)
+        {
+          if (lane == -1)
+            lane = atype.index;
+          else if (lane != atype.index)
+            {
+              first_error (_(type_error));
+              return FAIL;
+            }
+        }
+      else if (lane == -1)
+        lane = NEON_INTERLEAVE_LANES;
+      else if (lane != NEON_INTERLEAVE_LANES)
+        {
+          first_error (_(type_error));
+          return FAIL;
+        }
+      count++;
+    }
+  while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
+  
+  /* No lane set by [x]. We must be interleaving structures.  */
+  if (lane == -1)
+    lane = NEON_INTERLEAVE_LANES;
+  
+  /* Sanity check.  */
+  if (lane == -1 || base_reg == -1 || count < 1 || count > 4
+      || (count > 1 && reg_incr == -1))
+    {
+      first_error (_("error parsing element/structure list"));
+      return FAIL;
+    }
+
+  if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
+    {
+      first_error (_("expected }"));
+      return FAIL;
+    }
+  
+  if (reg_incr == -1)
+    reg_incr = 1;
+
+  if (eltype)
+    *eltype = firsttype.eltype;
+
+  *pbase = base_reg;
+  *str = ptr;
+  
+  return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
+}
+
 /* Parse an explicit relocation suffix on an expression.  This is
    either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
    arm_reloc_hsh contains no entries, so this function can only
@@ -1258,7 +1955,7 @@ parse_reloc (char **str)
 
 /* Directives: register aliases.  */
 
-static void
+static struct reg_entry *
 insert_reg_alias (char *str, int number, int type)
 {
   struct reg_entry *new;
@@ -1274,7 +1971,7 @@ insert_reg_alias (char *str, int number, int type)
       else if (new->number != number || new->type != type)
 	as_warn (_("ignoring redefinition of register alias '%s'"), str);
 
-      return;
+      return 0;
     }
 
   name = xstrdup (str);
@@ -1284,9 +1981,31 @@ insert_reg_alias (char *str, int number, int type)
   new->number = number;
   new->type = type;
   new->builtin = FALSE;
+  new->neon = NULL;
 
   if (hash_insert (arm_reg_hsh, name, (PTR) new))
     abort ();
+  
+  return new;
+}
+
+static void
+insert_neon_reg_alias (char *str, int number, int type,
+                       struct neon_typed_alias *atype)
+{
+  struct reg_entry *reg = insert_reg_alias (str, number, type);
+  
+  if (!reg)
+    {
+      first_error (_("attempt to redefine typed alias"));
+      return;
+    }
+  
+  if (atype)
+    {
+      reg->neon = xmalloc (sizeof (struct neon_typed_alias));
+      *reg->neon = *atype;
+    }
 }
 
 /* Look for the .req directive.	 This is of the form:
@@ -1354,6 +2073,148 @@ create_register_alias (char * newname, char *p)
   return 1;
 }
 
+/* Create a Neon typed/indexed register alias using directives, e.g.:
+     X .dn d5.s32[1]
+     Y .qn 6.s16
+     Z .dn d7
+     T .dn Z[0]
+   These typed registers can be used instead of the types specified after the
+   Neon mnemonic, so long as all operands given have types. Types can also be
+   specified directly, e.g.:
+     vadd d0.s32, d1.s32, d2.s32
+*/
+
+static int
+create_neon_reg_alias (char *newname, char *p)
+{
+  enum arm_reg_type basetype;
+  struct reg_entry *basereg;
+  struct reg_entry mybasereg;
+  struct neon_type ntype;
+  struct neon_typed_alias typeinfo;
+  char *namebuf, *nameend;
+  int namelen;
+  
+  typeinfo.defined = 0;
+  typeinfo.eltype.type = NT_invtype;
+  typeinfo.eltype.size = -1;
+  typeinfo.index = -1;
+  
+  nameend = p;
+  
+  if (strncmp (p, " .dn ", 5) == 0)
+    basetype = REG_TYPE_VFD;
+  else if (strncmp (p, " .qn ", 5) == 0)
+    basetype = REG_TYPE_NQ;
+  else
+    return 0;
+  
+  p += 5;
+  
+  if (*p == '\0')
+    return 0;
+  
+  basereg = arm_reg_parse_multi (&p);
+
+  if (basereg && basereg->type != basetype)
+    {
+      as_bad (_("bad type for register"));
+      return 0;
+    }
+
+  if (basereg == NULL)
+    {
+      expressionS exp;
+      /* Try parsing as an integer.  */
+      my_get_expression (&exp, &p, GE_NO_PREFIX);
+      if (exp.X_op != O_constant)
+        {
+          as_bad (_("expression must be constant"));
+          return 0;
+        }
+      basereg = &mybasereg;
+      basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
+                                                  : exp.X_add_number;
+      basereg->neon = 0;
+    }
+
+  if (basereg->neon)
+    typeinfo = *basereg->neon;
+
+  if (parse_neon_type (&ntype, &p) == SUCCESS)
+    {
+      /* We got a type.  */
+      if (typeinfo.defined & NTA_HASTYPE)
+        {
+          as_bad (_("can't redefine the type of a register alias"));
+          return 0;
+        }
+      
+      typeinfo.defined |= NTA_HASTYPE;
+      if (ntype.elems != 1)
+        {
+          as_bad (_("you must specify a single type only"));
+          return 0;
+        }
+      typeinfo.eltype = ntype.el[0];
+    }
+  
+  if (skip_past_char (&p, '[') == SUCCESS)
+    {
+      expressionS exp;
+      /* We got a scalar index.  */
+    
+      if (typeinfo.defined & NTA_HASINDEX)
+        {
+          as_bad (_("can't redefine the index of a scalar alias"));
+          return 0;
+        }
+    
+      my_get_expression (&exp, &p, GE_NO_PREFIX);
+    
+      if (exp.X_op != O_constant)
+        {
+          as_bad (_("scalar index must be constant"));
+          return 0;
+        }
+      
+      typeinfo.defined |= NTA_HASINDEX;
+      typeinfo.index = exp.X_add_number;
+    
+      if (skip_past_char (&p, ']') == FAIL)
+        {
+          as_bad (_("expecting ]"));
+          return 0;
+        }
+    }
+
+  namelen = nameend - newname;
+  namebuf = alloca (namelen + 1);
+  strncpy (namebuf, newname, namelen);
+  namebuf[namelen] = '\0';
+  
+  insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                         typeinfo.defined != 0 ? &typeinfo : NULL);
+    
+  /* Insert name in all uppercase.  */
+  for (p = namebuf; *p; p++)
+    *p = TOUPPER (*p);
+  
+  if (strncmp (namebuf, newname, namelen))
+    insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                           typeinfo.defined != 0 ? &typeinfo : NULL);
+  
+  /* Insert name in all lowercase.  */
+  for (p = namebuf; *p; p++)
+    *p = TOLOWER (*p);
+  
+  if (strncmp (namebuf, newname, namelen))
+    insert_neon_reg_alias (namebuf, basereg->number, basetype,
+                           typeinfo.defined != 0 ? &typeinfo : NULL);
+  
+  return 1;
+}
+
 /* Should never be called, as .req goes between the alias and the
    register name, not at the beginning of the line.  */
 static void
@@ -1362,6 +2223,18 @@ s_req (int a ATTRIBUTE_UNUSED)
   as_bad (_("invalid syntax for .req directive"));
 }
 
+static void
+s_dn (int a ATTRIBUTE_UNUSED)
+{
+  as_bad (_("invalid syntax for .dn directive"));
+}
+
+static void
+s_qn (int a ATTRIBUTE_UNUSED)
+{
+  as_bad (_("invalid syntax for .qn directive"));
+}
+
 /* The .unreq directive deletes an alias which was previously defined
    by .req.  For example:
 
@@ -1399,6 +2272,8 @@ s_unreq (int a ATTRIBUTE_UNUSED)
 	{
 	  hash_delete (arm_reg_hsh, name);
 	  free ((char *) reg->name);
+          if (reg->neon)
+            free (reg->neon);
 	  free (reg);
 	}
     }
@@ -1417,7 +2292,7 @@ s_unreq (int a ATTRIBUTE_UNUSED)
 
 static enum mstate mapstate = MAP_UNDEFINED;
 
-static void
+void
 mapping_state (enum mstate state)
 {
   symbolS * symbolP;
@@ -1738,6 +2613,7 @@ static void
 s_align (int unused ATTRIBUTE_UNUSED)
 {
   int temp;
+  bfd_boolean fill_p;
   long temp_fill;
   long max_alignment = 15;
 
@@ -1754,16 +2630,25 @@ s_align (int unused ATTRIBUTE_UNUSED)
     {
       input_line_pointer++;
       temp_fill = get_absolute_expression ();
+      fill_p = TRUE;
     }
   else
-    temp_fill = 0;
+    {
+      fill_p = FALSE;
+      temp_fill = 0;
+    }
 
   if (!temp)
     temp = 2;
 
   /* Only make a frag if we HAVE to.  */
   if (temp && !need_pass_2)
-    frag_align (temp, (int) temp_fill, 0);
+    {
+      if (!fill_p && subseg_text_p (now_seg))
+	frag_align_code (temp, 0);
+      else
+	frag_align (temp, (int) temp_fill, 0);
+    }
   demand_empty_rest_of_line ();
 
   record_alignment (now_seg, temp);
@@ -2414,7 +3299,57 @@ s_arm_unwind_save_fpa (int reg)
 }
 
 
-/* Parse a directive saving VFP registers.  */
+/* Parse a directive saving VFP registers for ARMv6 and above.  */
+
+static void
+s_arm_unwind_save_vfp_armv6 (void)
+{
+  int count;
+  unsigned int start;
+  valueT op;
+  int num_vfpv3_regs = 0;
+  int num_regs_below_16;
+
+  count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
+  if (count == FAIL)
+    {
+      as_bad (_("expected register list"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+
+  /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
+     than FSTMX/FLDMX-style ones).  */
+
+  /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31.  */
+  if (start >= 16)
+    num_vfpv3_regs = count;
+  else if (start + count > 16)
+    num_vfpv3_regs = start + count - 16;
+
+  if (num_vfpv3_regs > 0)
+    {
+      int start_offset = start > 16 ? start - 16 : 0;
+      op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
+      add_unwind_opcode (op, 2);
+    }
+
+  /* Generate opcode for registers numbered in the range 0 .. 15.  */
+  num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
+  assert (num_regs_below_16 + num_vfpv3_regs == count);
+  if (num_regs_below_16 > 0)
+    {
+      op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
+      add_unwind_opcode (op, 2);
+    }
+
+  unwind.frame_size += count * 8;
+}
+
+
+/* Parse a directive saving VFP registers for pre-ARMv6.  */
 
 static void
 s_arm_unwind_save_vfp (void)
@@ -2423,7 +3358,7 @@ s_arm_unwind_save_vfp (void)
   unsigned int reg;
   valueT op;
 
-  count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
+  count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
   if (count == FAIL)
     {
       as_bad (_("expected register list"));
@@ -2502,7 +3437,7 @@ s_arm_unwind_save_mmxwr (void)
 
   demand_empty_rest_of_line ();
 
-  /* Generate any deferred opcodes becuuse we're going to be looking at
+  /* Generate any deferred opcodes because we're going to be looking at
      the list.	*/
   flush_pending_unwind ();
 
@@ -2538,7 +3473,7 @@ s_arm_unwind_save_mmxwr (void)
 
 	      op = 0xffff << (reg - 1);
 	      if (reg > 0
-		  || ((mask & op) == (1u << (reg - 1))))
+		  && ((mask & op) == (1u << (reg - 1))))
 		{
 		  op = (1 << (reg + i + 1)) - 1;
 		  op &= ~((1 << reg) - 1);
@@ -2635,7 +3570,7 @@ s_arm_unwind_save_mmxwcg (void)
 
   demand_empty_rest_of_line ();
 
-  /* Generate any deferred opcodes becuuse we're going to be looking at
+  /* Generate any deferred opcodes because we're going to be looking at
      the list.	*/
   flush_pending_unwind ();
 
@@ -2652,10 +3587,11 @@ error:
 }
 
 
-/* Parse an unwind_save directive.  */
+/* Parse an unwind_save directive.
+   If the argument is non-zero, this is a .vsave directive.  */
 
 static void
-s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
+s_arm_unwind_save (int arch_v6)
 {
   char *peek;
   struct reg_entry *reg;
@@ -2692,7 +3628,12 @@ s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
       return;
 
     case REG_TYPE_RN:	  s_arm_unwind_save_core ();   return;
-    case REG_TYPE_VFD:	   s_arm_unwind_save_vfp ();	return;
+    case REG_TYPE_VFD:
+      if (arch_v6)
+        s_arm_unwind_save_vfp_armv6 ();
+      else
+        s_arm_unwind_save_vfp ();
+      return;
     case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
     case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
 
@@ -2710,6 +3651,7 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
 {
   int reg;
   valueT op;
+  int offset;
 
   reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
   if (reg == FAIL)
@@ -2718,6 +3660,16 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
       ignore_rest_of_line ();
       return;
     }
+
+  /* Optional constant.	 */
+  if (skip_past_comma (&input_line_pointer) != FAIL)
+    {
+      if (immediate_for_directive (&offset) == FAIL)
+	return;
+    }
+  else
+    offset = 0;
+
   demand_empty_rest_of_line ();
 
   if (reg == REG_SP || reg == REG_PC)
@@ -2735,7 +3687,7 @@ s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
 
   /* Record the information for later.	*/
   unwind.fp_reg = reg;
-  unwind.fp_offset = unwind.frame_size;
+  unwind.fp_offset = unwind.frame_size - offset;
   unwind.sp_restored = 1;
 }
 
@@ -2818,7 +3770,7 @@ static void
 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
 {
   expressionS exp;
-  /* This is an arbitary limit.	 */
+  /* This is an arbitrary limit.	 */
   unsigned char op[16];
   int count;
 
@@ -2877,90 +3829,36 @@ s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
 static void
 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
 {
-  expressionS exp;
-  bfd_boolean is_string;
-  int tag;
-  unsigned int i = 0;
-  char *s = NULL;
-  char saved_char;
+  s_vendor_attribute (OBJ_ATTR_PROC);
+}
+#endif /* OBJ_ELF */
 
-  expression (& exp);
-  if (exp.X_op != O_constant)
-    goto bad;
+static void s_arm_arch (int);
+static void s_arm_object_arch (int);
+static void s_arm_cpu (int);
+static void s_arm_fpu (int);
 
-  tag = exp.X_add_number;
-  if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
-    is_string = 1;
-  else
-    is_string = 0;
+#ifdef TE_PE
 
-  if (skip_past_comma (&input_line_pointer) == FAIL)
-    goto bad;
-  if (tag == 32 || !is_string)
-    {
-      expression (& exp);
-      if (exp.X_op != O_constant)
-	{
-	  as_bad (_("expected numeric constant"));
-	  ignore_rest_of_line ();
-	  return;
-	}
-      i = exp.X_add_number;
-    }
-  if (tag == Tag_compatibility
-      && skip_past_comma (&input_line_pointer) == FAIL)
-    {
-      as_bad (_("expected comma"));
-      ignore_rest_of_line ();
-      return;
-    }
-  if (is_string)
-    {
-      skip_whitespace(input_line_pointer);
-      if (*input_line_pointer != '"')
-	goto bad_string;
-      input_line_pointer++;
-      s = input_line_pointer;
-      while (*input_line_pointer && *input_line_pointer != '"')
-	input_line_pointer++;
-      if (*input_line_pointer != '"')
-	goto bad_string;
-      saved_char = *input_line_pointer;
-      *input_line_pointer = 0;
-    }
-  else
-    {
-      s = NULL;
-      saved_char = 0;
-    }
-  
-  if (tag == Tag_compatibility)
-    elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
-  else if (is_string)
-    elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
-  else
-    elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
+static void
+pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 
+{
+  expressionS exp;
 
-  if (s)
+  do
     {
-      *input_line_pointer = saved_char;
-      input_line_pointer++;
+      expression (&exp);
+      if (exp.X_op == O_symbol)
+	exp.X_op = O_secrel;
+
+      emit_expr (&exp, 4);
     }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;
   demand_empty_rest_of_line ();
-  return;
-bad_string:
-  as_bad (_("bad string constant"));
-  ignore_rest_of_line ();
-  return;
-bad:
-  as_bad (_("expected <tag> , <value>"));
-  ignore_rest_of_line ();
 }
-
-static void s_arm_arch (int);
-static void s_arm_cpu (int);
-static void s_arm_fpu (int);
-#endif /* OBJ_ELF */
+#endif /* TE_PE */
 
 /* This table describes all the machine specific pseudo-ops the assembler
    has to support.  The fields are:
@@ -2972,6 +3870,9 @@ const pseudo_typeS md_pseudo_table[] =
 {
   /* Never called because '.req' does not start a line.	 */
   { "req",	   s_req,	  0 },
+  /* Following two are likewise never called.  */
+  { "dn",	   s_dn,          0 },
+  { "qn",          s_qn,          0 },
   { "unreq",	   s_unreq,	  0 },
   { "bss",	   s_bss,	  0 },
   { "align",	   s_align,	  0 },
@@ -2985,6 +3886,10 @@ const pseudo_typeS md_pseudo_table[] =
   { "ltorg",	   s_ltorg,	  0 },
   { "pool",	   s_ltorg,	  0 },
   { "syntax",	   s_syntax,	  0 },
+  { "cpu",	   s_arm_cpu,	  0 },
+  { "arch",	   s_arm_arch,	  0 },
+  { "object_arch", s_arm_object_arch,	0 },
+  { "fpu",	   s_arm_fpu,	  0 },
 #ifdef OBJ_ELF
   { "word",	   s_arm_elf_cons, 4 },
   { "long",	   s_arm_elf_cons, 4 },
@@ -2996,20 +3901,30 @@ const pseudo_typeS md_pseudo_table[] =
   { "personalityindex",	s_arm_unwind_personalityindex, 0 },
   { "handlerdata",	s_arm_unwind_handlerdata, 0 },
   { "save",		s_arm_unwind_save,	0 },
+  { "vsave",		s_arm_unwind_save,	1 },
   { "movsp",		s_arm_unwind_movsp,	0 },
   { "pad",		s_arm_unwind_pad,	0 },
   { "setfp",		s_arm_unwind_setfp,	0 },
   { "unwind_raw",	s_arm_unwind_raw,	0 },
-  { "cpu",		s_arm_cpu,		0 },
-  { "arch",		s_arm_arch,		0 },
-  { "fpu",		s_arm_fpu,		0 },
   { "eabi_attribute",	s_arm_eabi_attribute,	0 },
 #else
   { "word",	   cons, 4},
+
+  /* These are used for dwarf.  */
+  {"2byte", cons, 2},
+  {"4byte", cons, 4},
+  {"8byte", cons, 8},
+  /* These are used for dwarf2.  */
+  { "file", (void (*) (int)) dwarf2_directive_file, 0 },
+  { "loc",  dwarf2_directive_loc,  0 },
+  { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
 #endif
   { "extend",	   float_cons, 'x' },
   { "ldouble",	   float_cons, 'x' },
   { "packed",	   float_cons, 'p' },
+#ifdef TE_PE
+  {"secrel32", pe_directive_secrel, 0},
+#endif
   { 0, 0, 0 }
 };
 
@@ -3043,6 +3958,58 @@ parse_immediate (char **str, int *val, int min, int max,
   return SUCCESS;
 }
 
+/* Less-generic immediate-value read function with the possibility of loading a
+   big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
+   instructions. Puts the result directly in inst.operands[i].  */
+
+static int
+parse_big_immediate (char **str, int i)
+{
+  expressionS exp;
+  char *ptr = *str;
+
+  my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
+
+  if (exp.X_op == O_constant)
+    {
+      inst.operands[i].imm = exp.X_add_number & 0xffffffff;
+      /* If we're on a 64-bit host, then a 64-bit number can be returned using
+	 O_constant.  We have to be careful not to break compilation for
+	 32-bit X_add_number, though.  */
+      if ((exp.X_add_number & ~0xffffffffl) != 0)
+	{
+          /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4.  */
+	  inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
+	  inst.operands[i].regisimm = 1;
+	}
+    }
+  else if (exp.X_op == O_big
+           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
+           && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
+    {
+      unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
+      /* Bignums have their least significant bits in
+         generic_bignum[0]. Make sure we put 32 bits in imm and
+         32 bits in reg,  in a (hopefully) portable way.  */
+      assert (parts != 0);
+      inst.operands[i].imm = 0;
+      for (j = 0; j < parts; j++, idx++)
+        inst.operands[i].imm |= generic_bignum[idx]
+                                << (LITTLENUM_NUMBER_OF_BITS * j);
+      inst.operands[i].reg = 0;
+      for (j = 0; j < parts; j++, idx++)
+        inst.operands[i].reg |= generic_bignum[idx]
+                                << (LITTLENUM_NUMBER_OF_BITS * j);
+      inst.operands[i].regisimm = 1;
+    }
+  else
+    return FAIL;
+  
+  *str = ptr;
+
+  return SUCCESS;
+}
+
 /* Returns the pseudo-register number of an FPA immediate constant,
    or FAIL if there isn't a valid constant here.  */
 
@@ -3134,6 +4101,80 @@ parse_fpa_immediate (char ** str)
   return FAIL;
 }
 
+/* Returns 1 if a number has "quarter-precision" float format
+   0baBbbbbbc defgh000 00000000 00000000.  */
+
+static int
+is_quarter_float (unsigned imm)
+{
+  int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
+  return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
+}
+
+/* Parse an 8-bit "quarter-precision" floating point number of the form:
+   0baBbbbbbc defgh000 00000000 00000000.
+   The zero and minus-zero cases need special handling, since they can't be
+   encoded in the "quarter-precision" float format, but can nonetheless be
+   loaded as integer constants.  */
+
+static unsigned
+parse_qfloat_immediate (char **ccp, int *immed)
+{
+  char *str = *ccp;
+  char *fpnum;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  int found_fpchar = 0;
+  
+  skip_past_char (&str, '#');
+  
+  /* We must not accidentally parse an integer as a floating-point number. Make
+     sure that the value we parse is not an integer by checking for special
+     characters '.' or 'e'.
+     FIXME: This is a horrible hack, but doing better is tricky because type
+     information isn't in a very usable state at parse time.  */
+  fpnum = str;
+  skip_whitespace (fpnum);
+
+  if (strncmp (fpnum, "0x", 2) == 0)
+    return FAIL;
+  else
+    {
+      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
+        if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
+          {
+            found_fpchar = 1;
+            break;
+          }
+
+      if (!found_fpchar)
+        return FAIL;
+    }
+  
+  if ((str = atof_ieee (str, 's', words)) != NULL)
+    {
+      unsigned fpword = 0;
+      int i;
+      
+      /* Our FP word must be 32 bits (single-precision FP).  */
+      for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
+        {
+          fpword <<= LITTLENUM_NUMBER_OF_BITS;
+          fpword |= words[i];
+        }
+      
+      if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
+        *immed = fpword;
+      else
+        return FAIL;
+
+      *ccp = str;
+      
+      return SUCCESS;
+    }
+  
+  return FAIL;
+}
+
 /* Shift operands.  */
 enum shift_kind
 {
@@ -3317,6 +4358,168 @@ parse_shifter_operand (char **str, int i)
   return SUCCESS;
 }
 
+/* Group relocation information.  Each entry in the table contains the
+   textual name of the relocation as may appear in assembler source
+   and must end with a colon.
+   Along with this textual name are the relocation codes to be used if
+   the corresponding instruction is an ALU instruction (ADD or SUB only),
+   an LDR, an LDRS, or an LDC.  */
+
+struct group_reloc_table_entry
+{
+  const char *name;
+  int alu_code;
+  int ldr_code;
+  int ldrs_code;
+  int ldc_code;
+};
+
+typedef enum
+{
+  /* Varieties of non-ALU group relocation.  */
+
+  GROUP_LDR,
+  GROUP_LDRS,
+  GROUP_LDC
+} group_reloc_type;
+
+static struct group_reloc_table_entry group_reloc_table[] =
+  { /* Program counter relative: */
+    { "pc_g0_nc",
+      BFD_RELOC_ARM_ALU_PC_G0_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "pc_g0",
+      BFD_RELOC_ARM_ALU_PC_G0,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G0,		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G0,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G0 },	/* LDC */
+    { "pc_g1_nc",
+      BFD_RELOC_ARM_ALU_PC_G1_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "pc_g1",
+      BFD_RELOC_ARM_ALU_PC_G1,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G1, 		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G1,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G1 },	/* LDC */
+    { "pc_g2",
+      BFD_RELOC_ARM_ALU_PC_G2,		/* ALU */
+      BFD_RELOC_ARM_LDR_PC_G2,		/* LDR */
+      BFD_RELOC_ARM_LDRS_PC_G2,		/* LDRS */
+      BFD_RELOC_ARM_LDC_PC_G2 },	/* LDC */
+    /* Section base relative */
+    { "sb_g0_nc",
+      BFD_RELOC_ARM_ALU_SB_G0_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "sb_g0",
+      BFD_RELOC_ARM_ALU_SB_G0,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G0,		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G0,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G0 },	/* LDC */
+    { "sb_g1_nc",
+      BFD_RELOC_ARM_ALU_SB_G1_NC,	/* ALU */
+      0,				/* LDR */
+      0,				/* LDRS */
+      0 },				/* LDC */
+    { "sb_g1",
+      BFD_RELOC_ARM_ALU_SB_G1,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G1, 		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G1,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G1 },	/* LDC */
+    { "sb_g2",
+      BFD_RELOC_ARM_ALU_SB_G2,		/* ALU */
+      BFD_RELOC_ARM_LDR_SB_G2,		/* LDR */
+      BFD_RELOC_ARM_LDRS_SB_G2,		/* LDRS */
+      BFD_RELOC_ARM_LDC_SB_G2 }	};	/* LDC */
+
+/* Given the address of a pointer pointing to the textual name of a group
+   relocation as may appear in assembler source, attempt to find its details
+   in group_reloc_table.  The pointer will be updated to the character after
+   the trailing colon.  On failure, FAIL will be returned; SUCCESS
+   otherwise.  On success, *entry will be updated to point at the relevant
+   group_reloc_table entry. */
+
+static int
+find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
+{
+  unsigned int i;
+  for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
+    {
+      int length = strlen (group_reloc_table[i].name);
+
+      if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
+          (*str)[length] == ':')
+        {
+          *out = &group_reloc_table[i];
+          *str += (length + 1);
+          return SUCCESS;
+        }
+    }
+
+  return FAIL;
+}
+
+/* Parse a <shifter_operand> for an ARM data processing instruction
+   (as for parse_shifter_operand) where group relocations are allowed:
+
+      #<immediate>
+      #<immediate>, <rotate>
+      #:<group_reloc>:<expression>
+      <Rm>
+      <Rm>, <shift>
+
+   where <group_reloc> is one of the strings defined in group_reloc_table.
+   The hashes are optional.
+
+   Everything else is as for parse_shifter_operand.  */
+
+static parse_operand_result
+parse_shifter_operand_group_reloc (char **str, int i)
+{
+  /* Determine if we have the sequence of characters #: or just :
+     coming next.  If we do, then we check for a group relocation.
+     If we don't, punt the whole lot to parse_shifter_operand.  */
+
+  if (((*str)[0] == '#' && (*str)[1] == ':')
+      || (*str)[0] == ':')
+    {
+      struct group_reloc_table_entry *entry;
+
+      if ((*str)[0] == '#')
+        (*str) += 2;
+      else
+        (*str)++;
+
+      /* Try to parse a group relocation.  Anything else is an error.  */
+      if (find_group_reloc_table_entry (str, &entry) == FAIL)
+        {
+          inst.error = _("unknown group relocation");
+          return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+        }
+
+      /* We now have the group relocation table entry corresponding to
+         the name in the assembler source.  Next, we parse the expression.  */
+      if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
+        return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+
+      /* Record the relocation type (always the ALU variant here).  */
+      inst.reloc.type = entry->alu_code;
+      assert (inst.reloc.type != 0);
+
+      return PARSE_OPERAND_SUCCESS;
+    }
+  else
+    return parse_shifter_operand (str, i) == SUCCESS
+           ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
+
+  /* Never reached.  */
+}
+
 /* Parse all forms of an ARM address expression.  Information is written
    to inst.operands[i] and/or inst.reloc.
 
@@ -3349,8 +4552,9 @@ parse_shifter_operand (char **str, int i)
   It is the caller's responsibility to check for addressing modes not
   supported by the instruction, and to set inst.reloc.type.  */
 
-static int
-parse_address (char **str, int i)
+static parse_operand_result
+parse_address_main (char **str, int i, int group_relocations,
+                    group_reloc_type group_type)
 {
   char *p = *str;
   int reg;
@@ -3368,16 +4572,16 @@ parse_address (char **str, int i)
       /* else a load-constant pseudo op, no special treatment needed here */
 
       if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
-	return FAIL;
+	return PARSE_OPERAND_FAIL;
 
       *str = p;
-      return SUCCESS;
+      return PARSE_OPERAND_SUCCESS;
     }
 
   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
       inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
-      return FAIL;
+      return PARSE_OPERAND_FAIL;
     }
   inst.operands[i].reg = reg;
   inst.operands[i].isreg = 1;
@@ -3396,8 +4600,25 @@ parse_address (char **str, int i)
 
 	  if (skip_past_comma (&p) == SUCCESS)
 	    if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	}
+      else if (skip_past_char (&p, ':') == SUCCESS)
+        {
+          /* FIXME: '@' should be used here, but it's filtered out by generic
+             code before we get to see it here. This may be subject to
+             change.  */
+          expressionS exp;
+          my_get_expression (&exp, &p, GE_NO_PREFIX);
+          if (exp.X_op != O_constant)
+            {
+              inst.error = _("alignment must be constant");
+              return PARSE_OPERAND_FAIL;
+            }
+          inst.operands[i].imm = exp.X_add_number << 8;
+          inst.operands[i].immisalign = 1;
+          /* Alignments are not pre-indexes.  */
+          inst.operands[i].preind = 0;
+        }
       else
 	{
 	  if (inst.operands[i].negative)
@@ -3405,15 +4626,68 @@ parse_address (char **str, int i)
 	      inst.operands[i].negative = 0;
 	      p--;
 	    }
-	  if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
-	    return FAIL;
+
+	  if (group_relocations &&
+              ((*p == '#' && *(p + 1) == ':') || *p == ':'))
+
+	    {
+	      struct group_reloc_table_entry *entry;
+
+              /* Skip over the #: or : sequence.  */
+              if (*p == '#')
+                p += 2;
+              else
+                p++;
+
+	      /* Try to parse a group relocation.  Anything else is an
+                 error.  */
+	      if (find_group_reloc_table_entry (&p, &entry) == FAIL)
+		{
+		  inst.error = _("unknown group relocation");
+		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+		}
+
+	      /* We now have the group relocation table entry corresponding to
+		 the name in the assembler source.  Next, we parse the
+                 expression.  */
+	      if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+		return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+
+	      /* Record the relocation type.  */
+              switch (group_type)
+                {
+                  case GROUP_LDR:
+	            inst.reloc.type = entry->ldr_code;
+                    break;
+
+                  case GROUP_LDRS:
+	            inst.reloc.type = entry->ldrs_code;
+                    break;
+
+                  case GROUP_LDC:
+	            inst.reloc.type = entry->ldc_code;
+                    break;
+
+                  default:
+                    assert (0);
+                }
+
+              if (inst.reloc.type == 0)
+		{
+		  inst.error = _("this group relocation is not allowed on this instruction");
+		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
+		}
+            }
+          else
+	    if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+	      return PARSE_OPERAND_FAIL;
 	}
     }
 
   if (skip_past_char (&p, ']') == FAIL)
     {
       inst.error = _("']' expected");
-      return FAIL;
+      return PARSE_OPERAND_FAIL;
     }
 
   if (skip_past_char (&p, '!') == SUCCESS)
@@ -3426,20 +4700,20 @@ parse_address (char **str, int i)
 	  /* [Rn], {expr} - unindexed, with option */
 	  if (parse_immediate (&p, &inst.operands[i].imm,
 			       0, 255, TRUE) == FAIL)
-	    return FAIL;
+	    return PARSE_OPERAND_FAIL;
 
 	  if (skip_past_char (&p, '}') == FAIL)
 	    {
 	      inst.error = _("'}' expected at end of 'option' field");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 	  if (inst.operands[i].preind)
 	    {
 	      inst.error = _("cannot combine index with option");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 	  *str = p;
-	  return SUCCESS;
+	  return PARSE_OPERAND_SUCCESS;
 	}
       else
 	{
@@ -3449,7 +4723,7 @@ parse_address (char **str, int i)
 	  if (inst.operands[i].preind)
 	    {
 	      inst.error = _("cannot combine pre- and post-indexing");
-	      return FAIL;
+	      return PARSE_OPERAND_FAIL;
 	    }
 
 	  if (*p == '+') p++;
@@ -3457,12 +4731,17 @@ parse_address (char **str, int i)
 
 	  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
 	    {
-	      inst.operands[i].imm = reg;
+              /* We might be using the immediate for alignment already. If we
+                 are, OR the register number into the low-order bits.  */
+              if (inst.operands[i].immisalign)
+	        inst.operands[i].imm |= reg;
+              else
+                inst.operands[i].imm = reg;
 	      inst.operands[i].immisreg = 1;
 
 	      if (skip_past_comma (&p) == SUCCESS)
 		if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
-		  return FAIL;
+		  return PARSE_OPERAND_FAIL;
 	    }
 	  else
 	    {
@@ -3472,7 +4751,7 @@ parse_address (char **str, int i)
 		  p--;
 		}
 	      if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
-		return FAIL;
+		return PARSE_OPERAND_FAIL;
 	    }
 	}
     }
@@ -3486,6 +4765,59 @@ parse_address (char **str, int i)
       inst.reloc.exp.X_add_number = 0;
     }
   *str = p;
+  return PARSE_OPERAND_SUCCESS;
+}
+
+static int
+parse_address (char **str, int i)
+{
+  return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
+         ? SUCCESS : FAIL;
+}
+
+static parse_operand_result
+parse_address_group_reloc (char **str, int i, group_reloc_type type)
+{
+  return parse_address_main (str, i, 1, type);
+}
+
+/* Parse an operand for a MOVW or MOVT instruction.  */
+static int
+parse_half (char **str)
+{
+  char * p;
+  
+  p = *str;
+  skip_past_char (&p, '#');
+  if (strncasecmp (p, ":lower16:", 9) == 0) 
+    inst.reloc.type = BFD_RELOC_ARM_MOVW;
+  else if (strncasecmp (p, ":upper16:", 9) == 0)
+    inst.reloc.type = BFD_RELOC_ARM_MOVT;
+
+  if (inst.reloc.type != BFD_RELOC_UNUSED)
+    {
+      p += 9;
+      skip_whitespace(p);
+    }
+
+  if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+    return FAIL;
+
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      if (inst.reloc.exp.X_op != O_constant)
+	{
+	  inst.error = _("constant expression expected");
+	  return FAIL;
+	}
+      if (inst.reloc.exp.X_add_number < 0
+	  || inst.reloc.exp.X_add_number > 0xffff)
+	{
+	  inst.error = _("immediate value out of range");
+	  return FAIL;
+	}
+    }
+  *str = p;
   return SUCCESS;
 }
 
@@ -3752,6 +5084,228 @@ parse_tb (char **str)
   return SUCCESS;
 }
 
+/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
+   information on the types the operands can take and how they are encoded.
+   Up to four operands may be read; this function handles setting the
+   ".present" field for each read operand itself.
+   Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
+   else returns FAIL.  */
+
+static int
+parse_neon_mov (char **str, int *which_operand)
+{
+  int i = *which_operand, val;
+  enum arm_reg_type rtype;
+  char *ptr = *str;
+  struct neon_type_el optype;
+  
+  if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
+    {
+      /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>.  */
+      inst.operands[i].reg = val;
+      inst.operands[i].isscalar = 1;
+      inst.operands[i].vectype = optype;
+      inst.operands[i++].present = 1;
+
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+        goto wanted_arm;
+      
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i].present = 1;
+    }
+  else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
+           != FAIL)
+    {
+      /* Cases 0, 1, 2, 3, 5 (D only).  */
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
+      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+      inst.operands[i].isvec = 1;
+      inst.operands[i].vectype = optype;
+      inst.operands[i++].present = 1;
+
+      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+        {
+          /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
+             Case 13: VMOV <Sd>, <Rm>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].present = 1;
+
+          if (rtype == REG_TYPE_NQ)
+            {
+              first_error (_("can't use Neon quad register here"));
+              return FAIL;
+            }
+          else if (rtype != REG_TYPE_VFS)
+            {
+              i++;
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i].present = 1;
+            }
+        }
+      else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
+          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
+             Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
+             Case 10: VMOV.F32 <Sd>, #<imm>
+             Case 11: VMOV.F64 <Dd>, #<imm>  */
+        inst.operands[i].immisfloat = 1;
+      else if (parse_big_immediate (&ptr, i) == SUCCESS)
+          /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
+             Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
+        ;
+      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
+                                           &optype)) != FAIL)
+        {
+          /* Case 0: VMOV<c><q> <Qd>, <Qm>
+             Case 1: VMOV<c><q> <Dd>, <Dm>
+             Case 8: VMOV.F32 <Sd>, <Sm>
+             Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
+
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
+          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+          inst.operands[i].isvec = 1;
+          inst.operands[i].vectype = optype;
+          inst.operands[i].present = 1;
+          
+          if (skip_past_comma (&ptr) == SUCCESS)
+            {
+              /* Case 15.  */
+              i++;
+
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i++].present = 1;
+              
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              
+              if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
+                goto wanted_arm;
+              
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i++].present = 1;
+            }
+        }
+      else
+        {
+          first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
+          return FAIL;
+        }
+    }
+  else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+    {
+      /* Cases 6, 7.  */
+      inst.operands[i].reg = val;
+      inst.operands[i].isreg = 1;
+      inst.operands[i++].present = 1;
+      
+      if (skip_past_comma (&ptr) == FAIL)
+        goto wanted_comma;
+      
+      if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
+        {
+          /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isscalar = 1;
+          inst.operands[i].present = 1;
+          inst.operands[i].vectype = optype;
+        }
+      else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
+        {
+          /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i++].present = 1;
+          
+          if (skip_past_comma (&ptr) == FAIL)
+            goto wanted_comma;
+          
+          if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
+              == FAIL)
+            {
+              first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
+              return FAIL;
+            }
+
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isvec = 1;
+          inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
+          inst.operands[i].vectype = optype;
+          inst.operands[i].present = 1;
+          
+          if (rtype == REG_TYPE_VFS)
+            {
+              /* Case 14.  */
+              i++;
+              if (skip_past_comma (&ptr) == FAIL)
+                goto wanted_comma;
+              if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
+                                              &optype)) == FAIL)
+                {
+                  first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
+                  return FAIL;
+                }
+              inst.operands[i].reg = val;
+              inst.operands[i].isreg = 1;
+              inst.operands[i].isvec = 1;
+              inst.operands[i].issingle = 1;
+              inst.operands[i].vectype = optype;
+              inst.operands[i].present = 1;
+            }
+        }
+      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
+               != FAIL)
+        {
+          /* Case 13.  */
+          inst.operands[i].reg = val;
+          inst.operands[i].isreg = 1;
+          inst.operands[i].isvec = 1;
+          inst.operands[i].issingle = 1;
+          inst.operands[i].vectype = optype;
+          inst.operands[i++].present = 1;
+        }
+    }
+  else
+    {
+      first_error (_("parse error"));
+      return FAIL;
+    }
+
+  /* Successfully parsed the operands. Update args.  */
+  *which_operand = i;
+  *str = ptr;
+  return SUCCESS;
+
+  wanted_comma:
+  first_error (_("expected comma"));
+  return FAIL;
+  
+  wanted_arm:
+  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
+  return FAIL;
+}
+
 /* Matcher codes for parse_operands.  */
 enum operand_parse_code
 {
@@ -3765,7 +5319,13 @@ enum operand_parse_code
   OP_RCN,	/* Coprocessor register */
   OP_RF,	/* FPA register */
   OP_RVS,	/* VFP single precision register */
-  OP_RVD,	/* VFP double precision register */
+  OP_RVD,	/* VFP double precision register (0..15) */
+  OP_RND,       /* Neon double precision register (0..31) */
+  OP_RNQ,	/* Neon quad precision register */
+  OP_RVSD,	/* VFP single or double precision register */
+  OP_RNDQ,      /* Neon double or quad precision register */
+  OP_RNSDQ,	/* Neon single, double or quad precision register */
+  OP_RNSC,      /* Neon scalar D[X] */
   OP_RVC,	/* VFP control register */
   OP_RMF,	/* Maverick F register */
   OP_RMD,	/* Maverick D register */
@@ -3781,16 +5341,36 @@ enum operand_parse_code
   OP_REGLST,	/* ARM register list */
   OP_VRSLST,	/* VFP single-precision register list */
   OP_VRDLST,	/* VFP double-precision register list */
-
+  OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
+  OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
+  OP_NSTRLST,   /* Neon element/structure list */
+
+  OP_NILO,      /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...)  */
+  OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
+  OP_RVSD_I0,	/* VFP S or D reg, or immediate zero.  */
+  OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
+  OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
+  OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
+  OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
+  OP_VMOV,      /* Neon VMOV operands.  */
+  OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
+  OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
+  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
+
+  OP_I0,        /* immediate zero */
   OP_I7,	/* immediate value 0 .. 7 */
   OP_I15,	/*		   0 .. 15 */
   OP_I16,	/*		   1 .. 16 */
+  OP_I16z,      /*                 0 .. 16 */
   OP_I31,	/*		   0 .. 31 */
   OP_I31w,	/*		   0 .. 31, optional trailing ! */
   OP_I32,	/*		   1 .. 32 */
+  OP_I32z,	/*		   0 .. 32 */
+  OP_I63,	/*		   0 .. 63 */
   OP_I63s,	/*		 -64 .. 63 */
+  OP_I64,	/*		   1 .. 64 */
+  OP_I64z,	/*		   0 .. 64 */
   OP_I255,	/*		   0 .. 255 */
-  OP_Iffff,	/*		   0 .. 65535 */
 
   OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
   OP_I7b,	/*			       0 .. 7 */
@@ -3798,10 +5378,15 @@ enum operand_parse_code
   OP_I31b,	/*			       0 .. 31 */
 
   OP_SH,	/* shifter operand */
+  OP_SHG,	/* shifter operand with possible group relocation */
   OP_ADDR,	/* Memory address expression (any mode) */
+  OP_ADDRGLDR,	/* Mem addr expr (any mode) with possible LDR group reloc */
+  OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
+  OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
   OP_EXP,	/* arbitrary expression */
   OP_EXPi,	/* same, with optional immediate prefix */
   OP_EXPr,	/* same, with optional relocation suffix */
+  OP_HALF,	/* 0 .. 65535 or low/high reloc.  */
 
   OP_CPSF,	/* CPS flags */
   OP_ENDI,	/* Endianness specifier */
@@ -3809,20 +5394,30 @@ enum operand_parse_code
   OP_COND,	/* conditional code */
   OP_TB,	/* Table branch.  */
 
+  OP_RVC_PSR,	/* CPSR/SPSR mask for msr, or VFP control register.  */
+  OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */
+
   OP_RRnpc_I0,	/* ARM register or literal 0 */
   OP_RR_EXr,	/* ARM register or expression with opt. reloc suff. */
   OP_RR_EXi,	/* ARM register or expression with imm prefix */
   OP_RF_IF,	/* FPA register or immediate */
   OP_RIWR_RIWC, /* iWMMXt R or C reg */
+  OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
 
   /* Optional operands.	 */
   OP_oI7b,	 /* immediate, prefix optional, 0 .. 7 */
   OP_oI31b,	 /*				0 .. 31 */
+  OP_oI32b,      /*                             1 .. 32 */
   OP_oIffffb,	 /*				0 .. 65535 */
   OP_oI255c,	 /*	  curly-brace enclosed, 0 .. 255 */
 
   OP_oRR,	 /* ARM register */
   OP_oRRnpc,	 /* ARM register, not the PC */
+  OP_oRRw,	 /* ARM register, not r15, optional trailing ! */
+  OP_oRND,       /* Optional Neon double precision register */
+  OP_oRNQ,       /* Optional Neon quad precision register */
+  OP_oRNDQ,      /* Optional Neon double or quad precision register */
+  OP_oRNSDQ,	 /* Optional single, double or quad precision vector register */
   OP_oSHll,	 /* LSL immediate */
   OP_oSHar,	 /* ASR immediate */
   OP_oSHllar,	 /* LSL or ASR immediate */
@@ -3843,30 +5438,44 @@ parse_operands (char *str, const unsigned char *pattern)
   char *backtrack_pos = 0;
   const char *backtrack_error = 0;
   int i, val, backtrack_index = 0;
+  enum arm_reg_type rtype;
+  parse_operand_result result;
 
 #define po_char_or_fail(chr) do {		\
   if (skip_past_char (&str, chr) == FAIL)	\
     goto bad_args;				\
 } while (0)
 
-#define po_reg_or_fail(regtype) do {			\
-  val = arm_reg_parse (&str, regtype);			\
-  if (val == FAIL)					\
-    {							\
-      inst.error = _(reg_expected_msgs[regtype]);	\
-      goto failure;					\
-    }							\
-  inst.operands[i].reg = val;				\
-  inst.operands[i].isreg = 1;				\
+#define po_reg_or_fail(regtype) do {				\
+  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
+  			     &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    {								\
+      first_error (_(reg_expected_msgs[regtype]));		\
+      goto failure;						\
+    }								\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isreg = 1;					\
+  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
+  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
+  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
+                            || rtype == REG_TYPE_VFD		\
+                            || rtype == REG_TYPE_NQ);		\
 } while (0)
 
-#define po_reg_or_goto(regtype, label) do {	\
-  val = arm_reg_parse (&str, regtype);		\
-  if (val == FAIL)				\
-    goto label;					\
-						\
-  inst.operands[i].reg = val;			\
-  inst.operands[i].isreg = 1;			\
+#define po_reg_or_goto(regtype, label) do {			\
+  val = arm_typed_reg_parse (&str, regtype, &rtype,		\
+                             &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    goto label;							\
+								\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isreg = 1;					\
+  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
+  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);		\
+  inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
+                            || rtype == REG_TYPE_VFD		\
+                            || rtype == REG_TYPE_NQ);		\
 } while (0)
 
 #define po_imm_or_fail(min, max, popt) do {			\
@@ -3875,11 +5484,27 @@ parse_operands (char *str, const unsigned char *pattern)
   inst.operands[i].imm = val;					\
 } while (0)
 
+#define po_scalar_or_goto(elsz, label) do {			\
+  val = parse_scalar (&str, elsz, &inst.operands[i].vectype);	\
+  if (val == FAIL)						\
+    goto label;							\
+  inst.operands[i].reg = val;					\
+  inst.operands[i].isscalar = 1;				\
+} while (0)
+
 #define po_misc_or_fail(expr) do {		\
   if (expr)					\
     goto failure;				\
 } while (0)
 
+#define po_misc_or_fail_no_backtrack(expr) do {	\
+  result = expr;				\
+  if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
+    backtrack_pos = 0;				\
+  if (result != PARSE_OPERAND_SUCCESS)		\
+    goto failure;				\
+} while (0)
+
   skip_whitespace (str);
 
   for (i = 0; upat[i] != OP_stop; i++)
@@ -3893,7 +5518,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	  backtrack_index = i;
 	}
 
-      if (i > 0)
+      if (i > 0 && (i > 1 || inst.operands[0].present))
 	po_char_or_fail (',');
 
       switch (upat[i])
@@ -3908,7 +5533,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
 	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
 	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
-	case OP_RVC:   po_reg_or_fail (REG_TYPE_VFC);	  break;
+        case OP_oRND:
+	case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);	  break;
+	case OP_RVC:
+	  po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
+	  break;
+	  /* Also accept generic coprocessor regs for unknown registers.  */
+	  coproc_reg:
+	  po_reg_or_fail (REG_TYPE_CN);
+	  break;
 	case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);	  break;
 	case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);	  break;
 	case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);	  break;
@@ -3919,6 +5552,126 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);	  break;
 	case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
 	case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
+        case OP_oRNQ:
+	case OP_RNQ:   po_reg_or_fail (REG_TYPE_NQ);      break;
+        case OP_oRNDQ:
+	case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
+        case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
+        case OP_oRNSDQ:
+        case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
+
+        /* Neon scalar. Using an element size of 8 means that some invalid
+           scalars are accepted here, so deal with those in later code.  */
+        case OP_RNSC:  po_scalar_or_goto (8, failure);    break;
+
+        /* WARNING: We can expand to two operands here. This has the potential
+           to totally confuse the backtracking mechanism! It will be OK at
+           least as long as we don't try to use optional args as well,
+           though.  */
+        case OP_NILO:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_imm);
+	    inst.operands[i].present = 1;
+            i++;
+            skip_past_comma (&str);
+            po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
+            break;
+            one_reg_only:
+            /* Optional register operand was omitted. Unfortunately, it's in
+               operands[i-1] and we need it to be in inst.operands[i]. Fix that
+               here (this is a bit grotty).  */
+            inst.operands[i] = inst.operands[i-1];
+            inst.operands[i-1].present = 0;
+            break;
+            try_imm:
+	    /* There's a possibility of getting a 64-bit immediate here, so
+	       we need special handling.  */
+	    if (parse_big_immediate (&str, i) == FAIL)
+	      {
+		inst.error = _("immediate value is out of range");
+		goto failure;
+	      }
+          }
+          break;
+
+        case OP_RNDQ_I0:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
+            break;
+            try_imm0:
+            po_imm_or_fail (0, 0, TRUE);
+          }
+          break;
+
+        case OP_RVSD_I0:
+          po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
+          break;
+
+        case OP_RR_RNSC:
+          {
+            po_scalar_or_goto (8, try_rr);
+            break;
+            try_rr:
+            po_reg_or_fail (REG_TYPE_RN);
+          }
+          break;
+
+        case OP_RNSDQ_RNSC:
+          {
+            po_scalar_or_goto (8, try_nsdq);
+            break;
+            try_nsdq:
+            po_reg_or_fail (REG_TYPE_NSDQ);
+          }
+          break;
+
+        case OP_RNDQ_RNSC:
+          {
+            po_scalar_or_goto (8, try_ndq);
+            break;
+            try_ndq:
+            po_reg_or_fail (REG_TYPE_NDQ);
+          }
+          break;
+
+        case OP_RND_RNSC:
+          {
+            po_scalar_or_goto (8, try_vfd);
+            break;
+            try_vfd:
+            po_reg_or_fail (REG_TYPE_VFD);
+          }
+          break;
+
+        case OP_VMOV:
+          /* WARNING: parse_neon_mov can move the operand counter, i. If we're
+             not careful then bad things might happen.  */
+          po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
+          break;
+
+        case OP_RNDQ_IMVNb:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
+            break;
+            try_mvnimm:
+            /* There's a possibility of getting a 64-bit immediate here, so
+               we need special handling.  */
+            if (parse_big_immediate (&str, i) == FAIL)
+              {
+                inst.error = _("immediate value is out of range");
+                goto failure;
+              }
+          }
+          break;
+
+        case OP_RNDQ_I63b:
+          {
+            po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
+            break;
+            try_shimm:
+            po_imm_or_fail (0, 63, TRUE);
+          }
+          break;
 
 	case OP_RRnpcb:
 	  po_char_or_fail ('[');
@@ -3927,6 +5680,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	  break;
 
 	case OP_RRw:
+	case OP_oRRw:
 	  po_reg_or_fail (REG_TYPE_RN);
 	  if (skip_past_char (&str, '!') == SUCCESS)
 	    inst.operands[i].writeback = 1;
@@ -3936,11 +5690,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_I7:	 po_imm_or_fail (  0,	   7, FALSE);	break;
 	case OP_I15:	 po_imm_or_fail (  0,	  15, FALSE);	break;
 	case OP_I16:	 po_imm_or_fail (  1,	  16, FALSE);	break;
+        case OP_I16z:	 po_imm_or_fail (  0,     16, FALSE);   break;
 	case OP_I31:	 po_imm_or_fail (  0,	  31, FALSE);	break;
 	case OP_I32:	 po_imm_or_fail (  1,	  32, FALSE);	break;
+        case OP_I32z:	 po_imm_or_fail (  0,     32, FALSE);   break;
 	case OP_I63s:	 po_imm_or_fail (-64,	  63, FALSE);	break;
+        case OP_I63:	 po_imm_or_fail (  0,     63, FALSE);   break;
+        case OP_I64:	 po_imm_or_fail (  1,     64, FALSE);   break;
+        case OP_I64z:	 po_imm_or_fail (  0,     64, FALSE);   break;
 	case OP_I255:	 po_imm_or_fail (  0,	 255, FALSE);	break;
-	case OP_Iffff:	 po_imm_or_fail (  0, 0xffff, FALSE);	break;
 
 	case OP_I4b:	 po_imm_or_fail (  1,	   4, TRUE);	break;
 	case OP_oI7b:
@@ -3948,6 +5706,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_I15b:	 po_imm_or_fail (  0,	  15, TRUE);	break;
 	case OP_oI31b:
 	case OP_I31b:	 po_imm_or_fail (  0,	  31, TRUE);	break;
+        case OP_oI32b:   po_imm_or_fail (  1,     32, TRUE);    break;
 	case OP_oIffffb: po_imm_or_fail (  0, 0xffff, TRUE);	break;
 
 	  /* Immediate variants */
@@ -4005,6 +5764,11 @@ parse_operands (char *str, const unsigned char *pattern)
 	    }
 	  break;
 
+	  /* Operand for MOVW or MOVT.  */
+	case OP_HALF:
+	  po_misc_or_fail (parse_half (&str));
+	  break;
+
 	  /* Register or expression */
 	case OP_RR_EXr:	  po_reg_or_goto (REG_TYPE_RN, EXPr); break;
 	case OP_RR_EXi:	  po_reg_or_goto (REG_TYPE_RN, EXPi); break;
@@ -4027,13 +5791,17 @@ parse_operands (char *str, const unsigned char *pattern)
 	  inst.operands[i].isreg = 1;
 	  break;
 
+	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
+	I32z:		  po_imm_or_fail (0, 32, FALSE);	  break;
+
 	  /* Two kinds of register */
 	case OP_RIWR_RIWC:
 	  {
 	    struct reg_entry *rege = arm_reg_parse_multi (&str);
-	    if (rege->type != REG_TYPE_MMXWR
-		&& rege->type != REG_TYPE_MMXWC
-		&& rege->type != REG_TYPE_MMXWCG)
+	    if (!rege
+		|| (rege->type != REG_TYPE_MMXWR
+		    && rege->type != REG_TYPE_MMXWC
+		    && rege->type != REG_TYPE_MMXWCG))
 	      {
 		inst.error = _("iWMMXt data or control register expected");
 		goto failure;
@@ -4043,6 +5811,21 @@ parse_operands (char *str, const unsigned char *pattern)
 	  }
 	  break;
 
+	case OP_RIWC_RIWG:
+	  {
+	    struct reg_entry *rege = arm_reg_parse_multi (&str);
+	    if (!rege
+		|| (rege->type != REG_TYPE_MMXWC
+		    && rege->type != REG_TYPE_MMXWCG))
+	      {
+		inst.error = _("iWMMXt control register expected");
+		goto failure;
+	      }
+	    inst.operands[i].reg = rege->number;
+	    inst.operands[i].isreg = 1;
+	  }
+	  break;
+
 	  /* Misc */
 	case OP_CPSF:	 val = parse_cps_flags (&str);		break;
 	case OP_ENDI:	 val = parse_endian_specifier (&str);	break;
@@ -4051,6 +5834,41 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_COND:	 val = parse_cond (&str);		break;
 	case OP_oBARRIER:val = parse_barrier (&str);		break;
 
+        case OP_RVC_PSR:
+          po_reg_or_goto (REG_TYPE_VFC, try_psr);
+          inst.operands[i].isvec = 1;  /* Mark VFP control reg as vector.  */
+          break;
+          try_psr:
+          val = parse_psr (&str);
+          break;
+
+        case OP_APSR_RR:
+          po_reg_or_goto (REG_TYPE_RN, try_apsr);
+          break;
+          try_apsr:
+          /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
+             instruction).  */
+          if (strncasecmp (str, "APSR_", 5) == 0)
+            {
+              unsigned found = 0;
+              str += 5;
+              while (found < 15)
+                switch (*str++)
+                  {
+                  case 'c': found = (found & 1) ? 16 : found | 1; break;
+                  case 'n': found = (found & 2) ? 16 : found | 2; break;
+                  case 'z': found = (found & 4) ? 16 : found | 4; break;
+                  case 'v': found = (found & 8) ? 16 : found | 8; break;
+                  default: found = 16;
+                  }
+              if (found != 15)
+                goto failure;
+              inst.operands[i].isvec = 1;
+            }
+          else
+            goto failure;
+          break;
+
 	case OP_TB:
 	  po_misc_or_fail (parse_tb (&str));
 	  break;
@@ -4066,22 +5884,65 @@ parse_operands (char *str, const unsigned char *pattern)
 	  break;
 
 	case OP_VRSLST:
-	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
 	  break;
 
 	case OP_VRDLST:
-	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
 	  break;
 
+        case OP_VRSDLST:
+          /* Allow Q registers too.  */
+          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                    REGLIST_NEON_D);
+          if (val == FAIL)
+            {
+              inst.error = NULL;
+              val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                        REGLIST_VFP_S);
+              inst.operands[i].issingle = 1;
+            }
+          break;
+
+        case OP_NRDLST:
+          val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
+                                    REGLIST_NEON_D);
+          break;
+
+	case OP_NSTRLST:
+          val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
+                                           &inst.operands[i].vectype);
+          break;
+
 	  /* Addressing modes */
 	case OP_ADDR:
 	  po_misc_or_fail (parse_address (&str, i));
 	  break;
 
+	case OP_ADDRGLDR:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDR));
+	  break;
+
+	case OP_ADDRGLDRS:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDRS));
+	  break;
+
+	case OP_ADDRGLDC:
+	  po_misc_or_fail_no_backtrack (
+            parse_address_group_reloc (&str, i, GROUP_LDC));
+	  break;
+
 	case OP_SH:
 	  po_misc_or_fail (parse_shifter_operand (&str, i));
 	  break;
 
+	case OP_SHG:
+	  po_misc_or_fail_no_backtrack (
+            parse_shifter_operand_group_reloc (&str, i));
+	  break;
+
 	case OP_oSHll:
 	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
 	  break;
@@ -4107,6 +5968,7 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_RRnpc:
 	case OP_RRnpcb:
 	case OP_RRw:
+	case OP_oRRw:
 	case OP_RRnpc_I0:
 	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
 	    inst.error = BAD_PC;
@@ -4116,11 +5978,15 @@ parse_operands (char *str, const unsigned char *pattern)
 	case OP_ENDI:
 	case OP_oROR:
 	case OP_PSR:
+        case OP_RVC_PSR:
 	case OP_COND:
 	case OP_oBARRIER:
 	case OP_REGLST:
 	case OP_VRSLST:
 	case OP_VRDLST:
+        case OP_VRSDLST:
+        case OP_NRDLST:
+        case OP_NSTRLST:
 	  if (val == FAIL)
 	    goto failure;
 	  inst.operands[i].imm = val;
@@ -4178,6 +6044,7 @@ parse_operands (char *str, const unsigned char *pattern)
 #undef po_reg_or_fail
 #undef po_reg_or_goto
 #undef po_imm_or_fail
+#undef po_scalar_or_fail
 
 /* Shorthand macro for instruction encoding functions issuing errors.  */
 #define constraint(expr, err) do {		\
@@ -4236,11 +6103,30 @@ encode_thumb32_immediate (unsigned int val)
 
   return FAIL;
 }
-/* Encode a VFP SP register number into inst.instruction.  */
+/* Encode a VFP SP or DP register number into inst.instruction.  */
 
 static void
-encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
-{
+encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
+{
+  if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
+      && reg > 15)
+    {
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
+        {
+          if (thumb_mode)
+            ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+                                    fpu_vfp_ext_v3);
+          else
+            ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
+                                    fpu_vfp_ext_v3);
+        }
+      else
+        {
+          first_error (_("D register out of range for selected VFP version"));
+          return;
+        }
+    }
+
   switch (pos)
     {
     case VFP_REG_Sd:
@@ -4255,6 +6141,18 @@ encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
       inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
       break;
 
+    case VFP_REG_Dd:
+      inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
+      break;
+    
+    case VFP_REG_Dn:
+      inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
+      break;
+    
+    case VFP_REG_Dm:
+      inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
+      break;
+
     default:
       abort ();
     }
@@ -4399,7 +6297,8 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
    into a coprocessor load/store instruction.  If wb_ok is false,
    reject use of writeback; if unind_ok is false, reject use of
    unindexed addressing.  If reloc_override is not 0, use it instead
-   of BFD_ARM_CP_OFF_IMM.  */
+   of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
+   (in which case it is preserved).  */
 
 static int
 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
@@ -4441,10 +6340,16 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
 
   if (reloc_override)
     inst.reloc.type = reloc_override;
-  else if (thumb_mode)
-    inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
-  else
-    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+  else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
+            || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
+           && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
+    {
+      if (thumb_mode)
+        inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
+      else
+        inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+    }
+
   return SUCCESS;
 }
 
@@ -4570,7 +6475,7 @@ static void
 do_rd_rm_rn (void)
 {
   unsigned Rn = inst.operands[2].reg;
-  /* Enforce resutrictions on SWP instruction.  */
+  /* Enforce restrictions on SWP instruction.  */
   if ((inst.instruction & 0x0fbfffff) == 0x01000090)
     constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
 		_("Rn must not overlap other operands"));
@@ -4894,7 +6799,11 @@ static void
 do_cpsi (void)
 {
   inst.instruction |= inst.operands[0].imm << 6;
-  inst.instruction |= inst.operands[1].imm;
+  if (inst.operands[1].present)
+    {
+      inst.instruction |= CPSI_MMOD;
+      inst.instruction |= inst.operands[1].imm;
+    }
 }
 
 static void
@@ -5112,17 +7021,16 @@ do_lstc (void)
 static void
 do_mlas (void)
 {
-  /* This restriction does not apply to mls (nor to mla in v6, but
-     that's hard to detect at present).	 */
+  /* This restriction does not apply to mls (nor to mla in v6 or later).  */
   if (inst.operands[0].reg == inst.operands[1].reg
+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
       && !(inst.instruction & 0x00400000))
-    as_tsktsk (_("rd and rm should be different in mla"));
+    as_tsktsk (_("Rd and Rm should be different in mla"));
 
   inst.instruction |= inst.operands[0].reg << 16;
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
   inst.instruction |= inst.operands[3].reg << 12;
-
 }
 
 static void
@@ -5136,15 +7044,62 @@ do_mov (void)
 static void
 do_mov16 (void)
 {
+  bfd_vma imm;
+  bfd_boolean top;
+
+  top = (inst.instruction & 0x00400000) != 0;
+  constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
+	      _(":lower16: not allowed this instruction"));
+  constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
+	      _(":upper16: not allowed instruction"));
   inst.instruction |= inst.operands[0].reg << 12;
-  /* The value is in two pieces: 0:11, 16:19.  */
-  inst.instruction |= (inst.operands[1].imm & 0x00000fff);
-  inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      imm = inst.reloc.exp.X_add_number;
+      /* The value is in two pieces: 0:11, 16:19.  */
+      inst.instruction |= (imm & 0x00000fff);
+      inst.instruction |= (imm & 0x0000f000) << 4;
+    }
+}
+
+static void do_vfp_nsyn_opcode (const char *);
+
+static int
+do_vfp_nsyn_mrs (void)
+{
+  if (inst.operands[0].isvec)
+    {
+      if (inst.operands[1].reg != 1)
+        first_error (_("operand 1 must be FPSCR"));
+      memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
+      memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
+      do_vfp_nsyn_opcode ("fmstat");
+    }
+  else if (inst.operands[1].isvec)
+    do_vfp_nsyn_opcode ("fmrx");
+  else
+    return FAIL;
+    
+  return SUCCESS;
+}
+
+static int
+do_vfp_nsyn_msr (void)
+{
+  if (inst.operands[0].isvec)
+    do_vfp_nsyn_opcode ("fmxr");
+  else
+    return FAIL;
+
+  return SUCCESS;
 }
 
 static void
 do_mrs (void)
 {
+  if (do_vfp_nsyn_mrs () == SUCCESS)
+    return;
+
   /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
   constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
 	      != (PSR_c|PSR_f),
@@ -5160,6 +7115,9 @@ do_mrs (void)
 static void
 do_msr (void)
 {
+  if (do_vfp_nsyn_msr () == SUCCESS)
+    return;
+
   inst.instruction |= inst.operands[0].imm;
   if (inst.operands[1].isreg)
     inst.instruction |= inst.operands[1].reg;
@@ -5180,8 +7138,9 @@ do_mul (void)
   inst.instruction |= inst.operands[1].reg;
   inst.instruction |= inst.operands[2].reg << 8;
 
-  if (inst.operands[0].reg == inst.operands[1].reg)
-    as_tsktsk (_("rd and rm should be different in mul"));
+  if (inst.operands[0].reg == inst.operands[1].reg
+      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
+    as_tsktsk (_("Rd and Rm should be different in mul"));
 }
 
 /* Long Multiply Parser
@@ -5447,13 +7406,25 @@ do_smul (void)
   inst.instruction |= inst.operands[2].reg << 8;
 }
 
-/* ARM V6 srs (argument parse).	 */
+/* ARM V6 srs (argument parse).  The variable fields in the encoding are
+   the same for both ARM and Thumb-2.  */
 
 static void
 do_srs (void)
 {
-  inst.instruction |= inst.operands[0].imm;
-  if (inst.operands[0].writeback)
+  int reg;
+
+  if (inst.operands[0].present)
+    {
+      reg = inst.operands[0].reg;
+      constraint (reg != 13, _("SRS base register must be r13"));
+    }
+  else
+    reg = 13;
+
+  inst.instruction |= reg << 16;
+  inst.instruction |= inst.operands[1].imm;
+  if (inst.operands[0].writeback || inst.operands[1].writeback)
     inst.instruction |= WRITE_BACK;
 }
 
@@ -5542,43 +7513,43 @@ do_sxth (void)
 static void
 do_vfp_sp_monadic (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_dyadic (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
-  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_compare_z (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
 }
 
 static void
 do_vfp_dp_sp_cvt (void)
 {
-  inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_dp_cvt (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
-  inst.instruction |= inst.operands[1].reg;
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
 }
 
 static void
 do_vfp_reg_from_sp (void)
 {
   inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
 }
 
 static void
@@ -5588,13 +7559,13 @@ do_vfp_reg2_from_sp2 (void)
 	      _("only two consecutive VFP SP registers allowed here"));
   inst.instruction |= inst.operands[0].reg << 12;
   inst.instruction |= inst.operands[1].reg << 16;
-  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
 }
 
 static void
 do_vfp_sp_from_reg (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
   inst.instruction |= inst.operands[1].reg << 12;
 }
 
@@ -5603,7 +7574,7 @@ do_vfp_sp2_from_reg2 (void)
 {
   constraint (inst.operands[0].imm != 2,
 	      _("only two consecutive VFP SP registers allowed here"));
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
   inst.instruction |= inst.operands[1].reg << 12;
   inst.instruction |= inst.operands[2].reg << 16;
 }
@@ -5611,14 +7582,14 @@ do_vfp_sp2_from_reg2 (void)
 static void
 do_vfp_sp_ldst (void)
 {
-  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
   encode_arm_cp_address (1, FALSE, TRUE, 0);
 }
 
 static void
 do_vfp_dp_ldst (void)
 {
-  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
   encode_arm_cp_address (1, FALSE, TRUE, 0);
 }
 
@@ -5632,7 +7603,7 @@ vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
     constraint (ldstm_type != VFP_LDSTMIA,
 		_("this addressing mode requires base-register writeback"));
   inst.instruction |= inst.operands[0].reg << 16;
-  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
   inst.instruction |= inst.operands[1].imm;
 }
 
@@ -5648,7 +7619,7 @@ vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
 		_("this addressing mode requires base-register writeback"));
 
   inst.instruction |= inst.operands[0].reg << 16;
-  inst.instruction |= inst.operands[1].reg << 12;
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
 
   count = inst.operands[1].imm << 1;
   if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
@@ -5692,6 +7663,103 @@ do_vfp_xp_ldstmdb (void)
 {
   vfp_dp_ldstm (VFP_LDSTMDBX);
 }
+
+static void
+do_vfp_dp_rd_rm (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
+}
+
+static void
+do_vfp_dp_rn_rd (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
+}
+
+static void
+do_vfp_dp_rd_rn (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
+}
+
+static void
+do_vfp_dp_rd_rn_rm (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
+}
+
+static void
+do_vfp_dp_rd (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+}
+
+static void
+do_vfp_dp_rm_rd_rn (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
+  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
+  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
+}
+
+/* VFPv3 instructions.  */
+static void
+do_vfp_sp_const (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
+}
+
+static void
+do_vfp_dp_const (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
+  inst.instruction |= (inst.operands[1].imm & 0x0f);
+}
+
+static void
+vfp_conv (int srcsize)
+{
+  unsigned immbits = srcsize - inst.operands[1].imm;
+  inst.instruction |= (immbits & 1) << 5;
+  inst.instruction |= (immbits >> 1);
+}
+
+static void
+do_vfp_sp_conv_16 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  vfp_conv (16);
+}
+
+static void
+do_vfp_dp_conv_16 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  vfp_conv (16);
+}
+
+static void
+do_vfp_sp_conv_32 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  vfp_conv (32);
+}
+
+static void
+do_vfp_dp_conv_32 (void)
+{
+  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
+  vfp_conv (32);
+}
+
 
 /* FPA instructions.  Also in a logical order.	*/
 
@@ -5740,6 +7808,7 @@ do_fpa_ldmstm (void)
 
   encode_arm_cp_address (2, TRUE, TRUE, 0);
 }
+
 
 /* iWMMXt instructions: strictly in alphabetical order.	 */
 
@@ -5790,6 +7859,15 @@ do_iwmmxt_waligni (void)
 }
 
 static void
+do_iwmmxt_wmerge (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 21;
+}
+
+static void
 do_iwmmxt_wmov (void)
 {
   /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
@@ -5828,7 +7906,23 @@ static void
 do_iwmmxt_wldstd (void)
 {
   inst.instruction |= inst.operands[0].reg << 12;
-  encode_arm_cp_address (1, TRUE, FALSE, 0);
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
+      && inst.operands[1].immisreg)
+    {
+      inst.instruction &= ~0x1a000ff;
+      inst.instruction |= (0xf << 28);
+      if (inst.operands[1].preind)
+	inst.instruction |= PRE_INDEX;
+      if (!inst.operands[1].negative)
+	inst.instruction |= INDEX_UP;
+      if (inst.operands[1].writeback)
+	inst.instruction |= WRITE_BACK;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.reloc.exp.X_add_number << 4;
+      inst.instruction |= inst.operands[1].imm;
+    }
+  else
+    encode_arm_cp_address (1, TRUE, FALSE, 0);
 }
 
 static void
@@ -5848,6 +7942,56 @@ do_iwmmxt_wzero (void)
   inst.instruction |= inst.operands[0].reg << 12;
   inst.instruction |= inst.operands[0].reg << 16;
 }
+
+static void
+do_iwmmxt_wrwrwr_or_imm5 (void)
+{
+  if (inst.operands[2].isreg)
+    do_rd_rn_rm ();
+  else {
+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
+		_("immediate operand requires iWMMXt2"));
+    do_rd_rn ();
+    if (inst.operands[2].imm == 0)
+      {
+	switch ((inst.instruction >> 20) & 0xf)
+	  {
+	  case 4:
+	  case 5:
+	  case 6:
+	  case 7: 
+	    /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
+	    inst.operands[2].imm = 16;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
+	    break;
+	  case 8:
+	  case 9:
+	  case 10:
+	  case 11:
+	    /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
+	    inst.operands[2].imm = 32;
+	    inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
+	    break;
+	  case 12:
+	  case 13:
+	  case 14:
+	  case 15:
+	    {
+	      /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
+	      unsigned long wrn;
+	      wrn = (inst.instruction >> 16) & 0xf;
+	      inst.instruction &= 0xff0fff0f;
+	      inst.instruction |= wrn;
+	      /* Bail out here; the instruction is now assembled.  */
+	      return;
+	    }
+	  }
+      }
+    /* Map 32 -> 0, etc.  */
+    inst.operands[2].imm &= 0x1f;
+    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
+  }
+}
 
 /* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
    operations first, then control, shift, and load/store.  */
@@ -6082,7 +8226,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(cpsie, b660, f3af8400),			\
   X(cpsid, b670, f3af8600),			\
   X(cpy,   4600, ea4f0000),			\
-  X(dec_sp,80dd, f1bd0d00),			\
+  X(dec_sp,80dd, f1ad0d00),			\
   X(eor,   4040, ea800000),			\
   X(eors,  4040, ea900000),			\
   X(inc_sp,00dd, f10d0d00),			\
@@ -6200,13 +8344,13 @@ do_t_add_sub (void)
 	narrow = (current_it_mask != 0);
       if (!inst.operands[2].isreg)
 	{
+	  int add;
+
+	  add = (inst.instruction == T_MNEM_add
+		 || inst.instruction == T_MNEM_adds);
 	  opcode = 0;
 	  if (inst.size_req != 4)
 	    {
-	      int add;
-
-	      add = (inst.instruction == T_MNEM_add
-		     || inst.instruction == T_MNEM_adds);
 	      /* Attempt to use a narrow opcode, with relaxation if
 	         appropriate.  */
 	      if (Rd == REG_SP && Rs == REG_SP && !flags)
@@ -6236,12 +8380,38 @@ do_t_add_sub (void)
 	  if (inst.size_req == 4
 	      || (inst.size_req != 2 && !opcode))
 	    {
-	      /* ??? Convert large immediates to addw/subw.  */
-	      inst.instruction = THUMB_OP32 (inst.instruction);
-	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-	      inst.instruction |= inst.operands[0].reg << 8;
-	      inst.instruction |= inst.operands[1].reg << 16;
-	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	      if (Rd == REG_PC)
+		{
+		  constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
+			     _("only SUBS PC, LR, #const allowed"));
+		  constraint (inst.reloc.exp.X_op != O_constant,
+			      _("expression too complex"));
+		  constraint (inst.reloc.exp.X_add_number < 0
+			      || inst.reloc.exp.X_add_number > 0xff,
+			     _("immediate value out of range"));
+		  inst.instruction = T2_SUBS_PC_LR
+				     | inst.reloc.exp.X_add_number;
+		  inst.reloc.type = BFD_RELOC_UNUSED;
+		  return;
+		}
+	      else if (Rs == REG_PC)
+		{
+		  /* Always use addw/subw.  */
+		  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
+		  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
+		}
+	      else
+		{
+		  inst.instruction = THUMB_OP32 (inst.instruction);
+		  inst.instruction = (inst.instruction & 0xe1ffffff)
+				     | 0x10000000;
+		  if (flags)
+		    inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+		  else
+		    inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
+		}
+	      inst.instruction |= Rd << 8;
+	      inst.instruction |= Rs << 16;
 	    }
 	}
       else
@@ -6807,7 +8977,7 @@ do_t_cpy (void)
 }
 
 static void
-do_t_czb (void)
+do_t_cbz (void)
 {
   constraint (current_it_mask, BAD_NOT_IT);
   constraint (inst.operands[0].reg > 7, BAD_HIREG);
@@ -6871,6 +9041,68 @@ do_t_it (void)
   inst.instruction |= cond << 4;
 }
 
+/* Helper function used for both push/pop and ldm/stm.  */
+static void
+encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
+{
+  bfd_boolean load;
+
+  load = (inst.instruction & (1 << 20)) != 0;
+
+  if (mask & (1 << 13))
+    inst.error =  _("SP not allowed in register list");
+  if (load)
+    {
+      if (mask & (1 << 14)
+	  && mask & (1 << 15))
+	inst.error = _("LR and PC should not both be in register list");
+
+      if ((mask & (1 << base)) != 0
+	  && writeback)
+	as_warn (_("base register should not be in register list "
+		   "when written back"));
+    }
+  else
+    {
+      if (mask & (1 << 15))
+	inst.error = _("PC not allowed in register list");
+
+      if (mask & (1 << base))
+	as_warn (_("value stored for r%d is UNPREDICTABLE"), base);
+    }
+
+  if ((mask & (mask - 1)) == 0)
+    {
+      /* Single register transfers implemented as str/ldr.  */
+      if (writeback)
+	{
+	  if (inst.instruction & (1 << 23))
+	    inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
+	  else
+	    inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
+	}
+      else
+	{
+	  if (inst.instruction & (1 << 23))
+	    inst.instruction = 0x00800000; /* ia -> [base] */
+	  else
+	    inst.instruction = 0x00000c04; /* db -> [base, #-4] */
+	}
+
+      inst.instruction |= 0xf8400000;
+      if (load)
+	inst.instruction |= 0x00100000;
+
+      mask = ffs(mask) - 1;
+      mask <<= 12;
+    }
+  else if (writeback)
+    inst.instruction |= WRITE_BACK;
+
+  inst.instruction |= mask;
+  inst.instruction |= base << 16;
+}
+
 static void
 do_t_ldmstm (void)
 {
@@ -6882,60 +9114,60 @@ do_t_ldmstm (void)
 
   if (unified_syntax)
     {
+      bfd_boolean narrow;
+      unsigned mask;
+
+      narrow = FALSE;
       /* See if we can use a 16-bit instruction.  */
       if (inst.instruction < 0xffff /* not ldmdb/stmdb */
 	  && inst.size_req != 4
-	  && inst.operands[0].reg <= 7
-	  && !(inst.operands[1].imm & ~0xff)
-	  && (inst.instruction == T_MNEM_stmia
-	      ? inst.operands[0].writeback
-	      : (inst.operands[0].writeback
-		 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
-	{
-	  if (inst.instruction == T_MNEM_stmia
-	      && (inst.operands[1].imm & (1 << inst.operands[0].reg))
-	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
-	    as_warn (_("value stored for r%d is UNPREDICTABLE"),
-		     inst.operands[0].reg);
-
-	  inst.instruction = THUMB_OP16 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << 8;
-	  inst.instruction |= inst.operands[1].imm;
-	}
-      else
+	  && !(inst.operands[1].imm & ~0xff))
 	{
-	  if (inst.operands[1].imm & (1 << 13))
-	    as_warn (_("SP should not be in register list"));
-	  if (inst.instruction == T_MNEM_stmia)
+	  mask = 1 << inst.operands[0].reg;
+
+	  if (inst.operands[0].reg <= 7
+	      && (inst.instruction == T_MNEM_stmia
+		  ? inst.operands[0].writeback
+		  : (inst.operands[0].writeback
+		     == !(inst.operands[1].imm & mask))))
 	    {
-	      if (inst.operands[1].imm & (1 << 15))
-		as_warn (_("PC should not be in register list"));
-	      if (inst.operands[1].imm & (1 << inst.operands[0].reg))
+	      if (inst.instruction == T_MNEM_stmia
+		  && (inst.operands[1].imm & mask)
+		  && (inst.operands[1].imm & (mask - 1)))
 		as_warn (_("value stored for r%d is UNPREDICTABLE"),
 			 inst.operands[0].reg);
+
+	      inst.instruction = THUMB_OP16 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].imm;
+	      narrow = TRUE;
 	    }
-	  else
+	  else if (inst.operands[0] .reg == REG_SP
+		   && inst.operands[0].writeback)
 	    {
-	      if (inst.operands[1].imm & (1 << 14)
-		  && inst.operands[1].imm & (1 << 15))
-		as_warn (_("LR and PC should not both be in register list"));
-	      if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
-		  && inst.operands[0].writeback)
-		as_warn (_("base register should not be in register list "
-			   "when written back"));
+	      inst.instruction = THUMB_OP16 (inst.instruction == T_MNEM_stmia
+					     ? T_MNEM_push : T_MNEM_pop);
+	      inst.instruction |= inst.operands[1].imm;
+	      narrow = TRUE;
 	    }
+	}
+
+      if (!narrow)
+	{
 	  if (inst.instruction < 0xffff)
 	    inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << 16;
-	  inst.instruction |= inst.operands[1].imm;
-	  if (inst.operands[0].writeback)
-	    inst.instruction |= WRITE_BACK;
+
+	  encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
+			       inst.operands[0].writeback);
 	}
     }
   else
     {
       constraint (inst.operands[0].reg > 7
 		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
+      constraint (inst.instruction != T_MNEM_ldmia
+		  && inst.instruction != T_MNEM_stmia,
+		  _("Thumb-2 instruction only valid in unified syntax"));
       if (inst.instruction == T_MNEM_stmia)
 	{
 	  if (!inst.operands[0].writeback)
@@ -7209,6 +9441,16 @@ do_t_mov_cmp (void)
 	  || inst.operands[1].shifted)
 	narrow = FALSE;
 
+      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
+      if (opcode == T_MNEM_movs && inst.operands[1].isreg
+	  && !inst.operands[1].shifted
+	  && inst.operands[0].reg == REG_PC
+	  && inst.operands[1].reg == REG_LR)
+	{
+	  inst.instruction = T2_SUBS_PC_LR;
+	  return;
+	}
+
       if (!inst.operands[1].isreg)
 	{
 	  /* Immediate operand.  */
@@ -7231,11 +9473,98 @@ do_t_mov_cmp (void)
 	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	    }
 	}
+      else if (inst.operands[1].shifted && inst.operands[1].immisreg
+	       && (inst.instruction == T_MNEM_mov
+		   || inst.instruction == T_MNEM_movs))
+	{
+	  /* Register shifts are encoded as separate shift instructions.  */
+	  bfd_boolean flags = (inst.instruction == T_MNEM_movs);
+
+	  if (current_it_mask)
+	    narrow = !flags;
+	  else
+	    narrow = flags;
+
+	  if (inst.size_req == 4)
+	    narrow = FALSE;
+
+	  if (!low_regs || inst.operands[1].imm > 7)
+	    narrow = FALSE;
+
+	  if (inst.operands[0].reg != inst.operands[1].reg)
+	    narrow = FALSE;
+
+	  switch (inst.operands[1].shift_kind)
+	    {
+	    case SHIFT_LSL:
+	      opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
+	      break;
+	    case SHIFT_ASR:
+	      opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
+	      break;
+	    case SHIFT_LSR:
+	      opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
+	      break;
+	    case SHIFT_ROR:
+	      opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
+	      break;
+	    default:
+	      abort();
+	    }
+
+	  inst.instruction = opcode;
+	  if (narrow)
+	    {
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].imm << 3;
+	    }
+	  else
+	    {
+	      if (flags)
+		inst.instruction |= CONDS_BIT;
+
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.instruction |= inst.operands[1].imm;
+	    }
+	}
       else if (!narrow)
 	{
-	  inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction |= inst.operands[0].reg << r0off;
-	  encode_thumb32_shifted_operand (1);
+	  /* Some mov with immediate shift have narrow variants.
+	     Register shifts are handled above.  */
+	  if (low_regs && inst.operands[1].shifted
+	      && (inst.instruction == T_MNEM_mov
+		  || inst.instruction == T_MNEM_movs))
+	    {
+	      if (current_it_mask)
+		narrow = (inst.instruction == T_MNEM_mov);
+	      else
+		narrow = (inst.instruction == T_MNEM_movs);
+	    }
+
+	  if (narrow)
+	    {
+	      switch (inst.operands[1].shift_kind)
+		{
+		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
+		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
+		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
+		default: narrow = FALSE; break;
+		}
+	    }
+
+	  if (narrow)
+	    {
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].reg << 3;
+	      inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+	    }
+	  else
+	    {
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << r0off;
+	      encode_thumb32_shifted_operand (1);
+	    }
 	}
       else
 	switch (inst.instruction)
@@ -7310,11 +9639,30 @@ do_t_mov_cmp (void)
 static void
 do_t_mov16 (void)
 {
+  bfd_vma imm;
+  bfd_boolean top;
+
+  top = (inst.instruction & 0x00800000) != 0;
+  if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
+    {
+      constraint (top, _(":lower16: not allowed this instruction"));
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
+    }
+  else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
+    {
+      constraint (!top, _(":upper16: not allowed this instruction"));
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
+    }
+
   inst.instruction |= inst.operands[0].reg << 8;
-  inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
-  inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
-  inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
-  inst.instruction |= (inst.operands[1].imm & 0x00ff);
+  if (inst.reloc.type == BFD_RELOC_UNUSED)
+    {
+      imm = inst.reloc.exp.X_add_number;
+      inst.instruction |= (imm & 0xf000) << 4;
+      inst.instruction |= (imm & 0x0800) << 15;
+      inst.instruction |= (imm & 0x0700) << 4;
+      inst.instruction |= (imm & 0x00ff);
+    }
 }
 
 static void
@@ -7388,6 +9736,10 @@ static void
 do_t_mrs (void)
 {
   int flags;
+
+  if (do_vfp_nsyn_mrs () == SUCCESS)
+    return;
+
   flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
   if (flags == 0)
     {
@@ -7415,6 +9767,9 @@ do_t_msr (void)
 {
   int flags;
 
+  if (do_vfp_nsyn_msr () == SUCCESS)
+    return;
+
   constraint (!inst.operands[1].isreg,
 	      _("Thumb encoding does not support an immediate here"));
   flags = inst.operands[0].imm;
@@ -7589,7 +9944,7 @@ do_t_push_pop (void)
 
   mask = inst.operands[0].imm;
   if ((mask & ~0xff) == 0)
-    inst.instruction = THUMB_OP16 (inst.instruction);
+    inst.instruction = THUMB_OP16 (inst.instruction) | mask;
   else if ((inst.instruction == T_MNEM_push
 	    && (mask & ~0xff) == 1 << REG_LR)
 	   || (inst.instruction == T_MNEM_pop
@@ -7597,43 +9952,18 @@ do_t_push_pop (void)
     {
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.instruction |= THUMB_PP_PC_LR;
-      mask &= 0xff;
+      inst.instruction |= mask & 0xff;
     }
   else if (unified_syntax)
     {
-      if (mask & (1 << 13))
-	inst.error =  _("SP not allowed in register list");
-      if (inst.instruction == T_MNEM_push)
-	{
-	  if (mask & (1 << 15))
-	    inst.error = _("PC not allowed in register list");
-	}
-      else
-	{
-	  if (mask & (1 << 14)
-	      && mask & (1 << 15))
-	    inst.error = _("LR and PC should not both be in register list");
-	}
-      if ((mask & (mask - 1)) == 0)
-	{
-	  /* Single register push/pop implemented as str/ldr.  */
-	  if (inst.instruction == T_MNEM_push)
-	    inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
-	  else
-	    inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
-	  mask = ffs(mask) - 1;
-	  mask <<= 12;
-	}
-      else
-	inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      encode_thumb2_ldmstm(13, mask, TRUE);
     }
   else
     {
       inst.error = _("invalid register list to push/pop instruction");
       return;
     }
-
-  inst.instruction |= mask;
 }
 
 static void
@@ -7678,8 +10008,37 @@ do_t_rsb (void)
   inst.instruction |= Rs << 16;
   if (!inst.operands[2].isreg)
     {
-      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+      bfd_boolean narrow;
+
+      if ((inst.instruction & 0x00100000) != 0)
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
+
+      if (Rd > 7 || Rs > 7)
+	narrow = FALSE;
+
+      if (inst.size_req == 4 || !unified_syntax)
+	narrow = FALSE;
+
+      if (inst.reloc.exp.X_op != O_constant
+	  || inst.reloc.exp.X_add_number != 0)
+	narrow = FALSE;
+
+      /* Turn rsb #0 into 16-bit neg.  We should probably do this via
+         relaxation, but it doesn't seem worth the hassle.  */
+      if (narrow)
+	{
+	  inst.reloc.type = BFD_RELOC_UNUSED;
+	  inst.instruction = THUMB_OP16 (T_MNEM_negs);
+	  inst.instruction |= Rs << 3;
+	  inst.instruction |= Rd;
+	}
+      else
+	{
+	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
     }
   else
     encode_thumb32_shifted_operand (2);
@@ -7997,6 +10356,3387 @@ do_t_usat16 (void)
   inst.instruction |= inst.operands[1].imm;
   inst.instruction |= inst.operands[2].reg << 16;
 }
+
+/* Neon instruction encoder helpers.  */
+  
+/* Encodings for the different types for various Neon opcodes.  */
+
+/* An "invalid" code for the following tables.  */
+#define N_INV -1u
+
+struct neon_tab_entry
+{
+  unsigned integer;
+  unsigned float_or_poly;
+  unsigned scalar_or_imm;
+};
+  
+/* Map overloaded Neon opcodes to their respective encodings.  */
+#define NEON_ENC_TAB					\
+  X(vabd,	0x0000700, 0x1200d00, N_INV),		\
+  X(vmax,	0x0000600, 0x0000f00, N_INV),		\
+  X(vmin,	0x0000610, 0x0200f00, N_INV),		\
+  X(vpadd,	0x0000b10, 0x1000d00, N_INV),		\
+  X(vpmax,	0x0000a00, 0x1000f00, N_INV),		\
+  X(vpmin,	0x0000a10, 0x1200f00, N_INV),		\
+  X(vadd,	0x0000800, 0x0000d00, N_INV),		\
+  X(vsub,	0x1000800, 0x0200d00, N_INV),		\
+  X(vceq,	0x1000810, 0x0000e00, 0x1b10100),	\
+  X(vcge,	0x0000310, 0x1000e00, 0x1b10080),	\
+  X(vcgt,	0x0000300, 0x1200e00, 0x1b10000),	\
+  /* Register variants of the following two instructions are encoded as
+     vcge / vcgt with the operands reversed. */  	\
+  X(vclt,	0x0000300, 0x1200e00, 0x1b10200),	\
+  X(vcle,	0x0000310, 0x1000e00, 0x1b10180),	\
+  X(vmla,	0x0000900, 0x0000d10, 0x0800040),	\
+  X(vmls,	0x1000900, 0x0200d10, 0x0800440),	\
+  X(vmul,	0x0000910, 0x1000d10, 0x0800840),	\
+  X(vmull,	0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float.  */ \
+  X(vmlal,	0x0800800, N_INV,     0x0800240),	\
+  X(vmlsl,	0x0800a00, N_INV,     0x0800640),	\
+  X(vqdmlal,	0x0800900, N_INV,     0x0800340),	\
+  X(vqdmlsl,	0x0800b00, N_INV,     0x0800740),	\
+  X(vqdmull,	0x0800d00, N_INV,     0x0800b40),	\
+  X(vqdmulh,    0x0000b00, N_INV,     0x0800c40),	\
+  X(vqrdmulh,   0x1000b00, N_INV,     0x0800d40),	\
+  X(vshl,	0x0000400, N_INV,     0x0800510),	\
+  X(vqshl,	0x0000410, N_INV,     0x0800710),	\
+  X(vand,	0x0000110, N_INV,     0x0800030),	\
+  X(vbic,	0x0100110, N_INV,     0x0800030),	\
+  X(veor,	0x1000110, N_INV,     N_INV),		\
+  X(vorn,	0x0300110, N_INV,     0x0800010),	\
+  X(vorr,	0x0200110, N_INV,     0x0800010),	\
+  X(vmvn,	0x1b00580, N_INV,     0x0800030),	\
+  X(vshll,	0x1b20300, N_INV,     0x0800a10), /* max shift, immediate.  */ \
+  X(vcvt,       0x1b30600, N_INV,     0x0800e10), /* integer, fixed-point.  */ \
+  X(vdup,       0xe800b10, N_INV,     0x1b00c00), /* arm, scalar.  */ \
+  X(vld1,       0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup.  */ \
+  X(vst1,	0x0000000, 0x0800000, N_INV),		\
+  X(vld2,	0x0200100, 0x0a00100, 0x0a00d00),	\
+  X(vst2,	0x0000100, 0x0800100, N_INV),		\
+  X(vld3,	0x0200200, 0x0a00200, 0x0a00e00),	\
+  X(vst3,	0x0000200, 0x0800200, N_INV),		\
+  X(vld4,	0x0200300, 0x0a00300, 0x0a00f00),	\
+  X(vst4,	0x0000300, 0x0800300, N_INV),		\
+  X(vmovn,	0x1b20200, N_INV,     N_INV),		\
+  X(vtrn,	0x1b20080, N_INV,     N_INV),		\
+  X(vqmovn,	0x1b20200, N_INV,     N_INV),		\
+  X(vqmovun,	0x1b20240, N_INV,     N_INV),		\
+  X(vnmul,      0xe200a40, 0xe200b40, N_INV),		\
+  X(vnmla,      0xe000a40, 0xe000b40, N_INV),		\
+  X(vnmls,      0xe100a40, 0xe100b40, N_INV),		\
+  X(vcmp,	0xeb40a40, 0xeb40b40, N_INV),		\
+  X(vcmpz,	0xeb50a40, 0xeb50b40, N_INV),		\
+  X(vcmpe,	0xeb40ac0, 0xeb40bc0, N_INV),		\
+  X(vcmpez,     0xeb50ac0, 0xeb50bc0, N_INV)
+
+enum neon_opc
+{
+#define X(OPC,I,F,S) N_MNEM_##OPC
+NEON_ENC_TAB
+#undef X
+};
+
+static const struct neon_tab_entry neon_enc_tab[] =
+{
+#define X(OPC,I,F,S) { (I), (F), (S) }
+NEON_ENC_TAB
+#undef X
+};
+
+#define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_ARMREG(X)  (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_POLY(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_FLOAT(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_SCALAR(X)  (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_IMMED(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
+#define NEON_ENC_LANE(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
+#define NEON_ENC_DUP(X)     (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
+#define NEON_ENC_SINGLE(X) \
+  ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
+#define NEON_ENC_DOUBLE(X) \
+  ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
+
+/* Define shapes for instruction operands. The following mnemonic characters
+   are used in this table:
+
+     F - VFP S<n> register
+     D - Neon D<n> register
+     Q - Neon Q<n> register
+     I - Immediate
+     S - Scalar
+     R - ARM register
+     L - D<n> register list
+   
+   This table is used to generate various data:
+     - enumerations of the form NS_DDR to be used as arguments to
+       neon_select_shape.
+     - a table classifying shapes into single, double, quad, mixed.
+     - a table used to drive neon_select_shape.
+*/
+
+#define NEON_SHAPE_DEF			\
+  X(3, (D, D, D), DOUBLE),		\
+  X(3, (Q, Q, Q), QUAD),		\
+  X(3, (D, D, I), DOUBLE),		\
+  X(3, (Q, Q, I), QUAD),		\
+  X(3, (D, D, S), DOUBLE),		\
+  X(3, (Q, Q, S), QUAD),		\
+  X(2, (D, D), DOUBLE),			\
+  X(2, (Q, Q), QUAD),			\
+  X(2, (D, S), DOUBLE),			\
+  X(2, (Q, S), QUAD),			\
+  X(2, (D, R), DOUBLE),			\
+  X(2, (Q, R), QUAD),			\
+  X(2, (D, I), DOUBLE),			\
+  X(2, (Q, I), QUAD),			\
+  X(3, (D, L, D), DOUBLE),		\
+  X(2, (D, Q), MIXED),			\
+  X(2, (Q, D), MIXED),			\
+  X(3, (D, Q, I), MIXED),		\
+  X(3, (Q, D, I), MIXED),		\
+  X(3, (Q, D, D), MIXED),		\
+  X(3, (D, Q, Q), MIXED),		\
+  X(3, (Q, Q, D), MIXED),		\
+  X(3, (Q, D, S), MIXED),		\
+  X(3, (D, Q, S), MIXED),		\
+  X(4, (D, D, D, I), DOUBLE),		\
+  X(4, (Q, Q, Q, I), QUAD),		\
+  X(2, (F, F), SINGLE),			\
+  X(3, (F, F, F), SINGLE),		\
+  X(2, (F, I), SINGLE),			\
+  X(2, (F, D), MIXED),			\
+  X(2, (D, F), MIXED),			\
+  X(3, (F, F, I), MIXED),		\
+  X(4, (R, R, F, F), SINGLE),		\
+  X(4, (F, F, R, R), SINGLE),		\
+  X(3, (D, R, R), DOUBLE),		\
+  X(3, (R, R, D), DOUBLE),		\
+  X(2, (S, R), SINGLE),			\
+  X(2, (R, S), SINGLE),			\
+  X(2, (F, R), SINGLE),			\
+  X(2, (R, F), SINGLE)
+
+#define S2(A,B)		NS_##A##B
+#define S3(A,B,C)	NS_##A##B##C
+#define S4(A,B,C,D)	NS_##A##B##C##D
+
+#define X(N, L, C) S##N L
+
+enum neon_shape
+{
+  NEON_SHAPE_DEF,
+  NS_NULL
+};
+
+#undef X
+#undef S2
+#undef S3
+#undef S4
+
+enum neon_shape_class
+{
+  SC_SINGLE,
+  SC_DOUBLE,
+  SC_QUAD,
+  SC_MIXED
+};
+
+#define X(N, L, C) SC_##C
+
+static enum neon_shape_class neon_shape_class[] =
+{
+  NEON_SHAPE_DEF
+};
+
+#undef X
+
+enum neon_shape_el
+{
+  SE_F,
+  SE_D,
+  SE_Q,
+  SE_I,
+  SE_S,
+  SE_R,
+  SE_L
+};
+
+/* Register widths of above.  */
+static unsigned neon_shape_el_size[] =
+{
+  32,
+  64,
+  128,
+  0,
+  32,
+  32,
+  0
+};
+
+struct neon_shape_info
+{
+  unsigned els;
+  enum neon_shape_el el[NEON_MAX_TYPE_ELS];
+};
+
+#define S2(A,B)		{ SE_##A, SE_##B }
+#define S3(A,B,C)	{ SE_##A, SE_##B, SE_##C }
+#define S4(A,B,C,D)	{ SE_##A, SE_##B, SE_##C, SE_##D }
+
+#define X(N, L, C) { N, S##N L }
+
+static struct neon_shape_info neon_shape_tab[] =
+{
+  NEON_SHAPE_DEF
+};
+
+#undef X
+#undef S2
+#undef S3
+#undef S4
+
+/* Bit masks used in type checking given instructions.
+  'N_EQK' means the type must be the same as (or based on in some way) the key
+   type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
+   set, various other bits can be set as well in order to modify the meaning of
+   the type constraint.  */
+
+enum neon_type_mask
+{
+  N_S8   = 0x000001,
+  N_S16  = 0x000002,
+  N_S32  = 0x000004,
+  N_S64  = 0x000008,
+  N_U8   = 0x000010,
+  N_U16  = 0x000020,
+  N_U32  = 0x000040,
+  N_U64  = 0x000080,
+  N_I8   = 0x000100,
+  N_I16  = 0x000200,
+  N_I32  = 0x000400,
+  N_I64  = 0x000800,
+  N_8    = 0x001000,
+  N_16   = 0x002000,
+  N_32   = 0x004000,
+  N_64   = 0x008000,
+  N_P8   = 0x010000,
+  N_P16  = 0x020000,
+  N_F32  = 0x040000,
+  N_F64  = 0x080000,
+  N_KEY  = 0x100000, /* key element (main type specifier).  */
+  N_EQK  = 0x200000, /* given operand has the same type & size as the key.  */
+  N_VFP  = 0x400000, /* VFP mode: operand size must match register width.  */
+  N_DBL  = 0x000001, /* if N_EQK, this operand is twice the size.  */
+  N_HLF  = 0x000002, /* if N_EQK, this operand is half the size.  */
+  N_SGN  = 0x000004, /* if N_EQK, this operand is forced to be signed.  */
+  N_UNS  = 0x000008, /* if N_EQK, this operand is forced to be unsigned.  */
+  N_INT  = 0x000010, /* if N_EQK, this operand is forced to be integer.  */
+  N_FLT  = 0x000020, /* if N_EQK, this operand is forced to be float.  */
+  N_SIZ  = 0x000040, /* if N_EQK, this operand is forced to be size-only.  */
+  N_UTYP = 0,
+  N_MAX_NONSPECIAL = N_F64
+};
+
+#define N_ALLMODS  (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
+
+#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
+#define N_SU_32    (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
+#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
+#define N_SUF_32   (N_SU_32 | N_F32)
+#define N_I_ALL    (N_I8 | N_I16 | N_I32 | N_I64)
+#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F32)
+
+/* Pass this as the first type argument to neon_check_type to ignore types
+   altogether.  */
+#define N_IGNORE_TYPE (N_KEY | N_EQK)
+
+/* Select a "shape" for the current instruction (describing register types or
+   sizes) from a list of alternatives. Return NS_NULL if the current instruction
+   doesn't fit. For non-polymorphic shapes, checking is usually done as a
+   function of operand parsing, so this function doesn't need to be called.
+   Shapes should be listed in order of decreasing length.  */
+
+static enum neon_shape
+neon_select_shape (enum neon_shape shape, ...)
+{
+  va_list ap;
+  enum neon_shape first_shape = shape;
+
+  /* Fix missing optional operands. FIXME: we don't know at this point how
+     many arguments we should have, so this makes the assumption that we have
+     > 1. This is true of all current Neon opcodes, I think, but may not be
+     true in the future.  */
+  if (!inst.operands[1].present)
+    inst.operands[1] = inst.operands[0];
+
+  va_start (ap, shape);
+  
+  for (; shape != NS_NULL; shape = va_arg (ap, int))
+    {
+      unsigned j;
+      int matches = 1;
+
+      for (j = 0; j < neon_shape_tab[shape].els; j++)
+        {
+          if (!inst.operands[j].present)
+            {
+              matches = 0;
+              break;
+            }
+
+          switch (neon_shape_tab[shape].el[j])
+            {
+            case SE_F:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && inst.operands[j].issingle
+                    && !inst.operands[j].isquad))
+                matches = 0;
+              break;
+
+            case SE_D:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && !inst.operands[j].isquad
+                    && !inst.operands[j].issingle))
+                matches = 0;
+              break;
+
+            case SE_R:
+              if (!(inst.operands[j].isreg
+                    && !inst.operands[j].isvec))
+                matches = 0;
+              break;
+
+            case SE_Q:
+              if (!(inst.operands[j].isreg
+                    && inst.operands[j].isvec
+                    && inst.operands[j].isquad
+                    && !inst.operands[j].issingle))
+                matches = 0;
+              break;
+
+            case SE_I:
+              if (!(!inst.operands[j].isreg
+                    && !inst.operands[j].isscalar))
+                matches = 0;
+              break;
+
+            case SE_S:
+              if (!(!inst.operands[j].isreg
+                    && inst.operands[j].isscalar))
+                matches = 0;
+              break;
+
+            case SE_L:
+              break;
+            }
+        }
+      if (matches)
+        break;
+    }
+  
+  va_end (ap);
+
+  if (shape == NS_NULL && first_shape != NS_NULL)
+    first_error (_("invalid instruction shape"));
+
+  return shape;
+}
+
+/* True if SHAPE is predominantly a quadword operation (most of the time, this
+   means the Q bit should be set).  */
+
+static int
+neon_quad (enum neon_shape shape)
+{
+  return neon_shape_class[shape] == SC_QUAD;
+}
+
+static void
+neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
+                       unsigned *g_size)
+{
+  /* Allow modification to be made to types which are constrained to be
+     based on the key element, based on bits set alongside N_EQK.  */
+  if ((typebits & N_EQK) != 0)
+    {
+      if ((typebits & N_HLF) != 0)
+	*g_size /= 2;
+      else if ((typebits & N_DBL) != 0)
+	*g_size *= 2;
+      if ((typebits & N_SGN) != 0)
+	*g_type = NT_signed;
+      else if ((typebits & N_UNS) != 0)
+        *g_type = NT_unsigned;
+      else if ((typebits & N_INT) != 0)
+        *g_type = NT_integer;
+      else if ((typebits & N_FLT) != 0)
+        *g_type = NT_float;
+      else if ((typebits & N_SIZ) != 0)
+        *g_type = NT_untyped;
+    }
+}
+  
+/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
+   operand type, i.e. the single type specified in a Neon instruction when it
+   is the only one given.  */
+
+static struct neon_type_el
+neon_type_promote (struct neon_type_el *key, unsigned thisarg)
+{
+  struct neon_type_el dest = *key;
+  
+  assert ((thisarg & N_EQK) != 0);
+  
+  neon_modify_type_size (thisarg, &dest.type, &dest.size);
+
+  return dest;
+}
+
+/* Convert Neon type and size into compact bitmask representation.  */
+
+static enum neon_type_mask
+type_chk_of_el_type (enum neon_el_type type, unsigned size)
+{
+  switch (type)
+    {
+    case NT_untyped:
+      switch (size)
+        {
+        case 8:  return N_8;
+        case 16: return N_16;
+        case 32: return N_32;
+        case 64: return N_64;
+        default: ;
+        }
+      break;
+
+    case NT_integer:
+      switch (size)
+        {
+        case 8:  return N_I8;
+        case 16: return N_I16;
+        case 32: return N_I32;
+        case 64: return N_I64;
+        default: ;
+        }
+      break;
+
+    case NT_float:
+      switch (size)
+        {
+        case 32: return N_F32;
+        case 64: return N_F64;
+        default: ;
+        }
+      break;
+
+    case NT_poly:
+      switch (size)
+        {
+        case 8:  return N_P8;
+        case 16: return N_P16;
+        default: ;
+        }
+      break;
+
+    case NT_signed:
+      switch (size)
+        {
+        case 8:  return N_S8;
+        case 16: return N_S16;
+        case 32: return N_S32;
+        case 64: return N_S64;
+        default: ;
+        }
+      break;
+
+    case NT_unsigned:
+      switch (size)
+        {
+        case 8:  return N_U8;
+        case 16: return N_U16;
+        case 32: return N_U32;
+        case 64: return N_U64;
+        default: ;
+        }
+      break;
+
+    default: ;
+    }
+  
+  return N_UTYP;
+}
+
+/* Convert compact Neon bitmask type representation to a type and size. Only
+   handles the case where a single bit is set in the mask.  */
+
+static int
+el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
+                     enum neon_type_mask mask)
+{
+  if ((mask & N_EQK) != 0)
+    return FAIL;
+
+  if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
+    *size = 8;
+  else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
+    *size = 16;
+  else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
+    *size = 32;
+  else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
+    *size = 64;
+  else
+    return FAIL;
+
+  if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
+    *type = NT_signed;
+  else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
+    *type = NT_unsigned;
+  else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
+    *type = NT_integer;
+  else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
+    *type = NT_untyped;
+  else if ((mask & (N_P8 | N_P16)) != 0)
+    *type = NT_poly;
+  else if ((mask & (N_F32 | N_F64)) != 0)
+    *type = NT_float;
+  else
+    return FAIL;
+  
+  return SUCCESS;
+}
+
+/* Modify a bitmask of allowed types. This is only needed for type
+   relaxation.  */
+
+static unsigned
+modify_types_allowed (unsigned allowed, unsigned mods)
+{
+  unsigned size;
+  enum neon_el_type type;
+  unsigned destmask;
+  int i;
+  
+  destmask = 0;
+  
+  for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
+    {
+      if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
+        {
+          neon_modify_type_size (mods, &type, &size);
+          destmask |= type_chk_of_el_type (type, size);
+        }
+    }
+  
+  return destmask;
+}
+
+/* Check type and return type classification.
+   The manual states (paraphrase): If one datatype is given, it indicates the
+   type given in:
+    - the second operand, if there is one
+    - the operand, if there is no second operand
+    - the result, if there are no operands.
+   This isn't quite good enough though, so we use a concept of a "key" datatype
+   which is set on a per-instruction basis, which is the one which matters when
+   only one data type is written.
+   Note: this function has side-effects (e.g. filling in missing operands). All
+   Neon instructions should call it before performing bit encoding.  */
+
+static struct neon_type_el
+neon_check_type (unsigned els, enum neon_shape ns, ...)
+{
+  va_list ap;
+  unsigned i, pass, key_el = 0;
+  unsigned types[NEON_MAX_TYPE_ELS];
+  enum neon_el_type k_type = NT_invtype;
+  unsigned k_size = -1u;
+  struct neon_type_el badtype = {NT_invtype, -1};
+  unsigned key_allowed = 0;
+
+  /* Optional registers in Neon instructions are always (not) in operand 1.
+     Fill in the missing operand here, if it was omitted.  */
+  if (els > 1 && !inst.operands[1].present)
+    inst.operands[1] = inst.operands[0];
+
+  /* Suck up all the varargs.  */
+  va_start (ap, ns);
+  for (i = 0; i < els; i++)
+    {
+      unsigned thisarg = va_arg (ap, unsigned);
+      if (thisarg == N_IGNORE_TYPE)
+        {
+          va_end (ap);
+          return badtype;
+        }
+      types[i] = thisarg;
+      if ((thisarg & N_KEY) != 0)
+        key_el = i;
+    }
+  va_end (ap);
+
+  if (inst.vectype.elems > 0)
+    for (i = 0; i < els; i++)
+      if (inst.operands[i].vectype.type != NT_invtype)
+        {
+          first_error (_("types specified in both the mnemonic and operands"));
+          return badtype;
+        }
+
+  /* Duplicate inst.vectype elements here as necessary.
+     FIXME: No idea if this is exactly the same as the ARM assembler,
+     particularly when an insn takes one register and one non-register
+     operand. */
+  if (inst.vectype.elems == 1 && els > 1)
+    {
+      unsigned j;
+      inst.vectype.elems = els;
+      inst.vectype.el[key_el] = inst.vectype.el[0];
+      for (j = 0; j < els; j++)
+        if (j != key_el)
+          inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
+                                                  types[j]);
+    }
+  else if (inst.vectype.elems == 0 && els > 0)
+    {
+      unsigned j;
+      /* No types were given after the mnemonic, so look for types specified
+         after each operand. We allow some flexibility here; as long as the
+         "key" operand has a type, we can infer the others.  */
+      for (j = 0; j < els; j++)
+        if (inst.operands[j].vectype.type != NT_invtype)
+          inst.vectype.el[j] = inst.operands[j].vectype;
+
+      if (inst.operands[key_el].vectype.type != NT_invtype)
+        {
+          for (j = 0; j < els; j++)
+            if (inst.operands[j].vectype.type == NT_invtype)
+              inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
+                                                      types[j]);
+        }
+      else
+        {
+          first_error (_("operand types can't be inferred"));
+          return badtype;
+        }
+    }
+  else if (inst.vectype.elems != els)
+    {
+      first_error (_("type specifier has the wrong number of parts"));
+      return badtype;
+    }
+
+  for (pass = 0; pass < 2; pass++)
+    {
+      for (i = 0; i < els; i++)
+        {
+          unsigned thisarg = types[i];
+          unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
+            ? modify_types_allowed (key_allowed, thisarg) : thisarg;
+          enum neon_el_type g_type = inst.vectype.el[i].type;
+          unsigned g_size = inst.vectype.el[i].size;
+
+          /* Decay more-specific signed & unsigned types to sign-insensitive
+	     integer types if sign-specific variants are unavailable.  */
+          if ((g_type == NT_signed || g_type == NT_unsigned)
+	      && (types_allowed & N_SU_ALL) == 0)
+	    g_type = NT_integer;
+
+          /* If only untyped args are allowed, decay any more specific types to
+	     them. Some instructions only care about signs for some element
+	     sizes, so handle that properly.  */
+          if ((g_size == 8 && (types_allowed & N_8) != 0)
+	      || (g_size == 16 && (types_allowed & N_16) != 0)
+	      || (g_size == 32 && (types_allowed & N_32) != 0)
+	      || (g_size == 64 && (types_allowed & N_64) != 0))
+	    g_type = NT_untyped;
+
+          if (pass == 0)
+            {
+              if ((thisarg & N_KEY) != 0)
+                {
+                  k_type = g_type;
+                  k_size = g_size;
+                  key_allowed = thisarg & ~N_KEY;
+                }
+            }
+          else
+            {
+              if ((thisarg & N_VFP) != 0)
+                {
+                  enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
+                  unsigned regwidth = neon_shape_el_size[regshape], match;
+
+                  /* In VFP mode, operands must match register widths. If we
+                     have a key operand, use its width, else use the width of
+                     the current operand.  */
+                  if (k_size != -1u)
+                    match = k_size;
+                  else
+                    match = g_size;
+
+                  if (regwidth != match)
+                    {
+                      first_error (_("operand size must match register width"));
+                      return badtype;
+                    }
+                }
+            
+              if ((thisarg & N_EQK) == 0)
+                {
+                  unsigned given_type = type_chk_of_el_type (g_type, g_size);
+
+                  if ((given_type & types_allowed) == 0)
+                    {
+	              first_error (_("bad type in Neon instruction"));
+	              return badtype;
+                    }
+                }
+              else
+                {
+                  enum neon_el_type mod_k_type = k_type;
+                  unsigned mod_k_size = k_size;
+                  neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
+                  if (g_type != mod_k_type || g_size != mod_k_size)
+                    {
+                      first_error (_("inconsistent types in Neon instruction"));
+                      return badtype;
+                    }
+                }
+            }
+        }
+    }
+
+  return inst.vectype.el[key_el];
+}
+
+/* Neon-style VFP instruction forwarding.  */
+
+/* Thumb VFP instructions have 0xE in the condition field.  */
+
+static void
+do_vfp_cond_or_thumb (void)
+{
+  if (thumb_mode)
+    inst.instruction |= 0xe0000000;
+  else
+    inst.instruction |= inst.cond << 28;
+}
+
+/* Look up and encode a simple mnemonic, for use as a helper function for the
+   Neon-style VFP syntax.  This avoids duplication of bits of the insns table,
+   etc.  It is assumed that operand parsing has already been done, and that the
+   operands are in the form expected by the given opcode (this isn't necessarily
+   the same as the form in which they were parsed, hence some massaging must
+   take place before this function is called).
+   Checks current arch version against that in the looked-up opcode.  */
+
+static void
+do_vfp_nsyn_opcode (const char *opname)
+{
+  const struct asm_opcode *opcode;
+  
+  opcode = hash_find (arm_ops_hsh, opname);
+
+  if (!opcode)
+    abort ();
+
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
+                thumb_mode ? *opcode->tvariant : *opcode->avariant),
+              _(BAD_FPU));
+
+  if (thumb_mode)
+    {
+      inst.instruction = opcode->tvalue;
+      opcode->tencode ();
+    }
+  else
+    {
+      inst.instruction = (inst.cond << 28) | opcode->avalue;
+      opcode->aencode ();
+    }
+}
+
+static void
+do_vfp_nsyn_add_sub (enum neon_shape rs)
+{
+  int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
+
+  if (rs == NS_FFF)
+    {
+      if (is_add)
+        do_vfp_nsyn_opcode ("fadds");
+      else
+        do_vfp_nsyn_opcode ("fsubs");
+    }
+  else
+    {
+      if (is_add)
+        do_vfp_nsyn_opcode ("faddd");
+      else
+        do_vfp_nsyn_opcode ("fsubd");
+    }
+}
+
+/* Check operand types to see if this is a VFP instruction, and if so call
+   PFN ().  */
+
+static int
+try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
+{
+  enum neon_shape rs;
+  struct neon_type_el et;
+
+  switch (args)
+    {
+    case 2:
+      rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+      et = neon_check_type (2, rs,
+        N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      break;
+    
+    case 3:
+      rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+      et = neon_check_type (3, rs,
+        N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (et.type != NT_invtype)
+    {
+      pfn (rs);
+      return SUCCESS;
+    }
+  else
+    inst.error = NULL;
+
+  return FAIL;
+}
+
+static void
+do_vfp_nsyn_mla_mls (enum neon_shape rs)
+{
+  int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
+  
+  if (rs == NS_FFF)
+    {
+      if (is_mla)
+        do_vfp_nsyn_opcode ("fmacs");
+      else
+        do_vfp_nsyn_opcode ("fmscs");
+    }
+  else
+    {
+      if (is_mla)
+        do_vfp_nsyn_opcode ("fmacd");
+      else
+        do_vfp_nsyn_opcode ("fmscd");
+    }
+}
+
+static void
+do_vfp_nsyn_mul (enum neon_shape rs)
+{
+  if (rs == NS_FFF)
+    do_vfp_nsyn_opcode ("fmuls");
+  else
+    do_vfp_nsyn_opcode ("fmuld");
+}
+
+static void
+do_vfp_nsyn_abs_neg (enum neon_shape rs)
+{
+  int is_neg = (inst.instruction & 0x80) != 0;
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
+
+  if (rs == NS_FF)
+    {
+      if (is_neg)
+        do_vfp_nsyn_opcode ("fnegs");
+      else
+        do_vfp_nsyn_opcode ("fabss");
+    }
+  else
+    {
+      if (is_neg)
+        do_vfp_nsyn_opcode ("fnegd");
+      else
+        do_vfp_nsyn_opcode ("fabsd");
+    }
+}
+
+/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
+   insns belong to Neon, and are handled elsewhere.  */
+
+static void
+do_vfp_nsyn_ldm_stm (int is_dbmode)
+{
+  int is_ldm = (inst.instruction & (1 << 20)) != 0;
+  if (is_ldm)
+    {
+      if (is_dbmode)
+        do_vfp_nsyn_opcode ("fldmdbs");
+      else
+        do_vfp_nsyn_opcode ("fldmias");
+    }
+  else
+    {
+      if (is_dbmode)
+        do_vfp_nsyn_opcode ("fstmdbs");
+      else
+        do_vfp_nsyn_opcode ("fstmias");
+    }
+}
+
+static void
+do_vfp_nsyn_sqrt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+  neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      
+  if (rs == NS_FF)
+    do_vfp_nsyn_opcode ("fsqrts");
+  else
+    do_vfp_nsyn_opcode ("fsqrtd");
+}
+
+static void
+do_vfp_nsyn_div (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
+    N_F32 | N_F64 | N_KEY | N_VFP);
+  
+  if (rs == NS_FFF)
+    do_vfp_nsyn_opcode ("fdivs");
+  else
+    do_vfp_nsyn_opcode ("fdivd");
+}
+
+static void
+do_vfp_nsyn_nmul (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
+  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
+    N_F32 | N_F64 | N_KEY | N_VFP);
+  
+  if (rs == NS_FFF)
+    {
+      inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+      do_vfp_sp_dyadic ();
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+      do_vfp_dp_rd_rn_rm ();
+    }
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+do_vfp_nsyn_cmp (void)
+{
+  if (inst.operands[1].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
+      neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
+      
+      if (rs == NS_FF)
+        {
+          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+          do_vfp_sp_monadic ();
+        }
+      else
+        {
+          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+          do_vfp_dp_rd_rm ();
+        }
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
+      neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
+
+      switch (inst.instruction & 0x0fffffff)
+        {
+        case N_MNEM_vcmp:
+          inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
+          break;
+        case N_MNEM_vcmpe:
+          inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
+          break;
+        default:
+          abort ();
+        }
+     
+      if (rs == NS_FI)
+        {
+          inst.instruction = NEON_ENC_SINGLE (inst.instruction);
+          do_vfp_sp_compare_z ();
+        }
+      else
+        {
+          inst.instruction = NEON_ENC_DOUBLE (inst.instruction);
+          do_vfp_dp_rd ();
+        }
+    }
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+nsyn_insert_sp (void)
+{
+  inst.operands[1] = inst.operands[0];
+  memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
+  inst.operands[0].reg = 13;
+  inst.operands[0].isreg = 1;
+  inst.operands[0].writeback = 1;
+  inst.operands[0].present = 1;
+}
+
+static void
+do_vfp_nsyn_push (void)
+{
+  nsyn_insert_sp ();
+  if (inst.operands[1].issingle)
+    do_vfp_nsyn_opcode ("fstmdbs");
+  else
+    do_vfp_nsyn_opcode ("fstmdbd");
+}
+
+static void
+do_vfp_nsyn_pop (void)
+{
+  nsyn_insert_sp ();
+  if (inst.operands[1].issingle)
+    do_vfp_nsyn_opcode ("fldmias");
+  else
+    do_vfp_nsyn_opcode ("fldmiad");
+}
+
+/* Fix up Neon data-processing instructions, ORing in the correct bits for
+   ARM mode or Thumb mode and moving the encoded bit 24 to bit 28.  */
+
+static unsigned
+neon_dp_fixup (unsigned i)
+{
+  if (thumb_mode)
+    {
+      /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode.  */
+      if (i & (1 << 24))
+        i |= 1 << 28;
+      
+      i &= ~(1 << 24);
+      
+      i |= 0xef000000;
+    }
+  else
+    i |= 0xf2000000;
+  
+  return i;
+}
+
+/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
+   (0, 1, 2, 3).  */
+
+static unsigned
+neon_logbits (unsigned x)
+{
+  return ffs (x) - 4;
+}
+
+#define LOW4(R) ((R) & 0xf)
+#define HI1(R) (((R) >> 4) & 1)
+
+/* Encode insns with bit pattern:
+
+  |28/24|23|22 |21 20|19 16|15 12|11    8|7|6|5|4|3  0|
+  |  U  |x |D  |size | Rn  | Rd  |x x x x|N|Q|M|x| Rm |
+  
+  SIZE is passed in bits. -1 means size field isn't changed, in case it has a
+  different meaning for some instruction.  */
+
+static void
+neon_three_same (int isquad, int ubit, int size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= (isquad != 0) << 6;
+  inst.instruction |= (ubit != 0) << 24;
+  if (size != -1)
+    inst.instruction |= neon_logbits (size) << 20;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Encode instructions of the form:
+
+  |28/24|23|22|21 20|19 18|17 16|15 12|11      7|6|5|4|3  0|
+  |  U  |x |D |x  x |size |x  x | Rd  |x x x x x|Q|M|x| Rm |
+
+  Don't write size if SIZE == -1.  */
+
+static void
+neon_two_same (int qbit, int ubit, int size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= (qbit != 0) << 6;
+  inst.instruction |= (ubit != 0) << 24;
+
+  if (size != -1)
+    inst.instruction |= neon_logbits (size) << 18;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Neon instruction encoders, in approximate order of appearance.  */
+
+static void
+do_neon_dyadic_i_su (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_32 | N_KEY);
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static void
+do_neon_dyadic_i64_su (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_ALL | N_KEY);
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static void
+neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
+                unsigned immbits)
+{
+  unsigned size = et.size >> 3;
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= (isquad != 0) << 6;
+  inst.instruction |= immbits << 16;
+  inst.instruction |= (size >> 3) << 7;
+  inst.instruction |= (size & 0x7) << 19;
+  if (write_ubit)
+    inst.instruction |= (uval != 0) << 24;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_shl_imm (void)
+{
+  if (!inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
+      unsigned int tmp;
+
+      /* VSHL/VQSHL 3-register variants have syntax such as:
+           vshl.xx Dd, Dm, Dn
+         whereas other 3-register operations encoded by neon_three_same have
+         syntax like:
+           vadd.xx Dd, Dn, Dm
+         (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
+         here.  */
+      tmp = inst.operands[2].reg;
+      inst.operands[2].reg = inst.operands[1].reg;
+      inst.operands[1].reg = tmp;
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+    }
+}
+
+static void
+do_neon_qshl_imm (void)
+{
+  if (!inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
+                      inst.operands[2].imm);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
+      unsigned int tmp;
+
+      /* See note in do_neon_shl_imm.  */
+      tmp = inst.operands[2].reg;
+      inst.operands[2].reg = inst.operands[1].reg;
+      inst.operands[1].reg = tmp;
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+    }
+}
+
+static void
+do_neon_rshl (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_SU_ALL | N_KEY);
+  unsigned int tmp;
+
+  tmp = inst.operands[2].reg;
+  inst.operands[2].reg = inst.operands[1].reg;
+  inst.operands[1].reg = tmp;
+  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
+}
+
+static int
+neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
+{
+  /* Handle .I8 pseudo-instructions.  */
+  if (size == 8)
+    {
+      /* Unfortunately, this will make everything apart from zero out-of-range.
+         FIXME is this the intended semantics? There doesn't seem much point in
+         accepting .I8 if so.  */
+      immediate |= immediate << 8;
+      size = 16;
+    }
+
+  if (size >= 32)
+    {
+      if (immediate == (immediate & 0x000000ff))
+	{
+	  *immbits = immediate;
+	  return 0x1;
+	}
+      else if (immediate == (immediate & 0x0000ff00))
+	{
+	  *immbits = immediate >> 8;
+	  return 0x3;
+	}
+      else if (immediate == (immediate & 0x00ff0000))
+	{
+	  *immbits = immediate >> 16;
+	  return 0x5;
+	}
+      else if (immediate == (immediate & 0xff000000))
+	{
+	  *immbits = immediate >> 24;
+	  return 0x7;
+	}
+      if ((immediate & 0xffff) != (immediate >> 16))
+	goto bad_immediate;
+      immediate &= 0xffff;
+    }
+
+  if (immediate == (immediate & 0x000000ff))
+    {
+      *immbits = immediate;
+      return 0x9;
+    }
+  else if (immediate == (immediate & 0x0000ff00))
+    {
+      *immbits = immediate >> 8;
+      return 0xb;
+    }
+
+  bad_immediate:
+  first_error (_("immediate value out of range"));
+  return FAIL;
+}
+
+/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
+   A, B, C, D.  */
+
+static int
+neon_bits_same_in_bytes (unsigned imm)
+{
+  return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
+         && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
+         && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
+         && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
+}
+
+/* For immediate of above form, return 0bABCD.  */
+
+static unsigned
+neon_squash_bits (unsigned imm)
+{
+  return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
+         | ((imm & 0x01000000) >> 21);
+}
+
+/* Compress quarter-float representation to 0b...000 abcdefgh.  */
+
+static unsigned
+neon_qfloat_bits (unsigned imm)
+{
+  return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
+}
+
+/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
+   the instruction. *OP is passed as the initial value of the op field, and
+   may be set to a different value depending on the constant (i.e.
+   "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
+   MVN).  If the immediate looks like a repeated parttern then also
+   try smaller element sizes.  */
+
+static int
+neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
+			 unsigned *immbits, int *op, int size,
+			 enum neon_el_type type)
+{
+  /* Only permit float immediates (including 0.0/-0.0) if the operand type is
+     float.  */
+  if (type == NT_float && !float_p)
+    return FAIL;
+
+  if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
+    {
+      if (size != 32 || *op == 1)
+        return FAIL;
+      *immbits = neon_qfloat_bits (immlo);
+      return 0xf;
+    }
+
+  if (size == 64)
+    {
+      if (neon_bits_same_in_bytes (immhi)
+	  && neon_bits_same_in_bytes (immlo))
+	{
+	  if (*op == 1)
+	    return FAIL;
+	  *immbits = (neon_squash_bits (immhi) << 4)
+		     | neon_squash_bits (immlo);
+	  *op = 1;
+	  return 0xe;
+	}
+
+      if (immhi != immlo)
+	return FAIL;
+    }
+
+  if (size >= 32)
+    {
+      if (immlo == (immlo & 0x000000ff))
+	{
+	  *immbits = immlo;
+	  return 0x0;
+	}
+      else if (immlo == (immlo & 0x0000ff00))
+	{
+	  *immbits = immlo >> 8;
+	  return 0x2;
+	}
+      else if (immlo == (immlo & 0x00ff0000))
+	{
+	  *immbits = immlo >> 16;
+	  return 0x4;
+	}
+      else if (immlo == (immlo & 0xff000000))
+	{
+	  *immbits = immlo >> 24;
+	  return 0x6;
+	}
+      else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
+	{
+	  *immbits = (immlo >> 8) & 0xff;
+	  return 0xc;
+	}
+      else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
+	{
+	  *immbits = (immlo >> 16) & 0xff;
+	  return 0xd;
+	}
+
+      if ((immlo & 0xffff) != (immlo >> 16))
+	return FAIL;
+      immlo &= 0xffff;
+    }
+
+  if (size >= 16)
+    {
+      if (immlo == (immlo & 0x000000ff))
+	{
+	  *immbits = immlo;
+	  return 0x8;
+	}
+      else if (immlo == (immlo & 0x0000ff00))
+	{
+	  *immbits = immlo >> 8;
+	  return 0xa;
+	}
+
+      if ((immlo & 0xff) != (immlo >> 8))
+	return FAIL;
+      immlo &= 0xff;
+    }
+
+  if (immlo == (immlo & 0x000000ff))
+    {
+      /* Don't allow MVN with 8-bit immediate.  */
+      if (*op == 1)
+	return FAIL;
+      *immbits = immlo;
+      return 0xe;
+    }
+
+  return FAIL;
+}
+
+/* Write immediate bits [7:0] to the following locations:
+
+  |28/24|23     19|18 16|15                    4|3     0|
+  |  a  |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
+
+  This function is used by VMOV/VMVN/VORR/VBIC.  */
+
+static void
+neon_write_immbits (unsigned immbits)
+{
+  inst.instruction |= immbits & 0xf;
+  inst.instruction |= ((immbits >> 4) & 0x7) << 16;
+  inst.instruction |= ((immbits >> 7) & 0x1) << 24;
+}
+
+/* Invert low-order SIZE bits of XHI:XLO.  */
+
+static void
+neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
+{
+  unsigned immlo = xlo ? *xlo : 0;
+  unsigned immhi = xhi ? *xhi : 0;
+
+  switch (size)
+    {
+    case 8:
+      immlo = (~immlo) & 0xff;
+      break;
+
+    case 16:
+      immlo = (~immlo) & 0xffff;
+      break;
+
+    case 64:
+      immhi = (~immhi) & 0xffffffff;
+      /* fall through.  */
+
+    case 32:
+      immlo = (~immlo) & 0xffffffff;
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (xlo)
+    *xlo = immlo;
+
+  if (xhi)
+    *xhi = immhi;
+}
+
+static void
+do_neon_logic (void)
+{
+  if (inst.operands[2].present && inst.operands[2].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      neon_check_type (3, rs, N_IGNORE_TYPE);
+      /* U bit and size field were set as part of the bitmask.  */
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), 0, -1);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
+      enum neon_opc opcode = inst.instruction & 0x0fffffff;
+      unsigned immbits;
+      int cmode;
+      
+      if (et.type == NT_invtype)
+        return;
+      
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+
+      immbits = inst.operands[1].imm;
+      if (et.size == 64)
+	{
+	  /* .i64 is a pseudo-op, so the immediate must be a repeating
+	     pattern.  */
+	  if (immbits != (inst.operands[1].regisimm ?
+			  inst.operands[1].reg : 0))
+	    {
+	      /* Set immbits to an invalid constant.  */
+	      immbits = 0xdeadbeef;
+	    }
+	}
+
+      switch (opcode)
+        {
+        case N_MNEM_vbic:
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vorr:
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vand:
+          /* Pseudo-instruction for VBIC.  */
+          neon_invert_size (&immbits, 0, et.size);
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        case N_MNEM_vorn:
+          /* Pseudo-instruction for VORR.  */
+          neon_invert_size (&immbits, 0, et.size);
+          cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
+          break;
+        
+        default:
+          abort ();
+        }
+
+      if (cmode == FAIL)
+        return;
+
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= cmode << 8;
+      neon_write_immbits (immbits);
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+}
+
+static void
+do_neon_bitfield (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_IGNORE_TYPE);
+  neon_three_same (neon_quad (rs), 0, -1);
+}
+
+static void
+neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
+                  unsigned destbits)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
+                                            types | N_KEY);
+  if (et.type == NT_float)
+    {
+      inst.instruction = NEON_ENC_FLOAT (inst.instruction);
+      neon_three_same (neon_quad (rs), 0, -1);
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
+    }
+}
+
+static void
+do_neon_dyadic_if_su (void)
+{
+  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
+}
+
+static void
+do_neon_dyadic_if_su_d (void)
+{
+  /* This version only allow D registers, but that constraint is enforced during
+     operand parsing so we don't need to do anything extra here.  */
+  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
+}
+
+static void
+do_neon_dyadic_if_i_d (void)
+{
+  /* The "untyped" case can't happen. Do this to stop the "U" bit being
+     affected if we specify unsigned args.  */
+  neon_dyadic_misc (NT_untyped, N_IF_32, 0);
+}
+
+enum vfp_or_neon_is_neon_bits
+{
+  NEON_CHECK_CC = 1,
+  NEON_CHECK_ARCH = 2
+};
+
+/* Call this function if an instruction which may have belonged to the VFP or
+   Neon instruction sets, but turned out to be a Neon instruction (due to the
+   operand types involved, etc.). We have to check and/or fix-up a couple of
+   things:
+
+     - Make sure the user hasn't attempted to make a Neon instruction
+       conditional.
+     - Alter the value in the condition code field if necessary.
+     - Make sure that the arch supports Neon instructions.
+
+   Which of these operations take place depends on bits from enum
+   vfp_or_neon_is_neon_bits.
+
+   WARNING: This function has side effects! If NEON_CHECK_CC is used and the
+   current instruction's condition is COND_ALWAYS, the condition field is
+   changed to inst.uncond_value. This is necessary because instructions shared
+   between VFP and Neon may be conditional for the VFP variants only, and the
+   unconditional Neon version must have, e.g., 0xF in the condition field.  */
+
+static int
+vfp_or_neon_is_neon (unsigned check)
+{
+  /* Conditions are always legal in Thumb mode (IT blocks).  */
+  if (!thumb_mode && (check & NEON_CHECK_CC))
+    {
+      if (inst.cond != COND_ALWAYS)
+        {
+          first_error (_(BAD_COND));
+          return FAIL;
+        }
+      if (inst.uncond_value != -1)
+        inst.instruction |= inst.uncond_value << 28;
+    }
+  
+  if ((check & NEON_CHECK_ARCH)
+      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+    {
+      first_error (_(BAD_FPU));
+      return FAIL;
+    }
+  
+  return SUCCESS;
+}
+
+static void
+do_neon_addsub_if_i (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  /* The "untyped" case can't happen. Do this to stop the "U" bit being
+     affected if we specify unsigned args.  */
+  neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
+}
+
+/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
+   result to be:
+     V<op> A,B     (A is operand 0, B is operand 2)
+   to mean:
+     V<op> A,B,A
+   not:
+     V<op> A,B,B
+   so handle that case specially.  */
+
+static void
+neon_exchange_operands (void)
+{
+  void *scratch = alloca (sizeof (inst.operands[0]));
+  if (inst.operands[1].present)
+    {
+      /* Swap operands[1] and operands[2].  */
+      memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
+      inst.operands[1] = inst.operands[2];
+      memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
+    }
+  else
+    {
+      inst.operands[1] = inst.operands[2];
+      inst.operands[2] = inst.operands[0];
+    }
+}
+
+static void
+neon_compare (unsigned regtypes, unsigned immtypes, int invert)
+{
+  if (inst.operands[2].isreg)
+    {
+      if (invert)
+        neon_exchange_operands ();
+      neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_EQK | N_SIZ, immtypes | N_KEY);
+
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= (et.type == NT_float) << 10;
+      inst.instruction |= neon_logbits (et.size) << 18;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+}
+
+static void
+do_neon_cmp (void)
+{
+  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
+}
+
+static void
+do_neon_cmp_inv (void)
+{
+  neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
+}
+
+static void
+do_neon_ceq (void)
+{
+  neon_compare (N_IF_32, N_IF_32, FALSE);
+}
+
+/* For multiply instructions, we have the possibility of 16-bit or 32-bit
+   scalars, which are encoded in 5 bits, M : Rm.
+   For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
+   M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
+   index in M.  */
+
+static unsigned
+neon_scalar_for_mul (unsigned scalar, unsigned elsize)
+{
+  unsigned regno = NEON_SCALAR_REG (scalar);
+  unsigned elno = NEON_SCALAR_INDEX (scalar);
+
+  switch (elsize)
+    {
+    case 16:
+      if (regno > 7 || elno > 3)
+        goto bad_scalar;
+      return regno | (elno << 3);
+    
+    case 32:
+      if (regno > 15 || elno > 1)
+        goto bad_scalar;
+      return regno | (elno << 4);
+
+    default:
+    bad_scalar:
+      first_error (_("scalar out of range for multiply instruction"));
+    }
+
+  return 0;
+}
+
+/* Encode multiply / multiply-accumulate scalar instructions.  */
+
+static void
+neon_mul_mac (struct neon_type_el et, int ubit)
+{
+  unsigned scalar;
+
+  /* Give a more helpful error message if we have an invalid type.  */
+  if (et.type == NT_invtype)
+    return;
+  
+  scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (scalar);
+  inst.instruction |= HI1 (scalar) << 5;
+  inst.instruction |= (et.type == NT_float) << 8;
+  inst.instruction |= neon_logbits (et.size) << 20;
+  inst.instruction |= (ubit != 0) << 24;
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_mac_maybe_scalar (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  if (inst.operands[2].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, neon_quad (rs));
+    }
+  else
+    {
+      /* The "untyped" case can't happen.  Do this to stop the "U" bit being
+	 affected if we specify unsigned args.  */
+      neon_dyadic_misc (NT_untyped, N_IF_32, 0);
+    }
+}
+
+static void
+do_neon_tst (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  neon_three_same (neon_quad (rs), 0, et.size);
+}
+
+/* VMUL with 3 registers allows the P8 type. The scalar version supports the
+   same types as the MAC equivalents. The polynomial type for this instruction
+   is encoded the same as the integer type.  */
+
+static void
+do_neon_mul (void)
+{
+  if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  if (inst.operands[2].isscalar)
+    do_neon_mac_maybe_scalar ();
+  else
+    neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
+}
+
+static void
+do_neon_qdmulh (void)
+{
+  if (inst.operands[2].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, neon_quad (rs));
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+      struct neon_type_el et = neon_check_type (3, rs,
+        N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      /* The U bit (rounding) comes from bit mask.  */
+      neon_three_same (neon_quad (rs), 0, et.size);
+    }
+}
+
+static void
+do_neon_fcmp_absolute (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
+  /* Size field comes from bit mask.  */
+  neon_three_same (neon_quad (rs), 1, -1);
+}
+
+static void
+do_neon_fcmp_absolute_inv (void)
+{
+  neon_exchange_operands ();
+  do_neon_fcmp_absolute ();
+}
+
+static void
+do_neon_step (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
+  neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
+  neon_three_same (neon_quad (rs), 0, -1);
+}
+
+static void
+do_neon_abs_neg (void)
+{
+  enum neon_shape rs;
+  struct neon_type_el et;
+  
+  if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
+    return;
+
+  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+    return;
+
+  rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
+  
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg);
+  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= (et.type == NT_float) << 10;
+  inst.instruction |= neon_logbits (et.size) << 18;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_sli (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 0 || (unsigned)imm >= et.size,
+              _("immediate out of range for insert"));
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+}
+
+static void
+do_neon_sri (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for insert"));
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
+}
+
+static void
+do_neon_qshlu_imm (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  constraint (imm < 0 || (unsigned)imm >= et.size,
+              _("immediate out of range for shift"));
+  /* Only encodes the 'U present' variant of the instruction.
+     In this case, signed types have OP (bit 8) set to 0.
+     Unsigned types have OP set to 1.  */
+  inst.instruction |= (et.type == NT_unsigned) << 8;
+  /* The rest of the bits are the same as other immediate shifts.  */
+  neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
+}
+
+static void
+do_neon_qmovn (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
+  /* Saturating move where operands can be signed or unsigned, and the
+     destination has the same signedness.  */
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  if (et.type == NT_unsigned)
+    inst.instruction |= 0xc0;
+  else
+    inst.instruction |= 0x80;
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_qmovun (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
+  /* Saturating move with unsigned results. Operands must be signed.  */
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_rshift_sat_narrow (void)
+{
+  /* FIXME: Types for narrowing. If operands are signed, results can be signed
+     or unsigned. If operands are unsigned, results must also be unsigned.  */
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+  
+  /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
+     VQMOVN.I<size> <Dd>, <Qm>.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vqmovn;
+      do_neon_qmovn ();
+      return;
+    }
+  
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range"));
+  neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
+}
+
+static void
+do_neon_rshift_sat_narrow_u (void)
+{
+  /* FIXME: Types for narrowing. If operands are signed, results can be signed
+     or unsigned. If operands are unsigned, results must also be unsigned.  */
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+
+  /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
+     VQMOVUN.I<size> <Dd>, <Qm>.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vqmovun;
+      do_neon_qmovun ();
+      return;
+    }
+
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range"));
+  /* FIXME: The manual is kind of unclear about what value U should have in
+     VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
+     must be 1.  */
+  neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
+}
+
+static void
+do_neon_movn (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQ,
+    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (0, 1, et.size / 2);
+}
+
+static void
+do_neon_rshift_narrow (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_DQI,
+    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
+  int imm = inst.operands[2].imm;
+  /* This gets the bounds check, size encoding and immediate bits calculation
+     right.  */
+  et.size /= 2;
+  
+  /* If immediate is zero then we are a pseudo-instruction for
+     VMOVN.I<size> <Dd>, <Qm>  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      inst.instruction = N_MNEM_vmovn;
+      do_neon_movn ();
+      return;
+    }
+  
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for narrowing operation"));
+  neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
+}
+
+static void
+do_neon_shll (void)
+{
+  /* FIXME: Type checking when lengthening.  */
+  struct neon_type_el et = neon_check_type (2, NS_QDI,
+    N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
+  unsigned imm = inst.operands[2].imm;
+
+  if (imm == et.size)
+    {
+      /* Maximum shift variant.  */
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_logbits (et.size) << 18;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+  else
+    {
+      /* A more-specific type check for non-max versions.  */
+      et = neon_check_type (2, NS_QDI,
+        N_EQK | N_DBL, N_SU_32 | N_KEY);
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
+    }
+}
+
+/* Check the various types for the VCVT instruction, and return which version
+   the current instruction is.  */
+
+static int
+neon_cvt_flavour (enum neon_shape rs)
+{
+#define CVT_VAR(C,X,Y)							\
+  et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y));	\
+  if (et.type != NT_invtype)						\
+    {									\
+      inst.error = NULL;						\
+      return (C);							\
+    }
+  struct neon_type_el et;
+  unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
+                        || rs == NS_FF) ? N_VFP : 0;
+  /* The instruction versions which take an immediate take one register
+     argument, which is extended to the width of the full register. Thus the
+     "source" and "destination" registers must have the same width.  Hack that
+     here by making the size equal to the key (wider, in this case) operand.  */
+  unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
+  
+  CVT_VAR (0, N_S32, N_F32);
+  CVT_VAR (1, N_U32, N_F32);
+  CVT_VAR (2, N_F32, N_S32);
+  CVT_VAR (3, N_F32, N_U32);
+  
+  whole_reg = N_VFP;
+  
+  /* VFP instructions.  */
+  CVT_VAR (4, N_F32, N_F64);
+  CVT_VAR (5, N_F64, N_F32);
+  CVT_VAR (6, N_S32, N_F64 | key);
+  CVT_VAR (7, N_U32, N_F64 | key);
+  CVT_VAR (8, N_F64 | key, N_S32);
+  CVT_VAR (9, N_F64 | key, N_U32);
+  /* VFP instructions with bitshift.  */
+  CVT_VAR (10, N_F32 | key, N_S16);
+  CVT_VAR (11, N_F32 | key, N_U16);
+  CVT_VAR (12, N_F64 | key, N_S16);
+  CVT_VAR (13, N_F64 | key, N_U16);
+  CVT_VAR (14, N_S16, N_F32 | key);
+  CVT_VAR (15, N_U16, N_F32 | key);
+  CVT_VAR (16, N_S16, N_F64 | key);
+  CVT_VAR (17, N_U16, N_F64 | key);
+  
+  return -1;
+#undef CVT_VAR
+}
+
+/* Neon-syntax VFP conversions.  */
+
+static void
+do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
+{
+  const char *opname = 0;
+  
+  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
+    {
+      /* Conversions with immediate bitshift.  */
+      const char *enc[] =
+        {
+          "ftosls",
+          "ftouls",
+          "fsltos",
+          "fultos",
+          NULL,
+          NULL,
+          "ftosld",
+          "ftould",
+          "fsltod",
+          "fultod",
+          "fshtos",
+          "fuhtos",
+          "fshtod",
+          "fuhtod",
+          "ftoshs",
+          "ftouhs",
+          "ftoshd",
+          "ftouhd"
+        };
+
+      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+        {
+          opname = enc[flavour];
+          constraint (inst.operands[0].reg != inst.operands[1].reg,
+                      _("operands 0 and 1 must be the same register"));
+          inst.operands[1] = inst.operands[2];
+          memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
+        }
+    }
+  else
+    {
+      /* Conversions without bitshift.  */
+      const char *enc[] =
+        {
+          "ftosis",
+          "ftouis",
+          "fsitos",
+          "fuitos",
+          "fcvtsd",
+          "fcvtds",
+          "ftosid",
+          "ftouid",
+          "fsitod",
+          "fuitod"
+        };
+
+      if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
+        opname = enc[flavour];
+    }
+
+  if (opname)
+    do_vfp_nsyn_opcode (opname);
+}
+
+static void
+do_vfp_nsyn_cvtz (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
+  int flavour = neon_cvt_flavour (rs);
+  const char *enc[] =
+    {
+      "ftosizs",
+      "ftouizs",
+      NULL,
+      NULL,
+      NULL,
+      NULL,
+      "ftosizd",
+      "ftouizd"
+    };
+
+  if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
+    do_vfp_nsyn_opcode (enc[flavour]);
+}
+
+static void
+do_neon_cvt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
+    NS_FD, NS_DF, NS_FF, NS_NULL);
+  int flavour = neon_cvt_flavour (rs);
+
+  /* VFP rather than Neon conversions.  */
+  if (flavour >= 4)
+    {
+      do_vfp_nsyn_cvt (rs, flavour);
+      return;
+    }
+
+  switch (rs)
+    {
+    case NS_DDI:
+    case NS_QQI:
+      {
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+
+        /* Fixed-point conversion with #0 immediate is encoded as an
+           integer conversion.  */
+        if (inst.operands[2].present && inst.operands[2].imm == 0)
+          goto int_encode;
+        unsigned immbits = 32 - inst.operands[2].imm;
+        unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
+        inst.instruction = NEON_ENC_IMMED (inst.instruction);
+        if (flavour != -1)
+          inst.instruction |= enctab[flavour];
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= neon_quad (rs) << 6;
+        inst.instruction |= 1 << 21;
+        inst.instruction |= immbits << 16;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+      break;
+
+    case NS_DD:
+    case NS_QQ:
+    int_encode:
+      {
+        unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
+
+        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+
+        if (flavour != -1)
+          inst.instruction |= enctab[flavour];
+
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= neon_quad (rs) << 6;
+        inst.instruction |= 2 << 18;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+    break;
+
+    default:
+      /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32).  */
+      do_vfp_nsyn_cvt (rs, flavour);
+    }
+}
+
+static void
+neon_move_immediate (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
+  unsigned immlo, immhi = 0, immbits;
+  int op, cmode, float_p;
+
+  constraint (et.type == NT_invtype,
+              _("operand size must be specified for immediate VMOV"));
+
+  /* We start out as an MVN instruction if OP = 1, MOV otherwise.  */
+  op = (inst.instruction & (1 << 5)) != 0;
+
+  immlo = inst.operands[1].imm;
+  if (inst.operands[1].regisimm)
+    immhi = inst.operands[1].reg;
+
+  constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
+              _("immediate has bits set outside the operand size"));
+
+  float_p = inst.operands[1].immisfloat;
+
+  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
+                                        et.size, et.type)) == FAIL)
+    {
+      /* Invert relevant bits only.  */
+      neon_invert_size (&immlo, &immhi, et.size);
+      /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
+         with one or the other; those cases are caught by
+         neon_cmode_for_move_imm.  */
+      op = !op;
+      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
+					    &op, et.size, et.type)) == FAIL)
+        {
+          first_error (_("immediate out of range"));
+          return;
+        }
+    }
+
+  inst.instruction &= ~(1 << 5);
+  inst.instruction |= op << 5;
+
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= cmode << 8;
+
+  neon_write_immbits (immbits);
+}
+
+static void
+do_neon_mvn (void)
+{
+  if (inst.operands[1].isreg)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+      
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[1].reg);
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+    }
+  else
+    {
+      inst.instruction = NEON_ENC_IMMED (inst.instruction);
+      neon_move_immediate ();
+    }
+
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+/* Encode instructions of form:
+
+  |28/24|23|22|21 20|19 16|15 12|11    8|7|6|5|4|3  0|
+  |  U  |x |D |size | Rn  | Rd  |x x x x|N|x|M|x| Rm |
+
+*/
+
+static void
+neon_mixed_length (struct neon_type_el et, unsigned size)
+{
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= (et.type == NT_unsigned) << 24;
+  inst.instruction |= neon_logbits (size) << 20;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_dyadic_long (void)
+{
+  /* FIXME: Type checking for lengthening op.  */
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+do_neon_abal (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
+{
+  if (inst.operands[2].isscalar)
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDS,
+        N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      neon_mul_mac (et, et.type == NT_unsigned);
+    }
+  else
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDD,
+        N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
+      inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      neon_mixed_length (et, et.size);
+    }
+}
+
+static void
+do_neon_mac_maybe_scalar_long (void)
+{
+  neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
+}
+
+static void
+do_neon_dyadic_wide (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QQD,
+    N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
+  neon_mixed_length (et, et.size);
+}
+
+static void
+do_neon_dyadic_narrow (void)
+{
+  struct neon_type_el et = neon_check_type (3, NS_QDD,
+    N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
+  /* Operand sign is unimportant, and the U bit is part of the opcode,
+     so force the operand type to integer.  */
+  et.type = NT_integer;
+  neon_mixed_length (et, et.size / 2);
+}
+
+static void
+do_neon_mul_sat_scalar_long (void)
+{
+  neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
+}
+
+static void
+do_neon_vmull (void)
+{
+  if (inst.operands[2].isscalar)
+    do_neon_mac_maybe_scalar_long ();
+  else
+    {
+      struct neon_type_el et = neon_check_type (3, NS_QDD,
+        N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
+      if (et.type == NT_poly)
+        inst.instruction = NEON_ENC_POLY (inst.instruction);
+      else
+        inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+      /* For polynomial encoding, size field must be 0b00 and the U bit must be
+         zero. Should be OK as-is.  */
+      neon_mixed_length (et, et.size);
+    }
+}
+
+static void
+do_neon_ext (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (3, rs,
+    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
+  unsigned imm = (inst.operands[3].imm * et.size) / 8;
+  constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= neon_quad (rs) << 6;
+  inst.instruction |= imm << 8;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_rev (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  unsigned op = (inst.instruction >> 7) & 3;
+  /* N (width of reversed regions) is encoded as part of the bitmask. We
+     extract it here to check the elements to be reversed are smaller.
+     Otherwise we'd get a reserved instruction.  */
+  unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
+  assert (elsize != 0);
+  constraint (et.size >= elsize,
+              _("elements must be smaller than reversal region"));
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_dup (void)
+{
+  if (inst.operands[1].isscalar)
+    {
+      enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_EQK, N_8 | N_16 | N_32 | N_KEY);
+      unsigned sizebits = et.size >> 3;
+      unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
+      int logsize = neon_logbits (et.size);
+      unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
+
+      if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
+        return;
+
+      inst.instruction = NEON_ENC_SCALAR (inst.instruction);
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (dm);
+      inst.instruction |= HI1 (dm) << 5;
+      inst.instruction |= neon_quad (rs) << 6;
+      inst.instruction |= x << 17;
+      inst.instruction |= sizebits << 16;
+      
+      inst.instruction = neon_dp_fixup (inst.instruction);
+    }
+  else
+    {
+      enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
+      struct neon_type_el et = neon_check_type (2, rs,
+        N_8 | N_16 | N_32 | N_KEY, N_EQK);
+      /* Duplicate ARM register to lanes of vector.  */
+      inst.instruction = NEON_ENC_ARMREG (inst.instruction);
+      switch (et.size)
+        {
+        case 8:  inst.instruction |= 0x400000; break;
+        case 16: inst.instruction |= 0x000020; break;
+        case 32: inst.instruction |= 0x000000; break;
+        default: break;
+        }
+      inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 7;
+      inst.instruction |= neon_quad (rs) << 21;
+      /* The encoding for this instruction is identical for the ARM and Thumb
+         variants, except for the condition field.  */
+      do_vfp_cond_or_thumb ();
+    }
+}
+
+/* VMOV has particularly many variations. It can be one of:
+     0. VMOV<c><q> <Qd>, <Qm>
+     1. VMOV<c><q> <Dd>, <Dm>
+   (Register operations, which are VORR with Rm = Rn.)
+     2. VMOV<c><q>.<dt> <Qd>, #<imm>
+     3. VMOV<c><q>.<dt> <Dd>, #<imm>
+   (Immediate loads.)
+     4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
+   (ARM register to scalar.)
+     5. VMOV<c><q> <Dm>, <Rd>, <Rn>
+   (Two ARM registers to vector.)
+     6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
+   (Scalar to ARM register.)
+     7. VMOV<c><q> <Rd>, <Rn>, <Dm>
+   (Vector to two ARM registers.)
+     8. VMOV.F32 <Sd>, <Sm>
+     9. VMOV.F64 <Dd>, <Dm>
+   (VFP register moves.)
+    10. VMOV.F32 <Sd>, #imm
+    11. VMOV.F64 <Dd>, #imm
+   (VFP float immediate load.)
+    12. VMOV <Rd>, <Sm>
+   (VFP single to ARM reg.)
+    13. VMOV <Sd>, <Rm>
+   (ARM reg to VFP single.)
+    14. VMOV <Rd>, <Re>, <Sn>, <Sm>
+   (Two ARM regs to two VFP singles.)
+    15. VMOV <Sd>, <Se>, <Rn>, <Rm>
+   (Two VFP singles to two ARM regs.)
+  
+   These cases can be disambiguated using neon_select_shape, except cases 1/9
+   and 3/11 which depend on the operand type too.
+   
+   All the encoded bits are hardcoded by this function.
+   
+   Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
+   Cases 5, 7 may be used with VFPv2 and above.
+   
+   FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
+   can specify a type where it doesn't make sense to, and is ignored).
+*/
+
+static void
+do_neon_mov (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
+    NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
+    NS_NULL);
+  struct neon_type_el et;
+  const char *ldconst = 0;
+
+  switch (rs)
+    {
+    case NS_DD:  /* case 1/9.  */
+      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
+      /* It is not an error here if no type is given.  */
+      inst.error = NULL;
+      if (et.type == NT_float && et.size == 64)
+        {
+          do_vfp_nsyn_opcode ("fcpyd");
+          break;
+        }
+      /* fall through.  */
+
+    case NS_QQ:  /* case 0/1.  */
+      {
+        if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+          return;
+        /* The architecture manual I have doesn't explicitly state which
+           value the U bit should have for register->register moves, but
+           the equivalent VORR instruction has U = 0, so do that.  */
+        inst.instruction = 0x0200110;
+        inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+        inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+        inst.instruction |= LOW4 (inst.operands[1].reg);
+        inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+        inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+        inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+        inst.instruction |= neon_quad (rs) << 6;
+
+        inst.instruction = neon_dp_fixup (inst.instruction);
+      }
+      break;
+        
+    case NS_DI:  /* case 3/11.  */
+      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
+      inst.error = NULL;
+      if (et.type == NT_float && et.size == 64)
+        {
+          /* case 11 (fconstd).  */
+          ldconst = "fconstd";
+          goto encode_fconstd;
+        }
+      /* fall through.  */
+
+    case NS_QI:  /* case 2/3.  */
+      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+        return;
+      inst.instruction = 0x0800010;
+      neon_move_immediate ();
+      inst.instruction = neon_dp_fixup (inst.instruction);
+      break;
+    
+    case NS_SR:  /* case 4.  */
+      {
+        unsigned bcdebits = 0;
+        struct neon_type_el et = neon_check_type (2, NS_NULL,
+          N_8 | N_16 | N_32 | N_KEY, N_EQK);
+        int logsize = neon_logbits (et.size);
+        unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
+        unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
+
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                    _(BAD_FPU));
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                    && et.size != 32, _(BAD_FPU));
+        constraint (et.type == NT_invtype, _("bad type for scalar"));
+        constraint (x >= 64 / et.size, _("scalar index out of range"));
+
+        switch (et.size)
+          {
+          case 8:  bcdebits = 0x8; break;
+          case 16: bcdebits = 0x1; break;
+          case 32: bcdebits = 0x0; break;
+          default: ;
+          }
+
+        bcdebits |= x << logsize;
+
+        inst.instruction = 0xe000b10;
+        do_vfp_cond_or_thumb ();
+        inst.instruction |= LOW4 (dn) << 16;
+        inst.instruction |= HI1 (dn) << 7;
+        inst.instruction |= inst.operands[1].reg << 12;
+        inst.instruction |= (bcdebits & 3) << 5;
+        inst.instruction |= (bcdebits >> 2) << 21;
+      }
+      break;
+    
+    case NS_DRR:  /* case 5 (fmdrr).  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+                  _(BAD_FPU));
+
+      inst.instruction = 0xc400b10;
+      do_vfp_cond_or_thumb ();
+      inst.instruction |= LOW4 (inst.operands[0].reg);
+      inst.instruction |= HI1 (inst.operands[0].reg) << 5;
+      inst.instruction |= inst.operands[1].reg << 12;
+      inst.instruction |= inst.operands[2].reg << 16;
+      break;
+    
+    case NS_RS:  /* case 6.  */
+      {
+        struct neon_type_el et = neon_check_type (2, NS_NULL,
+          N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
+        unsigned logsize = neon_logbits (et.size);
+        unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
+        unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
+        unsigned abcdebits = 0;
+
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
+                    _(BAD_FPU));
+        constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
+                    && et.size != 32, _(BAD_FPU));
+        constraint (et.type == NT_invtype, _("bad type for scalar"));
+        constraint (x >= 64 / et.size, _("scalar index out of range"));
+
+        switch (et.size)
+          {
+          case 8:  abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
+          case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
+          case 32: abcdebits = 0x00; break;
+          default: ;
+          }
+
+        abcdebits |= x << logsize;
+        inst.instruction = 0xe100b10;
+        do_vfp_cond_or_thumb ();
+        inst.instruction |= LOW4 (dn) << 16;
+        inst.instruction |= HI1 (dn) << 7;
+        inst.instruction |= inst.operands[0].reg << 12;
+        inst.instruction |= (abcdebits & 3) << 5;
+        inst.instruction |= (abcdebits >> 2) << 21;
+      }
+      break;
+    
+    case NS_RRD:  /* case 7 (fmrrd).  */
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
+                  _(BAD_FPU));
+
+      inst.instruction = 0xc500b10;
+      do_vfp_cond_or_thumb ();
+      inst.instruction |= inst.operands[0].reg << 12;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= LOW4 (inst.operands[2].reg);
+      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+      break;
+    
+    case NS_FF:  /* case 8 (fcpys).  */
+      do_vfp_nsyn_opcode ("fcpys");
+      break;
+    
+    case NS_FI:  /* case 10 (fconsts).  */
+      ldconst = "fconsts";
+      encode_fconstd:
+      if (is_quarter_float (inst.operands[1].imm))
+        {
+          inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
+          do_vfp_nsyn_opcode (ldconst);
+        }
+      else
+        first_error (_("immediate out of range"));
+      break;
+    
+    case NS_RF:  /* case 12 (fmrs).  */
+      do_vfp_nsyn_opcode ("fmrs");
+      break;
+    
+    case NS_FR:  /* case 13 (fmsr).  */
+      do_vfp_nsyn_opcode ("fmsr");
+      break;
+    
+    /* The encoders for the fmrrs and fmsrr instructions expect three operands
+       (one of which is a list), but we have parsed four.  Do some fiddling to
+       make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
+       expect.  */
+    case NS_RRFF:  /* case 14 (fmrrs).  */
+      constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
+                  _("VFP registers must be adjacent"));
+      inst.operands[2].imm = 2;
+      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
+      do_vfp_nsyn_opcode ("fmrrs");
+      break;
+    
+    case NS_FFRR:  /* case 15 (fmsrr).  */
+      constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
+                  _("VFP registers must be adjacent"));
+      inst.operands[1] = inst.operands[2];
+      inst.operands[2] = inst.operands[3];
+      inst.operands[0].imm = 2;
+      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
+      do_vfp_nsyn_opcode ("fmsrr");
+      break;
+    
+    default:
+      abort ();
+    }
+}
+
+static void
+do_neon_rshift_round_imm (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
+  int imm = inst.operands[2].imm;
+
+  /* imm == 0 case is encoded as VMOV for V{R}SHR.  */
+  if (imm == 0)
+    {
+      inst.operands[2].present = 0;
+      do_neon_mov ();
+      return;
+    }
+
+  constraint (imm < 1 || (unsigned)imm > et.size,
+              _("immediate out of range for shift"));
+  neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
+                  et.size - imm);
+}
+
+static void
+do_neon_movl (void)
+{
+  struct neon_type_el et = neon_check_type (2, NS_QD,
+    N_EQK | N_DBL, N_SU_32 | N_KEY);
+  unsigned sizebits = et.size >> 3;
+  inst.instruction |= sizebits << 19;
+  neon_two_same (0, et.type == NT_unsigned, -1);
+}
+
+static void
+do_neon_trn (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  inst.instruction = NEON_ENC_INTEGER (inst.instruction);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_zip_uzp (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_8 | N_16 | N_32 | N_KEY);
+  if (rs == NS_DD && et.size == 32)
+    {
+      /* Special case: encode as VTRN.32 <Dd>, <Dm>.  */
+      inst.instruction = N_MNEM_vtrn;
+      do_neon_trn ();
+      return;
+    }
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_sat_abs_neg (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_pair_long (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
+  /* Unsigned is encoded in OP field (bit 7) for these instruction.  */
+  inst.instruction |= (et.type == NT_unsigned) << 7;
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_recip_est (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
+  inst.instruction |= (et.type == NT_float) << 8;
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_cls (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_clz (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_cnt (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  struct neon_type_el et = neon_check_type (2, rs,
+    N_EQK | N_INT, N_8 | N_KEY);
+  neon_two_same (neon_quad (rs), 1, et.size);
+}
+
+static void
+do_neon_swp (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
+  neon_two_same (neon_quad (rs), 1, -1);
+}
+
+static void
+do_neon_tbl_tbx (void)
+{
+  unsigned listlenbits;
+  neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
+  
+  if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
+    {
+      first_error (_("bad list length for table lookup"));
+      return;
+    }
+  
+  listlenbits = inst.operands[1].imm - 1;
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+  inst.instruction |= LOW4 (inst.operands[2].reg);
+  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
+  inst.instruction |= listlenbits << 8;
+  
+  inst.instruction = neon_dp_fixup (inst.instruction);
+}
+
+static void
+do_neon_ldm_stm (void)
+{
+  /* P, U and L bits are part of bitmask.  */
+  int is_dbmode = (inst.instruction & (1 << 24)) != 0;
+  unsigned offsetbits = inst.operands[1].imm * 2;
+
+  if (inst.operands[1].issingle)
+    {
+      do_vfp_nsyn_ldm_stm (is_dbmode);
+      return;
+    }
+
+  constraint (is_dbmode && !inst.operands[0].writeback,
+              _("writeback (!) must be used for VLDMDB and VSTMDB"));
+
+  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
+              _("register list must contain at least 1 and at most 16 "
+                "registers"));
+
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[0].writeback << 21;
+  inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[1].reg) << 22;
+
+  inst.instruction |= offsetbits;
+  
+  do_vfp_cond_or_thumb ();
+}
+
+static void
+do_neon_ldr_str (void)
+{
+  int is_ldr = (inst.instruction & (1 << 20)) != 0;
+  
+  if (inst.operands[0].issingle)
+    {
+      if (is_ldr)
+        do_vfp_nsyn_opcode ("flds");
+      else
+        do_vfp_nsyn_opcode ("fsts");
+    }
+  else
+    {
+      if (is_ldr)
+        do_vfp_nsyn_opcode ("fldd");
+      else
+        do_vfp_nsyn_opcode ("fstd");
+    }
+}
+
+/* "interleave" version also handles non-interleaving register VLD1/VST1
+   instructions.  */
+
+static void
+do_neon_ld_st_interleave (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL,
+                                            N_8 | N_16 | N_32 | N_64);
+  unsigned alignbits = 0;
+  unsigned idx;
+  /* The bits in this table go:
+     0: register stride of one (0) or two (1)
+     1,2: register list length, minus one (1, 2, 3, 4).
+     3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
+     We use -1 for invalid entries.  */
+  const int typetable[] =
+    {
+      0x7,  -1, 0xa,  -1, 0x6,  -1, 0x2,  -1, /* VLD1 / VST1.  */
+       -1,  -1, 0x8, 0x9,  -1,  -1, 0x3,  -1, /* VLD2 / VST2.  */
+       -1,  -1,  -1,  -1, 0x4, 0x5,  -1,  -1, /* VLD3 / VST3.  */
+       -1,  -1,  -1,  -1,  -1,  -1, 0x0, 0x1  /* VLD4 / VST4.  */
+    };
+  int typebits;
+
+  if (et.type == NT_invtype)
+    return;
+
+  if (inst.operands[1].immisalign)
+    switch (inst.operands[1].imm >> 8)
+      {
+      case 64: alignbits = 1; break;
+      case 128:
+        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
+          goto bad_alignment;
+        alignbits = 2;
+        break;
+      case 256:
+        if (NEON_REGLIST_LENGTH (inst.operands[0].imm) == 3)
+          goto bad_alignment;
+        alignbits = 3;
+        break;
+      default:
+      bad_alignment:
+        first_error (_("bad alignment"));
+        return;
+      }
+
+  inst.instruction |= alignbits << 4;
+  inst.instruction |= neon_logbits (et.size) << 6;
+
+  /* Bits [4:6] of the immediate in a list specifier encode register stride
+     (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
+     VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
+     up the right value for "type" in a table based on this value and the given
+     list style, then stick it back.  */
+  idx = ((inst.operands[0].imm >> 4) & 7)
+        | (((inst.instruction >> 8) & 3) << 3);
+
+  typebits = typetable[idx];
+  
+  constraint (typebits == -1, _("bad list type for instruction"));
+
+  inst.instruction &= ~0xf00;
+  inst.instruction |= typebits << 8;
+}
+
+/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
+   *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
+   otherwise. The variable arguments are a list of pairs of legal (size, align)
+   values, terminated with -1.  */
+
+static int
+neon_alignment_bit (int size, int align, int *do_align, ...)
+{
+  va_list ap;
+  int result = FAIL, thissize, thisalign;
+    
+  if (!inst.operands[1].immisalign)
+    {
+      *do_align = 0;
+      return SUCCESS;
+    }
+      
+  va_start (ap, do_align);
+
+  do
+    {
+      thissize = va_arg (ap, int);
+      if (thissize == -1)
+        break;
+      thisalign = va_arg (ap, int);
+
+      if (size == thissize && align == thisalign)
+        result = SUCCESS;
+    }
+  while (result != SUCCESS);
+
+  va_end (ap);
+
+  if (result == SUCCESS)
+    *do_align = 1;
+  else
+    first_error (_("unsupported alignment for instruction"));
+    
+  return result;
+}
+
+static void
+do_neon_ld_st_lane (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
+  int align_good, do_align = 0;
+  int logsize = neon_logbits (et.size);
+  int align = inst.operands[1].imm >> 8;
+  int n = (inst.instruction >> 8) & 3;
+  int max_el = 64 / et.size;
+  
+  if (et.type == NT_invtype)
+    return;
+  
+  constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
+              _("bad list length"));
+  constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
+              _("scalar index out of range"));
+  constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
+              && et.size == 8,
+              _("stride of 2 unavailable when element size is 8"));
+  
+  switch (n)
+    {
+    case 0:  /* VLD1 / VST1.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
+                                       32, 32, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        {
+          unsigned alignbits = 0;
+          switch (et.size)
+            {
+            case 16: alignbits = 0x1; break;
+            case 32: alignbits = 0x3; break;
+            default: ;
+            }
+          inst.instruction |= alignbits << 4;
+        }
+      break;
+
+    case 1:  /* VLD2 / VST2.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
+                                       32, 64, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        inst.instruction |= 1 << 4;
+      break;
+
+    case 2:  /* VLD3 / VST3.  */
+      constraint (inst.operands[1].immisalign,
+                  _("can't use alignment with this instruction"));
+      break;
+
+    case 3:  /* VLD4 / VST4.  */
+      align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+                                       16, 64, 32, 64, 32, 128, -1);
+      if (align_good == FAIL)
+        return;
+      if (do_align)
+        {
+          unsigned alignbits = 0;
+          switch (et.size)
+            {
+            case 8:  alignbits = 0x1; break;
+            case 16: alignbits = 0x1; break;
+            case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
+            default: ;
+            }
+          inst.instruction |= alignbits << 4;
+        }
+      break;
+
+    default: ;
+    }
+
+  /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32.  */
+  if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+    inst.instruction |= 1 << (4 + logsize);
+      
+  inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
+  inst.instruction |= logsize << 10;
+}
+
+/* Encode single n-element structure to all lanes VLD<n> instructions.  */
+
+static void
+do_neon_ld_dup (void)
+{
+  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
+  int align_good, do_align = 0;
+
+  if (et.type == NT_invtype)
+    return;
+
+  switch ((inst.instruction >> 8) & 3)
+    {
+    case 0:  /* VLD1.  */
+      assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
+      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
+                                       &do_align, 16, 16, 32, 32, -1);
+      if (align_good == FAIL)
+        return;
+      switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
+        {
+        case 1: break;
+        case 2: inst.instruction |= 1 << 5; break;
+        default: first_error (_("bad list length")); return;
+        }
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 1:  /* VLD2.  */
+      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
+                                       &do_align, 8, 16, 16, 32, 32, 64, -1);
+      if (align_good == FAIL)
+        return;
+      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
+                  _("bad list length"));
+      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+        inst.instruction |= 1 << 5;
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 2:  /* VLD3.  */
+      constraint (inst.operands[1].immisalign,
+                  _("can't use alignment with this instruction"));
+      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
+                  _("bad list length"));
+      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+        inst.instruction |= 1 << 5;
+      inst.instruction |= neon_logbits (et.size) << 6;
+      break;
+
+    case 3:  /* VLD4.  */
+      {
+        int align = inst.operands[1].imm >> 8;
+        align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
+                                         16, 64, 32, 64, 32, 128, -1);
+        if (align_good == FAIL)
+          return;
+        constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
+                    _("bad list length"));
+        if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
+          inst.instruction |= 1 << 5;
+        if (et.size == 32 && align == 128)
+          inst.instruction |= 0x3 << 6;
+        else
+          inst.instruction |= neon_logbits (et.size) << 6;
+      }
+      break;
+
+    default: ;
+    }
+
+  inst.instruction |= do_align << 4;
+}
+
+/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
+   apart from bits [11:4].  */
+
+static void
+do_neon_ldx_stx (void)
+{
+  switch (NEON_LANE (inst.operands[0].imm))
+    {
+    case NEON_INTERLEAVE_LANES:
+      inst.instruction = NEON_ENC_INTERLV (inst.instruction);
+      do_neon_ld_st_interleave ();
+      break;
+    
+    case NEON_ALL_LANES:
+      inst.instruction = NEON_ENC_DUP (inst.instruction);
+      do_neon_ld_dup ();
+      break;
+    
+    default:
+      inst.instruction = NEON_ENC_LANE (inst.instruction);
+      do_neon_ld_st_lane ();
+    }
+
+  /* L bit comes from bit mask.  */
+  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+  inst.instruction |= inst.operands[1].reg << 16;
+  
+  if (inst.operands[1].postind)
+    {
+      int postreg = inst.operands[1].imm & 0xf;
+      constraint (!inst.operands[1].immisreg,
+                  _("post-index must be a register"));
+      constraint (postreg == 0xd || postreg == 0xf,
+                  _("bad register for post-index"));
+      inst.instruction |= postreg;
+    }
+  else if (inst.operands[1].writeback)
+    {
+      inst.instruction |= 0xd;
+    }
+  else
+    inst.instruction |= 0xf; 
+  
+  if (thumb_mode)
+    inst.instruction |= 0xf9000000;
+  else
+    inst.instruction |= 0xf4000000;
+}
+
 
 /* Overall per-instruction processing.	*/
 
@@ -8045,11 +13785,9 @@ output_relax_insn (void)
   symbolS *sym;
   int offset;
 
-#ifdef OBJ_ELF
   /* The size of the instruction is unknown, so tie the debug info to the
      start of the instruction.  */
   dwarf2_emit_insn (0);
-#endif
 
   switch (inst.reloc.exp.X_op)
     {
@@ -8117,9 +13855,7 @@ output_inst (const char * str)
 		 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
 		 inst.reloc.type);
 
-#ifdef OBJ_ELF
   dwarf2_emit_insn (inst.size);
-#endif
 }
 
 /* Tag values used in struct asm_opcode's tag field.  */
@@ -8130,9 +13866,14 @@ enum opcode_tag
   OT_unconditionalF,	/* Instruction cannot be conditionalized
 			   and carries 0xF in its ARM condition field.  */
   OT_csuffix,		/* Instruction takes a conditional suffix.  */
+  OT_csuffixF,		/* Some forms of the instruction take a conditional
+                           suffix, others place 0xF where the condition field
+                           would be.  */
   OT_cinfix3,		/* Instruction takes a conditional infix,
 			   beginning at character index 3.  (In
 			   unified mode, it becomes a suffix.)  */
+  OT_cinfix3_deprecated, /* The same as OT_cinfix3.  This is used for
+			    tsts, cmps, cmns, and teqs. */
   OT_cinfix3_legacy,	/* Legacy instruction takes a conditional infix at
 			   character index 3, even in unified mode.  Used for
 			   legacy instructions where suffix and infix forms
@@ -8211,27 +13952,46 @@ opcode_lookup (char **str)
   const struct asm_opcode *opcode;
   const struct asm_cond *cond;
   char save[2];
+  bfd_boolean neon_supported;
+  
+  neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
 
   /* Scan up to the end of the mnemonic, which must end in white space,
-     '.' (in unified mode only), or end of string.  */
+     '.' (in unified mode, or for Neon instructions), or end of string.  */
   for (base = end = *str; *end != '\0'; end++)
-    if (*end == ' ' || (unified_syntax && *end == '.'))
+    if (*end == ' ' || ((unified_syntax || neon_supported) && *end == '.'))
       break;
 
   if (end == base)
     return 0;
 
-  /* Handle a possible width suffix.  */
+  /* Handle a possible width suffix and/or Neon type suffix.  */
   if (end[0] == '.')
     {
-      if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
+      int offset = 2;
+      
+      /* The .w and .n suffixes are only valid if the unified syntax is in
+         use.  */
+      if (unified_syntax && end[1] == 'w')
 	inst.size_req = 4;
-      else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
+      else if (unified_syntax && end[1] == 'n')
 	inst.size_req = 2;
       else
-	return 0;
+        offset = 0;
+
+      inst.vectype.elems = 0;
 
-      *str = end + 2;
+      *str = end + offset;
+
+      if (end[offset] == '.')      
+	{
+	  /* See if we have a Neon type suffix (possible in either unified or
+             non-unified ARM syntax mode).  */
+          if (parse_neon_type (&inst.vectype, str) == FAIL)
+	    return 0;
+        }
+      else if (end[offset] != '\0' && end[offset] != ' ')
+        return 0;
     }
   else
     *str = end;
@@ -8276,12 +14036,14 @@ opcode_lookup (char **str)
 	  break;
 
 	case OT_cinfix3:
+	case OT_cinfix3_deprecated:
 	case OT_odd_infix_unc:
 	  if (!unified_syntax)
 	    return 0;
 	  /* else fall through */
 
 	case OT_csuffix:
+        case OT_csuffixF:
 	case OT_csuf_or_in3:
 	  inst.cond = cond->value;
 	  return opcode;
@@ -8322,11 +14084,16 @@ opcode_lookup (char **str)
   memmove (affix + 2, affix, (end - affix) - 2);
   memcpy (affix, save, 2);
 
-  if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
-		 || opcode->tag == OT_cinfix3_legacy))
+  if (opcode
+      && (opcode->tag == OT_cinfix3
+	  || opcode->tag == OT_cinfix3_deprecated
+	  || opcode->tag == OT_csuf_or_in3
+	  || opcode->tag == OT_cinfix3_legacy))
     {
       /* step CM */
-      if (unified_syntax && opcode->tag == OT_cinfix3)
+      if (unified_syntax
+	  && (opcode->tag == OT_cinfix3
+	      || opcode->tag == OT_cinfix3_deprecated))
 	as_warn (_("conditional infixes are deprecated in unified syntax"));
 
       inst.cond = cond->value;
@@ -8357,13 +14124,21 @@ md_assemble (char *str)
   if (!opcode)
     {
       /* It wasn't an instruction, but it might be a register alias of
-	 the form alias .req reg.  */
-      if (!create_register_alias (str, p))
+	 the form alias .req reg, or a Neon .dn/.qn directive.  */
+      if (!create_register_alias (str, p)
+          && !create_neon_reg_alias (str, p))
 	as_bad (_("bad instruction `%s'"), str);
 
       return;
     }
 
+  if (opcode->tag == OT_cinfix3_deprecated)
+    as_warn (_("s suffix on comparison instruction is deprecated"));
+
+  /* The value which unconditional instructions should have in place of the
+     condition field.  */
+  inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
+
   if (thumb_mode)
     {
       arm_feature_set variant;
@@ -8387,6 +14162,14 @@ md_assemble (char *str)
 	  return;
 	}
 
+      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) && !inst.size_req)
+	{
+	  /* Implicit require narrow instructions on Thumb-1.  This avoids
+	     relaxation accidentally introducing Thumb-2 instructions.  */
+	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
+	    inst.size_req = 2;
+	}
+
       /* Check conditional suffixes.  */
       if (current_it_mask)
 	{
@@ -8428,10 +14211,15 @@ md_assemble (char *str)
 	      return;
 	    }
 	}
+
+      /* Something has gone badly wrong if we try to relax a fixed size
+         instruction.  */
+      assert (inst.size_req == 0 || !inst.relax);
+
       ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 			      *opcode->tvariant);
       /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
-	 set those bits when Thumb-2 32-bit instuctions are seen.  ie.
+	 set those bits when Thumb-2 32-bit instructions are seen.  ie.
 	 anything other than bl/blx.
 	 This is overly pessimistic for relaxable instructions.  */
       if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
@@ -8439,7 +14227,7 @@ md_assemble (char *str)
 	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 				arm_ext_v6t2);
     }
-  else
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
     {
       /* Check that this instruction is supported for this CPU.  */
       if (!opcode->avariant ||
@@ -8472,6 +14260,12 @@ md_assemble (char *str)
 	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
 				*opcode->avariant);
     }
+  else
+    {
+      as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
+		"-- `%s'"), str);
+      return;
+    }
   output_inst (str);
 }
 
@@ -8537,9 +14331,7 @@ arm_frob_label (symbolS * sym)
       label_is_thumb_function_name = FALSE;
     }
 
-#ifdef OBJ_ELF
   dwarf2_emit_label (sym);
-#endif
 }
 
 int
@@ -8573,13 +14365,24 @@ arm_canonicalize_symbol_name (char * name)
    should appear in both upper and lowercase variants.	Some registers
    also have mixed-case names.	*/
 
-#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
+#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
 #define REGSET(p,t) \
   REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
   REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
   REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
   REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
+#define REGSETH(p,t) \
+  REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
+  REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
+  REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
+  REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
+#define REGSET2(p,t) \
+  REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
+  REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
+  REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
+  REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
 
 static const struct reg_entry reg_names[] =
 {
@@ -8618,24 +14421,24 @@ static const struct reg_entry reg_names[] =
   REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
 
   /* VFP SP registers.	*/
-  REGSET(s,VFS),
-  REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
-  REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
-  REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
-  REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
-
-  REGSET(S,VFS),
-  REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
-  REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
-  REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
-  REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
+  REGSET(s,VFS),  REGSET(S,VFS),
+  REGSETH(s,VFS), REGSETH(S,VFS),
 
   /* VFP DP Registers.	*/
-  REGSET(d,VFD), REGSET(D,VFS),
+  REGSET(d,VFD),  REGSET(D,VFD),
+  /* Extra Neon DP registers.  */
+  REGSETH(d,VFD), REGSETH(D,VFD),
+
+  /* Neon QP registers.  */
+  REGSET2(q,NQ),  REGSET2(Q,NQ),
 
   /* VFP control registers.  */
   REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
   REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
+  REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
+  REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
+  REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
+  REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
 
   /* Maverick DSP coprocessor registers.  */
   REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
@@ -8752,20 +14555,21 @@ static const struct asm_psr psrs[] =
 /* Table of V7M psr names.  */
 static const struct asm_psr v7m_psrs[] =
 {
-  {"apsr",	0 },
-  {"iapsr",	1 },
-  {"eapsr",	2 },
-  {"psr",	3 },
-  {"ipsr",	5 },
-  {"epsr",	6 },
-  {"iepsr",	7 },
-  {"msp",	8 },
-  {"psp",	9 },
-  {"primask",	16},
-  {"basepri",	17},
-  {"basepri_max", 18},
-  {"faultmask",	19},
-  {"control",	20}
+  {"apsr",	  0 }, {"APSR",		0 },
+  {"iapsr",	  1 }, {"IAPSR",	1 },
+  {"eapsr",	  2 }, {"EAPSR",	2 },
+  {"psr",	  3 }, {"PSR",		3 },
+  {"xpsr",	  3 }, {"XPSR",		3 }, {"xPSR",	  3 },
+  {"ipsr",	  5 }, {"IPSR",		5 },
+  {"epsr",	  6 }, {"EPSR",		6 },
+  {"iepsr",	  7 }, {"IEPSR",	7 },
+  {"msp",	  8 }, {"MSP",		8 },
+  {"psp",	  9 }, {"PSP",		9 },
+  {"primask",	  16}, {"PRIMASK",	16},
+  {"basepri",	  17}, {"BASEPRI",	17},
+  {"basepri_max", 18}, {"BASEPRI_MAX",	18},
+  {"faultmask",	  19}, {"FAULTMASK",	19},
+  {"control",	  20}, {"CONTROL",	20}
 };
 
 /* Table of all shift-in-operand names.	 */
@@ -8858,10 +14662,17 @@ static struct asm_barrier_opt barrier_opt_names[] =
 #define TxC3(mnem, op, top, nops, ops, ae, te) \
   { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
     THUMB_VARIANT, do_##ae, do_##te }
+#define TxC3w(mnem, op, top, nops, ops, ae, te) \
+  { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
 #define TC3(mnem, aop, top, nops, ops, ae, te) \
        TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
+#define TC3w(mnem, aop, top, nops, ops, ae, te) \
+       TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
 #define tC3(mnem, aop, top, nops, ops, ae, te) \
        TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
+#define tC3w(mnem, aop, top, nops, ops, ae, te) \
+       TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
 
 /* Mnemonic with a conditional infix in an unusual place.  Each and every variant has to
    appear in the condition table.  */
@@ -8970,6 +14781,42 @@ static struct asm_barrier_opt barrier_opt_names[] =
 #define UF(mnem, op, nops, ops, ae)	\
   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
 
+/* Neon data-processing. ARM versions are unconditional with cond=0xf.
+   The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
+   use the same encoding function for each.  */
+#define NUF(mnem, op, nops, ops, enc)					\
+  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+/* Neon data processing, version which indirects through neon_enc_tab for
+   the various overloaded versions of opcodes.  */
+#define nUF(mnem, op, nops, ops, enc)					\
+  { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op,	\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+/* Neon insn with conditional suffix for the ARM version, non-overloaded
+   version.  */
+#define NCE_tag(mnem, op, nops, ops, enc, tag)				\
+  { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,		\
+    THUMB_VARIANT, do_##enc, do_##enc }
+
+#define NCE(mnem, op, nops, ops, enc)					\
+  NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
+
+#define NCEF(mnem, op, nops, ops, enc)					\
+  NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
+
+/* Neon insn with conditional suffix for the ARM version, overloaded types.  */
+#define nCE_tag(mnem, op, nops, ops, enc, tag)				\
+  { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op,		\
+    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
+
+#define nCE(mnem, op, nops, ops, enc)					\
+  nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
+
+#define nCEF(mnem, op, nops, ops, enc)					\
+  nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
+
 #define do_0 0
 
 /* Thumb-only, unconditional.  */
@@ -8985,8 +14832,8 @@ static const struct asm_opcode insns[] =
  tC3(eors,	0300000, eors,	   3, (RR, oRR, SH), arit, t_arit3c),
  tCE(sub,	0400000, sub,	   3, (RR, oRR, SH), arit, t_add_sub),
  tC3(subs,	0500000, subs,	   3, (RR, oRR, SH), arit, t_add_sub),
- tCE(add,	0800000, add,	   3, (RR, oRR, SH), arit, t_add_sub),
- tC3(adds,	0900000, adds,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tCE(add,	0800000, add,	   3, (RR, oRR, SHG), arit, t_add_sub),
+ tC3(adds,	0900000, adds,	   3, (RR, oRR, SHG), arit, t_add_sub),
  tCE(adc,	0a00000, adc,	   3, (RR, oRR, SH), arit, t_arit3c),
  tC3(adcs,	0b00000, adcs,	   3, (RR, oRR, SH), arit, t_arit3c),
  tCE(sbc,	0c00000, sbc,	   3, (RR, oRR, SH), arit, t_arit3),
@@ -9000,13 +14847,13 @@ static const struct asm_opcode insns[] =
     for setting PSR flag bits.  They are obsolete in V6 and do not
     have Thumb equivalents. */
  tCE(tst,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
- tC3(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3w(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
   CL(tstp,	110f000,     	   2, (RR, SH),      cmp),
  tCE(cmp,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
- tC3(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
+ tC3w(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
   CL(cmpp,	150f000,     	   2, (RR, SH),      cmp),
  tCE(cmn,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
- tC3(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3w(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
   CL(cmnp,	170f000,     	   2, (RR, SH),      cmp),
 
  tCE(mov,	1a00000, mov,	   2, (RR, SH),      mov,  t_mov_cmp),
@@ -9014,10 +14861,10 @@ static const struct asm_opcode insns[] =
  tCE(mvn,	1e00000, mvn,	   2, (RR, SH),      mov,  t_mvn_tst),
  tC3(mvns,	1f00000, mvns,	   2, (RR, SH),      mov,  t_mvn_tst),
 
- tCE(ldr,	4100000, ldr,	   2, (RR, ADDR),    ldst, t_ldst),
- tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDR),    ldst, t_ldst),
- tCE(str,	4000000, str,	   2, (RR, ADDR),    ldst, t_ldst),
- tC3(strb,	4400000, strb,	   2, (RR, ADDR),    ldst, t_ldst),
+ tCE(ldr,	4100000, ldr,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tCE(str,	4000000, str,	   2, (RR, ADDRGLDR),ldst, t_ldst),
+ tC3(strb,	4400000, strb,	   2, (RR, ADDRGLDR),ldst, t_ldst),
 
  tCE(stm,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
  tC3(stmia,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
@@ -9050,6 +14897,10 @@ static const struct asm_opcode insns[] =
  tCE(push,	92d0000, push,     1, (REGLST),	     push_pop, t_push_pop),
  tCE(pop,	8bd0000, pop,	   1, (REGLST),	     push_pop, t_push_pop),
 
+ /* These may simplify to neg.  */
+ TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6
  TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
@@ -9057,10 +14908,8 @@ static const struct asm_opcode insns[] =
  /* V1 instructions with no Thumb analogue prior to V6T2.  */
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
- TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
- TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
  TCE(teq,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
- TC3(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
+ TC3w(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
   CL(teqp,	130f000,           2, (RR, SH),      cmp),
 
  TC3(ldrt,	4300000, f8500e00, 2, (RR, ADDR),    ldstt, t_ldstt),
@@ -9101,10 +14950,10 @@ static const struct asm_opcode insns[] =
 
   /* Generic coprocessor instructions.	*/
  TCE(cdp,	e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
- TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
- TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
+ TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
  TCE(mcr,	e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
  TCE(mrc,	e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
 
@@ -9115,8 +14964,8 @@ static const struct asm_opcode insns[] =
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v3	/* ARM 6 Status register instructions.	*/
- TCE(mrs,	10f0000, f3ef8000, 2, (RR, PSR),     mrs, t_mrs),
- TCE(msr,	120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
+ TCE(mrs,	10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
+ TCE(msr,	120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v3m	 /* ARM 7M long multiplies.  */
@@ -9133,12 +14982,12 @@ static const struct asm_opcode insns[] =
 #define ARM_VARIANT &arm_ext_v4	/* ARM Architecture 4.	*/
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v4t
- tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDR), ldstv4, t_ldst),
- tC3(strh,	00000b0, strh,     2, (RR, ADDR), ldstv4, t_ldst),
- tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
- tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
- tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
- tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
+ tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(strh,	00000b0, strh,     2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
+ tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDRGLDRS), ldstv4, t_ldst),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v4t_5
@@ -9159,10 +15008,10 @@ static const struct asm_opcode insns[] =
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(clz,	16f0f10, fab0f080, 2, (RRnpc, RRnpc),		        rd_rm,  t_clz),
- TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
- TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
+ TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
+ TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
+ TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
  TUF(cdp2,	e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
  TUF(mcr2,	e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
  TUF(mrc2,	e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
@@ -9198,8 +15047,8 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
  TUF(pld,	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
- TC3(ldrd,	00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
- TC3(strd,	00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
+ TC3(ldrd,	00000d0, e8500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
+ TC3(strd,	00000f0, e8400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
 
  TCE(mcrr,	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TCE(mrrc,	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
@@ -9226,6 +15075,7 @@ static const struct asm_opcode insns[] =
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
  TCE(ldrex,	1900f9f, e8500f00, 2, (RRnpc, ADDR),		  ldrex, t_ldrex),
+ TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
  TUF(mcrr2,	c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
  TUF(mrrc2,	c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
 
@@ -9309,12 +15159,11 @@ static const struct asm_opcode insns[] =
  TCE(smuadx,	700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
  TCE(smusd,	700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
  TCE(smusdx,	700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
- TUF(srsia,	8cd0500, e980c000, 1, (I31w),			   srs,  srs),
-  UF(srsib,	9cd0500,           1, (I31w),			   srs),
-  UF(srsda,	84d0500,	   1, (I31w),			   srs),
- TUF(srsdb,	94d0500, e800c000, 1, (I31w),			   srs,  srs),
+ TUF(srsia,	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
+  UF(srsib,	9c00500,           2, (oRRw, I31w),		   srs),
+  UF(srsda,	8400500,	   2, (oRRw, I31w),		   srs),
+ TUF(srsdb,	9400500, e800c000, 2, (oRRw, I31w),		   srs,  srs),
  TCE(ssat16,	6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),	   ssat16, t_ssat16),
- TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
  TCE(umaal,	0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
  TCE(usad8,	780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),	   smul,   t_simd),
  TCE(usada8,	7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
@@ -9354,18 +15203,20 @@ static const struct asm_opcode insns[] =
  TCE(ubfx,	7e00050, f3c00000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
 
  TCE(mls,	0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
- TCE(movw,	3000000, f2400000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
- TCE(movt,	3400000, f2c00000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
- TCE(rbit,	3ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
+ TCE(movw,	3000000, f2400000, 2, (RRnpc, HALF),		    mov16, t_mov16),
+ TCE(movt,	3400000, f2c00000, 2, (RRnpc, HALF),		    mov16, t_mov16),
+ TCE(rbit,	6ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
 
  TC3(ldrht,	03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(ldrsht,	03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(ldrsbt,	03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
  TC3(strht,	02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
 
-  UT(cbnz,      b900,    2, (RR, EXP), t_czb),
-  UT(cbz,       b100,    2, (RR, EXP), t_czb),
- /* ARM does not really have an IT instruction.  */
+  UT(cbnz,      b900,    2, (RR, EXP), t_cbz),
+  UT(cbz,       b100,    2, (RR, EXP), t_cbz),
+ /* ARM does not really have an IT instruction, so always allow it.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v1
  TUE(it,        0, bf08, 1, (COND),    it, t_it),
  TUE(itt,       0, bf0c, 1, (COND),    it, t_it),
  TUE(ite,       0, bf04, 1, (COND),    it, t_it),
@@ -9415,15 +15266,15 @@ static const struct asm_opcode insns[] =
  cCE(wfc,	e400110, 1, (RR),	     rd),
  cCE(rfc,	e500110, 1, (RR),	     rd),
 
- cCL(ldfs,	c100100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfd,	c108100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfe,	c500100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(ldfp,	c508100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(ldfs,	c100100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfd,	c108100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfe,	c500100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(ldfp,	c508100, 2, (RF, ADDRGLDC),  rd_cpaddr),
 
- cCL(stfs,	c000100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfd,	c008100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfe,	c400100, 2, (RF, ADDR),	     rd_cpaddr),
- cCL(stfp,	c408100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(stfs,	c000100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfd,	c008100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfe,	c400100, 2, (RF, ADDRGLDC),  rd_cpaddr),
+ cCL(stfp,	c408100, 2, (RF, ADDRGLDC),  rd_cpaddr),
 
  cCL(mvfs,	e008100, 2, (RF, RF_IF),     rd_rm),
  cCL(mvfsp,	e008120, 2, (RF, RF_IF),     rd_rm),
@@ -9866,8 +15717,8 @@ static const struct asm_opcode insns[] =
  cCE(fmxr,	ee00a10, 2, (RVC, RR),	      rn_rd),
 
   /* Memory operations.	 */
- cCE(flds,	d100a00, 2, (RVS, ADDR),      vfp_sp_ldst),
- cCE(fsts,	d000a00, 2, (RVS, ADDR),      vfp_sp_ldst),
+ cCE(flds,	d100a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
+ cCE(fsts,	d000a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
  cCE(fldmias,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
  cCE(fldmfds,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
  cCE(fldmdbs,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
@@ -9910,13 +15761,13 @@ static const struct asm_opcode insns[] =
 #undef ARM_VARIANT
 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision).  */
   /* Moves and type conversions.  */
- cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      rd_rm),
+ cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
  cCE(fcvtds,	eb70ac0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(fcvtsd,	eb70bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
- cCE(fmdhr,	e200b10, 2, (RVD, RR),	      rn_rd),
- cCE(fmdlr,	e000b10, 2, (RVD, RR),	      rn_rd),
- cCE(fmrdh,	e300b10, 2, (RR, RVD),	      rd_rn),
- cCE(fmrdl,	e100b10, 2, (RR, RVD),	      rd_rn),
+ cCE(fmdhr,	e200b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
+ cCE(fmdlr,	e000b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
+ cCE(fmrdh,	e300b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
+ cCE(fmrdl,	e100b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
  cCE(fsitod,	eb80bc0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(fuitod,	eb80b40, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
  cCE(ftosid,	ebd0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
@@ -9925,8 +15776,8 @@ static const struct asm_opcode insns[] =
  cCE(ftouizd,	ebc0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
 
   /* Memory operations.	 */
- cCE(fldd,	d100b00, 2, (RVD, ADDR),      vfp_dp_ldst),
- cCE(fstd,	d000b00, 2, (RVD, ADDR),      vfp_dp_ldst),
+ cCE(fldd,	d100b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
+ cCE(fstd,	d000b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
  cCE(fldmiad,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
  cCE(fldmfdd,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
  cCE(fldmdbd,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
@@ -9937,34 +15788,347 @@ static const struct asm_opcode insns[] =
  cCE(fstmfdd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
 
   /* Monadic operations.  */
- cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      rd_rm),
- cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      rd_rm),
- cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      rd_rm),
+ cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
 
   /* Dyadic operations.	 */
- cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
- cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
+ cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
 
   /* Comparisons.  */
- cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      rd_rm),
- cCE(fcmpzd,	eb50b40, 1, (RVD),	      rd),
- cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      rd_rm),
- cCE(fcmpezd,	eb50bc0, 1, (RVD),	      rd),
+ cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fcmpzd,	eb50b40, 1, (RVD),	      vfp_dp_rd),
+ cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
+ cCE(fcmpezd,	eb50bc0, 1, (RVD),	      vfp_dp_rd),
 
 #undef ARM_VARIANT
 #define ARM_VARIANT &fpu_vfp_ext_v2
  cCE(fmsrr,	c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
  cCE(fmrrs,	c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
- cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    rm_rd_rn),
- cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    rd_rn_rm),
+ cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    vfp_dp_rm_rd_rn),
+ cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    vfp_dp_rd_rn_rm),
+
+/* Instructions which may belong to either the Neon or VFP instruction sets.
+   Individual encoder functions perform additional architecture checks.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v1xd
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_ext_v1xd
+  /* These mnemonics are unique to VFP.  */
+ NCE(vsqrt,     0,       2, (RVSD, RVSD),       vfp_nsyn_sqrt),
+ NCE(vdiv,      0,       3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
+ nCE(vnmul,     vnmul,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vnmla,     vnmla,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vnmls,     vnmls,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
+ nCE(vcmp,      vcmp,    2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
+ nCE(vcmpe,     vcmpe,   2, (RVSD, RVSD_I0),    vfp_nsyn_cmp),
+ NCE(vpush,     0,       1, (VRSDLST),          vfp_nsyn_push),
+ NCE(vpop,      0,       1, (VRSDLST),          vfp_nsyn_pop),
+ NCE(vcvtz,     0,       2, (RVSD, RVSD),       vfp_nsyn_cvtz),
+
+  /* Mnemonics shared by Neon and VFP.  */
+ nCEF(vmul,     vmul,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
+ nCEF(vmla,     vmla,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
+ nCEF(vmls,     vmls,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
+
+ nCEF(vadd,     vadd,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
+ nCEF(vsub,     vsub,    3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
+
+ NCEF(vabs,     1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
+ NCEF(vneg,     1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
+
+ NCE(vldm,      c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldmia,    c900b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldmdb,    d100b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstm,      c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstmia,    c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vstmdb,    d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
+ NCE(vldr,      d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
+ NCE(vstr,      d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
+
+ nCEF(vcvt,     vcvt,    3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
+
+  /* NOTE: All VMOV encoding is special-cased!  */
+ NCE(vmov,      0,       1, (VMOV), neon_mov),
+ NCE(vmovq,     0,       1, (VMOV), neon_mov),
 
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_neon_ext_v1
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_neon_ext_v1
+  /* Data processing with three registers of the same length.  */
+  /* integer ops, valid types S8 S16 S32 U8 U16 U32.  */
+ NUF(vaba,      0000710, 3, (RNDQ, RNDQ,  RNDQ), neon_dyadic_i_su),
+ NUF(vabaq,     0000710, 3, (RNQ,  RNQ,   RNQ),  neon_dyadic_i_su),
+ NUF(vhadd,     0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vhaddq,    0000000, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+ NUF(vrhadd,    0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vrhaddq,   0000100, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+ NUF(vhsub,     0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
+ NUF(vhsubq,    0000200, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
+  /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vqadd,     0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
+ NUF(vqaddq,    0000010, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
+ NUF(vqsub,     0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
+ NUF(vqsubq,    0000210, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
+ NUF(vrshl,     0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
+ NUF(vrshlq,    0000500, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
+ NUF(vqrshl,    0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
+ NUF(vqrshlq,   0000510, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
+  /* If not immediate, fall back to neon_dyadic_i64_su.
+     shl_imm should accept I8 I16 I32 I64,
+     qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64.  */
+ nUF(vshl,      vshl,    3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
+ nUF(vshlq,     vshl,    3, (RNQ,  oRNQ,  RNDQ_I63b), neon_shl_imm),
+ nUF(vqshl,     vqshl,   3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
+ nUF(vqshlq,    vqshl,   3, (RNQ,  oRNQ,  RNDQ_I63b), neon_qshl_imm),
+  /* Logic ops, types optional & ignored.  */
+ nUF(vand,      vand,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vandq,     vand,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vbic,      vbic,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vbicq,     vbic,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vorr,      vorr,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vorrq,     vorr,    2, (RNQ,  NILO),        neon_logic),
+ nUF(vorn,      vorn,    2, (RNDQ, NILO),        neon_logic),
+ nUF(vornq,     vorn,    2, (RNQ,  NILO),        neon_logic),
+ nUF(veor,      veor,    3, (RNDQ, oRNDQ, RNDQ), neon_logic),
+ nUF(veorq,     veor,    3, (RNQ,  oRNQ,  RNQ),  neon_logic),
+  /* Bitfield ops, untyped.  */
+ NUF(vbsl,      1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbslq,     1100110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+ NUF(vbit,      1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbitq,     1200110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+ NUF(vbif,      1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
+ NUF(vbifq,     1300110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
+  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32.  */
+ nUF(vabd,      vabd,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vabdq,     vabd,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+ nUF(vmax,      vmax,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vmaxq,     vmax,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+ nUF(vmin,      vmin,    3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
+ nUF(vminq,     vmin,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
+  /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
+     back to neon_dyadic_if_su.  */
+ nUF(vcge,      vcge,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
+ nUF(vcgeq,     vcge,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
+ nUF(vcgt,      vcgt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
+ nUF(vcgtq,     vcgt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
+ nUF(vclt,      vclt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
+ nUF(vcltq,     vclt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
+ nUF(vcle,      vcle,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
+ nUF(vcleq,     vcle,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
+  /* Comparison. Type I8 I16 I32 F32.  */
+ nUF(vceq,      vceq,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
+ nUF(vceqq,     vceq,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_ceq),
+  /* As above, D registers only.  */
+ nUF(vpmax,     vpmax,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
+ nUF(vpmin,     vpmin,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
+  /* Int and float variants, signedness unimportant.  */
+ nUF(vmlaq,     vmla,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
+ nUF(vmlsq,     vmls,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
+ nUF(vpadd,     vpadd,   3, (RND,  oRND,  RND),       neon_dyadic_if_i_d),
+  /* Add/sub take types I8 I16 I32 I64 F32.  */
+ nUF(vaddq,     vadd,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
+ nUF(vsubq,     vsub,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
+  /* vtst takes sizes 8, 16, 32.  */
+ NUF(vtst,      0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
+ NUF(vtstq,     0000810, 3, (RNQ,  oRNQ,  RNQ),  neon_tst),
+  /* VMUL takes I8 I16 I32 F32 P8.  */
+ nUF(vmulq,     vmul,     3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mul),
+  /* VQD{R}MULH takes S16 S32.  */
+ nUF(vqdmulh,   vqdmulh,  3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqdmulhq,  vqdmulh,  3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmulh,  vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
+ nUF(vqrdmulhq, vqrdmulh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
+ NUF(vacge,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
+ NUF(vacgeq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
+ NUF(vacgt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
+ NUF(vacgtq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
+ NUF(vaclt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacltq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
+ NUF(vacle,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
+ NUF(vacleq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
+ NUF(vrecps,    0000f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
+ NUF(vrecpsq,   0000f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
+ NUF(vrsqrts,   0200f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
+ NUF(vrsqrtsq,  0200f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
+
+  /* Two address, int/float. Types S8 S16 S32 F32.  */
+ NUF(vabsq,     1b10300, 2, (RNQ,  RNQ),      neon_abs_neg),
+ NUF(vnegq,     1b10380, 2, (RNQ,  RNQ),      neon_abs_neg),
+
+  /* Data processing with two registers and a shift amount.  */
+  /* Right shifts, and variants with rounding.
+     Types accepted S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vshr,      0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
+ NUF(vshrq,     0800010, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
+ NUF(vrshr,     0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
+ NUF(vrshrq,    0800210, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
+ NUF(vsra,      0800110, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
+ NUF(vsraq,     0800110, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
+ NUF(vrsra,     0800310, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
+ NUF(vrsraq,    0800310, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
+  /* Shift and insert. Sizes accepted 8 16 32 64.  */
+ NUF(vsli,      1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
+ NUF(vsliq,     1800510, 3, (RNQ,  oRNQ,  I63), neon_sli),
+ NUF(vsri,      1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
+ NUF(vsriq,     1800410, 3, (RNQ,  oRNQ,  I64), neon_sri),
+  /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64.  */
+ NUF(vqshlu,    1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
+ NUF(vqshluq,   1800610, 3, (RNQ,  oRNQ,  I63), neon_qshlu_imm),
+  /* Right shift immediate, saturating & narrowing, with rounding variants.
+     Types accepted S16 S32 S64 U16 U32 U64.  */
+ NUF(vqshrn,    0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
+ NUF(vqrshrn,   0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
+  /* As above, unsigned. Types accepted S16 S32 S64.  */
+ NUF(vqshrun,   0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
+ NUF(vqrshrun,  0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
+  /* Right shift narrowing. Types accepted I16 I32 I64.  */
+ NUF(vshrn,     0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
+ NUF(vrshrn,    0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
+  /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant.  */
+ nUF(vshll,     vshll,   3, (RNQ, RND, I32),  neon_shll),
+  /* CVT with optional immediate for fixed-point variant.  */
+ nUF(vcvtq,     vcvt,    3, (RNQ, RNQ, oI32b), neon_cvt),
+
+ nUF(vmvn,      vmvn,    2, (RNDQ, RNDQ_IMVNb), neon_mvn),
+ nUF(vmvnq,     vmvn,    2, (RNQ,  RNDQ_IMVNb), neon_mvn),
+
+  /* Data processing, three registers of different lengths.  */
+  /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vabal,     0800500, 3, (RNQ, RND, RND),  neon_abal),
+ NUF(vabdl,     0800700, 3, (RNQ, RND, RND),  neon_dyadic_long),
+ NUF(vaddl,     0800000, 3, (RNQ, RND, RND),  neon_dyadic_long),
+ NUF(vsubl,     0800200, 3, (RNQ, RND, RND),  neon_dyadic_long),
+  /* If not scalar, fall back to neon_dyadic_long.
+     Vector types as above, scalar types S16 S32 U16 U32.  */
+ nUF(vmlal,     vmlal,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
+ nUF(vmlsl,     vmlsl,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
+  /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vaddw,     0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
+ NUF(vsubw,     0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
+  /* Dyadic, narrowing insns. Types I16 I32 I64.  */
+ NUF(vaddhn,    0800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vraddhn,   1800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vsubhn,    0800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+ NUF(vrsubhn,   1800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
+  /* Saturating doubling multiplies. Types S16 S32.  */
+ nUF(vqdmlal,   vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+ nUF(vqdmlsl,   vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+ nUF(vqdmull,   vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
+  /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
+     S16 S32 U16 U32.  */
+ nUF(vmull,     vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
+
+  /* Extract. Size 8.  */
+ NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
+ NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),
+
+  /* Two registers, miscellaneous.  */
+  /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
+ NUF(vrev64,    1b00000, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev64q,   1b00000, 2, (RNQ,  RNQ),      neon_rev),
+ NUF(vrev32,    1b00080, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev32q,   1b00080, 2, (RNQ,  RNQ),      neon_rev),
+ NUF(vrev16,    1b00100, 2, (RNDQ, RNDQ),     neon_rev),
+ NUF(vrev16q,   1b00100, 2, (RNQ,  RNQ),      neon_rev),
+  /* Vector replicate. Sizes 8 16 32.  */
+ nCE(vdup,      vdup,    2, (RNDQ, RR_RNSC),  neon_dup),
+ nCE(vdupq,     vdup,    2, (RNQ,  RR_RNSC),  neon_dup),
+  /* VMOVL. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vmovl,     0800a10, 2, (RNQ, RND),       neon_movl),
+  /* VMOVN. Types I16 I32 I64.  */
+ nUF(vmovn,     vmovn,   2, (RND, RNQ),       neon_movn),
+  /* VQMOVN. Types S16 S32 S64 U16 U32 U64.  */
+ nUF(vqmovn,    vqmovn,  2, (RND, RNQ),       neon_qmovn),
+  /* VQMOVUN. Types S16 S32 S64.  */
+ nUF(vqmovun,   vqmovun, 2, (RND, RNQ),       neon_qmovun),
+  /* VZIP / VUZP. Sizes 8 16 32.  */
+ NUF(vzip,      1b20180, 2, (RNDQ, RNDQ),     neon_zip_uzp),
+ NUF(vzipq,     1b20180, 2, (RNQ,  RNQ),      neon_zip_uzp),
+ NUF(vuzp,      1b20100, 2, (RNDQ, RNDQ),     neon_zip_uzp),
+ NUF(vuzpq,     1b20100, 2, (RNQ,  RNQ),      neon_zip_uzp),
+  /* VQABS / VQNEG. Types S8 S16 S32.  */
+ NUF(vqabs,     1b00700, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
+ NUF(vqabsq,    1b00700, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
+ NUF(vqneg,     1b00780, 2, (RNDQ, RNDQ),     neon_sat_abs_neg),
+ NUF(vqnegq,    1b00780, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
+  /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32.  */
+ NUF(vpadal,    1b00600, 2, (RNDQ, RNDQ),     neon_pair_long),
+ NUF(vpadalq,   1b00600, 2, (RNQ,  RNQ),      neon_pair_long),
+ NUF(vpaddl,    1b00200, 2, (RNDQ, RNDQ),     neon_pair_long),
+ NUF(vpaddlq,   1b00200, 2, (RNQ,  RNQ),      neon_pair_long),
+  /* Reciprocal estimates. Types U32 F32.  */
+ NUF(vrecpe,    1b30400, 2, (RNDQ, RNDQ),     neon_recip_est),
+ NUF(vrecpeq,   1b30400, 2, (RNQ,  RNQ),      neon_recip_est),
+ NUF(vrsqrte,   1b30480, 2, (RNDQ, RNDQ),     neon_recip_est),
+ NUF(vrsqrteq,  1b30480, 2, (RNQ,  RNQ),      neon_recip_est),
+  /* VCLS. Types S8 S16 S32.  */
+ NUF(vcls,      1b00400, 2, (RNDQ, RNDQ),     neon_cls),
+ NUF(vclsq,     1b00400, 2, (RNQ,  RNQ),      neon_cls),
+  /* VCLZ. Types I8 I16 I32.  */
+ NUF(vclz,      1b00480, 2, (RNDQ, RNDQ),     neon_clz),
+ NUF(vclzq,     1b00480, 2, (RNQ,  RNQ),      neon_clz),
+  /* VCNT. Size 8.  */
+ NUF(vcnt,      1b00500, 2, (RNDQ, RNDQ),     neon_cnt),
+ NUF(vcntq,     1b00500, 2, (RNQ,  RNQ),      neon_cnt),
+  /* Two address, untyped.  */
+ NUF(vswp,      1b20000, 2, (RNDQ, RNDQ),     neon_swp),
+ NUF(vswpq,     1b20000, 2, (RNQ,  RNQ),      neon_swp),
+  /* VTRN. Sizes 8 16 32.  */
+ nUF(vtrn,      vtrn,    2, (RNDQ, RNDQ),     neon_trn),
+ nUF(vtrnq,     vtrn,    2, (RNQ,  RNQ),      neon_trn),
+
+  /* Table lookup. Size 8.  */
+ NUF(vtbl,      1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
+ NUF(vtbx,      1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
+  /* Neon element/structure load/store.  */
+ nUF(vld1,      vld1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst1,      vst1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld2,      vld2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst2,      vst2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld3,      vld3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst3,      vst3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vld4,      vld4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+ nUF(vst4,      vst4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &fpu_vfp_ext_v3
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v3
+ cCE(fconsts,   eb00a00, 2, (RVS, I255),      vfp_sp_const),
+ cCE(fconstd,   eb00b00, 2, (RVD, I255),      vfp_dp_const),
+ cCE(fshtos,    eba0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(fshtod,    eba0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(fsltos,    eba0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(fsltod,    eba0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(fuhtos,    ebb0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(fuhtod,    ebb0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(fultos,    ebb0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(fultod,    ebb0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(ftoshs,    ebe0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(ftoshd,    ebe0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(ftosls,    ebe0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(ftosld,    ebe0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+ cCE(ftouhs,    ebf0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
+ cCE(ftouhd,    ebf0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
+ cCE(ftouls,    ebf0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
+ cCE(ftould,    ebf0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
+
+#undef THUMB_VARIANT
 #undef ARM_VARIANT
 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions.	 */
  cCE(mia,	e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
@@ -9996,7 +16160,7 @@ static const struct asm_opcode insns[] =
  cCE(tinsrb,	e600010, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
  cCE(tinsrh,	e600050, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
  cCE(tinsrw,	e600090, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
- cCE(tmcr,	e000110, 2, (RIWC, RR),		    rn_rd),
+ cCE(tmcr,	e000110, 2, (RIWC_RIWG, RR),	    rn_rd),
  cCE(tmcrr,	c400000, 3, (RIWR, RR, RR),	    rm_rd_rn),
  cCE(tmia,	e200010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
  cCE(tmiaph,	e280010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
@@ -10007,7 +16171,7 @@ static const struct asm_opcode insns[] =
  cCE(tmovmskb,	e100030, 2, (RR, RIWR),		    rd_rn),
  cCE(tmovmskh,	e500030, 2, (RR, RIWR),		    rd_rn),
  cCE(tmovmskw,	e900030, 2, (RR, RIWR),		    rd_rn),
- cCE(tmrc,	e100110, 2, (RR, RIWC),		    rd_rn),
+ cCE(tmrc,	e100110, 2, (RR, RIWC_RIWG),	    rd_rn),
  cCE(tmrrc,	c500000, 3, (RR, RR, RIWR),	    rd_rn_rm),
  cCE(torcb,	e13f150, 1, (RR),		    iwmmxt_tandorc),
  cCE(torch,	e53f150, 1, (RR),		    iwmmxt_tandorc),
@@ -10078,34 +16242,34 @@ static const struct asm_opcode insns[] =
  cCE(wpackwus,	e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdss,	ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wpackdus,	ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
- cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorhg,	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrorwg,	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wrordg,	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wsadb,	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadbz,	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadh,	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wsadhz,	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
  cCE(wshufh,	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
- cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllhg,	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsllwg,	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wslldg,	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrahg,	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrawg,	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsradg,	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlhg,	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrlwg,	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
- cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
  cCE(wsrldg,	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
  cCE(wstrb,	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
  cCE(wstrh,	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
@@ -10142,15 +16306,75 @@ static const struct asm_opcode insns[] =
  cCE(wzero,	e300000, 1, (RIWR),		    iwmmxt_wzero),
 
 #undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2.  */
+ cCE(torvscb,   e13f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvsch,   e53f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torvscw,   e93f190, 1, (RR),		    iwmmxt_tandorc),
+ cCE(wabsb,     e2001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsh,     e6001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsw,     ea001c0, 2, (RIWR, RIWR),           rd_rn),
+ cCE(wabsdiffb, e1001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffh, e5001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wabsdiffw, e9001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusl, e2001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddbhusm, e6001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddhc,    e600180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddwc,    ea00180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(waddsubhx, ea001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4,	e400000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wavg4r,    e500000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsn,   ee00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddsx,   eb00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddun,   ec00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmaddux,   e900100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmerge,    e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
+ cCE(wmiabb,    e0000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabt,    e1000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatb,    e2000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatt,    e3000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabbn,   e4000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiabtn,   e5000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiatbn,   e6000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiattn,   e7000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbb,   e800120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbt,   e900120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtb,   ea00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtt,   eb00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbbn,  ec00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawbtn,  ed00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawtbn,  ee00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmiawttn,  ef00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulsmr,   ef00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulumr,   ed00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwumr,  ec000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsmr,  ee000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwum,   ed000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwsm,   ef000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wmulwl,    eb000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabb,   e8000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabt,   e9000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatb,   ea000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatt,   eb000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabbn,  ec000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiabtn,  ed000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiatbn,  ee000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmiattn,  ef000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulm,    e100080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulmr,   e300080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwm,   ec000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wqmulwmr,  ee000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+ cCE(wsubaddhx, ed001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
+
+#undef ARM_VARIANT
 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions.	*/
- cCE(cfldrs,	c100400, 2, (RMF, ADDR),	      rd_cpaddr),
- cCE(cfldrd,	c500400, 2, (RMD, ADDR),	      rd_cpaddr),
- cCE(cfldr32,	c100500, 2, (RMFX, ADDR),	      rd_cpaddr),
- cCE(cfldr64,	c500500, 2, (RMDX, ADDR),	      rd_cpaddr),
- cCE(cfstrs,	c000400, 2, (RMF, ADDR),	      rd_cpaddr),
- cCE(cfstrd,	c400400, 2, (RMD, ADDR),	      rd_cpaddr),
- cCE(cfstr32,	c000500, 2, (RMFX, ADDR),	      rd_cpaddr),
- cCE(cfstr64,	c400500, 2, (RMDX, ADDR),	      rd_cpaddr),
+ cCE(cfldrs,	c100400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldrd,	c500400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldr32,	c100500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfldr64,	c500500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstrs,	c000400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstrd,	c400400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstr32,	c000500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
+ cCE(cfstr64,	c400500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
  cCE(cfmvsr,	e000450, 2, (RMF, RR),		      rn_rd),
  cCE(cfmvrs,	e100450, 2, (RR, RMF),		      rd_rn),
  cCE(cfmvdlr,	e000410, 2, (RMD, RR),		      rn_rd),
@@ -10235,6 +16459,10 @@ static const struct asm_opcode insns[] =
 #undef UE
 #undef UF
 #undef UT
+#undef NUF
+#undef nUF
+#undef NCE
+#undef nCE
 #undef OPS0
 #undef OPS1
 #undef OPS2
@@ -10428,7 +16656,10 @@ md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
 	  insn = THUMB_OP32 (opcode);
 	  insn |= (old_op & 0xf0) << 4;
 	  put_thumb32_insn (buf, insn);
-	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  if (opcode == T_MNEM_add_pc)
+	    reloc_type = BFD_RELOC_ARM_T32_IMM12;
+	  else
+	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
 	}
       else
 	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
@@ -10445,7 +16676,10 @@ md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
 	  insn |= (old_op & 0xf0) << 4;
 	  insn |= (old_op & 0xf) << 16;
 	  put_thumb32_insn (buf, insn);
-	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  if (insn & (1 << 20))
+	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
+	  else
+	    reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	}
       else
 	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
@@ -10479,16 +16713,42 @@ relax_immediate (fragS *fragp, int size, int shift)
   offset = fragp->fr_offset;
   /* Force misaligned offsets to 32-bit variant.  */
   if (offset & low)
-    return -4;
+    return 4;
   if (offset & ~mask)
     return 4;
   return 2;
 }
 
+/* Get the address of a symbol during relaxation.  */
+static addressT
+relaxed_symbol_addr(fragS *fragp, long stretch)
+{
+  fragS *sym_frag;
+  addressT addr;
+  symbolS *sym;
+
+  sym = fragp->fr_symbol;
+  sym_frag = symbol_get_frag (sym);
+  know (S_GET_SEGMENT (sym) != absolute_section
+	|| sym_frag == &zero_address_frag);
+  addr = S_GET_VALUE (sym) + fragp->fr_offset;
+
+  /* If frag has yet to be reached on this pass, assume it will
+     move by STRETCH just as we did.  If this is not so, it will
+     be because some frag between grows, and that will force
+     another pass.  */
+
+  if (stretch != 0
+      && sym_frag->relax_marker != fragp->relax_marker)
+    addr += stretch;
+
+  return addr;
+}
+
 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
    load.  */
 static int
-relax_adr (fragS *fragp, asection *sec)
+relax_adr (fragS *fragp, asection *sec, long stretch)
 {
   addressT addr;
   offsetT val;
@@ -10498,14 +16758,12 @@ relax_adr (fragS *fragp, asection *sec)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);
   addr = fragp->fr_address + fragp->fr_fix;
   addr = (addr + 4) & ~3;
-  /* Fix the insn as the 4-byte version if the target address is not
-     sufficiently aligned.  This is prevents an infinite loop when two
-     instructions have contradictory range/alignment requirements.  */
+  /* Force misaligned targets to 32-bit variant.  */
   if (val & 3)
-    return -4;
+    return 4;
   val -= addr;
   if (val < 0 || val > 1020)
     return 4;
@@ -10532,7 +16790,7 @@ relax_addsub (fragS *fragp, asection *sec)
    size of the offset field in the narrow instruction.  */
 
 static int
-relax_branch (fragS *fragp, asection *sec, int bits)
+relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
 {
   addressT addr;
   offsetT val;
@@ -10543,7 +16801,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
       || sec != S_GET_SEGMENT (fragp->fr_symbol))
     return 4;
 
-  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  val = relaxed_symbol_addr(fragp, stretch);
   addr = fragp->fr_address + fragp->fr_fix + 4;
   val -= addr;
 
@@ -10559,7 +16817,7 @@ relax_branch (fragS *fragp, asection *sec, int bits)
    the current size of the frag should change.  */
 
 int
-arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
+arm_relax_frag (asection *sec, fragS *fragp, long stretch)
 {
   int oldsize;
   int newsize;
@@ -10568,7 +16826,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
   switch (fragp->fr_subtype)
     {
     case T_MNEM_ldr_pc2:
-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);
       break;
     case T_MNEM_ldr_pc:
     case T_MNEM_ldr_sp:
@@ -10588,7 +16846,7 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 5, 0);
       break;
     case T_MNEM_adr:
-      newsize = relax_adr(fragp, sec);
+      newsize = relax_adr(fragp, sec, stretch);
       break;
     case T_MNEM_mov:
     case T_MNEM_movs:
@@ -10597,10 +16855,10 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
       newsize = relax_immediate(fragp, 8, 0);
       break;
     case T_MNEM_b:
-      newsize = relax_branch(fragp, sec, 11);
+      newsize = relax_branch(fragp, sec, 11, stretch);
       break;
     case T_MNEM_bcond:
-      newsize = relax_branch(fragp, sec, 8);
+      newsize = relax_branch(fragp, sec, 8, stretch);
       break;
     case T_MNEM_add_sp:
     case T_MNEM_add_pc:
@@ -10619,14 +16877,18 @@ arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
     default:
       abort();
     }
-  if (newsize < 0)
+
+  fragp->fr_var = newsize;
+  /* Freeze wide instructions that are at or before the same location as
+     in the previous pass.  This avoids infinite loops.
+     Don't freeze them unconditionally because targets may be artificialy
+     misaligned by the expansion of preceeding frags.  */
+  if (stretch <= 0 && newsize > 2)
     {
-      fragp->fr_var = -newsize;
       md_convert_frag (sec->owner, sec, fragp);
       frag_wane(fragp);
-      return -(newsize + oldsize);
     }
-  fragp->fr_var = newsize;
+
   return newsize - oldsize;
 }
 
@@ -10636,12 +16898,22 @@ valueT
 md_section_align (segT	 segment ATTRIBUTE_UNUSED,
 		  valueT size)
 {
-#ifdef OBJ_ELF
-  return size;
-#else
-  /* Round all sects to multiple of 4.	*/
-  return (size + 3) & ~3;
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
+  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
+    {
+      /* For a.out, force the section size to be aligned.  If we don't do
+	 this, BFD will align it for us, but it will not write out the
+	 final bytes of the section.  This may be a bug in BFD, but it is
+	 easier to fix it here since that is how the other a.out targets
+	 work.  */
+      int align;
+
+      align = bfd_get_section_alignment (stdoutput, segment);
+      size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
+    }
 #endif
+
+  return size;
 }
 
 /* This is called from HANDLE_ALIGN in write.c.	 Fill in the contents
@@ -10893,7 +17165,7 @@ finish_unwind_opcodes (void)
 
   if (unwind.fp_used)
     {
-      /* Adjust sp as neccessary.  */
+      /* Adjust sp as necessary.  */
       unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
       flush_pending_unwind ();
 
@@ -11141,12 +17413,22 @@ create_unwind_entry (int have_data)
   return 0;
 }
 
+
+/* Initialize the DWARF-2 unwind information for this procedure.  */
+
+void
+tc_arm_frame_initial_instructions (void)
+{
+  cfi_add_CFA_def_cfa (REG_SP, 0);
+}
+#endif /* OBJ_ELF */
+
 /* Convert REGNAME to a DWARF-2 register number.  */
 
 int
-tc_arm_regname_to_dw2regnum (const char *regname)
+tc_arm_regname_to_dw2regnum (char *regname)
 {
-  int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
+  int reg = arm_reg_parse (&regname, REG_TYPE_RN);
 
   if (reg == FAIL)
     return -1;
@@ -11154,15 +17436,18 @@ tc_arm_regname_to_dw2regnum (const char *regname)
   return reg;
 }
 
-/* Initialize the DWARF-2 unwind information for this procedure.  */
-
+#ifdef TE_PE
 void
-tc_arm_frame_initial_instructions (void)
+tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
 {
-  cfi_add_CFA_def_cfa (REG_SP, 0);
-}
-#endif /* OBJ_ELF */
+  expressionS expr;
 
+  expr.X_op = O_secrel;
+  expr.X_add_symbol = symbol;
+  expr.X_add_number = 0;
+  emit_expr (&expr, size);
+}
+#endif
 
 /* MD interface: Symbol and relocation handling.  */
 
@@ -11179,10 +17464,16 @@ md_pcrel_from_section (fixS * fixP, segT seg)
 
   /* If this is pc-relative and we are going to emit a relocation
      then we just want to put out any pipeline compensation that the linker
-     will need.  Otherwise we want to use the calculated base.  */
+     will need.  Otherwise we want to use the calculated base.
+     For WinCE we skip the bias for externals as well, since this
+     is how the MS ARM-CE assembler behaves and we want to be compatible.  */
   if (fixP->fx_pcrel 
       && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
-	  || arm_force_relocation (fixP)))
+	  || (arm_force_relocation (fixP)
+#ifdef TE_WINCE
+	      && !S_IS_EXTERNAL (fixP->fx_addsy)
+#endif
+	      )))
     base = 0;
 
   switch (fixP->fx_r_type)
@@ -11219,6 +17510,17 @@ md_pcrel_from_section (fixS * fixP, segT seg)
     case BFD_RELOC_ARM_PCREL_BLX:
     case BFD_RELOC_ARM_PLT32:
 #ifdef TE_WINCE
+      /* When handling fixups immediately, because we have already 
+         discovered the value of a symbol, or the address of the frag involved
+	 we must account for the offset by +8, as the OS loader will never see the reloc.
+         see fixup_segment() in write.c
+         The S_IS_EXTERNAL test handles the case of global symbols.
+         Those need the calculated base, not just the pipe compensation the linker will need.  */
+      if (fixP->fx_pcrel
+	  && fixP->fx_addsy != NULL
+	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
+	  && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
+	return base + 8;
       return base;
 #else
       return base + 8;
@@ -11406,11 +17708,11 @@ negate_data_op (unsigned long * instruction,
 /* Like negate_data_op, but for Thumb-2.   */
 
 static unsigned int
-thumb32_negate_data_op (offsetT *instruction, offsetT value)
+thumb32_negate_data_op (offsetT *instruction, unsigned int value)
 {
   int op, new_inst;
   int rd;
-  offsetT negated, inverted;
+  unsigned int negated, inverted;
 
   negated = encode_thumb32_immediate (-value);
   inverted = encode_thumb32_immediate (~value);
@@ -11471,7 +17773,7 @@ thumb32_negate_data_op (offsetT *instruction, offsetT value)
       return FAIL;
     }
 
-  if (value == FAIL)
+  if (value == (unsigned int)FAIL)
     return FAIL;
 
   *instruction &= T2_OPCODE_MASK;
@@ -11528,6 +17830,7 @@ md_apply_fix (fixS *	fixP,
   assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
 
   /* Note whether this will delete the relocation.  */
+
   if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
     fixP->fx_done = 1;
 
@@ -11676,7 +17979,7 @@ md_apply_fix (fixS *	fixP,
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid literal constant: pool needs to be closer"));
 	  else
-	    as_bad (_("bad immediate value for half-word offset (%ld)"),
+	    as_bad (_("bad immediate value for 8-bit offset (%ld)"),
 		    (long) value);
 	  break;
 	}
@@ -11835,6 +18138,7 @@ md_apply_fix (fixS *	fixP,
       break;
 
     case BFD_RELOC_ARM_T32_IMMEDIATE:
+    case BFD_RELOC_ARM_T32_ADD_IMM:
     case BFD_RELOC_ARM_T32_IMM12:
     case BFD_RELOC_ARM_T32_ADD_PC12:
       /* We claim that this fixup has been processed here,
@@ -11855,15 +18159,21 @@ md_apply_fix (fixS *	fixP,
       newval <<= 16;
       newval |= md_chars_to_number (buf+2, THUMB_SIZE);
 
-      /* FUTURE: Implement analogue of negate_data_op for T32.  */
-      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
+      newimm = FAIL;
+      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
+	  || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
 	{
 	  newimm = encode_thumb32_immediate (value);
 	  if (newimm == (unsigned int) FAIL)
 	    newimm = thumb32_negate_data_op (&newval, value);
 	}
-      else
+      if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
+	  && newimm == (unsigned int) FAIL)
 	{
+	  /* Turn add/sum into addw/subw.  */
+	  if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
+	    newval = (newval & 0xfeffffff) | 0x02000000;
+
 	  /* 12 bit immediate for addw/subw.  */
 	  if (value < 0)
 	    {
@@ -11977,18 +18287,34 @@ md_apply_fix (fixS *	fixP,
 	}
       break;
 
-    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
-      /* CZB can only branch forward.  */
-      if (value & ~0x7e)
-	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("branch out of range"));
+    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
+      /* CBZ can only branch forward.  */
 
-      if (fixP->fx_done || !seg->use_rela_p)
+      /* Attempts to use CBZ to branch to the next instruction
+         (which, strictly speaking, are prohibited) will be turned into
+         no-ops.
+
+	 FIXME: It may be better to remove the instruction completely and
+	 perform relaxation.  */
+      if (value == -2)
 	{
 	  newval = md_chars_to_number (buf, THUMB_SIZE);
-	  newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+	  newval = 0xbf00; /* NOP encoding T1 */
 	  md_number_to_chars (buf, newval, THUMB_SIZE);
 	}
+      else
+	{
+	  if (value & ~0x7e)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+		          _("branch out of range"));
+
+          if (fixP->fx_done || !seg->use_rela_p)
+	    {
+	      newval = md_chars_to_number (buf, THUMB_SIZE);
+	      newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+	      md_number_to_chars (buf, newval, THUMB_SIZE);
+	    }
+	}
       break;
 
     case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.	*/
@@ -12129,8 +18455,15 @@ md_apply_fix (fixS *	fixP,
     case BFD_RELOC_ARM_ROSEGREL32:
     case BFD_RELOC_ARM_SBREL32:
     case BFD_RELOC_32_PCREL:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       if (fixP->fx_done || !seg->use_rela_p)
-	md_number_to_chars (buf, value, 4);
+#ifdef TE_WINCE
+	/* For WinCE we only do this for pcrel fixups.  */
+	if (fixP->fx_done || fixP->fx_pcrel)
+#endif
+	  md_number_to_chars (buf, value, 4);
       break;
 
 #ifdef OBJ_ELF
@@ -12165,8 +18498,6 @@ md_apply_fix (fixS *	fixP,
 	newval = get_thumb32_insn (buf);
       newval &= 0xff7fff00;
       newval |= (value >> 2) | (sign ? INDEX_UP : 0);
-      if (value == 0)
-	newval &= ~WRITE_BACK;
       if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
 	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
 	md_number_to_chars (buf, newval, INSN_SIZE);
@@ -12358,6 +18689,216 @@ md_apply_fix (fixS *	fixP,
       fixP->fx_done = 0;
       return;
 
+    case BFD_RELOC_ARM_MOVW:
+    case BFD_RELOC_ARM_MOVT:
+    case BFD_RELOC_ARM_THUMB_MOVW:
+    case BFD_RELOC_ARM_THUMB_MOVT:
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  /* REL format relocations are limited to a 16-bit addend.  */
+	  if (!fixP->fx_done)
+	    {
+	      if (value < -0x1000 || value > 0xffff)
+		  as_bad_where (fixP->fx_file, fixP->fx_line,
+				_("offset too big"));
+	    }
+	  else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
+		   || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
+	    {
+	      value >>= 16;
+	    }
+
+	  if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
+	      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
+	    {
+	      newval = get_thumb32_insn (buf);
+	      newval &= 0xfbf08f00;
+	      newval |= (value & 0xf000) << 4;
+	      newval |= (value & 0x0800) << 15;
+	      newval |= (value & 0x0700) << 4;
+	      newval |= (value & 0x00ff);
+	      put_thumb32_insn (buf, newval);
+	    }
+	  else
+	    {
+	      newval = md_chars_to_number (buf, 4);
+	      newval &= 0xfff0f000;
+	      newval |= value & 0x0fff;
+	      newval |= (value & 0xf000) << 4;
+	      md_number_to_chars (buf, newval, 4);
+	    }
+	}
+      return;
+
+   case BFD_RELOC_ARM_ALU_PC_G0_NC:
+   case BFD_RELOC_ARM_ALU_PC_G0:
+   case BFD_RELOC_ARM_ALU_PC_G1_NC:
+   case BFD_RELOC_ARM_ALU_PC_G1:
+   case BFD_RELOC_ARM_ALU_PC_G2:
+   case BFD_RELOC_ARM_ALU_SB_G0_NC:
+   case BFD_RELOC_ARM_ALU_SB_G0:
+   case BFD_RELOC_ARM_ALU_SB_G1_NC:
+   case BFD_RELOC_ARM_ALU_SB_G1:
+   case BFD_RELOC_ARM_ALU_SB_G2:
+     assert (!fixP->fx_done);
+     if (!seg->use_rela_p)
+       {
+         bfd_vma insn;
+         bfd_vma encoded_addend;
+         bfd_vma addend_abs = abs (value);
+
+         /* Check that the absolute value of the addend can be
+            expressed as an 8-bit constant plus a rotation.  */
+         encoded_addend = encode_arm_immediate (addend_abs);
+         if (encoded_addend == (unsigned int) FAIL)
+	   as_bad_where (fixP->fx_file, fixP->fx_line,
+	                 _("the offset 0x%08lX is not representable"),
+                         addend_abs);
+
+         /* Extract the instruction.  */
+         insn = md_chars_to_number (buf, INSN_SIZE);
+
+         /* If the addend is positive, use an ADD instruction.
+            Otherwise use a SUB.  Take care not to destroy the S bit.  */
+         insn &= 0xff1fffff;
+         if (value < 0)
+           insn |= 1 << 22;
+         else
+           insn |= 1 << 23;
+
+         /* Place the encoded addend into the first 12 bits of the
+            instruction.  */
+         insn &= 0xfffff000;
+         insn |= encoded_addend;
+   
+         /* Update the instruction.  */  
+         md_number_to_chars (buf, insn, INSN_SIZE);
+       }
+     break;
+
+    case BFD_RELOC_ARM_LDR_PC_G0:
+    case BFD_RELOC_ARM_LDR_PC_G1:
+    case BFD_RELOC_ARM_LDR_PC_G2:
+    case BFD_RELOC_ARM_LDR_SB_G0:
+    case BFD_RELOC_ARM_LDR_SB_G1:
+    case BFD_RELOC_ARM_LDR_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend can be
+             encoded in 12 bits.  */
+          if (addend_abs >= 0x1000)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
+                          addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the absolute value of the addend into the first 12 bits
+             of the instruction.  */
+          insn &= 0xfffff000;
+          insn |= addend_abs;
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
+    case BFD_RELOC_ARM_LDRS_PC_G0:
+    case BFD_RELOC_ARM_LDRS_PC_G1:
+    case BFD_RELOC_ARM_LDRS_PC_G2:
+    case BFD_RELOC_ARM_LDRS_SB_G0:
+    case BFD_RELOC_ARM_LDRS_SB_G1:
+    case BFD_RELOC_ARM_LDRS_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend can be
+             encoded in 8 bits.  */
+          if (addend_abs >= 0x100)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
+                          addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the first four bits of the absolute value of the addend
+             into the first 4 bits of the instruction, and the remaining
+             four into bits 8 .. 11.  */
+          insn &= 0xfffff0f0;
+          insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
+    case BFD_RELOC_ARM_LDC_PC_G0:
+    case BFD_RELOC_ARM_LDC_PC_G1:
+    case BFD_RELOC_ARM_LDC_PC_G2:
+    case BFD_RELOC_ARM_LDC_SB_G0:
+    case BFD_RELOC_ARM_LDC_SB_G1:
+    case BFD_RELOC_ARM_LDC_SB_G2:
+      assert (!fixP->fx_done);
+      if (!seg->use_rela_p)
+        {
+          bfd_vma insn;
+          bfd_vma addend_abs = abs (value);
+
+          /* Check that the absolute value of the addend is a multiple of
+             four and, when divided by four, fits in 8 bits.  */
+          if (addend_abs & 0x3)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (must be word-aligned)"),
+                          addend_abs);
+
+          if ((addend_abs >> 2) > 0xff)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+	  	          _("bad offset 0x%08lX (must be an 8-bit number of words)"),
+                          addend_abs);
+
+          /* Extract the instruction.  */
+          insn = md_chars_to_number (buf, INSN_SIZE);
+
+          /* If the addend is negative, clear bit 23 of the instruction.
+             Otherwise set it.  */
+          if (value < 0)
+            insn &= ~(1 << 23);
+          else
+            insn |= 1 << 23;
+
+          /* Place the addend (divided by four) into the first eight
+             bits of the instruction.  */
+          insn &= 0xfffffff0;
+          insn |= addend_abs >> 2;
+    
+          /* Update the instruction.  */  
+          md_number_to_chars (buf, insn, INSN_SIZE);
+        }
+      break;
+
     case BFD_RELOC_UNUSED:
     default:
       as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -12412,6 +18953,34 @@ tc_gen_reloc (asection *section, fixS *fixp)
 	  break;
 	}
 
+    case BFD_RELOC_ARM_MOVW:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_MOVW_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_MOVT:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_MOVT_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_THUMB_MOVW:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
+	  break;
+	}
+
+    case BFD_RELOC_ARM_THUMB_MOVT:
+      if (fixp->fx_pcrel)
+	{
+	  code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
+	  break;
+	}
+
     case BFD_RELOC_NONE:
     case BFD_RELOC_ARM_PCREL_BRANCH:
     case BFD_RELOC_ARM_PCREL_BLX:
@@ -12425,6 +18994,9 @@ tc_gen_reloc (asection *section, fixS *fixp)
     case BFD_RELOC_THUMB_PCREL_BLX:
     case BFD_RELOC_VTABLE_ENTRY:
     case BFD_RELOC_VTABLE_INHERIT:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       code = fixp->fx_r_type;
       break;
 
@@ -12449,6 +19021,34 @@ tc_gen_reloc (asection *section, fixS *fixp)
     case BFD_RELOC_ARM_TLS_LDO32:
     case BFD_RELOC_ARM_PCREL_CALL:
     case BFD_RELOC_ARM_PCREL_JUMP:
+    case BFD_RELOC_ARM_ALU_PC_G0_NC:
+    case BFD_RELOC_ARM_ALU_PC_G0:
+    case BFD_RELOC_ARM_ALU_PC_G1_NC:
+    case BFD_RELOC_ARM_ALU_PC_G1:
+    case BFD_RELOC_ARM_ALU_PC_G2:
+    case BFD_RELOC_ARM_LDR_PC_G0:
+    case BFD_RELOC_ARM_LDR_PC_G1:
+    case BFD_RELOC_ARM_LDR_PC_G2:
+    case BFD_RELOC_ARM_LDRS_PC_G0:
+    case BFD_RELOC_ARM_LDRS_PC_G1:
+    case BFD_RELOC_ARM_LDRS_PC_G2:
+    case BFD_RELOC_ARM_LDC_PC_G0:
+    case BFD_RELOC_ARM_LDC_PC_G1:
+    case BFD_RELOC_ARM_LDC_PC_G2:
+    case BFD_RELOC_ARM_ALU_SB_G0_NC:
+    case BFD_RELOC_ARM_ALU_SB_G0:
+    case BFD_RELOC_ARM_ALU_SB_G1_NC:
+    case BFD_RELOC_ARM_ALU_SB_G1:
+    case BFD_RELOC_ARM_ALU_SB_G2:
+    case BFD_RELOC_ARM_LDR_SB_G0:
+    case BFD_RELOC_ARM_LDR_SB_G1:
+    case BFD_RELOC_ARM_LDR_SB_G2:
+    case BFD_RELOC_ARM_LDRS_SB_G0:
+    case BFD_RELOC_ARM_LDRS_SB_G1:
+    case BFD_RELOC_ARM_LDRS_SB_G2:
+    case BFD_RELOC_ARM_LDC_SB_G0:
+    case BFD_RELOC_ARM_LDC_SB_G1:
+    case BFD_RELOC_ARM_LDC_SB_G2:
       code = fixp->fx_r_type;
       break;
 
@@ -12579,6 +19179,14 @@ cons_fix_new_arm (fragS *	frag,
       break;
     }
 
+#ifdef TE_PE
+  if (exp->X_op == O_secrel)
+  {
+    exp->X_op = O_symbol;
+    type = BFD_RELOC_32_SECREL;
+  }
+#endif
+
   fix_new_exp (frag, where, (int) size, exp, pcrel, type);
 }
 
@@ -12612,34 +19220,31 @@ arm_force_relocation (struct fix * fixp)
   if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
       || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
       || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
       || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
     return 0;
 
-  return generic_force_reloc (fixp);
-}
-
-#ifdef OBJ_COFF
-/* This is a little hack to help the gas/arm/adrl.s test.  It prevents
-   local labels from being added to the output symbol table when they
-   are used with the ADRL pseudo op.  The ADRL relocation should always
-   be resolved before the binbary is emitted, so it is safe to say that
-   it is adjustable.  */
+  /* Always leave these relocations for the linker.  */
+  if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
+       && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
+      || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
+    return 1;
 
-bfd_boolean
-arm_fix_adjustable (fixS * fixP)
-{
-  if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+  /* Always generate relocations against function symbols.  */
+  if (fixp->fx_r_type == BFD_RELOC_32
+      && fixp->fx_addsy
+      && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
     return 1;
-  return 0;
+
+  return generic_force_reloc (fixp);
 }
-#endif
 
-#ifdef OBJ_ELF
-/* Relocations against Thumb function names must be left unadjusted,
-   so that the linker can use this information to correctly set the
-   bottom bit of their addresses.  The MIPS version of this function
+#if defined (OBJ_ELF) || defined (OBJ_COFF)
+/* Relocations against function names must be left unadjusted,
+   so that the linker can use this information to generate interworking
+   stubs.  The MIPS version of this function
    also prevents relocations that are mips-16 specific, but I do not
    know why it does this.
 
@@ -12656,6 +19261,10 @@ arm_fix_adjustable (fixS * fixP)
   if (fixP->fx_addsy == NULL)
     return 1;
 
+  /* Preserve relocations against symbols with function type.  */
+  if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
+    return 0;
+
   if (THUMB_IS_FUNC (fixP->fx_addsy)
       && fixP->fx_subsy == NULL)
     return 0;
@@ -12677,8 +19286,17 @@ arm_fix_adjustable (fixS * fixP)
       || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
     return 0;
 
+  /* Similarly for group relocations.  */
+  if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
+       && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
+      || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
+    return 0;
+
   return 1;
 }
+#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
+
+#ifdef OBJ_ELF
 
 const char *
 elf32_arm_target_format (void)
@@ -12789,14 +19407,15 @@ arm_adjust_symtab (void)
 	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
 	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
 
-	  if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
+	  if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
+		BFD_ARM_SPECIAL_SYM_TYPE_ANY))
 	    {
 	      /* If it's a .thumb_func, declare it as so,
 		 otherwise tag label as .code 16.  */
 	      if (THUMB_IS_FUNC (sym))
 		elf_sym->internal_elf_sym.st_info =
 		  ELF_ST_INFO (bind, STT_ARM_TFUNC);
-	      else
+	      else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
 		elf_sym->internal_elf_sym.st_info =
 		  ELF_ST_INFO (bind, STT_ARM_16BIT);
 	    }
@@ -12817,6 +19436,16 @@ set_constant_flonums (void)
       abort ();
 }
 
+/* Auto-select Thumb mode if it's the only available instruction set for the
+   given architecture.  */
+
+static void
+autoselect_thumb_from_cpu_variant (void)
+{
+  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+    opcode_select (16);
+}
+
 void
 md_begin (void)
 {
@@ -12894,9 +19523,9 @@ md_begin (void)
 
   if (!mfpu_opt)
     {
-      if (!mcpu_cpu_opt)
+      if (mcpu_cpu_opt != NULL)
 	mfpu_opt = &fpu_default;
-      else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
+      else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
 	mfpu_opt = &fpu_arch_vfp_v2;
       else
 	mfpu_opt = &fpu_arch_fpa;
@@ -12917,6 +19546,8 @@ md_begin (void)
 
   ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
 
+  autoselect_thumb_from_cpu_variant ();
+
   arm_arch_used = thumb_arch_used = arm_arch_none;
 
 #if defined OBJ_COFF || defined OBJ_ELF
@@ -12992,7 +19623,9 @@ md_begin (void)
 #endif
 
   /* Record the CPU type as well.  */
-  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
+    mach = bfd_mach_arm_iWMMXt2;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
     mach = bfd_mach_arm_iWMMXt;
   else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
     mach = bfd_mach_arm_XScale;
@@ -13362,13 +19995,16 @@ static const struct arm_cpu_option_table arm_cpus[] =
   {"arm1156t2f-s",	ARM_ARCH_V6T2,	 FPU_ARCH_VFP_V2, NULL},
   {"arm1176jz-s",	ARM_ARCH_V6ZK,	 FPU_NONE,	  NULL},
   {"arm1176jzf-s",	ARM_ARCH_V6ZK,	 FPU_ARCH_VFP_V2, NULL},
-  {"cortex-a8",		ARM_ARCH_V7A,	 FPU_ARCH_VFP_V2, NULL},
+  {"cortex-a8",		ARM_ARCH_V7A,	 ARM_FEATURE(0, FPU_VFP_V3
+                                                        | FPU_NEON_EXT_V1),
+                                                          NULL},
   {"cortex-r4",		ARM_ARCH_V7R,	 FPU_NONE,	  NULL},
   {"cortex-m3",		ARM_ARCH_V7M,	 FPU_NONE,	  NULL},
   /* ??? XSCALE is really an architecture.  */
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* ??? iwmmxt is not a processor.  */
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
   {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* Maverick */
   {"ep9312",	ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
@@ -13413,11 +20049,17 @@ static const struct arm_arch_option_table arm_archs[] =
   {"armv6zt2",		ARM_ARCH_V6ZT2,	 FPU_ARCH_VFP},
   {"armv6zkt2",		ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
   {"armv7",		ARM_ARCH_V7,	 FPU_ARCH_VFP},
+  /* The official spelling of the ARMv7 profile variants is the dashed form.
+     Accept the non-dashed form for compatibility with old toolchains.  */
   {"armv7a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
   {"armv7r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
   {"armv7m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
+  {"armv7-a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
+  {"armv7-r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
+  {"armv7-m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
+  {"iwmmxt2",		ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
   {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE}
 };
 
@@ -13433,6 +20075,7 @@ static const struct arm_option_cpu_value_table arm_extensions[] =
   {"maverick",		ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
   {"xscale",		ARM_FEATURE (0, ARM_CEXT_XSCALE)},
   {"iwmmxt",		ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
+  {"iwmmxt2",		ARM_FEATURE (0, ARM_CEXT_IWMMXT2)},
   {NULL,		ARM_ARCH_NONE}
 };
 
@@ -13452,6 +20095,7 @@ static const struct arm_option_cpu_value_table arm_fpus[] =
   {"softvfp+vfp",	FPU_ARCH_VFP_V2},
   {"vfp",		FPU_ARCH_VFP_V2},
   {"vfp9",		FPU_ARCH_VFP_V2},
+  {"vfp3",              FPU_ARCH_VFP_V3},
   {"vfp10",		FPU_ARCH_VFP_V2},
   {"vfp10-r0",		FPU_ARCH_VFP_V1},
   {"vfpxd",		FPU_ARCH_VFP_V1xD},
@@ -13460,6 +20104,7 @@ static const struct arm_option_cpu_value_table arm_fpus[] =
   {"arm1136jfs",	FPU_ARCH_VFP_V2},
   {"arm1136jf-s",	FPU_ARCH_VFP_V2},
   {"maverick",		FPU_ARCH_MAVERICK},
+  {"neon",              FPU_ARCH_VFP_V3_PLUS_NEON_V1},
   {NULL,		ARM_ARCH_NONE}
 };
 
@@ -13855,7 +20500,13 @@ aeabi_set_public_attributes (void)
   ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
   ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
   ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
-  
+  /*Allow the user to override the reported architecture.  */
+  if (object_arch)
+    {
+      ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
+      ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
+    }
+
   tmp = flags;
   arch = 0;
   for (p = cpu_arch_ver; p->val; p++)
@@ -13881,57 +20532,56 @@ aeabi_set_public_attributes (void)
 	  for (i = 0; p[i]; i++)
 	    p[i] = TOUPPER (p[i]);
 	}
-      elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
+      bfd_elf_add_proc_attr_string (stdoutput, 5, p);
     }
   /* Tag_CPU_arch.  */
-  elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
+  bfd_elf_add_proc_attr_int (stdoutput, 6, arch);
   /* Tag_CPU_arch_profile.  */
   if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
   else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
-    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
+    bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
   /* Tag_ARM_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
-    elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 8, 1);
   /* Tag_THUMB_ISA_use.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
-    elf32_arm_add_eabi_attr_int (stdoutput, 9,
+    bfd_elf_add_proc_attr_int (stdoutput, 9,
 	ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
   /* Tag_VFP_arch.  */
-  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
-      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
-  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
-	   || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
-    elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v3)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v3))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 3);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v2)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v2))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 2);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1)
+           || ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_vfp_ext_v1xd)
+           || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_vfp_ext_v1xd))
+    bfd_elf_add_proc_attr_int (stdoutput, 10, 1);
   /* Tag_WMMX_arch.  */
   if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
       || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
-    elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
+    bfd_elf_add_proc_attr_int (stdoutput, 11, 1);
+  /* Tag_NEON_arch.  */
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1))
+    bfd_elf_add_proc_attr_int (stdoutput, 12, 1);
 }
 
-/* Add the .ARM.attributes section.  */
+/* Add the default contents for the .ARM.attributes section.  */
 void
 arm_md_end (void)
 {
-  segT s;
-  char *p;
-  addressT addr;
-  offsetT size;
-  
   if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
     return;
 
   aeabi_set_public_attributes ();
-  size = elf32_arm_eabi_attr_size (stdoutput);
-  s = subseg_new (".ARM.attributes", 0);
-  bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
-  addr = frag_now_fix ();
-  p = frag_more (size);
-  elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
 }
+#endif /* OBJ_ELF */
 
 
 /* Parse a .cpu directive.  */
@@ -14009,6 +20659,37 @@ s_arm_arch (int ignored ATTRIBUTE_UNUSED)
 }
 
 
+/* Parse a .object_arch directive.  */
+
+static void
+s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
+{
+  const struct arm_arch_option_table *opt;
+  char saved_char;
+  char *name;
+
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
+
+  /* Skip the first "all" entry.  */
+  for (opt = arm_archs + 1; opt->name != NULL; opt++)
+    if (streq (opt->name, name))
+      {
+	object_arch = &opt->value;
+	*input_line_pointer = saved_char;
+	demand_empty_rest_of_line ();
+	return;
+      }
+
+  as_bad (_("unknown architecture `%s'\n"), name);
+  *input_line_pointer = saved_char;
+  ignore_rest_of_line ();
+}
+
+
 /* Parse a .fpu directive.  */
 
 static void
@@ -14038,5 +20719,10 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
   *input_line_pointer = saved_char;
   ignore_rest_of_line ();
 }
-#endif /* OBJ_ELF */
 
+/* Copy symbol information.  */
+void
+arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
+{
+  ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
+}
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index f2615770c47d..d6dee9b1a9aa 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -1,6 +1,6 @@
 /* This file is tc-arm.h
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
 
@@ -66,6 +66,8 @@ struct fix;
 # if defined TE_PE
 #  if defined TE_EPOC
 #   define TARGET_FORMAT (target_big_endian ? "epoc-pe-arm-big" : "epoc-pe-arm-little")
+#  elif defined TE_WINCE
+#   define TARGET_FORMAT (target_big_endian ? "pe-arm-wince-big" : "pe-arm-wince-little")
 #  else
 #   define TARGET_FORMAT (target_big_endian ? "pe-arm-big" : "pe-arm-little")
 #  endif
@@ -98,6 +100,7 @@ extern int arm_optimize_expr (expressionS *, operatorT, expressionS *);
 #ifdef OBJ_ELF
 #define md_end arm_md_end
 extern void arm_md_end (void);
+bfd_boolean arm_is_eabi (void);
 #endif
 
 /* NOTE: The fake label creation in stabs.c:s_stab_generic() has
@@ -120,12 +123,30 @@ extern void arm_md_end (void);
 
 #define ARM_IS_THUMB(s)		(ARM_GET_FLAG (s) & ARM_FLAG_THUMB)
 #define ARM_IS_INTERWORK(s)	(ARM_GET_FLAG (s) & ARM_FLAG_INTERWORK)
+#ifdef OBJ_ELF
+
+/* For ELF objects THUMB_IS_FUNC is inferred from
+   ARM_IS_TUMB and the function type.  */
+#define THUMB_IS_FUNC(s) \
+  ((arm_is_eabi () \
+    && (ARM_IS_THUMB (s)) \
+    && (symbol_get_bfdsym (s)->flags & BSF_FUNCTION)) \
+   || (ARM_GET_FLAG (s) & THUMB_FLAG_FUNC))
+
+#else
 #define THUMB_IS_FUNC(s)	(ARM_GET_FLAG (s) & THUMB_FLAG_FUNC)
+#endif
 
 #define ARM_SET_THUMB(s,t)      ((t) ? ARM_SET_FLAG (s, ARM_FLAG_THUMB)     : ARM_RESET_FLAG (s, ARM_FLAG_THUMB))
 #define ARM_SET_INTERWORK(s,t)  ((t) ? ARM_SET_FLAG (s, ARM_FLAG_INTERWORK) : ARM_RESET_FLAG (s, ARM_FLAG_INTERWORK))
 #define THUMB_SET_FUNC(s,t)     ((t) ? ARM_SET_FLAG (s, THUMB_FLAG_FUNC)    : ARM_RESET_FLAG (s, THUMB_FLAG_FUNC))
 
+void arm_copy_symbol_attributes (symbolS *, symbolS *);
+#ifndef TC_COPY_SYMBOL_ATTRIBUTES
+#define TC_COPY_SYMBOL_ATTRIBUTES(DEST, SRC) \
+  (arm_copy_symbol_attributes (DEST, SRC))
+#endif
+
 #define TC_START_LABEL(C,STR)            (c == ':' || (c == '/' && arm_data_in_code ()))
 #define tc_canonicalize_symbol_name(str) arm_canonicalize_symbol_name (str);
 #define obj_adjust_symtab() 		 arm_adjust_symtab ()
@@ -146,7 +167,6 @@ extern void arm_md_end (void);
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_ARM_GOT32		\
    || (FIX)->fx_r_type == BFD_RELOC_32			\
    || TC_FORCE_RELOCATION (FIX))
@@ -175,14 +195,27 @@ extern void arm_md_end (void);
       goto LABEL;								\
     }
 
+#define DWARF2_LINE_MIN_INSN_LENGTH 	2
+
+/* The lr register is r14.  */
+#define DWARF2_DEFAULT_RETURN_COLUMN  14
+
+/* Registers are generally saved at negative offsets to the CFA.  */
+#define DWARF2_CIE_DATA_ALIGNMENT     (-4)
+
 #ifdef OBJ_ELF
-# define DWARF2_LINE_MIN_INSN_LENGTH 	2
 # define obj_frob_symbol(sym, punt)	armelf_frob_symbol ((sym), & (punt))
 # define md_elf_section_change_hook()	arm_elf_change_section ()
 # define md_elf_section_type(str, len)	arm_elf_section_type (str, len)
 # define GLOBAL_OFFSET_TABLE_NAME	"_GLOBAL_OFFSET_TABLE_"
 # define TC_SEGMENT_INFO_TYPE 		struct arm_segment_info_type
 
+/* This is not really an alignment operation, but it's something we
+   need to do at the same time: whenever we are figuring out the
+   alignment for data, we should check whether a $d symbol is
+   necessary.  */
+# define md_cons_align(nbytes)		mapping_state (MAP_DATA)
+
 enum mstate
 {
   MAP_UNDEFINED = 0, /* Must be zero, for seginfo in new sections.  */
@@ -191,6 +224,8 @@ enum mstate
   MAP_THUMB
 };
 
+void mapping_state (enum mstate);
+
 struct arm_segment_info_type
 {
   enum mstate mapstate;
@@ -200,12 +235,6 @@ struct arm_segment_info_type
 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 #define TARGET_USE_CFIPOP              1
 
-/* The lr register is r14.  */
-#define DWARF2_DEFAULT_RETURN_COLUMN  14
-
-/* Registers are generally saved at negative offsets to the CFA.  */
-#define DWARF2_CIE_DATA_ALIGNMENT     -4
-
 /* CFI hooks.  */
 #define tc_regname_to_dw2regnum            tc_arm_regname_to_dw2regnum
 #define tc_cfi_frame_initial_instructions  tc_arm_frame_initial_instructions
@@ -244,5 +273,14 @@ extern void arm_init_frag (struct frag *);
 extern void arm_handle_align (struct frag *);
 extern bfd_boolean arm_fix_adjustable (struct fix *);
 extern int arm_elf_section_type (const char *, size_t);
-extern int tc_arm_regname_to_dw2regnum (const char *regname);
+extern int tc_arm_regname_to_dw2regnum (char *regname);
 extern void tc_arm_frame_initial_instructions (void);
+
+#ifdef TE_PE
+
+#define O_secrel O_md1
+
+#define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
+void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
+
+#endif /* TE_PE */
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c
index 7a95033d53a3..2de962dd2b2a 100644
--- a/gas/config/tc-avr.c
+++ b/gas/config/tc-avr.c
@@ -21,11 +21,9 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
-#include "libiberty.h"
 
 struct avr_opcodes_s
 {
@@ -63,89 +61,104 @@ struct mcu_type_s
 
 static struct mcu_type_s mcu_types[] =
 {
-  {"avr1",      AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"avr2",      AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"avr3",      AVR_ISA_M103,     bfd_mach_avr3},
-  {"avr4",      AVR_ISA_M8,       bfd_mach_avr4},
-  {"avr5",      AVR_ISA_ALL,      bfd_mach_avr5},
-  {"at90s1200", AVR_ISA_1200,     bfd_mach_avr1},
-  {"attiny10",  AVR_ISA_TINY1,    bfd_mach_avr1}, /* XXX -> tn11 */
-  {"attiny11",  AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"attiny12",  AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"attiny15",  AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"attiny28",  AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"at90s2313", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90s2323", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90s2333", AVR_ISA_2xxx,     bfd_mach_avr2}, /* XXX -> 4433 */
-  {"at90s2343", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"attiny22",  AVR_ISA_2xxx,     bfd_mach_avr2}, /* XXX -> 2343 */
-  {"attiny26",  AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90s4433", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90s4414", AVR_ISA_2xxx,     bfd_mach_avr2}, /* XXX -> 8515 */
-  {"at90s4434", AVR_ISA_2xxx,     bfd_mach_avr2}, /* XXX -> 8535 */
-  {"at90s8515", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90s8535", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at90c8534", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"at86rf401", AVR_ISA_2xxx,     bfd_mach_avr2},
-  {"attiny13",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny2313",AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny261", AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny461", AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny861", AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny24",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny44",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny84",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny25",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny45",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"attiny85",  AVR_ISA_TINY2,    bfd_mach_avr2},
-  {"atmega603", AVR_ISA_M603,     bfd_mach_avr3}, /* XXX -> m103 */
-  {"atmega103", AVR_ISA_M103,     bfd_mach_avr3},
-  {"at43usb320",AVR_ISA_M103,     bfd_mach_avr3},
-  {"at43usb355",AVR_ISA_M603,     bfd_mach_avr3},
-  {"at76c711",  AVR_ISA_M603,     bfd_mach_avr3},
-  {"atmega48",  AVR_ISA_PWMx,     bfd_mach_avr4},
-  {"atmega8",   AVR_ISA_M8,       bfd_mach_avr4},
-  {"atmega83",  AVR_ISA_M8,       bfd_mach_avr4}, /* XXX -> m8535 */
-  {"atmega85",  AVR_ISA_M8,       bfd_mach_avr4}, /* XXX -> m8 */
-  {"atmega88",  AVR_ISA_PWMx,     bfd_mach_avr4},
-  {"atmega8515",AVR_ISA_M8,       bfd_mach_avr4},
-  {"atmega8535",AVR_ISA_M8,       bfd_mach_avr4},
-  {"at90pwm2",  AVR_ISA_PWMx,     bfd_mach_avr4},
-  {"at90pwm3",  AVR_ISA_PWMx,     bfd_mach_avr4},
-  {"atmega16",  AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega161", AVR_ISA_M161,     bfd_mach_avr5},
-  {"atmega162", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega163", AVR_ISA_M161,     bfd_mach_avr5},
-  {"atmega164", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega165", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega168", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega169", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega32",  AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega323", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega324", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega325", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega329", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega3250",AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega3290",AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega406", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega64",  AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega640", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega644", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega128", AVR_ISA_M128,     bfd_mach_avr5},
-  {"atmega1280",AVR_ISA_M128,     bfd_mach_avr5},
-  {"atmega1281",AVR_ISA_M128,     bfd_mach_avr5},
-  {"atmega645", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega649", AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega6450",AVR_ISA_M323,     bfd_mach_avr5},
-  {"atmega6490",AVR_ISA_M323,     bfd_mach_avr5},
-  {"at90can32" ,AVR_ISA_M323,     bfd_mach_avr5},
-  {"at90can64" ,AVR_ISA_M323,     bfd_mach_avr5},
-  {"at90can128",AVR_ISA_M128,     bfd_mach_avr5},
+  {"avr1",       AVR_ISA_TINY1,   bfd_mach_avr1},
+  {"avr2",       AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"avr3",       AVR_ISA_M103,    bfd_mach_avr3},
+  {"avr4",       AVR_ISA_M8,      bfd_mach_avr4},
+  {"avr5",       AVR_ISA_ALL,     bfd_mach_avr5},
+  {"avr6",       AVR_ISA_ALL,     bfd_mach_avr6},
+  {"at90s1200",  AVR_ISA_1200,    bfd_mach_avr1},
+  {"attiny10",   AVR_ISA_TINY1,   bfd_mach_avr1}, /* XXX -> tn11 */
+  {"attiny11",   AVR_ISA_TINY1,   bfd_mach_avr1},
+  {"attiny12",   AVR_ISA_TINY1,   bfd_mach_avr1},
+  {"attiny15",   AVR_ISA_TINY1,   bfd_mach_avr1},
+  {"attiny28",   AVR_ISA_TINY1,   bfd_mach_avr1},
+  {"at90s2313",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90s2323",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90s2333",  AVR_ISA_2xxx,    bfd_mach_avr2}, /* XXX -> 4433 */
+  {"at90s2343",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"attiny22",   AVR_ISA_2xxx,    bfd_mach_avr2}, /* XXX -> 2343 */
+  {"attiny26",   AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90s4433",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90s4414",  AVR_ISA_2xxx,    bfd_mach_avr2}, /* XXX -> 8515 */
+  {"at90s4434",  AVR_ISA_2xxx,    bfd_mach_avr2}, /* XXX -> 8535 */
+  {"at90s8515",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90s8535",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at90c8534",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"at86rf401",  AVR_ISA_2xxx,    bfd_mach_avr2},
+  {"attiny13",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny2313", AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny261",  AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny461",  AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny861",  AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny24",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny44",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny84",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny25",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny45",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"attiny85",   AVR_ISA_TINY2,   bfd_mach_avr2},
+  {"atmega603",  AVR_ISA_M603,    bfd_mach_avr3}, /* XXX -> m103 */
+  {"atmega103",  AVR_ISA_M103,    bfd_mach_avr3},
+  {"at43usb320", AVR_ISA_M103,    bfd_mach_avr3},
+  {"at43usb355", AVR_ISA_M603,    bfd_mach_avr3},
+  {"at76c711",   AVR_ISA_M603,    bfd_mach_avr3},
+  {"atmega48",   AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"atmega8",    AVR_ISA_M8,      bfd_mach_avr4},
+  {"atmega83",   AVR_ISA_M8,      bfd_mach_avr4}, /* XXX -> m8535 */
+  {"atmega85",   AVR_ISA_M8,      bfd_mach_avr4}, /* XXX -> m8 */
+  {"atmega88",   AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"atmega8515", AVR_ISA_M8,      bfd_mach_avr4},
+  {"atmega8535", AVR_ISA_M8,      bfd_mach_avr4},
+  {"atmega8hva", AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"at90pwm1",   AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"at90pwm2",   AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"at90pwm3",   AVR_ISA_PWMx,    bfd_mach_avr4},
+  {"atmega16",   AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega161",  AVR_ISA_M161,    bfd_mach_avr5},
+  {"atmega162",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega163",  AVR_ISA_M161,    bfd_mach_avr5},
+  {"atmega164p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega165",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega165p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega168",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega169",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega169p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega32",   AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega323",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega324p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega325",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega325p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega329",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega329p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega3250", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega3250p",AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega3290", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega3290p",AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega406",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega64",   AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega640",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega644",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega644p", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega128",  AVR_ISA_M128,    bfd_mach_avr5},
+  {"atmega1280", AVR_ISA_M128,    bfd_mach_avr5},
+  {"atmega1281", AVR_ISA_M128,    bfd_mach_avr5},
+  {"atmega645",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega649",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega6450", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega6490", AVR_ISA_M323,    bfd_mach_avr5},
+  {"atmega16hva",AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90can32" , AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90can64" , AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90can128", AVR_ISA_M128,    bfd_mach_avr5},
+  {"at90usb82",  AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90usb162", AVR_ISA_M323,    bfd_mach_avr5},
   {"at90usb646", AVR_ISA_M323,    bfd_mach_avr5},
   {"at90usb647", AVR_ISA_M323,    bfd_mach_avr5},
   {"at90usb1286",AVR_ISA_M128,    bfd_mach_avr5},
   {"at90usb1287",AVR_ISA_M128,    bfd_mach_avr5},
-  {"at94k",     AVR_ISA_94K,      bfd_mach_avr5},
+  {"at94k",      AVR_ISA_94K,     bfd_mach_avr5},
+  {"atmega2560", AVR_ISA_ALL,     bfd_mach_avr6},
+  {"atmega2561", AVR_ISA_ALL,     bfd_mach_avr6},
   {NULL, 0, 0}
 };
 
@@ -512,7 +525,7 @@ avr_offset_expression (expressionS *exp)
   if (exp->X_op == O_constant)
     {
       int x = exp->X_add_number;
-      
+
       if (x < -255 || x > 255)
 	as_warn (_("constant out of 8-bit range: %d"), x);
     }
@@ -544,6 +557,8 @@ avr_ldi_expression (expressionS *exp)
   char *tmp;
   char op[8];
   int mod;
+  int linker_stubs_should_be_generated = 0;
+
   tmp = str;
 
   str = extract_word (str, op, sizeof (op));
@@ -551,7 +566,7 @@ avr_ldi_expression (expressionS *exp)
   if (op[0])
     {
       mod_index m;
-      
+
       m.ptr = hash_find (avr_mod_hash, op);
       mod = m.index;
 
@@ -564,11 +579,14 @@ avr_ldi_expression (expressionS *exp)
 
 	  if (*str == '(')
 	    {
+	      bfd_reloc_code_real_type  reloc_to_return;
 	      int neg_p = 0;
 
 	      ++str;
 
 	      if (strncmp ("pm(", str, 3) == 0
+                  || strncmp ("gs(",str,3) == 0
+                  || strncmp ("-(gs(",str,5) == 0
 		  || strncmp ("-(pm(", str, 5) == 0)
 		{
 		  if (HAVE_PM_P (mod))
@@ -579,6 +597,9 @@ avr_ldi_expression (expressionS *exp)
 		  else
 		    as_bad (_("illegal expression"));
 
+                  if (str[0] == 'g' || str[2] == 'g')
+                    linker_stubs_should_be_generated = 1;
+
 		  if (*str == '-')
 		    {
 		      neg_p = 1;
@@ -610,7 +631,24 @@ avr_ldi_expression (expressionS *exp)
 		}
 	      while (closes--);
 
-	      return neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
+	      reloc_to_return =
+		neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
+	      if (linker_stubs_should_be_generated)
+		{
+		  switch (reloc_to_return)
+		    {
+		    case BFD_RELOC_AVR_LO8_LDI_PM:
+		      reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
+		      break;
+		    case BFD_RELOC_AVR_HI8_LDI_PM:
+		      reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
+		      break;
+
+		    default:
+		      as_warn (_("expression dangerous with linker stubs"));
+		    }
+		}
+	      return reloc_to_return;
 	    }
 	}
     }
@@ -1227,7 +1265,7 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
           return NULL;
         }
 
-      /* We are dealing with two symbols defined in the same section. 
+      /* We are dealing with two symbols defined in the same section.
          Let us fix-up them here.  */
       value += S_GET_VALUE (fixp->fx_addsy);
       value -= S_GET_VALUE (fixp->fx_subsy);
@@ -1310,7 +1348,8 @@ md_assemble (char *str)
 static int exp_mod_pm = 0;
 
 /* Parse special CONS expression: pm (expression)
-   which is used for addressing to a program memory.
+   or alternatively: gs (expression).
+   These are used for addressing program memory.
    Relocation: BFD_RELOC_AVR_16_PM.  */
 
 void
@@ -1324,10 +1363,13 @@ avr_parse_cons_expression (expressionS *exp, int nbytes)
 
   if (nbytes == 2)
     {
-      char *pm_name = "pm";
-      int len = strlen (pm_name);
+      char *pm_name1 = "pm";
+      char *pm_name2 = "gs";
+      int len = strlen (pm_name1);
+      /* len must be the same for both pm identifiers.  */
 
-      if (strncasecmp (input_line_pointer, pm_name, len) == 0)
+      if (strncasecmp (input_line_pointer, pm_name1, len) == 0
+          || strncasecmp (input_line_pointer, pm_name2, len) == 0)
 	{
 	  input_line_pointer = skip_space (input_line_pointer + len);
 
diff --git a/gas/config/tc-avr.h b/gas/config/tc-avr.h
index 61fc5941cd23..02f82896531f 100644
--- a/gas/config/tc-avr.h
+++ b/gas/config/tc-avr.h
@@ -1,5 +1,6 @@
 /* This file is tc-avr.h
-   Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2005, 2006, 2007
+   Free Software Foundation, Inc.
 
    Contributed by Denis Chertykov <denisc@overta.ru>
 
@@ -109,7 +110,7 @@ extern long md_pcrel_from_section (struct fix *, segT);
    would print `12 34 56 78'.  The default value is 4.  */
 #define LISTING_WORD_SIZE 2
 
-/* AVR port uses `$' as a logical line separator */
+/* AVR port uses `$' as a logical line separator.  */
 #define LEX_DOLLAR 0
 
 /* An `.lcomm' directive with no explicit alignment parameter will
@@ -125,16 +126,24 @@ extern long md_pcrel_from_section (struct fix *, segT);
    We will need them in case that we want to do linker relaxation.
    We could in principle keep these fixups in gas when not relaxing.
    However, there is no serious performance penilty when making the linker
-   make the fixup work.  */
-#define TC_VALIDATE_FIX(FIXP,SEG,SKIP)                     \
- if (   (FIXP->fx_r_type == BFD_RELOC_AVR_7_PCREL          \
-      || FIXP->fx_r_type == BFD_RELOC_AVR_13_PCREL         \
-      || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM       \
-      || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM       \
-      || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM       \
-      || FIXP->fx_r_type == BFD_RELOC_AVR_16_PM)           \
-     && (FIXP->fx_addsy))                                  \
-   {                                                       \
-     goto SKIP;                                            \
+   make the fixup work.  Check also that fx_addsy is not NULL, in order to make
+   sure that the fixup refers to some sort of lable.  */
+#define TC_VALIDATE_FIX(FIXP,SEG,SKIP)                       \
+  if (   (FIXP->fx_r_type == BFD_RELOC_AVR_7_PCREL           \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_13_PCREL          \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM        \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_GS        \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM        \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_GS        \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM        \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM_NEG    \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM_NEG    \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM_NEG    \
+       || FIXP->fx_r_type == BFD_RELOC_AVR_16_PM)            \
+      && (FIXP->fx_addsy))			             \
+    {                                                        \
+      goto SKIP;                                             \
    }
 
+/* This target is buggy, and sets fix size too large.  */
+#define TC_FX_SIZE_SLACK(FIX) 2
diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c
index 43d48d624ea0..aff8ed8a8fd7 100644
--- a/gas/config/tc-bfin.c
+++ b/gas/config/tc-bfin.c
@@ -1,5 +1,5 @@
 /* tc-bfin.c -- Assembler for the ADI Blackfin.
-   Copyright 2005
+   Copyright 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -21,7 +21,6 @@
 
 #include "as.h"
 #include "struc-symbol.h"
-#include "obj-elf.h"
 #include "bfin-defs.h"
 #include "obstack.h"
 #include "safe-ctype.h"
@@ -834,9 +833,14 @@ bfin_start_line_hook ()
   char *c1, *label_name;
   symbolS *line_label;
   char *c = input_line_pointer;
+  int cr_num = 0;
 
   while (ISSPACE (*c))
-    c++;
+    {
+      if (*c == '\n')
+	cr_num++;
+      c++;
+    }
 
   /* Look for Loop_Begin or Loop_End statements.  */
 
@@ -902,6 +906,12 @@ bfin_start_line_hook ()
   c1 = c;
   while (ISALPHA (*c) || ISDIGIT (*c) || *c == '_') c++;
 
+  if (input_line_pointer[-1] == '\n')
+    bump_line_counters ();
+
+  while (cr_num--)
+    bump_line_counters ();
+
   input_line_pointer = c;
   if (maybe_end)
     {
@@ -929,11 +939,7 @@ bfin_start_line_hook ()
 
 /* Special extra functions that help bfin-parse.y perform its job.  */
 
-#include <stdio.h>
 #include <assert.h>
-#include <obstack.h>
-#include <bfd.h>
-#include "bfin-defs.h"
 
 struct obstack mempool;
 
@@ -1054,7 +1060,7 @@ Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
 	}
       switch (parent_reloc)
 	{
-	  /*  Some reloctions will need to allocate extra words.  */
+	  /*  Some relocations will need to allocate extra words.  */
 	case BFD_RELOC_BFIN_16_IMM:
 	case BFD_RELOC_BFIN_16_LOW:
 	case BFD_RELOC_BFIN_16_HIGH:
@@ -1969,42 +1975,6 @@ bfin_eol_in_insn (char *line)
 }
 
 bfd_boolean
-bfin_name_is_register (char *name)
-{
-  int i;
-
-  if (*name == '[' || *name == '(')
-    return TRUE;
-
-  if ((name[0] == 'W' || name[0] == 'w') && name[1] == '[')
-    return TRUE;
-
-  if ((name[0] == 'B' || name[0] == 'b') && name[1] == '[')
-    return TRUE;
-
-  for (i=0; bfin_reg_info[i].name != 0; i++)
-   {
-     if (!strcasecmp (bfin_reg_info[i].name, name))
-       return TRUE;
-   }
-  return FALSE;
-}
-
-void
-bfin_equals (Expr_Node *sym)
-{
-  char *c;
-
-  c = input_line_pointer;
-  while (*c != '=')
-   c--;
-
-  input_line_pointer = c;
-
-  equals ((char *) sym->value.s_value, 1);
-}
-
-bfd_boolean
 bfin_start_label (char *ptr)
 {
   ptr--;
diff --git a/gas/config/tc-bfin.h b/gas/config/tc-bfin.h
index 773030cbb720..e1f95a9e57c5 100644
--- a/gas/config/tc-bfin.h
+++ b/gas/config/tc-bfin.h
@@ -52,9 +52,9 @@ extern bfd_boolean bfin_start_label PARAMS ((char *));
 #define TC_EOL_IN_INSN(PTR) (bfin_eol_in_insn(PTR) ? 1 : 0)
 extern bfd_boolean bfin_eol_in_insn PARAMS ((char *));
 
-/* The instruction is permitted to contain an = character.  */
-#define TC_EQUAL_IN_INSN(C, NAME) (bfin_name_is_register (NAME) ? 1 : 0)
-extern bfd_boolean bfin_name_is_register PARAMS ((char *));
+/* Almost all instructions of Blackfin contain an = character.  */
+#define TC_EQUAL_IN_INSN(C, NAME) 1
+
 #define NOP_OPCODE 0x0000 
 
 #define LOCAL_LABELS_FB 1
@@ -75,4 +75,7 @@ extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
 /* Values passed to md_apply_fix3 don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
+/* This target is buggy, and sets fix size too large.  */
+#define TC_FX_SIZE_SLACK(FIX) 2
+
 /* end of tc-bfin.h */
diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c
new file mode 100644
index 000000000000..2c4c6a476849
--- /dev/null
+++ b/gas/config/tc-cr16.c
@@ -0,0 +1,2444 @@
+/* tc-cr16.c -- Assembler code for the CR16 CPU core.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "dwarf2dbg.h"
+#include "opcode/cr16.h"
+#include "elf/cr16.h"
+
+
+/* Word is considered here as a 16-bit unsigned short int.  */
+#define WORD_SHIFT  16
+
+/* Register is 2-byte size.  */
+#define REG_SIZE   2
+
+/* Maximum size of a single instruction (in words).  */
+#define INSN_MAX_SIZE   3
+
+/* Maximum bits which may be set in a `mask16' operand.  */
+#define MAX_REGS_IN_MASK16  8
+
+/* Assign a number NUM, shifted by SHIFT bytes, into a location
+   pointed by index BYTE of array 'output_opcode'.  */
+#define CR16_PRINT(BYTE, NUM, SHIFT)   output_opcode[BYTE] |= (NUM << SHIFT)
+
+/* Operand errors.  */
+typedef enum
+  {
+    OP_LEGAL = 0,       /* Legal operand.  */
+    OP_OUT_OF_RANGE,    /* Operand not within permitted range.  */
+    OP_NOT_EVEN         /* Operand is Odd number, should be even.  */
+  }
+op_err;
+
+/* Opcode mnemonics hash table.  */
+static struct hash_control *cr16_inst_hash;
+/* CR16 registers hash table.  */
+static struct hash_control *reg_hash;
+/* CR16 register pair hash table.  */
+static struct hash_control *regp_hash;
+/* CR16 processor registers hash table.  */
+static struct hash_control *preg_hash;
+/* CR16 processor registers 32 bit hash table.  */
+static struct hash_control *pregp_hash;
+/* Current instruction we're assembling.  */
+const inst *instruction;
+
+
+static int code_label = 0;
+
+/* Global variables.  */
+
+/* Array to hold an instruction encoding.  */
+long output_opcode[2];
+
+/* Nonzero means a relocatable symbol.  */
+int relocatable;
+
+/* A copy of the original instruction (used in error messages).  */
+char ins_parse[MAX_INST_LEN];
+
+/* The current processed argument number.  */
+int cur_arg_num;
+
+/* Generic assembler global variables which must be defined by all targets.  */
+
+/* Characters which always start a comment.  */
+const char comment_chars[] = "#";
+
+/* Characters which start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* This array holds machine specific line separator characters.  */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums.  */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant as in 0f12.456  */
+const char FLT_CHARS[] = "f'";
+
+/* Target-specific multicharacter options, not const-declared at usage.  */
+const char *md_shortopts = "";
+struct option md_longopts[] =
+{
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+static void
+l_cons (int nbytes)
+{
+  int c;
+  expressionS exp;
+
+#ifdef md_flush_pending_output
+    md_flush_pending_output ();
+#endif
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+#ifdef TC_ADDRESS_BYTES
+  if (nbytes == 0)
+    nbytes = TC_ADDRESS_BYTES ();
+#endif
+
+#ifdef md_cons_align
+  md_cons_align (nbytes);
+#endif
+
+  c = 0;
+  do
+    {
+      unsigned int bits_available = BITS_PER_CHAR * nbytes;
+      char *hold = input_line_pointer;
+
+      expression (&exp);
+
+      if (*input_line_pointer == ':')
+	{
+	  /* Bitfields.  */
+	  long value = 0;
+
+	  for (;;)
+	    {
+	      unsigned long width;
+
+	      if (*input_line_pointer != ':')
+		{
+		  input_line_pointer = hold;
+		  break;
+		}
+	      if (exp.X_op == O_absent)
+		{
+		  as_warn (_("using a bit field width of zero"));
+		  exp.X_add_number = 0;
+		  exp.X_op = O_constant;
+		}
+
+	      if (exp.X_op != O_constant)
+		{
+		  *input_line_pointer = '\0';
+		  as_bad (_("field width \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = ':';
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      if ((width = exp.X_add_number) >
+		  (unsigned int)(BITS_PER_CHAR * nbytes))
+		{
+		  as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes));
+		  width = BITS_PER_CHAR * nbytes;
+		}                   /* Too big.  */
+
+
+	      if (width > bits_available)
+		{
+		  /* FIXME-SOMEDAY: backing up and reparsing is wasteful.  */
+		  input_line_pointer = hold;
+		  exp.X_add_number = value;
+		  break;
+		}
+
+	      /* Skip ':'.  */
+	      hold = ++input_line_pointer;
+
+	      expression (&exp);
+	      if (exp.X_op != O_constant)
+		{
+		  char cache = *input_line_pointer;
+
+		  *input_line_pointer = '\0';
+		  as_bad (_("field value \"%s\" too complex for a bitfield"), hold);
+		  *input_line_pointer = cache;
+		  demand_empty_rest_of_line ();
+		  return;
+		}
+
+	      value |= ((~(-1 << width) & exp.X_add_number)
+			<< ((BITS_PER_CHAR * nbytes) - bits_available));
+
+	      if ((bits_available -= width) == 0
+		  || is_it_end_of_statement ()
+		  || *input_line_pointer != ',')
+		break;
+
+	      hold = ++input_line_pointer;
+	      expression (&exp);
+	    }
+
+	  exp.X_add_number = value;
+	  exp.X_op = O_constant;
+	  exp.X_unsigned = 1;
+	}
+
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	code_label = 1;
+      emit_expr (&exp, (unsigned int) nbytes);
+      ++c;
+      if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
+	{
+	  input_line_pointer +=3;
+	  break;
+	}
+    }
+  while ((*input_line_pointer++ == ','));
+
+  /* Put terminator back into stream.  */
+  input_line_pointer--;
+
+  demand_empty_rest_of_line ();
+}
+
+
+/* This table describes all the machine specific pseudo-ops
+   the assembler has to support.  The fields are:
+   *** Pseudo-op name without dot.
+   *** Function to call to execute this pseudo-op.
+   *** Integer arg to pass to the function.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* In CR16 machine, align is in bytes (not a ptwo boundary).  */
+  {"align", s_align_bytes, 0},
+  {"long", l_cons,  4 },
+  {0, 0, 0}
+};
+
+/* CR16 relaxation table.  */
+const relax_typeS md_relax_table[] =
+{
+  /* bCC  */
+  {0xfa, -0x100, 2, 1},                 /*  8 */
+  {0xfffe, -0x10000, 4, 2},             /* 16 */
+  {0xfffffe, -0x1000000, 6, 0},         /* 24 */
+};
+
+/* Return the bit size for a given operand.  */
+
+static int
+get_opbits (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].bit_size;
+
+  return 0;
+}
+
+/* Return the argument type of a given operand.  */
+
+static argtype
+get_optype (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].arg_type;
+  else
+    return nullargs;
+}
+
+/* Return the flags of a given operand.  */
+
+static int
+get_opflags (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return cr16_optab[op].flags;
+
+  return 0;
+}
+
+/* Get the cc code.  */
+
+static int
+get_cc (char *cc_name)
+{
+   unsigned int i;
+
+   for (i = 0; i < cr16_num_cc; i++)
+     if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0)
+       return i;
+
+   return -1;
+}
+
+/* Get the core processor register 'reg_name'.  */
+
+static reg
+get_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor register-pair 'reg_name'.  */
+
+static reg
+get_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+  char tmp_rp[16]="\0";
+
+  /* Add '(' and ')' to the reg pair, if its not present.  */
+  if (reg_name[0] != '(') 
+    {
+      tmp_rp[0] = '(';
+      strcat (tmp_rp, reg_name);
+      strcat (tmp_rp,")");
+      reg = (const reg_entry *) hash_find (regp_hash, tmp_rp);
+    }
+  else
+    reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+
+  return nullregister;
+} 
+
+/* Get the index register 'reg_name'.  */
+
+static reg
+get_index_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if ((reg != NULL)
+      && ((reg->value.reg_val == 12) || (reg->value.reg_val == 13)))
+    return reg->value.reg_val;
+
+  return nullregister;
+}
+/* Get the core processor index register-pair 'reg_name'.  */
+
+static reg
+get_index_register_pair (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (regp_hash, reg_name);
+
+  if (reg != NULL)
+    {
+      if ((reg->value.reg_val != 1) || (reg->value.reg_val != 7)
+	  || (reg->value.reg_val != 9) || (reg->value.reg_val > 10))
+	return reg->value.reg_val;
+
+      as_bad (_("Unknown register pair - index relative mode: `%d'"), reg->value.reg_val);
+    }
+
+  return nullregister;
+}
+
+/* Get the processor register 'preg_name'.  */
+
+static preg
+get_pregister (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (preg_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+/* Get the processor register 'preg_name 32 bit'.  */
+
+static preg
+get_pregisterp (char *preg_name)
+{
+  const reg_entry *preg;
+
+  preg = (const reg_entry *) hash_find (pregp_hash, preg_name);
+
+  if (preg != NULL)
+    return preg->value.preg_val;
+
+  return nullpregister;
+}
+
+
+/* Round up a section size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT val)
+{
+  /* Round .text section to a multiple of 2.  */
+  if (seg == text_section)
+    return (val + 1) & ~1;
+  return val;
+}
+
+/* Parse an operand that is machine-specific (remove '*').  */
+
+void
+md_operand (expressionS * exp)
+{
+  char c = *input_line_pointer;
+
+  switch (c)
+    {
+    case '*':
+      input_line_pointer++;
+      expression (exp);
+      break;
+    default:
+      break;
+    }
+}
+
+/* Reset global variables before parsing a new instruction.  */
+
+static void
+reset_vars (char *op)
+{
+  cur_arg_num = relocatable = 0;
+  memset (& output_opcode, '\0', sizeof (output_opcode));
+
+  /* Save a copy of the original OP (used in error messages).  */
+  strncpy (ins_parse, op, sizeof ins_parse - 1);
+  ins_parse [sizeof ins_parse - 1] = 0;
+}
+
+/* This macro decides whether a particular reloc is an entry in a
+   switch table.  It is used when relaxing, because the linker needs
+   to know about all such entries so that it can adjust them if
+   necessary.  */
+
+#define SWITCH_TABLE(fix)                                  \
+  (   (fix)->fx_addsy != NULL                              \
+   && (fix)->fx_subsy != NULL                              \
+   && S_GET_SEGMENT ((fix)->fx_addsy) ==                   \
+      S_GET_SEGMENT ((fix)->fx_subsy)                      \
+   && S_GET_SEGMENT (fix->fx_addsy) != undefined_section   \
+   && (   (fix)->fx_r_type == BFD_RELOC_CR16_NUM8          \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32         \
+       || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a))
+
+/* See whether we need to force a relocation into the output file.
+   This is used to force out switch and PC relative relocations when
+   relaxing.  */
+
+int
+cr16_force_relocation (fixS *fix)
+{
+  /* REVISIT: Check if the "SWITCH_TABLE (fix)" should be added
+     if (generic_force_reloc (fix) || SWITCH_TABLE (fix))  */
+  if (generic_force_reloc (fix))
+    return 1;
+
+  return 0;
+}
+
+/* Record a fixup for a cons expression.  */
+
+void
+cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp)
+{
+  int rtype;
+  switch (len)
+    {
+    default: rtype = BFD_RELOC_NONE; break;
+    case 1: rtype = BFD_RELOC_CR16_NUM8 ; break;
+    case 2: rtype = BFD_RELOC_CR16_NUM16; break;
+    case 4:
+      if (code_label)
+	{
+	  rtype = BFD_RELOC_CR16_NUM32a;
+	  code_label = 0;
+	}
+      else
+	rtype = BFD_RELOC_CR16_NUM32;
+      break;
+    }
+
+  fix_new_exp (frag, offset, len, exp, 0, rtype);
+}
+
+/* Generate a relocation entry for a fixup.  */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
+{
+  arelent * reloc;
+
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+  reloc->addend = fixP->fx_offset;
+
+  if (fixP->fx_subsy != NULL)
+    {
+      if (SWITCH_TABLE (fixP))
+        {
+          /* Keep the current difference in the addend.  */
+          reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
+                           - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
+
+          switch (fixP->fx_r_type)
+            {
+	    case BFD_RELOC_CR16_NUM8:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM8;
+	      break;
+	    case BFD_RELOC_CR16_NUM16:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM16;
+	      break;
+	    case BFD_RELOC_CR16_NUM32:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32;
+	      break;
+	    case BFD_RELOC_CR16_NUM32a:
+	      fixP->fx_r_type = BFD_RELOC_CR16_NUM32a;
+	      break;
+	    default:
+	      abort ();
+	      break;
+            }
+        }
+      else
+        {
+          /* We only resolve difference expressions in the same section.  */
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+                        fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+                        segment_name (fixP->fx_addsy
+                                      ? S_GET_SEGMENT (fixP->fx_addsy)
+                                      : absolute_section),
+                        S_GET_NAME (fixP->fx_subsy),
+                        segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
+        }
+    }
+
+  assert ((int) fixP->fx_r_type > 0);
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+                    _("internal error: reloc %d (`%s') not supported by object file format"),
+                    fixP->fx_r_type,
+                    bfd_get_reloc_code_name (fixP->fx_r_type));
+      return NULL;
+    }
+  assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+  return reloc;
+}
+
+/* Prepare machine-dependent frags for relaxation.  */
+
+int
+md_estimate_size_before_relax (fragS *fragp, asection *seg)
+{
+  /* If symbol is undefined or located in a different section,
+     select the largest supported relocation.  */
+  relax_substateT subtype;
+  relax_substateT rlx_state[] = {0, 2};
+
+  for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
+    {
+      if (fragp->fr_subtype == rlx_state[subtype]
+          && (!S_IS_DEFINED (fragp->fr_symbol)
+              || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+        {
+          fragp->fr_subtype = rlx_state[subtype + 1];
+          break;
+        }
+    }
+
+  if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
+    abort ();
+
+  return md_relax_table[fragp->fr_subtype].rlx_length;
+}
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
+{
+  /* 'opcode' points to the start of the instruction, whether
+     we need to change the instruction's fixed encoding.  */
+  bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
+
+  subseg_change (sec, 0);
+
+  fix_new (fragP, fragP->fr_fix,
+           bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
+           fragP->fr_symbol, fragP->fr_offset, 1, reloc);
+  fragP->fr_var = 0;
+  fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+/* Process machine-dependent command line options.  Called once for
+   each option on the command line that the machine-independent part of
+   GAS does not understand.  */
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Machine-dependent usage-output.  */
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+  return;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  int i;
+  LITTLENUM_TYPE words[4];
+  char *t;
+
+  switch (type)
+    {
+      case 'f':
+        prec = 2;
+        break;
+
+      case 'd':
+        prec = 4;
+        break;
+
+      default:
+        *sizeP = 0;
+        return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  if (! target_big_endian)
+    {
+      for (i = prec - 1; i >= 0; i--)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+  else
+    {
+      for (i = 0; i < prec; i++)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+
+  return NULL;
+}
+
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+   enough info to complete immediately) to the data in a frag.
+   Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
+   relaxation of debug sections, this function is called only when
+   fixuping relocations of debug sections.  */
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  valueT val = * valP;
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+  fixP->fx_offset = 0;
+
+  switch (fixP->fx_r_type)
+    {
+      case BFD_RELOC_CR16_NUM8:
+        bfd_put_8 (stdoutput, (unsigned char) val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM16:
+        bfd_put_16 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      case BFD_RELOC_CR16_NUM32a:
+        bfd_put_32 (stdoutput, val, buf);
+        break;
+      default:
+        /* We shouldn't ever get here because linkrelax is nonzero.  */
+        abort ();
+        break;
+    }
+
+  fixP->fx_done = 0;
+
+  if (fixP->fx_addsy == NULL
+      && fixP->fx_pcrel == 0)
+    fixP->fx_done = 1;
+
+  if (fixP->fx_pcrel == 1
+      && fixP->fx_addsy != NULL
+      && S_GET_SEGMENT (fixP->fx_addsy) == seg)
+    fixP->fx_done = 1;
+}
+
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+static void
+initialise_reg_hash_table (struct hash_control ** hash_table,
+			   const reg_entry * register_table,
+			   const unsigned int num_entries)
+{
+  const reg_entry * reg;
+  const char *hashret;
+
+  if ((* hash_table = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  for (reg = register_table;
+       reg < (register_table + num_entries);
+       reg++)
+    {
+      hashret = hash_insert (* hash_table, reg->name, (char *) reg);
+      if (hashret)
+	as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		  reg->name, hashret);
+    }
+}
+
+/* This function is called once, at assembler startup time.  This should
+   set up all the tables, etc that the MD part of the assembler needs.  */
+
+void
+md_begin (void)
+{
+  int i = 0;
+
+  /* Set up a hash table for the instructions.  */
+  if ((cr16_inst_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  while (cr16_instruction[i].mnemonic != NULL)
+    {
+      const char *hashret;
+      const char *mnemonic = cr16_instruction[i].mnemonic;
+
+      hashret = hash_insert (cr16_inst_hash, mnemonic,
+			     (char *)(cr16_instruction + i));
+
+      if (hashret != NULL && *hashret != '\0')
+        as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic,
+                  *hashret == 0 ? _("(unknown reason)") : hashret);
+
+      /* Insert unique names into hash table.  The CR16 instruction set
+         has many identical opcode names that have different opcodes based
+         on the operands.  This hash table then provides a quick index to
+         the first opcode with a particular name in the opcode table.  */
+      do
+        {
+          ++i;
+        }
+      while (cr16_instruction[i].mnemonic != NULL
+             && streq (cr16_instruction[i].mnemonic, mnemonic));
+    }
+
+  /* Initialize reg_hash hash table.  */
+  initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS);
+  /* Initialize regp_hash hash table.  */
+  initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS);
+  /* Initialize preg_hash hash table.  */
+  initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS);
+  /* Initialize pregp_hash hash table.  */
+  initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS);
+
+  /*  Set linkrelax here to avoid fixups in most sections.  */
+  linkrelax = 1;
+}
+
+/* Process constants (immediate/absolute)
+   and labels (jump targets/Memory locations).  */
+
+static void
+process_label_constant (char *str, ins * cr16_ins)
+{
+  char *saved_input_line_pointer;
+  int symbol_with_at = 0;
+  int symbol_with_s = 0;
+  int symbol_with_m = 0;
+  int symbol_with_l = 0;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num;  /* Current argument.  */
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
+
+  expression (&cr16_ins->exp);
+
+  switch (cr16_ins->exp.X_op)
+    {
+    case O_big:
+    case O_absent:
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      str);
+      cr16_ins->exp.X_op = O_constant;
+      cr16_ins->exp.X_add_number = 0;
+      cr16_ins->exp.X_add_symbol = NULL;
+      cr16_ins->exp.X_op_symbol = NULL;
+      /* Fall through.  */
+
+    case O_constant:
+      cur_arg->X_op = O_constant;
+      cur_arg->constant = cr16_ins->exp.X_add_number;
+      break;
+
+    case O_symbol:
+    case O_subtract:
+    case O_add:
+      cur_arg->X_op = O_symbol;
+      cr16_ins->rtype = BFD_RELOC_NONE;
+      relocatable = 1;
+
+      if (strneq (input_line_pointer, "@c", 2))
+	symbol_with_at = 1;
+
+      if (strneq (input_line_pointer, "@l", 2)
+	  || strneq (input_line_pointer, ":l", 2))
+	symbol_with_l = 1;
+
+      if (strneq (input_line_pointer, "@m", 2)
+	  || strneq (input_line_pointer, ":m", 2))
+	symbol_with_m = 1;
+
+      if (strneq (input_line_pointer, "@s", 2)
+	  || strneq (input_line_pointer, ":s", 2))
+	symbol_with_s = 1;
+
+      switch (cur_arg->type)
+        {
+	case arg_cr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (cur_arg->size == 20)
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+	    }
+	  break;
+
+	case arg_crp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1:
+		switch (cur_arg->size)
+		  {
+		  case 0:
+		    cr16_ins->rtype = BFD_RELOC_CR16_REGREL0;
+		    break;
+		  case 4:
+		    if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4;
+		    else
+		      cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a;
+		    break;
+		  default: break;
+		  }
+		break;
+	      case 2:
+		cr16_ins->rtype = BFD_RELOC_CR16_REGREL16;
+		break;
+	      case 3:
+		if (cur_arg->size == 20)
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+		else
+		  cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
+		break;
+	      default:
+		break;
+	      }
+	  break;
+
+	case arg_idxr:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
+	  break;
+
+	case arg_idxrp:
+	  if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
+	    switch (instruction->size)
+	      {
+	      case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break;
+	      case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break;
+	      case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break;
+	      default: break;
+	      }
+	  break;
+
+	case arg_c:
+	  if (IS_INSN_MNEMONIC ("bal"))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	  else if (IS_INSN_TYPE (BRANCH_INS))
+	    {
+	      if (symbol_with_s)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP8;
+	      else if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP16;
+	      else
+		cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
+	    }
+	  else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS)
+		   || IS_INSN_TYPE (CSTBIT_INS))
+	    {
+	      if (symbol_with_s)
+		as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str);
+	      if (symbol_with_m)
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS20;
+	      else /* Default to (symbol_with_l) */
+		cr16_ins->rtype = BFD_RELOC_CR16_ABS24;
+	    }
+	  else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
+	    cr16_ins->rtype = BFD_RELOC_CR16_DISP4;
+          break;
+
+        case arg_ic:
+          if (IS_INSN_TYPE (ARITH_INS))
+            {
+              if (symbol_with_s)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM4;
+              else if (symbol_with_m)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM20;
+              else if (symbol_with_at)
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32a;
+              else /* Default to (symbol_with_l) */
+                cr16_ins->rtype = BFD_RELOC_CR16_IMM32;
+            }
+          else if (IS_INSN_TYPE (ARITH_BYTE_INS))
+	    {
+	      cr16_ins->rtype = BFD_RELOC_CR16_IMM16;
+	    }
+          break;
+        default:
+          break;
+	}
+      break;
+
+    default:
+      cur_arg->X_op = cr16_ins->exp.X_op;
+      break;
+    }
+
+  input_line_pointer = saved_input_line_pointer;
+  return;
+}
+
+/* Retrieve the opcode image of a given register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int is_procreg = 0; /* Nonzero means argument should be processor reg.  */
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regtab + r;
+  else /* Register not found.  */
+    {
+      as_bad (_("Unknown register: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register is illegal.  */
+#define IMAGE_ERR \
+  as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                            \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_R_REGTYPE:
+      if (! is_procreg)
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CR16_P_REGTYPE:
+      return reg->image;
+      break;
+
+    default:
+      IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Parsing different types of operands
+   -> constants             Immediate/Absolute/Relative numbers
+   -> Labels                Relocatable symbols
+   -> (reg pair base)       Register pair base
+   -> (rbase)               Register base
+   -> disp(rbase)           Register relative
+   -> [rinx]disp(reg pair)  Register index with reg pair mode
+   -> disp(rbase,ridx,scl)  Register index mode.  */
+
+static void
+set_operand (char *operand, ins * cr16_ins)
+{
+  char *operandS; /* Pointer to start of sub-opearand.  */
+  char *operandE; /* Pointer to end of sub-opearand.  */
+
+  argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument.  */
+
+  /* Initialize pointers.  */
+  operandS = operandE = operand;
+
+  switch (cur_arg->type)
+    {
+    case arg_ic:    /* Case $0x18.  */
+      operandS++;
+    case arg_c:     /* Case 0x18.  */
+      /* Set constant.  */
+      process_label_constant (operandS, cr16_ins);
+
+      if (cur_arg->type != arg_ic)
+        cur_arg->type = arg_c;
+      break;
+
+    case arg_icr:   /* Case $0x18(r1).  */
+      operandS++;
+    case arg_cr:    /* Case 0x18(r1).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+    case arg_rbase: /* Case (r1) or (r1,r0).  */
+      operandS++;
+      /* Set register base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->r = get_register (operandS)) == nullregister)
+         as_bad (_("Illegal register `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+
+      /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
+      if ((cur_arg->type != arg_rbase)
+	  && ((getreg_image (cur_arg->r) == 12)
+	      || (getreg_image (cur_arg->r) == 13)
+	      || (getreg_image (cur_arg->r) == 14)
+	      || (getreg_image (cur_arg->r) == 15)))
+         {
+           cur_arg->type = arg_crp;
+           cur_arg->rp = cur_arg->r;
+         }
+      break;
+
+    case arg_crp:    /* Case 0x18(r1,r0).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+        operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, cr16_ins);
+      operandS = operandE;
+      operandS++;
+      /* Set register pair base.  */
+      while (*operandE != ')')
+        operandE++;
+      *operandE = '\0';
+      if ((cur_arg->rp = get_register_pair (operandS)) == nullregister)
+         as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+              operandS, ins_parse);
+      break;
+
+    case arg_idxr:
+      /* Set register pair base.  */
+      if ((strchr (operandS,'(') != NULL))
+        {
+         while ((*operandE != '(') && (! ISSPACE (*operandE)))
+           operandE++;
+         if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister)
+              as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
+                            operandS, ins_parse);
+         *operandE++ = '\0';
+         cur_arg->type = arg_idxrp;
+        }
+      else
+	cur_arg->rp = -1;
+
+       operandE = operandS;
+      /* Set displacement constant.  */
+      while (*operandE != ']')
+        operandE++;
+      process_label_constant (++operandE, cr16_ins);
+      *operandE++ = '\0';
+      operandE = operandS;
+
+      /* Set index register .  */
+      operandS = strchr (operandE,'[');
+      if (operandS != NULL)
+        { /* Eliminate '[', detach from rest of operand.  */
+          *operandS++ = '\0';
+
+          operandE = strchr (operandS, ']');
+
+          if (operandE == NULL)
+            as_bad (_("unmatched '['"));
+          else
+            { /* Eliminate ']' and make sure it was the last thing
+                 in the string.  */
+              *operandE = '\0';
+              if (*(operandE + 1) != '\0')
+                as_bad (_("garbage after index spec ignored"));
+            }
+        }
+
+      if ((cur_arg->i_r = get_index_register (operandS)) == nullregister)
+        as_bad (_("Illegal register `%s' in Instruction `%s'"),
+                operandS, ins_parse);
+      *operandE = '\0';
+      *operandS = '\0';
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Parse a single operand.
+   operand - Current operand to parse.
+   cr16_ins - Current assembled instruction.  */
+
+static void
+parse_operand (char *operand, ins * cr16_ins)
+{
+  int ret_val;
+  argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument.  */
+
+  /* Initialize the type to NULL before parsing.  */
+  cur_arg->type = nullargs;
+
+  /* Check whether this is a condition code .  */
+  if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1))
+    {
+      cur_arg->type = arg_cc;
+      cur_arg->cc = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a general processor register.  */
+  if ((ret_val = get_register (operand)) != nullregister)
+    {
+      cur_arg->type = arg_r;
+      cur_arg->r = ret_val;
+      cur_arg->X_op = 0;
+      return;
+    }
+
+  /* Check whether this is a general processor register pair.  */
+  if ((operand[0] == '(')
+      && ((ret_val = get_register_pair (operand)) != nullregister))
+    {
+      cur_arg->type = arg_rp;
+      cur_arg->rp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether the operand is a processor register.
+     For "lprd" and "sprd" instruction, only 32 bit
+     processor registers used.  */
+  if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
+      && ((ret_val = get_pregister (operand)) != nullpregister))
+    {
+      cur_arg->type = arg_pr;
+      cur_arg->pr = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a processor register - 32 bit.  */
+  if ((ret_val = get_pregisterp (operand)) != nullpregister)
+    {
+      cur_arg->type = arg_prp;
+      cur_arg->prp = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Deal with special characters.  */
+  switch (operand[0])
+    {
+    case '$':
+      if (strchr (operand, '(') != NULL)
+	cur_arg->type = arg_icr;
+      else
+	cur_arg->type = arg_ic;
+      goto set_params;
+      break;
+
+    case '(':
+      cur_arg->type = arg_rbase;
+      goto set_params;
+      break;
+
+    case '[':
+      cur_arg->type = arg_idxr;
+      goto set_params;
+      break;
+
+    default:
+      break;
+    }
+
+  if (strchr (operand, '(') != NULL)
+    {
+      if (strchr (operand, ',') != NULL
+          && (strchr (operand, ',') > strchr (operand, '(')))
+        cur_arg->type = arg_crp;
+      else
+        cur_arg->type = arg_cr;
+    }
+  else
+    cur_arg->type = arg_c;
+
+/* Parse an operand according to its type.  */
+ set_params:
+  cur_arg->constant = 0;
+  set_operand (operand, cr16_ins);
+}
+
+/* Parse the various operands. Each operand is then analyzed to fillup
+   the fields in the cr16_ins data structure.  */
+
+static void
+parse_operands (ins * cr16_ins, char *operands)
+{
+  char *operandS;            /* Operands string.  */
+  char *operandH, *operandT; /* Single operand head/tail pointers.  */
+  int allocated = 0;         /* Indicates a new operands string was allocated.*/
+  char *operand[MAX_OPERANDS];/* Separating the operands.  */
+  int op_num = 0;             /* Current operand number we are parsing.  */
+  int bracket_flag = 0;       /* Indicates a bracket '(' was found.  */
+  int sq_bracket_flag = 0;    /* Indicates a square bracket '[' was found.  */
+
+  /* Preprocess the list of registers, if necessary.  */
+  operandS = operandH = operandT = operands;
+
+  while (*operandT != '\0')
+    {
+      if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
+        {
+          *operandT++ = '\0';
+          operand[op_num++] = strdup (operandH);
+          operandH = operandT;
+          continue;
+        }
+
+      if (*operandT == ' ')
+        as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
+
+      if (*operandT == '(')
+        bracket_flag = 1;
+      else if (*operandT == '[')
+        sq_bracket_flag = 1;
+
+      if (*operandT == ')')
+        {
+          if (bracket_flag)
+            bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+      else if (*operandT == ']')
+        {
+          if (sq_bracket_flag)
+            sq_bracket_flag = 0;
+          else
+            as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+        }
+
+      if (bracket_flag == 1 && *operandT == ')')
+        bracket_flag = 0;
+      else if (sq_bracket_flag == 1 && *operandT == ']')
+        sq_bracket_flag = 0;
+
+      operandT++;
+    }
+
+  /* Adding the last operand.  */
+  operand[op_num++] = strdup (operandH);
+  cr16_ins->nargs = op_num;
+
+  /* Verifying correct syntax of operands (all brackets should be closed).  */
+  if (bracket_flag || sq_bracket_flag)
+    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+
+  /* Now we parse each operand separately.  */
+  for (op_num = 0; op_num < cr16_ins->nargs; op_num++)
+    {
+      cur_arg_num = op_num;
+      parse_operand (operand[op_num], cr16_ins);
+      free (operand[op_num]);
+    }
+
+  if (allocated)
+    free (operandS);
+}
+
+/* Get the trap index in dispatch table, given its name.
+   This routine is used by assembling the 'excp' instruction.  */
+
+static int
+gettrap (char *s)
+{
+  const trap_entry *trap;
+
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (strcasecmp (trap->name, s) == 0)
+      return trap->entry;
+
+  /* To make compatable with CR16 4.1 tools, the below 3-lines of
+   * code added. Refer: Development Tracker item #123 */
+  for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
+    if (trap->entry  == (unsigned int) atoi (s))
+      return trap->entry;
+
+  as_bad (_("Unknown exception: `%s'"), s);
+  return 0;
+}
+
+/* Top level module where instruction parsing starts.
+   cr16_ins - data structure holds some information.
+   operands - holds the operands part of the whole instruction.  */
+
+static void
+parse_insn (ins *insn, char *operands)
+{
+  int i;
+
+  /* Handle instructions with no operands.  */
+  for (i = 0; cr16_no_op_insn[i] != NULL; i++)
+  {
+    if (streq (cr16_no_op_insn[i], instruction->mnemonic))
+    {
+      insn->nargs = 0;
+      return;
+    }
+  }
+
+  /* Handle 'excp' instructions.  */
+  if (IS_INSN_MNEMONIC ("excp"))
+    {
+      insn->nargs = 1;
+      insn->arg[0].type = arg_ic;
+      insn->arg[0].constant = gettrap (operands);
+      insn->arg[0].X_op = O_constant;
+      return;
+    }
+
+  if (operands != NULL)
+    parse_operands (insn, operands);
+}
+
+/* bCC instruction requires special handling.  */
+static char *
+get_b_cc (char * op)
+{
+  unsigned int i;
+  char op1[5];
+
+  for (i = 1; i < strlen (op); i++)
+     op1[i-1] = op[i];
+
+  op1[i-1] = '\0';
+
+  for (i = 0; i < cr16_num_cc ; i++)
+    if (streq (op1, cr16_b_cond_tab[i]))
+      return (char *) cr16_b_cond_tab[i];
+
+   return NULL;
+}
+
+/* bCC instruction requires special handling.  */
+static int
+is_bcc_insn (char * op)
+{
+  if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b")
+	|| streq (op, "beq0w") || streq (op, "bnq0w")))
+    if ((op[0] == 'b') && (get_b_cc (op) != NULL))
+      return 1;
+  return 0;
+}
+
+/* Cinv instruction requires special handling.  */
+
+static int
+check_cinv_options (char * operand)
+{
+  char *p = operand;
+  int i_used = 0, u_used = 0, d_used = 0;
+
+  while (*++p != ']')
+    {
+      if (*p == ',' || *p == ' ')
+        continue;
+
+      else if (*p == 'i')
+        i_used = 1;
+      else if (*p == 'u')
+        u_used = 1;
+      else if (*p == 'd')
+        d_used = 1;
+      else
+        as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                 \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_RP_REGTYPE:
+      return reg->image;
+    default:
+      RPAIR_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given index register pair.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getidxregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = cr16_regptab + r;
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register pair: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define IDX_RPAIR_IMAGE_ERR \
+  as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                       \
+
+  if (reg->type == CR16_RP_REGTYPE)
+    {
+      switch (reg->image)
+	{
+	case 0:  return 0; break;
+	case 2:  return 1; break;
+	case 4:  return 2; break;
+	case 6:  return 3; break;
+	case 8:  return 4; break;
+	case 10: return 5; break;
+	case 3:  return 6; break;
+	case 5:  return 7; break;
+	default:
+	  break;
+	}
+    }
+
+  IDX_RPAIR_IMAGE_ERR;
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    reg = &cr16_pregtab[r - MAX_REG];
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREG_IMAGE_ERR \
+  as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
+            reg_name, ins_parse);                                      \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREG_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Retrieve the opcode image of a given processort register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+static int
+getprocregp_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int pregptab_disp = 0;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_PREG)
+    {
+      r = r - MAX_REG;
+      switch (r)
+        {
+	case 4: pregptab_disp = 1;  break;
+	case 6: pregptab_disp = 2;  break;
+	case 8:
+	case 9:
+	case 10:
+	  pregptab_disp = 3;  break;
+	case 12:
+	  pregptab_disp = 4;  break;
+	case 14:
+	  pregptab_disp = 5;  break;
+	default: break;
+        }
+      reg = &cr16_pregptab[r - pregptab_disp];
+    }
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown processor register (32 bit) : `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register  pair is illegal.  */
+#define PROCREGP_IMAGE_ERR \
+  as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\
+            reg_name, ins_parse);                                              \
+  break;
+
+  switch (reg->type)
+    {
+    case CR16_P_REGTYPE:
+      return reg->image;
+    default:
+      PROCREGP_IMAGE_ERR;
+    }
+
+  return 0;
+}
+
+/* Routine used to represent integer X using NBITS bits.  */
+
+static long
+getconstant (long x, int nbits)
+{
+  /* The following expression avoids overflow if
+     'nbits' is the number of bits in 'bfd_vma'.  */
+  return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
+}
+
+/* Print a constant value to 'output_opcode':
+   ARG holds the operand's type and value.
+   SHIFT represents the location of the operand to be print into.
+   NBITS determines the size (in bits) of the constant.  */
+
+static void
+print_constant (int nbits, int shift, argument *arg)
+{
+  unsigned long mask = 0;
+
+  long constant = getconstant (arg->constant, nbits);
+
+  switch (nbits)
+    {
+    case 32:
+    case 28:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | x X x X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
+      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+      break;
+
+    case 21:
+      if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20;
+    case 24:
+    case 22:
+    case 20:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+	 0        1         2          3
+	 +---------+---------+---------+---------+
+	 |         | X X X X | - X - X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	{
+	  if (arg->type == arg_idxrp)
+	    {
+	      CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	  else
+	    {
+	      CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0);
+	      CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+	    }
+	}
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 14:
+      if (arg->type == arg_idxrp)
+	{
+	  if (instruction->size == 2)
+	    {
+	      CR16_PRINT (0, ((constant)&0xf), shift);         // 0-3 bits
+	      CR16_PRINT (0, ((constant>>4)&0x3), (shift+20)); // 4-5 bits
+	      CR16_PRINT (0, ((constant>>6)&0x3), (shift+14)); // 6-7 bits
+	      CR16_PRINT (0, ((constant>>8)&0x3f), (shift+8)); // 8-13 bits
+	    }
+	  else
+	    CR16_PRINT (0, constant, shift);
+	}
+      break;
+
+    case 16:
+    case 12:
+      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+	 always filling the upper part of output_opcode[1]. If we mistakenly
+	 write it to output_opcode[0], the constant prefix (that is, 'match')
+	 will be overriden.
+	 0        1         2         3
+	 +---------+---------+---------+---------+
+	 | 'match' |         | X X X X |         |
+	 +---------+---------+---------+---------+
+	 output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	CR16_PRINT (1, constant, WORD_SHIFT);
+      else
+	CR16_PRINT (0, constant, shift);
+      break;
+
+    case 8:
+      CR16_PRINT (0, ((constant/2)&0xf), shift);
+      CR16_PRINT (0, ((constant/2)>>4),  (shift+8));
+      break;
+
+    default:
+      CR16_PRINT (0, constant,  shift);
+      break;
+    }
+}
+
+/* Print an operand to 'output_opcode', which later on will be
+   printed to the object file:
+   ARG holds the operand's type, size and value.
+   SHIFT represents the printing location of operand.
+   NBITS determines the size (in bits) of a constant operand.  */
+
+static void
+print_operand (int nbits, int shift, argument *arg)
+{
+  switch (arg->type)
+    {
+    case arg_cc:
+      CR16_PRINT (0, arg->cc, shift);
+      break;
+
+    case arg_r:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_rp:
+      CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    case arg_pr:
+      CR16_PRINT (0, getprocreg_image (arg->pr), shift);
+      break;
+
+    case arg_prp:
+      CR16_PRINT (0, getprocregp_image (arg->prp), shift);
+      break;
+
+    case arg_idxrp:
+      /*    16      12      8    6      0
+            +-----------------------------+
+            | r_index | disp  | rp_base   |
+            +-----------------------------+          */
+
+      if (instruction->size == 3)
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 0);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 3);
+	  else
+	    CR16_PRINT (0, 1, 3);
+	}
+      else
+	{
+	  CR16_PRINT (0, getidxregp_image (arg->rp), 16);
+	  if (getreg_image (arg->i_r) == 12)
+	    CR16_PRINT (0, 0, 19);
+	  else
+	    CR16_PRINT (0, 1, 19);
+	}
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_idxr:
+      if (getreg_image (arg->i_r) == 12)
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 0, 23);
+	else CR16_PRINT (0, 0, 24);
+      else
+	if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb")
+	    || IS_INSN_MNEMONIC ("tbitb"))
+	  CR16_PRINT (0, 1, 23);
+	else CR16_PRINT (0, 1, 24);
+
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_ic:
+    case arg_c:
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_rbase:
+      CR16_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_cr:
+      print_constant (nbits, shift , arg);
+      /* Add the register argument to the output_opcode.  */
+      CR16_PRINT (0, getreg_image (arg->r), (shift+16));
+      break;
+
+    case arg_crp:
+      print_constant (nbits, shift , arg);
+      if (instruction->size > 1)
+	CR16_PRINT (0, getregp_image (arg->rp), (shift + 16));
+      else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS)))
+	{
+	  if (instruction->size == 2)
+	    CR16_PRINT (0, getregp_image (arg->rp), (shift - 8));
+	  else if (instruction->size == 1)
+	    CR16_PRINT (0, getregp_image (arg->rp), 16);
+	}
+      else
+	CR16_PRINT (0, getregp_image (arg->rp), shift);
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Retrieve the number of operands for the current assembled instruction.  */
+
+static int
+get_number_of_operands (void)
+{
+  int i;
+
+  for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+    ;
+  return i;
+}
+
+/* Verify that the number NUM can be represented in BITS bits (that is,
+   within its permitted range), based on the instruction's FLAGS.
+   If UPDATE is nonzero, update the value of NUM if necessary.
+   Return OP_LEGAL upon success, actual error type upon failure.  */
+
+static op_err
+check_range (long *num, int bits, int unsigned flags, int update)
+{
+  long min, max;
+  int retval = OP_LEGAL;
+  long value = *num;
+
+  if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
+
+  /* For hosts witah longs bigger than 32-bits make sure that the top
+     bits of a 32-bit negative value read in by the parser are set,
+     so that the correct comparisons are made.  */
+  if (value & 0x80000000)
+    value |= (-1L << 31);
+
+
+  /* Verify operand value is even.  */
+  if (flags & OP_EVEN)
+    {
+      if (value % 2)
+        return OP_NOT_EVEN;
+    }
+
+  if (flags & OP_DEC)
+    {
+      value -= 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_SHIFT)
+    {
+      value >>= 1;
+      if (update)
+        *num = value;
+    }
+  else if (flags & OP_SHIFT_DEC)
+    {
+      value = (value >> 1) - 1;
+      if (update)
+        *num = value;
+    }
+
+  if (flags & OP_ABS20)
+    {
+      if (value > 0xEFFFF)
+        return OP_OUT_OF_RANGE;
+    }
+
+  if (flags & OP_ESC)
+    {
+      if (value == 0xB || value == 0x9)
+        return OP_OUT_OF_RANGE;
+      else if (value == -1)
+	{
+	  if (update)
+	    *num = 9;
+	  return retval;
+	}
+    }
+
+  if (flags & OP_ESC1)
+    {
+      if (value > 13)
+        return OP_OUT_OF_RANGE;
+    }
+
+   if (flags & OP_SIGNED)
+     {
+       max = (1 << (bits - 1)) - 1;
+       min = - (1 << (bits - 1));
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_UNSIGNED)
+     {
+       max = ((((1 << (bits - 1)) - 1) << 1) | 1);
+       min = 0;
+       if (((unsigned long) value > (unsigned long) max)
+            || ((unsigned long) value < (unsigned long) min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   else if (flags & OP_NEG)
+     {
+       max = - 1;
+       min = - ((1 << (bits - 1))-1);
+       if ((value > max) || (value < min))
+         retval = OP_OUT_OF_RANGE;
+     }
+   return retval;
+}
+
+/* Bunch of error checkings.
+   The checks are made after a matching instruction was found.  */
+
+static void
+warn_if_needed (ins *insn)
+{
+  /* If the post-increment address mode is used and the load/store
+     source register is the same as rbase, the result of the
+     instruction is undefined.  */
+  if (IS_INSN_TYPE (LD_STOR_INS_INC))
+    {
+      /* Enough to verify that one of the arguments is a simple reg.  */
+      if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
+        if (insn->arg[0].r == insn->arg[1].r)
+          as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r);
+    }
+
+  if (IS_INSN_MNEMONIC ("pop")
+      || IS_INSN_MNEMONIC ("push")
+      || IS_INSN_MNEMONIC ("popret"))
+    {
+      unsigned int count = insn->arg[0].constant, reg_val;
+
+      /* Check if count operand caused to save/retrive the RA twice
+	 to generate warning message.  */
+     if (insn->nargs > 2)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         if (   ((reg_val == 9) &&  (count > 7))
+	     || ((reg_val == 10) && (count > 6))
+	     || ((reg_val == 11) && (count > 5))
+	     || ((reg_val == 12) && (count > 4))
+	     || ((reg_val == 13) && (count > 2))
+	     || ((reg_val == 14) && (count > 0)))
+           as_warn (_("RA register is saved twice."));
+
+         /* Check if the third operand is "RA" or "ra" */
+         if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA)))
+           as_bad (_("`%s' Illegal use of registers."), ins_parse);
+       }
+
+      if (insn->nargs > 1)
+       {
+         reg_val = getreg_image (insn->arg[1].r);
+
+         /* If register is a register pair ie r12/r13/r14 in operand1, then
+            the count constant should be validated.  */
+         if (((reg_val == 11) && (count > 7))
+	     || ((reg_val == 12) && (count > 6))
+	     || ((reg_val == 13) && (count > 4))
+	     || ((reg_val == 14) && (count > 2))
+	     || ((reg_val == 15) && (count > 0)))
+           as_bad (_("`%s' Illegal count-register combination."), ins_parse);
+       }
+     else
+       {
+         /* Check if the operand is "RA" or "ra" */
+         if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA)))
+           as_bad (_("`%s' Illegal use of register."), ins_parse);
+       }
+    }
+
+  /* Some instruction assume the stack pointer as rptr operand.
+     Issue an error when the register to be loaded is also SP.  */
+  if (instruction->flags & NO_SP)
+    {
+      if (getreg_image (insn->arg[1].r) == getreg_image (sp))
+        as_bad (_("`%s' has undefined result"), ins_parse);
+    }
+
+  /* If the rptr register is specified as one of the registers to be loaded,
+     the final contents of rptr are undefined. Thus, we issue an error.  */
+  if (instruction->flags & NO_RPTR)
+    {
+      if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
+        as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
+                  getreg_image (insn->arg[0].r));
+    }
+}
+
+/* In some cases, we need to adjust the instruction pointer although a
+   match was already found. Here, we gather all these cases.
+   Returns 1 if instruction pointer was adjusted, otherwise 0.  */
+
+static int
+adjust_if_needed (ins *insn ATTRIBUTE_UNUSED)
+{
+  int ret_value = 0;
+
+  if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS)))
+    {
+      if ((instruction->operands[0].op_type == abs24)
+           && ((insn->arg[0].constant) > 0xF00000))
+        {
+          insn->arg[0].constant &= 0xFFFFF;
+          instruction--;
+          ret_value = 1;
+        }
+    }
+
+  return ret_value;
+}
+
+/* Assemble a single instruction:
+   INSN is already parsed (that is, all operand values and types are set).
+   For instruction to be assembled, we need to find an appropriate template in
+   the instruction table, meeting the following conditions:
+    1: Has the same number of operands.
+    2: Has the same operand types.
+    3: Each operand size is sufficient to represent the instruction's values.
+   Returns 1 upon success, 0 upon failure.  */
+
+static int
+assemble_insn (char *mnemonic, ins *insn)
+{
+  /* Type of each operand in the current template.  */
+  argtype cur_type[MAX_OPERANDS];
+  /* Size (in bits) of each operand in the current template.  */
+  unsigned int cur_size[MAX_OPERANDS];
+  /* Flags of each operand in the current template.  */
+  unsigned int cur_flags[MAX_OPERANDS];
+  /* Instruction type to match.  */
+  unsigned int ins_type;
+  /* Boolean flag to mark whether a match was found.  */
+  int match = 0;
+  int i;
+  /* Nonzero if an instruction with same number of operands was found.  */
+  int found_same_number_of_operands = 0;
+  /* Nonzero if an instruction with same argument types was found.  */
+  int found_same_argument_types = 0;
+  /* Nonzero if a constant was found within the required range.  */
+  int found_const_within_range  = 0;
+  /* Argument number of an operand with invalid type.  */
+  int invalid_optype = -1;
+  /* Argument number of an operand with invalid constant value.  */
+  int invalid_const  = -1;
+  /* Operand error (used for issuing various constant error messages).  */
+  op_err op_error, const_err = OP_LEGAL;
+
+/* Retrieve data (based on FUNC) for each operand of a given instruction.  */
+#define GET_CURRENT_DATA(FUNC, ARRAY)                           \
+  for (i = 0; i < insn->nargs; i++)                             \
+    ARRAY[i] = FUNC (instruction->operands[i].op_type)
+
+#define GET_CURRENT_TYPE    GET_CURRENT_DATA (get_optype, cur_type)
+#define GET_CURRENT_SIZE    GET_CURRENT_DATA (get_opbits, cur_size)
+#define GET_CURRENT_FLAGS   GET_CURRENT_DATA (get_opflags, cur_flags)
+
+  /* Instruction has no operands -> only copy the constant opcode.   */
+  if (insn->nargs == 0)
+    {
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+      return 1;
+    }
+
+  /* In some case, same mnemonic can appear with different instruction types.
+     For example, 'storb' is supported with 3 different types :
+     LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
+     We assume that when reaching this point, the instruction type was
+     pre-determined. We need to make sure that the type stays the same
+     during a search for matching instruction.  */
+  ins_type = CR16_INS_TYPE (instruction->flags);
+
+  while (/* Check that match is still not found.  */
+         match != 1
+         /* Check we didn't get to end of table.  */
+         && instruction->mnemonic != NULL
+         /* Check that the actual mnemonic is still available.  */
+         && IS_INSN_MNEMONIC (mnemonic)
+         /* Check that the instruction type wasn't changed.  */
+         && IS_INSN_TYPE (ins_type))
+    {
+      /* Check whether number of arguments is legal.  */
+      if (get_number_of_operands () != insn->nargs)
+        goto next_insn;
+      found_same_number_of_operands = 1;
+
+      /* Initialize arrays with data of each operand in current template.  */
+      GET_CURRENT_TYPE;
+      GET_CURRENT_SIZE;
+      GET_CURRENT_FLAGS;
+
+      /* Check for type compatibility.  */
+      for (i = 0; i < insn->nargs; i++)
+        {
+          if (cur_type[i] != insn->arg[i].type)
+            {
+              if (invalid_optype == -1)
+                invalid_optype = i + 1;
+              goto next_insn;
+            }
+        }
+      found_same_argument_types = 1;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          /* If 'bal' instruction size is '2' and reg operand is not 'ra'
+             then goto next instruction.  */
+          if (IS_INSN_MNEMONIC ("bal") && (i == 0)
+	      && (instruction->size == 2) && (insn->arg[i].rp != 14))
+            goto next_insn;
+
+          /* If 'storb' instruction with 'sp' reg and 16-bit disp of
+           * reg-pair, leads to undifined trap, so this should use
+           * 20-bit disp of reg-pair.  */
+          if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
+	      && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
+            goto next_insn;
+
+          /* Only check range - don't update the constant's value, since the
+             current instruction may not be the last we try to match.
+             The constant's value will be updated later, right before printing
+             it to the object file.  */
+          if ((insn->arg[i].X_op == O_constant)
+              && (op_error = check_range (&insn->arg[i].constant, cur_size[i],
+                                          cur_flags[i], 0)))
+            {
+              if (invalid_const == -1)
+                {
+                  invalid_const = i + 1;
+                  const_err = op_error;
+                }
+              goto next_insn;
+            }
+          /* For symbols, we make sure the relocation size (which was already
+             determined) is sufficient.  */
+          else if ((insn->arg[i].X_op == O_symbol)
+                   && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
+		       > cur_size[i]))
+                  goto next_insn;
+        }
+      found_const_within_range = 1;
+
+      /* If we got till here -> Full match is found.  */
+      match = 1;
+      break;
+
+/* Try again with next instruction.  */
+next_insn:
+      instruction++;
+    }
+
+  if (!match)
+    {
+      /* We haven't found a match - instruction can't be assembled.  */
+      if (!found_same_number_of_operands)
+        as_bad (_("Incorrect number of operands"));
+      else if (!found_same_argument_types)
+        as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
+      else if (!found_const_within_range)
+        {
+          switch (const_err)
+            {
+	    case OP_OUT_OF_RANGE:
+	      as_bad (_("Operand out of range (arg %d)"), invalid_const);
+	      break;
+	    case OP_NOT_EVEN:
+	      as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
+	      break;
+	    default:
+	      as_bad (_("Illegal operand (arg %d)"), invalid_const);
+	      break;
+            }
+        }
+
+       return 0;
+    }
+  else
+    /* Full match - print the encoding to output file.  */
+    {
+      /* Make further checkings (such that couldn't be made earlier).
+         Warn the user if necessary.  */
+      warn_if_needed (insn);
+
+      /* Check whether we need to adjust the instruction pointer.  */
+      if (adjust_if_needed (insn))
+        /* If instruction pointer was adjusted, we need to update
+           the size of the current template operands.  */
+        GET_CURRENT_SIZE;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+          int j = instruction->flags & REVERSE_MATCH ?
+                  i == 0 ? 1 :
+                  i == 1 ? 0 : i :
+                  i;
+
+          /* This time, update constant value before printing it.  */
+            if ((insn->arg[j].X_op == O_constant)
+               && (check_range (&insn->arg[j].constant, cur_size[j],
+                                cur_flags[j], 1) != OP_LEGAL))
+              as_fatal (_("Illegal operand (arg %d)"), j+1);
+        }
+
+      /* First, copy the instruction's opcode.  */
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+         /* For BAL (ra),disp17 instuction only. And also set the
+            DISP24a relocation type.  */
+         if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
+           {
+             insn->rtype = BFD_RELOC_CR16_DISP24a;
+             continue;
+           }
+          cur_arg_num = i;
+          print_operand (cur_size[i], instruction->operands[i].shift,
+                         &insn->arg[i]);
+        }
+    }
+
+  return 1;
+}
+
+/* Print the instruction.
+   Handle also cases where the instruction is relaxable/relocatable.  */
+
+static void
+print_insn (ins *insn)
+{
+  unsigned int i, j, insn_size;
+  char *this_frag;
+  unsigned short words[4];
+  int addr_mod;
+
+  /* Arrange the insn encodings in a WORD size array.  */
+  for (i = 0, j = 0; i < 2; i++)
+    {
+      words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
+      words[j++] = output_opcode[i] & 0xFFFF;
+    }
+
+    insn_size = instruction->size;
+    this_frag = frag_more (insn_size * 2);
+
+    /* Handle relocation.  */
+    if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
+      {
+         reloc_howto_type *reloc_howto;
+         int size;
+
+         reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
+
+         if (!reloc_howto)
+           abort ();
+
+         size = bfd_get_reloc_size (reloc_howto);
+
+         if (size < 1 || size > 4)
+           abort ();
+
+         fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                      size, &insn->exp, reloc_howto->pc_relative,
+                      insn->rtype);
+      }
+
+  /* Verify a 2-byte code alignment.  */
+  addr_mod = frag_now_fix () & 1;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 2"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
+  /* Write the instruction encoding to frag.  */
+  for (i = 0; i < insn_size; i++)
+    {
+      md_number_to_chars (this_frag, (valueT) words[i], 2);
+      this_frag += 2;
+    }
+}
+
+/* This is the guts of the machine-dependent assembler.  OP points to a
+   machine dependent instruction.  This function is supposed to emit
+   the frags/bytes it assembles to.  */
+
+void
+md_assemble (char *op)
+{
+  ins cr16_ins;
+  char *param, param1[32];
+  char c;
+
+  /* Reset global variables for a new instruction.  */
+  reset_vars (op);
+
+  /* Strip the mnemonic.  */
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param++ = '\0';
+
+  /* bCC instuctions and adjust the mnemonic by adding extra white spaces.  */
+  if (is_bcc_insn (op))
+    {
+      strcpy (param1, get_b_cc (op));
+      op = "b";
+      strcat (param1,",");
+      strcat (param1, param);
+      param = (char *) &param1;
+    }
+
+  /* Checking the cinv options and adjust the mnemonic by removing the
+     extra white spaces.  */
+  if (streq ("cinv", op))
+    {
+     /* Validate the cinv options.  */
+      check_cinv_options (param);
+      strcat (op, param);
+    }
+
+  /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
+     lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
+     as CR16 core doesn't support lsh[b/w] right shift operaions.  */
+  if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
+      && (param [0] == '$'))
+    {
+      strcpy (param1, param);
+      /* Find the instruction.  */
+      instruction = (const inst *) hash_find (cr16_inst_hash, op);
+       parse_operands (&cr16_ins, param1);
+      if (((&cr16_ins)->arg[0].type == arg_ic)
+	  && ((&cr16_ins)->arg[0].constant >= 0))
+        {
+           if (streq ("lshb", op))
+	     op = "ashub";
+           else if (streq ("lshd", op))
+	     op = "ashud";
+	   else
+	     op = "ashuw";
+        }
+    }
+
+  /* Find the instruction.  */
+  instruction = (const inst *) hash_find (cr16_inst_hash, op);
+  if (instruction == NULL)
+    {
+      as_bad (_("Unknown opcode: `%s'"), op);
+      return;
+    }
+
+  /* Tie dwarf2 debug info to the address at the start of the insn.  */
+  dwarf2_emit_insn (0);
+
+  /* Parse the instruction's operands.  */
+  parse_insn (&cr16_ins, param);
+
+  /* Assemble the instruction - return upon failure.  */
+  if (assemble_insn (op, &cr16_ins) == 0)
+    return;
+
+  /* Print the instruction.  */
+  print_insn (&cr16_ins);
+}
diff --git a/gas/config/tc-cr16.h b/gas/config/tc-cr16.h
new file mode 100644
index 000000000000..6d06151eb166
--- /dev/null
+++ b/gas/config/tc-cr16.h
@@ -0,0 +1,73 @@
+/* tc-cr16.h -- Header file for tc-cr16.c, the CR16 GAS port.
+   Copyright 2007 Free Software Foundation, Inc.
+
+   Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_CR16_H
+#define TC_CR16_H
+
+#define TC_CR16 1
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_FORMAT "elf32-cr16"
+#define TARGET_ARCH   bfd_arch_cr16
+
+#define WORKING_DOT_WORD
+#define LOCAL_LABEL_PREFIX '.'
+
+#define md_undefined_symbol(s)  0
+#define md_number_to_chars      number_to_chars_littleendian
+
+/* We do relaxing in the assembler as well as the linker.  */
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* We do not want to adjust any relocations to make implementation of
+   linker relaxations easier.  */
+#define tc_fix_adjustable(fixP)  0
+
+/* We need to force out some relocations when relaxing.  */
+#define TC_FORCE_RELOCATION(FIXP) cr16_force_relocation (FIXP)
+extern int cr16_force_relocation (struct fix *);
+
+/* Fixup debug sections since we will never relax them.  */
+#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
+
+/* CR16 instructions, with operands included, are a multiple
+   of two bytes long.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *);
+/* This is called by emit_expr when creating a reloc for a cons.
+   We could use the definition there, except that we want to handle 
+   the CR16 reloc type specially, rather than the BFD_RELOC type.  */
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
+  cr16_cons_fix_new (FRAG, OFF, LEN, EXP) 
+
+/* Give an error if a frag containing code is not aligned to a 2-byte 
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code                                                \
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 1) != 0)        \
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,                 \
+                  _("instruction address is not a multiple of 2"));
+
+#endif /* TC_CR16_H */
diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c
index 1c8e6dc64529..83e01c589545 100644
--- a/gas/config/tc-cris.c
+++ b/gas/config/tc-cris.c
@@ -1,5 +1,6 @@
 /* tc-cris.c -- Assembler code for the CRIS CPU core.
-   Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2006
+   Free Software Foundation, Inc.
 
    Contributed by Axis Communications AB, Lund, Sweden.
    Originally written for GAS 1.38.1 by Mikael Asker.
@@ -22,7 +23,6 @@
    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -991,7 +991,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
       break;
 
     case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
-      /* This is the only time we check position and aligmnent of the
+      /* This is the only time we check position and alignment of the
 	 placement-tracking frag.  */
       if (sec->alignment_power < 2)
 	as_bad_where (fragP->fr_file, fragP->fr_line,
diff --git a/gas/config/tc-cris.h b/gas/config/tc-cris.h
index 34e6ef8153c5..59bbc0716379 100644
--- a/gas/config/tc-cris.h
+++ b/gas/config/tc-cris.h
@@ -1,5 +1,5 @@
 /* tc-cris.h -- Header file for tc-cris.c, the CRIS GAS port.
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2007
    Free Software Foundation, Inc.
 
    Contributed by Axis Communications AB, Lund, Sweden.
@@ -99,10 +99,9 @@ extern int md_cris_force_relocation (struct fix *);
    || (RTYPE) == BFD_RELOC_CRIS_32_PLT_PCREL)
 
 /* Make sure we don't resolve fixups for which we want to emit dynamic
-   relocations.  FIXME: Set fx_plt instead of using IS_CRIS_PIC_RELOC.  */
+   relocations.  */
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || IS_CRIS_PIC_RELOC ((FIX)->fx_r_type)		\
    || TC_FORCE_RELOCATION (FIX))
 
diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c
index 34448cd8dca7..961776f9e3a4 100644
--- a/gas/config/tc-crx.c
+++ b/gas/config/tc-crx.c
@@ -1271,7 +1271,7 @@ print_constant (int nbits, int shift, argument *arg)
       /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 
 	 always filling the upper part of output_opcode[1]. If we mistakenly 
 	 write it to output_opcode[0], the constant prefix (that is, 'match')
-	 will be overriden.
+	 will be overridden.
 		 0	   1	     2	       3
 	    +---------+---------+---------+---------+
 	    | 'match' |         | X X X X |	    |
diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c
index 6c94edbb4ef3..245162a50d9d 100644
--- a/gas/config/tc-d10v.c
+++ b/gas/config/tc-d10v.c
@@ -1,5 +1,5 @@
 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -1441,7 +1440,6 @@ do_assemble (char *str, struct d10v_opcode **opcode)
   char name[20];
   int nlen = 0;
   expressionS myops[6];
-  unsigned long insn;
 
   /* Drop leading whitespace.  */
   while (*str == ' ')
@@ -1463,7 +1461,7 @@ do_assemble (char *str, struct d10v_opcode **opcode)
   /* Find the first opcode with the proper name.  */
   *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
   if (*opcode == NULL)
-    as_fatal (_("unknown opcode: %s"), name);
+    return -1;
 
   save = input_line_pointer;
   input_line_pointer = (char *) op_end;
@@ -1472,8 +1470,7 @@ do_assemble (char *str, struct d10v_opcode **opcode)
     return -1;
   input_line_pointer = save;
 
-  insn = build_insn ((*opcode), myops, 0);
-  return insn;
+  return build_insn ((*opcode), myops, 0);
 }
 
 /* If while processing a fixup, a reloc really needs to be created.
@@ -1779,7 +1776,7 @@ md_assemble (char *str)
 	  prev_seg = now_seg;
 	  prev_subseg = now_subseg;
 	  if (prev_insn == (unsigned long) -1)
-	    as_fatal (_("can't find opcode "));
+	    as_fatal (_("can't find previous opcode "));
 	  fixups = fixups->next;
 	  str = str2 + 2;
 	}
@@ -1789,11 +1786,10 @@ md_assemble (char *str)
   if (insn == (unsigned long) -1)
     {
       if (extype != PACK_UNSPEC)
-	{
-	  etype = extype;
-	  return;
-	}
-      as_fatal (_("can't find opcode "));
+	etype = extype;
+      else
+	as_bad (_("could not assemble: %s"), str);
+      return;
     }
 
   if (etype != PACK_UNSPEC)
diff --git a/gas/config/tc-d30v.c b/gas/config/tc-d30v.c
index 848ad0341f09..fb7776a39532 100644
--- a/gas/config/tc-d30v.c
+++ b/gas/config/tc-d30v.c
@@ -1,5 +1,5 @@
 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
-   Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-dlx.h b/gas/config/tc-dlx.h
index 309f03738163..2cf3d8163a34 100644
--- a/gas/config/tc-dlx.h
+++ b/gas/config/tc-dlx.h
@@ -1,5 +1,5 @@
 /* tc-dlx.h -- Assemble for the DLX
-   Copyright 2002, 2003, 2005 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -22,10 +22,6 @@
 
 #define TC_DLX
 
-#ifndef  __BFD_H_SEEN__
-#include "bfd.h"
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH              bfd_arch_dlx
 #define TARGET_FORMAT            "elf32-dlx"
@@ -48,10 +44,6 @@ extern bfd_boolean md_dlx_fix_adjustable  (struct fix *);
 
 #define tc_unrecognized_line(c) dlx_unrecognized_line (c)
 
-#define tc_coff_symbol_emit_hook(a)	;	/* Not used.  */
-
-#define COFF_MAGIC DLXMAGIC
-
 /* No shared lib support, so we don't need to ensure externally
    visible symbols can be overridden.  */
 #define EXTERN_FORCE_RELOC 0
diff --git a/gas/config/tc-fr30.c b/gas/config/tc-fr30.c
index b0f2204c7f08..b7004c017552 100644
--- a/gas/config/tc-fr30.c
+++ b/gas/config/tc-fr30.c
@@ -1,5 +1,5 @@
 /* tc-fr30.c -- Assembler for the Fujitsu FR30.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index a2f4ccef4a60..77787719bcdb 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -18,7 +18,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"     
 #include "symcat.h"
diff --git a/gas/config/tc-h8300.c b/gas/config/tc-h8300.c
index 7db600c72bb8..bfea99207620 100644
--- a/gas/config/tc-h8300.c
+++ b/gas/config/tc-h8300.c
@@ -1,6 +1,6 @@
 /* tc-h8300.c -- Assemble code for the Renesas H8/300
    Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
-   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -21,10 +21,8 @@
 
 /* Written By Steve Chamberlain <sac@cygnus.com>.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"
-#include "bfd.h"
 #include "dwarf2dbg.h"
 
 #define DEFINE_TABLE
@@ -1391,7 +1389,7 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
 {
   int i;
   char *output = frag_more (this_try->length);
-  op_type *nibble_ptr = this_try->opcode->data.nib;
+  const op_type *nibble_ptr = this_try->opcode->data.nib;
   op_type c;
   unsigned int nibble_count = 0;
   int op_at[3];
diff --git a/gas/config/tc-h8300.h b/gas/config/tc-h8300.h
index bfc8f724c543..7191181e5c0c 100644
--- a/gas/config/tc-h8300.h
+++ b/gas/config/tc-h8300.h
@@ -86,3 +86,6 @@ extern int Nmode;
 extern int SXmode;
 
 #define md_operand(x)
+
+/* This target is buggy, and sets fix size too large.  */
+#define TC_FX_SIZE_SLACK(FIX) 1
diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c
index 8ae5a57e9039..71968c0383d5 100644
--- a/gas/config/tc-hppa.c
+++ b/gas/config/tc-hppa.c
@@ -1,6 +1,6 @@
 /* tc-hppa.c -- Assemble for the PA
    Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-   2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -22,11 +22,10 @@
 /* HP PA-RISC support was contributed by the Center for Software Science
    at the University of Utah.  */
 
-#include <stdio.h>
-
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
+#include "dw2gencfi.h"
 
 #include "bfd/libhppa.h"
 
@@ -490,112 +489,42 @@ struct selector_entry
 /* Prototypes for functions local to tc-hppa.c.  */
 
 #ifdef OBJ_SOM
-static void pa_check_current_space_and_subspace PARAMS ((void));
+static void pa_check_current_space_and_subspace (void);
 #endif
 
 #if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
-static void pa_text PARAMS ((int));
-static void pa_data PARAMS ((int));
-static void pa_comm PARAMS ((int));
+static void pa_text (int);
+static void pa_data (int);
+static void pa_comm (int);
 #endif
-static fp_operand_format pa_parse_fp_format PARAMS ((char **s));
-static void pa_cons PARAMS ((int));
-static void pa_float_cons PARAMS ((int));
-static void pa_fill PARAMS ((int));
-static void pa_lcomm PARAMS ((int));
-static void pa_lsym PARAMS ((int));
-static void pa_stringer PARAMS ((int));
-static void pa_version PARAMS ((int));
-static int pa_parse_fp_cmp_cond PARAMS ((char **));
-static int get_expression PARAMS ((char *));
-static int pa_get_absolute_expression PARAMS ((struct pa_it *, char **));
-static int evaluate_absolute PARAMS ((struct pa_it *));
-static unsigned int pa_build_arg_reloc PARAMS ((char *));
-static unsigned int pa_align_arg_reloc PARAMS ((unsigned int, unsigned int));
-static int pa_parse_nullif PARAMS ((char **));
-static int pa_parse_nonneg_cmpsub_cmpltr PARAMS ((char **));
-static int pa_parse_neg_cmpsub_cmpltr PARAMS ((char **));
-static int pa_parse_neg_add_cmpltr PARAMS ((char **));
-static int pa_parse_nonneg_add_cmpltr PARAMS ((char **));
-static int pa_parse_cmpb_64_cmpltr PARAMS ((char **));
-static int pa_parse_cmpib_64_cmpltr PARAMS ((char **));
-static int pa_parse_addb_64_cmpltr PARAMS ((char **));
-static void pa_block PARAMS ((int));
-static void pa_brtab PARAMS ((int));
-static void pa_try PARAMS ((int));
-static void pa_call PARAMS ((int));
-static void pa_call_args PARAMS ((struct call_desc *));
-static void pa_callinfo PARAMS ((int));
-static void pa_copyright PARAMS ((int));
-static void pa_end PARAMS ((int));
-static void pa_enter PARAMS ((int));
-static void pa_entry PARAMS ((int));
-static void pa_equ PARAMS ((int));
-static void pa_exit PARAMS ((int));
-static void pa_export PARAMS ((int));
-static void pa_type_args PARAMS ((symbolS *, int));
-static void pa_import PARAMS ((int));
-static void pa_label PARAMS ((int));
-static void pa_leave PARAMS ((int));
-static void pa_level PARAMS ((int));
-static void pa_origin PARAMS ((int));
-static void pa_proc PARAMS ((int));
-static void pa_procend PARAMS ((int));
-static void pa_param PARAMS ((int));
-static void pa_undefine_label PARAMS ((void));
-static int need_pa11_opcode PARAMS ((void));
-static int pa_parse_number PARAMS ((char **, int));
-static label_symbol_struct *pa_get_label PARAMS ((void));
 #ifdef OBJ_SOM
-static int exact_log2 PARAMS ((int));
-static void pa_compiler PARAMS ((int));
-static void pa_align PARAMS ((int));
-static void pa_space PARAMS ((int));
-static void pa_spnum PARAMS ((int));
-static void pa_subspace PARAMS ((int));
-static sd_chain_struct *create_new_space PARAMS ((char *, int, int,
+static int exact_log2 (int);
+static void pa_compiler (int);
+static void pa_align (int);
+static void pa_space (int);
+static void pa_spnum (int);
+static void pa_subspace (int);
+static sd_chain_struct *create_new_space (char *, int, int,
 						  int, int, int,
-						  asection *, int));
-static ssd_chain_struct *create_new_subspace PARAMS ((sd_chain_struct *,
+						  asection *, int);
+static ssd_chain_struct *create_new_subspace (sd_chain_struct *,
 						      char *, int, int,
 						      int, int, int, int,
 						      int, int, int, int,
-						      int, asection *));
-static ssd_chain_struct *update_subspace PARAMS ((sd_chain_struct *,
+						      int, asection *);
+static ssd_chain_struct *update_subspace (sd_chain_struct *,
 						  char *, int, int, int,
 						  int, int, int, int,
 						  int, int, int, int,
-						  asection *));
-static sd_chain_struct *is_defined_space PARAMS ((char *));
-static ssd_chain_struct *is_defined_subspace PARAMS ((char *));
-static sd_chain_struct *pa_segment_to_space PARAMS ((asection *));
-static ssd_chain_struct *pa_subsegment_to_subspace PARAMS ((asection *,
-							    subsegT));
-static sd_chain_struct *pa_find_space_by_number PARAMS ((int));
-static unsigned int pa_subspace_start PARAMS ((sd_chain_struct *, int));
-static sd_chain_struct *pa_parse_space_stmt PARAMS ((char *, int));
-static void pa_spaces_begin PARAMS ((void));
-#endif
-static void pa_ip PARAMS ((char *));
-static void fix_new_hppa PARAMS ((fragS *, int, int, symbolS *,
-				  offsetT, expressionS *, int,
-				  bfd_reloc_code_real_type,
-				  enum hppa_reloc_field_selector_type_alt,
-				  int, unsigned int, int));
-static int is_end_of_statement PARAMS ((void));
-static int reg_name_search PARAMS ((char *));
-static int pa_chk_field_selector PARAMS ((char **));
-static int is_same_frag PARAMS ((fragS *, fragS *));
-static void process_exit PARAMS ((void));
-static unsigned int pa_stringer_aux PARAMS ((char *));
-static fp_operand_format pa_parse_fp_cnv_format PARAMS ((char **s));
-static int pa_parse_ftest_gfx_completer PARAMS ((char **));
-
-#ifdef OBJ_ELF
-static void hppa_elf_mark_end_of_function PARAMS ((void));
-static void pa_build_unwind_subspace PARAMS ((struct call_info *));
-static void pa_vtable_entry PARAMS ((int));
-static void pa_vtable_inherit  PARAMS ((int));
+						  asection *);
+static sd_chain_struct *is_defined_space (char *);
+static ssd_chain_struct *is_defined_subspace (char *);
+static sd_chain_struct *pa_segment_to_space (asection *);
+static ssd_chain_struct *pa_subsegment_to_subspace (asection *,
+							    subsegT);
+static sd_chain_struct *pa_find_space_by_number (int);
+static unsigned int pa_subspace_start (sd_chain_struct *, int);
+static sd_chain_struct *pa_parse_space_stmt (char *, int);
 #endif
 
 /* File and globally scoped variable declarations.  */
@@ -629,96 +558,6 @@ static struct hash_control *op_hash = NULL;
    as they never appear followed by meaningful whitespace.  */
 const char hppa_symbol_chars[] = "*?=<>";
 
-/* Table of pseudo ops for the PA.  FIXME -- how many of these
-   are now redundant with the overall GAS and the object file
-   dependent tables?  */
-const pseudo_typeS md_pseudo_table[] =
-{
-  /* align pseudo-ops on the PA specify the actual alignment requested,
-     not the log2 of the requested alignment.  */
-#ifdef OBJ_SOM
-  {"align", pa_align, 8},
-#endif
-#ifdef OBJ_ELF
-  {"align", s_align_bytes, 8},
-#endif
-  {"begin_brtab", pa_brtab, 1},
-  {"begin_try", pa_try, 1},
-  {"block", pa_block, 1},
-  {"blockz", pa_block, 0},
-  {"byte", pa_cons, 1},
-  {"call", pa_call, 0},
-  {"callinfo", pa_callinfo, 0},
-#if defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD))
-  {"code", obj_elf_text, 0},
-#else
-  {"code", pa_text, 0},
-  {"comm", pa_comm, 0},
-#endif
-#ifdef OBJ_SOM
-  {"compiler", pa_compiler, 0},
-#endif
-  {"copyright", pa_copyright, 0},
-#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
-  {"data", pa_data, 0},
-#endif
-  {"double", pa_float_cons, 'd'},
-  {"dword", pa_cons, 8},
-  {"end", pa_end, 0},
-  {"end_brtab", pa_brtab, 0},
-#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
-  {"end_try", pa_try, 0},
-#endif
-  {"enter", pa_enter, 0},
-  {"entry", pa_entry, 0},
-  {"equ", pa_equ, 0},
-  {"exit", pa_exit, 0},
-  {"export", pa_export, 0},
-  {"fill", pa_fill, 0},
-  {"float", pa_float_cons, 'f'},
-  {"half", pa_cons, 2},
-  {"import", pa_import, 0},
-  {"int", pa_cons, 4},
-  {"label", pa_label, 0},
-  {"lcomm", pa_lcomm, 0},
-  {"leave", pa_leave, 0},
-  {"level", pa_level, 0},
-  {"long", pa_cons, 4},
-  {"lsym", pa_lsym, 0},
-#ifdef OBJ_SOM
-  {"nsubspa", pa_subspace, 1},
-#endif
-  {"octa", pa_cons, 16},
-  {"org", pa_origin, 0},
-  {"origin", pa_origin, 0},
-  {"param", pa_param, 0},
-  {"proc", pa_proc, 0},
-  {"procend", pa_procend, 0},
-  {"quad", pa_cons, 8},
-  {"reg", pa_equ, 1},
-  {"short", pa_cons, 2},
-  {"single", pa_float_cons, 'f'},
-#ifdef OBJ_SOM
-  {"space", pa_space, 0},
-  {"spnum", pa_spnum, 0},
-#endif
-  {"string", pa_stringer, 0},
-  {"stringz", pa_stringer, 1},
-#ifdef OBJ_SOM
-  {"subspa", pa_subspace, 0},
-#endif
-#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
-  {"text", pa_text, 0},
-#endif
-  {"version", pa_version, 0},
-#ifdef OBJ_ELF
-  {"vtable_entry", pa_vtable_entry, 0},
-  {"vtable_inherit", pa_vtable_inherit, 0},
-#endif
-  {"word", pa_cons, 4},
-  {NULL, 0, 0}
-};
-
 /* This array holds the chars that only start a comment at the beginning of
    a line.  If the line seems to have the form '# 123 filename'
    .line and .file directives will appear in the pre-processed output.
@@ -1215,6 +1054,26 @@ static struct default_space_dict pa_def_spaces[] =
   ((exp).X_op == O_subtract			\
    && strcmp (S_GET_NAME ((exp).X_op_symbol), "$PIC_pcrel$0") == 0)
 
+#define is_tls_gdidx(exp)			\
+  ((exp).X_op == O_subtract			\
+   && strcmp (S_GET_NAME ((exp).X_op_symbol), "$tls_gdidx$") == 0)
+
+#define is_tls_ldidx(exp)			\
+  ((exp).X_op == O_subtract			\
+   && strcmp (S_GET_NAME ((exp).X_op_symbol), "$tls_ldidx$") == 0)
+
+#define is_tls_dtpoff(exp)			\
+  ((exp).X_op == O_subtract			\
+   && strcmp (S_GET_NAME ((exp).X_op_symbol), "$tls_dtpoff$") == 0)
+
+#define is_tls_ieoff(exp)			\
+  ((exp).X_op == O_subtract			\
+   && strcmp (S_GET_NAME ((exp).X_op_symbol), "$tls_ieoff$") == 0)
+
+#define is_tls_leoff(exp)			\
+  ((exp).X_op == O_subtract			\
+   && strcmp (S_GET_NAME ((exp).X_op_symbol), "$tls_leoff$") == 0)
+
 /* We need some complex handling for stabs (sym1 - sym2).  Luckily, we'll
    always be able to reduce the expression to a constant, so we don't
    need real complex handling yet.  */
@@ -1227,7 +1086,7 @@ static struct default_space_dict pa_def_spaces[] =
    proc/procend pairs match.  */
 
 void
-pa_check_eof ()
+pa_check_eof (void)
 {
   if (within_entry_exit)
     as_fatal (_("Missing .exit\n"));
@@ -1240,7 +1099,7 @@ pa_check_eof ()
    or NULL if no label_symbol_struct exists for the current space.  */
 
 static label_symbol_struct *
-pa_get_label ()
+pa_get_label (void)
 {
   label_symbol_struct *label_chain;
 
@@ -1265,8 +1124,7 @@ pa_get_label ()
    this function will replace it with the new label.  */
 
 void
-pa_define_label (symbol)
-     symbolS *symbol;
+pa_define_label (symbolS *symbol)
 {
   label_symbol_struct *label_chain = pa_get_label ();
 
@@ -1275,8 +1133,7 @@ pa_define_label (symbol)
   else
     {
       /* Create a new label entry and add it to the head of the chain.  */
-      label_chain
-	= (label_symbol_struct *) xmalloc (sizeof (label_symbol_struct));
+      label_chain = xmalloc (sizeof (label_symbol_struct));
       label_chain->lss_label = symbol;
 #ifdef OBJ_SOM
       label_chain->lss_space = current_space;
@@ -1301,7 +1158,7 @@ pa_define_label (symbol)
    If there is no label_symbol_struct entry, then no action is taken.  */
 
 static void
-pa_undefine_label ()
+pa_undefine_label (void)
 {
   label_symbol_struct *label_chain;
   label_symbol_struct *prev_label_chain = NULL;
@@ -1340,25 +1197,21 @@ pa_undefine_label ()
    tc_fix_data field.  */
 
 static void
-fix_new_hppa (frag, where, size, add_symbol, offset, exp, pcrel,
-	      r_type, r_field, r_format, arg_reloc, unwind_bits)
-     fragS *frag;
-     int where;
-     int size;
-     symbolS *add_symbol;
-     offsetT offset;
-     expressionS *exp;
-     int pcrel;
-     bfd_reloc_code_real_type r_type;
-     enum hppa_reloc_field_selector_type_alt r_field;
-     int r_format;
-     unsigned int arg_reloc;
-     int unwind_bits ATTRIBUTE_UNUSED;
+fix_new_hppa (fragS *frag,
+	      int where,
+	      int size,
+	      symbolS *add_symbol,
+	      offsetT offset,
+	      expressionS *exp,
+	      int pcrel,
+	      bfd_reloc_code_real_type r_type,
+	      enum hppa_reloc_field_selector_type_alt r_field,
+	      int r_format,
+	      unsigned int arg_reloc,
+	      int unwind_bits ATTRIBUTE_UNUSED)
 {
   fixS *new_fix;
-
-  struct hppa_fix_struct *hppa_fix = (struct hppa_fix_struct *)
-  obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
+  struct hppa_fix_struct *hppa_fix = obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
 
   if (exp != NULL)
     new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
@@ -1380,30 +1233,20 @@ fix_new_hppa (frag, where, size, add_symbol, offset, exp, pcrel,
      it now so as not to confuse write.c.  Ditto for $PIC_pcrel$0.  */
   if (new_fix->fx_subsy
       && (strcmp (S_GET_NAME (new_fix->fx_subsy), "$global$") == 0
-	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$PIC_pcrel$0") == 0))
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$PIC_pcrel$0") == 0
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$tls_gdidx$") == 0
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$tls_ldidx$") == 0
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$tls_dtpoff$") == 0
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$tls_ieoff$") == 0
+	  || strcmp (S_GET_NAME (new_fix->fx_subsy), "$tls_leoff$") == 0))
     new_fix->fx_subsy = NULL;
 }
 
-/* Parse a .byte, .word, .long expression for the HPPA.  Called by
-   cons via the TC_PARSE_CONS_EXPRESSION macro.  */
-
-void
-parse_cons_expression_hppa (exp)
-     expressionS *exp;
-{
-  hppa_field_selector = pa_chk_field_selector (&input_line_pointer);
-  expression (exp);
-}
-
 /* This fix_new is called by cons via TC_CONS_FIX_NEW.
    hppa_field_selector is set by the parse_cons_expression_hppa.  */
 
 void
-cons_fix_new_hppa (frag, where, size, exp)
-     fragS *frag;
-     int where;
-     int size;
-     expressionS *exp;
+cons_fix_new_hppa (fragS *frag, int where, int size, expressionS *exp)
 {
   unsigned int rel_type;
 
@@ -1412,6 +1255,18 @@ cons_fix_new_hppa (frag, where, size, exp)
     rel_type = R_HPPA_GOTOFF;
   else if (is_PC_relative (*exp))
     rel_type = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+  else if (is_tls_gdidx (*exp))
+    rel_type = R_PARISC_TLS_GD21L;
+  else if (is_tls_ldidx (*exp))
+    rel_type = R_PARISC_TLS_LDM21L;
+  else if (is_tls_dtpoff (*exp))
+    rel_type = R_PARISC_TLS_LDO21L;
+  else if (is_tls_ieoff (*exp))
+    rel_type = R_PARISC_TLS_IE21L;
+  else if (is_tls_leoff (*exp))
+    rel_type = R_PARISC_TLS_LE21L;
+#endif
   else if (is_complex (*exp))
     rel_type = R_HPPA_COMPLEX;
   else
@@ -1431,155 +1286,1936 @@ cons_fix_new_hppa (frag, where, size, exp)
   hppa_field_selector = 0;
 }
 
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc. that the MD part of the assembler will need.  */
+/* Mark (via expr_end) the end of an expression (I think).  FIXME.  */
+
+static void
+get_expression (char *str)
+{
+  char *save_in;
+  asection *seg;
+
+  save_in = input_line_pointer;
+  input_line_pointer = str;
+  seg = expression (&the_insn.exp);
+  if (!(seg == absolute_section
+	|| seg == undefined_section
+	|| SEG_NORMAL (seg)))
+    {
+      as_warn (_("Bad segment in expression."));
+      expr_end = input_line_pointer;
+      input_line_pointer = save_in;
+      return;
+    }
+  expr_end = input_line_pointer;
+  input_line_pointer = save_in;
+}
+
+/* Parse a PA nullification completer (,n).  Return nonzero if the
+   completer was found; return zero if no completer was found.  */
+
+static int
+pa_parse_nullif (char **s)
+{
+  int nullif;
+
+  nullif = 0;
+  if (**s == ',')
+    {
+      *s = *s + 1;
+      if (strncasecmp (*s, "n", 1) == 0)
+	nullif = 1;
+      else
+	{
+	  as_bad (_("Invalid Nullification: (%c)"), **s);
+	  nullif = 0;
+	}
+      *s = *s + 1;
+    }
+
+  return nullif;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message or NULL is returned.  */
+
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  char *t;
+
+  switch (type)
+    {
+
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    case 'x':
+    case 'X':
+      prec = 6;
+      break;
+
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to MD_ATOF()");
+    }
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+  for (wordP = words; prec--;)
+    {
+      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+  return NULL;
+}
+
+/* Write out big-endian.  */
 
 void
-md_begin ()
+md_number_to_chars (char *buf, valueT val, int n)
 {
-  const char *retval = NULL;
-  int lose = 0;
-  unsigned int i = 0;
+  number_to_chars_bigendian (buf, val, n);
+}
 
-  last_call_info = NULL;
-  call_info_root = NULL;
+/* Translate internal representation of relocation info to BFD target
+   format.  */
 
-  /* Set the default machine type.  */
-  if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, DEFAULT_LEVEL))
-    as_warn (_("could not set architecture and machine"));
+arelent **
+tc_gen_reloc (asection *section, fixS *fixp)
+{
+  arelent *reloc;
+  struct hppa_fix_struct *hppa_fixp;
+  static arelent *no_relocs = NULL;
+  arelent **relocs;
+  reloc_type **codes;
+  reloc_type code;
+  int n_relocs;
+  int i;
 
-  /* Folding of text and data segments fails miserably on the PA.
-     Warn user and disable "-R" option.  */
-  if (flag_readonly_data_in_text)
+  hppa_fixp = (struct hppa_fix_struct *) fixp->tc_fix_data;
+  if (fixp->fx_addsy == 0)
+    return &no_relocs;
+
+  assert (hppa_fixp != 0);
+  assert (section != 0);
+
+  reloc = xmalloc (sizeof (arelent));
+
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  codes = hppa_gen_reloc_type (stdoutput,
+			       fixp->fx_r_type,
+			       hppa_fixp->fx_r_format,
+			       hppa_fixp->fx_r_field,
+			       fixp->fx_subsy != NULL,
+			       symbol_get_bfdsym (fixp->fx_addsy));
+
+  if (codes == NULL)
     {
-      as_warn (_("-R option not supported on this target."));
-      flag_readonly_data_in_text = 0;
+      as_bad_where (fixp->fx_file, fixp->fx_line, _("Cannot handle fixup"));
+      abort ();
     }
 
-#ifdef OBJ_SOM
-  pa_spaces_begin ();
+  for (n_relocs = 0; codes[n_relocs]; n_relocs++)
+    ;
+
+  relocs = xmalloc (sizeof (arelent *) * n_relocs + 1);
+  reloc = xmalloc (sizeof (arelent) * n_relocs);
+  for (i = 0; i < n_relocs; i++)
+    relocs[i] = &reloc[i];
+
+  relocs[n_relocs] = NULL;
+
+#ifdef OBJ_ELF
+  switch (fixp->fx_r_type)
+    {
+    default:
+      assert (n_relocs == 1);
+
+      code = *codes[0];
+
+      /* Now, do any processing that is dependent on the relocation type.  */
+      switch (code)
+	{
+	case R_PARISC_DLTREL21L:
+	case R_PARISC_DLTREL14R:
+	case R_PARISC_DLTREL14F:
+	case R_PARISC_PLABEL32:
+	case R_PARISC_PLABEL21L:
+	case R_PARISC_PLABEL14R:
+	  /* For plabel relocations, the addend of the
+	     relocation should be either 0 (no static link) or 2
+	     (static link required).  This adjustment is done in
+	     bfd/elf32-hppa.c:elf32_hppa_relocate_section.
+
+	     We also slam a zero addend into the DLT relative relocs;
+	     it doesn't make a lot of sense to use any addend since
+	     it gets you a different (eg unknown) DLT entry.  */
+	  reloc->addend = 0;
+	  break;
+
+#ifdef ELF_ARG_RELOC
+	case R_PARISC_PCREL17R:
+	case R_PARISC_PCREL17F:
+	case R_PARISC_PCREL17C:
+	case R_PARISC_DIR17R:
+	case R_PARISC_DIR17F:
+	case R_PARISC_PCREL21L:
+	case R_PARISC_DIR21L:
+	  reloc->addend = HPPA_R_ADDEND (hppa_fixp->fx_arg_reloc,
+					 fixp->fx_offset);
+	  break;
 #endif
 
-  op_hash = hash_new ();
+	case R_PARISC_DIR32:
+	  /* Facilitate hand-crafted unwind info.  */
+	  if (strcmp (section->name, UNWIND_SECTION_NAME) == 0)
+	    code = R_PARISC_SEGREL32;
+	  /* Fall thru */
 
-  while (i < NUMOPCODES)
+	default:
+	  reloc->addend = fixp->fx_offset;
+	  break;
+	}
+
+      reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+      *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+      reloc->howto = bfd_reloc_type_lookup (stdoutput,
+					    (bfd_reloc_code_real_type) code);
+      reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
+      assert (reloc->howto && (unsigned int) code == reloc->howto->type);
+      break;
+    }
+#else /* OBJ_SOM */
+
+  /* Walk over reach relocation returned by the BFD backend.  */
+  for (i = 0; i < n_relocs; i++)
     {
-      const char *name = pa_opcodes[i].name;
-      retval = hash_insert (op_hash, name, (struct pa_opcode *) &pa_opcodes[i]);
-      if (retval != NULL && *retval != '\0')
+      code = *codes[i];
+
+      relocs[i]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+      *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+      relocs[i]->howto =
+	bfd_reloc_type_lookup (stdoutput,
+			       (bfd_reloc_code_real_type) code);
+      relocs[i]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
+      switch (code)
 	{
-	  as_fatal (_("Internal error: can't hash `%s': %s\n"), name, retval);
-	  lose = 1;
+	case R_COMP2:
+	  /* The only time we ever use a R_COMP2 fixup is for the difference
+	     of two symbols.  With that in mind we fill in all four
+	     relocs now and break out of the loop.  */
+	  assert (i == 1);
+	  relocs[0]->sym_ptr_ptr
+	    = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
+	  relocs[0]->howto
+	    = bfd_reloc_type_lookup (stdoutput,
+				     (bfd_reloc_code_real_type) *codes[0]);
+	  relocs[0]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+	  relocs[0]->addend = 0;
+	  relocs[1]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+	  *relocs[1]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+	  relocs[1]->howto
+	    = bfd_reloc_type_lookup (stdoutput,
+				     (bfd_reloc_code_real_type) *codes[1]);
+	  relocs[1]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+	  relocs[1]->addend = 0;
+	  relocs[2]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+	  *relocs[2]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
+	  relocs[2]->howto
+	    = bfd_reloc_type_lookup (stdoutput,
+				     (bfd_reloc_code_real_type) *codes[2]);
+	  relocs[2]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+	  relocs[2]->addend = 0;
+	  relocs[3]->sym_ptr_ptr
+	    = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
+	  relocs[3]->howto
+	    = bfd_reloc_type_lookup (stdoutput,
+				     (bfd_reloc_code_real_type) *codes[3]);
+	  relocs[3]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+	  relocs[3]->addend = 0;
+	  relocs[4]->sym_ptr_ptr
+	    = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
+	  relocs[4]->howto
+	    = bfd_reloc_type_lookup (stdoutput,
+				     (bfd_reloc_code_real_type) *codes[4]);
+	  relocs[4]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+	  relocs[4]->addend = 0;
+	  goto done;
+	case R_PCREL_CALL:
+	case R_ABS_CALL:
+	  relocs[i]->addend = HPPA_R_ADDEND (hppa_fixp->fx_arg_reloc, 0);
+	  break;
+
+	case R_DLT_REL:
+	case R_DATA_PLABEL:
+	case R_CODE_PLABEL:
+	  /* For plabel relocations, the addend of the
+	     relocation should be either 0 (no static link) or 2
+	     (static link required).
+
+	     FIXME: We always assume no static link!
+
+	     We also slam a zero addend into the DLT relative relocs;
+	     it doesn't make a lot of sense to use any addend since
+	     it gets you a different (eg unknown) DLT entry.  */
+	  relocs[i]->addend = 0;
+	  break;
+
+	case R_N_MODE:
+	case R_S_MODE:
+	case R_D_MODE:
+	case R_R_MODE:
+	case R_FSEL:
+	case R_LSEL:
+	case R_RSEL:
+	case R_BEGIN_BRTAB:
+	case R_END_BRTAB:
+	case R_BEGIN_TRY:
+	case R_N0SEL:
+	case R_N1SEL:
+	  /* There is no symbol or addend associated with these fixups.  */
+	  relocs[i]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+	  *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
+	  relocs[i]->addend = 0;
+	  break;
+
+	case R_END_TRY:
+	case R_ENTRY:
+	case R_EXIT:
+	  /* There is no symbol associated with these fixups.  */
+	  relocs[i]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+	  *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
+	  relocs[i]->addend = fixp->fx_offset;
+	  break;
+
+	default:
+	  relocs[i]->addend = fixp->fx_offset;
 	}
-      do
+    }
+
+ done:
+#endif
+
+  return relocs;
+}
+
+/* Process any machine dependent frag types.  */
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
+{
+  unsigned int address;
+
+  if (fragP->fr_type == rs_machine_dependent)
+    {
+      switch ((int) fragP->fr_subtype)
 	{
-	  if ((pa_opcodes[i].match & pa_opcodes[i].mask)
-	      != pa_opcodes[i].match)
+	case 0:
+	  fragP->fr_type = rs_fill;
+	  know (fragP->fr_var == 1);
+	  know (fragP->fr_next);
+	  address = fragP->fr_address + fragP->fr_fix;
+	  if (address % fragP->fr_offset)
 	    {
-	      fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
-		       pa_opcodes[i].name, pa_opcodes[i].args);
-	      lose = 1;
+	      fragP->fr_offset =
+		fragP->fr_next->fr_address
+		- fragP->fr_address
+		- fragP->fr_fix;
 	    }
-	  ++i;
+	  else
+	    fragP->fr_offset = 0;
+	  break;
 	}
-      while (i < NUMOPCODES && !strcmp (pa_opcodes[i].name, name));
     }
+}
 
-  if (lose)
-    as_fatal (_("Broken assembler.  No assembly attempted."));
+/* Round up a section size to the appropriate boundary.  */
+
+valueT
+md_section_align (asection *segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+  int align2 = (1 << align) - 1;
+
+  return (size + align2) & ~align2;
+}
+
+/* Return the approximate size of a frag before relaxation has occurred.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP, asection *segment ATTRIBUTE_UNUSED)
+{
+  int size;
+
+  size = 0;
+
+  while ((fragP->fr_fix + size) % fragP->fr_offset)
+    size++;
+
+  return size;
+}
+
+#ifdef OBJ_ELF
+# ifdef WARN_COMMENTS
+const char *md_shortopts = "Vc";
+# else
+const char *md_shortopts = "V";
+# endif
+#else
+# ifdef WARN_COMMENTS
+const char *md_shortopts = "c";
+# else
+const char *md_shortopts = "";
+# endif
+#endif
+
+struct option md_longopts[] =
+{
+#ifdef WARN_COMMENTS
+  {"warn-comment", no_argument, NULL, 'c'},
+#endif
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    default:
+      return 0;
+
+#ifdef OBJ_ELF
+    case 'V':
+      print_version_id ();
+      break;
+#endif
+#ifdef WARN_COMMENTS
+    case 'c':
+      warn_comment = 1;
+      break;
+#endif
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_ELF
+  fprintf (stream, _("\
+  -Q                      ignored\n"));
+#endif
+#ifdef WARN_COMMENTS
+  fprintf (stream, _("\
+  -c                      print a warning if a comment is found\n"));
+#endif
+}
+
+/* We have no need to default values of symbols.  */
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return NULL;
+}
+
+#if defined (OBJ_SOM) || defined (ELF_ARG_RELOC)
+#define nonzero_dibits(x) \
+  ((x) | (((x) & 0x55555555) << 1) | (((x) & 0xAAAAAAAA) >> 1))
+#define arg_reloc_stub_needed(CALLER, CALLEE) \
+  (((CALLER) ^ (CALLEE)) & nonzero_dibits (CALLER) & nonzero_dibits (CALLEE))
+#else
+#define arg_reloc_stub_needed(CALLER, CALLEE) 0
+#endif
+
+/* Apply a fixup to an instruction.  */
 
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  char *fixpos;
+  struct hppa_fix_struct *hppa_fixP;
+  offsetT new_val;
+  int insn, val, fmt;
+
+  /* SOM uses R_HPPA_ENTRY and R_HPPA_EXIT relocations which can
+     never be "applied" (they are just markers).  Likewise for
+     R_HPPA_BEGIN_BRTAB and R_HPPA_END_BRTAB.  */
 #ifdef OBJ_SOM
-  /* SOM will change text_section.  To make sure we never put
-     anything into the old one switch to the new one now.  */
-  subseg_set (text_section, 0);
+  if (fixP->fx_r_type == R_HPPA_ENTRY
+      || fixP->fx_r_type == R_HPPA_EXIT
+      || fixP->fx_r_type == R_HPPA_BEGIN_BRTAB
+      || fixP->fx_r_type == R_HPPA_END_BRTAB
+      || fixP->fx_r_type == R_HPPA_BEGIN_TRY)
+    return;
+
+  /* Disgusting.  We must set fx_offset ourselves -- R_HPPA_END_TRY
+     fixups are considered not adjustable, which in turn causes
+     adjust_reloc_syms to not set fx_offset.  Ugh.  */
+  if (fixP->fx_r_type == R_HPPA_END_TRY)
+    {
+      fixP->fx_offset = * valP;
+      return;
+    }
+#endif
+#ifdef OBJ_ELF
+  if (fixP->fx_r_type == (int) R_PARISC_GNU_VTENTRY
+      || fixP->fx_r_type == (int) R_PARISC_GNU_VTINHERIT)
+    return;
+#endif
+
+  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
+    fixP->fx_done = 1;
+
+  /* There should be a HPPA specific fixup associated with the GAS fixup.  */
+  hppa_fixP = (struct hppa_fix_struct *) fixP->tc_fix_data;
+  if (hppa_fixP == NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("no hppa_fixup entry for fixup type 0x%x"),
+		    fixP->fx_r_type);
+      return;
+    }
+
+  fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  if (fixP->fx_size != 4 || hppa_fixP->fx_r_format == 32)
+    {
+      /* Handle constant output. */
+      number_to_chars_bigendian (fixpos, *valP, fixP->fx_size);
+      return;
+    }
+
+  insn = bfd_get_32 (stdoutput, fixpos);
+  fmt = bfd_hppa_insn2fmt (stdoutput, insn);
+
+  /* If there is a symbol associated with this fixup, then it's something
+     which will need a SOM relocation (except for some PC-relative relocs).
+     In such cases we should treat the "val" or "addend" as zero since it
+     will be added in as needed from fx_offset in tc_gen_reloc.  */
+  if ((fixP->fx_addsy != NULL
+       || fixP->fx_r_type == (int) R_HPPA_NONE)
+#ifdef OBJ_SOM
+      && fmt != 32
 #endif
+      )
+    new_val = ((fmt == 12 || fmt == 17 || fmt == 22) ? 8 : 0);
+#ifdef OBJ_SOM
+  /* These field selectors imply that we do not want an addend.  */
+  else if (hppa_fixP->fx_r_field == e_psel
+	   || hppa_fixP->fx_r_field == e_rpsel
+	   || hppa_fixP->fx_r_field == e_lpsel
+	   || hppa_fixP->fx_r_field == e_tsel
+	   || hppa_fixP->fx_r_field == e_rtsel
+	   || hppa_fixP->fx_r_field == e_ltsel)
+    new_val = ((fmt == 12 || fmt == 17 || fmt == 22) ? 8 : 0);
+#endif
+  else
+    new_val = hppa_field_adjust (* valP, 0, hppa_fixP->fx_r_field);
 
+  /* Handle pc-relative exceptions from above.  */
+  if ((fmt == 12 || fmt == 17 || fmt == 22)
+      && fixP->fx_addsy
+      && fixP->fx_pcrel
+      && !arg_reloc_stub_needed (symbol_arg_reloc_info (fixP->fx_addsy),
+				 hppa_fixP->fx_arg_reloc)
+#ifdef OBJ_ELF
+      && (* valP - 8 + 8192 < 16384
+	  || (fmt == 17 && * valP - 8 + 262144 < 524288)
+	  || (fmt == 22 && * valP - 8 + 8388608 < 16777216))
+#endif
 #ifdef OBJ_SOM
-  dummy_symbol = symbol_find_or_make ("L$dummy");
-  S_SET_SEGMENT (dummy_symbol, text_section);
-  /* Force the symbol to be converted to a real symbol.  */
-  (void) symbol_get_bfdsym (dummy_symbol);
+      && (* valP - 8 + 262144 < 524288
+	  || (fmt == 22 && * valP - 8 + 8388608 < 16777216))
+#endif
+      && !S_IS_EXTERNAL (fixP->fx_addsy)
+      && !S_IS_WEAK (fixP->fx_addsy)
+      && S_GET_SEGMENT (fixP->fx_addsy) == hppa_fixP->segment
+      && !(fixP->fx_subsy
+	   && S_GET_SEGMENT (fixP->fx_subsy) != hppa_fixP->segment))
+    {
+      new_val = hppa_field_adjust (* valP, 0, hppa_fixP->fx_r_field);
+    }
+
+  switch (fmt)
+    {
+    case 10:
+      CHECK_FIELD_WHERE (new_val, 8191, -8192,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val;
+
+      insn = (insn & ~ 0x3ff1) | (((val & 0x1ff8) << 1)
+				  | ((val & 0x2000) >> 13));
+      break;
+    case -11:
+      CHECK_FIELD_WHERE (new_val, 8191, -8192,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val;
+
+      insn = (insn & ~ 0x3ff9) | (((val & 0x1ffc) << 1)
+				  | ((val & 0x2000) >> 13));
+      break;
+      /* Handle all opcodes with the 'j' operand type.  */
+    case 14:
+      CHECK_FIELD_WHERE (new_val, 8191, -8192,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val;
+
+      insn = ((insn & ~ 0x3fff) | low_sign_unext (val, 14));
+      break;
+
+      /* Handle all opcodes with the 'k' operand type.  */
+    case 21:
+      CHECK_FIELD_WHERE (new_val, 1048575, -1048576,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val;
+
+      insn = (insn & ~ 0x1fffff) | re_assemble_21 (val);
+      break;
+
+      /* Handle all the opcodes with the 'i' operand type.  */
+    case 11:
+      CHECK_FIELD_WHERE (new_val, 1023, -1024,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val;
+
+      insn = (insn & ~ 0x7ff) | low_sign_unext (val, 11);
+      break;
+
+      /* Handle all the opcodes with the 'w' operand type.  */
+    case 12:
+      CHECK_FIELD_WHERE (new_val - 8, 8191, -8192,
+			 fixP->fx_file, fixP->fx_line);
+      val = new_val - 8;
+
+      insn = (insn & ~ 0x1ffd) | re_assemble_12 (val >> 2);
+      break;
+
+      /* Handle some of the opcodes with the 'W' operand type.  */
+    case 17:
+      {
+	offsetT distance = * valP;
+
+	/* If this is an absolute branch (ie no link) with an out of
+	   range target, then we want to complain.  */
+	if (fixP->fx_r_type == (int) R_HPPA_PCREL_CALL
+	    && (insn & 0xffe00000) == 0xe8000000)
+	  CHECK_FIELD_WHERE (distance - 8, 262143, -262144,
+			     fixP->fx_file, fixP->fx_line);
+
+	CHECK_FIELD_WHERE (new_val - 8, 262143, -262144,
+			   fixP->fx_file, fixP->fx_line);
+	val = new_val - 8;
+
+	insn = (insn & ~ 0x1f1ffd) | re_assemble_17 (val >> 2);
+	break;
+      }
+
+    case 22:
+      {
+	offsetT distance = * valP;
+
+	/* If this is an absolute branch (ie no link) with an out of
+	   range target, then we want to complain.  */
+	if (fixP->fx_r_type == (int) R_HPPA_PCREL_CALL
+	    && (insn & 0xffe00000) == 0xe8000000)
+	  CHECK_FIELD_WHERE (distance - 8, 8388607, -8388608,
+			     fixP->fx_file, fixP->fx_line);
+
+	CHECK_FIELD_WHERE (new_val - 8, 8388607, -8388608,
+			   fixP->fx_file, fixP->fx_line);
+	val = new_val - 8;
+
+	insn = (insn & ~ 0x3ff1ffd) | re_assemble_22 (val >> 2);
+	break;
+      }
+
+    case -10:
+      val = new_val;
+      insn = (insn & ~ 0xfff1) | re_assemble_16 (val & -8);
+      break;
+
+    case -16:
+      val = new_val;
+      insn = (insn & ~ 0xfff9) | re_assemble_16 (val & -4);
+      break;
+
+    case 16:
+      val = new_val;
+      insn = (insn & ~ 0xffff) | re_assemble_16 (val);
+      break;
+
+    case 32:
+      insn = new_val;
+      break;
+
+    default:
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("Unknown relocation encountered in md_apply_fix."));
+      return;
+    }
+
+#ifdef OBJ_ELF
+  switch (fixP->fx_r_type)
+    {
+      case R_PARISC_TLS_GD21L:
+      case R_PARISC_TLS_GD14R:
+      case R_PARISC_TLS_LDM21L:
+      case R_PARISC_TLS_LDM14R:
+      case R_PARISC_TLS_LE21L:
+      case R_PARISC_TLS_LE14R:
+      case R_PARISC_TLS_IE21L:
+      case R_PARISC_TLS_IE14R:
+        if (fixP->fx_addsy)
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
+	break;
+      default:
+	break;
+    }
 #endif
+
+  /* Insert the relocation.  */
+  bfd_put_32 (stdoutput, insn, fixpos);
 }
 
-/* Assemble a single instruction storing it into a frag.  */
-void
-md_assemble (str)
-     char *str;
+/* Exactly what point is a PC-relative offset relative TO?
+   On the PA, they're relative to the address of the offset.  */
+
+long
+md_pcrel_from (fixS *fixP)
 {
-  char *to;
+  return fixP->fx_where + fixP->fx_frag->fr_address;
+}
 
-  /* The had better be something to assemble.  */
-  assert (str);
+/* Return nonzero if the input line pointer is at the end of
+   a statement.  */
 
-  /* If we are within a procedure definition, make sure we've
-     defined a label for the procedure; handle case where the
-     label was defined after the .PROC directive.
+static int
+is_end_of_statement (void)
+{
+  return ((*input_line_pointer == '\n')
+	  || (*input_line_pointer == ';')
+	  || (*input_line_pointer == '!'));
+}
 
-     Note there's not need to diddle with the segment or fragment
-     for the label symbol in this case.  We have already switched
-     into the new $CODE$ subspace at this point.  */
-  if (within_procedure && last_call_info->start_symbol == NULL)
+#define REG_NAME_CNT	(sizeof (pre_defined_registers) / sizeof (struct pd_reg))
+
+/* Given NAME, find the register number associated with that name, return
+   the integer value associated with the given name or -1 on failure.  */
+
+static int
+reg_name_search (char *name)
+{
+  int middle, low, high;
+  int cmp;
+
+  low = 0;
+  high = REG_NAME_CNT - 1;
+
+  do
     {
-      label_symbol_struct *label_symbol = pa_get_label ();
+      middle = (low + high) / 2;
+      cmp = strcasecmp (name, pre_defined_registers[middle].name);
+      if (cmp < 0)
+	high = middle - 1;
+      else if (cmp > 0)
+	low = middle + 1;
+      else
+	return pre_defined_registers[middle].value;
+    }
+  while (low <= high);
 
-      if (label_symbol)
+  return -1;
+}
+
+/* Read a number from S.  The number might come in one of many forms,
+   the most common will be a hex or decimal constant, but it could be
+   a pre-defined register (Yuk!), or an absolute symbol.
+
+   Return 1 on success or 0 on failure.  If STRICT, then a missing
+   register prefix will cause a failure.  The number itself is
+   returned in `pa_number'.
+
+   IS_FLOAT indicates that a PA-89 FP register number should be
+   parsed;  A `l' or `r' suffix is checked for if but 2 of IS_FLOAT is
+   not set.
+
+   pa_parse_number can not handle negative constants and will fail
+   horribly if it is passed such a constant.  */
+
+static int
+pa_parse_number (char **s, int is_float)
+{
+  int num;
+  char *name;
+  char c;
+  symbolS *sym;
+  int status;
+  char *p = *s;
+  bfd_boolean have_prefix;
+
+  /* Skip whitespace before the number.  */
+  while (*p == ' ' || *p == '\t')
+    p = p + 1;
+
+  pa_number = -1;
+  have_prefix = 0;
+  num = 0;
+  if (!strict && ISDIGIT (*p))
+    {
+      /* Looks like a number.  */
+
+      if (*p == '0' && (*(p + 1) == 'x' || *(p + 1) == 'X'))
 	{
-	  if (label_symbol->lss_label)
+	  /* The number is specified in hex.  */
+	  p += 2;
+	  while (ISDIGIT (*p) || ((*p >= 'a') && (*p <= 'f'))
+		 || ((*p >= 'A') && (*p <= 'F')))
 	    {
-	      last_call_info->start_symbol = label_symbol->lss_label;
-	      symbol_get_bfdsym (label_symbol->lss_label)->flags
-		|= BSF_FUNCTION;
-#ifdef OBJ_SOM
-	      /* Also handle allocation of a fixup to hold the unwind
-		 information when the label appears after the proc/procend.  */
-	      if (within_entry_exit)
-		{
-		  char *where;
-		  unsigned int u;
+	      if (ISDIGIT (*p))
+		num = num * 16 + *p - '0';
+	      else if (*p >= 'a' && *p <= 'f')
+		num = num * 16 + *p - 'a' + 10;
+	      else
+		num = num * 16 + *p - 'A' + 10;
+	      ++p;
+	    }
+	}
+      else
+	{
+	  /* The number is specified in decimal.  */
+	  while (ISDIGIT (*p))
+	    {
+	      num = num * 10 + *p - '0';
+	      ++p;
+	    }
+	}
 
-		  where = frag_more (0);
-		  u = UNWIND_LOW32 (&last_call_info->ci_unwind.descriptor);
-		  fix_new_hppa (frag_now, where - frag_now->fr_literal, 0,
-				NULL, (offsetT) 0, NULL,
-				0, R_HPPA_ENTRY, e_fsel, 0, 0, u);
+      pa_number = num;
+
+      /* Check for a `l' or `r' suffix.  */
+      if (is_float)
+	{
+	  pa_number += FP_REG_BASE;
+	  if (! (is_float & 2))
+	    {
+	      if (IS_R_SELECT (p))
+		{
+		  pa_number += FP_REG_RSEL;
+		  ++p;
 		}
-#endif
+	      else if (IS_L_SELECT (p))
+		{
+		  ++p;
+		}
+	    }
+	}
+    }
+  else if (*p == '%')
+    {
+      /* The number might be a predefined register.  */
+      have_prefix = 1;
+      name = p;
+      p++;
+      c = *p;
+      /* Tege hack: Special case for general registers as the general
+         code makes a binary search with case translation, and is VERY
+         slow.  */
+      if (c == 'r')
+	{
+	  p++;
+	  if (*p == 'e' && *(p + 1) == 't'
+	      && (*(p + 2) == '0' || *(p + 2) == '1'))
+	    {
+	      p += 2;
+	      num = *p - '0' + 28;
+	      p++;
+	    }
+	  else if (*p == 'p')
+	    {
+	      num = 2;
+	      p++;
+	    }
+	  else if (!ISDIGIT (*p))
+	    {
+	      if (print_errors)
+		as_bad (_("Undefined register: '%s'."), name);
+	      num = -1;
 	    }
 	  else
-	    as_bad (_("Missing function name for .PROC (corrupted label chain)"));
+	    {
+	      do
+		num = num * 10 + *p++ - '0';
+	      while (ISDIGIT (*p));
+	    }
 	}
       else
-	as_bad (_("Missing function name for .PROC"));
+	{
+	  /* Do a normal register search.  */
+	  while (is_part_of_name (c))
+	    {
+	      p = p + 1;
+	      c = *p;
+	    }
+	  *p = 0;
+	  status = reg_name_search (name);
+	  if (status >= 0)
+	    num = status;
+	  else
+	    {
+	      if (print_errors)
+		as_bad (_("Undefined register: '%s'."), name);
+	      num = -1;
+	    }
+	  *p = c;
+	}
+
+      pa_number = num;
     }
+  else
+    {
+      /* And finally, it could be a symbol in the absolute section which
+         is effectively a constant, or a register alias symbol.  */
+      name = p;
+      c = *p;
+      while (is_part_of_name (c))
+	{
+	  p = p + 1;
+	  c = *p;
+	}
+      *p = 0;
+      if ((sym = symbol_find (name)) != NULL)
+	{
+	  if (S_GET_SEGMENT (sym) == reg_section)
+	    {
+	      num = S_GET_VALUE (sym);
+	      /* Well, we don't really have one, but we do have a
+		 register, so...  */
+	      have_prefix = TRUE;
+	    }
+	  else if (S_GET_SEGMENT (sym) == &bfd_abs_section)
+	    num = S_GET_VALUE (sym);
+	  else if (!strict)
+	    {
+	      if (print_errors)
+		as_bad (_("Non-absolute symbol: '%s'."), name);
+	      num = -1;
+	    }
+	}
+      else if (!strict)
+	{
+	  /* There is where we'd come for an undefined symbol
+	     or for an empty string.  For an empty string we
+	     will return zero.  That's a concession made for
+	     compatibility with the braindamaged HP assemblers.  */
+	  if (*name == 0)
+	    num = 0;
+	  else
+	    {
+	      if (print_errors)
+		as_bad (_("Undefined absolute constant: '%s'."), name);
+	      num = -1;
+	    }
+	}
+      *p = c;
 
-  /* Assemble the instruction.  Results are saved into "the_insn".  */
-  pa_ip (str);
+      pa_number = num;
+    }
 
-  /* Get somewhere to put the assembled instruction.  */
-  to = frag_more (4);
+  if (!strict || have_prefix)
+    {
+      *s = p;
+      return 1;
+    }
+  return 0;
+}
 
-  /* Output the opcode.  */
-  md_number_to_chars (to, the_insn.opcode, 4);
+/* Return nonzero if the given INSN and L/R information will require
+   a new PA-1.1 opcode.  */
 
-  /* If necessary output more stuff.  */
-  if (the_insn.reloc != R_HPPA_NONE)
-    fix_new_hppa (frag_now, (to - frag_now->fr_literal), 4, NULL,
-		  (offsetT) 0, &the_insn.exp, the_insn.pcrel,
-		  the_insn.reloc, the_insn.field_selector,
-		  the_insn.format, the_insn.arg_reloc, 0);
+static int
+need_pa11_opcode (void)
+{
+  if ((pa_number & FP_REG_RSEL) != 0
+      && !(the_insn.fpof1 == DBL && the_insn.fpof2 == DBL))
+    {
+      /* If this instruction is specific to a particular architecture,
+	 then set a new architecture.  */
+      if (bfd_get_mach (stdoutput) < pa11)
+	{
+	  if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, pa11))
+	    as_warn (_("could not update architecture and machine"));
+	}
+      return TRUE;
+    }
+  else
+    return FALSE;
+}
 
-#ifdef OBJ_ELF
-  dwarf2_emit_insn (4);
+/* Parse a condition for a fcmp instruction.  Return the numerical
+   code associated with the condition.  */
+
+static int
+pa_parse_fp_cmp_cond (char **s)
+{
+  int cond, i;
+
+  cond = 0;
+
+  for (i = 0; i < 32; i++)
+    {
+      if (strncasecmp (*s, fp_cond_map[i].string,
+		       strlen (fp_cond_map[i].string)) == 0)
+	{
+	  cond = fp_cond_map[i].cond;
+	  *s += strlen (fp_cond_map[i].string);
+	  /* If not a complete match, back up the input string and
+	     report an error.  */
+	  if (**s != ' ' && **s != '\t')
+	    {
+	      *s -= strlen (fp_cond_map[i].string);
+	      break;
+	    }
+	  while (**s == ' ' || **s == '\t')
+	    *s = *s + 1;
+	  return cond;
+	}
+    }
+
+  as_bad (_("Invalid FP Compare Condition: %s"), *s);
+
+  /* Advance over the bogus completer.  */
+  while (**s != ',' && **s != ' ' && **s != '\t')
+    *s += 1;
+
+  return 0;
+}
+
+/* Parse a graphics test complete for ftest.  */
+
+static int
+pa_parse_ftest_gfx_completer (char **s)
+{
+  int value;
+
+  value = 0;
+  if (strncasecmp (*s, "acc8", 4) == 0)
+    {
+      value = 5;
+      *s += 4;
+    }
+  else if (strncasecmp (*s, "acc6", 4) == 0)
+    {
+      value = 9;
+      *s += 4;
+    }
+  else if (strncasecmp (*s, "acc4", 4) == 0)
+    {
+      value = 13;
+      *s += 4;
+    }
+  else if (strncasecmp (*s, "acc2", 4) == 0)
+    {
+      value = 17;
+      *s += 4;
+    }
+  else if (strncasecmp (*s, "acc", 3) == 0)
+    {
+      value = 1;
+      *s += 3;
+    }
+  else if (strncasecmp (*s, "rej8", 4) == 0)
+    {
+      value = 6;
+      *s += 4;
+    }
+  else if (strncasecmp (*s, "rej", 3) == 0)
+    {
+      value = 2;
+      *s += 3;
+    }
+  else
+    {
+      value = 0;
+      as_bad (_("Invalid FTEST completer: %s"), *s);
+    }
+
+  return value;
+}
+
+/* Parse an FP operand format completer returning the completer
+   type.  */
+
+static fp_operand_format
+pa_parse_fp_cnv_format (char **s)
+{
+  int format;
+
+  format = SGL;
+  if (**s == ',')
+    {
+      *s += 1;
+      if (strncasecmp (*s, "sgl", 3) == 0)
+	{
+	  format = SGL;
+	  *s += 4;
+	}
+      else if (strncasecmp (*s, "dbl", 3) == 0)
+	{
+	  format = DBL;
+	  *s += 4;
+	}
+      else if (strncasecmp (*s, "quad", 4) == 0)
+	{
+	  format = QUAD;
+	  *s += 5;
+	}
+      else if (strncasecmp (*s, "w", 1) == 0)
+	{
+	  format = W;
+	  *s += 2;
+	}
+      else if (strncasecmp (*s, "uw", 2) == 0)
+	{
+	  format = UW;
+	  *s += 3;
+	}
+      else if (strncasecmp (*s, "dw", 2) == 0)
+	{
+	  format = DW;
+	  *s += 3;
+	}
+      else if (strncasecmp (*s, "udw", 3) == 0)
+	{
+	  format = UDW;
+	  *s += 4;
+	}
+      else if (strncasecmp (*s, "qw", 2) == 0)
+	{
+	  format = QW;
+	  *s += 3;
+	}
+      else if (strncasecmp (*s, "uqw", 3) == 0)
+	{
+	  format = UQW;
+	  *s += 4;
+	}
+      else
+	{
+	  format = ILLEGAL_FMT;
+	  as_bad (_("Invalid FP Operand Format: %3s"), *s);
+	}
+    }
+
+  return format;
+}
+
+/* Parse an FP operand format completer returning the completer
+   type.  */
+
+static fp_operand_format
+pa_parse_fp_format (char **s)
+{
+  int format;
+
+  format = SGL;
+  if (**s == ',')
+    {
+      *s += 1;
+      if (strncasecmp (*s, "sgl", 3) == 0)
+	{
+	  format = SGL;
+	  *s += 4;
+	}
+      else if (strncasecmp (*s, "dbl", 3) == 0)
+	{
+	  format = DBL;
+	  *s += 4;
+	}
+      else if (strncasecmp (*s, "quad", 4) == 0)
+	{
+	  format = QUAD;
+	  *s += 5;
+	}
+      else
+	{
+	  format = ILLEGAL_FMT;
+	  as_bad (_("Invalid FP Operand Format: %3s"), *s);
+	}
+    }
+
+  return format;
+}
+
+/* Convert from a selector string into a selector type.  */
+
+static int
+pa_chk_field_selector (char **str)
+{
+  int middle, low, high;
+  int cmp;
+  char name[4];
+
+  /* Read past any whitespace.  */
+  /* FIXME: should we read past newlines and formfeeds??? */
+  while (**str == ' ' || **str == '\t' || **str == '\n' || **str == '\f')
+    *str = *str + 1;
+
+  if ((*str)[1] == '\'' || (*str)[1] == '%')
+    name[0] = TOLOWER ((*str)[0]),
+    name[1] = 0;
+  else if ((*str)[2] == '\'' || (*str)[2] == '%')
+    name[0] = TOLOWER ((*str)[0]),
+    name[1] = TOLOWER ((*str)[1]),
+    name[2] = 0;
+  else if ((*str)[3] == '\'' || (*str)[3] == '%')
+    name[0] = TOLOWER ((*str)[0]),
+    name[1] = TOLOWER ((*str)[1]),
+    name[2] = TOLOWER ((*str)[2]),
+    name[3] = 0;
+  else
+    return e_fsel;
+
+  low = 0;
+  high = sizeof (selector_table) / sizeof (struct selector_entry) - 1;
+
+  do
+    {
+      middle = (low + high) / 2;
+      cmp = strcmp (name, selector_table[middle].prefix);
+      if (cmp < 0)
+	high = middle - 1;
+      else if (cmp > 0)
+	low = middle + 1;
+      else
+	{
+	  *str += strlen (name) + 1;
+#ifndef OBJ_SOM
+	  if (selector_table[middle].field_selector == e_nsel)
+	    return e_fsel;
 #endif
+	  return selector_table[middle].field_selector;
+	}
+    }
+  while (low <= high);
+
+  return e_fsel;
+}
+
+/* Parse a .byte, .word, .long expression for the HPPA.  Called by
+   cons via the TC_PARSE_CONS_EXPRESSION macro.  */
+
+void
+parse_cons_expression_hppa (expressionS *exp)
+{
+  hppa_field_selector = pa_chk_field_selector (&input_line_pointer);
+  expression (exp);
+}
+
+/* Evaluate an absolute expression EXP which may be modified by
+   the selector FIELD_SELECTOR.  Return the value of the expression.  */
+static int
+evaluate_absolute (struct pa_it *insn)
+{
+  offsetT value;
+  expressionS exp;
+  int field_selector = insn->field_selector;
+
+  exp = insn->exp;
+  value = exp.X_add_number;
+
+  return hppa_field_adjust (0, value, field_selector);
+}
+
+/* Mark (via expr_end) the end of an absolute expression.  FIXME.  */
+
+static int
+pa_get_absolute_expression (struct pa_it *insn, char **strp)
+{
+  char *save_in;
+
+  insn->field_selector = pa_chk_field_selector (strp);
+  save_in = input_line_pointer;
+  input_line_pointer = *strp;
+  expression (&insn->exp);
+  /* This is not perfect, but is a huge improvement over doing nothing.
+
+     The PA assembly syntax is ambiguous in a variety of ways.  Consider
+     this string "4 %r5"  Is that the number 4 followed by the register
+     r5, or is that 4 MOD r5?
+
+     If we get a modulo expression when looking for an absolute, we try
+     again cutting off the input string at the first whitespace character.  */
+  if (insn->exp.X_op == O_modulus)
+    {
+      char *s, c;
+      int retval;
+
+      input_line_pointer = *strp;
+      s = *strp;
+      while (*s != ',' && *s != ' ' && *s != '\t')
+	s++;
+
+      c = *s;
+      *s = 0;
+
+      retval = pa_get_absolute_expression (insn, strp);
+
+      input_line_pointer = save_in;
+      *s = c;
+      return evaluate_absolute (insn);
+    }
+  /* When in strict mode we have a non-match, fix up the pointers
+     and return to our caller.  */
+  if (insn->exp.X_op != O_constant && strict)
+    {
+      expr_end = input_line_pointer;
+      input_line_pointer = save_in;
+      return 0;
+    }
+  if (insn->exp.X_op != O_constant)
+    {
+      as_bad (_("Bad segment (should be absolute)."));
+      expr_end = input_line_pointer;
+      input_line_pointer = save_in;
+      return 0;
+    }
+  expr_end = input_line_pointer;
+  input_line_pointer = save_in;
+  return evaluate_absolute (insn);
+}
+
+/* Given an argument location specification return the associated
+   argument location number.  */
+
+static unsigned int
+pa_build_arg_reloc (char *type_name)
+{
+
+  if (strncasecmp (type_name, "no", 2) == 0)
+    return 0;
+  if (strncasecmp (type_name, "gr", 2) == 0)
+    return 1;
+  else if (strncasecmp (type_name, "fr", 2) == 0)
+    return 2;
+  else if (strncasecmp (type_name, "fu", 2) == 0)
+    return 3;
+  else
+    as_bad (_("Invalid argument location: %s\n"), type_name);
+
+  return 0;
+}
+
+/* Encode and return an argument relocation specification for
+   the given register in the location specified by arg_reloc.  */
+
+static unsigned int
+pa_align_arg_reloc (unsigned int reg, unsigned int arg_reloc)
+{
+  unsigned int new_reloc;
+
+  new_reloc = arg_reloc;
+  switch (reg)
+    {
+    case 0:
+      new_reloc <<= 8;
+      break;
+    case 1:
+      new_reloc <<= 6;
+      break;
+    case 2:
+      new_reloc <<= 4;
+      break;
+    case 3:
+      new_reloc <<= 2;
+      break;
+    default:
+      as_bad (_("Invalid argument description: %d"), reg);
+    }
+
+  return new_reloc;
+}
+
+/* Parse a non-negated compare/subtract completer returning the
+   number (for encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_nonneg_cmpsub_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+  char *save_s = *s;
+  int nullify = 0;
+
+  cmpltr = 0;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+
+      if (strcmp (name, "=") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, "<") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, "<=") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcmp (name, "<<") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcmp (name, "<<=") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "sv") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "od") == 0)
+	{
+	  cmpltr = 7;
+	}
+      /* If we have something like addb,n then there is no condition
+         completer.  */
+      else if (strcasecmp (name, "n") == 0)
+	{
+	  cmpltr = 0;
+	  nullify = 1;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  /* Reset pointers if this was really a ,n for a branch instruction.  */
+  if (nullify)
+    *s = save_s;
+
+  return cmpltr;
+}
+
+/* Parse a negated compare/subtract completer returning the
+   number (for encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_neg_cmpsub_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+  char *save_s = *s;
+  int nullify = 0;
+
+  cmpltr = 0;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+
+      if (strcasecmp (name, "tr") == 0)
+	{
+	  cmpltr = 0;
+	}
+      else if (strcmp (name, "<>") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, ">=") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, ">") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcmp (name, ">>=") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcmp (name, ">>") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "nsv") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "ev") == 0)
+	{
+	  cmpltr = 7;
+	}
+      /* If we have something like addb,n then there is no condition
+         completer.  */
+      else if (strcasecmp (name, "n") == 0)
+	{
+	  cmpltr = 0;
+	  nullify = 1;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  /* Reset pointers if this was really a ,n for a branch instruction.  */
+  if (nullify)
+    *s = save_s;
+
+  return cmpltr;
+}
+
+/* Parse a 64 bit compare and branch completer returning the number (for
+   encoding in instructions) of the given completer.
+
+   Nonnegated comparisons are returned as 0-7, negated comparisons are
+   returned as 8-15.  */
+
+static int
+pa_parse_cmpb_64_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+
+  cmpltr = -1;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+
+      if (strcmp (name, "*") == 0)
+	{
+	  cmpltr = 0;
+	}
+      else if (strcmp (name, "*=") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, "*<") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, "*<=") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcmp (name, "*<<") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcmp (name, "*<<=") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "*sv") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "*od") == 0)
+	{
+	  cmpltr = 7;
+	}
+      else if (strcasecmp (name, "*tr") == 0)
+	{
+	  cmpltr = 8;
+	}
+      else if (strcmp (name, "*<>") == 0)
+	{
+	  cmpltr = 9;
+	}
+      else if (strcmp (name, "*>=") == 0)
+	{
+	  cmpltr = 10;
+	}
+      else if (strcmp (name, "*>") == 0)
+	{
+	  cmpltr = 11;
+	}
+      else if (strcmp (name, "*>>=") == 0)
+	{
+	  cmpltr = 12;
+	}
+      else if (strcmp (name, "*>>") == 0)
+	{
+	  cmpltr = 13;
+	}
+      else if (strcasecmp (name, "*nsv") == 0)
+	{
+	  cmpltr = 14;
+	}
+      else if (strcasecmp (name, "*ev") == 0)
+	{
+	  cmpltr = 15;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  return cmpltr;
+}
+
+/* Parse a 64 bit compare immediate and branch completer returning the number
+   (for encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_cmpib_64_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+
+  cmpltr = -1;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+
+      if (strcmp (name, "*<<") == 0)
+	{
+	  cmpltr = 0;
+	}
+      else if (strcmp (name, "*=") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, "*<") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, "*<=") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcmp (name, "*>>=") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcmp (name, "*<>") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "*>=") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "*>") == 0)
+	{
+	  cmpltr = 7;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  return cmpltr;
+}
+
+/* Parse a non-negated addition completer returning the number
+   (for encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_nonneg_add_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+  char *save_s = *s;
+  int nullify = 0;
+
+  cmpltr = 0;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+      if (strcmp (name, "=") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, "<") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, "<=") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcasecmp (name, "nuv") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcasecmp (name, "znv") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "sv") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "od") == 0)
+	{
+	  cmpltr = 7;
+	}
+      /* If we have something like addb,n then there is no condition
+         completer.  */
+      else if (strcasecmp (name, "n") == 0)
+	{
+	  cmpltr = 0;
+	  nullify = 1;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  /* Reset pointers if this was really a ,n for a branch instruction.  */
+  if (nullify)
+    *s = save_s;
+
+  return cmpltr;
+}
+
+/* Parse a negated addition completer returning the number
+   (for encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_neg_add_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+  char *save_s = *s;
+  int nullify = 0;
+
+  cmpltr = 0;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+      if (strcasecmp (name, "tr") == 0)
+	{
+	  cmpltr = 0;
+	}
+      else if (strcmp (name, "<>") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, ">=") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, ">") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcasecmp (name, "uv") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcasecmp (name, "vnz") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "nsv") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "ev") == 0)
+	{
+	  cmpltr = 7;
+	}
+      /* If we have something like addb,n then there is no condition
+         completer.  */
+      else if (strcasecmp (name, "n") == 0)
+	{
+	  cmpltr = 0;
+	  nullify = 1;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  /* Reset pointers if this was really a ,n for a branch instruction.  */
+  if (nullify)
+    *s = save_s;
+
+  return cmpltr;
+}
+
+/* Parse a 64 bit wide mode add and branch completer returning the number (for
+   encoding in instructions) of the given completer.  */
+
+static int
+pa_parse_addb_64_cmpltr (char **s)
+{
+  int cmpltr;
+  char *name = *s + 1;
+  char c;
+  char *save_s = *s;
+  int nullify = 0;
+
+  cmpltr = 0;
+  if (**s == ',')
+    {
+      *s += 1;
+      while (**s != ',' && **s != ' ' && **s != '\t')
+	*s += 1;
+      c = **s;
+      **s = 0x00;
+      if (strcmp (name, "=") == 0)
+	{
+	  cmpltr = 1;
+	}
+      else if (strcmp (name, "<") == 0)
+	{
+	  cmpltr = 2;
+	}
+      else if (strcmp (name, "<=") == 0)
+	{
+	  cmpltr = 3;
+	}
+      else if (strcasecmp (name, "nuv") == 0)
+	{
+	  cmpltr = 4;
+	}
+      else if (strcasecmp (name, "*=") == 0)
+	{
+	  cmpltr = 5;
+	}
+      else if (strcasecmp (name, "*<") == 0)
+	{
+	  cmpltr = 6;
+	}
+      else if (strcasecmp (name, "*<=") == 0)
+	{
+	  cmpltr = 7;
+	}
+      else if (strcmp (name, "tr") == 0)
+	{
+	  cmpltr = 8;
+	}
+      else if (strcmp (name, "<>") == 0)
+	{
+	  cmpltr = 9;
+	}
+      else if (strcmp (name, ">=") == 0)
+	{
+	  cmpltr = 10;
+	}
+      else if (strcmp (name, ">") == 0)
+	{
+	  cmpltr = 11;
+	}
+      else if (strcasecmp (name, "uv") == 0)
+	{
+	  cmpltr = 12;
+	}
+      else if (strcasecmp (name, "*<>") == 0)
+	{
+	  cmpltr = 13;
+	}
+      else if (strcasecmp (name, "*>=") == 0)
+	{
+	  cmpltr = 14;
+	}
+      else if (strcasecmp (name, "*>") == 0)
+	{
+	  cmpltr = 15;
+	}
+      /* If we have something like addb,n then there is no condition
+         completer.  */
+      else if (strcasecmp (name, "n") == 0)
+	{
+	  cmpltr = 0;
+	  nullify = 1;
+	}
+      else
+	{
+	  cmpltr = -1;
+	}
+      **s = c;
+    }
+
+  /* Reset pointers if this was really a ,n for a branch instruction.  */
+  if (nullify)
+    *s = save_s;
+
+  return cmpltr;
 }
 
 /* Do the real work for assembling a single instruction.  Store results
    into the global "the_insn" variable.  */
 
 static void
-pa_ip (str)
-     char *str;
+pa_ip (char *str)
 {
   char *error_message = "";
   char *s, c, *argstart, *name, *save_s;
@@ -1634,9 +3270,7 @@ pa_ip (str)
     }
 
   if (comma)
-    {
-      *--s = ',';
-    }
+    *--s = ',';
 
   /* Mark the location where arguments for the instruction start, then
      start processing them.  */
@@ -1664,7 +3298,6 @@ pa_ip (str)
 
 	  switch (*args)
 	    {
-
 	    /* End of arguments.  */
 	    case '\0':
 	      if (*s == '\0')
@@ -2974,6 +4607,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 11;
@@ -3093,6 +4738,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3123,6 +4780,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3147,6 +4816,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3171,6 +4852,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 21;
@@ -3196,6 +4889,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3222,6 +4927,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3248,6 +4965,18 @@ pa_ip (str)
 		    the_insn.reloc = R_HPPA_GOTOFF;
 		  else if (is_PC_relative (the_insn.exp))
 		    the_insn.reloc = R_HPPA_PCREL_CALL;
+#ifdef OBJ_ELF
+		  else if (is_tls_gdidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_GD21L;
+		  else if (is_tls_ldidx (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDM21L;
+		  else if (is_tls_dtpoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LDO21L;
+		  else if (is_tls_ieoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_IE21L;
+		  else if (is_tls_leoff (the_insn.exp))
+		    the_insn.reloc = R_PARISC_TLS_LE21L;
+#endif
 		  else
 		    the_insn.reloc = R_HPPA;
 		  the_insn.format = 14;
@@ -3992,1947 +5721,83 @@ pa_ip (str)
   the_insn.opcode = opcode;
 }
 
-/* Turn a string in input_line_pointer into a floating point constant of type
-   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
-   emitted is stored in *sizeP .  An error message or NULL is returned.  */
-
-#define MAX_LITTLENUMS 6
-
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to MD_ATOF()");
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  for (wordP = words; prec--;)
-    {
-      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return NULL;
-}
-
-/* Write out big-endian.  */
+/* Assemble a single instruction storing it into a frag.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
-{
-  number_to_chars_bigendian (buf, val, n);
-}
-
-/* Translate internal representation of relocation info to BFD target
-   format.  */
-
-arelent **
-tc_gen_reloc (section, fixp)
-     asection *section;
-     fixS *fixp;
+md_assemble (char *str)
 {
-  arelent *reloc;
-  struct hppa_fix_struct *hppa_fixp;
-  static arelent *no_relocs = NULL;
-  arelent **relocs;
-  reloc_type **codes;
-  reloc_type code;
-  int n_relocs;
-  int i;
-
-  hppa_fixp = (struct hppa_fix_struct *) fixp->tc_fix_data;
-  if (fixp->fx_addsy == 0)
-    return &no_relocs;
-
-  assert (hppa_fixp != 0);
-  assert (section != 0);
-
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-  codes = hppa_gen_reloc_type (stdoutput,
-			       fixp->fx_r_type,
-			       hppa_fixp->fx_r_format,
-			       hppa_fixp->fx_r_field,
-			       fixp->fx_subsy != NULL,
-			       symbol_get_bfdsym (fixp->fx_addsy));
-
-  if (codes == NULL)
-    {
-      as_bad_where (fixp->fx_file, fixp->fx_line, _("Cannot handle fixup"));
-      abort ();
-    }
-
-  for (n_relocs = 0; codes[n_relocs]; n_relocs++)
-    ;
-
-  relocs = (arelent **) xmalloc (sizeof (arelent *) * n_relocs + 1);
-  reloc = (arelent *) xmalloc (sizeof (arelent) * n_relocs);
-  for (i = 0; i < n_relocs; i++)
-    relocs[i] = &reloc[i];
-
-  relocs[n_relocs] = NULL;
-
-#ifdef OBJ_ELF
-  switch (fixp->fx_r_type)
-    {
-    default:
-      assert (n_relocs == 1);
-
-      code = *codes[0];
-
-      /* Now, do any processing that is dependent on the relocation type.  */
-      switch (code)
-	{
-	case R_PARISC_DLTREL21L:
-	case R_PARISC_DLTREL14R:
-	case R_PARISC_DLTREL14F:
-	case R_PARISC_PLABEL32:
-	case R_PARISC_PLABEL21L:
-	case R_PARISC_PLABEL14R:
-	  /* For plabel relocations, the addend of the
-	     relocation should be either 0 (no static link) or 2
-	     (static link required).  This adjustment is done in
-	     bfd/elf32-hppa.c:elf32_hppa_relocate_section.
-
-	     We also slam a zero addend into the DLT relative relocs;
-	     it doesn't make a lot of sense to use any addend since
-	     it gets you a different (eg unknown) DLT entry.  */
-	  reloc->addend = 0;
-	  break;
-
-#ifdef ELF_ARG_RELOC
-	case R_PARISC_PCREL17R:
-	case R_PARISC_PCREL17F:
-	case R_PARISC_PCREL17C:
-	case R_PARISC_DIR17R:
-	case R_PARISC_DIR17F:
-	case R_PARISC_PCREL21L:
-	case R_PARISC_DIR21L:
-	  reloc->addend = HPPA_R_ADDEND (hppa_fixp->fx_arg_reloc,
-					 fixp->fx_offset);
-	  break;
-#endif
-
-	case R_PARISC_DIR32:
-	  /* Facilitate hand-crafted unwind info.  */
-	  if (strcmp (section->name, UNWIND_SECTION_NAME) == 0)
-	    code = R_PARISC_SEGREL32;
-	  /* Fall thru */
-
-	default:
-	  reloc->addend = fixp->fx_offset;
-	  break;
-	}
+  char *to;
 
-      reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-      *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-      reloc->howto = bfd_reloc_type_lookup (stdoutput,
-					    (bfd_reloc_code_real_type) code);
-      reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  /* The had better be something to assemble.  */
+  assert (str);
 
-      assert (reloc->howto && (unsigned int) code == reloc->howto->type);
-      break;
-    }
-#else /* OBJ_SOM */
+  /* If we are within a procedure definition, make sure we've
+     defined a label for the procedure; handle case where the
+     label was defined after the .PROC directive.
 
-  /* Walk over reach relocation returned by the BFD backend.  */
-  for (i = 0; i < n_relocs; i++)
+     Note there's not need to diddle with the segment or fragment
+     for the label symbol in this case.  We have already switched
+     into the new $CODE$ subspace at this point.  */
+  if (within_procedure && last_call_info->start_symbol == NULL)
     {
-      code = *codes[i];
-
-      relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-      *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-      relocs[i]->howto =
-	bfd_reloc_type_lookup (stdoutput,
-			       (bfd_reloc_code_real_type) code);
-      relocs[i]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-
-      switch (code)
-	{
-	case R_COMP2:
-	  /* The only time we ever use a R_COMP2 fixup is for the difference
-	     of two symbols.  With that in mind we fill in all four
-	     relocs now and break out of the loop.  */
-	  assert (i == 1);
-	  relocs[0]->sym_ptr_ptr = (asymbol **) &(bfd_abs_symbol);
-	  relocs[0]->howto =
-	    bfd_reloc_type_lookup (stdoutput,
-				   (bfd_reloc_code_real_type) *codes[0]);
-	  relocs[0]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-	  relocs[0]->addend = 0;
-	  relocs[1]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-	  *relocs[1]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-	  relocs[1]->howto =
-	    bfd_reloc_type_lookup (stdoutput,
-				   (bfd_reloc_code_real_type) *codes[1]);
-	  relocs[1]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-	  relocs[1]->addend = 0;
-	  relocs[2]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-	  *relocs[2]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
-	  relocs[2]->howto =
-	    bfd_reloc_type_lookup (stdoutput,
-				   (bfd_reloc_code_real_type) *codes[2]);
-	  relocs[2]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-	  relocs[2]->addend = 0;
-	  relocs[3]->sym_ptr_ptr = (asymbol **) &(bfd_abs_symbol);
-	  relocs[3]->howto =
-	    bfd_reloc_type_lookup (stdoutput,
-				   (bfd_reloc_code_real_type) *codes[3]);
-	  relocs[3]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-	  relocs[3]->addend = 0;
-	  relocs[4]->sym_ptr_ptr = (asymbol **) &(bfd_abs_symbol);
-	  relocs[4]->howto =
-	    bfd_reloc_type_lookup (stdoutput,
-				   (bfd_reloc_code_real_type) *codes[4]);
-	  relocs[4]->address = fixp->fx_frag->fr_address + fixp->fx_where;
-	  relocs[4]->addend = 0;
-	  goto done;
-	case R_PCREL_CALL:
-	case R_ABS_CALL:
-	  relocs[i]->addend = HPPA_R_ADDEND (hppa_fixp->fx_arg_reloc, 0);
-	  break;
-
-	case R_DLT_REL:
-	case R_DATA_PLABEL:
-	case R_CODE_PLABEL:
-	  /* For plabel relocations, the addend of the
-	     relocation should be either 0 (no static link) or 2
-	     (static link required).
-
-	     FIXME: We always assume no static link!
-
-	     We also slam a zero addend into the DLT relative relocs;
-	     it doesn't make a lot of sense to use any addend since
-	     it gets you a different (eg unknown) DLT entry.  */
-	  relocs[i]->addend = 0;
-	  break;
-
-	case R_N_MODE:
-	case R_S_MODE:
-	case R_D_MODE:
-	case R_R_MODE:
-	case R_FSEL:
-	case R_LSEL:
-	case R_RSEL:
-	case R_BEGIN_BRTAB:
-	case R_END_BRTAB:
-	case R_BEGIN_TRY:
-	case R_N0SEL:
-	case R_N1SEL:
-	  /* There is no symbol or addend associated with these fixups.  */
-	  relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-	  *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
-	  relocs[i]->addend = 0;
-	  break;
-
-	case R_END_TRY:
-	case R_ENTRY:
-	case R_EXIT:
-	  /* There is no symbol associated with these fixups.  */
-	  relocs[i]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-	  *relocs[i]->sym_ptr_ptr = symbol_get_bfdsym (dummy_symbol);
-	  relocs[i]->addend = fixp->fx_offset;
-	  break;
-
-	default:
-	  relocs[i]->addend = fixp->fx_offset;
-	}
-    }
-
- done:
-#endif
-
-  return relocs;
-}
-
-/* Process any machine dependent frag types.  */
-
-void
-md_convert_frag (abfd, sec, fragP)
-     register bfd *abfd ATTRIBUTE_UNUSED;
-     register asection *sec ATTRIBUTE_UNUSED;
-     register fragS *fragP;
-{
-  unsigned int address;
+      label_symbol_struct *label_symbol = pa_get_label ();
 
-  if (fragP->fr_type == rs_machine_dependent)
-    {
-      switch ((int) fragP->fr_subtype)
+      if (label_symbol)
 	{
-	case 0:
-	  fragP->fr_type = rs_fill;
-	  know (fragP->fr_var == 1);
-	  know (fragP->fr_next);
-	  address = fragP->fr_address + fragP->fr_fix;
-	  if (address % fragP->fr_offset)
+	  if (label_symbol->lss_label)
 	    {
-	      fragP->fr_offset =
-		fragP->fr_next->fr_address
-		- fragP->fr_address
-		- fragP->fr_fix;
-	    }
-	  else
-	    fragP->fr_offset = 0;
-	  break;
-	}
-    }
-}
-
-/* Round up a section size to the appropriate boundary.  */
-
-valueT
-md_section_align (segment, size)
-     asection *segment;
-     valueT size;
-{
-  int align = bfd_get_section_alignment (stdoutput, segment);
-  int align2 = (1 << align) - 1;
-
-  return (size + align2) & ~align2;
-}
-
-/* Return the approximate size of a frag before relaxation has occurred.  */
-int
-md_estimate_size_before_relax (fragP, segment)
-     register fragS *fragP;
-     asection *segment ATTRIBUTE_UNUSED;
-{
-  int size;
-
-  size = 0;
-
-  while ((fragP->fr_fix + size) % fragP->fr_offset)
-    size++;
-
-  return size;
-}
-
-#ifdef OBJ_ELF
-# ifdef WARN_COMMENTS
-const char *md_shortopts = "Vc";
-# else
-const char *md_shortopts = "V";
-# endif
-#else
-# ifdef WARN_COMMENTS
-const char *md_shortopts = "c";
-# else
-const char *md_shortopts = "";
-# endif
-#endif
-
-struct option md_longopts[] = {
-#ifdef WARN_COMMENTS
-  {"warn-comment", no_argument, NULL, 'c'},
-#endif
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
-{
-  switch (c)
-    {
-    default:
-      return 0;
-
-#ifdef OBJ_ELF
-    case 'V':
-      print_version_id ();
-      break;
-#endif
-#ifdef WARN_COMMENTS
-    case 'c':
-      warn_comment = 1;
-      break;
-#endif
-    }
-
-  return 1;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
-{
-#ifdef OBJ_ELF
-  fprintf (stream, _("\
-  -Q                      ignored\n"));
-#endif
-#ifdef WARN_COMMENTS
-  fprintf (stream, _("\
-  -c                      print a warning if a comment is found\n"));
-#endif
-}
-
-/* We have no need to default values of symbols.  */
-
-symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-#if defined (OBJ_SOM) || defined (ELF_ARG_RELOC)
-#define nonzero_dibits(x) \
-  ((x) | (((x) & 0x55555555) << 1) | (((x) & 0xAAAAAAAA) >> 1))
-#define arg_reloc_stub_needed(CALLER, CALLEE) \
-  (((CALLER) ^ (CALLEE)) & nonzero_dibits (CALLER) & nonzero_dibits (CALLEE))
-#else
-#define arg_reloc_stub_needed(CALLER, CALLEE) 0
-#endif
-
-/* Apply a fixup to an instruction.  */
-
-void
-md_apply_fix (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  char *fixpos;
-  struct hppa_fix_struct *hppa_fixP;
-  offsetT new_val;
-  int insn, val, fmt;
-
-  /* SOM uses R_HPPA_ENTRY and R_HPPA_EXIT relocations which can
-     never be "applied" (they are just markers).  Likewise for
-     R_HPPA_BEGIN_BRTAB and R_HPPA_END_BRTAB.  */
-#ifdef OBJ_SOM
-  if (fixP->fx_r_type == R_HPPA_ENTRY
-      || fixP->fx_r_type == R_HPPA_EXIT
-      || fixP->fx_r_type == R_HPPA_BEGIN_BRTAB
-      || fixP->fx_r_type == R_HPPA_END_BRTAB
-      || fixP->fx_r_type == R_HPPA_BEGIN_TRY)
-    return;
-
-  /* Disgusting.  We must set fx_offset ourselves -- R_HPPA_END_TRY
-     fixups are considered not adjustable, which in turn causes
-     adjust_reloc_syms to not set fx_offset.  Ugh.  */
-  if (fixP->fx_r_type == R_HPPA_END_TRY)
-    {
-      fixP->fx_offset = * valP;
-      return;
-    }
-#endif
-#ifdef OBJ_ELF
-  if (fixP->fx_r_type == (int) R_PARISC_GNU_VTENTRY
-      || fixP->fx_r_type == (int) R_PARISC_GNU_VTINHERIT)
-    return;
-#endif
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-
-  /* There should be a HPPA specific fixup associated with the GAS fixup.  */
-  hppa_fixP = (struct hppa_fix_struct *) fixP->tc_fix_data;
-  if (hppa_fixP == NULL)
-    {
-      as_bad_where (fixP->fx_file, fixP->fx_line,
-		    _("no hppa_fixup entry for fixup type 0x%x"),
-		    fixP->fx_r_type);
-      return;
-    }
-
-  fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
-
-  if (fixP->fx_size != 4 || hppa_fixP->fx_r_format == 32)
-    {
-      /* Handle constant output. */
-      number_to_chars_bigendian (fixpos, *valP, fixP->fx_size);
-      return;
-    }
-
-  insn = bfd_get_32 (stdoutput, fixpos);
-  fmt = bfd_hppa_insn2fmt (stdoutput, insn);
-
-  /* If there is a symbol associated with this fixup, then it's something
-     which will need a SOM relocation (except for some PC-relative relocs).
-     In such cases we should treat the "val" or "addend" as zero since it
-     will be added in as needed from fx_offset in tc_gen_reloc.  */
-  if ((fixP->fx_addsy != NULL
-       || fixP->fx_r_type == (int) R_HPPA_NONE)
-#ifdef OBJ_SOM
-      && fmt != 32
-#endif
-      )
-    new_val = ((fmt == 12 || fmt == 17 || fmt == 22) ? 8 : 0);
-#ifdef OBJ_SOM
-  /* These field selectors imply that we do not want an addend.  */
-  else if (hppa_fixP->fx_r_field == e_psel
-	   || hppa_fixP->fx_r_field == e_rpsel
-	   || hppa_fixP->fx_r_field == e_lpsel
-	   || hppa_fixP->fx_r_field == e_tsel
-	   || hppa_fixP->fx_r_field == e_rtsel
-	   || hppa_fixP->fx_r_field == e_ltsel)
-    new_val = ((fmt == 12 || fmt == 17 || fmt == 22) ? 8 : 0);
-#endif
-  else
-    new_val = hppa_field_adjust (* valP, 0, hppa_fixP->fx_r_field);
-
-  /* Handle pc-relative exceptions from above.  */
-  if ((fmt == 12 || fmt == 17 || fmt == 22)
-      && fixP->fx_addsy
-      && fixP->fx_pcrel
-      && !arg_reloc_stub_needed (symbol_arg_reloc_info (fixP->fx_addsy),
-				 hppa_fixP->fx_arg_reloc)
-#ifdef OBJ_ELF
-      && (* valP - 8 + 8192 < 16384
-	  || (fmt == 17 && * valP - 8 + 262144 < 524288)
-	  || (fmt == 22 && * valP - 8 + 8388608 < 16777216))
-#endif
+	      last_call_info->start_symbol = label_symbol->lss_label;
+	      symbol_get_bfdsym (label_symbol->lss_label)->flags
+		|= BSF_FUNCTION;
 #ifdef OBJ_SOM
-      && (* valP - 8 + 262144 < 524288
-	  || (fmt == 22 && * valP - 8 + 8388608 < 16777216))
-#endif
-      && !S_IS_EXTERNAL (fixP->fx_addsy)
-      && !S_IS_WEAK (fixP->fx_addsy)
-      && S_GET_SEGMENT (fixP->fx_addsy) == hppa_fixP->segment
-      && !(fixP->fx_subsy
-	   && S_GET_SEGMENT (fixP->fx_subsy) != hppa_fixP->segment))
-    {
-      new_val = hppa_field_adjust (* valP, 0, hppa_fixP->fx_r_field);
-    }
-
-  switch (fmt)
-    {
-    case 10:
-      CHECK_FIELD_WHERE (new_val, 8191, -8192,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val;
-
-      insn = (insn & ~ 0x3ff1) | (((val & 0x1ff8) << 1)
-				  | ((val & 0x2000) >> 13));
-      break;
-    case -11:
-      CHECK_FIELD_WHERE (new_val, 8191, -8192,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val;
-
-      insn = (insn & ~ 0x3ff9) | (((val & 0x1ffc) << 1)
-				  | ((val & 0x2000) >> 13));
-      break;
-      /* Handle all opcodes with the 'j' operand type.  */
-    case 14:
-      CHECK_FIELD_WHERE (new_val, 8191, -8192,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val;
-
-      insn = ((insn & ~ 0x3fff) | low_sign_unext (val, 14));
-      break;
-
-      /* Handle all opcodes with the 'k' operand type.  */
-    case 21:
-      CHECK_FIELD_WHERE (new_val, 1048575, -1048576,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val;
-
-      insn = (insn & ~ 0x1fffff) | re_assemble_21 (val);
-      break;
-
-      /* Handle all the opcodes with the 'i' operand type.  */
-    case 11:
-      CHECK_FIELD_WHERE (new_val, 1023, -1024,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val;
-
-      insn = (insn & ~ 0x7ff) | low_sign_unext (val, 11);
-      break;
-
-      /* Handle all the opcodes with the 'w' operand type.  */
-    case 12:
-      CHECK_FIELD_WHERE (new_val - 8, 8191, -8192,
-			 fixP->fx_file, fixP->fx_line);
-      val = new_val - 8;
-
-      insn = (insn & ~ 0x1ffd) | re_assemble_12 (val >> 2);
-      break;
-
-      /* Handle some of the opcodes with the 'W' operand type.  */
-    case 17:
-      {
-	offsetT distance = * valP;
-
-	/* If this is an absolute branch (ie no link) with an out of
-	   range target, then we want to complain.  */
-	if (fixP->fx_r_type == (int) R_HPPA_PCREL_CALL
-	    && (insn & 0xffe00000) == 0xe8000000)
-	  CHECK_FIELD_WHERE (distance - 8, 262143, -262144,
-			     fixP->fx_file, fixP->fx_line);
-
-	CHECK_FIELD_WHERE (new_val - 8, 262143, -262144,
-			   fixP->fx_file, fixP->fx_line);
-	val = new_val - 8;
-
-	insn = (insn & ~ 0x1f1ffd) | re_assemble_17 (val >> 2);
-	break;
-      }
-
-    case 22:
-      {
-	offsetT distance = * valP;
-
-	/* If this is an absolute branch (ie no link) with an out of
-	   range target, then we want to complain.  */
-	if (fixP->fx_r_type == (int) R_HPPA_PCREL_CALL
-	    && (insn & 0xffe00000) == 0xe8000000)
-	  CHECK_FIELD_WHERE (distance - 8, 8388607, -8388608,
-			     fixP->fx_file, fixP->fx_line);
-
-	CHECK_FIELD_WHERE (new_val - 8, 8388607, -8388608,
-			   fixP->fx_file, fixP->fx_line);
-	val = new_val - 8;
-
-	insn = (insn & ~ 0x3ff1ffd) | re_assemble_22 (val >> 2);
-	break;
-      }
-
-    case -10:
-      val = new_val;
-      insn = (insn & ~ 0xfff1) | re_assemble_16 (val & -8);
-      break;
-
-    case -16:
-      val = new_val;
-      insn = (insn & ~ 0xfff9) | re_assemble_16 (val & -4);
-      break;
-
-    case 16:
-      val = new_val;
-      insn = (insn & ~ 0xffff) | re_assemble_16 (val);
-      break;
-
-    case 32:
-      insn = new_val;
-      break;
-
-    default:
-      as_bad_where (fixP->fx_file, fixP->fx_line,
-		    _("Unknown relocation encountered in md_apply_fix."));
-      return;
-    }
-
-  /* Insert the relocation.  */
-  bfd_put_32 (stdoutput, insn, fixpos);
-}
-
-/* Exactly what point is a PC-relative offset relative TO?
-   On the PA, they're relative to the address of the offset.  */
-
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  return fixP->fx_where + fixP->fx_frag->fr_address;
-}
-
-/* Return nonzero if the input line pointer is at the end of
-   a statement.  */
-
-static int
-is_end_of_statement ()
-{
-  return ((*input_line_pointer == '\n')
-	  || (*input_line_pointer == ';')
-	  || (*input_line_pointer == '!'));
-}
-
-/* Read a number from S.  The number might come in one of many forms,
-   the most common will be a hex or decimal constant, but it could be
-   a pre-defined register (Yuk!), or an absolute symbol.
-
-   Return 1 on success or 0 on failure.  If STRICT, then a missing
-   register prefix will cause a failure.  The number itself is
-   returned in `pa_number'.
-
-   IS_FLOAT indicates that a PA-89 FP register number should be
-   parsed;  A `l' or `r' suffix is checked for if but 2 of IS_FLOAT is
-   not set.
-
-   pa_parse_number can not handle negative constants and will fail
-   horribly if it is passed such a constant.  */
-
-static int
-pa_parse_number (s, is_float)
-     char **s;
-     int is_float;
-{
-  int num;
-  char *name;
-  char c;
-  symbolS *sym;
-  int status;
-  char *p = *s;
-  bfd_boolean have_prefix;
-
-  /* Skip whitespace before the number.  */
-  while (*p == ' ' || *p == '\t')
-    p = p + 1;
-
-  pa_number = -1;
-  have_prefix = 0;
-  num = 0;
-  if (!strict && ISDIGIT (*p))
-    {
-      /* Looks like a number.  */
-
-      if (*p == '0' && (*(p + 1) == 'x' || *(p + 1) == 'X'))
-	{
-	  /* The number is specified in hex.  */
-	  p += 2;
-	  while (ISDIGIT (*p) || ((*p >= 'a') && (*p <= 'f'))
-		 || ((*p >= 'A') && (*p <= 'F')))
-	    {
-	      if (ISDIGIT (*p))
-		num = num * 16 + *p - '0';
-	      else if (*p >= 'a' && *p <= 'f')
-		num = num * 16 + *p - 'a' + 10;
-	      else
-		num = num * 16 + *p - 'A' + 10;
-	      ++p;
-	    }
-	}
-      else
-	{
-	  /* The number is specified in decimal.  */
-	  while (ISDIGIT (*p))
-	    {
-	      num = num * 10 + *p - '0';
-	      ++p;
-	    }
-	}
-
-      pa_number = num;
-
-      /* Check for a `l' or `r' suffix.  */
-      if (is_float)
-	{
-	  pa_number += FP_REG_BASE;
-	  if (! (is_float & 2))
-	    {
-	      if (IS_R_SELECT (p))
-		{
-		  pa_number += FP_REG_RSEL;
-		  ++p;
-		}
-	      else if (IS_L_SELECT (p))
+	      /* Also handle allocation of a fixup to hold the unwind
+		 information when the label appears after the proc/procend.  */
+	      if (within_entry_exit)
 		{
-		  ++p;
-		}
-	    }
-	}
-    }
-  else if (*p == '%')
-    {
-      /* The number might be a predefined register.  */
-      have_prefix = 1;
-      name = p;
-      p++;
-      c = *p;
-      /* Tege hack: Special case for general registers as the general
-         code makes a binary search with case translation, and is VERY
-         slow.  */
-      if (c == 'r')
-	{
-	  p++;
-	  if (*p == 'e' && *(p + 1) == 't'
-	      && (*(p + 2) == '0' || *(p + 2) == '1'))
-	    {
-	      p += 2;
-	      num = *p - '0' + 28;
-	      p++;
-	    }
-	  else if (*p == 'p')
-	    {
-	      num = 2;
-	      p++;
-	    }
-	  else if (!ISDIGIT (*p))
-	    {
-	      if (print_errors)
-		as_bad (_("Undefined register: '%s'."), name);
-	      num = -1;
-	    }
-	  else
-	    {
-	      do
-		num = num * 10 + *p++ - '0';
-	      while (ISDIGIT (*p));
-	    }
-	}
-      else
-	{
-	  /* Do a normal register search.  */
-	  while (is_part_of_name (c))
-	    {
-	      p = p + 1;
-	      c = *p;
-	    }
-	  *p = 0;
-	  status = reg_name_search (name);
-	  if (status >= 0)
-	    num = status;
-	  else
-	    {
-	      if (print_errors)
-		as_bad (_("Undefined register: '%s'."), name);
-	      num = -1;
-	    }
-	  *p = c;
-	}
+		  char *where;
+		  unsigned int u;
 
-      pa_number = num;
-    }
-  else
-    {
-      /* And finally, it could be a symbol in the absolute section which
-         is effectively a constant, or a register alias symbol.  */
-      name = p;
-      c = *p;
-      while (is_part_of_name (c))
-	{
-	  p = p + 1;
-	  c = *p;
-	}
-      *p = 0;
-      if ((sym = symbol_find (name)) != NULL)
-	{
-	  if (S_GET_SEGMENT (sym) == reg_section)
-	    {
-	      num = S_GET_VALUE (sym);
-	      /* Well, we don't really have one, but we do have a
-		 register, so...  */
-	      have_prefix = TRUE;
-	    }
-	  else if (S_GET_SEGMENT (sym) == &bfd_abs_section)
-	    num = S_GET_VALUE (sym);
-	  else if (!strict)
-	    {
-	      if (print_errors)
-		as_bad (_("Non-absolute symbol: '%s'."), name);
-	      num = -1;
+		  where = frag_more (0);
+		  u = UNWIND_LOW32 (&last_call_info->ci_unwind.descriptor);
+		  fix_new_hppa (frag_now, where - frag_now->fr_literal, 0,
+				NULL, (offsetT) 0, NULL,
+				0, R_HPPA_ENTRY, e_fsel, 0, 0, u);
+		}
+#endif
 	    }
-	}
-      else if (!strict)
-	{
-	  /* There is where we'd come for an undefined symbol
-	     or for an empty string.  For an empty string we
-	     will return zero.  That's a concession made for
-	     compatibility with the braindamaged HP assemblers.  */
-	  if (*name == 0)
-	    num = 0;
 	  else
-	    {
-	      if (print_errors)
-		as_bad (_("Undefined absolute constant: '%s'."), name);
-	      num = -1;
-	    }
-	}
-      *p = c;
-
-      pa_number = num;
-    }
-
-  if (!strict || have_prefix)
-    {
-      *s = p;
-      return 1;
-    }
-  return 0;
-}
-
-#define REG_NAME_CNT	(sizeof (pre_defined_registers) / sizeof (struct pd_reg))
-
-/* Given NAME, find the register number associated with that name, return
-   the integer value associated with the given name or -1 on failure.  */
-
-static int
-reg_name_search (name)
-     char *name;
-{
-  int middle, low, high;
-  int cmp;
-
-  low = 0;
-  high = REG_NAME_CNT - 1;
-
-  do
-    {
-      middle = (low + high) / 2;
-      cmp = strcasecmp (name, pre_defined_registers[middle].name);
-      if (cmp < 0)
-	high = middle - 1;
-      else if (cmp > 0)
-	low = middle + 1;
-      else
-	return pre_defined_registers[middle].value;
-    }
-  while (low <= high);
-
-  return -1;
-}
-
-/* Return nonzero if the given INSN and L/R information will require
-   a new PA-1.1 opcode.  */
-
-static int
-need_pa11_opcode ()
-{
-  if ((pa_number & FP_REG_RSEL) != 0
-      && !(the_insn.fpof1 == DBL && the_insn.fpof2 == DBL))
-    {
-      /* If this instruction is specific to a particular architecture,
-	 then set a new architecture.  */
-      if (bfd_get_mach (stdoutput) < pa11)
-	{
-	  if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, pa11))
-	    as_warn (_("could not update architecture and machine"));
-	}
-      return TRUE;
-    }
-  else
-    return FALSE;
-}
-
-/* Parse a condition for a fcmp instruction.  Return the numerical
-   code associated with the condition.  */
-
-static int
-pa_parse_fp_cmp_cond (s)
-     char **s;
-{
-  int cond, i;
-
-  cond = 0;
-
-  for (i = 0; i < 32; i++)
-    {
-      if (strncasecmp (*s, fp_cond_map[i].string,
-		       strlen (fp_cond_map[i].string)) == 0)
-	{
-	  cond = fp_cond_map[i].cond;
-	  *s += strlen (fp_cond_map[i].string);
-	  /* If not a complete match, back up the input string and
-	     report an error.  */
-	  if (**s != ' ' && **s != '\t')
-	    {
-	      *s -= strlen (fp_cond_map[i].string);
-	      break;
-	    }
-	  while (**s == ' ' || **s == '\t')
-	    *s = *s + 1;
-	  return cond;
-	}
-    }
-
-  as_bad (_("Invalid FP Compare Condition: %s"), *s);
-
-  /* Advance over the bogus completer.  */
-  while (**s != ',' && **s != ' ' && **s != '\t')
-    *s += 1;
-
-  return 0;
-}
-
-/* Parse a graphics test complete for ftest.  */
-
-static int
-pa_parse_ftest_gfx_completer (s)
-     char **s;
-{
-  int value;
-
-  value = 0;
-  if (strncasecmp (*s, "acc8", 4) == 0)
-    {
-      value = 5;
-      *s += 4;
-    }
-  else if (strncasecmp (*s, "acc6", 4) == 0)
-    {
-      value = 9;
-      *s += 4;
-    }
-  else if (strncasecmp (*s, "acc4", 4) == 0)
-    {
-      value = 13;
-      *s += 4;
-    }
-  else if (strncasecmp (*s, "acc2", 4) == 0)
-    {
-      value = 17;
-      *s += 4;
-    }
-  else if (strncasecmp (*s, "acc", 3) == 0)
-    {
-      value = 1;
-      *s += 3;
-    }
-  else if (strncasecmp (*s, "rej8", 4) == 0)
-    {
-      value = 6;
-      *s += 4;
-    }
-  else if (strncasecmp (*s, "rej", 3) == 0)
-    {
-      value = 2;
-      *s += 3;
-    }
-  else
-    {
-      value = 0;
-      as_bad (_("Invalid FTEST completer: %s"), *s);
-    }
-
-  return value;
-}
-
-/* Parse an FP operand format completer returning the completer
-   type.  */
-
-static fp_operand_format
-pa_parse_fp_cnv_format (s)
-     char **s;
-{
-  int format;
-
-  format = SGL;
-  if (**s == ',')
-    {
-      *s += 1;
-      if (strncasecmp (*s, "sgl", 3) == 0)
-	{
-	  format = SGL;
-	  *s += 4;
-	}
-      else if (strncasecmp (*s, "dbl", 3) == 0)
-	{
-	  format = DBL;
-	  *s += 4;
-	}
-      else if (strncasecmp (*s, "quad", 4) == 0)
-	{
-	  format = QUAD;
-	  *s += 5;
-	}
-      else if (strncasecmp (*s, "w", 1) == 0)
-	{
-	  format = W;
-	  *s += 2;
-	}
-      else if (strncasecmp (*s, "uw", 2) == 0)
-	{
-	  format = UW;
-	  *s += 3;
-	}
-      else if (strncasecmp (*s, "dw", 2) == 0)
-	{
-	  format = DW;
-	  *s += 3;
-	}
-      else if (strncasecmp (*s, "udw", 3) == 0)
-	{
-	  format = UDW;
-	  *s += 4;
-	}
-      else if (strncasecmp (*s, "qw", 2) == 0)
-	{
-	  format = QW;
-	  *s += 3;
-	}
-      else if (strncasecmp (*s, "uqw", 3) == 0)
-	{
-	  format = UQW;
-	  *s += 4;
-	}
-      else
-	{
-	  format = ILLEGAL_FMT;
-	  as_bad (_("Invalid FP Operand Format: %3s"), *s);
-	}
-    }
-
-  return format;
-}
-
-/* Parse an FP operand format completer returning the completer
-   type.  */
-
-static fp_operand_format
-pa_parse_fp_format (s)
-     char **s;
-{
-  int format;
-
-  format = SGL;
-  if (**s == ',')
-    {
-      *s += 1;
-      if (strncasecmp (*s, "sgl", 3) == 0)
-	{
-	  format = SGL;
-	  *s += 4;
-	}
-      else if (strncasecmp (*s, "dbl", 3) == 0)
-	{
-	  format = DBL;
-	  *s += 4;
-	}
-      else if (strncasecmp (*s, "quad", 4) == 0)
-	{
-	  format = QUAD;
-	  *s += 5;
+	    as_bad (_("Missing function name for .PROC (corrupted label chain)"));
 	}
       else
-	{
-	  format = ILLEGAL_FMT;
-	  as_bad (_("Invalid FP Operand Format: %3s"), *s);
-	}
+	as_bad (_("Missing function name for .PROC"));
     }
 
-  return format;
-}
-
-/* Convert from a selector string into a selector type.  */
-
-static int
-pa_chk_field_selector (str)
-     char **str;
-{
-  int middle, low, high;
-  int cmp;
-  char name[4];
+  /* Assemble the instruction.  Results are saved into "the_insn".  */
+  pa_ip (str);
 
-  /* Read past any whitespace.  */
-  /* FIXME: should we read past newlines and formfeeds??? */
-  while (**str == ' ' || **str == '\t' || **str == '\n' || **str == '\f')
-    *str = *str + 1;
+  /* Get somewhere to put the assembled instruction.  */
+  to = frag_more (4);
 
-  if ((*str)[1] == '\'' || (*str)[1] == '%')
-    name[0] = TOLOWER ((*str)[0]),
-    name[1] = 0;
-  else if ((*str)[2] == '\'' || (*str)[2] == '%')
-    name[0] = TOLOWER ((*str)[0]),
-    name[1] = TOLOWER ((*str)[1]),
-    name[2] = 0;
-  else if ((*str)[3] == '\'' || (*str)[3] == '%')
-    name[0] = TOLOWER ((*str)[0]),
-    name[1] = TOLOWER ((*str)[1]),
-    name[2] = TOLOWER ((*str)[2]),
-    name[3] = 0;
-  else
-    return e_fsel;
+  /* Output the opcode.  */
+  md_number_to_chars (to, the_insn.opcode, 4);
 
-  low = 0;
-  high = sizeof (selector_table) / sizeof (struct selector_entry) - 1;
+  /* If necessary output more stuff.  */
+  if (the_insn.reloc != R_HPPA_NONE)
+    fix_new_hppa (frag_now, (to - frag_now->fr_literal), 4, NULL,
+		  (offsetT) 0, &the_insn.exp, the_insn.pcrel,
+		  the_insn.reloc, the_insn.field_selector,
+		  the_insn.format, the_insn.arg_reloc, 0);
 
-  do
-    {
-      middle = (low + high) / 2;
-      cmp = strcmp (name, selector_table[middle].prefix);
-      if (cmp < 0)
-	high = middle - 1;
-      else if (cmp > 0)
-	low = middle + 1;
-      else
-	{
-	  *str += strlen (name) + 1;
-#ifndef OBJ_SOM
-	  if (selector_table[middle].field_selector == e_nsel)
-	    return e_fsel;
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (4);
 #endif
-	  return selector_table[middle].field_selector;
-	}
-    }
-  while (low <= high);
-
-  return e_fsel;
-}
-
-/* Mark (via expr_end) the end of an expression (I think).  FIXME.  */
-
-static int
-get_expression (str)
-     char *str;
-{
-  char *save_in;
-  asection *seg;
-
-  save_in = input_line_pointer;
-  input_line_pointer = str;
-  seg = expression (&the_insn.exp);
-  if (!(seg == absolute_section
-	|| seg == undefined_section
-	|| SEG_NORMAL (seg)))
-    {
-      as_warn (_("Bad segment in expression."));
-      expr_end = input_line_pointer;
-      input_line_pointer = save_in;
-      return 1;
-    }
-  expr_end = input_line_pointer;
-  input_line_pointer = save_in;
-  return 0;
-}
-
-/* Mark (via expr_end) the end of an absolute expression.  FIXME.  */
-static int
-pa_get_absolute_expression (insn, strp)
-     struct pa_it *insn;
-     char **strp;
-{
-  char *save_in;
-
-  insn->field_selector = pa_chk_field_selector (strp);
-  save_in = input_line_pointer;
-  input_line_pointer = *strp;
-  expression (&insn->exp);
-  /* This is not perfect, but is a huge improvement over doing nothing.
-
-     The PA assembly syntax is ambiguous in a variety of ways.  Consider
-     this string "4 %r5"  Is that the number 4 followed by the register
-     r5, or is that 4 MOD r5?
-
-     If we get a modulo expression when looking for an absolute, we try
-     again cutting off the input string at the first whitespace character.  */
-  if (insn->exp.X_op == O_modulus)
-    {
-      char *s, c;
-      int retval;
-
-      input_line_pointer = *strp;
-      s = *strp;
-      while (*s != ',' && *s != ' ' && *s != '\t')
-	s++;
-
-      c = *s;
-      *s = 0;
-
-      retval = pa_get_absolute_expression (insn, strp);
-
-      input_line_pointer = save_in;
-      *s = c;
-      return evaluate_absolute (insn);
-    }
-  /* When in strict mode we have a non-match, fix up the pointers
-     and return to our caller.  */
-  if (insn->exp.X_op != O_constant && strict)
-    {
-      expr_end = input_line_pointer;
-      input_line_pointer = save_in;
-      return 0;
-    }
-  if (insn->exp.X_op != O_constant)
-    {
-      as_bad (_("Bad segment (should be absolute)."));
-      expr_end = input_line_pointer;
-      input_line_pointer = save_in;
-      return 0;
-    }
-  expr_end = input_line_pointer;
-  input_line_pointer = save_in;
-  return evaluate_absolute (insn);
-}
-
-/* Evaluate an absolute expression EXP which may be modified by
-   the selector FIELD_SELECTOR.  Return the value of the expression.  */
-static int
-evaluate_absolute (insn)
-     struct pa_it *insn;
-{
-  offsetT value;
-  expressionS exp;
-  int field_selector = insn->field_selector;
-
-  exp = insn->exp;
-  value = exp.X_add_number;
-
-  return hppa_field_adjust (0, value, field_selector);
-}
-
-/* Given an argument location specification return the associated
-   argument location number.  */
-
-static unsigned int
-pa_build_arg_reloc (type_name)
-     char *type_name;
-{
-
-  if (strncasecmp (type_name, "no", 2) == 0)
-    return 0;
-  if (strncasecmp (type_name, "gr", 2) == 0)
-    return 1;
-  else if (strncasecmp (type_name, "fr", 2) == 0)
-    return 2;
-  else if (strncasecmp (type_name, "fu", 2) == 0)
-    return 3;
-  else
-    as_bad (_("Invalid argument location: %s\n"), type_name);
-
-  return 0;
-}
-
-/* Encode and return an argument relocation specification for
-   the given register in the location specified by arg_reloc.  */
-
-static unsigned int
-pa_align_arg_reloc (reg, arg_reloc)
-     unsigned int reg;
-     unsigned int arg_reloc;
-{
-  unsigned int new_reloc;
-
-  new_reloc = arg_reloc;
-  switch (reg)
-    {
-    case 0:
-      new_reloc <<= 8;
-      break;
-    case 1:
-      new_reloc <<= 6;
-      break;
-    case 2:
-      new_reloc <<= 4;
-      break;
-    case 3:
-      new_reloc <<= 2;
-      break;
-    default:
-      as_bad (_("Invalid argument description: %d"), reg);
-    }
-
-  return new_reloc;
-}
-
-/* Parse a PA nullification completer (,n).  Return nonzero if the
-   completer was found; return zero if no completer was found.  */
-
-static int
-pa_parse_nullif (s)
-     char **s;
-{
-  int nullif;
-
-  nullif = 0;
-  if (**s == ',')
-    {
-      *s = *s + 1;
-      if (strncasecmp (*s, "n", 1) == 0)
-	nullif = 1;
-      else
-	{
-	  as_bad (_("Invalid Nullification: (%c)"), **s);
-	  nullif = 0;
-	}
-      *s = *s + 1;
-    }
-
-  return nullif;
-}
-
-/* Parse a non-negated compare/subtract completer returning the
-   number (for encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_nonneg_cmpsub_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-  char *save_s = *s;
-  int nullify = 0;
-
-  cmpltr = 0;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-
-      if (strcmp (name, "=") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, "<") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, "<=") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcmp (name, "<<") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcmp (name, "<<=") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "sv") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "od") == 0)
-	{
-	  cmpltr = 7;
-	}
-      /* If we have something like addb,n then there is no condition
-         completer.  */
-      else if (strcasecmp (name, "n") == 0)
-	{
-	  cmpltr = 0;
-	  nullify = 1;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  /* Reset pointers if this was really a ,n for a branch instruction.  */
-  if (nullify)
-    *s = save_s;
-
-  return cmpltr;
-}
-
-/* Parse a negated compare/subtract completer returning the
-   number (for encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_neg_cmpsub_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-  char *save_s = *s;
-  int nullify = 0;
-
-  cmpltr = 0;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-
-      if (strcasecmp (name, "tr") == 0)
-	{
-	  cmpltr = 0;
-	}
-      else if (strcmp (name, "<>") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, ">=") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, ">") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcmp (name, ">>=") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcmp (name, ">>") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "nsv") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "ev") == 0)
-	{
-	  cmpltr = 7;
-	}
-      /* If we have something like addb,n then there is no condition
-         completer.  */
-      else if (strcasecmp (name, "n") == 0)
-	{
-	  cmpltr = 0;
-	  nullify = 1;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  /* Reset pointers if this was really a ,n for a branch instruction.  */
-  if (nullify)
-    *s = save_s;
-
-  return cmpltr;
-}
-
-/* Parse a 64 bit compare and branch completer returning the number (for
-   encoding in instructions) of the given completer.
-
-   Nonnegated comparisons are returned as 0-7, negated comparisons are
-   returned as 8-15.  */
-
-static int
-pa_parse_cmpb_64_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-
-  cmpltr = -1;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-
-      if (strcmp (name, "*") == 0)
-	{
-	  cmpltr = 0;
-	}
-      else if (strcmp (name, "*=") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, "*<") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, "*<=") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcmp (name, "*<<") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcmp (name, "*<<=") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "*sv") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "*od") == 0)
-	{
-	  cmpltr = 7;
-	}
-      else if (strcasecmp (name, "*tr") == 0)
-	{
-	  cmpltr = 8;
-	}
-      else if (strcmp (name, "*<>") == 0)
-	{
-	  cmpltr = 9;
-	}
-      else if (strcmp (name, "*>=") == 0)
-	{
-	  cmpltr = 10;
-	}
-      else if (strcmp (name, "*>") == 0)
-	{
-	  cmpltr = 11;
-	}
-      else if (strcmp (name, "*>>=") == 0)
-	{
-	  cmpltr = 12;
-	}
-      else if (strcmp (name, "*>>") == 0)
-	{
-	  cmpltr = 13;
-	}
-      else if (strcasecmp (name, "*nsv") == 0)
-	{
-	  cmpltr = 14;
-	}
-      else if (strcasecmp (name, "*ev") == 0)
-	{
-	  cmpltr = 15;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  return cmpltr;
-}
-
-/* Parse a 64 bit compare immediate and branch completer returning the number
-   (for encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_cmpib_64_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-
-  cmpltr = -1;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-
-      if (strcmp (name, "*<<") == 0)
-	{
-	  cmpltr = 0;
-	}
-      else if (strcmp (name, "*=") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, "*<") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, "*<=") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcmp (name, "*>>=") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcmp (name, "*<>") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "*>=") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "*>") == 0)
-	{
-	  cmpltr = 7;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  return cmpltr;
-}
-
-/* Parse a non-negated addition completer returning the number
-   (for encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_nonneg_add_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-  char *save_s = *s;
-  int nullify = 0;
-
-  cmpltr = 0;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-      if (strcmp (name, "=") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, "<") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, "<=") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcasecmp (name, "nuv") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcasecmp (name, "znv") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "sv") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "od") == 0)
-	{
-	  cmpltr = 7;
-	}
-      /* If we have something like addb,n then there is no condition
-         completer.  */
-      else if (strcasecmp (name, "n") == 0)
-	{
-	  cmpltr = 0;
-	  nullify = 1;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  /* Reset pointers if this was really a ,n for a branch instruction.  */
-  if (nullify)
-    *s = save_s;
-
-  return cmpltr;
-}
-
-/* Parse a negated addition completer returning the number
-   (for encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_neg_add_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-  char *save_s = *s;
-  int nullify = 0;
-
-  cmpltr = 0;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-      if (strcasecmp (name, "tr") == 0)
-	{
-	  cmpltr = 0;
-	}
-      else if (strcmp (name, "<>") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, ">=") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, ">") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcasecmp (name, "uv") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcasecmp (name, "vnz") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "nsv") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "ev") == 0)
-	{
-	  cmpltr = 7;
-	}
-      /* If we have something like addb,n then there is no condition
-         completer.  */
-      else if (strcasecmp (name, "n") == 0)
-	{
-	  cmpltr = 0;
-	  nullify = 1;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  /* Reset pointers if this was really a ,n for a branch instruction.  */
-  if (nullify)
-    *s = save_s;
-
-  return cmpltr;
-}
-
-/* Parse a 64 bit wide mode add and branch completer returning the number (for
-   encoding in instructions) of the given completer.  */
-
-static int
-pa_parse_addb_64_cmpltr (s)
-     char **s;
-{
-  int cmpltr;
-  char *name = *s + 1;
-  char c;
-  char *save_s = *s;
-  int nullify = 0;
-
-  cmpltr = 0;
-  if (**s == ',')
-    {
-      *s += 1;
-      while (**s != ',' && **s != ' ' && **s != '\t')
-	*s += 1;
-      c = **s;
-      **s = 0x00;
-      if (strcmp (name, "=") == 0)
-	{
-	  cmpltr = 1;
-	}
-      else if (strcmp (name, "<") == 0)
-	{
-	  cmpltr = 2;
-	}
-      else if (strcmp (name, "<=") == 0)
-	{
-	  cmpltr = 3;
-	}
-      else if (strcasecmp (name, "nuv") == 0)
-	{
-	  cmpltr = 4;
-	}
-      else if (strcasecmp (name, "*=") == 0)
-	{
-	  cmpltr = 5;
-	}
-      else if (strcasecmp (name, "*<") == 0)
-	{
-	  cmpltr = 6;
-	}
-      else if (strcasecmp (name, "*<=") == 0)
-	{
-	  cmpltr = 7;
-	}
-      else if (strcmp (name, "tr") == 0)
-	{
-	  cmpltr = 8;
-	}
-      else if (strcmp (name, "<>") == 0)
-	{
-	  cmpltr = 9;
-	}
-      else if (strcmp (name, ">=") == 0)
-	{
-	  cmpltr = 10;
-	}
-      else if (strcmp (name, ">") == 0)
-	{
-	  cmpltr = 11;
-	}
-      else if (strcasecmp (name, "uv") == 0)
-	{
-	  cmpltr = 12;
-	}
-      else if (strcasecmp (name, "*<>") == 0)
-	{
-	  cmpltr = 13;
-	}
-      else if (strcasecmp (name, "*>=") == 0)
-	{
-	  cmpltr = 14;
-	}
-      else if (strcasecmp (name, "*>") == 0)
-	{
-	  cmpltr = 15;
-	}
-      /* If we have something like addb,n then there is no condition
-         completer.  */
-      else if (strcasecmp (name, "n") == 0)
-	{
-	  cmpltr = 0;
-	  nullify = 1;
-	}
-      else
-	{
-	  cmpltr = -1;
-	}
-      **s = c;
-    }
-
-  /* Reset pointers if this was really a ,n for a branch instruction.  */
-  if (nullify)
-    *s = save_s;
-
-  return cmpltr;
 }
 
 #ifdef OBJ_SOM
 /* Handle an alignment directive.  Special so that we can update the
    alignment of the subspace if necessary.  */
 static void
-pa_align (bytes)
-     int bytes;
+pa_align (int bytes)
 {
   /* We must have a valid space and subspace.  */
   pa_check_current_space_and_subspace ();
@@ -5950,8 +5815,7 @@ pa_align (bytes)
 /* Handle a .BLOCK type pseudo-op.  */
 
 static void
-pa_block (z)
-     int z ATTRIBUTE_UNUSED;
+pa_block (int z ATTRIBUTE_UNUSED)
 {
   unsigned int temp_size;
 
@@ -5981,8 +5845,7 @@ pa_block (z)
 /* Handle a .begin_brtab and .end_brtab pseudo-op.  */
 
 static void
-pa_brtab (begin)
-     int begin ATTRIBUTE_UNUSED;
+pa_brtab (int begin ATTRIBUTE_UNUSED)
 {
 
 #ifdef OBJ_SOM
@@ -6002,8 +5865,7 @@ pa_brtab (begin)
 /* Handle a .begin_try and .end_try pseudo-op.  */
 
 static void
-pa_try (begin)
-     int begin ATTRIBUTE_UNUSED;
+pa_try (int begin ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   expressionS exp;
@@ -6024,29 +5886,11 @@ pa_try (begin)
   demand_empty_rest_of_line ();
 }
 
-/* Handle a .CALL pseudo-op.  This involves storing away information
-   about where arguments are to be found so the linker can detect
-   (and correct) argument location mismatches between caller and callee.  */
-
-static void
-pa_call (unused)
-     int unused ATTRIBUTE_UNUSED;
-{
-#ifdef OBJ_SOM
-  /* We must have a valid space and subspace.  */
-  pa_check_current_space_and_subspace ();
-#endif
-
-  pa_call_args (&last_call_desc);
-  demand_empty_rest_of_line ();
-}
-
 /* Do the dirty work of building a call descriptor which describes
    where the caller placed arguments to a function call.  */
 
 static void
-pa_call_args (call_desc)
-     struct call_desc *call_desc;
+pa_call_args (struct call_desc *call_desc)
 {
   char *name, c, *p;
   unsigned int temp, arg_reloc;
@@ -6089,24 +5933,38 @@ pa_call_args (call_desc)
     }
 }
 
+/* Handle a .CALL pseudo-op.  This involves storing away information
+   about where arguments are to be found so the linker can detect
+   (and correct) argument location mismatches between caller and callee.  */
+
+static void
+pa_call (int unused ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_SOM
+  /* We must have a valid space and subspace.  */
+  pa_check_current_space_and_subspace ();
+#endif
+
+  pa_call_args (&last_call_desc);
+  demand_empty_rest_of_line ();
+}
+
 /* Return TRUE if FRAG1 and FRAG2 are the same.  */
 
-static int
-is_same_frag (frag1, frag2)
-     fragS *frag1;
-     fragS *frag2;
+static bfd_boolean
+is_same_frag (fragS *frag1, fragS *frag2)
 {
 
   if (frag1 == NULL)
-    return (FALSE);
+    return FALSE;
   else if (frag2 == NULL)
-    return (FALSE);
+    return FALSE;
   else if (frag1 == frag2)
-    return (TRUE);
+    return TRUE;
   else if (frag2->fr_type == rs_fill && frag2->fr_fix == 0)
     return (is_same_frag (frag1, frag2->fr_next));
   else
-    return (FALSE);
+    return FALSE;
 }
 
 #ifdef OBJ_ELF
@@ -6116,8 +5974,7 @@ is_same_frag (frag1, frag2)
    of the unwind spaces.  */
 
 static void
-pa_build_unwind_subspace (call_info)
-     struct call_info *call_info;
+pa_build_unwind_subspace (struct call_info *call_info)
 {
   asection *seg, *save_seg;
   subsegT save_subseg;
@@ -6189,8 +6046,7 @@ pa_build_unwind_subspace (call_info)
    .ENTER and .LEAVE.  */
 
 static void
-pa_callinfo (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_callinfo (int unused ATTRIBUTE_UNUSED)
 {
   char *name, c, *p;
   int temp;
@@ -6332,9 +6188,9 @@ pa_callinfo (unused)
 #if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
 /* Switch to the text space.  Like s_text, but delete our
    label when finished.  */
+
 static void
-pa_text (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_text (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   current_space = is_defined_space ("$TEXT$");
@@ -6347,9 +6203,9 @@ pa_text (unused)
 }
 
 /* Switch to the data space.  As usual delete our label.  */
+
 static void
-pa_data (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_data (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   current_space = is_defined_space ("$PRIVATE$");
@@ -6381,8 +6237,7 @@ pa_data (unused)
    This also makes error detection all but impossible.  */
 
 static void
-pa_comm (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_comm (int unused ATTRIBUTE_UNUSED)
 {
   unsigned int size;
   symbolS *symbol;
@@ -6415,16 +6270,15 @@ pa_comm (unused)
 /* Process a .END pseudo-op.  */
 
 static void
-pa_end (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_end (int unused ATTRIBUTE_UNUSED)
 {
   demand_empty_rest_of_line ();
 }
 
 /* Process a .ENTER pseudo-op.  This is not supported.  */
+
 static void
-pa_enter (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_enter (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -6437,9 +6291,9 @@ pa_enter (unused)
 
 /* Process a .ENTRY pseudo-op.  .ENTRY marks the beginning of the
    procedure.  */
+
 static void
-pa_entry (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_entry (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -6486,10 +6340,9 @@ pa_entry (unused)
 static int fudge_reg_expressions;
 
 int
-hppa_force_reg_syms_absolute (resultP, op, rightP)
-     expressionS *resultP;
-     operatorT op ATTRIBUTE_UNUSED;
-     expressionS *rightP;
+hppa_force_reg_syms_absolute (expressionS *resultP,
+			      operatorT op ATTRIBUTE_UNUSED,
+			      expressionS *rightP)
 {
   if (fudge_reg_expressions
       && rightP->X_op == O_register
@@ -6504,8 +6357,7 @@ hppa_force_reg_syms_absolute (resultP, op, rightP)
 /* Handle a .EQU pseudo-op.  */
 
 static void
-pa_equ (reg)
-     int reg;
+pa_equ (int reg)
 {
   label_symbol_struct *label_symbol = pa_get_label ();
   symbolS *symbol;
@@ -6553,12 +6405,75 @@ pa_equ (reg)
   demand_empty_rest_of_line ();
 }
 
+#ifdef OBJ_ELF
+/* Mark the end of a function so that it's possible to compute
+   the size of the function in elf_hppa_final_processing.  */
+
+static void
+hppa_elf_mark_end_of_function (void)
+{
+  /* ELF does not have EXIT relocations.  All we do is create a
+     temporary symbol marking the end of the function.  */
+  char *name;
+
+  if (last_call_info == NULL || last_call_info->start_symbol == NULL)
+    {
+      /* We have already warned about a missing label,
+	 or other problems.  */
+      return;
+    }
+
+  name = xmalloc (strlen ("L$\001end_")
+		  + strlen (S_GET_NAME (last_call_info->start_symbol))
+		  + 1);
+  if (name)
+    {
+      symbolS *symbolP;
+
+      strcpy (name, "L$\001end_");
+      strcat (name, S_GET_NAME (last_call_info->start_symbol));
+
+      /* If we have a .exit followed by a .procend, then the
+	 symbol will have already been defined.  */
+      symbolP = symbol_find (name);
+      if (symbolP)
+	{
+	  /* The symbol has already been defined!  This can
+	     happen if we have a .exit followed by a .procend.
+
+	     This is *not* an error.  All we want to do is free
+	     the memory we just allocated for the name and continue.  */
+	  xfree (name);
+	}
+      else
+	{
+	  /* symbol value should be the offset of the
+	     last instruction of the function */
+	  symbolP = symbol_new (name, now_seg, (valueT) (frag_now_fix () - 4),
+				frag_now);
+
+	  assert (symbolP);
+	  S_CLEAR_EXTERNAL (symbolP);
+	  symbol_table_insert (symbolP);
+	}
+
+      if (symbolP)
+	last_call_info->end_symbol = symbolP;
+      else
+	as_bad (_("Symbol '%s' could not be created."), name);
+
+    }
+  else
+    as_bad (_("No memory for symbol name."));
+}
+#endif
+
 /* Helper function.  Does processing for the end of a function.  This
    usually involves creating some relocations or building special
    symbols to mark the end of the function.  */
 
 static void
-process_exit ()
+process_exit (void)
 {
   char *where;
 
@@ -6590,8 +6505,7 @@ process_exit ()
 /* Process a .EXIT pseudo-op.  */
 
 static void
-pa_exit (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_exit (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -6618,54 +6532,10 @@ pa_exit (unused)
   demand_empty_rest_of_line ();
 }
 
-/* Process a .EXPORT directive.  This makes functions external
-   and provides information such as argument relocation entries
-   to callers.  */
-
-static void
-pa_export (unused)
-     int unused ATTRIBUTE_UNUSED;
-{
-  char *name, c, *p;
-  symbolS *symbol;
-
-  name = input_line_pointer;
-  c = get_symbol_end ();
-  /* Make sure the given symbol exists.  */
-  if ((symbol = symbol_find_or_make (name)) == NULL)
-    {
-      as_bad (_("Cannot define export symbol: %s\n"), name);
-      p = input_line_pointer;
-      *p = c;
-      input_line_pointer++;
-    }
-  else
-    {
-      /* OK.  Set the external bits and process argument relocations.
-         For the HP, weak and global are not mutually exclusive.
-         S_SET_EXTERNAL will not set BSF_GLOBAL if WEAK is set.
-         Call S_SET_EXTERNAL to get the other processing.  Manually
-         set BSF_GLOBAL when we get back.  */
-      S_SET_EXTERNAL (symbol);
-      symbol_get_bfdsym (symbol)->flags |= BSF_GLOBAL;
-      p = input_line_pointer;
-      *p = c;
-      if (!is_end_of_statement ())
-	{
-	  input_line_pointer++;
-	  pa_type_args (symbol, 1);
-	}
-    }
-
-  demand_empty_rest_of_line ();
-}
-
 /* Helper function to process arguments to a .EXPORT pseudo-op.  */
 
 static void
-pa_type_args (symbolP, is_export)
-     symbolS *symbolP;
-     int is_export;
+pa_type_args (symbolS *symbolP, int is_export)
 {
   char *name, c, *p;
   unsigned int temp, arg_reloc;
@@ -6673,7 +6543,6 @@ pa_type_args (symbolP, is_export)
   asymbol *bfdsym = symbol_get_bfdsym (symbolP);
 
   if (strncasecmp (input_line_pointer, "absolute", 8) == 0)
-
     {
       input_line_pointer += 8;
       bfdsym->flags &= ~BSF_FUNCTION;
@@ -6818,13 +6687,53 @@ pa_type_args (symbolP, is_export)
     }
 }
 
+/* Process a .EXPORT directive.  This makes functions external
+   and provides information such as argument relocation entries
+   to callers.  */
+
+static void
+pa_export (int unused ATTRIBUTE_UNUSED)
+{
+  char *name, c, *p;
+  symbolS *symbol;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  /* Make sure the given symbol exists.  */
+  if ((symbol = symbol_find_or_make (name)) == NULL)
+    {
+      as_bad (_("Cannot define export symbol: %s\n"), name);
+      p = input_line_pointer;
+      *p = c;
+      input_line_pointer++;
+    }
+  else
+    {
+      /* OK.  Set the external bits and process argument relocations.
+         For the HP, weak and global are not mutually exclusive.
+         S_SET_EXTERNAL will not set BSF_GLOBAL if WEAK is set.
+         Call S_SET_EXTERNAL to get the other processing.  Manually
+         set BSF_GLOBAL when we get back.  */
+      S_SET_EXTERNAL (symbol);
+      symbol_get_bfdsym (symbol)->flags |= BSF_GLOBAL;
+      p = input_line_pointer;
+      *p = c;
+      if (!is_end_of_statement ())
+	{
+	  input_line_pointer++;
+	  pa_type_args (symbol, 1);
+	}
+    }
+
+  demand_empty_rest_of_line ();
+}
+
 /* Handle an .IMPORT pseudo-op.  Any symbol referenced in a given
    assembly file must either be defined in the assembly file, or
    explicitly IMPORTED from another.  */
 
 static void
-pa_import (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_import (int unused ATTRIBUTE_UNUSED)
 {
   char *name, c, *p;
   symbolS *symbol;
@@ -6875,8 +6784,7 @@ pa_import (unused)
 /* Handle a .LABEL pseudo-op.  */
 
 static void
-pa_label (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_label (int unused ATTRIBUTE_UNUSED)
 {
   char *name, c, *p;
 
@@ -6905,8 +6813,7 @@ pa_label (unused)
 /* Handle a .LEAVE pseudo-op.  This is not supported yet.  */
 
 static void
-pa_leave (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_leave (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -6920,8 +6827,7 @@ pa_leave (unused)
 /* Handle a .LEVEL pseudo-op.  */
 
 static void
-pa_level (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_level (int unused ATTRIBUTE_UNUSED)
 {
   char *level;
 
@@ -6961,8 +6867,7 @@ pa_level (unused)
 /* Handle a .ORIGIN pseudo-op.  */
 
 static void
-pa_origin (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_origin (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -6977,8 +6882,7 @@ pa_origin (unused)
    is for static functions.  FIXME.  Should share more code with .EXPORT.  */
 
 static void
-pa_param (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_param (int unused ATTRIBUTE_UNUSED)
 {
   char *name, c, *p;
   symbolS *symbol;
@@ -7012,8 +6916,7 @@ pa_param (unused)
    of a procedure from a syntactical point of view.  */
 
 static void
-pa_proc (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_proc (int unused ATTRIBUTE_UNUSED)
 {
   struct call_info *call_info;
 
@@ -7030,7 +6933,7 @@ pa_proc (unused)
   within_procedure = TRUE;
 
   /* Create another call_info structure.  */
-  call_info = (struct call_info *) xmalloc (sizeof (struct call_info));
+  call_info = xmalloc (sizeof (struct call_info));
 
   if (!call_info)
     as_fatal (_("Cannot allocate unwind descriptor\n"));
@@ -7082,10 +6985,8 @@ pa_proc (unused)
    appropriate pseudo-ops were found within the procedure.  */
 
 static void
-pa_procend (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_procend (int unused ATTRIBUTE_UNUSED)
 {
-
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
   pa_check_current_space_and_subspace ();
@@ -7157,8 +7058,7 @@ pa_procend (unused)
    return log2 (VALUE).  Else return -1.  */
 
 static int
-exact_log2 (value)
-     int value;
+exact_log2 (int value)
 {
   int shift = 0;
 
@@ -7174,7 +7074,7 @@ exact_log2 (value)
 /* Check to make sure we have a valid space and subspace.  */
 
 static void
-pa_check_current_space_and_subspace ()
+pa_check_current_space_and_subspace (void)
 {
   if (current_space == NULL)
     as_fatal (_("Not in a space.\n"));
@@ -7188,9 +7088,7 @@ pa_check_current_space_and_subspace ()
    by the parameters to the .SPACE directive.  */
 
 static sd_chain_struct *
-pa_parse_space_stmt (space_name, create_flag)
-     char *space_name;
-     int create_flag;
+pa_parse_space_stmt (char *space_name, int create_flag)
 {
   char *name, *ptemp, c;
   char loadable, defined, private, sort;
@@ -7198,7 +7096,7 @@ pa_parse_space_stmt (space_name, create_flag)
   asection *seg = NULL;
   sd_chain_struct *space;
 
-  /* load default values */
+  /* Load default values.  */
   spnum = 0;
   sort = 0;
   loadable = TRUE;
@@ -7310,8 +7208,7 @@ pa_parse_space_stmt (space_name, create_flag)
    given space, creating the new space if necessary.  */
 
 static void
-pa_space (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_space (int unused ATTRIBUTE_UNUSED)
 {
   char *name, c, *space_name, *save_s;
   sd_chain_struct *sd_chain;
@@ -7430,8 +7327,7 @@ pa_space (unused)
 /* Switch to a new space.  (I think).  FIXME.  */
 
 static void
-pa_spnum (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_spnum (int unused ATTRIBUTE_UNUSED)
 {
   char *name;
   char c;
@@ -7460,8 +7356,7 @@ pa_spnum (unused)
    they're broken up into subroutines.  */
 
 static void
-pa_subspace (create_new)
-     int create_new;
+pa_subspace (int create_new)
 {
   char *name, *ss_name, c;
   char loadable, code_only, comdat, common, dup_common, zero, sort;
@@ -7699,7 +7594,7 @@ pa_subspace (create_new)
 /* Create default space and subspace dictionaries.  */
 
 static void
-pa_spaces_begin ()
+pa_spaces_begin (void)
 {
   int i;
 
@@ -7826,25 +7721,23 @@ pa_spaces_begin ()
    by the given parameters.  */
 
 static sd_chain_struct *
-create_new_space (name, spnum, loadable, defined, private,
-		  sort, seg, user_defined)
-     char *name;
-     int spnum;
-     int loadable ATTRIBUTE_UNUSED;
-     int defined;
-     int private;
-     int sort;
-     asection *seg;
-     int user_defined;
+create_new_space (char *name,
+		  int spnum,
+		  int loadable ATTRIBUTE_UNUSED,
+		  int defined,
+		  int private,
+		  int sort,
+		  asection *seg,
+		  int user_defined)
 {
   sd_chain_struct *chain_entry;
 
-  chain_entry = (sd_chain_struct *) xmalloc (sizeof (sd_chain_struct));
+  chain_entry = xmalloc (sizeof (sd_chain_struct));
   if (!chain_entry)
     as_fatal (_("Out of memory: could not allocate new space chain entry: %s\n"),
 	      name);
 
-  SPACE_NAME (chain_entry) = (char *) xmalloc (strlen (name) + 1);
+  SPACE_NAME (chain_entry) = xmalloc (strlen (name) + 1);
   strcpy (SPACE_NAME (chain_entry), name);
   SPACE_DEFINED (chain_entry) = defined;
   SPACE_USER_DEFINED (chain_entry) = user_defined;
@@ -7910,29 +7803,28 @@ create_new_space (name, spnum, loadable, defined, private,
    order as defined by the SORT entries.  */
 
 static ssd_chain_struct *
-create_new_subspace (space, name, loadable, code_only, comdat, common,
-		     dup_common, is_zero, sort, access, space_index,
-		     alignment, quadrant, seg)
-     sd_chain_struct *space;
-     char *name;
-     int loadable ATTRIBUTE_UNUSED;
-     int code_only ATTRIBUTE_UNUSED;
-     int comdat, common, dup_common;
-     int is_zero ATTRIBUTE_UNUSED;
-     int sort;
-     int access;
-     int space_index ATTRIBUTE_UNUSED;
-     int alignment ATTRIBUTE_UNUSED;
-     int quadrant;
-     asection *seg;
+create_new_subspace (sd_chain_struct *space,
+		     char *name,
+		     int loadable ATTRIBUTE_UNUSED,
+		     int code_only ATTRIBUTE_UNUSED,
+		     int comdat,
+		     int common,
+		     int dup_common,
+		     int is_zero ATTRIBUTE_UNUSED,
+		     int sort,
+		     int access,
+		     int space_index ATTRIBUTE_UNUSED,
+		     int alignment ATTRIBUTE_UNUSED,
+		     int quadrant,
+		     asection *seg)
 {
   ssd_chain_struct *chain_entry;
 
-  chain_entry = (ssd_chain_struct *) xmalloc (sizeof (ssd_chain_struct));
+  chain_entry = xmalloc (sizeof (ssd_chain_struct));
   if (!chain_entry)
     as_fatal (_("Out of memory: could not allocate new subspace chain entry: %s\n"), name);
 
-  SUBSPACE_NAME (chain_entry) = (char *) xmalloc (strlen (name) + 1);
+  SUBSPACE_NAME (chain_entry) = xmalloc (strlen (name) + 1);
   strcpy (SUBSPACE_NAME (chain_entry), name);
 
   /* Initialize subspace_defined.  When we hit a .subspace directive
@@ -7986,22 +7878,20 @@ create_new_subspace (space, name, loadable, code_only, comdat, common,
    various arguments.   Return the modified subspace chain entry.  */
 
 static ssd_chain_struct *
-update_subspace (space, name, loadable, code_only, comdat, common, dup_common,
-		 sort, zero, access, space_index, alignment, quadrant, section)
-     sd_chain_struct *space;
-     char *name;
-     int loadable ATTRIBUTE_UNUSED;
-     int code_only ATTRIBUTE_UNUSED;
-     int comdat;
-     int common;
-     int dup_common;
-     int zero ATTRIBUTE_UNUSED;
-     int sort;
-     int access;
-     int space_index ATTRIBUTE_UNUSED;
-     int alignment ATTRIBUTE_UNUSED;
-     int quadrant;
-     asection *section;
+update_subspace (sd_chain_struct *space,
+		 char *name,
+		 int loadable ATTRIBUTE_UNUSED,
+		 int code_only ATTRIBUTE_UNUSED,
+		 int comdat,
+		 int common,
+		 int dup_common,
+		 int sort,
+		 int zero ATTRIBUTE_UNUSED,
+		 int access,
+		 int space_index ATTRIBUTE_UNUSED,
+		 int alignment ATTRIBUTE_UNUSED,
+		 int quadrant,
+		 asection *section)
 {
   ssd_chain_struct *chain_entry;
 
@@ -8019,18 +7909,15 @@ update_subspace (space, name, loadable, code_only, comdat, common, dup_common,
    NULL if no such space exists.  */
 
 static sd_chain_struct *
-is_defined_space (name)
-     char *name;
+is_defined_space (char *name)
 {
   sd_chain_struct *chain_pointer;
 
   for (chain_pointer = space_dict_root;
        chain_pointer;
        chain_pointer = chain_pointer->sd_next)
-    {
-      if (strcmp (SPACE_NAME (chain_pointer), name) == 0)
-	return chain_pointer;
-    }
+    if (strcmp (SPACE_NAME (chain_pointer), name) == 0)
+      return chain_pointer;
 
   /* No mapping from segment to space was found.  Return NULL.  */
   return NULL;
@@ -8043,8 +7930,7 @@ is_defined_space (name)
    so a linear exhaustive search is OK here.  */
 
 static sd_chain_struct *
-pa_segment_to_space (seg)
-     asection *seg;
+pa_segment_to_space (asection *seg)
 {
   sd_chain_struct *space_chain;
 
@@ -8052,10 +7938,8 @@ pa_segment_to_space (seg)
   for (space_chain = space_dict_root;
        space_chain;
        space_chain = space_chain->sd_next)
-    {
-      if (space_chain->sd_seg == seg)
-	return space_chain;
-    }
+    if (space_chain->sd_seg == seg)
+      return space_chain;
 
   /* Mapping was not found.  Return NULL.  */
   return NULL;
@@ -8068,14 +7952,13 @@ pa_segment_to_space (seg)
    the first (i.e., default) subspace is preferable in most situations.
    For example, it wouldn't be desirable to merge COMDAT data with non
    COMDAT data.
-    
+
    Uses a linear search through all the spaces and subspaces, this may
    not be appropriate if we ever being placing each function in its
    own subspace.  */
 
 static ssd_chain_struct *
-is_defined_subspace (name)
-     char *name;
+is_defined_subspace (char *name)
 {
   sd_chain_struct *space_chain;
   ssd_chain_struct *subspace_chain;
@@ -8105,9 +7988,7 @@ is_defined_subspace (name)
    to become more efficient.  */
 
 static ssd_chain_struct *
-pa_subsegment_to_subspace (seg, subseg)
-     asection *seg;
-     subsegT subseg;
+pa_subsegment_to_subspace (asection *seg, subsegT subseg)
 {
   sd_chain_struct *space_chain;
   ssd_chain_struct *subspace_chain;
@@ -8139,8 +8020,7 @@ pa_subsegment_to_subspace (seg, subseg)
    that was found or NULL on failure.  */
 
 static sd_chain_struct *
-pa_find_space_by_number (number)
-     int number;
+pa_find_space_by_number (int number)
 {
   sd_chain_struct *space_chain;
 
@@ -8160,9 +8040,7 @@ pa_find_space_by_number (number)
    address is unknown then return zero.  */
 
 static unsigned int
-pa_subspace_start (space, quadrant)
-     sd_chain_struct *space;
-     int quadrant;
+pa_subspace_start (sd_chain_struct *space, int quadrant)
 {
   /* FIXME.  Assumes everyone puts read/write data at 0x4000000, this
      is not correct for the PA OSF1 port.  */
@@ -8180,8 +8058,7 @@ pa_subspace_start (space, quadrant)
    a string.  */
 
 static unsigned int
-pa_stringer_aux (s)
-     char *s;
+pa_stringer_aux (char *s)
 {
   unsigned int c = *s & CHAR_MASK;
 
@@ -8199,8 +8076,7 @@ pa_stringer_aux (s)
 /* Handle a .STRING type pseudo-op.  */
 
 static void
-pa_stringer (append_zero)
-     int append_zero;
+pa_stringer (int append_zero)
 {
   char *s, num_buf[4];
   unsigned int c;
@@ -8281,8 +8157,7 @@ pa_stringer (append_zero)
 /* Handle a .VERSION pseudo-op.  */
 
 static void
-pa_version (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_version (int unused ATTRIBUTE_UNUSED)
 {
   obj_version (0);
   pa_undefine_label ();
@@ -8293,8 +8168,7 @@ pa_version (unused)
 /* Handle a .COMPILER pseudo-op.  */
 
 static void
-pa_compiler (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_compiler (int unused ATTRIBUTE_UNUSED)
 {
   obj_som_compiler (0);
   pa_undefine_label ();
@@ -8305,8 +8179,7 @@ pa_compiler (unused)
 /* Handle a .COPYRIGHT pseudo-op.  */
 
 static void
-pa_copyright (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_copyright (int unused ATTRIBUTE_UNUSED)
 {
   obj_copyright (0);
   pa_undefine_label ();
@@ -8316,8 +8189,7 @@ pa_copyright (unused)
    the latest space label.  */
 
 static void
-pa_cons (nbytes)
-     int nbytes;
+pa_cons (int nbytes)
 {
   cons (nbytes);
   pa_undefine_label ();
@@ -8326,8 +8198,7 @@ pa_cons (nbytes)
 /* Like float_cons, but we need to undefine our label.  */
 
 static void
-pa_float_cons (float_type)
-     int float_type;
+pa_float_cons (int float_type)
 {
   float_cons (float_type);
   pa_undefine_label ();
@@ -8336,8 +8207,7 @@ pa_float_cons (float_type)
 /* Like s_fill, but delete our label when finished.  */
 
 static void
-pa_fill (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_fill (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -8351,8 +8221,7 @@ pa_fill (unused)
 /* Like lcomm, but delete our label when finished.  */
 
 static void
-pa_lcomm (needs_align)
-     int needs_align;
+pa_lcomm (int needs_align)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -8366,8 +8235,7 @@ pa_lcomm (needs_align)
 /* Like lsym, but delete our label when finished.  */
 
 static void
-pa_lsym (unused)
-     int unused ATTRIBUTE_UNUSED;
+pa_lsym (int unused ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -8378,6 +8246,79 @@ pa_lsym (unused)
   pa_undefine_label ();
 }
 
+/* This function is called once, at assembler startup time.  It should
+   set up all the tables, etc. that the MD part of the assembler will need.  */
+
+void
+md_begin (void)
+{
+  const char *retval = NULL;
+  int lose = 0;
+  unsigned int i = 0;
+
+  last_call_info = NULL;
+  call_info_root = NULL;
+
+  /* Set the default machine type.  */
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, DEFAULT_LEVEL))
+    as_warn (_("could not set architecture and machine"));
+
+  /* Folding of text and data segments fails miserably on the PA.
+     Warn user and disable "-R" option.  */
+  if (flag_readonly_data_in_text)
+    {
+      as_warn (_("-R option not supported on this target."));
+      flag_readonly_data_in_text = 0;
+    }
+
+#ifdef OBJ_SOM
+  pa_spaces_begin ();
+#endif
+
+  op_hash = hash_new ();
+
+  while (i < NUMOPCODES)
+    {
+      const char *name = pa_opcodes[i].name;
+
+      retval = hash_insert (op_hash, name, (struct pa_opcode *) &pa_opcodes[i]);
+      if (retval != NULL && *retval != '\0')
+	{
+	  as_fatal (_("Internal error: can't hash `%s': %s\n"), name, retval);
+	  lose = 1;
+	}
+
+      do
+	{
+	  if ((pa_opcodes[i].match & pa_opcodes[i].mask)
+	      != pa_opcodes[i].match)
+	    {
+	      fprintf (stderr, _("internal error: losing opcode: `%s' \"%s\"\n"),
+		       pa_opcodes[i].name, pa_opcodes[i].args);
+	      lose = 1;
+	    }
+	  ++i;
+	}
+      while (i < NUMOPCODES && !strcmp (pa_opcodes[i].name, name));
+    }
+
+  if (lose)
+    as_fatal (_("Broken assembler.  No assembly attempted."));
+
+#ifdef OBJ_SOM
+  /* SOM will change text_section.  To make sure we never put
+     anything into the old one switch to the new one now.  */
+  subseg_set (text_section, 0);
+#endif
+
+#ifdef OBJ_SOM
+  dummy_symbol = symbol_find_or_make ("L$dummy");
+  S_SET_SEGMENT (dummy_symbol, text_section);
+  /* Force the symbol to be converted to a real symbol.  */
+  (void) symbol_get_bfdsym (dummy_symbol);
+#endif
+}
+
 /* On the PA relocations which involve function symbols must not be
    adjusted.  This so that the linker can know when/how to create argument
    relocation stubs for indirect calls and calls to static functions.
@@ -8400,8 +8341,7 @@ pa_lsym (unused)
    reductions make life a living hell for object file editors.  */
 
 int
-hppa_fix_adjustable (fixp)
-     fixS *fixp;
+hppa_fix_adjustable (fixS *fixp)
 {
 #ifdef OBJ_ELF
   reloc_type code;
@@ -8522,8 +8462,7 @@ hppa_fix_adjustable (fixp)
    within GAS.  */
 
 int
-hppa_force_relocation (fixp)
-     struct fix *fixp;
+hppa_force_relocation (struct fix *fixp)
 {
   struct hppa_fix_struct *hppa_fixp;
 
@@ -8597,75 +8536,13 @@ hppa_force_relocation (fixp)
 
 /* Now for some ELF specific code.  FIXME.  */
 #ifdef OBJ_ELF
-/* Mark the end of a function so that it's possible to compute
-   the size of the function in elf_hppa_final_processing.  */
-
-static void
-hppa_elf_mark_end_of_function ()
-{
-  /* ELF does not have EXIT relocations.  All we do is create a
-     temporary symbol marking the end of the function.  */
-  char *name;
-
-  if (last_call_info == NULL || last_call_info->start_symbol == NULL)
-    {
-      /* We have already warned about a missing label,
-	 or other problems.  */
-      return;
-    }
-
-  name = (char *) xmalloc (strlen ("L$\001end_")
-			   + strlen (S_GET_NAME (last_call_info->start_symbol))
-			   + 1);
-  if (name)
-    {
-      symbolS *symbolP;
-
-      strcpy (name, "L$\001end_");
-      strcat (name, S_GET_NAME (last_call_info->start_symbol));
-
-      /* If we have a .exit followed by a .procend, then the
-	 symbol will have already been defined.  */
-      symbolP = symbol_find (name);
-      if (symbolP)
-	{
-	  /* The symbol has already been defined!  This can
-	     happen if we have a .exit followed by a .procend.
-
-	     This is *not* an error.  All we want to do is free
-	     the memory we just allocated for the name and continue.  */
-	  xfree (name);
-	}
-      else
-	{
-	  /* symbol value should be the offset of the
-	     last instruction of the function */
-	  symbolP = symbol_new (name, now_seg, (valueT) (frag_now_fix () - 4),
-				frag_now);
-
-	  assert (symbolP);
-	  S_CLEAR_EXTERNAL (symbolP);
-	  symbol_table_insert (symbolP);
-	}
-
-      if (symbolP)
-	last_call_info->end_symbol = symbolP;
-      else
-	as_bad (_("Symbol '%s' could not be created."), name);
-
-    }
-  else
-    as_bad (_("No memory for symbol name."));
-
-}
-
 /* For ELF, this function serves one purpose:  to setup the st_size
    field of STT_FUNC symbols.  To do this, we need to scan the
    call_info structure list, determining st_size in by taking the
    difference in the address of the beginning/end marker symbols.  */
 
 void
-elf_hppa_final_processing ()
+elf_hppa_final_processing (void)
 {
   struct call_info *call_info_pointer;
 
@@ -8683,8 +8560,7 @@ elf_hppa_final_processing ()
 }
 
 static void
-pa_vtable_entry (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+pa_vtable_entry (int ignore ATTRIBUTE_UNUSED)
 {
   struct fix *new_fix;
 
@@ -8692,8 +8568,8 @@ pa_vtable_entry (ignore)
 
   if (new_fix)
     {
-      struct hppa_fix_struct *hppa_fix = (struct hppa_fix_struct *)
-	obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
+      struct hppa_fix_struct * hppa_fix = obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
+
       hppa_fix->fx_r_type = R_HPPA;
       hppa_fix->fx_r_field = e_fsel;
       hppa_fix->fx_r_format = 32;
@@ -8705,8 +8581,7 @@ pa_vtable_entry (ignore)
 }
 
 static void
-pa_vtable_inherit (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+pa_vtable_inherit (int ignore ATTRIBUTE_UNUSED)
 {
   struct fix *new_fix;
 
@@ -8714,8 +8589,8 @@ pa_vtable_inherit (ignore)
 
   if (new_fix)
     {
-      struct hppa_fix_struct *hppa_fix = (struct hppa_fix_struct *)
-	obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
+      struct hppa_fix_struct * hppa_fix = obstack_alloc (&notes, sizeof (struct hppa_fix_struct));
+
       hppa_fix->fx_r_type = R_HPPA;
       hppa_fix->fx_r_field = e_fsel;
       hppa_fix->fx_r_format = 32;
@@ -8726,3 +8601,135 @@ pa_vtable_inherit (ignore)
     }
 }
 #endif
+
+/* Table of pseudo ops for the PA.  FIXME -- how many of these
+   are now redundant with the overall GAS and the object file
+   dependent tables?  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* align pseudo-ops on the PA specify the actual alignment requested,
+     not the log2 of the requested alignment.  */
+#ifdef OBJ_SOM
+  {"align", pa_align, 8},
+#endif
+#ifdef OBJ_ELF
+  {"align", s_align_bytes, 8},
+#endif
+  {"begin_brtab", pa_brtab, 1},
+  {"begin_try", pa_try, 1},
+  {"block", pa_block, 1},
+  {"blockz", pa_block, 0},
+  {"byte", pa_cons, 1},
+  {"call", pa_call, 0},
+  {"callinfo", pa_callinfo, 0},
+#if defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD))
+  {"code", obj_elf_text, 0},
+#else
+  {"code", pa_text, 0},
+  {"comm", pa_comm, 0},
+#endif
+#ifdef OBJ_SOM
+  {"compiler", pa_compiler, 0},
+#endif
+  {"copyright", pa_copyright, 0},
+#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
+  {"data", pa_data, 0},
+#endif
+  {"double", pa_float_cons, 'd'},
+  {"dword", pa_cons, 8},
+  {"end", pa_end, 0},
+  {"end_brtab", pa_brtab, 0},
+#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
+  {"end_try", pa_try, 0},
+#endif
+  {"enter", pa_enter, 0},
+  {"entry", pa_entry, 0},
+  {"equ", pa_equ, 0},
+  {"exit", pa_exit, 0},
+  {"export", pa_export, 0},
+  {"fill", pa_fill, 0},
+  {"float", pa_float_cons, 'f'},
+  {"half", pa_cons, 2},
+  {"import", pa_import, 0},
+  {"int", pa_cons, 4},
+  {"label", pa_label, 0},
+  {"lcomm", pa_lcomm, 0},
+  {"leave", pa_leave, 0},
+  {"level", pa_level, 0},
+  {"long", pa_cons, 4},
+  {"lsym", pa_lsym, 0},
+#ifdef OBJ_SOM
+  {"nsubspa", pa_subspace, 1},
+#endif
+  {"octa", pa_cons, 16},
+  {"org", pa_origin, 0},
+  {"origin", pa_origin, 0},
+  {"param", pa_param, 0},
+  {"proc", pa_proc, 0},
+  {"procend", pa_procend, 0},
+  {"quad", pa_cons, 8},
+  {"reg", pa_equ, 1},
+  {"short", pa_cons, 2},
+  {"single", pa_float_cons, 'f'},
+#ifdef OBJ_SOM
+  {"space", pa_space, 0},
+  {"spnum", pa_spnum, 0},
+#endif
+  {"string", pa_stringer, 0},
+  {"stringz", pa_stringer, 1},
+#ifdef OBJ_SOM
+  {"subspa", pa_subspace, 0},
+#endif
+#if !(defined (OBJ_ELF) && (defined (TE_LINUX) || defined (TE_NetBSD)))
+  {"text", pa_text, 0},
+#endif
+  {"version", pa_version, 0},
+#ifdef OBJ_ELF
+  {"vtable_entry", pa_vtable_entry, 0},
+  {"vtable_inherit", pa_vtable_inherit, 0},
+#endif
+  {"word", pa_cons, 4},
+  {NULL, 0, 0}
+};
+
+#ifdef OBJ_ELF
+void
+hppa_cfi_frame_initial_instructions (void)
+{
+  cfi_add_CFA_def_cfa (30, 0);
+}
+
+int
+hppa_regname_to_dw2regnum (char *regname)
+{
+  unsigned int regnum = -1;
+  unsigned int i;
+  const char *p;
+  char *q;
+  static struct { char *name; int dw2regnum; } regnames[] =
+    {
+      { "sp", 30 }, { "rp", 2 },
+    };
+
+  for (i = 0; i < ARRAY_SIZE (regnames); ++i)
+    if (strcmp (regnames[i].name, regname) == 0)
+      return regnames[i].dw2regnum;
+
+  if (regname[0] == 'r')
+    {
+      p = regname + 1;
+      regnum = strtoul (p, &q, 10);
+      if (p == q || *q || regnum >= 32)
+	return -1;
+    }
+  else if (regname[0] == 'f' && regname[1] == 'r')
+    {
+      p = regname + 2;
+      regnum = strtoul (p, &q, 10);
+      if (p == q || *q || regnum <= 4 || regnum >= 32)
+	return -1;
+      regnum += 32 - 4;
+    }
+  return regnum;
+}
+#endif
diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h
index 9b3edc1878f5..f7bc8f8d97ab 100644
--- a/gas/config/tc-hppa.h
+++ b/gas/config/tc-hppa.h
@@ -1,6 +1,6 @@
 /* tc-hppa.h -- Header file for the PA
    Copyright 1989, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -90,15 +90,14 @@
 #define ASEC_NULL (asection *)0
 
 /* pa_define_label gets used outside of tc-hppa.c via tc_frob_label.  */
-extern void pa_define_label PARAMS ((symbolS *));
-
-extern void parse_cons_expression_hppa PARAMS ((expressionS *));
-extern void cons_fix_new_hppa PARAMS ((fragS *, int, int, expressionS *));
-extern int hppa_force_relocation PARAMS ((struct fix *));
+extern void pa_define_label (symbolS *);
+extern void parse_cons_expression_hppa (expressionS *);
+extern void cons_fix_new_hppa (fragS *, int, int, expressionS *);
+extern int hppa_force_relocation (struct fix *);
 
 /* This gets called before writing the object file to make sure
    things like entry/exit and proc/procend pairs match.  */
-extern void pa_check_eof PARAMS ((void));
+extern void pa_check_eof (void);
 #define tc_frob_file pa_check_eof
 
 #define tc_frob_label(sym) pa_define_label (sym)
@@ -120,7 +119,7 @@ extern const char	hppa_symbol_chars[];
    When used in an instruction it will always follow a comma.  */
 #define TC_EOL_IN_INSN(PTR)	(*(PTR) == '!' && (PTR)[-1] == ',')
 
-int hppa_fix_adjustable PARAMS((struct fix *));
+int hppa_fix_adjustable (struct fix *);
 #define tc_fix_adjustable hppa_fix_adjustable
 
 #define EXTERN_FORCE_RELOC 1
@@ -170,17 +169,23 @@ int hppa_fix_adjustable PARAMS((struct fix *));
 
 #define tc_frob_symbol(sym,punt) \
   { \
-    if ((S_GET_SEGMENT (sym) == &bfd_und_section && ! symbol_used_p (sym) && \
-  	 ELF_ST_VISIBILITY (S_GET_OTHER (sym)) == STV_DEFAULT) \
+    if ((S_GET_SEGMENT (sym) == &bfd_und_section \
+         && ! symbol_used_p (sym) \
+         && ELF_ST_VISIBILITY (S_GET_OTHER (sym)) == STV_DEFAULT) \
 	|| (S_GET_SEGMENT (sym) == &bfd_abs_section \
 	    && ! S_IS_EXTERNAL (sym)) \
 	|| strcmp (S_GET_NAME (sym), "$global$") == 0 \
-	|| strcmp (S_GET_NAME (sym), "$PIC_pcrel$0") == 0) \
+	|| strcmp (S_GET_NAME (sym), "$PIC_pcrel$0") == 0 \
+	|| strcmp (S_GET_NAME (sym), "$tls_gdidx$") == 0 \
+	|| strcmp (S_GET_NAME (sym), "$tls_ldidx$") == 0 \
+	|| strcmp (S_GET_NAME (sym), "$tls_dtpoff$") == 0 \
+	|| strcmp (S_GET_NAME (sym), "$tls_ieoff$") == 0 \
+	|| strcmp (S_GET_NAME (sym), "$tls_leoff$") == 0) \
       punt = 1; \
   }
 
 #define elf_tc_final_processing	elf_hppa_final_processing
-void elf_hppa_final_processing PARAMS ((void));
+void elf_hppa_final_processing (void);
 
 #define DWARF2_LINE_MIN_INSN_LENGTH 4
 #endif /* OBJ_ELF */
@@ -191,10 +196,27 @@ void elf_hppa_final_processing PARAMS ((void));
    A silly fudge required for backwards compatibility.  */
 #define md_optimize_expr hppa_force_reg_syms_absolute
 
-int hppa_force_reg_syms_absolute
-  PARAMS ((expressionS *, operatorT, expressionS *));
+int hppa_force_reg_syms_absolute (expressionS *, operatorT, expressionS *);
 
 #define TC_FIX_TYPE PTR
 #define TC_INIT_FIX_DATA(FIX) ((FIX)->tc_fix_data = NULL)
 
+#ifdef OBJ_ELF
+#define TARGET_USE_CFIPOP 1
+
+#define tc_cfi_frame_initial_instructions hppa_cfi_frame_initial_instructions
+extern void hppa_cfi_frame_initial_instructions (void);
+
+#define tc_regname_to_dw2regnum hppa_regname_to_dw2regnum
+extern int hppa_regname_to_dw2regnum (char *regname);
+
+#define DWARF2_LINE_MIN_INSN_LENGTH 4
+#define DWARF2_DEFAULT_RETURN_COLUMN 2
+#if TARGET_ARCH_SIZE == 64
+#define DWARF2_CIE_DATA_ALIGNMENT -8
+#else
+#define DWARF2_CIE_DATA_ALIGNMENT -4
+#endif
+#endif
+
 #endif /* _TC_HPPA_H */
diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c
index d87d2d9f808c..4445abeb406d 100644
--- a/gas/config/tc-i370.c
+++ b/gas/config/tc-i370.c
@@ -27,7 +27,6 @@
    similarities between HLASM and the MRI assemblers, such as section
    names, lack of leading . in pseudo-ops, DC and DS, etc.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index be384bc99a76..296fdcdde415 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1,6 +1,6 @@
-/* i386.c -- Assemble code for the Intel 80386
+/* tc-i386.c -- Assemble code for the Intel 80386
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -32,7 +32,6 @@
 #include "subsegs.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
-#include "opcode/i386.h"
 #include "elf/x86-64.h"
 
 #ifndef REGISTER_WARNINGS
@@ -63,54 +62,39 @@
 #endif
 #endif
 
-static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
-static INLINE int fits_in_signed_byte PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
-static INLINE int fits_in_signed_word PARAMS ((offsetT));
-static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
-static INLINE int fits_in_signed_long PARAMS ((offsetT));
-static int smallest_imm_type PARAMS ((offsetT));
-static offsetT offset_in_range PARAMS ((offsetT, int));
-static int add_prefix PARAMS ((unsigned int));
-static void set_code_flag PARAMS ((int));
-static void set_16bit_gcc_code_flag PARAMS ((int));
-static void set_intel_syntax PARAMS ((int));
-static void set_cpu_arch PARAMS ((int));
+static void set_code_flag (int);
+static void set_16bit_gcc_code_flag (int);
+static void set_intel_syntax (int);
+static void set_cpu_arch (int);
 #ifdef TE_PE
-static void pe_directive_secrel PARAMS ((int));
+static void pe_directive_secrel (int);
 #endif
-static void signed_cons PARAMS ((int));
-static char *output_invalid PARAMS ((int c));
-static int i386_operand PARAMS ((char *operand_string));
-static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
-static const reg_entry *parse_register PARAMS ((char *reg_string,
-						char **end_op));
-static char *parse_insn PARAMS ((char *, char *));
-static char *parse_operands PARAMS ((char *, const char *));
-static void swap_operands PARAMS ((void));
-static void optimize_imm PARAMS ((void));
-static void optimize_disp PARAMS ((void));
-static int match_template PARAMS ((void));
-static int check_string PARAMS ((void));
-static int process_suffix PARAMS ((void));
-static int check_byte_reg PARAMS ((void));
-static int check_long_reg PARAMS ((void));
-static int check_qword_reg PARAMS ((void));
-static int check_word_reg PARAMS ((void));
-static int finalize_imm PARAMS ((void));
-static int process_operands PARAMS ((void));
-static const seg_entry *build_modrm_byte PARAMS ((void));
-static void output_insn PARAMS ((void));
-static void output_branch PARAMS ((void));
-static void output_jump PARAMS ((void));
-static void output_interseg_jump PARAMS ((void));
-static void output_imm PARAMS ((fragS *insn_start_frag,
-				offsetT insn_start_off));
-static void output_disp PARAMS ((fragS *insn_start_frag,
-				 offsetT insn_start_off));
+static void signed_cons (int);
+static char *output_invalid (int c);
+static int i386_operand (char *);
+static int i386_intel_operand (char *, int);
+static const reg_entry *parse_register (char *, char **);
+static char *parse_insn (char *, char *);
+static char *parse_operands (char *, const char *);
+static void swap_operands (void);
+static void swap_2_operands (int, int);
+static void optimize_imm (void);
+static void optimize_disp (void);
+static int match_template (void);
+static int check_string (void);
+static int process_suffix (void);
+static int check_byte_reg (void);
+static int check_long_reg (void);
+static int check_qword_reg (void);
+static int check_word_reg (void);
+static int finalize_imm (void);
+static int process_operands (void);
+static const seg_entry *build_modrm_byte (void);
+static void output_insn (void);
+static void output_imm (fragS *, offsetT);
+static void output_disp (fragS *, offsetT);
 #ifndef I386COFF
-static void s_bss PARAMS ((int));
+static void s_bss (int);
 #endif
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
 static void handle_large_common (int small ATTRIBUTE_UNUSED);
@@ -271,8 +255,9 @@ static i386_insn i;
 /* Possible templates for current insn.  */
 static const templates *current_templates;
 
-/* Per instruction expressionS buffers: 2 displacements & 2 immediate max.  */
-static expressionS disp_expressions[2], im_expressions[2];
+/* Per instruction expressionS buffers: max displacements & immediates.  */
+static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
+static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
 
 /* Current operand we are working on.  */
 static int this_operand;
@@ -305,6 +290,9 @@ static int intel_syntax = 0;
 /* 1 if register prefix % not required.  */
 static int allow_naked_reg = 0;
 
+/* Register prefix used for error message.  */
+static const char *register_prefix = "%";
+
 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
    leave, push, and pop instructions so that gcc has the same stack
    frame as in 32 bit mode.  */
@@ -323,6 +311,21 @@ static const char *cpu_sub_arch_name = NULL;
 /* CPU feature flags.  */
 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
 
+/* If we have selected a cpu we are generating instructions for.  */
+static int cpu_arch_tune_set = 0;
+
+/* Cpu we are generating instructions for.  */
+static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
+
+/* CPU feature flags of cpu we are generating instructions for.  */
+static unsigned int cpu_arch_tune_flags = 0;
+
+/* CPU instruction set architecture used.  */
+static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
+
+/* CPU feature flags of instruction set architecture used.  */
+static unsigned int cpu_arch_isa_flags = 0;
+
 /* If set, conditional jumps are not automatically promoted to handle
    larger than a byte offset.  */
 static unsigned int no_cond_jump_promotion = 0;
@@ -415,35 +418,106 @@ const relax_typeS md_relax_table[] =
   {0, 0, 4, 0}
 };
 
-static const arch_entry cpu_arch[] = {
-  {"i8086",	Cpu086 },
-  {"i186",	Cpu086|Cpu186 },
-  {"i286",	Cpu086|Cpu186|Cpu286 },
-  {"i386",	Cpu086|Cpu186|Cpu286|Cpu386 },
-  {"i486",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
-  {"i586",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
-  {"i686",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
-  {"pentium",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
-  {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
-  {"pentiumii",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
-  {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
-  {"pentium4",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
-  {"prescott",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
-  {"k6",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
-  {"k6_2",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
-  {"athlon",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
-  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
-  {"opteron",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
-  {".mmx",	CpuMMX },
-  {".sse",	CpuMMX|CpuMMX2|CpuSSE },
-  {".sse2",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
-  {".sse3",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
-  {".3dnow",	CpuMMX|Cpu3dnow },
-  {".3dnowa",	CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
-  {".padlock",	CpuPadLock },
-  {".pacifica",	CpuSVME },
-  {".svme",	CpuSVME },
-  {NULL, 0 }
+static const arch_entry cpu_arch[] =
+{
+  {"generic32", PROCESSOR_GENERIC32,
+   Cpu186|Cpu286|Cpu386},
+  {"generic64", PROCESSOR_GENERIC64,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2},
+  {"i8086", PROCESSOR_UNKNOWN,
+   0},
+  {"i186", PROCESSOR_UNKNOWN,
+   Cpu186},
+  {"i286", PROCESSOR_UNKNOWN,
+   Cpu186|Cpu286},
+  {"i386", PROCESSOR_GENERIC32,
+   Cpu186|Cpu286|Cpu386},
+  {"i486", PROCESSOR_I486,
+   Cpu186|Cpu286|Cpu386|Cpu486},
+  {"i586", PROCESSOR_PENTIUM,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
+  {"i686", PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
+  {"pentium", PROCESSOR_PENTIUM,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
+  {"pentiumpro",PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
+  {"pentiumii",	PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
+  {"pentiumiii",PROCESSOR_PENTIUMPRO,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
+  {"pentium4", PROCESSOR_PENTIUM4,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2},
+  {"prescott", PROCESSOR_NOCONA,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"nocona", PROCESSOR_NOCONA,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"yonah", PROCESSOR_CORE,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"core", PROCESSOR_CORE,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {"merom", PROCESSOR_CORE2,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {"core2", PROCESSOR_CORE2,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
+   |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {"k6", PROCESSOR_K6,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
+  {"k6_2", PROCESSOR_K6,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
+  {"athlon", PROCESSOR_ATHLON,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
+  {"sledgehammer", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"opteron", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"k8", PROCESSOR_K8,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
+   |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
+  {"amdfam10", PROCESSOR_AMDFAM10,
+   Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
+   |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
+   |CpuABM},
+  {".mmx", PROCESSOR_UNKNOWN,
+   CpuMMX},
+  {".sse", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE},
+  {".sse2", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
+  {".sse3", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
+  {".ssse3", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
+  {".sse4.1", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
+  {".sse4.2", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
+  {".sse4", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
+  {".3dnow", PROCESSOR_UNKNOWN,
+   CpuMMX|Cpu3dnow},
+  {".3dnowa", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
+  {".padlock", PROCESSOR_UNKNOWN,
+   CpuPadLock},
+  {".pacifica", PROCESSOR_UNKNOWN,
+   CpuSVME},
+  {".svme", PROCESSOR_UNKNOWN,
+   CpuSVME},
+  {".sse4a", PROCESSOR_UNKNOWN,
+   CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
+  {".abm", PROCESSOR_UNKNOWN,
+   CpuABM}
 };
 
 const pseudo_typeS md_pseudo_table[] =
@@ -473,7 +547,7 @@ const pseudo_typeS md_pseudo_table[] =
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
   {"largecomm", handle_large_common, 0},
 #else
-  {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
+  {"file", (void (*) (int)) dwarf2_directive_file, 0},
   {"loc", dwarf2_directive_loc, 0},
   {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
 #endif
@@ -493,9 +567,7 @@ static struct hash_control *op_hash;
 static struct hash_control *reg_hash;
 
 void
-i386_align_code (fragP, count)
-     fragS *fragP;
-     int count;
+i386_align_code (fragS *fragP, int count)
 {
   /* Various efficient no-op patterns for aligning code labels.
      Note: Don't try to assemble the instructions in the comments.
@@ -503,7 +575,7 @@ i386_align_code (fragP, count)
   static const char f32_1[] =
     {0x90};					/* nop			*/
   static const char f32_2[] =
-    {0x89,0xf6};				/* movl %esi,%esi	*/
+    {0x66,0x90};				/* xchg %ax,%ax */
   static const char f32_3[] =
     {0x8d,0x76,0x00};				/* leal 0(%esi),%esi	*/
   static const char f32_4[] =
@@ -563,13 +635,141 @@ i386_align_code (fragP, count)
     f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
     f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
   };
+  /* nopl (%[re]ax) */
+  static const char alt_3[] =
+    {0x0f,0x1f,0x00};
+  /* nopl 0(%[re]ax) */
+  static const char alt_4[] =
+    {0x0f,0x1f,0x40,0x00};
+  /* nopl 0(%[re]ax,%[re]ax,1) */
+  static const char alt_5[] =
+    {0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_6[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopl 0L(%[re]ax) */
+  static const char alt_7[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_8[] =
+    {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopw 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_9[] =
+    {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_10[] =
+    {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_11[] =
+    {0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_12[] =
+    {0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_13[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_14[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* data16
+     data16
+     data16
+     data16
+     data16
+     nopw %cs:0L(%[re]ax,%[re]ax,1) */
+  static const char alt_long_15[] =
+    {0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,
+     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  /* nopl 0(%[re]ax,%[re]ax,1)
+     nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_short_11[] =
+    {0x0f,0x1f,0x44,0x00,0x00,
+     0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1)
+     nopw 0(%[re]ax,%[re]ax,1) */
+  static const char alt_short_12[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00,
+     0x66,0x0f,0x1f,0x44,0x00,0x00};
+  /* nopw 0(%[re]ax,%[re]ax,1)
+     nopl 0L(%[re]ax) */
+  static const char alt_short_13[] =
+    {0x66,0x0f,0x1f,0x44,0x00,0x00,
+     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax)
+     nopl 0L(%[re]ax) */
+  static const char alt_short_14[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
+     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
+  /* nopl 0L(%[re]ax)
+     nopl 0L(%[re]ax,%[re]ax,1) */
+  static const char alt_short_15[] =
+    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
+     0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
+  static const char *const alt_short_patt[] = {
+    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
+    alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
+    alt_short_14, alt_short_15
+  };
+  static const char *const alt_long_patt[] = {
+    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
+    alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
+    alt_long_14, alt_long_15
+  };
 
   if (count <= 0 || count > 15)
     return;
 
-  /* The recommended way to pad 64bit code is to use NOPs preceded by
-     maximally four 0x66 prefixes.  Balance the size of nops.  */
-  if (flag_code == CODE_64BIT)
+  /* We need to decide which NOP sequence to use for 32bit and
+     64bit. When -mtune= is used:
+
+     1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
+     f32_patt will be used.
+     2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
+     0x66 prefix will be used.
+     3. For PROCESSOR_CORE2, alt_long_patt will be used.
+     4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
+     PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
+     and PROCESSOR_GENERIC64, alt_short_patt will be used.
+
+     When -mtune= isn't used, alt_short_patt will be used if
+     cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
+
+     When -march= or .arch is used, we can't use anything beyond
+     cpu_arch_isa_flags.   */
+
+  if (flag_code == CODE_16BIT)
+    {
+      memcpy (fragP->fr_literal + fragP->fr_fix,
+	      f16_patt[count - 1], count);
+      if (count > 8)
+	/* Adjust jump offset.  */
+	fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
+    }
+  else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
     {
       int i;
       int nnops = (count + 3) / 4;
@@ -577,6 +777,8 @@ i386_align_code (fragP, count)
       int remains = count - nnops * len;
       int pos = 0;
 
+      /* The recommended way to pad 64bit code is to use NOPs preceded
+	 by maximally four 0x66 prefixes.  Balance the size of nops.  */
       for (i = 0; i < remains; i++)
 	{
 	  memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
@@ -591,57 +793,121 @@ i386_align_code (fragP, count)
 	}
     }
   else
-    if (flag_code == CODE_16BIT)
-      {
-	memcpy (fragP->fr_literal + fragP->fr_fix,
-		f16_patt[count - 1], count);
-	if (count > 8)
-	  /* Adjust jump offset.  */
-	  fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
-      }
-    else
+    {
+      const char *const *patt = NULL;
+
+      if (cpu_arch_isa == PROCESSOR_UNKNOWN)
+	{
+	  /* PROCESSOR_UNKNOWN means that all ISAs may be used.  */
+	  switch (cpu_arch_tune)
+	    {
+	    case PROCESSOR_UNKNOWN:
+	      /* We use cpu_arch_isa_flags to check if we SHOULD
+		 optimize for Cpu686.  */
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_short_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_CORE2:
+	      patt = alt_long_patt;
+	      break;
+	    case PROCESSOR_PENTIUMPRO:
+	    case PROCESSOR_PENTIUM4:
+	    case PROCESSOR_NOCONA:
+	    case PROCESSOR_CORE:
+	    case PROCESSOR_K6:
+	    case PROCESSOR_ATHLON:
+	    case PROCESSOR_K8:
+	    case PROCESSOR_GENERIC64:
+	    case PROCESSOR_AMDFAM10:
+	      patt = alt_short_patt;
+	      break;
+	    case PROCESSOR_I486:
+	    case PROCESSOR_PENTIUM:
+	    case PROCESSOR_GENERIC32:
+	      patt = f32_patt;
+	      break;
+	    }
+	}
+      else
+	{
+	  switch (cpu_arch_tune)
+	    {
+	    case PROCESSOR_UNKNOWN:
+	      /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
+		 PROCESSOR_UNKNOWN.  */
+	      abort ();
+	      break;
+
+	    case PROCESSOR_I486:
+	    case PROCESSOR_PENTIUM:
+	    case PROCESSOR_PENTIUMPRO:
+	    case PROCESSOR_PENTIUM4:
+	    case PROCESSOR_NOCONA:
+	    case PROCESSOR_CORE:
+	    case PROCESSOR_K6:
+	    case PROCESSOR_ATHLON:
+	    case PROCESSOR_K8:
+	    case PROCESSOR_AMDFAM10:
+	    case PROCESSOR_GENERIC32:
+	      /* We use cpu_arch_isa_flags to check if we CAN optimize
+		 for Cpu686.  */
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_short_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_CORE2:
+	      if ((cpu_arch_isa_flags & Cpu686) != 0)
+		patt = alt_long_patt;
+	      else
+		patt = f32_patt;
+	      break;
+	    case PROCESSOR_GENERIC64:
+	      patt = alt_short_patt;
+	      break;
+	    }
+	}
+
       memcpy (fragP->fr_literal + fragP->fr_fix,
-	      f32_patt[count - 1], count);
+	      patt[count - 1], count);
+    }
   fragP->fr_var = count;
 }
 
 static INLINE unsigned int
-mode_from_disp_size (t)
-     unsigned int t;
+mode_from_disp_size (unsigned int t)
 {
   return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
 }
 
 static INLINE int
-fits_in_signed_byte (num)
-     offsetT num;
+fits_in_signed_byte (offsetT num)
 {
   return (num >= -128) && (num <= 127);
 }
 
 static INLINE int
-fits_in_unsigned_byte (num)
-     offsetT num;
+fits_in_unsigned_byte (offsetT num)
 {
   return (num & 0xff) == num;
 }
 
 static INLINE int
-fits_in_unsigned_word (num)
-     offsetT num;
+fits_in_unsigned_word (offsetT num)
 {
   return (num & 0xffff) == num;
 }
 
 static INLINE int
-fits_in_signed_word (num)
-     offsetT num;
+fits_in_signed_word (offsetT num)
 {
   return (-32768 <= num) && (num <= 32767);
 }
+
 static INLINE int
-fits_in_signed_long (num)
-     offsetT num ATTRIBUTE_UNUSED;
+fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
 {
 #ifndef BFD64
   return 1;
@@ -650,9 +916,9 @@ fits_in_signed_long (num)
 	  || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
 #endif
 }				/* fits_in_signed_long() */
+
 static INLINE int
-fits_in_unsigned_long (num)
-     offsetT num ATTRIBUTE_UNUSED;
+fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
 {
 #ifndef BFD64
   return 1;
@@ -661,11 +927,10 @@ fits_in_unsigned_long (num)
 #endif
 }				/* fits_in_unsigned_long() */
 
-static int
-smallest_imm_type (num)
-     offsetT num;
+static unsigned int
+smallest_imm_type (offsetT num)
 {
-  if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
+  if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
     {
       /* This code is disabled on the 486 because all the Imm1 forms
 	 in the opcode table are slower on the i486.  They're the
@@ -689,9 +954,7 @@ smallest_imm_type (num)
 }
 
 static offsetT
-offset_in_range (val, size)
-     offsetT val;
-     int size;
+offset_in_range (offsetT val, int size)
 {
   addressT mask;
 
@@ -726,8 +989,7 @@ offset_in_range (val, size)
    class already exists, 1 if non rep/repne added, 2 if rep/repne
    added.  */
 static int
-add_prefix (prefix)
-     unsigned int prefix;
+add_prefix (unsigned int prefix)
 {
   int ret = 1;
   unsigned int q;
@@ -735,9 +997,9 @@ add_prefix (prefix)
   if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
       && flag_code == CODE_64BIT)
     {
-      if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
-	  || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
-	      && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
+      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
+	  || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
+	      && (prefix & (REX_R | REX_X | REX_B))))
 	ret = 0;
       q = REX_PREFIX;
     }
@@ -794,8 +1056,7 @@ add_prefix (prefix)
 }
 
 static void
-set_code_flag (value)
-     int value;
+set_code_flag (int value)
 {
   flag_code = value;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
@@ -812,8 +1073,7 @@ set_code_flag (value)
 }
 
 static void
-set_16bit_gcc_code_flag (new_code_flag)
-     int new_code_flag;
+set_16bit_gcc_code_flag (int new_code_flag)
 {
   flag_code = new_code_flag;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
@@ -822,8 +1082,7 @@ set_16bit_gcc_code_flag (new_code_flag)
 }
 
 static void
-set_intel_syntax (syntax_flag)
-     int syntax_flag;
+set_intel_syntax (int syntax_flag)
 {
   /* Find out if register prefixing is specified.  */
   int ask_naked_reg = 0;
@@ -854,11 +1113,11 @@ set_intel_syntax (syntax_flag)
 
   identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
   identifier_chars['$'] = intel_syntax ? '$' : 0;
+  register_prefix = allow_naked_reg ? "" : "%";
 }
 
 static void
-set_cpu_arch (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 {
   SKIP_WHITESPACE ();
 
@@ -866,9 +1125,9 @@ set_cpu_arch (dummy)
     {
       char *string = input_line_pointer;
       int e = get_symbol_end ();
-      int i;
+      unsigned int i;
 
-      for (i = 0; cpu_arch[i].name; i++)
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
 	{
 	  if (strcmp (string, cpu_arch[i].name) == 0)
 	    {
@@ -877,7 +1136,15 @@ set_cpu_arch (dummy)
 		  cpu_arch_name = cpu_arch[i].name;
 		  cpu_sub_arch_name = NULL;
 		  cpu_arch_flags = (cpu_arch[i].flags
-				    | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
+				    | (flag_code == CODE_64BIT
+				       ? Cpu64 : CpuNo64));
+		  cpu_arch_isa = cpu_arch[i].type;
+		  cpu_arch_isa_flags = cpu_arch[i].flags;
+		  if (!cpu_arch_tune_set)
+		    {
+		      cpu_arch_tune = cpu_arch_isa;
+		      cpu_arch_tune_flags = cpu_arch_isa_flags;
+		    }
 		  break;
 		}
 	      if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
@@ -890,7 +1157,7 @@ set_cpu_arch (dummy)
 	      return;
 	    }
 	}
-      if (!cpu_arch[i].name)
+      if (i >= ARRAY_SIZE (cpu_arch))
 	as_bad (_("no such architecture: `%s'"), string);
 
       *input_line_pointer = e;
@@ -976,10 +1243,9 @@ md_begin ()
   reg_hash = hash_new ();
   {
     const reg_entry *regtab;
+    unsigned int regtab_size = i386_regtab_size;
 
-    for (regtab = i386_regtab;
-	 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
-	 regtab++)
+    for (regtab = i386_regtab; regtab_size--; regtab++)
       {
 	hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
 	if (hash_err)
@@ -1034,6 +1300,7 @@ md_begin ()
 #endif
     digit_chars['-'] = '-';
     mnemonic_chars['-'] = '-';
+    mnemonic_chars['.'] = '.';
     identifier_chars['_'] = '_';
     identifier_chars['.'] = '.';
 
@@ -1063,8 +1330,7 @@ md_begin ()
 }
 
 void
-i386_print_statistics (file)
-     FILE *file;
+i386_print_statistics (FILE *file)
 {
   hash_print_statistics (file, "i386 opcode", op_hash);
   hash_print_statistics (file, "i386 register", reg_hash);
@@ -1073,16 +1339,13 @@ i386_print_statistics (file)
 #ifdef DEBUG386
 
 /* Debugging routines for md_assemble.  */
-static void pi PARAMS ((char *, i386_insn *));
-static void pte PARAMS ((template *));
-static void pt PARAMS ((unsigned int));
-static void pe PARAMS ((expressionS *));
-static void ps PARAMS ((symbolS *));
+static void pte (template *);
+static void pt (unsigned int);
+static void pe (expressionS *);
+static void ps (symbolS *);
 
 static void
-pi (line, x)
-     char *line;
-     i386_insn *x;
+pi (char *line, i386_insn *x)
 {
   unsigned int i;
 
@@ -1097,10 +1360,10 @@ pi (line, x)
   fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
 	   x->sib.base, x->sib.index, x->sib.scale);
   fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
-	   (x->rex & REX_MODE64) != 0,
-	   (x->rex & REX_EXTX) != 0,
-	   (x->rex & REX_EXTY) != 0,
-	   (x->rex & REX_EXTZ) != 0);
+	   (x->rex & REX_W) != 0,
+	   (x->rex & REX_R) != 0,
+	   (x->rex & REX_X) != 0,
+	   (x->rex & REX_B) != 0);
   for (i = 0; i < x->operands; i++)
     {
       fprintf (stdout, "    #%d:  ", i + 1);
@@ -1117,8 +1380,7 @@ pi (line, x)
 }
 
 static void
-pte (t)
-     template *t;
+pte (template *t)
 {
   unsigned int i;
   fprintf (stdout, " %d operands ", t->operands);
@@ -1139,8 +1401,7 @@ pte (t)
 }
 
 static void
-pe (e)
-     expressionS *e;
+pe (expressionS *e)
 {
   fprintf (stdout, "    operation     %d\n", e->X_op);
   fprintf (stdout, "    add_number    %ld (%lx)\n",
@@ -1160,8 +1421,7 @@ pe (e)
 }
 
 static void
-ps (s)
-     symbolS *s;
+ps (symbolS *s)
 {
   fprintf (stdout, "%s type %s%s",
 	   S_GET_NAME (s),
@@ -1226,9 +1486,9 @@ pt (t)
 
 static bfd_reloc_code_real_type
 reloc (unsigned int size,
-     int pcrel,
-     int sign,
-     bfd_reloc_code_real_type other)
+       int pcrel,
+       int sign,
+       bfd_reloc_code_real_type other)
 {
   if (other != NO_RELOC)
     {
@@ -1237,26 +1497,26 @@ reloc (unsigned int size,
       if (size == 8)
 	switch (other)
 	  {
-	    case BFD_RELOC_X86_64_GOT32:
-	      return BFD_RELOC_X86_64_GOT64;
-	      break;
-	    case BFD_RELOC_X86_64_PLTOFF64:
-	      return BFD_RELOC_X86_64_PLTOFF64;
-	      break;
-	    case BFD_RELOC_X86_64_GOTPC32:
-	      other = BFD_RELOC_X86_64_GOTPC64;
-	      break;
-	    case BFD_RELOC_X86_64_GOTPCREL:
-	      other = BFD_RELOC_X86_64_GOTPCREL64;
-	      break;
-	    case BFD_RELOC_X86_64_TPOFF32:
-	      other = BFD_RELOC_X86_64_TPOFF64;
-	      break;
-	    case BFD_RELOC_X86_64_DTPOFF32:
-	      other = BFD_RELOC_X86_64_DTPOFF64;
-	      break;
-	    default:
-	      break;
+	  case BFD_RELOC_X86_64_GOT32:
+	    return BFD_RELOC_X86_64_GOT64;
+	    break;
+	  case BFD_RELOC_X86_64_PLTOFF64:
+	    return BFD_RELOC_X86_64_PLTOFF64;
+	    break;
+	  case BFD_RELOC_X86_64_GOTPC32:
+	    other = BFD_RELOC_X86_64_GOTPC64;
+	    break;
+	  case BFD_RELOC_X86_64_GOTPCREL:
+	    other = BFD_RELOC_X86_64_GOTPCREL64;
+	    break;
+	  case BFD_RELOC_X86_64_TPOFF32:
+	    other = BFD_RELOC_X86_64_TPOFF64;
+	    break;
+	  case BFD_RELOC_X86_64_DTPOFF32:
+	    other = BFD_RELOC_X86_64_DTPOFF64;
+	    break;
+	  default:
+	    break;
 	  }
 
       /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
@@ -1275,7 +1535,7 @@ reloc (unsigned int size,
       else if ((reloc->complain_on_overflow == complain_overflow_signed
 		&& !sign)
 	       || (reloc->complain_on_overflow == complain_overflow_unsigned
-		&& sign > 0))
+		   && sign > 0))
 	as_bad (_("relocated field and relocation type differ in signedness"));
       else
 	return other;
@@ -1324,8 +1584,7 @@ reloc (unsigned int size,
    some cases we force the original symbol to be used.  */
 
 int
-tc_i386_fix_adjustable (fixP)
-     fixS *fixP ATTRIBUTE_UNUSED;
+tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
 {
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
   if (!IS_ELF)
@@ -1378,11 +1637,8 @@ tc_i386_fix_adjustable (fixP)
   return 1;
 }
 
-static int intel_float_operand PARAMS ((const char *mnemonic));
-
 static int
-intel_float_operand (mnemonic)
-     const char *mnemonic;
+intel_float_operand (const char *mnemonic)
 {
   /* Note that the value returned is meaningful only for opcodes with (memory)
      operands, hence the code here is free to improperly handle opcodes that
@@ -1465,16 +1721,29 @@ md_assemble (line)
   if (line == NULL)
     return;
 
+  /* The order of the immediates should be reversed
+     for 2 immediates extrq and insertq instructions */
+  if ((i.imm_operands == 2)
+      && ((strcmp (mnemonic, "extrq") == 0)
+	  || (strcmp (mnemonic, "insertq") == 0)))
+    {
+      swap_2_operands (0, 1);
+      /* "extrq" and insertq" are the only two instructions whose operands
+	 have to be reversed even though they have two immediate operands.
+      */
+      if (intel_syntax)
+	swap_operands ();
+    }
+
   /* Now we've parsed the mnemonic into a set of templates, and have the
      operands at hand.  */
 
   /* All intel opcodes have reversed operands except for "bound" and
      "enter".  We also don't reverse intersegment "jmp" and "call"
      instructions with 2 immediate operands so that the immediate segment
-     precedes the offset, as it does when in AT&T mode.  "enter" and the
-     intersegment "jmp" and "call" instructions are the only ones that
-     have two immediate operands.  */
-  if (intel_syntax && i.operands > 1
+     precedes the offset, as it does when in AT&T mode. */
+  if (intel_syntax
+      && i.operands > 1
       && (strcmp (mnemonic, "bound") != 0)
       && (strcmp (mnemonic, "invlpga") != 0)
       && !((i.types[0] & Imm) && (i.types[1] & Imm)))
@@ -1502,7 +1771,7 @@ md_assemble (line)
       /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
       if (SYSV386_COMPAT
 	  && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
-	i.tm.base_opcode ^= FloatR;
+	i.tm.base_opcode ^= Opcode_FloatR;
 
       /* Zap movzx and movsx suffix.  The suffix may have been set from
 	 "word ptr" or "byte ptr" on the source operand, but we'll use
@@ -1556,9 +1825,9 @@ md_assemble (line)
     {
       expressionS *exp;
 
-      if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
+      if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
 	{
-	  /* These Intel Prescott New Instructions have the fixed
+	  /* Streaming SIMD extensions 3 Instructions have the fixed
 	     operands with an opcode suffix which is coded in the same
 	     place as an 8-bit immediate field would be. Here we check
 	     those operands and remove them afterwards.  */
@@ -1566,8 +1835,11 @@ md_assemble (line)
 
 	  for (x = 0; x < i.operands; x++)
 	    if (i.op[x].regs->reg_num != x)
-	      as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
-			i.op[x].regs->reg_name, x + 1, i.tm.name);
+	      as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
+		      register_prefix,
+		      i.op[x].regs->reg_name,
+		      x + 1,
+		      i.tm.name);
 	  i.operands = 0;
  	}
 
@@ -1616,7 +1888,7 @@ md_assemble (line)
     }
 
   if ((i.tm.opcode_modifier & Rex64) != 0)
-    i.rex |= REX_MODE64;
+    i.rex |= REX_W;
 
   /* For 8 bit registers we need an empty rex prefix.  Also if the
      instruction already has a prefix, we need to convert old
@@ -1640,8 +1912,9 @@ md_assemble (line)
 	    {
 	      /* In case it is "hi" register, give up.  */
 	      if (i.op[x].regs->reg_num > 3)
-		as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
-			i.op[x].regs->reg_name);
+		as_bad (_("can't encode register '%s%s' in an "
+			  "instruction requiring REX prefix."),
+			register_prefix, i.op[x].regs->reg_name);
 
 	      /* Otherwise it is equivalent to the extended register.
 		 Since the encoding doesn't change this is merely
@@ -1660,9 +1933,7 @@ md_assemble (line)
 }
 
 static char *
-parse_insn (line, mnemonic)
-     char *line;
-     char *mnemonic;
+parse_insn (char *line, char *mnemonic)
 {
   char *l = line;
   char *token_start = l;
@@ -1832,9 +2103,9 @@ parse_insn (line, mnemonic)
     {
       if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
 	    & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
-	  supported |= 1;
+	supported |= 1;
       if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
-	  supported |= 2;
+	supported |= 2;
     }
   if (!(supported & 2))
     {
@@ -1867,7 +2138,7 @@ parse_insn (line, mnemonic)
       if (t >= current_templates->end)
 	{
 	  as_bad (_("expecting string instruction after `%s'"),
-	        expecting_string_instruction);
+		  expecting_string_instruction);
 	  return NULL;
 	}
       for (override.start = t; t < current_templates->end; ++t)
@@ -1881,9 +2152,7 @@ parse_insn (line, mnemonic)
 }
 
 static char *
-parse_operands (l, mnemonic)
-     char *l;
-     const char *mnemonic;
+parse_operands (char *l, const char *mnemonic)
 {
   char *token_start;
 
@@ -2001,24 +2270,12 @@ parse_operands (l, mnemonic)
 }
 
 static void
-swap_operands ()
+swap_2_operands (int xchg1, int xchg2)
 {
   union i386_op temp_op;
   unsigned int temp_type;
   enum bfd_reloc_code_real temp_reloc;
-  int xchg1 = 0;
-  int xchg2 = 0;
 
-  if (i.operands == 2)
-    {
-      xchg1 = 0;
-      xchg2 = 1;
-    }
-  else if (i.operands == 3)
-    {
-      xchg1 = 0;
-      xchg2 = 2;
-    }
   temp_type = i.types[xchg2];
   i.types[xchg2] = i.types[xchg1];
   i.types[xchg1] = temp_type;
@@ -2028,6 +2285,22 @@ swap_operands ()
   temp_reloc = i.reloc[xchg2];
   i.reloc[xchg2] = i.reloc[xchg1];
   i.reloc[xchg1] = temp_reloc;
+}
+
+static void
+swap_operands (void)
+{
+  switch (i.operands)
+    {
+    case 4:
+      swap_2_operands (1, i.operands - 2);
+    case 3:
+    case 2:
+      swap_2_operands (0, i.operands - 1);
+      break;
+    default:
+      abort ();
+    }
 
   if (i.mem_operands == 2)
     {
@@ -2041,7 +2314,7 @@ swap_operands ()
 /* Try to ensure constant immediates are represented in the smallest
    opcode possible.  */
 static void
-optimize_imm ()
+optimize_imm (void)
 {
   char guess_suffix = 0;
   int op;
@@ -2131,8 +2404,10 @@ optimize_imm ()
 	      unsigned int mask, allowed = 0;
 	      const template *t;
 
-	      for (t = current_templates->start; t < current_templates->end; ++t)
-	        allowed |= t->operand_types[op];
+	      for (t = current_templates->start;
+		   t < current_templates->end;
+		   ++t)
+		allowed |= t->operand_types[op];
 	      switch (guess_suffix)
 		{
 		case QWORD_MNEM_SUFFIX:
@@ -2151,8 +2426,8 @@ optimize_imm ()
 		  mask = 0;
 		  break;
 		}
-		if (mask & allowed)
-		  i.types[op] &= mask;
+	      if (mask & allowed)
+		i.types[op] &= mask;
 	    }
 	    break;
 	  }
@@ -2161,7 +2436,7 @@ optimize_imm ()
 
 /* Try to use the smallest displacement type too.  */
 static void
-optimize_disp ()
+optimize_disp (void)
 {
   int op;
 
@@ -2225,13 +2500,20 @@ optimize_disp ()
 }
 
 static int
-match_template ()
+match_template (void)
 {
   /* Points to template once we've found it.  */
   const template *t;
-  unsigned int overlap0, overlap1, overlap2;
+  unsigned int overlap0, overlap1, overlap2, overlap3;
   unsigned int found_reverse_match;
   int suffix_check;
+  unsigned int operand_types [MAX_OPERANDS];
+  int addr_prefix_disp;
+  unsigned int j;
+
+#if MAX_OPERANDS != 4
+# error "MAX_OPERANDS must be 4."
+#endif
 
 #define MATCH(overlap, given, template)				\
   ((overlap & ~JumpAbsolute)					\
@@ -2249,7 +2531,11 @@ match_template ()
   overlap0 = 0;
   overlap1 = 0;
   overlap2 = 0;
+  overlap3 = 0;
   found_reverse_match = 0;
+  for (j = 0; j < MAX_OPERANDS; j++)
+    operand_types [j] = 0;
+  addr_prefix_disp = -1;
   suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
 		  ? No_bSuf
 		  : (i.suffix == WORD_MNEM_SUFFIX
@@ -2265,6 +2551,8 @@ match_template ()
 
   for (t = current_templates->start; t < current_templates->end; t++)
     {
+      addr_prefix_disp = -1;
+
       /* Must have right number of operands.  */
       if (i.operands != t->operands)
 	continue;
@@ -2275,6 +2563,9 @@ match_template ()
 	       && (t->opcode_modifier & IgnoreSize)))
 	continue;
 
+      for (j = 0; j < MAX_OPERANDS; j++)
+	operand_types [j] = t->operand_types [j];
+
       /* In general, don't allow 64-bit operands in 32-bit mode.  */
       if (i.suffix == QWORD_MNEM_SUFFIX
 	  && flag_code != CODE_64BIT
@@ -2282,8 +2573,8 @@ match_template ()
 	      ? (!(t->opcode_modifier & IgnoreSize)
 		 && !intel_float_operand (t->name))
 	      : intel_float_operand (t->name) != 2)
-	  && (!(t->operand_types[0] & (RegMMX | RegXMM))
-	      || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
+	  && (!(operand_types[0] & (RegMMX | RegXMM))
+	      || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
 	  && (t->base_opcode != 0x0fc7
 	      || t->extension_opcode != 1 /* cmpxchg8b */))
 	continue;
@@ -2297,66 +2588,142 @@ match_template ()
 	  break;
 	}
 
-      overlap0 = i.types[0] & t->operand_types[0];
+      /* Address size prefix will turn Disp64/Disp32/Disp16 operand
+	 into Disp32/Disp16/Disp32 operand.  */
+      if (i.prefix[ADDR_PREFIX] != 0)
+	  {
+	    unsigned int DispOn = 0, DispOff = 0;
+
+	    switch (flag_code)
+	    {
+	    case CODE_16BIT:
+	      DispOn = Disp32;
+	      DispOff = Disp16;
+	      break;
+	    case CODE_32BIT:
+	      DispOn = Disp16;
+	      DispOff = Disp32;
+	      break;
+	    case CODE_64BIT:
+	      DispOn = Disp32;
+	      DispOff = Disp64;
+	      break;
+	    }
+
+	    for (j = 0; j < MAX_OPERANDS; j++)
+	      {
+		/* There should be only one Disp operand.  */
+		if ((operand_types[j] & DispOff))
+		  {
+		    addr_prefix_disp = j;
+		    operand_types[j] |= DispOn;
+		    operand_types[j] &= ~DispOff;
+		    break;
+		  }
+	      }
+	  }
+
+      overlap0 = i.types[0] & operand_types[0];
       switch (t->operands)
 	{
 	case 1:
-	  if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
+	  if (!MATCH (overlap0, i.types[0], operand_types[0]))
 	    continue;
 	  break;
 	case 2:
+	  /* xchg %eax, %eax is a special case. It is an aliase for nop
+	     only in 32bit mode and we can use opcode 0x90.  In 64bit
+	     mode, we can't use 0x90 for xchg %eax, %eax since it should
+	     zero-extend %eax to %rax.  */
+	  if (flag_code == CODE_64BIT
+	      && t->base_opcode == 0x90
+	      && i.types [0] == (Acc | Reg32)
+	      && i.types [1] == (Acc | Reg32))
+	    continue;
 	case 3:
-	  overlap1 = i.types[1] & t->operand_types[1];
-	  if (!MATCH (overlap0, i.types[0], t->operand_types[0])
-	      || !MATCH (overlap1, i.types[1], t->operand_types[1])
+	case 4:
+	  overlap1 = i.types[1] & operand_types[1];
+	  if (!MATCH (overlap0, i.types[0], operand_types[0])
+	      || !MATCH (overlap1, i.types[1], operand_types[1])
 	      /* monitor in SSE3 is a very special case.  The first
-		 register and the second register may have differnet
-		 sizes.  */
+		 register and the second register may have different
+		 sizes.  The same applies to crc32 in SSE4.2.  */
 	      || !((t->base_opcode == 0x0f01
 		    && t->extension_opcode == 0xc8)
+		   || t->base_opcode == 0xf20f38f1
 		   || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
-						 t->operand_types[0],
+						 operand_types[0],
 						 overlap1, i.types[1],
-						 t->operand_types[1])))
+						 operand_types[1])))
 	    {
 	      /* Check if other direction is valid ...  */
 	      if ((t->opcode_modifier & (D | FloatD)) == 0)
 		continue;
 
 	      /* Try reversing direction of operands.  */
-	      overlap0 = i.types[0] & t->operand_types[1];
-	      overlap1 = i.types[1] & t->operand_types[0];
-	      if (!MATCH (overlap0, i.types[0], t->operand_types[1])
-		  || !MATCH (overlap1, i.types[1], t->operand_types[0])
+	      overlap0 = i.types[0] & operand_types[1];
+	      overlap1 = i.types[1] & operand_types[0];
+	      if (!MATCH (overlap0, i.types[0], operand_types[1])
+		  || !MATCH (overlap1, i.types[1], operand_types[0])
 		  || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
-						 t->operand_types[1],
+						 operand_types[1],
 						 overlap1, i.types[1],
-						 t->operand_types[0]))
+						 operand_types[0]))
 		{
 		  /* Does not match either direction.  */
 		  continue;
 		}
 	      /* found_reverse_match holds which of D or FloatDR
 		 we've found.  */
-	      found_reverse_match = t->opcode_modifier & (D | FloatDR);
+	      if ((t->opcode_modifier & D))
+		found_reverse_match = Opcode_D;
+	      else if ((t->opcode_modifier & FloatD))
+		found_reverse_match = Opcode_FloatD;
+	      else
+		found_reverse_match = 0;
+	      if ((t->opcode_modifier & FloatR))
+		found_reverse_match |= Opcode_FloatR;
 	    }
-	  /* Found a forward 2 operand match here.  */
-	  else if (t->operands == 3)
+	  else
 	    {
-	      /* Here we make use of the fact that there are no
-		 reverse match 3 operand instructions, and all 3
-		 operand instructions only need to be checked for
-		 register consistency between operands 2 and 3.  */
-	      overlap2 = i.types[2] & t->operand_types[2];
-	      if (!MATCH (overlap2, i.types[2], t->operand_types[2])
-		  || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
-						 t->operand_types[1],
-						 overlap2, i.types[2],
-						 t->operand_types[2]))
+	      /* Found a forward 2 operand match here.  */
+	      switch (t->operands)
+		{
+		case 4:
+		  overlap3 = i.types[3] & operand_types[3];
+		case 3:
+		  overlap2 = i.types[2] & operand_types[2];
+		  break;
+		}
 
-		continue;
+	      switch (t->operands)
+		{
+		case 4:
+		  if (!MATCH (overlap3, i.types[3], operand_types[3])
+		      || !CONSISTENT_REGISTER_MATCH (overlap2,
+						     i.types[2],
+						     operand_types[2],
+						     overlap3,
+						     i.types[3],
+						     operand_types[3]))
+		    continue;
+		case 3:
+		  /* Here we make use of the fact that there are no
+		     reverse match 3 operand instructions, and all 3
+		     operand instructions only need to be checked for
+		     register consistency between operands 2 and 3.  */
+		  if (!MATCH (overlap2, i.types[2], operand_types[2])
+		      || !CONSISTENT_REGISTER_MATCH (overlap1,
+						     i.types[1],
+						     operand_types[1],
+						     overlap2,
+						     i.types[2],
+						     operand_types[2]))
+		    continue;
+		  break;
+		}
 	    }
-	  /* Found either forward/reverse 2 or 3 operand match here:
+	  /* Found either forward/reverse 2, 3 or 4 operand match here:
 	     slip through to break.  */
 	}
       if (t->cpu_flags & ~cpu_arch_flags)
@@ -2380,7 +2747,7 @@ match_template ()
     {
       if (!intel_syntax
 	  && ((i.types[0] & JumpAbsolute)
-	      != (t->operand_types[0] & JumpAbsolute)))
+	      != (operand_types[0] & JumpAbsolute)))
 	{
 	  as_warn (_("indirect %s without `*'"), t->name);
 	}
@@ -2396,6 +2763,11 @@ match_template ()
 
   /* Copy the template we found.  */
   i.tm = *t;
+
+  if (addr_prefix_disp != -1)
+    i.tm.operand_types[addr_prefix_disp]
+      = operand_types[addr_prefix_disp];
+
   if (found_reverse_match)
     {
       /* If we found a reverse match we must alter the opcode
@@ -2404,15 +2776,15 @@ match_template ()
 
       i.tm.base_opcode ^= found_reverse_match;
 
-      i.tm.operand_types[0] = t->operand_types[1];
-      i.tm.operand_types[1] = t->operand_types[0];
+      i.tm.operand_types[0] = operand_types[1];
+      i.tm.operand_types[1] = operand_types[0];
     }
 
   return 1;
 }
 
 static int
-check_string ()
+check_string (void)
 {
   int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
   if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
@@ -2465,19 +2837,44 @@ process_suffix (void)
 	{
 	  /* We take i.suffix from the last register operand specified,
 	     Destination register type is more significant than source
-	     register type.  */
-	  int op;
-
-	  for (op = i.operands; --op >= 0;)
-	    if ((i.types[op] & Reg)
-		&& !(i.tm.operand_types[op] & InOutPortReg))
-	      {
-		i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
-			    (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
-			    (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+	     register type.  crc32 in SSE4.2 prefers source register
+	     type. */
+	  if (i.tm.base_opcode == 0xf20f38f1)
+	    {
+	      if ((i.types[0] & Reg))
+		i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
 			    LONG_MNEM_SUFFIX);
-		break;
-	      }
+	    }
+	  else if (i.tm.base_opcode == 0xf20f38f0)
+	    {
+	      if ((i.types[0] & Reg8))
+		i.suffix = BYTE_MNEM_SUFFIX;
+	    }
+
+	  if (!i.suffix)
+	    {
+	      int op;
+
+	      if (i.tm.base_opcode == 0xf20f38f1
+		  || i.tm.base_opcode == 0xf20f38f0)
+		{
+		  /* We have to know the operand size for crc32.  */
+		  as_bad (_("ambiguous memory operand size for `%s`"),
+			  i.tm.name);
+		  return 0;
+		}
+
+	      for (op = i.operands; --op >= 0;)
+		if ((i.types[op] & Reg)
+		    && !(i.tm.operand_types[op] & InOutPortReg))
+		  {
+		    i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
+				(i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
+				(i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
+				LONG_MNEM_SUFFIX);
+		    break;
+		  }
+	    }
 	}
       else if (i.suffix == BYTE_MNEM_SUFFIX)
 	{
@@ -2515,9 +2912,9 @@ process_suffix (void)
   else if (intel_syntax
 	   && !i.suffix
 	   && ((i.tm.operand_types[0] & JumpAbsolute)
-	    || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
-	    || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
-		&& i.tm.extension_opcode <= 3)))
+	       || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
+	       || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
+		   && i.tm.extension_opcode <= 3)))
     {
       switch (flag_code)
 	{
@@ -2544,19 +2941,20 @@ process_suffix (void)
 	{
 	  if (i.tm.opcode_modifier & W)
 	    {
-	      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
+	      as_bad (_("no instruction mnemonic suffix given and "
+			"no register operands; can't size instruction"));
 	      return 0;
 	    }
 	}
       else
 	{
-	  unsigned int suffixes = ~i.tm.opcode_modifier
-				  & (No_bSuf
-				     | No_wSuf
-				     | No_lSuf
-				     | No_sSuf
-				     | No_xSuf
-				     | No_qSuf);
+	  unsigned int suffixes = (~i.tm.opcode_modifier
+				   & (No_bSuf
+				      | No_wSuf
+				      | No_lSuf
+				      | No_sSuf
+				      | No_xSuf
+				      | No_qSuf));
 
 	  if ((i.tm.opcode_modifier & W)
 	      || ((suffixes & (suffixes - 1))
@@ -2615,7 +3013,15 @@ process_suffix (void)
       if (i.suffix == QWORD_MNEM_SUFFIX
 	  && flag_code == CODE_64BIT
 	  && (i.tm.opcode_modifier & NoRex64) == 0)
-	i.rex |= REX_MODE64;
+	{
+	  /* Special case for xchg %rax,%rax.  It is NOP and doesn't
+	     need rex64.  */
+	  if (i.operands != 2
+	      || i.types [0] != (Acc | Reg64)
+	      || i.types [1] != (Acc | Reg64)
+	      || i.tm.base_opcode != 0x90)
+	    i.rex |= REX_W;
+	}
 
       /* Size floating point instruction.  */
       if (i.suffix == LONG_MNEM_SUFFIX)
@@ -2648,6 +3054,10 @@ check_byte_reg (void)
 	      || i.tm.base_opcode == 0xfbf))
 	continue;
 
+      /* crc32 doesn't generate this warning.  */
+      if (i.tm.base_opcode == 0xf20f38f0)
+	continue;
+
       if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
 	{
 	  /* Prohibit these changes in the 64bit mode, since the
@@ -2655,18 +3065,20 @@ check_byte_reg (void)
 	  if (flag_code == CODE_64BIT
 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
 	    {
-	      as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		      i.op[op].regs->reg_name,
+	      as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		      register_prefix, i.op[op].regs->reg_name,
 		      i.suffix);
 	      return 0;
 	    }
 #if REGISTER_WARNINGS
 	  if (!quiet_warnings
 	      && (i.tm.operand_types[op] & InOutPortReg) == 0)
-	    as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	    as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		     register_prefix,
 		     (i.op[op].regs + (i.types[op] & Reg16
 				       ? REGNAM_AL - REGNAM_AX
 				       : REGNAM_AL - REGNAM_EAX))->reg_name,
+		     register_prefix,
 		     i.op[op].regs->reg_name,
 		     i.suffix);
 #endif
@@ -2678,7 +3090,8 @@ check_byte_reg (void)
 			 | Control | Debug | Test
 			 | FloatReg | FloatAcc))
 	{
-	  as_bad (_("`%%%s' not allowed with `%s%c'"),
+	  as_bad (_("`%s%s' not allowed with `%s%c'"),
+		  register_prefix,
 		  i.op[op].regs->reg_name,
 		  i.tm.name,
 		  i.suffix);
@@ -2689,7 +3102,7 @@ check_byte_reg (void)
 }
 
 static int
-check_long_reg ()
+check_long_reg (void)
 {
   int op;
 
@@ -2699,7 +3112,8 @@ check_long_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2714,15 +3128,17 @@ check_long_reg ()
 	   lowering is more complicated.  */
 	if (flag_code == CODE_64BIT)
 	  {
-	    as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		    i.op[op].regs->reg_name,
+	    as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		    register_prefix, i.op[op].regs->reg_name,
 		    i.suffix);
 	    return 0;
 	  }
 #if REGISTER_WARNINGS
 	else
-	  as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	  as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		   register_prefix,
 		   (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
+		   register_prefix,
 		   i.op[op].regs->reg_name,
 		   i.suffix);
 #endif
@@ -2731,8 +3147,8 @@ check_long_reg ()
     else if ((i.types[op] & Reg64) != 0
 	     && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
       {
-	as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		i.op[op].regs->reg_name,
+	as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		register_prefix, i.op[op].regs->reg_name,
 		i.suffix);
 	return 0;
       }
@@ -2740,7 +3156,7 @@ check_long_reg ()
 }
 
 static int
-check_qword_reg ()
+check_qword_reg (void)
 {
   int op;
 
@@ -2750,7 +3166,8 @@ check_qword_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2763,8 +3180,8 @@ check_qword_reg ()
       {
 	/* Prohibit these changes in the 64bit mode, since the
 	   lowering is more complicated.  */
-	as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		i.op[op].regs->reg_name,
+	as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		register_prefix, i.op[op].regs->reg_name,
 		i.suffix);
 	return 0;
       }
@@ -2772,7 +3189,7 @@ check_qword_reg ()
 }
 
 static int
-check_word_reg ()
+check_word_reg (void)
 {
   int op;
   for (op = i.operands; --op >= 0;)
@@ -2781,7 +3198,8 @@ check_word_reg ()
     if ((i.types[op] & Reg8) != 0
 	&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
       {
-	as_bad (_("`%%%s' not allowed with `%s%c'"),
+	as_bad (_("`%s%s' not allowed with `%s%c'"),
+		register_prefix,
 		i.op[op].regs->reg_name,
 		i.tm.name,
 		i.suffix);
@@ -2796,15 +3214,17 @@ check_word_reg ()
 	   lowering is more complicated.  */
 	if (flag_code == CODE_64BIT)
 	  {
-	    as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
-		    i.op[op].regs->reg_name,
+	    as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
+		    register_prefix, i.op[op].regs->reg_name,
 		    i.suffix);
 	    return 0;
 	  }
 	else
 #if REGISTER_WARNINGS
-	  as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
+	  as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
+		   register_prefix,
 		   (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
+		   register_prefix,
 		   i.op[op].regs->reg_name,
 		   i.suffix);
 #endif
@@ -2813,7 +3233,7 @@ check_word_reg ()
 }
 
 static int
-finalize_imm ()
+finalize_imm (void)
 {
   unsigned int overlap0, overlap1, overlap2;
 
@@ -2844,7 +3264,8 @@ finalize_imm ()
 	  && overlap0 != Imm16 && overlap0 != Imm32S
 	  && overlap0 != Imm32 && overlap0 != Imm64)
 	{
-	  as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
+	  as_bad (_("no instruction mnemonic suffix given; "
+		    "can't determine immediate size"));
 	  return 0;
 	}
     }
@@ -2877,7 +3298,9 @@ finalize_imm ()
 	  && overlap1 != Imm16 && overlap1 != Imm32S
 	  && overlap1 != Imm32 && overlap1 != Imm64)
 	{
-	  as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
+	  as_bad (_("no instruction mnemonic suffix given; "
+		    "can't determine immediate size %x %c"),
+		  overlap1, i.suffix);
 	  return 0;
 	}
     }
@@ -2891,7 +3314,7 @@ finalize_imm ()
 }
 
 static int
-process_operands ()
+process_operands (void)
 {
   /* Default segment register this instruction will use for memory
      accesses.  0 means unknown.  This is only for optimizing out
@@ -2901,40 +3324,90 @@ process_operands ()
   /* The imul $imm, %reg instruction is converted into
      imul $imm, %reg, %reg, and the clr %reg instruction
      is converted into xor %reg, %reg.  */
-  if (i.tm.opcode_modifier & regKludge)
-    {
-      unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
-      /* Pretend we saw the extra register operand.  */
-      assert (i.op[first_reg_op + 1].regs == 0);
-      i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
-      i.types[first_reg_op + 1] = i.types[first_reg_op];
-      i.reg_operands = 2;
+  if (i.tm.opcode_modifier & RegKludge)
+    {
+       if ((i.tm.cpu_flags & CpuSSE4_1))
+	 {
+	   /* The first operand in instruction blendvpd, blendvps and
+	      pblendvb in SSE4.1 is implicit and must be xmm0.  */
+	   assert (i.operands == 3
+		   && i.reg_operands >= 2
+		   && i.types[0] == RegXMM);
+	   if (i.op[0].regs->reg_num != 0)
+	     {
+	       if (intel_syntax)
+		 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
+			 i.tm.name, register_prefix);
+	       else
+		 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
+			 i.tm.name, register_prefix);
+	       return 0;
+	     }
+	   i.op[0] = i.op[1];
+	   i.op[1] = i.op[2];
+	   i.types[0] = i.types[1];
+	   i.types[1] = i.types[2];
+	   i.operands--;
+	   i.reg_operands--;
+
+	   /* We need to adjust fields in i.tm since they are used by
+	      build_modrm_byte.  */
+	   i.tm.operand_types [0] = i.tm.operand_types [1];
+	   i.tm.operand_types [1] = i.tm.operand_types [2];
+	   i.tm.operands--;
+	 }
+       else
+	 {
+	   unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
+	   /* Pretend we saw the extra register operand.  */
+	   assert (i.reg_operands == 1
+		   && i.op[first_reg_op + 1].regs == 0);
+	   i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
+	   i.types[first_reg_op + 1] = i.types[first_reg_op];
+	   i.operands++;
+	   i.reg_operands++;
+	 }
     }
 
   if (i.tm.opcode_modifier & ShortForm)
     {
-      /* The register or float register operand is in operand 0 or 1.  */
-      unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
-      /* Register goes in low 3 bits of opcode.  */
-      i.tm.base_opcode |= i.op[op].regs->reg_num;
-      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-	i.rex |= REX_EXTZ;
-      if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
+      if (i.types[0] & (SReg2 | SReg3))
 	{
-	  /* Warn about some common errors, but press on regardless.
-	     The first case can be generated by gcc (<= 2.8.1).  */
-	  if (i.operands == 2)
+	  if (i.tm.base_opcode == POP_SEG_SHORT
+	      && i.op[0].regs->reg_num == 1)
 	    {
-	      /* Reversed arguments on faddp, fsubp, etc.  */
-	      as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
-		       i.op[1].regs->reg_name,
-		       i.op[0].regs->reg_name);
+	      as_bad (_("you can't `pop %%cs'"));
+	      return 0;
 	    }
-	  else
+	  i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
+	  if ((i.op[0].regs->reg_flags & RegRex) != 0)
+	    i.rex |= REX_B;
+	}
+      else
+	{
+	  /* The register or float register operand is in operand 0 or 1.  */
+	  unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
+	  /* Register goes in low 3 bits of opcode.  */
+	  i.tm.base_opcode |= i.op[op].regs->reg_num;
+	  if ((i.op[op].regs->reg_flags & RegRex) != 0)
+	    i.rex |= REX_B;
+	  if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
 	    {
-	      /* Extraneous `l' suffix on fp insn.  */
-	      as_warn (_("translating to `%s %%%s'"), i.tm.name,
-		       i.op[0].regs->reg_name);
+	      /* Warn about some common errors, but press on regardless.
+		 The first case can be generated by gcc (<= 2.8.1).  */
+	      if (i.operands == 2)
+		{
+		  /* Reversed arguments on faddp, fsubp, etc.  */
+		  as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
+			   register_prefix, i.op[1].regs->reg_name,
+			   register_prefix, i.op[0].regs->reg_name);
+		}
+	      else
+		{
+		  /* Extraneous `l' suffix on fp insn.  */
+		  as_warn (_("translating to `%s %s%s'"), i.tm.name,
+			   register_prefix, i.op[0].regs->reg_name);
+		}
 	    }
 	}
     }
@@ -2946,19 +3419,7 @@ process_operands ()
 
       default_seg = build_modrm_byte ();
     }
-  else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
-    {
-      if (i.tm.base_opcode == POP_SEG_SHORT
-	  && i.op[0].regs->reg_num == 1)
-	{
-	  as_bad (_("you can't `pop %%cs'"));
-	  return 0;
-	}
-      i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
-      if ((i.op[0].regs->reg_flags & RegRex) != 0)
-	i.rex |= REX_EXTZ;
-    }
-  else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
+  else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
     {
       default_seg = &ds;
     }
@@ -2988,7 +3449,7 @@ process_operands ()
 }
 
 static const seg_entry *
-build_modrm_byte ()
+build_modrm_byte (void)
 {
   const seg_entry *default_seg = 0;
 
@@ -2997,11 +3458,33 @@ build_modrm_byte ()
   if (i.reg_operands == 2)
     {
       unsigned int source, dest;
-      source = ((i.types[0]
-		 & (Reg | RegMMX | RegXMM
-		    | SReg2 | SReg3
-		    | Control | Debug | Test))
-		? 0 : 1);
+
+      switch (i.operands)
+	{
+	case 2:
+	  source = 0;
+	  break;
+	case 3:
+	  /* When there are 3 operands, one of them may be immediate,
+	     which may be the first or the last operand.  Otherwise,
+	     the first operand must be shift count register (cl). */
+	  assert (i.imm_operands == 1
+		  || (i.imm_operands == 0
+		      && (i.types[0] & ShiftCount)));
+	  source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
+	  break;
+	case 4:
+	  /* When there are 4 operands, the first two must be immediate
+	     operands. The source operand will be the 3rd one.  */
+	  assert (i.imm_operands == 2
+		  && (i.types[0] & Imm)
+		  && (i.types[1] & Imm));
+	  source = 2;
+	  break;
+	default:
+	  abort ();
+	}
+
       dest = source + 1;
 
       i.rm.mode = 3;
@@ -3011,29 +3494,29 @@ build_modrm_byte ()
 	 destination operand, then we assume the source operand may
 	 sometimes be a memory operand and so we need to store the
 	 destination in the i.rm.reg field.  */
-      if ((i.tm.operand_types[dest] & AnyMem) == 0)
+      if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
 	{
 	  i.rm.reg = i.op[dest].regs->reg_num;
 	  i.rm.regmem = i.op[source].regs->reg_num;
 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTX;
+	    i.rex |= REX_R;
 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTZ;
+	    i.rex |= REX_B;
 	}
       else
 	{
 	  i.rm.reg = i.op[source].regs->reg_num;
 	  i.rm.regmem = i.op[dest].regs->reg_num;
 	  if ((i.op[dest].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTZ;
+	    i.rex |= REX_B;
 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
-	    i.rex |= REX_EXTX;
+	    i.rex |= REX_R;
 	}
-      if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
+      if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
 	{
 	  if (!((i.types[0] | i.types[1]) & Control))
 	    abort ();
-	  i.rex &= ~(REX_EXTX | REX_EXTZ);
+	  i.rex &= ~(REX_R | REX_B);
 	  add_prefix (LOCK_PREFIX_OPCODE);
 	}
     }
@@ -3042,9 +3525,12 @@ build_modrm_byte ()
       if (i.mem_operands)
 	{
 	  unsigned int fake_zero_displacement = 0;
-	  unsigned int op = ((i.types[0] & AnyMem)
-			     ? 0
-			     : (i.types[1] & AnyMem) ? 1 : 2);
+	  unsigned int op;
+
+	  for (op = 0; op < i.operands; op++)
+	    if ((i.types[op] & AnyMem))
+	      break;
+	  assert (op < i.operands);
 
 	  default_seg = &ds;
 
@@ -3065,9 +3551,11 @@ build_modrm_byte ()
 		      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
 		      i.sib.base = NO_BASE_REGISTER;
 		      i.sib.index = NO_INDEX_REGISTER;
-		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
+		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
+				     ? Disp32S : Disp32);
 		    }
-		  else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
+		  else if ((flag_code == CODE_16BIT)
+			   ^ (i.prefix[ADDR_PREFIX] != 0))
 		    {
 		      i.rm.regmem = NO_BASE_REGISTER_16;
 		      i.types[op] = Disp16;
@@ -3090,7 +3578,7 @@ build_modrm_byte ()
 		  else
 		    i.types[op] |= Disp32S;
 		  if ((i.index_reg->reg_flags & RegRex) != 0)
-		    i.rex |= REX_EXTY;
+		    i.rex |= REX_X;
 		}
 	    }
 	  /* RIP addressing for 64bit mode.  */
@@ -3099,7 +3587,7 @@ build_modrm_byte ()
 	      i.rm.regmem = NO_BASE_REGISTER;
 	      i.types[op] &= ~ Disp;
 	      i.types[op] |= Disp32S;
-	      i.flags[op] = Operand_PCrel;
+	      i.flags[op] |= Operand_PCrel;
 	      if (! i.disp_operands)
 		fake_zero_displacement = 1;
 	    }
@@ -3137,11 +3625,13 @@ build_modrm_byte ()
 	    {
 	      if (flag_code == CODE_64BIT
 		  && (i.types[op] & Disp))
-		i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
+		i.types[op] = ((i.types[op] & Disp8)
+			       | (i.prefix[ADDR_PREFIX] == 0
+				  ? Disp32S : Disp32));
 
 	      i.rm.regmem = i.base_reg->reg_num;
 	      if ((i.base_reg->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTZ;
+		i.rex |= REX_B;
 	      i.sib.base = i.base_reg->reg_num;
 	      /* x86-64 ignores REX prefix bit here to avoid decoder
 		 complications.  */
@@ -3178,7 +3668,7 @@ build_modrm_byte ()
 		  i.sib.index = i.index_reg->reg_num;
 		  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
 		  if ((i.index_reg->reg_flags & RegRex) != 0)
-		    i.rex |= REX_EXTY;
+		    i.rex |= REX_X;
 		}
 
 	      if (i.disp_operands
@@ -3211,31 +3701,28 @@ build_modrm_byte ()
 	 registers are coded into the i.rm.reg field.  */
       if (i.reg_operands)
 	{
-	  unsigned int op =
-	    ((i.types[0]
-	      & (Reg | RegMMX | RegXMM
-		 | SReg2 | SReg3
-		 | Control | Debug | Test))
-	     ? 0
-	     : ((i.types[1]
-		 & (Reg | RegMMX | RegXMM
-		    | SReg2 | SReg3
-		    | Control | Debug | Test))
-		? 1
-		: 2));
+	  unsigned int op;
+
+	  for (op = 0; op < i.operands; op++)
+	    if ((i.types[op] & (Reg | RegMMX | RegXMM
+				| SReg2 | SReg3
+				| Control | Debug | Test)))
+	      break;
+	  assert (op < i.operands);
+
 	  /* If there is an extension opcode to put here, the register
 	     number must be put into the regmem field.  */
 	  if (i.tm.extension_opcode != None)
 	    {
 	      i.rm.regmem = i.op[op].regs->reg_num;
 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTZ;
+		i.rex |= REX_B;
 	    }
 	  else
 	    {
 	      i.rm.reg = i.op[op].regs->reg_num;
 	      if ((i.op[op].regs->reg_flags & RegRex) != 0)
-		i.rex |= REX_EXTX;
+		i.rex |= REX_R;
 	    }
 
 	  /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
@@ -3253,7 +3740,7 @@ build_modrm_byte ()
 }
 
 static void
-output_branch ()
+output_branch (void)
 {
   char *p;
   int code16;
@@ -3331,7 +3818,7 @@ output_branch ()
 }
 
 static void
-output_jump ()
+output_jump (void)
 {
   char *p;
   int size;
@@ -3397,7 +3884,7 @@ output_jump ()
 }
 
 static void
-output_interseg_jump ()
+output_interseg_jump (void)
 {
   char *p;
   int size;
@@ -3461,7 +3948,7 @@ output_interseg_jump ()
 }
 
 static void
-output_insn ()
+output_insn (void)
 {
   fragS *insn_start_frag;
   offsetT insn_start_off;
@@ -3488,10 +3975,12 @@ output_insn ()
       unsigned char *q;
       unsigned int prefix;
 
-      /* All opcodes on i386 have either 1 or 2 bytes.  Merom New
-	 Instructions have 3 bytes.  We may use one more higher byte
-	 to specify a prefix the instruction requires.  */
-      if ((i.tm.cpu_flags & CpuMNI) != 0)
+      /* All opcodes on i386 have either 1 or 2 bytes.  SSSE3 and
+	 SSE4 instructions have 3 bytes.  We may use one more higher
+	 byte to specify a prefix the instruction requires.  Exclude
+	 instructions which are in both SSE4 and ABM.  */
+      if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+	  && (i.tm.cpu_flags & CpuABM) == 0)
 	{
 	  if (i.tm.base_opcode & 0xff000000)
 	    {
@@ -3504,7 +3993,7 @@ output_insn ()
 	  prefix = (i.tm.base_opcode >> 16) & 0xff;
 	  if ((i.tm.cpu_flags & CpuPadLock) != 0)
 	    {
-check_prefix:
+	    check_prefix:
 	      if (prefix != REPE_PREFIX_OPCODE
 		  || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
 		add_prefix (prefix);
@@ -3532,7 +4021,8 @@ check_prefix:
 	}
       else
 	{
-	  if ((i.tm.cpu_flags & CpuMNI) != 0)
+	  if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+	      && (i.tm.cpu_flags & CpuABM) == 0)
 	    {
 	      p = frag_more (3);
 	      *p++ = (i.tm.base_opcode >> 16) & 0xff;
@@ -3586,10 +4076,42 @@ check_prefix:
 #endif /* DEBUG386  */
 }
 
+/* Return the size of the displacement operand N.  */
+
+static int
+disp_size (unsigned int n)
+{
+  int size = 4;
+  if (i.types[n] & (Disp8 | Disp16 | Disp64))
+    {
+      size = 2;
+      if (i.types[n] & Disp8)
+	size = 1;
+      if (i.types[n] & Disp64)
+	size = 8;
+    }
+  return size;
+}
+
+/* Return the size of the immediate operand N.  */
+
+static int
+imm_size (unsigned int n)
+{
+  int size = 4;
+  if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
+    {
+      size = 2;
+      if (i.types[n] & (Imm8 | Imm8S))
+	size = 1;
+      if (i.types[n] & Imm64)
+	size = 8;
+    }
+  return size;
+}
+
 static void
-output_disp (insn_start_frag, insn_start_off)
-    fragS *insn_start_frag;
-    offsetT insn_start_off;
+output_disp (fragS *insn_start_frag, offsetT insn_start_off)
 {
   char *p;
   unsigned int n;
@@ -3600,18 +4122,9 @@ output_disp (insn_start_frag, insn_start_off)
 	{
 	  if (i.op[n].disps->X_op == O_constant)
 	    {
-	      int size;
+	      int size = disp_size (n);
 	      offsetT val;
 
-	      size = 4;
-	      if (i.types[n] & (Disp8 | Disp16 | Disp64))
-		{
-		  size = 2;
-		  if (i.types[n] & Disp8)
-		    size = 1;
-		  if (i.types[n] & Disp64)
-		    size = 8;
-		}
 	      val = offset_in_range (i.op[n].disps->X_add_number,
 				     size);
 	      p = frag_more (size);
@@ -3620,45 +4133,32 @@ output_disp (insn_start_frag, insn_start_off)
 	  else
 	    {
 	      enum bfd_reloc_code_real reloc_type;
-	      int size = 4;
-	      int sign = 0;
+	      int size = disp_size (n);
+	      int sign = (i.types[n] & Disp32S) != 0;
 	      int pcrel = (i.flags[n] & Operand_PCrel) != 0;
 
+	      /* We can't have 8 bit displacement here.  */
+	      assert ((i.types[n] & Disp8) == 0);
+
 	      /* The PC relative address is computed relative
 		 to the instruction boundary, so in case immediate
 		 fields follows, we need to adjust the value.  */
 	      if (pcrel && i.imm_operands)
 		{
-		  int imm_size = 4;
 		  unsigned int n1;
+		  int sz = 0;
 
 		  for (n1 = 0; n1 < i.operands; n1++)
 		    if (i.types[n1] & Imm)
 		      {
-			if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
-			  {
-			    imm_size = 2;
-			    if (i.types[n1] & (Imm8 | Imm8S))
-			      imm_size = 1;
-			    if (i.types[n1] & Imm64)
-			      imm_size = 8;
-			  }
-			break;
+			/* Only one immediate is allowed for PC
+			   relative address.  */
+			assert (sz == 0);
+			sz = imm_size (n1);
+			i.op[n].disps->X_add_number -= sz;
 		      }
 		  /* We should find the immediate.  */
-		  if (n1 == i.operands)
-		    abort ();
-		  i.op[n].disps->X_add_number -= imm_size;
-		}
-
-	      if (i.types[n] & Disp32S)
-		sign = 1;
-
-	      if (i.types[n] & (Disp16 | Disp64))
-		{
-		  size = 2;
-		  if (i.types[n] & Disp64)
-		    size = 8;
+		  assert (sz != 0);
 		}
 
 	      p = frag_more (size);
@@ -3712,9 +4212,7 @@ output_disp (insn_start_frag, insn_start_off)
 }
 
 static void
-output_imm (insn_start_frag, insn_start_off)
-    fragS *insn_start_frag;
-    offsetT insn_start_off;
+output_imm (fragS *insn_start_frag, offsetT insn_start_off)
 {
   char *p;
   unsigned int n;
@@ -3725,18 +4223,9 @@ output_imm (insn_start_frag, insn_start_off)
 	{
 	  if (i.op[n].imms->X_op == O_constant)
 	    {
-	      int size;
+	      int size = imm_size (n);
 	      offsetT val;
 
-	      size = 4;
-	      if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
-		{
-		  size = 2;
-		  if (i.types[n] & (Imm8 | Imm8S))
-		    size = 1;
-		  else if (i.types[n] & Imm64)
-		    size = 8;
-		}
 	      val = offset_in_range (i.op[n].imms->X_add_number,
 				     size);
 	      p = frag_more (size);
@@ -3749,21 +4238,15 @@ output_imm (insn_start_frag, insn_start_off)
 		 non-absolute imms).  Try to support other
 		 sizes ...  */
 	      enum bfd_reloc_code_real reloc_type;
-	      int size = 4;
-	      int sign = 0;
+	      int size = imm_size (n);
+	      int sign;
 
 	      if ((i.types[n] & (Imm32S))
 		  && (i.suffix == QWORD_MNEM_SUFFIX
 		      || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
 		sign = 1;
-	      if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
-		{
-		  size = 2;
-		  if (i.types[n] & (Imm8 | Imm8S))
-		    size = 1;
-		  if (i.types[n] & Imm64)
-		    size = 8;
-		}
+	      else
+		sign = 0;
 
 	      p = frag_more (size);
 	      reloc_type = reloc (size, 0, sign, i.reloc[n]);
@@ -3857,10 +4340,8 @@ static enum bfd_reloc_code_real got_reloc = NO_RELOC;
 static int cons_sign = -1;
 
 void
-x86_cons_fix_new (fragS *frag,
-     unsigned int off,
-     unsigned int len,
-     expressionS *exp)
+x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
+		  expressionS *exp)
 {
   enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
 
@@ -3891,8 +4372,8 @@ x86_cons_fix_new (fragS *frag,
    input line.  Otherwise return NULL.  */
 static char *
 lex_got (enum bfd_reloc_code_real *reloc,
-     int *adjust,
-     unsigned int *types)
+	 int *adjust,
+	 unsigned int *types)
 {
   /* Some of the relocations depend on the size of what field is to
      be relocated.  But in our callers i386_immediate and i386_displacement
@@ -3904,23 +4385,57 @@ lex_got (enum bfd_reloc_code_real *reloc,
     const enum bfd_reloc_code_real rel[2];
     const unsigned int types64;
   } gotrel[] = {
-    { "PLTOFF",   { 0,                        BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
-    { "PLT",      { BFD_RELOC_386_PLT32,      BFD_RELOC_X86_64_PLT32    }, Imm32|Imm32S|Disp32 },
-    { "GOTPLT",   { 0,                        BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
-    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,     BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
-    { "GOTPCREL", { 0,                        BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
-    { "TLSGD",    { BFD_RELOC_386_TLS_GD,     BFD_RELOC_X86_64_TLSGD    }, Imm32|Imm32S|Disp32 },
-    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,    0                         }, 0 },
-    { "TLSLD",    { 0,                        BFD_RELOC_X86_64_TLSLD    }, Imm32|Imm32S|Disp32 },
-    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,  BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
-    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,  BFD_RELOC_X86_64_TPOFF32  }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
-    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,     0                         }, 0 },
-    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
-    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,  0                         }, 0 },
-    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,     0                         }, 0 },
-    { "GOT",      { BFD_RELOC_386_GOT32,      BFD_RELOC_X86_64_GOT32    }, Imm32|Imm32S|Disp32|Imm64 },
-    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
-    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
+    { "PLTOFF",   { 0,
+		    BFD_RELOC_X86_64_PLTOFF64 },
+      Imm64 },
+    { "PLT",      { BFD_RELOC_386_PLT32,
+		    BFD_RELOC_X86_64_PLT32    },
+      Imm32 | Imm32S | Disp32 },
+    { "GOTPLT",   { 0,
+		    BFD_RELOC_X86_64_GOTPLT64 },
+      Imm64 | Disp64 },
+    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,
+		    BFD_RELOC_X86_64_GOTOFF64 },
+      Imm64 | Disp64 },
+    { "GOTPCREL", { 0,
+		    BFD_RELOC_X86_64_GOTPCREL },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSGD",    { BFD_RELOC_386_TLS_GD,
+		    BFD_RELOC_X86_64_TLSGD    },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,
+		    0                         },
+      0 },
+    { "TLSLD",    { 0,
+		    BFD_RELOC_X86_64_TLSLD    },
+      Imm32 | Imm32S | Disp32 },
+    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
+		    BFD_RELOC_X86_64_GOTTPOFF },
+      Imm32 | Imm32S | Disp32 },
+    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,
+		    BFD_RELOC_X86_64_TPOFF32  },
+      Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
+    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,
+		    0                         },
+      0 },
+    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32,
+		    BFD_RELOC_X86_64_DTPOFF32 },
+      Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
+    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
+		    0                         },
+      0 },
+    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
+		    0                         },
+      0 },
+    { "GOT",      { BFD_RELOC_386_GOT32,
+		    BFD_RELOC_X86_64_GOT32    },
+      Imm32 | Imm32S | Disp32 | Imm64 },
+    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC,
+		    BFD_RELOC_X86_64_GOTPC32_TLSDESC },
+      Imm32 | Imm32S | Disp32 },
+    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL,
+		    BFD_RELOC_X86_64_TLSDESC_CALL },
+      Imm32 | Imm32S | Disp32 }
   };
   char *cp;
   unsigned int j;
@@ -3951,7 +4466,7 @@ lex_got (enum bfd_reloc_code_real *reloc,
 	      if (types)
 		{
 		  if (flag_code != CODE_64BIT)
-		    *types = Imm32|Disp32;
+		    *types = Imm32 | Disp32;
 		  else
 		    *types = gotrel[j].types64;
 		}
@@ -3959,9 +4474,6 @@ lex_got (enum bfd_reloc_code_real *reloc,
 	      if (GOT_symbol == NULL)
 		GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
 
-	      /* Replace the relocation token with ' ', so that
-		 errors like foo@GOTOFF1 will be detected.  */
-
 	      /* The length of the first part of our input line.  */
 	      first = cp - input_line_pointer;
 
@@ -3977,9 +4489,12 @@ lex_got (enum bfd_reloc_code_real *reloc,
 		 be necessary, but be safe.  */
 	      tmpbuf = xmalloc (first + second + 2);
 	      memcpy (tmpbuf, input_line_pointer, first);
-	      tmpbuf[first] = ' ';
-	      memcpy (tmpbuf + first + 1, past_reloc, second);
-	      tmpbuf[first + second + 1] = '\0';
+	      if (second != 0 && *past_reloc != ' ')
+		/* Replace the relocation token with ' ', so that
+		   errors like foo@GOTOFF1 will be detected.  */
+		tmpbuf[first++] = ' ';
+	      memcpy (tmpbuf + first, past_reloc, second);
+	      tmpbuf[first + second] = '\0';
 	      return tmpbuf;
 	    }
 
@@ -3994,9 +4509,7 @@ lex_got (enum bfd_reloc_code_real *reloc,
 }
 
 void
-x86_cons (exp, size)
-     expressionS *exp;
-     int size;
+x86_cons (expressionS *exp, int size)
 {
   if (size == 4 || (object_64bit && size == 8))
     {
@@ -4058,11 +4571,8 @@ pe_directive_secrel (dummy)
 }
 #endif
 
-static int i386_immediate PARAMS ((char *));
-
 static int
-i386_immediate (imm_start)
-     char *imm_start;
+i386_immediate (char *imm_start)
 {
   char *save_input_line_pointer;
   char *gotfree_input_line;
@@ -4072,7 +4582,8 @@ i386_immediate (imm_start)
 
   if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
     {
-      as_bad (_("only 1 or 2 immediate operands are allowed"));
+      as_bad (_("at most %d immediate operands are allowed"),
+	      MAX_IMMEDIATE_OPERANDS);
       return 0;
     }
 
@@ -4114,9 +4625,10 @@ i386_immediate (imm_start)
       /* Size it properly later.  */
       i.types[this_operand] |= Imm64;
       /* If BFD64, sign extend val.  */
-      if (!use_rela_relocations)
-	if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
-	  exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
+      if (!use_rela_relocations
+	  && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
+	exp->X_add_number
+	  = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
     }
 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
   else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
@@ -4131,6 +4643,11 @@ i386_immediate (imm_start)
       return 0;
     }
 #endif
+  else if (!intel_syntax && exp->X_op == O_register)
+    {
+      as_bad (_("illegal immediate register operand %s"), imm_start);
+      return 0;
+    }
   else
     {
       /* This is an address.  The size of the address will be
@@ -4143,11 +4660,8 @@ i386_immediate (imm_start)
   return 1;
 }
 
-static char *i386_scale PARAMS ((char *));
-
 static char *
-i386_scale (scale)
-     char *scale;
+i386_scale (char *scale)
 {
   offsetT val;
   char *save = input_line_pointer;
@@ -4194,12 +4708,8 @@ i386_scale (scale)
   return scale;
 }
 
-static int i386_displacement PARAMS ((char *, char *));
-
 static int
-i386_displacement (disp_start, disp_end)
-     char *disp_start;
-     char *disp_end;
+i386_displacement (char *disp_start, char *disp_end)
 {
   expressionS *exp;
   segT exp_seg = 0;
@@ -4208,6 +4718,13 @@ i386_displacement (disp_start, disp_end)
   int bigdisp, override;
   unsigned int types = Disp;
 
+  if (i.disp_operands == MAX_MEMORY_OPERANDS)
+    {
+      as_bad (_("at most %d displacement operands are allowed"),
+	      MAX_MEMORY_OPERANDS);
+      return 0;
+    }
+
   if ((i.types[this_operand] & JumpAbsolute)
       || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
     {
@@ -4224,9 +4741,9 @@ i386_displacement (disp_start, disp_end)
   if (flag_code == CODE_64BIT)
     {
       if (!bigdisp)
-	bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
-		  ? Disp16
-		  : Disp32S | Disp32;
+	bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
+		   ? Disp16
+		   : Disp32S | Disp32);
       else if (!override)
 	bigdisp = Disp64 | Disp32S | Disp32;
     }
@@ -4374,14 +4891,11 @@ i386_displacement (disp_start, disp_end)
   return 1;
 }
 
-static int i386_index_check PARAMS ((const char *));
-
 /* Make sure the memory operand we've been dealt is valid.
    Return 1 on success, 0 on a failure.  */
 
 static int
-i386_index_check (operand_string)
-     const char *operand_string;
+i386_index_check (const char *operand_string)
 {
   int ok;
 #if INFER_ADDR_PREFIX
@@ -4403,9 +4917,9 @@ i386_index_check (operand_string)
       else if (flag_code == CODE_64BIT)
 	RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
       else
-	RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
-		? Reg16
-		: Reg32;
+	RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
+		 ? Reg16
+		 : Reg32);
       if (!i.base_reg
 	  || !(i.base_reg->reg_type & Acc)
 	  || !(i.base_reg->reg_type & RegXX)
@@ -4414,17 +4928,17 @@ i386_index_check (operand_string)
 	ok = 0;
     }
   else if (flag_code == CODE_64BIT)
-     {
-       unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
-
-       if ((i.base_reg
-	    && ((i.base_reg->reg_type & RegXX) == 0)
-	    && (i.base_reg->reg_type != BaseIndex
-		|| i.index_reg))
-	   || (i.index_reg
-	       && ((i.index_reg->reg_type & (RegXX | BaseIndex))
-		   != (RegXX | BaseIndex))))
-	 ok = 0;
+    {
+      unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
+
+      if ((i.base_reg
+	   && ((i.base_reg->reg_type & RegXX) == 0)
+	   && (i.base_reg->reg_type != BaseIndex
+	       || i.index_reg))
+	  || (i.index_reg
+	      && ((i.index_reg->reg_type & (RegXX | BaseIndex))
+		  != (RegXX | BaseIndex))))
+	ok = 0;
     }
   else
     {
@@ -4466,8 +4980,9 @@ i386_index_check (operand_string)
 	     FIXME.  There doesn't seem to be any real need for separate
 	     Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
 	     Removing them would probably clean up the code quite a lot.  */
-	  if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
-	     i.types[this_operand] ^= (Disp16 | Disp32);
+	  if (flag_code != CODE_64BIT
+	      && (i.types[this_operand] & (Disp16 | Disp32)))
+	    i.types[this_operand] ^= (Disp16 | Disp32);
 	  fudged = 1;
 	  goto tryprefix;
 	}
@@ -4487,8 +5002,7 @@ i386_index_check (operand_string)
    on error.  */
 
 static int
-i386_operand (operand_string)
-     char *operand_string;
+i386_operand (char *operand_string)
 {
   const reg_entry *r;
   char *end_op;
@@ -4646,7 +5160,8 @@ i386_operand (operand_string)
 	    ++base_string;
 
 	  if (*base_string == ','
-	      || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
+	      || ((i.base_reg = parse_register (base_string, &end_op))
+		  != NULL))
 	    {
 	      displacement_string_end = temp_string;
 
@@ -4666,7 +5181,8 @@ i386_operand (operand_string)
 		  if (is_space_char (*base_string))
 		    ++base_string;
 
-		  if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
+		  if ((i.index_reg = parse_register (base_string, &end_op))
+		      != NULL)
 		    {
 		      base_string = end_op;
 		      if (is_space_char (*base_string))
@@ -4679,7 +5195,8 @@ i386_operand (operand_string)
 			}
 		      else if (*base_string != ')')
 			{
-			  as_bad (_("expecting `,' or `)' after index register in `%s'"),
+			  as_bad (_("expecting `,' or `)' "
+				    "after index register in `%s'"),
 				  operand_string);
 			  return 0;
 			}
@@ -4703,21 +5220,24 @@ i386_operand (operand_string)
 			++base_string;
 		      if (*base_string != ')')
 			{
-			  as_bad (_("expecting `)' after scale factor in `%s'"),
+			  as_bad (_("expecting `)' "
+				    "after scale factor in `%s'"),
 				  operand_string);
 			  return 0;
 			}
 		    }
 		  else if (!i.index_reg)
 		    {
-		      as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
+		      as_bad (_("expecting index register or scale factor "
+				"after `,'; got '%c'"),
 			      *base_string);
 		      return 0;
 		    }
 		}
 	      else if (*base_string != ')')
 		{
-		  as_bad (_("expecting `,' or `)' after base register in `%s'"),
+		  as_bad (_("expecting `,' or `)' "
+			    "after base register in `%s'"),
 			  operand_string);
 		  return 0;
 		}
@@ -4933,7 +5453,8 @@ md_convert_frag (abfd, sec, fragP)
     {
       if (no_cond_jump_promotion
 	  && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
-	as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
+	as_warn_where (fragP->fr_file, fragP->fr_line,
+		       _("long jump required"));
 
       switch (fragP->fr_subtype)
 	{
@@ -4984,8 +5505,8 @@ md_convert_frag (abfd, sec, fragP)
   if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
       && object_64bit
       && ((addressT) (displacement_from_opcode_start - extension
-                      + ((addressT) 1 << 31))
-          > (((addressT) 2 << 31) - 1)))
+		      + ((addressT) 1 << 31))
+	  > (((addressT) 2 << 31) - 1)))
     {
       as_bad_where (fragP->fr_file, fragP->fr_line,
 		    _("jump target out of range"));
@@ -5250,16 +5771,17 @@ md_atof (type, litP, sizeP)
   return 0;
 }
 
-static char output_invalid_buf[8];
+static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
 
 static char *
-output_invalid (c)
-     int c;
+output_invalid (int c)
 {
   if (ISPRINT (c))
-    sprintf (output_invalid_buf, "'%c'", c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+	      "'%c'", c);
   else
-    sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+	      "(0x%x)", (unsigned char) c);
   return output_invalid_buf;
 }
 
@@ -5310,14 +5832,16 @@ parse_real_register (char *reg_string, char **end_op)
 	    ++s;
 	  if (*s >= '0' && *s <= '7')
 	    {
-	      r = &i386_float_regtab[*s - '0'];
+	      int fpr = *s - '0';
 	      ++s;
 	      if (is_space_char (*s))
 		++s;
 	      if (*s == ')')
 		{
 		  *end_op = s + 1;
-		  return r;
+		  r = hash_find (reg_hash, "st(0)");
+		  know (r);
+		  return r + fpr;
 		}
 	    }
 	  /* We have "%st(" then garbage.  */
@@ -5359,7 +5883,8 @@ parse_register (char *reg_string, char **end_op)
 	  const expressionS *e = symbol_get_value_expression (symbolP);
 
 	  know (e->X_op == O_register);
-	  know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
+	  know (e->X_add_number >= 0
+		&& (valueT) e->X_add_number < i386_regtab_size);
 	  r = i386_regtab + e->X_add_number;
 	  *end_op = input_line_pointer;
 	}
@@ -5417,22 +5942,27 @@ const char *md_shortopts = "qn";
 #define OPTION_32 (OPTION_MD_BASE + 0)
 #define OPTION_64 (OPTION_MD_BASE + 1)
 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
+#define OPTION_MARCH (OPTION_MD_BASE + 3)
+#define OPTION_MTUNE (OPTION_MD_BASE + 4)
 
-struct option md_longopts[] = {
+struct option md_longopts[] =
+{
   {"32", no_argument, NULL, OPTION_32},
-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
   {"64", no_argument, NULL, OPTION_64},
 #endif
   {"divide", no_argument, NULL, OPTION_DIVIDE},
+  {"march", required_argument, NULL, OPTION_MARCH},
+  {"mtune", required_argument, NULL, OPTION_MTUNE},
   {NULL, no_argument, NULL, 0}
 };
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg)
 {
+  unsigned int i;
+
   switch (c)
     {
     case 'n':
@@ -5462,14 +5992,18 @@ md_parse_option (c, arg)
       /* -s: On i386 Solaris, this tells the native assembler to use
 	 .stab instead of .stab.excl.  We always use .stab anyhow.  */
       break;
-
+#endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
     case OPTION_64:
       {
 	const char **list, **l;
 
 	list = bfd_target_list ();
 	for (l = list; *l != NULL; l++)
-	  if (strcmp (*l, "elf64-x86-64") == 0)
+	  if (CONST_STRNEQ (*l, "elf64-x86-64")
+	      || strcmp (*l, "coff-x86-64") == 0
+	      || strcmp (*l, "pe-x86-64") == 0
+	      || strcmp (*l, "pei-x86-64") == 0)
 	    {
 	      default_arch = "x86_64";
 	      break;
@@ -5502,6 +6036,44 @@ md_parse_option (c, arg)
 #endif
       break;
 
+    case OPTION_MARCH:
+      if (*arg == '.')
+	as_fatal (_("Invalid -march= option: `%s'"), arg);
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
+	{
+	  if (strcmp (arg, cpu_arch [i].name) == 0)
+	    {
+	      cpu_arch_isa = cpu_arch[i].type;
+	      cpu_arch_isa_flags = cpu_arch[i].flags;
+	      if (!cpu_arch_tune_set)
+		{
+		  cpu_arch_tune = cpu_arch_isa;
+		  cpu_arch_tune_flags = cpu_arch_isa_flags;
+		}
+	      break;
+	    }
+	}
+      if (i >= ARRAY_SIZE (cpu_arch))
+	as_fatal (_("Invalid -march= option: `%s'"), arg);
+      break;
+
+    case OPTION_MTUNE:
+      if (*arg == '.')
+	as_fatal (_("Invalid -mtune= option: `%s'"), arg);
+      for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
+	{
+	  if (strcmp (arg, cpu_arch [i].name) == 0)
+	    {
+	      cpu_arch_tune_set = 1;
+	      cpu_arch_tune = cpu_arch [i].type;
+	      cpu_arch_tune_flags = cpu_arch[i].flags;
+	      break;
+	    }
+	}
+      if (i >= ARRAY_SIZE (cpu_arch))
+	as_fatal (_("Invalid -mtune= option: `%s'"), arg);
+      break;
+
     default:
       return 0;
     }
@@ -5525,6 +6097,10 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -s                      ignored\n"));
 #endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
+  fprintf (stream, _("\
+  --32/--64               generate 32bit/64bit code\n"));
+#endif
 #ifdef SVR4_COMMENT_CHARS
   fprintf (stream, _("\
   --divide                do not treat `/' as a comment character\n"));
@@ -5532,7 +6108,32 @@ md_show_usage (stream)
   fprintf (stream, _("\
   --divide                ignored\n"));
 #endif
+  fprintf (stream, _("\
+  -march=CPU/-mtune=CPU   generate code/optimize for CPU, where CPU is one of:\n\
+                           i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
+                           core, core2, k6, athlon, k8, generic32, generic64\n"));
+
+}
+
+#if defined(TE_PEP)
+const char *
+x86_64_target_format (void)
+{
+  if (strcmp (default_arch, "x86_64") == 0)
+    {
+      set_code_flag (CODE_64BIT);
+      return COFF_TARGET_FORMAT;
+    }
+  else if (strcmp (default_arch, "i386") == 0)
+    {
+      set_code_flag (CODE_32BIT);
+      return "coff-i386";
+    }
+
+  as_fatal (_("Unknown architecture"));
+  return NULL;
 }
+#endif
 
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
@@ -5540,12 +6141,28 @@ md_show_usage (stream)
 /* Pick the target format to use.  */
 
 const char *
-i386_target_format ()
+i386_target_format (void)
 {
   if (!strcmp (default_arch, "x86_64"))
-    set_code_flag (CODE_64BIT);
+    {
+      set_code_flag (CODE_64BIT);
+      if (cpu_arch_isa_flags == 0)
+	cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
+			     |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
+			     |CpuSSE|CpuSSE2;
+      if (cpu_arch_tune_flags == 0)
+	cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
+			      |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
+			      |CpuSSE|CpuSSE2;
+    }
   else if (!strcmp (default_arch, "i386"))
-    set_code_flag (CODE_32BIT);
+    {
+      set_code_flag (CODE_32BIT);
+      if (cpu_arch_isa_flags == 0)
+	cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
+      if (cpu_arch_tune_flags == 0)
+	cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
+    }
   else
     as_fatal (_("Unknown architecture"));
   switch (OUTPUT_FLAVOR)
@@ -5566,7 +6183,7 @@ i386_target_format ()
 	    object_64bit = 1;
 	    use_rela_relocations = 1;
 	  }
-	return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
+	return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
       }
 #endif
     default:
@@ -5578,7 +6195,8 @@ i386_target_format ()
 #endif /* OBJ_MAYBE_ more than one  */
 
 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-void i386_elf_emit_arch_note ()
+void
+i386_elf_emit_arch_note (void)
 {
   if (IS_ELF && cpu_arch_name != NULL)
     {
@@ -5669,8 +6287,7 @@ md_section_align (segment, size)
    size, since the offset is always the last part of the insn.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
 }
@@ -5678,8 +6295,7 @@ md_pcrel_from (fixP)
 #ifndef I386COFF
 
 static void
-s_bss (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_bss (int ignore ATTRIBUTE_UNUSED)
 {
   int temp;
 
@@ -5695,8 +6311,7 @@ s_bss (ignore)
 #endif
 
 void
-i386_validate_fix (fixp)
-     fixS *fixp;
+i386_validate_fix (fixS *fixp)
 {
   if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
     {
@@ -6045,8 +6660,8 @@ struct intel_parser_s
     int got_a_float;		/* Whether the operand is a float.  */
     int op_modifier;		/* Operand modifier.  */
     int is_mem;			/* 1 if operand is memory reference.  */
-    int in_offset;			/* >=1 if parsing operand of offset.  */
-    int in_bracket;			/* >=1 if parsing operand in brackets.  */
+    int in_offset;		/* >=1 if parsing operand of offset.  */
+    int in_bracket;		/* >=1 if parsing operand in brackets.  */
     const reg_entry *reg;	/* Last register reference found.  */
     char *disp;			/* Displacement string being built.  */
     char *next_operand;		/* Resume point when splitting operands.  */
@@ -6085,22 +6700,19 @@ static struct intel_token cur_token, prev_token;
 #define T_SHR		15
 
 /* Prototypes for intel parser functions.  */
-static int intel_match_token	PARAMS ((int code));
-static void intel_get_token	PARAMS ((void));
-static void intel_putback_token	PARAMS ((void));
-static int intel_expr		PARAMS ((void));
-static int intel_e04		PARAMS ((void));
-static int intel_e05		PARAMS ((void));
-static int intel_e06		PARAMS ((void));
-static int intel_e09		PARAMS ((void));
-static int intel_bracket_expr	PARAMS ((void));
-static int intel_e10		PARAMS ((void));
-static int intel_e11		PARAMS ((void));
+static int intel_match_token (int);
+static void intel_putback_token	(void);
+static void intel_get_token (void);
+static int intel_expr (void);
+static int intel_e04 (void);
+static int intel_e05 (void);
+static int intel_e06 (void);
+static int intel_e09 (void);
+static int intel_e10 (void);
+static int intel_e11 (void);
 
 static int
-i386_intel_operand (operand_string, got_a_float)
-     char *operand_string;
-     int got_a_float;
+i386_intel_operand (char *operand_string, int got_a_float)
 {
   int ret;
   char *p;
@@ -6190,7 +6802,7 @@ i386_intel_operand (operand_string, got_a_float)
 	ret = i386_immediate (intel_parser.disp);
 
       if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
-        ret = 0;
+	ret = 0;
       if (!ret || !intel_parser.next_operand)
 	break;
       intel_parser.op_string = intel_parser.next_operand;
@@ -6210,7 +6822,7 @@ i386_intel_operand (operand_string, got_a_float)
    expr'  cmpOp e04 expr'
 	| Empty  */
 static int
-intel_expr ()
+intel_expr (void)
 {
   /* XXX Implement the comparison operators.  */
   return intel_e04 ();
@@ -6221,7 +6833,7 @@ intel_expr ()
    e04'	addOp e05 e04'
 	| Empty  */
 static int
-intel_e04 ()
+intel_e04 (void)
 {
   int nregs = -1;
 
@@ -6250,7 +6862,7 @@ intel_e04 ()
    e05'	binOp e06 e05'
 	| Empty  */
 static int
-intel_e05 ()
+intel_e05 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
 
@@ -6259,7 +6871,9 @@ intel_e05 ()
       if (!intel_e06())
 	return 0;
 
-      if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
+      if (cur_token.code == '&'
+	  || cur_token.code == '|'
+	  || cur_token.code == '^')
 	{
 	  char str[2];
 
@@ -6285,7 +6899,7 @@ intel_e05 ()
    e06'	mulOp e09 e06'
 	| Empty  */
 static int
-intel_e06 ()
+intel_e06 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
 
@@ -6294,7 +6908,9 @@ intel_e06 ()
       if (!intel_e09())
 	return 0;
 
-      if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
+      if (cur_token.code == '*'
+	  || cur_token.code == '/'
+	  || cur_token.code == '%')
 	{
 	  char str[2];
 
@@ -6309,7 +6925,7 @@ intel_e06 ()
       else
 	break;
 
-     intel_match_token (cur_token.code);
+      intel_match_token (cur_token.code);
 
       if (nregs < 0)
 	nregs = ~nregs;
@@ -6331,7 +6947,7 @@ intel_e06 ()
 	| : e10 e09'
 	| Empty */
 static int
-intel_e09 ()
+intel_e09 (void)
 {
   int nregs = ~NUM_ADDRESS_REGS;
   int in_offset = 0;
@@ -6545,7 +7161,7 @@ intel_e09 ()
 }
 
 static int
-intel_bracket_expr ()
+intel_bracket_expr (void)
 {
   int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
   const char *start = intel_parser.op_string;
@@ -6581,7 +7197,7 @@ intel_bracket_expr ()
       intel_parser.op_modifier &= ~was_offset;
     }
   else
-      strcat (intel_parser.disp, "[");
+    strcat (intel_parser.disp, "[");
 
   /* Add a '+' to the displacement string if necessary.  */
   if (*intel_parser.disp != '\0'
@@ -6606,7 +7222,8 @@ intel_bracket_expr ()
 		/* Defer the warning until all of the operand was parsed.  */
 		intel_parser.is_mem = -1;
 	      else if (!quiet_warnings)
-		as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
+		as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
+			 len, start, len, start);
 	    }
 	}
       intel_parser.op_modifier |= was_offset;
@@ -6621,7 +7238,7 @@ intel_bracket_expr ()
    e10'	[ expr ] e10'
 	| Empty  */
 static int
-intel_e10 ()
+intel_e10 (void)
 {
   if (!intel_e11 ())
     return 0;
@@ -6651,7 +7268,7 @@ intel_e10 ()
 	| id
 	| constant  */
 static int
-intel_e11 ()
+intel_e11 (void)
 {
   switch (cur_token.code)
     {
@@ -6696,7 +7313,8 @@ intel_e11 ()
 	  {
 	    if (!(reg->reg_type & (SReg2 | SReg3)))
 	      {
-		as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
+		as_bad (_("`%s' is not a valid segment register"),
+			reg->reg_name);
 		return 0;
 	      }
 	    else if (i.seg[i.mem_operands])
@@ -6886,7 +7504,8 @@ intel_e11 ()
 	/* Get the next token to check for register scaling.  */
 	intel_match_token (cur_token.code);
 
-	/* Check if this constant is a scaling factor for an index register.  */
+	/* Check if this constant is a scaling factor for an
+	   index register.  */
 	if (cur_token.code == '*')
 	  {
 	    if (intel_match_token ('*') && cur_token.code == T_REG)
@@ -6895,14 +7514,17 @@ intel_e11 ()
 
 		if (!intel_parser.in_bracket)
 		  {
-		    as_bad (_("Register scaling only allowed in memory operands"));
+		    as_bad (_("Register scaling only allowed "
+			      "in memory operands"));
 		    return 0;
 		  }
 
-		if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
-		  reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+		 /* Disallow things like [1*si].
+		    sp and esp are invalid as index.  */
+		if (reg->reg_type & Reg16)
+		  reg = i386_regtab + REGNAM_AX + 4;
 		else if (i.index_reg)
-		  reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
+		  reg = i386_regtab + REGNAM_EAX + 4;
 
 		/* The constant is followed by `* reg', so it must be
 		   a valid scale.  */
@@ -6952,8 +7574,7 @@ intel_e11 ()
 /* Match the given token against cur_token. If they match, read the next
    token from the operand string.  */
 static int
-intel_match_token (code)
-     int code;
+intel_match_token (int code)
 {
   if (cur_token.code == code)
     {
@@ -6969,7 +7590,7 @@ intel_match_token (code)
 
 /* Read a new token from intel_parser.op_string and store it in cur_token.  */
 static void
-intel_get_token ()
+intel_get_token (void)
 {
   char *end_op;
   const reg_entry *reg;
@@ -7154,7 +7775,7 @@ intel_get_token ()
 /* Put cur_token back into the token stream and make cur_token point to
    prev_token.  */
 static void
-intel_putback_token ()
+intel_putback_token (void)
 {
   if (cur_token.code != T_NIL)
     {
@@ -7170,7 +7791,7 @@ intel_putback_token ()
 }
 
 int
-tc_x86_regname_to_dw2regnum (const char *regname)
+tc_x86_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum;
   unsigned int regnames_count;
@@ -7281,16 +7902,16 @@ x86_64_section_letter (int letter, char **ptr_msg)
 	return SHF_X86_64_LARGE;
 
       *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
-     }
+    }
   else
-   *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
+    *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
   return -1;
 }
 
 int
 x86_64_section_word (char *str, size_t len)
 {
-  if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
+  if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
     return SHF_X86_64_LARGE;
 
   return -1;
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 98517041dadd..51638b080337 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -1,6 +1,6 @@
 /* tc-i386.h -- Header file for tc-i386.c
    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004, 2005
+   2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -23,6 +23,8 @@
 #ifndef TC_I386
 #define TC_I386 1
 
+#include "opcodes/i386-opc.h"
+
 struct fix;
 
 #define TARGET_BYTES_BIG_ENDIAN	0
@@ -55,6 +57,7 @@ extern unsigned long i386_mach (void);
 
 #ifdef TE_FreeBSD
 #define ELF_TARGET_FORMAT	"elf32-i386-freebsd"
+#define ELF_TARGET_FORMAT64	"elf64-x86-64-freebsd"
 #elif defined (TE_VXWORKS)
 #define ELF_TARGET_FORMAT	"elf32-i386-vxworks"
 #endif
@@ -63,9 +66,13 @@ extern unsigned long i386_mach (void);
 #define ELF_TARGET_FORMAT	"elf32-i386"
 #endif
 
+#ifndef ELF_TARGET_FORMAT64
+#define ELF_TARGET_FORMAT64	"elf64-x86-64"
+#endif
+
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-extern const char *i386_target_format PARAMS ((void));
+extern const char *i386_target_format (void);
 #define TARGET_FORMAT i386_target_format ()
 #else
 #ifdef OBJ_ELF
@@ -78,7 +85,7 @@ extern const char *i386_target_format PARAMS ((void));
 
 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
 #define md_end i386_elf_emit_arch_note
-extern void i386_elf_emit_arch_note PARAMS ((void));
+extern void i386_elf_emit_arch_note (void);
 #endif
 
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
@@ -91,18 +98,16 @@ extern const char extra_symbol_chars[];
 extern const char *i386_comment_chars;
 #define tc_comment_chars i386_comment_chars
 
-#define MAX_OPERANDS 3		/* max operands per insn */
-#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
-#define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */
-
 /* Prefixes will be emitted in the order defined below.
    WAIT_PREFIX must be the first prefix since FWAIT is really is an
-   instruction, and so must come before any prefixes.  */
+   instruction, and so must come before any prefixes.
+   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
+   LOCKREP_PREFIX.  */
 #define WAIT_PREFIX	0
-#define LOCKREP_PREFIX	1
+#define SEG_PREFIX	1
 #define ADDR_PREFIX	2
 #define DATA_PREFIX	3
-#define SEG_PREFIX	4
+#define LOCKREP_PREFIX	4
 #define REX_PREFIX	5       /* must come last.  */
 #define MAX_PREFIXES	6	/* max prefixes per opcode */
 
@@ -111,21 +116,6 @@ extern const char *i386_comment_chars;
 #define IMMEDIATE_PREFIX '$'
 #define ABSOLUTE_PREFIX '*'
 
-#define TWO_BYTE_OPCODE_ESCAPE 0x0f
-#define NOP_OPCODE (char) 0x90
-
-/* register numbers */
-#define EBP_REG_NUM 5
-#define ESP_REG_NUM 4
-
-/* modrm_byte.regmem for twobyte escape */
-#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
-/* index_base_byte.index for no index register addressing */
-#define NO_INDEX_REGISTER ESP_REG_NUM
-/* index_base_byte.base for no base register addressing */
-#define NO_BASE_REGISTER EBP_REG_NUM
-#define NO_BASE_REGISTER_16 6
-
 /* these are the instruction mnemonic suffixes.  */
 #define WORD_MNEM_SUFFIX  'w'
 #define BYTE_MNEM_SUFFIX  'b'
@@ -135,184 +125,8 @@ extern const char *i386_comment_chars;
 /* Intel Syntax */
 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 
-/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
-#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
-#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
-
 #define END_OF_INSN '\0'
 
-typedef struct
-{
-  /* instruction name sans width suffix ("mov" for movl insns) */
-  char *name;
-
-  /* how many operands */
-  unsigned int operands;
-
-  /* base_opcode is the fundamental opcode byte without optional
-     prefix(es).  */
-  unsigned int base_opcode;
-
-  /* extension_opcode is the 3 bit extension for group <n> insns.
-     This field is also used to store the 8-bit opcode suffix for the
-     AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None */
-  unsigned int extension_opcode;
-#define None 0xffff		/* If no extension_opcode is possible.  */
-
-  /* cpu feature flags */
-  unsigned int cpu_flags;
-#define Cpu086		  0x1	/* Any old cpu will do, 0 does the same */
-#define Cpu186		  0x2	/* i186 or better required */
-#define Cpu286		  0x4	/* i286 or better required */
-#define Cpu386		  0x8	/* i386 or better required */
-#define Cpu486		 0x10	/* i486 or better required */
-#define Cpu586		 0x20	/* i585 or better required */
-#define Cpu686		 0x40	/* i686 or better required */
-#define CpuP4		 0x80	/* Pentium4 or better required */
-#define CpuK6		0x100	/* AMD K6 or better required*/
-#define CpuAthlon	0x200	/* AMD Athlon or better required*/
-#define CpuSledgehammer 0x400	/* Sledgehammer or better required */
-#define CpuMMX		0x800	/* MMX support required */
-#define CpuMMX2	       0x1000	/* extended MMX support (with SSE or 3DNow!Ext) required */
-#define CpuSSE	       0x2000	/* Streaming SIMD extensions required */
-#define CpuSSE2	       0x4000	/* Streaming SIMD extensions 2 required */
-#define Cpu3dnow       0x8000	/* 3dnow! support required */
-#define Cpu3dnowA     0x10000	/* 3dnow!Extensions support required */
-#define CpuSSE3	      0x20000	/* Streaming SIMD extensions 3 required */
-#define CpuPNI	      CpuSSE3	/* Prescott New Instructions required */
-#define CpuPadLock    0x40000	/* VIA PadLock required */
-#define CpuSVME	      0x80000	/* AMD Secure Virtual Machine Ext-s required */
-#define CpuVMX	     0x100000	/* VMX Instructions required */
-#define CpuMNI	     0x200000	/* Merom New Instructions required */
-
-  /* These flags are set by gas depending on the flag_code.  */
-#define Cpu64	     0x4000000   /* 64bit support required  */
-#define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
-
-  /* The default value for unknown CPUs - enable all features to avoid problems.  */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
-	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
-	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI)
-
-  /* the bits in opcode_modifier are used to generate the final opcode from
-     the base_opcode.  These bits also are used to detect alternate forms of
-     the same instruction */
-  unsigned int opcode_modifier;
-
-  /* opcode_modifier bits: */
-#define W		   0x1	/* set if operands can be words or dwords
-				   encoded the canonical way */
-#define D		   0x2	/* D = 0 if Reg --> Regmem;
-				   D = 1 if Regmem --> Reg:    MUST BE 0x2 */
-#define Modrm		   0x4
-#define FloatR		   0x8	/* src/dest swap for floats:   MUST BE 0x8 */
-#define ShortForm	  0x10	/* register is in low 3 bits of opcode */
-#define FloatMF		  0x20	/* FP insn memory format bit, sized by 0x4 */
-#define Jump		  0x40	/* special case for jump insns.  */
-#define JumpDword	  0x80  /* call and jump */
-#define JumpByte	 0x100  /* loop and jecxz */
-#define JumpInterSegment 0x200	/* special case for intersegment leaps/calls */
-#define FloatD		 0x400	/* direction for float insns:  MUST BE 0x400 */
-#define Seg2ShortForm	 0x800	/* encoding of load segment reg insns */
-#define Seg3ShortForm	0x1000	/* fs/gs segment register insns.  */
-#define Size16		0x2000	/* needs size prefix if in 32-bit mode */
-#define Size32		0x4000	/* needs size prefix if in 16-bit mode */
-#define Size64		0x8000	/* needs size prefix if in 16-bit mode */
-#define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
-#define DefaultSize    0x20000  /* default insn size depends on mode */
-#define No_bSuf	       0x40000	/* b suffix on instruction illegal */
-#define No_wSuf	       0x80000	/* w suffix on instruction illegal */
-#define No_lSuf	      0x100000 	/* l suffix on instruction illegal */
-#define No_sSuf	      0x200000	/* s suffix on instruction illegal */
-#define No_qSuf       0x400000  /* q suffix on instruction illegal */
-#define No_xSuf       0x800000  /* x suffix on instruction illegal */
-#define FWait	     0x1000000	/* instruction needs FWAIT */
-#define IsString     0x2000000	/* quick test for string instructions */
-#define regKludge    0x4000000	/* fake an extra reg operand for clr, imul */
-#define IsPrefix     0x8000000	/* opcode is a prefix */
-#define ImmExt	    0x10000000	/* instruction has extension in 8 bit imm */
-#define NoRex64	    0x20000000  /* instruction don't need Rex64 prefix.  */
-#define Rex64	    0x40000000  /* instruction require Rex64 prefix.  */
-#define Ugh	    0x80000000	/* deprecated fp insn, gets a warning */
-
-  /* operand_types[i] describes the type of operand i.  This is made
-     by OR'ing together all of the possible type masks.  (e.g.
-     'operand_types[i] = Reg|Imm' specifies that operand i can be
-     either a register or an immediate operand.  */
-  unsigned int operand_types[3];
-
-  /* operand_types[i] bits */
-  /* register */
-#define Reg8		   0x1	/* 8 bit reg */
-#define Reg16		   0x2	/* 16 bit reg */
-#define Reg32		   0x4	/* 32 bit reg */
-#define Reg64		   0x8	/* 64 bit reg */
-  /* immediate */
-#define Imm8		  0x10	/* 8 bit immediate */
-#define Imm8S		  0x20	/* 8 bit immediate sign extended */
-#define Imm16		  0x40	/* 16 bit immediate */
-#define Imm32		  0x80	/* 32 bit immediate */
-#define Imm32S		 0x100	/* 32 bit immediate sign extended */
-#define Imm64		 0x200	/* 64 bit immediate */
-#define Imm1		 0x400	/* 1 bit immediate */
-  /* memory */
-#define BaseIndex	 0x800
-  /* Disp8,16,32 are used in different ways, depending on the
-     instruction.  For jumps, they specify the size of the PC relative
-     displacement, for baseindex type instructions, they specify the
-     size of the offset relative to the base register, and for memory
-     offset instructions such as `mov 1234,%al' they specify the size of
-     the offset relative to the segment base.  */
-#define Disp8		0x1000	/* 8 bit displacement */
-#define Disp16		0x2000	/* 16 bit displacement */
-#define Disp32		0x4000	/* 32 bit displacement */
-#define Disp32S	        0x8000	/* 32 bit signed displacement */
-#define Disp64	       0x10000	/* 64 bit displacement */
-  /* specials */
-#define InOutPortReg   0x20000	/* register to hold in/out port addr = dx */
-#define ShiftCount     0x40000	/* register to hold shift cound = cl */
-#define Control	       0x80000	/* Control register */
-#define Debug	      0x100000	/* Debug register */
-#define Test	      0x200000	/* Test register */
-#define FloatReg      0x400000	/* Float register */
-#define FloatAcc      0x800000	/* Float stack top %st(0) */
-#define SReg2	     0x1000000	/* 2 bit segment register */
-#define SReg3	     0x2000000	/* 3 bit segment register */
-#define Acc	     0x4000000	/* Accumulator %al or %ax or %eax */
-#define JumpAbsolute 0x8000000
-#define RegMMX	    0x10000000	/* MMX register */
-#define RegXMM	    0x20000000	/* XMM registers in PIII */
-#define EsSeg	    0x40000000	/* String insn operand with fixed es segment */
-
-  /* InvMem is for instructions with a modrm byte that only allow a
-     general register encoding in the i.tm.mode and i.tm.regmem fields,
-     eg. control reg moves.  They really ought to support a memory form,
-     but don't, so we add an InvMem flag to the register operand to
-     indicate that it should be encoded in the i.tm.regmem field.  */
-#define InvMem	    0x80000000
-
-#define Reg	(Reg8|Reg16|Reg32|Reg64) /* gen'l register */
-#define WordReg (Reg16|Reg32|Reg64)
-#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
-#define Imm	(Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
-#define EncImm	(Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
-#define Disp	(Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
-#define AnyMem	(Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)	/* General memory */
-  /* The following aliases are defined because the opcode table
-     carefully specifies the allowed memory types for each instruction.
-     At the moment we can only tell a memory reference size by the
-     instruction suffix, so there's not much point in defining Mem8,
-     Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
-     the suffix directly to check memory operands.  */
-#define LLongMem AnyMem		/* 64 bits (or more) */
-#define LongMem AnyMem		/* 32 bit memory ref */
-#define ShortMem AnyMem		/* 16 bit memory ref */
-#define WordMem AnyMem		/* 16 or 32 bit memory ref */
-#define ByteMem AnyMem		/* 8 bit memory ref */
-}
-template;
-
 /*
   'templates' is for grouping together 'template' structures for opcodes
   of the same name.  This is only used for storing the insns in the grand
@@ -327,25 +141,6 @@ typedef struct
 }
 templates;
 
-/* these are for register name --> number & type hash lookup */
-typedef struct
-{
-  char *reg_name;
-  unsigned int reg_type;
-  unsigned int reg_flags;
-#define RegRex	    0x1  /* Extended register.  */
-#define RegRex64    0x2  /* Extended 8 bit register.  */
-  unsigned int reg_num;
-}
-reg_entry;
-
-typedef struct
-{
-  char *seg_name;
-  unsigned int seg_prefix;
-}
-seg_entry;
-
 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 typedef struct
 {
@@ -357,16 +152,6 @@ modrm_byte;
 
 /* x86-64 extension prefix.  */
 typedef int rex_byte;
-#define REX_OPCODE	0x40
-
-/* Indicates 64 bit operand size.  */
-#define REX_MODE64	8
-/* High extension to reg field of modrm byte.  */
-#define REX_EXTX	4
-/* High extension to SIB index field.  */
-#define REX_EXTY	2
-/* High extension to base field of modrm or SIB, or reg field of opcode.  */
-#define REX_EXTZ	1
 
 /* 386 opcode byte to code indirect addressing.  */
 typedef struct
@@ -377,11 +162,30 @@ typedef struct
 }
 sib_byte;
 
-/* x86 arch names and features */
+enum processor_type
+{
+  PROCESSOR_UNKNOWN,
+  PROCESSOR_I486,
+  PROCESSOR_PENTIUM,
+  PROCESSOR_PENTIUMPRO,
+  PROCESSOR_PENTIUM4,
+  PROCESSOR_NOCONA,
+  PROCESSOR_CORE,
+  PROCESSOR_CORE2,
+  PROCESSOR_K6,
+  PROCESSOR_ATHLON,
+  PROCESSOR_K8,
+  PROCESSOR_GENERIC32,
+  PROCESSOR_GENERIC64,
+  PROCESSOR_AMDFAM10
+};
+
+/* x86 arch names, types and features */
 typedef struct
 {
-  const char *name;	/* arch name */
-  unsigned int flags;	/* cpu feature flags */
+  const char *name;		/* arch name */
+  enum processor_type type;	/* arch type */
+  unsigned int flags;		/* cpu feature flags */
 }
 arch_entry;
 
@@ -393,22 +197,22 @@ arch_entry;
 
 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
-extern void x86_cons PARAMS ((expressionS *, int));
+extern void x86_cons (expressionS *, int);
 #endif
 
 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 extern void x86_cons_fix_new
-  PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
+  (fragS *, unsigned int, unsigned int, expressionS *);
 
 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 
 #define NO_RELOC BFD_RELOC_NONE
 
-void i386_validate_fix PARAMS ((struct fix *));
+void i386_validate_fix (struct fix *);
 #define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
 
 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
-extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
+extern int tc_i386_fix_adjustable (struct fix *);
 
 /* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
@@ -432,7 +236,6 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_386_PLT32		\
    || (FIX)->fx_r_type == BFD_RELOC_386_GOT32		\
    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC		\
@@ -460,7 +263,7 @@ if ((n)									\
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 
-extern void i386_align_code PARAMS ((fragS *, int));
+extern void i386_align_code (fragS *, int);
 
 #define HANDLE_ALIGN(fragP)						\
 if (fragP->fr_type == rs_align_code) 					\
@@ -468,16 +271,18 @@ if (fragP->fr_type == rs_align_code) 					\
 			   - fragP->fr_address				\
 			   - fragP->fr_fix));
 
-void i386_print_statistics PARAMS ((FILE *));
+void i386_print_statistics (FILE *);
 #define tc_print_statistics i386_print_statistics
 
 #define md_number_to_chars number_to_chars_littleendian
 
 #ifdef SCO_ELF
 #define tc_init_after_args() sco_id ()
-extern void sco_id PARAMS ((void));
+extern void sco_id (void);
 #endif
 
+#define WORKING_DOT_WORD 1
+
 /* We want .cfi_* pseudo-ops for generating unwind info.  */
 #define TARGET_USE_CFIPOP 1
 
@@ -488,17 +293,17 @@ extern int x86_cie_data_alignment;
 #define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
 
 #define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
-extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_x86_regname_to_dw2regnum (char *);
 
 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
-extern void tc_x86_frame_initial_instructions PARAMS ((void));
+extern void tc_x86_frame_initial_instructions (void);
 
 #define md_elf_section_type(str,len) i386_elf_section_type (str, len)
-extern int i386_elf_section_type PARAMS ((const char *, size_t len));
+extern int i386_elf_section_type (const char *, size_t);
 
 /* Support for SHF_X86_64_LARGE */
-extern int x86_64_section_word PARAMS ((char *, size_t));
-extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg));
+extern int x86_64_section_word (char *, size_t);
+extern int x86_64_section_letter (int, char **);
 #define md_elf_section_letter(LETTER, PTR_MSG)	x86_64_section_letter (LETTER, PTR_MSG)
 #define md_elf_section_word(STR, LEN)		x86_64_section_word (STR, LEN)
 
diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c
index 4a87c540576b..c5aca38e4502 100644
--- a/gas/config/tc-i860.c
+++ b/gas/config/tc-i860.c
@@ -1,6 +1,6 @@
 /* tc-i860.c -- Assembler for the Intel i860 architecture.
-   Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002,
+   2003, 2006 Free Software Foundation, Inc.
 
    Brought back from the dead and completely reworked
    by Jason Eckhardt <jle@cygnus.com>.
@@ -21,8 +21,6 @@
    with GAS; see the file COPYING.  If not, write to the Free Software
    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
-#include <string.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c
index a3206bbf2d0e..0af3a80c35e9 100644
--- a/gas/config/tc-i960.c
+++ b/gas/config/tc-i960.c
@@ -1,6 +1,6 @@
 /* tc-i960.c - All the i80960-specific stuff
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2005
+   1999, 2000, 2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -63,8 +63,6 @@
         less than 4096 is specified, in which case we need neither a fixup nor
         a relocation directive.  */
 
-#include <stdio.h>
-
 #include "as.h"
 
 #include "safe-ctype.h"
diff --git a/gas/config/tc-i960.h b/gas/config/tc-i960.h
index 05db36e40d5c..c5c33d37e07f 100644
--- a/gas/config/tc-i960.h
+++ b/gas/config/tc-i960.h
@@ -1,6 +1,6 @@
 /* tc-i960.h - Basic 80960 instruction formats.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003
+   2000, 2001, 2002, 2003, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -139,7 +139,6 @@ extern int reloc_callj PARAMS ((struct fix *));
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)		\
   (!(FIX)->fx_pcrel				\
-   || (FIX)->fx_plt				\
    || TC_FORCE_RELOCATION (FIX)		\
    || reloc_callj (FIX))
 
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index 426b60f589aa..5ed9ba82ad2e 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -1,5 +1,5 @@
 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
@@ -5634,7 +5634,7 @@ declare_register_set (prefix, num_regs, base_regnum)
 
   for (i = 0; i < num_regs; ++i)
     {
-      sprintf (name, "%s%u", prefix, i);
+      snprintf (name, sizeof (name), "%s%u", prefix, i);
       declare_register (name, base_regnum + i);
     }
 }
@@ -6691,7 +6691,7 @@ emit_one_bundle ()
   int addr_mod;
 
   first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
-  know (first >= 0 & first < NUM_SLOTS);
+  know (first >= 0 && first < NUM_SLOTS);
   n = MIN (3, md.num_slots_in_use);
 
   /* Determine template: user user_template if specified, best match
@@ -6971,7 +6971,8 @@ emit_one_bundle ()
 	  else
 	    as_fatal ("emit_one_bundle: unexpected dynamic op");
 
-	  sprintf (mnemonic, "%s.%c", idesc->name, "?imbfxx"[insn_unit]);
+	  snprintf (mnemonic, sizeof (mnemonic), "%s.%c",
+		    idesc->name, "?imbfxx"[insn_unit]);
 	  opnd1 = idesc->operands[0];
 	  opnd2 = idesc->operands[1];
 	  ia64_free_opcode (idesc);
@@ -7066,7 +7067,6 @@ emit_one_bundle ()
 	  fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
 			     &ifix->expr, ifix->is_pcrel, ifix->code);
 	  fix->tc_fix_data.opnd = ifix->opnd;
-	  fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
 	  fix->fx_file = md.slot[curr].src_file;
 	  fix->fx_line = md.slot[curr].src_line;
 	}
@@ -10544,12 +10544,15 @@ check_dependencies (idesc)
 	      int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
 
 	      if (path != 0)
-		sprintf (pathmsg, " when entry is at label '%s'",
+		snprintf (pathmsg, sizeof (pathmsg),
+			  " when entry is at label '%s'",
 			 md.entry_labels[path - 1]);
 	      if (matchtype == 1 && rs->index >= 0)
-		sprintf (indexmsg, ", specific resource number is %d",
+		snprintf (indexmsg, sizeof (indexmsg),
+			  ", specific resource number is %d",
 			 rs->index);
-	      sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
+	      snprintf (msg, sizeof (msg),
+			"Use of '%s' %s %s dependency '%s' (%s)%s%s",
 		       idesc->name,
 		       (certain ? "violates" : "may violate"),
 		       dv_mode[dep->mode], dep->name,
@@ -11862,7 +11865,7 @@ struct alias
 {
   char *file;		/* The file where the directive is seen.  */
   unsigned int line;	/* The line number the directive is at.  */
-  const char *name;	/* The orignale name of the symbol.  */
+  const char *name;	/* The original name of the symbol.  */
 };
 
 /* Called for .alias and .secalias directives. If SECTION is 1, it is
diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h
index c17494beb16b..b851b9f37eb4 100644
--- a/gas/config/tc-ia64.h
+++ b/gas/config/tc-ia64.h
@@ -1,5 +1,5 @@
 /* tc-ia64.h -- Header file for tc-ia64.c.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
@@ -315,5 +315,5 @@ typedef struct unwind_record
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   ((FIX)->fx_r_type != BFD_RELOC_UNUSED			\
    && (!(FIX)->fx_pcrel					\
-       || (FIX)->fx_plt					\
+       || (FIX)->fx_r_type == BFD_RELOC_IA64_PLTOFF22	\
        || TC_FORCE_RELOCATION (FIX)))
diff --git a/gas/config/tc-ip2k.c b/gas/config/tc-ip2k.c
index 10e9e2f3fa20..7c3f77513d81 100644
--- a/gas/config/tc-ip2k.c
+++ b/gas/config/tc-ip2k.c
@@ -1,5 +1,5 @@
 /* tc-ip2k.c -- Assembler for the Scenix IP2xxx.
-   Copyright (C) 2000, 2002, 2003, 2005 Free Software Foundation.
+   Copyright (C) 2000, 2002, 2003, 2005, 2006 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,7 +18,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"     
 #include "symcat.h"
diff --git a/gas/config/tc-iq2000.c b/gas/config/tc-iq2000.c
index 0d689c09a219..b7fddc5be3fd 100644
--- a/gas/config/tc-iq2000.c
+++ b/gas/config/tc-iq2000.c
@@ -1,5 +1,5 @@
 /* tc-iq2000.c -- Assembler for the Sitera IQ2000.
-   Copyright (C) 2003, 2004, 2005 Free Software Foundation.
+   Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,7 +18,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -29,7 +28,7 @@
 #include "elf/common.h"
 #include "elf/iq2000.h"
 #include "libbfd.h"
-#include "hash.h"
+#include "sb.h"
 #include "macro.h"
 
 /* Structure to hold all of the different components describing
diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
index 5f174d39c0d2..8194a673084a 100644
--- a/gas/config/tc-m32c.c
+++ b/gas/config/tc-m32c.c
@@ -1,5 +1,5 @@
 /* tc-m32c.c -- Assembler for the Renesas M32C.
-   Copyright (C) 2005 Free Software Foundation.
+   Copyright (C) 2005, 2006 Free Software Foundation.
    Contributed by RedHat.
 
    This file is part of GAS, the GNU Assembler.
@@ -19,7 +19,6 @@
    the Free Software Foundation, 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"     
 #include "symcat.h"
@@ -29,9 +28,7 @@
 #include "elf/common.h"
 #include "elf/m32c.h"
 #include "libbfd.h"
-#include "libiberty.h"
 #include "safe-ctype.h"
-#include "bfd.h"
 
 /* Structure to hold all of the different components
    describing an individual instruction.  */
@@ -55,8 +52,8 @@ typedef struct
 }
 m32c_insn;
 
-#define rl_for(insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&(insn.insn->base->attrs)))
-#define relaxable(insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&(insn.insn->base->attrs)))
+#define rl_for(_insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&((_insn).insn->base->attrs)))
+#define relaxable(_insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&((_insn).insn->base->attrs)))
 
 const char comment_chars[]        = ";";
 const char line_comment_chars[]   = "#";
@@ -154,6 +151,7 @@ s_bss (int ignore ATTRIBUTE_UNUSED)
 const pseudo_typeS md_pseudo_table[] =
 {
   { "bss",	s_bss, 		0},
+  { "3byte",	cons,		3 },
   { "word",	cons,		4 },
   { NULL, 	NULL, 		0 }
 };
@@ -450,7 +448,12 @@ const relax_typeS md_relax_table[] =
  /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
  /* 20 */ {     0,      0, 4,  0 }, /* jsr16.a */
  /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
- /* 22 */ {     0,      0, 4,  0 }  /* jsr32.a */
+ /* 22 */ {     0,      0, 4,  0 }, /* jsr32.a */
+
+ /* 23 */ {     0,      0, 3,  0 }, /* adjnz pc8 */
+ /* 24 */ {     0,      0, 4,  0 }, /* adjnz disp8 pc8 */
+ /* 25 */ {     0,      0, 5,  0 }, /* adjnz disp16 pc8 */
+ /* 26 */ {     0,      0, 6,  0 }  /* adjnz disp24 pc8 */
 };
 
 enum {
@@ -460,6 +463,11 @@ enum {
   M32C_MACRO_JCND16_A,
   M32C_MACRO_JCND32_W,
   M32C_MACRO_JCND32_A,
+  /* the digit is the array index of the pcrel byte */
+  M32C_MACRO_ADJNZ_2,
+  M32C_MACRO_ADJNZ_3,
+  M32C_MACRO_ADJNZ_4,
+  M32C_MACRO_ADJNZ_5,
 } M32C_Macros;
 
 static struct {
@@ -496,7 +504,12 @@ static struct {
  /* 19 */ {  M32C_INSN_JSR16_W,     3, M32C_INSN_JSR16_A,     2 },
  /* 20 */ {  M32C_INSN_JSR16_A,     4, M32C_INSN_JSR16_A,     0 },
  /* 21 */ {  M32C_INSN_JSR32_W,     3, M32C_INSN_JSR32_A,     2 },
- /* 22 */ {  M32C_INSN_JSR32_A,     4, M32C_INSN_JSR32_A,     0 }
+ /* 22 */ {  M32C_INSN_JSR32_A,     4, M32C_INSN_JSR32_A,     0 },
+
+ /* 23 */ { -M32C_MACRO_ADJNZ_2,    3, -M32C_MACRO_ADJNZ_2,    0 },
+ /* 24 */ { -M32C_MACRO_ADJNZ_3,    4, -M32C_MACRO_ADJNZ_3,    0 },
+ /* 25 */ { -M32C_MACRO_ADJNZ_4,    5, -M32C_MACRO_ADJNZ_4,    0 },
+ /* 26 */ { -M32C_MACRO_ADJNZ_5,    6, -M32C_MACRO_ADJNZ_5,    0 }
 };
 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
 
@@ -511,11 +524,21 @@ m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
 }
 
 static int
-insn_to_subtype (int insn)
+insn_to_subtype (int inum, const CGEN_INSN *insn)
 {
   unsigned int i;
+
+  if (insn
+      && (strncmp (insn->base->mnemonic, "adjnz", 5) == 0
+	  || strncmp (insn->base->mnemonic, "sbjnz", 5) == 0))
+    {
+      i = 23 + insn->base->bitsize/8 - 3;
+      /*printf("mapping %d used for %s\n", i, insn->base->mnemonic);*/
+      return i;
+    }
+
   for (i=0; i<NUM_MAPPINGS; i++)
-    if (insn == subtype_mappings[i].insn)
+    if (inum == subtype_mappings[i].insn)
       {
 	/*printf("mapping %d used\n", i);*/
 	return i;
@@ -540,14 +563,14 @@ md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
   int where = fragP->fr_opcode - fragP->fr_literal;
 
   if (fragP->fr_subtype == 1)
-    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
+    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num, fragP->fr_cgen.insn);
 
   if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
     {
       int new_insn;
 
       new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
-      fragP->fr_subtype = insn_to_subtype (new_insn);
+      fragP->fr_subtype = insn_to_subtype (new_insn, 0);
     }
 
   if (fragP->fr_cgen.insn->base
@@ -835,6 +858,26 @@ md_convert_frag (bfd *   abfd ATTRIBUTE_UNUSED,
       rl_addend = 0x41;
       break;
 
+    case -M32C_MACRO_ADJNZ_2:
+      rl_addend = 0x31;
+      op[2] = addend;
+      operand = M32C_OPERAND_LAB_16_8;
+      break;
+    case -M32C_MACRO_ADJNZ_3:
+      rl_addend = 0x41;
+      op[3] = addend;
+      operand = M32C_OPERAND_LAB_24_8;
+      break;
+    case -M32C_MACRO_ADJNZ_4:
+      rl_addend = 0x51;
+      op[4] = addend;
+      operand = M32C_OPERAND_LAB_32_8;
+      break;
+    case -M32C_MACRO_ADJNZ_5:
+      rl_addend = 0x61;
+      op[5] = addend;
+      operand = M32C_OPERAND_LAB_40_8;
+      break;
 
 
     default:
@@ -860,15 +903,16 @@ md_convert_frag (bfd *   abfd ATTRIBUTE_UNUSED,
       || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
 			 && operand != M32C_OPERAND_LAB32_JMP_S)))
     {
+      fixS *fixP;
       assert (fragP->fr_cgen.insn != 0);
-      gas_cgen_record_fixup (fragP,
-			     where,
-			     fragP->fr_cgen.insn,
-			     (fragP->fr_fix - where) * 8,
-			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
-							 operand),
-			     fragP->fr_cgen.opinfo,
-			     fragP->fr_symbol, fragP->fr_offset);
+      fixP = gas_cgen_record_fixup (fragP,
+				    where,
+				    fragP->fr_cgen.insn,
+				    (fragP->fr_fix - where) * 8,
+				    cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+								operand),
+				    fragP->fr_cgen.opinfo,
+				    fragP->fr_symbol, fragP->fr_offset);
     }
 }
 
@@ -1021,6 +1065,37 @@ md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
 }
 
 void
+m32c_cons_fix_new (fragS *	frag,
+		   int		where,
+		   int		size,
+		   expressionS *exp)
+{
+  bfd_reloc_code_real_type type;
+
+  switch (size)
+    {
+    case 1:
+      type = BFD_RELOC_8;
+      break;
+    case 2:
+      type = BFD_RELOC_16;
+      break;
+    case 3:
+      type = BFD_RELOC_24;
+      break;
+    case 4:
+    default:
+      type = BFD_RELOC_32;
+      break;
+    case 8:
+      type = BFD_RELOC_64;
+      break;
+    }
+
+  fix_new_exp (frag, where, (int) size, exp, 0, type);
+}
+
+void
 m32c_apply_fix (struct fix *f, valueT *t, segT s)
 {
   if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
diff --git a/gas/config/tc-m32c.h b/gas/config/tc-m32c.h
index 3cdd1a14e4f4..697e130e19d5 100644
--- a/gas/config/tc-m32c.h
+++ b/gas/config/tc-m32c.h
@@ -57,6 +57,10 @@ extern bfd_boolean m32c_fix_adjustable PARAMS ((struct fix *));
 #define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix)
 extern int m32c_force_relocation PARAMS ((struct fix *));
 
+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
+  m32c_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
+extern void m32c_cons_fix_new (fragS *, int, int, expressionS *);
+
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
 
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index 51b160a98f76..bec2a8ced1ac 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -1,6 +1,6 @@
 /* tc-m32r.c -- Assembler for the Renesas M32R.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h
index 69fe9453cc36..e5373cc160fa 100644
--- a/gas/config/tc-m32r.h
+++ b/gas/config/tc-m32r.h
@@ -1,6 +1,6 @@
 /* tc-m32r.h -- Header file for tc-m32r.c.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -88,13 +88,6 @@ extern bfd_boolean m32r_fix_adjustable (struct fix *);
    obj_fix_adjustable() says it is not adjustable.  */
 #define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
 
-#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
-   ((FIX)->fx_addsy == NULL                                     \
-    || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                       \
-        && ! S_IS_WEAK ((FIX)->fx_addsy)                        \
-        && S_IS_DEFINED ((FIX)->fx_addsy)                       \
-        && ! S_IS_COMMON ((FIX)->fx_addsy)))
-
 #define tc_frob_file_before_fix() m32r_frob_file ()
 extern void m32r_frob_file (void);
 
diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c
index e6d4235d7699..822174fa11ea 100644
--- a/gas/config/tc-m68hc11.c
+++ b/gas/config/tc-m68hc11.c
@@ -1,5 +1,5 @@
 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@nerim.fr)
 
@@ -210,7 +210,7 @@ static void s_m68hc11_mark_symbol (int);
             jmp L
 
   Setting the flag forbidds this.  */
-static short flag_fixed_branchs = 0;
+static short flag_fixed_branches = 0;
 
 /* Force to use long jumps (absolute) instead of relative branches.  */
 static short flag_force_long_jumps = 0;
@@ -290,10 +290,12 @@ const char *md_shortopts = "Sm:";
 
 struct option md_longopts[] = {
 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
-  {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
+  {"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
+  {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility.  */
 
-#define OPTION_SHORT_BRANCHS     (OPTION_MD_BASE + 1)
-  {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
+#define OPTION_SHORT_BRANCHES     (OPTION_MD_BASE + 1)
+  {"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES},
+  {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility.  */
 
 #define OPTION_STRICT_DIRECT_MODE  (OPTION_MD_BASE + 2)
   {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
@@ -374,8 +376,8 @@ Motorola 68HC11/68HC12/68HCS12 options:\n\
   -mlong                  use 32-bit int ABI\n\
   -mshort-double          use 32-bit double ABI\n\
   -mlong-double           use 64-bit double ABI (default)\n\
-  --force-long-branchs    always turn relative branchs into absolute ones\n\
-  -S,--short-branchs      do not turn relative branchs into absolute ones\n\
+  --force-long-branches   always turn relative branches into absolute ones\n\
+  -S,--short-branches     do not turn relative branches into absolute ones\n\
                           when the offset is out of range\n\
   --strict-direct-mode    do not turn the direct mode into extended mode\n\
                           when the instruction does not support direct mode\n\
@@ -447,9 +449,9 @@ md_parse_option (int c, char *arg)
   switch (c)
     {
       /* -S means keep external to 2 bit offset rather than 16 bit one.  */
-    case OPTION_SHORT_BRANCHS:
+    case OPTION_SHORT_BRANCHES:
     case 'S':
-      flag_fixed_branchs = 1;
+      flag_fixed_branches = 1;
       break;
 
     case OPTION_FORCE_LONG_BRANCH:
@@ -1516,7 +1518,7 @@ fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED)
       fixS *fixp;
 
       /* Now create a 24-bit fixup.  */
-      fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
+      fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 3,
 			  oper, FALSE, BFD_RELOC_M68HC11_24);
       number_to_chars_bigendian (f, 0, 3);
     }
@@ -1587,12 +1589,12 @@ build_jump_insn (struct m68hc11_opcode *opcode, operand operands[],
   if ((jmp_mode == 0 && flag_force_long_jumps)
       || (operands[0].exp.X_op == O_constant
 	  && (!check_range (n, opcode->format) &&
-	      (jmp_mode == 1 || flag_fixed_branchs == 0))))
+	      (jmp_mode == 1 || flag_fixed_branches == 0))))
     {
       frag = frag_now;
       where = frag_now_fix ();
 
-      fix_new (frag_now, frag_now_fix (), 1,
+      fix_new (frag_now, frag_now_fix (), 0,
                &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
 
       if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
@@ -1652,7 +1654,7 @@ build_jump_insn (struct m68hc11_opcode *opcode, operand operands[],
       frag = frag_now;
       where = frag_now_fix ();
 
-      fix_new (frag_now, frag_now_fix (), 1,
+      fix_new (frag_now, frag_now_fix (), 0,
                &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
 
       f = m68hc11_new_insn (2);
@@ -1667,11 +1669,11 @@ build_jump_insn (struct m68hc11_opcode *opcode, operand operands[],
       frag = frag_now;
       where = frag_now_fix ();
       
-      fix_new (frag_now, frag_now_fix (), 1,
+      fix_new (frag_now, frag_now_fix (), 0,
                &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
 
       /* Branch offset must fit in 8-bits, don't do some relax.  */
-      if (jmp_mode == 0 && flag_fixed_branchs)
+      if (jmp_mode == 0 && flag_fixed_branches)
 	{
 	  opcode = m68hc11_new_insn (1);
 	  number_to_chars_bigendian (opcode, code, 1);
@@ -1753,7 +1755,7 @@ build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[],
   if ((jmp_mode == 0 && flag_force_long_jumps)
       || (operands[1].exp.X_op == O_constant
 	  && (!check_range (n, M6812_OP_IBCC_MARKER) &&
-	      (jmp_mode == 1 || flag_fixed_branchs == 0))))
+	      (jmp_mode == 1 || flag_fixed_branches == 0))))
     {
       f = frag_more (2);
       code ^= 0x20;
@@ -1784,7 +1786,7 @@ build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[],
   else
     {
       /* Branch offset must fit in 8-bits, don't do some relax.  */
-      if (jmp_mode == 0 && flag_fixed_branchs)
+      if (jmp_mode == 0 && flag_fixed_branches)
 	{
 	  fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
 	}
@@ -2100,7 +2102,7 @@ build_insn (struct m68hc11_opcode *opcode, operand operands[],
   format = opcode->format;
 
   if (format & M6811_OP_BRANCH)
-    fix_new (frag_now, frag_now_fix (), 1,
+    fix_new (frag_now, frag_now_fix (), 0,
              &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
 
   if (format & OP_EXTENDED)
@@ -2455,7 +2457,7 @@ md_assemble (char *str)
   char name[20];
   int nlen = 0;
   operand operands[M6811_MAX_OPERANDS];
-  int nb_operands;
+  int nb_operands = 0;
   int branch_optimize = 0;
   int alias_id = -1;
 
@@ -2484,8 +2486,8 @@ md_assemble (char *str)
   opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
 
   /* If it's not recognized, look for 'jbsr' and 'jbxx'.  These are
-     pseudo insns for relative branch.  For these branchs, we always
-     optimize them (turned into absolute branchs) even if --short-branchs
+     pseudo insns for relative branch.  For these branches, we always
+     optimize them (turned into absolute branches) even if --short-branches
      is given.  */
   if (opc == NULL && name[0] == 'j' && name[1] == 'b')
     {
@@ -2702,7 +2704,7 @@ s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED)
       return;
     }
 
-  fix_new_exp (frag_now, frag_now_fix (), 2, &ex, 1,
+  fix_new_exp (frag_now, frag_now_fix (), 0, &ex, 1,
                BFD_RELOC_M68HC11_RL_GROUP);
 
   demand_empty_rest_of_line ();
@@ -3018,7 +3020,7 @@ md_estimate_size_before_relax (fragS *fragP, asection *segment)
 		      || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
 		      || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
 
-	      if (flag_fixed_branchs)
+	      if (flag_fixed_branches)
 		as_bad_where (fragP->fr_file, fragP->fr_line,
 			      _("bra or bsr with undefined symbol."));
 
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index 6cf85d7e603a..32c985324c26 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -1,6 +1,6 @@
 /* tc-m68k.c -- Assemble for the m68k family
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -173,62 +173,130 @@ static const enum m68k_register m68060_ctrl[] = {
 };
 static const enum m68k_register mcf_ctrl[] = {
   CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
-  RAMBAR0, RAMBAR1, MBAR,
+  RAMBAR0, RAMBAR1, RAMBAR, MBAR,
+  0
+};
+static const enum m68k_register mcf5206_ctrl[] = {
+  CACR, ACR0, ACR1,  VBR, RAMBAR0, RAMBAR_ALT, MBAR,
   0
 };
 static const enum m68k_register mcf5208_ctrl[] = {
-  CACR, ACR0, ACR1, VBR, RAMBAR1,
+  CACR, ACR0, ACR1, VBR,  RAMBAR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf5210a_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
   0
 };
 static const enum m68k_register mcf5213_ctrl[] = {
-  VBR, RAMBAR, FLASHBAR,
+  VBR, RAMBAR, RAMBAR1, FLASHBAR,
   0
 };
 static const enum m68k_register mcf5216_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf52223_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf52235_ctrl[] = {
+  VBR, FLASHBAR, RAMBAR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf5225_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcf5235_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR,
+  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcf5249_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
+  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
   0
 };
 static const enum m68k_register mcf5250_ctrl[] = {
   VBR,
   0
 };
+static const enum m68k_register mcf5253_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
+  0
+};
 static const enum m68k_register mcf5271_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR,
+  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcf5272_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
+  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
   0
 };
 static const enum m68k_register mcf5275_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR,
+  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcf5282_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf5307_ctrl[] = {
+  CACR, ACR0, ACR1,  VBR, RAMBAR0, RAMBAR_ALT, MBAR,
   0
 };
 static const enum m68k_register mcf5329_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR,
+  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcf5373_ctrl[] = {
-  VBR, CACR, ACR0, ACR1, RAMBAR,
+  VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
   0
 };
 static const enum m68k_register mcfv4e_ctrl[] = {
-  CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
-  ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
+  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
+  VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
+  MBAR, SECMBAR,
+  MPCR /* Multiprocessor Control register */,
+  EDRAMBAR /* Embedded DRAM Base Address Register */,
+  /* Permutation control registers.  */
   PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
   PCR3U0, PCR3L0, PCR3U1, PCR3L1,
+  /* Legacy names */
+  TC /* ASID */, BUSCR /* MMUBAR */,
+  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
+  MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
+  ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
+  0
+};
+static const enum m68k_register mcf54455_ctrl[] = {
+  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
+  VBR, PC, RAMBAR1, MBAR,
+  /* Legacy names */
+  TC /* ASID */, BUSCR /* MMUBAR */,
+  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
+  MBAR1 /* MBAR */,  RAMBAR /* RAMBAR1 */,
+  0
+};
+static const enum m68k_register mcf5475_ctrl[] = {
+  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
+  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
+  /* Legacy names */
+  TC /* ASID */, BUSCR /* MMUBAR */,
+  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
+  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
+  0
+};
+static const enum m68k_register mcf5485_ctrl[] = {
+  CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
+  VBR, PC, RAMBAR0, RAMBAR1, MBAR,
+  /* Legacy names */
+  TC /* ASID */, BUSCR /* MMUBAR */,
+  ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
+  MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
+  0
+};
+static const enum m68k_register fido_ctrl[] = {
+  SFC, DFC, USP, VBR, CAC, MBB,
   0
 };
 #define cpu32_ctrl m68010_ctrl
@@ -284,14 +352,21 @@ struct m68k_it
   reloc[5];			/* Five is enough???  */
 };
 
-#define cpu_of_arch(x)		((x) & (m68000up | mcfisa_a))
+#define cpu_of_arch(x)		((x) & (m68000up | mcfisa_a | fido_a))
 #define float_of_arch(x)	((x) & mfloat)
 #define mmu_of_arch(x)		((x) & mmmu)
 #define arch_coldfire_p(x)	((x) & mcfisa_a)
 #define arch_coldfire_fpu(x)	((x) & cfloat)
 
 /* Macros for determining if cpu supports a specific addressing mode.  */
-#define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
+#define HAVE_LONG_DISP(x)	\
+	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
+#define HAVE_LONG_CALL(x)	\
+	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
+#define HAVE_LONG_COND(x)	\
+	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
+#define HAVE_LONG_BRANCH(x)	\
+	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
 
 static struct m68k_it the_ins;	/* The instruction being assembled.  */
 
@@ -421,9 +496,11 @@ static const struct m68k_cpu m68k_archs[] =
   {m68040,					m68040_ctrl, "68040", 0},
   {m68060,					m68060_ctrl, "68060", 0},
   {cpu32|m68881,				cpu32_ctrl, "cpu32", 0},
+  {fido_a,					fido_ctrl, "fidoa", 0},
   {mcfisa_a|mcfhwdiv,				NULL, "isaa", 0},
   {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,		NULL, "isaaplus", 0},
   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,		NULL, "isab", 0},
+  {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp,		NULL, "isac", 0},
   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,	mcf_ctrl, "cfv4", 0},
   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
   {0,0,NULL, 0}
@@ -486,13 +563,16 @@ static const struct m68k_cpu m68k_cpus[] =
   {mcfisa_a,					mcf_ctrl, "5200", 0},
   {mcfisa_a,					mcf_ctrl, "5202", 1},
   {mcfisa_a,					mcf_ctrl, "5204", 1},
-  {mcfisa_a,					mcf_ctrl, "5206", 1},
+  {mcfisa_a,					mcf5206_ctrl, "5206", 1},
   
-  {mcfisa_a|mcfhwdiv|mcfmac,			mcf_ctrl, "5206e", 0},
+  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5206_ctrl, "5206e", 0},
   
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5207", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5208", 0},
   
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5210a", 0},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5211a", 1},
+  
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5211", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5212", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5213", 0},
@@ -501,6 +581,17 @@ static const struct m68k_cpu m68k_cpus[] =
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5216", 0},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "521x", 2},
 
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52221", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52223", 0},
+
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52230", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52233", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52234", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52235", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5224", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5225", 0},
+  
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5232", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5233", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5234", -1},
@@ -509,6 +600,7 @@ static const struct m68k_cpu m68k_cpus[] =
   
   {mcfisa_a|mcfhwdiv|mcfemac,			mcf5249_ctrl, "5249", 0},
   {mcfisa_a|mcfhwdiv|mcfemac,			mcf5250_ctrl, "5250", 0},
+  {mcfisa_a|mcfhwdiv|mcfemac, 			mcf5253_ctrl, "5253", 0},
   
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5270", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5271", 0},
@@ -523,7 +615,7 @@ static const struct m68k_cpu m68k_cpus[] =
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5282", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "528x", 0},
   
-  {mcfisa_a|mcfhwdiv|mcfmac,			mcf_ctrl, "5307", 0},
+  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5307_ctrl, "5307", 0},
   
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5327", -1},
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5328", -1},
@@ -535,23 +627,33 @@ static const struct m68k_cpu m68k_cpus[] =
   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "537x", 0},
   
   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,		mcf_ctrl, "5407",0},
+
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54450", -1},
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54451", -1},
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54452", -1},
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54453", -1},
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54454", -1},
+  {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54455", 0},
   
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
   
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
-  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
   
+  {fido_a,				fido_ctrl, "fidoa", 0},
+  {fido_a,				fido_ctrl, "fido", 1},
+
   {0,NULL,NULL, 0}
   };
 
@@ -957,7 +1059,9 @@ tc_m68k_fix_adjustable (fixS *fixP)
 
 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
 
-#define relaxable_symbol(symbol) 1
+/* PR gas/3041 Weak symbols are not relaxable
+   because they must be treated as extern.  */
+#define relaxable_symbol(symbol)   (!(S_IS_WEAK (symbol)))
 
 #endif /* OBJ_ELF */
 
@@ -1051,6 +1155,14 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 #ifndef OBJ_ELF
   if (fixp->fx_pcrel)
     reloc->addend = fixp->fx_addnumber;
+  else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
+	   && fixp->fx_addsy
+	   && S_IS_WEAK (fixp->fx_addsy)
+	   && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
+    /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
+       to put the symbol offset into frags referencing a weak symbol.  */
+    reloc->addend = fixp->fx_addnumber
+		    - (S_GET_VALUE (fixp->fx_addsy) * 2);
   else
     reloc->addend = 0;
 #else
@@ -1685,8 +1797,18 @@ m68k_ip (char *instring)
 		      const enum m68k_register *rp;
 		      
 		      for (rp = control_regs; *rp; rp++)
-			if (*rp == opP->reg)
-			  break;
+			{
+			  if (*rp == opP->reg)
+			    break;
+			  /* In most CPUs RAMBAR refers to control reg
+	     	 	     c05 (RAMBAR1), but a few CPUs have it
+	     	 	     refer to c04 (RAMBAR0).  */
+			  else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
+			    {
+			      opP->reg = RAMBAR_ALT;
+			      break;
+			    }
+			}
 		      if (*rp == 0)
 			losing++;
 		    }
@@ -1843,6 +1965,22 @@ m68k_ip (char *instring)
 		    losing++;
 		  break;
 
+		case 'j':
+		  if (opP->mode != IMMED)
+		    losing++;
+		  else if (opP->disp.exp.X_op != O_constant
+			   || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
+		    losing++;
+		  break;
+
+		case 'K':
+		  if (opP->mode != IMMED)
+		    losing++;
+		  else if (opP->disp.exp.X_op != O_constant
+			   || TRUNC (opP->disp.exp.X_add_number) > 511)
+		    losing++;
+		  break;
+
 		  /* JF these are out of order.  We could put them
 		     in order if we were willing to put up with
 		     bunches of #ifdef m68851s in the code.
@@ -2061,29 +2199,31 @@ m68k_ip (char *instring)
 		if (!cpu->alias && (cpu->arch & ok_arch))
 		  {
 		    const struct m68k_cpu *alias;
-
+		    int seen_master = 0;
+		    
 		    if (any)
 		      APPEND (", ");
 		    any = 0;
 		    APPEND (cpu->name);
-		    APPEND (" [");
-		    if (cpu != m68k_cpus)
-		      for (alias = cpu - 1; alias->alias; alias--)
+		    for (alias = cpu; alias != m68k_cpus; alias--)
+		      if (alias[-1].alias >= 0)
+			break;
+		    for (; !seen_master || alias->alias > 0; alias++)
 			{
-			  if (any)
-			    APPEND (", ");
-			  APPEND (alias->name);
-			  any = 1;
+			  if (!alias->alias)
+			    seen_master = 1;
+			  else
+			    {
+			      if (any)
+				APPEND (", ");
+			      else
+				APPEND (" [");
+			      APPEND (alias->name);
+			      any = 1;
+			    }
 			}
-		    for (alias = cpu + 1; alias->alias; alias++)
-		      {
-			if (any)
-			  APPEND (", ");
-			APPEND (alias->name);
-			any = 1;
-		      }
-		    
-		    APPEND ("]");
+		    if (any)
+		      APPEND ("]");
 		    any = 1;
 		  }
 	      if (paren)
@@ -2116,6 +2256,8 @@ m68k_ip (char *instring)
 
   for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
     {
+      int have_disp = 0;
+      
       /* This switch is a doozy.
 	 Watch the first step; its a big one! */
       switch (s[0])
@@ -2775,6 +2917,7 @@ m68k_ip (char *instring)
 
 	case 'B':
 	  tmpreg = get_num (&opP->disp, 90);
+	  
 	  switch (s[1])
 	    {
 	    case 'B':
@@ -2786,23 +2929,36 @@ m68k_ip (char *instring)
 	      break;
 	    case 'L':
 	    long_branch:
-	      if (! HAVE_LONG_BRANCH (current_architecture))
-		as_warn (_("Can't use long branches on 68000/68010/5200"));
 	      the_ins.opcode[0] |= 0xff;
 	      add_fix ('l', &opP->disp, 1, 0);
 	      addword (0);
 	      addword (0);
 	      break;
-	    case 'g':
-	      if (subs (&opP->disp))	/* We can't relax it.  */
-		goto long_branch;
-
+	    case 'g': /* Conditional branch */
+	      have_disp = HAVE_LONG_CALL (current_architecture);
+	      goto var_branch;
+	      
+	    case 'b': /* Unconditional branch */
+	      have_disp = HAVE_LONG_BRANCH (current_architecture);
+	      goto var_branch;
+	      
+	    case 's': /* Unconditional subroutine */
+	      have_disp = HAVE_LONG_CALL (current_architecture);
+	      
+	      var_branch:
+	      if (subs (&opP->disp)	/* We can't relax it.  */
 #ifdef OBJ_ELF
-	      /* If the displacement needs pic relocation it cannot be
-		 relaxed.  */
-	      if (opP->disp.pic_reloc != pic_none)
-		goto long_branch;
+		  /* If the displacement needs pic relocation it cannot be
+		     relaxed.  */
+		  || opP->disp.pic_reloc != pic_none
 #endif
+		  || 0)
+		{
+		  if (!have_disp)
+		    as_warn (_("Can't use long branches on this architecture"));
+		  goto long_branch;
+		}
+	      
 	      /* This could either be a symbol, or an absolute
 		 address.  If it's an absolute address, turn it into
 		 an absolute jump right here and keep it out of the
@@ -2828,7 +2984,7 @@ m68k_ip (char *instring)
 	      /* Now we know it's going into the relaxer.  Now figure
 		 out which mode.  We try in this order of preference:
 		 long branch, absolute jump, byte/word branches only.  */
-	      if (HAVE_LONG_BRANCH (current_architecture))
+	      if (have_disp)
 		add_frag (adds (&opP->disp),
 			  SEXT (offs (&opP->disp)),
 			  TAB (BRANCHBWL, SZ_UNDEF));
@@ -2857,7 +3013,7 @@ m68k_ip (char *instring)
 		     jumps.  */
 		  if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
 		      && (HAVE_LONG_BRANCH (current_architecture)
-			  || (! flag_keep_pcrel)))
+			  || ! flag_keep_pcrel))
 		    {
 		      if (HAVE_LONG_BRANCH (current_architecture))
 			add_frag (adds (&opP->disp),
@@ -2955,6 +3111,7 @@ m68k_ip (char *instring)
 	      tmpreg = 0x002;
 	      break;
 	    case TC:
+	    case ASID:
 	      tmpreg = 0x003;
 	      break;
 	    case ACR0:
@@ -2974,6 +3131,7 @@ m68k_ip (char *instring)
 	      tmpreg = 0x007;
 	      break;
 	    case BUSCR:
+	    case MMUBAR:
 	      tmpreg = 0x008;
 	      break;
 
@@ -3005,6 +3163,7 @@ m68k_ip (char *instring)
 	      tmpreg = 0x808;
 	      break;
             case ROMBAR:
+            case ROMBAR0:
 	      tmpreg = 0xC00;
 	      break;
             case ROMBAR1:
@@ -3012,6 +3171,7 @@ m68k_ip (char *instring)
               break;
 	    case FLASHBAR:
 	    case RAMBAR0:
+	    case RAMBAR_ALT:
 	      tmpreg = 0xC04;
 	      break;
 	    case RAMBAR:
@@ -3069,6 +3229,12 @@ m68k_ip (char *instring)
             case PCR3U1:
               tmpreg = 0xD0F;
               break;
+            case CAC:
+              tmpreg = 0xFFE;
+              break;
+            case MBB:
+              tmpreg = 0xFFF;
+              break;
 	    default:
 	      abort ();
 	    }
@@ -3332,6 +3498,14 @@ m68k_ip (char *instring)
 	    tmpreg = 0;
 	  install_operand (s[1], tmpreg);
 	  break;
+	case 'j':
+	  tmpreg = get_num (&opP->disp, 10);
+	  install_operand (s[1], tmpreg - 1);
+	  break;
+	case 'K':
+	  tmpreg = get_num (&opP->disp, 65);
+	  install_operand (s[1], tmpreg);
+	  break;
 	default:
 	  abort ();
 	}
@@ -3400,6 +3574,9 @@ install_operand (int mode, int val)
     case 'd':
       the_ins.opcode[0] |= val << 9;
       break;
+    case 'E':
+      the_ins.opcode[1] |= val << 9;
+      break;
     case '1':
       the_ins.opcode[1] |= val << 12;
       break;
@@ -3744,7 +3921,7 @@ static const struct init_entry init_table[] =
   { "dacr0", DTT0 },		/* Data Access Control Register 0.  */
   { "dacr1", DTT1 },		/* Data Access Control Register 0.  */
 
-  /* mcf5200 versions of same.  The ColdFire programmer's reference
+  /* Coldfire versions of same.  The ColdFire programmer's reference
      manual indicated that the order is 2,3,0,1, but Ken Rose
      <rose@netcom.com> says that 0,1,2,3 is the correct order.  */
   { "acr0", ACR0 },		/* Access Control Unit 0.  */
@@ -3754,12 +3931,14 @@ static const struct init_entry init_table[] =
 
   { "tc", TC },			/* MMU Translation Control Register.  */
   { "tcr", TC },
+  { "asid", ASID },
 
   { "mmusr", MMUSR },		/* MMU Status Register.  */
   { "srp", SRP },		/* User Root Pointer.  */
   { "urp", URP },		/* Supervisor Root Pointer.  */
 
   { "buscr", BUSCR },
+  { "mmubar", MMUBAR },
   { "pcr", PCR },
 
   { "rombar", ROMBAR },		/* ROM Base Address Register.  */
@@ -3769,7 +3948,7 @@ static const struct init_entry init_table[] =
 
   { "mbar0",    MBAR0 },	/* mcfv4e registers.  */
   { "mbar1",    MBAR1 },	/* mcfv4e registers.  */
-  { "rombar0",  ROMBAR },	/* mcfv4e registers.  */
+  { "rombar0",  ROMBAR0 },	/* mcfv4e registers.  */
   { "rombar1",  ROMBAR1 },	/* mcfv4e registers.  */
   { "mpcr",     MPCR },		/* mcfv4e registers.  */
   { "edrambar", EDRAMBAR },	/* mcfv4e registers.  */
@@ -3793,6 +3972,9 @@ static const struct init_entry init_table[] =
   { "rambar",   RAMBAR },  	/* mcf528x registers.  */
 
   { "mbar2",    MBAR2 },  	/* mcf5249 registers.  */
+
+  { "cac",    CAC },  		/* fido registers.  */
+  { "mbb",    MBB },  		/* fido registers.  */
   /* End of control registers.  */
 
   { "ac", AC },
@@ -4207,14 +4389,28 @@ md_begin (void)
 	{
 	  ins = m68k_sorted_opcodes[i];
 
-	  /* We *could* ignore insns that don't match our
-	     arch here by just leaving them out of the hash.  */
+	  /* We must enter all insns into the table, because .arch and
+	     .cpu directives can change things.  */
 	  slak->m_operands = ins->args;
-	  slak->m_opnum = strlen (slak->m_operands) / 2;
 	  slak->m_arch = ins->arch;
 	  slak->m_opcode = ins->opcode;
-	  /* This is kludgey.  */
-	  slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
+	  
+	  /* In most cases we can determine the number of opcode words
+	     by checking the second word of the mask.  Unfortunately
+	     some instructions have 2 opcode words, but no fixed bits
+	     in the second word.  A leading dot in the operands
+	     string also indicates 2 opcodes.  */
+	  if (*slak->m_operands == '.')
+	    {
+	      slak->m_operands++;
+	      slak->m_codenum = 2;
+	    }
+	  else if (ins->match & 0xffffL)
+	    slak->m_codenum = 2;
+	  else
+	    slak->m_codenum = 1;
+	  slak->m_opnum = strlen (slak->m_operands) / 2;
+	  
 	  if (i + 1 != m68k_numopcodes
 	      && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
 	    {
@@ -4547,6 +4743,14 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	S_SET_WEAK (fixP->fx_addsy);
       return;
     }
+#elif defined(OBJ_AOUT)
+  /* PR gas/3041 Do not fix frags referencing a weak symbol.  */
+  if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
+    {
+      memset (buf, 0, fixP->fx_size);
+      fixP->fx_addnumber = val;	/* Remember value for emit_reloc.  */
+      return;
+    }
 #endif
 
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
@@ -4597,7 +4801,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
   if ((addressT) val > upper_limit
       && (val > 0 || val < lower_limit))
-    as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
+    as_bad_where (fixP->fx_file, fixP->fx_line,
+		  _("value %ld out of range"), (long)val);
 
   /* A one byte PC-relative reloc means a short branch.  We can't use
      a short branch with a value of 0 or -1, because those indicate
@@ -4610,7 +4815,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       && (fixP->fx_addsy == NULL
 	  || S_IS_DEFINED (fixP->fx_addsy))
       && (val == 0 || val == -1))
-    as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
+    as_bad_where (fixP->fx_file, fixP->fx_line,
+		  _("invalid byte branch offset"));
 }
 
 /* *fragP has been relaxed to its final size, and now needs to have
@@ -4621,7 +4827,7 @@ static void
 md_convert_frag_1 (fragS *fragP)
 {
   long disp;
-  fixS *fixP;
+  fixS *fixP = NULL;
 
   /* Address in object code of the displacement.  */
   register int object_address = fragP->fr_fix + fragP->fr_address;
@@ -4656,35 +4862,37 @@ md_convert_frag_1 (fragS *fragP)
     case TAB (BRABSJCOND, SHORT):
     case TAB (BRANCHBW, SHORT):
       fragP->fr_opcode[1] = 0x00;
-      fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC16);
+      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
       fragP->fr_fix += 2;
       break;
     case TAB (BRANCHBWL, LONG):
       fragP->fr_opcode[1] = (char) 0xFF;
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
       fragP->fr_fix += 4;
       break;
     case TAB (BRABSJUNC, LONG):
       if (fragP->fr_opcode[0] == 0x61)		/* jbsr */
 	{
 	  if (flag_keep_pcrel)
-    	    as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
+    	    as_bad_where (fragP->fr_file, fragP->fr_line,
+			  _("Conversion of PC relative BSR to absolute JSR"));
 	  fragP->fr_opcode[0] = 0x4E;
 	  fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand.  */
-	  fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
-		   0, RELAX_RELOC_ABS32);
+	  fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+			  fragP->fr_offset, 0, RELAX_RELOC_ABS32);
 	  fragP->fr_fix += 4;
 	}
       else if (fragP->fr_opcode[0] == 0x60)	/* jbra */
 	{
 	  if (flag_keep_pcrel)
-	    as_fatal (_("Tried to convert PC relative branch to absolute jump"));
+	    as_bad_where (fragP->fr_file, fragP->fr_line,
+		      _("Conversion of PC relative branch to absolute jump"));
 	  fragP->fr_opcode[0] = 0x4E;
 	  fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand.  */
-	  fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
-		   0, RELAX_RELOC_ABS32);
+	  fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+			  fragP->fr_offset, 0, RELAX_RELOC_ABS32);
 	  fragP->fr_fix += 4;
 	}
       else
@@ -4696,7 +4904,8 @@ md_convert_frag_1 (fragS *fragP)
       break;
     case TAB (BRABSJCOND, LONG):
       if (flag_keep_pcrel)
-    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+    	as_bad_where (fragP->fr_file, fragP->fr_line,
+		  _("Conversion of PC relative conditional branch to absolute jump"));
 
       /* Only Bcc 68000 instructions can come here
 	 Change bcc into b!cc/jmp absl long.  */
@@ -4709,26 +4918,26 @@ md_convert_frag_1 (fragS *fragP)
       *buffer_address++ = 0x4e;	/* put in jmp long (0x4ef9) */
       *buffer_address++ = (char) 0xf9;
       fragP->fr_fix += 2;	/* Account for jmp instruction.  */
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
-	       fragP->fr_offset, 0, RELAX_RELOC_ABS32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
       fragP->fr_fix += 4;
       break;
     case TAB (FBRANCH, SHORT):
       know ((fragP->fr_opcode[1] & 0x40) == 0);
-      fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC16);
+      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
       fragP->fr_fix += 2;
       break;
     case TAB (FBRANCH, LONG):
       fragP->fr_opcode[1] |= 0x40;	/* Turn on LONG bit.  */
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
       fragP->fr_fix += 4;
       break;
     case TAB (DBCCLBR, SHORT):
     case TAB (DBCCABSJ, SHORT):
-      fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC16);
+      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
       fragP->fr_fix += 2;
       break;
     case TAB (DBCCLBR, LONG):
@@ -4736,7 +4945,8 @@ md_convert_frag_1 (fragS *fragP)
 	 Change dbcc into dbcc/bral.
 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
       if (flag_keep_pcrel)
-    	as_fatal (_("Tried to convert DBcc to absolute jump"));
+    	as_bad_where (fragP->fr_file, fragP->fr_line,
+		  _("Conversion of DBcc to absolute jump"));
 
       *buffer_address++ = 0x00;	/* Branch offset = 4.  */
       *buffer_address++ = 0x04;
@@ -4746,8 +4956,8 @@ md_convert_frag_1 (fragS *fragP)
       *buffer_address++ = (char) 0xff;
 
       fragP->fr_fix += 6;	/* Account for bra/jmp instructions.  */
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
-	       RELAX_RELOC_PC32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
       fragP->fr_fix += 4;
       break;
     case TAB (DBCCABSJ, LONG):
@@ -4755,7 +4965,8 @@ md_convert_frag_1 (fragS *fragP)
 	 Change dbcc into dbcc/jmp.
 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
       if (flag_keep_pcrel)
-    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+    	as_bad_where (fragP->fr_file, fragP->fr_line,
+		      _("Conversion of PC relative conditional branch to absolute jump"));
 
       *buffer_address++ = 0x00;		/* Branch offset = 4.  */
       *buffer_address++ = 0x04;
@@ -4765,15 +4976,15 @@ md_convert_frag_1 (fragS *fragP)
       *buffer_address++ = (char) 0xf9;
 
       fragP->fr_fix += 6;		/* Account for bra/jmp instructions.  */
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
-	       RELAX_RELOC_ABS32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
       fragP->fr_fix += 4;
       break;
     case TAB (PCREL1632, SHORT):
       fragP->fr_opcode[1] &= ~0x3F;
       fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
-      fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
-	       fragP->fr_offset, 1, RELAX_RELOC_PC16);
+      fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
       fragP->fr_fix += 2;
       break;
     case TAB (PCREL1632, LONG):
@@ -4813,24 +5024,29 @@ md_convert_frag_1 (fragS *fragP)
       fragP->fr_fix += 4;
       break;
     case TAB (ABSTOPCREL, SHORT):
-      fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
-	       1, RELAX_RELOC_PC16);
+      fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
       fragP->fr_fix += 2;
       break;
     case TAB (ABSTOPCREL, LONG):
       if (flag_keep_pcrel)
-    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
+	as_fatal (_("Conversion of PC relative displacement to absolute"));
       /* The thing to do here is force it to ABSOLUTE LONG, since
 	 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway.  */
       if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
 	abort ();
       fragP->fr_opcode[1] &= ~0x3F;
       fragP->fr_opcode[1] |= 0x39;	/* Mode 7.1 */
-      fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
-	       0, RELAX_RELOC_ABS32);
+      fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
+		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
       fragP->fr_fix += 4;
       break;
     }
+  if (fixP)
+    {
+      fixP->fx_file = fragP->fr_file;
+      fixP->fx_line = fragP->fr_line;
+    }
 }
 
 void
@@ -5054,6 +5270,7 @@ md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
    50:  absolute 0:127	   only
    55:  absolute -64:63    only
    60:  absolute -128:127  only
+   65:  absolute 0:511     only
    70:  absolute 0:4095	   only
    80:  absolute -1, 1:7   only
    90:  No bignums.          */
@@ -5109,6 +5326,10 @@ get_num (struct m68k_exp *exp, int ok)
 	  if ((valueT) SEXT (offs (exp)) + 128 > 255)
 	    goto outrange;
 	  break;
+	case 65:
+	  if ((valueT) TRUNC (offs (exp)) > 511)
+	    goto outrange;
+	  break;
 	case 70:
 	  if ((valueT) TRUNC (offs (exp)) > 4095)
 	    {
@@ -7497,6 +7718,8 @@ m68k_elf_final_processing (void)
   /* Set file-specific flags if this is a cpu32 processor.  */
   if (cpu_of_arch (current_architecture) & cpu32)
     flags |= EF_M68K_CPU32;
+  else if (cpu_of_arch (current_architecture) & fido_a)
+    flags |= EF_M68K_FIDO;
   else if ((cpu_of_arch (current_architecture) & m68000up)
 	   && !(cpu_of_arch (current_architecture) & m68020up))
     flags |= EF_M68K_M68000;
@@ -7505,24 +7728,25 @@ m68k_elf_final_processing (void)
     {
       static const unsigned isa_features[][2] =
       {
-	{EF_M68K_ISA_A_NODIV, mcfisa_a},
-	{EF_M68K_ISA_A,	mcfisa_a|mcfhwdiv},
-	{EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
-	{EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
-	{EF_M68K_ISA_B,	mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
+	{EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
+	{EF_M68K_CF_ISA_A,	mcfisa_a|mcfhwdiv},
+	{EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
+	{EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
+	{EF_M68K_CF_ISA_B,	mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
+	{EF_M68K_CF_ISA_C,	mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
 	{0,0},
       };
       static const unsigned mac_features[][2] =
       {
-	{EF_M68K_MAC, mcfmac},
-	{EF_M68K_EMAC, mcfemac},
+	{EF_M68K_CF_MAC, mcfmac},
+	{EF_M68K_CF_EMAC, mcfemac},
 	{0,0},
       };
       unsigned ix;
       unsigned pattern;
       
       pattern = (current_architecture
-		 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
+		 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
       for (ix = 0; isa_features[ix][1]; ix++)
 	{
 	  if (pattern == isa_features[ix][1])
@@ -7539,7 +7763,7 @@ m68k_elf_final_processing (void)
       else
 	{
 	  if (current_architecture & cfloat)
-	    flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
+	    flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
 
 	  pattern = current_architecture & (mcfmac|mcfemac);
 	  if (pattern)
@@ -7562,7 +7786,7 @@ m68k_elf_final_processing (void)
 #endif
 
 int
-tc_m68k_regname_to_dw2regnum (const char *regname)
+tc_m68k_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum;
   static const char *const regnames[] =
diff --git a/gas/config/tc-m68k.h b/gas/config/tc-m68k.h
index fc05a9264e6a..f1464fdbfc57 100644
--- a/gas/config/tc-m68k.h
+++ b/gas/config/tc-m68k.h
@@ -174,7 +174,7 @@ extern struct relax_type md_relax_table[];
 #define DWARF2_CIE_DATA_ALIGNMENT (-4)
 
 #define tc_regname_to_dw2regnum tc_m68k_regname_to_dw2regnum
-extern int tc_m68k_regname_to_dw2regnum (const char *regname);
+extern int tc_m68k_regname_to_dw2regnum (char *regname);
 
 #define tc_cfi_frame_initial_instructions tc_m68k_frame_initial_instructions
 extern void tc_m68k_frame_initial_instructions (void);
diff --git a/gas/config/tc-maxq.c b/gas/config/tc-maxq.c
index c1a11afc05fd..293d70003981 100644
--- a/gas/config/tc-maxq.c
+++ b/gas/config/tc-maxq.c
@@ -1,6 +1,6 @@
 /* tc-maxq.c -- assembler code for a MAXQ chip.
 
-   Copyright 2004, 2005 Free Software Foundation, Inc.
+   Copyright 2004, 2005, 2006 Free Software Foundation, Inc.
 
    Contributed by HCL Technologies Pvt. Ltd.
 
@@ -34,10 +34,6 @@
 #define MAXQ10S 1
 #endif
 
-#ifndef _STRING_H
-#include "string.h"
-#endif
-
 #ifndef DEFAULT_ARCH
 #define DEFAULT_ARCH "MAXQ20"
 #endif
@@ -451,7 +447,7 @@ maxq20_cons_fix_new (fragS * frag, unsigned int off, unsigned int len,
 }
 
 /* GAS will call this for every rs_machine_dependent fragment. The
-   instruction is compleated using the data from the relaxation pass. It may
+   instruction is completed using the data from the relaxation pass. It may
    also create any necessary relocations.  */
 void
 md_convert_frag (bfd *   headers ATTRIBUTE_UNUSED,
@@ -687,7 +683,7 @@ const pseudo_typeS md_pseudo_table[] =
 #define SET_PFX_ARG(x) (PFX_INSN[1] = x)
 
 
-/* This function sets the PFX value coresponding to the specs. Source
+/* This function sets the PFX value corresponding to the specs. Source
    Destination Index Selection ---------------------------------- Write To|
    SourceRegRange | Dest Addr Range
    ------------------------------------------------------ PFX[0] | 0h-Fh |
@@ -1150,7 +1146,7 @@ maxq20_immediate (char *imm_start)
       return 1;
     }
 
-  /* Check For Sign Charcater.  */
+  /* Check For Sign Character.  */
   sign_val = 0;
 
   do
@@ -1600,7 +1596,7 @@ maxq20_operand (char *operand_string)
 	  return 1;
 	}
 
-      /* Get the origanal string.  */
+      /* Get the original string.  */
       memcpy (op_string, operand_string, strlen (operand_string) + 1);
       ii = strlen (operand_string) + 1;
 
@@ -3101,7 +3097,7 @@ md_assemble (char *line)
   if (!match_filters ())
     return;
 
-  /* Check for the approprate PFX register.  */
+  /* Check for the appropriate PFX register.  */
   set_prefix ();
   pfx_for_imm_val (0);
 
diff --git a/gas/config/tc-maxq.h b/gas/config/tc-maxq.h
index 12b7a9497acc..dfa37f59ed65 100644
--- a/gas/config/tc-maxq.h
+++ b/gas/config/tc-maxq.h
@@ -1,4 +1,4 @@
-/* tc-maxq.h -- Header file for the asssembler(MAXQ)
+/* tc-maxq.h -- Header file for the assembler(MAXQ)
 
    Copyright 2004, 2005  Free Software Foundation, Inc.
 
@@ -116,10 +116,10 @@ extern void maxq20_cons_fix_new (fragS *, unsigned int, unsigned int, expression
 extern void maxq_number_to_chars (char *, valueT, int);
 
 /* If this macro is defined, it is a pointer to a NULL terminated list of
-   chracters which may appear in an operand. GAS already assumes that all
-   alphanumeric chracters, and '$', '.', and '_' may appear in an
+   characters which may appear in an operand. GAS already assumes that all
+   alphanumeric characters, and '$', '.', and '_' may appear in an
    operand("symbol_char"in app.c). This macro may be defined to treat
-   additional chracters as appearing in an operand. This affects the way in
+   additional characters as appearing in an operand. This affects the way in
    which GAS removes whitespaces before passing the string to md_assemble.  */
 #define tc_symbol_chars_extra_symbol_chars
 
diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c
index a795a5550362..e4adf0583542 100644
--- a/gas/config/tc-mcore.c
+++ b/gas/config/tc-mcore.c
@@ -1,5 +1,5 @@
 /* tc-mcore.c -- Assemble code for M*Core
-   Copyright 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -19,14 +19,11 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
-#include "bfd.h"
 #include "subsegs.h"
 #define DEFINE_TABLE
 #include "../opcodes/mcore-opc.h"
 #include "safe-ctype.h"
-#include <string.h>
 
 #ifdef OBJ_ELF
 #include "elf/mcore.h"
@@ -2173,24 +2170,10 @@ md_estimate_size_before_relax (fragS * fragP, segT segment_type)
 void
 md_number_to_chars (char * ptr, valueT use, int nbytes)
 {
-  if (! target_big_endian)
-    switch (nbytes)
-      {
-      case 4: ptr[3] = (use >> 24) & 0xff; /* Fall through.  */
-      case 3: ptr[2] = (use >> 16) & 0xff; /* Fall through.  */
-      case 2: ptr[1] = (use >>  8) & 0xff; /* Fall through.  */
-      case 1: ptr[0] = (use >>  0) & 0xff;    break;
-      default: abort ();
-      }
+  if (target_big_endian)
+    number_to_chars_bigendian (ptr, use, nbytes);
   else
-    switch (nbytes)
-      {
-      case 4: *ptr++ = (use >> 24) & 0xff; /* Fall through.  */
-      case 3: *ptr++ = (use >> 16) & 0xff; /* Fall through.  */
-      case 2: *ptr++ = (use >>  8) & 0xff; /* Fall through.  */
-      case 1: *ptr++ = (use >>  0) & 0xff;    break;
-      default: abort ();
-      }
+    number_to_chars_littleendian (ptr, use, nbytes);
 }
 
 /* Round up a section size to the appropriate boundary.  */
diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c
new file mode 100644
index 000000000000..b3b17d3c7a15
--- /dev/null
+++ b/gas/config/tc-mep.c
@@ -0,0 +1,1886 @@
+/* tc-mep.c -- Assembler for the Toshiba Media Processor.
+   Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#include <stdio.h>
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/mep-desc.h"
+#include "opcodes/mep-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/mep.h"
+#include "libbfd.h"
+#include "xregex.h"
+
+/* Structure to hold all of the different components describing
+   an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int                   num_fixups;
+  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
+  int                   indices [MAX_OPERAND_INSTANCES];
+} mep_insn;
+
+static int mode = CORE; /* Start in core mode. */
+static int pluspresent = 0;
+static int allow_disabled_registers = 0;
+static int library_flag = 0;
+
+/* We're going to need to store all of the instructions along with
+   their fixups so that we can parallelization grouping rules. */
+
+static mep_insn saved_insns[MAX_SAVED_FIXUP_CHAINS];
+static int num_insns_saved = 0;
+
+const char comment_chars[]        = "#";
+const char line_comment_chars[]   = ";#";
+const char line_separator_chars[] = ";";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+static void mep_switch_to_vliw_mode (int);
+static void mep_switch_to_core_mode (int);
+static void mep_s_vtext (int);
+static void mep_noregerr (int);
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word",	cons,	                        4 },
+  { "file",	(void (*) (int)) dwarf2_directive_file,   	0 },
+  { "loc",	dwarf2_directive_loc,   	0 },
+  { "vliw", 	mep_switch_to_vliw_mode,	0 },
+  { "core", 	mep_switch_to_core_mode,	0 },
+  { "vtext", 	mep_s_vtext,             	0 },
+  { "noregerr",	mep_noregerr,	             	0 },
+  { NULL, 	NULL,		        	0 }
+};
+
+/* Relocations against symbols are done in two
+   parts, with a HI relocation and a LO relocation.  Each relocation
+   has only 16 bits of space to store an addend.  This means that in
+   order for the linker to handle carries correctly, it must be able
+   to locate both the HI and the LO relocation.  This means that the
+   relocations must appear in order in the relocation table.
+
+   In order to implement this, we keep track of each unmatched HI
+   relocation.  We then sort them so that they immediately precede the
+   corresponding LO relocation. */
+
+struct mep_hi_fixup
+{
+  struct mep_hi_fixup * next;	/* Next HI fixup.  */
+  fixS * fixp;			/* This fixup.  */
+  segT seg;			/* The section this fixup is in.  */
+};
+
+/* The list of unmatched HI relocs.  */
+static struct mep_hi_fixup * mep_hi_fixup_list;
+
+
+#define OPTION_EB		(OPTION_MD_BASE + 0)
+#define OPTION_EL		(OPTION_MD_BASE + 1)
+#define OPTION_CONFIG		(OPTION_MD_BASE + 2)
+#define OPTION_AVERAGE		(OPTION_MD_BASE + 3)
+#define OPTION_NOAVERAGE	(OPTION_MD_BASE + 4)
+#define OPTION_MULT		(OPTION_MD_BASE + 5)
+#define OPTION_NOMULT		(OPTION_MD_BASE + 6)
+#define OPTION_DIV		(OPTION_MD_BASE + 7)
+#define OPTION_NODIV		(OPTION_MD_BASE + 8)
+#define OPTION_BITOPS		(OPTION_MD_BASE + 9)
+#define OPTION_NOBITOPS		(OPTION_MD_BASE + 10)
+#define OPTION_LEADZ		(OPTION_MD_BASE + 11)
+#define OPTION_NOLEADZ		(OPTION_MD_BASE + 12)
+#define OPTION_ABSDIFF		(OPTION_MD_BASE + 13)
+#define OPTION_NOABSDIFF	(OPTION_MD_BASE + 14)
+#define OPTION_MINMAX		(OPTION_MD_BASE + 15)
+#define OPTION_NOMINMAX		(OPTION_MD_BASE + 16)
+#define OPTION_CLIP		(OPTION_MD_BASE + 17)
+#define OPTION_NOCLIP		(OPTION_MD_BASE + 18)
+#define OPTION_SATUR		(OPTION_MD_BASE + 19)
+#define OPTION_NOSATUR		(OPTION_MD_BASE + 20)
+#define OPTION_COP32		(OPTION_MD_BASE + 21)
+#define OPTION_REPEAT		(OPTION_MD_BASE + 25)
+#define OPTION_NOREPEAT		(OPTION_MD_BASE + 26)
+#define OPTION_DEBUG		(OPTION_MD_BASE + 27)
+#define OPTION_NODEBUG		(OPTION_MD_BASE + 28)
+#define OPTION_LIBRARY		(OPTION_MD_BASE + 29)
+
+struct option md_longopts[] = {
+  { "EB",          no_argument, NULL, OPTION_EB},
+  { "EL",          no_argument, NULL, OPTION_EL},
+  { "mconfig",     required_argument, NULL, OPTION_CONFIG},
+  { "maverage",    no_argument, NULL, OPTION_AVERAGE},
+  { "mno-average", no_argument, NULL, OPTION_NOAVERAGE},
+  { "mmult",       no_argument, NULL, OPTION_MULT},
+  { "mno-mult",    no_argument, NULL, OPTION_NOMULT},
+  { "mdiv",        no_argument, NULL, OPTION_DIV},
+  { "mno-div",     no_argument, NULL, OPTION_NODIV},
+  { "mbitops",     no_argument, NULL, OPTION_BITOPS},
+  { "mno-bitops",  no_argument, NULL, OPTION_NOBITOPS},
+  { "mleadz",      no_argument, NULL, OPTION_LEADZ},
+  { "mno-leadz",   no_argument, NULL, OPTION_NOLEADZ},
+  { "mabsdiff",    no_argument, NULL, OPTION_ABSDIFF},
+  { "mno-absdiff", no_argument, NULL, OPTION_NOABSDIFF},
+  { "mminmax",     no_argument, NULL, OPTION_MINMAX},
+  { "mno-minmax",  no_argument, NULL, OPTION_NOMINMAX},
+  { "mclip",       no_argument, NULL, OPTION_CLIP},
+  { "mno-clip",    no_argument, NULL, OPTION_NOCLIP},
+  { "msatur",      no_argument, NULL, OPTION_SATUR},
+  { "mno-satur",   no_argument, NULL, OPTION_NOSATUR},
+  { "mcop32",	   no_argument, NULL, OPTION_COP32},
+  { "mdebug",      no_argument, NULL, OPTION_DEBUG},
+  { "mno-debug",   no_argument, NULL, OPTION_NODEBUG},
+  { "mlibrary",    no_argument, NULL, OPTION_LIBRARY},
+  { NULL, 0, NULL, 0 } };
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+static int optbits = 0;
+static int optbitset = 0;
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  int i, idx;
+  switch (c)
+    {
+    case OPTION_EB:
+      target_big_endian = 1;
+      break;
+    case OPTION_EL:
+      target_big_endian = 0;
+      break;
+    case OPTION_CONFIG:
+      idx = 0;
+      for (i=1; mep_config_map[i].name; i++)
+	if (strcmp (mep_config_map[i].name, arg) == 0)
+	  {
+	    idx = i;
+	    break;
+	  }
+      if (!idx)
+	{
+	  fprintf (stderr, "Error: unknown configuration %s\n", arg);
+	  return 0;
+	}
+      mep_config_index = idx;
+      target_big_endian = mep_config_map[idx].big_endian;
+      break;
+    case OPTION_AVERAGE:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      break;
+    case OPTION_NOAVERAGE:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+      break;
+    case OPTION_MULT:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      break;
+    case OPTION_NOMULT:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+      break;
+    case OPTION_DIV:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      break;
+    case OPTION_NODIV:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+      break;
+    case OPTION_BITOPS:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      break;
+    case OPTION_NOBITOPS:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+      break;
+    case OPTION_LEADZ:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      break;
+    case OPTION_NOLEADZ:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+      break;
+    case OPTION_ABSDIFF:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      break;
+    case OPTION_NOABSDIFF:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+      break;
+    case OPTION_MINMAX:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      break;
+    case OPTION_NOMINMAX:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+      break;
+    case OPTION_CLIP:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      break;
+    case OPTION_NOCLIP:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+      break;
+    case OPTION_SATUR:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      break;
+    case OPTION_NOSATUR:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+      break;
+    case OPTION_COP32:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+      break;
+    case OPTION_DEBUG:
+      optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      break;
+    case OPTION_NODEBUG:
+      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
+      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+      break;
+    case OPTION_LIBRARY:
+      library_flag = EF_MEP_LIBRARY;
+      break;
+    case OPTION_REPEAT:
+    case OPTION_NOREPEAT:
+      break;
+    default:
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  fprintf (stream, _("MeP specific command line options:\n\
+  -EB                     assemble for a big endian system (default)\n\
+  -EL                     assemble for a little endian system\n\
+  -mconfig=<name>         specify a chip configuration to use\n\
+  -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
+  -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
+  -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
+                          enable/disable the given opcodes\n\
+\n\
+  If -mconfig is given, the other -m options modify it.  Otherwise,\n\
+  if no -m options are given, all core opcodes are enabled;\n\
+  if any enabling -m options are given, only those are enabled;\n\
+  if only disabling -m options are given, only those are disabled.\n\
+"));
+  if (mep_config_map[1].name)
+    {
+      int i;
+      fprintf (stream, "  -mconfig=STR            specify the configuration to use\n");
+      fprintf (stream, "  Configurations:");
+      for (i=0; mep_config_map[i].name; i++)
+	fprintf (stream, " %s", mep_config_map[i].name);
+      fprintf (stream, "\n");
+    }
+}
+
+
+
+static void
+mep_check_for_disabled_registers (mep_insn *insn)
+{
+  static int initted = 0;
+  static int has_mul_div = 0;
+  static int has_cop = 0;
+  static int has_debug = 0;
+  unsigned int b, r;
+
+  if (allow_disabled_registers)
+    return;
+
+#if !CGEN_INT_INSN_P
+  if (target_big_endian)
+    b = insn->buffer[0] * 256 + insn->buffer[1];
+  else
+    b = insn->buffer[1] * 256 + insn->buffer[0];
+#else
+  b = insn->buffer[0];
+#endif
+
+  if ((b & 0xfffff00e) == 0x7008 /* stc */
+      || (b & 0xfffff00e) == 0x700a /* ldc */)
+    {
+      if (!initted)
+	{
+	  initted = 1;
+	  if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
+	      || (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
+	    has_mul_div = 1;
+	  if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
+	    has_debug = 1;
+	  if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
+	    has_cop = 1;
+	}
+
+      r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
+      switch (r)
+	{
+	case 7: /* $hi */
+	case 8: /* $lo */
+	  if (!has_mul_div)
+	    as_bad ("$hi and $lo are disabled when MUL and DIV are off");
+	  break;
+	case 12: /* $mb0 */
+	case 13: /* $me0 */
+	case 14: /* $mb1 */
+	case 15: /* $me1 */
+	  if (!has_cop)
+	    as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
+	  break;
+	case 24: /* $dbg */
+	case 25: /* $depc */
+	  if (!has_debug)
+	    as_bad ("$dbg and $depc are disabled when DEBUG is off");
+	  break;
+	}
+    }
+}
+
+static int
+mep_machine (void)
+{
+  switch (MEP_CPU)
+    {
+    default: break;
+    case EF_MEP_CPU_C2: return bfd_mach_mep;
+    case EF_MEP_CPU_C3: return bfd_mach_mep;
+    case EF_MEP_CPU_C4: return bfd_mach_mep;
+    case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
+    }
+
+  return bfd_mach_mep;
+}
+
+/* The MeP version of the cgen parse_operand function.  The only difference
+   from the standard version is that we want to avoid treating '$foo' and
+   '($foo...)' as references to a symbol called '$foo'.  The chances are
+   that '$foo' is really a misspelt register.  */
+
+static const char *
+mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
+		   const char **strP, int opindex, int opinfo,
+		   enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
+{
+  if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
+    {
+      const char *next;
+
+      next = *strP;
+      while (*next == '(')
+	next++;
+      if (*next == '$')
+	return "Not a valid literal";
+    }
+  return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
+				 resultP, valueP);
+}
+
+void
+md_begin ()
+{
+  /* Initialize the `cgen' interface.  */
+
+  /* If the user specifies no options, we default to allowing
+     everything.  If the user specifies any enabling options, we
+     default to allowing only what is specified.  If the user
+     specifies only disabling options, we only disable what is
+     specified.  If the user specifies options and a config, the
+     options modify the config.  */
+  if (optbits && mep_config_index == 0)
+    MEP_OMASK = optbits;
+  else
+    MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
+
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+					 CGEN_CPU_OPEN_ENDIAN,
+					 target_big_endian
+					 ? CGEN_ENDIAN_BIG
+					 : CGEN_ENDIAN_LITTLE,
+					 CGEN_CPU_OPEN_ISAS, 0,
+					 CGEN_CPU_OPEN_END);
+  mep_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);
+
+  /* Identify the architecture.  */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());
+
+  /* Store the configuration number and core.  */
+  bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);
+
+  /* Initialize the array we'll be using to store fixups.  */
+  gas_cgen_initialize_saved_fixups_array();
+}
+
+/* Variant of mep_cgen_assemble_insn.  Assemble insn STR of cpu CD as a 
+   coprocessor instruction, if possible, into FIELDS, BUF, and INSN.  */
+
+static const CGEN_INSN *
+mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
+			    const char *str,
+			    CGEN_FIELDS *fields,
+			    CGEN_INSN_BYTES_PTR buf,
+			    const struct cgen_insn *pinsn)
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *errmsg = NULL;
+
+  /* The instructions are stored in hashed lists. */
+  ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, 
+				CGEN_INSN_MNEMONIC (pinsn));
+
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), 
+		  CGEN_INSN_MNEMONIC (pinsn)) == 0
+	  && MEP_INSN_COP_P (ilist->insn)
+	  && mep_cgen_insn_supported (cd, insn))
+	{
+	  str = start;
+
+	  /* skip this insn if str doesn't look right lexically */
+	  if (CGEN_INSN_RX (insn) != NULL &&
+	      regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	    continue;
+
+	  /* Allow parse/insert handlers to obtain length of insn.  */
+	  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+	  errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+	  if (errmsg != NULL)
+	    continue;
+	  
+	  errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+					      (bfd_vma) 0);
+	  if (errmsg != NULL)
+	    continue;
+
+	  return insn;
+	}
+    }
+  return pinsn;
+}
+
+static void
+mep_save_insn (mep_insn insn)
+{
+  /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
+  if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
+    {
+      as_fatal("index into saved_insns[] out of bounds.");
+      return;
+    }
+  saved_insns[num_insns_saved] = insn;
+  gas_cgen_save_fixups(num_insns_saved);
+  num_insns_saved++;
+}
+
+static void
+mep_check_parallel32_scheduling (void)
+{
+  int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+  /* More than two instructions means that either someone is referring to
+     an internally parallel core or an internally parallel coprocessor,
+     neither of which are supported at this time.  */
+  if ( num_insns_saved > 2 )
+    as_fatal("Internally paralled cores and coprocessors not supported.");
+
+  /* If there are no insns saved, that's ok.  Just return.  This will
+     happen when mep_process_saved_insns is called when the end of the
+     source file is reached and there are no insns left to be processed.  */
+  if (num_insns_saved == 0)
+    return;
+
+  /* Check some of the attributes of the first insn.  */
+  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+  if (num_insns_saved == 2)
+    {
+      /* Check some of the attributes of the first insn.  */
+      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+      if ((insn0iscopro && !insn1iscopro)
+          || (insn1iscopro && !insn0iscopro))
+	{
+          /* We have one core and one copro insn.  If their sizes
+             add up to 32, then the combination is valid.  */
+	  if (insn0length + insn1length == 32)
+	    return;
+          else
+	    as_bad ("core and copro insn lengths must total 32 bits.");
+	}
+      else
+        as_bad ("vliw group must consist of 1 core and 1 copro insn."); 
+    }
+  else
+    {
+      /* If we arrive here, we have one saved instruction.  There are a
+	 number of possible cases:
+
+	 1.  The instruction is a 32 bit core or coprocessor insn and
+             can be executed by itself.  Valid.
+
+         2.  The instrucion is a core instruction for which a cop nop
+             exists.  In this case, insert the cop nop into the saved
+             insn array after the core insn and return.  Valid.
+
+         3.  The instruction is a coprocessor insn for which a core nop
+             exists.  In this case, move the coprocessor insn to the
+             second element of the array and put the nop in the first
+	     element then return.  Valid.
+
+         4. The instruction is a core or coprocessor instruction for
+            which there is no matching coprocessor or core nop to use
+	    to form a valid vliw insn combination.  In this case, we
+	    we have to abort.  */
+
+      if (insn0length > 32)
+	as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
+
+      if (insn0length == 32)
+	return;
+
+      /* Insn is smaller than datapath.  If there are no matching
+         nops for this insn, then terminate assembly.  */
+      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+                                CGEN_INSN_VLIW32_NO_MATCHING_NOP))
+	as_fatal ("No valid nop.");
+
+      /* At this point we know that we have a single 16-bit insn that has 
+	 a matching nop.  We have to assemble it and put it into the saved 
+         insn and fixup chain arrays. */
+
+      if (insn0iscopro)
+	{
+          char *errmsg;
+          mep_insn insn;
+         
+          /* Move the insn and it's fixups to the second element of the
+             saved insns arrary and insert a 16 bit core nope into the
+             first element. */
+             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+                                                 &insn.fields, insn.buffer,
+                                                 &errmsg);
+             if (!insn.insn)
+               {
+                 as_bad ("%s", errmsg);
+                 return;
+               }
+
+             /* Move the insn in element 0 to element 1 and insert the
+                 nop into element 0.  Move the fixups in element 0 to
+                 element 1 and save the current fixups to element 0.  
+                 Really there aren't any fixups at this point because we're
+                 inserting a nop but we might as well be general so that
+                 if there's ever a need to insert a general insn, we'll
+                 have an example. */
+              saved_insns[1] = saved_insns[0];
+              saved_insns[0] = insn;
+              num_insns_saved++;
+              gas_cgen_swap_fixups (0);
+              gas_cgen_save_fixups (1);
+	}
+      else
+	{
+          char * errmsg;
+          mep_insn insn;
+	  int insn_num = saved_insns[0].insn->base->num;
+
+	  /* Use 32 bit branches and skip the nop.  */
+	  if (insn_num == MEP_INSN_BSR12
+	      || insn_num == MEP_INSN_BEQZ
+	      || insn_num == MEP_INSN_BNEZ)
+	    return;
+
+          /* Insert a 16-bit coprocessor nop.  Note that at the time */
+          /* this was done, no 16-bit coprocessor nop was defined.   */
+	  insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+					      &insn.fields, insn.buffer,
+					      &errmsg);
+          if (!insn.insn)
+            {
+              as_bad ("%s", errmsg);
+              return;
+            }
+
+          /* Now put the insn and fixups into the arrays.  */
+          mep_save_insn (insn);
+	}
+    }
+}
+
+static void
+mep_check_parallel64_scheduling (void)
+{
+  int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+  /* More than two instructions means that someone is referring to an
+     internally parallel core or an internally parallel coprocessor.  */
+  /* These are not currently supported.  */
+  if (num_insns_saved > 2)
+    as_fatal ("Internally parallel cores of coprocessors not supported.");
+
+  /* If there are no insns saved, that's ok.  Just return.  This will
+     happen when mep_process_saved_insns is called when the end of the
+     source file is reached and there are no insns left to be processed.  */
+  if (num_insns_saved == 0)
+    return;
+
+  /* Check some of the attributes of the first insn.  */
+  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+  if (num_insns_saved == 2)
+    {
+      /* Check some of the attributes of the first insn. */
+      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+      if ((insn0iscopro && !insn1iscopro)
+	  || (insn1iscopro && !insn0iscopro))
+	{
+	  /* We have one core and one copro insn.  If their sizes
+	     add up to 64, then the combination is valid.  */
+	  if (insn0length + insn1length == 64)
+            return;
+	  else
+            as_bad ("core and copro insn lengths must total 64 bits.");
+	}
+      else
+        as_bad ("vliw group must consist of 1 core and 1 copro insn.");
+    }
+  else
+    {
+      /* If we arrive here, we have one saved instruction.  There are a
+	 number of possible cases:
+
+         1.  The instruction is a 64 bit coprocessor insn and can be
+             executed by itself.  Valid.
+
+         2.  The instrucion is a core instruction for which a cop nop
+             exists.  In this case, insert the cop nop into the saved
+             insn array after the core insn and return.  Valid.
+
+         3.  The instruction is a coprocessor insn for which a core nop
+             exists.  In this case, move the coprocessor insn to the
+             second element of the array and put the nop in the first
+             element then return.  Valid.
+
+         4.  The instruction is a core or coprocessor instruction for
+             which there is no matching coprocessor or core nop to use
+             to form a valid vliw insn combination.  In this case, we
+	     we have to abort.  */
+
+      /* If the insn is 64 bits long, it can run alone.  The size check
+	 is done indepependantly of whether the insn is core or copro
+	 in case 64 bit coprocessor insns are added later.  */
+      if (insn0length == 64)
+        return;
+
+      /* Insn is smaller than datapath.  If there are no matching
+	 nops for this insn, then terminate assembly.  */
+      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+				CGEN_INSN_VLIW64_NO_MATCHING_NOP))
+	as_fatal ("No valid nop.");
+
+      if (insn0iscopro)
+	{
+	  char *errmsg;
+	  mep_insn insn;
+          int i;
+
+          /* Initialize the insn buffer.  */
+          for (i = 0; i < 64; i++)
+             insn.buffer[i] = '\0';
+
+	  /* We have a coprocessor insn.  At this point in time there
+	     are is 32-bit core nop.  There is only a 16-bit core
+	     nop.  The idea is to allow for a relatively arbitrary
+	     coprocessor to be specified.  We aren't looking at
+	     trying to cover future changes in the core at this time
+	     since it is assumed that the core will remain fairly
+	     static.  If there ever are 32 or 48 bit core nops added,
+	     they will require entries below.  */
+
+	  if (insn0length == 48)
+	    {
+	      /* Move the insn and fixups to the second element of the
+		 arrays then assemble and insert a 16 bit core nop.  */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+						  & insn.fields, insn.buffer,
+						  & errmsg);
+	    }
+          else
+            {
+              /* If this is reached, then we have a single coprocessor
+                 insn that is not 48 bits long, but for which the assembler
+                 thinks there is a matching core nop.  If a 32-bit core
+                 nop has been added, then make the necessary changes and
+                 handle its assembly and insertion here.  Otherwise,
+                 go figure out why either:
+              
+                 1. The assembler thinks that there is a 32-bit core nop
+                    to match a 32-bit coprocessor insn, or
+                 2. The assembler thinks that there is a 48-bit core nop
+                    to match a 16-bit coprocessor insn.  */
+
+              as_fatal ("Assembler expects a non-existent core nop.");
+            }
+
+	 if (!insn.insn)
+	   {
+	     as_bad ("%s", errmsg);
+	     return;
+	   }
+
+         /* Move the insn in element 0 to element 1 and insert the
+            nop into element 0.  Move the fixups in element 0 to
+            element 1 and save the current fixups to element 0. 
+	    Really there aren't any fixups at this point because we're
+	    inserting a nop but we might as well be general so that
+	    if there's ever a need to insert a general insn, we'll
+	    have an example. */
+
+         saved_insns[1] = saved_insns[0];
+         saved_insns[0] = insn;
+         num_insns_saved++;
+         gas_cgen_swap_fixups(0);
+         gas_cgen_save_fixups(1);
+
+	}
+      else
+	{
+	  char * errmsg;
+	  mep_insn insn;
+          int i;
+
+          /* Initialize the insn buffer */
+          for (i = 0; i < 64; i++)
+             insn.buffer[i] = '\0';
+
+	  /* We have a core insn.  We have to handle all possible nop
+	     lengths.  If a coprocessor doesn't have a nop of a certain
+	     length but there exists core insns that when combined with
+	      a nop of that length would fill the datapath, those core
+	      insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
+	      attribute.  That will ensure that when used in a way that
+	      requires a nop to be inserted, assembly will terminate
+	      before reaching this section of code.  This guarantees
+	      that cases below which would result in the attempted
+	      insertion of nop that doesn't exist will never be entered.  */
+	  if (insn0length == 16)
+	    {
+	      /* Insert 48 bit coprocessor nop.          */
+	      /* Assemble it and put it into the arrays. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else if (insn0length == 32)
+	    {
+	      /* Insert 32 bit coprocessor nop. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else if (insn0length == 48)
+	    {
+	      /* Insert 16 bit coprocessor nop. */
+	      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+						  &insn.fields, insn.buffer,
+						  &errmsg);
+	    }
+	  else
+	    /* Core insn has an invalid length.  Something has gone wrong. */
+	    as_fatal ("Core insn has invalid length!  Something is wrong!");
+
+	  if (!insn.insn)
+	    {
+	      as_bad ("%s", errmsg);
+	      return;
+	    }
+
+	  /* Now put the insn and fixups into the arrays.  */
+	  mep_save_insn (insn);
+	}
+    }
+}
+
+/* The scheduling functions are just filters for invalid combinations.
+   If there is a violation, they terminate assembly.  Otherise they
+   just fall through.  Succesful combinations cause no side effects
+   other than valid nop insertion.  */
+
+static void
+mep_check_parallel_scheduling (void)
+{
+  /* This is where we will eventually read the config information
+     and choose which scheduling checking function to call.  */   
+  if (MEP_VLIW64)
+    mep_check_parallel64_scheduling ();
+  else
+    mep_check_parallel32_scheduling ();
+}
+
+static void
+mep_process_saved_insns (void)
+{
+  int i;
+
+  gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+  /* We have to check for valid scheduling here. */
+  mep_check_parallel_scheduling ();
+
+  /* If the last call didn't cause assembly to terminate, we have
+     a valid vliw insn/insn pair saved. Restore this instructions'
+     fixups and process the insns. */
+  for (i = 0;i<num_insns_saved;i++)
+    {
+      gas_cgen_restore_fixups (i);
+      gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
+			    CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
+			    1, NULL);
+    }
+  gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+  /* Clear the fixups and reset the number insn saved to 0. */
+  gas_cgen_initialize_saved_fixups_array ();
+  num_insns_saved = 0;
+  listing_prev_line ();
+}
+
+void
+md_assemble (char * str)
+{
+  static CGEN_BITSET* isas = NULL;
+  char * errmsg;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  /* There are two possible modes: core and vliw.  We have to assemble
+     differently for each.
+
+     Core Mode:  We assemble normally.  All instructions are on a
+                 single line and are made up of one mnemonic and one
+                 set of operands.
+     VLIW Mode:  Vliw combinations are indicated as follows:
+
+		       core insn
+		     + copro insn
+
+                 We want to handle the general case where more than
+                 one instruction can be preceeded by a +.  This will
+                 happen later if we add support for internally parallel
+                 coprocessors.  We'll make the parsing nice and general
+                 so that it can handle an arbitrary number of insns
+                 with leading +'s.  The actual checking for valid
+                 combinations is done elsewhere.  */
+
+  /* Initialize the isa to refer to the core.  */
+  if (isas == NULL)
+    isas = cgen_bitset_copy (& MEP_CORE_ISA);
+  else
+    {
+      cgen_bitset_clear (isas);
+      cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
+    }
+  gas_cgen_cpu_desc->isas = isas;
+
+  if (mode == VLIW)
+    {
+      /* VLIW mode.  */
+
+      int thisInsnIsCopro = 0;
+      mep_insn insn;
+      int i;
+      
+      /* Initialize the insn buffer */
+	
+      if (! CGEN_INT_INSN_P)
+         for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
+            insn.buffer[i]='\0';
+
+      /* Can't tell core / copro insns apart at parse time! */
+      cgen_bitset_union (isas, & MEP_COP_ISA, isas);
+
+      /* Assemble the insn so we can examine its attributes. */
+      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
+					  &insn.fields, insn.buffer,
+					  &errmsg);
+      if (!insn.insn)
+	{
+	  as_bad ("%s", errmsg);
+	  return;
+	}
+      mep_check_for_disabled_registers (&insn);
+
+      /* Check to see if it's a coprocessor instruction. */
+      thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+
+      if (!thisInsnIsCopro)
+	{
+	  insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
+						  &insn.fields, insn.buffer,
+						  insn.insn);
+	  thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+	  mep_check_for_disabled_registers (&insn);
+	}
+
+      if (pluspresent)
+	{
+	  /* A plus was present. */
+	  /* Check for a + with a core insn and abort if found. */
+	  if (!thisInsnIsCopro)
+	    {
+	      as_fatal("A core insn cannot be preceeded by a +.\n");
+	      return;
+	    }
+
+	  if (num_insns_saved > 0)
+	    {
+	      /* There are insns in the queue. Add this one. */
+	      mep_save_insn (insn);
+	    }
+	  else
+	    {
+	      /* There are no insns in the queue and a plus is present.
+		 This is a syntax error.  Let's not tolerate this.
+		 We can relax this later if necessary.  */
+	      as_bad (_("Invalid use of parallelization operator."));
+	      return;
+	    }
+	}
+      else
+	{
+	  /* No plus was present. */
+	  if (num_insns_saved > 0)
+	    {
+	      /* There are insns saved and we came across an insn without a
+		 leading +.  That's the signal to process the saved insns
+		 before proceeding then treat the current insn as the first
+		 in a new vliw group.  */
+	      mep_process_saved_insns ();
+	      num_insns_saved = 0;
+	      /* mep_save_insn (insn); */
+	    }
+	  mep_save_insn (insn);
+#if 0
+	  else
+	    {
+
+              /* Core Insn. Add it to the beginning of the queue. */
+              mep_save_insn (insn);
+	      /* gas_cgen_save_fixups(num_insns_saved); */
+	    }
+#endif
+	}
+
+      pluspresent = 0;
+    }
+  else
+    {
+      /* Core mode.  */
+
+      /* Only single instructions are assembled in core mode. */
+      mep_insn insn;
+
+      /* If a leading '+' was present, issue an error.
+	 That's not allowed in core mode. */
+      if (pluspresent)
+	{
+	  as_bad (_("Leading plus sign not allowed in core mode"));
+	  return;
+	}
+
+      insn.insn = mep_cgen_assemble_insn
+	(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+      if (!insn.insn)
+	{
+	  as_bad ("%s", errmsg);
+	  return;
+	}
+      gas_cgen_finish_insn (insn.insn, insn.buffer,
+			    CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+      mep_check_for_disabled_registers (&insn);
+    }
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Interface to relax_segment.  */
+
+
+const relax_typeS md_relax_table[] =
+{
+  /* The fields are:
+     1) most positive reach of this state,
+     2) most negative reach of this state,
+     3) how many bytes this mode will have in the variable part of the frag
+     4) which index into the table to try if we can't fit into this one.  */
+  /* Note that we use "beq" because "jmp" has a peculiarity - it cannot
+     jump to addresses with any bits 27..24 set.  So, we use beq as a
+     17-bit pc-relative branch to avoid using jmp, just in case.  */
+
+  /* 0 */ {     0,      0, 0, 0 }, /* unused */
+  /* 1 */ {     0,      0, 0, 0 }, /* marker for "don't know yet" */
+
+  /* 2 */ {  2047,  -2048, 0, 3 }, /* bsr12 */
+  /* 3 */ {     0,      0, 2, 0 }, /* bsr16 */
+
+  /* 4 */ {  2047,  -2048, 0, 5 }, /* bra */
+  /* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
+  /* 6 */ {     0,      0, 2, 0 }, /* jmp24 */
+
+  /* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
+  /* 8 */ {     0,      0, 4, 0 }, /* bnei/jmp */
+
+  /* 9 */  {   127,   -128, 0, 10 }, /* beqz */
+  /* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
+  /* 11 */ {     0,      0, 4,  0 }, /* bnei/jmp */
+
+  /* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
+  /* 13 */ {     0,      0, 4,  0 }, /* beqi/jmp */
+
+  /* 14 */ {   127,   -128, 0, 15 }, /* bnez */
+  /* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
+  /* 16 */ {     0,      0, 4,  0 },  /* beqi/jmp */
+
+  /* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
+  /* 18 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* blti */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
+  /* 20 */ {     0,      0, 4,  0 },
+  /* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
+  /* 20 */ {     0,      0, 4,  0 }
+};
+
+/* Pseudo-values for 64 bit "insns" which are combinations of two 32
+   bit insns.  */
+typedef enum {
+  MEP_PSEUDO64_NONE,
+  MEP_PSEUDO64_16BITCC,
+  MEP_PSEUDO64_32BITCC,
+} MepPseudo64Values;
+
+static struct {
+  int insn;
+  int growth;
+  int insn_for_extern;
+} subtype_mappings[] = {
+  { 0, 0, 0 },
+  { 0, 0, 0 },
+  { MEP_INSN_BSR12, 0, MEP_INSN_BSR24 },
+  { MEP_INSN_BSR24, 2, MEP_INSN_BSR24 },
+  { MEP_INSN_BRA,   0, MEP_INSN_BRA   },
+  { MEP_INSN_BEQ,   2, MEP_INSN_BEQ   },
+  { MEP_INSN_JMP,   2, MEP_INSN_JMP   },
+  { MEP_INSN_BEQI,  0, MEP_INSN_BEQI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BEQZ,  0, MEP_INSN_BEQZ  },
+  { MEP_INSN_BEQI,  2, MEP_INSN_BEQI  },
+  { -1,             4, MEP_PSEUDO64_16BITCC },
+  { MEP_INSN_BNEI,  0, MEP_INSN_BNEI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BNEZ,  0, MEP_INSN_BNEZ  },
+  { MEP_INSN_BNEI,  2, MEP_INSN_BNEI  },
+  { -1,             4, MEP_PSEUDO64_16BITCC },
+  { MEP_INSN_BGEI,  0, MEP_INSN_BGEI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BLTI,  0, MEP_INSN_BLTI  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPEQ, 0, MEP_INSN_BCPEQ  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPNE, 0, MEP_INSN_BCPNE  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPAT, 0, MEP_INSN_BCPAT  },
+  { -1,             4, MEP_PSEUDO64_32BITCC },
+  { MEP_INSN_BCPAF, 0, MEP_INSN_BCPAF  },
+  { -1,             4, MEP_PSEUDO64_32BITCC }
+};
+#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
+
+void
+mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
+{
+  symbolS *symbolP = fragP->fr_symbol;
+  if (symbolP && !S_IS_DEFINED (symbolP))
+    *aim = 0;
+  /* Adjust for MeP pcrel not being relative to the next opcode.  */
+  *aim += 2 + md_relax_table[this_state].rlx_length;
+}
+
+static int
+insn_to_subtype (int insn)
+{
+  unsigned int i;
+  for (i=0; i<NUM_MAPPINGS; i++)
+    if (insn == subtype_mappings[i].insn)
+      return i;
+  abort ();
+}
+
+/* Return an initial guess of the length by which a fragment must grow
+   to hold a branch to reach its destination.  Also updates fr_type
+   and fr_subtype as necessary.
+
+   Called just before doing relaxation.  Any symbol that is now
+   undefined will not become defined.  The guess for fr_var is
+   ACTUALLY the growth beyond fr_fix.  Whatever we do to grow fr_fix
+   or fr_var contributes to our returned value.  Although it may not
+   be explicit in the frag, pretend fr_var starts with a 0 value.  */
+
+int
+md_estimate_size_before_relax (fragS * fragP, segT segment)
+{
+  if (fragP->fr_subtype == 1)
+    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
+    {
+      int new_insn;
+
+      new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
+      fragP->fr_subtype = insn_to_subtype (new_insn);
+    }
+
+  if (MEP_VLIW && ! MEP_VLIW64
+      && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
+    {
+      /* Use 32 bit branches for vliw32 so the vliw word is not split.  */
+      switch (fragP->fr_cgen.insn->base->num)
+	{
+	case MEP_INSN_BSR12:
+	  fragP->fr_subtype = insn_to_subtype 
+	    (subtype_mappings[fragP->fr_subtype].insn_for_extern);
+	  break;
+	case MEP_INSN_BEQZ:
+	  fragP->fr_subtype ++;
+	  break;
+	case MEP_INSN_BNEZ:
+	  fragP->fr_subtype ++;
+	  break;
+	}
+    }
+
+  if (fragP->fr_cgen.insn->base
+      && fragP->fr_cgen.insn->base->num
+         != subtype_mappings[fragP->fr_subtype].insn)
+    {
+      int new_insn= subtype_mappings[fragP->fr_subtype].insn;
+      if (new_insn != -1)
+	{
+	  fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+				 - fragP->fr_cgen.insn->base->num
+				 + new_insn);
+	}
+    }
+
+  return subtype_mappings[fragP->fr_subtype].growth;
+}
+
+/* *fragP has been relaxed to its final size, and now needs to have
+   the bytes inside it modified to conform to the new size.
+
+   Called after relaxation is finished.
+   fragP->fr_type == rs_machine_dependent.
+   fragP->fr_subtype is the subtype of what the address relaxed to.  */
+
+static int
+target_address_for (fragS *frag)
+{
+  int rv = frag->fr_offset;
+  symbolS *sym = frag->fr_symbol;
+
+  if (sym)
+    rv += S_GET_VALUE (sym);
+
+  return rv;
+}
+
+void
+md_convert_frag (bfd *abfd  ATTRIBUTE_UNUSED, 
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
+{
+  int addend, rn, bit = 0;
+  int operand;
+  int where = fragP->fr_opcode - fragP->fr_literal;
+  int e = target_big_endian ? 0 : 1;
+
+  addend = target_address_for (fragP) - (fragP->fr_address + where);
+
+  if (subtype_mappings[fragP->fr_subtype].insn == -1)
+    {
+      fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+      switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
+	{
+	case MEP_PSEUDO64_16BITCC:
+	  fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
+	  fragP->fr_opcode[2^e] = 0xd8;
+	  fragP->fr_opcode[3^e] = 0x08;
+	  fragP->fr_opcode[4^e] = 0;
+	  fragP->fr_opcode[5^e] = 0;
+	  where += 2;
+	  break;
+	case MEP_PSEUDO64_32BITCC:
+	  if (fragP->fr_opcode[0^e] & 0x10)
+	    fragP->fr_opcode[1^e] ^= 0x01;
+	  else
+	    fragP->fr_opcode[1^e] ^= 0x04;
+	  fragP->fr_opcode[2^e] = 0;
+	  fragP->fr_opcode[3^e] = 4;
+	  fragP->fr_opcode[4^e] = 0xd8;
+	  fragP->fr_opcode[5^e] = 0x08;
+	  fragP->fr_opcode[6^e] = 0;
+	  fragP->fr_opcode[7^e] = 0;
+	  where += 4;
+	  break;
+	default:
+	  abort ();
+	}
+      fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+			     - fragP->fr_cgen.insn->base->num
+			     + MEP_INSN_JMP);
+      operand = MEP_OPERAND_PCABS24A2;
+    }
+  else
+    switch (fragP->fr_cgen.insn->base->num)
+      {
+      case MEP_INSN_BSR12:
+	fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+	fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL12A2;
+	break;
+
+      case MEP_INSN_BSR24:
+	fragP->fr_fix += 2;
+	fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+	fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+	operand = MEP_OPERAND_PCREL24A2;
+	break;
+
+      case MEP_INSN_BRA:
+	fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+	fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL12A2;
+	break;
+
+      case MEP_INSN_BEQ:
+	/* The default relax_frag doesn't change the state if there is no
+	   growth, so we must manually handle converting out-of-range BEQ
+	   instructions to JMP.  */
+	if (addend <= 65535 && addend >= -65536)
+	  {
+	    fragP->fr_fix += 2;
+	    fragP->fr_opcode[0^e] = 0xe0;
+	    fragP->fr_opcode[1^e] = 0x01;
+	    fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+	    fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+	    operand = MEP_OPERAND_PCREL17A2;
+	    break;
+	  }
+	/* ...FALLTHROUGH... */
+
+      case MEP_INSN_JMP:
+	addend = target_address_for (fragP);
+	fragP->fr_fix += 2;
+	fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+	fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+	operand = MEP_OPERAND_PCABS24A2;
+	break;
+
+      case MEP_INSN_BNEZ:
+	bit = 1;
+      case MEP_INSN_BEQZ:
+	fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
+	operand = MEP_OPERAND_PCREL8A2;
+	break;
+
+      case MEP_INSN_BNEI:
+	bit = 4;
+      case MEP_INSN_BEQI:
+	if (subtype_mappings[fragP->fr_subtype].growth)
+	  {
+	    fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+	    rn = fragP->fr_opcode[0^e] & 0x0f;
+	    fragP->fr_opcode[0^e] = 0xe0 | rn;
+	    fragP->fr_opcode[1^e] = bit;
+	  }
+	fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+	fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+	operand = MEP_OPERAND_PCREL17A2;
+	break;
+
+      case MEP_INSN_BLTI:
+      case MEP_INSN_BGEI:
+      case MEP_INSN_BCPEQ:
+      case MEP_INSN_BCPNE:
+      case MEP_INSN_BCPAT:
+      case MEP_INSN_BCPAF:
+	/* No opcode change needed, just operand.  */
+	fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
+	fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
+	operand = MEP_OPERAND_PCREL17A2;
+	break;
+
+      default:
+	abort ();
+      }
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+      || operand == MEP_OPERAND_PCABS24A2)
+    {
+      assert (fragP->fr_cgen.insn != 0);
+      gas_cgen_record_fixup (fragP,
+			     where,
+			     fragP->fr_cgen.insn,
+			     (fragP->fr_fix - where) * 8,
+			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+							 operand),
+			     fragP->fr_cgen.opinfo,
+			     fragP->fr_symbol, fragP->fr_offset);
+    }
+}
+
+
+/* Functions concerning relocs.  */
+
+void
+mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  /* If we already know the fixup value, adjust it in the same
+     way that the linker would have done.  */
+  if (fixP->fx_addsy == 0)
+    switch (fixP->fx_cgen.opinfo)
+      {
+      case BFD_RELOC_MEP_LOW16:
+	*valP = ((long)(*valP & 0xffff)) << 16 >> 16;
+	break;
+      case BFD_RELOC_MEP_HI16U:
+	*valP >>= 16;
+	break;
+      case BFD_RELOC_MEP_HI16S:
+	*valP = (*valP + 0x8000) >> 16;
+	break;
+      }
+
+  /* Now call cgen's md_aply_fix.  */
+  gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (! S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
+
+  /* Return the address of the opcode - cgen adjusts for opcode size
+     itself, to be consistent with the disassembler, which must do
+     so.  */
+  return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
+#else
+#define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
+#endif
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND *operand,
+		      fixS *fixP)
+{
+  enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
+  static char printed[MEP_OPERAND_MAX] = { 0 };
+
+  /* If there's a reloc here, it's because the parser saw a %foo() and
+     is giving us the correct reloc to use, or because we converted to
+     a different size reloc below and want to avoid "converting" more
+     than once.  */
+  if (reloc && reloc != BFD_RELOC_NONE)
+    return reloc;
+
+  switch (operand->type)
+    {
+      MAP (PCREL8A2);	/* beqz */
+      MAP (PCREL12A2);	/* bsr16 */
+      MAP (PCREL17A2);	/* beqi */
+      MAP (PCREL24A2);	/* bsr24 */
+      MAP (PCABS24A2);	/* jmp */
+      MAP (UIMM24);	/* mov */
+      MAP (ADDR24A4);	/* sw/lw */
+
+    /* The rest of the relocs should be generated by the parser,
+       for things such as %tprel(), etc. */
+    case MEP_OPERAND_SIMM16:
+#ifdef OBJ_COMPLEX_RELC
+      /* coalescing this into RELOC_MEP_16 is actually a bug,
+	 since it's a signed operand. let the relc code handle it. */
+      return BFD_RELOC_RELC; 
+#endif
+
+    case MEP_OPERAND_UIMM16:
+    case MEP_OPERAND_SDISP16:
+    case MEP_OPERAND_CODE16:
+      fixP->fx_where += 2;
+      /* to avoid doing the above add twice */
+      fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
+      return BFD_RELOC_MEP_16;
+
+    default:
+#ifdef OBJ_COMPLEX_RELC
+      /* this is not an error, yet. 
+	 pass it to the linker. */
+      return BFD_RELOC_RELC;
+#endif
+      if (printed[operand->type])
+	return BFD_RELOC_NONE;
+      printed[operand->type] = 1;
+
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("Don't know how to relocate plain operands of type %s"),
+		    operand->name);
+
+      /* Print some helpful hints for the user.  */
+      switch (operand->type)
+	{
+	case MEP_OPERAND_UDISP7:
+	case MEP_OPERAND_UDISP7A2:
+	case MEP_OPERAND_UDISP7A4:
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("Perhaps you are missing %%tpoff()?"));
+	  break;
+	default:
+	  break;
+	}
+      return BFD_RELOC_NONE;
+    }
+}
+
+/* Called while parsing an instruction to create a fixup.
+   We need to check for HI16 relocs and queue them up for later sorting.  */
+
+fixS *
+mep_cgen_record_fixup_exp (fragS *frag,
+			   int where,
+			   const CGEN_INSN *insn,
+			   int length,
+			   const CGEN_OPERAND *operand,
+			   int opinfo,
+			   expressionS *exp)
+{
+  fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
+					   operand, opinfo, exp);
+  return fixP;
+}
+
+/* Return BFD reloc type from opinfo field in a fixS.
+   It's tricky using fx_r_type in mep_frob_file because the values
+   are BFD_RELOC_UNUSED + operand number.  */
+#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
+
+/* Sort any unmatched HI16 relocs so that they immediately precede
+   the corresponding LO16 reloc.  This is called before md_apply_fix and
+   tc_gen_reloc.  */
+
+void
+mep_frob_file ()
+{
+  struct mep_hi_fixup * l;
+
+  for (l = mep_hi_fixup_list; l != NULL; l = l->next)
+    {
+      segment_info_type * seginfo;
+      int pass;
+
+      assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
+	      || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
+
+      /* Check quickly whether the next fixup happens to be a matching low.  */
+      if (l->fixp->fx_next != NULL
+	  && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
+	  && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
+	  && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
+	continue;
+
+      /* Look through the fixups for this segment for a matching
+         `low'.  When we find one, move the high just in front of it.
+         We do this in two passes.  In the first pass, we try to find
+         a unique `low'.  In the second pass, we permit multiple
+         high's relocs for a single `low'.  */
+      seginfo = seg_info (l->seg);
+      for (pass = 0; pass < 2; pass++)
+	{
+	  fixS * f;
+	  fixS * prev;
+
+	  prev = NULL;
+	  for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
+	    {
+	      /* Check whether this is a `low' fixup which matches l->fixp.  */
+	      if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
+		  && f->fx_addsy == l->fixp->fx_addsy
+		  && f->fx_offset == l->fixp->fx_offset
+		  && (pass == 1
+		      || prev == NULL
+		      || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
+		      || prev->fx_addsy != f->fx_addsy
+		      || prev->fx_offset !=  f->fx_offset))
+		{
+		  fixS ** pf;
+
+		  /* Move l->fixp before f.  */
+		  for (pf = &seginfo->fix_root;
+		       * pf != l->fixp;
+		       pf = & (* pf)->fx_next)
+		    assert (* pf != NULL);
+
+		  * pf = l->fixp->fx_next;
+
+		  l->fixp->fx_next = f;
+		  if (prev == NULL)
+		    seginfo->fix_root = l->fixp;
+		  else
+		    prev->fx_next = l->fixp;
+
+		  break;
+		}
+
+	      prev = f;
+	    }
+
+	  if (f != NULL)
+	    break;
+
+	  if (pass == 1)
+	    as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
+			   _("Unmatched high relocation"));
+	}
+    }
+}
+
+/* See whether we need to force a relocation into the output file. */
+
+int
+mep_force_relocation (fixS *fixp)
+{
+  if (   fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+	 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    return 1;
+
+  /* Allow branches to global symbols to be resolved at assembly time.
+     This is consistent with way relaxable branches are handled, since
+     branches to both global and local symbols are relaxed.  It also
+     corresponds to the assumptions made in md_pcrel_from_section.  */
+  return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type type, and store the appropriate bytes in *litP.  The number
+   of LITTLENUMS emitted is stored in *sizeP .  An error message is
+   returned, or NULL on OK. */
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int              i;
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  for (i = 0; i < prec; i++)
+    {
+      md_number_to_chars (litP, (valueT) words[i],
+			  sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+
+bfd_boolean
+mep_fix_adjustable (fixS *fixP)
+{
+  bfd_reloc_code_real_type reloc_type;
+
+  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+    {
+      const CGEN_INSN *insn = NULL;
+      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+      const CGEN_OPERAND *operand
+	= cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+    }
+  else
+    reloc_type = fixP->fx_r_type;
+
+  if (fixP->fx_addsy == NULL)
+    return 1;
+
+  /* Prevent all adjustments to global symbols. */
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
+    return 0;
+
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return 0;
+
+  /* We need the symbol name for the VTABLE entries */
+  if (reloc_type == BFD_RELOC_VTABLE_INHERIT
+      || reloc_type == BFD_RELOC_VTABLE_ENTRY)
+    return 0;
+
+  return 1;
+}
+
+int
+mep_elf_section_letter (int letter, char **ptrmsg)
+{
+  if (letter == 'v')
+    return SHF_MEP_VLIW;
+
+  *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
+  return 0;
+}
+
+flagword
+mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
+{
+  if (attr & SHF_MEP_VLIW)
+    flags |= SEC_MEP_VLIW;
+  return flags;
+}
+
+/* In vliw mode, the default section is .vtext.  We have to be able
+   to switch into .vtext using only the .vtext directive.  */
+
+static segT
+mep_vtext_section (void)
+{
+  static segT vtext_section;
+
+  if (! vtext_section)
+    {
+      flagword applicable = bfd_applicable_section_flags (stdoutput);
+      vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
+      bfd_set_section_flags (stdoutput, vtext_section,
+			     applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
+					   | SEC_CODE | SEC_READONLY
+					   | SEC_MEP_VLIW));
+    }
+
+  return vtext_section;
+}
+
+static void
+mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
+{
+  int temp;
+
+  /* Record previous_section and previous_subsection.  */
+  obj_elf_section_change_hook ();
+
+  temp = get_absolute_expression ();
+  subseg_set (mep_vtext_section (), (subsegT) temp);
+  demand_empty_rest_of_line ();
+}
+
+static void
+mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
+{
+  mep_process_saved_insns ();
+  pluspresent = 0;
+  mode = CORE;
+}
+
+static void
+mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
+{
+  if (! MEP_VLIW)
+    as_bad (_(".vliw unavailable when VLIW is disabled."));
+  mode = VLIW;
+  /* Switch into .vtext here too. */
+  /* mep_s_vtext(); */
+}
+
+/* This is an undocumented pseudo-op used to disable gas's
+   "disabled_registers" check.  Used for code which checks for those
+   registers at runtime.  */
+static void
+mep_noregerr (int i ATTRIBUTE_UNUSED)
+{
+  allow_disabled_registers = 1;
+}
+
+/* mep_unrecognized_line: This is called when a line that can't be parsed
+   is encountered.  We use it to check for a leading '+' sign which indicates
+   that the current instruction is a coprocessor instruction that is to be
+   parallelized with a previous core insn.  This function accepts the '+' and
+   rejects all other characters that might indicate garbage at the beginning
+   of the line.  The '+' character gets lost as the calling loop continues,
+   so we need to indicate that we saw it.  */
+
+int
+mep_unrecognized_line (int ch)
+{
+  switch (ch)
+    {
+    case '+':
+      pluspresent = 1;
+      return 1; /* '+' indicates an instruction to be parallelized. */
+    default:
+      return 0; /* If it's not a '+', the line can't be parsed. */
+    }
+}
+
+void
+mep_cleanup (void)
+{
+  /* Take care of any insns left to be parallelized when the file ends.
+     This is mainly here to handle the case where the file ends with an
+     insn preceeded by a + or the file ends unexpectedly.  */
+  if (mode == VLIW)
+    mep_process_saved_insns ();
+}
+
+int
+mep_flush_pending_output (void)
+{
+  if (mode == VLIW)
+    {
+      mep_process_saved_insns ();
+      pluspresent = 0;
+    }
+
+  return 1; 
+}
diff --git a/gas/config/tc-mep.h b/gas/config/tc-mep.h
new file mode 100644
index 000000000000..1d48bd4c9a4a
--- /dev/null
+++ b/gas/config/tc-mep.h
@@ -0,0 +1,119 @@
+/* tc-mep.h -- Header file for tc-mep.c.
+   Copyright (C) 2001, 2002, 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA. */
+
+#define TC_MEP
+
+/* Support computed relocations.  */
+#define OBJ_COMPLEX_RELC
+
+/* Support many operands per instruction.  */
+#define GAS_CGEN_MAX_FIXUPS 10
+
+#define LISTING_HEADER "MEP GAS "
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH bfd_arch_mep
+
+#define TARGET_FORMAT (target_big_endian ? "elf32-mep" : "elf32-mep-little")
+
+/* This is the default.  */
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely.  */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define MD_APPLY_FIX
+#define md_apply_fix mep_apply_fix
+extern void mep_apply_fix (struct fix *, valueT *, segT);
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define tc_frob_file() mep_frob_file ()
+extern void mep_frob_file (void);
+
+#define tc_fix_adjustable(fixP) mep_fix_adjustable (fixP)
+extern bfd_boolean mep_fix_adjustable (struct fix *);
+
+/* After creating a fixup for an instruction operand, we need
+   to check for HI16 relocs and queue them up for later sorting.  */
+#define md_cgen_record_fixup_exp  mep_cgen_record_fixup_exp
+
+/* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
+#define TC_FORCE_RELOCATION(fix) mep_force_relocation (fix)
+extern int mep_force_relocation (struct fix *);
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+extern void gas_cgen_md_operand (expressionS *);
+#define md_operand(x) gas_cgen_md_operand (x)
+
+#define md_flush_pending_output() mep_flush_pending_output()
+extern int mep_flush_pending_output(void);
+
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* Account for inserting a jmp after the insn.  */
+#define TC_CGEN_MAX_RELAX(insn, len) ((len) + 4)
+
+extern void mep_prepare_relax_scan (fragS *, offsetT *, relax_substateT);
+#define md_prepare_relax_scan(FRAGP, ADDR, AIM, STATE, TYPE) \
+	mep_prepare_relax_scan (FRAGP, &AIM, STATE)
+
+#define skip_whitespace(str) while (*(str) == ' ') ++(str)
+
+/* Support for core/vliw mode switching.  */
+#define CORE 0
+#define VLIW 1
+#define MAX_PARALLEL_INSNS 56 /* From email from Toshiba.  */
+#define VTEXT_SECTION_NAME ".vtext"
+
+/* Needed to process pending instructions when a label is encountered.  */
+#define TC_START_LABEL(ch, ptr)    ((ch == ':') && mep_flush_pending_output ())
+
+#define tc_unrecognized_line(c) mep_unrecognized_line (c)
+extern int mep_unrecognized_line (int);
+#define md_cleanup mep_cleanup
+extern void mep_cleanup (void);
+
+#define md_elf_section_letter		mep_elf_section_letter
+extern int mep_elf_section_letter (int, char **);
+#define md_elf_section_flags		mep_elf_section_flags
+extern flagword mep_elf_section_flags  (flagword, int, int);
+
+#define ELF_TC_SPECIAL_SECTIONS \
+  { VTEXT_SECTION_NAME, SHT_PROGBITS, SHF_ALLOC|SHF_EXECINSTR|SHF_MEP_VLIW },
+
+/* The values of the following enum are for use with parinsnum, which 
+   is a variable in md_assemble that keeps track of whether or not the
+   next instruction is expected to be the first or second instrucion in
+   a parallelization group.  */
+typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN;
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index c885205dad47..c2867bec72b0 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
 /* tc-mips.c -- assemble code for a MIPS chip.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
@@ -28,8 +28,6 @@
 #include "subsegs.h"
 #include "safe-ctype.h"
 
-#include <stdarg.h>
-
 #include "opcode/mips.h"
 #include "itbl-ops.h"
 #include "dwarf2dbg.h"
@@ -150,7 +148,7 @@ struct mips_cl_insn
   /* True if this entry cannot be moved from its current position.  */
   unsigned int fixed_p : 1;
 
-  /* True if this instruction occured in a .set noreorder block.  */
+  /* True if this instruction occurred in a .set noreorder block.  */
   unsigned int noreorder_p : 1;
 
   /* True for mips16 instructions that jump to an absolute address.  */
@@ -193,7 +191,9 @@ struct mips_set_options
      command line options, and based on the default architecture.  */
   int ase_mips3d;
   int ase_mdmx;
+  int ase_smartmips;
   int ase_dsp;
+  int ase_dspr2;
   int ase_mt;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
@@ -245,7 +245,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
+  ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -261,6 +261,11 @@ static int file_mips_isa = ISA_UNKNOWN;
    command line (e.g., by -march).  */
 static int file_ase_mips16;
 
+#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32		\
+			      || mips_opts.isa == ISA_MIPS32R2		\
+			      || mips_opts.isa == ISA_MIPS64		\
+			      || mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mips3d was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mips3d;
@@ -269,14 +274,36 @@ static int file_ase_mips3d;
    command line (e.g., by -march).  */
 static int file_ase_mdmx;
 
+/* True if -msmartmips was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_smartmips;
+
+#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32		\
+				|| mips_opts.isa == ISA_MIPS32R2)
+
 /* True if -mdsp was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_dsp;
 
+#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			      || mips_opts.isa == ISA_MIPS64R2)
+
+#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
+
+/* True if -mdspr2 was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_dspr2;
+
+#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			        || mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
 
+#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			     || mips_opts.isa == ISA_MIPS64R2)
+
 /* The argument of the -march= flag.  The architecture we are assembling.  */
 static int file_mips_arch = CPU_UNKNOWN;
 static const char *mips_arch_string;
@@ -293,41 +320,61 @@ static int mips_32bitmode = 0;
 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
 
 /* Likewise 64-bit registers.  */
-#define ABI_NEEDS_64BIT_REGS(ABI) \
-  ((ABI) == N32_ABI 		  \
-   || (ABI) == N64_ABI		  \
+#define ABI_NEEDS_64BIT_REGS(ABI)	\
+  ((ABI) == N32_ABI 			\
+   || (ABI) == N64_ABI			\
    || (ABI) == O64_ABI)
 
-/*  Return true if ISA supports 64 bit gp register instructions.  */
-#define ISA_HAS_64BIT_REGS(ISA) (    \
-   (ISA) == ISA_MIPS3                \
-   || (ISA) == ISA_MIPS4             \
-   || (ISA) == ISA_MIPS5             \
-   || (ISA) == ISA_MIPS64            \
-   || (ISA) == ISA_MIPS64R2          \
-   )
+/*  Return true if ISA supports 64 bit wide gp registers.  */
+#define ISA_HAS_64BIT_REGS(ISA)		\
+  ((ISA) == ISA_MIPS3			\
+   || (ISA) == ISA_MIPS4		\
+   || (ISA) == ISA_MIPS5		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
+
+/*  Return true if ISA supports 64 bit wide float registers.  */
+#define ISA_HAS_64BIT_FPRS(ISA)		\
+  ((ISA) == ISA_MIPS3			\
+   || (ISA) == ISA_MIPS4		\
+   || (ISA) == ISA_MIPS5		\
+   || (ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
 
 /* Return true if ISA supports 64-bit right rotate (dror et al.)
    instructions.  */
-#define ISA_HAS_DROR(ISA) (	\
-   (ISA) == ISA_MIPS64R2	\
-   )
+#define ISA_HAS_DROR(ISA)		\
+  ((ISA) == ISA_MIPS64R2)
 
 /* Return true if ISA supports 32-bit right rotate (ror et al.)
    instructions.  */
-#define ISA_HAS_ROR(ISA) (	\
-   (ISA) == ISA_MIPS32R2	\
-   || (ISA) == ISA_MIPS64R2	\
-   )
+#define ISA_HAS_ROR(ISA)		\
+  ((ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64R2		\
+   || mips_opts.ase_smartmips)
+
+/* Return true if ISA supports single-precision floats in odd registers.  */
+#define ISA_HAS_ODD_SINGLE_FPR(ISA)	\
+  ((ISA) == ISA_MIPS32			\
+   || (ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64		\
+   || (ISA) == ISA_MIPS64R2)
+
+/* Return true if ISA supports move to/from high part of a 64-bit
+   floating-point register. */
+#define ISA_HAS_MXHC1(ISA)		\
+  ((ISA) == ISA_MIPS32R2		\
+   || (ISA) == ISA_MIPS64R2)
 
 #define HAVE_32BIT_GPRS		                   \
-    (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+    (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
 
 #define HAVE_32BIT_FPRS                            \
-    (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
+    (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
 
-#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
-#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
+#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
+#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
 
 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
 
@@ -367,22 +414,6 @@ static int mips_32bitmode = 0;
    (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0		\
     || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
 
-/* Return true if the given CPU supports the MIPS3D ASE.  */
-#define CPU_HAS_MIPS3D(cpu)	((cpu) == CPU_SB1      \
-				 )
-
-/* Return true if the given CPU supports the MDMX ASE.  */
-#define CPU_HAS_MDMX(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the DSP ASE.  */
-#define CPU_HAS_DSP(cpu)	(FALSE                 \
-				 )
-
-/* Return true if the given CPU supports the MT ASE.  */
-#define CPU_HAS_MT(cpu)		(FALSE                 \
-				 )
-
 /* True if CPU has a dror instruction.  */
 #define CPU_HAS_DROR(CPU)	((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
 
@@ -476,7 +507,7 @@ static int mips_any_noreorder;
    an mfhi/mflo instruction is read in the next two instructions.  */
 static int mips_7000_hilo_fix;
 
-/* The size of the small data section.  */
+/* The size of objects in the small data section.  */
 static unsigned int g_switch_value = 8;
 /* Whether the -G option was used.  */
 static int g_switch_seen = 0;
@@ -993,6 +1024,8 @@ static void s_cpsetup (int);
 static void s_cplocal (int);
 static void s_cprestore (int);
 static void s_cpreturn (int);
+static void s_dtprelword (int);
+static void s_dtpreldword (int);
 static void s_gpvalue (int);
 static void s_gpword (int);
 static void s_gpdword (int);
@@ -1018,11 +1051,19 @@ static int validate_mips_insn (const struct mips_opcode *);
 struct mips_cpu_info
 {
   const char *name;           /* CPU or ISA name.  */
-  int is_isa;                 /* Is this an ISA?  (If 0, a CPU.) */
+  int flags;                  /* ASEs available, or ISA flag.  */
   int isa;                    /* ISA level.  */
   int cpu;                    /* CPU number (default CPU if ISA).  */
 };
 
+#define MIPS_CPU_IS_ISA		0x0001	/* Is this an ISA?  (If 0, a CPU.) */
+#define MIPS_CPU_ASE_SMARTMIPS	0x0002	/* CPU implements SmartMIPS ASE */
+#define MIPS_CPU_ASE_DSP	0x0004	/* CPU implements DSP ASE */
+#define MIPS_CPU_ASE_MT		0x0008	/* CPU implements MT ASE */
+#define MIPS_CPU_ASE_MIPS3D	0x0010	/* CPU implements MIPS-3D ASE */
+#define MIPS_CPU_ASE_MDMX	0x0020	/* CPU implements MDMX ASE */
+#define MIPS_CPU_ASE_DSPR2	0x0040	/* CPU implements DSP R2 ASE */
+
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
@@ -1042,8 +1083,7 @@ static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
    The following pseudo-ops from the Kane and Heinrich MIPS book are
    not MIPS CPU specific, but are also not specific to the object file
    format.  This file is probably the best place to define them, but
-   they are not currently supported: .asm0, .endr, .lab, .repeat,
-   .struct.  */
+   they are not currently supported: .asm0, .endr, .lab, .struct.  */
 
 static const pseudo_typeS mips_pseudo_table[] =
 {
@@ -1059,6 +1099,8 @@ static const pseudo_typeS mips_pseudo_table[] =
   {"cplocal", s_cplocal, 0},
   {"cprestore", s_cprestore, 0},
   {"cpreturn", s_cpreturn, 0},
+  {"dtprelword", s_dtprelword, 0},
+  {"dtpreldword", s_dtpreldword, 0},
   {"gpvalue", s_gpvalue, 0},
   {"gpword", s_gpword, 0},
   {"gpdword", s_gpdword, 0},
@@ -1073,6 +1115,8 @@ static const pseudo_typeS mips_pseudo_table[] =
   {"half", s_cons, 1},
   {"dword", s_cons, 3},
   {"weakext", s_mips_weakext, 0},
+  {"origin", s_org, 0},
+  {"repeat", s_rept, 0},
 
   /* These pseudo-ops are defined in read.c, but must be overridden
      here for one reason or another.  */
@@ -1136,8 +1180,8 @@ struct insn_label_list
   symbolS *label;
 };
 
-static struct insn_label_list *insn_labels;
 static struct insn_label_list *free_insn_labels;
+#define label_list tc_segment_info_data
 
 static void mips_clear_insn_labels (void);
 
@@ -1145,12 +1189,19 @@ static inline void
 mips_clear_insn_labels (void)
 {
   register struct insn_label_list **pl;
+  segment_info_type *si;
 
-  for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
-    ;
-  *pl = insn_labels;
-  insn_labels = NULL;
+  if (now_seg)
+    {
+      for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
+	;
+      
+      si = seg_info (now_seg);
+      *pl = si->label_list;
+      si->label_list = NULL;
+    }
 }
+
 
 static char *expr_end;
 
@@ -1393,13 +1444,302 @@ init_vr4120_conflicts (void)
 #undef CONFLICT
 }
 
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc. that the MD part of the assembler will need.  */
+struct regname {
+  const char *name;
+  unsigned int num;
+};
+
+#define RTYPE_MASK	0x1ff00
+#define RTYPE_NUM	0x00100
+#define RTYPE_FPU	0x00200
+#define RTYPE_FCC	0x00400
+#define RTYPE_VEC	0x00800
+#define RTYPE_GP	0x01000
+#define RTYPE_CP0	0x02000
+#define RTYPE_PC	0x04000
+#define RTYPE_ACC	0x08000
+#define RTYPE_CCC	0x10000
+#define RNUM_MASK	0x000ff
+#define RWARN		0x80000
+
+#define GENERIC_REGISTER_NUMBERS \
+    {"$0",	RTYPE_NUM | 0},  \
+    {"$1",	RTYPE_NUM | 1},  \
+    {"$2",	RTYPE_NUM | 2},  \
+    {"$3",	RTYPE_NUM | 3},  \
+    {"$4",	RTYPE_NUM | 4},  \
+    {"$5",	RTYPE_NUM | 5},  \
+    {"$6",	RTYPE_NUM | 6},  \
+    {"$7",	RTYPE_NUM | 7},  \
+    {"$8",	RTYPE_NUM | 8},  \
+    {"$9",	RTYPE_NUM | 9},  \
+    {"$10",	RTYPE_NUM | 10}, \
+    {"$11",	RTYPE_NUM | 11}, \
+    {"$12",	RTYPE_NUM | 12}, \
+    {"$13",	RTYPE_NUM | 13}, \
+    {"$14",	RTYPE_NUM | 14}, \
+    {"$15",	RTYPE_NUM | 15}, \
+    {"$16",	RTYPE_NUM | 16}, \
+    {"$17",	RTYPE_NUM | 17}, \
+    {"$18",	RTYPE_NUM | 18}, \
+    {"$19",	RTYPE_NUM | 19}, \
+    {"$20",	RTYPE_NUM | 20}, \
+    {"$21",	RTYPE_NUM | 21}, \
+    {"$22",	RTYPE_NUM | 22}, \
+    {"$23",	RTYPE_NUM | 23}, \
+    {"$24",	RTYPE_NUM | 24}, \
+    {"$25",	RTYPE_NUM | 25}, \
+    {"$26",	RTYPE_NUM | 26}, \
+    {"$27",	RTYPE_NUM | 27}, \
+    {"$28",	RTYPE_NUM | 28}, \
+    {"$29",	RTYPE_NUM | 29}, \
+    {"$30",	RTYPE_NUM | 30}, \
+    {"$31",	RTYPE_NUM | 31} 
+
+#define FPU_REGISTER_NAMES       \
+    {"$f0",	RTYPE_FPU | 0},  \
+    {"$f1",	RTYPE_FPU | 1},  \
+    {"$f2",	RTYPE_FPU | 2},  \
+    {"$f3",	RTYPE_FPU | 3},  \
+    {"$f4",	RTYPE_FPU | 4},  \
+    {"$f5",	RTYPE_FPU | 5},  \
+    {"$f6",	RTYPE_FPU | 6},  \
+    {"$f7",	RTYPE_FPU | 7},  \
+    {"$f8",	RTYPE_FPU | 8},  \
+    {"$f9",	RTYPE_FPU | 9},  \
+    {"$f10",	RTYPE_FPU | 10}, \
+    {"$f11",	RTYPE_FPU | 11}, \
+    {"$f12",	RTYPE_FPU | 12}, \
+    {"$f13",	RTYPE_FPU | 13}, \
+    {"$f14",	RTYPE_FPU | 14}, \
+    {"$f15",	RTYPE_FPU | 15}, \
+    {"$f16",	RTYPE_FPU | 16}, \
+    {"$f17",	RTYPE_FPU | 17}, \
+    {"$f18",	RTYPE_FPU | 18}, \
+    {"$f19",	RTYPE_FPU | 19}, \
+    {"$f20",	RTYPE_FPU | 20}, \
+    {"$f21",	RTYPE_FPU | 21}, \
+    {"$f22",	RTYPE_FPU | 22}, \
+    {"$f23",	RTYPE_FPU | 23}, \
+    {"$f24",	RTYPE_FPU | 24}, \
+    {"$f25",	RTYPE_FPU | 25}, \
+    {"$f26",	RTYPE_FPU | 26}, \
+    {"$f27",	RTYPE_FPU | 27}, \
+    {"$f28",	RTYPE_FPU | 28}, \
+    {"$f29",	RTYPE_FPU | 29}, \
+    {"$f30",	RTYPE_FPU | 30}, \
+    {"$f31",	RTYPE_FPU | 31}
+
+#define FPU_CONDITION_CODE_NAMES \
+    {"$fcc0",	RTYPE_FCC | 0},  \
+    {"$fcc1",	RTYPE_FCC | 1},  \
+    {"$fcc2",	RTYPE_FCC | 2},  \
+    {"$fcc3",	RTYPE_FCC | 3},  \
+    {"$fcc4",	RTYPE_FCC | 4},  \
+    {"$fcc5",	RTYPE_FCC | 5},  \
+    {"$fcc6",	RTYPE_FCC | 6},  \
+    {"$fcc7",	RTYPE_FCC | 7}
+
+#define COPROC_CONDITION_CODE_NAMES         \
+    {"$cc0",	RTYPE_FCC | RTYPE_CCC | 0}, \
+    {"$cc1",	RTYPE_FCC | RTYPE_CCC | 1}, \
+    {"$cc2",	RTYPE_FCC | RTYPE_CCC | 2}, \
+    {"$cc3",	RTYPE_FCC | RTYPE_CCC | 3}, \
+    {"$cc4",	RTYPE_FCC | RTYPE_CCC | 4}, \
+    {"$cc5",	RTYPE_FCC | RTYPE_CCC | 5}, \
+    {"$cc6",	RTYPE_FCC | RTYPE_CCC | 6}, \
+    {"$cc7",	RTYPE_FCC | RTYPE_CCC | 7}
+
+#define N32N64_SYMBOLIC_REGISTER_NAMES \
+    {"$a4",	RTYPE_GP | 8},  \
+    {"$a5",	RTYPE_GP | 9},  \
+    {"$a6",	RTYPE_GP | 10}, \
+    {"$a7",	RTYPE_GP | 11}, \
+    {"$ta0",	RTYPE_GP | 8},  /* alias for $a4 */ \
+    {"$ta1",	RTYPE_GP | 9},  /* alias for $a5 */ \
+    {"$ta2",	RTYPE_GP | 10}, /* alias for $a6 */ \
+    {"$ta3",	RTYPE_GP | 11}, /* alias for $a7 */ \
+    {"$t0",	RTYPE_GP | 12}, \
+    {"$t1",	RTYPE_GP | 13}, \
+    {"$t2",	RTYPE_GP | 14}, \
+    {"$t3",	RTYPE_GP | 15}
+
+#define O32_SYMBOLIC_REGISTER_NAMES \
+    {"$t0",	RTYPE_GP | 8},  \
+    {"$t1",	RTYPE_GP | 9},  \
+    {"$t2",	RTYPE_GP | 10}, \
+    {"$t3",	RTYPE_GP | 11}, \
+    {"$t4",	RTYPE_GP | 12}, \
+    {"$t5",	RTYPE_GP | 13}, \
+    {"$t6",	RTYPE_GP | 14}, \
+    {"$t7",	RTYPE_GP | 15}, \
+    {"$ta0",	RTYPE_GP | 12}, /* alias for $t4 */ \
+    {"$ta1",	RTYPE_GP | 13}, /* alias for $t5 */ \
+    {"$ta2",	RTYPE_GP | 14}, /* alias for $t6 */ \
+    {"$ta3",	RTYPE_GP | 15}  /* alias for $t7 */ 
+
+/* Remaining symbolic register names */
+#define SYMBOLIC_REGISTER_NAMES \
+    {"$zero",	RTYPE_GP | 0},  \
+    {"$at",	RTYPE_GP | 1},  \
+    {"$AT",	RTYPE_GP | 1},  \
+    {"$v0",	RTYPE_GP | 2},  \
+    {"$v1",	RTYPE_GP | 3},  \
+    {"$a0",	RTYPE_GP | 4},  \
+    {"$a1",	RTYPE_GP | 5},  \
+    {"$a2",	RTYPE_GP | 6},  \
+    {"$a3",	RTYPE_GP | 7},  \
+    {"$s0",	RTYPE_GP | 16}, \
+    {"$s1",	RTYPE_GP | 17}, \
+    {"$s2",	RTYPE_GP | 18}, \
+    {"$s3",	RTYPE_GP | 19}, \
+    {"$s4",	RTYPE_GP | 20}, \
+    {"$s5",	RTYPE_GP | 21}, \
+    {"$s6",	RTYPE_GP | 22}, \
+    {"$s7",	RTYPE_GP | 23}, \
+    {"$t8",	RTYPE_GP | 24}, \
+    {"$t9",	RTYPE_GP | 25}, \
+    {"$k0",	RTYPE_GP | 26}, \
+    {"$kt0",	RTYPE_GP | 26}, \
+    {"$k1",	RTYPE_GP | 27}, \
+    {"$kt1",	RTYPE_GP | 27}, \
+    {"$gp",	RTYPE_GP | 28}, \
+    {"$sp",	RTYPE_GP | 29}, \
+    {"$s8",	RTYPE_GP | 30}, \
+    {"$fp",	RTYPE_GP | 30}, \
+    {"$ra",	RTYPE_GP | 31}
+
+#define MIPS16_SPECIAL_REGISTER_NAMES \
+    {"$pc",	RTYPE_PC | 0}
+
+#define MDMX_VECTOR_REGISTER_NAMES \
+    /* {"$v0",	RTYPE_VEC | 0},  clash with REG 2 above */ \
+    /* {"$v1",	RTYPE_VEC | 1},  clash with REG 3 above */ \
+    {"$v2",	RTYPE_VEC | 2},  \
+    {"$v3",	RTYPE_VEC | 3},  \
+    {"$v4",	RTYPE_VEC | 4},  \
+    {"$v5",	RTYPE_VEC | 5},  \
+    {"$v6",	RTYPE_VEC | 6},  \
+    {"$v7",	RTYPE_VEC | 7},  \
+    {"$v8",	RTYPE_VEC | 8},  \
+    {"$v9",	RTYPE_VEC | 9},  \
+    {"$v10",	RTYPE_VEC | 10}, \
+    {"$v11",	RTYPE_VEC | 11}, \
+    {"$v12",	RTYPE_VEC | 12}, \
+    {"$v13",	RTYPE_VEC | 13}, \
+    {"$v14",	RTYPE_VEC | 14}, \
+    {"$v15",	RTYPE_VEC | 15}, \
+    {"$v16",	RTYPE_VEC | 16}, \
+    {"$v17",	RTYPE_VEC | 17}, \
+    {"$v18",	RTYPE_VEC | 18}, \
+    {"$v19",	RTYPE_VEC | 19}, \
+    {"$v20",	RTYPE_VEC | 20}, \
+    {"$v21",	RTYPE_VEC | 21}, \
+    {"$v22",	RTYPE_VEC | 22}, \
+    {"$v23",	RTYPE_VEC | 23}, \
+    {"$v24",	RTYPE_VEC | 24}, \
+    {"$v25",	RTYPE_VEC | 25}, \
+    {"$v26",	RTYPE_VEC | 26}, \
+    {"$v27",	RTYPE_VEC | 27}, \
+    {"$v28",	RTYPE_VEC | 28}, \
+    {"$v29",	RTYPE_VEC | 29}, \
+    {"$v30",	RTYPE_VEC | 30}, \
+    {"$v31",	RTYPE_VEC | 31}
+
+#define MIPS_DSP_ACCUMULATOR_NAMES \
+    {"$ac0",	RTYPE_ACC | 0}, \
+    {"$ac1",	RTYPE_ACC | 1}, \
+    {"$ac2",	RTYPE_ACC | 2}, \
+    {"$ac3",	RTYPE_ACC | 3}
+
+static const struct regname reg_names[] = {
+  GENERIC_REGISTER_NUMBERS,
+  FPU_REGISTER_NAMES,
+  FPU_CONDITION_CODE_NAMES,
+  COPROC_CONDITION_CODE_NAMES,
+
+  /* The $txx registers depends on the abi,
+     these will be added later into the symbol table from
+     one of the tables below once mips_abi is set after 
+     parsing of arguments from the command line. */
+  SYMBOLIC_REGISTER_NAMES,
+
+  MIPS16_SPECIAL_REGISTER_NAMES,
+  MDMX_VECTOR_REGISTER_NAMES,
+  MIPS_DSP_ACCUMULATOR_NAMES,
+  {0, 0}
+};
+
+static const struct regname reg_names_o32[] = {
+  O32_SYMBOLIC_REGISTER_NAMES,
+  {0, 0}
+};
+
+static const struct regname reg_names_n32n64[] = {
+  N32N64_SYMBOLIC_REGISTER_NAMES,
+  {0, 0}
+};
+
+static int
+reg_lookup (char **s, unsigned int types, unsigned int *regnop)
+{
+  symbolS *symbolP;
+  char *e;
+  char save_c;
+  int reg = -1;
+
+  /* Find end of name.  */
+  e = *s;
+  if (is_name_beginner (*e))
+    ++e;
+  while (is_part_of_name (*e))
+    ++e;
+
+  /* Terminate name.  */
+  save_c = *e;
+  *e = '\0';
+
+  /* Look for a register symbol.  */
+  if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
+    {
+      int r = S_GET_VALUE (symbolP);
+      if (r & types)
+	reg = r & RNUM_MASK;
+      else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
+	/* Convert GP reg $v0/1 to MDMX reg $v0/1!  */
+	reg = (r & RNUM_MASK) - 2;
+    }
+  /* Else see if this is a register defined in an itbl entry.  */
+  else if ((types & RTYPE_GP) && itbl_have_entries)
+    {
+      char *n = *s;
+      unsigned long r;
+
+      if (*n == '$')
+	++n;
+      if (itbl_get_reg_val (n, &r))
+	reg = r & RNUM_MASK;
+    }
+
+  /* Advance to next token if a register was recognised.  */
+  if (reg >= 0)
+    *s = e;
+  else if (types & RWARN)
+    as_warn ("Unrecognized register name `%s'", *s);
+
+  *e = save_c;
+  if (regnop)
+    *regnop = reg;
+  return reg >= 0;
+}
+
+/* This function is called once, at assembler startup time.  It should set up
+   all the tables, etc. that the MD part of the assembler will need.  */
 
 void
 md_begin (void)
 {
-  register const char *retval = NULL;
+  const char *retval = NULL;
   int i = 0;
   int broken = 0;
 
@@ -1481,46 +1821,20 @@ md_begin (void)
 
   /* We add all the general register names to the symbol table.  This
      helps us detect invalid uses of them.  */
-  for (i = 0; i < 32; i++)
-    {
-      char buf[5];
-
-      sprintf (buf, "$%d", i);
-      symbol_table_insert (symbol_new (buf, reg_section, i,
+  for (i = 0; reg_names[i].name; i++) 
+    symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
+				     reg_names[i].num, // & RNUM_MASK,
+				     &zero_address_frag));
+  if (HAVE_NEWABI)
+    for (i = 0; reg_names_n32n64[i].name; i++) 
+      symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
+				       reg_names_n32n64[i].num, // & RNUM_MASK,
 				       &zero_address_frag));
-    }
-  symbol_table_insert (symbol_new ("$ra", reg_section, RA,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$fp", reg_section, FP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$sp", reg_section, SP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$gp", reg_section, GP,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$at", reg_section, AT,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
-				   &zero_address_frag));
-  symbol_table_insert (symbol_new ("$pc", reg_section, -1,
-				   &zero_address_frag));
-
-  /* If we don't add these register names to the symbol table, they
-     may end up being added as regular symbols by operand(), and then
-     make it to the object file as undefined in case they're not
-     regarded as local symbols.  They're local in o32, since `$' is a
-     local symbol prefix, but not in n32 or n64.  */
-  for (i = 0; i < 8; i++)
-    {
-      char buf[6];
-
-      sprintf (buf, "$fcc%i", i);
-      symbol_table_insert (symbol_new (buf, reg_section, -1,
+  else
+    for (i = 0; reg_names_o32[i].name; i++) 
+      symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
+				       reg_names_o32[i].num, // & RNUM_MASK,
 				       &zero_address_frag));
-    }
 
   mips_no_prev_insn ();
 
@@ -1535,7 +1849,8 @@ md_begin (void)
 
   bfd_set_gp_size (stdoutput, g_switch_value);
 
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+#ifdef OBJ_ELF
+  if (IS_ELF)
     {
       /* On a native system other than VxWorks, sections must be aligned
 	 to 16 byte boundaries.  When configured for an embedded ELF
@@ -1573,9 +1888,7 @@ md_begin (void)
 	    bfd_set_section_flags (stdoutput, sec, flags);
 	    bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
 
-#ifdef OBJ_ELF
 	    mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
-#endif
 	  }
 	else
 	  {
@@ -1585,7 +1898,6 @@ md_begin (void)
 	    bfd_set_section_flags (stdoutput, sec, flags);
 	    bfd_set_section_alignment (stdoutput, sec, 3);
 
-#ifdef OBJ_ELF
 	    /* Set up the option header.  */
 	    {
 	      Elf_Internal_Options opthdr;
@@ -1602,7 +1914,6 @@ md_begin (void)
 
 	      mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
 	    }
-#endif
 	  }
 
 	if (ECOFF_DEBUGGING)
@@ -1612,8 +1923,7 @@ md_begin (void)
 					  SEC_HAS_CONTENTS | SEC_READONLY);
 	    (void) bfd_set_section_alignment (stdoutput, sec, 2);
 	  }
-#ifdef OBJ_ELF
-	else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
+	else if (mips_flag_pdr)
 	  {
 	    pdr_seg = subseg_new (".pdr", (subsegT) 0);
 	    (void) bfd_set_section_flags (stdoutput, pdr_seg,
@@ -1621,11 +1931,11 @@ md_begin (void)
 					  | SEC_DEBUGGING);
 	    (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
 	  }
-#endif
 
 	subseg_set (seg, subseg);
       }
     }
+#endif /* OBJ_ELF */
 
   if (! ECOFF_DEBUGGING)
     md_obj_begin ();
@@ -1824,10 +2134,11 @@ reg_needs_delay (unsigned int reg)
 static void
 mips_move_labels (void)
 {
+  segment_info_type *si = seg_info (now_seg);
   struct insn_label_list *l;
   valueT val;
 
-  for (l = insn_labels; l != NULL; l = l->next)
+  for (l = si->label_list; l != NULL; l = l->next)
     {
       assert (S_GET_SEGMENT (l->label) == now_seg);
       symbol_set_frag (l->label, frag_now);
@@ -1839,6 +2150,28 @@ mips_move_labels (void)
     }
 }
 
+static bfd_boolean
+s_is_linkonce (symbolS *sym, segT from_seg)
+{
+  bfd_boolean linkonce = FALSE;
+  segT symseg = S_GET_SEGMENT (sym);
+
+  if (symseg != from_seg && !S_IS_LOCAL (sym))
+    {
+      if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
+	linkonce = TRUE;
+#ifdef OBJ_ELF
+      /* The GNU toolchain uses an extension for ELF: a section
+	 beginning with the magic string .gnu.linkonce is a
+	 linkonce section.  */
+      if (strncmp (segment_name (symseg), ".gnu.linkonce",
+		   sizeof ".gnu.linkonce" - 1) == 0)
+	linkonce = TRUE;
+#endif
+    }
+  return linkonce;
+}
+
 /* Mark instruction labels in mips16 mode.  This permits the linker to
    handle them specially, such as generating jalx instructions when
    needed.  We also make them odd for the duration of the assembly, in
@@ -1850,21 +2183,29 @@ mips_move_labels (void)
 static void
 mips16_mark_labels (void)
 {
-  if (mips_opts.mips16)
-    {
-      struct insn_label_list *l;
-      valueT val;
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l;
 
-      for (l = insn_labels; l != NULL; l = l->next)
-	{
-#ifdef OBJ_ELF
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    S_SET_OTHER (l->label, STO_MIPS16);
+  if (!mips_opts.mips16)
+    return;
+
+  for (l = si->label_list; l != NULL; l = l->next)
+   {
+      symbolS *label = l->label;
+
+#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
+      if (IS_ELF)
+	S_SET_OTHER (label, STO_MIPS16);
 #endif
-	  val = S_GET_VALUE (l->label);
-	  if ((val & 1) == 0)
-	    S_SET_VALUE (l->label, val + 1);
-	}
+      if ((S_GET_VALUE (label) & 1) == 0
+	/* Don't adjust the address if the label is global or weak, or
+	   in a link-once section, since we'll be emitting symbol reloc
+	   references to it which will be patched up by the linker, and
+	   the final value of the symbol may or may not be MIPS16.  */
+	  && ! S_IS_WEAK (label)
+	  && ! S_IS_EXTERNAL (label)
+	  && ! s_is_linkonce (label, now_seg))
+	S_SET_VALUE (label, S_GET_VALUE (label) | 1);
     }
 }
 
@@ -2189,9 +2530,10 @@ static void
 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	     bfd_reloc_code_real_type *reloc_type)
 {
-  register unsigned long prev_pinfo, pinfo;
+  unsigned long prev_pinfo, pinfo;
   relax_stateT prev_insn_frag_type = 0;
   bfd_boolean relaxed_branch = FALSE;
+  segment_info_type *si = seg_info (now_seg);
 
   /* Mark instruction labels in mips16 mode.  */
   mips16_mark_labels ();
@@ -2454,6 +2796,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 				     reloc_type[0] == BFD_RELOC_16_PCREL_S2,
 				     reloc_type[0]);
 
+	  /* Tag symbols that have a R_MIPS16_26 relocation against them.  */
+	  if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
+	      && ip->fixp[0]->fx_addsy)
+	    *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
+
 	  /* These relocations can have an addend that won't fit in
 	     4 octets for 64bit assembly.  */
 	  if (HAVE_64BIT_GPRS
@@ -2608,7 +2955,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		 whether there is a label on this instruction.  If
 		 there are any branches to anything other than a
 		 label, users must use .set noreorder.  */
-	      || insn_labels != NULL
+	      || si->label_list != NULL
 	      /* If the previous instruction is in a variant frag
 		 other than this branch's one, we cannot do the swap.
 		 This does not apply to the mips16, which uses variant
@@ -2715,10 +3062,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      if (mips_opts.mips16
 		  && (pinfo & INSN_UNCOND_BRANCH_DELAY)
 		  && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
-		  && (mips_opts.isa == ISA_MIPS32
-		      || mips_opts.isa == ISA_MIPS32R2
-		      || mips_opts.isa == ISA_MIPS64
-		      || mips_opts.isa == ISA_MIPS64R2))
+		  && ISA_SUPPORTS_MIPS16E)
 		{
 		  /* Convert MIPS16 jr/jalr into a "compact" jump.  */
 		  ip->insn_opcode |= 0x0080;
@@ -3000,16 +3344,24 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
   assert (mo);
   assert (strcmp (name, mo->name) == 0);
 
-  /* Search until we get a match for NAME.  It is assumed here that
-     macros will never generate MDMX or MIPS-3D instructions.  */
-  while (strcmp (fmt, mo->args) != 0
-	 || mo->pinfo == INSN_MACRO
-	 || !OPCODE_IS_MEMBER (mo,
+  while (1)
+    {
+      /* Search until we get a match for NAME.  It is assumed here that
+	 macros will never generate MDMX, MIPS-3D, or MT instructions.  */
+      if (strcmp (fmt, mo->args) == 0
+	  && mo->pinfo != INSN_MACRO
+	  && OPCODE_IS_MEMBER (mo,
 			       (mips_opts.isa
-				| (file_ase_mips16 ? INSN_MIPS16 : 0)),
+				| (mips_opts.mips16 ? INSN_MIPS16 : 0)
+				| (mips_opts.ase_dsp ? INSN_DSP : 0)
+				| ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				   ? INSN_DSP64 : 0)
+				| (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
+				| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			       mips_opts.arch)
-	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
-    {
+	  && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
+	break;
+
       ++mo;
       assert (mo->name);
       assert (strcmp (name, mo->name) == 0);
@@ -3060,6 +3412,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	    }
 	  continue;
 
+	case '2':
+	  INSERT_OPERAND (BP, insn, va_arg (args, int));
+	  continue;
+
 	case 't':
 	case 'w':
 	case 'E':
@@ -3187,7 +3543,11 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	  continue;
 
 	case 'C':
-	  insn.insn_opcode |= va_arg (args, unsigned long);
+	  INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
+	  continue;
+
+	case 'k':
+	  INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
 	  continue;
 
 	default:
@@ -3271,7 +3631,7 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 
 	    regno = va_arg (args, int);
 	    regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
-	    insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
+	    MIPS16_INSERT_OPERAND (REG32R, insn, regno);
 	  }
 	  continue;
 
@@ -3387,7 +3747,7 @@ macro_build_lui (expressionS *ep, int regnum)
 
   if (high_expr.X_op == O_constant)
     {
-      /* we can compute the instruction now without a relocation entry */
+      /* We can compute the instruction now without a relocation entry.  */
       high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
 				>> 16) & 0xffff;
       *r = BFD_RELOC_UNUSED;
@@ -4164,7 +4524,7 @@ add_got_offset_hilo (int dest, expressionS *local, int tmp)
 static void
 macro (struct mips_cl_insn *ip)
 {
-  register int treg, sreg, dreg, breg;
+  int treg, sreg, dreg, breg;
   int tempreg;
   int mask;
   int used_at = 0;
@@ -4284,6 +4644,22 @@ macro (struct mips_cl_insn *ip)
       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
       break;
 
+    case M_BALIGN:
+      switch (imm_expr.X_add_number)
+	{
+	case 0:
+	  macro_build (NULL, "nop", "");
+	  break;
+	case 2:
+	  macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
+	  break;
+	default:
+	  macro_build (NULL, "balign", "t,s,2", treg, sreg,
+		       (int)imm_expr.X_add_number);
+	  break;
+	}
+      break;
+
     case M_BEQ_I:
       s = "beq";
       goto beq_i;
@@ -5814,6 +6190,9 @@ macro (struct mips_cl_insn *ip)
     case M_SCD_AB:
       s = "scd";
       goto st;
+    case M_CACHE_AB:
+      s = "cache";
+      goto st;
     case M_SDC1_AB:
       if (mips_opts.arch == CPU_R4650)
 	{
@@ -5851,6 +6230,8 @@ macro (struct mips_cl_insn *ip)
 	  || mask == M_L_DAB
 	  || mask == M_S_DAB)
 	fmt = "T,o(b)";
+      else if (mask == M_CACHE_AB)
+	fmt = "k,o(b)";
       else if (coproc)
 	fmt = "E,o(b)";
       else
@@ -6763,7 +7144,7 @@ macro (struct mips_cl_insn *ip)
 static void
 macro2 (struct mips_cl_insn *ip)
 {
-  register int treg, sreg, dreg, breg;
+  int treg, sreg, dreg, breg;
   int tempreg;
   int mask;
   int used_at;
@@ -7808,6 +8189,10 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '+':
     	switch (c = *p++)
 	  {
+	  case '1': USE_BITS (OP_MASK_UDI1,     OP_SH_UDI1); 	break;
+	  case '2': USE_BITS (OP_MASK_UDI2,	OP_SH_UDI2); 	break;
+	  case '3': USE_BITS (OP_MASK_UDI3,	OP_SH_UDI3); 	break;
+	  case '4': USE_BITS (OP_MASK_UDI4,	OP_SH_UDI4); 	break;
 	  case 'A': USE_BITS (OP_MASK_SHAMT,	OP_SH_SHAMT);	break;
 	  case 'B': USE_BITS (OP_MASK_INSMSB,	OP_SH_INSMSB);	break;
 	  case 'C': USE_BITS (OP_MASK_EXTMSBD,	OP_SH_EXTMSBD);	break;
@@ -7882,6 +8267,7 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+      case '2': USE_BITS (OP_MASK_BP,		OP_SH_BP);	break;
       case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
       case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;
       case '5': USE_BITS (OP_MASK_IMM8, 	OP_SH_IMM8);	break;
@@ -7913,6 +8299,62 @@ validate_mips_insn (const struct mips_opcode *opc)
   return 1;
 }
 
+/* UDI immediates.  */
+struct mips_immed {
+  char		type;
+  unsigned int	shift;
+  unsigned long	mask;
+  const char *	desc;
+};
+
+static const struct mips_immed mips_immed[] = {
+  { '1',	OP_SH_UDI1,	OP_MASK_UDI1,		0},
+  { '2',	OP_SH_UDI2,	OP_MASK_UDI2,		0},
+  { '3',	OP_SH_UDI3,	OP_MASK_UDI3,		0},
+  { '4',	OP_SH_UDI4,	OP_MASK_UDI4,		0},
+  { 0,0,0,0 }
+};
+
+/* Check whether an odd floating-point register is allowed.  */
+static int
+mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
+{
+  const char *s = insn->name;
+
+  if (insn->pinfo == INSN_MACRO)
+    /* Let a macro pass, we'll catch it later when it is expanded.  */
+    return 1;
+
+  if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
+    {
+      /* Allow odd registers for single-precision ops.  */
+      switch (insn->pinfo & (FP_S | FP_D))
+	{
+	case FP_S:
+	case 0:
+	  return 1;	/* both single precision - ok */
+	case FP_D:
+	  return 0;	/* both double precision - fail */
+	default:
+	  break;
+	}
+
+      /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand.  */
+      s = strchr (insn->name, '.');
+      if (argnum == 2)
+	s = s != NULL ? strchr (s + 1, '.') : NULL;
+      return (s != NULL && (s[1] == 'w' || s[1] == 's'));
+    } 
+
+  /* Single-precision coprocessor loads and moves are OK too.  */
+  if ((insn->pinfo & FP_S)
+      && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
+			 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
+    return 1;
+
+  return 0;
+}
+
 /* This routine assembles an instruction into its binary format.  As a
    side effect, it sets one of the global variables imm_reloc or
    offset_reloc to the type of relocation to do if one of the operands
@@ -7933,6 +8375,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
   char *s_reset;
   char save_c = 0;
   offsetT min_range, max_range;
+  int argnum;
+  unsigned int rtype;
 
   insn_error = NULL;
 
@@ -7993,11 +8437,18 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+			     /* We don't check for mips_opts.mips16 here since
+			        we want to allow jalx if -mips16 was specified
+			        on the command line.  */
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
+	      		     | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				? INSN_DSP64 : 0)
+	      		     | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
 	      		     | (mips_opts.ase_mt ? INSN_MT : 0)
-			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
+			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
+			     | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			    mips_opts.arch))
 	ok = TRUE;
       else
@@ -8036,6 +8487,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 
       create_insn (ip, insn);
       insn_error = NULL;
+      argnum = 1;
       for (args = insn->args;; ++args)
 	{
 	  int is_mdmx;
@@ -8049,16 +8501,29 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		return;
 	      break;
 
+	    case '2': /* dsp 2-bit unsigned immediate in bit 11 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if ((unsigned long) imm_expr.X_add_number != 1
+		  && (unsigned long) imm_expr.X_add_number != 3)
+		{
+		  as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
+			  (unsigned long) imm_expr.X_add_number);
+		}
+	      INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
 	    case '3': /* dsp 3-bit unsigned immediate in bit 21 */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_SA3)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_SA3;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
+	      INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8068,11 +8533,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_SA4)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_SA4;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
+	      INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8082,11 +8546,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_IMM8)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_IMM8;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
+	      INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8096,11 +8559,10 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_RS)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_RS;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
+	      INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8111,7 +8573,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_DSPACC;
+		  INSERT_OPERAND (DSPACC, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8123,12 +8585,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_WRDSP,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_WRDSP;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_WRDSP,
+			  (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
+	      INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8139,7 +8600,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_DSPACC_S;
+		  INSERT_OPERAND (DSPACC_S, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8154,13 +8615,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_DSPSFT;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_DSPSFT);
+	      INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8170,12 +8629,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
 		{
-		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
-			   OP_MASK_RDDSP,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_RDDSP;
+		  as_bad (_("DSP immediate not in range 0..%d (%lu)"),
+			  OP_MASK_RDDSP,
+			  (unsigned long) imm_expr.X_add_number);
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
+	      INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8188,13 +8646,11 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_DSPSFT_7);
+	      INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8207,41 +8663,33 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      if (imm_expr.X_add_number < min_range ||
 		  imm_expr.X_add_number > max_range)
 		{
-		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
-			   (long) min_range, (long) max_range,
-			   (long) imm_expr.X_add_number);
+		  as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
+			  (long) min_range, (long) max_range,
+			  (long) imm_expr.X_add_number);
 		}
-	      imm_expr.X_add_number &= OP_MASK_IMM10;
-	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
-				  << OP_SH_IMM10);
+	      INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-            case '!': /* mt 1-bit unsigned immediate in bit 5 */
+            case '!': /* MT usermode flag bit.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_MT_U)
-		{
-		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
-			   OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_MT_U;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+		as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
+			(unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-            case '$': /* mt 1-bit unsigned immediate in bit 4 */
+            case '$': /* MT load high flag bit.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number & ~OP_MASK_MT_H)
-		{
-		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
-			   OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_MT_H;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+		as_bad (_("MT load high bit not 0 or 1 (%lu)"),
+			(unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8252,7 +8700,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_MTACC_T;
+		  INSERT_OPERAND (MTACC_T, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8265,7 +8713,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		  regno = s[3] - '0';
 		  s += 4;
-		  ip->insn_opcode |= regno << OP_SH_MTACC_D;
+		  INSERT_OPERAND (MTACC_D, *ip, regno);
 		  continue;
 		}
 	      else
@@ -8273,6 +8721,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      break;
 
 	    case ',':
+	      ++argnum;
 	      if (*s++ == *args)
 		continue;
 	      s--;
@@ -8318,6 +8767,34 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	    case '+':		/* Opcode extension character.  */
 	      switch (*++args)
 		{
+		case '1':	/* UDI immediates.  */
+		case '2':
+		case '3':
+		case '4':
+		  {
+		    const struct mips_immed *imm = mips_immed;
+
+		    while (imm->type && imm->type != *args)
+		      ++imm;
+		    if (! imm->type)
+		      internalError ();
+		    my_getExpression (&imm_expr, s);
+		    check_absolute_expr (ip, &imm_expr);
+		    if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
+		      {
+		        as_warn (_("Illegal %s number (%lu, 0x%lx)"),
+				 imm->desc ? imm->desc : ip->insn_mo->name,
+				 (unsigned long) imm_expr.X_add_number,
+				 (unsigned long) imm_expr.X_add_number);
+			      imm_expr.X_add_number &= imm->mask;
+		      }
+		    ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
+					<< imm->shift);
+		    imm_expr.X_op = O_absent;
+		    s = expr_end;
+		  }
+		  continue;
+		  
 		case 'A':		/* ins/ext position, becomes LSB.  */
 		  limlo = 0;
 		  limhi = 31;
@@ -8424,11 +8901,11 @@ do_msbd:
 		  s = expr_end;
 		  continue;
 
-		case 'T': /* Coprocessor register */
+		case 'T': /* Coprocessor register.  */
 		  /* +T is for disassembly only; never match.  */
 		  break;
 
-		case 't': /* Coprocessor register number */
+		case 't': /* Coprocessor register number.  */
 		  if (s[0] == '$' && ISDIGIT (s[1]))
 		    {
 		      ++s;
@@ -8444,7 +8921,7 @@ do_msbd:
 			as_bad (_("Invalid register number (%d)"), regno);
 		      else
 			{
-			  ip->insn_opcode |= regno << OP_SH_RT;
+			  INSERT_OPERAND (RT, *ip, regno);
 			  continue;
 			}
 		    }
@@ -8507,8 +8984,9 @@ do_msbd:
 	    case 'c':		/* break code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		as_warn (_("Illegal break code (%lu)"),
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
+		as_warn (_("Code for %s not in range 0..1023 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8518,8 +8996,9 @@ do_msbd:
 	    case 'q':		/* lower break code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		as_warn (_("Illegal lower break code (%lu)"),
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
+		as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8530,7 +9009,8 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
-		as_warn (_("Illegal 20-bit code (%lu)"),
+		as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
+			 ip->insn_mo->name,
 			 (unsigned long) imm_expr.X_add_number);
 	      INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
@@ -8540,13 +9020,13 @@ do_msbd:
 	    case 'C':           /* Coprocessor code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
-	      if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
+	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
 		{
 		  as_warn (_("Coproccesor code > 25 bits (%lu)"),
 			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= ((1 << 25) - 1);
+		  imm_expr.X_add_number &= OP_MASK_COPZ;
 		}
-	      ip->insn_opcode |= imm_expr.X_add_number;
+	      INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8555,14 +9035,17 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
-		as_warn (_("Illegal 19-bit code (%lu)"),
-			 (unsigned long) imm_expr.X_add_number);
+		{
+		  as_warn (_("Illegal 19-bit code (%lu)"),
+			   (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_CODE19;
+		}
 	      INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
 
-	    case 'P':		/* Performance register */
+	    case 'P':		/* Performance register.  */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
@@ -8573,6 +9056,20 @@ do_msbd:
 	      s = expr_end;
 	      continue;
 
+	    case 'G':		/* Coprocessor destination register.  */
+	      if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
+		ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
+	      else
+		ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
+	      INSERT_OPERAND (RD, *ip, regno);
+	      if (ok) 
+		{
+		  lastregno = regno;
+		  continue;
+		}
+	      else
+		break;
+
 	    case 'b':		/* base register */
 	    case 'd':		/* destination register */
 	    case 's':		/* source register */
@@ -8581,106 +9078,22 @@ do_msbd:
 	    case 'v':		/* both dest and source */
 	    case 'w':		/* both dest and target */
 	    case 'E':		/* coprocessor target register */
-	    case 'G':		/* coprocessor destination register */
 	    case 'K':		/* 'rdhwr' destination register */
 	    case 'x':		/* ignore register name */
 	    case 'z':		/* must be zero register */
 	    case 'U':           /* destination register (clo/clz).  */
 	    case 'g':		/* coprocessor destination register */
-	      s_reset = s;
-	      if (s[0] == '$')
+	      s_reset = s;	      
+	      if (*args == 'E' || *args == 'K')
+		ok = reg_lookup (&s, RTYPE_NUM, &regno);
+	      else
+		{
+		  ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
+		  if (regno == AT && ! mips_opts.noat)
+		    as_warn ("Used $at without \".set noat\"");
+		}
+	      if (ok)
 		{
-		  if (ISDIGIT (s[1]))
-		    {
-		      ++s;
-		      regno = 0;
-		      do
-			{
-			  regno *= 10;
-			  regno += *s - '0';
-			  ++s;
-			}
-		      while (ISDIGIT (*s));
-		      if (regno > 31)
-			as_bad (_("Invalid register number (%d)"), regno);
-		    }
-		  else if (*args == 'E' || *args == 'G' || *args == 'K')
-		    goto notreg;
-		  else
-		    {
-		      if (s[1] == 'r' && s[2] == 'a')
-			{
-			  s += 3;
-			  regno = RA;
-			}
-		      else if (s[1] == 'f' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = FP;
-			}
-		      else if (s[1] == 's' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = SP;
-			}
-		      else if (s[1] == 'g' && s[2] == 'p')
-			{
-			  s += 3;
-			  regno = GP;
-			}
-		      else if (s[1] == 'a' && s[2] == 't')
-			{
-			  s += 3;
-			  regno = AT;
-			}
-		      else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
-			{
-			  s += 4;
-			  regno = KT0;
-			}
-		      else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
-			{
-			  s += 4;
-			  regno = KT1;
-			}
-		      else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
-			{
-			  s += 5;
-			  regno = ZERO;
-			}
-		      else if (itbl_have_entries)
-			{
-			  char *p, *n;
-			  unsigned long r;
-
-			  p = s + 1; 	/* advance past '$' */
-			  n = itbl_get_field (&p);  /* n is name */
-
-			  /* See if this is a register defined in an
-			     itbl entry.  */
-			  if (itbl_get_reg_val (n, &r))
-			    {
-			      /* Get_field advances to the start of
-				 the next field, so we need to back
-				 rack to the end of the last field.  */
-			      if (p)
-				s = p - 1;
-			      else
-				s = strchr (s, '\0');
-			      regno = r;
-			    }
-			  else
-			    goto notreg;
-			}
-		      else
-			goto notreg;
-		    }
-		  if (regno == AT
-		      && ! mips_opts.noat
-		      && *args != 'E'
-		      && *args != 'G'
-		      && *args != 'K')
-		    as_warn (_("Used $at without \".set noat\""));
 		  c = *args;
 		  if (*s == ' ')
 		    ++s;
@@ -8746,7 +9159,6 @@ do_msbd:
 		  lastregno = regno;
 		  continue;
 		}
-	    notreg:
 	      switch (*args++)
 		{
 		case 'r':
@@ -8799,40 +9211,22 @@ do_msbd:
 	    case 'R':		/* floating point source register */
 	    case 'V':
 	    case 'W':
+	      rtype = RTYPE_FPU;
+	      if (is_mdmx
+		  || (mips_opts.ase_mdmx
+		      && (ip->insn_mo->pinfo & FP_D)
+		      && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
+						| INSN_COPROC_MEMORY_DELAY
+						| INSN_LOAD_COPROC_DELAY
+						| INSN_LOAD_MEMORY_DELAY
+						| INSN_STORE_MEMORY))))
+		rtype |= RTYPE_VEC;
 	      s_reset = s;
-	      /* Accept $fN for FP and MDMX register numbers, and in
-                 addition accept $vN for MDMX register numbers.  */
-	      if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
-		  || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
-		      && ISDIGIT (s[2])))
+	      if (reg_lookup (&s, rtype, &regno))
 		{
-		  s += 2;
-		  regno = 0;
-		  do
-		    {
-		      regno *= 10;
-		      regno += *s - '0';
-		      ++s;
-		    }
-		  while (ISDIGIT (*s));
-
-		  if (regno > 31)
-		    as_bad (_("Invalid float register number (%d)"), regno);
-
 		  if ((regno & 1) != 0
 		      && HAVE_32BIT_FPRS
-		      && ! (strcmp (str, "mtc1") == 0
-			    || strcmp (str, "mfc1") == 0
-			    || strcmp (str, "lwc1") == 0
-			    || strcmp (str, "swc1") == 0
-			    || strcmp (str, "l.s") == 0
-			    || strcmp (str, "s.s") == 0
-			    || strcmp (str, "mftc1") == 0
-			    || strcmp (str, "mfthc1") == 0
-			    || strcmp (str, "cftc1") == 0
-			    || strcmp (str, "mttc1") == 0
-			    || strcmp (str, "mtthc1") == 0
-			    || strcmp (str, "cttc1") == 0))
+		      && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
 		    as_warn (_("Float register should be even, was %d"),
 			     regno);
 
@@ -9094,15 +9488,14 @@ do_msbd:
 			break;
 		      }
 		    new_seg = subseg_new (newname, (subsegT) 0);
-		    if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+		    if (IS_ELF)
 		      bfd_set_section_flags (stdoutput, new_seg,
 					     (SEC_ALLOC
 					      | SEC_LOAD
 					      | SEC_READONLY
 					      | SEC_DATA));
 		    frag_align (*args == 'l' ? 2 : 3, 0, 0);
-		    if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-			&& strcmp (TARGET_OS, "elf") != 0)
+		    if (IS_ELF && strcmp (TARGET_OS, "elf") != 0)
 		      record_alignment (new_seg, 4);
 		    else
 		      record_alignment (new_seg, *args == 'l' ? 2 : 3);
@@ -9220,19 +9613,11 @@ do_msbd:
 
 	    case 'N':		/* 3 bit branch condition code */
 	    case 'M':		/* 3 bit compare condition code */
-	      if (strncmp (s, "$fcc", 4) != 0)
+	      rtype = RTYPE_CCC;
+	      if (ip->insn_mo->pinfo & (FP_D| FP_S))
+		rtype |= RTYPE_FCC;
+	      if (!reg_lookup (&s, rtype, &regno))
 		break;
-	      s += 4;
-	      regno = 0;
-	      do
-		{
-		  regno *= 10;
-		  regno += *s - '0';
-		  ++s;
-		}
-	      while (ISDIGIT (*s));
-	      if (regno > 7)
-		as_bad (_("Invalid condition code register $fcc%d"), regno);
 	      if ((strcmp(str + strlen(str) - 3, ".ps") == 0
 		   || strcmp(str + strlen(str) - 5, "any2f") == 0
 		   || strcmp(str + strlen(str) - 5, "any2t") == 0)
@@ -9399,8 +9784,38 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   argsstart = s;
   for (;;)
     {
+      bfd_boolean ok;
+
       assert (strcmp (insn->name, str) == 0);
 
+      if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
+	ok = TRUE;
+      else
+	ok = FALSE;
+
+      if (! ok)
+	{
+	  if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
+	      && strcmp (insn->name, insn[1].name) == 0)
+	    {
+	      ++insn;
+	      continue;
+	    }
+	  else
+	    {
+	      if (!insn_error)
+		{
+		  static char buf[100];
+		  sprintf (buf,
+			   _("opcode not supported on this processor: %s (%s)"),
+			   mips_cpu_info_from_arch (mips_opts.arch)->name,
+			   mips_cpu_info_from_isa (mips_opts.isa)->name);
+		  insn_error = buf;
+		}
+	      return;
+	    }
+	}
+
       create_insn (ip, insn);
       imm_expr.X_op = O_absent;
       imm_reloc[0] = BFD_RELOC_UNUSED;
@@ -9513,70 +9928,19 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	    case 'R':
 	    case 'X':
 	    case 'Y':
-	      if (s[0] != '$')
-		break;
-	      s_reset = s;
-	      if (ISDIGIT (s[1]))
+  	      s_reset = s;
+	      if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
 		{
-		  ++s;
-		  regno = 0;
-		  do
-		    {
-		      regno *= 10;
-		      regno += *s - '0';
-		      ++s;
-		    }
-		  while (ISDIGIT (*s));
-		  if (regno > 31)
-		    {
-		      as_bad (_("invalid register number (%d)"), regno);
-		      regno = 2;
-		    }
-		}
-	      else
-		{
-		  if (s[1] == 'r' && s[2] == 'a')
-		    {
-		      s += 3;
-		      regno = RA;
-		    }
-		  else if (s[1] == 'f' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = FP;
-		    }
-		  else if (s[1] == 's' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = SP;
-		    }
-		  else if (s[1] == 'g' && s[2] == 'p')
-		    {
-		      s += 3;
-		      regno = GP;
-		    }
-		  else if (s[1] == 'a' && s[2] == 't')
-		    {
-		      s += 3;
-		      regno = AT;
-		    }
-		  else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
-		    {
-		      s += 4;
-		      regno = KT0;
-		    }
-		  else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
-		    {
-		      s += 4;
-		      regno = KT1;
-		    }
-		  else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
+		  if (c == 'v' || c == 'w')
 		    {
-		      s += 5;
-		      regno = ZERO;
+		      if (c == 'v')
+			MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
+		      else
+			MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
+		      ++args;
+		      continue;
 		    }
-		  else
-		    break;
+		  break;
 		}
 
 	      if (*s == ' ')
@@ -9782,29 +10146,18 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		  mask = 7 << 3;
 		while (*s != '\0')
 		  {
-		    int freg, reg1, reg2;
+		    unsigned int freg, reg1, reg2;
 
 		    while (*s == ' ' || *s == ',')
 		      ++s;
-		    if (*s != '$')
-		      {
-			as_bad (_("can't parse register list"));
-			break;
-		      }
-		    ++s;
-		    if (*s != 'f')
+		    if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
 		      freg = 0;
+		    else if (reg_lookup (&s, RTYPE_FPU, &reg1))
+		      freg = 1;
 		    else
 		      {
-			freg = 1;
-			++s;
-		      }
-		    reg1 = 0;
-		    while (ISDIGIT (*s))
-		      {
-			reg1 *= 10;
-			reg1 += *s - '0';
-			++s;
+			as_bad (_("can't parse register list"));
+			break;
 		      }
 		    if (*s == ' ')
 		      ++s;
@@ -9813,25 +10166,11 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		    else
 		      {
 			++s;
-			if (*s != '$')
-			  break;
-			++s;
-			if (freg)
+			if (!reg_lookup (&s, freg ? RTYPE_FPU 
+					 : (RTYPE_GP | RTYPE_NUM), &reg2))
 			  {
-			    if (*s == 'f')
-			      ++s;
-			    else
-			      {
-				as_bad (_("invalid register list"));
-				break;
-			      }
-			  }
-			reg2 = 0;
-			while (ISDIGIT (*s))
-			  {
-			    reg2 *= 10;
-			    reg2 += *s - '0';
-			    ++s;
+			    as_bad (_("invalid register list"));
+			    break;
 			  }
 		      }
 		    if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
@@ -9896,46 +10235,33 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 			continue;
 		      }
 
-		    if (*s != '$')
+		    if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
 		      {
 			as_bad (_("can't parse register list"));
 			break;
 		      }
-		    ++s;
 
-		    reg1 = 0;
-		    while (ISDIGIT (*s))
-		      {
-			reg1 *= 10;
-			reg1 += *s - '0';
-			++s;
-		      }
-		    SKIP_SPACE_TABS (s);
+		    while (*s == ' ')
+		      ++s;
+
 		    if (*s != '-')
 		      reg2 = reg1;
 		    else
 		      {
 			++s;
-			if (*s != '$')
+			if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
+			    || reg2 < reg1)
 			  {
 			    as_bad (_("can't parse register list"));
 			    break;
 			  }
-			++s;
-			reg2 = 0;
-			while (ISDIGIT (*s))
-			  {
-			    reg2 *= 10;
-			    reg2 += *s - '0';
-			    ++s;
-			  }
 		      }
 
 		    while (reg1 <= reg2)
 		      {
 			if (reg1 >= 4 && reg1 <= 7)
 			  {
-			    if (c == 'm' && !seen_framesz)
+			    if (!seen_framesz)
 				/* args $a0-$a3 */
 				args |= 1 << (reg1 - 4);
 			    else
@@ -10147,7 +10473,7 @@ mips16_immed (char *file, unsigned int line, int type, offsetT val,
 	      unsigned long *insn, bfd_boolean *use_extend,
 	      unsigned short *extend)
 {
-  register const struct mips16_immed_operand *op;
+  const struct mips16_immed_operand *op;
   int mintiny, maxtiny;
   bfd_boolean needext;
 
@@ -10557,9 +10883,17 @@ struct option md_longopts[] =
   {"mmt", no_argument, NULL, OPTION_MT},
 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
   {"mno-mt", no_argument, NULL, OPTION_NO_MT},
+#define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
+  {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
+#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
+  {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
+#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
+  {"mdspr2", no_argument, NULL, OPTION_DSPR2},
+#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
+  {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
 
   /* Old-style architecture options.  Don't add more of these.  */
-#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
+#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
   {"m4650", no_argument, NULL, OPTION_M4650},
 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
@@ -10711,7 +11045,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case 'O':
-      if (arg && arg[1] == '0')
+      if (arg && arg[0] == '0')
 	mips_optimize = 1;
       else
 	mips_optimize = 2;
@@ -10722,11 +11056,6 @@ md_parse_option (int c, char *arg)
 	mips_debug = 2;
       else
 	mips_debug = atoi (arg);
-      /* When the MIPS assembler sees -g or -g2, it does not do
-         optimizations which limit full symbolic debugging.  We take
-         that to be equivalent to -O0.  */
-      if (mips_debug == 2)
-	mips_optimize = 1;
       break;
 
     case OPTION_MIPS1:
@@ -10815,10 +11144,22 @@ md_parse_option (int c, char *arg)
 
     case OPTION_DSP:
       mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
       break;
 
     case OPTION_NO_DSP:
       mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+      break;
+
+    case OPTION_DSPR2:
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+      break;
+
+    case OPTION_NO_DSPR2:
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
       break;
 
     case OPTION_MT:
@@ -10847,6 +11188,14 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mips3d = 0;
       break;
 
+    case OPTION_SMARTMIPS:
+      mips_opts.ase_smartmips = 1;
+      break;
+
+    case OPTION_NO_SMARTMIPS:
+      mips_opts.ase_smartmips = 0;
+      break;
+
     case OPTION_FIX_VR4120:
       mips_fix_vr4120 = 1;
       break;
@@ -10892,7 +11241,7 @@ md_parse_option (int c, char *arg)
 	 select SVR4_PIC, and -non_shared to select no PIC.  This is
 	 intended to be compatible with Irix 5.  */
     case OPTION_CALL_SHARED:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-call_shared is supported only for ELF format"));
 	  return 0;
@@ -10902,7 +11251,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_NON_SHARED:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-non_shared is supported only for ELF format"));
 	  return 0;
@@ -10928,7 +11277,7 @@ md_parse_option (int c, char *arg)
       /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
 	 and -mabi=64.  */
     case OPTION_32:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-32 is supported for ELF format only"));
 	  return 0;
@@ -10937,7 +11286,7 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_N32:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-n32 is supported for ELF format only"));
 	  return 0;
@@ -10946,13 +11295,13 @@ md_parse_option (int c, char *arg)
       break;
 
     case OPTION_64:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-64 is supported for ELF format only"));
 	  return 0;
 	}
       mips_abi = N64_ABI;
-      if (! support_64bit_objects())
+      if (!support_64bit_objects())
 	as_fatal (_("No compiled in support for 64 bit object file format"));
       break;
 #endif /* OBJ_ELF */
@@ -10975,7 +11324,7 @@ md_parse_option (int c, char *arg)
 
 #ifdef OBJ_ELF
     case OPTION_MABI:
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  as_bad (_("-mabi is supported for ELF format only"));
 	  return 0;
@@ -11147,14 +11496,43 @@ mips_after_parse_args (void)
 			|| !ISA_HAS_64BIT_REGS (mips_opts.isa));
     }
 
-  /* ??? GAS treats single-float processors as though they had 64-bit
-     float registers (although it complains when double-precision
-     instructions are used).  As things stand, saying they have 32-bit
-     registers would lead to spurious "register must be even" messages.
-     So here we assume float registers are always the same size as
-     integer ones, unless the user says otherwise.  */
-  if (file_mips_fp32 < 0)
-    file_mips_fp32 = file_mips_gp32;
+  switch (file_mips_fp32)
+    {
+    default:
+    case -1:
+      /* No user specified float register size.
+	 ??? GAS treats single-float processors as though they had 64-bit
+	 float registers (although it complains when double-precision
+	 instructions are used).  As things stand, saying they have 32-bit
+	 registers would lead to spurious "register must be even" messages.
+	 So here we assume float registers are never smaller than the
+	 integer ones.  */
+      if (file_mips_gp32 == 0)
+	/* 64-bit integer registers implies 64-bit float registers.  */
+	file_mips_fp32 = 0;
+      else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
+	       && ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	/* -mips3d and -mdmx imply 64-bit float registers, if possible.  */
+	file_mips_fp32 = 0;
+      else
+	/* 32-bit float registers.  */
+	file_mips_fp32 = 1;
+      break;
+
+    /* The user specified the size of the float registers.  Check if it
+       agrees with the ABI and ISA.  */
+    case 0:
+      if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	as_bad (_("-mfp64 used with a 32-bit fpu"));
+      else if (ABI_NEEDS_32BIT_REGS (mips_abi)
+	       && !ISA_HAS_MXHC1 (mips_opts.isa))
+	as_warn (_("-mfp64 used with a 32-bit ABI"));
+      break;
+    case 1:
+      if (ABI_NEEDS_64BIT_REGS (mips_abi))
+	as_warn (_("-mfp32 used with a 64-bit ABI"));
+      break;
+    }
 
   /* End of GCC-shared inference code.  */
 
@@ -11173,19 +11551,51 @@ mips_after_parse_args (void)
   if (mips_opts.mips16 == -1)
     mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
   if (mips_opts.ase_mips3d == -1)
-    mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
+			    && file_mips_fp32 == 0) ? 1 : 0;
+  if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
+    as_bad (_("-mfp32 used with -mips3d"));
+
   if (mips_opts.ase_mdmx == -1)
-    mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
+			  && file_mips_fp32 == 0) ? 1 : 0;
+  if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
+    as_bad (_("-mfp32 used with -mdmx"));
+
+  if (mips_opts.ase_smartmips == -1)
+    mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
+  if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
+      as_warn ("%s ISA does not support SmartMIPS", 
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   if (mips_opts.ase_dsp == -1)
-    mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+  if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
+      as_warn ("%s ISA does not support DSP ASE", 
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
+  if (mips_opts.ase_dspr2 == -1)
+    {
+      mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
+      mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+    }
+  if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
+      as_warn ("%s ISA does not support DSP R2 ASE",
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   if (mips_opts.ase_mt == -1)
-    mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
+    mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
+  if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
+      as_warn ("%s ISA does not support MT ASE",
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
 
   file_mips_isa = mips_opts.isa;
   file_ase_mips16 = mips_opts.mips16;
   file_ase_mips3d = mips_opts.ase_mips3d;
   file_ase_mdmx = mips_opts.ase_mdmx;
+  file_ase_smartmips = mips_opts.ase_smartmips;
   file_ase_dsp = mips_opts.ase_dsp;
+  file_ase_dspr2 = mips_opts.ase_dspr2;
   file_ase_mt = mips_opts.ase_mt;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
@@ -11220,6 +11630,10 @@ md_pcrel_from (fixS *fixP)
       /* Return the address of the delay slot.  */
       return addr + 4;
     default:
+      /* We have no relocation type for PC relative MIPS16 instructions.  */
+      if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("PC relative MIPS16 instruction references a different section"));
       return addr;
     }
 }
@@ -11402,11 +11816,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  || fixP->fx_r_type == BFD_RELOC_CTOR
 	  || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
 	  || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
-	  || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
+	  || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+	  || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
 
   buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
 
-  assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
+  assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
 
   /* Don't treat parts of a composite relocation as done.  There are two
      reasons for this:
@@ -11418,13 +11833,15 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	 constants.  The easiest way of dealing with the pathological
 	 exceptions is to generate a relocation against STN_UNDEF and
 	 leave everything up to the linker.  */
-  if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
+  if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
     fixP->fx_done = 1;
 
   switch (fixP->fx_r_type)
     {
     case BFD_RELOC_MIPS_TLS_GD:
     case BFD_RELOC_MIPS_TLS_LDM:
+    case BFD_RELOC_MIPS_TLS_DTPREL32:
+    case BFD_RELOC_MIPS_TLS_DTPREL64:
     case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
     case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
     case BFD_RELOC_MIPS_TLS_GOTTPREL:
@@ -11463,14 +11880,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_MIPS16_GPREL:
     case BFD_RELOC_MIPS16_HI16:
     case BFD_RELOC_MIPS16_HI16_S:
-      /* Nothing needed to do. The value comes from the reloc entry */
-      break;
-
     case BFD_RELOC_MIPS16_JMP:
-      /* We currently always generate a reloc against a symbol, which
-         means that we don't want an addend even if the symbol is
-         defined.  */
-      *valP = 0;
+      /* Nothing needed to do.  The value comes from the reloc entry.  */
       break;
 
     case BFD_RELOC_64:
@@ -11498,18 +11909,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
     case BFD_RELOC_RVA:
     case BFD_RELOC_32:
-      /* If we are deleting this reloc entry, we must fill in the
-	 value now.  This can happen if we have a .word which is not
-	 resolved when it appears but is later defined.   */
-      if (fixP->fx_done)
-	md_number_to_chars ((char *) buf, *valP, 4);
-      break;
-
     case BFD_RELOC_16:
       /* If we are deleting this reloc entry, we must fill in the
-         value now.  */
+	 value now.  This can happen if we have a .word which is not
+	 resolved when it appears but is later defined.  */
       if (fixP->fx_done)
-	md_number_to_chars ((char *) buf, *valP, 2);
+	md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
       break;
 
     case BFD_RELOC_LO16:
@@ -11534,15 +11939,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
 		      _("Branch to misaligned address (%lx)"), (long) *valP);
 
-      /*
-       * We need to save the bits in the instruction since fixup_segment()
-       * might be deleting the relocation entry (i.e., a branch within
-       * the current segment).
-       */
+      /* We need to save the bits in the instruction since fixup_segment()
+	 might be deleting the relocation entry (i.e., a branch within
+	 the current segment).  */
       if (! fixP->fx_done)
 	break;
 
-      /* update old instruction data */
+      /* Update old instruction data.  */
       if (target_big_endian)
 	insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
       else
@@ -11642,21 +12045,17 @@ mips_align (int to, int fill, symbolS *label)
 static void
 s_align (int x ATTRIBUTE_UNUSED)
 {
-  register int temp;
-  register long temp_fill;
+  int temp;
+  long temp_fill;
   long max_alignment = 15;
 
-  /*
-
-    o  Note that the assembler pulls down any immediately preceding label
+  /* o Note that the assembler pulls down any immediately preceding label
        to the aligned address.
-    o  It's not documented but auto alignment is reinstated by
+     o It's not documented but auto alignment is reinstated by
        a .align pseudo instruction.
-    o  Note also that after auto alignment is turned off the mips assembler
+     o Note also that after auto alignment is turned off the mips assembler
        issues an error on attempt to assemble an improperly aligned data item.
-       We don't.
-
-    */
+       We don't.  */
 
   temp = get_absolute_expression ();
   if (temp > max_alignment)
@@ -11675,9 +12074,11 @@ s_align (int x ATTRIBUTE_UNUSED)
     temp_fill = 0;
   if (temp)
     {
+      segment_info_type *si = seg_info (now_seg);
+      struct insn_label_list *l = si->label_list;
+      /* Auto alignment should be switched on by next section change.  */
       auto_align = 1;
-      mips_align (temp, (int) temp_fill,
-		  insn_labels != NULL ? insn_labels->label : NULL);
+      mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL);
     }
   else
     {
@@ -11699,7 +12100,8 @@ s_change_sec (int sec)
      as it would not be appropriate to use it in the section changing
      functions in read.c, since obj-elf.c intercepts those.  FIXME:
      This should be cleaner, somehow.  */
-  obj_elf_section_change_hook ();
+  if (IS_ELF)
+    obj_elf_section_change_hook ();
 #endif
 
   mips_emit_delays ();
@@ -11719,7 +12121,7 @@ s_change_sec (int sec)
     case 'r':
       seg = subseg_new (RDATA_SECTION_NAME,
 			(subsegT) get_absolute_expression ());
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+      if (IS_ELF)
 	{
 	  bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
 						  | SEC_READONLY | SEC_RELOC
@@ -11732,7 +12134,7 @@ s_change_sec (int sec)
 
     case 's':
       seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+      if (IS_ELF)
 	{
 	  bfd_set_section_flags (stdoutput, seg,
 				 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
@@ -11758,7 +12160,7 @@ s_change_section (int ignore ATTRIBUTE_UNUSED)
   int section_entry_size;
   int section_alignment;
 
-  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+  if (!IS_ELF)
     return;
 
   section_name = input_line_pointer;
@@ -11803,7 +12205,7 @@ s_change_section (int ignore ATTRIBUTE_UNUSED)
 
      There's nothing really harmful in this, since bfd will correct
      SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file.  But it
-     means that, for backwards compatibiltiy, the special_section entries
+     means that, for backwards compatibility, the special_section entries
      for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
 
      Even so, we shouldn't force users of the MIPS .section syntax to
@@ -11830,9 +12232,11 @@ mips_enable_auto_align (void)
 static void
 s_cons (int log_size)
 {
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l = si->label_list;
   symbolS *label;
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (log_size > 0 && auto_align)
     mips_align (log_size, 0, label);
@@ -11843,9 +12247,11 @@ s_cons (int log_size)
 static void
 s_float_cons (int type)
 {
+  segment_info_type *si = seg_info (now_seg);
+  struct insn_label_list *l = si->label_list;
   symbolS *label;
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  label = l != NULL ? l->label : NULL;
 
   mips_emit_delays ();
 
@@ -12032,12 +12438,43 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     {
       mips_opts.nobopt = 1;
     }
+  else if (strcmp (name, "gp=default") == 0)
+    mips_opts.gp32 = file_mips_gp32;
+  else if (strcmp (name, "gp=32") == 0)
+    mips_opts.gp32 = 1;
+  else if (strcmp (name, "gp=64") == 0)
+    {
+      if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
+	as_warn ("%s isa does not support 64-bit registers",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.gp32 = 0;
+    }
+  else if (strcmp (name, "fp=default") == 0)
+    mips_opts.fp32 = file_mips_fp32;
+  else if (strcmp (name, "fp=32") == 0)
+    mips_opts.fp32 = 1;
+  else if (strcmp (name, "fp=64") == 0)
+    {
+      if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
+	as_warn ("%s isa does not support 64-bit floating point registers",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.fp32 = 0;
+    }
   else if (strcmp (name, "mips16") == 0
 	   || strcmp (name, "MIPS-16") == 0)
     mips_opts.mips16 = 1;
   else if (strcmp (name, "nomips16") == 0
 	   || strcmp (name, "noMIPS-16") == 0)
     mips_opts.mips16 = 0;
+  else if (strcmp (name, "smartmips") == 0)
+    {
+      if (!ISA_SUPPORTS_SMARTMIPS)
+	as_warn ("%s ISA does not support SmartMIPS ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_smartmips = 1;
+    }
+  else if (strcmp (name, "nosmartmips") == 0)
+    mips_opts.ase_smartmips = 0;
   else if (strcmp (name, "mips3d") == 0)
     mips_opts.ase_mips3d = 1;
   else if (strcmp (name, "nomips3d") == 0)
@@ -12047,11 +12484,38 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
   else if (strcmp (name, "nomdmx") == 0)
     mips_opts.ase_mdmx = 0;
   else if (strcmp (name, "dsp") == 0)
-    mips_opts.ase_dsp = 1;
+    {
+      if (!ISA_SUPPORTS_DSP_ASE)
+	as_warn ("%s ISA does not support DSP ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
+    }
   else if (strcmp (name, "nodsp") == 0)
-    mips_opts.ase_dsp = 0;
+    {
+      mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+    }
+  else if (strcmp (name, "dspr2") == 0)
+    {
+      if (!ISA_SUPPORTS_DSPR2_ASE)
+	as_warn ("%s ISA does not support DSP R2 ASE",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+    }
+  else if (strcmp (name, "nodspr2") == 0)
+    {
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
+    }
   else if (strcmp (name, "mt") == 0)
-    mips_opts.ase_mt = 1;
+    {
+      if (!ISA_SUPPORTS_MT_ASE)
+	as_warn ("%s ISA does not support MT ASE", 
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_mt = 1;
+    }
   else if (strcmp (name, "nomt") == 0)
     mips_opts.ase_mt = 0;
   else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
@@ -12162,6 +12626,14 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     mips_opts.sym32 = TRUE;
   else if (strcmp (name, "nosym32") == 0)
     mips_opts.sym32 = FALSE;
+  else if (strchr (name, ','))
+    {
+      /* Generic ".set" directive; use the generic handler.  */
+      *input_line_pointer = ch;
+      input_line_pointer = name;
+      s_set (0);
+      return;
+    }
   else
     {
       as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
@@ -12269,8 +12741,7 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
 
    The -mno-shared option replaces the last three instructions with
 	lui	$gp,%hi(_gp)
-	addiu	$gp,$gp,%lo(_gp)
-   */
+	addiu	$gp,$gp,%lo(_gp)  */
 
 static void
 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
@@ -12372,7 +12843,7 @@ static void
 s_cplocal (int ignore ATTRIBUTE_UNUSED)
 {
   /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
-   .cplocal is ignored.  */
+     .cplocal is ignored.  */
   if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
     {
       s_ignore (0);
@@ -12421,8 +12892,8 @@ s_cprestore (int ignore ATTRIBUTE_UNUSED)
      ld		$gp, offset($sp)
 
    If a register $reg2 was given there, it results in:
-     daddu	$gp, $reg2, $0
- */
+     daddu	$gp, $reg2, $0  */
+
 static void
 s_cpreturn (int ignore ATTRIBUTE_UNUSED)
 {
@@ -12454,6 +12925,52 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+/* Handle the .dtprelword and .dtpreldword pseudo-ops.  They generate
+   a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
+   use in DWARF debug information.  */
+
+static void
+s_dtprel_internal (size_t bytes)
+{
+  expressionS ex;
+  char *p;
+
+  expression (&ex);
+
+  if (ex.X_op != O_symbol)
+    {
+      as_bad (_("Unsupported use of %s"), (bytes == 8
+					   ? ".dtpreldword"
+					   : ".dtprelword"));
+      ignore_rest_of_line ();
+    }
+
+  p = frag_more (bytes);
+  md_number_to_chars (p, 0, bytes);
+  fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
+	       (bytes == 8
+		? BFD_RELOC_MIPS_TLS_DTPREL64
+		: BFD_RELOC_MIPS_TLS_DTPREL32));
+
+  demand_empty_rest_of_line ();
+}
+
+/* Handle .dtprelword.  */
+
+static void
+s_dtprelword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_dtprel_internal (4);
+}
+
+/* Handle .dtpreldword.  */
+
+static void
+s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
+{
+  s_dtprel_internal (8);
+}
+
 /* Handle the .gpvalue pseudo-op.  This is used when generating NewABI PIC
    code.  It sets the offset to use in gp_rel relocations.  */
 
@@ -12479,6 +12996,8 @@ s_gpvalue (int ignore ATTRIBUTE_UNUSED)
 static void
 s_gpword (int ignore ATTRIBUTE_UNUSED)
 {
+  segment_info_type *si;
+  struct insn_label_list *l;
   symbolS *label;
   expressionS ex;
   char *p;
@@ -12490,7 +13009,9 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
       return;
     }
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  si = seg_info (now_seg);
+  l = si->label_list;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (auto_align)
     mips_align (2, 0, label);
@@ -12515,6 +13036,8 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
 static void
 s_gpdword (int ignore ATTRIBUTE_UNUSED)
 {
+  segment_info_type *si;
+  struct insn_label_list *l;
   symbolS *label;
   expressionS ex;
   char *p;
@@ -12526,7 +13049,9 @@ s_gpdword (int ignore ATTRIBUTE_UNUSED)
       return;
     }
 
-  label = insn_labels != NULL ? insn_labels->label : NULL;
+  si = seg_info (now_seg);
+  l = si->label_list;
+  label = l != NULL ? l->label : NULL;
   mips_emit_delays ();
   if (auto_align)
     mips_align (3, 0, label);
@@ -12608,8 +13133,7 @@ s_mips_stab (int type)
   s_stab (type);
 }
 
-/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
- */
+/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.  */
 
 static void
 s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
@@ -12663,73 +13187,11 @@ s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
 int
 tc_get_register (int frame)
 {
-  int reg;
+  unsigned int reg;
 
   SKIP_WHITESPACE ();
-  if (*input_line_pointer++ != '$')
-    {
-      as_warn (_("expected `$'"));
-      reg = ZERO;
-    }
-  else if (ISDIGIT (*input_line_pointer))
-    {
-      reg = get_absolute_expression ();
-      if (reg < 0 || reg >= 32)
-	{
-	  as_warn (_("Bad register number"));
-	  reg = ZERO;
-	}
-    }
-  else
-    {
-      if (strncmp (input_line_pointer, "ra", 2) == 0)
-	{
-	  reg = RA;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "fp", 2) == 0)
-	{
-	  reg = FP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "sp", 2) == 0)
-	{
-	  reg = SP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "gp", 2) == 0)
-	{
-	  reg = GP;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "at", 2) == 0)
-	{
-	  reg = AT;
-	  input_line_pointer += 2;
-	}
-      else if (strncmp (input_line_pointer, "kt0", 3) == 0)
-	{
-	  reg = KT0;
-	  input_line_pointer += 3;
-	}
-      else if (strncmp (input_line_pointer, "kt1", 3) == 0)
-	{
-	  reg = KT1;
-	  input_line_pointer += 3;
-	}
-      else if (strncmp (input_line_pointer, "zero", 4) == 0)
-	{
-	  reg = ZERO;
-	  input_line_pointer += 4;
-	}
-      else
-	{
-	  as_warn (_("Unrecognized register name"));
-	  reg = ZERO;
-	  while (ISALNUM(*input_line_pointer))
-	   input_line_pointer++;
-	}
-    }
+  if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
+    reg = 0;
   if (frame)
     {
       mips_frame_reg = reg != 0 ? reg : SP;
@@ -12744,16 +13206,17 @@ md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
 
-#ifdef OBJ_ELF
-  /* We don't need to align ELF sections to the full alignment.
-     However, Irix 5 may prefer that we align them at least to a 16
-     byte boundary.  We don't bother to align the sections if we are
-     targeted for an embedded system.  */
-  if (strcmp (TARGET_OS, "elf") == 0)
-    return addr;
-  if (align > 4)
-    align = 4;
-#endif
+  if (IS_ELF)
+    {
+      /* We don't need to align ELF sections to the full alignment.
+	 However, Irix 5 may prefer that we align them at least to a 16
+	 byte boundary.  We don't bother to align the sections if we
+	 are targeted for an embedded system.  */
+      if (strcmp (TARGET_OS, "elf") == 0)
+        return addr;
+      if (align > 4)
+        align = 4;
+    }
 
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
@@ -12819,6 +13282,8 @@ nopic_need_relax (symbolS *sym, int before_relaxing)
 	  change = (strcmp (segname, ".sdata") != 0
 		    && strcmp (segname, ".sbss") != 0
 		    && strncmp (segname, ".sdata.", 7) != 0
+		    && strncmp (segname, ".sbss.", 6) != 0
+		    && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
 		    && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
 	}
       return change;
@@ -12835,48 +13300,32 @@ static bfd_boolean
 pic_need_relax (symbolS *sym, asection *segtype)
 {
   asection *symsec;
-  bfd_boolean linkonce;
 
   /* Handle the case of a symbol equated to another symbol.  */
   while (symbol_equated_reloc_p (sym))
     {
       symbolS *n;
 
-      /* It's possible to get a loop here in a badly written
-	 program.  */
+      /* It's possible to get a loop here in a badly written program.  */
       n = symbol_get_value_expression (sym)->X_add_symbol;
       if (n == sym)
 	break;
       sym = n;
     }
 
-  symsec = S_GET_SEGMENT (sym);
-
-  /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
-  linkonce = FALSE;
-  if (symsec != segtype && ! S_IS_LOCAL (sym))
-    {
-      if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
-	  != 0)
-	linkonce = TRUE;
+  if (symbol_section_p (sym))
+    return TRUE;
 
-      /* The GNU toolchain uses an extension for ELF: a section
-	 beginning with the magic string .gnu.linkonce is a linkonce
-	 section.  */
-      if (strncmp (segment_name (symsec), ".gnu.linkonce",
-		   sizeof ".gnu.linkonce" - 1) == 0)
-	linkonce = TRUE;
-    }
+  symsec = S_GET_SEGMENT (sym);
 
   /* This must duplicate the test in adjust_reloc_syms.  */
   return (symsec != &bfd_und_section
 	  && symsec != &bfd_abs_section
-	  && ! bfd_is_com_section (symsec)
-	  && !linkonce
+	  && !bfd_is_com_section (symsec)
+	  && !s_is_linkonce (sym, segtype)
 #ifdef OBJ_ELF
 	  /* A global or weak symbol is treated as external.  */
-	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
-	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
+	  && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
 #endif
 	  );
 }
@@ -12889,7 +13338,7 @@ static int
 mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
 {
   int type;
-  register const struct mips16_immed_operand *op;
+  const struct mips16_immed_operand *op;
   offsetT val;
   int mintiny, maxtiny;
   segT symsec;
@@ -13192,11 +13641,6 @@ md_estimate_size_before_relax (fragS *fragp, asection *segtype)
 int
 mips_fix_adjustable (fixS *fixp)
 {
-  /* Don't adjust MIPS16 jump relocations, so we don't have to worry
-     about the format of the offset in the .o file. */
-  if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
-    return 0;
-
   if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 0;
@@ -13226,11 +13670,50 @@ mips_fix_adjustable (fixS *fixp)
     return 0;
 
 #ifdef OBJ_ELF
-  /* Don't adjust relocations against mips16 symbols, so that the linker
-     can find them if it needs to set up a stub.  */
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-      && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
-      && fixp->fx_subsy == NULL)
+  /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
+     to a floating-point stub.  The same is true for non-R_MIPS16_26
+     relocations against MIPS16 functions; in this case, the stub becomes
+     the function's canonical address.
+
+     Floating-point stubs are stored in unique .mips16.call.* or
+     .mips16.fn.* sections.  If a stub T for function F is in section S,
+     the first relocation in section S must be against F; this is how the
+     linker determines the target function.  All relocations that might
+     resolve to T must also be against F.  We therefore have the following
+     restrictions, which are given in an intentionally-redundant way:
+
+       1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
+	  symbols.
+
+       2. We cannot reduce a stub's relocations against non-MIPS16 symbols
+	  if that stub might be used.
+
+       3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
+	  symbols.
+
+       4. We cannot reduce a stub's relocations against MIPS16 symbols if
+	  that stub might be used.
+
+     There is a further restriction:
+
+       5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
+	  on targets with in-place addends; the relocation field cannot
+	  encode the low bit.
+
+     For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
+     against a MIPS16 symbol.
+
+     We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
+     relocation against some symbol R, no relocation against R may be
+     reduced.  (Note that this deals with (2) as well as (1) because
+     relocations against global symbols will never be reduced on ELF
+     targets.)  This approach is a little simpler than trying to detect
+     stub sections, and gives the "all or nothing" per-symbol consistency
+     that we have for MIPS16 symbols.  */
+  if (IS_ELF
+      && fixp->fx_subsy == NULL
+      && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
+	  || *symbol_get_tc (fixp->fx_addsy)))
     return 0;
 #endif
 
@@ -13260,7 +13743,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
       /* At this point, fx_addnumber is "symbol offset - pcrel address".
 	 Relocations want only the symbol offset.  */
       reloc->addend = fixp->fx_addnumber + reloc->address;
-      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+      if (!IS_ELF)
 	{
 	  /* A gruesome hack which is a result of the gruesome gas
 	     reloc handling.  What's worse, for COFF (as opposed to
@@ -13359,7 +13842,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  exp.X_add_number = fragp->fr_offset;
 
 	  fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-			      4, &exp, 1, BFD_RELOC_16_PCREL_S2);
+			      4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
 	  fixp->fx_file = fragp->fr_file;
 	  fixp->fx_line = fragp->fr_line;
 
@@ -13391,14 +13874,14 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 
 		case 0:
 		  /* bltz	0x04000000	bgez	0x04010000
-		     bltzal	0x04100000	bgezal	0x04110000 */
+		     bltzal	0x04100000	bgezal	0x04110000  */
 		  assert ((insn & 0xfc0e0000) == 0x04000000);
 		  insn ^= 0x00010000;
 		  break;
 
 		case 1:
 		  /* beq	0x10000000	bne	0x14000000
-		     blez	0x18000000	bgtz	0x1c000000 */
+		     blez	0x18000000	bgtz	0x1c000000  */
 		  insn ^= 0x04000000;
 		  break;
 
@@ -13412,8 +13895,8 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      /* Clear the and-link bit.  */
 	      assert ((insn & 0xfc1c0000) == 0x04100000);
 
-	      /* bltzal	0x04100000	bgezal	0x04110000
-		bltzall	0x04120000     bgezall	0x04130000 */
+	      /* bltzal		0x04100000	bgezal	0x04110000
+		 bltzall	0x04120000	bgezall	0x04130000  */
 	      insn &= ~0x00100000;
 	    }
 
@@ -13438,7 +13921,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  md_number_to_chars ((char *) buf, insn, 4);
 	  buf += 4;
 
-	  /* Nop */
+	  /* nop */
 	  md_number_to_chars ((char *) buf, 0, 4);
 	  buf += 4;
 
@@ -13476,7 +13959,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      exp.X_add_number = fragp->fr_offset;
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_MIPS_JMP);
+				  4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13498,7 +13981,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 		}
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_MIPS_GOT16);
+				  4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13516,7 +13999,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
 
 	      fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-				  4, &exp, 0, BFD_RELOC_LO16);
+				  4, &exp, FALSE, BFD_RELOC_LO16);
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
@@ -13545,7 +14028,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
   if (RELAX_MIPS16_P (fragp->fr_subtype))
     {
       int type;
-      register const struct mips16_immed_operand *op;
+      const struct mips16_immed_operand *op;
       bfd_boolean small, ext;
       offsetT val;
       bfd_byte *buf;
@@ -13699,7 +14182,7 @@ mips_frob_file_after_relocs (void)
   asymbol **syms;
   unsigned int count, i;
 
-  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+  if (!IS_ELF)
     return;
 
   syms = bfd_get_outsymbols (stdoutput);
@@ -13727,6 +14210,7 @@ mips_frob_file_after_relocs (void)
 void
 mips_define_label (symbolS *sym)
 {
+  segment_info_type *si = seg_info (now_seg);
   struct insn_label_list *l;
 
   if (free_insn_labels == NULL)
@@ -13738,8 +14222,8 @@ mips_define_label (symbolS *sym)
     }
 
   l->label = sym;
-  l->next = insn_labels;
-  insn_labels = l;
+  l->next = si->label_list;
+  si->label_list = l;
 
 #ifdef OBJ_ELF
   dwarf2_emit_label (sym);
@@ -13801,6 +14285,7 @@ mips_elf_final_processing (void)
   /* Set MIPS ELF flags for ASEs.  */
   /* We may need to define a new flag for DSP ASE, and set this flag when
      file_ase_dsp is true.  */
+  /* Same for DSP R2.  */
   /* We may need to define a new flag for MT ASE, and set this flag when
      file_ase_mt is true.  */
   if (file_ase_mips16)
@@ -13831,6 +14316,12 @@ mips_elf_final_processing (void)
 
   if (mips_32bitmode)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
+
+#if 0 /* XXX FIXME */
+  /* 32 bit code with 64 bit FP registers.  */
+  if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
+    elf_elfheader (stdoutput)->e_flags |= ???;
+#endif
 }
 
 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
@@ -13891,7 +14382,7 @@ md_obj_begin (void)
 static void
 md_obj_end (void)
 {
-  /* check for premature end, nesting errors, etc */
+  /* Check for premature end, nesting errors, etc.  */
   if (cur_proc_ptr)
     as_warn (_("missing .end at end of assembly"));
 }
@@ -14048,8 +14539,7 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
     }
 
   /* Generate a .pdr section.  */
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
-      && mips_flag_pdr)
+  if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
     {
       segT saved_seg = now_seg;
       subsegT saved_subseg = now_subseg;
@@ -14143,7 +14633,7 @@ static void
 s_mips_frame (int ignore ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_ELF
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+  if (IS_ELF && !ECOFF_DEBUGGING)
     {
       long val;
 
@@ -14186,7 +14676,7 @@ static void
 s_mips_mask (int reg_type)
 {
 #ifdef OBJ_ELF
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
+  if (IS_ELF && !ECOFF_DEBUGGING)
     {
       long mask, off;
 
@@ -14233,72 +14723,102 @@ s_mips_mask (int reg_type)
 static const struct mips_cpu_info mips_cpu_info_table[] =
 {
   /* Entries for generic ISAs */
-  { "mips1",          1,      ISA_MIPS1,      CPU_R3000 },
-  { "mips2",          1,      ISA_MIPS2,      CPU_R6000 },
-  { "mips3",          1,      ISA_MIPS3,      CPU_R4000 },
-  { "mips4",          1,      ISA_MIPS4,      CPU_R8000 },
-  { "mips5",          1,      ISA_MIPS5,      CPU_MIPS5 },
-  { "mips32",         1,      ISA_MIPS32,     CPU_MIPS32 },
-  { "mips32r2",       1,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "mips64",         1,      ISA_MIPS64,     CPU_MIPS64 },
-  { "mips64r2",       1,      ISA_MIPS64R2,   CPU_MIPS64R2 },
+  { "mips1",          MIPS_CPU_IS_ISA,		ISA_MIPS1,      CPU_R3000 },
+  { "mips2",          MIPS_CPU_IS_ISA,		ISA_MIPS2,      CPU_R6000 },
+  { "mips3",          MIPS_CPU_IS_ISA,		ISA_MIPS3,      CPU_R4000 },
+  { "mips4",          MIPS_CPU_IS_ISA,		ISA_MIPS4,      CPU_R8000 },
+  { "mips5",          MIPS_CPU_IS_ISA,		ISA_MIPS5,      CPU_MIPS5 },
+  { "mips32",         MIPS_CPU_IS_ISA,		ISA_MIPS32,     CPU_MIPS32 },
+  { "mips32r2",       MIPS_CPU_IS_ISA,		ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "mips64",         MIPS_CPU_IS_ISA,		ISA_MIPS64,     CPU_MIPS64 },
+  { "mips64r2",       MIPS_CPU_IS_ISA,		ISA_MIPS64R2,   CPU_MIPS64R2 },
 
   /* MIPS I */
-  { "r3000",          0,      ISA_MIPS1,      CPU_R3000 },
-  { "r2000",          0,      ISA_MIPS1,      CPU_R3000 },
-  { "r3900",          0,      ISA_MIPS1,      CPU_R3900 },
+  { "r3000",          0,			ISA_MIPS1,      CPU_R3000 },
+  { "r2000",          0,			ISA_MIPS1,      CPU_R3000 },
+  { "r3900",          0,			ISA_MIPS1,      CPU_R3900 },
 
   /* MIPS II */
-  { "r6000",          0,      ISA_MIPS2,      CPU_R6000 },
+  { "r6000",          0,			ISA_MIPS2,      CPU_R6000 },
 
   /* MIPS III */
-  { "r4000",          0,      ISA_MIPS3,      CPU_R4000 },
-  { "r4010",          0,      ISA_MIPS2,      CPU_R4010 },
-  { "vr4100",         0,      ISA_MIPS3,      CPU_VR4100 },
-  { "vr4111",         0,      ISA_MIPS3,      CPU_R4111 },
-  { "vr4120",         0,      ISA_MIPS3,      CPU_VR4120 },
-  { "vr4130",         0,      ISA_MIPS3,      CPU_VR4120 },
-  { "vr4181",         0,      ISA_MIPS3,      CPU_R4111 },
-  { "vr4300",         0,      ISA_MIPS3,      CPU_R4300 },
-  { "r4400",          0,      ISA_MIPS3,      CPU_R4400 },
-  { "r4600",          0,      ISA_MIPS3,      CPU_R4600 },
-  { "orion",          0,      ISA_MIPS3,      CPU_R4600 },
-  { "r4650",          0,      ISA_MIPS3,      CPU_R4650 },
+  { "r4000",          0,			ISA_MIPS3,      CPU_R4000 },
+  { "r4010",          0,			ISA_MIPS2,      CPU_R4010 },
+  { "vr4100",         0,			ISA_MIPS3,      CPU_VR4100 },
+  { "vr4111",         0,			ISA_MIPS3,      CPU_R4111 },
+  { "vr4120",         0,			ISA_MIPS3,      CPU_VR4120 },
+  { "vr4130",         0,			ISA_MIPS3,      CPU_VR4120 },
+  { "vr4181",         0,			ISA_MIPS3,      CPU_R4111 },
+  { "vr4300",         0,			ISA_MIPS3,      CPU_R4300 },
+  { "r4400",          0,			ISA_MIPS3,      CPU_R4400 },
+  { "r4600",          0,			ISA_MIPS3,      CPU_R4600 },
+  { "orion",          0,			ISA_MIPS3,      CPU_R4600 },
+  { "r4650",          0,			ISA_MIPS3,      CPU_R4650 },
 
   /* MIPS IV */
-  { "r8000",          0,      ISA_MIPS4,      CPU_R8000 },
-  { "r10000",         0,      ISA_MIPS4,      CPU_R10000 },
-  { "r12000",         0,      ISA_MIPS4,      CPU_R12000 },
-  { "vr5000",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "vr5400",         0,      ISA_MIPS4,      CPU_VR5400 },
-  { "vr5500",         0,      ISA_MIPS4,      CPU_VR5500 },
-  { "rm5200",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5230",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5231",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5261",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm5721",         0,      ISA_MIPS4,      CPU_R5000 },
-  { "rm7000",         0,      ISA_MIPS4,      CPU_RM7000 },
-  { "rm9000",         0,      ISA_MIPS4,      CPU_RM9000 },
+  { "r8000",          0,			ISA_MIPS4,      CPU_R8000 },
+  { "r10000",         0,			ISA_MIPS4,      CPU_R10000 },
+  { "r12000",         0,			ISA_MIPS4,      CPU_R12000 },
+  { "vr5000",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "vr5400",         0,			ISA_MIPS4,      CPU_VR5400 },
+  { "vr5500",         0,			ISA_MIPS4,      CPU_VR5500 },
+  { "rm5200",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5230",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5231",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5261",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm5721",         0,			ISA_MIPS4,      CPU_R5000 },
+  { "rm7000",         0,			ISA_MIPS4,      CPU_RM7000 },
+  { "rm9000",         0,			ISA_MIPS4,      CPU_RM9000 },
 
   /* MIPS 32 */
-  { "4kc",            0,      ISA_MIPS32,     CPU_MIPS32 },
-  { "4km",            0,      ISA_MIPS32,     CPU_MIPS32 },
-  { "4kp",            0,      ISA_MIPS32,     CPU_MIPS32 },
-
-  /* MIPS32 Release 2 */
-  { "m4k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kc",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kf",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
-  { "24kx",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kc",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4km",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4kp",            0,			ISA_MIPS32,	CPU_MIPS32 },
+  { "4ksc",           MIPS_CPU_ASE_SMARTMIPS,	ISA_MIPS32,	CPU_MIPS32 },
+
+  /* MIPS 32 Release 2 */
+  { "4kec",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kem",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4kep",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "4ksd",           MIPS_CPU_ASE_SMARTMIPS,	ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "m4k",            0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "m4kp",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kc",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kf",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kx",           0,			ISA_MIPS32R2,   CPU_MIPS32R2 },
+  /* 24KE is a 24K with DSP ASE, other ASEs are optional.  */
+  { "24kec",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "24kef",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "24kex",          MIPS_CPU_ASE_DSP,		ISA_MIPS32R2,	CPU_MIPS32R2 },
+  /* 34K is a 24K with DSP and MT ASE, other ASEs are optional.  */
+  { "34kc",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "34kf",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "34kx",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  /* 74K with DSP and DSPR2 ASE, other ASEs are optional.  */
+  { "74kc",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "74kf",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
+  { "74kx",           MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
+						ISA_MIPS32R2,	CPU_MIPS32R2 },
 
   /* MIPS 64 */
-  { "5kc",            0,      ISA_MIPS64,     CPU_MIPS64 },
-  { "5kf",            0,      ISA_MIPS64,     CPU_MIPS64 },
-  { "20kc",           0,      ISA_MIPS64,     CPU_MIPS64 },
+  { "5kc",            0,			ISA_MIPS64,	CPU_MIPS64 },
+  { "5kf",            0,			ISA_MIPS64,	CPU_MIPS64 },
+  { "20kc",           MIPS_CPU_ASE_MIPS3D,	ISA_MIPS64,	CPU_MIPS64 },
+  { "25kf",           MIPS_CPU_ASE_MIPS3D,	ISA_MIPS64,     CPU_MIPS64 },
+
+  /* MIPS 64 Release 2 */
 
   /* Broadcom SB-1 CPU core */
-  { "sb1",            0,      ISA_MIPS64,     CPU_SB1 },
+  { "sb1",            MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+						ISA_MIPS64,	CPU_SB1 },
+  /* Broadcom SB-1A CPU core */
+  { "sb1a",           MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
+						ISA_MIPS64,	CPU_SB1 },
 
   /* End marker */
   { NULL, 0, 0, 0 }
@@ -14413,7 +14933,7 @@ mips_cpu_info_from_isa (int isa)
   int i;
 
   for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
-    if (mips_cpu_info_table[i].is_isa
+    if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
 	&& isa == mips_cpu_info_table[i].isa)
       return (&mips_cpu_info_table[i]);
 
@@ -14507,9 +15027,15 @@ MIPS options:\n\
 -mips16			generate mips16 instructions\n\
 -no-mips16		do not generate mips16 instructions\n"));
   fprintf (stream, _("\
+-msmartmips		generate smartmips instructions\n\
+-mno-smartmips		do not generate smartmips instructions\n"));  
+  fprintf (stream, _("\
 -mdsp			generate DSP instructions\n\
 -mno-dsp		do not generate DSP instructions\n"));
   fprintf (stream, _("\
+-mdspr2			generate DSP R2 instructions\n\
+-mno-dspr2		do not generate DSP R2 instructions\n"));
+  fprintf (stream, _("\
 -mmt			generate MT instructions\n\
 -mno-mt			do not generate MT instructions\n"));
   fprintf (stream, _("\
@@ -14517,7 +15043,6 @@ MIPS options:\n\
 -mfix-vr4130		work around VR4130 mflo/mfhi errata\n\
 -mgp32			use 32-bit GPRs, regardless of the chosen ISA\n\
 -mfp32			use 32-bit FPRs, regardless of the chosen ISA\n\
--mno-shared		optimize output for executables\n\
 -msym32			assume all symbols have 32-bit values\n\
 -O0			remove unneeded NOPs, do not swap branches\n\
 -O			remove unneeded NOPs and swap branches\n\
@@ -14527,11 +15052,12 @@ MIPS options:\n\
 #ifdef OBJ_ELF
   fprintf (stream, _("\
 -KPIC, -call_shared	generate SVR4 position independent code\n\
+-mvxworks-pic		generate VxWorks position independent code\n\
 -non_shared		do not generate position independent code\n\
 -xgot			assume a 32 bit GOT\n\
 -mpdr, -mno-pdr		enable/disable creation of .pdr sections\n\
 -mshared, -mno-shared   disable/enable .cpload optimization for\n\
-                        non-shared code\n\
+                        position dependent (non shared) code\n\
 -mabi=ABI		create ABI conformant object file for:\n"));
 
   first = 1;
@@ -14582,3 +15108,14 @@ mips_cfi_frame_initial_instructions (void)
   cfi_add_CFA_def_cfa_register (SP);
 }
 
+int
+tc_mips_regname_to_dw2regnum (char *regname)
+{
+  unsigned int regnum = -1;
+  unsigned int reg;
+
+  if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
+    regnum = reg;
+
+  return regnum;
+}
diff --git a/gas/config/tc-mips.h b/gas/config/tc-mips.h
index 5665d3decdd7..117417cfed5f 100644
--- a/gas/config/tc-mips.h
+++ b/gas/config/tc-mips.h
@@ -1,6 +1,6 @@
 /* tc-mips.h -- header file for tc-mips.c.
-   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004
-   Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004,
+   2005, 2006 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF support by Ian Lance Taylor of Cygnus Support.
@@ -58,6 +58,12 @@ extern void mips_handle_align (struct frag *);
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2)
 
+struct insn_label_list;
+#define TC_SEGMENT_INFO_TYPE struct insn_label_list *
+
+/* This field is nonzero if the symbol is the target of a MIPS16 jump.  */
+#define TC_SYMFIELD_TYPE int
+
 /* Tell assembler that we have an itbl_mips.h header file to include.  */
 #define HAVE_ITBL_CPU
 
@@ -149,6 +155,7 @@ extern void mips_emit_delays (void);
 extern void mips_enable_auto_align (void);
 #define md_elf_section_change_hook()	mips_enable_auto_align()
 
+enum dwarf2_format;
 extern enum dwarf2_format mips_dwarf2_format (void);
 #define DWARF2_FORMAT() mips_dwarf2_format ()
 
@@ -160,7 +167,10 @@ extern int mips_dwarf2_addr_size (void);
 #define tc_cfi_frame_initial_instructions mips_cfi_frame_initial_instructions
 extern void mips_cfi_frame_initial_instructions (void);
 
+#define tc_regname_to_dw2regnum tc_mips_regname_to_dw2regnum
+extern int tc_mips_regname_to_dw2regnum (char *regname);
+
 #define DWARF2_DEFAULT_RETURN_COLUMN 31
-#define DWARF2_CIE_DATA_ALIGNMENT -4
+#define DWARF2_CIE_DATA_ALIGNMENT (-4)
 
 #endif /* TC_MIPS */
diff --git a/gas/config/tc-mmix.c b/gas/config/tc-mmix.c
index c1a8d536b18c..ff522f62ad75 100644
--- a/gas/config/tc-mmix.c
+++ b/gas/config/tc-mmix.c
@@ -1,5 +1,6 @@
 /* tc-mmix.c -- Assembler for Don Knuth's MMIX.
-   Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -26,11 +27,9 @@
    compatible syntax, but the main purpose is to serve GCC.  */
 
 
-#include <stdio.h>
 #include <limits.h>
 #include "as.h"
 #include "subsegs.h"
-#include "bfd.h"
 #include "elf/mmix.h"
 #include "opcode/mmix.h"
 #include "safe-ctype.h"
diff --git a/gas/config/tc-mmix.h b/gas/config/tc-mmix.h
index 61bc881d1268..b4ab0c7482fc 100644
--- a/gas/config/tc-mmix.h
+++ b/gas/config/tc-mmix.h
@@ -221,3 +221,6 @@ extern void mmix_md_do_align (int, char *, int, int);
    sequences sprinkled in, we can get unaligned DWARF2 offsets, so let's
    explicitly say one byte.  */
 #define DWARF2_LINE_MIN_INSN_LENGTH 1
+
+/* This target is buggy, and sets fix size too large.  */
+#define TC_FX_SIZE_SLACK(FIX) 6
diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c
index 909652ef6e0e..9eecf47ea58a 100644
--- a/gas/config/tc-mn10200.c
+++ b/gas/config/tc-mn10200.c
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c
index 102c2eacef84..306e90c12e72 100644
--- a/gas/config/tc-mn10300.c
+++ b/gas/config/tc-mn10300.c
@@ -1,6 +1,6 @@
 /* tc-mn10300.c -- Assembler code for the Matsushita 10300
    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
-   2006  Free Software Foundation, Inc.
+   2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -692,7 +691,7 @@ void
 md_show_usage (stream)
      FILE *stream;
 {
-  fprintf (stream, _("MN10300 options:\n\
+  fprintf (stream, _("MN10300 assembler options:\n\
 none yet\n"));
 }
 
@@ -1020,7 +1019,7 @@ md_convert_frag (abfd, sec, fragP)
       int offset = fragP->fr_fix;
       fragP->fr_literal[offset] = 0xcc;
 
-      fix_new (fragP, fragP->fr_fix + 1, 4, fragP->fr_symbol,
+      fix_new (fragP, fragP->fr_fix + 1, 2, fragP->fr_symbol,
 	       fragP->fr_offset + 1, 1, BFD_RELOC_16_PCREL);
       fragP->fr_var = 0;
       fragP->fr_fix += 3;
@@ -2281,17 +2280,8 @@ keep_going:
 		    abort ();
 		}
 
-	      /* Convert the size of the reloc into what fix_new_exp wants.  */
-	      reloc_size = reloc_size / 8;
-	      if (reloc_size == 8)
-		reloc_size = 0;
-	      else if (reloc_size == 16)
-		reloc_size = 1;
-	      else if (reloc_size == 32)
-		reloc_size = 2;
-
 	      fixP = fix_new_exp (frag_now, f - frag_now->fr_literal + offset,
-				  reloc_size, &fixups[i].exp, pcrel,
+				  reloc_size / 8, &fixups[i].exp, pcrel,
 				  ((bfd_reloc_code_real_type) reloc));
 
 	      if (pcrel)
@@ -2407,7 +2397,8 @@ tc_gen_reloc (seg, fixp)
 	      break;
 
 	    default:
-	      reloc->sym_ptr_ptr = (asymbol **) &bfd_abs_symbol;
+	      reloc->sym_ptr_ptr
+		= (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
 	      return reloc;
 	    }
 	}
@@ -2545,7 +2536,7 @@ bfd_boolean
 mn10300_fix_adjustable (fixp)
      struct fix *fixp;
 {
-  if (! TC_RELOC_RTSYM_LOC_FIXUP (fixp))
+  if (TC_FORCE_RELOCATION_LOCAL (fixp))
     return 0;
 
   if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
diff --git a/gas/config/tc-mn10300.h b/gas/config/tc-mn10300.h
index dff663d29adf..8f5c81356de6 100644
--- a/gas/config/tc-mn10300.h
+++ b/gas/config/tc-mn10300.h
@@ -1,5 +1,5 @@
 /* tc-mn10300.h -- Header file for tc-mn10300.c.
-   Copyright 1996, 1997, 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 1996, 1997, 2000, 2001, 2002, 2003, 2004, 2005, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -26,15 +26,15 @@
 #define DIFF_EXPR_OK
 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 
-#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)				\
-  ((FIX)->fx_r_type != BFD_RELOC_32_PLT_PCREL			\
-   && (FIX)->fx_r_type != BFD_RELOC_MN10300_GOT32		\
-   && (FIX)->fx_r_type != BFD_RELOC_32_GOT_PCREL		\
-   && ((FIX)->fx_addsy == NULL					\
-       || (! S_IS_EXTERNAL ((FIX)->fx_addsy)			\
-	   && ! S_IS_WEAK ((FIX)->fx_addsy)			\
-	   && S_IS_DEFINED ((FIX)->fx_addsy)			\
-	   && ! S_IS_COMMON ((FIX)->fx_addsy))))
+#define TC_FORCE_RELOCATION(FIX)			\
+  (generic_force_reloc (FIX))
+
+#define TC_FORCE_RELOCATION_LOCAL(FIX)			\
+  (!(FIX)->fx_pcrel					\
+   || (FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL	\
+   || (FIX)->fx_r_type == BFD_RELOC_MN10300_GOT32	\
+   || (FIX)->fx_r_type == BFD_RELOC_32_GOT_PCREL	\
+   || TC_FORCE_RELOCATION (FIX))
 
 #define md_parse_name(name, exprP, mode, nextcharP) \
     mn10300_parse_name ((name), (exprP), (mode), (nextcharP))
diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c
index 6978b85a3e1a..6bf21549d456 100644
--- a/gas/config/tc-msp430.c
+++ b/gas/config/tc-msp430.c
@@ -1,6 +1,7 @@
 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
 
-  Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+  Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
+  Free Software Foundation, Inc.
   Contributed by Dmitry Diky <diwil@mail.ru>
 
   This file is part of GAS, the GNU Assembler.
@@ -20,9 +21,6 @@
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
   Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
 #include <limits.h>
 
 #define PUSH_1X_WORKAROUND
@@ -34,7 +32,7 @@
 
 /*
    We will disable polymorphs by default because it is dangerous.
-   The potencial problem here is the following: assume we got the
+   The potential problem here is the following: assume we got the
    following code:
 
 	jump .l1
@@ -168,7 +166,7 @@ static struct hcodes_s msp430_hcodes[] =
 
 const char comment_chars[] = ";";
 const char line_comment_chars[] = "#";
-const char line_separator_chars[] = "";
+const char line_separator_chars[] = "{";
 const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "dD";
 
@@ -487,7 +485,7 @@ skip_space (char * s)
   return s;
 }
 
-/* Extract one word from FROM and copy it to TO. Delimeters are ",;\n"  */
+/* Extract one word from FROM and copy it to TO. Delimiters are ",;\n"  */
 
 static char *
 extract_operand (char * from, char * to, int limit)
@@ -1918,7 +1916,6 @@ msp430_force_relocation_local(fixS *fixp)
     return 1;
   else
     return (!fixp->fx_pcrel
-	    || fixp->fx_plt
 	    || generic_force_reloc(fixp));
 }
 
diff --git a/gas/config/tc-mt.c b/gas/config/tc-mt.c
index f9a610e049c1..f2b9aa813069 100644
--- a/gas/config/tc-mt.c
+++ b/gas/config/tc-mt.c
@@ -1,5 +1,5 @@
 /* tc-mt.c -- Assembler for the Morpho Technologies mt .
-   Copyright (C) 2005 Free Software Foundation.
+   Copyright (C) 2005, 2006 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,7 +18,6 @@
    the Free Software Foundation, 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "dwarf2dbg.h"
 #include "subsegs.h"     
diff --git a/gas/config/tc-ns32k.c b/gas/config/tc-ns32k.c
index 1a8c3cb3eea8..58e124e76e01 100644
--- a/gas/config/tc-ns32k.c
+++ b/gas/config/tc-ns32k.c
@@ -1,6 +1,6 @@
 /* ns32k.c  -- Assemble on the National Semiconductor 32k series
    Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2005
+   2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -22,8 +22,6 @@
 
 /*#define SHOW_NUM 1*//* Uncomment for debugging.  */
 
-#include <stdio.h>
-
 #include "as.h"
 #include "opcode/ns32k.h"
 
@@ -1863,7 +1861,7 @@ convert_iif (void)
 			      size = 4;
 			    else
 			      {
-				as_bad (_("Displacement to large for :d"));
+				as_bad (_("Displacement too large for :d"));
 				size = 4;
 			      }
 			  }
diff --git a/gas/config/tc-openrisc.c b/gas/config/tc-openrisc.c
index 50597a7f9dc9..b27e022fecd1 100644
--- a/gas/config/tc-openrisc.c
+++ b/gas/config/tc-openrisc.c
@@ -1,5 +1,5 @@
 /* tc-openrisc.c -- Assembler for the OpenRISC family.
-   Copyright 2001, 2002, 2003, 2005 Free Software Foundation.
+   Copyright 2001, 2002, 2003, 2005, 2006 Free Software Foundation.
    Contributed by Johan Rydberg, jrydberg@opencores.org
 
    This file is part of GAS, the GNU Assembler.
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"
 #include "symcat.h"
diff --git a/gas/config/tc-or32.c b/gas/config/tc-or32.c
index 3099e9f58626..1d98b73f9771 100644
--- a/gas/config/tc-or32.c
+++ b/gas/config/tc-or32.c
@@ -1,5 +1,6 @@
 /* Assembly backend for the OpenRISC 1000.
-   Copyright (C) 2002, 2003, 2005 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003, 2005, 2007
+   Free Software Foundation, Inc.
    Contributed by Damjan Lampret <lampret@opencores.org>.
    Modified bu Johan Rydberg, <johan.rydberg@netinsight.se>.
    Based upon a29k port.
@@ -616,9 +617,6 @@ md_apply_fix (fixS * fixP, valueT * val, segT seg ATTRIBUTE_UNUSED)
 
   fixP->fx_addnumber = t_val; /* Remember value for emit_reloc.  */
 
-  know (fixP->fx_size == 4);
-  know (fixP->fx_r_type < BFD_RELOC_NONE);
-
   switch (fixP->fx_r_type)
     {
     case BFD_RELOC_32:      /* XXXXXXXX pattern in a word.  */
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index d5bdb9e643ea..a86a3bea92c6 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1,6 +1,6 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -85,67 +84,57 @@ static int set_target_endian = 0;
 
 static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
 
-static bfd_boolean register_name PARAMS ((expressionS *));
-static void ppc_set_cpu PARAMS ((void));
-static unsigned long ppc_insert_operand
-  PARAMS ((unsigned long insn, const struct powerpc_operand *operand,
-	   offsetT val, char *file, unsigned int line));
-static void ppc_macro PARAMS ((char *str, const struct powerpc_macro *macro));
-static void ppc_byte PARAMS ((int));
+static void ppc_macro (char *, const struct powerpc_macro *);
+static void ppc_byte (int);
 
 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
-static int ppc_is_toc_sym PARAMS ((symbolS *sym));
-static void ppc_tc PARAMS ((int));
-static void ppc_machine PARAMS ((int));
+static void ppc_tc (int);
+static void ppc_machine (int);
 #endif
 
 #ifdef OBJ_XCOFF
-static void ppc_comm PARAMS ((int));
-static void ppc_bb PARAMS ((int));
-static void ppc_bc PARAMS ((int));
-static void ppc_bf PARAMS ((int));
-static void ppc_biei PARAMS ((int));
-static void ppc_bs PARAMS ((int));
-static void ppc_eb PARAMS ((int));
-static void ppc_ec PARAMS ((int));
-static void ppc_ef PARAMS ((int));
-static void ppc_es PARAMS ((int));
-static void ppc_csect PARAMS ((int));
-static void ppc_change_csect PARAMS ((symbolS *, offsetT));
-static void ppc_function PARAMS ((int));
-static void ppc_extern PARAMS ((int));
-static void ppc_lglobl PARAMS ((int));
-static void ppc_section PARAMS ((int));
-static void ppc_named_section PARAMS ((int));
-static void ppc_stabx PARAMS ((int));
-static void ppc_rename PARAMS ((int));
-static void ppc_toc PARAMS ((int));
-static void ppc_xcoff_cons PARAMS ((int));
-static void ppc_vbyte PARAMS ((int));
+static void ppc_comm (int);
+static void ppc_bb (int);
+static void ppc_bc (int);
+static void ppc_bf (int);
+static void ppc_biei (int);
+static void ppc_bs (int);
+static void ppc_eb (int);
+static void ppc_ec (int);
+static void ppc_ef (int);
+static void ppc_es (int);
+static void ppc_csect (int);
+static void ppc_change_csect (symbolS *, offsetT);
+static void ppc_function (int);
+static void ppc_extern (int);
+static void ppc_lglobl (int);
+static void ppc_section (int);
+static void ppc_named_section (int);
+static void ppc_stabx (int);
+static void ppc_rename (int);
+static void ppc_toc (int);
+static void ppc_xcoff_cons (int);
+static void ppc_vbyte (int);
 #endif
 
 #ifdef OBJ_ELF
-static bfd_reloc_code_real_type ppc_elf_suffix PARAMS ((char **, expressionS *));
-static void ppc_elf_cons PARAMS ((int));
-static void ppc_elf_rdata PARAMS ((int));
-static void ppc_elf_lcomm PARAMS ((int));
-static void ppc_elf_validate_fix PARAMS ((fixS *, segT));
-static void ppc_apuinfo_section_add PARAMS ((unsigned int apu, unsigned int version));
+static void ppc_elf_cons (int);
+static void ppc_elf_rdata (int);
+static void ppc_elf_lcomm (int);
 #endif
 
 #ifdef TE_PE
-static void ppc_set_current_section PARAMS ((segT));
-static void ppc_previous PARAMS ((int));
-static void ppc_pdata PARAMS ((int));
-static void ppc_ydata PARAMS ((int));
-static void ppc_reldata PARAMS ((int));
-static void ppc_rdata PARAMS ((int));
-static void ppc_ualong PARAMS ((int));
-static void ppc_znop PARAMS ((int));
-static void ppc_pe_comm PARAMS ((int));
-static void ppc_pe_section PARAMS ((int));
-static void ppc_pe_function PARAMS ((int));
-static void ppc_pe_tocd PARAMS ((int));
+static void ppc_previous (int);
+static void ppc_pdata (int);
+static void ppc_ydata (int);
+static void ppc_reldata (int);
+static void ppc_rdata (int);
+static void ppc_ualong (int);
+static void ppc_znop (int);
+static void ppc_pe_comm (int);
+static void ppc_pe_section (int);
+static void ppc_pe_function (int);
+static void ppc_pe_tocd (int);
 #endif
 
 /* Generic assembler global variables which must be defined by all
@@ -183,11 +172,9 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-/* '+' and '-' can be used as postfix predicate predictors for conditional
-   branches.  So they need to be accepted as symbol characters.
-   Also, anything that can start an operand needs to be mentioned here,
+/* Anything that can start an operand needs to be mentioned here,
    to stop the input scrubber eating whitespace.  */
-const char ppc_symbol_chars[] = "+-%[";
+const char ppc_symbol_chars[] = "%[";
 
 /* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
 int ppc_cie_data_alignment;
@@ -567,14 +554,8 @@ static const struct pd_reg pre_defined_registers[] =
 /* Given NAME, find the register number associated with that name, return
    the integer value associated with the given name or -1 on failure.  */
 
-static int reg_name_search
-  PARAMS ((const struct pd_reg *, int, const char * name));
-
 static int
-reg_name_search (regs, regcount, name)
-     const struct pd_reg *regs;
-     int regcount;
-     const char *name;
+reg_name_search (const struct pd_reg *regs, int regcount, const char *name)
 {
   int middle, low, high;
   int cmp;
@@ -611,8 +592,7 @@ reg_name_search (regs, regcount, name)
  */
 
 static bfd_boolean
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -679,9 +659,7 @@ static const struct pd_reg cr_names[] =
    expression.  */
 
 int
-ppc_parse_name (name, expr)
-     const char *name;
-     expressionS *expr;
+ppc_parse_name (const char *name, expressionS *expr)
 {
   int val;
 
@@ -917,6 +895,18 @@ parse_cpu (const char *arg)
 		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
 		 | PPC_OPCODE_POWER5);
     }
+  else if (strcmp (arg, "power6") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+		 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6);
+    }
+  else if (strcmp (arg, "cell") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+		 | PPC_OPCODE_CELL);
+    }
   /* -mcom means assemble for the common intersection between Power
      and PowerPC.  At present, we just allow the union, rather
      than the intersection.  */
@@ -932,9 +922,7 @@ parse_cpu (const char *arg)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -1088,8 +1076,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 PowerPC options:\n\
@@ -1112,6 +1099,8 @@ PowerPC options:\n\
 -mbooke, mbooke32	generate code for 32-bit PowerPC BookE\n\
 -mpower4		generate code for Power4 architecture\n\
 -mpower5		generate code for Power5 architecture\n\
+-mpower6		generate code for Power6 architecture\n\
+-mcell			generate code for Cell Broadband Engine architecture\n\
 -mcom			generate code Power/PowerPC common instructions\n\
 -many			generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
@@ -1140,7 +1129,7 @@ PowerPC options:\n\
 /* Set ppc_cpu if it is not already set.  */
 
 static void
-ppc_set_cpu ()
+ppc_set_cpu (void)
 {
   const char *default_os  = TARGET_OS;
   const char *default_cpu = TARGET_CPU;
@@ -1168,7 +1157,7 @@ ppc_set_cpu ()
    are called well before md_begin, when the output file is opened.  */
 
 enum bfd_architecture
-ppc_arch ()
+ppc_arch (void)
 {
   const char *default_cpu = TARGET_CPU;
   ppc_set_cpu ();
@@ -1190,7 +1179,7 @@ ppc_arch ()
 }
 
 unsigned long
-ppc_mach ()
+ppc_mach (void)
 {
   if (ppc_obj64)
     return bfd_mach_ppc64;
@@ -1201,7 +1190,7 @@ ppc_mach ()
 }
 
 extern char*
-ppc_target_format ()
+ppc_target_format (void)
 {
 #ifdef OBJ_COFF
 #ifdef TE_PE
@@ -1233,11 +1222,11 @@ ppc_target_format ()
 static void
 ppc_setup_opcodes (void)
 {
-  register const struct powerpc_opcode *op;
+  const struct powerpc_opcode *op;
   const struct powerpc_opcode *op_end;
   const struct powerpc_macro *macro;
   const struct powerpc_macro *macro_end;
-  bfd_boolean dup_insn = FALSE;
+  bfd_boolean bad_insn = FALSE;
 
   if (ppc_hash != NULL)
     hash_die (ppc_hash);
@@ -1247,10 +1236,77 @@ ppc_setup_opcodes (void)
   /* Insert the opcodes into a hash table.  */
   ppc_hash = hash_new ();
 
+  if (ENABLE_CHECKING)
+    {
+      unsigned int i;
+
+      /* Check operand masks.  Code here and in the disassembler assumes
+	 all the 1's in the mask are contiguous.  */
+      for (i = 0; i < num_powerpc_operands; ++i)
+	{
+	  unsigned long mask = powerpc_operands[i].bitm;
+	  unsigned long right_bit;
+	  unsigned int j;
+
+	  right_bit = mask & -mask;
+	  mask += right_bit;
+	  right_bit = mask & -mask;
+	  if (mask != right_bit)
+	    {
+	      as_bad (_("powerpc_operands[%d].bitm invalid"), i);
+	      bad_insn = TRUE;
+	    }
+	  for (j = i + 1; j < num_powerpc_operands; ++j)
+	    if (memcmp (&powerpc_operands[i], &powerpc_operands[j],
+			sizeof (powerpc_operands[0])) == 0)
+	      {
+		as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
+			j, i);
+		bad_insn = TRUE;
+	      }
+	}
+    }
+
   op_end = powerpc_opcodes + powerpc_num_opcodes;
   for (op = powerpc_opcodes; op < op_end; op++)
     {
-      know ((op->opcode & op->mask) == op->opcode);
+      if (ENABLE_CHECKING)
+	{
+	  const unsigned char *o;
+	  unsigned long omask = op->mask;
+
+	  /* The mask had better not trim off opcode bits.  */
+	  if ((op->opcode & omask) != op->opcode)
+	    {
+	      as_bad (_("mask trims opcode bits for %s"),
+		      op->name);
+	      bad_insn = TRUE;
+	    }
+
+	  /* The operands must not overlap the opcode or each other.  */
+	  for (o = op->operands; *o; ++o)
+	    if (*o >= num_powerpc_operands)
+	      {
+		as_bad (_("operand index error for %s"),
+			op->name);
+		bad_insn = TRUE;
+	      }
+	    else
+	      {
+		const struct powerpc_operand *operand = &powerpc_operands[*o];
+		if (operand->shift >= 0)
+		  {
+		    unsigned long mask = operand->bitm << operand->shift;
+		    if (omask & mask)
+		      {
+			as_bad (_("operand %d overlap in %s"),
+				(int) (o - op->operands), op->name);
+			bad_insn = TRUE;
+		      }
+		    omask |= mask;
+		  }
+	      }
+	}
 
       if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
 	  && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
@@ -1270,11 +1326,14 @@ ppc_setup_opcodes (void)
 		  == (ppc_cpu & PPC_OPCODE_POWER4)))
 	  && ((op->flags & PPC_OPCODE_POWER5) == 0
 	      || ((op->flags & PPC_OPCODE_POWER5)
-		  == (ppc_cpu & PPC_OPCODE_POWER5))))
+		  == (ppc_cpu & PPC_OPCODE_POWER5)))
+	  && ((op->flags & PPC_OPCODE_POWER6) == 0
+	      || ((op->flags & PPC_OPCODE_POWER6)
+		  == (ppc_cpu & PPC_OPCODE_POWER6))))
 	{
 	  const char *retval;
 
-	  retval = hash_insert (ppc_hash, op->name, (PTR) op);
+	  retval = hash_insert (ppc_hash, op->name, (void *) op);
 	  if (retval != NULL)
 	    {
 	      /* Ignore Power duplicates for -m601.  */
@@ -1282,16 +1341,16 @@ ppc_setup_opcodes (void)
 		  && (op->flags & PPC_OPCODE_POWER) != 0)
 		continue;
 
-	      as_bad (_("Internal assembler error for instruction %s"),
+	      as_bad (_("duplicate instruction %s"),
 		      op->name);
-	      dup_insn = TRUE;
+	      bad_insn = TRUE;
 	    }
 	}
     }
 
   if ((ppc_cpu & PPC_OPCODE_ANY) != 0)
     for (op = powerpc_opcodes; op < op_end; op++)
-      hash_insert (ppc_hash, op->name, (PTR) op);
+      hash_insert (ppc_hash, op->name, (void *) op);
 
   /* Insert the macros into a hash table.  */
   ppc_macro_hash = hash_new ();
@@ -1303,16 +1362,16 @@ ppc_setup_opcodes (void)
 	{
 	  const char *retval;
 
-	  retval = hash_insert (ppc_macro_hash, macro->name, (PTR) macro);
+	  retval = hash_insert (ppc_macro_hash, macro->name, (void *) macro);
 	  if (retval != (const char *) NULL)
 	    {
-	      as_bad (_("Internal assembler error for macro %s"), macro->name);
-	      dup_insn = TRUE;
+	      as_bad (_("duplicate macro %s"), macro->name);
+	      bad_insn = TRUE;
 	    }
 	}
     }
 
-  if (dup_insn)
+  if (bad_insn)
     abort ();
 }
 
@@ -1321,7 +1380,7 @@ ppc_setup_opcodes (void)
    opened.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   ppc_set_cpu ();
 
@@ -1364,7 +1423,7 @@ md_begin ()
 }
 
 void
-ppc_cleanup ()
+ppc_cleanup (void)
 {
 #ifdef OBJ_ELF
   if (ppc_apuinfo_list == NULL)
@@ -1426,54 +1485,60 @@ ppc_cleanup ()
 /* Insert an operand value into an instruction.  */
 
 static unsigned long
-ppc_insert_operand (insn, operand, val, file, line)
-     unsigned long insn;
-     const struct powerpc_operand *operand;
-     offsetT val;
-     char *file;
-     unsigned int line;
+ppc_insert_operand (unsigned long insn,
+		    const struct powerpc_operand *operand,
+		    offsetT val,
+		    char *file,
+		    unsigned int line)
 {
-  if (operand->bits != 32)
+  long min, max, right;
+
+  max = operand->bitm;
+  right = max & -max;
+  min = 0;
+
+  if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
     {
-      long min, max;
-      offsetT test;
+      if ((operand->flags & PPC_OPERAND_SIGNOPT) == 0)
+	max = (max >> 1) & -right;
+      min = ~max & -right;
+    }
 
-      if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
-	{
-	  if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0)
-	    max = (1 << operand->bits) - 1;
-	  else
-	    max = (1 << (operand->bits - 1)) - 1;
-	  min = - (1 << (operand->bits - 1));
+  if ((operand->flags & PPC_OPERAND_PLUS1) != 0)
+    max++;
 
-	  if (!ppc_obj64)
-	    {
-	      /* Some people write 32 bit hex constants with the sign
-		 extension done by hand.  This shouldn't really be
-		 valid, but, to permit this code to assemble on a 64
-		 bit host, we sign extend the 32 bit value.  */
-	      if (val > 0
-		  && (val & (offsetT) 0x80000000) != 0
-		  && (val & (offsetT) 0xffffffff) == val)
-		{
-		  val -= 0x80000000;
-		  val -= 0x80000000;
-		}
-	    }
-	}
-      else
-	{
-	  max = (1 << operand->bits) - 1;
-	  min = 0;
-	}
+  if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
+    {
+      long tmp = min;
+      min = -max;
+      max = -tmp;
+    }
 
-      if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0)
-	test = - val;
-      else
-	test = val;
+  if (min <= max)
+    {
+      /* Some people write constants with the sign extension done by
+	 hand but only up to 32 bits.  This shouldn't really be valid,
+	 but, to permit this code to assemble on a 64-bit host, we
+	 sign extend the 32-bit value to 64 bits if so doing makes the
+	 value valid.  */
+      if (val > max
+	  && (offsetT) (val - 0x80000000 - 0x80000000) >= min
+	  && (offsetT) (val - 0x80000000 - 0x80000000) <= max
+	  && ((val - 0x80000000 - 0x80000000) & (right - 1)) == 0)
+	val = val - 0x80000000 - 0x80000000;
 
-      if (test < (offsetT) min || test > (offsetT) max)
-	as_bad_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
+      /* Similarly, people write expressions like ~(1<<15), and expect
+	 this to be OK for a 32-bit unsigned value.  */
+      else if (val < min
+	       && (offsetT) (val + 0x80000000 + 0x80000000) >= min
+	       && (offsetT) (val + 0x80000000 + 0x80000000) <= max
+	       && ((val + 0x80000000 + 0x80000000) & (right - 1)) == 0)
+	val = val + 0x80000000 + 0x80000000;
+
+      else if (val < min
+	       || val > max
+	       || (val & (right - 1)) != 0)
+	as_bad_value_out_of_range (_("operand"), val, min, max, file, line);
     }
 
   if (operand->insert)
@@ -1486,8 +1551,7 @@ ppc_insert_operand (insn, operand, val, file, line)
 	as_bad_where (file, line, errmsg);
     }
   else
-    insn |= (((long) val & ((1 << operand->bits) - 1))
-	     << operand->shift);
+    insn |= ((long) val & operand->bitm) << operand->shift;
 
   return insn;
 }
@@ -1496,9 +1560,7 @@ ppc_insert_operand (insn, operand, val, file, line)
 #ifdef OBJ_ELF
 /* Parse @got, etc. and return the desired relocation.  */
 static bfd_reloc_code_real_type
-ppc_elf_suffix (str_p, exp_p)
-     char **str_p;
-     expressionS *exp_p;
+ppc_elf_suffix (char **str_p, expressionS *exp_p)
 {
   struct map_bfd {
     char *string;
@@ -1676,8 +1738,7 @@ ppc_elf_suffix (str_p, exp_p)
 /* Like normal .long/.short/.word, except support @got, etc.
    Clobbers input_line_pointer, checks end-of-line.  */
 static void
-ppc_elf_cons (nbytes)
-     register int nbytes;	/* 1=.byte, 2=.word, 4=.long, 8=.llong.  */
+ppc_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long, 8=.llong */)
 {
   expressionS exp;
   bfd_reloc_code_real_type reloc;
@@ -1732,8 +1793,7 @@ ppc_elf_cons (nbytes)
 
 /* Solaris pseduo op to change to the .rodata section.  */
 static void
-ppc_elf_rdata (xxx)
-     int xxx;
+ppc_elf_rdata (int xxx)
 {
   char *save_line = input_line_pointer;
   static char section[] = ".rodata\n";
@@ -1747,14 +1807,13 @@ ppc_elf_rdata (xxx)
 
 /* Pseudo op to make file scope bss items.  */
 static void
-ppc_elf_lcomm (xxx)
-     int xxx ATTRIBUTE_UNUSED;
+ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT size;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
   segT old_sec;
   int old_subsec;
@@ -1857,9 +1916,7 @@ ppc_elf_lcomm (xxx)
    fixups for word relocations in writable segments, so we can adjust
    them at runtime.  */
 static void
-ppc_elf_validate_fix (fixp, seg)
-     fixS *fixp;
-     segT seg;
+ppc_elf_validate_fix (fixS *fixp, segT seg)
 {
   if (fixp->fx_done || fixp->fx_pcrel)
     return;
@@ -1904,7 +1961,7 @@ ppc_elf_validate_fix (fixp, seg)
    function descriptor sym if the corresponding code sym is used.  */
 
 void
-ppc_frob_file_before_adjust ()
+ppc_frob_file_before_adjust (void)
 {
   symbolS *symp;
   asection *toc;
@@ -1987,8 +2044,7 @@ enum toc_size_qualifier
 };
 
 static int
-parse_toc_entry (toc_kind)
-     enum toc_size_qualifier *toc_kind;
+parse_toc_entry (enum toc_size_qualifier *toc_kind)
 {
   char *start;
   char *toc_spec;
@@ -2052,8 +2108,7 @@ parse_toc_entry (toc_kind)
 #ifdef OBJ_ELF
 #define APUID(a,v)	((((a) & 0xffff) << 16) | ((v) & 0xffff))
 static void
-ppc_apuinfo_section_add (apu, version)
-      unsigned int apu, version;
+ppc_apuinfo_section_add (unsigned int apu, unsigned int version)
 {
   unsigned int i;
 
@@ -2099,8 +2154,7 @@ struct ppc_fixup
 /* This routine is called for each instruction to be assembled.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *s;
   const struct powerpc_opcode *opcode;
@@ -2724,16 +2778,14 @@ md_assemble (str)
    around operands here.  */
 
 static void
-ppc_macro (str, macro)
-     char *str;
-     const struct powerpc_macro *macro;
+ppc_macro (char *str, const struct powerpc_macro *macro)
 {
   char *operands[10];
   unsigned int count;
   char *s;
   unsigned int len;
   const char *format;
-  int arg;
+  unsigned int arg;
   char *send;
   char *complete;
 
@@ -2771,7 +2823,7 @@ ppc_macro (str, macro)
       else
 	{
 	  arg = strtol (format + 1, &send, 10);
-	  know (send != format && arg >= 0 && arg < count);
+	  know (send != format && arg < count);
 	  len += strlen (operands[arg]);
 	  format = send;
 	}
@@ -2802,9 +2854,7 @@ ppc_macro (str, macro)
 /* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED.  */
 
 int
-ppc_section_letter (letter, ptr_msg)
-     int letter;
-     char **ptr_msg;
+ppc_section_letter (int letter, char **ptr_msg)
 {
   if (letter == 'e')
     return SHF_EXCLUDE;
@@ -2814,9 +2864,7 @@ ppc_section_letter (letter, ptr_msg)
 }
 
 int
-ppc_section_word (str, len)
-     char *str;
-     size_t len;
+ppc_section_word (char *str, size_t len)
 {
   if (len == 7 && strncmp (str, "exclude", 7) == 0)
     return SHF_EXCLUDE;
@@ -2825,9 +2873,7 @@ ppc_section_word (str, len)
 }
 
 int
-ppc_section_type (str, len)
-     char *str;
-     size_t len;
+ppc_section_type (char *str, size_t len)
 {
   if (len == 7 && strncmp (str, "ordered", 7) == 0)
     return SHT_ORDERED;
@@ -2836,10 +2882,7 @@ ppc_section_type (str, len)
 }
 
 int
-ppc_section_flags (flags, attr, type)
-     int flags;
-     int attr;
-     int type;
+ppc_section_flags (int flags, int attr, int type)
 {
   if (type == SHT_ORDERED)
     flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
@@ -2858,8 +2901,7 @@ ppc_section_flags (flags, attr, type)
    pseudo-op, but it can also take a single ASCII string.  */
 
 static void
-ppc_byte (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_byte (int ignore ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer != '\"')
     {
@@ -2903,8 +2945,7 @@ static bfd_boolean ppc_stab_symbol;
    aligns .comm and .lcomm to 4 bytes.  */
 
 static void
-ppc_comm (lcomm)
-     int lcomm;
+ppc_comm (int lcomm)
 {
   asection *current_seg = now_seg;
   subsegT current_subseg = now_subseg;
@@ -3058,8 +3099,7 @@ ppc_comm (lcomm)
    optional second argument is the alignment (the default is 2).  */
 
 static void
-ppc_csect (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_csect (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3094,9 +3134,7 @@ ppc_csect (ignore)
 /* Change to a different csect.  */
 
 static void
-ppc_change_csect (sym, align)
-     symbolS *sym;
-     offsetT align;
+ppc_change_csect (symbolS *sym, offsetT align)
 {
   if (S_IS_DEFINED (sym))
     subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg);
@@ -3196,8 +3234,7 @@ ppc_change_csect (sym, align)
    convenience of people who aren't used to XCOFF.  */
 
 static void
-ppc_section (type)
-     int type;
+ppc_section (int type)
 {
   const char *name;
   symbolS *sym;
@@ -3221,8 +3258,7 @@ ppc_section (type)
    we do permit the user to name the text or data section.  */
 
 static void
-ppc_named_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_named_section (int ignore ATTRIBUTE_UNUSED)
 {
   char *user_name;
   const char *real_name;
@@ -3256,8 +3292,7 @@ ppc_named_section (ignore)
 /* The .extern pseudo-op.  We create an undefined symbol.  */
 
 static void
-ppc_extern (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_extern (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3275,8 +3310,7 @@ ppc_extern (ignore)
 /* The .lglobl pseudo-op.  Keep the symbol in the symbol table.  */
 
 static void
-ppc_lglobl (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_lglobl (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3298,8 +3332,7 @@ ppc_lglobl (ignore)
    although I don't know why it bothers.  */
 
 static void
-ppc_rename (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_rename (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3334,8 +3367,7 @@ ppc_rename (ignore)
    always zero, and I am assuming it is the type.  */
 
 static void
-ppc_stabx (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_stabx (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int len;
@@ -3461,8 +3493,7 @@ ppc_stabx (ignore)
    gets an aux entry like that used for a csect.  */
 
 static void
-ppc_function (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_function (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3555,8 +3586,7 @@ ppc_function (ignore)
 static symbolS *saved_bi_sym = 0;
 
 static void
-ppc_bf (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bf (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3591,8 +3621,7 @@ ppc_bf (ignore)
    most recent ".bf" symbol.  */
 
 static void
-ppc_ef (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ef (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3616,8 +3645,7 @@ ppc_ef (ignore)
    is encountered.  */
 
 static void
-ppc_biei (ei)
-     int ei;
+ppc_biei (int ei)
 {
   static symbolS *last_biei;
 
@@ -3671,8 +3699,7 @@ ppc_biei (ei)
    .bs symbol is the index of this csect symbol.  */
 
 static void
-ppc_bs (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bs (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -3707,8 +3734,7 @@ ppc_bs (ignore)
 /* The .es pseudo-op.  Generate a C_ESTART symbol named .es.  */
 
 static void
-ppc_es (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_es (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3732,8 +3758,7 @@ ppc_es (ignore)
    line number.  */
 
 static void
-ppc_bb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bb (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3759,8 +3784,7 @@ ppc_bb (ignore)
    line number.  */
 
 static void
-ppc_eb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_eb (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3784,8 +3808,7 @@ ppc_eb (ignore)
    specified name.  */
 
 static void
-ppc_bc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_bc (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int len;
@@ -3807,8 +3830,7 @@ ppc_bc (ignore)
 /* The .ec pseudo-op.  This just creates a C_ECOMM symbol.  */
 
 static void
-ppc_ec (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ec (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
 
@@ -3827,8 +3849,7 @@ ppc_ec (ignore)
 /* The .toc pseudo-op.  Switch to the .toc subsegment.  */
 
 static void
-ppc_toc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_toc (int ignore ATTRIBUTE_UNUSED)
 {
   if (ppc_toc_csect != (symbolS *) NULL)
     subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg);
@@ -3874,8 +3895,7 @@ ppc_toc (ignore)
    .short pseudo-op, and we want to be compatible.  */
 
 static void
-ppc_xcoff_cons (log_size)
-     int log_size;
+ppc_xcoff_cons (int log_size)
 {
   frag_align (log_size, 0, 0);
   record_alignment (now_seg, log_size);
@@ -3883,8 +3903,7 @@ ppc_xcoff_cons (log_size)
 }
 
 static void
-ppc_vbyte (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+ppc_vbyte (int dummy ATTRIBUTE_UNUSED)
 {
   expressionS exp;
   int byte_count;
@@ -3927,8 +3946,7 @@ ppc_vbyte (dummy)
    the first argument is simply ignored.  */
 
 static void
-ppc_tc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_tc (int ignore ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_XCOFF
 
@@ -4014,8 +4032,7 @@ ppc_tc (ignore)
 /* Pseudo-op .machine.  */
 
 static void
-ppc_machine (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_machine (int ignore ATTRIBUTE_UNUSED)
 {
   char *cpu_string;
 #define MAX_HISTORY 100
@@ -4078,8 +4095,7 @@ ppc_machine (ignore)
 /* See whether a symbol is in the TOC section.  */
 
 static int
-ppc_is_toc_sym (sym)
-     symbolS *sym;
+ppc_is_toc_sym (symbolS *sym)
 {
 #ifdef OBJ_XCOFF
   return symbol_get_tc (sym)->class == XMC_TC;
@@ -4100,8 +4116,7 @@ ppc_is_toc_sym (sym)
 
 /* Set the current section.  */
 static void
-ppc_set_current_section (new)
-     segT new;
+ppc_set_current_section (segT new)
 {
   ppc_previous_section = ppc_current_section;
   ppc_current_section = new;
@@ -4113,8 +4128,7 @@ ppc_set_current_section (new)
    warnings:  "No previous section"  */
 
 static void
-ppc_previous (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_previous (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *tmp;
 
@@ -4145,8 +4159,7 @@ ppc_previous (ignore)
    handling, debugging, etc.  */
 
 static void
-ppc_pdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pdata (int ignore ATTRIBUTE_UNUSED)
 {
   if (pdata_section == 0)
     {
@@ -4180,8 +4193,7 @@ ppc_pdata (ignore)
    debugging, etc.  */
 
 static void
-ppc_ydata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ydata (int ignore ATTRIBUTE_UNUSED)
 {
   if (ydata_section == 0)
     {
@@ -4217,8 +4229,7 @@ ppc_ydata (ignore)
    function descriptors, etc.  */
 
 static void
-ppc_reldata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_reldata (int ignore ATTRIBUTE_UNUSED)
 {
   if (reldata_section == 0)
     {
@@ -4248,8 +4259,7 @@ ppc_reldata (ignore)
 	      3 - double word aligned (that would be 4 byte boundary)  */
 
 static void
-ppc_rdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_rdata (int ignore ATTRIBUTE_UNUSED)
 {
   if (rdata_section == 0)
     {
@@ -4275,8 +4285,7 @@ ppc_rdata (ignore)
    warnings:  None  */
 
 static void
-ppc_ualong (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_ualong (int ignore ATTRIBUTE_UNUSED)
 {
   /* Try for long.  */
   cons (4);
@@ -4290,8 +4299,7 @@ ppc_ualong (ignore)
    warnings:  Missing symbol name  */
 
 static void
-ppc_znop (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_znop (int ignore ATTRIBUTE_UNUSED)
 {
   unsigned long insn;
   const struct powerpc_opcode *opcode;
@@ -4343,14 +4351,13 @@ ppc_znop (ignore)
    warnings:  */
 
 static void
-ppc_pe_comm (lcomm)
-     int lcomm;
+ppc_pe_comm (int lcomm)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT temp;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
 
   name = input_line_pointer;
@@ -4473,8 +4480,7 @@ ppc_pe_comm (lcomm)
  */
 
 void
-ppc_pe_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_section (int ignore ATTRIBUTE_UNUSED)
 {
   /* Strip out the section name.  */
   char *section_name;
@@ -4562,7 +4568,7 @@ ppc_pe_section (ignore)
 		case 'R': /* Remove section at link time */
 		  flags |= SEC_NEVER_LOAD;
 		  break;
-
+#if IFLICT_BRAIN_DAMAGE
 		  /* Section Protection */
 		case 'r': /* section is readable */
 		  flags |= IMAGE_SCN_MEM_READ;
@@ -4606,7 +4612,7 @@ ppc_pe_section (ignore)
 		  flags |= IMAGE_SCN_ALIGN_64BYTES;
 		  align = 6;
 		  break;
-
+#endif
 		default:
 		  as_bad (_("unknown section attribute '%c'"),
 			  *input_line_pointer);
@@ -4632,12 +4638,10 @@ ppc_pe_section (ignore)
     }
 
   bfd_set_section_alignment (stdoutput, sec, align);
-
 }
 
 static void
-ppc_pe_function (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_function (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char endc;
@@ -4659,8 +4663,7 @@ ppc_pe_function (ignore)
 }
 
 static void
-ppc_pe_tocd (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED)
 {
   if (tocdata_section == 0)
     {
@@ -4685,8 +4688,7 @@ ppc_pe_tocd (ignore)
 /* Don't adjust TOC relocs to use the section symbol.  */
 
 int
-ppc_pe_fix_adjustable (fix)
-     fixS *fix;
+ppc_pe_fix_adjustable (fixS *fix)
 {
   return fix->fx_r_type != BFD_RELOC_PPC_TOC16;
 }
@@ -4701,8 +4703,7 @@ ppc_pe_fix_adjustable (fix)
    any, to use square brackets, and to be in upper case.  */
 
 char *
-ppc_canonicalize_symbol_name (name)
-     char *name;
+ppc_canonicalize_symbol_name (char *name)
 {
   char *s;
 
@@ -4739,8 +4740,7 @@ ppc_canonicalize_symbol_name (name)
    called whenever a new symbol is created.  */
 
 void
-ppc_symbol_new_hook (sym)
-     symbolS *sym;
+ppc_symbol_new_hook (symbolS *sym)
 {
   struct ppc_tc_sy *tc;
   const char *s;
@@ -4828,8 +4828,7 @@ ppc_symbol_new_hook (sym)
    follows the csect symbol.  */
 
 void
-ppc_frob_label (sym)
-     symbolS *sym;
+ppc_frob_label (symbolS *sym)
 {
   if (ppc_current_csect != (symbolS *) NULL)
     {
@@ -4859,8 +4858,7 @@ static bfd_boolean ppc_saw_abs;
    symbol table.  */
 
 int
-ppc_frob_symbol (sym)
-     symbolS *sym;
+ppc_frob_symbol (symbolS *sym)
 {
   static symbolS *ppc_last_function;
   static symbolS *set_end;
@@ -5123,7 +5121,7 @@ ppc_frob_symbol (sym)
    absolute symbols.  */
 
 void
-ppc_adjust_symtab ()
+ppc_adjust_symtab (void)
 {
   symbolS *sym;
 
@@ -5169,8 +5167,7 @@ ppc_adjust_symtab ()
    turn.  */
 
 void
-ppc_frob_section (sec)
-     asection *sec;
+ppc_frob_section (asection *sec)
 {
   static bfd_vma vma = 0;
 
@@ -5187,10 +5184,7 @@ ppc_frob_section (sec)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litp, sizep)
-     int type;
-     char *litp;
-     int *sizep;
+md_atof (int type, char *litp, int *sizep)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -5242,10 +5236,7 @@ md_atof (type, litp, sizep)
    endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -5256,21 +5247,22 @@ md_number_to_chars (buf, val, n)
 /* Align a section (I don't know why this is machine dependent).  */
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr)
 {
+#ifdef OBJ_ELF
+  return addr;
+#else
   int align = bfd_get_section_alignment (stdoutput, seg);
 
   return ((addr + (1 << align) - 1) & (-1 << align));
+#endif
 }
 
 /* We don't have any form of relaxing.  */
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
@@ -5279,10 +5271,9 @@ md_estimate_size_before_relax (fragp, seg)
 /* Convert a machine dependent frag.  We never generate these.  */
 
 void
-md_convert_frag (abfd, sec, fragp)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragp ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragp ATTRIBUTE_UNUSED)
 {
   abort ();
 }
@@ -5290,8 +5281,7 @@ md_convert_frag (abfd, sec, fragp)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -5302,9 +5292,7 @@ md_undefined_symbol (name)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec ATTRIBUTE_UNUSED;
+md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
 {
   return fixp->fx_frag->fr_address + fixp->fx_where;
 }
@@ -5317,8 +5305,7 @@ md_pcrel_from_section (fixp, sec)
    corresponding .tc symbol.  */
 
 int
-ppc_fix_adjustable (fix)
-     fixS *fix;
+ppc_fix_adjustable (fixS *fix)
 {
   valueT val = resolve_symbol_value (fix->fx_addsy);
   segT symseg = S_GET_SEGMENT (fix->fx_addsy);
@@ -5443,8 +5430,7 @@ ppc_fix_adjustable (fix)
    between two csects in the same section.  */
 
 int
-ppc_force_relocation (fix)
-     fixS *fix;
+ppc_force_relocation (fixS *fix)
 {
   /* At this point fix->fx_addsy should already have been converted to
      a csect symbol.  If the csect does not include the fragment, then
@@ -5469,8 +5455,7 @@ ppc_force_relocation (fix)
    will be emitted for a fixup.  */
 
 int
-ppc_force_relocation (fix)
-     fixS *fix;
+ppc_force_relocation (fixS *fix)
 {
   /* Branch prediction relocations must force a relocation, as must
      the vtable description relocs.  */
@@ -5495,8 +5480,7 @@ ppc_force_relocation (fix)
 }
 
 int
-ppc_fix_adjustable (fix)
-     fixS *fix;
+ppc_fix_adjustable (fixS *fix)
 {
   return (fix->fx_r_type != BFD_RELOC_16_GOTOFF
 	  && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF
@@ -5510,6 +5494,47 @@ ppc_fix_adjustable (fix)
 }
 #endif
 
+/* Implement HANDLE_ALIGN.  This writes the NOP pattern into an
+   rs_align_code frag.  */
+
+void
+ppc_handle_align (struct frag *fragP)
+{
+  valueT count = (fragP->fr_next->fr_address
+		  - (fragP->fr_address + fragP->fr_fix));
+
+  if (count != 0 && (count & 3) == 0)
+    {
+      char *dest = fragP->fr_literal + fragP->fr_fix;
+
+      fragP->fr_var = 4;
+      md_number_to_chars (dest, 0x60000000, 4);
+
+      if ((ppc_cpu & PPC_OPCODE_POWER6) != 0)
+	{
+	  /* For power6, we want the last nop to be a group terminating
+	     one, "ori 1,1,0".  Do this by inserting an rs_fill frag
+	     immediately after this one, with its address set to the last
+	     nop location.  This will automatically reduce the number of
+	     nops in the current frag by one.  */
+	  if (count > 4)
+	    {
+	      struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4);
+
+	      memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG);
+	      group_nop->fr_address = group_nop->fr_next->fr_address - 4;
+	      group_nop->fr_fix = 0;
+	      group_nop->fr_offset = 1;
+	      group_nop->fr_type = rs_fill;
+	      fragP->fr_next = group_nop;
+	      dest = group_nop->fr_literal;
+	    }
+
+	  md_number_to_chars (dest, 0x60210000, 4);
+	}
+    }
+}
+
 /* Apply a fixup to the object code.  This is called for all the
    fixups we generated by the call to fix_new_exp, above.  In the call
    above we used a reloc code which was the largest legal reloc code
@@ -5520,10 +5545,7 @@ ppc_fix_adjustable (fix)
    fixup.  */
 
 void
-md_apply_fix (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   valueT value = * valP;
 
@@ -5580,7 +5602,7 @@ md_apply_fix (fixP, valP, seg)
 	 csect.  Other usages, such as `.long sym', generate relocs.  This
 	 is the documented behaviour of non-TOC symbols.  */
       if ((operand->flags & PPC_OPERAND_PARENS) != 0
-	  && operand->bits == 16
+	  && (operand->bitm & 0xfff0) == 0xfff0
 	  && operand->shift == 0
 	  && (operand->insert == NULL || ppc_obj64)
 	  && fixP->fx_addsy != NULL
@@ -5618,11 +5640,11 @@ md_apply_fix (fixP, valP, seg)
 	 We are only prepared to turn a few of the operands into
 	 relocs.  */
       if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
-	  && operand->bits == 26
+	  && operand->bitm == 0x3fffffc
 	  && operand->shift == 0)
 	fixP->fx_r_type = BFD_RELOC_PPC_B26;
       else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0
-	  && operand->bits == 16
+	  && operand->bitm == 0xfffc
 	  && operand->shift == 0)
 	{
 	  fixP->fx_r_type = BFD_RELOC_PPC_B16;
@@ -5633,11 +5655,11 @@ md_apply_fix (fixP, valP, seg)
 #endif
 	}
       else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
-	       && operand->bits == 26
+	       && operand->bitm == 0x3fffffc
 	       && operand->shift == 0)
 	fixP->fx_r_type = BFD_RELOC_PPC_BA26;
       else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0
-	       && operand->bits == 16
+	       && operand->bitm == 0xfffc
 	       && operand->shift == 0)
 	{
 	  fixP->fx_r_type = BFD_RELOC_PPC_BA16;
@@ -5649,7 +5671,7 @@ md_apply_fix (fixP, valP, seg)
 	}
 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
       else if ((operand->flags & PPC_OPERAND_PARENS) != 0
-	       && operand->bits == 16
+	       && (operand->bitm & 0xfff0) == 0xfff0
 	       && operand->shift == 0)
 	{
 	  if (ppc_is_toc_sym (fixP->fx_addsy))
@@ -6047,9 +6069,7 @@ md_apply_fix (fixP, valP, seg)
 /* Generate a reloc for a fixup.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
@@ -6072,13 +6092,13 @@ tc_gen_reloc (seg, fixp)
 }
 
 void
-ppc_cfi_frame_initial_instructions ()
+ppc_cfi_frame_initial_instructions (void)
 {
   cfi_add_CFA_def_cfa (1, 0);
 }
 
 int
-tc_ppc_regname_to_dw2regnum (const char *regname)
+tc_ppc_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum = -1;
   unsigned int i;
diff --git a/gas/config/tc-ppc.h b/gas/config/tc-ppc.h
index f7c2da619cbc..1e856497959a 100644
--- a/gas/config/tc-ppc.h
+++ b/gas/config/tc-ppc.h
@@ -1,6 +1,6 @@
 /* tc-ppc.h -- Header file for tc-ppc.c.
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006, 2007 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -42,15 +42,15 @@ struct fix;
 /* The target BFD architecture.  */
 #define TARGET_ARCH (ppc_arch ())
 #define TARGET_MACH (ppc_mach ())
-extern enum bfd_architecture ppc_arch PARAMS ((void));
-extern unsigned long ppc_mach PARAMS ((void));
+extern enum bfd_architecture ppc_arch (void);
+extern unsigned long ppc_mach (void);
 
 /* Whether or not the target is big endian */
 extern int target_big_endian;
 
 /* The target BFD format.  */
 #define TARGET_FORMAT (ppc_target_format ())
-extern char *ppc_target_format PARAMS ((void));
+extern char *ppc_target_format (void);
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
@@ -78,31 +78,12 @@ extern char *ppc_target_format PARAMS ((void));
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE 4
 #define HANDLE_ALIGN(FRAGP)						\
-  if ((FRAGP)->fr_type == rs_align_code) 				\
-    {									\
-      valueT count = ((FRAGP)->fr_next->fr_address			\
-		      - ((FRAGP)->fr_address + (FRAGP)->fr_fix));	\
-      if (count != 0 && (count & 3) == 0)				\
-	{								\
-	  char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;		\
-									\
-	  (FRAGP)->fr_var = 4;						\
-	  if (target_big_endian)					\
-	    {								\
-	      *dest++ = 0x60;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	    }								\
-	  else								\
-	    {								\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0;						\
-	      *dest++ = 0x60;						\
-	    }								\
-	}								\
-    }
+  if ((FRAGP)->fr_type == rs_align_code)				\
+    ppc_handle_align (FRAGP);
+
+extern void ppc_handle_align (struct frag *);
+
+#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 
 #define md_frag_check(FRAGP) \
   if ((FRAGP)->has_code							\
@@ -117,7 +98,7 @@ extern char *ppc_target_format PARAMS ((void));
 
 /* Don't adjust TOC relocs.  */
 #define tc_fix_adjustable(FIX) ppc_pe_fix_adjustable (FIX)
-extern int ppc_pe_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_pe_fix_adjustable (struct fix *);
 
 #endif
 
@@ -165,31 +146,31 @@ struct ppc_tc_sy
 
 /* Canonicalize the symbol name.  */
 #define tc_canonicalize_symbol_name(name) ppc_canonicalize_symbol_name (name)
-extern char *ppc_canonicalize_symbol_name PARAMS ((char *));
+extern char *ppc_canonicalize_symbol_name (char *);
 
 /* Get the symbol class from the name.  */
 #define tc_symbol_new_hook(sym) ppc_symbol_new_hook (sym)
-extern void ppc_symbol_new_hook PARAMS ((symbolS *));
+extern void ppc_symbol_new_hook (symbolS *);
 
 /* Set the symbol class of a label based on the csect.  */
 #define tc_frob_label(sym) ppc_frob_label (sym)
-extern void ppc_frob_label PARAMS ((symbolS *));
+extern void ppc_frob_label (symbolS *);
 
 /* TOC relocs requires special handling.  */
 #define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
-extern int ppc_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_fix_adjustable (struct fix *);
 
 /* We need to set the section VMA.  */
 #define tc_frob_section(sec) ppc_frob_section (sec)
-extern void ppc_frob_section PARAMS ((asection *));
+extern void ppc_frob_section (asection *);
 
 /* Finish up the symbol.  */
 #define tc_frob_symbol(sym, punt) punt = ppc_frob_symbol (sym)
-extern int ppc_frob_symbol PARAMS ((symbolS *));
+extern int ppc_frob_symbol (symbolS *);
 
 /* Finish up the entire symtab.  */
 #define tc_adjust_symtab() ppc_adjust_symtab ()
-extern void ppc_adjust_symtab PARAMS ((void));
+extern void ppc_adjust_symtab (void);
 
 /* We also need to copy, in particular, the class of the symbol,
    over what obj-coff would otherwise have copied.  */
@@ -211,10 +192,10 @@ extern const char       ppc_symbol_chars[];
 #ifdef OBJ_ELF
 
 /* Support for SHF_EXCLUDE and SHT_ORDERED */
-extern int ppc_section_letter PARAMS ((int, char **));
-extern int ppc_section_type PARAMS ((char *, size_t));
-extern int ppc_section_word PARAMS ((char *, size_t));
-extern int ppc_section_flags PARAMS ((int, int, int));
+extern int ppc_section_letter (int, char **);
+extern int ppc_section_type (char *, size_t);
+extern int ppc_section_word (char *, size_t);
+extern int ppc_section_flags (int, int, int);
 
 #define md_elf_section_letter(LETTER, PTR_MSG)	ppc_section_letter (LETTER, PTR_MSG)
 #define md_elf_section_type(STR, LEN)		ppc_section_type (STR, LEN)
@@ -226,40 +207,40 @@ extern const char *ppc_comment_chars;
 
 /* Keep relocations relative to the GOT, or non-PC relative.  */
 #define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
-extern int ppc_fix_adjustable PARAMS ((struct fix *));
+extern int ppc_fix_adjustable (struct fix *);
 
 /* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_frob_file_before_adjust ppc_frob_file_before_adjust
-extern void ppc_frob_file_before_adjust PARAMS ((void));
+extern void ppc_frob_file_before_adjust (void);
 
 #endif /* OBJ_ELF */
 
 #if defined (OBJ_ELF) || defined (OBJ_XCOFF)
 #define TC_FORCE_RELOCATION(FIX) ppc_force_relocation (FIX)
-extern int ppc_force_relocation PARAMS ((struct fix *));
+extern int ppc_force_relocation (struct fix *);
 #endif
 
 /* call md_pcrel_from_section, not md_pcrel_from */
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define md_parse_name(name, exp, mode, c) ppc_parse_name (name, exp)
-extern int ppc_parse_name PARAMS ((const char *, struct expressionS *));
+extern int ppc_parse_name (const char *, struct expressionS *);
 
 #define md_operand(x)
 
 #define md_cleanup() ppc_cleanup ()
- extern void ppc_cleanup PARAMS ((void));
+extern void ppc_cleanup (void);
 
 #define TARGET_USE_CFIPOP 1
 
 #define tc_cfi_frame_initial_instructions ppc_cfi_frame_initial_instructions
-extern void ppc_cfi_frame_initial_instructions PARAMS ((void));
+extern void ppc_cfi_frame_initial_instructions (void);
 
 #define tc_regname_to_dw2regnum tc_ppc_regname_to_dw2regnum
-extern int tc_ppc_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_ppc_regname_to_dw2regnum (char *);
 
 extern int ppc_cie_data_alignment;
 
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 56b5b2594f8f..6ca31f7b43b4 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -1,5 +1,5 @@
 /* tc-s390.c -- Assemble for the S390
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -412,6 +411,8 @@ md_parse_option (c, arg)
 	    current_cpu = S390_OPCODE_Z990;
 	  else if (strcmp (arg + 5, "z9-109") == 0)
 	    current_cpu = S390_OPCODE_Z9_109;
+	  else if (strcmp (arg + 5, "z9-ec") == 0)
+	    current_cpu = S390_OPCODE_Z9_EC;
 	  else
 	    {
 	      as_bad (_("invalid switch -m%s"), arg);
@@ -2322,7 +2323,7 @@ s390_cfi_frame_initial_instructions ()
 }
 
 int
-tc_s390_regname_to_dw2regnum (const char *regname)
+tc_s390_regname_to_dw2regnum (char *regname)
 {
   int regnum = -1;
 
diff --git a/gas/config/tc-s390.h b/gas/config/tc-s390.h
index dbecfef3a553..b387c3b867dc 100644
--- a/gas/config/tc-s390.h
+++ b/gas/config/tc-s390.h
@@ -88,7 +88,7 @@ extern void s390_md_end PARAMS ((void));
 extern void s390_cfi_frame_initial_instructions PARAMS ((void));
 
 #define tc_regname_to_dw2regnum tc_s390_regname_to_dw2regnum
-extern int tc_s390_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int tc_s390_regname_to_dw2regnum PARAMS ((char *regname));
 
 extern int s390_cie_data_alignment;
 
diff --git a/gas/config/tc-score.c b/gas/config/tc-score.c
new file mode 100644
index 000000000000..fe45b00bad6d
--- /dev/null
+++ b/gas/config/tc-score.c
@@ -0,0 +1,6661 @@
+/* tc-score.c -- Assembler for Score
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by:
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "config.h"
+#include "subsegs.h"
+#include "safe-ctype.h"
+#include "opcode/score-inst.h"
+#include "opcode/score-datadep.h"
+#include "struc-symbol.h"
+
+#ifdef OBJ_ELF
+#include "elf/score.h"
+#include "dwarf2dbg.h"
+#endif
+
+#define GP                     28
+#define PIC_CALL_REG           29
+#define MAX_LITERAL_POOL_SIZE  1024
+#define FAIL	               0x80000000
+#define SUCCESS         0
+#define INSN_SIZE       4
+#define INSN16_SIZE     2
+#define RELAX_INST_NUM  3
+
+/* For score5u : div/mul will pop warning message, mmu/alw/asw will pop error message.  */
+#define BAD_ARGS 	          _("bad arguments to instruction")
+#define BAD_PC 		          _("r15 not allowed here")
+#define BAD_COND 	          _("instruction is not conditional")
+#define ERR_NO_ACCUM	          _("acc0 expected")
+#define ERR_FOR_SCORE5U_MUL_DIV   _("div / mul are reserved instructions")
+#define ERR_FOR_SCORE5U_MMU       _("This architecture doesn't support mmu")
+#define ERR_FOR_SCORE5U_ATOMIC    _("This architecture doesn't support atomic instruction")
+#define LONG_LABEL_LEN            _("the label length is longer than 1024");
+#define BAD_SKIP_COMMA            BAD_ARGS
+#define BAD_GARBAGE               _("garbage following instruction");
+
+#define skip_whitespace(str)  while (*(str) == ' ') ++(str)
+
+/* The name of the readonly data section.  */
+#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
+			    ? ".data" \
+			    : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
+			    ? ".rdata" \
+			    : OUTPUT_FLAVOR == bfd_target_coff_flavour \
+			    ? ".rdata" \
+			    : OUTPUT_FLAVOR == bfd_target_elf_flavour \
+			    ? ".rodata" \
+			    : (abort (), ""))
+
+#define RELAX_ENCODE(old, new, type, reloc1, reloc2, opt) \
+  ((relax_substateT) \
+   (((old) << 23) \
+    | ((new) << 16) \
+    | ((type) << 9) \
+    | ((reloc1) << 5) \
+    | ((reloc2) << 1) \
+    | ((opt) ? 1 : 0)))
+
+#define RELAX_OLD(i)       (((i) >> 23) & 0x7f)
+#define RELAX_NEW(i)       (((i) >> 16) & 0x7f)
+#define RELAX_TYPE(i)      (((i) >> 9) & 0x7f)
+#define RELAX_RELOC1(i)    ((valueT) ((i) >> 5) & 0xf)
+#define RELAX_RELOC2(i)    ((valueT) ((i) >> 1) & 0xf)
+#define RELAX_OPT(i)       ((i) & 1)
+#define RELAX_OPT_CLEAR(i) ((i) & ~1)
+
+#define SET_INSN_ERROR(s) (inst.error = (s))
+#define INSN_IS_PCE_P(s)  (strstr (str, "||") != NULL)
+
+#define GET_INSN_CLASS(type) (get_insn_class_from_type (type))
+
+#define GET_INSN_SIZE(type) ((GET_INSN_CLASS (type) == INSN_CLASS_16) \
+                             ? INSN16_SIZE : INSN_SIZE)
+
+/* This array holds the chars that always start a comment.  If the
+   pre-processor is disabled, these aren't very useful.  */
+const char comment_chars[] = "#";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point numbers.  */
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+
+/* Used to contain constructed error messages.  */
+static char err_msg[255];
+
+fragS *score_fragp = 0;
+static int fix_data_dependency = 0;
+static int warn_fix_data_dependency = 1;
+static int score7 = 1;
+static int university_version = 0;
+
+static int in_my_get_expression = 0;
+
+#define USE_GLOBAL_POINTER_OPT 1
+#define SCORE_BI_ENDIAN
+
+/* Default, pop warning message when using r1.  */
+static int nor1 = 1;
+
+/* Default will do instruction relax, -O0 will set g_opt = 0.  */
+static unsigned int g_opt = 1;
+
+/* The size of the small data section.  */
+static unsigned int g_switch_value = 8;
+
+#ifdef OBJ_ELF
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
+symbolS *GOT_symbol;
+#endif
+static segT pdr_seg;
+
+enum score_pic_level score_pic = NO_PIC;
+
+#define INSN_NAME_LEN 16
+struct score_it
+{
+  char name[INSN_NAME_LEN];
+  unsigned long instruction;
+  unsigned long relax_inst;
+  int size;
+  int relax_size;
+  enum score_insn_type type;
+  char str[MAX_LITERAL_POOL_SIZE];
+  const char *error;
+  int bwarn;
+  char reg[INSN_NAME_LEN];
+  struct
+  {
+    bfd_reloc_code_real_type type;
+    expressionS exp;
+    int pc_rel;
+  }reloc;
+};
+struct score_it inst;
+
+typedef struct proc
+{
+  symbolS *isym;
+  unsigned long reg_mask;
+  unsigned long reg_offset;
+  unsigned long fpreg_mask;
+  unsigned long leaf;
+  unsigned long frame_offset;
+  unsigned long frame_reg;
+  unsigned long pc_reg;
+}
+procS;
+
+static procS cur_proc;
+static procS *cur_proc_ptr;
+static int numprocs;
+
+#define SCORE7_PIPELINE 7
+#define SCORE5_PIPELINE 5
+static int vector_size = SCORE7_PIPELINE;
+struct score_it dependency_vector[SCORE7_PIPELINE];
+
+/* Relax will need some padding for alignment.  */
+#define RELAX_PAD_BYTE 3
+
+/* Number of littlenums required to hold an extended precision number.  For md_atof.  */
+#define NUM_FLOAT_VALS 8
+#define MAX_LITTLENUMS 6
+LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
+
+/* Structure for a hash table entry for a register.  */
+struct reg_entry
+{
+  const char *name;
+  int number;
+};
+
+static const struct reg_entry score_rn_table[] =
+{
+  {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
+  {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
+  {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
+  {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15},
+  {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19},
+  {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23},
+  {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27},
+  {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31},
+  {NULL, 0}
+};
+
+static const struct reg_entry score_srn_table[] =
+{
+  {"sr0", 0}, {"sr1", 1}, {"sr2", 2},
+  {NULL, 0}
+};
+
+static const struct reg_entry score_crn_table[] =
+{
+  {"cr0", 0}, {"cr1", 1}, {"cr2", 2}, {"cr3", 3},
+  {"cr4", 4}, {"cr5", 5}, {"cr6", 6}, {"cr7", 7},
+  {"cr8", 8}, {"cr9", 9}, {"cr10", 10}, {"cr11", 11},
+  {"cr12", 12}, {"cr13", 13}, {"cr14", 14}, {"cr15", 15},
+  {"cr16", 16}, {"cr17", 17}, {"cr18", 18}, {"cr19", 19},
+  {"cr20", 20}, {"cr21", 21}, {"cr22", 22}, {"cr23", 23},
+  {"cr24", 24}, {"cr25", 25}, {"cr26", 26}, {"cr27", 27},
+  {"cr28", 28}, {"cr29", 29}, {"cr30", 30}, {"cr31", 31},
+  {NULL, 0}
+};
+
+struct reg_map
+{
+  const struct reg_entry *names;
+  int max_regno;
+  struct hash_control *htab;
+  const char *expected;
+};
+
+struct reg_map all_reg_maps[] =
+{
+  {score_rn_table, 31, NULL, N_("S+core register expected")},
+  {score_srn_table, 2, NULL, N_("S+core special-register expected")},
+  {score_crn_table, 31, NULL, N_("S+core co-processor register expected")},
+};
+
+static struct hash_control *score_ops_hsh = NULL;
+
+static struct hash_control *dependency_insn_hsh = NULL;
+
+/* Enumeration matching entries in table above.  */
+enum score_reg_type
+{
+  REG_TYPE_SCORE = 0,
+#define REG_TYPE_FIRST REG_TYPE_SCORE
+  REG_TYPE_SCORE_SR = 1,
+  REG_TYPE_SCORE_CR = 2,
+  REG_TYPE_MAX = 3
+};
+
+typedef struct literalS
+{
+  struct expressionS exp;
+  struct score_it *inst;
+}
+literalT;
+
+literalT literals[MAX_LITERAL_POOL_SIZE];
+
+static void do_ldst_insn (char *);
+static void do_crdcrscrsimm5 (char *);
+static void do_ldst_unalign (char *);
+static void do_ldst_atomic (char *);
+static void do_ldst_cop (char *);
+static void do_macro_li_rdi32 (char *);
+static void do_macro_la_rdi32 (char *);
+static void do_macro_rdi32hi (char *);
+static void do_macro_rdi32lo (char *);
+static void do_macro_mul_rdrsrs (char *);
+static void do_macro_ldst_label (char *);
+static void do_branch (char *);
+static void do_jump (char *);
+static void do_empty (char *);
+static void do_rdrsrs (char *);
+static void do_rdsi16 (char *);
+static void do_rdrssi14 (char *);
+static void do_sub_rdsi16 (char *);
+static void do_sub_rdrssi14 (char *);
+static void do_rdrsi5 (char *);
+static void do_rdrsi14 (char *);
+static void do_rdi16 (char *);
+static void do_xrsi5 (char *);
+static void do_rdrs (char *);
+static void do_rdxrs (char *);
+static void do_rsrs (char *);
+static void do_rdcrs (char *);
+static void do_rdsrs (char *);
+static void do_rd (char *);
+static void do_rs (char *);
+static void do_i15 (char *);
+static void do_xi5x (char *);
+static void do_ceinst (char *);
+static void do_cache (char *);
+static void do16_rdrs (char *);
+static void do16_rs (char *);
+static void do16_xrs (char *);
+static void do16_mv_rdrs (char *);
+static void do16_hrdrs (char *);
+static void do16_rdhrs (char *);
+static void do16_rdi4 (char *);
+static void do16_rdi5 (char *);
+static void do16_xi5 (char *);
+static void do16_ldst_insn (char *);
+static void do16_ldst_imm_insn (char *);
+static void do16_push_pop (char *);
+static void do16_branch (char *);
+static void do16_jump (char *);
+static void do_rdi16_pic (char *);
+static void do_addi_s_pic (char *);
+static void do_addi_u_pic (char *);
+static void do_lw_pic (char *);
+
+static const struct asm_opcode score_ldst_insns[] = 
+{
+  {"lw",        0x20000000, 0x3e000000, 0x2008,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lw",        0x06000000, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lw",        0x0e000000, 0x3e000007, 0x200a,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lh",        0x22000000, 0x3e000000, 0x2009,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lh",        0x06000001, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lh",        0x0e000001, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lhu",       0x24000000, 0x3e000000, 0x8000,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lhu",       0x06000002, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lhu",       0x0e000002, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"lb",        0x26000000, 0x3e000000, 0x8000,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lb",        0x06000003, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lb",        0x0e000003, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"sw",        0x28000000, 0x3e000000, 0x200c,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sw",        0x06000004, 0x3e000007, 0x200e,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sw",        0x0e000004, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+  {"sh",        0x2a000000, 0x3e000000, 0x200d,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sh",        0x06000005, 0x3e000007, 0x8000,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sh",        0x0e000005, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+  {"lbu",       0x2c000000, 0x3e000000, 0x200b,     Rd_rvalueRs_SI15,     do_ldst_insn},
+  {"lbu",       0x06000006, 0x3e000007, 0x8000,     Rd_rvalueRs_preSI12,  do_ldst_insn},
+  {"lbu",       0x0e000006, 0x3e000007, 0x8000,     Rd_rvalueRs_postSI12, do_ldst_insn},
+  {"sb",        0x2e000000, 0x3e000000, 0x200f,     Rd_lvalueRs_SI15,     do_ldst_insn},
+  {"sb",        0x06000007, 0x3e000007, 0x8000,     Rd_lvalueRs_preSI12,  do_ldst_insn},
+  {"sb",        0x0e000007, 0x3e000007, 0x8000,     Rd_lvalueRs_postSI12, do_ldst_insn},
+};
+
+static const struct asm_opcode score_insns[] = 
+{
+  {"abs",       0x3800000a, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"abs.s",     0x3800004b, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"add",       0x00000010, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"add.c",     0x00000011, 0x3e0003ff, 0x2000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"add.s",     0x38000048, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addc",      0x00000012, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addc.c",    0x00000013, 0x3e0003ff, 0x0009,     Rd_Rs_Rs,             do_rdrsrs},
+  {"addi",      0x02000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"addi.c",    0x02000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"addis",     0x0a000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdi16},
+  {"addis.c",   0x0a000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdi16},
+  {"addri",     0x10000000, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_rdrssi14},
+  {"addri.c",   0x10000001, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_rdrssi14},
+  {"addc!",     0x0009,     0x700f,     0x00000013, Rd_Rs,                do16_rdrs},
+  {"add!",      0x2000,     0x700f,     0x00000011, Rd_Rs,                do16_rdrs},
+  {"addei!",    0x6000    , 0x7087,     0x02000001, Rd_I4,                do16_rdi4},
+  {"subi",      0x02000000, 0x3e0e0001, 0x8000,     Rd_SI16,              do_sub_rdsi16},
+  {"subi.c",    0x02000001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_sub_rdsi16},
+  {"subri",     0x10000000, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_sub_rdrssi14},
+  {"subri.c",   0x10000001, 0x3e000001, 0x8000,     Rd_Rs_SI14,           do_sub_rdrssi14},
+  {"and",       0x00000020, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"and.c",     0x00000021, 0x3e0003ff, 0x2004,     Rd_Rs_Rs,             do_rdrsrs},
+  {"andi",      0x02080000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andi.c",    0x02080001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andis",     0x0a080000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andis.c",   0x0a080001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"andri",     0x18000000, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"andri.c",   0x18000001, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"and!",      0x2004,     0x700f,     0x00000021, Rd_Rs,                do16_rdrs},
+  {"bcs",       0x08000000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcc",       0x08000400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcnz",      0x08003800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bcsl",      0x08000001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bccl",      0x08000401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bcnzl",     0x08003801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bcs!",      0x4000,     0x7f00,     0x08000000, PC_DISP8div2,         do16_branch},
+  {"bcc!",      0x4100,     0x7f00,     0x08000400, PC_DISP8div2,         do16_branch},
+  {"bcnz!",     0x4e00,     0x7f00,     0x08003800, PC_DISP8div2,         do16_branch},
+  {"beq",       0x08001000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"beql",      0x08001001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"beq!",      0x4400,     0x7f00,     0x08001000, PC_DISP8div2,         do16_branch},
+  {"bgtu",      0x08000800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bgt",       0x08001800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bge",       0x08002000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bgtul",     0x08000801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgtl",      0x08001801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgel",      0x08002001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bgtu!",     0x4200,     0x7f00,     0x08000800, PC_DISP8div2,         do16_branch},
+  {"bgt!",      0x4600,     0x7f00,     0x08001800, PC_DISP8div2,         do16_branch},
+  {"bge!",      0x4800,     0x7f00,     0x08002000, PC_DISP8div2,         do16_branch},
+  {"bitclr.c",  0x00000029, 0x3e0003ff, 0x6004,     Rd_Rs_I5,             do_rdrsi5},
+  {"bitrev",    0x3800000c, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"bitset.c",  0x0000002b, 0x3e0003ff, 0x6005,     Rd_Rs_I5,             do_rdrsi5},
+  {"bittst.c",  0x0000002d, 0x3e0003ff, 0x6006,     x_Rs_I5,              do_xrsi5},
+  {"bittgl.c",  0x0000002f, 0x3e0003ff, 0x6007,     Rd_Rs_I5,             do_rdrsi5},
+  {"bitclr!",   0x6004,     0x7007,     0x00000029, Rd_I5,                do16_rdi5},
+  {"bitset!",   0x6005,     0x7007,     0x0000002b, Rd_I5,                do16_rdi5},
+  {"bittst!",   0x6006,     0x7007,     0x0000002d, Rd_I5,                do16_rdi5},
+  {"bittgl!",   0x6007,     0x7007,     0x0000002f, Rd_I5,                do16_rdi5},
+  {"bleu",      0x08000c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"ble",       0x08001c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"blt",       0x08002400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bleul",     0x08000c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"blel",      0x08001c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bltl",      0x08002401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bl",        0x08003c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bleu!",     0x4300,     0x7f00,     0x08000c00, PC_DISP8div2,         do16_branch},
+  {"ble!",      0x4700,     0x7f00,     0x08001c00, PC_DISP8div2,         do16_branch},
+  {"blt!",      0x4900,     0x7f00,     0x08002400, PC_DISP8div2,         do16_branch},
+  {"bmi",       0x08002800, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bmil",      0x08002801, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bmi!",      0x00004a00, 0x00007f00, 0x08002800, PC_DISP8div2,         do16_branch},
+  {"bne",       0x08001400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bnel",      0x08001401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bne!",      0x4500,     0x7f00,     0x08001400, PC_DISP8div2,         do16_branch},
+  {"bpl",       0x08002c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bpll",      0x08002c01, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bpl!",      0x4b00,     0x7f00,     0x08002c00, PC_DISP8div2,         do16_branch},
+  {"brcs",      0x00000008, 0x3e007fff, 0x0004,     x_Rs_x,               do_rs},
+  {"brcc",      0x00000408, 0x3e007fff, 0x0104,     x_Rs_x,               do_rs},
+  {"brgtu",     0x00000808, 0x3e007fff, 0x0204,     x_Rs_x,               do_rs},
+  {"brleu",     0x00000c08, 0x3e007fff, 0x0304,     x_Rs_x,               do_rs},
+  {"breq",      0x00001008, 0x3e007fff, 0x0404,     x_Rs_x,               do_rs},
+  {"brne",      0x00001408, 0x3e007fff, 0x0504,     x_Rs_x,               do_rs},
+  {"brgt",      0x00001808, 0x3e007fff, 0x0604,     x_Rs_x,               do_rs},
+  {"brle",      0x00001c08, 0x3e007fff, 0x0704,     x_Rs_x,               do_rs},
+  {"brge",      0x00002008, 0x3e007fff, 0x0804,     x_Rs_x,               do_rs},
+  {"brlt",      0x00002408, 0x3e007fff, 0x0904,     x_Rs_x,               do_rs},
+  {"brmi",      0x00002808, 0x3e007fff, 0x0a04,     x_Rs_x,               do_rs},
+  {"brpl",      0x00002c08, 0x3e007fff, 0x0b04,     x_Rs_x,               do_rs},
+  {"brvs",      0x00003008, 0x3e007fff, 0x0c04,     x_Rs_x,               do_rs},
+  {"brvc",      0x00003408, 0x3e007fff, 0x0d04,     x_Rs_x,               do_rs},
+  {"brcnz",     0x00003808, 0x3e007fff, 0x0e04,     x_Rs_x,               do_rs},
+  {"br",        0x00003c08, 0x3e007fff, 0x0f04,     x_Rs_x,               do_rs},
+  {"brcsl",     0x00000009, 0x3e007fff, 0x000c,     x_Rs_x,               do_rs},
+  {"brccl",     0x00000409, 0x3e007fff, 0x010c,     x_Rs_x,               do_rs},
+  {"brgtul",    0x00000809, 0x3e007fff, 0x020c,     x_Rs_x,               do_rs},
+  {"brleul",    0x00000c09, 0x3e007fff, 0x030c,     x_Rs_x,               do_rs},
+  {"breql",     0x00001009, 0x3e007fff, 0x040c,     x_Rs_x,               do_rs}, 
+  {"brnel",     0x00001409, 0x3e007fff, 0x050c,     x_Rs_x,               do_rs},
+  {"brgtl",     0x00001809, 0x3e007fff, 0x060c,     x_Rs_x,               do_rs},
+  {"brlel",     0x00001c09, 0x3e007fff, 0x070c,     x_Rs_x,               do_rs},
+  {"brgel",     0x00002009, 0x3e007fff, 0x080c,     x_Rs_x,               do_rs},
+  {"brltl",     0x00002409, 0x3e007fff, 0x090c,     x_Rs_x,               do_rs},
+  {"brmil",     0x00002809, 0x3e007fff, 0x0a0c,     x_Rs_x,               do_rs},
+  {"brpll",     0x00002c09, 0x3e007fff, 0x0b0c,     x_Rs_x,               do_rs},
+  {"brvsl",     0x00003009, 0x3e007fff, 0x0c0c,     x_Rs_x,               do_rs},
+  {"brvcl",     0x00003409, 0x3e007fff, 0x0d0c,     x_Rs_x,               do_rs},
+  {"brcnzl",    0x00003809, 0x3e007fff, 0x0e0c,     x_Rs_x,               do_rs},
+  {"brl",       0x00003c09, 0x3e007fff, 0x0f0c,     x_Rs_x,               do_rs},
+  {"brcs!",     0x0004,     0x7f0f,     0x00000008, x_Rs,                 do16_xrs},
+  {"brcc!",     0x0104,     0x7f0f,     0x00000408, x_Rs,                 do16_xrs},
+  {"brgtu!",    0x0204,     0x7f0f,     0x00000808, x_Rs,                 do16_xrs},
+  {"brleu!",    0x0304,     0x7f0f,     0x00000c08, x_Rs,                 do16_xrs},
+  {"breq!",     0x0404,     0x7f0f,     0x00001008, x_Rs,                 do16_xrs},
+  {"brne!",     0x0504,     0x7f0f,     0x00001408, x_Rs,                 do16_xrs},
+  {"brgt!",     0x0604,     0x7f0f,     0x00001808, x_Rs,                 do16_xrs},
+  {"brle!",     0x0704,     0x7f0f,     0x00001c08, x_Rs,                 do16_xrs},
+  {"brge!",     0x0804,     0x7f0f,     0x00002008, x_Rs,                 do16_xrs},
+  {"brlt!",     0x0904,     0x7f0f,     0x00002408, x_Rs,                 do16_xrs},
+  {"brmi!",     0x0a04,     0x7f0f,     0x00002808, x_Rs,                 do16_xrs},
+  {"brpl!",     0x0b04,     0x7f0f,     0x00002c08, x_Rs,                 do16_xrs},
+  {"brvs!",     0x0c04,     0x7f0f,     0x00003008, x_Rs,                 do16_xrs},
+  {"brvc!",     0x0d04,     0x7f0f,     0x00003408, x_Rs,                 do16_xrs},
+  {"brcnz!",    0x0e04,     0x7f0f,     0x00003808, x_Rs,                 do16_xrs},
+  {"br!",       0x0f04,     0x7f0f,     0x00003c08, x_Rs,                 do16_xrs},
+  {"brcsl!",    0x000c,     0x7f0f,     0x00000009, x_Rs,                 do16_xrs},
+  {"brccl!",    0x010c,     0x7f0f,     0x00000409, x_Rs,                 do16_xrs},
+  {"brgtul!",   0x020c,     0x7f0f,     0x00000809, x_Rs,                 do16_xrs},
+  {"brleul!",   0x030c,     0x7f0f,     0x00000c09, x_Rs,                 do16_xrs},
+  {"breql!",    0x040c,     0x7f0f,     0x00001009, x_Rs,                 do16_xrs},
+  {"brnel!",    0x050c,     0x7f0f,     0x00001409, x_Rs,                 do16_xrs},
+  {"brgtl!",    0x060c,     0x7f0f,     0x00001809, x_Rs,                 do16_xrs},
+  {"brlel!",    0x070c,     0x7f0f,     0x00001c09, x_Rs,                 do16_xrs},
+  {"brgel!",    0x080c,     0x7f0f,     0x00002009, x_Rs,                 do16_xrs},
+  {"brltl!",    0x090c,     0x7f0f,     0x00002409, x_Rs,                 do16_xrs},
+  {"brmil!",    0x0a0c,     0x7f0f,     0x00002809, x_Rs,                 do16_xrs},
+  {"brpll!",    0x0b0c,     0x7f0f,     0x00002c09, x_Rs,                 do16_xrs},
+  {"brvsl!",    0x0c0c,     0x7f0f,     0x00003009, x_Rs,                 do16_xrs},
+  {"brvcl!",    0x0d0c,     0x7f0f,     0x00003409, x_Rs,                 do16_xrs},
+  {"brcnzl!",   0x0e0c,     0x7f0f,     0x00003809, x_Rs,                 do16_xrs},
+  {"brl!",      0x0f0c,     0x7f0f,     0x00003c09, x_Rs,                 do16_xrs},
+  {"bvs",       0x08003000, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bvc",       0x08003400, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"bvsl",      0x08003001, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bvcl",      0x08003401, 0x3e007c01, 0x8000,     PC_DISP19div2,        do_branch},
+  {"bvs!",      0x4c00,     0x7f00,     0x08003000, PC_DISP8div2,         do16_branch},
+  {"bvc!",      0x4d00,     0x7f00,     0x08003400, PC_DISP8div2,         do16_branch},
+  {"b!",        0x4f00,     0x7f00,     0x08003c00, PC_DISP8div2,         do16_branch},
+  {"b",         0x08003c00, 0x3e007c01, 0x4000,     PC_DISP19div2,        do_branch},
+  {"cache",     0x30000000, 0x3ff00000, 0x8000,     OP5_rvalueRs_SI15,    do_cache},
+  {"ceinst",    0x38000000, 0x3e000000, 0x8000,     I5_Rs_Rs_I5_OP5,      do_ceinst},
+  {"clz",       0x3800000d, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"cmpteq.c",  0x00000019, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"cmptmi.c",  0x00100019, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"cmp.c",     0x00300019, 0x3ff003ff, 0x2003,     x_Rs_Rs,              do_rsrs},
+  {"cmpzteq.c", 0x0000001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpztmi.c", 0x0010001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpz.c",    0x0030001b, 0x3ff07fff, 0x8000,     x_Rs_x,               do_rs},
+  {"cmpi.c",    0x02040001, 0x3e0e0001, 0x8000,     Rd_SI16,              do_rdsi16},
+  {"cmp!",      0x2003,     0x700f,     0x00300019, Rd_Rs,                do16_rdrs},
+  {"cop1",      0x0c00000c, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"cop2",      0x0c000014, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"cop3",      0x0c00001c, 0x3e00001f, 0x8000,     Rd_Rs_Rs_imm,         do_crdcrscrsimm5},
+  {"drte",      0x0c0000a4, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"extsb",     0x00000058, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsb.c",   0x00000059, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsh",     0x0000005a, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extsh.c",   0x0000005b, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzb",     0x0000005c, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzb.c",   0x0000005d, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzh",     0x0000005e, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"extzh.c",   0x0000005f, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"jl",        0x04000001, 0x3e000001, 0x8000,     PC_DISP24div2,        do_jump},
+  {"jl!",       0x3001,     0x7001,     0x04000001, PC_DISP11div2,        do16_jump},
+  {"j!",        0x3000,     0x7001,     0x04000000, PC_DISP11div2,        do16_jump},
+  {"j",         0x04000000, 0x3e000001, 0x8000,     PC_DISP24div2,        do_jump},
+  {"lbu!",      0x200b,     0x0000700f, 0x2c000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lbup!",     0x7003,     0x7007,     0x2c000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"alw",       0x0000000c, 0x3e0003ff, 0x8000,     Rd_rvalue32Rs,        do_ldst_atomic},
+  {"lcb",       0x00000060, 0x3e0003ff, 0x8000,     x_rvalueRs_post4,     do_ldst_unalign},
+  {"lcw",       0x00000062, 0x3e0003ff, 0x8000,     Rd_rvalueRs_post4,    do_ldst_unalign},
+  {"lce",       0x00000066, 0x3e0003ff, 0x8000,     Rd_rvalueRs_post4,    do_ldst_unalign},
+  {"ldc1",      0x0c00000a, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"ldc2",      0x0c000012, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"ldc3",      0x0c00001a, 0x3e00001f, 0x8000,     Rd_rvalueRs_SI10,     do_ldst_cop},
+  {"lh!",       0x2009,     0x700f,     0x22000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lhp!",      0x7001,     0x7007,     0x22000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"ldi",       0x020c0000, 0x3e0e0000, 0x5000,     Rd_SI16,              do_rdsi16},
+  {"ldis",      0x0a0c0000, 0x3e0e0000, 0x8000,     Rd_I16,               do_rdi16},
+  {"ldiu!",     0x5000,     0x7000,     0x020c0000, Rd_I8,                do16_ldst_imm_insn},
+  {"lw!",       0x2008,     0x700f,     0x20000000, Rd_rvalueRs,          do16_ldst_insn},
+  {"lwp!",      0x7000,     0x7007,     0x20000000, Rd_rvalueBP_I5,       do16_ldst_imm_insn},
+  {"mfcel",     0x00000448, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mfcel!",    0x1001,     0x7f0f,     0x00000448, x_Rs,                 do16_rs},
+  {"mad",       0x38000000, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mad.f!",    0x1004,     0x700f,     0x38000080, Rd_Rs,                do16_rdrs},
+  {"madh",      0x38000203, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madh.fs",   0x380002c3, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madh.fs!",  0x100b,     0x700f,     0x380002c3, Rd_Rs,                do16_rdrs},
+  {"madl",      0x38000002, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madl.fs",   0x380000c2, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madl.fs!",  0x100a,     0x700f,     0x380000c2, Rd_Rs,                do16_rdrs},
+  {"madu",      0x38000020, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"madu!",     0x1005,     0x700f,     0x38000020, Rd_Rs,                do16_rdrs},
+  {"mad.f",     0x38000080, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"max",       0x38000007, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"mazh",      0x38000303, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazh.f",    0x38000383, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazh.f!",   0x1009,     0x700f,     0x3800038c, Rd_Rs,                do16_rdrs},
+  {"mazl",      0x38000102, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazl.f",    0x38000182, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mazl.f!",   0x1008,     0x700f,     0x38000182, Rd_Rs,                do16_rdrs},
+  {"mfceh",     0x00000848, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mfceh!",    0x1101,     0x7f0f,     0x00000848, x_Rs,                 do16_rs},
+  {"mfcehl",    0x00000c48, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mfsr",      0x00000050, 0x3e0003ff, 0x8000,     Rd_x_I5,              do_rdsrs},
+  {"mfcr",      0x0c000001, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc1",      0x0c000009, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc2",      0x0c000011, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfc3",      0x0c000019, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc1",     0x0c00000f, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc2",     0x0c000017, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mfcc3",     0x0c00001f, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mhfl!",     0x0002,     0x700f,     0x00003c56, Rd_LowRs,             do16_hrdrs},
+  {"min",       0x38000006, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"mlfh!",     0x0001,     0x700f,     0x00003c56, Rd_HighRs,            do16_rdhrs},
+  {"msb",       0x38000001, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msb.f!",    0x1006,     0x700f,     0x38000081, Rd_Rs,                do16_rdrs},
+  {"msbh",      0x38000205, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbh.fs",   0x380002c5, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbh.fs!",  0x100f,     0x700f,     0x380002c5, Rd_Rs,                do16_rdrs},
+  {"msbl",      0x38000004, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbl.fs",   0x380000c4, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbl.fs!",  0x100e,     0x700f,     0x380000c4, Rd_Rs,                do16_rdrs},
+  {"msbu",      0x38000021, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"msbu!",     0x1007,     0x700f,     0x38000021, Rd_Rs,                do16_rdrs},
+  {"msb.f",     0x38000081, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh",      0x38000305, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh.f",    0x38000385, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszh.f!",   0x100d,     0x700f,     0x38000385, Rd_Rs,                do16_rdrs},
+  {"mszl",      0x38000104, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszl.f",    0x38000184, 0x3ff003ff, 0x8000,     x_Rs_Rs,              do_rsrs},
+  {"mszl.f!",   0x100c,     0x700f,     0x38000184, Rd_Rs,                do16_rdrs},
+  {"mtcel!",    0x1000,     0x7f0f,     0x0000044a, x_Rs,                 do16_rs},
+  {"mtcel",     0x0000044a, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mtceh",     0x0000084a, 0x3e007fff, 0x8000,     Rd_x_x,               do_rd},
+  {"mtceh!",    0x1100,     0x7f0f,     0x0000084a, x_Rs,                 do16_rs},
+  {"mtcehl",    0x00000c4a, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mtsr",      0x00000052, 0x3e0003ff, 0x8000,     x_Rs_I5,              do_rdsrs},
+  {"mtcr",      0x0c000000, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc1",      0x0c000008, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc2",      0x0c000010, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtc3",      0x0c000018, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc1",     0x0c00000e, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc2",     0x0c000016, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mtcc3",     0x0c00001e, 0x3e00001f, 0x8000,     Rd_Rs_x,              do_rdcrs},
+  {"mul.f!",    0x1002,     0x700f,     0x00000041, Rd_Rs,                do16_rdrs},
+  {"mulu!",     0x1003,     0x700f,     0x00000042, Rd_Rs,                do16_rdrs},
+  {"mvcs",      0x00000056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvcc",      0x00000456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvgtu",     0x00000856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvleu",     0x00000c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mveq",      0x00001056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvne",      0x00001456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvgt",      0x00001856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvle",      0x00001c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvge",      0x00002056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvlt",      0x00002456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvmi",      0x00002856, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvpl",      0x00002c56, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvvs",      0x00003056, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mvvc",      0x00003456, 0x3e007fff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"mv",        0x00003c56, 0x3e007fff, 0x0003,     Rd_Rs_x,              do_rdrs},
+  {"mv!",       0x0003,     0x700f,     0x00003c56, Rd_Rs,                do16_mv_rdrs},
+  {"neg",       0x0000001e, 0x3e0003ff, 0x8000,     Rd_x_Rs,              do_rdxrs},
+  {"neg.c",     0x0000001f, 0x3e0003ff, 0x2002,     Rd_x_Rs,              do_rdxrs},
+  {"neg!",      0x2002,     0x700f,     0x0000001f, Rd_Rs,                do16_rdrs},
+  {"nop",       0x00000000, 0x3e0003ff, 0x0000,     NO_OPD,               do_empty},
+  {"not",       0x00000024, 0x3e0003ff, 0x8000,     Rd_Rs_x,              do_rdrs},
+  {"not.c",     0x00000025, 0x3e0003ff, 0x2006,     Rd_Rs_x,              do_rdrs},
+  {"nop!",      0x0000,     0x700f,     0x00000000, NO16_OPD,               do_empty},
+  {"not!",      0x2006,     0x700f,     0x00000025, Rd_Rs,                do16_rdrs},
+  {"or",        0x00000022, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"or.c",      0x00000023, 0x3e0003ff, 0x2005,     Rd_Rs_Rs,             do_rdrsrs},
+  {"ori",       0x020a0000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"ori.c",     0x020a0001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"oris",      0x0a0a0000, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"oris.c",    0x0a0a0001, 0x3e0e0001, 0x8000,     Rd_I16,               do_rdi16},
+  {"orri",      0x1a000000, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"orri.c",    0x1a000001, 0x3e000001, 0x8000,     Rd_Rs_I14,            do_rdrsi14},
+  {"or!",       0x2005,     0x700f,     0x00000023, Rd_Rs,                do16_rdrs},
+  {"pflush",    0x0000000a, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"pop!",      0x200a,     0x700f,     0x0e000000, Rd_rvalueRs,          do16_push_pop},
+  {"push!",     0x200e,     0x700f,     0x06000004, Rd_lvalueRs,          do16_push_pop},
+  {"ror",       0x00000038, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"ror.c",     0x00000039, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rorc.c",    0x0000003b, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rol",       0x0000003c, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rol.c",     0x0000003d, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rolc.c",    0x0000003f, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"rori",      0x00000078, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rori.c",    0x00000079, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roric.c",   0x0000007b, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roli",      0x0000007c, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"roli.c",    0x0000007d, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rolic.c",   0x0000007f, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"rte",       0x0c000084, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"sb!",       0x200f,     0x700f,     0x2e000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"sbp!",      0x7007,     0x7007,     0x2e000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"asw",       0x0000000e, 0x3e0003ff, 0x8000,     Rd_lvalue32Rs,        do_ldst_atomic},
+  {"scb",       0x00000068, 0x3e0003ff, 0x8000,     Rd_lvalueRs_post4,    do_ldst_unalign},
+  {"scw",       0x0000006a, 0x3e0003ff, 0x8000,     Rd_lvalueRs_post4,    do_ldst_unalign},
+  {"sce",       0x0000006e, 0x3e0003ff, 0x8000,     x_lvalueRs_post4,     do_ldst_unalign},
+  {"sdbbp",     0x00000006, 0x3e0003ff, 0x6002,     x_I5_x,               do_xi5x},
+  {"sdbbp!",    0x6002,     0x7007,     0x00000006, Rd_I5,                do16_xi5},
+  {"sh!",       0x200d,     0x700f,     0x2a000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"shp!",      0x7005,     0x7007,     0x2a000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"sleep",     0x0c0000c4, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"sll",       0x00000030, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sll.c",     0x00000031, 0x3e0003ff, 0x0008,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sll.s",     0x3800004e, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"slli",      0x00000070, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"slli.c",    0x00000071, 0x3e0003ff, 0x6001,     Rd_Rs_I5,             do_rdrsi5},
+  {"sll!",      0x0008,     0x700f,     0x00000031, Rd_Rs,                do16_rdrs},
+  {"slli!",     0x6001,     0x7007,     0x00000071, Rd_I5,                do16_rdi5},
+  {"srl",       0x00000034, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"srl.c",     0x00000035, 0x3e0003ff, 0x000a,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sra",       0x00000036, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sra.c",     0x00000037, 0x3e0003ff, 0x000b,     Rd_Rs_Rs,             do_rdrsrs},
+  {"srli",      0x00000074, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srli.c",    0x00000075, 0x3e0003ff, 0x6003,     Rd_Rs_I5,             do_rdrsi5},
+  {"srai",      0x00000076, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srai.c",    0x00000077, 0x3e0003ff, 0x8000,     Rd_Rs_I5,             do_rdrsi5},
+  {"srl!",      0x000a,     0x700f,     0x00000035, Rd_Rs,                do16_rdrs},
+  {"sra!",      0x000b,     0x700f,     0x00000037, Rd_Rs,                do16_rdrs},
+  {"srli!",     0x6003,     0x7007,     0x00000075, Rd_Rs,                do16_rdi5},
+  {"stc1",      0x0c00000b, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"stc2",      0x0c000013, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"stc3",      0x0c00001b, 0x3e00001f, 0x8000,     Rd_lvalueRs_SI10,     do_ldst_cop},
+  {"sub",       0x00000014, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub.c",     0x00000015, 0x3e0003ff, 0x2001,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub.s",     0x38000049, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"subc",      0x00000016, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"subc.c",    0x00000017, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"sub!",      0x2001,     0x700f,     0x00000015, Rd_Rs,                do16_rdrs},
+  {"subei!",    0x6080,     0x7087,     0x02000001, Rd_I4,                do16_rdi4},
+  {"sw!",       0x200c,     0x700f,     0x28000000, Rd_lvalueRs,          do16_ldst_insn},
+  {"swp!",      0x7004,     0x7007,     0x28000000, Rd_lvalueBP_I5,       do16_ldst_imm_insn},
+  {"syscall",   0x00000002, 0x3e0003ff, 0x8000,     I15,                  do_i15},
+  {"tcs",       0x00000054, 0x3e007fff, 0x0005,     NO_OPD,               do_empty},
+  {"tcc",       0x00000454, 0x3e007fff, 0x0105,     NO_OPD,               do_empty},
+  {"tcnz",      0x00003854, 0x3e007fff, 0x0e05,     NO_OPD,               do_empty},
+  {"tcs!",      0x0005,     0x7f0f,     0x00000054, NO16_OPD,             do_empty},
+  {"tcc!",      0x0105,     0x7f0f,     0x00000454, NO16_OPD,             do_empty},
+  {"tcnz!",     0x0e05,     0x7f0f,     0x00003854, NO16_OPD,             do_empty},
+  {"teq",       0x00001054, 0x3e007fff, 0x0405,     NO_OPD,               do_empty},
+  {"teq!",      0x0405,     0x7f0f,     0x00001054, NO16_OPD,             do_empty},
+  {"tgtu",      0x00000854, 0x3e007fff, 0x0205,     NO_OPD,               do_empty},
+  {"tgt",       0x00001854, 0x3e007fff, 0x0605,     NO_OPD,               do_empty},
+  {"tge",       0x00002054, 0x3e007fff, 0x0805,     NO_OPD,               do_empty},
+  {"tgtu!",     0x0205,     0x7f0f,     0x00000854, NO16_OPD,             do_empty},
+  {"tgt!",      0x0605,     0x7f0f,     0x00001854, NO16_OPD,             do_empty},
+  {"tge!",      0x0805,     0x7f0f,     0x00002054, NO16_OPD,             do_empty},
+  {"tleu",      0x00000c54, 0x3e007fff, 0x0305,     NO_OPD,               do_empty},
+  {"tle",       0x00001c54, 0x3e007fff, 0x0705,     NO_OPD,               do_empty},
+  {"tlt",       0x00002454, 0x3e007fff, 0x0905,     NO_OPD,               do_empty},
+  {"stlb",      0x0c000004, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mftlb",     0x0c000024, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mtptlb",    0x0c000044, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"mtrtlb",    0x0c000064, 0x3e0003ff, 0x8000,     NO_OPD,               do_empty},
+  {"tleu!",     0x0305,     0x7f0f,     0x00000c54, NO16_OPD,             do_empty},
+  {"tle!",      0x0705,     0x7f0f,     0x00001c54, NO16_OPD,             do_empty},
+  {"tlt!",      0x0905,     0x7f0f,     0x00002454, NO16_OPD,             do_empty},
+  {"tmi",       0x00002854, 0x3e007fff, 0x0a05,     NO_OPD,               do_empty},
+  {"tmi!",      0x0a05,     0x7f0f,     0x00002854, NO16_OPD,             do_empty},
+  {"tne",       0x00001454, 0x3e007fff, 0x0505,     NO_OPD,               do_empty},
+  {"tne!",      0x0505,     0x7f0f,     0x00001454, NO16_OPD,             do_empty},
+  {"tpl",       0x00002c54, 0x3e007fff, 0x0b05,     NO_OPD,               do_empty},
+  {"tpl!",      0x0b05,     0x7f0f,     0x00002c54, NO16_OPD,             do_empty},
+  {"trapcs",    0x00000004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapcc",    0x00000404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapgtu",   0x00000804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapleu",   0x00000c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapeq",    0x00001004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapne",    0x00001404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapgt",    0x00001804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"traple",    0x00001c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapge",    0x00002004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"traplt",    0x00002404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapmi",    0x00002804, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trappl",    0x00002c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapvs",    0x00003004, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trapvc",    0x00003404, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"trap",      0x00003c04, 0x3e007fff, 0x8000,     x_I5_x,               do_xi5x},
+  {"tset",      0x00003c54, 0x3e007fff, 0x0f05,     NO_OPD,               do_empty},
+  {"tset!",     0x0f05,     0x00007f0f, 0x00003c54, NO16_OPD,             do_empty},
+  {"tvs",       0x00003054, 0x3e007fff, 0x0c05,     NO_OPD,               do_empty},
+  {"tvc",       0x00003454, 0x3e007fff, 0x0d05,     NO_OPD,               do_empty},
+  {"tvs!",      0x0c05,     0x7f0f,     0x00003054, NO16_OPD,             do_empty},
+  {"tvc!",      0x0d05,     0x7f0f,     0x00003454, NO16_OPD,             do_empty},
+  {"xor",       0x00000026, 0x3e0003ff, 0x8000,     Rd_Rs_Rs,             do_rdrsrs},
+  {"xor.c",     0x00000027, 0x3e0003ff, 0x2007,     Rd_Rs_Rs,             do_rdrsrs},
+  {"xor!",      0x2007,     0x700f,     0x00000027, Rd_Rs,                do16_rdrs},
+  /* Macro instruction.  */
+  {"li",        0x020c0000, 0x3e0e0000, 0x8000,     Insn_Type_SYN,        do_macro_li_rdi32},
+  /* la reg, imm32        -->(1)  ldi  reg, simm16
+                             (2)  ldis reg, %HI(imm32)        
+                                  ori  reg, %LO(imm32) 
+          
+     la reg, symbol       -->(1)  lis  reg, %HI(imm32)
+                                  ori  reg, %LO(imm32)  */
+  {"la",        0x020c0000, 0x3e0e0000, 0x8000,     Insn_Type_SYN,        do_macro_la_rdi32},
+  {"div",       0x00000044, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"divu",      0x00000046, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"rem",       0x00000044, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"remu",      0x00000046, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mul",       0x00000040, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mulu",      0x00000042, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"maz",       0x00000040, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mazu",      0x00000042, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"mul.f",     0x00000041, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"maz.f",     0x00000041, 0x3e0003ff, 0x8000,     Insn_Type_SYN,        do_macro_mul_rdrsrs},
+  {"lb",        INSN_LB,    0x00000000, 0x8000,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lbu",       INSN_LBU,   0x00000000, 0x200b,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lh",        INSN_LH,    0x00000000, 0x2009,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lhu",       INSN_LHU,   0x00000000, 0x8000,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"lw",        INSN_LW,    0x00000000, 0x2008,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sb",        INSN_SB,    0x00000000, 0x200f,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sh",        INSN_SH,    0x00000000, 0x200d,     Insn_Type_SYN,        do_macro_ldst_label},
+  {"sw",        INSN_SW,    0x00000000, 0x200c,     Insn_Type_SYN,        do_macro_ldst_label},
+  /* Assembler use internal.  */
+  {"ld_i32hi",  0x0a0c0000, 0x3e0e0000, 0x8000,     Insn_internal, do_macro_rdi32hi},
+  {"ld_i32lo",  0x020a0000, 0x3e0e0001, 0x8000,     Insn_internal, do_macro_rdi32lo},
+  {"ldis_pic",  0x0a0c0000, 0x3e0e0000, 0x5000,     Insn_internal, do_rdi16_pic},
+  {"addi_s_pic",0x02000000, 0x3e0e0001, 0x8000,     Insn_internal, do_addi_s_pic},
+  {"addi_u_pic",0x02000000, 0x3e0e0001, 0x8000,     Insn_internal, do_addi_u_pic},
+  {"lw_pic",    0x20000000, 0x3e000000, 0x8000,     Insn_internal, do_lw_pic},
+};
+
+/* Next free entry in the pool.  */
+int next_literal_pool_place = 0;
+
+/* Next literal pool number.  */
+int lit_pool_num = 1;
+symbolS *current_poolP = NULL;
+
+
+static int
+end_of_line (char *str)
+{
+  int retval = SUCCESS;
+
+  skip_whitespace (str);
+  if (*str != '\0')
+    {
+      retval = (int) FAIL;
+
+      if (!inst.error)
+        inst.error = BAD_GARBAGE;
+    }
+
+  return retval;
+}
+
+static int
+score_reg_parse (char **ccp, struct hash_control *htab)
+{
+  char *start = *ccp;
+  char c;
+  char *p;
+  struct reg_entry *reg;
+
+  p = start;
+  if (!ISALPHA (*p) || !is_name_beginner (*p))
+    return (int) FAIL;
+
+  c = *p++;
+
+  while (ISALPHA (c) || ISDIGIT (c) || c == '_')
+    c = *p++;
+
+  *--p = 0;
+  reg = (struct reg_entry *) hash_find (htab, start);
+  *p = c;
+
+  if (reg)
+    {
+      *ccp = p;
+      return reg->number;
+    }
+  return (int) FAIL;
+}
+
+/* If shift <= 0, only return reg.  */
+
+static int
+reg_required_here (char **str, int shift, enum score_reg_type reg_type)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg = (int) FAIL;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[reg_type].htab)) != (int) FAIL)
+    {
+      if (reg_type == REG_TYPE_SCORE)
+        {
+          if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
+            {
+              as_warn (_("Using temp register(r1)"));
+              inst.bwarn = 1;
+            }
+        }
+      if (shift >= 0)
+	{
+          if (reg_type == REG_TYPE_SCORE_CR)
+	    strcpy (inst.reg, score_crn_table[reg].name);
+          else if (reg_type == REG_TYPE_SCORE_SR)
+	    strcpy (inst.reg, score_srn_table[reg].name);
+          else
+	    strcpy (inst.reg, "");
+
+          inst.instruction |= reg << shift;
+	}
+    }
+  else
+    {
+      *str = start;
+      sprintf (buff, _("register expected, not '%.100s'"), start);
+      inst.error = buff;
+    }
+
+  return reg;
+}
+
+static int
+skip_past_comma (char **str)
+{
+  char *p = *str;
+  char c;
+  int comma = 0;
+
+  while ((c = *p) == ' ' || c == ',')
+    {
+      p++;
+      if (c == ',' && comma++)
+        {
+          inst.error = BAD_SKIP_COMMA;
+          return (int) FAIL;
+        }
+    }
+
+  if ((c == '\0') || (comma == 0))
+    {
+      inst.error = BAD_SKIP_COMMA;
+      return (int) FAIL;
+    }
+
+  *str = p;
+  return comma ? SUCCESS : (int) FAIL;
+}
+
+static void
+do_rdrsrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if ((((inst.instruction >> 15) & 0x10) == 0)
+          && (((inst.instruction >> 10) & 0x10) == 0)
+          && (((inst.instruction >> 20) & 0x10) == 0)
+          && (inst.relax_inst != 0x8000)
+          && (((inst.instruction >> 20) & 0xf) == ((inst.instruction >> 15) & 0xf)))
+        {
+          inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4)
+            | (((inst.instruction >> 15) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_inst = 0x8000;
+        }
+    }
+}
+
+static int
+walk_no_bignums (symbolS * sp)
+{
+  if (symbol_get_value_expression (sp)->X_op == O_big)
+    return 1;
+
+  if (symbol_get_value_expression (sp)->X_add_symbol)
+    return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+	    || (symbol_get_value_expression (sp)->X_op_symbol
+		&& walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));  
+
+  return 0;
+}
+
+static int
+my_get_expression (expressionS * ep, char **str)
+{
+  char *save_in;
+  segT seg;
+
+  save_in = input_line_pointer;
+  input_line_pointer = *str;
+  in_my_get_expression = 1;
+  seg = expression (ep);
+  in_my_get_expression = 0;
+
+  if (ep->X_op == O_illegal)
+    {
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      inst.error = _("illegal expression");
+      return (int) FAIL;
+    }
+  /* Get rid of any bignums now, so that we don't generate an error for which
+     we can't establish a line number later on.  Big numbers are never valid
+     in instructions, which is where this routine is always called.  */
+  if (ep->X_op == O_big
+      || (ep->X_add_symbol
+          && (walk_no_bignums (ep->X_add_symbol)
+              || (ep->X_op_symbol && walk_no_bignums (ep->X_op_symbol)))))
+    {
+      inst.error = _("invalid constant");
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return (int) FAIL;
+    }
+
+  if ((ep->X_add_symbol != NULL)
+      && (inst.type != PC_DISP19div2)
+      && (inst.type != PC_DISP8div2)
+      && (inst.type != PC_DISP24div2)
+      && (inst.type != PC_DISP11div2)
+      && (inst.type != Insn_Type_SYN)
+      && (inst.type != Rd_rvalueRs_SI15)
+      && (inst.type != Rd_lvalueRs_SI15)
+      && (inst.type != Insn_internal))
+    {
+      inst.error = BAD_ARGS;
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return (int) FAIL;
+    }
+
+  *str = input_line_pointer;
+  input_line_pointer = save_in;
+  return SUCCESS;
+}
+
+/* Check if an immediate is valid.  If so, convert it to the right format.  */
+
+static int
+validate_immediate (int val, unsigned int data_type, int hex_p)
+{
+  switch (data_type)
+    {
+    case _VALUE_HI16:
+      {
+        int val_hi = ((val & 0xffff0000) >> 16);
+
+        if (score_df_range[data_type].range[0] <= val_hi
+            && val_hi <= score_df_range[data_type].range[1])
+	  return val_hi;
+      }
+      break;
+
+    case _VALUE_LO16:
+      {
+        int val_lo = (val & 0xffff);
+
+        if (score_df_range[data_type].range[0] <= val_lo
+            && val_lo <= score_df_range[data_type].range[1])
+	  return val_lo;
+      }
+      break;
+
+    case _VALUE:
+      return val;
+      break;
+
+    case _SIMM14:
+      if (hex_p == 1)
+        {
+          if (!(val >= -0x2000 && val <= 0x3fff))
+            {
+              return (int) FAIL;
+            }
+        }
+      else
+        {
+          if (!(val >= -8192 && val <= 8191))
+            {
+              return (int) FAIL;
+            }
+        }
+
+      return val;
+      break;
+
+    case _SIMM16_NEG:
+      if (hex_p == 1)
+        {
+          if (!(val >= -0x7fff && val <= 0xffff && val != 0x8000))
+            {
+              return (int) FAIL;
+            }
+        }
+      else
+        {
+          if (!(val >= -32767 && val <= 32768))
+            {
+              return (int) FAIL;
+            }
+        }
+
+      val = -val;
+      return val;
+      break;
+
+    default:
+      if (data_type == _SIMM14_NEG || data_type == _IMM16_NEG)
+	val = -val;
+
+      if (score_df_range[data_type].range[0] <= val
+          && val <= score_df_range[data_type].range[1])
+	return val;
+
+      break;
+    }
+
+  return (int) FAIL;
+}
+
+static int
+data_op2 (char **str, int shift, enum score_data_type data_type)
+{
+  int value;
+  char data_exp[MAX_LITERAL_POOL_SIZE];
+  char *dataptr;
+  int cnt = 0;
+  char *pp = NULL;
+
+  skip_whitespace (*str);
+  inst.error = NULL;
+  dataptr = * str;
+
+  /* Set hex_p to zero.  */
+  int hex_p = 0;
+
+  while ((*dataptr != '\0') && (*dataptr != '|') && (cnt <= MAX_LITERAL_POOL_SIZE))     /* 0x7c = ='|' */
+    {
+      data_exp[cnt] = *dataptr;
+      dataptr++;
+      cnt++;
+    }
+
+  data_exp[cnt] = '\0';
+  pp = (char *)&data_exp;
+
+  if (*dataptr == '|')          /* process PCE */
+    {
+      if (my_get_expression (&inst.reloc.exp, &pp) == (int) FAIL)
+        return (int) FAIL;
+      end_of_line (pp);
+      if (inst.error != 0)
+        return (int) FAIL;       /* to ouptut_inst to printf out the error */
+      *str = dataptr;
+    }
+  else                          /* process  16 bit */
+    {
+      if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
+        {
+          return (int) FAIL;
+        }
+
+      dataptr = (char *)data_exp;
+      for (; *dataptr != '\0'; dataptr++)
+        {
+          *dataptr = TOLOWER (*dataptr);
+          if (*dataptr == '!' || *dataptr == ' ')
+            break;
+        }
+      dataptr = (char *)data_exp;
+
+      if ((dataptr != NULL)
+          && (((strstr (dataptr, "0x")) != NULL)
+              || ((strstr (dataptr, "0X")) != NULL)))
+        {
+          hex_p = 1;
+          if ((data_type != _SIMM16_LA)
+              && (data_type != _VALUE_HI16)
+              && (data_type != _VALUE_LO16)
+              && (data_type != _IMM16)
+              && (data_type != _IMM15)
+              && (data_type != _IMM14)
+              && (data_type != _IMM4)
+              && (data_type != _IMM5)
+              && (data_type != _IMM8)
+              && (data_type != _IMM5_RSHIFT_1)
+              && (data_type != _IMM5_RSHIFT_2)
+              && (data_type != _SIMM14)
+              && (data_type != _SIMM14_NEG)
+              && (data_type != _SIMM16_NEG)
+              && (data_type != _IMM10_RSHIFT_2)
+              && (data_type != _GP_IMM15))
+            {
+              data_type += 24;
+            }
+        }
+
+      if ((inst.reloc.exp.X_add_number == 0)
+          && (inst.type != Insn_Type_SYN)
+          && (inst.type != Rd_rvalueRs_SI15)
+          && (inst.type != Rd_lvalueRs_SI15)
+          && (inst.type != Insn_internal)
+          && (((*dataptr >= 'a') && (*dataptr <= 'z'))
+             || ((*dataptr == '0') && (*(dataptr + 1) == 'x') && (*(dataptr + 2) != '0'))
+             || ((*dataptr == '+') && (*(dataptr + 1) != '0'))
+             || ((*dataptr == '-') && (*(dataptr + 1) != '0'))))
+        {
+          inst.error = BAD_ARGS;
+          return (int) FAIL;
+        }
+    }
+
+  if ((inst.reloc.exp.X_add_symbol)
+      && ((data_type == _SIMM16)
+          || (data_type == _SIMM16_NEG)
+          || (data_type == _IMM16_NEG)
+          || (data_type == _SIMM14)
+          || (data_type == _SIMM14_NEG)
+          || (data_type == _IMM5)
+          || (data_type == _IMM14)
+          || (data_type == _IMM20)
+          || (data_type == _IMM16)
+          || (data_type == _IMM15)
+          || (data_type == _IMM4)))
+    {
+      inst.error = BAD_ARGS;
+      return (int) FAIL;
+    }
+
+  if (inst.reloc.exp.X_add_symbol)
+    {
+      switch (data_type)
+        {
+        case _SIMM16_LA:
+          return (int) FAIL;
+        case _VALUE_HI16:
+          inst.reloc.type = BFD_RELOC_HI16_S;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _VALUE_LO16:
+          inst.reloc.type = BFD_RELOC_LO16;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _GP_IMM15:
+          inst.reloc.type = BFD_RELOC_SCORE_GPREL15;
+          inst.reloc.pc_rel = 0;
+          break;
+        case _SIMM16_pic:
+        case _IMM16_LO16_pic:
+          inst.reloc.type = BFD_RELOC_SCORE_GOT_LO16;
+          inst.reloc.pc_rel = 0;
+          break;
+        default:
+          inst.reloc.type = BFD_RELOC_32;
+          inst.reloc.pc_rel = 0;
+          break;
+        }
+    }
+  else
+    {
+      if (data_type == _IMM16_pic)
+	{
+          inst.reloc.type = BFD_RELOC_SCORE_DUMMY_HI16;
+          inst.reloc.pc_rel = 0;
+	}
+
+      if (data_type == _SIMM16_LA && inst.reloc.exp.X_unsigned == 1)
+        {
+          value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM16_LA_POS, hex_p);
+          if (value == (int) FAIL)       /* for advance to check if this is ldis */
+            if ((inst.reloc.exp.X_add_number & 0xffff) == 0)
+              {
+                inst.instruction |= 0x8000000;
+                inst.instruction |= ((inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe;
+                return SUCCESS;
+              }
+        }
+      else
+        {
+          value = validate_immediate (inst.reloc.exp.X_add_number, data_type, hex_p);
+        }
+
+      if (value == (int) FAIL)
+        {
+          if ((data_type != _SIMM14_NEG) && (data_type != _SIMM16_NEG) && (data_type != _IMM16_NEG))
+            {
+              sprintf (err_msg,
+                       _("invalid constant: %d bit expression not in range %d..%d"),
+                       score_df_range[data_type].bits,
+                       score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+            }
+          else
+            {
+              sprintf (err_msg,
+                       _("invalid constant: %d bit expression not in range %d..%d"),
+                       score_df_range[data_type].bits,
+                       -score_df_range[data_type].range[1], -score_df_range[data_type].range[0]);
+            }
+
+          inst.error = err_msg;
+          return (int) FAIL;
+        }
+
+      if ((score_df_range[data_type].range[0] != 0) || (data_type == _IMM5_RANGE_8_31))
+        {
+          value &= (1 << score_df_range[data_type].bits) - 1;
+        }
+
+      inst.instruction |= value << shift;
+    }
+
+  if ((inst.instruction & 0xf0000000) == 0x30000000)
+    {
+      if ((((inst.instruction >> 20) & 0x1F) != 0)
+          && (((inst.instruction >> 20) & 0x1F) != 1)
+          && (((inst.instruction >> 20) & 0x1F) != 2)
+          && (((inst.instruction >> 20) & 0x1F) != 3)
+          && (((inst.instruction >> 20) & 0x1F) != 4)
+          && (((inst.instruction >> 20) & 0x1F) != 8)
+          && (((inst.instruction >> 20) & 0x1F) != 9)
+          && (((inst.instruction >> 20) & 0x1F) != 0xa)
+          && (((inst.instruction >> 20) & 0x1F) != 0xb)
+          && (((inst.instruction >> 20) & 0x1F) != 0xc)
+          && (((inst.instruction >> 20) & 0x1F) != 0xd)
+          && (((inst.instruction >> 20) & 0x1F) != 0xe)
+          && (((inst.instruction >> 20) & 0x1F) != 0x10)
+          && (((inst.instruction >> 20) & 0x1F) != 0x11)
+          && (((inst.instruction >> 20) & 0x1F) != 0x18)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1A)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1B)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1d)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1e)
+          && (((inst.instruction >> 20) & 0x1F) != 0x1f))
+        {
+          inst.error = _("invalid constant: bit expression not defined");
+          return (int) FAIL;
+        }
+    }
+
+  return SUCCESS;
+}
+
+/* Handle addi/addi.c/addis.c/cmpi.c/addis.c/ldi.  */
+
+static void
+do_rdsi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 1, _SIMM16) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  /* ldi.  */
+  if ((inst.instruction & 0x20c0000) == 0x20c0000)
+    {
+      if ((((inst.instruction >> 20) & 0x10) == 0x10) || ((inst.instruction & 0x1fe00) != 0))
+        {
+          inst.relax_inst = 0x8000;
+        }
+      else
+        {
+          inst.relax_inst |= (inst.instruction >> 1) & 0xff;
+          inst.relax_inst |= (((inst.instruction >> 20) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+    }
+  else if (((inst.instruction >> 20) & 0x10) == 0x10)
+    {
+      inst.relax_inst = 0x8000;
+    }
+}
+
+/* Handle subi/subi.c.  */
+
+static void
+do_sub_rdsi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM16_NEG) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addri/addri.c.  */
+
+static void
+do_rdrssi14 (char *str)         /* -(2^13)~((2^13)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _SIMM14);
+}
+
+/* Handle subri.c/subri.  */
+static void
+do_sub_rdrssi14 (char *str)     /* -(2^13)~((2^13)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM14_NEG) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle bitclr.c/bitset.c/bittgl.c/slli.c/srai.c/srli.c/roli.c/rori.c/rolic.c.  */
+static void
+do_rdrsi5 (char *str)           /* 0~((2^14)-1) */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 10, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((((inst.instruction >> 20) & 0x1f) == ((inst.instruction >> 15) & 0x1f))
+      && (inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle andri/orri/andri.c/orri.c.  */
+
+static void
+do_rdrsi14 (char *str)          /* 0 ~ ((2^14)-1)  */
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM14) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle bittst.c.  */
+static void
+do_xrsi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 10, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0x1f) << 3) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle addis/andi/ori/andis/oris/ldis.  */
+static void
+do_rdi16 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 1, _IMM16) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+  /*
+  if (((inst.instruction & 0xa0dfffe) != 0xa0c0000) || ((((inst.instruction >> 20) & 0x1f) & 0x10) == 0x10))
+    inst.relax_inst = 0x8000;
+  else
+    inst.relax_size = 2;
+  */
+}
+
+static void
+do_macro_rdi32hi (char *str)
+{
+  skip_whitespace (str);
+
+  /* Do not handle end_of_line().  */
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _VALUE_HI16);
+}
+
+static void
+do_macro_rdi32lo (char *str)
+{
+  skip_whitespace (str);
+
+  /* Do not handle end_of_line().  */
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL)
+    data_op2 (&str, 1, _VALUE_LO16);
+}
+
+/* Handle ldis_pic.  */
+
+static void
+do_rdi16_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addi_s_pic to generate R_SCORE_GOT_LO16 .  */
+
+static void
+do_addi_s_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _SIMM16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle addi_u_pic to generate R_SCORE_GOT_LO16 .  */
+
+static void
+do_addi_u_pic (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && data_op2 (&str, 1, _IMM16_LO16_pic) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle mfceh/mfcel/mtceh/mtchl.  */
+
+static void
+do_rd (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL)
+    end_of_line (str);
+}
+
+static void
+do_rs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8) | (((inst.instruction >> 15) & 0xf) << 4);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+static void
+do_i15 (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 10, _IMM15) != (int) FAIL)
+    end_of_line (str);
+}
+
+static void
+do_xi5x (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 15, _IMM5) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      inst.relax_inst |= (((inst.instruction >> 15) & 0x1f) << 3);
+      inst.relax_size = 2;
+    }
+}
+
+static void
+do_rdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      if (((inst.instruction & 0x7f) == 0x56))  /* adjust mv -> mv! / mlfh! / mhfl! */
+        {
+          /* mlfh */
+          if ((((inst.instruction >> 15) & 0x10) != 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+            {
+              inst.relax_inst = 0x00000001 | (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          /* mhfl */
+          else if ((((inst.instruction >> 15) & 0x10) == 0x0) && ((inst.instruction >> 20) & 0x10) != 0)
+            {
+              inst.relax_inst = 0x00000002 | (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+            {
+              inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                | (((inst.instruction >> 20) & 0xf) << 8);
+              inst.relax_size = 2;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+      else if ((((inst.instruction >> 15) & 0x10) == 0x0) && (((inst.instruction >> 20) & 0x10) == 0))
+        {
+          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+            | (((inst.instruction >> 20) & 0xf) << 8);
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_inst = 0x8000;
+        }
+    }
+}
+
+/* Handle mfcr/mtcr.  */
+static void
+do_rdcrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reg_required_here (&str, 15, REG_TYPE_SCORE_CR) != (int) FAIL)
+    end_of_line (str);
+}
+
+/* Handle mfsr/mtsr.  */
+
+static void
+do_rdsrs (char *str)
+{
+  skip_whitespace (str);
+
+  /* mfsr */
+  if ((inst.instruction & 0xff) == 0x50)
+    {
+      if (reg_required_here (&str, 20, REG_TYPE_SCORE) != (int) FAIL
+          && skip_past_comma (&str) != (int) FAIL
+          && reg_required_here (&str, 10, REG_TYPE_SCORE_SR) != (int) FAIL)
+	end_of_line (str);
+    }
+  else
+    {
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) != (int) FAIL
+          && skip_past_comma (&str) != (int) FAIL)
+	reg_required_here (&str, 10, REG_TYPE_SCORE_SR);
+    }
+}
+
+/* Handle neg.  */
+
+static void
+do_rdxrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 10) & 0x10) == 0)
+      && (((inst.instruction >> 20) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 20) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+/* Handle cmp.c/cmp<cond>.  */
+static void
+do_rsrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if ((inst.relax_inst != 0x8000) && (((inst.instruction >> 20) & 0x1f) == 3)
+      && (((inst.instruction >> 10) & 0x10) == 0) && (((inst.instruction >> 15) & 0x10) == 0))
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 4) | (((inst.instruction >> 15) & 0xf) << 8);
+      inst.relax_size = 2;
+    }
+  else
+    inst.relax_inst = 0x8000;
+}
+
+static void
+do_ceinst (char *str)
+{
+  char *strbak;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 20, _IMM5) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 5, _IMM5) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 0, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      str = strbak;
+      if (data_op2 (&str, 0, _IMM25) == (int) FAIL)
+	return;
+    }
+}
+
+static int
+reglow_required_here (char **str, int shift)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[REG_TYPE_SCORE].htab)) != (int) FAIL)
+    {
+      if ((reg == 1) && (nor1 == 1) && (inst.bwarn == 0))
+        {
+          as_warn (_("Using temp register(r1)"));
+          inst.bwarn = 1;
+        }
+      if (reg < 16)
+        {
+          if (shift >= 0)
+            inst.instruction |= reg << shift;
+
+          return reg;
+        }
+    }
+
+  /* Restore the start point, we may have got a reg of the wrong class.  */
+  *str = start;
+  sprintf (buff, _("low register(r0-r15)expected, not '%.100s'"), start);
+  inst.error = buff;
+  return (int) FAIL;
+}
+
+/* Handle addc!/add!/and!/cmp!/neg!/not!/or!/sll!/srl!/sra!/xor!/sub!.  */
+static void
+do16_rdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reglow_required_here (&str, 4) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if ((inst.instruction & 0x700f) == 0x2003)        /* cmp!  */
+        {
+          inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 15)
+            | (((inst.instruction >> 4) & 0xf) << 10);
+        }
+      else if ((inst.instruction & 0x700f) == 0x2006)   /* not!  */
+	{
+	  inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+	    | (((inst.instruction >> 4) & 0xf) << 15);
+	}
+      else
+        {
+          inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+            | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 4) & 0xf) << 10);
+        }
+      inst.relax_size = 4;
+    }
+}
+
+static void
+do16_rs (char *str)
+{
+  int rd = 0;
+
+  skip_whitespace (str);
+
+  if ((rd = reglow_required_here (&str, 4)) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      inst.relax_inst |= rd << 20;
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle br!/brl!.  */
+static void
+do16_xrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 4) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 10)
+                      | (((inst.instruction >> 4) & 0xf) << 15);
+      inst.relax_size = 4;
+    }
+}
+
+static int
+reghigh_required_here (char **str, int shift)
+{
+  static char buff[MAX_LITERAL_POOL_SIZE];
+  int reg;
+  char *start = *str;
+
+  if ((reg = score_reg_parse (str, all_reg_maps[REG_TYPE_SCORE].htab)) != (int) FAIL)
+    {
+      if (15 < reg && reg < 32)
+        {
+          if (shift >= 0)
+            inst.instruction |= (reg & 0xf) << shift;
+
+          return reg;
+        }
+    }
+
+  *str = start;
+  sprintf (buff, _("high register(r16-r31)expected, not '%.100s'"), start);
+  inst.error = buff;
+  return (int) FAIL;
+}
+
+/* Handle mhfl!.  */
+static void
+do16_hrdrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reghigh_required_here (&str, 8) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reglow_required_here (&str, 4) != (int) FAIL
+      && end_of_line (str) != (int) FAIL)
+    {
+      inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+        | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle mlfh!.  */
+static void
+do16_rdhrs (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) != (int) FAIL
+      && skip_past_comma (&str) != (int) FAIL
+      && reghigh_required_here (&str, 4) != (int) FAIL
+      && end_of_line (str) != (int) FAIL)
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+        | ((((inst.instruction >> 4) & 0xf) | 0x10) << 15) | (0xf << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* We need to be able to fix up arbitrary expressions in some statements.
+   This is so that we can handle symbols that are an arbitrary distance from
+   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
+   which returns part of an address in a form which will be valid for
+   a data instruction.  We do this by pushing the expression into a symbol
+   in the expr_section, and creating a fix for that.  */
+static fixS *
+fix_new_score (fragS * frag, int where, short int size, expressionS * exp, int pc_rel, int reloc)
+{
+  fixS *new_fix;
+
+  switch (exp->X_op)
+    {
+    case O_constant:
+    case O_symbol:
+    case O_add:
+    case O_subtract:
+      new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
+      break;
+    default:
+      new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0, pc_rel, reloc);
+      break;
+    }
+  return new_fix;
+}
+
+static void
+init_dependency_vector (void)
+{
+  int i;
+
+  for (i = 0; i < vector_size; i++)
+    memset (&dependency_vector[i], '\0', sizeof (dependency_vector[i]));
+
+  return;
+}
+
+static enum insn_type_for_dependency
+dependency_type_from_insn (char *insn_name)
+{
+  char name[INSN_NAME_LEN];
+  const struct insn_to_dependency *tmp;
+
+  strcpy (name, insn_name);
+  tmp = (const struct insn_to_dependency *) hash_find (dependency_insn_hsh, name);
+
+  if (tmp)
+    return tmp->type;
+
+  return D_all_insn;
+}
+
+static int
+check_dependency (char *pre_insn, char *pre_reg,
+                  char *cur_insn, char *cur_reg, int *warn_or_error)
+{
+  int bubbles = 0;
+  unsigned int i;
+  enum insn_type_for_dependency pre_insn_type;
+  enum insn_type_for_dependency cur_insn_type;
+
+  pre_insn_type = dependency_type_from_insn (pre_insn);
+  cur_insn_type = dependency_type_from_insn (cur_insn);
+
+  for (i = 0; i < sizeof (data_dependency_table) / sizeof (data_dependency_table[0]); i++)
+    {
+      if ((pre_insn_type == data_dependency_table[i].pre_insn_type)
+          && (D_all_insn == data_dependency_table[i].cur_insn_type
+              || cur_insn_type == data_dependency_table[i].cur_insn_type)
+          && (strcmp (data_dependency_table[i].pre_reg, "") == 0
+              || strcmp (data_dependency_table[i].pre_reg, pre_reg) == 0)
+          && (strcmp (data_dependency_table[i].cur_reg, "") == 0
+              || strcmp (data_dependency_table[i].cur_reg, cur_reg) == 0))
+        {
+          bubbles = (score7) ? data_dependency_table[i].bubblenum_7 : data_dependency_table[i].bubblenum_5;
+          *warn_or_error = data_dependency_table[i].warn_or_error;
+          break;
+        }
+    }
+
+  return bubbles;
+}
+
+static void
+build_one_frag (struct score_it one_inst)
+{
+  char *p;
+  int relaxable_p = g_opt;
+  int relax_size = 0;
+
+  /* Start a new frag if frag_now is not empty.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	frag_wane (frag_now);
+
+      frag_new (0);
+    }
+  frag_grow (20);
+
+  p = frag_more (one_inst.size);
+  md_number_to_chars (p, one_inst.instruction, one_inst.size);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (one_inst.size);
+#endif
+
+  relaxable_p &= (one_inst.relax_size != 0);
+  relax_size = relaxable_p ? one_inst.relax_size : 0;
+
+  p = frag_var (rs_machine_dependent, relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (one_inst.size, one_inst.relax_size,
+                              one_inst.type, 0, 0, relaxable_p),
+                NULL, 0, NULL);
+
+  if (relaxable_p)
+    md_number_to_chars (p, one_inst.relax_inst, relax_size);
+}
+
+static void
+handle_dependency (struct score_it *theinst)
+{
+  int i;
+  int warn_or_error = 0;   /* warn - 0; error - 1  */
+  int bubbles = 0;
+  int remainder_bubbles = 0;
+  char cur_insn[INSN_NAME_LEN];
+  char pre_insn[INSN_NAME_LEN];
+  struct score_it nop_inst;
+  struct score_it pflush_inst;
+
+  nop_inst.instruction = 0x0000;
+  nop_inst.size = 2;
+  nop_inst.relax_inst = 0x80008000;
+  nop_inst.relax_size = 4;
+  nop_inst.type = NO16_OPD;
+
+  pflush_inst.instruction = 0x8000800a;
+  pflush_inst.size = 4;
+  pflush_inst.relax_inst = 0x8000;
+  pflush_inst.relax_size = 0;
+  pflush_inst.type = NO_OPD;
+
+  /* pflush will clear all data dependency.  */
+  if (strcmp (theinst->name, "pflush") == 0)
+    {
+      init_dependency_vector ();
+      return;
+    }
+
+  /* Push current instruction to dependency_vector[0].  */
+  for (i = vector_size - 1; i > 0; i--)
+    memcpy (&dependency_vector[i], &dependency_vector[i - 1], sizeof (dependency_vector[i]));
+
+  memcpy (&dependency_vector[0], theinst, sizeof (dependency_vector[i]));
+
+  /* There is no dependency between nop and any instruction.  */
+  if (strcmp (dependency_vector[0].name, "nop") == 0
+      || strcmp (dependency_vector[0].name, "nop!") == 0)
+    return;
+
+  /* "pce" is defined in insn_to_dependency_table.  */
+#define PCE_NAME "pce"
+
+  if (dependency_vector[0].type == Insn_Type_PCE)
+    strcpy (cur_insn, PCE_NAME);
+  else
+    strcpy (cur_insn, dependency_vector[0].name);
+
+  for (i = 1; i < vector_size; i++)
+    {
+      /* The element of dependency_vector is NULL.  */
+      if (dependency_vector[i].name[0] == '\0')
+	continue;
+
+      if (dependency_vector[i].type == Insn_Type_PCE)
+	strcpy (pre_insn, PCE_NAME);
+      else
+	strcpy (pre_insn, dependency_vector[i].name);
+
+      bubbles = check_dependency (pre_insn, dependency_vector[i].reg,
+                                  cur_insn, dependency_vector[0].reg, &warn_or_error);
+      remainder_bubbles = bubbles - i + 1;
+
+      if (remainder_bubbles > 0)
+        {
+          int j;
+
+          if (fix_data_dependency == 1)
+            {
+	      if (remainder_bubbles <= 2)
+		{
+		  if (warn_fix_data_dependency)
+		    as_warn (_("Fix data dependency: %s %s -- %s %s  (insert %d nop!/%d)"),
+			     dependency_vector[i].name, dependency_vector[i].reg,
+			     dependency_vector[0].name, dependency_vector[0].reg,
+			     remainder_bubbles, bubbles);
+
+                  for (j = (vector_size - 1); (j - remainder_bubbles) > 0; j--)
+		    memcpy (&dependency_vector[j], &dependency_vector[j - remainder_bubbles],
+			    sizeof (dependency_vector[j]));
+
+                  for (j = 1; j <= remainder_bubbles; j++)
+                    {
+                      memset (&dependency_vector[j], '\0', sizeof (dependency_vector[j]));
+		      /* Insert nop!.  */
+    		      build_one_frag (nop_inst);
+                    }
+		}
+	      else
+		{
+		  if (warn_fix_data_dependency)
+		    as_warn (_("Fix data dependency: %s %s -- %s %s  (insert 1 pflush/%d)"),
+			     dependency_vector[i].name, dependency_vector[i].reg,
+			     dependency_vector[0].name, dependency_vector[0].reg,
+			     bubbles);
+
+                  for (j = 1; j < vector_size; j++)
+		    memset (&dependency_vector[j], '\0', sizeof (dependency_vector[j]));
+
+                  /* Insert pflush.  */
+                  build_one_frag (pflush_inst);
+		}
+            }
+          else
+            {
+	      if (warn_or_error)
+		{
+                  as_bad (_("data dependency: %s %s -- %s %s  (%d/%d bubble)"),
+                           dependency_vector[i].name, dependency_vector[i].reg,
+                           dependency_vector[0].name, dependency_vector[0].reg,
+                           remainder_bubbles, bubbles);
+		}
+	      else
+		{
+                  as_warn (_("data dependency: %s %s -- %s %s  (%d/%d bubble)"),
+                           dependency_vector[i].name, dependency_vector[i].reg,
+                           dependency_vector[0].name, dependency_vector[0].reg,
+                           remainder_bubbles, bubbles);
+		}
+            }
+        }
+    }
+}
+
+static enum insn_class
+get_insn_class_from_type (enum score_insn_type type)
+{
+  enum insn_class retval = (int) FAIL;
+
+  switch (type)
+    {
+    case Rd_I4:
+    case Rd_I5:
+    case Rd_rvalueBP_I5:
+    case Rd_lvalueBP_I5:
+    case Rd_I8:
+    case PC_DISP8div2:
+    case PC_DISP11div2:
+    case Rd_Rs:
+    case Rd_HighRs:
+    case Rd_lvalueRs:
+    case Rd_rvalueRs:
+    case x_Rs:
+    case Rd_LowRs:
+    case NO16_OPD:
+      retval = INSN_CLASS_16;
+      break;
+    case Rd_Rs_I5:
+    case x_Rs_I5:
+    case x_I5_x:
+    case Rd_Rs_I14:
+    case I15:
+    case Rd_I16:
+    case Rd_SI16:
+    case Rd_rvalueRs_SI10:
+    case Rd_lvalueRs_SI10:
+    case Rd_rvalueRs_preSI12:
+    case Rd_rvalueRs_postSI12:
+    case Rd_lvalueRs_preSI12:
+    case Rd_lvalueRs_postSI12:
+    case Rd_Rs_SI14:
+    case Rd_rvalueRs_SI15:
+    case Rd_lvalueRs_SI15:
+    case PC_DISP19div2:
+    case PC_DISP24div2:
+    case Rd_Rs_Rs:
+    case x_Rs_x:
+    case x_Rs_Rs:
+    case Rd_Rs_x:
+    case Rd_x_Rs:
+    case Rd_x_x:
+    case OP5_rvalueRs_SI15:
+    case I5_Rs_Rs_I5_OP5:
+    case x_rvalueRs_post4:
+    case Rd_rvalueRs_post4:
+    case Rd_x_I5:
+    case Rd_lvalueRs_post4:
+    case x_lvalueRs_post4:
+    case Rd_Rs_Rs_imm:
+    case NO_OPD:
+    case Rd_lvalue32Rs:
+    case Rd_rvalue32Rs:
+    case Insn_GP:
+    case Insn_PIC:
+    case Insn_internal:
+      retval = INSN_CLASS_32;
+      break;
+    case Insn_Type_PCE:
+      retval = INSN_CLASS_PCE;
+      break;
+    case Insn_Type_SYN:
+      retval = INSN_CLASS_SYN;
+      break;
+    default:
+      abort ();
+      break;
+    }
+  return retval;
+}
+
+static unsigned long
+adjust_paritybit (unsigned long m_code, enum insn_class class)
+{
+  unsigned long result = 0;
+  unsigned long m_code_high = 0;
+  unsigned long m_code_low = 0;
+  unsigned long pb_high = 0;
+  unsigned long pb_low = 0;
+
+  if (class == INSN_CLASS_32)
+    {
+      pb_high = 0x80000000;
+      pb_low = 0x00008000;
+    }
+  else if (class == INSN_CLASS_16)
+    {
+      pb_high = 0;
+      pb_low = 0;
+    }
+  else if (class == INSN_CLASS_PCE)
+    {
+      pb_high = 0;
+      pb_low = 0x00008000;
+    }
+  else if (class == INSN_CLASS_SYN)
+    {
+      /* FIXME.  at this time, INSN_CLASS_SYN must be 32 bit, but, instruction type should
+         be changed if macro instruction has been expanded.  */
+      pb_high = 0x80000000;
+      pb_low = 0x00008000;
+    }
+  else
+    {
+      abort ();
+    }
+
+  m_code_high = m_code & 0x3fff8000;
+  m_code_low = m_code & 0x00007fff;
+  result = pb_high | (m_code_high << 1) | pb_low | m_code_low;
+  return result;
+
+}
+
+static void
+gen_insn_frag (struct score_it *part_1, struct score_it *part_2)
+{
+  char *p;
+  bfd_boolean pce_p = FALSE;
+  int relaxable_p = g_opt;
+  int relax_size = 0;
+  struct score_it *inst1 = part_1;
+  struct score_it *inst2 = part_2;
+  struct score_it backup_inst1;
+
+  pce_p = (inst2) ? TRUE : FALSE;
+  memcpy (&backup_inst1, inst1, sizeof (struct score_it));
+
+  /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+  if (pce_p)
+    {
+      backup_inst1.instruction = ((backup_inst1.instruction & 0x7FFF) << 15)
+                                  | (inst2->instruction & 0x7FFF);
+      backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction, INSN_CLASS_PCE);
+      backup_inst1.relax_inst = 0x8000;
+      backup_inst1.size = INSN_SIZE;
+      backup_inst1.relax_size = 0;
+      backup_inst1.type = Insn_Type_PCE;
+    }
+  else
+    {
+      backup_inst1.instruction = adjust_paritybit (backup_inst1.instruction,
+						   GET_INSN_CLASS (backup_inst1.type));
+    }
+
+  if (backup_inst1.relax_size != 0)
+    {
+      enum insn_class tmp;
+
+      tmp = (backup_inst1.size == INSN_SIZE) ? INSN_CLASS_16 : INSN_CLASS_32;
+      backup_inst1.relax_inst = adjust_paritybit (backup_inst1.relax_inst, tmp);
+    }
+
+  /* Check data dependency.  */
+  handle_dependency (&backup_inst1);
+
+  /* Start a new frag if frag_now is not empty and is not instruction frag, maybe it contains
+     data produced by .ascii etc.  Doing this is to make one instruction per frag.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	frag_wane (frag_now);
+
+      frag_new (0);
+    }
+
+  /* Here, we must call frag_grow in order to keep the instruction frag type is
+     rs_machine_dependent.
+     For, frag_var may change frag_now->fr_type to rs_fill by calling frag_grow which
+     acturally will call frag_wane.
+     Calling frag_grow first will create a new frag_now which free size is 20 that is enough
+     for frag_var.  */
+  frag_grow (20);
+
+  p = frag_more (backup_inst1.size);
+  md_number_to_chars (p, backup_inst1.instruction, backup_inst1.size);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (backup_inst1.size);
+#endif
+
+  /* Generate fixup structure.  */
+  if (pce_p)
+    {
+      if (inst1->reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal,
+		       inst1->size, &inst1->reloc.exp,
+		       inst1->reloc.pc_rel, inst1->reloc.type);
+
+      if (inst2->reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal + 2,
+		       inst2->size, &inst2->reloc.exp, inst2->reloc.pc_rel, inst2->reloc.type);
+    }
+  else
+    {
+      if (backup_inst1.reloc.type != BFD_RELOC_NONE)
+	fix_new_score (frag_now, p - frag_now->fr_literal,
+		       backup_inst1.size, &backup_inst1.reloc.exp,
+		       backup_inst1.reloc.pc_rel, backup_inst1.reloc.type);
+    }
+
+  /* relax_size may be 2, 4, 12 or 0, 0 indicates no relaxation.  */
+  relaxable_p &= (backup_inst1.relax_size != 0);
+  relax_size = relaxable_p ? backup_inst1.relax_size : 0;
+
+  p = frag_var (rs_machine_dependent, relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (backup_inst1.size, backup_inst1.relax_size,
+                              backup_inst1.type, 0, 0, relaxable_p),
+                backup_inst1.reloc.exp.X_add_symbol, 0, NULL);
+
+  if (relaxable_p)
+    md_number_to_chars (p, backup_inst1.relax_inst, relax_size);
+
+  memcpy (inst1, &backup_inst1, sizeof (struct score_it));
+}
+
+static void
+parse_16_32_inst (char *insnstr, bfd_boolean gen_frag_p)
+{
+  char c;
+  char *p;
+  char *operator = insnstr;
+  const struct asm_opcode *opcode;
+
+  /* Parse operator and operands.  */
+  skip_whitespace (operator);
+
+  for (p = operator; *p != '\0'; p++)
+    if ((*p == ' ') || (*p == '!'))
+      break;
+
+  if (*p == '!')
+    p++;
+
+  c = *p;
+  *p = '\0';
+
+  opcode = (const struct asm_opcode *) hash_find (score_ops_hsh, operator);
+  *p = c;
+
+  memset (&inst, '\0', sizeof (inst));
+  sprintf (inst.str, "%s", insnstr);
+  if (opcode)
+    {
+      inst.instruction = opcode->value;
+      inst.relax_inst = opcode->relax_value;
+      inst.type = opcode->type;
+      inst.size = GET_INSN_SIZE (inst.type);
+      inst.relax_size = 0;
+      inst.bwarn = 0;
+      sprintf (inst.name, "%s", opcode->template);
+      strcpy (inst.reg, "");
+      inst.error = NULL;
+      inst.reloc.type = BFD_RELOC_NONE;
+
+      (*opcode->parms) (p);
+
+      /* It indicates current instruction is a macro instruction if inst.bwarn equals -1.  */
+      if ((inst.bwarn != -1) && (!inst.error) && (gen_frag_p))
+	gen_insn_frag (&inst, NULL);
+    }
+  else
+    inst.error = _("unrecognized opcode");
+}
+
+static int
+append_insn (char *str, bfd_boolean gen_frag_p)
+{
+  int retval = SUCCESS;
+
+  parse_16_32_inst (str, gen_frag_p);
+
+  if (inst.error)
+    {
+      retval = (int) FAIL;
+      as_bad (_("%s -- `%s'"), inst.error, inst.str);
+      inst.error = NULL;
+    }
+
+  return retval;
+}
+
+/* Handle mv! reg_high, reg_low;
+          mv! reg_low, reg_high;
+          mv! reg_low, reg_low;  */
+static void
+do16_mv_rdrs (char *str)
+{
+  int reg_rd;
+  int reg_rs;
+  char *backupstr = NULL;
+
+  backupstr = str;
+  skip_whitespace (str);
+
+  if ((reg_rd = reg_required_here (&str, 8, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || (reg_rs = reg_required_here (&str, 4, REG_TYPE_SCORE)) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      /* Case 1 : mv! or mlfh!.  */
+      if (reg_rd < 16)
+        {
+          if (reg_rs < 16)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | (((inst.instruction >> 4) & 0xf) << 15) | (0xf << 10);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              char append_str[MAX_LITERAL_POOL_SIZE];
+
+              sprintf (append_str, "mlfh! %s", backupstr);
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+      /* Case 2 : mhfl!.  */
+      else
+        {
+          if (reg_rs > 16)
+            {
+              SET_INSN_ERROR (BAD_ARGS);
+              return;
+            }
+          else
+            {
+              char append_str[MAX_LITERAL_POOL_SIZE];
+
+              sprintf (append_str, "mhfl! %s", backupstr);
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+    }
+}
+
+static void
+do16_rdi4 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 3, _IMM4) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      if (((inst.instruction >> 3) & 0x10) == 0)        /* for judge is addei or subei : bit 5 =0 : addei */
+        {
+          if (((inst.instruction >> 3) & 0xf) != 0xf)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | ((1 << ((inst.instruction >> 3) & 0xf)) << 1);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+      else
+        {
+          if (((inst.instruction >> 3) & 0xf) != 0xf)
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                | (((-(1 << ((inst.instruction >> 3) & 0xf))) & 0xffff) << 1);
+              inst.relax_size = 4;
+            }
+          else
+            {
+              inst.relax_inst = 0x8000;
+            }
+        }
+    }
+}
+
+static void
+do16_rdi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (reglow_required_here (&str, 8) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || data_op2 (&str, 3, _IMM5) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+        | (((inst.instruction >> 8) & 0xf) << 15) | (((inst.instruction >> 3) & 0x1f) << 10);
+      inst.relax_size = 4;
+    }
+}
+
+/* Handle sdbbp.  */
+static void
+do16_xi5 (char *str)
+{
+  skip_whitespace (str);
+
+  if (data_op2 (&str, 3, _IMM5) == (int) FAIL || end_of_line (str) == (int) FAIL)
+    return;
+  else
+    {
+      inst.relax_inst |= (((inst.instruction >> 3) & 0x1f) << 15);
+      inst.relax_size = 4;
+    }
+}
+
+/* Check that an immediate is word alignment or half word alignment.
+   If so, convert it to the right format.  */
+static int
+validate_immediate_align (int val, unsigned int data_type)
+{
+  if (data_type == _IMM5_RSHIFT_1)
+    {
+      if (val % 2)
+        {
+          inst.error = _("address offset must be half word alignment");
+          return (int) FAIL;
+        }
+    }
+  else if ((data_type == _IMM5_RSHIFT_2) || (data_type == _IMM10_RSHIFT_2))
+    {
+      if (val % 4)
+        {
+          inst.error = _("address offset must be word alignment");
+          return (int) FAIL;
+        }
+    }
+
+  return SUCCESS;
+}
+
+static int
+exp_ldst_offset (char **str, int shift, unsigned int data_type)
+{
+  char *dataptr;
+
+  dataptr = * str;
+
+  if ((*dataptr == '0') && (*(dataptr + 1) == 'x')
+      && (data_type != _SIMM16_LA)
+      && (data_type != _VALUE_HI16)
+      && (data_type != _VALUE_LO16)
+      && (data_type != _IMM16)
+      && (data_type != _IMM15)
+      && (data_type != _IMM14)
+      && (data_type != _IMM4)
+      && (data_type != _IMM5)
+      && (data_type != _IMM8)
+      && (data_type != _IMM5_RSHIFT_1)
+      && (data_type != _IMM5_RSHIFT_2)
+      && (data_type != _SIMM14_NEG)
+      && (data_type != _IMM10_RSHIFT_2))
+    {
+      data_type += 24;
+    }
+
+  if (my_get_expression (&inst.reloc.exp, str) == (int) FAIL)
+    return (int) FAIL;
+
+  if (inst.reloc.exp.X_op == O_constant)
+    {
+      /* Need to check the immediate align.  */
+      int value = validate_immediate_align (inst.reloc.exp.X_add_number, data_type);
+
+      if (value == (int) FAIL)
+	return (int) FAIL;
+
+      value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
+      if (value == (int) FAIL)
+        {
+          if (data_type < 30)
+            sprintf (err_msg,
+                     _("invalid constant: %d bit expression not in range %d..%d"),
+                     score_df_range[data_type].bits,
+                     score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+          else
+            sprintf (err_msg,
+                     _("invalid constant: %d bit expression not in range %d..%d"),
+                     score_df_range[data_type - 24].bits,
+                     score_df_range[data_type - 24].range[0], score_df_range[data_type - 24].range[1]);
+          inst.error = err_msg;
+          return (int) FAIL;
+        }
+
+      if (data_type == _IMM5_RSHIFT_1)
+        {
+          value >>= 1;
+        }
+      else if ((data_type == _IMM5_RSHIFT_2) || (data_type == _IMM10_RSHIFT_2))
+        {
+          value >>= 2;
+        }
+
+      if (score_df_range[data_type].range[0] != 0)
+        {
+          value &= (1 << score_df_range[data_type].bits) - 1;
+        }
+
+      inst.instruction |= value << shift;
+    }
+  else
+    {
+      inst.reloc.pc_rel = 0;
+    }
+
+  return SUCCESS;
+}
+
+static void
+do_ldst_insn (char *str)
+{
+  int pre_inc = 0;
+  int conflict_reg;
+  int value;
+  char * temp;
+  char *strbak;
+  char *dataptr;
+  int reg;
+  int ldst_idx = 0;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (((conflict_reg = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  /* ld/sw rD, [rA, simm15]    ld/sw rD, [rA]+, simm12     ld/sw rD, [rA, simm12]+.  */
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+	return;
+
+      /* Conflicts can occur on stores as well as loads.  */
+      conflict_reg = (conflict_reg == reg);
+      skip_whitespace (str);
+      temp = str + 1;    /* The latter will process decimal/hex expression.  */
+
+      /* ld/sw rD, [rA]+, simm12    ld/sw rD, [rA]+.  */
+      if (*str == ']')
+        {
+          str++;
+          if (*str == '+')
+            {
+              str++;
+              /* ld/sw rD, [rA]+, simm12.  */
+              if (skip_past_comma (&str) == SUCCESS)
+                {
+                  if ((exp_ldst_offset (&str, 3, _SIMM12) == (int) FAIL)
+                      || (end_of_line (str) == (int) FAIL))
+		    return;
+
+                  if (conflict_reg)
+                    {
+                      unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
+
+                      if ((ldst_func == INSN_LH)
+                          || (ldst_func == INSN_LHU)
+                          || (ldst_func == INSN_LW)
+                          || (ldst_func == INSN_LB)
+                          || (ldst_func == INSN_LBU))
+                        {
+                          inst.error = _("register same as write-back base");
+                          return;
+                        }
+                    }
+
+                  ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+                  inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+                  inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_POST].value;
+
+                  /* lw rD, [rA]+, 4 convert to pop rD, [rA].  */
+                  if ((inst.instruction & 0x3e000007) == 0x0e000000)
+                    {
+                      /* rs =  r0-r7, offset = 4 */
+                      if ((((inst.instruction >> 15) & 0x18) == 0)
+                          && (((inst.instruction >> 3) & 0xfff) == 4))
+                        {
+                          /* Relax to pophi.  */
+                          if ((((inst.instruction >> 20) & 0x10) == 0x10))
+                            {
+                              inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
+                                                              << 8) | 1 << 7 |
+                                (((inst.instruction >> 15) & 0x7) << 4);
+                            }
+                          /* Relax to pop.  */
+                          else
+                            {
+                              inst.relax_inst = 0x0000200a | (((inst.instruction >> 20) & 0xf)
+                                                              << 8) | 0 << 7 |
+                                (((inst.instruction >> 15) & 0x7) << 4);
+                            }
+                          inst.relax_size = 2;
+                        }
+                    }
+                  return;
+                }
+              /* ld/sw rD, [rA]+ convert to ld/sw rD, [rA, 0]+.  */
+              else
+                {
+                  SET_INSN_ERROR (NULL);
+                  if (end_of_line (str) == (int) FAIL)
+                    {
+                      return;
+                    }
+
+                  pre_inc = 1;
+                  value = validate_immediate (inst.reloc.exp.X_add_number, _SIMM12, 0);
+                  value &= (1 << score_df_range[_SIMM12].bits) - 1;
+                  ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+                  inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+                  inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
+                  inst.instruction |= value << 3;
+                  inst.relax_inst = 0x8000;
+                  return;
+                }
+            }
+          /* ld/sw rD, [rA] convert to ld/sw rD, [rA, simm15].  */
+          else
+            {
+              if (end_of_line (str) == (int) FAIL)
+		return;
+
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + LDST_NOUPDATE].value;
+
+              /* lbu rd, [rs] -> lbu! rd, [rs]  */
+              if (ldst_idx == INSN_LBU)
+                {
+                  inst.relax_inst = INSN16_LBU;
+                }
+              else if (ldst_idx == INSN_LH)
+                {
+                  inst.relax_inst = INSN16_LH;
+                }
+              else if (ldst_idx == INSN_LW)
+                {
+                  inst.relax_inst = INSN16_LW;
+                }
+              else if (ldst_idx == INSN_SB)
+                {
+                  inst.relax_inst = INSN16_SB;
+                }
+              else if (ldst_idx == INSN_SH)
+                {
+                  inst.relax_inst = INSN16_SH;
+                }
+              else if (ldst_idx == INSN_SW)
+                {
+                  inst.relax_inst = INSN16_SW;
+                }
+              else
+                {
+                  inst.relax_inst = 0x8000;
+                }
+
+              /* lw/lh/lbu/sw/sh/sb, offset = 0, relax to 16 bit instruction.  */
+              if ((ldst_idx == INSN_LBU)
+                  || (ldst_idx == INSN_LH)
+                  || (ldst_idx == INSN_LW)
+                  || (ldst_idx == INSN_SB) || (ldst_idx == INSN_SH) || (ldst_idx == INSN_SW))
+                {
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      inst.relax_inst |= (2 << 12) | (((inst.instruction >> 20) & 0xf) << 8) |
+                        (((inst.instruction >> 15) & 0xf) << 4);
+                      inst.relax_size = 2;
+                    }
+                }
+
+              return;
+            }
+        }
+      /* ld/sw rD, [rA, simm15]    ld/sw rD, [rA, simm12]+.  */
+      else
+        {
+          if (skip_past_comma (&str) == (int) FAIL)
+            {
+              inst.error = _("pre-indexed expression expected");
+              return;
+            }
+
+          if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
+	    return;
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+
+          skip_whitespace (str);
+          /* ld/sw rD, [rA, simm12]+.  */
+          if (*str == '+')
+            {
+              str++;
+              pre_inc = 1;
+              if (conflict_reg)
+                {
+                  unsigned int ldst_func = inst.instruction & OPC_PSEUDOLDST_MASK;
+
+                  if ((ldst_func == INSN_LH)
+                      || (ldst_func == INSN_LHU)
+                      || (ldst_func == INSN_LW)
+                      || (ldst_func == INSN_LB)
+                      || (ldst_func == INSN_LBU))
+                    {
+                      inst.error = _("register same as write-back base");
+                      return;
+                    }
+                }
+            }
+
+          if (end_of_line (str) == (int) FAIL)
+	    return;
+
+          if (inst.reloc.exp.X_op == O_constant)
+            {
+              int value;
+              unsigned int data_type;
+
+              if (pre_inc == 1)
+                data_type = _SIMM12;
+              else
+                data_type = _SIMM15;
+              dataptr = temp;
+
+              if ((*dataptr == '0') && (*(dataptr + 1) == 'x')
+                  && (data_type != _SIMM16_LA)
+                  && (data_type != _VALUE_HI16)
+                  && (data_type != _VALUE_LO16)
+                  && (data_type != _IMM16)
+                  && (data_type != _IMM15)
+                  && (data_type != _IMM14)
+                  && (data_type != _IMM4)
+                  && (data_type != _IMM5)
+                  && (data_type != _IMM8)
+                  && (data_type != _IMM5_RSHIFT_1)
+                  && (data_type != _IMM5_RSHIFT_2)
+                  && (data_type != _SIMM14_NEG)
+                  && (data_type != _IMM10_RSHIFT_2))
+                {
+                  data_type += 24;
+                }
+
+              value = validate_immediate (inst.reloc.exp.X_add_number, data_type, 0);
+              if (value == (int) FAIL)
+                {
+                  if (data_type < 30)
+                    sprintf (err_msg,
+                             _("invalid constant: %d bit expression not in range %d..%d"),
+                             score_df_range[data_type].bits,
+                             score_df_range[data_type].range[0], score_df_range[data_type].range[1]);
+                  else
+                    sprintf (err_msg,
+                             _("invalid constant: %d bit expression not in range %d..%d"),
+                             score_df_range[data_type - 24].bits,
+                             score_df_range[data_type - 24].range[0],
+                             score_df_range[data_type - 24].range[1]);
+                  inst.error = err_msg;
+                  return;
+                }
+
+              value &= (1 << score_df_range[data_type].bits) - 1;
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + pre_inc].value;
+              if (pre_inc == 1)
+                inst.instruction |= value << 3;
+              else
+                inst.instruction |= value;
+
+              /* lw rD, [rA, simm15]  */
+              if ((inst.instruction & 0x3e000000) == 0x20000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0)
+                      && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lw -> lw!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lw -> lwp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x3) == 0)
+                               && ((inst.instruction & 0x7fff) < 128))
+                        {
+                          inst.relax_inst = 0x7000 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 2) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sw rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x28000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sw -> sw!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sw -> swp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x3) == 0)
+                               && ((inst.instruction & 0x7fff) < 128))
+                        {
+                          inst.relax_inst = 0x7004 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 2) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sw rD, [rA, simm15]+    sw pre.  */
+              else if ((inst.instruction & 0x3e000007) == 0x06000004)
+                {
+                  /* rA is in [r0 - r7], and simm15 = -4.  */
+                  if ((((inst.instruction >> 15) & 0x18) == 0)
+                      && (((inst.instruction >> 3) & 0xfff) == 0xffc))
+                    {
+                      /* sw -> pushhi!.  */
+                      if ((((inst.instruction >> 20) & 0x10) == 0x10))
+                        {
+                          inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
+                            | 1 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
+                          inst.relax_size = 2;
+                        }
+                      /* sw -> push!.  */
+                      else
+                        {
+                          inst.relax_inst = 0x0000200e | (((inst.instruction >> 20) & 0xf) << 8)
+                            | 0 << 7 | (((inst.instruction >> 15) & 0x7) << 4);
+                          inst.relax_size = 2;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* lh rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x22000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lh -> lh!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lh -> lhp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x1) == 0)
+                               && ((inst.instruction & 0x7fff) < 64))
+                        {
+                          inst.relax_inst = 0x7001 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 1) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sh rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2a000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sh -> sh!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sh -> shp!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x1) == 0)
+                               && ((inst.instruction & 0x7fff) < 64))
+                        {
+                          inst.relax_inst = 0x7005 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | (((inst.instruction & 0x7fff) >> 1) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* lbu rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2c000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, lbu -> lbu!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, lbu -> lbup!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x7fff) < 32))
+                        {
+                          inst.relax_inst = 0x7003 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | ((inst.instruction & 0x7fff) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              /* sb rD, [rA, simm15]  */
+              else if ((inst.instruction & 0x3e000000) == 0x2e000000)
+                {
+                  /* Both rD and rA are in [r0 - r15].  */
+                  if ((((inst.instruction >> 15) & 0x10) == 0) && (((inst.instruction >> 20) & 0x10) == 0))
+                    {
+                      /* simm15 = 0, sb -> sb!.  */
+                      if ((inst.instruction & 0x7fff) == 0)
+                        {
+                          inst.relax_inst |= (((inst.instruction >> 15) & 0xf) << 4)
+                            | (((inst.instruction >> 20) & 0xf) << 8);
+                          inst.relax_size = 2;
+                        }
+                      /* rA = r2, sb -> sb!.  */
+                      else if ((((inst.instruction >> 15) & 0xf) == 2)
+                               && ((inst.instruction & 0x7fff) < 32))
+                        {
+                          inst.relax_inst = 0x7007 | (((inst.instruction >> 20) & 0xf) << 8)
+                            | ((inst.instruction & 0x7fff) << 3);
+                          inst.relax_size = 2;
+                        }
+                      else
+                        {
+                          inst.relax_inst = 0x8000;
+                        }
+                    }
+                  else
+                    {
+                      inst.relax_inst = 0x8000;
+                    }
+                }
+              else
+                {
+                  inst.relax_inst = 0x8000;
+                }
+
+              return;
+            }
+          else
+            {
+              /* FIXME: may set error, for there is no ld/sw rD, [rA, label] */
+              inst.reloc.pc_rel = 0;
+            }
+        }
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle cache.  */
+
+static void
+do_cache (char *str)
+{
+  skip_whitespace (str);
+
+  if ((data_op2 (&str, 20, _IMM5) == (int) FAIL) || (skip_past_comma (&str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      int cache_op;
+
+      cache_op = (inst.instruction >> 20) & 0x1F;
+      sprintf (inst.name, "cache %d", cache_op);
+    }
+
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+
+      /* cache op, [rA]  */
+      if (skip_past_comma (&str) == (int) FAIL)
+        {
+          SET_INSN_ERROR (NULL);
+          if (*str != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+          str++;
+        }
+      /* cache op, [rA, simm15]  */
+      else
+        {
+          if (exp_ldst_offset (&str, 0, _SIMM15) == (int) FAIL)
+            {
+              return;
+            }
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+
+      if (end_of_line (str) == (int) FAIL)
+	return;
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+static void
+do_crdcrscrsimm5 (char *str)
+{
+  char *strbak;
+
+  strbak = str;
+  skip_whitespace (str);
+
+  if (reg_required_here (&str, 20, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 15, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL
+      || reg_required_here (&str, 10, REG_TYPE_SCORE_CR) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      str = strbak;
+      /* cop1 cop_code20.  */
+      if (data_op2 (&str, 5, _IMM20) == (int) FAIL)
+	return;
+    }
+  else
+    {
+      if (data_op2 (&str, 5, _IMM5) == (int) FAIL)
+	return;
+    }
+
+  end_of_line (str);
+}
+
+/* Handle ldc/stc.  */
+static void
+do_ldst_cop (char *str)
+{
+  skip_whitespace (str);
+
+  if ((reg_required_here (&str, 15, REG_TYPE_SCORE_CR) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+
+      if (*str++ != ']')
+        {
+          if (exp_ldst_offset (&str, 5, _IMM10_RSHIFT_2) == (int) FAIL)
+	    return;
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+
+      end_of_line (str);
+    }
+  else
+    inst.error = BAD_ARGS;
+}
+
+static void
+do16_ldst_insn (char *str)
+{
+  skip_whitespace (str);
+
+  if ((reglow_required_here (&str, 8) == (int) FAIL) || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (*str == '[')
+    {
+      int reg;
+
+      str++;
+      skip_whitespace (str);
+
+      if ((reg = reglow_required_here (&str, 4)) == (int) FAIL)
+	return;
+
+      skip_whitespace (str);
+      if (*str++ == ']')
+        {
+          if (end_of_line (str) == (int) FAIL)
+	    return;
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                              | (((inst.instruction >> 4) & 0xf) << 15);
+	      inst.relax_size = 4;
+            }
+        }
+      else
+        {
+          inst.error = _("missing ]");
+        }
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle lbup!/lhp!/ldiu!/lwp!/sbp!/shp!/swp!.  */
+static void
+do16_ldst_imm_insn (char *str)
+{
+  char data_exp[MAX_LITERAL_POOL_SIZE];
+  int reg_rd;
+  char *dataptr = NULL, *pp = NULL;
+  int cnt = 0;
+  int assign_data = (int) FAIL;
+  unsigned int ldst_func;
+
+  skip_whitespace (str);
+
+  if (((reg_rd = reglow_required_here (&str, 8)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  skip_whitespace (str);
+  dataptr = str;
+
+  while ((*dataptr != '\0') && (*dataptr != '|') && (cnt <= MAX_LITERAL_POOL_SIZE))
+    {
+      data_exp[cnt] = *dataptr;
+      dataptr++;
+      cnt++;
+    }
+
+  data_exp[cnt] = '\0';
+  pp = &data_exp[0];
+
+  str = dataptr;
+
+  ldst_func = inst.instruction & LDST16_RI_MASK;
+  if (ldst_func == N16_LIU)
+    assign_data = exp_ldst_offset (&pp, 0, _IMM8);
+  else if (ldst_func == N16_LHP || ldst_func == N16_SHP)
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5_RSHIFT_1);
+  else if (ldst_func == N16_LWP || ldst_func == N16_SWP)
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5_RSHIFT_2);
+  else
+    assign_data = exp_ldst_offset (&pp, 3, _IMM5);
+
+  if ((assign_data == (int) FAIL) || (end_of_line (pp) == (int) FAIL))
+    return;
+  else
+    {
+      if ((inst.instruction & 0x7000) == N16_LIU)
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20
+                          | ((inst.instruction & 0xff) << 1);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LHP)
+               || ((inst.instruction & 0x7007) == N16_SHP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f) << 1);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LWP)
+               || ((inst.instruction & 0x7007) == N16_SWP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f) << 2);
+        }
+      else if (((inst.instruction & 0x7007) == N16_LBUP)
+               || ((inst.instruction & 0x7007) == N16_SBP))
+        {
+          inst.relax_inst |= ((inst.instruction >> 8) & 0xf) << 20 | 2 << 15
+                          | (((inst.instruction >> 3) & 0x1f));
+        }
+
+      inst.relax_size = 4;
+    }
+}
+
+static void
+do16_push_pop (char *str)
+{
+  int reg_rd;
+  int H_bit_mask = 0;
+
+  skip_whitespace (str);
+  if (((reg_rd = reg_required_here (&str, 8, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    return;
+
+  if (reg_rd >= 16)
+    H_bit_mask = 1;
+
+  /* reg_required_here will change bit 12 of opcode, so we must restore bit 12.  */
+  inst.instruction &= ~(1 << 12);
+
+  inst.instruction |= H_bit_mask << 7;
+
+  if (*str == '[')
+    {
+      int reg;
+
+      str++;
+      skip_whitespace (str);
+      if ((reg = reg_required_here (&str, 4, REG_TYPE_SCORE)) == (int) FAIL)
+	return;
+      else if (reg > 7)
+        {
+          if (!inst.error)
+	    inst.error = _("base register nums are over 3 bit");
+
+          return;
+        }
+
+      skip_whitespace (str);
+      if ((*str++ != ']') || (end_of_line (str) == (int) FAIL))
+        {
+          if (!inst.error)
+	    inst.error = _("missing ]");
+
+          return;
+        }
+
+      /* pop! */
+      if ((inst.instruction & 0xf) == 0xa)
+        {
+          if (H_bit_mask)
+            {
+              inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
+            }
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (4 << 3);
+            }
+        }
+      /* push! */
+      else
+        {
+          if (H_bit_mask)
+            {
+              inst.relax_inst |= ((((inst.instruction >> 8) & 0xf) | 0x10) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
+            }
+          else
+            {
+              inst.relax_inst |= (((inst.instruction >> 8) & 0xf) << 20)
+                                  | (((inst.instruction >> 4) & 0x7) << 15) | (((-4) & 0xfff) << 3);
+            }
+        }
+      inst.relax_size = 4;
+    }
+  else
+    {
+      inst.error = BAD_ARGS;
+    }
+}
+
+/* Handle lcb/lcw/lce/scb/scw/sce.  */
+static void
+do_ldst_unalign (char *str)
+{
+  int conflict_reg;
+
+  if (university_version == 1)
+    {
+      inst.error = ERR_FOR_SCORE5U_ATOMIC;
+      return;
+    }
+
+  skip_whitespace (str);
+
+  /* lcb/scb [rA]+.  */
+  if (*str == '[')
+    {
+      str++;
+      skip_whitespace (str);
+
+      if (reg_required_here (&str, 15, REG_TYPE_SCORE) == (int) FAIL)
+	return;
+
+      if (*str++ == ']')
+        {
+          if (*str++ != '+')
+            {
+              inst.error = _("missing +");
+              return;
+            }
+        }
+      else
+        {
+          inst.error = _("missing ]");
+          return;
+        }
+
+      if (end_of_line (str) == (int) FAIL)
+	return;
+    }
+  /* lcw/lce/scb/sce rD, [rA]+.  */
+  else
+    {
+      if (((conflict_reg = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+          || (skip_past_comma (&str) == (int) FAIL))
+        {
+          return;
+        }
+
+      skip_whitespace (str);
+      if (*str++ == '[')
+        {
+          int reg;
+
+          skip_whitespace (str);
+          if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+            {
+              return;
+            }
+
+          /* Conflicts can occur on stores as well as loads.  */
+          conflict_reg = (conflict_reg == reg);
+          skip_whitespace (str);
+          if (*str++ == ']')
+            {
+              unsigned int ldst_func = inst.instruction & LDST_UNALIGN_MASK;
+
+              if (*str++ == '+')
+                {
+                  if (conflict_reg)
+                    {
+                      as_warn (_("%s register same as write-back base"),
+                               ((ldst_func & UA_LCE) || (ldst_func & UA_LCW)
+                                ? _("destination") : _("source")));
+                    }
+                }
+              else
+                {
+                  inst.error = _("missing +");
+                  return;
+                }
+
+              if (end_of_line (str) == (int) FAIL)
+		return;
+            }
+          else
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+        }
+      else
+        {
+          inst.error = BAD_ARGS;
+          return;
+        }
+    }
+}
+
+/* Handle alw/asw.  */
+static void
+do_ldst_atomic (char *str)
+{
+  if (university_version == 1)
+    {
+      inst.error = ERR_FOR_SCORE5U_ATOMIC;
+      return;
+    }
+
+  skip_whitespace (str);
+
+  if ((reg_required_here (&str, 20, REG_TYPE_SCORE) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+
+      skip_whitespace (str);
+      if (*str++ == '[')
+        {
+          int reg;
+
+          skip_whitespace (str);
+          if ((reg = reg_required_here (&str, 15, REG_TYPE_SCORE)) == (int) FAIL)
+            {
+              return;
+            }
+
+          skip_whitespace (str);
+          if (*str++ != ']')
+            {
+              inst.error = _("missing ]");
+              return;
+            }
+
+          end_of_line (str);
+        }
+      else
+	inst.error = BAD_ARGS;
+    }
+}
+
+static void
+build_relax_frag (struct score_it fix_insts[RELAX_INST_NUM], int fix_num ATTRIBUTE_UNUSED,
+                  struct score_it var_insts[RELAX_INST_NUM], int var_num,
+                  symbolS *add_symbol)
+{
+  int i;
+  char *p;
+  fixS *fixp = NULL;
+  fixS *cur_fixp = NULL;
+  long where;
+  struct score_it inst_main;
+
+  memcpy (&inst_main, &fix_insts[0], sizeof (struct score_it));
+
+  /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+  inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
+  inst_main.type = Insn_PIC;
+
+  for (i = 0; i < var_num; i++)
+    {
+      inst_main.relax_size += var_insts[i].size;
+      var_insts[i].instruction = adjust_paritybit (var_insts[i].instruction,
+                                                   GET_INSN_CLASS (var_insts[i].type));
+    }
+
+  /* Check data dependency.  */
+  handle_dependency (&inst_main);
+
+  /* Start a new frag if frag_now is not empty.  */
+  if (frag_now_fix () != 0)
+    {
+      if (!frag_now->tc_frag_data.is_insn)
+	{
+          frag_wane (frag_now);
+	}
+      frag_new (0);
+    }
+  frag_grow (20);
+
+  /* Write fr_fix part.  */
+  p = frag_more (inst_main.size);
+  md_number_to_chars (p, inst_main.instruction, inst_main.size);
+
+  if (inst_main.reloc.type != BFD_RELOC_NONE)
+    fixp = fix_new_score (frag_now, p - frag_now->fr_literal, inst_main.size,
+			  &inst_main.reloc.exp, inst_main.reloc.pc_rel, inst_main.reloc.type);
+
+  frag_now->tc_frag_data.fixp = fixp;
+  cur_fixp = frag_now->tc_frag_data.fixp;
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (inst_main.size);
+#endif
+
+  where = p - frag_now->fr_literal + inst_main.size;
+  for (i = 0; i < var_num; i++)
+    {
+      if (i > 0)
+        where += var_insts[i - 1].size;
+
+      if (var_insts[i].reloc.type != BFD_RELOC_NONE)
+        {
+          fixp = fix_new_score (frag_now, where, var_insts[i].size,
+                                &var_insts[i].reloc.exp, var_insts[i].reloc.pc_rel,
+                                var_insts[i].reloc.type);
+          if (fixp)
+            {
+              if (cur_fixp)
+                {
+                  cur_fixp->fx_next = fixp;
+                  cur_fixp = cur_fixp->fx_next;
+                }
+              else
+                {
+                  frag_now->tc_frag_data.fixp = fixp;
+                  cur_fixp = frag_now->tc_frag_data.fixp;
+                }
+	    }
+        }
+    }
+
+  p = frag_var (rs_machine_dependent, inst_main.relax_size + RELAX_PAD_BYTE, 0,
+                RELAX_ENCODE (inst_main.size, inst_main.relax_size, inst_main.type,
+                0, inst_main.size, 0), add_symbol, 0, NULL);
+
+  /* Write fr_var part.
+     no calling gen_insn_frag, no fixS will be generated.  */
+  for (i = 0; i < var_num; i++)
+    {
+      md_number_to_chars (p, var_insts[i].instruction, var_insts[i].size);
+      p += var_insts[i].size;
+    }
+  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+  inst.bwarn = -1;
+}
+
+/* Build a relax frag for la instruction when generating PIC,
+   external symbol first and local symbol second.  */
+
+static void
+build_la_pic (int reg_rd, expressionS exp)
+{
+  symbolS *add_symbol = exp.X_add_symbol;
+  offsetT add_number = exp.X_add_number;
+  struct score_it fix_insts[RELAX_INST_NUM];
+  struct score_it var_insts[RELAX_INST_NUM];
+  int fix_num = 0;
+  int var_num = 0;
+  char tmp[MAX_LITERAL_POOL_SIZE];
+  int r1_bak;
+
+  r1_bak = nor1;
+  nor1 = 0;
+
+  if (add_number == 0)
+    {
+      fix_num = 1;
+      var_num = 2;
+
+      /* For an external symbol, only one insn is generated; 
+         For a local symbol, two insns are generated.  */
+      /* Fix part
+         For an external symbol: lw rD, <sym>($gp)
+                                 (BFD_RELOC_SCORE_GOT15 or BFD_RELOC_SCORE_CALL15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      if (reg_rd == PIC_CALL_REG)
+        inst.reloc.type = BFD_RELOC_SCORE_CALL15;
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol :
+         lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)
+	 addi rD, <sym>       (BFD_RELOC_GOT_LO16) */
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      sprintf (tmp, "addi_s_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[1], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+    }
+  else if (add_number >= -0x8000 && add_number <= 0x7fff)
+    {
+      /* Insn 1: lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+      /* Insn 2  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+         For an external symbol: addi rD, <constant> */
+      sprintf (tmp, "addi r%d, %d", reg_rd, (int)add_number);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+ 	 For a local symbol: addi rD, <sym>+<constant>    (BFD_RELOC_GOT_LO16)  */
+      sprintf (tmp, "addi_s_pic r%d, %s + %d", reg_rd, add_symbol->bsym->name, (int)add_number);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+    }
+  else
+    {
+      int hi = (add_number >> 16) & 0x0000FFFF;
+      int lo = add_number & 0x0000FFFF;
+
+      /* Insn 1: lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r%d, %s", reg_rd, add_symbol->bsym->name);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+      /* Insn 2  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+	 For an external symbol: ldis r1, HI%<constant>  */
+      sprintf (tmp, "ldis r1, %d", hi);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol: ldis r1, HI%<constant>
+         but, if lo is outof 16 bit, make hi plus 1  */
+      if ((lo < -0x8000) || (lo > 0x7fff))
+	{
+	  hi += 1;
+	}
+      sprintf (tmp, "ldis_pic r1, %d", hi);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 3  */
+      fix_num = 1;
+      var_num = 1;
+      /* Fix part
+	 For an external symbol: ori r1, LO%<constant>  */
+      sprintf (tmp, "ori r1, %d", lo);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+  	 For a local symbol: addi r1, <sym>+LO%<constant>    (BFD_RELOC_GOT_LO16)  */
+      sprintf (tmp, "addi_u_pic r1, %s + %d", add_symbol->bsym->name, lo);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 4: add rD, rD, r1  */
+      sprintf (tmp, "add r%d, r%d, r1", reg_rd, reg_rd);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+	return;
+
+     /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+     inst.bwarn = -1;
+    }
+
+  nor1 = r1_bak;
+}
+
+/* Handle la.  */
+static void
+do_macro_la_rdi32 (char *str)
+{
+  int reg_rd;
+
+  skip_whitespace (str);
+  if ((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      char append_str[MAX_LITERAL_POOL_SIZE];
+      char *keep_data = str;
+
+      /* la rd, simm16.  */
+      if (data_op2 (&str, 1, _SIMM16_LA) != (int) FAIL)
+        {
+          end_of_line (str);
+          return;
+        }
+      /* la rd, imm32 or la rd, label.  */
+      else
+        {
+          SET_INSN_ERROR (NULL);
+          str = keep_data;
+          if ((data_op2 (&str, 1, _VALUE_HI16) == (int) FAIL)
+              || (end_of_line (str) == (int) FAIL))
+            {
+              return;
+            }
+          else
+            {
+              if ((score_pic == NO_PIC) || (!inst.reloc.exp.X_add_symbol))
+                {
+                  sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+
+                  sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+		}
+	      else
+		{
+		  assert (inst.reloc.exp.X_add_symbol);
+		  build_la_pic (reg_rd, inst.reloc.exp);
+		}
+
+              /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+              inst.bwarn = -1;
+            }
+        }
+    }
+}
+
+/* Handle li.  */
+static void
+do_macro_li_rdi32 (char *str){
+
+  int reg_rd;
+
+  skip_whitespace (str);
+  if ((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&str) == (int) FAIL)
+    {
+      return;
+    }
+  else
+    {
+      char *keep_data = str;
+
+      /* li rd, simm16.  */
+      if (data_op2 (&str, 1, _SIMM16_LA) != (int) FAIL)
+        {
+          end_of_line (str);
+          return;
+        }
+      /* li rd, imm32.  */
+      else
+        {
+          char append_str[MAX_LITERAL_POOL_SIZE];
+
+          str = keep_data;
+
+          if ((data_op2 (&str, 1, _VALUE_HI16) == (int) FAIL)
+              || (end_of_line (str) == (int) FAIL))
+            {
+              return;
+            }
+          else if (inst.reloc.exp.X_add_symbol)
+            {
+              inst.error = _("li rd label isn't correct instruction form");
+              return;
+            }
+          else
+            {
+              sprintf (append_str, "ld_i32hi r%d, %s", reg_rd, keep_data);
+
+              if (append_insn (append_str, TRUE) == (int) FAIL)
+		return;
+              else
+                {
+                  sprintf (append_str, "ld_i32lo r%d, %s", reg_rd, keep_data);
+                  if (append_insn (append_str, TRUE) == (int) FAIL)
+		    return;
+
+                  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+                  inst.bwarn = -1;
+                }
+            }
+        }
+    }
+}
+
+/* Handle mul/mulu/div/divu/rem/remu.  */
+static void
+do_macro_mul_rdrsrs (char *str)
+{
+  int reg_rd;
+  int reg_rs1;
+  int reg_rs2;
+  char *backupstr;
+  char append_str[MAX_LITERAL_POOL_SIZE];
+
+  if (university_version == 1)
+    as_warn ("%s", ERR_FOR_SCORE5U_MUL_DIV);
+
+  strcpy (append_str, str);
+  backupstr = append_str;
+  skip_whitespace (backupstr);
+  if (((reg_rd = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&backupstr) == (int) FAIL)
+      || ((reg_rs1 = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL))
+    {
+      inst.error = BAD_ARGS;
+      return;
+    }
+
+  if (skip_past_comma (&backupstr) == (int) FAIL)
+    {
+      /* rem/remu rA, rB is error format.  */
+      if (strcmp (inst.name, "rem") == 0 || strcmp (inst.name, "remu") == 0)
+        {
+          SET_INSN_ERROR (BAD_ARGS);
+        }
+      else
+        {
+          SET_INSN_ERROR (NULL);
+          do_rsrs (str);
+        }
+      return;
+    }
+  else
+    {
+      SET_INSN_ERROR (NULL);
+      if (((reg_rs2 = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+          || (end_of_line (backupstr) == (int) FAIL))
+        {
+          return;
+        }
+      else
+        {
+          char append_str1[MAX_LITERAL_POOL_SIZE];
+
+          if (strcmp (inst.name, "rem") == 0)
+            {
+              sprintf (append_str, "mul r%d, r%d", reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfceh  r%d", reg_rd);
+            }
+          else if (strcmp (inst.name, "remu") == 0)
+            {
+              sprintf (append_str, "mulu r%d, r%d", reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfceh  r%d", reg_rd);
+            }
+          else
+            {
+              sprintf (append_str, "%s r%d, r%d", inst.name, reg_rs1, reg_rs2);
+              sprintf (append_str1, "mfcel  r%d", reg_rd);
+            }
+
+          /* Output mul/mulu or div/divu or rem/remu.  */
+          if (append_insn (append_str, TRUE) == (int) FAIL)
+	    return;
+
+          /* Output mfcel or mfceh.  */
+          if (append_insn (append_str1, TRUE) == (int) FAIL)
+	    return;
+
+          /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+          inst.bwarn = -1;
+        }
+    }
+}
+
+static void
+exp_macro_ldst_abs (char *str)
+{
+  int reg_rd;
+  char *backupstr, *tmp;
+  char append_str[MAX_LITERAL_POOL_SIZE];
+  char verifystr[MAX_LITERAL_POOL_SIZE];
+  struct score_it inst_backup;
+  int r1_bak = 0;
+
+  r1_bak = nor1;
+  nor1 = 0;
+  memcpy (&inst_backup, &inst, sizeof (struct score_it));
+
+  strcpy (verifystr, str);
+  backupstr = verifystr;
+  skip_whitespace (backupstr);
+  if ((reg_rd = reg_required_here (&backupstr, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  tmp = backupstr;
+  if (skip_past_comma (&backupstr) == (int) FAIL)
+    return;
+
+  backupstr = tmp;
+  sprintf (append_str, "li r1  %s", backupstr);
+  append_insn (append_str, TRUE);
+
+  memcpy (&inst, &inst_backup, sizeof (struct score_it));
+  sprintf (append_str, " r%d, [r1,0]", reg_rd);
+  do_ldst_insn (append_str);
+
+  nor1 = r1_bak;
+}
+
+static int
+nopic_need_relax (symbolS * sym, int before_relaxing)
+{
+  if (sym == NULL)
+    return 0;
+  else if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
+    {
+      const char *symname;
+      const char *segname;
+
+      /* Find out whether this symbol can be referenced off the $gp
+         register.  It can be if it is smaller than the -G size or if
+         it is in the .sdata or .sbss section.  Certain symbols can
+         not be referenced off the $gp, although it appears as though
+         they can.  */
+      symname = S_GET_NAME (sym);
+      if (symname != (const char *)NULL
+          && (strcmp (symname, "eprol") == 0
+              || strcmp (symname, "etext") == 0
+              || strcmp (symname, "_gp") == 0
+              || strcmp (symname, "edata") == 0
+              || strcmp (symname, "_fbss") == 0
+              || strcmp (symname, "_fdata") == 0
+              || strcmp (symname, "_ftext") == 0
+              || strcmp (symname, "end") == 0
+              || strcmp (symname, GP_DISP_LABEL) == 0))
+        {
+          return 1;
+        }
+      else if ((!S_IS_DEFINED (sym) || S_IS_COMMON (sym)) && (0
+      /* We must defer this decision until after the whole file has been read,
+         since there might be a .extern after the first use of this symbol.  */
+               || (before_relaxing
+                   && S_GET_VALUE (sym) == 0)
+               || (S_GET_VALUE (sym) != 0
+                   && S_GET_VALUE (sym) <= g_switch_value)))
+        {
+          return 0;
+        }
+
+      segname = segment_name (S_GET_SEGMENT (sym));
+      return (strcmp (segname, ".sdata") != 0
+	      && strcmp (segname, ".sbss") != 0
+	      && strncmp (segname, ".sdata.", 7) != 0
+	      && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
+    }
+  /* We are not optimizing for the $gp register.  */
+  else
+    return 1;
+}
+
+/* Build a relax frag for lw/st instruction when generating PIC,
+   external symbol first and local symbol second.  */
+
+static void
+build_lwst_pic (int reg_rd, expressionS exp, const char *insn_name)
+{
+  symbolS *add_symbol = exp.X_add_symbol;
+  int add_number = exp.X_add_number;
+  struct score_it fix_insts[RELAX_INST_NUM];
+  struct score_it var_insts[RELAX_INST_NUM];
+  int fix_num = 0;
+  int var_num = 0;
+  char tmp[MAX_LITERAL_POOL_SIZE];
+  int r1_bak;
+
+  r1_bak = nor1;
+  nor1 = 0;
+
+  if ((add_number == 0) || (add_number >= -0x8000 && add_number <= 0x7fff))
+    {
+      fix_num = 1;
+      var_num = 2;
+
+      /* For an external symbol, two insns are generated;
+         For a local symbol, three insns are generated.  */
+      /* Fix part
+         For an external symbol: lw rD, <sym>($gp)
+                                 (BFD_RELOC_SCORE_GOT15)  */
+      sprintf (tmp, "lw_pic r1, %s", add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+        return;
+
+      memcpy (&fix_insts[0], &inst, sizeof (struct score_it));
+
+      /* Var part
+	 For a local symbol :
+         lw rD, <sym>($gp)    (BFD_RELOC_SCORE_GOT15)
+	 addi rD, <sym>       (BFD_RELOC_GOT_LO16) */
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+      memcpy (&var_insts[0], &inst, sizeof (struct score_it));
+      sprintf (tmp, "addi_s_pic r1, %s", add_symbol->bsym->name);
+      if (append_insn (tmp, FALSE) == (int) FAIL)
+        return;
+
+      memcpy (&var_insts[1], &inst, sizeof (struct score_it));
+      build_relax_frag (fix_insts, fix_num, var_insts, var_num, add_symbol);
+
+      /* Insn 2 or Insn 3: lw/st rD, [r1, constant]  */
+      sprintf (tmp, "%s r%d, [r1, %d]", insn_name, reg_rd, add_number);
+      if (append_insn (tmp, TRUE) == (int) FAIL)
+        return;
+
+      /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+      inst.bwarn = -1;
+    }
+  else
+    {
+      inst.error = _("PIC code offset overflow (max 16 signed bits)");
+      return;
+    }
+
+  nor1 = r1_bak;
+}
+
+static void
+do_macro_ldst_label (char *str)
+{
+  int i;
+  int ldst_gp_p = 0;
+  int reg_rd;
+  int r1_bak;
+  char *backup_str;
+  char *label_str;
+  char *absolute_value;
+  char append_str[3][MAX_LITERAL_POOL_SIZE];
+  char verifystr[MAX_LITERAL_POOL_SIZE];
+  struct score_it inst_backup;
+  struct score_it inst_expand[3];
+  struct score_it inst_main;
+
+  memcpy (&inst_backup, &inst, sizeof (struct score_it));
+  strcpy (verifystr, str);
+  backup_str = verifystr;
+
+  skip_whitespace (backup_str);
+  if ((reg_rd = reg_required_here (&backup_str, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  if (skip_past_comma (&backup_str) == (int) FAIL)
+    return;
+
+  label_str = backup_str;
+
+  /* Ld/st rD, [rA, imm]      ld/st rD, [rA]+, imm      ld/st rD, [rA, imm]+.  */
+  if (*backup_str == '[')
+    {
+      inst.type = Rd_rvalueRs_preSI12;
+      do_ldst_insn (str);
+      return;
+    }
+
+  /* Ld/st rD, imm.  */
+  absolute_value = backup_str;
+  inst.type = Rd_rvalueRs_SI15;
+  if ((my_get_expression (&inst.reloc.exp, &backup_str) == (int) FAIL)
+      || (validate_immediate (inst.reloc.exp.X_add_number, _VALUE, 0) == (int) FAIL)
+      || (end_of_line (backup_str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          memcpy (&inst, &inst_backup, sizeof (struct score_it));
+          exp_macro_ldst_abs (str);
+          return;
+        }
+    }
+
+  /* Ld/st rD, label.  */
+  inst.type = Rd_rvalueRs_SI15;
+  backup_str = absolute_value;
+  if ((data_op2 (&backup_str, 1, _GP_IMM15) == (int) FAIL)
+      || (end_of_line (backup_str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          if (!inst.error)
+	    inst.error = BAD_ARGS;
+
+          return;
+        }
+
+      if (score_pic == PIC)
+        {
+          int ldst_idx = 0;
+          ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+          build_lwst_pic (reg_rd, inst.reloc.exp, score_ldst_insns[ldst_idx * 3 + 0].template);
+          return;
+        }
+      else
+	{
+          if ((inst.reloc.exp.X_add_number <= 0x3fff)
+               && (inst.reloc.exp.X_add_number >= -0x4000)
+               && (!nopic_need_relax (inst.reloc.exp.X_add_symbol, 1)))
+	    {
+              int ldst_idx = 0;
+
+              /* Assign the real opcode.  */
+              ldst_idx = inst.instruction & OPC_PSEUDOLDST_MASK;
+              inst.instruction &= ~OPC_PSEUDOLDST_MASK;
+              inst.instruction |= score_ldst_insns[ldst_idx * 3 + 0].value;
+              inst.instruction |= reg_rd << 20;
+              inst.instruction |= GP << 15;
+              inst.relax_inst = 0x8000;
+              inst.relax_size = 0;
+              ldst_gp_p = 1;
+	    }
+	}
+    }
+
+  /* Backup inst.  */
+  memcpy (&inst_main, &inst, sizeof (struct score_it));
+  r1_bak = nor1;
+  nor1 = 0;
+
+  /* Determine which instructions should be output.  */
+  sprintf (append_str[0], "ld_i32hi r1, %s", label_str);
+  sprintf (append_str[1], "ld_i32lo r1, %s", label_str);
+  sprintf (append_str[2], "%s r%d, [r1, 0]", inst_backup.name, reg_rd);
+
+  /* Generate three instructions.
+     la r1, label
+     ld/st rd, [r1, 0]  */
+  for (i = 0; i < 3; i++)
+    {
+      if (append_insn (append_str[i], FALSE) == (int) FAIL)
+	return;
+
+      memcpy (&inst_expand[i], &inst, sizeof (struct score_it));
+    }
+
+  if (ldst_gp_p)
+    {
+      char *p;
+
+      /* Adjust instruction opcode and to be relaxed instruction opcode.  */
+      inst_main.instruction = adjust_paritybit (inst_main.instruction, GET_INSN_CLASS (inst_main.type));
+      inst_main.relax_size = inst_expand[0].size + inst_expand[1].size + inst_expand[2].size;
+      inst_main.type = Insn_GP;
+
+      for (i = 0; i < 3; i++)
+	inst_expand[i].instruction = adjust_paritybit (inst_expand[i].instruction
+						       , GET_INSN_CLASS (inst_expand[i].type));
+
+      /* Check data dependency.  */
+      handle_dependency (&inst_main);
+
+      /* Start a new frag if frag_now is not empty.  */
+      if (frag_now_fix () != 0)
+        {
+          if (!frag_now->tc_frag_data.is_insn)
+	    frag_wane (frag_now);
+
+          frag_new (0);
+        }
+      frag_grow (20);
+
+      /* Write fr_fix part.  */
+      p = frag_more (inst_main.size);
+      md_number_to_chars (p, inst_main.instruction, inst_main.size);
+
+      if (inst_main.reloc.type != BFD_RELOC_NONE)
+        {
+          fix_new_score (frag_now, p - frag_now->fr_literal, inst_main.size,
+                         &inst_main.reloc.exp, inst_main.reloc.pc_rel, inst_main.reloc.type);
+        }
+
+#ifdef OBJ_ELF
+      dwarf2_emit_insn (inst_main.size);
+#endif
+
+      /* GP instruction can not do optimization, only can do relax between
+         1 instruction and 3 instructions.  */
+      p = frag_var (rs_machine_dependent, inst_main.relax_size + RELAX_PAD_BYTE, 0,
+                    RELAX_ENCODE (inst_main.size, inst_main.relax_size, inst_main.type, 0, 4, 0),
+                    inst_main.reloc.exp.X_add_symbol, 0, NULL);
+
+      /* Write fr_var part.
+         no calling gen_insn_frag, no fixS will be generated.  */
+      md_number_to_chars (p, inst_expand[0].instruction, inst_expand[0].size);
+      p += inst_expand[0].size;
+      md_number_to_chars (p, inst_expand[1].instruction, inst_expand[1].size);
+      p += inst_expand[1].size;
+      md_number_to_chars (p, inst_expand[2].instruction, inst_expand[2].size);
+    }
+  else
+    {
+      gen_insn_frag (&inst_expand[0], NULL);
+      gen_insn_frag (&inst_expand[1], NULL);
+      gen_insn_frag (&inst_expand[2], NULL);
+    }
+  nor1 = r1_bak;
+
+  /* Set bwarn as -1, so macro instruction itself will not be generated frag.  */
+  inst.bwarn = -1;
+}
+
+static void
+do_lw_pic (char *str)
+{
+  int reg_rd;
+
+  skip_whitespace (str);
+  if (((reg_rd = reg_required_here (&str, 20, REG_TYPE_SCORE)) == (int) FAIL)
+      || (skip_past_comma (&str) == (int) FAIL)
+      || (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL)
+      || (end_of_line (str) == (int) FAIL))
+    {
+      return;
+    }
+  else
+    {
+      if (inst.reloc.exp.X_add_symbol == 0)
+        {
+          if (!inst.error)
+	    inst.error = BAD_ARGS;
+
+          return;
+        }
+
+      inst.instruction |= GP << 15;
+      inst.reloc.type = BFD_RELOC_SCORE_GOT15;
+    }
+}
+
+static void
+do_empty (char *str)
+{
+  str = str;
+  if (university_version == 1)
+    {
+      if (((inst.instruction & 0x3e0003ff) == 0x0c000004)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000024)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000044)
+          || ((inst.instruction & 0x3e0003ff) == 0x0c000064))
+        {
+          inst.error = ERR_FOR_SCORE5U_MMU;
+          return;
+        }
+    }
+  if (end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.relax_inst != 0x8000)
+    {
+      if (inst.type == NO_OPD)
+        {
+          inst.relax_size = 2;
+        }
+      else
+        {
+          inst.relax_size = 4;
+        }
+    }
+}
+
+static void
+do_jump (char *str)
+{
+  char *save_in;
+
+  skip_whitespace (str);
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    return;
+
+  if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+
+  if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
+      && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
+    {
+      inst.error = _("invalid constant: 25 bit expression not in range -2^24..2^24");
+      return;
+    }
+
+  save_in = input_line_pointer;
+  input_line_pointer = str;
+  inst.reloc.type = BFD_RELOC_SCORE_JMP;
+  inst.reloc.pc_rel = 1;
+  input_line_pointer = save_in;
+}
+
+static void
+do16_jump (char *str)
+{
+  skip_whitespace (str);
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xfffff800) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xfffff800) != 0xfffff800))
+    {
+      inst.error = _("invalid constant: 12 bit expression not in range -2^11..2^11");
+      return;
+    }
+
+  inst.reloc.type = BFD_RELOC_SCORE16_JMP;
+  inst.reloc.pc_rel = 1;
+}
+
+static void
+do_branch (char *str)
+{
+  unsigned long abs_value = 0;
+
+  if (my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL)
+    {
+      return;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label  ");
+      return;
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xff000000) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xff000000) != 0xff000000))
+    {
+      inst.error = _("invalid constant: 20 bit expression not in range -2^19..2^19");
+      return;
+    }
+
+  inst.reloc.type = BFD_RELOC_SCORE_BRANCH;
+  inst.reloc.pc_rel = 1;
+
+  /* Branch 32  offset field : 20 bit, 16 bit branch offset field : 8 bit.  */
+  inst.instruction |= (inst.reloc.exp.X_add_number & 0x3fe) | ((inst.reloc.exp.X_add_number & 0xffc00) << 5);
+
+  /* Compute 16 bit branch instruction.  */
+  if ((inst.relax_inst != 0x8000) && (abs_value & 0xfffffe00) == 0)
+    {
+      inst.relax_inst |= (((inst.instruction >> 10) & 0xf) << 8);
+      inst.relax_inst |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
+      inst.relax_size = 2;
+    }
+  else
+    {
+      inst.relax_inst = 0x8000;
+    }
+}
+
+static void
+do16_branch (char *str)
+{
+  if ((my_get_expression (&inst.reloc.exp, &str) == (int) FAIL
+      || end_of_line (str) == (int) FAIL))
+    {
+      ;
+    }
+  else if (inst.reloc.exp.X_add_symbol == 0)
+    {
+      inst.error = _("lacking label");
+    }
+  else if (((inst.reloc.exp.X_add_number & 0xffffff00) != 0)
+           && ((inst.reloc.exp.X_add_number & 0xffffff00) != 0xffffff00))
+    {
+      inst.error = _("invalid constant: 9 bit expression not in range -2^8..2^8");
+    }
+  else
+    {
+      inst.reloc.type = BFD_RELOC_SCORE16_BRANCH;
+      inst.reloc.pc_rel = 1;
+      inst.instruction |= ((inst.reloc.exp.X_add_number >> 1) & 0xff);
+    }
+}
+
+/* Iterate over the base tables to create the instruction patterns.  */
+static void
+build_score_ops_hsh (void)
+{
+  unsigned int i;
+  static struct obstack insn_obstack;
+
+  obstack_begin (&insn_obstack, 4000);
+  for (i = 0; i < sizeof (score_insns) / sizeof (struct asm_opcode); i++)
+    {
+      const struct asm_opcode *insn = score_insns + i;
+      unsigned len = strlen (insn->template);
+      struct asm_opcode *new;
+      char *template;
+      new = obstack_alloc (&insn_obstack, sizeof (struct asm_opcode));
+      template = obstack_alloc (&insn_obstack, len + 1);
+
+      strcpy (template, insn->template);
+      new->template = template;
+      new->parms = insn->parms;
+      new->value = insn->value;
+      new->relax_value = insn->relax_value;
+      new->type = insn->type;
+      new->bitmask = insn->bitmask;
+      hash_insert (score_ops_hsh, new->template, (void *) new);
+    }
+}
+
+static void
+build_dependency_insn_hsh (void)
+{
+  unsigned int i;
+  static struct obstack dependency_obstack;
+
+  obstack_begin (&dependency_obstack, 4000);
+  for (i = 0; i < sizeof (insn_to_dependency_table) / sizeof (insn_to_dependency_table[0]); i++)
+    {
+      const struct insn_to_dependency *tmp = insn_to_dependency_table + i;
+      unsigned len = strlen (tmp->insn_name);
+      struct insn_to_dependency *new;
+
+      new = obstack_alloc (&dependency_obstack, sizeof (struct insn_to_dependency));
+      new->insn_name = obstack_alloc (&dependency_obstack, len + 1);
+
+      strcpy (new->insn_name, tmp->insn_name);
+      new->type = tmp->type;
+      hash_insert (dependency_insn_hsh, new->insn_name, (void *) new);
+    }
+}
+
+/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
+   for use in the a.out file, and stores them in the array pointed to by buf.
+   This knows about the endian-ness of the target machine and does
+   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
+   2 (short) and 4 (long)  Floating numbers are put out as a series of
+   LITTLENUMS (shorts, here at least).  */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+static valueT
+md_chars_to_number (char *buf, int n)
+{
+  valueT result = 0;
+  unsigned char *where = (unsigned char *)buf;
+
+  if (target_big_endian)
+    {
+      while (n--)
+        {
+          result <<= 8;
+          result |= (*where++ & 255);
+        }
+    }
+  else
+    {
+      while (n--)
+        {
+          result <<= 8;
+          result |= (where[n] & 255);
+        }
+    }
+
+  return result;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.
+
+   Note that fp constants aren't represent in the normal way on the ARM.
+   In big endian mode, things are as expected.  However, in little endian
+   mode fp constants are big-endian word-wise, and little-endian byte-wise
+   within the words.  For example, (double) 1.1 in big endian mode is
+   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
+   the byte sequence 99 99 f1 3f 9a 99 99 99.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  char *t;
+  int i;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+    case 'x':
+    case 'X':
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+    default:
+      *sizeP = 0;
+      return _("bad call to MD_ATOF()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * 2;
+
+  if (target_big_endian)
+    {
+      for (i = 0; i < prec; i++)
+        {
+          md_number_to_chars (litP, (valueT) words[i], 2);
+          litP += 2;
+        }
+    }
+  else
+    {
+      for (i = 0; i < prec; i += 2)
+        {
+          md_number_to_chars (litP, (valueT) words[i + 1], 2);
+          md_number_to_chars (litP + 2, (valueT) words[i], 2);
+          litP += 4;
+        }
+    }
+
+  return 0;
+}
+
+/* Return true if the given symbol should be considered local for PIC.  */
+
+static bfd_boolean
+pic_need_relax (symbolS *sym, asection *segtype)
+{
+  asection *symsec;
+  bfd_boolean linkonce;
+
+  /* Handle the case of a symbol equated to another symbol.  */
+  while (symbol_equated_reloc_p (sym))
+    {
+      symbolS *n;
+
+      /* It's possible to get a loop here in a badly written
+	 program.  */
+      n = symbol_get_value_expression (sym)->X_add_symbol;
+      if (n == sym)
+	break;
+      sym = n;
+    }
+
+  symsec = S_GET_SEGMENT (sym);
+
+  /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
+  linkonce = FALSE;
+  if (symsec != segtype && ! S_IS_LOCAL (sym))
+    {
+      if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE) != 0)
+	linkonce = TRUE;
+
+      /* The GNU toolchain uses an extension for ELF: a section
+	  beginning with the magic string .gnu.linkonce is a linkonce
+	  section.  */
+      if (strncmp (segment_name (symsec), ".gnu.linkonce",
+		   sizeof ".gnu.linkonce" - 1) == 0)
+	linkonce = TRUE;
+    }
+
+  /* This must duplicate the test in adjust_reloc_syms.  */
+  return (symsec != &bfd_und_section
+	    && symsec != &bfd_abs_section
+	  && ! bfd_is_com_section (symsec)
+	    && !linkonce
+#ifdef OBJ_ELF
+	  /* A global or weak symbol is treated as external.  */
+	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
+	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
+#endif
+	  );
+}
+
+static int
+judge_size_before_relax (fragS * fragp, asection *sec)
+{
+  int change = 0;
+
+  if (score_pic == NO_PIC)
+    change = nopic_need_relax (fragp->fr_symbol, 0);
+  else
+    change = pic_need_relax (fragp->fr_symbol, sec);
+
+  if (change == 1)
+    {
+      /* Only at the first time determining whether GP instruction relax should be done,
+         return the difference between insntruction size and instruction relax size.  */
+      if (fragp->fr_opcode == NULL)
+	{
+	  fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+	  fragp->fr_opcode = fragp->fr_literal + RELAX_RELOC1 (fragp->fr_subtype);
+          return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
+	}
+    }
+
+  return 0;
+}
+
+/* In this function, we determine whether GP instruction should do relaxation,
+   for the label being against was known now.
+   Doing this here but not in md_relax_frag() can induce iteration times
+   in stage of doing relax.  */
+int
+md_estimate_size_before_relax (fragS * fragp, asection * sec ATTRIBUTE_UNUSED)
+{
+  if ((RELAX_TYPE (fragp->fr_subtype) == Insn_GP)
+      || (RELAX_TYPE (fragp->fr_subtype) == Insn_PIC))
+    return judge_size_before_relax (fragp, sec);
+
+  return 0;
+}
+
+static int
+b32_relax_to_b16 (fragS * fragp)
+{
+  int grows = 0;
+  int relaxable_p = 0;
+  int old;
+  int new;
+  int frag_addr = fragp->fr_address + fragp->insn_addr;
+
+  addressT symbol_address = 0;
+  symbolS *s;
+  offsetT offset;
+  unsigned long value;
+  unsigned long abs_value;
+
+  /* FIXME : here may be able to modify better .
+     I don't know how to get the fragp's section ,
+     so in relax stage , it may be wrong to calculate the symbol's offset when the frag's section
+     is different from the symbol's.  */
+
+  old = RELAX_OLD (fragp->fr_subtype);
+  new = RELAX_NEW (fragp->fr_subtype);
+  relaxable_p = RELAX_OPT (fragp->fr_subtype);
+
+  s = fragp->fr_symbol;
+  /* b/bl immediate  */
+  if (s == NULL)
+    frag_addr = 0;
+  else
+    {
+      if (s->bsym != 0)
+	symbol_address = (addressT) s->sy_frag->fr_address;
+    }
+
+  value = md_chars_to_number (fragp->fr_literal, INSN_SIZE);
+
+  /* b 32's offset : 20 bit, b 16's tolerate field : 0xff.  */
+  offset = ((value & 0x3ff0000) >> 6) | (value & 0x3fe);
+  if ((offset & 0x80000) == 0x80000)
+    offset |= 0xfff00000;
+
+  abs_value = offset + symbol_address - frag_addr;
+  if ((abs_value & 0x80000000) == 0x80000000)
+    abs_value = 0xffffffff - abs_value + 1;
+
+  /* Relax branch 32 to branch 16.  */
+  if (relaxable_p && (s->bsym != NULL) && ((abs_value & 0xffffff00) == 0)
+      && (S_IS_DEFINED (s) && !S_IS_COMMON (s) && !S_IS_EXTERNAL (s)))
+    {
+      /* do nothing.  */
+    }
+  else
+    {
+      /* Branch 32 can not be relaxed to b 16, so clear OPT bit.  */
+      fragp->fr_opcode = NULL;
+      fragp->fr_subtype = RELAX_OPT_CLEAR (fragp->fr_subtype);
+    }
+
+  return grows;
+}
+
+/* Main purpose is to determine whether one frag should do relax.
+   frag->fr_opcode indicates this point.  */
+
+int
+score_relax_frag (asection * sec ATTRIBUTE_UNUSED, fragS * fragp, long stretch ATTRIBUTE_UNUSED)
+{
+  int grows = 0;
+  int insn_size;
+  int insn_relax_size;
+  int do_relax_p = 0;           /* Indicate doing relaxation for this frag.  */
+  int relaxable_p = 0;
+  bfd_boolean word_align_p = FALSE;
+  fragS *next_fragp;
+
+  /* If the instruction address is odd, make it half word align first.  */
+  if ((fragp->fr_address) % 2 != 0)
+    {
+      if ((fragp->fr_address + fragp->insn_addr) % 2 != 0)
+	{
+          fragp->insn_addr = 1;
+          grows += 1;
+	}
+    }
+
+  word_align_p = ((fragp->fr_address + fragp->insn_addr) % 4 == 0) ? TRUE : FALSE;
+
+  /* Get instruction size and relax size after the last relaxation.  */
+  if (fragp->fr_opcode)
+    {
+      insn_size = RELAX_NEW (fragp->fr_subtype);
+      insn_relax_size = RELAX_OLD (fragp->fr_subtype);
+    }
+  else
+    {
+      insn_size = RELAX_OLD (fragp->fr_subtype);
+      insn_relax_size = RELAX_NEW (fragp->fr_subtype);
+    }
+
+  /* Handle specially for GP instruction.  for, judge_size_before_relax() has already determine
+     whether the GP instruction should do relax.  */
+  if ((RELAX_TYPE (fragp->fr_subtype) == Insn_GP)
+      || (RELAX_TYPE (fragp->fr_subtype) == Insn_PIC))
+    {
+      if (!word_align_p)
+        {
+          if (fragp->insn_addr < 2)
+            {
+              fragp->insn_addr += 2;
+              grows += 2;
+            }
+          else
+            {
+              fragp->insn_addr -= 2;
+              grows -= 2;
+            }
+        }
+
+      if (fragp->fr_opcode)
+	fragp->fr_fix = RELAX_NEW (fragp->fr_subtype) + fragp->insn_addr;
+      else
+	fragp->fr_fix = RELAX_OLD (fragp->fr_subtype) + fragp->insn_addr;
+    }
+  else
+    {
+      if (RELAX_TYPE (fragp->fr_subtype) == PC_DISP19div2)
+	b32_relax_to_b16 (fragp);
+
+      relaxable_p = RELAX_OPT (fragp->fr_subtype);
+      next_fragp = fragp->fr_next;
+      while ((next_fragp) && (next_fragp->fr_type != rs_machine_dependent))
+	{
+          next_fragp = next_fragp->fr_next;
+	}
+
+      if (next_fragp)
+        {
+          int n_insn_size;
+          int n_relaxable_p = 0;
+
+          if (next_fragp->fr_opcode)
+            {
+              n_insn_size = RELAX_NEW (next_fragp->fr_subtype);
+            }
+          else
+            {
+              n_insn_size = RELAX_OLD (next_fragp->fr_subtype);
+            }
+
+          if (RELAX_TYPE (next_fragp->fr_subtype) == PC_DISP19div2)
+            b32_relax_to_b16 (next_fragp);
+          n_relaxable_p = RELAX_OPT (next_fragp->fr_subtype);
+
+          if (word_align_p)
+            {
+              if (insn_size == 4)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p && ((n_insn_size == 2) || n_relaxable_p))
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                }
+              else if (insn_size == 2)
+                {
+                  /* 16 -> 32.  */
+                  if (relaxable_p && (((n_insn_size == 4) && !n_relaxable_p) || (n_insn_size > 4)))
+                    {
+                      grows += 2;
+                      do_relax_p = 1;
+                    }
+                }
+              else
+                {
+		  abort ();
+                }
+            }
+          else
+            {
+              if (insn_size == 4)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p)
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                  /* Make the 32 bit insturction word align.  */
+                  else
+                    {
+                      fragp->insn_addr += 2;
+                      grows += 2;
+		    }
+                }
+              else if (insn_size == 2)
+                {
+                  /* Do nothing.  */
+                }
+              else
+                {
+		  abort ();
+                }
+            }
+        }
+      else
+        {
+	  /* Here, try best to do relax regardless fragp->fr_next->fr_type.  */
+          if (word_align_p == FALSE)
+            {
+              if (insn_size % 4 == 0)
+                {
+                  /* 32 -> 16.  */
+                  if (relaxable_p)
+                    {
+                      grows -= 2;
+                      do_relax_p = 1;
+                    }
+                  else
+                    {
+                      fragp->insn_addr += 2;
+                      grows += 2;
+                    }
+                }
+            }
+          else
+            {
+	      /* Do nothing.  */
+            }
+        }
+
+      /* fragp->fr_opcode indicates whether this frag should be relaxed.  */
+      if (do_relax_p)
+        {
+          if (fragp->fr_opcode)
+            {
+              fragp->fr_opcode = NULL;
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_OLD (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+          else
+            {
+              fragp->fr_opcode = fragp->fr_literal + RELAX_RELOC1 (fragp->fr_subtype);
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+        }
+      else
+	{
+          if (fragp->fr_opcode)
+            {
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_NEW (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+          else
+            {
+	      /* Guarantee estimate stage is correct.  */
+              fragp->fr_fix = RELAX_OLD (fragp->fr_subtype);
+              fragp->fr_fix += fragp->insn_addr;
+            }
+	}
+    }
+
+  return grows;
+}
+
+void
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, fragS * fragp)
+{
+  int old;
+  int new;
+  char backup[20];
+  fixS *fixp;
+
+  old = RELAX_OLD (fragp->fr_subtype);
+  new = RELAX_NEW (fragp->fr_subtype);
+
+  /* fragp->fr_opcode indicates whether this frag should be relaxed.  */
+  if (fragp->fr_opcode == NULL)
+    {
+      memcpy (backup, fragp->fr_literal, old);
+      fragp->fr_fix = old;
+    }
+  else
+    {
+      memcpy (backup, fragp->fr_literal + old, new);
+      fragp->fr_fix = new;
+    }
+
+  fixp = fragp->tc_frag_data.fixp;
+  while (fixp && fixp->fx_frag == fragp && fixp->fx_where < old)
+    {
+      if (fragp->fr_opcode)
+	fixp->fx_done = 1;
+      fixp = fixp->fx_next;
+    }
+  while (fixp && fixp->fx_frag == fragp)
+    {
+      if (fragp->fr_opcode)
+	fixp->fx_where -= old + fragp->insn_addr;
+      else
+	fixp->fx_done = 1;
+      fixp = fixp->fx_next;
+    }
+
+  if (fragp->insn_addr)
+    {
+      md_number_to_chars (fragp->fr_literal, 0x0, fragp->insn_addr);
+    }
+  memcpy (fragp->fr_literal + fragp->insn_addr, backup, fragp->fr_fix);
+  fragp->fr_fix += fragp->insn_addr;
+}
+
+/* Implementation of md_frag_check.
+   Called after md_convert_frag().  */
+
+void
+score_frag_check (fragS * fragp ATTRIBUTE_UNUSED)
+{
+  know (fragp->insn_addr <= RELAX_PAD_BYTE);
+}
+
+bfd_boolean
+score_fix_adjustable (fixS * fixP)
+{
+  if (fixP->fx_addsy == NULL)
+    {
+      return 1;
+    }
+  else if (OUTPUT_FLAVOR == bfd_target_elf_flavour
+      && (S_IS_EXTERNAL (fixP->fx_addsy) || S_IS_WEAK (fixP->fx_addsy)))
+    {
+      return 0;
+    }
+  else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    {
+      return 0;
+    }
+
+  return 1;
+}
+
+/* Implementation of TC_VALIDATE_FIX.
+   Called before md_apply_fix() and after md_convert_frag().  */
+void
+score_validate_fix (fixS *fixP)
+{
+  fixP->fx_where += fixP->fx_frag->insn_addr;
+}
+
+long
+md_pcrel_from (fixS * fixP)
+{
+  long retval = 0;
+
+  if (fixP->fx_addsy
+      && (S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
+      && (fixP->fx_subsy == NULL))
+    {
+      retval = 0;
+    }
+  else
+    {
+      retval = fixP->fx_where + fixP->fx_frag->fr_address;
+    }
+
+  return retval;
+}
+
+int
+score_force_relocation (struct fix *fixp)
+{
+  int retval = 0;
+
+  if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+      || fixp->fx_r_type == BFD_RELOC_SCORE_JMP
+      || fixp->fx_r_type == BFD_RELOC_SCORE_BRANCH
+      || fixp->fx_r_type == BFD_RELOC_SCORE16_JMP
+      || fixp->fx_r_type == BFD_RELOC_SCORE16_BRANCH)
+    {
+      retval = 1;
+    }
+
+  return retval;
+}
+
+/* Round up a section size to the appropriate boundary.  */
+valueT
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  offsetT value = *valP;
+  offsetT abs_value = 0;
+  offsetT newval;
+  offsetT content;
+  unsigned short HI, LO;
+
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
+  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
+    {
+      if (fixP->fx_r_type != BFD_RELOC_SCORE_DUMMY_HI16)
+        fixP->fx_done = 1;
+    }
+
+  /* If this symbol is in a different section then we need to leave it for
+     the linker to deal with.  Unfortunately, md_pcrel_from can't tell,
+     so we have to undo it's effects here.  */
+  if (fixP->fx_pcrel)
+    {
+      if (fixP->fx_addsy != NULL
+	  && S_IS_DEFINED (fixP->fx_addsy)
+	  && S_GET_SEGMENT (fixP->fx_addsy) != seg)
+	value += md_pcrel_from (fixP);
+    }
+
+  /* Remember value for emit_reloc.  */
+  fixP->fx_addnumber = value;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_HI16_S:
+      if (fixP->fx_done)
+        {                       /* For la rd, imm32.  */
+          newval = md_chars_to_number (buf, INSN_SIZE);
+          HI = (value) >> 16;   /* mul to 2, then take the hi 16 bit.  */
+          newval |= (HI & 0x3fff) << 1;
+          newval |= ((HI >> 14) & 0x3) << 16;
+          md_number_to_chars (buf, newval, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_LO16:
+      if (fixP->fx_done)        /* For la rd, imm32.  */
+        {
+          newval = md_chars_to_number (buf, INSN_SIZE);
+          LO = (value) & 0xffff;
+          newval |= (LO & 0x3fff) << 1; /* 16 bit: imm -> 14 bit in lo, 2 bit in hi.  */
+          newval |= ((LO >> 14) & 0x3) << 16;
+          md_number_to_chars (buf, newval, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_SCORE_JMP:
+      {
+        content = md_chars_to_number (buf, INSN_SIZE);
+        value = fixP->fx_offset;
+        content = (content & ~0x3ff7ffe) | ((value << 1) & 0x3ff0000) | (value & 0x7fff);
+        md_number_to_chars (buf, content, INSN_SIZE);
+      }
+      break;
+    case BFD_RELOC_SCORE_BRANCH:
+      if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) || (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+        value = fixP->fx_offset;
+      else
+        fixP->fx_done = 1;
+
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0x80008000) != 0x80008000))
+        {
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xffffff00) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^8 ~ 2^8]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN16_SIZE);
+          content &= 0xff00;
+          content = (content & 0xff00) | ((value >> 1) & 0xff);
+          md_number_to_chars (buf, content, INSN16_SIZE);
+          fixP->fx_r_type = BFD_RELOC_SCORE16_BRANCH;
+          fixP->fx_size = 2;
+        }
+      else
+        {
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xfff80000) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN_SIZE);
+          content &= 0xfc00fc01;
+          content = (content & 0xfc00fc01) | (value & 0x3fe) | ((value << 6) & 0x3ff0000);
+          md_number_to_chars (buf, content, INSN_SIZE);
+        }
+      break;
+    case BFD_RELOC_SCORE16_JMP:
+      content = md_chars_to_number (buf, INSN16_SIZE);
+      content &= 0xf001;
+      value = fixP->fx_offset & 0xfff;
+      content = (content & 0xfc01) | (value & 0xffe);
+      md_number_to_chars (buf, content, INSN16_SIZE);
+      break;
+    case BFD_RELOC_SCORE16_BRANCH:
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0x80008000) == 0x80008000))
+        {
+          if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) ||
+              (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+            value = fixP->fx_offset;
+          else
+            fixP->fx_done = 1;
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xfff80000) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN_SIZE);
+          content = (content & 0xfc00fc01) | (value & 0x3fe) | ((value << 6) & 0x3ff0000);
+          md_number_to_chars (buf, content, INSN_SIZE);
+          fixP->fx_r_type = BFD_RELOC_SCORE_BRANCH;
+          fixP->fx_size = 4;
+          break;
+        }
+      else
+        {
+          /* In differnt section.  */
+          if ((S_GET_SEGMENT (fixP->fx_addsy) != seg) ||
+              (fixP->fx_addsy != NULL && S_IS_EXTERNAL (fixP->fx_addsy)))
+            value = fixP->fx_offset;
+          else
+            fixP->fx_done = 1;
+
+          if ((value & 0x80000000) == 0x80000000)
+            abs_value = 0xffffffff - value + 1;
+          if ((abs_value & 0xffffff00) != 0)
+            {
+              as_bad_where (fixP->fx_file, fixP->fx_line,
+                            _(" branch relocation truncate (0x%x)  [-2^8 ~ 2^8]"), (unsigned int)value);
+              return;
+            }
+          content = md_chars_to_number (buf, INSN16_SIZE);
+          content = (content & 0xff00) | ((value >> 1) & 0xff);
+          md_number_to_chars (buf, content, INSN16_SIZE);
+          break;
+        }
+    case BFD_RELOC_8:
+      if (fixP->fx_done || fixP->fx_pcrel)
+	md_number_to_chars (buf, value, 1);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 1);
+        }
+#endif
+      break;
+
+    case BFD_RELOC_16:
+      if (fixP->fx_done || fixP->fx_pcrel)
+        md_number_to_chars (buf, value, 2);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 2);
+        }
+#endif
+      break;
+    case BFD_RELOC_RVA:
+    case BFD_RELOC_32:
+      if (fixP->fx_done || fixP->fx_pcrel)
+        md_number_to_chars (buf, value, 4);
+#ifdef OBJ_ELF
+      else
+        {
+          value = fixP->fx_offset;
+          md_number_to_chars (buf, value, 4);
+        }
+#endif
+      break;
+    case BFD_RELOC_VTABLE_INHERIT:
+      fixP->fx_done = 0;
+      if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy) && !S_IS_WEAK (fixP->fx_addsy))
+        S_SET_WEAK (fixP->fx_addsy);
+      break;
+    case BFD_RELOC_VTABLE_ENTRY:
+      fixP->fx_done = 0;
+      break;
+    case BFD_RELOC_SCORE_GPREL15:
+      content = md_chars_to_number (buf, INSN_SIZE);
+      if ((fixP->fx_frag->fr_opcode != 0) && ((content & 0xfc1c8000) != 0x94188000))
+        fixP->fx_r_type = BFD_RELOC_NONE;
+      fixP->fx_done = 0;
+      break;
+    case BFD_RELOC_SCORE_GOT15:
+    case BFD_RELOC_SCORE_DUMMY_HI16:
+    case BFD_RELOC_SCORE_GOT_LO16:
+    case BFD_RELOC_SCORE_CALL15:
+    case BFD_RELOC_GPREL32:
+      break;
+    case BFD_RELOC_NONE:
+    default:
+      as_bad_where (fixP->fx_file, fixP->fx_line, _("bad relocation fixup type (%d)"), fixP->fx_r_type);
+    }
+}
+
+/* Translate internal representation of relocation info to BFD target format.  */
+arelent **
+tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+{
+  static arelent *retval[MAX_RELOC_EXPANSION + 1];  /* MAX_RELOC_EXPANSION equals 2.  */
+  arelent *reloc;
+  bfd_reloc_code_real_type code;
+  char *type;
+  fragS *f;
+  symbolS *s;
+  expressionS e;
+
+  reloc = retval[0] = xmalloc (sizeof (arelent));
+  retval[1] = NULL;
+
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->addend = fixp->fx_offset;
+
+  /* If this is a variant frag, we may need to adjust the existing
+     reloc and generate a new one.  */
+  if (fixp->fx_frag->fr_opcode != NULL && (fixp->fx_r_type == BFD_RELOC_SCORE_GPREL15))
+    {
+      /* Update instruction imm bit.  */
+      offsetT newval;
+      unsigned short off;
+      char *buf;
+
+      buf = fixp->fx_frag->fr_literal + fixp->fx_frag->insn_addr;
+      newval = md_chars_to_number (buf, INSN_SIZE);
+      off = fixp->fx_offset >> 16;
+      newval |= (off & 0x3fff) << 1;
+      newval |= ((off >> 14) & 0x3) << 16;
+      md_number_to_chars (buf, newval, INSN_SIZE);
+
+      buf += INSN_SIZE;
+      newval = md_chars_to_number (buf, INSN_SIZE);
+      off = fixp->fx_offset & 0xffff;
+      newval |= ((off & 0x3fff) << 1);
+      newval |= (((off >> 14) & 0x3) << 16);
+      md_number_to_chars (buf, newval, INSN_SIZE);
+
+      retval[1] = xmalloc (sizeof (arelent));
+      retval[2] = NULL;
+      retval[1]->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+      *retval[1]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+      retval[1]->address = (reloc->address + RELAX_RELOC2 (fixp->fx_frag->fr_subtype));
+
+      f = fixp->fx_frag;
+      s = f->fr_symbol;
+      e = s->sy_value;
+
+      retval[1]->addend = 0;
+      retval[1]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
+      assert (retval[1]->howto != NULL);
+
+      fixp->fx_r_type = BFD_RELOC_HI16_S;
+    }
+
+  code = fixp->fx_r_type;
+  switch (fixp->fx_r_type)
+    {
+    case BFD_RELOC_32:
+      if (fixp->fx_pcrel)
+        {
+          code = BFD_RELOC_32_PCREL;
+          break;
+        }
+    case BFD_RELOC_HI16_S:
+    case BFD_RELOC_LO16:
+    case BFD_RELOC_SCORE_JMP:
+    case BFD_RELOC_SCORE_BRANCH:
+    case BFD_RELOC_SCORE16_JMP:
+    case BFD_RELOC_SCORE16_BRANCH:
+    case BFD_RELOC_VTABLE_ENTRY:
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_SCORE_GPREL15:
+    case BFD_RELOC_SCORE_GOT15:
+    case BFD_RELOC_SCORE_DUMMY_HI16:
+    case BFD_RELOC_SCORE_GOT_LO16:
+    case BFD_RELOC_SCORE_CALL15:
+    case BFD_RELOC_GPREL32:
+    case BFD_RELOC_NONE:
+      code = fixp->fx_r_type;
+      break;
+    default:
+      type = _("<unknown>");
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+                    _("cannot represent %s relocation in this object file format"), type);
+      return NULL;
+    }
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+                    _("cannot represent %s relocation in this object file format1"),
+                    bfd_get_reloc_code_name (code));
+      return NULL;
+    }
+  /* HACK: Since arm ELF uses Rel instead of Rela, encode the
+     vtable entry to be used in the relocation's section offset.  */
+  if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    reloc->address = fixp->fx_offset;
+
+  return retval;
+}
+
+void
+score_elf_final_processing (void)
+{
+  if (fix_data_dependency == 1)
+    {
+      elf_elfheader (stdoutput)->e_flags |= EF_SCORE_FIXDEP;
+    }
+  if (score_pic == PIC)
+    {
+      elf_elfheader (stdoutput)->e_flags |= EF_SCORE_PIC;
+    }
+}
+
+static void
+parse_pce_inst (char *insnstr)
+{
+  char c;
+  char *p;
+  char first[MAX_LITERAL_POOL_SIZE];
+  char second[MAX_LITERAL_POOL_SIZE];
+  struct score_it pec_part_1;
+
+  /* Get first part string of PCE.  */
+  p = strstr (insnstr, "||");
+  c = *p;
+  *p = '\0';
+  sprintf (first, "%s", insnstr);
+
+  /* Get second part string of PCE.  */
+  *p = c;
+  p += 2;
+  sprintf (second, "%s", p);
+
+  parse_16_32_inst (first, FALSE);
+  if (inst.error)
+    return;
+
+  memcpy (&pec_part_1, &inst, sizeof (inst));
+
+  parse_16_32_inst (second, FALSE);
+  if (inst.error)
+    return;
+
+  if (   ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN_SIZE))
+      || ((pec_part_1.size == INSN_SIZE) && (inst.size == INSN16_SIZE))
+      || ((pec_part_1.size == INSN16_SIZE) && (inst.size == INSN_SIZE)))
+    {
+      inst.error = _("pce instruction error (16 bit || 16 bit)'");
+      sprintf (inst.str, insnstr);
+      return;
+    }
+
+  if (!inst.error)
+    gen_insn_frag (&pec_part_1, &inst);
+}
+
+void
+md_assemble (char *str)
+{
+  know (str);
+  know (strlen (str) < MAX_LITERAL_POOL_SIZE);
+
+  memset (&inst, '\0', sizeof (inst));
+  if (INSN_IS_PCE_P (str))
+    parse_pce_inst (str);
+  else
+    parse_16_32_inst (str, TRUE);
+
+  if (inst.error)
+    as_bad (_("%s -- `%s'"), inst.error, inst.str);
+}
+
+/* We handle all bad expressions here, so that we can report the faulty
+   instruction in the error message.  */
+void
+md_operand (expressionS * expr)
+{
+  if (in_my_get_expression)
+    {
+      expr->X_op = O_illegal;
+      if (inst.error == NULL)
+        {
+          inst.error = _("bad expression");
+        }
+    }
+}
+
+const char *md_shortopts = "nO::g::G:";
+
+#ifdef SCORE_BI_ENDIAN
+#define OPTION_EB             (OPTION_MD_BASE + 0)
+#define OPTION_EL             (OPTION_MD_BASE + 1)
+#else
+#if TARGET_BYTES_BIG_ENDIAN
+#define OPTION_EB             (OPTION_MD_BASE + 0)
+#else
+#define OPTION_EL             (OPTION_MD_BASE + 1)
+#endif
+#endif
+#define OPTION_FIXDD          (OPTION_MD_BASE + 2)
+#define OPTION_NWARN          (OPTION_MD_BASE + 3)
+#define OPTION_SCORE5         (OPTION_MD_BASE + 4)
+#define OPTION_SCORE5U        (OPTION_MD_BASE + 5)
+#define OPTION_SCORE7         (OPTION_MD_BASE + 6)
+#define OPTION_R1             (OPTION_MD_BASE + 7)
+#define OPTION_O0             (OPTION_MD_BASE + 8)
+#define OPTION_SCORE_VERSION  (OPTION_MD_BASE + 9)
+#define OPTION_PIC            (OPTION_MD_BASE + 10)
+
+struct option md_longopts[] =
+{
+#ifdef OPTION_EB
+  {"EB"     , no_argument, NULL, OPTION_EB},
+#endif
+#ifdef OPTION_EL
+  {"EL"     , no_argument, NULL, OPTION_EL},
+#endif
+  {"FIXDD"  , no_argument, NULL, OPTION_FIXDD},
+  {"NWARN"  , no_argument, NULL, OPTION_NWARN},
+  {"SCORE5" , no_argument, NULL, OPTION_SCORE5},
+  {"SCORE5U", no_argument, NULL, OPTION_SCORE5U},
+  {"SCORE7" , no_argument, NULL, OPTION_SCORE7},
+  {"USE_R1" , no_argument, NULL, OPTION_R1},
+  {"O0"     , no_argument, NULL, OPTION_O0},
+  {"V"      , no_argument, NULL, OPTION_SCORE_VERSION},
+  {"KPIC"   , no_argument, NULL, OPTION_PIC},
+  {NULL     , no_argument, NULL, 0}
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+int
+md_parse_option (int c, char *arg)
+{
+  switch (c)
+    {
+#ifdef OPTION_EB
+    case OPTION_EB:
+      target_big_endian = 1;
+      break;
+#endif
+#ifdef OPTION_EL
+    case OPTION_EL:
+      target_big_endian = 0;
+      break;
+#endif
+    case OPTION_FIXDD:
+      fix_data_dependency = 1;
+      break;
+    case OPTION_NWARN:
+      warn_fix_data_dependency = 0;
+      break;
+    case OPTION_SCORE5:
+      score7 = 0;
+      university_version = 0;
+      vector_size = SCORE5_PIPELINE;
+      break;
+    case OPTION_SCORE5U:
+      score7 = 0;
+      university_version = 1;
+      vector_size = SCORE5_PIPELINE;
+      break;
+    case OPTION_SCORE7:
+      score7 = 1;
+      university_version = 0;
+      vector_size = SCORE7_PIPELINE;
+      break;
+    case OPTION_R1:
+      nor1 = 0;
+      break;
+    case 'G':
+      g_switch_value = atoi (arg);
+      break;
+    case OPTION_O0:
+      g_opt = 0;
+      break;
+    case OPTION_SCORE_VERSION:
+      printf (_("Sunplus-v2-0-0-20060510\n"));
+      break;
+    case OPTION_PIC:
+      score_pic = PIC;
+      g_switch_value = 0;    /* Must set -G num as 0 to generate PIC code.  */
+      break;
+    default:
+      /* as_bad (_("unrecognized option `-%c%s'"), c, arg ? arg : "");  */
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE * fp)
+{
+  fprintf (fp, _(" Score-specific assembler options:\n"));
+#ifdef OPTION_EB
+  fprintf (fp, _("\
+        -EB\t\tassemble code for a big-endian cpu\n"));
+#endif
+
+#ifdef OPTION_EL
+  fprintf (fp, _("\
+        -EL\t\tassemble code for a little-endian cpu\n"));
+#endif
+
+  fprintf (fp, _("\
+        -FIXDD\t\tassemble code for fix data dependency\n"));
+  fprintf (fp, _("\
+        -NWARN\t\tassemble code for no warning message for fix data dependency\n"));
+  fprintf (fp, _("\
+        -SCORE5\t\tassemble code for target is SCORE5\n"));
+  fprintf (fp, _("\
+        -SCORE5U\tassemble code for target is SCORE5U\n"));
+  fprintf (fp, _("\
+        -SCORE7\t\tassemble code for target is SCORE7, this is default setting\n"));
+  fprintf (fp, _("\
+        -USE_R1\t\tassemble code for no warning message when using temp register r1\n"));
+  fprintf (fp, _("\
+        -KPIC\t\tassemble code for PIC\n"));
+  fprintf (fp, _("\
+        -O0\t\tassembler will not perform any optimizations\n"));
+  fprintf (fp, _("\
+        -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"));
+  fprintf (fp, _("\
+        -V \t\tSunplus release version \n"));
+}
+
+
+/* Pesudo handling functions.  */
+
+/* If we change section we must dump the literal pool first.  */
+static void
+s_score_bss (int ignore ATTRIBUTE_UNUSED)
+{
+  subseg_set (bss_section, (subsegT) get_absolute_expression ());
+  demand_empty_rest_of_line ();
+}
+
+static void
+s_score_text (int ignore)
+{
+  obj_elf_text (ignore);
+  record_alignment (now_seg, 2);
+}
+
+static void
+score_s_section (int ignore)
+{
+  obj_elf_section (ignore);
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    record_alignment (now_seg, 2);
+
+}
+
+static void
+s_change_sec (int sec)
+{
+  segT seg;
+
+#ifdef OBJ_ELF
+  /* The ELF backend needs to know that we are changing sections, so
+     that .previous works correctly.  We could do something like check
+     for an obj_section_change_hook macro, but that might be confusing
+     as it would not be appropriate to use it in the section changing
+     functions in read.c, since obj-elf.c intercepts those.  FIXME:
+     This should be cleaner, somehow.  */
+  obj_elf_section_change_hook ();
+#endif
+  switch (sec)
+    {
+    case 'r':
+      seg = subseg_new (RDATA_SECTION_NAME, (subsegT) get_absolute_expression ());
+      bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_RELOC | SEC_DATA));
+      if (strcmp (TARGET_OS, "elf") != 0)
+        record_alignment (seg, 4);
+      demand_empty_rest_of_line ();
+      break;
+    case 's':
+      seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
+      bfd_set_section_flags (stdoutput, seg, SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
+      if (strcmp (TARGET_OS, "elf") != 0)
+        record_alignment (seg, 4);
+      demand_empty_rest_of_line ();
+      break;
+    }
+}
+
+static void
+s_score_mask (int reg_type ATTRIBUTE_UNUSED)
+{
+  long mask, off;
+
+  if (cur_proc_ptr == (procS *) NULL)
+    {
+      as_warn (_(".mask outside of .ent"));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  if (get_absolute_expression_and_terminator (&mask) != ',')
+    {
+      as_warn (_("Bad .mask directive"));
+      --input_line_pointer;
+      demand_empty_rest_of_line ();
+      return;
+    }
+  off = get_absolute_expression ();
+  cur_proc_ptr->reg_mask = mask;
+  cur_proc_ptr->reg_offset = off;
+  demand_empty_rest_of_line ();
+}
+
+static symbolS *
+get_symbol (void)
+{
+  int c;
+  char *name;
+  symbolS *p;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = (symbolS *) symbol_find_or_make (name);
+  *input_line_pointer = c;
+  return p;
+}
+
+static long
+get_number (void)
+{
+  int negative = 0;
+  long val = 0;
+
+  if (*input_line_pointer == '-')
+    {
+      ++input_line_pointer;
+      negative = 1;
+    }
+  if (!ISDIGIT (*input_line_pointer))
+    as_bad (_("expected simple number"));
+  if (input_line_pointer[0] == '0')
+    {
+      if (input_line_pointer[1] == 'x')
+        {
+          input_line_pointer += 2;
+          while (ISXDIGIT (*input_line_pointer))
+            {
+              val <<= 4;
+              val |= hex_value (*input_line_pointer++);
+            }
+          return negative ? -val : val;
+        }
+      else
+        {
+          ++input_line_pointer;
+          while (ISDIGIT (*input_line_pointer))
+            {
+              val <<= 3;
+              val |= *input_line_pointer++ - '0';
+            }
+          return negative ? -val : val;
+        }
+    }
+  if (!ISDIGIT (*input_line_pointer))
+    {
+      printf (_(" *input_line_pointer == '%c' 0x%02x\n"), *input_line_pointer, *input_line_pointer);
+      as_warn (_("invalid number"));
+      return -1;
+    }
+  while (ISDIGIT (*input_line_pointer))
+    {
+      val *= 10;
+      val += *input_line_pointer++ - '0';
+    }
+  return negative ? -val : val;
+}
+
+/* The .aent and .ent directives.  */
+
+static void
+s_score_ent (int aent)
+{
+  symbolS *symbolP;
+  int maybe_text;
+
+  symbolP = get_symbol ();
+  if (*input_line_pointer == ',')
+    ++input_line_pointer;
+  SKIP_WHITESPACE ();
+  if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
+    get_number ();
+
+#ifdef BFD_ASSEMBLER
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#else
+  if (now_seg != data_section && now_seg != bss_section)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#endif
+  if (!maybe_text)
+    as_warn (_(".ent or .aent not in text section."));
+  if (!aent && cur_proc_ptr)
+    as_warn (_("missing .end"));
+  if (!aent)
+    {
+      cur_proc_ptr = &cur_proc;
+      cur_proc_ptr->reg_mask = 0xdeadbeaf;
+      cur_proc_ptr->reg_offset = 0xdeadbeaf;
+      cur_proc_ptr->fpreg_mask = 0xdeafbeaf;
+      cur_proc_ptr->leaf = 0xdeafbeaf;
+      cur_proc_ptr->frame_offset = 0xdeafbeaf;
+      cur_proc_ptr->frame_reg = 0xdeafbeaf;
+      cur_proc_ptr->pc_reg = 0xdeafbeaf;
+      cur_proc_ptr->isym = symbolP;
+      symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
+      ++numprocs;
+      if (debug_type == DEBUG_STABS)
+        stabs_generate_asm_func (S_GET_NAME (symbolP), S_GET_NAME (symbolP));
+    }
+  demand_empty_rest_of_line ();
+}
+
+static void
+s_score_frame (int ignore ATTRIBUTE_UNUSED)
+{
+  char *backupstr;
+  char str[30];
+  long val;
+  int i = 0;
+
+  backupstr = input_line_pointer;
+
+#ifdef OBJ_ELF
+  if (cur_proc_ptr == (procS *) NULL)
+    {
+      as_warn (_(".frame outside of .ent"));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  cur_proc_ptr->frame_reg = reg_required_here ((&backupstr), 0, REG_TYPE_SCORE);
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  while (*backupstr != ',')
+    {
+      str[i] = *backupstr;
+      i++;
+      backupstr++;
+    }
+  str[i] = '\0';
+  val = atoi (str);
+
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  cur_proc_ptr->frame_offset = val;
+  cur_proc_ptr->pc_reg = reg_required_here ((&backupstr), 0, REG_TYPE_SCORE);
+
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+  i = 0;
+  while (*backupstr != '\n')
+    {
+      str[i] = *backupstr;
+      i++;
+      backupstr++;
+    }
+  str[i] = '\0';
+  val = atoi (str);
+  cur_proc_ptr->leaf = val;
+  SKIP_WHITESPACE ();
+  skip_past_comma (&backupstr);
+
+#endif /* OBJ_ELF */
+  while (input_line_pointer != backupstr)
+    input_line_pointer++;
+}
+
+/* The .end directive.  */
+static void
+s_score_end (int x ATTRIBUTE_UNUSED)
+{
+  symbolS *p;
+  int maybe_text;
+
+  /* Generate a .pdr section.  */
+  segT saved_seg = now_seg;
+  subsegT saved_subseg = now_subseg;
+  valueT dot;
+  expressionS exp;
+  char *fragp;
+
+  if (!is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      p = get_symbol ();
+      demand_empty_rest_of_line ();
+    }
+  else
+    p = NULL;
+
+#ifdef BFD_ASSEMBLER
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#else
+  if (now_seg != data_section && now_seg != bss_section)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+#endif
+
+  if (!maybe_text)
+    as_warn (_(".end not in text section"));
+  if (!cur_proc_ptr)
+    {
+      as_warn (_(".end directive without a preceding .ent directive."));
+      demand_empty_rest_of_line ();
+      return;
+    }
+  if (p != NULL)
+    {
+      assert (S_GET_NAME (p));
+      if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
+        as_warn (_(".end symbol does not match .ent symbol."));
+      if (debug_type == DEBUG_STABS)
+        stabs_generate_asm_endfunc (S_GET_NAME (p), S_GET_NAME (p));
+    }
+  else
+    as_warn (_(".end directive missing or unknown symbol"));
+
+  if ((cur_proc_ptr->reg_mask == 0xdeadbeaf) ||
+      (cur_proc_ptr->reg_offset == 0xdeadbeaf) ||
+      (cur_proc_ptr->leaf == 0xdeafbeaf) ||
+      (cur_proc_ptr->frame_offset == 0xdeafbeaf) ||
+      (cur_proc_ptr->frame_reg == 0xdeafbeaf) || (cur_proc_ptr->pc_reg == 0xdeafbeaf));
+
+  else
+    {
+      dot = frag_now_fix ();
+      assert (pdr_seg);
+      subseg_set (pdr_seg, 0);
+      /* Write the symbol.  */
+      exp.X_op = O_symbol;
+      exp.X_add_symbol = p;
+      exp.X_add_number = 0;
+      emit_expr (&exp, 4);
+      fragp = frag_more (7 * 4);
+      md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
+      md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
+      md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
+      md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->leaf, 4);
+      md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
+      md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
+      md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
+      subseg_set (saved_seg, saved_subseg);
+
+    }
+  cur_proc_ptr = NULL;
+}
+
+/* Handle the .set pseudo-op.  */
+static void
+s_score_set (int x ATTRIBUTE_UNUSED)
+{
+  int i = 0;
+  char name[MAX_LITERAL_POOL_SIZE];
+  char * orig_ilp = input_line_pointer;
+
+  while (!is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      name[i] = (char) * input_line_pointer;
+      i++;
+      ++input_line_pointer;
+    }
+
+  name[i] = '\0';
+
+  if (strcmp (name, "nwarn") == 0)
+    {
+      warn_fix_data_dependency = 0;
+    }
+  else if (strcmp (name, "fixdd") == 0)
+    {
+      fix_data_dependency = 1;
+    }
+  else if (strcmp (name, "nofixdd") == 0)
+    {
+      fix_data_dependency = 0;
+    }
+  else if (strcmp (name, "r1") == 0)
+    {
+      nor1 = 0;
+    }
+  else if (strcmp (name, "nor1") == 0)
+    {
+      nor1 = 1;
+    }
+  else if (strcmp (name, "optimize") == 0)
+    {
+      g_opt = 1;
+    }
+  else if (strcmp (name, "volatile") == 0)
+    {
+      g_opt = 0;
+    }
+  else if (strcmp (name, "pic") == 0)
+    {
+      score_pic = PIC;
+    }
+  else
+    {
+      input_line_pointer = orig_ilp;
+      s_set (0);
+    }
+}
+
+/* Handle the .cpload pseudo-op.  This is used when generating PIC code.  It sets the
+   $gp register for the function based on the function address, which is in the register
+   named in the argument. This uses a relocation against GP_DISP_LABEL, which is handled
+   specially by the linker.  The result is:
+   ldis gp, %hi(GP_DISP_LABEL)
+   ori  gp, %low(GP_DISP_LABEL)
+   add  gp, gp, .cpload argument
+   The .cpload argument is normally r29.  */
+
+static void
+s_score_cpload (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cpload is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    return;
+
+  demand_empty_rest_of_line ();
+
+  sprintf (insn_str, "ld_i32hi r%d, %s", GP, GP_DISP_LABEL);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+
+  sprintf (insn_str, "ld_i32lo r%d, %s", GP, GP_DISP_LABEL);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+
+  sprintf (insn_str, "add r%d, r%d, r%d", GP, GP, reg);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+}
+
+/* Handle the .cprestore pseudo-op.  This stores $gp into a given
+   offset from $sp.  The offset is remembered, and after making a PIC
+   call $gp is restored from that location.  */
+
+static void
+s_score_cprestore (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  int cprestore_offset;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cprestore is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL
+      || skip_past_comma (&input_line_pointer) == (int) FAIL)
+    {
+      return;
+    }
+
+  cprestore_offset = get_absolute_expression ();
+
+  if (cprestore_offset <= 0x3fff)
+    {
+      sprintf (insn_str, "sw r%d, [r%d, %d]", GP, reg, cprestore_offset);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+    }
+  else
+    {
+      int r1_bak;
+
+      r1_bak = nor1;
+      nor1 = 0;
+
+      sprintf (insn_str, "li r1, %d", cprestore_offset);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      sprintf (insn_str, "add r1, r1, r%d", reg);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      sprintf (insn_str, "sw r%d, [r1]", GP);
+      if (append_insn (insn_str, TRUE) == (int) FAIL)
+        return;
+
+      nor1 = r1_bak;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+/* Handle the .gpword pseudo-op.  This is used when generating PIC
+   code.  It generates a 32 bit GP relative reloc.  */
+static void
+s_score_gpword (int ignore ATTRIBUTE_UNUSED)
+{
+  expressionS ex;
+  char *p;
+
+  /* When not generating PIC code, this is treated as .word.  */
+  if (score_pic == NO_PIC)
+    {
+      cons (4);
+      return;
+    }
+  expression (&ex);
+  if (ex.X_op != O_symbol || ex.X_add_number != 0)
+    {
+      as_bad (_("Unsupported use of .gpword"));
+      ignore_rest_of_line ();
+    }
+  p = frag_more (4);
+  md_number_to_chars (p, (valueT) 0, 4);
+  fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE, BFD_RELOC_GPREL32);
+  demand_empty_rest_of_line ();
+}
+
+/* Handle the .cpadd pseudo-op.  This is used when dealing with switch
+   tables in PIC code.  */
+
+static void
+s_score_cpadd (int ignore ATTRIBUTE_UNUSED)
+{
+  int reg;
+  char insn_str[MAX_LITERAL_POOL_SIZE];
+
+  /* If we are not generating PIC code, .cpload is ignored.  */
+  if (score_pic == NO_PIC)
+    {
+      s_ignore (0);
+      return;
+    }
+
+  if ((reg = reg_required_here (&input_line_pointer, -1, REG_TYPE_SCORE)) == (int) FAIL)
+    {
+      return;
+    }
+  demand_empty_rest_of_line ();
+
+  /* Add $gp to the register named as an argument.  */
+  sprintf (insn_str, "add r%d, r%d, r%d", reg, reg, GP);
+  if (append_insn (insn_str, TRUE) == (int) FAIL)
+    return;
+}
+
+#ifndef TC_IMPLICIT_LCOMM_ALIGNMENT
+#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)        	\
+    do								\
+    {                                                   	\
+    if ((SIZE) >= 8)                                      	\
+    (P2VAR) = 3;                                        	\
+    else if ((SIZE) >= 4)                                 	\
+    (P2VAR) = 2;                                        	\
+    else if ((SIZE) >= 2)                                 	\
+    (P2VAR) = 1;                                        	\
+    else                                                  	\
+    (P2VAR) = 0;                                        	\
+    }								\
+  while (0)
+#endif
+
+static void
+s_score_lcomm (int bytes_p)
+{
+  char *name;
+  char c;
+  char *p;
+  int temp;
+  symbolS *symbolP;
+  segT current_seg = now_seg;
+  subsegT current_subseg = now_subseg;
+  const int max_alignment = 15;
+  int align = 0;
+  segT bss_seg = bss_section;
+  int needs_align = 0;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = input_line_pointer;
+  *p = c;
+
+  if (name == p)
+    {
+      as_bad (_("expected symbol name"));
+      discard_rest_of_line ();
+      return;
+    }
+
+  SKIP_WHITESPACE ();
+
+  /* Accept an optional comma after the name.  The comma used to be
+     required, but Irix 5 cc does not generate it.  */
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+    }
+
+  if (is_end_of_line[(unsigned char)*input_line_pointer])
+    {
+      as_bad (_("missing size expression"));
+      return;
+    }
+
+  if ((temp = get_absolute_expression ()) < 0)
+    {
+      as_warn (_("BSS length (%d) < 0 ignored"), temp);
+      ignore_rest_of_line ();
+      return;
+    }
+
+#if defined (TC_SCORE)
+  if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour || OUTPUT_FLAVOR == bfd_target_elf_flavour)
+    {
+      /* For Score and Alpha ECOFF or ELF, small objects are put in .sbss.  */
+      if ((unsigned)temp <= bfd_get_gp_size (stdoutput))
+        {
+          bss_seg = subseg_new (".sbss", 1);
+          seg_info (bss_seg)->bss = 1;
+#ifdef BFD_ASSEMBLER
+          if (!bfd_set_section_flags (stdoutput, bss_seg, SEC_ALLOC))
+            as_warn (_("error setting flags for \".sbss\": %s"), bfd_errmsg (bfd_get_error ()));
+#endif
+        }
+    }
+#endif
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      SKIP_WHITESPACE ();
+
+      if (is_end_of_line[(unsigned char)*input_line_pointer])
+        {
+          as_bad (_("missing alignment"));
+          return;
+        }
+      else
+        {
+          align = get_absolute_expression ();
+          needs_align = 1;
+        }
+    }
+
+  if (!needs_align)
+    {
+      TC_IMPLICIT_LCOMM_ALIGNMENT (temp, align);
+
+      /* Still zero unless TC_IMPLICIT_LCOMM_ALIGNMENT set it.  */
+      if (align)
+        record_alignment (bss_seg, align);
+    }
+
+  if (needs_align)
+    {
+      if (bytes_p)
+        {
+          /* Convert to a power of 2.  */
+          if (align != 0)
+            {
+              unsigned int i;
+
+              for (i = 0; align != 0; align >>= 1, ++i)
+                ;
+              align = i - 1;
+            }
+        }
+
+      if (align > max_alignment)
+        {
+          align = max_alignment;
+          as_warn (_("alignment too large; %d assumed"), align);
+        }
+      else if (align < 0)
+        {
+          align = 0;
+          as_warn (_("alignment negative; 0 assumed"));
+        }
+
+      record_alignment (bss_seg, align);
+    }
+  else
+    {
+      /* Assume some objects may require alignment on some systems.  */
+#if defined (TC_ALPHA) && ! defined (VMS)
+      if (temp > 1)
+        {
+          align = ffs (temp) - 1;
+          if (temp % (1 << align))
+            abort ();
+        }
+#endif
+    }
+
+  *p = 0;
+  symbolP = symbol_find_or_make (name);
+  *p = c;
+
+  if (
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT) \
+     || defined (OBJ_BOUT) || defined (OBJ_MAYBE_BOUT))
+#ifdef BFD_ASSEMBLER
+       (OUTPUT_FLAVOR != bfd_target_aout_flavour
+        || (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0)) &&
+#else
+       (S_GET_OTHER (symbolP) == 0 && S_GET_DESC (symbolP) == 0) &&
+#endif
+#endif
+       (S_GET_SEGMENT (symbolP) == bss_seg || (!S_IS_DEFINED (symbolP) && S_GET_VALUE (symbolP) == 0)))
+    {
+      char *pfrag;
+
+      subseg_set (bss_seg, 1);
+
+      if (align)
+        frag_align (align, 0, 0);
+
+      /* Detach from old frag.  */
+      if (S_GET_SEGMENT (symbolP) == bss_seg)
+        symbol_get_frag (symbolP)->fr_symbol = NULL;
+
+      symbol_set_frag (symbolP, frag_now);
+      pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, (offsetT) temp, NULL);
+      *pfrag = 0;
+
+
+      S_SET_SEGMENT (symbolP, bss_seg);
+
+#ifdef OBJ_COFF
+      /* The symbol may already have been created with a preceding
+         ".globl" directive -- be careful not to step on storage class
+         in that case.  Otherwise, set it to static.  */
+      if (S_GET_STORAGE_CLASS (symbolP) != C_EXT)
+        {
+          S_SET_STORAGE_CLASS (symbolP, C_STAT);
+        }
+#endif /* OBJ_COFF */
+
+#ifdef S_SET_SIZE
+      S_SET_SIZE (symbolP, temp);
+#endif
+    }
+  else
+    as_bad (_("symbol `%s' is already defined"), S_GET_NAME (symbolP));
+
+  subseg_set (current_seg, current_subseg);
+
+  demand_empty_rest_of_line ();
+}
+
+static void
+insert_reg (const struct reg_entry *r, struct hash_control *htab)
+{
+  int i = 0;
+  int len = strlen (r->name) + 2;
+  char *buf = xmalloc (len);
+  char *buf2 = xmalloc (len);
+
+  strcpy (buf + i, r->name);
+  for (i = 0; buf[i]; i++)
+    {
+      buf2[i] = TOUPPER (buf[i]);
+    }
+  buf2[i] = '\0';
+
+  hash_insert (htab, buf, (void *) r);
+  hash_insert (htab, buf2, (void *) r);
+}
+
+static void
+build_reg_hsh (struct reg_map *map)
+{
+  const struct reg_entry *r;
+
+  if ((map->htab = hash_new ()) == NULL)
+    {
+      as_fatal (_("virtual memory exhausted"));
+    }
+  for (r = map->names; r->name != NULL; r++)
+    {
+      insert_reg (r, map->htab);
+    }
+}
+
+void
+md_begin (void)
+{
+  unsigned int i;
+  segT seg;
+  subsegT subseg;
+
+  if ((score_ops_hsh = hash_new ()) == NULL)
+    as_fatal (_("virtual memory exhausted"));
+
+  build_score_ops_hsh ();
+
+  if ((dependency_insn_hsh = hash_new ()) == NULL)
+    as_fatal (_("virtual memory exhausted"));
+
+  build_dependency_insn_hsh ();
+
+  for (i = (int)REG_TYPE_FIRST; i < (int)REG_TYPE_MAX; i++)
+    build_reg_hsh (all_reg_maps + i);
+
+  /* Initialize dependency vector.  */
+  init_dependency_vector ();
+
+  bfd_set_arch_mach (stdoutput, TARGET_ARCH, 0);
+  seg = now_seg;
+  subseg = now_subseg;
+  pdr_seg = subseg_new (".pdr", (subsegT) 0);
+  (void)bfd_set_section_flags (stdoutput, pdr_seg, SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
+  (void)bfd_set_section_alignment (stdoutput, pdr_seg, 2);
+  subseg_set (seg, subseg);
+
+  if (USE_GLOBAL_POINTER_OPT)
+    bfd_set_gp_size (stdoutput, g_switch_value);
+}
+
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"bss", s_score_bss, 0},
+  {"text", s_score_text, 0},
+  {"word", cons, 4},
+  {"long", cons, 4},
+  {"extend", float_cons, 'x'},
+  {"ldouble", float_cons, 'x'},
+  {"packed", float_cons, 'p'},
+  {"end", s_score_end, 0},
+  {"ent", s_score_ent, 0},
+  {"frame", s_score_frame, 0},
+  {"rdata", s_change_sec, 'r'},
+  {"sdata", s_change_sec, 's'},
+  {"set", s_score_set, 0},
+  {"mask", s_score_mask, 'R'},
+  {"dword", cons, 8},
+  {"lcomm", s_score_lcomm, 1},
+  {"section", score_s_section, 0},
+  {"cpload", s_score_cpload, 0},
+  {"cprestore", s_score_cprestore, 0},
+  {"gpword", s_score_gpword, 0},
+  {"cpadd", s_score_cpadd, 0},
+  {0, 0, 0}
+};
+
diff --git a/gas/config/tc-score.h b/gas/config/tc-score.h
new file mode 100644
index 000000000000..2cd403956884
--- /dev/null
+++ b/gas/config/tc-score.h
@@ -0,0 +1,83 @@
+/* tc-score.h -- Score specific file for assembler
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by: 
+   Mei Ligang (ligang@sunnorth.com.cn)
+   Pei-Lin Tsai (pltsai@sunplus.com)
+ 
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_SCORE
+#define TC_SCORE
+
+#define TARGET_ARCH 	            bfd_arch_score
+#define WORKING_DOT_WORD
+#define DIFF_EXPR_OK
+#define RELOC_EXPANSION_POSSIBLE
+#define MAX_RELOC_EXPANSION         2
+#define MAX_MEM_FOR_RS_ALIGN_CODE  (3 + 4)
+
+#define md_undefined_symbol(name)  NULL
+
+#define TARGET_FORMAT  (target_big_endian ? "elf32-bigscore" : "elf32-littlescore")
+
+#define md_relax_frag(segment, fragp, stretch)  score_relax_frag (segment, fragp, stretch)
+extern int score_relax_frag (asection *, struct frag *, long);
+
+#define md_frag_check(fragp)  score_frag_check (fragp)
+extern void score_frag_check (fragS *);
+
+#define TC_VALIDATE_FIX(FIXP, SEGTYPE, SKIP)  score_validate_fix (FIXP)
+extern void score_validate_fix (struct fix *);
+
+#define TC_FORCE_RELOCATION(FIXP)  score_force_relocation (FIXP)
+extern int score_force_relocation (struct fix *);
+
+#define tc_fix_adjustable(fixp)  score_fix_adjustable (fixp)
+extern bfd_boolean score_fix_adjustable (struct fix *);
+
+#define elf_tc_final_processing  score_elf_final_processing
+extern void score_elf_final_processing (void);
+
+struct score_tc_frag_data
+{
+  unsigned int is_insn;
+  struct fix *fixp;
+};
+
+#define TC_FRAG_TYPE struct score_tc_frag_data
+
+#define TC_FRAG_INIT(FRAGP) \
+  do \
+    { \
+      (FRAGP)->tc_frag_data.is_insn = (((FRAGP)->fr_type == rs_machine_dependent) ? 1 : 0); \
+    } \
+  while (0)
+
+#ifdef OBJ_ELF
+#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
+#else
+#define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
+#endif
+
+enum score_pic_level
+{
+  NO_PIC,
+  PIC
+};
+
+#endif /*TC_SCORE */
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index acf62aef21d6..5545e94cbf29 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -1,6 +1,6 @@
 /* tc-sh.c -- Assemble code for the Renesas / SuperH SH
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005  Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -21,9 +21,7 @@
 
 /* Written By Steve Chamberlain <sac@cygnus.com>  */
 
-#include <stdio.h>
 #include "as.h"
-#include "bfd.h"
 #include "subsegs.h"
 #define DEFINE_TABLE
 #include "opcodes/sh-opc.h"
@@ -827,8 +825,97 @@ sh_elf_cons (register int nbytes)
   else
     demand_empty_rest_of_line ();
 }
-#endif /* OBJ_ELF */
 
+/* The regular frag_offset_fixed_p doesn't work for rs_align_test
+   frags.  */
+
+static bfd_boolean
+align_test_frag_offset_fixed_p (const fragS *frag1, const fragS *frag2,
+				bfd_vma *offset)
+{
+  const fragS *frag;
+  bfd_vma off;
+
+  /* Start with offset initialised to difference between the two frags.
+     Prior to assigning frag addresses this will be zero.  */
+  off = frag1->fr_address - frag2->fr_address;
+  if (frag1 == frag2)
+    {
+      *offset = off;
+      return TRUE;
+    }
+
+  /* Maybe frag2 is after frag1.  */
+  frag = frag1;
+  while (frag->fr_type == rs_fill
+	 || frag->fr_type == rs_align_test)
+    {
+      if (frag->fr_type == rs_fill)
+	off += frag->fr_fix + frag->fr_offset * frag->fr_var;
+      else
+	off += frag->fr_fix;
+      frag = frag->fr_next;
+      if (frag == NULL)
+	break;
+      if (frag == frag2)
+	{
+	  *offset = off;
+	  return TRUE;
+	}
+    }
+
+  /* Maybe frag1 is after frag2.  */
+  off = frag1->fr_address - frag2->fr_address;
+  frag = frag2;
+  while (frag->fr_type == rs_fill
+	 || frag->fr_type == rs_align_test)
+    {
+      if (frag->fr_type == rs_fill)
+	off -= frag->fr_fix + frag->fr_offset * frag->fr_var;
+      else
+	off -= frag->fr_fix;
+      frag = frag->fr_next;
+      if (frag == NULL)
+	break;
+      if (frag == frag1)
+	{
+	  *offset = off;
+	  return TRUE;
+	}
+    }
+
+  return FALSE;
+}
+
+/* Optimize a difference of symbols which have rs_align_test frag if
+   possible.  */
+
+int
+sh_optimize_expr (expressionS *l, operatorT op, expressionS *r)
+{
+  bfd_vma frag_off;
+
+  if (op == O_subtract
+      && l->X_op == O_symbol
+      && r->X_op == O_symbol
+      && S_GET_SEGMENT (l->X_add_symbol) == S_GET_SEGMENT (r->X_add_symbol)
+      && (SEG_NORMAL (S_GET_SEGMENT (l->X_add_symbol))
+	  || r->X_add_symbol == l->X_add_symbol)
+      && align_test_frag_offset_fixed_p (symbol_get_frag (l->X_add_symbol),
+					 symbol_get_frag (r->X_add_symbol),
+					 &frag_off))
+    {
+      l->X_add_number -= r->X_add_number;
+      l->X_add_number -= frag_off / OCTETS_PER_BYTE;
+      l->X_add_number += (S_GET_VALUE (l->X_add_symbol)
+			  - S_GET_VALUE (r->X_add_symbol));
+      l->X_op = O_constant;
+      l->X_add_symbol = 0;
+      return 1;
+    }
+  return 0;
+}
+#endif /* OBJ_ELF */
 
 /* This function is called once, at assembler startup time.  This should
    set up all the tables, etc that the MD part of the assembler needs.  */
@@ -2798,7 +2885,7 @@ md_assemble (char *str)
   if (opcode == NULL)
     {
       /* The opcode is not in the hash table.
-	 This means we definately have an assembly failure,
+	 This means we definitely have an assembly failure,
 	 but the instruction may be valid in another CPU variant.
 	 In this case emit something better than 'unknown opcode'.
 	 Search the full table in sh-opc.h to check. */
@@ -2867,6 +2954,9 @@ md_assemble (char *str)
 	    as_bad (_("Delayed branches not available on SH1"));
 	  parse_exp (op_end + 1, &operand[0]);
 	  build_relax (opcode, &operand[0]);
+
+	  /* All branches are currently 16 bit.  */
+	  size = 2;
 	}
       else
 	{
@@ -3065,6 +3155,10 @@ struct option md_longopts[] =
   {"relax", no_argument, NULL, OPTION_RELAX},
   {"big", no_argument, NULL, OPTION_BIG},
   {"little", no_argument, NULL, OPTION_LITTLE},
+  /* The next two switches are here because the
+     generic parts of the linker testsuite uses them.  */
+  {"EB", no_argument, NULL, OPTION_BIG},
+  {"EL", no_argument, NULL, OPTION_LITTLE},
   {"small", no_argument, NULL, OPTION_SMALL},
   {"dsp", no_argument, NULL, OPTION_DSP},
   {"isa", required_argument, NULL, OPTION_ISA},
@@ -3316,6 +3410,21 @@ sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
   for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
     {
       symbolS *sym;
+
+      sym = fix->fx_addsy;
+      /* Check for a local_symbol.  */
+      if (sym && sym->bsym == NULL)
+	{
+	  struct local_symbol *ls = (struct local_symbol *)sym;
+	  /* See if it's been converted.  If so, canonicalize.  */
+	  if (local_symbol_converted_p (ls))
+	    fix->fx_addsy = local_symbol_get_real_symbol (ls);
+	}
+    }
+
+  for (fix = seginfo->fix_root; fix != NULL; fix = fix->fx_next)
+    {
+      symbolS *sym;
       bfd_vma val;
       fixS *fscan;
       struct sh_count_relocs info;
@@ -3666,7 +3775,7 @@ sh_handle_align (fragS *frag)
   else if (frag->fr_type == rs_align_test)
     {
       if (bytes != 0)
-	as_warn_where (frag->fr_file, frag->fr_line, _("misaligned data"));
+	as_bad_where (frag->fr_file, frag->fr_line, _("misaligned data"));
     }
 
   if (sh_relax
@@ -3780,6 +3889,28 @@ sh_elf_final_processing (void)
 }
 #endif
 
+/* Apply fixup FIXP to SIZE-byte field BUF given that VAL is its
+   assembly-time value.  If we're generating a reloc for FIXP,
+   see whether the addend should be stored in-place or whether
+   it should be in an ELF r_addend field.  */
+
+static void
+apply_full_field_fix (fixS *fixP, char *buf, bfd_vma val, int size)
+{
+  reloc_howto_type *howto;
+
+  if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
+    {
+      howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+      if (howto && !howto->partial_inplace)
+	{
+	  fixP->fx_addnumber = val;
+	  return;
+	}
+    }
+  md_number_to_chars (buf, val, size);
+}
+
 /* Apply a fixup to the object file.  */
 
 void
@@ -3980,11 +4111,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
     case BFD_RELOC_32:
     case BFD_RELOC_32_PCREL:
-      md_number_to_chars (buf, val, 4);
+      apply_full_field_fix (fixP, buf, val, 4);
       break;
 
     case BFD_RELOC_16:
-      md_number_to_chars (buf, val, 2);
+      apply_full_field_fix (fixP, buf, val, 2);
       break;
 
     case BFD_RELOC_SH_USES:
@@ -4016,8 +4147,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       val = fixP->fx_offset;
       if (fixP->fx_subsy)
 	val -= S_GET_VALUE (fixP->fx_subsy);
-      fixP->fx_addnumber = val;
-      md_number_to_chars (buf, val, 4);
+      apply_full_field_fix (fixP, buf, val, 4);
       break;
 
     case BFD_RELOC_SH_GOTPC:
@@ -4038,7 +4168,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
          was used to store the correction, but since the expression is
          not pcrel, I felt it would be confusing to do it this way.  */
       * valP -= 1;
-      md_number_to_chars (buf, val, 4);
+      apply_full_field_fix (fixP, buf, val, 4);
       break;
 
     case BFD_RELOC_SH_TLS_GD_32:
@@ -4049,7 +4179,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_32_GOT_PCREL:
     case BFD_RELOC_SH_GOTPLT32:
       * valP = 0; /* Fully resolved at runtime.  No addend.  */
-      md_number_to_chars (buf, 0, 4);
+      apply_full_field_fix (fixP, buf, 0, 4);
       break;
 
     case BFD_RELOC_SH_TLS_LDO_32:
@@ -4057,7 +4187,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       S_SET_THREAD_LOCAL (fixP->fx_addsy);
       /* Fallthrough */
     case BFD_RELOC_32_GOTOFF:
-      md_number_to_chars (buf, val, 4);
+      apply_full_field_fix (fixP, buf, val, 4);
       break;
 #endif
 
@@ -4082,6 +4212,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     }
   if (max != 0 && (val < min || val > max))
     as_bad_where (fixP->fx_file, fixP->fx_line, _("offset out of range"));
+  else if (max != 0)
+    /* Stop the generic code from trying to overlow check the value as well.
+       It may not have the correct value anyway, as we do not store val back
+       into *valP.  */
+    fixP->fx_no_overflow = 1;
 
   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
     fixP->fx_done = 1;
@@ -4255,12 +4390,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
   else if (shmedia_init_reloc (rel, fixp))
     ;
 #endif
-  else if (fixp->fx_pcrel)
-    rel->addend = fixp->fx_addnumber;
-  else if (r_type == BFD_RELOC_32 || r_type == BFD_RELOC_32_GOTOFF)
-    rel->addend = fixp->fx_addnumber;
   else
-    rel->addend = 0;
+    rel->addend = fixp->fx_addnumber;
 
   rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
 
@@ -4382,7 +4513,7 @@ sh_cfi_frame_initial_instructions (void)
 }
 
 int
-sh_regname_to_dw2regnum (const char *regname)
+sh_regname_to_dw2regnum (char *regname)
 {
   unsigned int regnum = -1;
   unsigned int i;
diff --git a/gas/config/tc-sh.h b/gas/config/tc-sh.h
index a812036fcd51..80542f465548 100644
--- a/gas/config/tc-sh.h
+++ b/gas/config/tc-sh.h
@@ -1,6 +1,6 @@
 /* This file is tc-sh.h
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -44,6 +44,14 @@ extern int sh_small;
 #define md_cons_align(nbytes) sh_cons_align (nbytes)
 extern void sh_cons_align (int);
 
+/* We need to optimize expr with taking account of rs_align_test
+   frags.  */
+
+#ifdef OBJ_ELF
+#define md_optimize_expr(l,o,r) sh_optimize_expr (l, o, r)
+extern int sh_optimize_expr (expressionS *, operatorT, expressionS *);
+#endif
+
 /* When relaxing, we need to generate relocations for alignment
    directives.  */
 #define HANDLE_ALIGN(frag) sh_handle_align (frag)
@@ -81,6 +89,11 @@ extern int sh_force_relocation (struct fix *);
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
 extern long md_pcrel_from_section (struct fix *, segT);
 
+/* SH_COUNT relocs are allowed outside of frag.
+   The target is also buggy and sets fix size too large for other relocs.  */
+#define TC_FX_SIZE_SLACK(FIX) \
+  ((FIX)->fx_r_type == BFD_RELOC_SH_COUNT ? -1 : 2)
+
 #define IGNORE_NONSTANDARD_ESCAPES
 
 #define LISTING_HEADER \
@@ -149,6 +162,8 @@ extern int target_big_endian;
 #define TARGET_FORMAT (!target_big_endian ? "elf32-shl-nbsd" : "elf32-sh-nbsd")
 #elif defined TARGET_SYMBIAN
 #define TARGET_FORMAT (!target_big_endian ? "elf32-shl-symbian" : "elf32-sh-symbian")
+#elif defined (TE_VXWORKS)
+#define TARGET_FORMAT (!target_big_endian ? "elf32-shl-vxworks" : "elf32-sh-vxworks")
 #else
 #define TARGET_FORMAT (!target_big_endian ? "elf32-shl" : "elf32-sh")
 #endif
@@ -187,7 +202,6 @@ extern bfd_boolean sh_fix_adjustable (struct fix *);
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL	\
    || (FIX)->fx_r_type == BFD_RELOC_32_GOT_PCREL	\
    || (FIX)->fx_r_type == BFD_RELOC_SH_GOTPC		\
@@ -225,11 +239,11 @@ void sh_cons_fix_new (fragS *, int, int, expressionS *);
 extern void sh_cfi_frame_initial_instructions (void);
 
 #define tc_regname_to_dw2regnum sh_regname_to_dw2regnum
-extern int sh_regname_to_dw2regnum (const char *regname);
+extern int sh_regname_to_dw2regnum (char *regname);
 
 /* All SH instructions are multiples of 16 bits.  */
 #define DWARF2_LINE_MIN_INSN_LENGTH 2
 #define DWARF2_DEFAULT_RETURN_COLUMN 17
-#define DWARF2_CIE_DATA_ALIGNMENT -4
+#define DWARF2_CIE_DATA_ALIGNMENT (-4)
 
 #endif /* OBJ_ELF */
diff --git a/gas/config/tc-sh64.c b/gas/config/tc-sh64.c
index 74330612e43a..a306c1b8ddf2 100644
--- a/gas/config/tc-sh64.c
+++ b/gas/config/tc-sh64.c
@@ -1,5 +1,6 @@
 /* tc-sh64.c -- Assemble code for the SuperH SH SHcompact and SHmedia.
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -25,7 +26,6 @@
 
 #define HAVE_SH64
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "opcodes/sh64-opc.h"
@@ -1533,7 +1533,7 @@ shmedia_check_limits (offsetT *valp, bfd_reloc_code_real_type reloc,
 
     case BFD_RELOC_SH_IMMU16:
       if (val < 0 || val > (1 << 16) - 1)
-	msg = _("invalid operand, not an 16-bit unsigned value: %d");
+	msg = _("invalid operand, not a 16-bit unsigned value: %d");
       break;
 
     case BFD_RELOC_SH_PT_16:
@@ -3035,8 +3035,6 @@ sh64_target_mach (void)
 valueT
 shmedia_md_pcrel_from_section (struct fix *fixP, segT sec ATTRIBUTE_UNUSED)
 {
-  know (fixP->fx_frag->fr_type == rs_machine_dependent);
-
   /* Use the ISA for the instruction to decide which offset to use.  We
      can glean it from the fisup type.  */
   switch (fixP->fx_r_type)
diff --git a/gas/config/tc-sh64.h b/gas/config/tc-sh64.h
index 21f5d59f4c56..f31f7501b00f 100644
--- a/gas/config/tc-sh64.h
+++ b/gas/config/tc-sh64.h
@@ -1,5 +1,6 @@
 /* This file is tc-sh64.h
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -79,7 +80,6 @@ extern int sh64_target_mach (void);
 #undef TC_FORCE_RELOCATION_LOCAL
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
-   || (FIX)->fx_plt					\
    || (FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL	\
    || (FIX)->fx_r_type == BFD_RELOC_SH_PLT_LOW16	\
    || (FIX)->fx_r_type == BFD_RELOC_SH_PLT_MEDLOW16	\
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 10a1411b5260..d4a409fbc345 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -1,6 +1,6 @@
 /* tc-sparc.c -- Assemble for the SPARC
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -19,8 +19,6 @@
    to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
-
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -339,7 +337,7 @@ sparc_target_format ()
 #endif
 
 #ifdef OBJ_ELF
-  return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
+  return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
 #endif
 
   abort ();
@@ -547,12 +545,12 @@ md_parse_option (c, arg)
 	  {
 	    if (sparc_arch_size == 32)
 	      {
-		if (strcmp (*l, "elf32-sparc") == 0)
+		if (CONST_STRNEQ (*l, "elf32-sparc"))
 		  break;
 	      }
 	    else
 	      {
-		if (strcmp (*l, "elf64-sparc") == 0)
+		if (CONST_STRNEQ (*l, "elf64-sparc"))
 		  break;
 	      }
 	  }
@@ -1862,7 +1860,8 @@ sparc_ip (str, pinsn)
 	    case '\0':		/* End of args.  */
 	      if (s[0] == ',' && s[1] == '%')
 		{
-		  static const struct tls_ops {
+		  static const struct tls_ops
+		  {
 		    /* The name as it appears in assembler.  */
 		    char *name;
 		    /* strlen (name), precomputed for speed */
@@ -1871,7 +1870,9 @@ sparc_ip (str, pinsn)
 		    int reloc;
 		    /* 1 if call.  */
 		    int call;
-		  } tls_ops[] = {
+		  }
+		  tls_ops[] =
+		  {
 		    { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
 		    { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
 		    { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
@@ -1879,7 +1880,8 @@ sparc_ip (str, pinsn)
 		    { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
 		    { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
 		    { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
-		    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
+		    { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
+		    { NULL, 0, 0, 0 }
 		  };
 		  const struct tls_ops *o;
 		  char *s1;
@@ -3311,9 +3313,9 @@ md_apply_fix (fixP, valP, segment)
 	  break;
 
 	case BFD_RELOC_SPARC_WDISP16:
-	  /* FIXME: simplify.  */
-	  if (((val > 0) && (val & ~0x3fffc))
-	      || ((val < 0) && (~(val - 1) & ~0x3fffc)))
+	  if ((val & 3)
+	      || val >= 0x1fffc
+	      || val <= -(offsetT) 0x20008)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("relocation overflow"));
 	  /* FIXME: The +1 deserves a comment.  */
@@ -3322,9 +3324,9 @@ md_apply_fix (fixP, valP, segment)
 	  break;
 
 	case BFD_RELOC_SPARC_WDISP19:
-	  /* FIXME: simplify.  */
-	  if (((val > 0) && (val & ~0x1ffffc))
-	      || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
+	  if ((val & 3)
+	      || val >= 0xffffc
+	      || val <= -(offsetT) 0x100008)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("relocation overflow"));
 	  /* FIXME: The +1 deserves a comment.  */
@@ -3439,7 +3441,7 @@ md_apply_fix (fixP, valP, segment)
 
 arelent **
 tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
+     asection *section;
      fixS *fixp;
 {
   static arelent *relocs[3];
@@ -3582,6 +3584,16 @@ tc_gen_reloc (section, fixp)
     }
 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT)  */
 
+  /* Nothing is aligned in DWARF debugging sections.  */
+  if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
+    switch (code)
+      {
+      case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
+      case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
+      case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
+      default: break;
+      }
+
   if (code == BFD_RELOC_SPARC_OLO10)
     reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
   else
@@ -4602,7 +4614,7 @@ sparc_cfi_frame_initial_instructions ()
 }
 
 int
-sparc_regname_to_dw2regnum (const char *regname)
+sparc_regname_to_dw2regnum (char *regname)
 {
   char *p, *q;
 
diff --git a/gas/config/tc-sparc.h b/gas/config/tc-sparc.h
index 14da16ad627a..90c0e95d0f55 100644
--- a/gas/config/tc-sparc.h
+++ b/gas/config/tc-sparc.h
@@ -1,6 +1,7 @@
 /* tc-sparc.h - Macros and type defines for the sparc.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
+   1999, 2000, 2001, 2002, 2003, 2005, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -31,6 +32,19 @@ struct frag;
 
 #define TARGET_ARCH bfd_arch_sparc
 
+#ifdef TE_FreeBSD
+#define ELF_TARGET_FORMAT	"elf32-sparc-freebsd"
+#define ELF64_TARGET_FORMAT	"elf64-sparc-freebsd"
+#endif
+
+#ifndef ELF_TARGET_FORMAT
+#define ELF_TARGET_FORMAT	"elf32-sparc"
+#endif
+
+#ifndef ELF64_TARGET_FORMAT
+#define ELF64_TARGET_FORMAT	"elf64-sparc"
+#endif
+
 extern const char *sparc_target_format PARAMS ((void));
 #define TARGET_FORMAT sparc_target_format ()
 
@@ -78,7 +92,6 @@ extern void sparc_handle_align PARAMS ((struct frag *));
 
 #define TC_FORCE_RELOCATION_LOCAL(FIX)		\
   (!(FIX)->fx_pcrel				\
-   || (FIX)->fx_plt				\
    || (sparc_pic_code				\
        && S_IS_EXTERNAL ((FIX)->fx_addsy))	\
    || TC_FORCE_RELOCATION (FIX))
@@ -171,7 +184,7 @@ extern void cons_fix_new_sparc
 extern void sparc_cfi_frame_initial_instructions PARAMS ((void));
 
 #define tc_regname_to_dw2regnum sparc_regname_to_dw2regnum
-extern int sparc_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int sparc_regname_to_dw2regnum PARAMS ((char *regname));
 
 #define tc_cfi_emit_pcrel_expr sparc_cfi_emit_pcrel_expr
 extern void sparc_cfi_emit_pcrel_expr PARAMS ((expressionS *, unsigned int));
diff --git a/gas/config/tc-spu.c b/gas/config/tc-spu.c
new file mode 100644
index 000000000000..ef801df9a768
--- /dev/null
+++ b/gas/config/tc-spu.c
@@ -0,0 +1,1083 @@
+/* spu.c -- Assembler for the IBM Synergistic Processing Unit (SPU)
+
+   Copyright 2006, 2007 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "dwarf2dbg.h" 
+
+const struct spu_opcode spu_opcodes[] = {
+#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, (OPCODE) << (32-11), MNEMONIC, ASMFORMAT },
+#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
+	{ MACFORMAT, ((OPCODE) << (32-11)) | ((FB) << (32-18)), MNEMONIC, ASMFORMAT },
+#include "opcode/spu-insns.h"
+#undef APUOP
+#undef APUOPFB
+};
+
+static const int spu_num_opcodes =
+  sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);
+
+#define MAX_RELOCS 2
+
+struct spu_insn
+{
+  unsigned int opcode;
+  expressionS exp[MAX_RELOCS];
+  int reloc_arg[MAX_RELOCS];
+  int flag[MAX_RELOCS];
+  enum spu_insns tag;
+};
+
+static const char *get_imm (const char *param, struct spu_insn *insn, int arg);
+static const char *get_reg (const char *param, struct spu_insn *insn, int arg,
+			    int accept_expr);
+static int calcop (struct spu_opcode *format, const char *param,
+		   struct spu_insn *insn);
+static void spu_cons (int);
+
+extern char *myname;
+static struct hash_control *op_hash = NULL;
+
+/* These bits should be turned off in the first address of every segment */
+int md_seg_align = 7;
+
+/* These chars start a comment anywhere in a source file (except inside
+   another comment */
+const char comment_chars[] = "#";
+
+/* These chars only start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* gods own line continuation char */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant */
+/* as in 0f123.456 */
+/* or    0H1.234E-12 (see exp chars above) */
+const char FLT_CHARS[] = "dDfF";
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"align", s_align_ptwo, 4},
+  {"bss", s_lcomm_bytes, 1},
+  {"def", s_set, 0},
+  {"dfloat", float_cons, 'd'},
+  {"ffloat", float_cons, 'f'},
+  {"global", s_globl, 0},
+  {"half", cons, 2},
+  {"int", spu_cons, 4},
+  {"long", spu_cons, 4},
+  {"quad", spu_cons, 8},
+  {"string", stringer, 1},
+  {"word", spu_cons, 4},
+  /* Force set to be treated as an instruction.  */
+  {"set", NULL, 0},
+  {".set", s_set, 0},
+  /* Likewise for eqv.  */
+  {"eqv", NULL, 0},
+  {".eqv", s_set, -1},
+  {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, 
+  {"loc", dwarf2_directive_loc, 0}, 
+  {0,0,0}
+};
+
+void
+md_begin (void)
+{
+  const char *retval = NULL;
+  int i;
+
+  /* initialize hash table */
+
+  op_hash = hash_new ();
+
+  /* loop until you see the end of the list */
+
+  for (i = 0; i < spu_num_opcodes; i++)
+    {
+      /* hash each mnemonic and record its position */
+
+      retval = hash_insert (op_hash, spu_opcodes[i].mnemonic, (PTR)&spu_opcodes[i]);
+
+      if (retval != NULL && strcmp (retval, "exists") != 0)
+	as_fatal (_("Can't hash instruction '%s':%s"),
+		  spu_opcodes[i].mnemonic, retval);
+    }
+}
+
+const char *md_shortopts = "";
+struct option md_longopts[] = {
+#define OPTION_APUASM (OPTION_MD_BASE)
+  {"apuasm", no_argument, NULL, OPTION_APUASM},
+#define OPTION_DD2 (OPTION_MD_BASE+1)
+  {"mdd2.0", no_argument, NULL, OPTION_DD2},
+#define OPTION_DD1 (OPTION_MD_BASE+2)
+  {"mdd1.0", no_argument, NULL, OPTION_DD1},
+#define OPTION_DD3 (OPTION_MD_BASE+3)
+  {"mdd3.0", no_argument, NULL, OPTION_DD3},
+  { NULL, no_argument, NULL, 0 }
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* When set (by -apuasm) our assembler emulates the behaviour of apuasm.
+ * e.g. don't add bias to float conversion and don't right shift
+ * immediate values. */
+static int emulate_apuasm;
+
+/* Use the dd2.0 instructions set.  The only differences are some new
+ * register names and the orx insn */
+static int use_dd2 = 1;
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    case OPTION_APUASM:
+      emulate_apuasm = 1;
+      break;
+    case OPTION_DD3:
+      use_dd2 = 1;
+      break;
+    case OPTION_DD2:
+      use_dd2 = 1;
+      break;
+    case OPTION_DD1:
+      use_dd2 = 0;
+      break;
+    default:
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  fputs (_("\
+SPU options:\n\
+  --apuasm		  emulate behaviour of apuasm\n"),
+	stream);
+}
+
+
+struct arg_encode {
+  int size;
+  int pos;
+  int rshift;
+  int lo, hi;
+  int wlo, whi;
+  bfd_reloc_code_real_type reloc;
+};
+
+static struct arg_encode arg_encode[A_MAX] = {
+  {  7,  0, 0,       0,    127,    0,   -1,  0 }, /* A_T */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_A */
+  {  7, 14, 0,       0,    127,    0,   -1,  0 }, /* A_B */
+  {  7, 21, 0,       0,    127,    0,   -1,  0 }, /* A_C */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_S */
+  {  7,  7, 0,       0,    127,    0,   -1,  0 }, /* A_H */
+  {  0,  0, 0,       0,     -1,    0,   -1,  0 }, /* A_P */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_S3 */
+  {  7, 14, 0,     -32,     31,  -31,    0,  BFD_RELOC_SPU_IMM7 }, /* A_S6 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_S7N */
+  {  7, 14, 0,     -64,     63,  -63,    0,  BFD_RELOC_SPU_IMM7 }, /* A_S7 */
+  {  8, 14, 0,       0,    127,    0,   -1,  BFD_RELOC_SPU_IMM8 }, /* A_U7A */
+  {  8, 14, 0,       0,    127,    0,   -1,  BFD_RELOC_SPU_IMM8 }, /* A_U7B */
+  { 10, 14, 0,    -512,    511, -128,  255,  BFD_RELOC_SPU_IMM10 }, /* A_S10B */
+  { 10, 14, 0,    -512,    511,    0,   -1,  BFD_RELOC_SPU_IMM10 }, /* A_S10 */
+  {  2, 23, 9,   -1024,   1023,    0,   -1,  BFD_RELOC_SPU_PCREL9a }, /* A_S11 */
+  {  2, 14, 9,   -1024,   1023,    0,   -1,  BFD_RELOC_SPU_PCREL9b }, /* A_S11I */
+  { 10, 14, 4,   -8192,   8191,    0,   -1,  BFD_RELOC_SPU_IMM10W }, /* A_S14 */
+  { 16,  7, 0,  -32768,  32767,    0,   -1,  BFD_RELOC_SPU_IMM16 }, /* A_S16 */
+  { 16,  7, 2, -131072, 262143,    0,   -1,  BFD_RELOC_SPU_IMM16W }, /* A_S18 */
+  { 16,  7, 2, -262144, 262143,    0,   -1,  BFD_RELOC_SPU_PCREL16 }, /* A_R18 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_U3 */
+  {  7, 14, 0,       0,    127,    0,   31,  BFD_RELOC_SPU_IMM7 }, /* A_U5 */
+  {  7, 14, 0,       0,    127,    0,   63,  BFD_RELOC_SPU_IMM7 }, /* A_U6 */
+  {  7, 14, 0,       0,     -1,    0,   -1,  BFD_RELOC_SPU_IMM7 }, /* A_U7 */
+  { 14,  0, 0,       0,  16383,    0,   -1,  0 }, /* A_U14 */
+  { 16,  7, 0,  -32768,  65535,    0,   -1,  BFD_RELOC_SPU_IMM16 }, /* A_X16 */
+  { 18,  7, 0,       0, 262143,    0,   -1,  BFD_RELOC_SPU_IMM18 }, /* A_U18 */
+};
+
+/* Some flags for handling errors.  This is very hackish and added after
+ * the fact. */
+static int syntax_error_arg;
+static const char *syntax_error_param;
+static int syntax_reg;
+
+static char *
+insn_fmt_string (struct spu_opcode *format)
+{
+  static char buf[64];
+  int len = 0;
+  int i;
+
+  len += sprintf (&buf[len], "%s\t", format->mnemonic);
+  for (i = 1; i <= format->arg[0]; i++)
+    {
+      int arg = format->arg[i];
+      char *exp;
+      if (i > 1 && arg != A_P && format->arg[i-1] != A_P) 
+	buf[len++] =  ',';
+      if (arg == A_P)
+	exp = "(";
+      else if (arg < A_P)
+	exp = i == syntax_error_arg ? "REG" : "reg";
+      else 
+	exp = i == syntax_error_arg ? "IMM" : "imm";
+      len += sprintf (&buf[len], "%s", exp);
+      if (i > 1 && format->arg[i-1] == A_P) 
+	buf[len++] =  ')';
+    }
+  buf[len] = 0;
+  return buf;
+}
+
+void
+md_assemble (char *op)
+{
+  char *param, *thisfrag;
+  char c;
+  struct spu_opcode *format;
+  struct spu_insn insn;
+  int i;
+
+  assert (op);
+
+  /* skip over instruction to find parameters */
+
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param = 0;
+
+  if (c != 0 && c != '\n')
+    param++;
+
+  /* try to find the instruction in the hash table */
+
+  if ((format = (struct spu_opcode *) hash_find (op_hash, op)) == NULL)
+    {
+      as_bad (_("Invalid mnemonic '%s'"), op);
+      return;
+    }
+
+  if (!use_dd2 && strcmp (format->mnemonic, "orx") == 0)
+    {
+      as_bad (_("'%s' is only available in DD2.0 or higher."), op);
+      return;
+    }
+
+  while (1)
+    {
+      /* try parsing this instruction into insn */
+      for (i = 0; i < MAX_RELOCS; i++)
+	{
+	  insn.exp[i].X_add_symbol = 0;
+	  insn.exp[i].X_op_symbol = 0;
+	  insn.exp[i].X_add_number = 0;
+	  insn.exp[i].X_op = O_illegal;
+	  insn.reloc_arg[i] = -1;
+	  insn.flag[i] = 0;
+	}
+      insn.opcode = format->opcode;
+      insn.tag = (enum spu_insns) (format - spu_opcodes);
+
+      syntax_error_arg = 0;
+      syntax_error_param = 0;
+      syntax_reg = 0;
+      if (calcop (format, param, &insn))
+	break;
+
+      /* if it doesn't parse try the next instruction */
+      if (!strcmp (format[0].mnemonic, format[1].mnemonic))
+	format++;
+      else
+	{
+	  int parg = format[0].arg[syntax_error_arg-1];
+
+	  as_fatal (_("Error in argument %d.  Expecting:  \"%s\""),
+		    syntax_error_arg - (parg == A_P),
+		    insn_fmt_string (format));
+	  return;
+	}
+    }
+
+  if ((syntax_reg & 4)
+      && ! (insn.tag == M_RDCH
+	    || insn.tag == M_RCHCNT
+	    || insn.tag == M_WRCH))
+    as_warn (_("Mixing register syntax, with and without '$'."));
+  if (syntax_error_param)
+    {
+      const char *d = syntax_error_param;
+      while (*d != '$')
+	d--;
+      as_warn (_("Treating '%-*s' as a symbol."), (int)(syntax_error_param - d), d);
+    }
+
+  /* grow the current frag and plop in the opcode */
+
+  thisfrag = frag_more (4);
+  md_number_to_chars (thisfrag, insn.opcode, 4);
+
+  /* if this instruction requires labels mark it for later */
+
+  for (i = 0; i < MAX_RELOCS; i++)
+    if (insn.reloc_arg[i] >= 0) 
+      {
+        fixS *fixP;
+        bfd_reloc_code_real_type reloc = arg_encode[insn.reloc_arg[i]].reloc;
+	int pcrel = 0;
+
+        if (reloc == BFD_RELOC_SPU_PCREL9a
+	    || reloc == BFD_RELOC_SPU_PCREL9b
+            || reloc == BFD_RELOC_SPU_PCREL16)
+	  pcrel = 1;
+	if (insn.flag[i] == 1)
+	  reloc = BFD_RELOC_SPU_HI16;
+	else if (insn.flag[i] == 2)
+	  reloc = BFD_RELOC_SPU_LO16;
+	fixP = fix_new_exp (frag_now,
+			    thisfrag - frag_now->fr_literal,
+			    4,
+			    &insn.exp[i],
+			    pcrel,
+			    reloc);
+	fixP->tc_fix_data.arg_format = insn.reloc_arg[i];
+	fixP->tc_fix_data.insn_tag = insn.tag;
+      }
+  dwarf2_emit_insn (4);
+}
+
+static int
+calcop (struct spu_opcode *format, const char *param, struct spu_insn *insn)
+{
+  int i;
+  int paren = 0;
+  int arg;
+
+  for (i = 1; i <= format->arg[0]; i++)
+    {
+      arg = format->arg[i];
+      syntax_error_arg = i;
+
+      while (ISSPACE (*param))
+        param++;
+      if (*param == 0 || *param == ',')
+	return 0;
+      if (arg < A_P)
+        param = get_reg (param, insn, arg, 1);
+      else if (arg > A_P)
+        param = get_imm (param, insn,  arg);
+      else if (arg == A_P)
+	{
+	  paren++;
+	  if ('(' != *param++)
+	    return 0;
+	}
+
+      if (!param)
+	return 0;
+
+      while (ISSPACE (*param))
+        param++;
+
+      if (arg != A_P && paren)
+	{
+	  paren--;
+	  if (')' != *param++)
+	    return 0;
+	}
+      else if (i < format->arg[0]
+	       && format->arg[i] != A_P
+	       && format->arg[i+1] != A_P)
+	{
+	  if (',' != *param++)
+	    {
+	      syntax_error_arg++;
+	      return 0;
+	    }
+	}
+    }
+  while (ISSPACE (*param))
+    param++;
+  return !paren && (*param == 0 || *param == '\n');
+}
+
+struct reg_name {
+    unsigned int regno;
+    unsigned int length;
+    char name[32];
+};
+
+#define REG_NAME(NO,NM) { NO, sizeof (NM) - 1, NM }
+
+static struct reg_name reg_name[] = {
+  REG_NAME (0, "lr"),  /* link register */
+  REG_NAME (1, "sp"),  /* stack pointer */
+  REG_NAME (0, "rp"),  /* link register */
+  REG_NAME (127, "fp"),  /* frame pointer */
+};
+
+static struct reg_name sp_reg_name[] = {
+};
+
+static struct reg_name ch_reg_name[] = {
+  REG_NAME (  0, "SPU_RdEventStat"),
+  REG_NAME (  1, "SPU_WrEventMask"),
+  REG_NAME (  2, "SPU_WrEventAck"),
+  REG_NAME (  3, "SPU_RdSigNotify1"),
+  REG_NAME (  4, "SPU_RdSigNotify2"),
+  REG_NAME (  7, "SPU_WrDec"),
+  REG_NAME (  8, "SPU_RdDec"),
+  REG_NAME ( 11, "SPU_RdEventMask"), /* DD2.0 only */
+  REG_NAME ( 13, "SPU_RdMachStat"),
+  REG_NAME ( 14, "SPU_WrSRR0"),
+  REG_NAME ( 15, "SPU_RdSRR0"),
+  REG_NAME ( 28, "SPU_WrOutMbox"),
+  REG_NAME ( 29, "SPU_RdInMbox"),
+  REG_NAME ( 30, "SPU_WrOutIntrMbox"),
+  REG_NAME (  9, "MFC_WrMSSyncReq"),
+  REG_NAME ( 12, "MFC_RdTagMask"),   /* DD2.0 only */
+  REG_NAME ( 16, "MFC_LSA"),
+  REG_NAME ( 17, "MFC_EAH"),
+  REG_NAME ( 18, "MFC_EAL"),
+  REG_NAME ( 19, "MFC_Size"),
+  REG_NAME ( 20, "MFC_TagID"),
+  REG_NAME ( 21, "MFC_Cmd"),
+  REG_NAME ( 22, "MFC_WrTagMask"),
+  REG_NAME ( 23, "MFC_WrTagUpdate"),
+  REG_NAME ( 24, "MFC_RdTagStat"),
+  REG_NAME ( 25, "MFC_RdListStallStat"),
+  REG_NAME ( 26, "MFC_WrListStallAck"),
+  REG_NAME ( 27, "MFC_RdAtomicStat"),
+};
+#undef REG_NAME
+
+static const char *
+get_reg (const char *param, struct spu_insn *insn, int arg, int accept_expr)
+{
+  unsigned regno;
+  int saw_prefix = 0;
+
+  if (*param == '$')
+    {
+      saw_prefix = 1;
+      param++;
+    }
+    
+  if (arg == A_H) /* Channel */
+    {
+      if ((param[0] == 'c' || param[0] == 'C')
+	  && (param[1] == 'h' || param[1] == 'H')
+	  && ISDIGIT (param[2]))
+        param += 2;
+    }
+  else if (arg == A_S) /* Special purpose register */
+    {
+      if ((param[0] == 's' || param[0] == 'S')
+	  && (param[1] == 'p' || param[1] == 'P')
+	  && ISDIGIT (param[2]))
+        param += 2;
+    }
+
+  if (ISDIGIT (*param))
+    {
+      regno = 0;
+      while (ISDIGIT (*param))
+	regno = regno * 10 + *param++ - '0';
+    }
+  else
+    {
+      struct reg_name *rn;
+      unsigned int i, n, l = 0;
+
+      if (arg == A_H) /* Channel */
+	{
+	  rn = ch_reg_name;
+	  n = sizeof (ch_reg_name) / sizeof (*ch_reg_name);
+	}
+      else if (arg == A_S) /* Special purpose register */
+	{
+	  rn = sp_reg_name;
+	  n = sizeof (sp_reg_name) / sizeof (*sp_reg_name);
+	}
+      else
+	{
+	  rn = reg_name;
+	  n = sizeof (reg_name) / sizeof (*reg_name);
+	}
+      regno = 128;
+      for (i = 0; i < n; i++)
+	if (rn[i].length > l
+	    && 0 == strncasecmp (param, rn[i].name, rn[i].length))
+          {
+	    l = rn[i].length;
+            regno = rn[i].regno;
+          }
+      param += l;
+    }
+
+  if (!use_dd2
+      && arg == A_H)
+    {
+      if (regno == 11)
+	as_bad (_("'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher."));
+      else if (regno == 12)
+	as_bad (_("'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher."));
+    }
+
+  if (regno < 128)
+    {
+      insn->opcode |= regno << arg_encode[arg].pos;
+      if ((!saw_prefix && syntax_reg == 1)
+	  || (saw_prefix && syntax_reg == 2))
+	syntax_reg |= 4;
+      syntax_reg |= saw_prefix ? 1 : 2;
+      return param;
+    }
+
+  if (accept_expr)
+    {
+      char *save_ptr;
+      expressionS ex;
+      save_ptr = input_line_pointer;
+      input_line_pointer = (char *)param;
+      expression (&ex);
+      param = input_line_pointer;
+      input_line_pointer = save_ptr;
+      if (ex.X_op == O_register || ex.X_op == O_constant)
+	{
+	  insn->opcode |= ex.X_add_number << arg_encode[arg].pos;
+	  return param;
+	}
+    }
+  return 0;
+}
+
+static const char *
+get_imm (const char *param, struct spu_insn *insn, int arg)
+{
+  int val;
+  char *save_ptr;
+  int low = 0, high = 0;
+  int reloc_i = insn->reloc_arg[0] >= 0 ? 1 : 0;
+
+  if (strncasecmp (param, "%lo(", 4) == 0)
+    {
+      param += 3;
+      low = 1;
+      as_warn (_("Using old style, %%lo(expr), please change to PPC style, expr@l."));
+    }
+  else if (strncasecmp (param, "%hi(", 4) == 0)
+    {
+      param += 3;
+      high = 1;
+      as_warn (_("Using old style, %%hi(expr), please change to PPC style, expr@h."));
+    }
+  else if (strncasecmp (param, "%pic(", 5) == 0)
+    {
+      /* Currently we expect %pic(expr) == expr, so do nothing here.
+	 i.e. for code loaded at address 0 $toc will be 0.  */
+      param += 4;
+    }
+      
+  if (*param == '$')
+    {
+      /* Symbols can start with $, but if this symbol matches a register
+	 name, it's probably a mistake.  The only way to avoid this
+	 warning is to rename the symbol.  */
+      struct spu_insn tmp_insn;
+      const char *np = get_reg (param, &tmp_insn, arg, 0);
+
+      if (np)
+	syntax_error_param = np;
+    }
+      
+  save_ptr = input_line_pointer;
+  input_line_pointer = (char *) param;
+  expression (&insn->exp[reloc_i]);
+  param = input_line_pointer;
+  input_line_pointer = save_ptr;
+
+  /* Similar to ppc_elf_suffix in tc-ppc.c.  We have so few cases to
+     handle we do it inlined here. */
+  if (param[0] == '@' && !ISALNUM (param[2]) && param[2] != '@')
+    {
+      if (param[1] == 'h' || param[1] == 'H')
+	{
+	  high = 1;
+	  param += 2;
+	}
+      else if (param[1] == 'l' || param[1] == 'L')
+	{
+	  low = 1;
+	  param += 2;
+	}
+    }
+
+  if (insn->exp[reloc_i].X_op == O_constant)
+    {
+      val = insn->exp[reloc_i].X_add_number;
+
+      if (emulate_apuasm)
+	{
+	  /* Convert the value to a format we expect. */ 
+          val <<= arg_encode[arg].rshift;
+	  if (arg == A_U7A)
+	    val = 173 - val;
+	  else if (arg == A_U7B)
+	    val = 155 - val; 
+	}
+
+      if (high)
+	val = val >> 16;
+      else if (low)
+	val = val & 0xffff;
+
+      /* Warn about out of range expressions. */
+      {
+	int hi = arg_encode[arg].hi;
+	int lo = arg_encode[arg].lo;
+	int whi = arg_encode[arg].whi;
+	int wlo = arg_encode[arg].wlo;
+
+	if (hi > lo && (val < lo || val > hi))
+	  as_fatal (_("Constant expression %d out of range, [%d, %d]."),
+		    val, lo, hi);
+	else if (whi > wlo && (val < wlo || val > whi))
+	  as_warn (_("Constant expression %d out of range, [%d, %d]."),
+		   val, wlo, whi);
+      }
+
+      if (arg == A_U7A)
+        val = 173 - val;
+      else if (arg == A_U7B)
+        val = 155 - val; 
+
+      /* Branch hints have a split encoding.  Do the bottom part. */
+      if (arg == A_S11 || arg == A_S11I)
+	insn->opcode |= ((val >> 2) & 0x7f);
+
+      insn->opcode |= (((val >> arg_encode[arg].rshift)
+			& ((1 << arg_encode[arg].size) - 1))
+		       << arg_encode[arg].pos);
+      insn->reloc_arg[reloc_i] = -1;
+      insn->flag[reloc_i] = 0;
+    }
+  else
+    {
+      insn->reloc_arg[reloc_i] = arg;
+      if (high)
+	insn->flag[reloc_i] = 1;
+      else if (low)
+	insn->flag[reloc_i] = 2;
+    }
+
+  return param;
+}
+
+#define MAX_LITTLENUMS 6
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
+ */
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  char *t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+    case 'x':
+    case 'X':
+      prec = 6;
+      break;
+
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to MD_ATOF()");
+    }
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+  for (wordP = words; prec--;)
+    {
+      md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+  return 0;
+}
+
+#ifndef WORKING_DOT_WORD
+int md_short_jump_size = 4;
+
+void
+md_create_short_jump (char *ptr,
+		      addressT from_addr ATTRIBUTE_UNUSED,
+		      addressT to_addr ATTRIBUTE_UNUSED,
+		      fragS *frag,
+		      symbolS *to_symbol)
+{
+  ptr[0] = (char) 0xc0;
+  ptr[1] = 0x00;
+  ptr[2] = 0x00;
+  ptr[3] = 0x00;
+  fix_new (frag,
+	   ptr - frag->fr_literal,
+	   4,
+	   to_symbol,
+	   (offsetT) 0,
+	   0,
+	   BFD_RELOC_SPU_PCREL16);
+}
+
+int md_long_jump_size = 4;
+
+void
+md_create_long_jump (char *ptr,
+		     addressT from_addr ATTRIBUTE_UNUSED,
+		     addressT to_addr ATTRIBUTE_UNUSED,
+		     fragS *frag,
+		     symbolS *to_symbol)
+{
+  ptr[0] = (char) 0xc0;
+  ptr[1] = 0x00;
+  ptr[2] = 0x00;
+  ptr[3] = 0x00;
+  fix_new (frag,
+	   ptr - frag->fr_literal,
+	   4,
+	   to_symbol,
+	   (offsetT) 0,
+	   0,
+	   BFD_RELOC_SPU_PCREL16);
+}
+#endif
+
+/* Support @ppu on symbols referenced in .int/.long/.word/.quad.  */
+static void
+spu_cons (int nbytes)
+{
+  expressionS exp;
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+  do
+    {
+      deferred_expression (&exp);
+      if ((exp.X_op == O_symbol
+	   || exp.X_op == O_constant)
+	  && strncasecmp (input_line_pointer, "@ppu", 4) == 0)
+	{
+	  char *p = frag_more (nbytes);
+	  enum bfd_reloc_code_real reloc;
+
+	  /* Check for identifier@suffix+constant.  */
+	  input_line_pointer += 4;
+	  if (*input_line_pointer == '-' || *input_line_pointer == '+')
+	    {
+	      expressionS new_exp;
+
+	      expression (&new_exp);
+	      if (new_exp.X_op == O_constant)
+		exp.X_add_number += new_exp.X_add_number;
+	    }
+
+	  reloc = nbytes == 4 ? BFD_RELOC_SPU_PPU32 : BFD_RELOC_SPU_PPU64;
+	  fix_new_exp (frag_now, p - frag_now->fr_literal, nbytes,
+		       &exp, 0, reloc);
+	}
+      else
+	emit_expr (&exp, nbytes);
+    }
+  while (*input_line_pointer++ == ',');
+
+  /* Put terminator back into stream.  */
+  input_line_pointer--;
+  demand_empty_rest_of_line ();
+}
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+			       segT segment_type ATTRIBUTE_UNUSED)
+{
+  as_fatal (_("Relaxation should never occur"));
+  return -1;
+}
+
+/* If while processing a fixup, a reloc really needs to be created,
+   then it is done here.  */
+
+arelent *
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *reloc;
+  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  if (fixp->fx_addsy)
+    *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  else if (fixp->fx_subsy)
+    *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
+  else
+    abort ();
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+  if (reloc->howto == (reloc_howto_type *) NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("reloc %d not supported by object file format"),
+		    (int) fixp->fx_r_type);
+      return NULL;
+    }
+  reloc->addend = fixp->fx_addnumber;
+  return reloc;
+}
+
+/* Round up a section's size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, seg);
+  valueT mask = ((valueT) 1 << align) - 1;
+
+  return (size + mask) & ~mask;
+}
+
+/* Where a PC relative offset is calculated from.  On the spu they
+   are calculated from the beginning of the branch instruction.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+/* Fill in rs_align_code fragments.  */
+
+void
+spu_handle_align (fragS *fragp)
+{
+  static const unsigned char nop_pattern[8] = {
+    0x40, 0x20, 0x00, 0x00, /* even nop */
+    0x00, 0x20, 0x00, 0x00, /* odd  nop */
+  };
+
+  int bytes;
+  char *p;
+
+  if (fragp->fr_type != rs_align_code)
+    return;
+
+  bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+  p = fragp->fr_literal + fragp->fr_fix;
+
+  if (bytes & 3)
+    {
+      int fix = bytes & 3;
+      memset (p, 0, fix);
+      p += fix;
+      bytes -= fix;
+      fragp->fr_fix += fix;
+    }
+  if (bytes & 4)
+    {
+      memcpy (p, &nop_pattern[4], 4);
+      p += 4;
+      bytes -= 4;
+      fragp->fr_fix += 4;
+    }
+
+  memcpy (p, nop_pattern, 8);
+  fragp->fr_var = 8;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  unsigned int res;
+  valueT val = *valP;
+  char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
+
+  if (fixP->fx_subsy != (symbolS *) NULL)
+    {
+      /* We can't actually support subtracting a symbol.  */
+      as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
+    }
+
+  if (fixP->fx_addsy != NULL)
+    {
+      if (fixP->fx_pcrel)
+	{
+	  /* Hack around bfd_install_relocation brain damage.  */
+	  val += fixP->fx_frag->fr_address + fixP->fx_where;
+
+	  switch (fixP->fx_r_type)
+	    {
+	    case BFD_RELOC_32:
+	      fixP->fx_r_type = BFD_RELOC_32_PCREL;
+	      break;
+
+	    case BFD_RELOC_SPU_PCREL16:
+	    case BFD_RELOC_SPU_PCREL9a:
+	    case BFD_RELOC_SPU_PCREL9b:
+	    case BFD_RELOC_32_PCREL:
+	      break;
+
+	    default:
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("expression too complex"));
+	      break;
+	    }
+	}
+    }
+
+  fixP->fx_addnumber = val;
+
+  if (fixP->fx_r_type == BFD_RELOC_SPU_PPU32
+      || fixP->fx_r_type == BFD_RELOC_SPU_PPU64)
+    return;
+
+  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
+    {
+      fixP->fx_done = 1;
+      res = 0;
+      if (fixP->tc_fix_data.arg_format > A_P)
+	{
+	  int hi = arg_encode[fixP->tc_fix_data.arg_format].hi;
+	  int lo = arg_encode[fixP->tc_fix_data.arg_format].lo;
+	  if (hi > lo && ((offsetT) val < lo || (offsetT) val > hi))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  "Relocation doesn't fit. (relocation value = 0x%lx)",
+			  (long) val);
+	}
+
+      switch (fixP->fx_r_type)
+        {
+        case BFD_RELOC_8:
+	  md_number_to_chars (place, val, 1);
+	  return;
+
+        case BFD_RELOC_16:
+	  md_number_to_chars (place, val, 2);
+	  return;
+
+        case BFD_RELOC_32:
+	  md_number_to_chars (place, val, 4);
+	  return;
+
+        case BFD_RELOC_64:
+	  md_number_to_chars (place, val, 8);
+	  return;
+
+        case BFD_RELOC_SPU_IMM7:
+          res = (val & 0x7f) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM8:
+          res = (val & 0xff) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM10:
+          res = (val & 0x3ff) << 14;
+          break;
+
+        case BFD_RELOC_SPU_IMM10W:
+          res = (val & 0x3ff0) << 10;
+          break;
+
+        case BFD_RELOC_SPU_IMM16:
+          res = (val & 0xffff) << 7;
+          break;
+
+        case BFD_RELOC_SPU_IMM16W:
+          res = (val & 0x3fffc) << 5;
+          break;
+
+        case BFD_RELOC_SPU_IMM18:
+          res = (val & 0x3ffff) << 7;
+          break;
+
+        case BFD_RELOC_SPU_PCREL9a:
+          res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 14);
+          break;
+
+        case BFD_RELOC_SPU_PCREL9b:
+          res = ((val & 0x1fc) >> 2) | ((val & 0x600) << 5);
+          break;
+
+        case BFD_RELOC_SPU_PCREL16:
+          res = (val & 0x3fffc) << 5;
+          break;
+
+        default:
+          as_bad_where (fixP->fx_file, fixP->fx_line,
+                        _("reloc %d not supported by object file format"),
+                        (int) fixP->fx_r_type);
+        }
+
+      if (res != 0)
+        {
+          place[0] |= (res >> 24) & 0xff;
+          place[1] |= (res >> 16) & 0xff;
+          place[2] |= (res >> 8) & 0xff;
+          place[3] |= (res) & 0xff;
+        }
+    }
+}
diff --git a/gas/config/tc-spu.h b/gas/config/tc-spu.h
new file mode 100644
index 000000000000..4c6c2d4566ef
--- /dev/null
+++ b/gas/config/tc-spu.h
@@ -0,0 +1,107 @@
+/* spu.h -- Assembler for spu
+
+   Copyright 2006, 2007 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef TC_SPU
+#define TC_SPU 1
+
+#include "opcode/spu.h"
+
+#define TARGET_FORMAT "elf32-spu"
+#define TARGET_ARCH bfd_arch_spu
+#define TARGET_NAME "elf32-spu"
+
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+struct tc_fix_info {
+  unsigned short arg_format;
+  unsigned short insn_tag;
+};
+
+/* fixS will have a member named tc_fix_data of this type.  */
+#define TC_FIX_TYPE struct tc_fix_info
+#define TC_INIT_FIX_DATA(FIXP) \
+  do						\
+    {						\
+      (FIXP)->tc_fix_data.arg_format = 0;	\
+      (FIXP)->tc_fix_data.insn_tag = 0;		\
+    }						\
+  while (0)
+
+/* Don't reduce function symbols to section symbols, and don't adjust
+   references to PPU symbols.  */
+#define tc_fix_adjustable(FIXP) \
+  (!(S_IS_FUNCTION ((FIXP)->fx_addsy)			\
+     || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32	\
+     || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64))
+
+/* Keep relocs on calls.  Branches to function symbols are tail or
+   sibling calls.  */
+#define TC_FORCE_RELOCATION(FIXP) \
+  ((FIXP)->tc_fix_data.insn_tag == M_BRSL		\
+   || (FIXP)->tc_fix_data.insn_tag == M_BRASL		\
+   || (((FIXP)->tc_fix_data.insn_tag == M_BR		\
+	|| (FIXP)->tc_fix_data.insn_tag == M_BRA)	\
+       && (FIXP)->fx_addsy != NULL			\
+       && S_IS_FUNCTION ((FIXP)->fx_addsy))		\
+   || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU32		\
+   || (FIXP)->fx_r_type == BFD_RELOC_SPU_PPU64		\
+   || generic_force_reloc (FIXP))
+
+/* Values passed to md_apply_fix don't include symbol values.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+/* The spu uses pseudo-ops with no leading period.  */
+#define NO_PSEUDO_DOT 1
+
+/* Don't warn on word overflow; it happens on %hi relocs.  */
+#undef WARN_SIGNED_OVERFLOW_WORD
+
+#define DIFF_EXPR_OK
+
+#define WORKING_DOT_WORD
+
+#define md_number_to_chars number_to_chars_bigendian
+
+#define md_convert_frag(b,s,f)		{as_fatal (_("spu convert_frag\n"));}
+
+/* We don't need to do anything special for undefined symbols.  */
+#define md_undefined_symbol(s) 0
+
+extern symbolS *section_symbol (asection *);
+#define md_operand(e) \
+  do {								\
+    if (strncasecmp (input_line_pointer, "@ppu", 4) == 0)	\
+      {								\
+	e->X_op = O_symbol;					\
+	if (abs_section_sym == NULL)				\
+	  abs_section_sym = section_symbol (absolute_section);	\
+	e->X_add_symbol = abs_section_sym;			\
+	e->X_add_number = 0;					\
+      }								\
+  } while (0)
+
+/* Fill in rs_align_code fragments.  */
+extern void spu_handle_align PARAMS ((fragS *));
+#define HANDLE_ALIGN(frag)  spu_handle_align (frag)
+
+#define MAX_MEM_FOR_RS_ALIGN_CODE  (7 + 8)
+
+#endif /* TC_SPU */
diff --git a/gas/config/tc-tic30.c b/gas/config/tc-tic30.c
index b4acccc59bf5..e6ffbb8226de 100644
--- a/gas/config/tc-tic30.c
+++ b/gas/config/tc-tic30.c
@@ -1,5 +1,5 @@
 /* tc-c30.c -- Assembly code for the Texas Instruments TMS320C30
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2006
    Free Software Foundation, Inc.
    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
@@ -28,7 +28,6 @@
 #include "as.h"
 #include "safe-ctype.h"
 #include "opcode/tic30.h"
-#include <stdarg.h>
 
 /* Put here all non-digit non-letter characters that may occur in an
    operand.  */
@@ -273,15 +272,17 @@ struct tic30_insn
 struct tic30_insn insn;
 static int found_parallel_insn;
 
-static char output_invalid_buf[8];
+static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
 
 static char *
 output_invalid (char c)
 {
   if (ISPRINT (c))
-    sprintf (output_invalid_buf, "'%c'", c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf),
+	      "'%c'", c);
   else
-    sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
+    snprintf (output_invalid_buf, sizeof (output_invalid_buf), 
+	      "(0x%x)", (unsigned char) c);
   return output_invalid_buf;
 }
 
diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c
index 8707180c1328..a92d6a6d22a9 100644
--- a/gas/config/tc-tic4x.c
+++ b/gas/config/tc-tic4x.c
@@ -1,5 +1,5 @@
 /* tc-tic4x.c -- Assemble for the Texas Instruments TMS320C[34]x.
-   Copyright (C) 1997,1998, 2002, 2003, 2005 Free Software Foundation.
+   Copyright (C) 1997,1998, 2002, 2003, 2005, 2006 Free Software Foundation.
 
    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
 
@@ -45,14 +45,11 @@
   o Support 'abc' constants (that is 0x616263)
 */
 
-#include <stdio.h>
 #include "safe-ctype.h"
 #include "as.h"
 #include "opcode/tic4x.h"
 #include "subsegs.h"
 #include "obstack.h"
-#include "symbols.h"
-#include "listing.h"
 
 /* OK, we accept a syntax similar to the other well known C30
    assembly tools.  With TIC4X_ALT_SYNTAX defined we are more
@@ -2640,7 +2637,7 @@ md_assemble (str)
 
       if ((i = tic4x_operands_parse (s, insn->operands, 0)) < 0)
 	{
-	  insn->inst = NULL;	/* Flag that error occured.  */
+	  insn->inst = NULL;	/* Flag that error occurred.  */
 	  insn->parallel = 0;
 	  insn->in_use = 0;
 	  return;
diff --git a/gas/config/tc-tic54x.c b/gas/config/tc-tic54x.c
index f84afcd838e7..412473b98e1f 100644
--- a/gas/config/tc-tic54x.c
+++ b/gas/config/tc-tic54x.c
@@ -45,9 +45,7 @@
    COFF1 limits section names to 8 characters.
    Some of the default behavior changed from COFF1 to COFF2.  */
 
-#include <stdlib.h>
 #include <limits.h>
-#include <errno.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "sb.h"
@@ -2514,8 +2512,8 @@ tic54x_mlib (ignore)
   abfd = bfd_openr (path, NULL);
   if (!abfd)
     {
-      as_bad (_("Can't open macro library file '%s' for reading."), path);
-      as_perror ("%s", path);
+      as_bad (_("can't open macro library file '%s' for reading: %s"),
+	      path, bfd_errmsg (bfd_get_error ()));
       ignore_rest_of_line ();
       return;
     }
diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index 798495616014..dc98bd5a1f5f 100644
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -19,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
diff --git a/gas/config/tc-vax.c b/gas/config/tc-vax.c
index b0ac3f745f36..93cacd6e69be 100644
--- a/gas/config/tc-vax.c
+++ b/gas/config/tc-vax.c
@@ -2035,8 +2035,6 @@ main (void)
    We declare arrays non-local in case some of our tiny-minded machines
    default to small stacks. Also, helps with some debuggers.  */
 
-#include <stdio.h>
-
 char answer[100];		/* Human types into here.  */
 char *p;			/*  */
 char *myerr;
@@ -3267,3 +3265,143 @@ md_begin (void)
       fP->high = &big_operand_bits[i][SIZE_OF_LARGE_NUMBER - 1];
     }
 }
+
+static char *vax_cons_special_reloc;
+
+void
+vax_cons (expressionS *exp, int size)
+{
+  char *save;
+
+  SKIP_WHITESPACE ();
+  vax_cons_special_reloc = NULL;
+  save = input_line_pointer;
+  if (input_line_pointer[0] == '%')
+    {
+      if (strncmp (input_line_pointer + 1, "pcrel", 5) == 0)
+	{
+	  input_line_pointer += 6;
+	  vax_cons_special_reloc = "pcrel";
+	}
+      if (vax_cons_special_reloc)
+	{
+	  int bad = 0;
+
+	  switch (size)
+	    {
+	    case 1:
+	      if (*input_line_pointer != '8')
+		bad = 1;
+	      input_line_pointer--;
+	      break;
+	    case 2:
+	      if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
+		bad = 1;
+	      break;
+	    case 4:
+	      if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
+		bad = 1;
+	      break;
+	    default:
+	      bad = 1;
+	      break;
+	    }
+
+	  if (bad)
+	    {
+	      as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
+		      vax_cons_special_reloc, size * 8, size);
+	    }
+	  else
+	    {
+	      input_line_pointer += 2;
+	      if (*input_line_pointer != '(')
+		{
+		  as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
+			  vax_cons_special_reloc, size * 8);
+		  bad = 1;
+		}
+	    }
+
+	  if (bad)
+	    {
+	      input_line_pointer = save;
+	      vax_cons_special_reloc = NULL;
+	    }
+	  else
+	    {
+	      int c;
+	      char *end = ++input_line_pointer;
+	      int npar = 0;
+
+	      while (! is_end_of_line[(c = *end)])
+		{
+		  if (c == '(')
+	  	    npar++;
+		  else if (c == ')')
+	  	    {
+		      if (!npar)
+	      		break;
+		      npar--;
+		    }
+	    	  end++;
+		}
+
+	      if (c != ')')
+		as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
+			vax_cons_special_reloc, size * 8);
+	      else
+		{
+		  *end = '\0';
+		  expression (exp);
+		  *end = c;
+		  if (input_line_pointer != end)
+		    {
+		      as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
+			      vax_cons_special_reloc, size * 8);
+		    }
+		  else
+		    {
+		      input_line_pointer++;
+		      SKIP_WHITESPACE ();
+		      c = *input_line_pointer;
+		      if (! is_end_of_line[c] && c != ',')
+			as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
+			        vax_cons_special_reloc, size * 8);
+		    }
+		}
+	    }
+	}
+    }
+  if (vax_cons_special_reloc == NULL)
+    expression (exp);
+}
+
+/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
+   reloc for a cons.  */
+
+void
+vax_cons_fix_new (fragS *frag, int where, unsigned int nbytes, expressionS *exp)
+{
+  bfd_reloc_code_real_type r;
+
+  r = (nbytes == 1 ? BFD_RELOC_8 :
+       (nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32));
+
+  if (vax_cons_special_reloc)
+    {
+      if (*vax_cons_special_reloc == 'p')
+	{
+	  switch (nbytes)
+	    {
+	    case 1: r = BFD_RELOC_8_PCREL; break;
+	    case 2: r = BFD_RELOC_16_PCREL; break;
+	    case 4: r = BFD_RELOC_32_PCREL; break;
+	    default: abort ();
+	    }
+	}
+    }
+
+  fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
+  vax_cons_special_reloc = NULL;
+}
diff --git a/gas/config/tc-vax.h b/gas/config/tc-vax.h
index 715d54a812f6..4f16e5837d32 100644
--- a/gas/config/tc-vax.h
+++ b/gas/config/tc-vax.h
@@ -47,6 +47,13 @@
 
 #define md_operand(x)
 
+#ifdef OBJ_ELF
+#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) vax_cons (EXP, NBYTES)
+#define TC_CONS_FIX_NEW vax_cons_fix_new
+void vax_cons (expressionS *, int);
+void vax_cons_fix_new (struct frag *, int, unsigned int, struct expressionS *);
+#endif
+
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
 
diff --git a/gas/config/tc-xc16x.c b/gas/config/tc-xc16x.c
index 7a369b42ec29..2027dbdcaace 100644
--- a/gas/config/tc-xc16x.c
+++ b/gas/config/tc-xc16x.c
@@ -20,7 +20,6 @@
    02110-1301, USA.  */
 
 
-#include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
@@ -28,7 +27,6 @@
 #include "opcodes/xc16x-desc.h"
 #include "opcodes/xc16x-opc.h"
 #include "cgen.h"
-#include "bfd.h"
 #include "dwarf2dbg.h"
 
 
diff --git a/gas/config/tc-xc16x.h b/gas/config/tc-xc16x.h
index aa510d8e1a59..8aa6d07785f3 100644
--- a/gas/config/tc-xc16x.h
+++ b/gas/config/tc-xc16x.h
@@ -25,11 +25,6 @@
 
 #define TARGET_ARCH bfd_arch_xc16x
 
-#ifdef BFD_ASSEMBLER
-/* Fixup debug sections since we will never relax them.  */
-#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
-#endif
-
 #ifdef OBJ_ELF
 #define TARGET_FORMAT       "elf32-xc16x"
 #define LOCAL_LABEL_PREFIX  '.'
diff --git a/gas/config/tc-xstormy16.c b/gas/config/tc-xstormy16.c
index 29e019942457..e2f4631a8ecc 100644
--- a/gas/config/tc-xstormy16.c
+++ b/gas/config/tc-xstormy16.c
@@ -1,5 +1,6 @@
 /* tc-xstormy16.c -- Assembler for the Sanyo XSTORMY16.
-   Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,7 +19,6 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
    Boston, MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "as.h"
 #include "subsegs.h"
 #include "symcat.h"
diff --git a/gas/config/tc-xstormy16.h b/gas/config/tc-xstormy16.h
index 542587452a4c..727a4964e5c4 100644
--- a/gas/config/tc-xstormy16.h
+++ b/gas/config/tc-xstormy16.h
@@ -63,3 +63,6 @@ extern void xstormy16_cons_fix_new (fragS *f, int, int, expressionS *);
 
 /* Minimum instruction is two bytes.  */
 #define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+/* This target is buggy, and sets fix size too large.  */
+#define TC_FX_SIZE_SLACK(FIX) 2
diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index d7f059e6f5ea..aef6b65e77bf 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -1,5 +1,5 @@
 /* tc-xtensa.c -- Assemble Xtensa instructions.
-   Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,13 +18,11 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#include <string.h>
 #include <limits.h>
 #include "as.h"
 #include "sb.h"
 #include "safe-ctype.h"
 #include "tc-xtensa.h"
-#include "frags.h"
 #include "subsegs.h"
 #include "xtensa-relax.h"
 #include "xtensa-istack.h"
@@ -32,6 +30,11 @@
 #include "struc-symbol.h"
 #include "xtensa-config.h"
 
+/* Provide default values for new configuration settings.  */
+#ifndef XSHAL_ABI
+#define XSHAL_ABI 0
+#endif
+
 #ifndef uint32
 #define uint32 unsigned int
 #endif
@@ -97,33 +100,32 @@ static bfd_boolean past_xtensa_end = FALSE;
 
 #define LITERAL_SECTION_NAME		xtensa_section_rename (".literal")
 #define LIT4_SECTION_NAME		xtensa_section_rename (".lit4")
-#define FINI_SECTION_NAME		xtensa_section_rename (".fini")
 #define INIT_SECTION_NAME		xtensa_section_rename (".init")
-#define FINI_LITERAL_SECTION_NAME	xtensa_section_rename (".fini.literal")
-#define INIT_LITERAL_SECTION_NAME	xtensa_section_rename (".init.literal")
+#define FINI_SECTION_NAME		xtensa_section_rename (".fini")
 
 
 /* This type is used for the directive_stack to keep track of the
-   state of the literal collection pools.  */
+   state of the literal collection pools.  If lit_prefix is set, it is
+   used to determine the literal section names; otherwise, the literal
+   sections are determined based on the current text section.  The
+   lit_seg and lit4_seg fields cache these literal sections, with the
+   current_text_seg field used a tag to indicate whether the cached
+   values are valid.  */
 
 typedef struct lit_state_struct
 {
-  const char *lit_seg_name;
-  const char *lit4_seg_name;
-  const char *init_lit_seg_name;
-  const char *fini_lit_seg_name;
+  char *lit_prefix;
+  segT current_text_seg;
   segT lit_seg;
   segT lit4_seg;
-  segT init_lit_seg;
-  segT fini_lit_seg;
 } lit_state;
 
 static lit_state default_lit_sections;
 
 
-/* We keep lists of literal segments.  The seg_list type is the node
-   for such a list.  The *_literal_head locals are the heads of the
-   various lists.  All of these lists have a dummy node at the start.  */
+/* We keep a list of literal segments.  The seg_list type is the node
+   for this list.  The literal_head pointer is the head of the list,
+   with the literal_head_h dummy node at the start.  */
 
 typedef struct seg_list_struct
 {
@@ -133,10 +135,6 @@ typedef struct seg_list_struct
 
 static seg_list literal_head_h;
 static seg_list *literal_head = &literal_head_h;
-static seg_list init_literal_head_h;
-static seg_list *init_literal_head = &init_literal_head_h;
-static seg_list fini_literal_head_h;
-static seg_list *fini_literal_head = &fini_literal_head_h;
 
 
 /* Lists of symbols.  We keep a list of symbols that label the current
@@ -189,7 +187,9 @@ int generating_literals = 0;
 /* Instruction only properties about code.  */
 #define XTENSA_PROP_INSN_NO_DENSITY	0x00000040
 #define XTENSA_PROP_INSN_NO_REORDER	0x00000080
-#define XTENSA_PROP_INSN_NO_TRANSFORM	0x00000100
+/* Historically, NO_TRANSFORM was a property of instructions,
+   but it should apply to literals under certain circumstances.  */
+#define XTENSA_PROP_NO_TRANSFORM	0x00000100
 
 /*  Branch target alignment information.  This transmits information
     to the linker optimization about the priority of aligning a
@@ -265,6 +265,9 @@ struct frag_flags_struct
   unsigned is_data : 1;
   unsigned is_unreachable : 1;
 
+  /* is_specific_opcode implies no_transform.  */
+  unsigned is_no_transform : 1;
+
   struct
   {
     unsigned is_loop_target : 1;
@@ -273,8 +276,6 @@ struct frag_flags_struct
 
     unsigned is_no_density : 1;
     /* no_longcalls flag does not need to be placed in the object file.  */
-    /* is_specific_opcode implies no_transform.  */
-    unsigned is_no_transform : 1;
 
     unsigned is_no_reorder : 1;
 
@@ -354,6 +355,24 @@ op_placement_info_table op_placement_table;
 #define O_hi16		O_md2	/* use high 16 bits of symbolic value */
 #define O_lo16		O_md3	/* use low 16 bits of symbolic value */
 
+struct suffix_reloc_map
+{
+  char *suffix;
+  int length;
+  bfd_reloc_code_real_type reloc;
+  unsigned char operator;
+};
+
+#define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
+
+static struct suffix_reloc_map suffix_relocs[] =
+{
+  SUFFIX_MAP ("l",	BFD_RELOC_LO16,			O_lo16),
+  SUFFIX_MAP ("h",	BFD_RELOC_HI16,			O_hi16),
+  SUFFIX_MAP ("plt",	BFD_RELOC_XTENSA_PLT,		O_pltrel),
+  { (char *) 0, 0,	BFD_RELOC_UNUSED,		0 }
+};
+
 
 /* Directives.  */
 
@@ -403,7 +422,7 @@ bfd_boolean directive_state[] =
   FALSE,			/* freeregs */
   FALSE,			/* longcalls */
   FALSE,			/* literal_prefix */
-  TRUE,				/* schedule */
+  FALSE,			/* schedule */
 #if XSHAL_USE_ABSOLUTE_LITERALS
   TRUE				/* absolute_literals */
 #else
@@ -416,7 +435,7 @@ bfd_boolean directive_state[] =
 
 static void xtensa_begin_directive (int);
 static void xtensa_end_directive (int);
-static void xtensa_literal_prefix (char const *, int);
+static void xtensa_literal_prefix (void);
 static void xtensa_literal_position (int);
 static void xtensa_literal_pseudo (int);
 static void xtensa_frequency_pseudo (int);
@@ -465,12 +484,11 @@ static void xtensa_switch_to_literal_fragment (emit_state *);
 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
 static void xtensa_restore_emit_state (emit_state *);
-static void cache_literal_section
-  (seg_list *, const char *, segT *, bfd_boolean);
+static segT cache_literal_section (bfd_boolean);
 
 /* Import from elf32-xtensa.c in BFD library.  */
 
-extern char *xtensa_get_property_section_name (asection *, const char *);
+extern asection *xtensa_get_property_section (asection *, const char *);
 
 /* op_placement_info functions.  */
 
@@ -944,43 +962,16 @@ xtensa_clear_insn_labels (void)
 }
 
 
-/* The "loops_ok" argument is provided to allow ignoring labels that
-   define loop ends.  This fixes a bug where the NOPs to align a
-   loop opcode were included in a previous zero-cost loop:
-
-   loop a0, loopend
-     <loop1 body>
-   loopend:
-
-   loop a2, loopend2
-     <loop2 body>
-
-   would become:
-
-   loop a0, loopend
-     <loop1 body>
-     nop.n <===== bad!
-   loopend:
-
-   loop a2, loopend2
-     <loop2 body>
-
-   This argument is used to prevent moving the NOP to before the
-   loop-end label, which is what you want in this special case.  */
-
 static void
-xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
+xtensa_move_labels (fragS *new_frag, valueT new_offset)
 {
   sym_list *lit;
 
   for (lit = insn_labels; lit; lit = lit->next)
     {
       symbolS *lit_sym = lit->sym;
-      if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
-	{
-	  S_SET_VALUE (lit_sym, new_offset);
-	  symbol_set_frag (lit_sym, new_frag);
-	}
+      S_SET_VALUE (lit_sym, new_offset);
+      symbol_set_frag (lit_sym, new_frag);
     }
 }
 
@@ -1175,7 +1166,6 @@ xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
   directiveE directive;
   bfd_boolean negated;
   emit_state *state;
-  int len;
   lit_state *ls;
 
   get_directive (&directive, &negated);
@@ -1222,20 +1212,10 @@ xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
       assert (ls);
 
       *ls = default_lit_sections;
-
       directive_push (directive_literal_prefix, negated, ls);
 
-      /* Parse the new prefix from the input_line_pointer.  */
-      SKIP_WHITESPACE ();
-      len = strspn (input_line_pointer,
-		    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
-		    "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
-
       /* Process the new prefix.  */
-      xtensa_literal_prefix (input_line_pointer, len);
-
-      /* Skip the name in the input line.  */
-      input_line_pointer += len;
+      xtensa_literal_prefix ();
       break;
 
     case directive_freeregs:
@@ -1355,10 +1335,10 @@ xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
 	      /* Restore the default collection sections from saved state.  */
 	      s = (lit_state *) state;
 	      assert (s);
-
 	      default_lit_sections = *s;
 
-	      /* free the state storage */
+	      /* Free the state storage.  */
+	      free (s->lit_prefix);
 	      free (s);
 	      break;
 
@@ -1465,62 +1445,31 @@ xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
 
 
 static void
-xtensa_literal_prefix (char const *start, int len)
+xtensa_literal_prefix (void)
 {
-  char *name, *linkonce_suffix;
-  char *newname, *newname4;
-  size_t linkonce_len;
+  char *name;
+  int len;
+
+  /* Parse the new prefix from the input_line_pointer.  */
+  SKIP_WHITESPACE ();
+  len = strspn (input_line_pointer,
+		"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
+		"abcdefghijklmnopqrstuvwxyz_/0123456789.$");
 
   /* Get a null-terminated copy of the name.  */
   name = xmalloc (len + 1);
   assert (name);
-
-  strncpy (name, start, len);
+  strncpy (name, input_line_pointer, len);
   name[len] = 0;
 
-  /* Allocate the sections (interesting note: the memory pointing to
-     the name is actually used for the name by the new section). */
-
-  newname = xmalloc (len + strlen (".literal") + 1);
-  newname4 = xmalloc (len + strlen (".lit4") + 1);
+  /* Skip the name in the input line.  */
+  input_line_pointer += len;
 
-  linkonce_len = sizeof (".gnu.linkonce.") - 1;
-  if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
-      && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
-    {
-      strcpy (newname, ".gnu.linkonce.literal");
-      strcpy (newname4, ".gnu.linkonce.lit4");
+  default_lit_sections.lit_prefix = name;
 
-      strcat (newname, linkonce_suffix);
-      strcat (newname4, linkonce_suffix);
-    }
-  else
-    {
-      int suffix_pos = len;
-
-      /* If the section name ends with ".text", then replace that suffix
-	 instead of appending an additional suffix.  */
-      if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
-	suffix_pos -= 5;
-
-      strcpy (newname, name);
-      strcpy (newname4, name);
-
-      strcpy (newname + suffix_pos, ".literal");
-      strcpy (newname4 + suffix_pos, ".lit4");
-    }
-
-  /* Note that cache_literal_section does not create a segment if
-     it already exists.  */
+  /* Clear cached literal sections, since the prefix has changed.  */
   default_lit_sections.lit_seg = NULL;
   default_lit_sections.lit4_seg = NULL;
-
-  /* Canonicalizing section names allows renaming literal
-     sections to occur correctly.  */
-  default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
-  default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
-
-  free (name);
 }
 
 
@@ -1619,29 +1568,12 @@ xtensa_elf_cons (int nbytes)
 static bfd_reloc_code_real_type
 xtensa_elf_suffix (char **str_p, expressionS *exp_p)
 {
-  struct map_bfd
-  {
-    char *string;
-    int length;
-    bfd_reloc_code_real_type reloc;
-  };
-
   char ident[20];
   char *str = *str_p;
   char *str2;
   int ch;
   int len;
-  struct map_bfd *ptr;
-
-#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
-
-  static struct map_bfd mapping[] =
-  {
-    MAP ("l",		BFD_RELOC_LO16),
-    MAP ("h",		BFD_RELOC_HI16),
-    MAP ("plt",		BFD_RELOC_XTENSA_PLT),
-    { (char *) 0, 0,	BFD_RELOC_UNUSED }
-  };
+  struct suffix_reloc_map *ptr;
 
   if (*str++ != '@')
     return BFD_RELOC_NONE;
@@ -1658,10 +1590,10 @@ xtensa_elf_suffix (char **str_p, expressionS *exp_p)
   len = str2 - ident;
 
   ch = ident[0];
-  for (ptr = &mapping[0]; ptr->length > 0; ptr++)
-    if (ch == ptr->string[0]
+  for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++)
+    if (ch == ptr->suffix[0]
 	&& len == ptr->length
-	&& memcmp (ident, ptr->string, ptr->length) == 0)
+	&& memcmp (ident, ptr->suffix, ptr->length) == 0)
       {
 	/* Now check for "identifier@suffix+constant".  */
 	if (*str == '-' || *str == '+')
@@ -1689,6 +1621,49 @@ xtensa_elf_suffix (char **str_p, expressionS *exp_p)
 }
 
 
+/* Find the matching operator type.  */
+static unsigned char
+map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc)
+{
+  struct suffix_reloc_map *sfx;
+  unsigned char operator = (unsigned char) -1;
+  
+  for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
+    {
+      if (sfx->reloc == reloc)
+	{
+	  operator = sfx->operator;
+	  break;
+	}
+    }
+  assert (operator != (unsigned char) -1);
+  return operator;
+}
+
+
+/* Find the matching reloc type.  */
+static bfd_reloc_code_real_type
+map_operator_to_reloc (unsigned char operator)
+{
+  struct suffix_reloc_map *sfx;
+  bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
+
+  for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++)
+    {
+      if (sfx->operator == operator)
+	{
+	  reloc = sfx->reloc;
+	  break;
+	}
+    }
+
+  if (reloc == BFD_RELOC_UNUSED)
+    return BFD_RELOC_32;
+
+  return reloc;
+}
+
+
 static const char *
 expression_end (const char *name)
 {
@@ -1789,34 +1764,32 @@ expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
 	}
 
       if ((tok->X_op == O_constant || tok->X_op == O_symbol)
-	  && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
-	  && (reloc != BFD_RELOC_NONE))
+	  && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok))
+	      != BFD_RELOC_NONE))
 	{
-	  switch (reloc)
+	  if (reloc == BFD_RELOC_UNUSED)
 	    {
-	      default:
-	      case BFD_RELOC_UNUSED:
-		as_bad (_("unsupported relocation"));
-	        break;
-
-	      case BFD_RELOC_XTENSA_PLT:
-		tok->X_op = O_pltrel;
-		break;
+	      as_bad (_("unsupported relocation"));
+	      return;
+	    }
 
-	      case BFD_RELOC_LO16:
-		if (tok->X_op == O_constant)
+	  if (tok->X_op == O_constant)
+	    {
+	      switch (reloc)
+		{
+		case BFD_RELOC_LO16:
 		  tok->X_add_number &= 0xffff;
-		else
-		  tok->X_op = O_lo16;
-		break;
+		  return;
 
-	      case BFD_RELOC_HI16:
-		if (tok->X_op == O_constant)
+		case BFD_RELOC_HI16:
 		  tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
-		else
-		  tok->X_op = O_hi16;
-		break;
+		  return;
+
+		default:
+		  break;
+		}
 	    }
+	  tok->X_op = map_suffix_reloc_to_operator (reloc);
 	}
     }
   else
@@ -2340,9 +2313,6 @@ xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
   char *opname = *popname;
   bfd_boolean has_underbar = FALSE;
 
-  if (cur_vinsn.inside_bundle)
-    return 0;
-
   if (*opname == '_')
     {
       has_underbar = TRUE;
@@ -2385,7 +2355,11 @@ xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
       return 0;
     }
 
-  if (xtensa_nop_opcode == XTENSA_UNDEFINED
+  /* Don't do anything special with NOPs inside FLIX instructions.  They
+     are handled elsewhere.  Real NOP instructions are always available 
+     in configurations with FLIX, so this should never be an issue but
+     check for it anyway.  */
+  if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED
       && strcmp (opname, "nop") == 0)
     {
       if (use_transform () && !has_underbar && density_supported)
@@ -2589,7 +2563,7 @@ is_direct_call_opcode (xtensa_opcode opcode)
   xtensa_isa isa = xtensa_default_isa;
   int n, num_operands;
 
-  if (xtensa_opcode_is_call (isa, opcode) == 0)
+  if (xtensa_opcode_is_call (isa, opcode) != 1)
     return FALSE;
 
   num_operands = xtensa_opcode_num_operands (isa, opcode);
@@ -3312,7 +3286,7 @@ xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
   BuildOp *op;
   symbolS *sym;
 
-  memset (targ, 0, sizeof (TInsn));
+  tinsn_init (targ);
   targ->linenum = insn->linenum;
   switch (bi->typ)
     {
@@ -3524,7 +3498,33 @@ xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
 
 
 /* Relax the assembly instruction at least "min_steps".
-   Return the number of steps taken.  */
+   Return the number of steps taken.
+
+   For relaxation to correctly terminate, every relaxation chain must
+   terminate in one of two ways:
+
+   1.  If the chain from one instruction to the next consists entirely of
+       single instructions, then the chain *must* handle all possible
+       immediates without failing.  It must not ever fail because an
+       immediate is out of range.  The MOVI.N -> MOVI -> L32R relaxation
+       chain is one example.  L32R loads 32 bits, and there cannot be an
+       immediate larger than 32 bits, so it satisfies this condition.
+       Single instruction relaxation chains are as defined by
+       xg_is_single_relaxable_instruction.
+
+   2.  Otherwise, the chain must end in a multi-instruction expansion: e.g.,
+       BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
+
+   Strictly speaking, in most cases you can violate condition 1 and be OK
+   -- in particular when the last two instructions have the same single
+   size.  But nevertheless, you should guarantee the above two conditions.
+
+   We could fix this so that single-instruction expansions correctly
+   terminate when they can't handle the range, but the error messages are
+   worse, and it actually turns out that in every case but one (18-bit wide
+   branches), you need a multi-instruction expansion to get the full range
+   anyway.  And because 18-bit branches are handled identically to 15-bit
+   branches, there isn't any point in changing it.  */
 
 static int
 xg_assembly_relax (IStack *istack,
@@ -3537,12 +3537,9 @@ xg_assembly_relax (IStack *istack,
 {
   int steps_taken = 0;
 
-  /* assert (has no symbolic operands)
-     Some of its immeds don't fit.
-     Try to build a relaxed version.
-     This may go through a couple of stages
-     of single instruction transformations before
-     we get there.  */
+  /* Some of its immeds don't fit.  Try to build a relaxed version.
+     This may go through a couple of stages of single instruction
+     transformations before we get there.  */
 
   TInsn single_target;
   TInsn current_insn;
@@ -3680,8 +3677,8 @@ is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
   symbolS *sym;
   fragS *target_frag;
 
-  if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
-      && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
+  if (xtensa_opcode_is_branch (isa, insn->opcode) != 1
+      && xtensa_opcode_is_jump (isa, insn->opcode) != 1)
     return FALSE;
 
   for (i = 0; i < num_ops; i++)
@@ -3861,7 +3858,7 @@ xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
   TInsn new_insn;
   bfd_boolean do_expand;
 
-  memset (&new_insn, 0, sizeof (TInsn));
+  tinsn_init (&new_insn);
 
   /* Narrow it if we can.  xg_simplify_insn now does all the
      appropriate checking (e.g., for the density option).  */
@@ -3923,7 +3920,9 @@ xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
 
 
 /* Return TRUE if the section flags are marked linkonce
-   or the name is .gnu.linkonce*.  */
+   or the name is .gnu.linkonce.*.  */
+
+static int linkonce_len = sizeof (".gnu.linkonce.") - 1;
 
 static bfd_boolean
 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
@@ -3934,13 +3933,10 @@ get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
   link_once_flags = (flags & SEC_LINK_ONCE);
 
   /* Flags might not be set yet.  */
-  if (!link_once_flags)
-    {
-      static size_t len = sizeof ".gnu.linkonce.t.";
+  if (!link_once_flags
+      && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0)
+    link_once_flags = SEC_LINK_ONCE;
 
-      if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
-	link_once_flags = SEC_LINK_ONCE;
-    }
   return (link_once_flags != 0);
 }
 
@@ -3992,6 +3988,8 @@ xg_assemble_literal (/* const */ TInsn *insn)
 {
   emit_state state;
   symbolS *lit_sym = NULL;
+  bfd_reloc_code_real_type reloc;
+  char *p;
 
   /* size = 4 for L32R.  It could easily be larger when we move to
      larger constants.  Add a parameter later.  */
@@ -4027,19 +4025,24 @@ xg_assemble_literal (/* const */ TInsn *insn)
   frag_align (litalign, 0, 0);
   record_alignment (now_seg, litalign);
 
-  if (emit_val->X_op == O_pltrel)
+  switch (emit_val->X_op)
     {
-      char *p = frag_more (litsize);
+    case O_pltrel:
+      p = frag_more (litsize);
       xtensa_set_frag_assembly_state (frag_now);
+      reloc = map_operator_to_reloc (emit_val->X_op);
       if (emit_val->X_add_symbol)
 	emit_val->X_op = O_symbol;
       else
 	emit_val->X_op = O_constant;
       fix_new_exp (frag_now, p - frag_now->fr_literal,
-		   litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
+		   litsize, emit_val, 0, reloc);
+      break;
+
+    default:
+      emit_expr (emit_val, litsize);
+      break;
     }
-  else
-    emit_expr (emit_val, litsize);
 
   assert (frag_now->tc_frag_data.literal_frag == NULL);
   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
@@ -4160,12 +4163,6 @@ xg_add_opcode_fix (TInsn *tinsn,
   the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
 			 howto->pc_relative, reloc);
   the_fix->fx_no_overflow = 1;
-
-  if (expr->X_add_symbol
-      && (S_IS_EXTERNAL (expr->X_add_symbol)
-	  || S_IS_WEAK (expr->X_add_symbol)))
-    the_fix->fx_plt = TRUE;
-
   the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
   the_fix->tc_fix_data.X_add_number = expr->X_add_number;
   the_fix->tc_fix_data.slot = slot;
@@ -4410,7 +4407,8 @@ frag_format_size (const fragS *fragP)
 
   /* If an instruction is about to grow, return the longer size.  */
   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
-      || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
+      || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2
+      || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3)
     return 3;
 
   if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
@@ -4567,16 +4565,14 @@ xtensa_mark_literal_pool_location (void)
   emit_state s;
   fragS *pool_location;
 
-  if (use_literal_section && !directive_state[directive_absolute_literals])
+  if (use_literal_section)
     return;
 
-  frag_align (2, 0, 0);
-  record_alignment (now_seg, 2);
-
   /* We stash info in these frags so we can later move the literal's
      fixes into this frchain's fix list.  */
   pool_location = frag_now;
   frag_now->tc_frag_data.lit_frchain = frchain_now;
+  frag_now->tc_frag_data.literal_frag = frag_now;
   frag_variant (rs_machine_dependent, 0, 0,
 		RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
   xtensa_set_frag_assembly_state (frag_now);
@@ -4722,6 +4718,55 @@ relaxable_section (asection *sec)
 
 
 static void
+xtensa_mark_frags_for_org (void)
+{
+  segT *seclist;
+
+  /* Walk over each fragment of all of the current segments.  If we find
+     a .org frag in any of the segments, mark all frags prior to it as
+     "no transform", which will prevent linker optimizations from messing
+     up the .org distance.  This should be done after
+     xtensa_find_unmarked_state_frags, because we don't want to worry here
+     about that function trashing the data we save here.  */
+
+  for (seclist = &stdoutput->sections;
+       seclist && *seclist;
+       seclist = &(*seclist)->next)
+    {
+      segT sec = *seclist;
+      segment_info_type *seginfo;
+      fragS *fragP;
+      flagword flags;
+      flags = bfd_get_section_flags (stdoutput, sec);
+      if (flags & SEC_DEBUGGING)
+	continue;
+      if (!(flags & SEC_ALLOC))
+	continue;
+
+      seginfo = seg_info (sec);
+      if (seginfo && seginfo->frchainP)
+	{
+	  fragS *last_fragP = seginfo->frchainP->frch_root;
+	  for (fragP = seginfo->frchainP->frch_root; fragP;
+	       fragP = fragP->fr_next)
+	    {
+	      /* cvt_frag_to_fill has changed the fr_type of org frags to
+		 rs_fill, so use the value as cached in rs_subtype here.  */
+	      if (fragP->fr_subtype == RELAX_ORG)
+		{
+		  while (last_fragP != fragP->fr_next)
+		    {
+		      last_fragP->tc_frag_data.is_no_transform = TRUE;
+		      last_fragP = last_fragP->fr_next;
+		    }
+		}
+	    }
+	}
+    }
+}
+
+
+static void
 xtensa_find_unmarked_state_frags (void)
 {
   segT *seclist;
@@ -4948,12 +4993,8 @@ md_begin (void)
 
   linkrelax = 1;
 
-  /* Set up the .literal, .fini.literal and .init.literal sections.  */
+  /* Set up the literal sections.  */
   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
-  default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
-  default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
-  default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
-  default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
 
   subseg_set (current_section, current_subsec);
 
@@ -5044,7 +5085,7 @@ xtensa_frob_label (symbolS *sym)
 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
 
       xtensa_set_frag_assembly_state (frag_now);
-      xtensa_move_labels (frag_now, 0, TRUE);
+      xtensa_move_labels (frag_now, 0);
     }
 
   /* No target aligning in the absolute section.  */
@@ -5060,7 +5101,7 @@ xtensa_frob_label (symbolS *sym)
 		RELAX_DESIRE_ALIGN_IF_TARGET,
 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
       xtensa_set_frag_assembly_state (frag_now);
-      xtensa_move_labels (frag_now, 0, TRUE);
+      xtensa_move_labels (frag_now, 0);
     }
 
   /* We need to mark the following properties even if we aren't aligning.  */
@@ -5129,6 +5170,15 @@ xtensa_unrecognized_line (int ch)
 void
 xtensa_flush_pending_output (void)
 {
+  /* This line fixes a bug where automatically generated gstabs info
+     separates a function label from its entry instruction, ending up
+     with the literal position between the function label and the entry
+     instruction and crashing code.  It only happens with --gstabs and
+     --text-section-literals, and when several other obscure relaxation
+     conditions are met.  */
+  if (outputting_stabs_line_debug)
+    return;
+
   if (cur_vinsn.inside_bundle)
     as_bad (_("missing closing brace"));
 
@@ -5325,6 +5375,9 @@ xtensa_handle_align (fragS *fragP)
 	as_bad_where (fragP->fr_file, fragP->fr_line,
 		      _("unaligned entry instruction"));
     }
+
+  if (linkrelax && fragP->fr_type == rs_org)
+    fragP->fr_subtype = RELAX_ORG;
 }
 
 
@@ -5619,7 +5672,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg)
 	     readable when all branch targets are encoded in relocations.  */
 
 	  assert (fixP->fx_addsy);
-	  if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt
+	  if (S_GET_SEGMENT (fixP->fx_addsy) == seg
 	      && !S_FORCE_RELOC (fixP->fx_addsy, 1))
 	    {
 	      val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
@@ -6743,15 +6796,13 @@ xg_assemble_vliw_tokens (vliw_insn *vinsn)
 	frag_var (rs_machine_dependent, 0, 0,
 		  RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
       xtensa_set_frag_assembly_state (frag_now);
-
-      xtensa_move_labels (frag_now, 0, FALSE);
     }
 
   if (vinsn->slots[0].opcode == xtensa_entry_opcode
       && !vinsn->slots[0].is_specific_opcode)
     {
       xtensa_mark_literal_pool_location ();
-      xtensa_move_labels (frag_now, 0, TRUE);
+      xtensa_move_labels (frag_now, 0);
       frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
     }
 
@@ -6831,7 +6882,7 @@ xg_assemble_vliw_tokens (vliw_insn *vinsn)
      when converting them.  */
 
   /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
-  if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
+  if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1
       && !vinsn->slots[0].is_specific_opcode)
     {
       if (workaround_short_loop && use_transform ())
@@ -6917,6 +6968,7 @@ static void xtensa_fix_b_j_loop_end_frags (void);
 static void xtensa_fix_close_loop_end_frags (void);
 static void xtensa_fix_short_loop_frags (void);
 static void xtensa_sanity_check (void);
+static void xtensa_add_config_info (void);
 
 void
 xtensa_end (void)
@@ -6947,6 +6999,8 @@ xtensa_end (void)
   xtensa_mark_zcl_first_insns ();
 
   xtensa_sanity_check ();
+
+  xtensa_add_config_info ();
 }
 
 
@@ -6954,44 +7008,46 @@ static void
 xtensa_cleanup_align_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if ((fragP->fr_type == rs_align
-	       || fragP->fr_type == rs_align_code
-	       || (fragP->fr_type == rs_machine_dependent
-		   && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
-		       || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
-	      && fragP->fr_fix == 0)
-	    {
-	      fragS *next = fragP->fr_next;
-
-	      while (next
-		     && next->fr_fix == 0
-		     && next->fr_type == rs_machine_dependent
-		     && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
-		{
-		  frag_wane (next);
-		  next = next->fr_next;
-		}
-	    }
-	  /* If we don't widen branch targets, then they
-	     will be easier to align.  */
-	  if (fragP->tc_frag_data.is_branch_target
-	      && fragP->fr_opcode == fragP->fr_literal
-	      && fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_SLOTS
-	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
-	    frag_wane (fragP);
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_UNREACHABLE)
-	    fragP->tc_frag_data.is_unreachable = TRUE;
-	}
-    }
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if ((fragP->fr_type == rs_align
+		 || fragP->fr_type == rs_align_code
+		 || (fragP->fr_type == rs_machine_dependent
+		     && (fragP->fr_subtype == RELAX_DESIRE_ALIGN
+			 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
+		&& fragP->fr_fix == 0)
+	      {
+		fragS *next = fragP->fr_next;
+
+		while (next
+		       && next->fr_fix == 0
+		       && next->fr_type == rs_machine_dependent
+		       && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
+		  {
+		    frag_wane (next);
+		    next = next->fr_next;
+		  }
+	      }
+	    /* If we don't widen branch targets, then they
+	       will be easier to align.  */
+	    if (fragP->tc_frag_data.is_branch_target
+		&& fragP->fr_opcode == fragP->fr_literal
+		&& fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_SLOTS
+		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+	      frag_wane (fragP);
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_UNREACHABLE)
+	      fragP->tc_frag_data.is_unreachable = TRUE;
+	  }
+      }
 }
 
 
@@ -7004,26 +7060,28 @@ static void
 xtensa_fix_target_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
   /* When this routine is called, all of the subsections are still intact
      so we walk over subsections instead of sections.  */
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
 
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
-	    {
-	      if (next_frag_is_branch_target (fragP))
-		fragP->fr_subtype = RELAX_DESIRE_ALIGN;
-	      else
-		frag_wane (fragP);
-	    }
-	}
-    }
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
+	      {
+		if (next_frag_is_branch_target (fragP))
+		  fragP->fr_subtype = RELAX_DESIRE_ALIGN;
+		else
+		  frag_wane (fragP);
+	      }
+	  }
+      }
 }
 
 
@@ -7033,36 +7091,38 @@ static void
 xtensa_mark_narrow_branches (void)
 {
   frchainS *frchP;
+  asection *s;
 
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_SLOTS
-	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
-	    {
-	      vliw_insn vinsn;
-
-	      vinsn_from_chars (&vinsn, fragP->fr_opcode);
-	      tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
-
-	      if (vinsn.num_slots == 1
-		  && xtensa_opcode_is_branch (xtensa_default_isa,
-					      vinsn.slots[0].opcode)
-		  && xg_get_single_size (vinsn.slots[0].opcode) == 2
-		  && is_narrow_branch_guaranteed_in_range (fragP,
-							   &vinsn.slots[0]))
-		{
-		  fragP->fr_subtype = RELAX_SLOTS;
-		  fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
-		  fragP->tc_frag_data.is_aligning_branch = 1;
-		}
-	    }
-	}
-    }
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_SLOTS
+		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
+	      {
+		vliw_insn vinsn;
+
+		vinsn_from_chars (&vinsn, fragP->fr_opcode);
+		tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
+
+		if (vinsn.num_slots == 1
+		    && xtensa_opcode_is_branch (xtensa_default_isa,
+						vinsn.slots[0].opcode) == 1
+		    && xg_get_single_size (vinsn.slots[0].opcode) == 2
+		    && is_narrow_branch_guaranteed_in_range (fragP,
+							     &vinsn.slots[0]))
+		  {
+		    fragP->fr_subtype = RELAX_SLOTS;
+		    fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
+		    fragP->tc_frag_data.is_aligning_branch = 1;
+		  }
+	      }
+	  }
+      }
 }
 
 
@@ -7119,48 +7179,50 @@ static void
 xtensa_mark_zcl_first_insns (void)
 {
   frchainS *frchP;
+  asection *s;
 
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
-		  || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
-	    {
-	      /* Find the loop frag.  */
-	      fragS *targ_frag = next_non_empty_frag (fragP);
-	      /* Find the first insn frag.  */
-	      targ_frag = next_non_empty_frag (targ_frag);
-
-	      /* Of course, sometimes (mostly for toy test cases) a
-		 zero-cost loop instruction is the last in a section.  */
-	      if (targ_frag)
-		{
-		  targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
-		  /* Do not widen a frag that is the first instruction of a
-		     zero-cost loop.  It makes that loop harder to align.  */
-		  if (targ_frag->fr_type == rs_machine_dependent
-		      && targ_frag->fr_subtype == RELAX_SLOTS
-		      && (targ_frag->tc_frag_data.slot_subtypes[0]
-			  == RELAX_NARROW))
-		    {
-		      if (targ_frag->tc_frag_data.is_aligning_branch)
-			targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
-		      else
-			{
-			  frag_wane (targ_frag);
-			  targ_frag->tc_frag_data.slot_subtypes[0] = 0;
-			}
-		    }
-		}
-	      if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
-		frag_wane (fragP);
-	    }
-	}
-    }
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
+		    || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
+	      {
+		/* Find the loop frag.  */
+		fragS *targ_frag = next_non_empty_frag (fragP);
+		/* Find the first insn frag.  */
+		targ_frag = next_non_empty_frag (targ_frag);
+
+		/* Of course, sometimes (mostly for toy test cases) a
+		   zero-cost loop instruction is the last in a section.  */
+		if (targ_frag)
+		  {
+		    targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
+		    /* Do not widen a frag that is the first instruction of a
+		       zero-cost loop.  It makes that loop harder to align.  */
+		    if (targ_frag->fr_type == rs_machine_dependent
+			&& targ_frag->fr_subtype == RELAX_SLOTS
+			&& (targ_frag->tc_frag_data.slot_subtypes[0]
+			    == RELAX_NARROW))
+		      {
+			if (targ_frag->tc_frag_data.is_aligning_branch)
+			  targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
+			else
+			  {
+			    frag_wane (targ_frag);
+			    targ_frag->tc_frag_data.slot_subtypes[0] = 0;
+			  }
+		      }
+		  }
+		if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
+		  frag_wane (fragP);
+	      }
+	  }
+      }
 }
 
 
@@ -7175,30 +7237,32 @@ static void
 xtensa_fix_a0_b_retw_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
   /* When this routine is called, all of the subsections are still intact
      so we walk over subsections instead of sections.  */
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
 
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
-	    {
-	      if (next_instrs_are_b_retw (fragP))
-		{
-		  if (fragP->tc_frag_data.is_no_transform)
-		    as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
-		  else
-		    relax_frag_add_nop (fragP);
-		}
-	      frag_wane (fragP);
-	    }
-	}
-    }
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
+	      {
+		if (next_instrs_are_b_retw (fragP))
+		  {
+		    if (fragP->tc_frag_data.is_no_transform)
+		      as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
+		    else
+		      relax_frag_add_nop (fragP);
+		  }
+		frag_wane (fragP);
+	      }
+	  }
+      }
 }
 
 
@@ -7285,30 +7349,32 @@ static void
 xtensa_fix_b_j_loop_end_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
   /* When this routine is called, all of the subsections are still intact
      so we walk over subsections instead of sections.  */
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
 
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
-	    {
-	      if (next_instr_is_loop_end (fragP))
-		{
-		  if (fragP->tc_frag_data.is_no_transform)
-		    as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
-		  else
-		    relax_frag_add_nop (fragP);
-		}
-	      frag_wane (fragP);
-	    }
-	}
-    }
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
+	      {
+		if (next_instr_is_loop_end (fragP))
+		  {
+		    if (fragP->tc_frag_data.is_no_transform)
+		      as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
+		    else
+		      relax_frag_add_nop (fragP);
+		  }
+		frag_wane (fragP);
+	      }
+	  }
+      }
 }
 
 
@@ -7349,66 +7415,68 @@ static void
 xtensa_fix_close_loop_end_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
   /* When this routine is called, all of the subsections are still intact
      so we walk over subsections instead of sections.  */
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
 
-      fragS *current_target = NULL;
+	fragS *current_target = NULL;
 
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
-		  || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
+		    || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
 	      current_target = symbol_get_frag (fragP->fr_symbol);
 
-	  if (current_target
-	      && fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
-	    {
-	      offsetT min_bytes;
-	      int bytes_added = 0;
+	    if (current_target
+		&& fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
+	      {
+		offsetT min_bytes;
+		int bytes_added = 0;
 
 #define REQUIRED_LOOP_DIVIDING_BYTES 12
-	      /* Max out at 12.  */
-	      min_bytes = min_bytes_to_other_loop_end
-		(fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
-
-	      if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
-		{
-		  if (fragP->tc_frag_data.is_no_transform)
-		    as_bad (_("loop end too close to another loop end may trigger hardware errata"));
-		  else
-		    {
-		      while (min_bytes + bytes_added
-			     < REQUIRED_LOOP_DIVIDING_BYTES)
-			{
-			  int length = 3;
-
-			  if (fragP->fr_var < length)
-			    as_fatal (_("fr_var %lu < length %d"),
-				      (long) fragP->fr_var, length);
-			  else
-			    {
-			      assemble_nop (length,
-					    fragP->fr_literal + fragP->fr_fix);
-			      fragP->fr_fix += length;
-			      fragP->fr_var -= length;
-			    }
-			  bytes_added += length;
-			}
-		    }
-		}
-	      frag_wane (fragP);
-	    }
-	  assert (fragP->fr_type != rs_machine_dependent
-		  || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
-	}
-    }
+		/* Max out at 12.  */
+		min_bytes = min_bytes_to_other_loop_end
+		  (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
+
+		if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
+		  {
+		    if (fragP->tc_frag_data.is_no_transform)
+		      as_bad (_("loop end too close to another loop end may trigger hardware errata"));
+		    else
+		      {
+			while (min_bytes + bytes_added
+			       < REQUIRED_LOOP_DIVIDING_BYTES)
+			  {
+			    int length = 3;
+
+			    if (fragP->fr_var < length)
+			      as_fatal (_("fr_var %lu < length %d"),
+					(long) fragP->fr_var, length);
+			    else
+			      {
+				assemble_nop (length,
+					      fragP->fr_literal + fragP->fr_fix);
+				fragP->fr_fix += length;
+				fragP->fr_var -= length;
+			      }
+			    bytes_added += length;
+			  }
+		      }
+		  }
+		frag_wane (fragP);
+	      }
+	    assert (fragP->fr_type != rs_machine_dependent
+		    || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
+	  }
+      }
 }
 
 
@@ -7512,49 +7580,51 @@ static void
 xtensa_fix_short_loop_frags (void)
 {
   frchainS *frchP;
+  asection *s;
 
   /* When this routine is called, all of the subsections are still intact
      so we walk over subsections instead of sections.  */
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
-      fragS *current_target = NULL;
-      xtensa_opcode current_opcode = XTENSA_UNDEFINED;
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
+	fragS *current_target = NULL;
+	xtensa_opcode current_opcode = XTENSA_UNDEFINED;
 
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  if (fragP->fr_type == rs_machine_dependent
-	      && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
-		  || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
-	    {
-	      TInsn t_insn;
-	      fragS *loop_frag = next_non_empty_frag (fragP);
-	      tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
-	      current_target = symbol_get_frag (fragP->fr_symbol);
-	      current_opcode = t_insn.opcode;
-	      assert (xtensa_opcode_is_loop (xtensa_default_isa,
-					     current_opcode));
-	    }
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
+		    || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
+	      {
+		TInsn t_insn;
+		fragS *loop_frag = next_non_empty_frag (fragP);
+		tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
+		current_target = symbol_get_frag (fragP->fr_symbol);
+		current_opcode = t_insn.opcode;
+		assert (xtensa_opcode_is_loop (xtensa_default_isa,
+					       current_opcode) == 1);
+	      }
 
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
-	    {
-	      if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
-		  && (branch_before_loop_end (fragP->fr_next)
-		      || (workaround_all_short_loops
-			  && current_opcode != XTENSA_UNDEFINED
-			  && current_opcode != xtensa_loop_opcode)))
-		{
-		  if (fragP->tc_frag_data.is_no_transform)
-		    as_bad (_("loop containing less than three instructions may trigger hardware errata"));
-		  else
-		    relax_frag_add_nop (fragP);
-		}
-	      frag_wane (fragP);
-	    }
-	}
-    }
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
+	      {
+		if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
+		    && (branch_before_loop_end (fragP->fr_next)
+			|| (workaround_all_short_loops
+			    && current_opcode != XTENSA_UNDEFINED
+			    && current_opcode != xtensa_loop_opcode)))
+		  {
+		    if (fragP->tc_frag_data.is_no_transform)
+		      as_bad (_("loop containing less than three instructions may trigger hardware errata"));
+		    else
+		      relax_frag_add_nop (fragP);
+		  }
+		frag_wane (fragP);
+	      }
+	  }
+      }
 }
 
 
@@ -7697,50 +7767,51 @@ xtensa_sanity_check (void)
 {
   char *file_name;
   unsigned line;
-
   frchainS *frchP;
+  asection *s;
 
   as_where (&file_name, &line);
-  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
-    {
-      fragS *fragP;
-
-      /* Walk over all of the fragments in a subsection.  */
-      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
-	{
-	  /* Currently we only check for empty loops here.  */
-	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_IMMED)
-	    {
-	      static xtensa_insnbuf insnbuf = NULL;
-	      TInsn t_insn;
-
-	      if (fragP->fr_opcode != NULL)
-		{
-		  if (!insnbuf)
-		    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-		  tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
-		  tinsn_immed_from_frag (&t_insn, fragP, 0);
+  for (s = stdoutput->sections; s; s = s->next)
+    for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next)
+      {
+	fragS *fragP;
 
-		  if (xtensa_opcode_is_loop (xtensa_default_isa,
-					     t_insn.opcode) == 1)
-		    {
-		      if (is_empty_loop (&t_insn, fragP))
-			{
-			  new_logical_line (fragP->fr_file, fragP->fr_line);
-			  as_bad (_("invalid empty loop"));
-			}
-		      if (!is_local_forward_loop (&t_insn, fragP))
-			{
-			  new_logical_line (fragP->fr_file, fragP->fr_line);
-			  as_bad (_("loop target does not follow "
-				    "loop instruction in section"));
-			}
-		    }
-		}
-	    }
-	}
-    }
+	/* Walk over all of the fragments in a subsection.  */
+	for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	  {
+	    if (fragP->fr_type == rs_machine_dependent
+		&& fragP->fr_subtype == RELAX_SLOTS 
+		&& fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
+	      {
+		static xtensa_insnbuf insnbuf = NULL;
+		TInsn t_insn;
+
+		if (fragP->fr_opcode != NULL)
+		  {
+		    if (!insnbuf)
+		      insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
+		    tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
+		    tinsn_immed_from_frag (&t_insn, fragP, 0);
+
+		    if (xtensa_opcode_is_loop (xtensa_default_isa,
+					       t_insn.opcode) == 1)
+		      {
+			if (is_empty_loop (&t_insn, fragP))
+			  {
+			    new_logical_line (fragP->fr_file, fragP->fr_line);
+			    as_bad (_("invalid empty loop"));
+			  }
+			if (!is_local_forward_loop (&t_insn, fragP))
+			  {
+			    new_logical_line (fragP->fr_file, fragP->fr_line);
+			    as_bad (_("loop target does not follow "
+				      "loop instruction in section"));
+			  }
+		      }
+		  }
+	      }
+	  }
+      }
   new_logical_line (file_name, line);
 }
 
@@ -7806,7 +7877,7 @@ is_local_forward_loop (const TInsn *insn, fragS *fragP)
   if (insn->insn_type != ITYPE_INSN)
     return FALSE;
 
-  if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
+  if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
     return FALSE;
 
   if (insn->ntok <= LOOP_IMMED_OPN)
@@ -7838,6 +7909,55 @@ is_local_forward_loop (const TInsn *insn, fragS *fragP)
   return FALSE;
 }
 
+
+#define XTINFO_NAME "Xtensa_Info"
+#define XTINFO_NAMESZ 12
+#define XTINFO_TYPE 1
+
+static void
+xtensa_add_config_info (void)
+{
+  asection *info_sec;
+  char *data, *p;
+  int sz;
+
+  info_sec = subseg_new (".xtensa.info", 0);
+  bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY);
+
+  data = xmalloc (100);
+  sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
+	   XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI);
+  sz = strlen (data) + 1;
+
+  /* Add enough null terminators to pad to a word boundary.  */
+  do
+    data[sz++] = 0;
+  while ((sz & 3) != 0);
+
+  /* Follow the standard note section layout:
+     First write the length of the name string.  */
+  p = frag_more (4);
+  md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4);
+
+  /* Next comes the length of the "descriptor", i.e., the actual data.  */
+  p = frag_more (4);
+  md_number_to_chars (p, (valueT) sz, 4);
+
+  /* Write the note type.  */
+  p = frag_more (4);
+  md_number_to_chars (p, (valueT) XTINFO_TYPE, 4);
+
+  /* Write the name field.  */
+  p = frag_more (XTINFO_NAMESZ);
+  memcpy (p, XTINFO_NAME, XTINFO_NAMESZ);
+
+  /* Finally, write the descriptor.  */
+  p = frag_more (sz);
+  memcpy (p, data, sz);
+
+  free (data);
+}
+
 
 /* Alignment Functions.  */
 
@@ -8228,6 +8348,7 @@ xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
 	    case RELAX_IMMED:
 	    case RELAX_IMMED_STEP1:
 	    case RELAX_IMMED_STEP2:
+	    case RELAX_IMMED_STEP3:
 	      /* Place the immediate.  */
 	      new_stretch += relax_frag_immed
 		(now_seg, fragP, stretch,
@@ -8612,7 +8733,7 @@ future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
     c          0      2         1 (case 5b makes this case unnecessary)
    6a          2      0         0
     b          1      0         3
-    c          0      1         4 (case 6b makes this case unneccesary)
+    c          0      1         4 (case 6b makes this case unnecessary)
     d          1      1         1 (case 6a makes this case unnecessary)
     e          0      2         2 (case 6a makes this case unnecessary)
     f          0      3         0 (case 6a makes this case unnecessary)
@@ -8792,7 +8913,7 @@ relax_frag_immed (segT segP,
   tinsn = cur_vinsn.slots[slot];
   tinsn_immed_from_frag (&tinsn, fragP, slot);
 
-  if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
+  if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1)
     return 0;
 
   if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
@@ -8945,6 +9066,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
 	    case RELAX_IMMED:
 	    case RELAX_IMMED_STEP1:
 	    case RELAX_IMMED_STEP2:
+	    case RELAX_IMMED_STEP3:
 	      /* Place the immediate.  */
 	      convert_frag_immed
 		(sec, fragp,
@@ -9292,10 +9414,7 @@ convert_frag_immed (segT segP,
 	      /* Add a fixup.  */
 	      target_seg = S_GET_SEGMENT (lit_sym);
 	      assert (target_seg);
-	      if (tinsn->tok[0].X_op == O_pltrel)
-		reloc_type = BFD_RELOC_XTENSA_PLT;
-	      else
-		reloc_type = BFD_RELOC_32;
+	      reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op);
 	      fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
 				  &tinsn->tok[0], FALSE, reloc_type);
 	      break;
@@ -9476,11 +9595,6 @@ convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
       target = 0;
     }
 
-  know (symbolP);
-  know (symbolP->sy_frag);
-  know (!(S_GET_SEGMENT (symbolP) == absolute_section)
-	|| symbol_get_frag (symbolP) == &zero_address_frag);
-
   loop_length = target - (fragP->fr_address + fragP->fr_fix);
   loop_length_hi = loop_length & ~0x0ff;
   loop_length_lo = loop_length & 0x0ff;
@@ -9679,15 +9793,17 @@ xtensa_move_literals (void)
   sym_list *lit;
 
   mark_literal_frags (literal_head->next);
-  mark_literal_frags (init_literal_head->next);
-  mark_literal_frags (fini_literal_head->next);
 
   if (use_literal_section)
     return;
 
-  segment = literal_head->next;
-  while (segment)
+  for (segment = literal_head->next; segment; segment = segment->next)
     {
+      /* Keep the literals for .init and .fini in separate sections.  */
+      if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME)
+	  || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME))
+	continue;
+
       frchain_from = seg_info (segment->seg)->frchainP;
       search_frag = frchain_from->frch_root;
       literal_pool = NULL;
@@ -9728,17 +9844,14 @@ xtensa_move_literals (void)
 	      frchain_to = literal_pool->tc_frag_data.lit_frchain;
 	      assert (frchain_to);
 	    }
-	  insert_after = literal_pool;
-
-	  while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
-	    insert_after = insert_after->fr_next;
-
+	  insert_after = literal_pool->tc_frag_data.literal_frag;
 	  dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
 
 	  *frag_splice = next_frag;
 	  search_frag->fr_next = insert_after->fr_next;
 	  insert_after->fr_next = search_frag;
 	  search_frag->tc_frag_data.lit_seg = dest_seg;
+	  literal_pool->tc_frag_data.literal_frag = search_frag;
 
 	  /* Now move any fixups associated with this frag to the
 	     right section.  */
@@ -9771,7 +9884,6 @@ xtensa_move_literals (void)
 	}
       frchain_from->fix_tail = NULL;
       xtensa_restore_emit_state (&state);
-      segment = segment->next;
     }
 
   /* Now fix up the SEGMENT value for all the literal symbols.  */
@@ -9852,8 +9964,6 @@ xtensa_reorder_segments (void)
   /* Now that we have the last section, push all the literal
      sections to the end.  */
   xtensa_reorder_seg_list (literal_head, last_sec);
-  xtensa_reorder_seg_list (init_literal_head, last_sec);
-  xtensa_reorder_seg_list (fini_literal_head, last_sec);
 
   /* Now perform the final error check.  */
   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
@@ -9871,10 +9981,8 @@ xtensa_switch_to_literal_fragment (emit_state *result)
 {
   if (directive_state[directive_absolute_literals])
     {
-      cache_literal_section (0, default_lit_sections.lit4_seg_name,
-			     &default_lit_sections.lit4_seg, FALSE);
-      xtensa_switch_section_emit_state (result,
-					default_lit_sections.lit4_seg, 0);
+      segT lit4_seg = cache_literal_section (TRUE);
+      xtensa_switch_section_emit_state (result, lit4_seg, 0);
     }
   else
     xtensa_switch_to_non_abs_literal_fragment (result);
@@ -9888,17 +9996,11 @@ xtensa_switch_to_literal_fragment (emit_state *result)
 static void
 xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
 {
-  /* When we mark a literal pool location, we want to put a frag in
-     the literal pool that points to it.  But to do that, we want to
-     switch_to_literal_fragment.  But literal sections don't have
-     literal pools, so their location is always null, so we would
-     recurse forever.  This is kind of hacky, but it works.  */
-
   static bfd_boolean recursive = FALSE;
   fragS *pool_location = get_literal_pool_location (now_seg);
+  segT lit_seg;
   bfd_boolean is_init =
     (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
-
   bfd_boolean is_fini =
     (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
 
@@ -9908,39 +10010,20 @@ xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
       && !is_init && ! is_fini)
     {
       as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
+
+      /* When we mark a literal pool location, we want to put a frag in
+	 the literal pool that points to it.  But to do that, we want to
+	 switch_to_literal_fragment.  But literal sections don't have
+	 literal pools, so their location is always null, so we would
+	 recurse forever.  This is kind of hacky, but it works.  */
+
       recursive = TRUE;
       xtensa_mark_literal_pool_location ();
       recursive = FALSE;
     }
 
-  /* Special case: If we are in the ".fini" or ".init" section, then
-     we will ALWAYS be generating to the ".fini.literal" and
-     ".init.literal" sections.  */
-
-  if (is_init)
-    {
-      cache_literal_section (init_literal_head,
-			     default_lit_sections.init_lit_seg_name,
-			     &default_lit_sections.init_lit_seg, TRUE);
-      xtensa_switch_section_emit_state (result,
-					default_lit_sections.init_lit_seg, 0);
-    }
-  else if (is_fini)
-    {
-      cache_literal_section (fini_literal_head,
-			     default_lit_sections.fini_lit_seg_name,
-			     &default_lit_sections.fini_lit_seg, TRUE);
-      xtensa_switch_section_emit_state (result,
-					default_lit_sections.fini_lit_seg, 0);
-    }
-  else
-    {
-      cache_literal_section (literal_head,
-			     default_lit_sections.lit_seg_name,
-			     &default_lit_sections.lit_seg, TRUE);
-      xtensa_switch_section_emit_state (result,
-					default_lit_sections.lit_seg, 0);
-    }
+  lit_seg = cache_literal_section (FALSE);
+  xtensa_switch_section_emit_state (result, lit_seg, 0);
 
   if (!use_literal_section
       && !is_init && !is_fini
@@ -9984,49 +10067,129 @@ xtensa_restore_emit_state (emit_state *state)
 }
 
 
-/* Get a segment of a given name.  If the segment is already
-   present, return it; otherwise, create a new one.  */
+/* Predicate function used to look up a section in a particular group.  */
 
-static void
-cache_literal_section (seg_list *head,
-		       const char *name,
-		       segT *pseg,
-		       bfd_boolean is_code)
+static bfd_boolean
+match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
 {
-  segT current_section = now_seg;
-  int current_subsec = now_subseg;
-  segT seg;
+  const char *gname = inf;
+  const char *group_name = elf_group_name (sec);
+  
+  return (group_name == gname
+	  || (group_name != NULL
+	      && gname != NULL
+	      && strcmp (group_name, gname) == 0));
+}
 
-  if (*pseg != 0)
-    return;
 
-  /* Check if the named section exists.  */
-  for (seg = stdoutput->sections; seg; seg = seg->next)
+/* Get the literal section to be used for the current text section.
+   The result may be cached in the default_lit_sections structure.  */
+
+static segT
+cache_literal_section (bfd_boolean use_abs_literals)
+{
+  const char *text_name, *group_name = 0;
+  char *base_name, *name, *suffix;
+  segT *pcached;
+  segT seg, current_section;
+  int current_subsec;
+  bfd_boolean linkonce = FALSE;
+
+  /* Save the current section/subsection.  */
+  current_section = now_seg;
+  current_subsec = now_subseg;
+
+  /* Clear the cached values if they are no longer valid.  */
+  if (now_seg != default_lit_sections.current_text_seg)
     {
-      if (!strcmp (segment_name (seg), name))
-	break;
+      default_lit_sections.current_text_seg = now_seg;
+      default_lit_sections.lit_seg = NULL;
+      default_lit_sections.lit4_seg = NULL;
     }
 
-  if (!seg)
+  /* Check if the literal section is already cached.  */
+  if (use_abs_literals)
+    pcached = &default_lit_sections.lit4_seg;
+  else
+    pcached = &default_lit_sections.lit_seg;
+
+  if (*pcached)
+    return *pcached;
+  
+  text_name = default_lit_sections.lit_prefix;
+  if (! text_name || ! *text_name)
     {
-      /* Create a new literal section.  */
-      seg = subseg_new (name, (subsegT) 0);
-      if (head)
+      text_name = segment_name (current_section);
+      group_name = elf_group_name (current_section);
+      linkonce = (current_section->flags & SEC_LINK_ONCE) != 0;
+    }
+
+  base_name = use_abs_literals ? ".lit4" : ".literal";
+  if (group_name)
+    {
+      name = xmalloc (strlen (base_name) + strlen (group_name) + 2);
+      sprintf (name, "%s.%s", base_name, group_name);
+    }
+  else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0)
+    {
+      suffix = strchr (text_name + linkonce_len, '.');
+
+      name = xmalloc (linkonce_len + strlen (base_name) + 1
+		      + (suffix ? strlen (suffix) : 0));
+      strcpy (name, ".gnu.linkonce");
+      strcat (name, base_name);
+      if (suffix)
+	strcat (name, suffix);
+      linkonce = TRUE;
+    }
+  else
+    {
+      /* If the section name ends with ".text", then replace that suffix
+	 instead of appending an additional suffix.  */
+      size_t len = strlen (text_name);
+      if (len >= 5 && strcmp (text_name + len - 5, ".text") == 0)
+	len -= 5;
+
+      name = xmalloc (len + strlen (base_name) + 1);
+      strcpy (name, text_name);
+      strcpy (name + len, base_name);
+    }
+
+  /* Canonicalize section names to allow renaming literal sections.
+     The group name, if any, came from the current text section and
+     has already been canonicalized.  */
+  name = tc_canonicalize_symbol_name (name);
+
+  seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group,
+				    (void *) group_name);
+  if (! seg)
+    {
+      flagword flags;
+
+      seg = subseg_force_new (name, 0);
+
+      if (! use_abs_literals)
 	{
-	  /* Add the newly created literal segment to the specified list.  */
+	  /* Add the newly created literal segment to the list.  */
 	  seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
 	  n->seg = seg;
-	  n->next = head->next;
-	  head->next = n;
+	  n->next = literal_head->next;
+	  literal_head->next = n;
 	}
-      bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
-			     SEC_READONLY | SEC_ALLOC | SEC_LOAD
-			     | (is_code ? SEC_CODE : SEC_DATA));
+
+      flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD
+	       | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0)
+	       | (use_abs_literals ? SEC_DATA : SEC_CODE));
+
+      elf_group_name (seg) = group_name;
+
+      bfd_set_section_flags (stdoutput, seg, flags);
       bfd_set_section_alignment (stdoutput, seg, 2);
     }
 
-  *pseg = seg;
+  *pcached = seg;
   subseg_set (current_section, current_subsec);
+  return seg;
 }
 
 
@@ -10045,7 +10208,6 @@ static void xtensa_create_property_segments
 static void xtensa_create_xproperty_segments
   (frag_flags_fn, const char *, xt_section_type);
 static segment_info_type *retrieve_segment_info (segT);
-static segT retrieve_xtensa_section (char *);
 static bfd_boolean section_has_property (segT, frag_predicate);
 static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
 static void add_xt_block_frags
@@ -10063,10 +10225,9 @@ void
 xtensa_post_relax_hook (void)
 {
   xtensa_move_seg_list_to_beginning (literal_head);
-  xtensa_move_seg_list_to_beginning (init_literal_head);
-  xtensa_move_seg_list_to_beginning (fini_literal_head);
 
   xtensa_find_unmarked_state_frags ();
+  xtensa_mark_frags_for_org ();
 
   xtensa_create_property_segments (get_frag_is_literal,
 				   NULL,
@@ -10120,9 +10281,8 @@ xtensa_create_property_segments (frag_predicate property_function,
 
       if (section_has_property (sec, property_function))
 	{
-	  char *property_section_name =
-	    xtensa_get_property_section_name (sec, section_name_base);
-	  segT insn_sec = retrieve_xtensa_section (property_section_name);
+	  segT insn_sec = 
+	    xtensa_get_property_section (sec, section_name_base);
 	  segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
 	  xtensa_block_info **xt_blocks =
 	    &xt_seg_info->tc_segment_info_data.blocks[sec_type];
@@ -10253,9 +10413,8 @@ xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
 
       if (section_has_xproperty (sec, flag_fn))
 	{
-	  char *property_section_name =
-	    xtensa_get_property_section_name (sec, section_name_base);
-	  segT insn_sec = retrieve_xtensa_section (property_section_name);
+	  segT insn_sec =
+	    xtensa_get_property_section (sec, section_name_base);
 	  segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
 	  xtensa_block_info **xt_blocks =
 	    &xt_seg_info->tc_segment_info_data.blocks[sec_type];
@@ -10384,7 +10543,6 @@ retrieve_segment_info (segT seg)
       frchainP->frch_root = NULL;
       frchainP->frch_last = NULL;
       frchainP->frch_next = NULL;
-      frchainP->frch_seg = seg;
       frchainP->frch_subseg = 0;
       frchainP->fix_root = NULL;
       frchainP->fix_tail = NULL;
@@ -10400,29 +10558,6 @@ retrieve_segment_info (segT seg)
 }
 
 
-static segT
-retrieve_xtensa_section (char *sec_name)
-{
-  bfd *abfd = stdoutput;
-  flagword flags, out_flags, link_once_flags;
-  segT s;
-
-  flags = bfd_get_section_flags (abfd, now_seg);
-  link_once_flags = (flags & SEC_LINK_ONCE);
-  if (link_once_flags)
-    link_once_flags |= (flags & SEC_LINK_DUPLICATES);
-  out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags);
-
-  s = bfd_make_section_old_way (abfd, sec_name);
-  if (s == NULL)
-    as_bad (_("could not create section %s"), sec_name);
-  if (!bfd_set_section_flags (abfd, s, out_flags))
-    as_bad (_("invalid flag combination on section %s"), sec_name);
-
-  return s;
-}
-
-
 static bfd_boolean
 section_has_property (segT sec, frag_predicate property_function)
 {
@@ -10553,6 +10688,9 @@ get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
   xtensa_frag_flags_init (prop_flags);
   if (fragP->tc_frag_data.is_literal)
     prop_flags->is_literal = TRUE;
+  if (fragP->tc_frag_data.is_specific_opcode
+      || fragP->tc_frag_data.is_no_transform)
+    prop_flags->is_no_transform = TRUE;
   if (fragP->tc_frag_data.is_unreachable)
     prop_flags->is_unreachable = TRUE;
   else if (fragP->tc_frag_data.is_insn)
@@ -10562,9 +10700,6 @@ get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
 	prop_flags->insn.is_loop_target = TRUE;
       if (fragP->tc_frag_data.is_branch_target)
 	prop_flags->insn.is_branch_target = TRUE;
-      if (fragP->tc_frag_data.is_specific_opcode
-	  || fragP->tc_frag_data.is_no_transform)
-	prop_flags->insn.is_no_transform = TRUE;
       if (fragP->tc_frag_data.is_no_density)
 	prop_flags->insn.is_no_density = TRUE;
       if (fragP->tc_frag_data.use_absolute_literals)
@@ -10602,8 +10737,8 @@ frag_flags_to_number (const frag_flags *prop_flags)
 
   if (prop_flags->insn.is_no_density)
     num |= XTENSA_PROP_INSN_NO_DENSITY;
-  if (prop_flags->insn.is_no_transform)
-    num |= XTENSA_PROP_INSN_NO_TRANSFORM;
+  if (prop_flags->is_no_transform)
+    num |= XTENSA_PROP_NO_TRANSFORM;
   if (prop_flags->insn.is_no_reorder)
     num |= XTENSA_PROP_INSN_NO_REORDER;
   if (prop_flags->insn.is_abslit)
@@ -10642,8 +10777,8 @@ xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
       if (prop_flags_1->insn.is_no_density !=
 	  prop_flags_2->insn.is_no_density)
 	return FALSE;
-      if (prop_flags_1->insn.is_no_transform !=
-	  prop_flags_2->insn.is_no_transform)
+      if (prop_flags_1->is_no_transform !=
+	  prop_flags_2->is_no_transform)
 	return FALSE;
       if (prop_flags_1->insn.is_no_reorder !=
 	  prop_flags_2->insn.is_no_reorder)
@@ -10930,7 +11065,7 @@ istack_push_space (IStack *stack)
   TInsn *insn;
   assert (!istack_full (stack));
   insn = &stack->insn[rec];
-  memset (insn, 0, sizeof (TInsn));
+  tinsn_init (insn);
   stack->ninsn++;
   return insn;
 }
@@ -10945,7 +11080,7 @@ istack_pop (IStack *stack)
   int rec = stack->ninsn - 1;
   assert (!istack_empty (stack));
   stack->ninsn--;
-  memset (&stack->insn[rec], 0, sizeof (TInsn));
+  tinsn_init (&stack->insn[rec]);
 }
 
 
@@ -10958,17 +11093,6 @@ tinsn_init (TInsn *dst)
 }
 
 
-/* Get the ``num''th token of the TInsn.
-   It is illegal to call this if num > insn->ntoks.  */
-
-expressionS *
-tinsn_get_tok (TInsn *insn, int num)
-{
-  assert (num < insn->ntok);
-  return &insn->tok[num];
-}
-
-
 /* Return TRUE if ANY of the operands in the insn are symbolic.  */
 
 static bfd_boolean
diff --git a/gas/config/tc-xtensa.h b/gas/config/tc-xtensa.h
index 71f1ebbd3b38..40653213d311 100644
--- a/gas/config/tc-xtensa.h
+++ b/gas/config/tc-xtensa.h
@@ -1,5 +1,5 @@
 /* tc-xtensa.h -- Header file for tc-xtensa.c.
-   Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -131,18 +131,20 @@ enum xtensa_relax_statesE
 
   RELAX_IMMED,
   /* The last instruction in this fragment (at->fr_opcode) contains
-     the value defined by fr_symbol (fr_offset = 0).  If the value
-     does not fit, use the specified expansion.  This is similar to
-     "NARROW", except that these may not be expanded in order to align
-     code.  */
+     an immediate or symbol.  If the value does not fit, relax the
+     opcode using expansions from the relax table.  */
 
   RELAX_IMMED_STEP1,
   /* The last instruction in this fragment (at->fr_opcode) contains a
-     literal.  It has already been expanded at least 1 step.  */
+     literal.  It has already been expanded 1 step.  */
 
   RELAX_IMMED_STEP2,
   /* The last instruction in this fragment (at->fr_opcode) contains a
-     literal.  It has already been expanded at least 2 steps.  */
+     literal.  It has already been expanded 2 steps.  */
+
+  RELAX_IMMED_STEP3,
+  /* The last instruction in this fragment (at->fr_opcode) contains a
+     literal.  It has already been expanded 3 steps.  */
 
   RELAX_SLOTS,
   /* There are instructions within the last VLIW instruction that need
@@ -167,12 +169,19 @@ enum xtensa_relax_statesE
      branch is relaxed, then this frag will be converted to a
      RELAX_UNREACHABLE frag.  */
 
+  RELAX_ORG,
+  /* This marks the location as having previously been an rs_org frag.  
+     rs_org frags are converted to fill-zero frags immediately after
+     relaxation.  However, we need to remember where they were so we can
+     prevent the linker from changing the size of any frag between the
+     section start and the org frag.  */
+
   RELAX_NONE
 };
 
 /* This is used as a stopper to bound the number of steps that
    can be taken.  */
-#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP2 - RELAX_IMMED)
+#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP3 - RELAX_IMMED)
 
 struct xtensa_frag_type
 {
@@ -221,7 +230,9 @@ struct xtensa_frag_type
      variable points to the frag where the literal will be stored.  For
      literal frags, this variable points to the nearest literal pool
      location frag.  This literal frag will be moved to after this
-     location.  */
+     location.  For RELAX_LITERAL_POOL_BEGIN frags, this field points
+     to the frag immediately before the corresponding RELAX_LITERAL_POOL_END
+     frag, to make moving frags for this literal pool efficient.  */
   fragS *literal_frag;
 
   /* The destination segment for literal frags.  (Note that this is only
@@ -371,6 +382,9 @@ extern char *xtensa_section_rename (char *);
 #define MD_APPLY_SYM_VALUE(FIX) 0
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 
+/* Use line number format that is amenable to linker relaxation.  */
+#define DWARF2_USE_FIXED_ADVANCE_PC (linkrelax != 0)
+
 
 /* Resource reservation info functions.  */
 
diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
index 413e336a2c89..73b3fc831507 100644
--- a/gas/config/tc-z80.c
+++ b/gas/config/tc-z80.c
@@ -1,5 +1,5 @@
 /* tc-z80.c -- Assemble code for the Zilog Z80 and ASCII R800
-   Copyright 2005 Free Software Foundation, Inc.
+   Copyright 2005, 2006 Free Software Foundation, Inc.
    Contributed by Arnold Metselaar <arnold_m@operamail.com>
 
    This file is part of GAS, the GNU Assembler.
@@ -20,12 +20,8 @@
    02110-1301, USA.  */
 
 #include "as.h"
-#include "listing.h"
-#include "bfd.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
-#include "symbols.h"
-#include "libiberty.h"
 
 /* Exported constants.  */
 const char comment_chars[] = ";\0";
diff --git a/gas/config/tc-z8k.c b/gas/config/tc-z8k.c
index 355ac12c2bbb..e3893668ff10 100644
--- a/gas/config/tc-z8k.c
+++ b/gas/config/tc-z8k.c
@@ -1,6 +1,6 @@
 /* tc-z8k.c -- Assemble code for the Zilog Z800n
    Copyright 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, 2002, 2003,
-   2005 Free Software Foundation, Inc.
+   2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -21,10 +21,7 @@
 
 /* Written By Steve Chamberlain <sac@cygnus.com>.  */
 
-#include <stdio.h>
-
 #include "as.h"
-#include "bfd.h"
 #include "safe-ctype.h"
 #define DEFINE_TABLE
 #include "opcodes/z8k-opc.h"
@@ -199,19 +196,34 @@ static int the_ctrl;
 static int the_flags;
 static int the_interrupt;
 
+/* Determine register number.  src points to the ascii number
+   (after "rl", "rh", "r", "rr", or "rq").  If a character
+   outside the set of {0,',',')','('} follows the number,
+   return NULL to indicate that it's not a valid register
+   number.  */
+
 static char *
 whatreg (unsigned int *reg, char *src)
 {
+  unsigned int new_reg;
+
+  /* src[0] is already known to be a digit.  */
   if (ISDIGIT (src[1]))
     {
-      *reg = (src[0] - '0') * 10 + src[1] - '0';
-      return src + 2;
+      new_reg = (src[0] - '0') * 10 + src[1] - '0';
+      src += 2;
     }
   else
     {
-      *reg = (src[0] - '0');
-      return src + 1;
+      new_reg = (src[0] - '0');
+      src += 1;
     }
+
+  if (src[0] != 0 && src[0] != ',' && src[0] != '(' && src[0] != ')')
+    return NULL;
+
+  *reg = new_reg;
+  return src;
 }
 
 /* Parse operands
@@ -234,7 +246,7 @@ whatreg (unsigned int *reg, char *src)
 static char *
 parse_reg (char *src, int *mode, unsigned int *reg)
 {
-  char *res = 0;
+  char *res = NULL;
   char regno;
 
   /* Check for stack pointer "sp" alias.  */
@@ -260,9 +272,11 @@ parse_reg (char *src, int *mode, unsigned int *reg)
       if (src[1] == 'r' || src[1] == 'R')
 	{
 	  if (src[2] < '0' || src[2] > '9')
-	    return res;	 /* Assume no register name but a label starting with 'rr'.  */
+	    return NULL;	/* Assume no register name but a label starting with 'rr'.  */
 	  *mode = CLASS_REG_LONG;
 	  res = whatreg (reg, src + 2);
+	  if (res == NULL)
+	    return NULL;	/* Not a valid register name.  */
 	  regno = *reg;
 	  if (regno > 14)
 	    as_bad (_("register rr%d out of range"), regno);
@@ -272,9 +286,11 @@ parse_reg (char *src, int *mode, unsigned int *reg)
       else if (src[1] == 'h' || src[1] == 'H')
 	{
 	  if (src[2] < '0' || src[2] > '9')
-	    return res;	 /* Assume no register name but a label starting with 'rh'.  */
+	    return NULL;	/* Assume no register name but a label starting with 'rh'.  */
 	  *mode = CLASS_REG_BYTE;
 	  res = whatreg (reg, src + 2);
+	  if (res == NULL)
+	    return NULL;	/* Not a valid register name.  */
 	  regno = *reg;
 	  if (regno > 7)
 	    as_bad (_("register rh%d out of range"), regno);
@@ -282,9 +298,11 @@ parse_reg (char *src, int *mode, unsigned int *reg)
       else if (src[1] == 'l' || src[1] == 'L')
 	{
 	  if (src[2] < '0' || src[2] > '9')
-	    return res;	 /* Assume no register name but a label starting with 'rl'.  */
+	    return NULL;	/* Assume no register name but a label starting with 'rl'.  */
 	  *mode = CLASS_REG_BYTE;
 	  res = whatreg (reg, src + 2);
+	  if (res == NULL)
+	    return NULL;	/* Not a valid register name.  */
 	  regno = *reg;
 	  if (regno > 7)
 	    as_bad (_("register rl%d out of range"), regno);
@@ -293,9 +311,11 @@ parse_reg (char *src, int *mode, unsigned int *reg)
       else if (src[1] == 'q' || src[1] == 'Q')
 	{
 	  if (src[2] < '0' || src[2] > '9')
-	    return res;	 /* Assume no register name but a label starting with 'rq'.  */
+	    return NULL;	/* Assume no register name but a label starting with 'rq'.  */
 	  *mode = CLASS_REG_QUAD;
 	  res = whatreg (reg, src + 2);
+	  if (res == NULL)
+	    return NULL;	/* Not a valid register name.  */
 	  regno = *reg;
 	  if (regno > 12)
 	    as_bad (_("register rq%d out of range"), regno);
@@ -305,9 +325,11 @@ parse_reg (char *src, int *mode, unsigned int *reg)
       else
 	{
 	  if (src[1] < '0' || src[1] > '9')
-	    return res;	 /* Assume no register name but a label starting with 'r'.  */
+	    return NULL;	/* Assume no register name but a label starting with 'r'.  */
 	  *mode = CLASS_REG_WORD;
 	  res = whatreg (reg, src + 1);
+	  if (res == NULL)
+	    return NULL;	/* Not a valid register name.  */
 	  regno = *reg;
 	  if (regno > 15)
 	    as_bad (_("register r%d out of range"), regno);
diff --git a/gas/config/te-pep.h b/gas/config/te-pep.h
new file mode 100644
index 000000000000..164b22d98403
--- /dev/null
+++ b/gas/config/te-pep.h
@@ -0,0 +1,10 @@
+#define TE_PEP
+#define COFF_WITH_pex64
+
+#define TE_PE
+#define LEX_AT (LEX_BEGIN_NAME | LEX_NAME) /* Can have @'s inside labels.  */
+
+/* The PE format supports long section names.  */
+#define COFF_LONG_SECTION_NAMES
+
+#include "obj-format.h"
diff --git a/gas/config/xtensa-istack.h b/gas/config/xtensa-istack.h
index 7d2471abd465..a6ec40b8388d 100644
--- a/gas/config/xtensa-istack.h
+++ b/gas/config/xtensa-istack.h
@@ -1,5 +1,5 @@
 /* Declarations for stacks of tokenized Xtensa instructions.
-   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -48,8 +48,6 @@ typedef struct tinsn_struct
   expressionS tok[MAX_INSN_ARGS];
   unsigned linenum;
 
-  struct fixP *fixup;
-
   /* Filled out by relaxation_requirements:  */
   enum xtensa_relax_statesE subtype;
   int literal_space;
@@ -79,7 +77,6 @@ void istack_pop (IStack *);
 
 /* TInsn utilities.  */
 void tinsn_init (TInsn *);
-expressionS *tinsn_get_tok (TInsn *, int);
 
 
 /* vliw_insn: bundles of TInsns.  */
diff --git a/gas/config/xtensa-relax.c b/gas/config/xtensa-relax.c
index a0848820eb36..779c9076a424 100644
--- a/gas/config/xtensa-relax.c
+++ b/gas/config/xtensa-relax.c
@@ -1,5 +1,5 @@
 /* Table of relaxations for Xtensa assembly.
-   Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -49,8 +49,8 @@
    The replacement language
    INSN_REPL      ::= INSN_LABEL_LIT ( ';' INSN_LABEL_LIT )*
    INSN_LABEL_LIT ::= INSN_TEMPL
-                      | 'LABEL' num
-                      | 'LITERAL' num ' ' VARIABLE
+                      | 'LABEL'
+                      | 'LITERAL' VARIABLE
 
    The operands in a PRECOND must be constants or variables bound by
    the INSN_PATTERN.
@@ -72,12 +72,12 @@
    movi.n instruction to the wide movi instruction.
 
    A more complex example of a branch around:
-   {"beqz %as,%label", "bnez %as,%LABEL0;j %label;LABEL0"}
+   {"beqz %as,%label", "bnez %as,%LABEL;j %label;LABEL"}
    would convert a branch to a negated branch to the following instruction
    with a jump to the original label.
 
    An Xtensa-specific example that generates a literal:
-   {"movi %at,%imm", "LITERAL0 %imm; l32r %at,%LITERAL0"}
+   {"movi %at,%imm", "LITERAL %imm; l32r %at,%LITERAL"}
    will convert a movi instruction to an l32r of a literal
    literal defined in the literal pool.
 
@@ -87,7 +87,7 @@
    when the first and second operands are not the same as specified
    by the "| %at!=%as" precondition clause.
    {"l32i %at,%as,%imm | %at!=%as",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l32i %at,%at,0"}
+   "LITERAL %imm; l32r %at,%LITERAL; add %at,%at,%as; l32i %at,%at,0"}
 
    There is special case for loop instructions here, but because we do
    not currently have the ability to represent the difference of two
@@ -247,7 +247,10 @@ struct string_pattern_pair_struct
      addi.n a4, 0x1010
      => addi a4, 0x1010
      => addmi a4, 0x1010
-     => addmi a4, 0x1000, addi a4, 0x10.  */
+     => addmi a4, 0x1000, addi a4, 0x10.  
+
+   See the comments in xg_assembly_relax for some important details
+   regarding how these chains must be built.  */
 
 static string_pattern_pair widen_spec_list[] =
 {
@@ -268,7 +271,7 @@ static string_pattern_pair widen_spec_list[] =
 
   /* Widening with literals or const16.  */
   {"movi %at,%imm ? IsaUseL32R ",
-   "LITERAL0 %imm; l32r %at,%LITERAL0"},
+   "LITERAL %imm; l32r %at,%LITERAL"},
   {"movi %at,%imm ? IsaUseConst16",
    "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm)"},
 
@@ -279,19 +282,19 @@ static string_pattern_pair widen_spec_list[] =
 
   /* In the end convert to either an l32r or const16.  */
   {"addmi %ar,%as,%imm | %ar!=%as ? IsaUseL32R",
-   "LITERAL0 %imm; l32r %ar,%LITERAL0; add %ar,%as,%ar"},
+   "LITERAL %imm; l32r %ar,%LITERAL; add %ar,%as,%ar"},
   {"addmi %ar,%as,%imm | %ar!=%as ? IsaUseConst16",
    "const16 %ar,HI16U(%imm); const16 %ar,LOW16U(%imm); add %ar,%as,%ar"},
 
   /* Widening the load instructions with too-large immediates */
   {"l8ui %at,%as,%imm | %at!=%as ? IsaUseL32R",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l8ui %at,%at,0"},
+   "LITERAL %imm; l32r %at,%LITERAL; add %at,%at,%as; l8ui %at,%at,0"},
   {"l16si %at,%as,%imm | %at!=%as ? IsaUseL32R",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l16si %at,%at,0"},
+   "LITERAL %imm; l32r %at,%LITERAL; add %at,%at,%as; l16si %at,%at,0"},
   {"l16ui %at,%as,%imm | %at!=%as ? IsaUseL32R",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l16ui %at,%at,0"},
+   "LITERAL %imm; l32r %at,%LITERAL; add %at,%at,%as; l16ui %at,%at,0"},
   {"l32i %at,%as,%imm | %at!=%as ? IsaUseL32R",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l32i %at,%at,0"},
+   "LITERAL %imm; l32r %at,%LITERAL; add %at,%at,%as; l32i %at,%at,0"},
 
   /* Widening load instructions with const16s.  */
   {"l8ui %at,%as,%imm | %at!=%as ? IsaUseConst16",
@@ -307,7 +310,7 @@ static string_pattern_pair widen_spec_list[] =
      hardcoded into its use is a modification of the final operand in
      the instruction in bytes 9 and 12.  */
   {"loop %as,%label | %as!=1 ? IsaUseLoops",
-   "loop %as,%LABEL0;"
+   "loop %as,%LABEL;"
    "rsr.lend    %as;"		/* LEND */
    "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
@@ -316,11 +319,11 @@ static string_pattern_pair widen_spec_list[] =
    "isync;"
    "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
-   "LABEL0"},
+   "LABEL"},
   {"loopgtz %as,%label | %as!=1 ? IsaUseLoops",
    "beqz    %as,%label;"
    "bltz    %as,%label;"
-   "loopgtz %as,%LABEL0;"
+   "loopgtz %as,%LABEL;"
    "rsr.lend    %as;"		/* LEND */
    "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
@@ -329,10 +332,10 @@ static string_pattern_pair widen_spec_list[] =
    "isync;"
    "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
-   "LABEL0"},
+   "LABEL"},
   {"loopnez %as,%label | %as!=1 ? IsaUseLoops",
    "beqz     %as,%label;"
-   "loopnez %as,%LABEL0;"
+   "loopnez %as,%LABEL;"
    "rsr.lend    %as;"		/* LEND */
    "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
@@ -341,7 +344,7 @@ static string_pattern_pair widen_spec_list[] =
    "isync;"
    "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
-   "LABEL0"},
+   "LABEL"},
 
   /* Relaxing to wide branches.  Order is important here.  With wide
      branches, there is more than one correct relaxation for an
@@ -376,54 +379,81 @@ static string_pattern_pair widen_spec_list[] =
   
   /* Widening branch comparisons eq/ne to zero.  Prefer relaxing to narrow
      branches if the density option is available.  */
-  {"beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL0;j %label;LABEL0"},
-  {"bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL0;j %label;LABEL0"},
-  {"beqz %as,%label", "bnez %as,%LABEL0;j %label;LABEL0"},
-  {"bnez %as,%label", "beqz %as,%LABEL0;j %label;LABEL0"},
+  {"beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL;j %label;LABEL"},
+  {"bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL;j %label;LABEL"},
+  {"beqz %as,%label", "bnez %as,%LABEL;j %label;LABEL"},
+  {"bnez %as,%label", "beqz %as,%LABEL;j %label;LABEL"},
+  {"WIDE.beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL;j %label;LABEL"},
+  {"WIDE.bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL;j %label;LABEL"},
+  {"WIDE.beqz %as,%label", "bnez %as,%LABEL;j %label;LABEL"},
+  {"WIDE.bnez %as,%label", "beqz %as,%LABEL;j %label;LABEL"},
 
   /* Widening expect-taken branches.  */
-  {"beqzt %as,%label ? IsaUsePredictedBranches", "bnez %as,%LABEL0;j %label;LABEL0"},
-  {"bnezt %as,%label ? IsaUsePredictedBranches", "beqz %as,%LABEL0;j %label;LABEL0"},
-  {"beqt %as,%at,%label ? IsaUsePredictedBranches", "bne %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bnet %as,%at,%label ? IsaUsePredictedBranches", "beq %as,%at,%LABEL0;j %label;LABEL0"},
+  {"beqzt %as,%label ? IsaUsePredictedBranches", "bnez %as,%LABEL;j %label;LABEL"},
+  {"bnezt %as,%label ? IsaUsePredictedBranches", "beqz %as,%LABEL;j %label;LABEL"},
+  {"beqt %as,%at,%label ? IsaUsePredictedBranches", "bne %as,%at,%LABEL;j %label;LABEL"},
+  {"bnet %as,%at,%label ? IsaUsePredictedBranches", "beq %as,%at,%LABEL;j %label;LABEL"},
 
   /* Widening branches from the Xtensa boolean option.  */
-  {"bt %bs,%label ? IsaUseBooleans", "bf %bs,%LABEL0;j %label;LABEL0"},
-  {"bf %bs,%label ? IsaUseBooleans", "bt %bs,%LABEL0;j %label;LABEL0"},
+  {"bt %bs,%label ? IsaUseBooleans", "bf %bs,%LABEL;j %label;LABEL"},
+  {"bf %bs,%label ? IsaUseBooleans", "bt %bs,%LABEL;j %label;LABEL"},
 
   /* Other branch-around-jump widenings.  */
-  {"bgez %as,%label", "bltz %as,%LABEL0;j %label;LABEL0"},
-  {"bltz %as,%label", "bgez %as,%LABEL0;j %label;LABEL0"},
-  {"beqi %as,%imm,%label", "bnei %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bnei %as,%imm,%label", "beqi %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bgei %as,%imm,%label", "blti %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"blti %as,%imm,%label", "bgei %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bgeui %as,%imm,%label", "bltui %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bltui %as,%imm,%label", "bgeui %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bbci %as,%imm,%label", "bbsi %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"bbsi %as,%imm,%label", "bbci %as,%imm,%LABEL0;j %label;LABEL0"},
-  {"beq %as,%at,%label", "bne %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bne %as,%at,%label", "beq %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bge %as,%at,%label", "blt %as,%at,%LABEL0;j %label;LABEL0"},
-  {"blt %as,%at,%label", "bge %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bgeu %as,%at,%label", "bltu %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bltu %as,%at,%label", "bgeu %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bany %as,%at,%label", "bnone %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bnone %as,%at,%label", "bany %as,%at,%LABEL0;j %label;LABEL0"},
-  {"ball %as,%at,%label", "bnall %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bnall %as,%at,%label", "ball %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bbc %as,%at,%label", "bbs %as,%at,%LABEL0;j %label;LABEL0"},
-  {"bbs %as,%at,%label", "bbc %as,%at,%LABEL0;j %label;LABEL0"},
+  {"bgez %as,%label", "bltz %as,%LABEL;j %label;LABEL"},
+  {"bltz %as,%label", "bgez %as,%LABEL;j %label;LABEL"},
+  {"beqi %as,%imm,%label", "bnei %as,%imm,%LABEL;j %label;LABEL"},
+  {"bnei %as,%imm,%label", "beqi %as,%imm,%LABEL;j %label;LABEL"},
+  {"bgei %as,%imm,%label", "blti %as,%imm,%LABEL;j %label;LABEL"},
+  {"blti %as,%imm,%label", "bgei %as,%imm,%LABEL;j %label;LABEL"},
+  {"bgeui %as,%imm,%label", "bltui %as,%imm,%LABEL;j %label;LABEL"},
+  {"bltui %as,%imm,%label", "bgeui %as,%imm,%LABEL;j %label;LABEL"},
+  {"bbci %as,%imm,%label", "bbsi %as,%imm,%LABEL;j %label;LABEL"},
+  {"bbsi %as,%imm,%label", "bbci %as,%imm,%LABEL;j %label;LABEL"},
+  {"beq %as,%at,%label", "bne %as,%at,%LABEL;j %label;LABEL"},
+  {"bne %as,%at,%label", "beq %as,%at,%LABEL;j %label;LABEL"},
+  {"bge %as,%at,%label", "blt %as,%at,%LABEL;j %label;LABEL"},
+  {"blt %as,%at,%label", "bge %as,%at,%LABEL;j %label;LABEL"},
+  {"bgeu %as,%at,%label", "bltu %as,%at,%LABEL;j %label;LABEL"},
+  {"bltu %as,%at,%label", "bgeu %as,%at,%LABEL;j %label;LABEL"},
+  {"bany %as,%at,%label", "bnone %as,%at,%LABEL;j %label;LABEL"},
+  {"bnone %as,%at,%label", "bany %as,%at,%LABEL;j %label;LABEL"},
+  {"ball %as,%at,%label", "bnall %as,%at,%LABEL;j %label;LABEL"},
+  {"bnall %as,%at,%label", "ball %as,%at,%LABEL;j %label;LABEL"},
+  {"bbc %as,%at,%label", "bbs %as,%at,%LABEL;j %label;LABEL"},
+  {"bbs %as,%at,%label", "bbc %as,%at,%LABEL;j %label;LABEL"},
+
+  {"WIDE.bgez %as,%label", "bltz %as,%LABEL;j %label;LABEL"},
+  {"WIDE.bltz %as,%label", "bgez %as,%LABEL;j %label;LABEL"},
+  {"WIDE.beqi %as,%imm,%label", "bnei %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bnei %as,%imm,%label", "beqi %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bgei %as,%imm,%label", "blti %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.blti %as,%imm,%label", "bgei %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bgeui %as,%imm,%label", "bltui %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bltui %as,%imm,%label", "bgeui %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bbci %as,%imm,%label", "bbsi %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.bbsi %as,%imm,%label", "bbci %as,%imm,%LABEL;j %label;LABEL"},
+  {"WIDE.beq %as,%at,%label", "bne %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bne %as,%at,%label", "beq %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bge %as,%at,%label", "blt %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.blt %as,%at,%label", "bge %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bgeu %as,%at,%label", "bltu %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bltu %as,%at,%label", "bgeu %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bany %as,%at,%label", "bnone %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bnone %as,%at,%label", "bany %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.ball %as,%at,%label", "bnall %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bnall %as,%at,%label", "ball %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bbc %as,%at,%label", "bbs %as,%at,%LABEL;j %label;LABEL"},
+  {"WIDE.bbs %as,%at,%label", "bbc %as,%at,%LABEL;j %label;LABEL"},
 
   /* Expanding calls with literals.  */
   {"call0 %label,%ar0 ? IsaUseL32R",
-   "LITERAL0 %label; l32r a0,%LITERAL0; callx0 a0,%ar0"},
+   "LITERAL %label; l32r a0,%LITERAL; callx0 a0,%ar0"},
   {"call4 %label,%ar4 ? IsaUseL32R",
-   "LITERAL0 %label; l32r a4,%LITERAL0; callx4 a4,%ar4"},
+   "LITERAL %label; l32r a4,%LITERAL; callx4 a4,%ar4"},
   {"call8 %label,%ar8 ? IsaUseL32R",
-   "LITERAL0 %label; l32r a8,%LITERAL0; callx8 a8,%ar8"},
+   "LITERAL %label; l32r a8,%LITERAL; callx8 a8,%ar8"},
   {"call12 %label,%ar12 ? IsaUseL32R",
-   "LITERAL0 %label; l32r a12,%LITERAL0; callx12 a12,%ar12"},
+   "LITERAL %label; l32r a12,%LITERAL; callx12 a12,%ar12"},
 
   /* Expanding calls with const16.  */
   {"call0 %label,%ar0 ? IsaUseConst16",
@@ -615,26 +645,26 @@ append_op (BuildInstr *bi, BuildOp *b_op)
 
 
 static void
-append_literal_op (BuildInstr *bi, unsigned op1, unsigned litnum)
+append_literal_op (BuildInstr *bi, unsigned op1)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
   b_op->op_num = op1;
   b_op->typ = OP_LITERAL;
-  b_op->op_data = litnum;
+  b_op->op_data = 0;
   b_op->next = NULL;
   append_op (bi, b_op);
 }
 
 
 static void
-append_label_op (BuildInstr *bi, unsigned op1, unsigned labnum)
+append_label_op (BuildInstr *bi, unsigned op1)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
   b_op->op_num = op1;
   b_op->typ = OP_LABEL;
-  b_op->op_data = labnum;
+  b_op->op_data = 0;
   b_op->next = NULL;
   append_op (bi, b_op);
 }
@@ -982,30 +1012,6 @@ parse_constant (const char *in, unsigned *val_p)
 }
 
 
-/* Match a pattern like "foo1" with
-   parse_id_constant("foo1", "foo", &num).
-   This may also be used to just match a number.  */
-
-static bfd_boolean
-parse_id_constant (const char *in, const char *name, unsigned *val_p)
-{
-  unsigned namelen = 0;
-  const char *p;
-
-  if (in == NULL)
-    return FALSE;
-
-  if (name != NULL)
-    namelen = strlen (name);
-
-  if (name != NULL && strncmp (in, name, namelen) != 0)
-    return FALSE;
-
-  p = &in[namelen];
-  return parse_constant (p, val_p);
-}
-
-
 static bfd_boolean
 parse_special_fn (const char *name,
 		  const char **fn_name_p,
@@ -1594,12 +1600,11 @@ build_transition (insn_pattern *initial_insn,
 
   precond_e *precond;
   insn_repl_e *r;
-  unsigned label_count = 0;
-  unsigned max_label_count = 0;
-  bfd_boolean has_label = FALSE;
-  unsigned literal_count = 0;
 
-  opcode = xtensa_opcode_lookup (isa, initial_insn->t.opcode_name);
+  if (!wide_branch_opcode (initial_insn->t.opcode_name, ".w18", &opcode) 
+      && !wide_branch_opcode (initial_insn->t.opcode_name, ".w15", &opcode))
+    opcode = xtensa_opcode_lookup (isa, initial_insn->t.opcode_name);
+
   if (opcode == XTENSA_UNDEFINED)
     {
       /* It is OK to not be able to translate some of these opcodes.  */
@@ -1661,35 +1666,26 @@ build_transition (insn_pattern *initial_insn,
 	{
 	  op1 = get_opmatch (&initial_insn->t.operand_map, precond->opname1);
 	  if (op1 == NULL)
-	    {
-	      as_fatal (_("opcode '%s': no bound opname '%s' "
-			  "for precondition in '%s'"),
-			xtensa_opcode_name (isa, opcode),
-			precond->opname1, from_string);
-	      return NULL;
-	    }
+	    as_fatal (_("opcode '%s': no bound opname '%s' "
+			"for precondition in '%s'"),
+		      xtensa_opcode_name (isa, opcode),
+		      precond->opname1, from_string);
 	}
 
       if (precond->opname2)
 	{
 	  op2 = get_opmatch (&initial_insn->t.operand_map, precond->opname2);
 	  if (op2 == NULL)
-	    {
-	      as_fatal (_("opcode '%s': no bound opname '%s' "
-			  "for precondition in %s"),
-		       xtensa_opcode_name (isa, opcode),
-		       precond->opname2, from_string);
-	      return NULL;
-	    }
+	    as_fatal (_("opcode '%s': no bound opname '%s' "
+			"for precondition in %s"),
+		      xtensa_opcode_name (isa, opcode),
+		      precond->opname2, from_string);
 	}
 
       if (op1 == NULL && op2 == NULL)
-	{
-	  as_fatal (_("opcode '%s': precondition only contains "
-		      "constants in '%s'"),
-		    xtensa_opcode_name (isa, opcode), from_string);
-	  return NULL;
-	}
+	as_fatal (_("opcode '%s': precondition only contains "
+		    "constants in '%s'"),
+		  xtensa_opcode_name (isa, opcode), from_string);
       else if (op1 != NULL && op2 != NULL)
 	append_value_condition (tr, precond->cmpop,
 				op1->operand_num, op2->operand_num);
@@ -1704,12 +1700,11 @@ build_transition (insn_pattern *initial_insn,
   tr->options = clone_req_option_list (initial_insn->options);
 
   /* Generate the replacement instructions.  Some of these
-     "instructions" are actually labels and literals.  The literals
-     must be defined in order 0..n and a literal must be defined
-     (e.g., "LITERAL0 %imm") before use (e.g., "%LITERAL0").  The
-     labels must be defined in order, but they can be used before they
-     are defined.  Also there are a number of special operands (e.g.,
-     HI24S).  */
+     "instructions" are actually labels and literals.  There can be at
+     most one literal and at most one label.  A literal must be defined
+     (e.g., "LITERAL %imm") before use (e.g., "%LITERAL").  The labels
+     can be used before they are defined.  Also there are a number of
+     special operands (e.g., HI24S).  */
 
   for (r = replace_insns->head; r != NULL; r = r->next)
     {
@@ -1717,14 +1712,12 @@ build_transition (insn_pattern *initial_insn,
       const char *opcode_name;
       int operand_count;
       opname_map_e *op;
-      unsigned idnum = 0;
       const char *fn_name;
       const char *operand_arg_name;
 
       bi = (BuildInstr *) xmalloc (sizeof (BuildInstr));
       append_build_insn (tr, bi);
 
-      bi->id = 0;
       bi->opcode = XTENSA_UNDEFINED;
       bi->ops = NULL;
       bi->next = NULL;
@@ -1732,24 +1725,15 @@ build_transition (insn_pattern *initial_insn,
       opcode_name = r->t.opcode_name;
       operand_count = insn_templ_operand_count (&r->t);
 
-      if (parse_id_constant (opcode_name, "LITERAL", &idnum))
+      if (strcmp (opcode_name, "LITERAL") == 0)
 	{
 	  bi->typ = INSTR_LITERAL_DEF;
-	  bi->id = idnum;
-	  if (idnum != literal_count)
-	    as_fatal (_("generated literals must be numbered consecutively"));
-	  ++literal_count;
 	  if (operand_count != 1)
 	    as_fatal (_("expected one operand for generated literal"));
-
 	}
-      else if (parse_id_constant (opcode_name, "LABEL", &idnum))
+      else if (strcmp (opcode_name, "LABEL") == 0)
 	{
 	  bi->typ = INSTR_LABEL_DEF;
-	  bi->id = idnum;
-	  if (idnum != label_count)
-	    as_fatal (_("generated labels must be numbered consecutively"));
-	  ++label_count;
 	  if (operand_count != 0)
 	    as_fatal (_("expected 0 operands for generated label"));
 	}
@@ -1783,22 +1767,12 @@ build_transition (insn_pattern *initial_insn,
 
 	  if (op_is_constant (op))
 	    append_constant_op (bi, op->operand_num, op_get_constant (op));
-	  else if (parse_id_constant (op->operand_name, "%LITERAL", &idnum))
-	    {
-	      if (idnum >= literal_count)
-		as_fatal (_("opcode %s: replacement "
-			    "literal %d >= literal_count(%d)"),
-			  opcode_name, idnum, literal_count);
-	      append_literal_op (bi, op->operand_num, idnum);
-	    }
-	  else if (parse_id_constant (op->operand_name, "%LABEL", &idnum))
-	    {
-	      has_label = TRUE;
-	      if (idnum > max_label_count)
-		max_label_count = idnum;
-	      append_label_op (bi, op->operand_num, idnum);
-	    }
-	  else if (parse_id_constant (op->operand_name, "a", &idnum))
+	  else if (strcmp (op->operand_name, "%LITERAL") == 0)
+	    append_literal_op (bi, op->operand_num);
+	  else if (strcmp (op->operand_name, "%LABEL") == 0)
+	    append_label_op (bi, op->operand_num);
+	  else if (op->operand_name[0] == 'a'
+		   && parse_constant (op->operand_name + 1, &idnum))
 	    append_constant_op (bi, op->operand_num, idnum);
 	  else if (op->operand_name[0] == '%')
 	    {
@@ -1806,14 +1780,9 @@ build_transition (insn_pattern *initial_insn,
 	      orig_op = get_opmatch (&initial_insn->t.operand_map,
 				     op->operand_name);
 	      if (orig_op == NULL)
-		{
-		  as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
-			    opcode_name, op->operand_name, to_string);
-
-		  append_constant_op (bi, op->operand_num, 0);
-		}
-	      else
-		append_field_op (bi, op->operand_num, orig_op->operand_num);
+		as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
+			  opcode_name, op->operand_name, to_string);
+	      append_field_op (bi, op->operand_num, orig_op->operand_num);
 	    }
 	  else if (parse_special_fn (op->operand_name,
 				     &fn_name, &operand_arg_name))
@@ -1837,30 +1806,16 @@ build_transition (insn_pattern *initial_insn,
 	      orig_op = get_opmatch (&initial_insn->t.operand_map,
 				     operand_arg_name);
 	      if (orig_op == NULL)
-		{
-		  as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
-			    opcode_name, op->operand_name, to_string);
-		  append_constant_op (bi, op->operand_num, 0);
-		}
-	      else
-		append_user_fn_field_op (bi, op->operand_num,
-					 typ, orig_op->operand_num);
+		as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
+			  opcode_name, op->operand_name, to_string);
+	      append_user_fn_field_op (bi, op->operand_num,
+				       typ, orig_op->operand_num);
 	    }
 	  else
-	    {
-	      as_fatal (_("opcode %s: could not parse operand '%s' in '%s'"),
-			opcode_name, op->operand_name, to_string);
-	      append_constant_op (bi, op->operand_num, 0);
-	    }
+	    as_fatal (_("opcode %s: could not parse operand '%s' in '%s'"),
+		      opcode_name, op->operand_name, to_string);
 	}
     }
-  if (has_label && max_label_count >= label_count)
-    {
-      as_fatal (_("opcode %s: replacement label %d >= label_count(%d)"),
-		xtensa_opcode_name (isa, opcode),
-		max_label_count, label_count);
-      return NULL;
-    }
 
   return tr;
 }
@@ -1898,20 +1853,11 @@ build_transition_table (const string_pattern_pair *transitions,
 
       init_insn_pattern (&initial_insn);
       if (!parse_insn_pattern (from_string, &initial_insn))
-	{
-	  as_fatal (_("could not parse INSN_PATTERN '%s'"), from_string);
-	  clear_insn_pattern (&initial_insn);
-	  continue;
-	}
+	as_fatal (_("could not parse INSN_PATTERN '%s'"), from_string);
 
       init_insn_repl (&replace_insns);
       if (!parse_insn_repl (to_string, &replace_insns))
-	{
-	  as_fatal (_("could not parse INSN_REPL '%s'"), to_string);
-	  clear_insn_pattern (&initial_insn);
-	  clear_insn_repl (&replace_insns);
-	  continue;
-	}
+	as_fatal (_("could not parse INSN_REPL '%s'"), to_string);
 
       if (transition_applies (&initial_insn, from_string, to_string))
 	{
diff --git a/gas/config/xtensa-relax.h b/gas/config/xtensa-relax.h
index 6ae11e379cef..fa1abb070207 100644
--- a/gas/config/xtensa-relax.h
+++ b/gas/config/xtensa-relax.h
@@ -1,5 +1,5 @@
 /* Table of relaxations for Xtensa assembly.
-   Copyright 2003, 2004 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -135,10 +135,7 @@ struct build_op
 				   OPERAND: op_data is the field in the
 				   source instruction to take the value from
 				   and encode in the op_num field here.
-				   LITERAL or LABEL: op_data is the ordinal
-				   that identifies the appropriate one, i.e.,
-				   there can be more than one literal or
-				   label in an expansion.  */
+				   LITERAL or LABEL: unused.  */
   BuildOp *next;
 };
 
@@ -155,8 +152,6 @@ enum instr_type
 struct build_instr
 {
   InstrType typ;
-  unsigned id;			/* LITERAL_DEF or LABEL_DEF: an ordinal to
-				   identify which one.  */
   xtensa_opcode opcode;		/* Unused for LITERAL_DEF or LABEL_DEF.  */
   BuildOp *ops;
   BuildInstr *next;
diff --git a/gas/configure b/gas/configure
index dca6497031ce..d2cc2e704e04 100755
--- a/gas/configure
+++ b/gas/configure
@@ -241,6 +241,155 @@ IFS=" 	$as_nl"
 $as_unset CDPATH
 
 
+
+# Check that we are running under the correct shell.
+SHELL=${CONFIG_SHELL-/bin/sh}
+
+case X$lt_ECHO in
+X*--fallback-echo)
+  # Remove one level of quotation (which was required for Make).
+  ECHO=`echo "$lt_ECHO" | sed 's,\\\\\$\\$0,'$0','`
+  ;;
+esac
+
+ECHO=${lt_ECHO-echo}
+if test "X$1" = X--no-reexec; then
+  # Discard the --no-reexec flag, and continue.
+  shift
+elif test "X$1" = X--fallback-echo; then
+  # Avoid inline document here, it may be left over
+  :
+elif test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' ; then
+  # Yippee, $ECHO works!
+  :
+else
+  # Restart under the correct shell.
+  exec $SHELL "$0" --no-reexec ${1+"$@"}
+fi
+
+if test "X$1" = X--fallback-echo; then
+  # used as fallback echo
+  shift
+  cat <<_LT_EOF
+$*
+_LT_EOF
+  exit 0
+fi
+
+# The HP-UX ksh and POSIX shell print the target directory to stdout
+# if CDPATH is set.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+if test -z "$lt_ECHO"; then
+  if test "X${echo_test_string+set}" != Xset; then
+    # find a string as large as possible, as long as the shell can cope with it
+    for cmd in 'sed 50q "$0"' 'sed 20q "$0"' 'sed 10q "$0"' 'sed 2q "$0"' 'echo test'; do
+      # expected sizes: less than 2Kb, 1Kb, 512 bytes, 16 bytes, ...
+      if { echo_test_string=`eval $cmd`; } 2>/dev/null &&
+	 { test "X$echo_test_string" = "X$echo_test_string"; } 2>/dev/null
+      then
+        break
+      fi
+    done
+  fi
+
+  if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' &&
+     echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` &&
+     test "X$echo_testing_string" = "X$echo_test_string"; then
+    :
+  else
+    # The Solaris, AIX, and Digital Unix default echo programs unquote
+    # backslashes.  This makes it impossible to quote backslashes using
+    #   echo "$something" | sed 's/\\/\\\\/g'
+    #
+    # So, first we look for a working echo in the user's PATH.
+
+    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+    for dir in $PATH /usr/ucb; do
+      IFS="$lt_save_ifs"
+      if (test -f $dir/echo || test -f $dir/echo$ac_exeext) &&
+         test "X`($dir/echo '\t') 2>/dev/null`" = 'X\t' &&
+         echo_testing_string=`($dir/echo "$echo_test_string") 2>/dev/null` &&
+         test "X$echo_testing_string" = "X$echo_test_string"; then
+        ECHO="$dir/echo"
+        break
+      fi
+    done
+    IFS="$lt_save_ifs"
+
+    if test "X$ECHO" = Xecho; then
+      # We didn't find a better echo, so look for alternatives.
+      if test "X`{ print -r '\t'; } 2>/dev/null`" = 'X\t' &&
+         echo_testing_string=`{ print -r "$echo_test_string"; } 2>/dev/null` &&
+         test "X$echo_testing_string" = "X$echo_test_string"; then
+        # This shell has a builtin print -r that does the trick.
+        ECHO='print -r'
+      elif { test -f /bin/ksh || test -f /bin/ksh$ac_exeext; } &&
+	   test "X$CONFIG_SHELL" != X/bin/ksh; then
+        # If we have ksh, try running configure again with it.
+        ORIGINAL_CONFIG_SHELL=${CONFIG_SHELL-/bin/sh}
+        export ORIGINAL_CONFIG_SHELL
+        CONFIG_SHELL=/bin/ksh
+        export CONFIG_SHELL
+        exec $CONFIG_SHELL "$0" --no-reexec ${1+"$@"}
+      else
+        # Try using printf.
+        ECHO='printf %s\n'
+        if test "X`{ $ECHO '\t'; } 2>/dev/null`" = 'X\t' &&
+	   echo_testing_string=`{ $ECHO "$echo_test_string"; } 2>/dev/null` &&
+	   test "X$echo_testing_string" = "X$echo_test_string"; then
+	  # Cool, printf works
+	  :
+        elif echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` &&
+	     test "X$echo_testing_string" = 'X\t' &&
+	     echo_testing_string=`($ORIGINAL_CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` &&
+	     test "X$echo_testing_string" = "X$echo_test_string"; then
+	  CONFIG_SHELL=$ORIGINAL_CONFIG_SHELL
+	  export CONFIG_SHELL
+	  SHELL="$CONFIG_SHELL"
+	  export SHELL
+	  ECHO="$CONFIG_SHELL $0 --fallback-echo"
+        elif echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo '\t') 2>/dev/null` &&
+	     test "X$echo_testing_string" = 'X\t' &&
+	     echo_testing_string=`($CONFIG_SHELL "$0" --fallback-echo "$echo_test_string") 2>/dev/null` &&
+	     test "X$echo_testing_string" = "X$echo_test_string"; then
+	  ECHO="$CONFIG_SHELL $0 --fallback-echo"
+        else
+	  # maybe with a smaller string...
+	  prev=:
+
+	  for cmd in 'echo test' 'sed 2q "$0"' 'sed 10q "$0"' 'sed 20q "$0"' 'sed 50q "$0"'; do
+	    if { test "X$echo_test_string" = "X`eval $cmd`"; } 2>/dev/null
+	    then
+	      break
+	    fi
+	    prev="$cmd"
+	  done
+
+	  if test "$prev" != 'sed 50q "$0"'; then
+	    echo_test_string=`eval $prev`
+	    export echo_test_string
+	    exec ${ORIGINAL_CONFIG_SHELL-${CONFIG_SHELL-/bin/sh}} "$0" ${1+"$@"}
+	  else
+	    # Oops.  We lost completely, so just stick with echo.
+	    ECHO=echo
+	  fi
+        fi
+      fi
+    fi
+  fi
+fi
+
+# Copy echo and quote the copy suitably for passing to libtool from
+# the Makefile, instead of quoting the original, which is used later.
+lt_ECHO=$ECHO
+if test "X$lt_ECHO" = "X$CONFIG_SHELL $0 --fallback-echo"; then
+   lt_ECHO="$CONFIG_SHELL \\\$\$0 --fallback-echo"
+fi
+
+
+
+
 # Name of the host.
 # hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
 # so uname gets run too.
@@ -309,7 +458,7 @@ ac_includes_default="\
 # include <unistd.h>
 #endif"
 
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LN_S RANLIB ac_ct_RANLIB LIBTOOL WARN_CFLAGS NO_WERROR GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof BFDLIB OPCODES_LIB BFDVER_H ALL_OBJ_DEPS YACC LEX LEXLIB LEX_OUTPUT_ROOT CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBM datarootdir docdir htmldir LIBOBJS LTLIBOBJS'
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LIBTOOL SED EGREP FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM LN_S AR ac_ct_AR RANLIB ac_ct_RANLIB lt_ECHO CPP WARN_CFLAGS NO_WERROR GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof OPCODES_LIB YACC LEX LEXLIB LEX_OUTPUT_ROOT USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT MKINSTALLDIRS MSGFMT MSGMERGE MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT GENINSRC_NEVER_TRUE GENINSRC_NEVER_FALSE ALLOCA LIBM datarootdir docdir htmldir LIBOBJS LTLIBOBJS'
 ac_subst_files=''
 
 # Initialize some variables set by options.
@@ -852,14 +1001,18 @@ Optional Features:
   --enable-FEATURE[=ARG]  include FEATURE [ARG=yes]
   --disable-dependency-tracking  speeds up one-time build
   --enable-dependency-tracking   do not reject slow dependency extractors
-  --enable-shared=PKGS  build shared libraries default=yes
-  --enable-static=PKGS  build static libraries default=yes
-  --enable-fast-install=PKGS  optimize for fast installation default=yes
+  --enable-shared[=PKGS]
+                          build shared libraries [default=yes]
+  --enable-static[=PKGS]
+                          build static libraries [default=yes]
+  --enable-fast-install[=PKGS]
+                          optimize for fast installation [default=yes]
   --disable-libtool-lock  avoid locking (might break parallel builds)
-   --enable-targets       alternative target configurations besides the primary
+  --enable-targets        alternative target configurations besides the primary
   --enable-commonbfdlib   build shared BFD/opcodes/libiberty library
-  --enable-werror    treat compile warnings as errors
-  --enable-build-warnings Enable build-time compiler warnings
+  --enable-checking       enable run-time checks
+  --enable-werror         treat compile warnings as errors
+  --enable-build-warnings enable build-time compiler warnings
   --disable-nls           do not use Native Language Support
   --enable-maintainer-mode  enable make rules and dependencies not useful
 			  (and sometimes confusing) to the casual installer
@@ -867,9 +1020,9 @@ Optional Features:
 Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
   --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
-  --with-gnu-ld           assume the C compiler uses GNU ld default=no
-  --with-pic              try to use only PIC/non-PIC objects default=use both
-  --with-included-gettext use the GNU gettext library included here
+  --with-pic              try to use only PIC/non-PIC objects [default=use
+                          both]
+  --with-gnu-ld           assume the C compiler uses GNU ld [default=no]
 
 Some influential environment variables:
   CC          C compiler command
@@ -3072,73 +3225,264 @@ fi
 
 
 
+
+
+macro_version='2.1a'
+macro_revision='1.2435'
+
+
+
+
+
+
+
+
+
+
+
+
+ltmain="$ac_aux_dir/ltmain.sh"
+
+# Set options
+
+enable_dlopen=no
+
+
+enable_win32_dll=no
+
+
 # Check whether --enable-shared or --disable-shared was given.
 if test "${enable_shared+set}" = set; then
   enableval="$enable_shared"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_shared=yes ;;
-no) enable_shared=no ;;
-*)
-  enable_shared=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_shared=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_shared=yes ;;
+    no) enable_shared=no ;;
+    *)
+      enable_shared=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_shared=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_shared=yes
 fi;
+
+
+
+
+
+
+
+
 # Check whether --enable-static or --disable-static was given.
 if test "${enable_static+set}" = set; then
   enableval="$enable_static"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_static=yes ;;
-no) enable_static=no ;;
-*)
-  enable_static=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_static=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_static=yes ;;
+    no) enable_static=no ;;
+    *)
+     enable_static=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_static=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_static=yes
 fi;
+
+
+
+
+
+
+
+
+
+# Check whether --with-pic or --without-pic was given.
+if test "${with_pic+set}" = set; then
+  withval="$with_pic"
+  pic_mode="$withval"
+else
+  pic_mode=default
+fi;
+
+test -z "$pic_mode" && pic_mode=default
+
+
+
+
+
+
+
 # Check whether --enable-fast-install or --disable-fast-install was given.
 if test "${enable_fast_install+set}" = set; then
   enableval="$enable_fast_install"
   p=${PACKAGE-default}
-case $enableval in
-yes) enable_fast_install=yes ;;
-no) enable_fast_install=no ;;
-*)
-  enable_fast_install=no
-  # Look at the argument we got.  We use all the common list separators.
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:,"
-  for pkg in $enableval; do
-    if test "X$pkg" = "X$p"; then
-      enable_fast_install=yes
-    fi
-  done
-  IFS="$ac_save_ifs"
-  ;;
-esac
+    case $enableval in
+    yes) enable_fast_install=yes ;;
+    no) enable_fast_install=no ;;
+    *)
+      enable_fast_install=no
+      # Look at the argument we got.  We use all the common list separators.
+      lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR,"
+      for pkg in $enableval; do
+	IFS="$lt_save_ifs"
+	if test "X$pkg" = "X$p"; then
+	  enable_fast_install=yes
+	fi
+      done
+      IFS="$lt_save_ifs"
+      ;;
+    esac
 else
   enable_fast_install=yes
 fi;
 
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for a sed that does not truncate output" >&5
+echo $ECHO_N "checking for a sed that does not truncate output... $ECHO_C" >&6
+if test "${lt_cv_path_SED+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  # Loop through the user's path and test for sed and gsed.
+# Then use that list of sed's as ones to test for truncation.
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for lt_ac_prog in sed gsed; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      if $as_executable_p "$as_dir/$lt_ac_prog$ac_exec_ext"; then
+        lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext"
+      fi
+    done
+  done
+done
+IFS=$as_save_IFS
+lt_ac_max=0
+lt_ac_count=0
+# Add /usr/xpg4/bin/sed as it is typically found on Solaris
+# along with /bin/sed that truncates output.
+for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do
+  test ! -f $lt_ac_sed && continue
+  cat /dev/null > conftest.in
+  lt_ac_count=0
+  echo $ECHO_N "0123456789$ECHO_C" >conftest.in
+  # Check for GNU sed and select it if it is found.
+  if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then
+    lt_cv_path_SED=$lt_ac_sed
+    break
+  fi
+  while true; do
+    cat conftest.in conftest.in >conftest.tmp
+    mv conftest.tmp conftest.in
+    cp conftest.in conftest.nl
+    echo >>conftest.nl
+    $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break
+    cmp -s conftest.out conftest.nl || break
+    # 10000 chars as input seems more than enough
+    test $lt_ac_count -gt 10 && break
+    lt_ac_count=`expr $lt_ac_count + 1`
+    if test $lt_ac_count -gt $lt_ac_max; then
+      lt_ac_max=$lt_ac_count
+      lt_cv_path_SED=$lt_ac_sed
+    fi
+  done
+done
+
+fi
+
+SED=$lt_cv_path_SED
+
+echo "$as_me:$LINENO: result: $SED" >&5
+echo "${ECHO_T}$SED" >&6
+
+test -z "$SED" && SED=sed
+Xsed="$SED -e 1s/^X//"
+
+
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for egrep" >&5
+echo $ECHO_N "checking for egrep... $ECHO_C" >&6
+if test "${ac_cv_prog_egrep+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
+    then ac_cv_prog_egrep='grep -E'
+    else ac_cv_prog_egrep='egrep'
+    fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
+echo "${ECHO_T}$ac_cv_prog_egrep" >&6
+ EGREP=$ac_cv_prog_egrep
+
+
+echo "$as_me:$LINENO: checking for fgrep" >&5
+echo $ECHO_N "checking for fgrep... $ECHO_C" >&6
+if test "${ac_cv_prog_fgrep+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if echo 'ab*c' | (grep -F 'ab*c') >/dev/null 2>&1
+    then ac_cv_prog_fgrep='grep -F'
+    else ac_cv_prog_fgrep='fgrep'
+    fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_fgrep" >&5
+echo "${ECHO_T}$ac_cv_prog_fgrep" >&6
+ FGREP=$ac_cv_prog_fgrep
+
+
+test -z "$GREP" && GREP=grep
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 # Check whether --with-gnu-ld or --without-gnu-ld was given.
 if test "${with_gnu_ld+set}" = set; then
   withval="$with_gnu_ld"
@@ -3149,8 +3493,8 @@ fi;
 ac_prog=ld
 if test "$GCC" = yes; then
   # Check if gcc -print-prog-name=ld gives a path.
-  echo "$as_me:$LINENO: checking for ld used by GCC" >&5
-echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6
+  echo "$as_me:$LINENO: checking for ld used by $CC" >&5
+echo $ECHO_N "checking for ld used by $CC... $ECHO_C" >&6
   case $host in
   *-*-mingw*)
     # gcc leaves a trailing carriage return which upsets mingw
@@ -3160,12 +3504,12 @@ echo $ECHO_N "checking for ld used by GCC... $ECHO_C" >&6
   esac
   case $ac_prog in
     # Accept absolute paths.
-    [\\/]* | [A-Za-z]:[\\/]*)
+    [\\/]* | ?:[\\/]*)
       re_direlt='/[^/][^/]*/\.\./'
-      # Canonicalize the path of ld
-      ac_prog=`echo $ac_prog| sed 's%\\\\%/%g'`
-      while echo $ac_prog | grep "$re_direlt" > /dev/null 2>&1; do
-	ac_prog=`echo $ac_prog| sed "s%$re_direlt%/%"`
+      # Canonicalize the pathname of ld
+      ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'`
+      while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do
+	ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"`
       done
       test -z "$LD" && LD="$ac_prog"
       ;;
@@ -3189,22 +3533,26 @@ if test "${lt_cv_path_LD+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   if test -z "$LD"; then
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
   for ac_dir in $PATH; do
+    IFS="$lt_save_ifs"
     test -z "$ac_dir" && ac_dir=.
     if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then
       lt_cv_path_LD="$ac_dir/$ac_prog"
       # Check to see if the program is GNU ld.  I'd rather use --version,
-      # but apparently some GNU ld's only accept -v.
+      # but apparently some variants of GNU ld only accept -v.
       # Break only if it was the GNU/non-GNU ld that we prefer.
-      if "$lt_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then
+      case `"$lt_cv_path_LD" -v 2>&1 </dev/null` in
+      *GNU* | *'with BFD'*)
 	test "$with_gnu_ld" != no && break
-      else
+	;;
+      *)
 	test "$with_gnu_ld" != yes && break
-      fi
+	;;
+      esac
     fi
   done
-  IFS="$ac_save_ifs"
+  IFS="$lt_save_ifs"
 else
   lt_cv_path_LD="$LD" # Let the user override the test with a path.
 fi
@@ -3226,32 +3574,31 @@ echo $ECHO_N "checking if the linker ($LD) is GNU ld... $ECHO_C" >&6
 if test "${lt_cv_prog_gnu_ld+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  # I'd rather use --version here, but apparently some GNU ld's only accept -v.
-if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then
+  # I'd rather use --version here, but apparently some GNU lds only accept -v.
+case `$LD -v 2>&1 </dev/null` in
+*GNU* | *'with BFD'*)
   lt_cv_prog_gnu_ld=yes
-else
+  ;;
+*)
   lt_cv_prog_gnu_ld=no
-fi
+  ;;
+esac
 fi
 echo "$as_me:$LINENO: result: $lt_cv_prog_gnu_ld" >&5
 echo "${ECHO_T}$lt_cv_prog_gnu_ld" >&6
 with_gnu_ld=$lt_cv_prog_gnu_ld
 
 
-echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5
-echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6
-if test "${lt_cv_ld_reload_flag+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  lt_cv_ld_reload_flag='-r'
-fi
-echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5
-echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6
-reload_flag=$lt_cv_ld_reload_flag
-test -n "$reload_flag" && reload_flag=" $reload_flag"
 
-echo "$as_me:$LINENO: checking for BSD-compatible nm" >&5
-echo $ECHO_N "checking for BSD-compatible nm... $ECHO_C" >&6
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for BSD- or MS-compatible name lister (nm)" >&5
+echo $ECHO_N "checking for BSD- or MS-compatible name lister (nm)... $ECHO_C" >&6
 if test "${lt_cv_path_NM+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
@@ -3259,35 +3606,173 @@ else
   # Let the user override the test.
   lt_cv_path_NM="$NM"
 else
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}"
-  for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do
-    test -z "$ac_dir" && ac_dir=.
-    tmp_nm=$ac_dir/${ac_tool_prefix}nm
-    if test -f $tmp_nm || test -f $tmp_nm$ac_exeext ; then
-      # Check to see if the nm accepts a BSD-compat flag.
-      # Adding the `sed 1q' prevents false positives on HP-UX, which says:
-      #   nm: unknown option "B" ignored
-      # Tru64's nm complains that /dev/null is an invalid object file
-      if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then
-	lt_cv_path_NM="$tmp_nm -B"
-	break
-      elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then
-	lt_cv_path_NM="$tmp_nm -p"
-	break
-      else
-	lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
-	continue # so that we can try to find one that supports BSD flags
+  lt_nm_to_check="${ac_tool_prefix}nm"
+  if test -n "$ac_tool_prefix" && test "$build" = "$host"; then
+    lt_nm_to_check="$lt_nm_to_check nm"
+  fi
+  for lt_tmp_nm in $lt_nm_to_check; do
+    lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do
+      IFS="$lt_save_ifs"
+      test -z "$ac_dir" && ac_dir=.
+      tmp_nm="$ac_dir/$lt_tmp_nm"
+      if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then
+	# Check to see if the nm accepts a BSD-compat flag.
+	# Adding the `sed 1q' prevents false positives on HP-UX, which says:
+	#   nm: unknown option "B" ignored
+	# Tru64's nm complains that /dev/null is an invalid object file
+	case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in
+	*/dev/null* | *'Invalid file or object type'*)
+	  lt_cv_path_NM="$tmp_nm -B"
+	  break
+	  ;;
+	*)
+	  case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in
+	  */dev/null*)
+	    lt_cv_path_NM="$tmp_nm -p"
+	    break
+	    ;;
+	  *)
+	    lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but
+	    continue # so that we can try to find one that supports BSD flags
+	    ;;
+	  esac
+	  ;;
+	esac
       fi
-    fi
+    done
+    IFS="$lt_save_ifs"
   done
-  IFS="$ac_save_ifs"
-  test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm
+  : ${lt_cv_path_NM=no}
+fi
+fi
+echo "$as_me:$LINENO: result: $lt_cv_path_NM" >&5
+echo "${ECHO_T}$lt_cv_path_NM" >&6
+if test "$lt_cv_path_NM" != "no"; then
+  NM="$lt_cv_path_NM"
+else
+  # Didn't find any BSD compatible name lister, look for dumpbin.
+  if test -n "$ac_tool_prefix"; then
+  for ac_prog in "dumpbin -symbols" "link -dump -symbols"
+  do
+    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_DUMPBIN+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$DUMPBIN"; then
+  ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
 fi
+DUMPBIN=$ac_cv_prog_DUMPBIN
+if test -n "$DUMPBIN"; then
+  echo "$as_me:$LINENO: result: $DUMPBIN" >&5
+echo "${ECHO_T}$DUMPBIN" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
 fi
 
-NM="$lt_cv_path_NM"
-echo "$as_me:$LINENO: result: $NM" >&5
-echo "${ECHO_T}$NM" >&6
+    test -n "$DUMPBIN" && break
+  done
+fi
+if test -z "$DUMPBIN"; then
+  ac_ct_DUMPBIN=$DUMPBIN
+  for ac_prog in "dumpbin -symbols" "link -dump -symbols"
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_DUMPBIN+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$ac_ct_DUMPBIN"; then
+  ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_DUMPBIN="$ac_prog"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
+fi
+ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN
+if test -n "$ac_ct_DUMPBIN"; then
+  echo "$as_me:$LINENO: result: $ac_ct_DUMPBIN" >&5
+echo "${ECHO_T}$ac_ct_DUMPBIN" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+  test -n "$ac_ct_DUMPBIN" && break
+done
+test -n "$ac_ct_DUMPBIN" || ac_ct_DUMPBIN=":"
+
+  DUMPBIN=$ac_ct_DUMPBIN
+fi
+
+
+  if test "$DUMPBIN" != ":"; then
+    NM="$DUMPBIN"
+  fi
+fi
+test -z "$NM" && NM=nm
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking the name lister ($NM) interface" >&5
+echo $ECHO_N "checking the name lister ($NM) interface... $ECHO_C" >&6
+if test "${lt_cv_nm_interface+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_nm_interface="BSD nm"
+  echo "int some_variable = 0;" > conftest.$ac_ext
+  (eval echo "\"\$as_me:3761: $ac_compile\"" >&5)
+  (eval "$ac_compile" 2>conftest.err)
+  cat conftest.err >&5
+  (eval echo "\"\$as_me:3764: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
+  (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
+  cat conftest.err >&5
+  (eval echo "\"\$as_me:3767: output\"" >&5)
+  cat conftest.out >&5
+  if $GREP 'External.*some_variable' conftest.out > /dev/null; then
+    lt_cv_nm_interface="MS dumpbin"
+  fi
+  rm -f conftest*
+fi
+echo "$as_me:$LINENO: result: $lt_cv_nm_interface" >&5
+echo "${ECHO_T}$lt_cv_nm_interface" >&6
 
 echo "$as_me:$LINENO: checking whether ln -s works" >&5
 echo $ECHO_N "checking whether ln -s works... $ECHO_C" >&6
@@ -3300,8 +3785,234 @@ else
 echo "${ECHO_T}no, using $LN_S" >&6
 fi
 
-echo "$as_me:$LINENO: checking how to recognise dependant libraries" >&5
-echo $ECHO_N "checking how to recognise dependant libraries... $ECHO_C" >&6
+# find the maximum length of command line arguments
+echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5
+echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6
+if test "${lt_cv_sys_max_cmd_len+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+    i=0
+  teststring="ABCD"
+
+  case $build_os in
+  msdosdjgpp*)
+    # On DJGPP, this test can blow up pretty badly due to problems in libc
+    # (any single argument exceeding 2000 bytes causes a buffer overrun
+    # during glob expansion).  Even if it were fixed, the result of this
+    # check would be larger than it should be.
+    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
+    ;;
+
+  gnu*)
+    # Under GNU Hurd, this test is not required because there is
+    # no limit to the length of command line arguments.
+    # Libtool will interpret -1 as no limit whatsoever
+    lt_cv_sys_max_cmd_len=-1;
+    ;;
+
+  cygwin* | mingw*)
+    # On Win9x/ME, this test blows up -- it succeeds, but takes
+    # about 5 minutes as the teststring grows exponentially.
+    # Worse, since 9x/ME are not pre-emptively multitasking,
+    # you end up with a "frozen" computer, even though with patience
+    # the test eventually succeeds (with a max line length of 256k).
+    # Instead, let's just punt: use the minimum linelength reported by
+    # all of the supported platforms: 8192 (on NT/2K/XP).
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  amigaos*)
+    # On AmigaOS with pdksh, this test takes hours, literally.
+    # So we just punt and use a minimum line length of 8192.
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
+    # This has been around since 386BSD, at least.  Likely further.
+    if test -x /sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
+    elif test -x /usr/sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
+    else
+      lt_cv_sys_max_cmd_len=65536	# usable default for all BSDs
+    fi
+    # And add a safety zone
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    ;;
+
+  interix*)
+    # We know the value 262144 and hardcode it with a safety zone (like BSD)
+    lt_cv_sys_max_cmd_len=196608
+    ;;
+
+  osf*)
+    # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure
+    # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not
+    # nice to cause kernel panics so lets avoid the loop below.
+    # First set a reasonable default.
+    lt_cv_sys_max_cmd_len=16384
+    #
+    if test -x /sbin/sysconfig; then
+      case `/sbin/sysconfig -q proc exec_disable_arg_limit` in
+        *1*) lt_cv_sys_max_cmd_len=-1 ;;
+      esac
+    fi
+    ;;
+  sco3.2v5*)
+    lt_cv_sys_max_cmd_len=102400
+    ;;
+  sysv5* | sco5v6* | sysv4.2uw2*)
+    kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null`
+    if test -n "$kargmax"; then
+      lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[	 ]//'`
+    else
+      lt_cv_sys_max_cmd_len=32768
+    fi
+    ;;
+  *)
+    lt_cv_sys_max_cmd_len=`getconf ARG_MAX 2> /dev/null`
+    if test -n $lt_cv_sys_max_cmd_len; then
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    else
+      # Make teststring a little bigger before we do anything with it.
+      # a 1K string should be a reasonable start.
+      for i in 1 2 3 4 5 6 7 8 ; do
+        teststring=$teststring$teststring
+      done
+      SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}}
+      # If test is not a shell built-in, we'll probably end up computing a
+      # maximum length that is only half of the actual maximum length, but
+      # we can't tell.
+      while { test "X"`$SHELL $0 --fallback-echo "X$teststring$teststring" 2>/dev/null` \
+	         = "XX$teststring$teststring"; } >/dev/null 2>&1 &&
+	      test $i != 17 # 1/2 MB should be enough
+      do
+        i=`expr $i + 1`
+        teststring=$teststring$teststring
+      done
+      # Only check the string length outside the loop.
+      lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1`
+      teststring=
+      # Add a significant safety factor because C++ compilers can tack on
+      # massive amounts of additional arguments before passing them to the
+      # linker.  It appears as though 1/2 is a usable value.
+      lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2`
+    fi
+    ;;
+  esac
+
+fi
+
+if test -n $lt_cv_sys_max_cmd_len ; then
+  echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5
+echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6
+else
+  echo "$as_me:$LINENO: result: none" >&5
+echo "${ECHO_T}none" >&6
+fi
+max_cmd_len=$lt_cv_sys_max_cmd_len
+
+
+
+
+
+
+
+: ${CP="cp -f"}
+: ${MV="mv -f"}
+: ${RM="rm -f"}
+
+echo "$as_me:$LINENO: checking whether the shell understands some XSI constructs" >&5
+echo $ECHO_N "checking whether the shell understands some XSI constructs... $ECHO_C" >&6
+# Try some XSI features
+xsi_shell=no
+( _lt_dummy="a/b/c"
+  test "${_lt_dummy##*/},${_lt_dummy%/*},"${_lt_dummy%"$_lt_dummy"}, \
+      = c,a/b,, ) >/dev/null 2>&1 \
+  && xsi_shell=yes
+echo "$as_me:$LINENO: result: $xsi_shell" >&5
+echo "${ECHO_T}$xsi_shell" >&6
+
+
+echo "$as_me:$LINENO: checking whether the shell understands \"+=\"" >&5
+echo $ECHO_N "checking whether the shell understands \"+=\"... $ECHO_C" >&6
+lt_shell_append=no
+( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \
+    >/dev/null 2>&1 \
+  && lt_shell_append=yes
+echo "$as_me:$LINENO: result: $lt_shell_append" >&5
+echo "${ECHO_T}$lt_shell_append" >&6
+
+
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+  lt_unset=unset
+else
+  lt_unset=false
+fi
+
+
+
+
+
+# test EBCDIC or ASCII
+case `echo X|tr X '\101'` in
+ A) # ASCII based system
+    # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr
+  lt_SP2NL='tr \040 \012'
+  lt_NL2SP='tr \015\012 \040\040'
+  ;;
+ *) # EBCDIC based system
+  lt_SP2NL='tr \100 \n'
+  lt_NL2SP='tr \r\n \100\100'
+  ;;
+esac
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking for $LD option to reload object files" >&5
+echo $ECHO_N "checking for $LD option to reload object files... $ECHO_C" >&6
+if test "${lt_cv_ld_reload_flag+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_ld_reload_flag='-r'
+fi
+echo "$as_me:$LINENO: result: $lt_cv_ld_reload_flag" >&5
+echo "${ECHO_T}$lt_cv_ld_reload_flag" >&6
+reload_flag=$lt_cv_ld_reload_flag
+case $reload_flag in
+"" | " "*) ;;
+*) reload_flag=" $reload_flag" ;;
+esac
+reload_cmds='$LD$reload_flag -o $output$reload_objs'
+case $host_os in
+  darwin*)
+    if test "$GCC" = yes; then
+      reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs'
+    else
+      reload_cmds='$LD$reload_flag -o $output$reload_objs'
+    fi
+    ;;
+esac
+
+
+
+
+
+
+
+
+
+
+echo "$as_me:$LINENO: checking how to recognize dependent libraries" >&5
+echo $ECHO_N "checking how to recognize dependent libraries... $ECHO_C" >&6
 if test "${lt_cv_deplibs_check_method+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
@@ -3314,13 +4025,13 @@ lt_cv_deplibs_check_method='unknown'
 # `unknown' -- same as none, but documents that we really don't know.
 # 'pass_all' -- all dependencies passed with no checks.
 # 'test_compile' -- check by making test program.
-# 'file_magic [regex]' -- check by looking for files in library path
-# which responds to the $file_magic_cmd with a given egrep regex.
+# 'file_magic [[regex]]' -- check by looking for files in library path
+# which responds to the $file_magic_cmd with a given extended regex.
 # If you have `file' or equivalent on your system and you're not sure
 # whether `pass_all' will *always* work, you probably want this one.
 
 case $host_os in
-aix*)
+aix4* | aix5*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
@@ -3328,39 +4039,42 @@ beos*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-bsdi4*)
+bsdi[45]*)
   lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)'
   lt_cv_file_magic_cmd='/usr/bin/file -L'
   lt_cv_file_magic_test_file=/shlib/libc.so
   ;;
 
-cygwin* | mingw* |pw32*)
-  lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
-  lt_cv_file_magic_cmd='$OBJDUMP -f'
+cygwin*)
+  # func_win32_libid is a shell function defined in ltmain.sh
+  lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
+  lt_cv_file_magic_cmd='func_win32_libid'
+  ;;
+
+mingw* | pw32*)
+  # Base MSYS/MinGW do not provide the 'file' command needed by
+  # func_win32_libid shell function, so use a weaker test based on 'objdump',
+  # unless we find 'file', for example because we are cross-compiling.
+  if ( file / ) >/dev/null 2>&1; then
+    lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL'
+    lt_cv_file_magic_cmd='func_win32_libid'
+  else
+    lt_cv_deplibs_check_method='file_magic file format pei*-i386(.*architecture: i386)?'
+    lt_cv_file_magic_cmd='$OBJDUMP -f'
+  fi
   ;;
 
 darwin* | rhapsody*)
-  # this will be overwritten by pass_all, but leave it in just in case
-  lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library'
-  lt_cv_file_magic_cmd='/usr/bin/file -L'
-  case "$host_os" in
-  rhapsody* | darwin1.012)
-    lt_cv_file_magic_test_file='/System/Library/Frameworks/System.framework/System'
-    ;;
-  *) # Darwin 1.3 on
-    lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib'
-    ;;
-  esac
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-freebsd* | kfreebsd*-gnu)
-  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
+freebsd* | dragonfly*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
     case $host_cpu in
     i*86 )
       # Not sure whether the presence of OpenBSD here was a mistake.
       # Let's accept both of them until this is cleared up.
-      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library'
+      lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library'
       lt_cv_file_magic_cmd=/usr/bin/file
       lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*`
       ;;
@@ -3374,92 +4088,116 @@ gnu*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-hpux10.20*|hpux11*)
+hpux10.20* | hpux11*)
+  lt_cv_file_magic_cmd=/usr/bin/file
   case $host_cpu in
-  hppa*)
-    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library'
-    lt_cv_file_magic_cmd=/usr/bin/file
-    lt_cv_file_magic_test_file=/usr/lib/libc.sl
-    ;;
   ia64*)
     lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64'
-    lt_cv_file_magic_cmd=/usr/bin/file
     lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so
     ;;
-  esac
-  ;;
-
-irix5* | irix6*)
-  case $host_os in
-  irix5*)
-    # this will be overridden with pass_all, but let us keep it just in case
-    lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1"
+  hppa*64*)
+    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - PA-RISC [0-9].[0-9]'
+    lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl
     ;;
   *)
-    case $LD in
-    *-32|*"-32 ") libmagic=32-bit;;
-    *-n32|*"-n32 ") libmagic=N32;;
-    *-64|*"-64 ") libmagic=64-bit;;
-    *) libmagic=never-match;;
-    esac
-    # this will be overridden with pass_all, but let us keep it just in case
-    lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1"
+    lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library'
+    lt_cv_file_magic_test_file=/usr/lib/libc.sl
     ;;
   esac
-  lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*`
+  ;;
+
+interix[3-9]*)
+  # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here
+  lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$'
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $LD in
+  *-32|*"-32 ") libmagic=32-bit;;
+  *-n32|*"-n32 ") libmagic=N32;;
+  *-64|*"-64 ") libmagic=64-bit;;
+  *) libmagic=never-match;;
+  esac
   lt_cv_deplibs_check_method=pass_all
   ;;
 
 # This must be Linux ELF.
-linux-gnu*)
+linux* | k*bsd*-gnu)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-netbsd* | knetbsd*-gnu)
-  if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
-    lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$'
+netbsd*)
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
   else
-    lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so$'
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$'
   fi
   ;;
 
-newsos6)
+newos6*)
   lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)'
   lt_cv_file_magic_cmd=/usr/bin/file
   lt_cv_file_magic_test_file=/usr/lib/libnls.so
   ;;
 
+*nto* | *qnx*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
+
+openbsd*)
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$'
+  else
+    lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$'
+  fi
+  ;;
+
 osf3* | osf4* | osf5*)
-  # this will be overridden with pass_all, but let us keep it just in case
-  lt_cv_deplibs_check_method='file_magic COFF format alpha shared library'
-  lt_cv_file_magic_test_file=/shlib/libc.so
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-sco3.2v5*)
+rdos*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
 solaris*)
   lt_cv_deplibs_check_method=pass_all
-  lt_cv_file_magic_test_file=/lib/libc.so
   ;;
 
-sysv5uw[78]* | sysv4*uw2*)
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
   lt_cv_deplibs_check_method=pass_all
   ;;
 
-sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+sysv4 | sysv4.3*)
   case $host_vendor in
-  ncr)
-    lt_cv_deplibs_check_method=pass_all
-    ;;
   motorola)
     lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]'
     lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*`
     ;;
+  ncr)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  sequent)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )'
+    ;;
+  sni)
+    lt_cv_file_magic_cmd='/bin/file'
+    lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib"
+    lt_cv_file_magic_test_file=/lib/libc.so
+    ;;
+  siemens)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
+  pc)
+    lt_cv_deplibs_check_method=pass_all
+    ;;
   esac
   ;;
+
+tpf*)
+  lt_cv_deplibs_check_method=pass_all
+  ;;
 esac
 
 fi
@@ -3467,222 +4205,29 @@ echo "$as_me:$LINENO: result: $lt_cv_deplibs_check_method" >&5
 echo "${ECHO_T}$lt_cv_deplibs_check_method" >&6
 file_magic_cmd=$lt_cv_file_magic_cmd
 deplibs_check_method=$lt_cv_deplibs_check_method
+test -z "$deplibs_check_method" && deplibs_check_method=unknown
 
 
 
 
-# Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers!
-
-# find the maximum length of command line arguments
-echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5
-echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6
-if test "${lt_cv_sys_max_cmd_len+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-    i=0
-  teststring="ABCD"
-
-  case $build_os in
-  msdosdjgpp*)
-    # On DJGPP, this test can blow up pretty badly due to problems in libc
-    # (any single argument exceeding 2000 bytes causes a buffer overrun
-    # during glob expansion).  Even if it were fixed, the result of this
-    # check would be larger than it should be.
-    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
-    ;;
-
-  cygwin* | mingw*)
-    # On Win9x/ME, this test blows up -- it succeeds, but takes
-    # about 5 minutes as the teststring grows exponentially.
-    # Worse, since 9x/ME are not pre-emptively multitasking,
-    # you end up with a "frozen" computer, even though with patience
-    # the test eventually succeeds (with a max line length of 256k).
-    # Instead, let's just punt: use the minimum linelength reported by
-    # all of the supported platforms: 8192 (on NT/2K/XP).
-    lt_cv_sys_max_cmd_len=8192;
-    ;;
-
-  amigaos*)
-    # On AmigaOS with pdksh, this test takes hours, literally.
-    # So we just punt and use a minimum line length of 8192.
-    lt_cv_sys_max_cmd_len=8192;
-    ;;
-
-  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
-    # This has been around since 386BSD, at least.  Likely further.
-    if test -x /sbin/sysctl; then
-      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
-    elif test -x /usr/sbin/sysctl; then
-      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
-    else
-      lt_cv_sys_max_cmd_len=65536 # usable default for *BSD
-    fi
-    # And add a safety zone
-    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
-    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
-    ;;
-  esac
-
-fi
-
-if test -n "$lt_cv_sys_max_cmd_len" ; then
-  echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5
-echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6
-else
-  echo "$as_me:$LINENO: result: none" >&5
-echo "${ECHO_T}none" >&6
-fi
-
-
-# Only perform the check for file, if the check method requires it
-case $deplibs_check_method in
-file_magic*)
-  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
-    echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5
-echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6
-if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $MAGIC_CMD in
-  /*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
-  ;;
-  ?:/*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  ac_save_MAGIC_CMD="$MAGIC_CMD"
-  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="/usr/bin:$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/${ac_tool_prefix}file; then
-      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
-      if test -n "$file_magic_test_file"; then
-	case $deplibs_check_method in
-	"file_magic "*)
-	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
-	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
-	    egrep "$file_magic_regex" > /dev/null; then
-	    :
-	  else
-	    cat <<EOF 1>&2
-
-*** Warning: the command libtool uses to detect shared libraries,
-*** $file_magic_cmd, produces output that libtool cannot recognize.
-*** The result is that libtool may fail to recognize shared libraries
-*** as such.  This will affect the creation of libtool libraries that
-*** depend on shared libraries, but programs linked with such libtool
-*** libraries will work regardless of this problem.  Nevertheless, you
-*** may want to report the problem to your system manager and/or to
-*** bug-libtool@gnu.org
-
-EOF
-	  fi ;;
-	esac
-      fi
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  MAGIC_CMD="$ac_save_MAGIC_CMD"
-  ;;
-esac
-fi
 
-MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-if test -n "$MAGIC_CMD"; then
-  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
-echo "${ECHO_T}$MAGIC_CMD" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
 
-if test -z "$lt_cv_path_MAGIC_CMD"; then
-  if test -n "$ac_tool_prefix"; then
-    echo "$as_me:$LINENO: checking for file" >&5
-echo $ECHO_N "checking for file... $ECHO_C" >&6
-if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $MAGIC_CMD in
-  /*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
-  ;;
-  ?:/*)
-  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a dos path.
-  ;;
-  *)
-  ac_save_MAGIC_CMD="$MAGIC_CMD"
-  IFS="${IFS=   }"; ac_save_ifs="$IFS"; IFS=":"
-  ac_dummy="/usr/bin:$PATH"
-  for ac_dir in $ac_dummy; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/file; then
-      lt_cv_path_MAGIC_CMD="$ac_dir/file"
-      if test -n "$file_magic_test_file"; then
-	case $deplibs_check_method in
-	"file_magic "*)
-	  file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`"
-	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
-	    egrep "$file_magic_regex" > /dev/null; then
-	    :
-	  else
-	    cat <<EOF 1>&2
 
-*** Warning: the command libtool uses to detect shared libraries,
-*** $file_magic_cmd, produces output that libtool cannot recognize.
-*** The result is that libtool may fail to recognize shared libraries
-*** as such.  This will affect the creation of libtool libraries that
-*** depend on shared libraries, but programs linked with such libtool
-*** libraries will work regardless of this problem.  Nevertheless, you
-*** may want to report the problem to your system manager and/or to
-*** bug-libtool@gnu.org
 
-EOF
-	  fi ;;
-	esac
-      fi
-      break
-    fi
-  done
-  IFS="$ac_save_ifs"
-  MAGIC_CMD="$ac_save_MAGIC_CMD"
-  ;;
-esac
-fi
 
-MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
-if test -n "$MAGIC_CMD"; then
-  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
-echo "${ECHO_T}$MAGIC_CMD" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
 
-  else
-    MAGIC_CMD=:
-  fi
-fi
 
-  fi
-  ;;
-esac
 
 if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+  # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ar; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
+if test "${ac_cv_prog_AR+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+  if test -n "$AR"; then
+  ac_cv_prog_AR="$AR" # Let the user override the test.
 else
 as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
 for as_dir in $PATH
@@ -3691,7 +4236,7 @@ do
   test -z "$as_dir" && as_dir=.
   for ac_exec_ext in '' $ac_executable_extensions; do
   if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    ac_cv_prog_AR="${ac_tool_prefix}ar"
     echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
     break 2
   fi
@@ -3700,27 +4245,27 @@ done
 
 fi
 fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
+AR=$ac_cv_prog_AR
+if test -n "$AR"; then
+  echo "$as_me:$LINENO: result: $AR" >&5
+echo "${ECHO_T}$AR" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
 fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
+if test -z "$ac_cv_prog_AR"; then
+  ac_ct_AR=$AR
+  # Extract the first word of "ar", so it can be a program name with args.
+set dummy ar; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+if test "${ac_cv_prog_ac_ct_AR+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+  if test -n "$ac_ct_AR"; then
+  ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test.
 else
 as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
 for as_dir in $PATH
@@ -3729,30 +4274,43 @@ do
   test -z "$as_dir" && as_dir=.
   for ac_exec_ext in '' $ac_executable_extensions; do
   if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    ac_cv_prog_ac_ct_AR="ar"
     echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
     break 2
   fi
 done
 done
 
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+  test -z "$ac_cv_prog_ac_ct_AR" && ac_cv_prog_ac_ct_AR="false"
 fi
 fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
+ac_ct_AR=$ac_cv_prog_ac_ct_AR
+if test -n "$ac_ct_AR"; then
+  echo "$as_me:$LINENO: result: $ac_ct_AR" >&5
+echo "${ECHO_T}$ac_ct_AR" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
-  RANLIB=$ac_ct_RANLIB
+  AR=$ac_ct_AR
 else
-  RANLIB="$ac_cv_prog_RANLIB"
+  AR="$ac_cv_prog_AR"
 fi
 
+test -z "$AR" && AR=ar
+test -z "$AR_FLAGS" && AR_FLAGS=cru
+
+
+
+
+
+
+
+
+
+
+
 if test -n "$ac_tool_prefix"; then
   # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args.
 set dummy ${ac_tool_prefix}strip; ac_word=$2
@@ -3833,96 +4391,471 @@ else
   STRIP="$ac_cv_prog_STRIP"
 fi
 
+test -z "$STRIP" && STRIP=:
 
-# Check for any special flags to pass to ltconfig.
-libtool_flags="--cache-file=$cache_file"
-test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared"
-test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static"
-test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install"
-test "$GCC" = yes && libtool_flags="$libtool_flags --with-gcc"
-test "$lt_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld"
 
 
-# Check whether --enable-libtool-lock or --disable-libtool-lock was given.
-if test "${enable_libtool_lock+set}" = set; then
-  enableval="$enable_libtool_lock"
 
-fi;
-test "x$enable_libtool_lock" = xno && libtool_flags="$libtool_flags --disable-lock"
-test x"$silent" = xyes && libtool_flags="$libtool_flags --silent"
 
 
-# Check whether --with-pic or --without-pic was given.
-if test "${with_pic+set}" = set; then
-  withval="$with_pic"
-  pic_mode="$withval"
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_RANLIB+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  pic_mode=default
+  if test -n "$RANLIB"; then
+  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+  echo "$as_me:$LINENO: result: $RANLIB" >&5
+echo "${ECHO_T}$RANLIB" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+  ac_ct_RANLIB=$RANLIB
+  # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  if test -n "$ac_ct_RANLIB"; then
+  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  for ac_exec_ext in '' $ac_executable_extensions; do
+  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_RANLIB="ranlib"
+    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+done
+
+  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
+echo "${ECHO_T}$ac_ct_RANLIB" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+  RANLIB=$ac_ct_RANLIB
+else
+  RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+test -z "$RANLIB" && RANLIB=:
+
+
+
+
+
+
+# Determine commands to create old-style static archives.
+old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs$old_deplibs'
+old_postinstall_cmds='chmod 644 $oldlib'
+old_postuninstall_cmds=
+
+if test -n "$RANLIB"; then
+  case $host_os in
+  openbsd*)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib"
+    ;;
+  *)
+    old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib"
+    ;;
+  esac
+  old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib"
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# If no C compiler was specified, use CC.
+LTCC=${LTCC-"$CC"}
+
+# If no C compiler flags were specified, use CFLAGS.
+LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
+
+# Allow CC to be a program name with arguments.
+compiler=$CC
+
+
+# Check for command to grab the raw symbol name followed by C symbol from nm.
+echo "$as_me:$LINENO: checking command to parse $NM output from $compiler object" >&5
+echo $ECHO_N "checking command to parse $NM output from $compiler object... $ECHO_C" >&6
+if test "${lt_cv_sys_global_symbol_pipe+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+
+# These are sane defaults that work on at least a few old systems.
+# [They come from Ultrix.  What could be older than Ultrix?!! ;)]
+
+# Character class describing NM global symbol codes.
+symcode='[BCDEGRST]'
+
+# Regexp to match symbols that can be accessed directly from C.
+sympat='\([_A-Za-z][_A-Za-z0-9]*\)'
+
+# Define system-specific variables.
+case $host_os in
+aix*)
+  symcode='[BCDT]'
+  ;;
+cygwin* | mingw* | pw32*)
+  symcode='[ABCDGISTW]'
+  ;;
+hpux*)
+  if test "$host_cpu" = ia64; then
+    symcode='[ABCDEGRST]'
+  fi
+  ;;
+irix* | nonstopux*)
+  symcode='[BCDEGRST]'
+  ;;
+osf*)
+  symcode='[BCDEGQRST]'
+  ;;
+solaris*)
+  symcode='[BDRT]'
+  ;;
+sco3.2v5*)
+  symcode='[DT]'
+  ;;
+sysv4.2uw2*)
+  symcode='[DT]'
+  ;;
+sysv5* | sco5v6* | unixware* | OpenUNIX*)
+  symcode='[ABDT]'
+  ;;
+sysv4)
+  symcode='[DFNSTU]'
+  ;;
+esac
+
+# If we're using GNU nm, then use its standard symbol codes.
+case `$NM -V 2>&1` in
+*GNU* | *'with BFD'*)
+  symcode='[ABCDGIRSTW]' ;;
+esac
+
+# Transform an extracted symbol line into a proper C declaration.
+# Some systems (esp. on ia64) link data and code symbols differently,
+# so use this general approach.
+lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'"
+
+# Transform an extracted symbol line into symbol name and symbol address
+lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\) $/  {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/  {\"\2\", (void *) \&\2},/p'"
+
+# Handle CRLF in mingw tool chain
+opt_cr=
+case $build_os in
+mingw*)
+  opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp
+  ;;
+esac
+
+# Try without a prefix underscore, then with it.
+for ac_symprfx in "" "_"; do
+
+  # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol.
+  symxfrm="\\1 $ac_symprfx\\2 \\2"
+
+  # Write the raw and C identifiers.
+  if test "$lt_cv_nm_interface" = "MS dumpbin"; then
+    # Fake it for dumpbin and say T for any non-static function
+    # and D for any global variable.
+    # Also find C++ and __fastcall symbols from MSVC++,
+    # which start with @ or ?.
+    lt_cv_sys_global_symbol_pipe="$AWK '"\
+"     {last_section=section; section=\$ 3};"\
+"     /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\
+"     \$ 0!~/External *\|/{next};"\
+"     / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\
+"     {if(hide[section]) next};"\
+"     {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\
+"     {split(\$ 0, a, /\||\r/); split(a[2], s)};"\
+"     s[1]~/^[@?]/{print s[1], s[1]; next};"\
+"     s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\
+"     ' prfx=^$ac_symprfx"
+  else
+    lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[	 ]\($symcode$symcode*\)[	 ][	 ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'"
+  fi
+
+  # Check to see that the pipe works correctly.
+  pipe_works=no
+
+  rm -f conftest*
+  cat > conftest.$ac_ext <<_LT_EOF
+#ifdef __cplusplus
+extern "C" {
+#endif
+char nm_test_var;
+void nm_test_func(void);
+void nm_test_func(void){}
+#ifdef __cplusplus
+}
+#endif
+int main(){nm_test_var='a';nm_test_func();return(0);}
+_LT_EOF
+
+  if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+    # Now try to grab the symbols.
+    nlist=conftest.nm
+    if { (eval echo "$as_me:$LINENO: \"$NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist\"") >&5
+  (eval $NM conftest.$ac_objext \| $lt_cv_sys_global_symbol_pipe \> $nlist) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s "$nlist"; then
+      # Try sorting and uniquifying the output.
+      if sort "$nlist" | uniq > "$nlist"T; then
+	mv -f "$nlist"T "$nlist"
+      else
+	rm -f "$nlist"T
+      fi
+
+      # Make sure that we snagged all the symbols we need.
+      if $GREP ' nm_test_var$' "$nlist" >/dev/null; then
+	if $GREP ' nm_test_func$' "$nlist" >/dev/null; then
+	  cat <<_LT_EOF > conftest.$ac_ext
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+_LT_EOF
+	  # Now generate the symbol file.
+	  eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext'
+
+	  cat <<_LT_EOF >> conftest.$ac_ext
+
+/* The mapping between symbol names and symbols.  */
+const struct {
+  const char *name;
+  void       *address;
+}
+lt__PROGRAM__LTX_preloaded_symbols[] =
+{
+  { "@PROGRAM@", (void *) 0 },
+_LT_EOF
+	  $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/  {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext
+	  cat <<\_LT_EOF >> conftest.$ac_ext
+  {0, (void *) 0}
+};
+
+/* This works around a problem in FreeBSD linker */
+#ifdef FREEBSD_WORKAROUND
+static const void *lt_preloaded_setup() {
+  return lt__PROGRAM__LTX_preloaded_symbols;
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+_LT_EOF
+	  # Now try linking the two files.
+	  mv conftest.$ac_objext conftstm.$ac_objext
+	  lt_save_LIBS="$LIBS"
+	  lt_save_CFLAGS="$CFLAGS"
+	  LIBS="conftstm.$ac_objext"
+	  CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag"
+	  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext}; then
+	    pipe_works=yes
+	  fi
+	  LIBS="$lt_save_LIBS"
+	  CFLAGS="$lt_save_CFLAGS"
+	else
+	  echo "cannot find nm_test_func in $nlist" >&5
+	fi
+      else
+	echo "cannot find nm_test_var in $nlist" >&5
+      fi
+    else
+      echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5
+    fi
+  else
+    echo "$progname: failed program was:" >&5
+    cat conftest.$ac_ext >&5
+  fi
+  rm -f conftest* conftst*
+
+  # Do not use the global_symbol_pipe unless it works.
+  if test "$pipe_works" = yes; then
+    break
+  else
+    lt_cv_sys_global_symbol_pipe=
+  fi
+done
+
+fi
+
+if test -z "$lt_cv_sys_global_symbol_pipe"; then
+  lt_cv_sys_global_symbol_to_cdecl=
+fi
+if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then
+  echo "$as_me:$LINENO: result: failed" >&5
+echo "${ECHO_T}failed" >&6
+else
+  echo "$as_me:$LINENO: result: ok" >&5
+echo "${ECHO_T}ok" >&6
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# Check whether --enable-libtool-lock or --disable-libtool-lock was given.
+if test "${enable_libtool_lock+set}" = set; then
+  enableval="$enable_libtool_lock"
+
 fi;
-test x"$pic_mode" = xyes && libtool_flags="$libtool_flags --prefer-pic"
-test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
+test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes
 
 # Some flags need to be propagated to the compiler or linker for good
 # libtool support.
 case $host in
-*-*-irix6*)
+ia64-*-hpux*)
   # Find out which ABI we are using.
-  echo '#line 3870 "configure"' > conftest.$ac_ext
+  echo 'int i;' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-   if test "$lt_cv_prog_gnu_ld" = yes; then
-    case `/usr/bin/file conftest.$ac_objext` in
-    *32-bit*)
-      LD="${LD-ld} -melf32bsmip"
-      ;;
-    *N32*)
-      LD="${LD-ld} -melf32bmipn32"
-      ;;
-    *64-bit*)
-      LD="${LD-ld} -melf64bmip"
-      ;;
-    esac
-   else
     case `/usr/bin/file conftest.$ac_objext` in
-    *32-bit*)
-      LD="${LD-ld} -32"
-      ;;
-    *N32*)
-      LD="${LD-ld} -n32"
-      ;;
-    *64-bit*)
-      LD="${LD-ld} -64"
-      ;;
+      *ELF-32*)
+	HPUX_IA64_MODE="32"
+	;;
+      *ELF-64*)
+	HPUX_IA64_MODE="64"
+	;;
     esac
-   fi
   fi
   rm -rf conftest*
   ;;
-
-ia64-*-hpux*)
+*-*-irix6*)
   # Find out which ABI we are using.
-  echo 'int i;' > conftest.$ac_ext
+  echo '#line 4822 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-    case "`/usr/bin/file conftest.o`" in
-    *ELF-32*)
-      HPUX_IA64_MODE="32"
-      ;;
-    *ELF-64*)
-      HPUX_IA64_MODE="64"
-      ;;
-    esac
+    if test "$lt_cv_prog_gnu_ld" = yes; then
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -melf32bsmip"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -melf32bmipn32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -melf64bmip"
+	;;
+      esac
+    else
+      case `/usr/bin/file conftest.$ac_objext` in
+	*32-bit*)
+	  LD="${LD-ld} -32"
+	  ;;
+	*N32*)
+	  LD="${LD-ld} -n32"
+	  ;;
+	*64-bit*)
+	  LD="${LD-ld} -64"
+	  ;;
+      esac
+    fi
   fi
   rm -rf conftest*
   ;;
 
-x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
+x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \
+s390*-*linux*|s390*-*tpf*|sparc*-*linux*)
   # Find out which ABI we are using.
   echo 'int i;' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
@@ -3930,39 +4863,45 @@ x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; then
-    case "`/usr/bin/file conftest.o`" in
-    *32-bit*)
-      case $host in
-        x86_64-*linux*)
-          LD="${LD-ld} -m elf_i386"
-          ;;
-        ppc64-*linux*|powerpc64-*linux*)
-          LD="${LD-ld} -m elf32ppclinux"
-          ;;
-        s390x-*linux*)
-          LD="${LD-ld} -m elf_s390"
-          ;;
-        sparc64-*linux*)
-          LD="${LD-ld} -m elf32_sparc"
-          ;;
-      esac
-      ;;
-    *64-bit*)
-      case $host in
-        x86_64-*linux*)
-          LD="${LD-ld} -m elf_x86_64"
-          ;;
-        ppc*-*linux*|powerpc*-*linux*)
-          LD="${LD-ld} -m elf64ppc"
-          ;;
-        s390*-*linux*)
-          LD="${LD-ld} -m elf64_s390"
-          ;;
-        sparc*-*linux*)
-          LD="${LD-ld} -m elf64_sparc"
-          ;;
-      esac
-      ;;
+    case `/usr/bin/file conftest.o` in
+      *32-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_i386_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_i386"
+	    ;;
+	  ppc64-*linux*|powerpc64-*linux*)
+	    LD="${LD-ld} -m elf32ppclinux"
+	    ;;
+	  s390x-*linux*)
+	    LD="${LD-ld} -m elf_s390"
+	    ;;
+	  sparc64-*linux*)
+	    LD="${LD-ld} -m elf32_sparc"
+	    ;;
+	esac
+	;;
+      *64-bit*)
+	case $host in
+	  x86_64-*kfreebsd*-gnu)
+	    LD="${LD-ld} -m elf_x86_64_fbsd"
+	    ;;
+	  x86_64-*linux*)
+	    LD="${LD-ld} -m elf_x86_64"
+	    ;;
+	  ppc*-*linux*|powerpc*-*linux*)
+	    LD="${LD-ld} -m elf64ppc"
+	    ;;
+	  s390*-*linux*|s390*-*tpf*)
+	    LD="${LD-ld} -m elf64_s390"
+	    ;;
+	  sparc*-*linux*)
+	    LD="${LD-ld} -m elf64_sparc"
+	    ;;
+	esac
+	;;
     esac
   fi
   rm -rf conftest*
@@ -3977,9 +4916,7 @@ echo $ECHO_N "checking whether the C compiler needs -belf... $ECHO_C" >&6
 if test "${lt_cv_cc_needs_belf+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-
-
-     ac_ext=c
+  ac_ext=c
 ac_cpp='$CPP $CPPFLAGS'
 ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
 ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
@@ -4045,112 +4982,4551 @@ echo "${ECHO_T}$lt_cv_cc_needs_belf" >&6
     CFLAGS="$SAVE_CFLAGS"
   fi
   ;;
+sparc*-*solaris*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+    case `/usr/bin/file conftest.o` in
+    *64-bit*)
+      case $lt_cv_prog_gnu_ld in
+      yes*) LD="${LD-ld} -m elf64_sparc" ;;
+      *)    LD="${LD-ld} -64" ;;
+      esac
+      ;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+esac
+
+need_locks="$enable_libtool_lock"
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
+echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+  CPP=
+fi
+if test -z "$CPP"; then
+  if test "${ac_cv_prog_CPP+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+      # Double quotes because CPP needs to be expanded
+    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+    do
+      ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+		     Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  :
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether non-existent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  # Broken: success on invalid input.
+continue
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  break
+fi
+
+    done
+    ac_cv_prog_CPP=$CPP
+
+fi
+  CPP=$ac_cv_prog_CPP
+else
+  ac_cv_prog_CPP=$CPP
+fi
+echo "$as_me:$LINENO: result: $CPP" >&5
+echo "${ECHO_T}$CPP" >&6
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+  # Use a header file that comes with gcc, so configuring glibc
+  # with a fresh cross-compiler works.
+  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+  # <limits.h> exists even on freestanding compilers.
+  # On the NeXT, cc -E runs the code through the compiler's parser,
+  # not just through cpp. "Syntax error" is here to catch this case.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+		     Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  :
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+  # OK, works on sane cases.  Now check whether non-existent headers
+  # can be detected and how.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } >/dev/null; then
+  if test -s conftest.err; then
+    ac_cpp_err=$ac_c_preproc_warn_flag
+    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+  else
+    ac_cpp_err=
+  fi
+else
+  ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+  # Broken: success on invalid input.
+continue
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+  # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+  :
+else
+  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&5
+echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&2;}
+   { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+echo "$as_me:$LINENO: checking for ANSI C header files" >&5
+echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
+if test "${ac_cv_header_stdc+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_header_stdc=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_header_stdc=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <string.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "memchr" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <stdlib.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+  $EGREP "free" >/dev/null 2>&1; then
+  :
+else
+  ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+  if test "$cross_compiling" = yes; then
+  :
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <ctype.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+		   (('a' <= (c) && (c) <= 'i') \
+		     || ('j' <= (c) && (c) <= 'r') \
+		     || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+  int i;
+  for (i = 0; i < 256; i++)
+    if (XOR (islower (i), ISLOWER (i))
+	|| toupper (i) != TOUPPER (i))
+      exit(2);
+  exit (0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  :
+else
+  echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_header_stdc=no
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
+echo "${ECHO_T}$ac_cv_header_stdc" >&6
+if test $ac_cv_header_stdc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define STDC_HEADERS 1
+_ACEOF
+
+fi
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+
+
+
+
+
+
+
+
+
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+		  inttypes.h stdint.h unistd.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  eval "$as_ac_Header=yes"
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in dlfcn.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  eval "$as_ac_Header=yes"
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+  cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+# This can be used to rebuild libtool when needed
+LIBTOOL_DEPS="$ltmain"
+
+# Always use our own libtool.
+LIBTOOL='$(SHELL) $(top_builddir)/libtool'
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+test -z "$LN_S" && LN_S="ln -s"
+
+
 
 
+
+
+
+
+
+
+
+
+
+
+if test -n "${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+
+echo "$as_me:$LINENO: checking for objdir" >&5
+echo $ECHO_N "checking for objdir... $ECHO_C" >&6
+if test "${lt_cv_objdir+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  rm -f .libs 2>/dev/null
+mkdir .libs 2>/dev/null
+if test -d .libs; then
+  lt_cv_objdir=.libs
+else
+  # MS-DOS does not allow filenames that begin with a dot.
+  lt_cv_objdir=_libs
+fi
+rmdir .libs 2>/dev/null
+fi
+echo "$as_me:$LINENO: result: $lt_cv_objdir" >&5
+echo "${ECHO_T}$lt_cv_objdir" >&6
+objdir=$lt_cv_objdir
+
+
+
+
+
+cat >>confdefs.h <<_ACEOF
+#define LT_OBJDIR "$lt_cv_objdir/"
+_ACEOF
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+case $host_os in
+aix3*)
+  # AIX sometimes has problems with the GCC collect2 program.  For some
+  # reason, if we set the COLLECT_NAMES environment variable, the problems
+  # vanish in a puff of smoke.
+  if test "X${COLLECT_NAMES+set}" != Xset; then
+    COLLECT_NAMES=
+    export COLLECT_NAMES
+  fi
+  ;;
 esac
 
+# Sed substitution that helps us do robust quoting.  It backslashifies
+# metacharacters that are still active within double-quoted strings.
+sed_quote_subst='s/\(["`$\\]\)/\\\1/g'
+
+# Same as above, but do not quote variable references.
+double_quote_subst='s/\(["`\\]\)/\\\1/g'
+
+# Sed substitution to delay expansion of an escaped shell variable in a
+# double_quote_subst'ed string.
+delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g'
+
+# Sed substitution to delay expansion of an escaped single quote.
+delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g'
+
+# Sed substitution to avoid accidental globbing in evaled expressions
+no_glob_subst='s/\*/\\\*/g'
+
+# Global variables:
+ofile=libtool
+can_build_shared=yes
+
+# All known linkers require a `.a' archive for static linking (except MSVC,
+# which needs '.lib').
+libext=a
+
+with_gnu_ld="$lt_cv_prog_gnu_ld"
+
+old_CC="$CC"
+old_CFLAGS="$CFLAGS"
+
+# Set sane defaults for various variables
+test -z "$CC" && CC=cc
+test -z "$LTCC" && LTCC=$CC
+test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS
+test -z "$LD" && LD=ld
+test -z "$ac_objext" && ac_objext=o
+
+for cc_temp in $compiler""; do
+  case $cc_temp in
+    compile | *[\\/]compile | ccache | *[\\/]ccache ) ;;
+    distcc | *[\\/]distcc | purify | *[\\/]purify ) ;;
+    \-*) ;;
+    *) break;;
+  esac
+done
+cc_basename=`$ECHO "X$cc_temp" | $Xsed -e 's%.*/%%' -e "s%^$host_alias-%%"`
+
+
+# Only perform the check for file, if the check method requires it
+test -z "$MAGIC_CMD" && MAGIC_CMD=file
+case $deplibs_check_method in
+file_magic*)
+  if test "$file_magic_cmd" = '$MAGIC_CMD'; then
+    echo "$as_me:$LINENO: checking for ${ac_tool_prefix}file" >&5
+echo $ECHO_N "checking for ${ac_tool_prefix}file... $ECHO_C" >&6
+if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  case $MAGIC_CMD in
+[\\/*] |  ?:[\\/]*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+*)
+  lt_save_MAGIC_CMD="$MAGIC_CMD"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
+  for ac_dir in $ac_dummy; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/${ac_tool_prefix}file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file"
+      if test -n "$file_magic_test_file"; then
+	case $deplibs_check_method in
+	"file_magic "*)
+	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    $EGREP "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<_LT_EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+_LT_EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$lt_save_ifs"
+  MAGIC_CMD="$lt_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
+echo "${ECHO_T}$MAGIC_CMD" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+
+
+
+
+if test -z "$lt_cv_path_MAGIC_CMD"; then
+  if test -n "$ac_tool_prefix"; then
+    echo "$as_me:$LINENO: checking for file" >&5
+echo $ECHO_N "checking for file... $ECHO_C" >&6
+if test "${lt_cv_path_MAGIC_CMD+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  case $MAGIC_CMD in
+[\\/*] |  ?:[\\/]*)
+  lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path.
+  ;;
+*)
+  lt_save_MAGIC_CMD="$MAGIC_CMD"
+  lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR
+  ac_dummy="/usr/bin$PATH_SEPARATOR$PATH"
+  for ac_dir in $ac_dummy; do
+    IFS="$lt_save_ifs"
+    test -z "$ac_dir" && ac_dir=.
+    if test -f $ac_dir/file; then
+      lt_cv_path_MAGIC_CMD="$ac_dir/file"
+      if test -n "$file_magic_test_file"; then
+	case $deplibs_check_method in
+	"file_magic "*)
+	  file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"`
+	  MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+	  if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null |
+	    $EGREP "$file_magic_regex" > /dev/null; then
+	    :
+	  else
+	    cat <<_LT_EOF 1>&2
+
+*** Warning: the command libtool uses to detect shared libraries,
+*** $file_magic_cmd, produces output that libtool cannot recognize.
+*** The result is that libtool may fail to recognize shared libraries
+*** as such.  This will affect the creation of libtool libraries that
+*** depend on shared libraries, but programs linked with such libtool
+*** libraries will work regardless of this problem.  Nevertheless, you
+*** may want to report the problem to your system manager and/or to
+*** bug-libtool@gnu.org
+
+_LT_EOF
+	  fi ;;
+	esac
+      fi
+      break
+    fi
+  done
+  IFS="$lt_save_ifs"
+  MAGIC_CMD="$lt_save_MAGIC_CMD"
+  ;;
+esac
+fi
+
+MAGIC_CMD="$lt_cv_path_MAGIC_CMD"
+if test -n "$MAGIC_CMD"; then
+  echo "$as_me:$LINENO: result: $MAGIC_CMD" >&5
+echo "${ECHO_T}$MAGIC_CMD" >&6
+else
+  echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+
+  else
+    MAGIC_CMD=:
+  fi
+fi
+
+  fi
+  ;;
+esac
+
+# Use C for the default configuration in the libtool script
+
+lt_save_CC="$CC"
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+# Source file extension for C test sources.
+ac_ext=c
+
+# Object file extension for compiled C test sources.
+objext=o
+objext=$objext
+
+# Code to be used in simple compile tests
+lt_simple_compile_test_code="int some_variable = 0;"
+
+# Code to be used in simple link tests
+lt_simple_link_test_code='int main(){return(0);}'
+
+
+
+
+
+
+
+# If no C compiler was specified, use CC.
+LTCC=${LTCC-"$CC"}
+
+# If no C compiler flags were specified, use CFLAGS.
+LTCFLAGS=${LTCFLAGS-"$CFLAGS"}
+
+# Allow CC to be a program name with arguments.
+compiler=$CC
+
+# Save the default compiler, since it gets overwritten when the other
+# tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP.
+compiler_DEFAULT=$CC
+
+# save warnings/boilerplate of simple test code
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_compile_test_code" >conftest.$ac_ext
+eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_compiler_boilerplate=`cat conftest.err`
+$RM conftest*
+
+ac_outfile=conftest.$ac_objext
+echo "$lt_simple_link_test_code" >conftest.$ac_ext
+eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err
+_lt_linker_boilerplate=`cat conftest.err`
+$RM conftest*
+
+
+## CAVEAT EMPTOR:
+## There is no encapsulation within the following macros, do not change
+## the running order or otherwise move them around unless you know exactly
+## what you are doing...
+if test -n "$compiler"; then
+
+lt_prog_compiler_no_builtin_flag=
+
+if test "$GCC" = yes; then
+  lt_prog_compiler_no_builtin_flag=' -fno-builtin'
+
+  echo "$as_me:$LINENO: checking if $compiler supports -fno-rtti -fno-exceptions" >&5
+echo $ECHO_N "checking if $compiler supports -fno-rtti -fno-exceptions... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_rtti_exceptions+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_rtti_exceptions=no
+   ac_outfile=conftest.$ac_objext
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+   lt_compiler_flag="-fno-rtti -fno-exceptions"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   # The option is referenced via a variable to avoid confusing sed.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:5922: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>conftest.err)
+   ac_status=$?
+   cat conftest.err >&5
+   echo "$as_me:5926: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s "$ac_outfile"; then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings other than the usual output.
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp
+     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_rtti_exceptions=yes
+     fi
+   fi
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_rtti_exceptions" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_rtti_exceptions" >&6
+
+if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then
+    lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions"
+else
+    :
+fi
+
+fi
+
+
+
+
+
+
+  lt_prog_compiler_wl=
+lt_prog_compiler_pic=
+lt_prog_compiler_static=
+
+echo "$as_me:$LINENO: checking for $compiler option to produce PIC" >&5
+echo $ECHO_N "checking for $compiler option to produce PIC... $ECHO_C" >&6
+
+  if test "$GCC" = yes; then
+    lt_prog_compiler_wl='-Wl,'
+    lt_prog_compiler_static='-static'
+
+    case $host_os in
+      aix*)
+      # All AIX code is PIC.
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	lt_prog_compiler_static='-Bstatic'
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        # FIXME: we need at least 68020 code to build shared libraries, but
+        # adding the `-m68020' flag to GCC prevents building anything better,
+        # like `-m68040'.
+        lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4'
+      fi
+      ;;
+
+    beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*)
+      # PIC is the default for these OSes.
+      ;;
+
+    mingw* | cygwin* | pw32* | os2*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      # Although the cygwin gcc ignores -fPIC, still need this for old-style
+      # (--disable-auto-import) libraries
+      lt_prog_compiler_pic='-DDLL_EXPORT'
+      ;;
+
+    darwin* | rhapsody*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      lt_prog_compiler_pic='-fno-common'
+      ;;
+
+    hpux*)
+      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
+      # not for PA HP-UX.
+      case $host_cpu in
+      hppa*64*|ia64*)
+	# +Z the default
+	;;
+      *)
+	lt_prog_compiler_pic='-fPIC'
+	;;
+      esac
+      ;;
+
+    interix[3-9]*)
+      # Interix 3.x gcc -fpic/-fPIC options generate broken code.
+      # Instead, we relocate shared libraries at runtime.
+      ;;
+
+    msdosdjgpp*)
+      # Just because we use GCC doesn't mean we suddenly get shared libraries
+      # on systems that don't support them.
+      lt_prog_compiler_can_build_shared=no
+      enable_shared=no
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      lt_prog_compiler_pic='-fPIC -shared'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	lt_prog_compiler_pic=-Kconform_pic
+      fi
+      ;;
+
+    *)
+      lt_prog_compiler_pic='-fPIC'
+      ;;
+    esac
+  else
+    # PORTME Check for flag to pass linker flags through the system compiler.
+    case $host_os in
+    aix*)
+      lt_prog_compiler_wl='-Wl,'
+      if test "$host_cpu" = ia64; then
+	# AIX 5 now supports IA64 processor
+	lt_prog_compiler_static='-Bstatic'
+      else
+	lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp'
+      fi
+      ;;
+    darwin*)
+      # PIC is the default on this platform
+      # Common symbols not allowed in MH_DYLIB files
+      case $cc_basename in
+      xlc*)
+        lt_prog_compiler_pic='-qnocommon'
+        lt_prog_compiler_wl='-Wl,'
+        ;;
+      esac
+      ;;
+
+    mingw* | cygwin* | pw32* | os2*)
+      # This hack is so that the source file can tell whether it is being
+      # built for inclusion in a dll (and should export symbols for example).
+      lt_prog_compiler_pic='-DDLL_EXPORT'
+      ;;
+
+    hpux9* | hpux10* | hpux11*)
+      lt_prog_compiler_wl='-Wl,'
+      # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but
+      # not for PA HP-UX.
+      case $host_cpu in
+      hppa*64*|ia64*)
+	# +Z the default
+	;;
+      *)
+	lt_prog_compiler_pic='+Z'
+	;;
+      esac
+      # Is there a better lt_prog_compiler_static that works with the bundled CC?
+      lt_prog_compiler_static='${wl}-a ${wl}archive'
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      lt_prog_compiler_wl='-Wl,'
+      # PIC (with -KPIC) is the default.
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    linux* | k*bsd*-gnu)
+      case $cc_basename in
+      icc* | ecc*)
+	lt_prog_compiler_wl='-Wl,'
+	lt_prog_compiler_pic='-KPIC'
+	lt_prog_compiler_static='-static'
+        ;;
+      pgcc* | pgf77* | pgf90* | pgf95*)
+        # Portland Group compilers (*not* the Pentium gcc compiler,
+	# which looks to be a dead project)
+	lt_prog_compiler_wl='-Wl,'
+	lt_prog_compiler_pic='-fpic'
+	lt_prog_compiler_static='-Bstatic'
+        ;;
+      ccc*)
+        lt_prog_compiler_wl='-Wl,'
+        # All Alpha code is PIC.
+        lt_prog_compiler_static='-non_shared'
+        ;;
+      *)
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ C*)
+	  # Sun C 5.9
+	  lt_prog_compiler_pic='-KPIC'
+	  lt_prog_compiler_static='-Bstatic'
+	  lt_prog_compiler_wl='-Wl,'
+	  ;;
+	*Sun\ F*)
+	  # Sun Fortran 8.3 passes all unrecognized flags to the linker
+	  lt_prog_compiler_pic='-KPIC'
+	  lt_prog_compiler_static='-Bstatic'
+	  lt_prog_compiler_wl=''
+	  ;;
+	esac
+	;;
+      esac
+      ;;
+
+    newsos6)
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    *nto* | *qnx*)
+      # QNX uses GNU C++, but need to define -shared option too, otherwise
+      # it will coredump.
+      lt_prog_compiler_pic='-fPIC -shared'
+      ;;
+
+    osf3* | osf4* | osf5*)
+      lt_prog_compiler_wl='-Wl,'
+      # All OSF/1 code is PIC.
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    rdos*)
+      lt_prog_compiler_static='-non_shared'
+      ;;
+
+    solaris*)
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      case $cc_basename in
+      f77* | f90* | f95*)
+	lt_prog_compiler_wl='-Qoption ld ';;
+      *)
+	lt_prog_compiler_wl='-Wl,';;
+      esac
+      ;;
+
+    sunos4*)
+      lt_prog_compiler_wl='-Qoption ld '
+      lt_prog_compiler_pic='-PIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    sysv4 | sysv4.2uw2* | sysv4.3*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec ;then
+	lt_prog_compiler_pic='-Kconform_pic'
+	lt_prog_compiler_static='-Bstatic'
+      fi
+      ;;
+
+    sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_pic='-KPIC'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    unicos*)
+      lt_prog_compiler_wl='-Wl,'
+      lt_prog_compiler_can_build_shared=no
+      ;;
+
+    uts4*)
+      lt_prog_compiler_pic='-pic'
+      lt_prog_compiler_static='-Bstatic'
+      ;;
+
+    *)
+      lt_prog_compiler_can_build_shared=no
+      ;;
+    esac
+  fi
+
+case $host_os in
+  # For platforms which do not support PIC, -DPIC is meaningless:
+  *djgpp*)
+    lt_prog_compiler_pic=
+    ;;
+  *)
+    lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC"
+    ;;
+esac
+echo "$as_me:$LINENO: result: $lt_prog_compiler_pic" >&5
+echo "${ECHO_T}$lt_prog_compiler_pic" >&6
+
+
+
+
+
 
-# Save cache, so that ltconfig can load it
-cat >confcache <<\_ACEOF
-# This file is a shell script that caches the results of configure
-# tests run on this system so they can be shared between configure
-# scripts and configure runs, see configure's option --config-cache.
-# It is not useful on other systems.  If it contains results you don't
-# want to keep, you may remove or edit it.
 #
-# config.status only pays attention to the cache file if you give it
-# the --recheck option to rerun configure.
+# Check to make sure the PIC flag actually works.
 #
-# `ac_cv_env_foo' variables (set or unset) will be overridden when
-# loading this file, other *unset* `ac_cv_foo' will be assigned the
-# following values.
+if test -n "$lt_prog_compiler_pic"; then
+  echo "$as_me:$LINENO: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5
+echo $ECHO_N "checking if $compiler PIC flag $lt_prog_compiler_pic works... $ECHO_C" >&6
+if test "${lt_prog_compiler_pic_works+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_prog_compiler_pic_works=no
+   ac_outfile=conftest.$ac_objext
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+   lt_compiler_flag="$lt_prog_compiler_pic -DPIC"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   # The option is referenced via a variable to avoid confusing sed.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6244: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>conftest.err)
+   ac_status=$?
+   cat conftest.err >&5
+   echo "$as_me:6248: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s "$ac_outfile"; then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings other than the usual output.
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' >conftest.exp
+     $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+     if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then
+       lt_prog_compiler_pic_works=yes
+     fi
+   fi
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_prog_compiler_pic_works" >&5
+echo "${ECHO_T}$lt_prog_compiler_pic_works" >&6
+
+if test x"$lt_prog_compiler_pic_works" = xyes; then
+    case $lt_prog_compiler_pic in
+     "" | " "*) ;;
+     *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;;
+     esac
+else
+    lt_prog_compiler_pic=
+     lt_prog_compiler_can_build_shared=no
+fi
+
+fi
+
+
+
+
+
+
+#
+# Check to make sure the static flag actually works.
+#
+wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\"
+echo "$as_me:$LINENO: checking if $compiler static flag $lt_tmp_static_flag works" >&5
+echo $ECHO_N "checking if $compiler static flag $lt_tmp_static_flag works... $ECHO_C" >&6
+if test "${lt_prog_compiler_static_works+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_prog_compiler_static_works=no
+   save_LDFLAGS="$LDFLAGS"
+   LDFLAGS="$LDFLAGS $lt_tmp_static_flag"
+   echo "$lt_simple_link_test_code" > conftest.$ac_ext
+   if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then
+     # The linker can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     if test -s conftest.err; then
+       # Append any errors to the config.log.
+       cat conftest.err 1>&5
+       $ECHO "X$_lt_linker_boilerplate" | $Xsed -e '/^$/d' > conftest.exp
+       $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2
+       if diff conftest.exp conftest.er2 >/dev/null; then
+         lt_prog_compiler_static_works=yes
+       fi
+     else
+       lt_prog_compiler_static_works=yes
+     fi
+   fi
+   $RM conftest*
+   LDFLAGS="$save_LDFLAGS"
+
+fi
+echo "$as_me:$LINENO: result: $lt_prog_compiler_static_works" >&5
+echo "${ECHO_T}$lt_prog_compiler_static_works" >&6
+
+if test x"$lt_prog_compiler_static_works" = xyes; then
+    :
+else
+    lt_prog_compiler_static=
+fi
+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5
+echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_c_o+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_c_o=no
+   $RM -r conftest 2>/dev/null
+   mkdir conftest
+   cd conftest
+   mkdir out
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+   lt_compiler_flag="-o out/conftest2.$ac_objext"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6349: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>out/conftest.err)
+   ac_status=$?
+   cat out/conftest.err >&5
+   echo "$as_me:6353: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s out/conftest2.$ac_objext
+   then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp
+     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
+     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_c_o=yes
+     fi
+   fi
+   chmod u+w . 2>&5
+   $RM conftest*
+   # SGI C++ compiler will create directory out/ii_files/ for
+   # template instantiation
+   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
+   $RM out/* && rmdir out
+   cd ..
+   $RM -r conftest
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking if $compiler supports -c -o file.$ac_objext" >&5
+echo $ECHO_N "checking if $compiler supports -c -o file.$ac_objext... $ECHO_C" >&6
+if test "${lt_cv_prog_compiler_c_o+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_prog_compiler_c_o=no
+   $RM -r conftest 2>/dev/null
+   mkdir conftest
+   cd conftest
+   mkdir out
+   echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+   lt_compiler_flag="-o out/conftest2.$ac_objext"
+   # Insert the option either (1) after the last *FLAGS variable, or
+   # (2) before a word containing "conftest.", or (3) at the end.
+   # Note that $ac_compile itself does not contain backslashes and begins
+   # with a dollar sign (not a hyphen), so the echo should work correctly.
+   lt_compile=`echo "$ac_compile" | $SED \
+   -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
+   -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
+   -e 's:$: $lt_compiler_flag:'`
+   (eval echo "\"\$as_me:6404: $lt_compile\"" >&5)
+   (eval "$lt_compile" 2>out/conftest.err)
+   ac_status=$?
+   cat out/conftest.err >&5
+   echo "$as_me:6408: \$? = $ac_status" >&5
+   if (exit $ac_status) && test -s out/conftest2.$ac_objext
+   then
+     # The compiler can only warn and ignore the option if not recognized
+     # So say no if there are warnings
+     $ECHO "X$_lt_compiler_boilerplate" | $Xsed -e '/^$/d' > out/conftest.exp
+     $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2
+     if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then
+       lt_cv_prog_compiler_c_o=yes
+     fi
+   fi
+   chmod u+w . 2>&5
+   $RM conftest*
+   # SGI C++ compiler will create directory out/ii_files/ for
+   # template instantiation
+   test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files
+   $RM out/* && rmdir out
+   cd ..
+   $RM -r conftest
+   $RM conftest*
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_prog_compiler_c_o" >&5
+echo "${ECHO_T}$lt_cv_prog_compiler_c_o" >&6
+
+
+
+
+hard_links="nottested"
+if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then
+  # do not overwrite the value of need_locks provided by the user
+  echo "$as_me:$LINENO: checking if we can lock with hard links" >&5
+echo $ECHO_N "checking if we can lock with hard links... $ECHO_C" >&6
+  hard_links=yes
+  $RM conftest*
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  touch conftest.a
+  ln conftest.a conftest.b 2>&5 || hard_links=no
+  ln conftest.a conftest.b 2>/dev/null && hard_links=no
+  echo "$as_me:$LINENO: result: $hard_links" >&5
+echo "${ECHO_T}$hard_links" >&6
+  if test "$hard_links" = no; then
+    { echo "$as_me:$LINENO: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5
+echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;}
+    need_locks=warn
+  fi
+else
+  need_locks=no
+fi
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking whether the $compiler linker ($LD) supports shared libraries" >&5
+echo $ECHO_N "checking whether the $compiler linker ($LD) supports shared libraries... $ECHO_C" >&6
+
+  runpath_var=
+  allow_undefined_flag=
+  always_export_symbols=no
+  archive_cmds=
+  archive_expsym_cmds=
+  compiler_needs_object=no
+  enable_shared_with_static_runtimes=no
+  export_dynamic_flag_spec=
+  export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols'
+  hardcode_automatic=no
+  hardcode_direct=no
+  hardcode_direct_absolute=no
+  hardcode_libdir_flag_spec=
+  hardcode_libdir_flag_spec_ld=
+  hardcode_libdir_separator=
+  hardcode_minus_L=no
+  hardcode_shlibpath_var=unsupported
+  inherit_rpath=no
+  link_all_deplibs=unknown
+  module_cmds=
+  module_expsym_cmds=
+  old_archive_from_new_cmds=
+  old_archive_from_expsyms_cmds=
+  thread_safe_flag_spec=
+  whole_archive_flag_spec=
+  # include_expsyms should be a list of space-separated symbols to be *always*
+  # included in the symbol list
+  include_expsyms=
+  # exclude_expsyms can be an extended regexp of symbols to exclude
+  # it will be wrapped by ` (' and `)$', so one must not match beginning or
+  # end of line.  Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc',
+  # as well as any symbol that contains `d'.
+  exclude_expsyms="_GLOBAL_OFFSET_TABLE_"
+  # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out
+  # platforms (ab)use it in PIC code, but their linkers get confused if
+  # the symbol is explicitly referenced.  Since portable code cannot
+  # rely on this symbol name, it's probably fine to never include it in
+  # preloaded symbol tables.
+  extract_expsyms_cmds=
+
+  case $host_os in
+  cygwin* | mingw* | pw32*)
+    # FIXME: the MSVC++ port hasn't been tested in a loooong time
+    # When not using gcc, we currently assume that we are using
+    # Microsoft Visual C++.
+    if test "$GCC" != yes; then
+      with_gnu_ld=no
+    fi
+    ;;
+  interix*)
+    # we just hope/assume this is gcc and not c89 (= MSVC++)
+    with_gnu_ld=yes
+    ;;
+  openbsd*)
+    with_gnu_ld=no
+    ;;
+  esac
+
+  ld_shlibs=yes
+  if test "$with_gnu_ld" = yes; then
+    # If archive_cmds runs LD, not CC, wlarc should be empty
+    wlarc='${wl}'
+
+    # Set some defaults for GNU ld with shared library support. These
+    # are reset later if shared libraries are not supported. Putting them
+    # here allows them to be overridden if necessary.
+    runpath_var=LD_RUN_PATH
+    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+    export_dynamic_flag_spec='${wl}--export-dynamic'
+    # ancient GNU ld didn't support --whole-archive et. al.
+    if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then
+      whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
+    else
+      whole_archive_flag_spec=
+    fi
+    supports_anon_versioning=no
+    case `$LD -v 2>&1` in
+      *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11
+      *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ...
+      *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ...
+      *\ 2.11.*) ;; # other 2.11 versions
+      *) supports_anon_versioning=yes ;;
+    esac
+
+    # See if GNU ld supports shared libraries.
+    case $host_os in
+    aix3* | aix4* | aix5*)
+      # On AIX/PPC, the GNU linker is very broken
+      if test "$host_cpu" != ia64; then
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: the GNU linker, at least up to release 2.9.1, is reported
+*** to be unable to reliably create shared libraries on AIX.
+*** Therefore, libtool is disabling shared libraries support.  If you
+*** really care for shared libraries, you may want to modify your PATH
+*** so that a non-GNU linker is found, and then restart.
+
+_LT_EOF
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+        hardcode_libdir_flag_spec='-L$libdir'
+        hardcode_minus_L=yes
+      fi
+
+      # Samuel A. Falvo II <kc5tja@dolphin.openprojects.net> reports
+      # that the semantics of dynamic libraries on AmigaOS, at least up
+      # to version 4, is to share data among multiple programs linked
+      # with the same dynamic library.  Since this doesn't match the
+      # behavior of shared libraries on other platforms, we can't use
+      # them.
+      ld_shlibs=no
+      ;;
+
+    beos*)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	allow_undefined_flag=unsupported
+	# Joseph Beckenbach <jrb3@best.com> says some releases of gcc
+	# support --undefined.  This deserves some investigation.  FIXME
+	archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    cygwin* | mingw* | pw32*)
+      # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless,
+      # as there is no search path for DLLs.
+      hardcode_libdir_flag_spec='-L$libdir'
+      allow_undefined_flag=unsupported
+      always_export_symbols=no
+      enable_shared_with_static_runtimes=yes
+      export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols'
+
+      if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then
+        archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+	# If the export-symbols file already is a .def file (1st line
+	# is EXPORTS), use it as is; otherwise, prepend...
+	archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then
+	  cp $export_symbols $output_objdir/$soname.def;
+	else
+	  echo EXPORTS > $output_objdir/$soname.def;
+	  cat $export_symbols >> $output_objdir/$soname.def;
+	fi~
+	$CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    interix[3-9]*)
+      hardcode_direct=no
+      hardcode_shlibpath_var=no
+      hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+      export_dynamic_flag_spec='${wl}-E'
+      # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc.
+      # Instead, shared libraries are loaded at an image base (0x10000000 by
+      # default) and relocated if they conflict, which is a slow very memory
+      # consuming and fragmenting process.  To avoid this, we pick a random,
+      # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link
+      # time.  Moving up from 0x10000000 also allows more sbrk(2) space.
+      archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib'
+      ;;
+
+    gnu* | linux* | tpf* | k*bsd*-gnu)
+      tmp_diet=no
+      if test "$host_os" = linux-dietlibc; then
+	case $cc_basename in
+	  diet\ *) tmp_diet=yes;;	# linux-dietlibc with static linking (!diet-dyn)
+	esac
+      fi
+      if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \
+	 && test "$tmp_diet" = no
+      then
+	tmp_addflag=
+	case $cc_basename,$host_cpu in
+        pgcc*)				# Portland Group C compiler
+	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag'
+	  ;;
+	pgf77* | pgf90* | pgf95*)	# Portland Group f77 and f90 compilers
+	  whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test  -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  tmp_addflag=' $pic_flag -Mnomain' ;;
+	ecc*,ia64* | icc*,ia64*)	# Intel C compiler on ia64
+	  tmp_addflag=' -i_dynamic' ;;
+	efc*,ia64* | ifort*,ia64*)	# Intel Fortran compiler on ia64
+	  tmp_addflag=' -i_dynamic -nofor_main' ;;
+	ifc* | ifort*)			# Intel Fortran compiler
+	  tmp_addflag=' -nofor_main' ;;
+	esac
+	case `$CC -V 2>&1 | sed 5q` in
+	*Sun\ C*)			# Sun C 5.9
+	  whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; $ECHO \"$new_convenience\"` ${wl}--no-whole-archive'
+	  compiler_needs_object=yes
+	  tmp_sharedflag='-G' ;;
+	*Sun\ F*)			# Sun Fortran 8.3
+	  tmp_sharedflag='-G' ;;
+	*)
+	  tmp_sharedflag='-shared' ;;
+	esac
+	archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+
+        if test "x$supports_anon_versioning" = xyes; then
+          archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~
+	    cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~
+	    echo "local: *; };" >> $output_objdir/$libname.ver~
+	    $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib'
+        fi
+      else
+        ld_shlibs=no
+      fi
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib'
+	wlarc=
+      else
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      fi
+      ;;
+
+    solaris*)
+      if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: The releases 2.8.* of the GNU linker cannot reliably
+*** create shared libraries on Solaris systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.9.1 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+      elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*)
+      case `$LD -v 2>&1` in
+        *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*)
+	ld_shlibs=no
+	cat <<_LT_EOF 1>&2
+
+*** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not
+*** reliably create shared libraries on SCO systems.  Therefore, libtool
+*** is disabling shared libraries support.  We urge you to upgrade GNU
+*** binutils to release 2.16.91.0.3 or newer.  Another option is to modify
+*** your PATH or compiler configuration so that the native linker is
+*** used, and then restart.
+
+_LT_EOF
+	;;
+	*)
+	  # For security reasons, it is highly recommended that you always
+	  # use absolute paths for naming shared libraries, and exclude the
+	  # DT_RUNPATH tag from executables and libraries.  But doing so
+	  # requires that you compile everything twice, which is a pain.
+	  if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	    hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+	    archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	    archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+	  else
+	    ld_shlibs=no
+	  fi
+	;;
+      esac
+      ;;
+
+    sunos4*)
+      archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      wlarc=
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    *)
+      if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
+      else
+	ld_shlibs=no
+      fi
+      ;;
+    esac
+
+    if test "$ld_shlibs" = no; then
+      runpath_var=
+      hardcode_libdir_flag_spec=
+      export_dynamic_flag_spec=
+      whole_archive_flag_spec=
+    fi
+  else
+    # PORTME fill in a description of your system's linker (not GNU ld)
+    case $host_os in
+    aix3*)
+      allow_undefined_flag=unsupported
+      always_export_symbols=yes
+      archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname'
+      # Note: this linker hardcodes the directories in LIBPATH if there
+      # are no directories specified by -L.
+      hardcode_minus_L=yes
+      if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then
+	# Neither direct hardcoding nor static linking is supported with a
+	# broken collect2.
+	hardcode_direct=unsupported
+      fi
+      ;;
+
+    aix4* | aix5*)
+      if test "$host_cpu" = ia64; then
+	# On IA64, the linker does run time linking by default, so we don't
+	# have to do anything special.
+	aix_use_runtimelinking=no
+	exp_sym_flag='-Bexport'
+	no_entry_flag=""
+      else
+	# If we're using GNU nm, then we don't want the "-C" option.
+	# -C means demangle to AIX nm, but means don't demangle with GNU nm
+	if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then
+	  export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	else
+	  export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols'
+	fi
+	aix_use_runtimelinking=no
+
+	# Test if we are trying to use run time linking or normal
+	# AIX style linking. If -brtl is somewhere in LDFLAGS, we
+	# need to do runtime linking.
+	case $host_os in aix4.[23]|aix4.[23].*|aix5*)
+	  for ld_flag in $LDFLAGS; do
+	  if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then
+	    aix_use_runtimelinking=yes
+	    break
+	  fi
+	  done
+	  ;;
+	esac
+
+	exp_sym_flag='-bexport'
+	no_entry_flag='-bnoentry'
+      fi
+
+      # When large executables or shared objects are built, AIX ld can
+      # have problems creating the table of contents.  If linking a library
+      # or program results in "error TOC overflow" add -mminimal-toc to
+      # CXXFLAGS/CFLAGS for g++/gcc.  In the cases where that is not
+      # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS.
+
+      archive_cmds=''
+      hardcode_direct=yes
+      hardcode_direct_absolute=yes
+      hardcode_libdir_separator=':'
+      link_all_deplibs=yes
+      file_list_spec='${wl}-f,'
+
+      if test "$GCC" = yes; then
+	case $host_os in aix4.[012]|aix4.[012].*)
+	# We only want to do this on AIX 4.2 and lower, the check
+	# below for broken collect2 doesn't work under 4.3+
+	  collect2name=`${CC} -print-prog-name=collect2`
+	  if test -f "$collect2name" &&
+	   strings "$collect2name" | $GREP resolve_lib_name >/dev/null
+	  then
+	  # We have reworked collect2
+	  :
+	  else
+	  # We have old collect2
+	  hardcode_direct=unsupported
+	  # It fails to find uninstalled libraries when the uninstalled
+	  # path is not listed in the libpath.  Setting hardcode_minus_L
+	  # to unsupported forces relinking
+	  hardcode_minus_L=yes
+	  hardcode_libdir_flag_spec='-L$libdir'
+	  hardcode_libdir_separator=
+	  fi
+	  ;;
+	esac
+	shared_flag='-shared'
+	if test "$aix_use_runtimelinking" = yes; then
+	  shared_flag="$shared_flag "'${wl}-G'
+	fi
+      else
+	# not using gcc
+	if test "$host_cpu" = ia64; then
+	# VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release
+	# chokes on -Wl,-G. The following line is correct:
+	  shared_flag='-G'
+	else
+	  if test "$aix_use_runtimelinking" = yes; then
+	    shared_flag='${wl}-G'
+	  else
+	    shared_flag='${wl}-bM:SRE'
+	  fi
+	fi
+      fi
 
+      # It seems that -bexpall does not export symbols beginning with
+      # underscore (_), so it is better to generate a list of symbols to export.
+      always_export_symbols=yes
+      if test "$aix_use_runtimelinking" = yes; then
+	# Warning - without using the other runtime loading flags (-brtl),
+	# -berok will link without error, but may produce a broken library.
+	allow_undefined_flag='-berok'
+        # Determine the default libpath from the value encoded in an
+        # empty executable.
+        cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
 _ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
 
-# The following way of writing the cache mishandles newlines in values,
-# but we know of no workaround that is simple, portable, and efficient.
-# So, don't put newlines in cache variables' values.
-# Ultrix sh set writes to stderr and can't be redirected directly,
-# and sets the high bit in the cache file unless we assign to the vars.
+int
+main ()
 {
-  (set) 2>&1 |
-    case `(ac_space=' '; set | grep ac_space) 2>&1` in
-    *ac_space=\ *)
-      # `set' does not quote correctly, so add quotes (double-quote
-      # substitution turns \\\\ into \\, and sed turns \\ into \).
-      sed -n \
-	"s/'/'\\\\''/g;
-	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+
+lt_aix_libpath_sed='
+    /Import File Strings/,/^$/ {
+	/^0/ {
+	    s/^0  *\(.*\)$/\1/
+	    p
+	}
+    }'
+aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+# Check for a 64-bit object if we didn't find anything.
+if test -z "$aix_libpath"; then
+  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+fi
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
+
+        hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
+        archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then $ECHO "X${wl}${allow_undefined_flag}" | $Xsed; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag"
+      else
+	if test "$host_cpu" = ia64; then
+	  hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib'
+	  allow_undefined_flag="-z nodefs"
+	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols"
+	else
+	 # Determine the default libpath from the value encoded in an
+	 # empty executable.
+	 cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+
+lt_aix_libpath_sed='
+    /Import File Strings/,/^$/ {
+	/^0/ {
+	    s/^0  *\(.*\)$/\1/
+	    p
+	}
+    }'
+aix_libpath=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+# Check for a 64-bit object if we didn't find anything.
+if test -z "$aix_libpath"; then
+  aix_libpath=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"`
+fi
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi
+
+	 hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath"
+	  # Warning - without using the other run time loading flags,
+	  # -berok will link without error, but may produce a broken library.
+	  no_undefined_flag=' ${wl}-bernotok'
+	  allow_undefined_flag=' ${wl}-berok'
+	  # Exported symbols can be pulled into shared objects from archives
+	  whole_archive_flag_spec='$convenience'
+	  archive_cmds_need_lc=yes
+	  # This is similar to how AIX traditionally builds its shared libraries.
+	  archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname'
+	fi
+      fi
+      ;;
+
+    amigaos*)
+      if test "$host_cpu" = m68k; then
+        archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
+        hardcode_libdir_flag_spec='-L$libdir'
+        hardcode_minus_L=yes
+      fi
+      # see comment about different semantics on the GNU ld section
+      ld_shlibs=no
+      ;;
+
+    bsdi[45]*)
+      export_dynamic_flag_spec=-rdynamic
+      ;;
+
+    cygwin* | mingw* | pw32*)
+      # When not using gcc, we currently assume that we are using
+      # Microsoft Visual C++.
+      # hardcode_libdir_flag_spec is actually meaningless, as there is
+      # no search path for DLLs.
+      hardcode_libdir_flag_spec=' '
+      allow_undefined_flag=unsupported
+      # Tell ltmain to make .lib files, not .a files.
+      libext=lib
+      # Tell ltmain to make .dll files, not .so files.
+      shrext_cmds=".dll"
+      # FIXME: Setting linknames here is a bad hack.
+      archive_cmds='$CC -o $lib $libobjs $compiler_flags `$ECHO "X$deplibs" | $Xsed -e '\''s/ -lc$//'\''` -link -dll~linknames='
+      # The linker will automatically build a .lib file if we build a DLL.
+      old_archive_from_new_cmds='true'
+      # FIXME: Should let the user specify the lib program.
+      old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs'
+      fix_srcfile_path='`cygpath -w "$srcfile"`'
+      enable_shared_with_static_runtimes=yes
+      ;;
+
+    darwin* | rhapsody*)
+      case $host_os in
+      rhapsody* | darwin1.[012])
+	allow_undefined_flag='${wl}-undefined ${wl}suppress'
+	;;
+      *) # Darwin 1.3 on
+	case ${MACOSX_DEPLOYMENT_TARGET-10.0} in
+	10.[012])
+	  allow_undefined_flag='${wl}-flat_namespace ${wl}-undefined ${wl}suppress'
+	  ;;
+	10.*)
+	  allow_undefined_flag='${wl}-undefined ${wl}dynamic_lookup'
+	  ;;
+	esac
+	;;
+      esac
+      archive_cmds_need_lc=no
+      hardcode_direct=no
+      hardcode_automatic=yes
+      hardcode_shlibpath_var=unsupported
+      whole_archive_flag_spec=''
+      link_all_deplibs=yes
+      if test "$GCC" = yes ; then
+	if test "${lt_cv_apple_cc_single_mod+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  lt_cv_apple_cc_single_mod=no
+	if test -z "${LT_MULTI_MODULE}"; then
+	  # By default we will add the -single_module flag. You can override
+	  # by either setting the environment variable LT_MULTI_MODULE
+	  # non-empty at configure time, or by adding -multi-module to the
+	  # link flags.
+	  echo "int foo(void){return 1;}" > conftest.c
+	  $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \
+	      -dynamiclib ${wl}-single_module conftest.c
+	  if test -f libconftest.dylib; then
+	      lt_cv_apple_cc_single_mod=yes
+	      rm libconftest.dylib
+	  fi
+	  rm conftest.$ac_ext
+	fi
+fi
+
+	output_verbose_link_cmd=echo
+	if test "X$lt_cv_apple_cc_single_mod" = Xyes ; then
+	  archive_cmds='$CC -dynamiclib $single_module $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring'
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $single_module -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	else
+	  archive_cmds='$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring'
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -dynamiclib $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags -install_name $rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	fi
+	module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags'
+	module_expsym_cmds='sed -e "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag  -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+      else
+	case $cc_basename in
+	xlc*)
+	  output_verbose_link_cmd=echo
+	  archive_cmds='$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}`$ECHO $rpath/$soname` $verstring'
+	  module_cmds='$CC $allow_undefined_flag -o $lib -bundle $libobjs $deplibs$compiler_flags'
+	  # Don't fix this by using the ld -exported_symbols_list flag, it doesn't exist in older darwin lds
+	  archive_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC -qmkshrobj $allow_undefined_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-install_name ${wl}$rpath/$soname $verstring~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	  module_expsym_cmds='sed "s,^,_," < $export_symbols > $output_objdir/${libname}-symbols.expsym~$CC $allow_undefined_flag  -o $lib -bundle $libobjs $deplibs$compiler_flags~nmedit -s $output_objdir/${libname}-symbols.expsym ${lib}'
+	  ;;
+	*)
+	  ld_shlibs=no
+	  ;;
+	esac
+      fi
+      ;;
+
+    dgux*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_shlibpath_var=no
+      ;;
+
+    freebsd1*)
+      ld_shlibs=no
+      ;;
+
+    # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor
+    # support.  Future versions do this automatically, but an explicit c++rt0.o
+    # does not break anything, and helps significantly (at the cost of a little
+    # extra space).
+    freebsd2.2*)
+      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o'
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    # Unfortunately, older versions of FreeBSD 2 do not have this feature.
+    freebsd2*)
+      archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_direct=yes
+      hardcode_minus_L=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    # FreeBSD 3 and greater uses gcc -shared to do shared libraries.
+    freebsd* | dragonfly*)
+      archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags'
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    hpux9*)
+      if test "$GCC" = yes; then
+	archive_cmds='$RM $output_objdir/$soname~$CC -shared -fPIC ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      else
+	archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib'
+      fi
+      hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+      hardcode_libdir_separator=:
+      hardcode_direct=yes
+
+      # hardcode_minus_L: Not really in the search PATH,
+      # but as the default location of the library.
+      hardcode_minus_L=yes
+      export_dynamic_flag_spec='${wl}-E'
+      ;;
+
+    hpux10*)
+      if test "$GCC" = yes -a "$with_gnu_ld" = no; then
+	archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      if test "$with_gnu_ld" = no; then
+	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+	hardcode_libdir_flag_spec_ld='+b $libdir'
+	hardcode_libdir_separator=:
+	hardcode_direct=yes
+	hardcode_direct_absolute=yes
+	export_dynamic_flag_spec='${wl}-E'
+	# hardcode_minus_L: Not really in the search PATH,
+	# but as the default location of the library.
+	hardcode_minus_L=yes
+      fi
+      ;;
+
+    hpux11*)
+      if test "$GCC" = yes -a "$with_gnu_ld" = no; then
+	case $host_cpu in
+	hppa*64*)
+	  archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  archive_cmds='$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  archive_cmds='$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	esac
+      else
+	case $host_cpu in
+	hppa*64*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	ia64*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	*)
+	  archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'
+	  ;;
+	esac
+      fi
+      if test "$with_gnu_ld" = no; then
+	hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
+	hardcode_libdir_separator=:
+
+	case $host_cpu in
+	hppa*64*|ia64*)
+	  hardcode_direct=no
+	  hardcode_shlibpath_var=no
+	  ;;
+	*)
+	  hardcode_direct=yes
+	  hardcode_direct_absolute=yes
+	  export_dynamic_flag_spec='${wl}-E'
+
+	  # hardcode_minus_L: Not really in the search PATH,
+	  # but as the default location of the library.
+	  hardcode_minus_L=yes
+	  ;;
+	esac
+      fi
+      ;;
+
+    irix5* | irix6* | nonstopux*)
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	# Try to use the -exported_symbol ld option, if it does not
+	# work, assume that -exports_file does not work either and
+	# implicitly export all symbols.
+        save_LDFLAGS="$LDFLAGS"
+        LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null"
+        cat >conftest.$ac_ext <<_ACEOF
+int foo(void) {}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib'
+
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+        LDFLAGS="$save_LDFLAGS"
+      else
+	archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+	archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
+      inherit_rpath=yes
+      link_all_deplibs=yes
+      ;;
+
+    netbsd*)
+      if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+	archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'  # a.out
+      else
+	archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags'      # ELF
+      fi
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    newsos6)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_direct=yes
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
+      hardcode_shlibpath_var=no
+      ;;
+
+    *nto* | *qnx*)
+      ;;
+
+    openbsd*)
+      hardcode_direct=yes
+      hardcode_shlibpath_var=no
+      hardcode_direct_absolute=yes
+      if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+	archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols'
+	hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+	export_dynamic_flag_spec='${wl}-E'
+      else
+        case $host_os in
+	openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*)
+	  archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_libdir_flag_spec='-R$libdir'
+	  ;;
+	*)
+	  archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags'
+	  hardcode_libdir_flag_spec='${wl}-rpath,$libdir'
+	  ;;
+        esac
+      fi
+      ;;
+
+    os2*)
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_minus_L=yes
+      allow_undefined_flag=unsupported
+      archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$ECHO DATA >> $output_objdir/$libname.def~$ECHO " SINGLE NONSHARED" >> $output_objdir/$libname.def~$ECHO EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def'
+      old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def'
+      ;;
+
+    osf3*)
+      if test "$GCC" = yes; then
+	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+      else
+	allow_undefined_flag=' -expect_unresolved \*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      hardcode_libdir_separator=:
       ;;
+
+    osf4* | osf5*)	# as osf3* with the addition of -msym flag
+      if test "$GCC" = yes; then
+	allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && $ECHO "X${wl}-set_version ${wl}$verstring" | $Xsed` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib'
+	hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
+      else
+	allow_undefined_flag=' -expect_unresolved \*'
+	archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib'
+	archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~
+	$CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "X-set_version $verstring" | $Xsed` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp'
+
+	# Both c and cxx compiler support -rpath directly
+	hardcode_libdir_flag_spec='-rpath $libdir'
+      fi
+      archive_cmds_need_lc='no'
+      hardcode_libdir_separator=:
+      ;;
+
+    solaris*)
+      no_undefined_flag=' -z defs'
+      if test "$GCC" = yes; then
+	wlarc='${wl}'
+	archive_cmds='$CC -shared ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -shared ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+      else
+	case `$CC -V 2>&1` in
+	*"Compilers 5.0"*)
+	  wlarc=''
+	  archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp'
+	  ;;
+	*)
+	  wlarc='${wl}'
+	  archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags'
+	  archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~
+	  $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp'
+	  ;;
+	esac
+      fi
+      hardcode_libdir_flag_spec='-R$libdir'
+      hardcode_shlibpath_var=no
+      case $host_os in
+      solaris2.[0-5] | solaris2.[0-5].*) ;;
+      *)
+	# The compiler driver will combine and reorder linker options,
+	# but understands `-z linker_flag'.  GCC discards it without `$wl',
+	# but is careful enough not to reorder.
+	# Supported since Solaris 2.6 (maybe 2.5.1?)
+	if test "$GCC" = yes; then
+	  whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract'
+	else
+	  whole_archive_flag_spec='-z allextract$convenience -z defaultextract'
+	fi
+	;;
+      esac
+      link_all_deplibs=yes
+      ;;
+
+    sunos4*)
+      if test "x$host_vendor" = xsequent; then
+	# Use $CC to link under sequent, because it throws in some extra .o
+	# files that make .init and .fini sections work.
+	archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags'
+      fi
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_direct=yes
+      hardcode_minus_L=yes
+      hardcode_shlibpath_var=no
+      ;;
+
+    sysv4)
+      case $host_vendor in
+	sni)
+	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_direct=yes # is this really true???
+	;;
+	siemens)
+	  ## LD is ld it makes a PLAMLIB
+	  ## CC just makes a GrossModule.
+	  archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags'
+	  reload_cmds='$CC -r -o $output$reload_objs'
+	  hardcode_direct=no
+        ;;
+	motorola)
+	  archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	  hardcode_direct=no #Motorola manual says yes, but my tests say they lie
+	;;
+      esac
+      runpath_var='LD_RUN_PATH'
+      hardcode_shlibpath_var=no
+      ;;
+
+    sysv4.3*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_shlibpath_var=no
+      export_dynamic_flag_spec='-Bexport'
+      ;;
+
+    sysv4*MP*)
+      if test -d /usr/nec; then
+	archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+	hardcode_shlibpath_var=no
+	runpath_var=LD_RUN_PATH
+	hardcode_runpath_var=yes
+	ld_shlibs=yes
+      fi
+      ;;
+
+    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*)
+      no_undefined_flag='${wl}-z,text'
+      archive_cmds_need_lc=no
+      hardcode_shlibpath_var=no
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    sysv5* | sco3.2v5* | sco5v6*)
+      # Note: We can NOT use -z defs as we might desire, because we do not
+      # link with -lc, and that would cause any symbols used from libc to
+      # always be unresolved, which means just about no library would
+      # ever link correctly.  If we're not using GNU ld we use -z text
+      # though, which does catch some bad symbols but isn't as heavy-handed
+      # as -z defs.
+      no_undefined_flag='${wl}-z,text'
+      allow_undefined_flag='${wl}-z,nodefs'
+      archive_cmds_need_lc=no
+      hardcode_shlibpath_var=no
+      hardcode_libdir_flag_spec='${wl}-R,$libdir'
+      hardcode_libdir_separator=':'
+      link_all_deplibs=yes
+      export_dynamic_flag_spec='${wl}-Bexport'
+      runpath_var='LD_RUN_PATH'
+
+      if test "$GCC" = yes; then
+	archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      else
+	archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+	archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags'
+      fi
+      ;;
+
+    uts4*)
+      archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
+      hardcode_libdir_flag_spec='-L$libdir'
+      hardcode_shlibpath_var=no
+      ;;
+
     *)
-      # `set' quotes correctly as required by POSIX, so do not add quotes.
-      sed -n \
-	"s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+      ld_shlibs=no
       ;;
-    esac;
-} |
-  sed '
-     t clear
-     : clear
-     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
-     t end
-     /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
-     : end' >>confcache
-if diff $cache_file confcache >/dev/null 2>&1; then :; else
-  if test -w $cache_file; then
-    test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
-    cat confcache >$cache_file
+    esac
+
+    if test x$host_vendor = xsni; then
+      case $host in
+      sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
+	export_dynamic_flag_spec='${wl}-Blargedynsym'
+	;;
+      esac
+    fi
+  fi
+
+echo "$as_me:$LINENO: result: $ld_shlibs" >&5
+echo "${ECHO_T}$ld_shlibs" >&6
+test "$ld_shlibs" = no && can_build_shared=no
+
+with_gnu_ld=$with_gnu_ld
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#
+# Do we need to explicitly link libc?
+#
+case "x$archive_cmds_need_lc" in
+x|xyes)
+  # Assume -lc should be added
+  archive_cmds_need_lc=yes
+
+  if test "$enable_shared" = yes && test "$GCC" = yes; then
+    case $archive_cmds in
+    *'~'*)
+      # FIXME: we may have to deal with multi-command sequences.
+      ;;
+    '$CC '*)
+      # Test whether the compiler implicitly links with -lc since on some
+      # systems, -lgcc has to come before -lc. If gcc already passes -lc
+      # to ld, don't add -lc before -lgcc.
+      echo "$as_me:$LINENO: checking whether -lc should be explicitly linked in" >&5
+echo $ECHO_N "checking whether -lc should be explicitly linked in... $ECHO_C" >&6
+      $RM conftest*
+      echo "$lt_simple_compile_test_code" > conftest.$ac_ext
+
+      if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } 2>conftest.err; then
+        soname=conftest
+        lib=conftest
+        libobjs=conftest.$ac_objext
+        deplibs=
+        wl=$lt_prog_compiler_wl
+	pic_flag=$lt_prog_compiler_pic
+        compiler_flags=-v
+        linker_flags=-v
+        verstring=
+        output_objdir=.
+        libname=conftest
+        lt_save_allow_undefined_flag=$allow_undefined_flag
+        allow_undefined_flag=
+        if { (eval echo "$as_me:$LINENO: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\"") >&5
+  (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }
+        then
+	  archive_cmds_need_lc=no
+        else
+	  archive_cmds_need_lc=yes
+        fi
+        allow_undefined_flag=$lt_save_allow_undefined_flag
+      else
+        cat conftest.err 1>&5
+      fi
+      $RM conftest*
+      echo "$as_me:$LINENO: result: $archive_cmds_need_lc" >&5
+echo "${ECHO_T}$archive_cmds_need_lc" >&6
+      ;;
+    esac
+  fi
+  ;;
+esac
+
+
+
+
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+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking dynamic linker characteristics" >&5
+echo $ECHO_N "checking dynamic linker characteristics... $ECHO_C" >&6
+withGCC=$GCC
+if test "$withGCC" = yes; then
+  case $host_os in
+    darwin*) lt_awk_arg="/^libraries:/,/LR/" ;;
+    *) lt_awk_arg="/^libraries:/" ;;
+  esac
+  lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e "s,=/,/,g"`
+  if $ECHO "$lt_search_path_spec" | $GREP ';' >/dev/null ; then
+    # if the path contains ";" then we assume it to be the separator
+    # otherwise default to the standard path separator (i.e. ":") - it is
+    # assumed that no part of a normal pathname contains ";" but that should
+    # okay in the real world where ";" in dirpaths is itself problematic.
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED -e 's/;/ /g'`
   else
-    echo "not updating unwritable cache $cache_file"
+    lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED  -e "s/$PATH_SEPARATOR/ /g"`
+  fi
+  # Ok, now we have the path, separated by spaces, we can step through it
+  # and add multilib dir if necessary.
+  lt_tmp_lt_search_path_spec=
+  lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null`
+  for lt_sys_path in $lt_search_path_spec; do
+    if test -d "$lt_sys_path/$lt_multi_os_dir"; then
+      lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir"
+    else
+      test -d "$lt_sys_path" && \
+	lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path"
+    fi
+  done
+  lt_search_path_spec=`$ECHO $lt_tmp_lt_search_path_spec | awk '
+BEGIN {RS=" "; FS="/|\n";} {
+  lt_foo="";
+  lt_count=0;
+  for (lt_i = NF; lt_i > 0; lt_i--) {
+    if ($lt_i != "" && $lt_i != ".") {
+      if ($lt_i == "..") {
+        lt_count++;
+      } else {
+        if (lt_count == 0) {
+          lt_foo="/" $lt_i lt_foo;
+        } else {
+          lt_count--;
+        }
+      }
+    }
+  }
+  if (lt_foo != "") { lt_freq[lt_foo]++; }
+  if (lt_freq[lt_foo] == 1) { print lt_foo; }
+}'`
+  sys_lib_search_path_spec=`$ECHO $lt_search_path_spec`
+else
+  sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib"
+fi
+library_names_spec=
+libname_spec='lib$name'
+soname_spec=
+shrext_cmds=".so"
+postinstall_cmds=
+postuninstall_cmds=
+finish_cmds=
+finish_eval=
+shlibpath_var=
+shlibpath_overrides_runpath=unknown
+version_type=none
+dynamic_linker="$host_os ld.so"
+sys_lib_dlsearch_path_spec="/lib /usr/lib"
+need_lib_prefix=unknown
+hardcode_into_libs=no
+
+# when you set need_version to no, make sure it does not cause -set_version
+# flags to be left without arguments
+need_version=unknown
+
+case $host_os in
+aix3*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a'
+  shlibpath_var=LIBPATH
+
+  # AIX 3 has no versioning support, so we append a major version to the name.
+  soname_spec='${libname}${release}${shared_ext}$major'
+  ;;
+
+aix4* | aix5*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  hardcode_into_libs=yes
+  if test "$host_cpu" = ia64; then
+    # AIX 5 supports IA64
+    library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}'
+    shlibpath_var=LD_LIBRARY_PATH
+  else
+    # With GCC up to 2.95.x, collect2 would create an import file
+    # for dependence libraries.  The import file would start with
+    # the line `#! .'.  This would cause the generated library to
+    # depend on `.', always an invalid library.  This was fixed in
+    # development snapshots of GCC prior to 3.0.
+    case $host_os in
+      aix4 | aix4.[01] | aix4.[01].*)
+      if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)'
+	   echo ' yes '
+	   echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then
+	:
+      else
+	can_build_shared=no
+      fi
+      ;;
+    esac
+    # AIX (on Power*) has no versioning support, so currently we can not hardcode correct
+    # soname into executable. Probably we can add versioning support to
+    # collect2, so additional links can be useful in future.
+    if test "$aix_use_runtimelinking" = yes; then
+      # If using run time linking (on AIX 4.2 or later) use lib<name>.so
+      # instead of lib<name>.a to let people know that these are not
+      # typical AIX shared libraries.
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    else
+      # We preserve .a as extension for shared libraries through AIX4.2
+      # and later when we are not doing run time linking.
+      library_names_spec='${libname}${release}.a $libname.a'
+      soname_spec='${libname}${release}${shared_ext}$major'
+    fi
+    shlibpath_var=LIBPATH
+  fi
+  ;;
+
+amigaos*)
+  if test "$host_cpu" = m68k; then
+    library_names_spec='$libname.ixlibrary $libname.a'
+    # Create ${libname}_ixlibrary.a entries in /sys/libs.
+    finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`$ECHO "X$lib" | $Xsed -e '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done'
+  else
+    dynamic_linker=no
+  fi
+  ;;
+
+beos*)
+  library_names_spec='${libname}${shared_ext}'
+  dynamic_linker="$host_os ld.so"
+  shlibpath_var=LIBRARY_PATH
+  ;;
+
+bsdi[45]*)
+  version_type=linux
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib"
+  sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib"
+  # the default ld.so.conf also contains /usr/contrib/lib and
+  # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow
+  # libtool to hard-code these into programs
+  ;;
+
+cygwin* | mingw* | pw32*)
+  version_type=windows
+  shrext_cmds=".dll"
+  need_version=no
+  need_lib_prefix=no
+
+  case $withGCC,$host_os in
+  yes,cygwin* | yes,mingw* | yes,pw32*)
+    library_names_spec='$libname.dll.a'
+    # DLL is installed to $(libdir)/../bin by postinstall_cmds
+    postinstall_cmds='base_file=`basename \${file}`~
+      dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~
+      dldir=$destdir/`dirname \$dlpath`~
+      test -d \$dldir || mkdir -p \$dldir~
+      $install_prog $dir/$dlname \$dldir/$dlname~
+      chmod a+x \$dldir/$dlname~
+      if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then
+        eval '\''$striplib \$dldir/$dlname'\'' || exit \$?;
+      fi'
+    postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~
+      dlpath=$dir/\$dldll~
+       $RM \$dlpath'
+    shlibpath_overrides_runpath=yes
+
+    case $host_os in
+    cygwin*)
+      # Cygwin DLLs use 'cyg' prefix rather than 'lib'
+      soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      sys_lib_search_path_spec="/usr/lib /lib/w32api /lib /usr/local/lib"
+      ;;
+    mingw*)
+      # MinGW DLLs use traditional 'lib' prefix
+      soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      sys_lib_search_path_spec=`$CC -print-search-dirs | $GREP "^libraries:" | $SED -e "s/^libraries://" -e "s,=/,/,g"`
+      if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then
+        # It is most probably a Windows format PATH printed by
+        # mingw gcc, but we are running on Cygwin. Gcc prints its search
+        # path with ; separators, and with drive letters. We can handle the
+        # drive letters (cygwin fileutils understands them), so leave them,
+        # especially as we might pass files found there to a mingw objdump,
+        # which wouldn't understand a cygwinified path. Ahh.
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'`
+      else
+        sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED  -e "s/$PATH_SEPARATOR/ /g"`
+      fi
+      ;;
+    pw32*)
+      # pw32 DLLs use 'pw' prefix rather than 'lib'
+      library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}'
+      ;;
+    esac
+    ;;
+
+  *)
+    library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib'
+    ;;
+  esac
+  dynamic_linker='Win32 ld.exe'
+  # FIXME: first we should search . and the directory the executable is in
+  shlibpath_var=PATH
+  ;;
+
+darwin* | rhapsody*)
+  dynamic_linker="$host_os dyld"
+  version_type=darwin
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext'
+  soname_spec='${libname}${release}${major}$shared_ext'
+  shlibpath_overrides_runpath=yes
+  shlibpath_var=DYLD_LIBRARY_PATH
+  shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`'
+
+  sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib"
+  sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib'
+  ;;
+
+dgux*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+freebsd1*)
+  dynamic_linker=no
+  ;;
+
+freebsd* | dragonfly*)
+  # DragonFly does not have aout.  When/if they implement a new
+  # versioning mechanism, adjust this.
+  if test -x /usr/bin/objformat; then
+    objformat=`/usr/bin/objformat`
+  else
+    case $host_os in
+    freebsd[123]*) objformat=aout ;;
+    *) objformat=elf ;;
+    esac
   fi
+  version_type=freebsd-$objformat
+  case $version_type in
+    freebsd-elf*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+      need_version=no
+      need_lib_prefix=no
+      ;;
+    freebsd-*)
+      library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix'
+      need_version=yes
+      ;;
+  esac
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_os in
+  freebsd2*)
+    shlibpath_overrides_runpath=yes
+    ;;
+  freebsd3.[01]* | freebsdelf3.[01]*)
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  freebsd3.[2-9]* | freebsdelf3.[2-9]* | \
+  freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1)
+    shlibpath_overrides_runpath=no
+    hardcode_into_libs=yes
+    ;;
+  *) # from 4.6 on, and DragonFly
+    shlibpath_overrides_runpath=yes
+    hardcode_into_libs=yes
+    ;;
+  esac
+  ;;
+
+gnu*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  hardcode_into_libs=yes
+  ;;
+
+hpux9* | hpux10* | hpux11*)
+  # Give a soname corresponding to the major version so that dld.sl refuses to
+  # link against other versions.
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  case $host_cpu in
+  ia64*)
+    shrext_cmds='.so'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.so"
+    shlibpath_var=LD_LIBRARY_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    if test "X$HPUX_IA64_MODE" = X32; then
+      sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib"
+    else
+      sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64"
+    fi
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  hppa*64*)
+    shrext_cmds='.sl'
+    hardcode_into_libs=yes
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH
+    shlibpath_overrides_runpath=yes # Unless +noenvvar is specified.
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64"
+    sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec
+    ;;
+  *)
+    shrext_cmds='.sl'
+    dynamic_linker="$host_os dld.sl"
+    shlibpath_var=SHLIB_PATH
+    shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    ;;
+  esac
+  # HP-UX runs *really* slowly unless shared libraries are mode 555.
+  postinstall_cmds='chmod 555 $lib'
+  ;;
+
+interix[3-9]*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+irix5* | irix6* | nonstopux*)
+  case $host_os in
+    nonstopux*) version_type=nonstopux ;;
+    *)
+	if test "$lt_cv_prog_gnu_ld" = yes; then
+		version_type=linux
+	else
+		version_type=irix
+	fi ;;
+  esac
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}'
+  case $host_os in
+  irix5* | nonstopux*)
+    libsuff= shlibsuff=
+    ;;
+  *)
+    case $LD in # libtool.m4 will add one of these switches to LD
+    *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ")
+      libsuff= shlibsuff= libmagic=32-bit;;
+    *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ")
+      libsuff=32 shlibsuff=N32 libmagic=N32;;
+    *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ")
+      libsuff=64 shlibsuff=64 libmagic=64-bit;;
+    *) libsuff= shlibsuff= libmagic=never-match;;
+    esac
+    ;;
+  esac
+  shlibpath_var=LD_LIBRARY${shlibsuff}_PATH
+  shlibpath_overrides_runpath=no
+  sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}"
+  sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}"
+  hardcode_into_libs=yes
+  ;;
+
+# No shared lib support for Linux oldld, aout, or coff.
+linux*oldld* | linux*aout* | linux*coff*)
+  dynamic_linker=no
+  ;;
+
+# This must be Linux ELF.
+linux* | k*bsd*-gnu)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  # Some binutils ld are patched to set DT_RUNPATH
+  save_LDFLAGS=$LDFLAGS
+  save_libdir=$libdir
+  eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \
+       LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\""
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  if  ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir"; then
+  shlibpath_overrides_runpath=yes
 fi
-rm -f confcache
 
-# Actually configure libtool.  ac_aux_dir is where install-sh is found.
-AR="$AR" LTCC="$CC" CC="$CC" CFLAGS="$CFLAGS" CPPFLAGS="$CPPFLAGS" \
-MAGIC_CMD="$MAGIC_CMD" LD="$LD" LDFLAGS="$LDFLAGS" LIBS="$LIBS" \
-LN_S="$LN_S" NM="$NM" RANLIB="$RANLIB" STRIP="$STRIP" \
-AS="$AS" DLLTOOL="$DLLTOOL" OBJDUMP="$OBJDUMP" \
-objext="$OBJEXT" exeext="$EXEEXT" reload_flag="$reload_flag" \
-deplibs_check_method="$deplibs_check_method" file_magic_cmd="$file_magic_cmd" \
-${CONFIG_SHELL-/bin/sh} $ac_aux_dir/ltconfig --no-reexec \
-$libtool_flags --no-verify --build="$build" $ac_aux_dir/ltmain.sh $host \
-|| { { echo "$as_me:$LINENO: error: libtool configure failed" >&5
-echo "$as_me: error: libtool configure failed" >&2;}
-   { (exit 1); exit 1; }; }
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
 
-# Reload cache, that may have been modified by ltconfig
-if test -r "$cache_file"; then
-  # Some versions of bash will fail to source /dev/null (special
-  # files actually), so we avoid doing that.
-  if test -f "$cache_file"; then
-    { echo "$as_me:$LINENO: loading cache $cache_file" >&5
-echo "$as_me: loading cache $cache_file" >&6;}
-    case $cache_file in
-      [\\/]* | ?:[\\/]* ) . $cache_file;;
-      *)                      . ./$cache_file;;
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+  LDFLAGS=$save_LDFLAGS
+  libdir=$save_libdir
+
+  # This implies no fast_install, which is unacceptable.
+  # Some rework will be needed to allow for fast_install
+  # before this can be enabled.
+  hardcode_into_libs=yes
+
+  # Append ld.so.conf contents to the search path
+  if test -f /etc/ld.so.conf; then
+    lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;s/[:,	]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;/^$/d' | tr '\n' ' '`
+    sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+  fi
+
+  # We used to test for /lib/ld.so.1 and disable shared libraries on
+  # powerpc, because MkLinux only supported shared libraries with the
+  # GNU dynamic linker.  Since this was broken with cross compilers,
+  # most powerpc-linux boxes support dynamic linking these days and
+  # people can always --disable-shared, the test was removed, and we
+  # assume the GNU/Linux dynamic linker is in use.
+  dynamic_linker='GNU/Linux ld.so'
+  ;;
+
+netbsd*)
+  version_type=sunos
+  need_lib_prefix=no
+  need_version=no
+  if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+    finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+    dynamic_linker='NetBSD (a.out) ld.so'
+  else
+    library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}'
+    soname_spec='${libname}${release}${shared_ext}$major'
+    dynamic_linker='NetBSD ld.elf_so'
+  fi
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  ;;
+
+newsos6)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  ;;
+
+*nto* | *qnx*)
+  version_type=qnx
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  dynamic_linker='ldqnx.so'
+  ;;
+
+openbsd*)
+  version_type=sunos
+  sys_lib_dlsearch_path_spec="/usr/lib"
+  need_lib_prefix=no
+  # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs.
+  case $host_os in
+    openbsd3.3 | openbsd3.3.*)	need_version=yes ;;
+    *)				need_version=no  ;;
+  esac
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then
+    case $host_os in
+      openbsd2.[89] | openbsd2.[89].*)
+	shlibpath_overrides_runpath=no
+	;;
+      *)
+	shlibpath_overrides_runpath=yes
+	;;
+      esac
+  else
+    shlibpath_overrides_runpath=yes
+  fi
+  ;;
+
+os2*)
+  libname_spec='$name'
+  shrext_cmds=".dll"
+  need_lib_prefix=no
+  library_names_spec='$libname${shared_ext} $libname.a'
+  dynamic_linker='OS/2 ld.exe'
+  shlibpath_var=LIBPATH
+  ;;
+
+osf3* | osf4* | osf5*)
+  version_type=osf
+  need_lib_prefix=no
+  need_version=no
+  soname_spec='${libname}${release}${shared_ext}$major'
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib"
+  sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec"
+  ;;
+
+rdos*)
+  dynamic_linker=no
+  ;;
+
+solaris*)
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  # ldd complains unless libraries are executable
+  postinstall_cmds='chmod +x $lib'
+  ;;
+
+sunos4*)
+  version_type=sunos
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix'
+  finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  if test "$with_gnu_ld" = yes; then
+    need_lib_prefix=no
+  fi
+  need_version=yes
+  ;;
+
+sysv4 | sysv4.3*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  case $host_vendor in
+    sni)
+      shlibpath_overrides_runpath=no
+      need_lib_prefix=no
+      runpath_var=LD_RUN_PATH
+      ;;
+    siemens)
+      need_lib_prefix=no
+      ;;
+    motorola)
+      need_lib_prefix=no
+      need_version=no
+      shlibpath_overrides_runpath=no
+      sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib'
+      ;;
+  esac
+  ;;
+
+sysv4*MP*)
+  if test -d /usr/nec ;then
+    version_type=linux
+    library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}'
+    soname_spec='$libname${shared_ext}.$major'
+    shlibpath_var=LD_LIBRARY_PATH
+  fi
+  ;;
+
+sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)
+  version_type=freebsd-elf
+  need_lib_prefix=no
+  need_version=no
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=yes
+  hardcode_into_libs=yes
+  if test "$with_gnu_ld" = yes; then
+    sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib'
+  else
+    sys_lib_search_path_spec='/usr/ccs/lib /usr/lib'
+    case $host_os in
+      sco3.2v5*)
+        sys_lib_search_path_spec="$sys_lib_search_path_spec /lib"
+	;;
     esac
   fi
+  sys_lib_dlsearch_path_spec='/usr/lib'
+  ;;
+
+tpf*)
+  # TPF is a cross-target only.  Preferred cross-host = GNU/Linux.
+  version_type=linux
+  need_lib_prefix=no
+  need_version=no
+  library_name_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  shlibpath_var=LD_LIBRARY_PATH
+  shlibpath_overrides_runpath=no
+  hardcode_into_libs=yes
+  ;;
+
+uts4*)
+  version_type=linux
+  library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}'
+  soname_spec='${libname}${release}${shared_ext}$major'
+  shlibpath_var=LD_LIBRARY_PATH
+  ;;
+
+*)
+  dynamic_linker=no
+  ;;
+esac
+echo "$as_me:$LINENO: result: $dynamic_linker" >&5
+echo "${ECHO_T}$dynamic_linker" >&6
+test "$dynamic_linker" = no && can_build_shared=no
+
+variables_saved_for_relink="PATH $shlibpath_var $runpath_var"
+if test "$GCC" = yes; then
+  variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH"
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  echo "$as_me:$LINENO: checking how to hardcode library paths into programs" >&5
+echo $ECHO_N "checking how to hardcode library paths into programs... $ECHO_C" >&6
+hardcode_action=
+if test -n "$hardcode_libdir_flag_spec" ||
+   test -n "$runpath_var" ||
+   test "X$hardcode_automatic" = "Xyes" ; then
+
+  # We can hardcode non-existent directories.
+  if test "$hardcode_direct" != no &&
+     # If the only mechanism to avoid hardcoding is shlibpath_var, we
+     # have to relink, otherwise we might link with an installed library
+     # when we should be linking with a yet-to-be-installed one
+     ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no &&
+     test "$hardcode_minus_L" != no; then
+    # Linking always hardcodes the temporary library directory.
+    hardcode_action=relink
+  else
+    # We can link without hardcoding, and we can hardcode nonexisting dirs.
+    hardcode_action=immediate
+  fi
 else
-  { echo "$as_me:$LINENO: creating cache $cache_file" >&5
-echo "$as_me: creating cache $cache_file" >&6;}
-  >$cache_file
+  # We cannot hardcode anything, or else we can only hardcode existing
+  # directories.
+  hardcode_action=unsupported
 fi
+echo "$as_me:$LINENO: result: $hardcode_action" >&5
+echo "${ECHO_T}$hardcode_action" >&6
 
+if test "$hardcode_action" = relink ||
+   test "$inherit_rpath" = yes; then
+  # Fast installation is not supported
+  enable_fast_install=no
+elif test "$shlibpath_overrides_runpath" = yes ||
+     test "$enable_shared" = no; then
+  # Fast installation is not necessary
+  enable_fast_install=needless
+fi
 
-# This can be used to rebuild libtool when needed
-LIBTOOL_DEPS="$ac_aux_dir/ltconfig $ac_aux_dir/ltmain.sh $ac_aux_dir/ltcf-c.sh"
 
-# Always use our own libtool.
-LIBTOOL='$(SHELL) $(top_builddir)/libtool'
 
-# Redirect the config.log output again, so that the ltconfig log is not
-# clobbered by the next message.
-exec 5>>./config.log
 
 
 
+  if test "x$enable_dlopen" != xyes; then
+  enable_dlopen=unknown
+  enable_dlopen_self=unknown
+  enable_dlopen_self_static=unknown
+else
+  lt_cv_dlopen=no
+  lt_cv_dlopen_libs=
+
+  case $host_os in
+  beos*)
+    lt_cv_dlopen="load_add_on"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+    ;;
+
+  mingw* | pw32*)
+    lt_cv_dlopen="LoadLibrary"
+    lt_cv_dlopen_libs=
+    ;;
+
+  cygwin*)
+    lt_cv_dlopen="dlopen"
+    lt_cv_dlopen_libs=
+    ;;
+
+  darwin*)
+  # if libdl is installed we need to link against it
+    echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5
+echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6
+if test "${ac_cv_lib_dl_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldl  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dl_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dl_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6
+if test $ac_cv_lib_dl_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
+else
+
+    lt_cv_dlopen="dyld"
+    lt_cv_dlopen_libs=
+    lt_cv_dlopen_self=yes
+
+fi
+
+    ;;
+
+  *)
+    echo "$as_me:$LINENO: checking for shl_load" >&5
+echo $ECHO_N "checking for shl_load... $ECHO_C" >&6
+if test "${ac_cv_func_shl_load+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+/* Define shl_load to an innocuous variant, in case <limits.h> declares shl_load.
+   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
+#define shl_load innocuous_shl_load
+
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char shl_load (); below.
+    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+    <limits.h> exists even on freestanding compilers.  */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef shl_load
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char shl_load ();
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_shl_load) || defined (__stub___shl_load)
+choke me
+#else
+char (*f) () = shl_load;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != shl_load;
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_func_shl_load=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_func_shl_load=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_shl_load" >&5
+echo "${ECHO_T}$ac_cv_func_shl_load" >&6
+if test $ac_cv_func_shl_load = yes; then
+  lt_cv_dlopen="shl_load"
+else
+  echo "$as_me:$LINENO: checking for shl_load in -ldld" >&5
+echo $ECHO_N "checking for shl_load in -ldld... $ECHO_C" >&6
+if test "${ac_cv_lib_dld_shl_load+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char shl_load ();
+int
+main ()
+{
+shl_load ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dld_shl_load=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dld_shl_load=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dld_shl_load" >&5
+echo "${ECHO_T}$ac_cv_lib_dld_shl_load" >&6
+if test $ac_cv_lib_dld_shl_load = yes; then
+  lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-dld"
+else
+  echo "$as_me:$LINENO: checking for dlopen" >&5
+echo $ECHO_N "checking for dlopen... $ECHO_C" >&6
+if test "${ac_cv_func_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+/* Define dlopen to an innocuous variant, in case <limits.h> declares dlopen.
+   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
+#define dlopen innocuous_dlopen
+
+/* System header to define __stub macros and hopefully few prototypes,
+    which can conflict with char dlopen (); below.
+    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+    <limits.h> exists even on freestanding compilers.  */
 
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef dlopen
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+/* The GNU C library defines this for functions which it implements
+    to always fail with ENOSYS.  Some functions are actually named
+    something starting with __ and the normal name is an alias.  */
+#if defined (__stub_dlopen) || defined (__stub___dlopen)
+choke me
+#else
+char (*f) () = dlopen;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != dlopen;
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_func_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_func_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_dlopen" >&5
+echo "${ECHO_T}$ac_cv_func_dlopen" >&6
+if test $ac_cv_func_dlopen = yes; then
+  lt_cv_dlopen="dlopen"
+else
+  echo "$as_me:$LINENO: checking for dlopen in -ldl" >&5
+echo $ECHO_N "checking for dlopen in -ldl... $ECHO_C" >&6
+if test "${ac_cv_lib_dl_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldl  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dl_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dl_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dl_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_dl_dlopen" >&6
+if test $ac_cv_lib_dl_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"
+else
+  echo "$as_me:$LINENO: checking for dlopen in -lsvld" >&5
+echo $ECHO_N "checking for dlopen in -lsvld... $ECHO_C" >&6
+if test "${ac_cv_lib_svld_dlopen+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsvld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dlopen ();
+int
+main ()
+{
+dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_svld_dlopen=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_svld_dlopen=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_svld_dlopen" >&5
+echo "${ECHO_T}$ac_cv_lib_svld_dlopen" >&6
+if test $ac_cv_lib_svld_dlopen = yes; then
+  lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld"
+else
+  echo "$as_me:$LINENO: checking for dld_link in -ldld" >&5
+echo $ECHO_N "checking for dld_link in -ldld... $ECHO_C" >&6
+if test "${ac_cv_lib_dld_dld_link+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-ldld  $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char dld_link ();
+int
+main ()
+{
+dld_link ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_lib_dld_dld_link=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_dld_dld_link=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_dld_dld_link" >&5
+echo "${ECHO_T}$ac_cv_lib_dld_dld_link" >&6
+if test $ac_cv_lib_dld_dld_link = yes; then
+  lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-dld"
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+
+fi
+
+    ;;
+  esac
+
+  if test "x$lt_cv_dlopen" != xno; then
+    enable_dlopen=yes
+  else
+    enable_dlopen=no
+  fi
+
+  case $lt_cv_dlopen in
+  dlopen)
+    save_CPPFLAGS="$CPPFLAGS"
+    test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H"
+
+    save_LDFLAGS="$LDFLAGS"
+    wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\"
+
+    save_LIBS="$LIBS"
+    LIBS="$lt_cv_dlopen_libs $LIBS"
+
+    echo "$as_me:$LINENO: checking whether a program can dlopen itself" >&5
+echo $ECHO_N "checking whether a program can dlopen itself... $ECHO_C" >&6
+if test "${lt_cv_dlopen_self+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  	  if test "$cross_compiling" = yes; then :
+  lt_cv_dlopen_self=cross
+else
+  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+  lt_status=$lt_dlunknown
+  cat > conftest.$ac_ext <<_LT_EOF
+#line 9201 "configure"
+#include "confdefs.h"
+
+#if HAVE_DLFCN_H
+#include <dlfcn.h>
+#endif
+
+#include <stdio.h>
+
+#ifdef RTLD_GLOBAL
+#  define LT_DLGLOBAL		RTLD_GLOBAL
+#else
+#  ifdef DL_GLOBAL
+#    define LT_DLGLOBAL		DL_GLOBAL
+#  else
+#    define LT_DLGLOBAL		0
+#  endif
+#endif
+
+/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
+   find out it does not work in some platform. */
+#ifndef LT_DLLAZY_OR_NOW
+#  ifdef RTLD_LAZY
+#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
+#  else
+#    ifdef DL_LAZY
+#      define LT_DLLAZY_OR_NOW		DL_LAZY
+#    else
+#      ifdef RTLD_NOW
+#        define LT_DLLAZY_OR_NOW	RTLD_NOW
+#      else
+#        ifdef DL_NOW
+#          define LT_DLLAZY_OR_NOW	DL_NOW
+#        else
+#          define LT_DLLAZY_OR_NOW	0
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+#ifdef __cplusplus
+extern "C" void exit (int);
+#endif
+
+void fnord() { int i=42;}
+int main ()
+{
+  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
+  int status = $lt_dlunknown;
+
+  if (self)
+    {
+      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
+      else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore;
+      /* dlclose (self); */
+    }
+  else
+    puts (dlerror ());
+
+    exit (status);
+}
+_LT_EOF
+  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then
+    (./conftest; exit; ) >&5 2>/dev/null
+    lt_status=$?
+    case x$lt_status in
+      x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;;
+      x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;;
+      x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;;
+    esac
+  else :
+    # compilation failed
+    lt_cv_dlopen_self=no
+  fi
+fi
+rm -fr conftest*
+
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_dlopen_self" >&5
+echo "${ECHO_T}$lt_cv_dlopen_self" >&6
+
+    if test "x$lt_cv_dlopen_self" = xyes; then
+      wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\"
+      echo "$as_me:$LINENO: checking whether a statically linked program can dlopen itself" >&5
+echo $ECHO_N "checking whether a statically linked program can dlopen itself... $ECHO_C" >&6
+if test "${lt_cv_dlopen_self_static+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  	  if test "$cross_compiling" = yes; then :
+  lt_cv_dlopen_self_static=cross
+else
+  lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
+  lt_status=$lt_dlunknown
+  cat > conftest.$ac_ext <<_LT_EOF
+#line 9301 "configure"
+#include "confdefs.h"
+
+#if HAVE_DLFCN_H
+#include <dlfcn.h>
+#endif
+
+#include <stdio.h>
+
+#ifdef RTLD_GLOBAL
+#  define LT_DLGLOBAL		RTLD_GLOBAL
+#else
+#  ifdef DL_GLOBAL
+#    define LT_DLGLOBAL		DL_GLOBAL
+#  else
+#    define LT_DLGLOBAL		0
+#  endif
+#endif
+
+/* We may have to define LT_DLLAZY_OR_NOW in the command line if we
+   find out it does not work in some platform. */
+#ifndef LT_DLLAZY_OR_NOW
+#  ifdef RTLD_LAZY
+#    define LT_DLLAZY_OR_NOW		RTLD_LAZY
+#  else
+#    ifdef DL_LAZY
+#      define LT_DLLAZY_OR_NOW		DL_LAZY
+#    else
+#      ifdef RTLD_NOW
+#        define LT_DLLAZY_OR_NOW	RTLD_NOW
+#      else
+#        ifdef DL_NOW
+#          define LT_DLLAZY_OR_NOW	DL_NOW
+#        else
+#          define LT_DLLAZY_OR_NOW	0
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+#ifdef __cplusplus
+extern "C" void exit (int);
+#endif
+
+void fnord() { int i=42;}
+int main ()
+{
+  void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW);
+  int status = $lt_dlunknown;
+
+  if (self)
+    {
+      if (dlsym (self,"fnord"))       status = $lt_dlno_uscore;
+      else if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore;
+      /* dlclose (self); */
+    }
+  else
+    puts (dlerror ());
+
+    exit (status);
+}
+_LT_EOF
+  if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && test -s conftest${ac_exeext} 2>/dev/null; then
+    (./conftest; exit; ) >&5 2>/dev/null
+    lt_status=$?
+    case x$lt_status in
+      x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;;
+      x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;;
+      x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;;
+    esac
+  else :
+    # compilation failed
+    lt_cv_dlopen_self_static=no
+  fi
+fi
+rm -fr conftest*
+
+
+fi
+echo "$as_me:$LINENO: result: $lt_cv_dlopen_self_static" >&5
+echo "${ECHO_T}$lt_cv_dlopen_self_static" >&6
+    fi
+
+    CPPFLAGS="$save_CPPFLAGS"
+    LDFLAGS="$save_LDFLAGS"
+    LIBS="$save_LIBS"
+    ;;
+  esac
+
+  case $lt_cv_dlopen_self in
+  yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;;
+  *) enable_dlopen_self=unknown ;;
+  esac
+
+  case $lt_cv_dlopen_self_static in
+  yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;;
+  *) enable_dlopen_self_static=unknown ;;
+  esac
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+striplib=
+old_striplib=
+echo "$as_me:$LINENO: checking whether stripping libraries is possible" >&5
+echo $ECHO_N "checking whether stripping libraries is possible... $ECHO_C" >&6
+if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then
+  test -z "$old_striplib" && old_striplib="$STRIP --strip-debug"
+  test -z "$striplib" && striplib="$STRIP --strip-unneeded"
+  echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+else
+# FIXME - insert some real tests, host_os isn't really good enough
+  case $host_os in
+  darwin*)
+    if test -n "$STRIP" ; then
+      striplib="$STRIP -x"
+      old_striplib="$STRIP -S"
+      echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+    else
+      echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+    fi
+    ;;
+  *)
+    echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+    ;;
+  esac
+fi
+
+
+
+
+
+
+
+
+
+
+
+
+  # Report which library types will actually be built
+  echo "$as_me:$LINENO: checking if libtool supports shared libraries" >&5
+echo $ECHO_N "checking if libtool supports shared libraries... $ECHO_C" >&6
+  echo "$as_me:$LINENO: result: $can_build_shared" >&5
+echo "${ECHO_T}$can_build_shared" >&6
+
+  echo "$as_me:$LINENO: checking whether to build shared libraries" >&5
+echo $ECHO_N "checking whether to build shared libraries... $ECHO_C" >&6
+  test "$can_build_shared" = "no" && enable_shared=no
+
+  # On AIX, shared libraries and static libraries use the same namespace, and
+  # are all built from PIC.
+  case $host_os in
+  aix3*)
+    test "$enable_shared" = yes && enable_static=no
+    if test -n "$RANLIB"; then
+      archive_cmds="$archive_cmds~\$RANLIB \$lib"
+      postinstall_cmds='$RANLIB $lib'
+    fi
+    ;;
+
+  aix4* | aix5*)
+    if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then
+      test "$enable_shared" = yes && enable_static=no
+    fi
+    ;;
+  esac
+  echo "$as_me:$LINENO: result: $enable_shared" >&5
+echo "${ECHO_T}$enable_shared" >&6
+
+  echo "$as_me:$LINENO: checking whether to build static libraries" >&5
+echo $ECHO_N "checking whether to build static libraries... $ECHO_C" >&6
+  # Make sure either enable_shared or enable_static is yes.
+  test "$enable_shared" = yes || enable_static=yes
+  echo "$as_me:$LINENO: result: $enable_static" >&5
+echo "${ECHO_T}$enable_static" >&6
+
+
+
+
+fi
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+CC="$lt_save_CC"
+
+
+
+
+
+
+
+
+
+
+
+
+
+                  ac_config_commands="$ac_config_commands libtool"
+
+
+
+
+# Only expand once:
 
 
 
@@ -4165,7 +9541,8 @@ echo "$as_me: error: enable-targets option must specify target names or 'all'" >
   no)	    enable_targets= ;;
   *)	    enable_targets=$enableval ;;
 esac
-fi; # Check whether --enable-commonbfdlib or --disable-commonbfdlib was given.
+fi;
+# Check whether --enable-commonbfdlib or --disable-commonbfdlib was given.
 if test "${enable_commonbfdlib+set}" = set; then
   enableval="$enable_commonbfdlib"
   case "${enableval}" in
@@ -4176,6 +9553,25 @@ echo "$as_me: error: bad value ${enableval} for BFD commonbfdlib option" >&2;}
    { (exit 1); exit 1; }; } ;;
 esac
 fi;
+ac_checking=yes
+if grep '^RELEASE=y' ${srcdir}/../bfd/Makefile.am >/dev/null 2>/dev/null ; then
+  ac_checking=
+fi
+# Check whether --enable-checking or --disable-checking was given.
+if test "${enable_checking+set}" = set; then
+  enableval="$enable_checking"
+  case "${enableval}" in
+  no|none)  ac_checking= ;;
+  *)	    ac_checking=yes ;;
+esac
+fi; if test x$ac_checking != x ; then
+
+cat >>confdefs.h <<\_ACEOF
+#define ENABLE_CHECKING 1
+_ACEOF
+
+fi
+
 using_cgen=no
 
 
@@ -4733,7 +10129,7 @@ _ACEOF
 
     # Do we need the opcodes library?
     case ${cpu_type} in
-      vax | i386 | tic30)
+      vax | tic30)
 	;;
 
       *)
@@ -4779,6 +10175,10 @@ _ACEOF
 	esac
 	;;
 
+      mep)
+	using_cgen=yes
+	;;
+
       mips)
 	echo ${extra_objects} | grep -s "itbl-parse.o"
 	if test $? -ne 0 ; then
@@ -4896,6 +10296,19 @@ if test ${all_targets} = "yes"; then
       ;;
     esac
   ;;
+  x86_64)
+    case ${obj_format} in
+    aout)
+      emulations="$emulations i386coff i386elf"
+      ;;
+    coff)
+      emulations="$emulations i386aout i386elf"
+    ;;
+    elf)
+      emulations="$emulations i386aout i386coff"
+      ;;
+    esac
+  ;;
   esac
 fi
 
@@ -4903,8 +10316,7 @@ fi
 # IEEE FP.  On those that don't support FP at all, usually IEEE
 # is emulated.
 case ${target_cpu} in
-  vax | tahoe )	atof=${target_cpu} ;;
-  pdp11)	atof=vax ;;
+  vax | pdp11 )	atof=vax ;;
   *)		atof=ieee ;;
 esac
 
@@ -4960,6 +10372,11 @@ cat >>confdefs.h <<\_ACEOF
 #define M88KCOFF 1
 _ACEOF
  ;;
+      x86_64)
+cat >>confdefs.h <<\_ACEOF
+#define I386COFF 1
+_ACEOF
+ ;;
     esac
     ;;
 esac
@@ -5069,11 +10486,6 @@ cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_GENERIC 1
 _ACEOF
  ;;
-      ieee)
-cat >>confdefs.h <<\_ACEOF
-#define OBJ_MAYBE_IEEE 1
-_ACEOF
-    ;;
       som)
 cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_SOM 1
@@ -5134,14 +10546,6 @@ yes)
   ;;
 esac
 
-BFDLIB=../bfd/libbfd.la
-BFDVER_H=../bfd/bfdver.h
-ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-
-
-
-
-
 
 
 
@@ -6220,2479 +11624,138 @@ if test "$LEX" = :; then
 fi
 
 ALL_LINGUAS="fr tr es rw"
-if test -n "$ac_tool_prefix"; then
-  # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
-set dummy ${ac_tool_prefix}ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$RANLIB"; then
-  ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-fi
-fi
-RANLIB=$ac_cv_prog_RANLIB
-if test -n "$RANLIB"; then
-  echo "$as_me:$LINENO: result: $RANLIB" >&5
-echo "${ECHO_T}$RANLIB" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-fi
-if test -z "$ac_cv_prog_RANLIB"; then
-  ac_ct_RANLIB=$RANLIB
-  # Extract the first word of "ranlib", so it can be a program name with args.
-set dummy ranlib; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test -n "$ac_ct_RANLIB"; then
-  ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
-else
-as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_prog_ac_ct_RANLIB="ranlib"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
-  fi
-done
-done
-
-  test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
-fi
-fi
-ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
-if test -n "$ac_ct_RANLIB"; then
-  echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
-echo "${ECHO_T}$ac_ct_RANLIB" >&6
-else
+# If we haven't got the data from the intl directory,
+# assume NLS is disabled.
+USE_NLS=no
+LIBINTL=
+LIBINTL_DEP=
+INCINTL=
+XGETTEXT=
+GMSGFMT=
+POSUB=
+
+if test -f  ../intl/config.intl; then
+  .  ../intl/config.intl
+fi
+echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
+if test x"$USE_NLS" != xyes; then
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
-fi
-
-  RANLIB=$ac_ct_RANLIB
-else
-  RANLIB="$ac_cv_prog_RANLIB"
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
-echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
-# On Suns, sometimes $CPP names a directory.
-if test -n "$CPP" && test -d "$CPP"; then
-  CPP=
-fi
-if test -z "$CPP"; then
-  if test "${ac_cv_prog_CPP+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-      # Double quotes because CPP needs to be expanded
-    for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
-    do
-      ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  break
-fi
-
-    done
-    ac_cv_prog_CPP=$CPP
-
-fi
-  CPP=$ac_cv_prog_CPP
-else
-  ac_cv_prog_CPP=$CPP
-fi
-echo "$as_me:$LINENO: result: $CPP" >&5
-echo "${ECHO_T}$CPP" >&6
-ac_preproc_ok=false
-for ac_c_preproc_warn_flag in '' yes
-do
-  # Use a header file that comes with gcc, so configuring glibc
-  # with a fresh cross-compiler works.
-  # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-  # <limits.h> exists even on freestanding compilers.
-  # On the NeXT, cc -E runs the code through the compiler's parser,
-  # not just through cpp. "Syntax error" is here to catch this case.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-		     Syntax error
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  :
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Broken: fails on valid input.
-continue
-fi
-rm -f conftest.err conftest.$ac_ext
-
-  # OK, works on sane cases.  Now check whether non-existent headers
-  # can be detected and how.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ac_nonexistent.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
-  fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  # Broken: success on invalid input.
-continue
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  # Passes both tests.
-ac_preproc_ok=:
-break
-fi
-rm -f conftest.err conftest.$ac_ext
-
-done
-# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
-rm -f conftest.err conftest.$ac_ext
-if $ac_preproc_ok; then
-  :
-else
-  { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&5
-echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." >&2;}
-   { (exit 1); exit 1; }; }
-fi
-
-ac_ext=c
-ac_cpp='$CPP $CPPFLAGS'
-ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
-ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
-ac_compiler_gnu=$ac_cv_c_compiler_gnu
-
-
-echo "$as_me:$LINENO: checking for egrep" >&5
-echo $ECHO_N "checking for egrep... $ECHO_C" >&6
-if test "${ac_cv_prog_egrep+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if echo a | (grep -E '(a|b)') >/dev/null 2>&1
-    then ac_cv_prog_egrep='grep -E'
-    else ac_cv_prog_egrep='egrep'
-    fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
-echo "${ECHO_T}$ac_cv_prog_egrep" >&6
- EGREP=$ac_cv_prog_egrep
-
-
-echo "$as_me:$LINENO: checking for ANSI C header files" >&5
-echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
-if test "${ac_cv_header_stdc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-#include <stdarg.h>
-#include <string.h>
-#include <float.h>
-
-int
-main ()
-{
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_header_stdc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_header_stdc=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-
-if test $ac_cv_header_stdc = yes; then
-  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <string.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "memchr" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <stdlib.h>
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "free" >/dev/null 2>&1; then
-  :
-else
-  ac_cv_header_stdc=no
-fi
-rm -f conftest*
-
-fi
-
-if test $ac_cv_header_stdc = yes; then
-  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
-  if test "$cross_compiling" = yes; then
-  :
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <ctype.h>
-#if ((' ' & 0x0FF) == 0x020)
-# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
-# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
-#else
-# define ISLOWER(c) \
-		   (('a' <= (c) && (c) <= 'i') \
-		     || ('j' <= (c) && (c) <= 'r') \
-		     || ('s' <= (c) && (c) <= 'z'))
-# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
-#endif
-
-#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
-int
-main ()
-{
-  int i;
-  for (i = 0; i < 256; i++)
-    if (XOR (islower (i), ISLOWER (i))
-	|| toupper (i) != TOUPPER (i))
-      exit(2);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  :
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_header_stdc=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
-echo "${ECHO_T}$ac_cv_header_stdc" >&6
-if test $ac_cv_header_stdc = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define STDC_HEADERS 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5
-echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6
-if test "${ac_cv_c_const+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-/* FIXME: Include the comments suggested by Paul. */
-#ifndef __cplusplus
-  /* Ultrix mips cc rejects this.  */
-  typedef int charset[2];
-  const charset x;
-  /* SunOS 4.1.1 cc rejects this.  */
-  char const *const *ccp;
-  char **p;
-  /* NEC SVR4.0.2 mips cc rejects this.  */
-  struct point {int x, y;};
-  static struct point const zero = {0,0};
-  /* AIX XL C 1.02.0.0 rejects this.
-     It does not let you subtract one const X* pointer from another in
-     an arm of an if-expression whose if-part is not a constant
-     expression */
-  const char *g = "string";
-  ccp = &g + (g ? g-g : 0);
-  /* HPUX 7.0 cc rejects these. */
-  ++ccp;
-  p = (char**) ccp;
-  ccp = (char const *const *) p;
-  { /* SCO 3.2v4 cc rejects this.  */
-    char *t;
-    char const *s = 0 ? (char *) 0 : (char const *) 0;
-
-    *t++ = 0;
-  }
-  { /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */
-    int x[] = {25, 17};
-    const int *foo = &x[0];
-    ++foo;
-  }
-  { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
-    typedef const int *iptr;
-    iptr p = 0;
-    ++p;
-  }
-  { /* AIX XL C 1.02.0.0 rejects this saying
-       "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
-    struct s { int j; const int *ap[3]; };
-    struct s *b; b->j = 5;
-  }
-  { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
-    const int foo = 10;
-  }
-#endif
-
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_const=yes
 else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_c_const=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5
-echo "${ECHO_T}$ac_cv_c_const" >&6
-if test $ac_cv_c_const = no; then
+  echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
 
 cat >>confdefs.h <<\_ACEOF
-#define const
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for inline" >&5
-echo $ECHO_N "checking for inline... $ECHO_C" >&6
-if test "${ac_cv_c_inline+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_c_inline=no
-for ac_kw in inline __inline__ __inline; do
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifndef __cplusplus
-typedef int foo_t;
-static $ac_kw foo_t static_foo () {return 0; }
-$ac_kw foo_t foo () {return 0; }
-#endif
-
+#define ENABLE_NLS 1
 _ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_inline=$ac_kw; break
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-done
 
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5
-echo "${ECHO_T}$ac_cv_c_inline" >&6
-
-
-case $ac_cv_c_inline in
-  inline | yes) ;;
-  *)
-    case $ac_cv_c_inline in
-      no) ac_val=;;
-      *) ac_val=$ac_cv_c_inline;;
+  echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
+echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
+  # Look for .po and .gmo files in the source directory.
+  CATALOGS=
+  XLINGUAS=
+  for cat in $srcdir/po/*.gmo $srcdir/po/*.po; do
+    # If there aren't any .gmo files the shell will give us the
+    # literal string "../path/to/srcdir/po/*.gmo" which has to be
+    # weeded out.
+    case "$cat" in *\**)
+      continue;;
     esac
-    cat >>confdefs.h <<_ACEOF
-#ifndef __cplusplus
-#define inline $ac_val
-#endif
-_ACEOF
-    ;;
-esac
-
-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-
-
-
-
-
-
-
-
-
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-		  inttypes.h stdint.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_Header=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_Header=no"
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-echo "$as_me:$LINENO: checking for off_t" >&5
-echo $ECHO_N "checking for off_t... $ECHO_C" >&6
-if test "${ac_cv_type_off_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((off_t *) 0)
-  return 0;
-if (sizeof (off_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_off_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_off_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5
-echo "${ECHO_T}$ac_cv_type_off_t" >&6
-if test $ac_cv_type_off_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define off_t long
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for size_t" >&5
-echo $ECHO_N "checking for size_t... $ECHO_C" >&6
-if test "${ac_cv_type_size_t+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-int
-main ()
-{
-if ((size_t *) 0)
-  return 0;
-if (sizeof (size_t))
-  return 0;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_type_size_t=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_type_size_t=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5
-echo "${ECHO_T}$ac_cv_type_size_t" >&6
-if test $ac_cv_type_size_t = yes; then
-  :
-else
-
-cat >>confdefs.h <<_ACEOF
-#define size_t unsigned
-_ACEOF
-
-fi
-
-# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
-# for constant arguments.  Useless!
-echo "$as_me:$LINENO: checking for working alloca.h" >&5
-echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6
-if test "${ac_cv_working_alloca_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <alloca.h>
-int
-main ()
-{
-char *p = (char *) alloca (2 * sizeof (int));
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_working_alloca_h=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_working_alloca_h=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5
-echo "${ECHO_T}$ac_cv_working_alloca_h" >&6
-if test $ac_cv_working_alloca_h = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA_H 1
-_ACEOF
-
-fi
-
-echo "$as_me:$LINENO: checking for alloca" >&5
-echo $ECHO_N "checking for alloca... $ECHO_C" >&6
-if test "${ac_cv_func_alloca_works+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#ifdef __GNUC__
-# define alloca __builtin_alloca
-#else
-# ifdef _MSC_VER
-#  include <malloc.h>
-#  define alloca _alloca
-# else
-#  if HAVE_ALLOCA_H
-#   include <alloca.h>
-#  else
-#   ifdef _AIX
- #pragma alloca
-#   else
-#    ifndef alloca /* predefined by HP cc +Olibcalls */
-char *alloca ();
-#    endif
-#   endif
-#  endif
-# endif
-#endif
-
-int
-main ()
-{
-char *p = (char *) alloca (1);
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_alloca_works=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_func_alloca_works=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5
-echo "${ECHO_T}$ac_cv_func_alloca_works" >&6
-
-if test $ac_cv_func_alloca_works = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_ALLOCA 1
-_ACEOF
-
-else
-  # The SVR3 libPW and SVR4 libucb both contain incompatible functions
-# that cause trouble.  Some versions do not even contain alloca or
-# contain a buggy version.  If you still want to use their alloca,
-# use ar to extract alloca.o from them instead of compiling alloca.c.
-
-ALLOCA=alloca.$ac_objext
-
-cat >>confdefs.h <<\_ACEOF
-#define C_ALLOCA 1
-_ACEOF
-
-
-echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5
-echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6
-if test "${ac_cv_os_cray+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#if defined(CRAY) && ! defined(CRAY2)
-webecray
-#else
-wenotbecray
-#endif
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "webecray" >/dev/null 2>&1; then
-  ac_cv_os_cray=yes
-else
-  ac_cv_os_cray=no
-fi
-rm -f conftest*
-
-fi
-echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5
-echo "${ECHO_T}$ac_cv_os_cray" >&6
-if test $ac_cv_os_cray = yes; then
-  for ac_func in _getb67 GETB67 getb67; do
-    as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-
-cat >>confdefs.h <<_ACEOF
-#define CRAY_STACKSEG_END $ac_func
-_ACEOF
-
-    break
-fi
-
+    # The quadruple backslash is collapsed to a double backslash
+    # by the backticks, then collapsed again by the double quotes,
+    # leaving us with one backslash in the sed expression (right
+    # before the dot that mustn't act as a wildcard).
+    cat=`echo $cat | sed -e "s!$srcdir/po/!!" -e "s!\\\\.po!.gmo!"`
+    lang=`echo $cat | sed -e "s!\\\\.gmo!!"`
+    # The user is allowed to set LINGUAS to a list of languages to
+    # install catalogs for.  If it's empty that means "all of them."
+    if test "x$LINGUAS" = x; then
+      CATALOGS="$CATALOGS $cat"
+      XLINGUAS="$XLINGUAS $lang"
+    else
+      case "$LINGUAS" in *$lang*)
+        CATALOGS="$CATALOGS $cat"
+        XLINGUAS="$XLINGUAS $lang"
+        ;;
+      esac
+    fi
   done
-fi
-
-echo "$as_me:$LINENO: checking stack direction for C alloca" >&5
-echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6
-if test "${ac_cv_c_stack_direction+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_c_stack_direction=0
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-int
-find_stack_direction ()
-{
-  static char *addr = 0;
-  auto char dummy;
-  if (addr == 0)
-    {
-      addr = &dummy;
-      return find_stack_direction ();
-    }
-  else
-    return (&dummy > addr) ? 1 : -1;
-}
-
-int
-main ()
-{
-  exit (find_stack_direction () < 0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_c_stack_direction=1
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_c_stack_direction=-1
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5
-echo "${ECHO_T}$ac_cv_c_stack_direction" >&6
-
-cat >>confdefs.h <<_ACEOF
-#define STACK_DIRECTION $ac_cv_c_stack_direction
-_ACEOF
+  LINGUAS="$XLINGUAS"
+  echo "$as_me:$LINENO: result: $LINGUAS" >&5
+echo "${ECHO_T}$LINGUAS" >&6
 
 
-fi
+    DATADIRNAME=share
 
+  INSTOBJEXT=.mo
 
+  GENCAT=gencat
 
-for ac_header in stdlib.h unistd.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
+  CATOBJEXT=.gmo
 
-ac_header_compiler=no
 fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
 
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+        MKINSTALLDIRS=
+  if test -n "$ac_aux_dir"; then
+    case "$ac_aux_dir" in
+      /*) MKINSTALLDIRS="$ac_aux_dir/mkinstalldirs" ;;
+      *) MKINSTALLDIRS="\$(top_builddir)/$ac_aux_dir/mkinstalldirs" ;;
+    esac
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-for ac_func in getpagesize
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-echo "$as_me:$LINENO: checking for working mmap" >&5
-echo $ECHO_N "checking for working mmap... $ECHO_C" >&6
-if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  if test "$cross_compiling" = yes; then
-  ac_cv_func_mmap_fixed_mapped=no
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-/* malloc might have been renamed as rpl_malloc. */
-#undef malloc
-
-/* Thanks to Mike Haertel and Jim Avera for this test.
-   Here is a matrix of mmap possibilities:
-	mmap private not fixed
-	mmap private fixed at somewhere currently unmapped
-	mmap private fixed at somewhere already mapped
-	mmap shared not fixed
-	mmap shared fixed at somewhere currently unmapped
-	mmap shared fixed at somewhere already mapped
-   For private mappings, we should verify that changes cannot be read()
-   back from the file, nor mmap's back from the file at a different
-   address.  (There have been systems where private was not correctly
-   implemented like the infamous i386 svr4.0, and systems where the
-   VM page cache was not coherent with the file system buffer cache
-   like early versions of FreeBSD and possibly contemporary NetBSD.)
-   For shared mappings, we should conversely verify that changes get
-   propagated back to all the places they're supposed to be.
-
-   Grep wants private fixed already mapped.
-   The main things grep needs to know about mmap are:
-   * does it exist and is it safe to write into the mmap'd area
-   * how to use it (BSD variants)  */
-
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#if !STDC_HEADERS && !HAVE_STDLIB_H
-char *malloc ();
-#endif
-
-/* This mess was copied from the GNU getpagesize.h.  */
-#if !HAVE_GETPAGESIZE
-/* Assume that all systems that can run configure have sys/param.h.  */
-# if !HAVE_SYS_PARAM_H
-#  define HAVE_SYS_PARAM_H 1
-# endif
-
-# ifdef _SC_PAGESIZE
-#  define getpagesize() sysconf(_SC_PAGESIZE)
-# else /* no _SC_PAGESIZE */
-#  if HAVE_SYS_PARAM_H
-#   include <sys/param.h>
-#   ifdef EXEC_PAGESIZE
-#    define getpagesize() EXEC_PAGESIZE
-#   else /* no EXEC_PAGESIZE */
-#    ifdef NBPG
-#     define getpagesize() NBPG * CLSIZE
-#     ifndef CLSIZE
-#      define CLSIZE 1
-#     endif /* no CLSIZE */
-#    else /* no NBPG */
-#     ifdef NBPC
-#      define getpagesize() NBPC
-#     else /* no NBPC */
-#      ifdef PAGESIZE
-#       define getpagesize() PAGESIZE
-#      endif /* PAGESIZE */
-#     endif /* no NBPC */
-#    endif /* no NBPG */
-#   endif /* no EXEC_PAGESIZE */
-#  else /* no HAVE_SYS_PARAM_H */
-#   define getpagesize() 8192	/* punt totally */
-#  endif /* no HAVE_SYS_PARAM_H */
-# endif /* no _SC_PAGESIZE */
-
-#endif /* no HAVE_GETPAGESIZE */
-
-int
-main ()
-{
-  char *data, *data2, *data3;
-  int i, pagesize;
-  int fd;
-
-  pagesize = getpagesize ();
-
-  /* First, make a file with some known garbage in it. */
-  data = (char *) malloc (pagesize);
-  if (!data)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    *(data + i) = rand ();
-  umask (0);
-  fd = creat ("conftest.mmap", 0600);
-  if (fd < 0)
-    exit (1);
-  if (write (fd, data, pagesize) != pagesize)
-    exit (1);
-  close (fd);
-
-  /* Next, try to mmap the file at a fixed address which already has
-     something else allocated at it.  If we can, also make sure that
-     we see the same garbage.  */
-  fd = open ("conftest.mmap", O_RDWR);
-  if (fd < 0)
-    exit (1);
-  data2 = (char *) malloc (2 * pagesize);
-  if (!data2)
-    exit (1);
-  data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1);
-  if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE,
-		     MAP_PRIVATE | MAP_FIXED, fd, 0L))
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data2 + i))
-      exit (1);
-
-  /* Finally, make sure that changes to the mapped area do not
-     percolate back to the file as seen by read().  (This is a bug on
-     some variants of i386 svr4.0.)  */
-  for (i = 0; i < pagesize; ++i)
-    *(data2 + i) = *(data2 + i) + 1;
-  data3 = (char *) malloc (pagesize);
-  if (!data3)
-    exit (1);
-  if (read (fd, data3, pagesize) != pagesize)
-    exit (1);
-  for (i = 0; i < pagesize; ++i)
-    if (*(data + i) != *(data3 + i))
-      exit (1);
-  close (fd);
-  exit (0);
-}
-_ACEOF
-rm -f conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_func_mmap_fixed_mapped=yes
-else
-  echo "$as_me: program exited with status $ac_status" >&5
-echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-( exit $ac_status )
-ac_cv_func_mmap_fixed_mapped=no
-fi
-rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
-fi
-fi
-echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5
-echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6
-if test $ac_cv_func_mmap_fixed_mapped = yes; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_MMAP 1
-_ACEOF
-
-fi
-rm -f conftest.mmap
-
-
-
-
-
-
-
-
-
-
-
-for ac_header in argz.h limits.h locale.h nl_types.h malloc.h string.h \
-unistd.h values.h sys/param.h
-do
-as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking $ac_header usability" >&5
-echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <$ac_header>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking $ac_header presence" >&5
-echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <$ac_header>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+  if test -z "$MKINSTALLDIRS"; then
+    MKINSTALLDIRS="\$(top_srcdir)/mkinstalldirs"
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
-echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: $ac_header:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: $ac_header:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for $ac_header" >&5
-echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
-if eval "test \"\${$as_ac_Header+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  eval "$as_ac_Header=\$ac_header_preproc"
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
-
-fi
-if test `eval echo '${'$as_ac_Header'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-
-
-
-
-
-
-
-
-
-
-for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
-__argz_count __argz_stringify __argz_next
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-
-   if test "${ac_cv_func_stpcpy+set}" != "set"; then
-
-for ac_func in stpcpy
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
-
-   fi
-   if test "${ac_cv_func_stpcpy}" = "yes"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_STPCPY 1
-_ACEOF
-
-   fi
-
-   if test $ac_cv_header_locale_h = yes; then
-    echo "$as_me:$LINENO: checking for LC_MESSAGES" >&5
-echo $ECHO_N "checking for LC_MESSAGES... $ECHO_C" >&6
-if test "${am_cv_val_LC_MESSAGES+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <locale.h>
-int
-main ()
-{
-return LC_MESSAGES
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  am_cv_val_LC_MESSAGES=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-am_cv_val_LC_MESSAGES=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $am_cv_val_LC_MESSAGES" >&5
-echo "${ECHO_T}$am_cv_val_LC_MESSAGES" >&6
-    if test $am_cv_val_LC_MESSAGES = yes; then
 
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_LC_MESSAGES 1
-_ACEOF
 
-    fi
-  fi
-   echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+  echo "$as_me:$LINENO: checking whether NLS is requested" >&5
 echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
-        # Check whether --enable-nls or --disable-nls was given.
+    # Check whether --enable-nls or --disable-nls was given.
 if test "${enable_nls+set}" = set; then
   enableval="$enable_nls"
   USE_NLS=$enableval
 else
   USE_NLS=yes
 fi;
-    echo "$as_me:$LINENO: result: $USE_NLS" >&5
+  echo "$as_me:$LINENO: result: $USE_NLS" >&5
 echo "${ECHO_T}$USE_NLS" >&6
 
 
-    USE_INCLUDED_LIBINTL=no
 
-        if test "$USE_NLS" = "yes"; then
-      echo "$as_me:$LINENO: checking whether included gettext is requested" >&5
-echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6
 
-# Check whether --with-included-gettext or --without-included-gettext was given.
-if test "${with_included_gettext+set}" = set; then
-  withval="$with_included_gettext"
-  nls_cv_force_use_gnu_gettext=$withval
-else
-  nls_cv_force_use_gnu_gettext=no
-fi;
-      echo "$as_me:$LINENO: result: $nls_cv_force_use_gnu_gettext" >&5
-echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6
-
-      nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
-      if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
-                        		nls_cv_header_intl=
-	nls_cv_header_libgt=
-	CATOBJEXT=
-
-	if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking libintl.h usability" >&5
-echo $ECHO_N "checking libintl.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <libintl.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
 
-# Is the header present?
-echo "$as_me:$LINENO: checking libintl.h presence" >&5
-echo $ECHO_N "checking libintl.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
   else
-    ac_cpp_err=
+    PATH_SEPARATOR=:
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
-
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: libintl.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: libintl.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: libintl.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: libintl.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: libintl.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: libintl.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: libintl.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: libintl.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for libintl.h" >&5
-echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
-if test "${ac_cv_header_libintl_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_libintl_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
-echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
-
-fi
-if test $ac_cv_header_libintl_h = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libc" >&5
-echo $ECHO_N "checking for gettext in libc... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libc+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <libintl.h>
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libc=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libc" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libc" >&6
-
-	   if test "$gt_cv_func_gettext_libc" != "yes"; then
-	     echo "$as_me:$LINENO: checking for bindtextdomain in -lintl" >&5
-echo $ECHO_N "checking for bindtextdomain in -lintl... $ECHO_C" >&6
-if test "${ac_cv_lib_intl_bindtextdomain+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lintl  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char bindtextdomain ();
-int
-main ()
-{
-bindtextdomain ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_intl_bindtextdomain=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_cv_lib_intl_bindtextdomain=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
+  rm -f conf$$.sh
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_intl_bindtextdomain" >&5
-echo "${ECHO_T}$ac_cv_lib_intl_bindtextdomain" >&6
-if test $ac_cv_lib_intl_bindtextdomain = yes; then
-  echo "$as_me:$LINENO: checking for gettext in libintl" >&5
-echo $ECHO_N "checking for gettext in libintl... $ECHO_C" >&6
-if test "${gt_cv_func_gettext_libintl+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
 
-int
-main ()
-{
-return (int) gettext ("")
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  gt_cv_func_gettext_libintl=yes
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
 else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-gt_cv_func_gettext_libintl=no
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libintl" >&5
-echo "${ECHO_T}$gt_cv_func_gettext_libintl" >&6
+  ac_executable_p="test -f"
 fi
+rm -f conf$$.file
 
-	   fi
-
-	   if test "$gt_cv_func_gettext_libc" = "yes" \
-	      || test "$gt_cv_func_gettext_libintl" = "yes"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define HAVE_GETTEXT 1
-_ACEOF
-
-	      # Extract the first word of "msgfmt", so it can be a program name with args.
+# Extract the first word of "msgfmt", so it can be a program name with args.
 set dummy msgfmt; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8700,137 +11763,39 @@ if test "${ac_cv_path_MSGFMT+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
-  ;;
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --statistics /dev/null >/dev/null 2>&1 &&
+     (if $ac_dir/$ac_word --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+            ac_cv_path_MSGFMT="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
+  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT=":"
+    ;;
 esac
 fi
 MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
+if test "$MSGFMT" != ":"; then
   echo "$as_me:$LINENO: result: $MSGFMT" >&5
 echo "${ECHO_T}$MSGFMT" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
-	      if test "$MSGFMT" != "no"; then
-
-for ac_func in dcgettext
-do
-as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
-echo "$as_me:$LINENO: checking for $ac_func" >&5
-echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
-if eval "test \"\${$as_ac_var+set}\" = set"; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
-   For example, HP-UX 11i <limits.h> declares gettimeofday.  */
-#define $ac_func innocuous_$ac_func
-
-/* System header to define __stub macros and hopefully few prototypes,
-    which can conflict with char $ac_func (); below.
-    Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
-    <limits.h> exists even on freestanding compilers.  */
-
-#ifdef __STDC__
-# include <limits.h>
-#else
-# include <assert.h>
-#endif
-
-#undef $ac_func
-
-/* Override any gcc2 internal prototype to avoid an error.  */
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-/* We use char because int might match the return type of a gcc2
-   builtin and then its argument prototype would still apply.  */
-char $ac_func ();
-/* The GNU C library defines this for functions which it implements
-    to always fail with ENOSYS.  Some functions are actually named
-    something starting with __ and the normal name is an alias.  */
-#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
-choke me
-#else
-char (*f) () = $ac_func;
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-int
-main ()
-{
-return f != $ac_func;
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  eval "$as_ac_var=yes"
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-eval "$as_ac_var=no"
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-fi
-echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
-echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
-if test `eval echo '${'$as_ac_var'}'` = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-done
 
-		# Extract the first word of "gmsgfmt", so it can be a program name with args.
+  # Extract the first word of "gmsgfmt", so it can be a program name with args.
 set dummy gmsgfmt; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8870,7 +11835,37 @@ else
 echo "${ECHO_T}no" >&6
 fi
 
-		# Extract the first word of "xgettext", so it can be a program name with args.
+
+
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
+  else
+    PATH_SEPARATOR=:
+  fi
+  rm -f conf$$.sh
+fi
+
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
+else
+  ac_executable_p="test -f"
+fi
+rm -f conf$$.file
+
+# Extract the first word of "xgettext", so it can be a program name with args.
 set dummy xgettext; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
@@ -8878,27 +11873,31 @@ if test "${ac_cv_path_XGETTEXT+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 &&
+     (if $ac_dir/$ac_word --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+            ac_cv_path_XGETTEXT="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
   test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
+    ;;
 esac
 fi
 XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
+if test "$XGETTEXT" != ":"; then
   echo "$as_me:$LINENO: result: $XGETTEXT" >&5
 echo "${ECHO_T}$XGETTEXT" >&6
 else
@@ -8906,461 +11905,103 @@ else
 echo "${ECHO_T}no" >&6
 fi
 
-		cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-int
-main ()
-{
-extern int _nl_msg_cat_cntr;
-			       return _nl_msg_cat_cntr
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  CATOBJEXT=.gmo
-		   DATADIRNAME=share
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-CATOBJEXT=.mo
-		   DATADIRNAME=lib
-fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-		INSTOBJEXT=.mo
-	      fi
-	    fi
-
-fi
-
-
+    rm -f messages.po
 
 
-        if test x"$CATOBJEXT" = x && test -d $srcdir/../intl; then
-	  # Neither gettext nor catgets in included in the C library.
-	  # Fall back on GNU gettext library (assuming it is present).
-	  nls_cv_use_gnu_gettext=yes
-        fi
-      fi
-
-      if test "$nls_cv_use_gnu_gettext" = "yes"; then
-                INTLOBJS="\$(GETTOBJS)"
-        # Extract the first word of "msgfmt", so it can be a program name with args.
-set dummy msgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_MSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case "$MSGFMT" in
-  /*)
-  ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
-	ac_cv_path_MSGFMT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
-  ;;
-esac
-fi
-MSGFMT="$ac_cv_path_MSGFMT"
-if test -n "$MSGFMT"; then
-  echo "$as_me:$LINENO: result: $MSGFMT" >&5
-echo "${ECHO_T}$MSGFMT" >&6
-else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
-fi
-
-        # Extract the first word of "gmsgfmt", so it can be a program name with args.
-set dummy gmsgfmt; ac_word=$2
-echo "$as_me:$LINENO: checking for $ac_word" >&5
-echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_GMSGFMT+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  case $GMSGFMT in
-  [\\/]* | ?:[\\/]*)
-  ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
-  ;;
-  *)
-  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
-for as_dir in $PATH
-do
-  IFS=$as_save_IFS
-  test -z "$as_dir" && as_dir=.
-  for ac_exec_ext in '' $ac_executable_extensions; do
-  if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
-    ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
-    echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
-    break 2
+# Prepare PATH_SEPARATOR.
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  echo "#! /bin/sh" >conf$$.sh
+  echo  "exit 0"   >>conf$$.sh
+  chmod +x conf$$.sh
+  if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+    PATH_SEPARATOR=';'
+  else
+    PATH_SEPARATOR=:
   fi
-done
-done
-
-  test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
-  ;;
-esac
+  rm -f conf$$.sh
 fi
-GMSGFMT=$ac_cv_path_GMSGFMT
 
-if test -n "$GMSGFMT"; then
-  echo "$as_me:$LINENO: result: $GMSGFMT" >&5
-echo "${ECHO_T}$GMSGFMT" >&6
+# Find out how to test for executable files. Don't use a zero-byte file,
+# as systems may use methods other than mode bits to determine executability.
+cat >conf$$.file <<_ASEOF
+#! /bin/sh
+exit 0
+_ASEOF
+chmod +x conf$$.file
+if test -x conf$$.file >/dev/null 2>&1; then
+  ac_executable_p="test -x"
 else
-  echo "$as_me:$LINENO: result: no" >&5
-echo "${ECHO_T}no" >&6
+  ac_executable_p="test -f"
 fi
+rm -f conf$$.file
 
-        # Extract the first word of "xgettext", so it can be a program name with args.
-set dummy xgettext; ac_word=$2
+# Extract the first word of "msgmerge", so it can be a program name with args.
+set dummy msgmerge; ac_word=$2
 echo "$as_me:$LINENO: checking for $ac_word" >&5
 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
-if test "${ac_cv_path_XGETTEXT+set}" = set; then
+if test "${ac_cv_path_MSGMERGE+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
-  case "$XGETTEXT" in
-  /*)
-  ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
-  ;;
+  case "$MSGMERGE" in
+  [\\/]* | ?:[\\/]*)
+    ac_cv_path_MSGMERGE="$MSGMERGE" # Let the user override the test with a path.
+    ;;
   *)
-  IFS="${IFS= 	}"; ac_save_ifs="$IFS"; IFS="${IFS}:"
-  for ac_dir in $PATH; do
-    test -z "$ac_dir" && ac_dir=.
-    if test -f $ac_dir/$ac_word; then
-      if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
-	ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
-	break
-      fi
-    fi
-  done
-  IFS="$ac_save_ifs"
-  test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
-  ;;
+    ac_save_IFS="$IFS"; IFS=$PATH_SEPARATOR
+    for ac_dir in $PATH; do
+      IFS="$ac_save_IFS"
+      test -z "$ac_dir" && ac_dir=.
+      for ac_exec_ext in '' $ac_executable_extensions; do
+        if $ac_executable_p "$ac_dir/$ac_word$ac_exec_ext"; then
+          if $ac_dir/$ac_word --update -q /dev/null /dev/null >/dev/null 2>&1; then
+            ac_cv_path_MSGMERGE="$ac_dir/$ac_word$ac_exec_ext"
+            break 2
+          fi
+        fi
+      done
+    done
+    IFS="$ac_save_IFS"
+  test -z "$ac_cv_path_MSGMERGE" && ac_cv_path_MSGMERGE=":"
+    ;;
 esac
 fi
-XGETTEXT="$ac_cv_path_XGETTEXT"
-if test -n "$XGETTEXT"; then
-  echo "$as_me:$LINENO: result: $XGETTEXT" >&5
-echo "${ECHO_T}$XGETTEXT" >&6
+MSGMERGE="$ac_cv_path_MSGMERGE"
+if test "$MSGMERGE" != ":"; then
+  echo "$as_me:$LINENO: result: $MSGMERGE" >&5
+echo "${ECHO_T}$MSGMERGE" >&6
 else
   echo "$as_me:$LINENO: result: no" >&5
 echo "${ECHO_T}no" >&6
 fi
 
 
-	USE_INCLUDED_LIBINTL=yes
-        CATOBJEXT=.gmo
-        INSTOBJEXT=.mo
-        DATADIRNAME=share
-	INTLDEPS='$(top_builddir)/../intl/libintl.a'
-	INTLLIBS=$INTLDEPS
-	LIBS=`echo $LIBS | sed -e 's/-lintl//'`
-        nls_cv_header_intl=libintl.h
-        nls_cv_header_libgt=libgettext.h
-      fi
-
-            if test "$XGETTEXT" != ":"; then
-			if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
-	  : ;
-	else
-	  echo "$as_me:$LINENO: result: found xgettext programs is not GNU xgettext; ignore it" >&5
-echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6
-	  XGETTEXT=":"
-	fi
-      fi
-
-      # We need to process the po/ directory.
-      POSUB=po
+      if test "$GMSGFMT" != ":"; then
+            if $GMSGFMT --statistics /dev/null >/dev/null 2>&1 &&
+       (if $GMSGFMT --statistics /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+      : ;
     else
-      DATADIRNAME=share
-      nls_cv_header_intl=libintl.h
-      nls_cv_header_libgt=libgettext.h
-    fi
-
-    # If this is used in GNU gettext we have to set USE_NLS to `yes'
-    # because some of the sources are only built for this goal.
-    if test "$PACKAGE" = gettext; then
-      USE_NLS=yes
-      USE_INCLUDED_LIBINTL=yes
+      GMSGFMT=`echo "$GMSGFMT" | sed -e 's,^.*/,,'`
+      echo "$as_me:$LINENO: result: found $GMSGFMT program is not GNU msgfmt; ignore it" >&5
+echo "${ECHO_T}found $GMSGFMT program is not GNU msgfmt; ignore it" >&6
+      GMSGFMT=":"
     fi
+  fi
 
-                for lang in $ALL_LINGUAS; do
-      GMOFILES="$GMOFILES $lang.gmo"
-      POFILES="$POFILES $lang.po"
-    done
-
-
-
-
-
-
-
-
-
-
-
-
-    if test "x$CATOBJEXT" != "x"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
+      if test "$XGETTEXT" != ":"; then
+            if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null >/dev/null 2>&1 &&
+       (if $XGETTEXT --omit-header --copyright-holder= --msgid-bugs-address= /dev/null 2>&1 >/dev/null | grep usage >/dev/null; then exit 1; else exit 0; fi); then
+      : ;
+    else
+      echo "$as_me:$LINENO: result: found xgettext program is not GNU xgettext; ignore it" >&5
+echo "${ECHO_T}found xgettext program is not GNU xgettext; ignore it" >&6
+      XGETTEXT=":"
     fi
-
-
-   if test "x$CATOBJEXT" != "x"; then
-     if test "x$ALL_LINGUAS" = "x"; then
-       LINGUAS=
-     else
-       echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
-echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
-       NEW_LINGUAS=
-       for lang in ${LINGUAS=$ALL_LINGUAS}; do
-         case "$ALL_LINGUAS" in
-          *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
-         esac
-       done
-       LINGUAS=$NEW_LINGUAS
-       echo "$as_me:$LINENO: result: $LINGUAS" >&5
-echo "${ECHO_T}$LINGUAS" >&6
-     fi
-
-          if test -n "$LINGUAS"; then
-       for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
-     fi
-   fi
-
-            if test $ac_cv_header_locale_h = yes; then
-     INCLUDE_LOCALE_H="#include <locale.h>"
-   else
-     INCLUDE_LOCALE_H="\
-/* The system does not provide the header <locale.h>.  Take care yourself.  */"
-   fi
-
-
-            if test -f $srcdir/po2tbl.sed.in; then
-      if test "$CATOBJEXT" = ".cat"; then
-	 if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-else
-  # Is the header compilable?
-echo "$as_me:$LINENO: checking linux/version.h usability" >&5
-echo $ECHO_N "checking linux/version.h usability... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-$ac_includes_default
-#include <linux/version.h>
-_ACEOF
-rm -f conftest.$ac_objext
-if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
-  (eval $ac_compile) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"
-			 || test ! -s conftest.err'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest.$ac_objext'
-  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
-  (eval $ac_try) 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_header_compiler=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-ac_header_compiler=no
-fi
-rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
-echo "${ECHO_T}$ac_header_compiler" >&6
-
-# Is the header present?
-echo "$as_me:$LINENO: checking linux/version.h presence" >&5
-echo $ECHO_N "checking linux/version.h presence... $ECHO_C" >&6
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-#include <linux/version.h>
-_ACEOF
-if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
-  (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } >/dev/null; then
-  if test -s conftest.err; then
-    ac_cpp_err=$ac_c_preproc_warn_flag
-    ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
-  else
-    ac_cpp_err=
+        rm -f messages.po
   fi
-else
-  ac_cpp_err=yes
-fi
-if test -z "$ac_cpp_err"; then
-  ac_header_preproc=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
 
-  ac_header_preproc=no
-fi
-rm -f conftest.err conftest.$ac_ext
-echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
-echo "${ECHO_T}$ac_header_preproc" >&6
+            ac_config_commands="$ac_config_commands default-1"
 
-# So?  What about this header?
-case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
-  yes:no: )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&5
-echo "$as_me: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the compiler's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the compiler's result" >&2;}
-    ac_header_preproc=yes
-    ;;
-  no:yes:* )
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: present but cannot be compiled" >&5
-echo "$as_me: WARNING: linux/version.h: present but cannot be compiled" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     check for missing prerequisite headers?" >&5
-echo "$as_me: WARNING: linux/version.h:     check for missing prerequisite headers?" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: see the Autoconf documentation" >&5
-echo "$as_me: WARNING: linux/version.h: see the Autoconf documentation" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&5
-echo "$as_me: WARNING: linux/version.h:     section \"Present But Cannot Be Compiled\"" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the preprocessor's result" >&5
-echo "$as_me: WARNING: linux/version.h: proceeding with the preprocessor's result" >&2;}
-    { echo "$as_me:$LINENO: WARNING: linux/version.h: in the future, the compiler will take precedence" >&5
-echo "$as_me: WARNING: linux/version.h: in the future, the compiler will take precedence" >&2;}
-    (
-      cat <<\_ASBOX
-## ------------------------------------------ ##
-## Report this to the AC_PACKAGE_NAME lists.  ##
-## ------------------------------------------ ##
-_ASBOX
-    ) |
-      sed "s/^/$as_me: WARNING:     /" >&2
-    ;;
-esac
-echo "$as_me:$LINENO: checking for linux/version.h" >&5
-echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
-if test "${ac_cv_header_linux_version_h+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_cv_header_linux_version_h=$ac_header_preproc
-fi
-echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
-echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
-
-fi
-if test $ac_cv_header_linux_version_h = yes; then
-  msgformat=linux
-else
-  msgformat=xopen
-fi
-
-
-
-	          	 sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
-      fi
-            sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
-	 $srcdir/po2tbl.sed.in > po2tbl.sed
-   fi
-
-            if test "$PACKAGE" = "gettext"; then
-     GT_NO="#NO#"
-     GT_YES=
-   else
-     GT_NO=
-     GT_YES="#YES#"
-   fi
-
-
-
-   MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
-
-
-      l=
-
-
-            if test -f $srcdir/po/POTFILES.in; then
-      test -d po || mkdir po
-      if test "x$srcdir" != "x."; then
-	 if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
-	    posrcprefix="$srcdir/"
-	 else
-	    posrcprefix="../$srcdir/"
-	 fi
-      else
-	 posrcprefix="../"
-      fi
-      rm -f po/POTFILES
-      sed -e "/^#/d" -e "/^\$/d" -e "s,.*,	$posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
-	 < $srcdir/po/POTFILES.in > po/POTFILES
-   fi
 
 
 echo "$as_me:$LINENO: checking whether to enable maintainer-specific portions of Makefiles" >&5
@@ -9389,6 +12030,16 @@ fi
 
 
 
+if false; then
+  GENINSRC_NEVER_TRUE=
+  GENINSRC_NEVER_FALSE='#'
+else
+  GENINSRC_NEVER_TRUE='#'
+  GENINSRC_NEVER_FALSE=
+fi
+
+
+
 
 
 
@@ -10211,8 +12862,7 @@ yes)
   LIBM=
 case $host in
 *-*-beos* | *-*-cygwin* | *-*-pw32* | *-*-darwin*)
-  # These system don't have libm
-  # on darwin the libm is a symbolic link to libSystem.dylib
+  # These system don't have libm, or don't need it
   ;;
 *-ncr-sysv4.3*)
   echo "$as_me:$LINENO: checking for _mwvalidcheckl in -lmw" >&5
@@ -10283,9 +12933,9 @@ if test $ac_cv_lib_mw__mwvalidcheckl = yes; then
   LIBM="-lmw"
 fi
 
-  echo "$as_me:$LINENO: checking for main in -lm" >&5
-echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6
-if test "${ac_cv_lib_m_main+set}" = set; then
+  echo "$as_me:$LINENO: checking for cos in -lm" >&5
+echo $ECHO_N "checking for cos in -lm... $ECHO_C" >&6
+if test "${ac_cv_lib_m_cos+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   ac_check_lib_save_LIBS=$LIBS
@@ -10297,11 +12947,17 @@ cat confdefs.h >>conftest.$ac_ext
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
 
-
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char cos ();
 int
 main ()
 {
-main ();
+cos ();
   ;
   return 0;
 }
@@ -10328,28 +12984,28 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  ac_cv_lib_m_main=yes
+  ac_cv_lib_m_cos=yes
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_cv_lib_m_main=no
+ac_cv_lib_m_cos=no
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 LIBS=$ac_check_lib_save_LIBS
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5
-echo "${ECHO_T}$ac_cv_lib_m_main" >&6
-if test $ac_cv_lib_m_main = yes; then
+echo "$as_me:$LINENO: result: $ac_cv_lib_m_cos" >&5
+echo "${ECHO_T}$ac_cv_lib_m_cos" >&6
+if test $ac_cv_lib_m_cos = yes; then
   LIBM="$LIBM -lm"
 fi
 
   ;;
 *)
-  echo "$as_me:$LINENO: checking for main in -lm" >&5
-echo $ECHO_N "checking for main in -lm... $ECHO_C" >&6
-if test "${ac_cv_lib_m_main+set}" = set; then
+  echo "$as_me:$LINENO: checking for cos in -lm" >&5
+echo $ECHO_N "checking for cos in -lm... $ECHO_C" >&6
+if test "${ac_cv_lib_m_cos+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   ac_check_lib_save_LIBS=$LIBS
@@ -10361,11 +13017,17 @@ cat confdefs.h >>conftest.$ac_ext
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
 
-
+/* Override any gcc2 internal prototype to avoid an error.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+   builtin and then its argument prototype would still apply.  */
+char cos ();
 int
 main ()
 {
-main ();
+cos ();
   ;
   return 0;
 }
@@ -10392,20 +13054,20 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  ac_cv_lib_m_main=yes
+  ac_cv_lib_m_cos=yes
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-ac_cv_lib_m_main=no
+ac_cv_lib_m_cos=no
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 LIBS=$ac_check_lib_save_LIBS
 fi
-echo "$as_me:$LINENO: result: $ac_cv_lib_m_main" >&5
-echo "${ECHO_T}$ac_cv_lib_m_main" >&6
-if test $ac_cv_lib_m_main = yes; then
+echo "$as_me:$LINENO: result: $ac_cv_lib_m_cos" >&5
+echo "${ECHO_T}$ac_cv_lib_m_cos" >&6
+if test $ac_cv_lib_m_cos = yes; then
   LIBM="-lm"
 fi
 
@@ -10413,6 +13075,7 @@ fi
 esac
 
 
+
   ;;
 esac
 
@@ -11124,6 +13787,16 @@ fi
 
 
 
+case "${host}" in
+*-*-msdos* | *-*-go32* | *-*-mingw32* | *-*-cygwin* | *-*-windows*)
+
+cat >>confdefs.h <<\_ACEOF
+#define USE_BINARY_FOPEN 1
+_ACEOF
+ ;;
+esac
+
+
 
 
 
@@ -11246,6 +13919,13 @@ echo "$as_me: error: conditional \"MAINTAINER_MODE\" was never defined.
 Usually this means the macro was only invoked conditionally." >&2;}
    { (exit 1); exit 1; }; }
 fi
+if test -z "${GENINSRC_NEVER_TRUE}" && test -z "${GENINSRC_NEVER_FALSE}"; then
+  { { echo "$as_me:$LINENO: error: conditional \"GENINSRC_NEVER\" was never defined.
+Usually this means the macro was only invoked conditionally." >&5
+echo "$as_me: error: conditional \"GENINSRC_NEVER\" was never defined.
+Usually this means the macro was only invoked conditionally." >&2;}
+   { (exit 1); exit 1; }; }
+fi
 
 : ${CONFIG_STATUS=./config.status}
 ac_clean_files_save=$ac_clean_files
@@ -11680,6 +14360,254 @@ cat >>$CONFIG_STATUS <<_ACEOF
 #
 
 AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"
+
+
+# The HP-UX ksh and POSIX shell print the target directory to stdout
+# if CDPATH is set.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+sed_quote_subst='$sed_quote_subst'
+double_quote_subst='$double_quote_subst'
+delay_variable_subst='$delay_variable_subst'
+macro_version='`$ECHO "X$macro_version" | $Xsed -e "$delay_single_quote_subst"`'
+macro_revision='`$ECHO "X$macro_revision" | $Xsed -e "$delay_single_quote_subst"`'
+enable_shared='`$ECHO "X$enable_shared" | $Xsed -e "$delay_single_quote_subst"`'
+enable_static='`$ECHO "X$enable_static" | $Xsed -e "$delay_single_quote_subst"`'
+pic_mode='`$ECHO "X$pic_mode" | $Xsed -e "$delay_single_quote_subst"`'
+enable_fast_install='`$ECHO "X$enable_fast_install" | $Xsed -e "$delay_single_quote_subst"`'
+host_alias='`$ECHO "X$host_alias" | $Xsed -e "$delay_single_quote_subst"`'
+host='`$ECHO "X$host" | $Xsed -e "$delay_single_quote_subst"`'
+host_os='`$ECHO "X$host_os" | $Xsed -e "$delay_single_quote_subst"`'
+build_alias='`$ECHO "X$build_alias" | $Xsed -e "$delay_single_quote_subst"`'
+build='`$ECHO "X$build" | $Xsed -e "$delay_single_quote_subst"`'
+build_os='`$ECHO "X$build_os" | $Xsed -e "$delay_single_quote_subst"`'
+SED='`$ECHO "X$SED" | $Xsed -e "$delay_single_quote_subst"`'
+Xsed='`$ECHO "X$Xsed" | $Xsed -e "$delay_single_quote_subst"`'
+GREP='`$ECHO "X$GREP" | $Xsed -e "$delay_single_quote_subst"`'
+EGREP='`$ECHO "X$EGREP" | $Xsed -e "$delay_single_quote_subst"`'
+FGREP='`$ECHO "X$FGREP" | $Xsed -e "$delay_single_quote_subst"`'
+LD='`$ECHO "X$LD" | $Xsed -e "$delay_single_quote_subst"`'
+NM='`$ECHO "X$NM" | $Xsed -e "$delay_single_quote_subst"`'
+LN_S='`$ECHO "X$LN_S" | $Xsed -e "$delay_single_quote_subst"`'
+max_cmd_len='`$ECHO "X$max_cmd_len" | $Xsed -e "$delay_single_quote_subst"`'
+ac_objext='`$ECHO "X$ac_objext" | $Xsed -e "$delay_single_quote_subst"`'
+exeext='`$ECHO "X$exeext" | $Xsed -e "$delay_single_quote_subst"`'
+lt_unset='`$ECHO "X$lt_unset" | $Xsed -e "$delay_single_quote_subst"`'
+lt_SP2NL='`$ECHO "X$lt_SP2NL" | $Xsed -e "$delay_single_quote_subst"`'
+lt_NL2SP='`$ECHO "X$lt_NL2SP" | $Xsed -e "$delay_single_quote_subst"`'
+reload_flag='`$ECHO "X$reload_flag" | $Xsed -e "$delay_single_quote_subst"`'
+reload_cmds='`$ECHO "X$reload_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+deplibs_check_method='`$ECHO "X$deplibs_check_method" | $Xsed -e "$delay_single_quote_subst"`'
+file_magic_cmd='`$ECHO "X$file_magic_cmd" | $Xsed -e "$delay_single_quote_subst"`'
+AR='`$ECHO "X$AR" | $Xsed -e "$delay_single_quote_subst"`'
+AR_FLAGS='`$ECHO "X$AR_FLAGS" | $Xsed -e "$delay_single_quote_subst"`'
+STRIP='`$ECHO "X$STRIP" | $Xsed -e "$delay_single_quote_subst"`'
+RANLIB='`$ECHO "X$RANLIB" | $Xsed -e "$delay_single_quote_subst"`'
+old_postinstall_cmds='`$ECHO "X$old_postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_postuninstall_cmds='`$ECHO "X$old_postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_cmds='`$ECHO "X$old_archive_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+CC='`$ECHO "X$CC" | $Xsed -e "$delay_single_quote_subst"`'
+CFLAGS='`$ECHO "X$CFLAGS" | $Xsed -e "$delay_single_quote_subst"`'
+compiler='`$ECHO "X$compiler" | $Xsed -e "$delay_single_quote_subst"`'
+GCC='`$ECHO "X$GCC" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_pipe='`$ECHO "X$lt_cv_sys_global_symbol_pipe" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_to_cdecl='`$ECHO "X$lt_cv_sys_global_symbol_to_cdecl" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "X$lt_cv_sys_global_symbol_to_c_name_address" | $Xsed -e "$delay_single_quote_subst"`'
+objdir='`$ECHO "X$objdir" | $Xsed -e "$delay_single_quote_subst"`'
+SHELL='`$ECHO "X$SHELL" | $Xsed -e "$delay_single_quote_subst"`'
+ECHO='`$ECHO "X$ECHO" | $Xsed -e "$delay_single_quote_subst"`'
+MAGIC_CMD='`$ECHO "X$MAGIC_CMD" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_no_builtin_flag='`$ECHO "X$lt_prog_compiler_no_builtin_flag" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_wl='`$ECHO "X$lt_prog_compiler_wl" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_pic='`$ECHO "X$lt_prog_compiler_pic" | $Xsed -e "$delay_single_quote_subst"`'
+lt_prog_compiler_static='`$ECHO "X$lt_prog_compiler_static" | $Xsed -e "$delay_single_quote_subst"`'
+lt_cv_prog_compiler_c_o='`$ECHO "X$lt_cv_prog_compiler_c_o" | $Xsed -e "$delay_single_quote_subst"`'
+need_locks='`$ECHO "X$need_locks" | $Xsed -e "$delay_single_quote_subst"`'
+libext='`$ECHO "X$libext" | $Xsed -e "$delay_single_quote_subst"`'
+shrext_cmds='`$ECHO "X$shrext_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+extract_expsyms_cmds='`$ECHO "X$extract_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_cmds_need_lc='`$ECHO "X$archive_cmds_need_lc" | $Xsed -e "$delay_single_quote_subst"`'
+enable_shared_with_static_runtimes='`$ECHO "X$enable_shared_with_static_runtimes" | $Xsed -e "$delay_single_quote_subst"`'
+export_dynamic_flag_spec='`$ECHO "X$export_dynamic_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+whole_archive_flag_spec='`$ECHO "X$whole_archive_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+compiler_needs_object='`$ECHO "X$compiler_needs_object" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_from_new_cmds='`$ECHO "X$old_archive_from_new_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+old_archive_from_expsyms_cmds='`$ECHO "X$old_archive_from_expsyms_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_cmds='`$ECHO "X$archive_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+archive_expsym_cmds='`$ECHO "X$archive_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+module_cmds='`$ECHO "X$module_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+module_expsym_cmds='`$ECHO "X$module_expsym_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+with_gnu_ld='`$ECHO "X$with_gnu_ld" | $Xsed -e "$delay_single_quote_subst"`'
+allow_undefined_flag='`$ECHO "X$allow_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`'
+no_undefined_flag='`$ECHO "X$no_undefined_flag" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_flag_spec='`$ECHO "X$hardcode_libdir_flag_spec" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_flag_spec_ld='`$ECHO "X$hardcode_libdir_flag_spec_ld" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_libdir_separator='`$ECHO "X$hardcode_libdir_separator" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_direct='`$ECHO "X$hardcode_direct" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_direct_absolute='`$ECHO "X$hardcode_direct_absolute" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_minus_L='`$ECHO "X$hardcode_minus_L" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_shlibpath_var='`$ECHO "X$hardcode_shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_automatic='`$ECHO "X$hardcode_automatic" | $Xsed -e "$delay_single_quote_subst"`'
+inherit_rpath='`$ECHO "X$inherit_rpath" | $Xsed -e "$delay_single_quote_subst"`'
+link_all_deplibs='`$ECHO "X$link_all_deplibs" | $Xsed -e "$delay_single_quote_subst"`'
+fix_srcfile_path='`$ECHO "X$fix_srcfile_path" | $Xsed -e "$delay_single_quote_subst"`'
+always_export_symbols='`$ECHO "X$always_export_symbols" | $Xsed -e "$delay_single_quote_subst"`'
+export_symbols_cmds='`$ECHO "X$export_symbols_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+exclude_expsyms='`$ECHO "X$exclude_expsyms" | $Xsed -e "$delay_single_quote_subst"`'
+include_expsyms='`$ECHO "X$include_expsyms" | $Xsed -e "$delay_single_quote_subst"`'
+prelink_cmds='`$ECHO "X$prelink_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+file_list_spec='`$ECHO "X$file_list_spec" | $Xsed -e "$delay_single_quote_subst"`'
+variables_saved_for_relink='`$ECHO "X$variables_saved_for_relink" | $Xsed -e "$delay_single_quote_subst"`'
+need_lib_prefix='`$ECHO "X$need_lib_prefix" | $Xsed -e "$delay_single_quote_subst"`'
+need_version='`$ECHO "X$need_version" | $Xsed -e "$delay_single_quote_subst"`'
+version_type='`$ECHO "X$version_type" | $Xsed -e "$delay_single_quote_subst"`'
+runpath_var='`$ECHO "X$runpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+shlibpath_var='`$ECHO "X$shlibpath_var" | $Xsed -e "$delay_single_quote_subst"`'
+shlibpath_overrides_runpath='`$ECHO "X$shlibpath_overrides_runpath" | $Xsed -e "$delay_single_quote_subst"`'
+libname_spec='`$ECHO "X$libname_spec" | $Xsed -e "$delay_single_quote_subst"`'
+library_names_spec='`$ECHO "X$library_names_spec" | $Xsed -e "$delay_single_quote_subst"`'
+soname_spec='`$ECHO "X$soname_spec" | $Xsed -e "$delay_single_quote_subst"`'
+postinstall_cmds='`$ECHO "X$postinstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+postuninstall_cmds='`$ECHO "X$postuninstall_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+finish_cmds='`$ECHO "X$finish_cmds" | $Xsed -e "$delay_single_quote_subst"`'
+finish_eval='`$ECHO "X$finish_eval" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_into_libs='`$ECHO "X$hardcode_into_libs" | $Xsed -e "$delay_single_quote_subst"`'
+sys_lib_search_path_spec='`$ECHO "X$sys_lib_search_path_spec" | $Xsed -e "$delay_single_quote_subst"`'
+sys_lib_dlsearch_path_spec='`$ECHO "X$sys_lib_dlsearch_path_spec" | $Xsed -e "$delay_single_quote_subst"`'
+hardcode_action='`$ECHO "X$hardcode_action" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen='`$ECHO "X$enable_dlopen" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen_self='`$ECHO "X$enable_dlopen_self" | $Xsed -e "$delay_single_quote_subst"`'
+enable_dlopen_self_static='`$ECHO "X$enable_dlopen_self_static" | $Xsed -e "$delay_single_quote_subst"`'
+old_striplib='`$ECHO "X$old_striplib" | $Xsed -e "$delay_single_quote_subst"`'
+striplib='`$ECHO "X$striplib" | $Xsed -e "$delay_single_quote_subst"`'
+
+LTCC='$LTCC'
+LTCFLAGS='$LTCFLAGS'
+compiler='$compiler_DEFAULT'
+
+# Quote evaled strings.
+for var in SED \
+GREP \
+EGREP \
+FGREP \
+LD \
+NM \
+LN_S \
+lt_SP2NL \
+lt_NL2SP \
+reload_flag \
+deplibs_check_method \
+file_magic_cmd \
+AR \
+AR_FLAGS \
+STRIP \
+RANLIB \
+CC \
+CFLAGS \
+compiler \
+lt_cv_sys_global_symbol_pipe \
+lt_cv_sys_global_symbol_to_cdecl \
+lt_cv_sys_global_symbol_to_c_name_address \
+SHELL \
+ECHO \
+lt_prog_compiler_no_builtin_flag \
+lt_prog_compiler_wl \
+lt_prog_compiler_pic \
+lt_prog_compiler_static \
+lt_cv_prog_compiler_c_o \
+need_locks \
+shrext_cmds \
+export_dynamic_flag_spec \
+whole_archive_flag_spec \
+compiler_needs_object \
+with_gnu_ld \
+allow_undefined_flag \
+no_undefined_flag \
+hardcode_libdir_flag_spec \
+hardcode_libdir_flag_spec_ld \
+hardcode_libdir_separator \
+fix_srcfile_path \
+exclude_expsyms \
+include_expsyms \
+file_list_spec \
+variables_saved_for_relink \
+libname_spec \
+library_names_spec \
+soname_spec \
+finish_eval \
+old_striplib \
+striplib; do
+    case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in
+    *[\\\\\\\`\\"\\\$]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$sed_quote_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+# Double-quote double-evaled strings.
+for var in reload_cmds \
+old_postinstall_cmds \
+old_postuninstall_cmds \
+old_archive_cmds \
+extract_expsyms_cmds \
+old_archive_from_new_cmds \
+old_archive_from_expsyms_cmds \
+archive_cmds \
+archive_expsym_cmds \
+module_cmds \
+module_expsym_cmds \
+export_symbols_cmds \
+prelink_cmds \
+postinstall_cmds \
+postuninstall_cmds \
+finish_cmds \
+sys_lib_search_path_spec \
+sys_lib_dlsearch_path_spec; do
+    case \`eval \\\\\$ECHO "X\\\\\$\$var"\` in
+    *[\\\\\\\`\\"\\\$]*)
+      eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"X\\\$\$var\\" | \\\$Xsed -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\""
+      ;;
+    *)
+      eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\""
+      ;;
+    esac
+done
+
+# Fix-up fallback echo if it was mangled by the above quoting rules.
+case \$lt_ECHO in
+*'\\\$0 --fallback-echo"')  lt_ECHO=\`\$ECHO "X\$lt_ECHO" | \$Xsed -e 's/\\\\\\\\\\\\\\\$0 --fallback-echo"\$/\$0 --fallback-echo"/'\`
+  ;;
+esac
+
+ac_aux_dir='$ac_aux_dir'
+xsi_shell='$xsi_shell'
+lt_shell_append='$lt_shell_append'
+
+# See if we are running on zsh, and set the options which allow our
+# commands through without removal of \ escapes INIT.
+if test -n "\${ZSH_VERSION+set}" ; then
+   setopt NO_GLOB_SUBST
+fi
+
+
+    PACKAGE='$PACKAGE'
+    VERSION='$VERSION'
+    TIMESTAMP='$TIMESTAMP'
+    RM='$RM'
+    ofile='$ofile'
+
+
+
+# Capture the value of obsolete ALL_LINGUAS because we need it to compute
+    # POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES, CATALOGS. But hide it
+    # from automake.
+    eval 'OBSOLETE_ALL_LINGUAS''="$ALL_LINGUAS"'
+    # Capture the value of LINGUAS because we need it to compute CATALOGS.
+    LINGUAS="${LINGUAS-%UNSET%}"
+
 target_cpu_type=${target_cpu_type}
  cgen_cpu_prefix=${cgen_cpu_prefix}
  obj_format=${obj_format}
@@ -11700,6 +14628,8 @@ do
   "doc/Makefile" ) CONFIG_FILES="$CONFIG_FILES doc/Makefile" ;;
   "po/Makefile.in" ) CONFIG_FILES="$CONFIG_FILES po/Makefile.in:po/Make-in" ;;
   "depfiles" ) CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
+  "libtool" ) CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;;
+  "default-1" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default-1" ;;
   "default" ) CONFIG_COMMANDS="$CONFIG_COMMANDS default" ;;
   "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
   *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
@@ -11837,10 +14767,22 @@ s,@AMDEPBACKSLASH@,$AMDEPBACKSLASH,;t t
 s,@CCDEPMODE@,$CCDEPMODE,;t t
 s,@am__fastdepCC_TRUE@,$am__fastdepCC_TRUE,;t t
 s,@am__fastdepCC_FALSE@,$am__fastdepCC_FALSE,;t t
+s,@LIBTOOL@,$LIBTOOL,;t t
+s,@SED@,$SED,;t t
+s,@EGREP@,$EGREP,;t t
+s,@FGREP@,$FGREP,;t t
+s,@GREP@,$GREP,;t t
+s,@LD@,$LD,;t t
+s,@DUMPBIN@,$DUMPBIN,;t t
+s,@ac_ct_DUMPBIN@,$ac_ct_DUMPBIN,;t t
+s,@NM@,$NM,;t t
 s,@LN_S@,$LN_S,;t t
+s,@AR@,$AR,;t t
+s,@ac_ct_AR@,$ac_ct_AR,;t t
 s,@RANLIB@,$RANLIB,;t t
 s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
-s,@LIBTOOL@,$LIBTOOL,;t t
+s,@lt_ECHO@,$lt_ECHO,;t t
+s,@CPP@,$CPP,;t t
 s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
 s,@NO_WERROR@,$NO_WERROR,;t t
 s,@GDBINIT@,$GDBINIT,;t t
@@ -11851,40 +14793,32 @@ s,@obj_format@,$obj_format,;t t
 s,@te_file@,$te_file,;t t
 s,@install_tooldir@,$install_tooldir,;t t
 s,@atof@,$atof,;t t
-s,@BFDLIB@,$BFDLIB,;t t
 s,@OPCODES_LIB@,$OPCODES_LIB,;t t
-s,@BFDVER_H@,$BFDVER_H,;t t
-s,@ALL_OBJ_DEPS@,$ALL_OBJ_DEPS,;t t
 s,@YACC@,$YACC,;t t
 s,@LEX@,$LEX,;t t
 s,@LEXLIB@,$LEXLIB,;t t
 s,@LEX_OUTPUT_ROOT@,$LEX_OUTPUT_ROOT,;t t
-s,@CPP@,$CPP,;t t
-s,@EGREP@,$EGREP,;t t
-s,@ALLOCA@,$ALLOCA,;t t
 s,@USE_NLS@,$USE_NLS,;t t
-s,@MSGFMT@,$MSGFMT,;t t
-s,@GMSGFMT@,$GMSGFMT,;t t
+s,@LIBINTL@,$LIBINTL,;t t
+s,@LIBINTL_DEP@,$LIBINTL_DEP,;t t
+s,@INCINTL@,$INCINTL,;t t
 s,@XGETTEXT@,$XGETTEXT,;t t
-s,@USE_INCLUDED_LIBINTL@,$USE_INCLUDED_LIBINTL,;t t
+s,@GMSGFMT@,$GMSGFMT,;t t
+s,@POSUB@,$POSUB,;t t
 s,@CATALOGS@,$CATALOGS,;t t
-s,@CATOBJEXT@,$CATOBJEXT,;t t
 s,@DATADIRNAME@,$DATADIRNAME,;t t
-s,@GMOFILES@,$GMOFILES,;t t
 s,@INSTOBJEXT@,$INSTOBJEXT,;t t
-s,@INTLDEPS@,$INTLDEPS,;t t
-s,@INTLLIBS@,$INTLLIBS,;t t
-s,@INTLOBJS@,$INTLOBJS,;t t
-s,@POFILES@,$POFILES,;t t
-s,@POSUB@,$POSUB,;t t
-s,@INCLUDE_LOCALE_H@,$INCLUDE_LOCALE_H,;t t
-s,@GT_NO@,$GT_NO,;t t
-s,@GT_YES@,$GT_YES,;t t
+s,@GENCAT@,$GENCAT,;t t
+s,@CATOBJEXT@,$CATOBJEXT,;t t
 s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t
-s,@l@,$l,;t t
+s,@MSGFMT@,$MSGFMT,;t t
+s,@MSGMERGE@,$MSGMERGE,;t t
 s,@MAINTAINER_MODE_TRUE@,$MAINTAINER_MODE_TRUE,;t t
 s,@MAINTAINER_MODE_FALSE@,$MAINTAINER_MODE_FALSE,;t t
 s,@MAINT@,$MAINT,;t t
+s,@GENINSRC_NEVER_TRUE@,$GENINSRC_NEVER_TRUE,;t t
+s,@GENINSRC_NEVER_FALSE@,$GENINSRC_NEVER_FALSE,;t t
+s,@ALLOCA@,$ALLOCA,;t t
 s,@LIBM@,$LIBM,;t t
 s,@datarootdir@,$datarootdir,;t t
 s,@docdir@,$docdir,;t t
@@ -12573,6 +15507,656 @@ echo "$as_me: error: cannot create directory $dirpart/$fdir" >&2;}
   done
 done
  ;;
+    libtool )
+
+    # See if we are running on zsh, and set the options which allow our
+    # commands through without removal of \ escapes.
+    if test -n "${ZSH_VERSION+set}" ; then
+      setopt NO_GLOB_SUBST
+    fi
+
+    cfgfile="${ofile}T"
+    trap "$RM \"$cfgfile\"; exit 1" 1 2 15
+    $RM "$cfgfile"
+
+    cat <<_LT_EOF >> "$cfgfile"
+#! $SHELL
+
+# `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services.
+# Generated automatically by $as_me (GNU $PACKAGE$TIMESTAMP) $VERSION
+# Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+# NOTE: Changes made to this file will be lost: look at ltmain.sh.
+#
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005,
+# 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Libtool:
+# Originally by Gordon Matzigkeit <gord@gnu.ai.mit.edu>, 1996
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, a copy can be downloaded from
+# http://www.gnu.org/copyleft/gpl.html, or by writing to the Free
+# Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+
+# The names of the tagged configurations supported by this script.
+available_tags=""
+
+# ### BEGIN LIBTOOL CONFIG
+
+# Which release of libtool.m4 was used?
+macro_version=$macro_version
+macro_revision=$macro_revision
+
+# Whether or not to build shared libraries.
+build_libtool_libs=$enable_shared
+
+# Whether or not to build static libraries.
+build_old_libs=$enable_static
+
+# What type of objects to build.
+pic_mode=$pic_mode
+
+# Whether or not to optimize for fast installation.
+fast_install=$enable_fast_install
+
+# The host system.
+host_alias=$host_alias
+host=$host
+host_os=$host_os
+
+# The build system.
+build_alias=$build_alias
+build=$build
+build_os=$build_os
+
+# A sed program that does not truncate output.
+SED=$lt_SED
+
+# Sed that helps us avoid accidentally triggering echo(1) options like -n.
+Xsed="\$SED -e 1s/^X//"
+
+# A grep program that handles long lines.
+GREP=$lt_GREP
+
+# An ERE matcher.
+EGREP=$lt_EGREP
+
+# A literal string matcher.
+FGREP=$lt_FGREP
+
+# A BSD- or MS-compatible name lister.
+NM=$lt_NM
+
+# Whether we need soft or hard links.
+LN_S=$lt_LN_S
+
+# What is the maximum length of a command?
+max_cmd_len=$max_cmd_len
+
+# Object file suffix (normally "o").
+objext=$ac_objext
+
+# Executable file suffix (normally "").
+exeext=$exeext
+
+# whether the shell understands "unset".
+lt_unset=$lt_unset
+
+# turn spaces into newlines.
+SP2NL=$lt_lt_SP2NL
+
+# turn newlines into spaces.
+NL2SP=$lt_lt_NL2SP
+
+# How to create reloadable object files.
+reload_flag=$lt_reload_flag
+reload_cmds=$lt_reload_cmds
+
+# Method to check whether dependent libraries are shared objects.
+deplibs_check_method=$lt_deplibs_check_method
+
+# Command to use when deplibs_check_method == "file_magic".
+file_magic_cmd=$lt_file_magic_cmd
+
+# The archiver.
+AR=$lt_AR
+AR_FLAGS=$lt_AR_FLAGS
+
+# A symbol stripping program.
+STRIP=$lt_STRIP
+
+# Commands used to install an old-style archive.
+RANLIB=$lt_RANLIB
+old_postinstall_cmds=$lt_old_postinstall_cmds
+old_postuninstall_cmds=$lt_old_postuninstall_cmds
+
+# A C compiler.
+LTCC=$lt_CC
+
+# LTCC compiler flags.
+LTCFLAGS=$lt_CFLAGS
+
+# Take the output of nm and produce a listing of raw symbols and C names.
+global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe
+
+# Transform the output of nm in a proper C declaration.
+global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl
+
+# Transform the output of nm in a C name address pair.
+global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address
+
+# The name of the directory that contains temporary libtool files.
+objdir=$objdir
+
+# Shell to use when invoking shell scripts.
+SHELL=$lt_SHELL
+
+# An echo program that does not interpret backslashes.
+ECHO=$lt_ECHO
+
+# Used to examine libraries when file_magic_cmd begins with "file".
+MAGIC_CMD=$MAGIC_CMD
+
+# Must we lock files when doing compilation?
+need_locks=$lt_need_locks
+
+# Old archive suffix (normally "a").
+libext=$libext
+
+# Shared library suffix (normally ".so").
+shrext_cmds=$lt_shrext_cmds
+
+# The commands to extract the exported symbol list from a shared archive.
+extract_expsyms_cmds=$lt_extract_expsyms_cmds
+
+# Variables whose values should be saved in libtool wrapper scripts and
+# restored at link time.
+variables_saved_for_relink=$lt_variables_saved_for_relink
+
+# Do we need the "lib" prefix for modules?
+need_lib_prefix=$need_lib_prefix
+
+# Do we need a version for libraries?
+need_version=$need_version
+
+# Library versioning type.
+version_type=$version_type
+
+# Shared library runtime path variable.
+runpath_var=$runpath_var
+
+# Shared library path variable.
+shlibpath_var=$shlibpath_var
+
+# Is shlibpath searched before the hard-coded library search path?
+shlibpath_overrides_runpath=$shlibpath_overrides_runpath
+
+# Format of library name prefix.
+libname_spec=$lt_libname_spec
+
+# List of archive names.  First name is the real one, the rest are links.
+# The last name is the one that the linker finds with -lNAME
+library_names_spec=$lt_library_names_spec
+
+# The coded name of the library, if different from the real name.
+soname_spec=$lt_soname_spec
+
+# Command to use after installation of a shared archive.
+postinstall_cmds=$lt_postinstall_cmds
+
+# Command to use after uninstallation of a shared archive.
+postuninstall_cmds=$lt_postuninstall_cmds
+
+# Commands used to finish a libtool library installation in a directory.
+finish_cmds=$lt_finish_cmds
+
+# As "finish_cmds", except a single script fragment to be evaled but
+# not shown.
+finish_eval=$lt_finish_eval
+
+# Whether we should hardcode library paths into libraries.
+hardcode_into_libs=$hardcode_into_libs
+
+# Compile-time system search path for libraries.
+sys_lib_search_path_spec=$lt_sys_lib_search_path_spec
+
+# Run-time system search path for libraries.
+sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec
+
+# Whether dlopen is supported.
+dlopen_support=$enable_dlopen
+
+# Whether dlopen of programs is supported.
+dlopen_self=$enable_dlopen_self
+
+# Whether dlopen of statically linked programs is supported.
+dlopen_self_static=$enable_dlopen_self_static
+
+# Commands to strip libraries.
+old_striplib=$lt_old_striplib
+striplib=$lt_striplib
+
+
+# The linker used to build libraries.
+LD=$lt_LD
+
+# Commands used to build an old-style archive.
+old_archive_cmds=$lt_old_archive_cmds
+
+# A language specific compiler.
+CC=$lt_compiler
+
+# Is the compiler the GNU compiler?
+with_gcc=$GCC
+
+# Compiler flag to turn off builtin functions.
+no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag
+
+# How to pass a linker flag through the compiler.
+wl=$lt_lt_prog_compiler_wl
+
+# Additional compiler flags for building library objects.
+pic_flag=$lt_lt_prog_compiler_pic
+
+# Compiler flag to prevent dynamic linking.
+link_static_flag=$lt_lt_prog_compiler_static
+
+# Does compiler simultaneously support -c and -o options?
+compiler_c_o=$lt_lt_cv_prog_compiler_c_o
+
+# Whether or not to add -lc for building shared libraries.
+build_libtool_need_lc=$archive_cmds_need_lc
+
+# Whether or not to disallow shared libs when runtime libs are static.
+allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes
+
+# Compiler flag to allow reflexive dlopens.
+export_dynamic_flag_spec=$lt_export_dynamic_flag_spec
+
+# Compiler flag to generate shared objects directly from archives.
+whole_archive_flag_spec=$lt_whole_archive_flag_spec
+
+# Whether the compiler copes with passing no objects directly.
+compiler_needs_object=$lt_compiler_needs_object
+
+# Create an old-style archive from a shared archive.
+old_archive_from_new_cmds=$lt_old_archive_from_new_cmds
+
+# Create a temporary old-style archive to link instead of a shared archive.
+old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds
+
+# Commands used to build a shared archive.
+archive_cmds=$lt_archive_cmds
+archive_expsym_cmds=$lt_archive_expsym_cmds
+
+# Commands used to build a loadable module if different from building
+# a shared archive.
+module_cmds=$lt_module_cmds
+module_expsym_cmds=$lt_module_expsym_cmds
+
+# Whether we are building with GNU ld or not.
+with_gnu_ld=$lt_with_gnu_ld
+
+# Flag that allows shared libraries with undefined symbols to be built.
+allow_undefined_flag=$lt_allow_undefined_flag
+
+# Flag that enforces no undefined symbols.
+no_undefined_flag=$lt_no_undefined_flag
+
+# Flag to hardcode \$libdir into a binary during linking.
+# This must work even if \$libdir does not exist
+hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec
+
+# If ld is used when linking, flag to hardcode \$libdir into a binary
+# during linking.  This must work even if \$libdir does not exist.
+hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld
+
+# Whether we need a single "-rpath" flag with a separated argument.
+hardcode_libdir_separator=$lt_hardcode_libdir_separator
+
+# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
+# DIR into the resulting binary.
+hardcode_direct=$hardcode_direct
+
+# Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes
+# DIR into the resulting binary and the resulting library dependency is
+# "absolute",i.e impossible to change by setting \${shlibpath_var} if the
+# library is relocated.
+hardcode_direct_absolute=$hardcode_direct_absolute
+
+# Set to "yes" if using the -LDIR flag during linking hardcodes DIR
+# into the resulting binary.
+hardcode_minus_L=$hardcode_minus_L
+
+# Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR
+# into the resulting binary.
+hardcode_shlibpath_var=$hardcode_shlibpath_var
+
+# Set to "yes" if building a shared library automatically hardcodes DIR
+# into the library and all subsequent libraries and executables linked
+# against it.
+hardcode_automatic=$hardcode_automatic
+
+# Set to yes if linker adds runtime paths of dependent libraries
+# to runtime path list.
+inherit_rpath=$inherit_rpath
+
+# Whether libtool must link a program against all its dependency libraries.
+link_all_deplibs=$link_all_deplibs
+
+# Fix the shell variable \$srcfile for the compiler.
+fix_srcfile_path=$lt_fix_srcfile_path
+
+# Set to "yes" if exported symbols are required.
+always_export_symbols=$always_export_symbols
+
+# The commands to list exported symbols.
+export_symbols_cmds=$lt_export_symbols_cmds
+
+# Symbols that should not be listed in the preloaded symbols.
+exclude_expsyms=$lt_exclude_expsyms
+
+# Symbols that must always be exported.
+include_expsyms=$lt_include_expsyms
+
+# Commands necessary for linking programs (against libraries) with templates.
+prelink_cmds=$lt_prelink_cmds
+
+# Specify filename containing input files.
+file_list_spec=$lt_file_list_spec
+
+# How to hardcode a shared library path into an executable.
+hardcode_action=$hardcode_action
+
+# ### END LIBTOOL CONFIG
+
+_LT_EOF
+
+  case $host_os in
+  aix3*)
+    cat <<\_LT_EOF >> "$cfgfile"
+# AIX sometimes has problems with the GCC collect2 program.  For some
+# reason, if we set the COLLECT_NAMES environment variable, the problems
+# vanish in a puff of smoke.
+if test "X${COLLECT_NAMES+set}" != Xset; then
+  COLLECT_NAMES=
+  export COLLECT_NAMES
+fi
+_LT_EOF
+    ;;
+  esac
+
+
+ltmain="$ac_aux_dir/ltmain.sh"
+
+
+  # We use sed instead of cat because bash on DJGPP gets confused if
+  # if finds mixed CR/LF and LF-only lines.  Since sed operates in
+  # text mode, it properly converts lines to CR/LF.  This bash problem
+  # is reportedly fixed, but why not run on old versions too?
+  sed '/^# Generated shell functions inserted here/q' "$ltmain" >> "$cfgfile" \
+    || (rm -f "$cfgfile"; exit 1)
+
+  case $xsi_shell in
+  yes)
+    cat << \_LT_EOF >> "$cfgfile"
+# func_dirname file append nondir_replacement
+# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
+# otherwise set result to NONDIR_REPLACEMENT.
+func_dirname ()
+{
+  case ${1} in
+    */*) func_dirname_result="${1%/*}${2}" ;;
+    *  ) func_dirname_result="${3}" ;;
+  esac
+}
+
+# func_basename file
+func_basename ()
+{
+  func_basename_result="${1##*/}"
+}
+
+# func_stripname prefix suffix name
+# strip PREFIX and SUFFIX off of NAME.
+# PREFIX and SUFFIX must not contain globbing or regex special
+# characters, hashes, percent signs, but SUFFIX may contain a leading
+# dot (in which case that matches only a dot).
+func_stripname ()
+{
+  # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are
+  # positional parameters, so assign one to ordinary parameter first.
+  func_stripname_result=${3}
+  func_stripname_result=${func_stripname_result#"${1}"}
+  func_stripname_result=${func_stripname_result%"${2}"}
+}
+
+# func_opt_split
+func_opt_split ()
+{
+  func_opt_split_opt=${1%%=*}
+  func_opt_split_arg=${1#*=}
+}
+
+# func_lo2o object
+func_lo2o ()
+{
+  case ${1} in
+    *.lo) func_lo2o_result=${1%.lo}.${objext} ;;
+    *)    func_lo2o_result=${1} ;;
+  esac
+}
+_LT_EOF
+    ;;
+  *) # Bourne compatible functions.
+    cat << \_LT_EOF >> "$cfgfile"
+# func_dirname file append nondir_replacement
+# Compute the dirname of FILE.  If nonempty, add APPEND to the result,
+# otherwise set result to NONDIR_REPLACEMENT.
+func_dirname ()
+{
+  # Extract subdirectory from the argument.
+  func_dirname_result=`$ECHO "X${1}" | $Xsed -e "$dirname"`
+  if test "X$func_dirname_result" = "X${1}"; then
+    func_dirname_result="${3}"
+  else
+    func_dirname_result="$func_dirname_result${2}"
+  fi
+}
+
+# func_basename file
+func_basename ()
+{
+  func_basename_result=`$ECHO "X${1}" | $Xsed -e "$basename"`
+}
+
+# func_stripname prefix suffix name
+# strip PREFIX and SUFFIX off of NAME.
+# PREFIX and SUFFIX must not contain globbing or regex special
+# characters, hashes, percent signs, but SUFFIX may contain a leading
+# dot (in which case that matches only a dot).
+# func_strip_suffix prefix name
+func_stripname ()
+{
+  case ${2} in
+    .*) func_stripname_result=`$ECHO "X${3}" \
+           | $Xsed -e "s%^${1}%%" -e "s%\\\\${2}\$%%"`;;
+    *)  func_stripname_result=`$ECHO "X${3}" \
+           | $Xsed -e "s%^${1}%%" -e "s%${2}\$%%"`;;
+  esac
+}
+
+# sed scripts:
+my_sed_long_opt='1s/^\(-[^=]*\)=.*/\1/;q'
+my_sed_long_arg='1s/^-[^=]*=//'
+
+# func_opt_split
+func_opt_split ()
+{
+  func_opt_split_opt=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_opt"`
+  func_opt_split_arg=`$ECHO "X${1}" | $Xsed -e "$my_sed_long_arg"`
+}
+
+# func_lo2o object
+func_lo2o ()
+{
+  func_lo2o_result=`$ECHO "X${1}" | $Xsed -e "$lo2o"`
+}
+_LT_EOF
+esac
+
+case $lt_shell_append in
+  yes)
+    cat << \_LT_EOF >> "$cfgfile"
+
+# func_append var value
+# Append VALUE to the end of shell variable VAR.
+func_append ()
+{
+  eval "$1+=\$2"
+}
+_LT_EOF
+    ;;
+  *)
+    cat << \_LT_EOF >> "$cfgfile"
+
+# func_append var value
+# Append VALUE to the end of shell variable VAR.
+func_append ()
+{
+  eval "$1=\$$1\$2"
+}
+_LT_EOF
+    ;;
+  esac
+
+
+  sed -n '/^# Generated shell functions inserted here/,$p' "$ltmain" >> "$cfgfile" \
+    || (rm -f "$cfgfile"; exit 1)
+
+  mv -f "$cfgfile" "$ofile" ||
+    (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile")
+  chmod +x "$ofile"
+
+ ;;
+    default-1 )
+    for ac_file in $CONFIG_FILES; do
+      # Support "outfile[:infile[:infile...]]"
+      case "$ac_file" in
+        *:*) ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+      esac
+      # PO directories have a Makefile.in generated from Makefile.in.in.
+      case "$ac_file" in */Makefile.in)
+        # Adjust a relative srcdir.
+        ac_dir=`echo "$ac_file"|sed 's%/[^/][^/]*$%%'`
+        ac_dir_suffix="/`echo "$ac_dir"|sed 's%^\./%%'`"
+        ac_dots=`echo "$ac_dir_suffix"|sed 's%/[^/]*%../%g'`
+        # In autoconf-2.13 it is called $ac_given_srcdir.
+        # In autoconf-2.50 it is called $srcdir.
+        test -n "$ac_given_srcdir" || ac_given_srcdir="$srcdir"
+        case "$ac_given_srcdir" in
+          .)  top_srcdir=`echo $ac_dots|sed 's%/$%%'` ;;
+          /*) top_srcdir="$ac_given_srcdir" ;;
+          *)  top_srcdir="$ac_dots$ac_given_srcdir" ;;
+        esac
+        if test -f "$ac_given_srcdir/$ac_dir/POTFILES.in"; then
+          rm -f "$ac_dir/POTFILES"
+          test -n "$as_me" && echo "$as_me: creating $ac_dir/POTFILES" || echo "creating $ac_dir/POTFILES"
+          cat "$ac_given_srcdir/$ac_dir/POTFILES.in" | sed -e "/^#/d" -e "/^[ 	]*\$/d" -e "s,.*,     $top_srcdir/& \\\\," | sed -e "\$s/\(.*\) \\\\/\1/" > "$ac_dir/POTFILES"
+          POMAKEFILEDEPS="POTFILES.in"
+          # ALL_LINGUAS, POFILES, GMOFILES, UPDATEPOFILES, DUMMYPOFILES depend
+          # on $ac_dir but don't depend on user-specified configuration
+          # parameters.
+          if test -f "$ac_given_srcdir/$ac_dir/LINGUAS"; then
+            # The LINGUAS file contains the set of available languages.
+            if test -n "$OBSOLETE_ALL_LINGUAS"; then
+              test -n "$as_me" && echo "$as_me: setting ALL_LINGUAS in configure.in is obsolete" || echo "setting ALL_LINGUAS in configure.in is obsolete"
+            fi
+            ALL_LINGUAS_=`sed -e "/^#/d" "$ac_given_srcdir/$ac_dir/LINGUAS"`
+            # Hide the ALL_LINGUAS assigment from automake.
+            eval 'ALL_LINGUAS''=$ALL_LINGUAS_'
+            POMAKEFILEDEPS="$POMAKEFILEDEPS LINGUAS"
+          else
+            # The set of available languages was given in configure.in.
+            eval 'ALL_LINGUAS''=$OBSOLETE_ALL_LINGUAS'
+          fi
+          case "$ac_given_srcdir" in
+            .) srcdirpre= ;;
+            *) srcdirpre='$(srcdir)/' ;;
+          esac
+          POFILES=
+          GMOFILES=
+          UPDATEPOFILES=
+          DUMMYPOFILES=
+          for lang in $ALL_LINGUAS; do
+            POFILES="$POFILES $srcdirpre$lang.po"
+            GMOFILES="$GMOFILES $srcdirpre$lang.gmo"
+            UPDATEPOFILES="$UPDATEPOFILES $lang.po-update"
+            DUMMYPOFILES="$DUMMYPOFILES $lang.nop"
+          done
+          # CATALOGS depends on both $ac_dir and the user's LINGUAS
+          # environment variable.
+          INST_LINGUAS=
+          if test -n "$ALL_LINGUAS"; then
+            for presentlang in $ALL_LINGUAS; do
+              useit=no
+              if test "%UNSET%" != "$LINGUAS"; then
+                desiredlanguages="$LINGUAS"
+              else
+                desiredlanguages="$ALL_LINGUAS"
+              fi
+              for desiredlang in $desiredlanguages; do
+                # Use the presentlang catalog if desiredlang is
+                #   a. equal to presentlang, or
+                #   b. a variant of presentlang (because in this case,
+                #      presentlang can be used as a fallback for messages
+                #      which are not translated in the desiredlang catalog).
+                case "$desiredlang" in
+                  "$presentlang"*) useit=yes;;
+                esac
+              done
+              if test $useit = yes; then
+                INST_LINGUAS="$INST_LINGUAS $presentlang"
+              fi
+            done
+          fi
+          CATALOGS=
+          if test -n "$INST_LINGUAS"; then
+            for lang in $INST_LINGUAS; do
+              CATALOGS="$CATALOGS $lang.gmo"
+            done
+          fi
+          test -n "$as_me" && echo "$as_me: creating $ac_dir/Makefile" || echo "creating $ac_dir/Makefile"
+          sed -e "/^POTFILES =/r $ac_dir/POTFILES" -e "/^# Makevars/r $ac_given_srcdir/$ac_dir/Makevars" -e "s|@POFILES@|$POFILES|g" -e "s|@GMOFILES@|$GMOFILES|g" -e "s|@UPDATEPOFILES@|$UPDATEPOFILES|g" -e "s|@DUMMYPOFILES@|$DUMMYPOFILES|g" -e "s|@CATALOGS@|$CATALOGS|g" -e "s|@POMAKEFILEDEPS@|$POMAKEFILEDEPS|g" "$ac_dir/Makefile.in" > "$ac_dir/Makefile"
+          for f in "$ac_given_srcdir/$ac_dir"/Rules-*; do
+            if test -f "$f"; then
+              case "$f" in
+                *.orig | *.bak | *~) ;;
+                *) cat "$f" >> "$ac_dir/Makefile" ;;
+              esac
+            fi
+          done
+        fi
+        ;;
+      esac
+    done ;;
     default ) rm -f targ-cpu.c targ-cpu.h obj-format.h obj-format.c targ-env.h atof-targ.c itbl-cpu.h
  echo '#include "tc-'"${target_cpu_type}"'.h"' > targ-cpu.h
  echo '#include "obj-'"${obj_format}"'.h"' > obj-format.h
@@ -12580,9 +16164,7 @@ done
  echo '#include "itbl-'"${target_cpu_type}"'.h"' > itbl-cpu.h
  if test "x$cgen_cpu_prefix" != x ; then
    echo '#include "opcodes/'"${cgen_cpu_prefix}"'-desc.h"' > cgen-desc.h
- fi
-
- sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile ;;
+ fi ;;
   esac
 done
 _ACEOF
diff --git a/gas/configure.in b/gas/configure.in
index fe69a51c9259..02e8e53af4fe 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -23,13 +23,14 @@ AM_INIT_AUTOMAKE(gas, ${BFD_VERSION})
 AM_PROG_LIBTOOL
 
 AC_ARG_ENABLE(targets,
-[   --enable-targets       alternative target configurations besides the primary],
+[  --enable-targets        alternative target configurations besides the primary],
 [case "${enableval}" in
   yes | "") AC_ERROR(enable-targets option must specify target names or 'all')
 	    ;;
   no)	    enable_targets= ;;
   *)	    enable_targets=$enableval ;;
 esac])dnl
+
 AC_ARG_ENABLE(commonbfdlib,
 [  --enable-commonbfdlib   build shared BFD/opcodes/libiberty library],
 [case "${enableval}" in
@@ -38,6 +39,20 @@ AC_ARG_ENABLE(commonbfdlib,
   *)   AC_MSG_ERROR([bad value ${enableval} for BFD commonbfdlib option]) ;;
 esac])dnl
 
+ac_checking=yes
+if grep '^RELEASE=y' ${srcdir}/../bfd/Makefile.am >/dev/null 2>/dev/null ; then
+  ac_checking=
+fi
+AC_ARG_ENABLE(checking,
+[  --enable-checking       enable run-time checks],
+[case "${enableval}" in
+  no|none)  ac_checking= ;;
+  *)	    ac_checking=yes ;;
+esac])dnl
+if test x$ac_checking != x ; then
+  AC_DEFINE(ENABLE_CHECKING, 1, [Define if you want run-time sanity checks.])
+fi
+
 using_cgen=no
 
 AM_BINUTILS_WARNINGS
@@ -258,7 +273,7 @@ changequote([,])dnl
 
     # Do we need the opcodes library?
     case ${cpu_type} in
-      vax | i386 | tic30)
+      vax | tic30)
 	;;
 
       *)
@@ -304,18 +319,22 @@ changequote([,])dnl
 	esac
 	;;
 
+      mep)
+	using_cgen=yes
+	;;
+
       mips)
-	echo ${extra_objects} | grep -s "itbl-parse.o" 
+	echo ${extra_objects} | grep -s "itbl-parse.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-parse.o"
 	fi
 
-	echo ${extra_objects} | grep -s "itbl-lex.o" 
+	echo ${extra_objects} | grep -s "itbl-lex.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-lex.o"
 	fi
 
-	echo ${extra_objects} | grep -s "itbl-ops.o" 
+	echo ${extra_objects} | grep -s "itbl-ops.o"
 	if test $? -ne 0 ; then
 	  extra_objects="$extra_objects itbl-ops.o"
 	fi
@@ -417,6 +436,19 @@ if test ${all_targets} = "yes"; then
       ;;
     esac
   ;;
+  x86_64)
+    case ${obj_format} in
+    aout)
+      emulations="$emulations i386coff i386elf"
+      ;;
+    coff)
+      emulations="$emulations i386aout i386elf"
+    ;;
+    elf)
+      emulations="$emulations i386aout i386coff"
+      ;;
+    esac
+  ;;
   esac
 fi
 
@@ -424,8 +456,7 @@ fi
 # IEEE FP.  On those that don't support FP at all, usually IEEE
 # is emulated.
 case ${target_cpu} in
-  vax | tahoe )	atof=${target_cpu} ;;
-  pdp11)	atof=vax ;;
+  vax | pdp11 )	atof=vax ;;
   *)		atof=ieee ;;
 esac
 
@@ -462,6 +493,7 @@ case ${obj_format} in
       i386) AC_DEFINE(I386COFF, 1, [Using i386 COFF?]) ;;
       m68k) AC_DEFINE(M68KCOFF, 1, [Using m68k COFF?]) ;;
       m88k) AC_DEFINE(M88KCOFF, 1, [Using m88k COFF?]) ;;
+      x86_64) AC_DEFINE(I386COFF, 1, [Using i386 COFF?]) ;;
     esac
     ;;
 esac
@@ -511,7 +543,6 @@ if test `set . $formats ; shift ; echo $#` -gt 1 ; then
       ecoff)	AC_DEFINE(OBJ_MAYBE_ECOFF, 1,   [ECOFF support?])   ;;
       elf)	AC_DEFINE(OBJ_MAYBE_ELF, 1,     [ELF support?])     ;;
       generic)	AC_DEFINE(OBJ_MAYBE_GENERIC, 1, [generic support?]) ;;
-      ieee)	AC_DEFINE(OBJ_MAYBE_IEEE, 1,    [IEEE support?])    ;;
       som)	AC_DEFINE(OBJ_MAYBE_SOM, 1,     [SOM support?])     ;;
     esac
     extra_objects="$extra_objects obj-$fmt.o"
@@ -556,16 +587,8 @@ yes)
   ;;
 esac
 
-BFDLIB=../bfd/libbfd.la
-BFDVER_H=../bfd/bfdver.h
-ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-
-AC_SUBST(BFDLIB)
 AC_SUBST(OPCODES_LIB)
 
-AC_SUBST(BFDVER_H)
-AC_SUBST(ALL_OBJ_DEPS)
-
 AC_DEFINE_UNQUOTED(TARGET_ALIAS,	"${target_alias}", [Target alias.])
 AC_DEFINE_UNQUOTED(TARGET_CANONICAL,	"${target}",       [Canonical target.])
 AC_DEFINE_UNQUOTED(TARGET_CPU,		"${target_cpu}",   [Target CPU.])
@@ -578,9 +601,11 @@ AC_PROG_YACC
 AM_PROG_LEX
 
 ALL_LINGUAS="fr tr es rw"
-CY_GNU_GETTEXT
+ZW_GNU_GETTEXT_SISTER_DIR
+AM_PO_SUBDIRS
 
 AM_MAINTAINER_MODE
+AM_CONDITIONAL(GENINSRC_NEVER, false)
 AC_EXEEXT
 
 AC_CHECK_HEADERS(string.h stdlib.h memory.h strings.h unistd.h stdarg.h varargs.h errno.h sys/types.h)
@@ -609,7 +634,7 @@ AC_CHECK_FUNCS(sbrk)
 
 # do we need the math library?
 case "${need_libm}" in
-yes) 
+yes)
   AC_CHECK_LIBM
   AC_SUBST(LIBM)
   ;;
@@ -669,6 +694,8 @@ GAS_CHECK_DECL_NEEDED(strstr, f, char *(*f)(), $gas_test_headers)
 
 AC_CHECK_DECLS([vsnprintf])
 
+BFD_BINARY_FOPEN
+
 dnl Required for html and install-html targets.
 AC_SUBST(datarootdir)
 AC_SUBST(docdir)
@@ -691,9 +718,7 @@ AC_CONFIG_COMMANDS([default],
  echo '#include "itbl-'"${target_cpu_type}"'.h"' > itbl-cpu.h
  if test "x$cgen_cpu_prefix" != x ; then
    echo '#include "opcodes/'"${cgen_cpu_prefix}"'-desc.h"' > cgen-desc.h
- fi
-
- sed -e '/POTFILES =/r po/POTFILES' po/Makefile.in > po/Makefile],
+ fi],
 [target_cpu_type=${target_cpu_type}
  cgen_cpu_prefix=${cgen_cpu_prefix}
  obj_format=${obj_format}
diff --git a/gas/configure.tgt b/gas/configure.tgt
index 696daaa128fb..3b7fb19f3108 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -35,8 +35,10 @@ case ${cpu} in
   arm*)			cpu_type=arm endian=little ;;
   bfin*)		cpu_type=bfin endian=little ;;
   c4x*)			cpu_type=tic4x ;;
+  cr16*)		cpu_type=cr16 endian=little ;;
   crisv32)		cpu_type=cris arch=crisv32 ;;
   crx*)			cpu_type=crx endian=little ;;
+  fido)			cpu_type=m68k ;;
   hppa*)		cpu_type=hppa ;;
   i[3-7]86)		cpu_type=i386 arch=i386;;
   ia64)			cpu_type=ia64 ;;
@@ -51,6 +53,7 @@ case ${cpu} in
   m6811|m6812|m68hc12)	cpu_type=m68hc11 ;;
   m683??)		cpu_type=m68k ;;
   maxq)			cpu_type=maxq ;;
+  mep-*-elf)		cpu_type=mep endian=big ;;
   mips*el)		cpu_type=mips endian=little ;;
   mips*)		cpu_type=mips endian=big ;;
   mt)                   cpu_type=mt endian=big ;;
@@ -62,6 +65,8 @@ case ${cpu} in
   rs6000*)		cpu_type=ppc ;;
   s390x*)		cpu_type=s390 arch=s390x ;;
   s390*)		cpu_type=s390 arch=s390 ;;
+  score*l)              cpu_type=score endian=little ;;
+  score*)               cpu_type=score endian=big ;;
   sh5le*)		cpu_type=sh64 endian=little ;;
   sh5*)			cpu_type=sh64 endian=big ;;
   sh64le*)		cpu_type=sh64 endian=little ;;
@@ -77,7 +82,7 @@ case ${cpu} in
   strongarm*b)		cpu_type=arm endian=big ;;
   strongarm*)		cpu_type=arm endian=little ;;
   v850*)		cpu_type=v850 ;;
-  x86_64)		cpu_type=i386 arch=x86_64;;
+  x86_64*)		cpu_type=i386 arch=x86_64;;
   xscale*be|xscale*b)	cpu_type=arm endian=big ;;
   xscale*)		cpu_type=arm endian=little ;;
   xtensa*)		cpu_type=xtensa arch=xtensa ;;
@@ -109,6 +114,7 @@ case ${generic_target} in
   arm-*-linux*aout*)			fmt=aout em=linux ;;
   arm-*-linux-*eabi*)			fmt=elf  em=armlinuxeabi ;;
   arm-*-linux-*)			fmt=elf  em=linux ;;
+  arm-*-uclinux*eabi*)			fmt=elf  em=armlinuxeabi ;;
   arm-*-uclinux*)			fmt=elf  em=linux ;;
   arm-*-netbsdelf*)                 	fmt=elf  em=nbsd ;;
   arm-*-*n*bsd*)			fmt=aout em=nbsd ;;
@@ -121,6 +127,7 @@ case ${generic_target} in
   avr-*-*)				fmt=elf bfd_gas=yes ;;
   bfin-*-*)				fmt=elf bfd_gas=yes ;;
   bfin-*elf)				fmt=elf ;;
+  cr16-*-elf*)	    			fmt=elf ;;
 
   cris-*-linux-* | crisv32-*-linux-*)
 					fmt=multi em=linux ;;
@@ -209,7 +216,11 @@ case ${generic_target} in
   i386-*-pe)				fmt=coff em=pe ;;
   i386-*-cygwin*)			fmt=coff em=pe ;;
   i386-*-interix*)			fmt=coff em=interix ;;
-  i386-*-mingw32*)			fmt=coff em=pe ;;
+  i386-*-mingw*)
+    case ${cpu} in
+      x86_64*)				fmt=coff em=pep ;;
+      i*)				fmt=coff em=pe ;;
+    esac ;;
   i386-*-nto-qnx*)			fmt=elf ;;
   i386-*-*nt*)				fmt=coff em=pe ;;
   i386-*-chaos)				fmt=elf ;;
@@ -250,6 +261,8 @@ case ${generic_target} in
 
   maxq-*-coff)      			fmt=coff bfd_gas=yes ;;
 
+  mep-*-elf)				fmt=elf ;;
+
   mcore-*-elf)				fmt=elf ;;
   mcore-*-pe)				fmt=coff em=pe bfd_gas=yes ;;
 
@@ -266,6 +279,7 @@ case ${generic_target} in
   mips-*-riscos*)			fmt=ecoff ;;
   mips*-*-linux*)			fmt=elf em=tmips ;;
   mips-*-sysv4*MP* | mips-*-gnu*)	fmt=elf em=tmips ;;
+  mips*-sde-elf*)			fmt=elf em=tmips ;;
   mips-*-sysv*)				fmt=ecoff ;;
   mips-*-elf* | mips-*-rtems*)		fmt=elf ;;
   mips-*-netbsd*)			fmt=elf em=tmips ;;
@@ -314,6 +328,8 @@ case ${generic_target} in
   s390-*-linux-*)			fmt=elf em=linux ;;
   s390-*-tpf*)				fmt=elf ;;
 
+  score-*-elf)                          fmt=elf ;;
+
   sh*-*-linux*)				fmt=elf em=linux
     case ${cpu} in
       sh*eb)	endian=big ;;
@@ -323,7 +339,7 @@ case ${generic_target} in
   sh64*-*-netbsd*)			fmt=elf em=nbsd ;;
   sh*-*-netbsdelf*)			fmt=elf em=nbsd ;;
   sh*-*-symbianelf*)			fmt=elf endian=little ;;
-  sh-*-elf*)				fmt=elf ;;
+  sh-*-elf* | sh-*-uclinux* | sh[12]-*-uclinux*)	fmt=elf ;;
   sh-*-coff*)				fmt=coff ;;
   sh-*-nto*)				fmt=elf ;;
   sh-*-pe*)				fmt=coff em=pe bfd_gas=yes endian=little ;;
@@ -357,6 +373,8 @@ case ${generic_target} in
     esac ;;
   sparc-*-openbsd*)			fmt=elf em=nbsd ;;
 
+  spu-*-elf)				fmt=elf ;;
+
   tic30-*-*aout*)			fmt=aout bfd_gas=yes ;;
   tic30-*-*coff*)			fmt=coff bfd_gas=yes ;;
   tic4x-*-* | c4x-*-*)			fmt=coff bfd_gas=yes ;;
diff --git a/gas/debug.c b/gas/debug.c
index fe2ed8c6536f..3218fff538a3 100644
--- a/gas/debug.c
+++ b/gas/debug.c
@@ -1,5 +1,5 @@
 /* This file is debug.c
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000
+   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,26 +25,28 @@
 
 dmp_frags ()
 {
+  asection *s;
   frchainS *chp;
   char *p;
 
-  for (chp = frchain_root; chp; chp = chp->frch_next)
-    {
-      switch (chp->frch_seg)
-	{
-	case SEG_DATA:
-	  p = "Data";
-	  break;
-	case SEG_TEXT:
-	  p = "Text";
-	  break;
-	default:
-	  p = "???";
-	  break;
-	}
-      printf ("\nSEGMENT %s %d\n", p, chp->frch_subseg);
-      dmp_frag (chp->frch_root, "\t");
-    }
+  for (s = stdoutput->sections; s; s = s->next)
+    for (chp = seg_info (s)->frchainP; chp; chp = chp->frch_next)
+      {
+	switch (s)
+	  {
+	  case SEG_DATA:
+	    p = "Data";
+	    break;
+	  case SEG_TEXT:
+	    p = "Text";
+	    break;
+	  default:
+	    p = "???";
+	    break;
+	  }
+	printf ("\nSEGMENT %s %d\n", p, chp->frch_subseg);
+	dmp_frag (chp->frch_root, "\t");
+      }
 }
 
 dmp_frag (fp, indent)
diff --git a/gas/dep-in.sed b/gas/dep-in.sed
index f23c2018fe97..d81c4609b9c0 100644
--- a/gas/dep-in.sed
+++ b/gas/dep-in.sed
@@ -12,14 +12,13 @@ s!@SRCDIR@/config!$(srcdir)/config!g
 s!@SRCDIR@/\.\./opcodes!$(srcdir)/../opcodes!g
 s!@TOPDIR@/opcodes!$(srcdir)/../opcodes!g
 s!@SRCDIR@/!!g
-s!\.\./bfd/bfdver\.h!$(BFDVER_H)!g
 s! \$(srcdir)/config/te-generic\.h!!g
-s! \.\./bfd/bfd\.h!!g
 s! itbl-cpu\.h!!g
 s! itbl-parse\.h!!g
 s! \.\./intl/libintl\.h!!g
 
-s! \$(INCDIR)/bin-bugs\.h!!g
+s! \.\./bfd/bfd\.h!!g
+s! \$(INCDIR)/symcat\.h!!g
 s! \$(INCDIR)/ansidecl\.h!!g
 s! \$(INCDIR)/libiberty\.h!!g
 s! \$(INCDIR)/progress\.h!!g
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index d48a9ccb2412..4f6ff9294c08 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -16,9 +16,12 @@ POD2MAN = pod2man --center="GNU Development Tools" \
 man_MANS = as.1
 
 info_TEXINFOS = as.texinfo 
+as_TEXINFOS = asconfig.texi $(CPU_DOCS)
 
-AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
-TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
 
 asconfig.texi: $(CONFIG).texi
 	rm -f asconfig.texi
@@ -29,7 +32,9 @@ CPU_DOCS = \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
@@ -61,13 +66,6 @@ CPU_DOCS = \
 	c-z80.texi \
 	c-z8k.texi
 
-gasver.texi: $(srcdir)/../../bfd/configure
-	rm -f $@
-	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
-	  echo "@set VERSION $$VERSION" > $@
-
-$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
@@ -97,7 +95,7 @@ install-html-am: $(HTMLS)
 
 noinst_TEXINFOS = internals.texi
 
-MAINTAINERCLEANFILES = asconfig.texi gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi
 
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
@@ -112,7 +110,7 @@ info-local: $(MANS)
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
 # the man output looks standard.
-as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS)
 	touch $@
 	-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
 	-($(POD2MAN) as.pod | \
@@ -120,3 +118,12 @@ as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
 	        mv -f $@.T$$$$ $@) || \
 	        (rm -f $@.T$$$$ && exit 1)
 	rm -f as.pod
+
+MAINTAINERCLEANFILES += as.info
+
+# Automake 1.9 will only build info files in the objdir if they are
+# mentioned in DISTCLEANFILES.  It doesn't have to be unconditional,
+# though, so we use a bogus condition.
+if GENINSRC_NEVER
+DISTCLEANFILES = as.info
+endif
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index cd9dad2baaf8..86f3d7a42693 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -37,11 +37,19 @@ build_triplet = @build@
 host_triplet = @host@
 target_triplet = @target@
 subdir = doc
-DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am
+DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \
+	$(as_TEXINFOS)
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
-	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
+am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
+	$(top_srcdir)/../bfd/warning.m4 \
+	$(top_srcdir)/../config/depstand.m4 \
+	$(top_srcdir)/../config/gettext-sister.m4 \
+	$(top_srcdir)/../config/lead-dot.m4 \
+	$(top_srcdir)/../config/nls.m4 $(top_srcdir)/../config/po.m4 \
+	$(top_srcdir)/../config/progtest.m4 \
+	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
+	$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
+	$(top_srcdir)/acinclude.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
@@ -50,7 +58,7 @@ CONFIG_CLEAN_FILES =
 depcomp =
 am__depfiles_maybe =
 SOURCES =
-INFO_DEPS = $(srcdir)/as.info
+INFO_DEPS = as.info
 TEXINFO_TEX = $(top_srcdir)/../texinfo/texinfo.tex
 am__TEXINFO_TEX_DIR = $(top_srcdir)/../texinfo
 DVIS = as.dvi
@@ -68,16 +76,14 @@ NROFF = nroff
 MANS = $(man_MANS)
 ACLOCAL = @ACLOCAL@
 ALLOCA = @ALLOCA@
-ALL_OBJ_DEPS = @ALL_OBJ_DEPS@
 AMDEP_FALSE = @AMDEP_FALSE@
 AMDEP_TRUE = @AMDEP_TRUE@
 AMTAR = @AMTAR@
+AR = @AR@
 AUTOCONF = @AUTOCONF@
 AUTOHEADER = @AUTOHEADER@
 AUTOMAKE = @AUTOMAKE@
 AWK = @AWK@
-BFDLIB = @BFDLIB@
-BFDVER_H = @BFDVER_H@
 CATALOGS = @CATALOGS@
 CATOBJEXT = @CATOBJEXT@
 CC = @CC@
@@ -89,29 +95,32 @@ CYGPATH_W = @CYGPATH_W@
 DATADIRNAME = @DATADIRNAME@
 DEFS = @DEFS@
 DEPDIR = @DEPDIR@
+DUMPBIN = @DUMPBIN@
 ECHO_C = @ECHO_C@
 ECHO_N = @ECHO_N@
 ECHO_T = @ECHO_T@
 EGREP = @EGREP@
 EXEEXT = @EXEEXT@
+FGREP = @FGREP@
 GDBINIT = @GDBINIT@
-GMOFILES = @GMOFILES@
+GENCAT = @GENCAT@
+GENINSRC_NEVER_FALSE = @GENINSRC_NEVER_FALSE@
+GENINSRC_NEVER_TRUE = @GENINSRC_NEVER_TRUE@
 GMSGFMT = @GMSGFMT@
-GT_NO = @GT_NO@
-GT_YES = @GT_YES@
-INCLUDE_LOCALE_H = @INCLUDE_LOCALE_H@
+GREP = @GREP@
+INCINTL = @INCINTL@
 INSTALL_DATA = @INSTALL_DATA@
 INSTALL_PROGRAM = @INSTALL_PROGRAM@
 INSTALL_SCRIPT = @INSTALL_SCRIPT@
 INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
 INSTOBJEXT = @INSTOBJEXT@
-INTLDEPS = @INTLDEPS@
-INTLLIBS = @INTLLIBS@
-INTLOBJS = @INTLOBJS@
+LD = @LD@
 LDFLAGS = @LDFLAGS@
 LEX = @LEX@
 LEXLIB = @LEXLIB@
 LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@
+LIBINTL = @LIBINTL@
+LIBINTL_DEP = @LIBINTL_DEP@
 LIBM = @LIBM@
 LIBOBJS = @LIBOBJS@
 LIBS = @LIBS@
@@ -124,6 +133,8 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+MSGMERGE = @MSGMERGE@
+NM = @NM@
 NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
@@ -134,19 +145,20 @@ PACKAGE_STRING = @PACKAGE_STRING@
 PACKAGE_TARNAME = @PACKAGE_TARNAME@
 PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
-POFILES = @POFILES@
 POSUB = @POSUB@
 RANLIB = @RANLIB@
+SED = @SED@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
-USE_INCLUDED_LIBINTL = @USE_INCLUDED_LIBINTL@
 USE_NLS = @USE_NLS@
 VERSION = @VERSION@
 WARN_CFLAGS = @WARN_CFLAGS@
 XGETTEXT = @XGETTEXT@
 YACC = @YACC@
+ac_ct_AR = @ac_ct_AR@
 ac_ct_CC = @ac_ct_CC@
+ac_ct_DUMPBIN = @ac_ct_DUMPBIN@
 ac_ct_RANLIB = @ac_ct_RANLIB@
 ac_ct_STRIP = @ac_ct_STRIP@
 am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
@@ -179,10 +191,10 @@ includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
 install_tooldir = @install_tooldir@
-l = @l@
 libdir = @libdir@
 libexecdir = @libexecdir@
 localstatedir = @localstatedir@
+lt_ECHO = @lt_ECHO@
 mandir = @mandir@
 mkdir_p = @mkdir_p@
 obj_format = @obj_format@
@@ -212,13 +224,20 @@ POD2MAN = pod2man --center="GNU Development Tools" \
 
 man_MANS = as.1
 info_TEXINFOS = as.texinfo 
-AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
-TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+as_TEXINFOS = asconfig.texi $(CPU_DOCS)
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
+		   -I ../../bfd/doc
+
 CPU_DOCS = \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-avr.texi \
 	c-bfin.texi \
+	c-cr16.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
@@ -254,14 +273,19 @@ html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
 
 # This one isn't ready for prime time yet.  Not even a little bit.
 noinst_TEXINFOS = internals.texi
-MAINTAINERCLEANFILES = asconfig.texi gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi as.info
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
 CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
+
+# Automake 1.9 will only build info files in the objdir if they are
+# mentioned in DISTCLEANFILES.  It doesn't have to be unconditional,
+# though, so we use a bogus condition.
+@GENINSRC_NEVER_TRUE@DISTCLEANFILES = as.info
 all: all-am
 
 .SUFFIXES:
-.SUFFIXES: .dvi .html .info .pdf .ps .texinfo
+.SUFFIXES: .dvi .ps
 $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__configure_deps)
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
@@ -271,9 +295,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  doc/Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  doc/Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --foreign  doc/Makefile
+	  $(AUTOMAKE) --cygnus  doc/Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -301,42 +325,38 @@ clean-libtool:
 distclean-libtool:
 	-rm -f libtool
 
-.texinfo.info:
+as.info: as.texinfo $(as_TEXINFOS)
 	restore=: && backupdir="$(am__leading_dot)am$$$$" && \
-	am__cwd=`pwd` && cd $(srcdir) && \
 	rm -rf $$backupdir && mkdir $$backupdir && \
 	if ($(MAKEINFO) --version) >/dev/null 2>&1; then \
 	  for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \
 	    if test -f $$f; then mv $$f $$backupdir; restore=mv; else :; fi; \
 	  done; \
 	else :; fi && \
-	cd "$$am__cwd"; \
 	if $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-	 -o $@ $<; \
+	 -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
 	then \
 	  rc=0; \
-	  cd $(srcdir); \
 	else \
 	  rc=$$?; \
-	  cd $(srcdir) && \
 	  $$restore $$backupdir/* `echo "./$@" | sed 's|[^/]*$$||'`; \
 	fi; \
 	rm -rf $$backupdir; exit $$rc
 
-.texinfo.dvi:
+as.dvi: as.texinfo $(as_TEXINFOS) 
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
-	$(TEXI2DVI) $<
+	$(TEXI2DVI) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
 
-.texinfo.pdf:
+as.pdf: as.texinfo $(as_TEXINFOS) 
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \
-	$(TEXI2PDF) $<
+	$(TEXI2PDF) -o $@ `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo
 
-.texinfo.html:
+as.html: as.texinfo $(as_TEXINFOS) 
 	rm -rf $(@:.html=.htp)
 	if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-	 -o $(@:.html=.htp) $<; \
+	 -o $(@:.html=.htp) `test -f 'as.texinfo' || echo '$(srcdir)/'`as.texinfo; \
 	then \
 	  rm -rf $@; \
 	  if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \
@@ -346,10 +366,6 @@ distclean-libtool:
 	    rm -rf $(@:.html=); else rm -Rf $(@:.html=.htp) $@; fi; \
 	  exit 1; \
 	fi
-$(srcdir)/as.info: as.texinfo 
-as.dvi: as.texinfo 
-as.pdf: as.texinfo 
-as.html: as.texinfo 
 .dvi.ps:
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	$(DVIPS) -o $@ $<
@@ -481,6 +497,7 @@ clean-generic:
 
 distclean-generic:
 	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+	-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
 
 maintainer-clean-generic:
 	@echo "This command is intended for maintainers to use"
@@ -586,13 +603,6 @@ asconfig.texi: $(CONFIG).texi
 	cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
 	chmod u+w ./asconfig.texi
 
-gasver.texi: $(srcdir)/../../bfd/configure
-	rm -f $@
-	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
-	  echo "@set VERSION $$VERSION" > $@
-
-$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
@@ -624,7 +634,7 @@ info-local: $(MANS)
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
 # the man output looks standard.
-as.1: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS)
 	touch $@
 	-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
 	-($(POD2MAN) as.pod | \
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index 5192f5471c97..b4778bf8b283 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -29,7 +29,9 @@
 @set ALPHA
 @set ARC
 @set ARM
+@set AVR
 @set BFIN
+@set CR16
 @set CRIS
 @set D10V
 @set D30V
@@ -63,7 +65,7 @@
 @set Z80
 @set Z8000
 
-@c Does this version of the assembler use the difference-table kluge?
+@c Does this version of the assembler use the difference-table kludge?
 @set DIFF-TBL-KLUGE
 
 @c Do all machines described use IEEE floating point?
diff --git a/gas/doc/as.1 b/gas/doc/as.1
deleted file mode 100644
index 89e3b4c2c7c8..000000000000
--- a/gas/doc/as.1
+++ /dev/null
@@ -1,1109 +0,0 @@
-.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32
-.\"
-.\" Standard preamble:
-.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
-.if n .sp
-..
-.de Vb \" Begin verbatim text
-.ft CW
-.nf
-.ne \\$1
-..
-.de Ve \" End verbatim text
-.ft R
-.fi
-..
-.\" Set up some character translations and predefined strings.  \*(-- will
-.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
-.\" double quote, and \*(R" will give a right double quote.  \*(C+ will
-.\" give a nicer C++.  Capital omega is used to do unbreakable dashes and
-.\" therefore won't be available.  \*(C` and \*(C' expand to `' in nroff,
-.\" nothing in troff, for use with C<>.
-.tr \(*W-
-.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
-.ie n \{\
-.    ds -- \(*W-
-.    ds PI pi
-.    if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
-.    if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\"  diablo 12 pitch
-.    ds L" ""
-.    ds R" ""
-.    ds C` ""
-.    ds C' ""
-'br\}
-.el\{\
-.    ds -- \|\(em\|
-.    ds PI \(*p
-.    ds L" ``
-.    ds R" ''
-'br\}
-.\"
-.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
-.\" entries marked with X<> in POD.  Of course, you'll have to process the
-.\" output yourself in some meaningful fashion.
-.if \nF \{\
-.    de IX
-.    tm Index:\\$1\t\\n%\t"\\$2"
-..
-.    nr % 0
-.    rr F
-.\}
-.\"
-.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
-.\" way too many mistakes in technical documents.
-.hy 0
-.\"
-.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
-.\" Fear.  Run.  Save yourself.  No user-serviceable parts.
-.    \" fudge factors for nroff and troff
-.if n \{\
-.    ds #H 0
-.    ds #V .8m
-.    ds #F .3m
-.    ds #[ \f1
-.    ds #] \fP
-.\}
-.if t \{\
-.    ds #H ((1u-(\\\\n(.fu%2u))*.13m)
-.    ds #V .6m
-.    ds #F 0
-.    ds #[ \&
-.    ds #] \&
-.\}
-.    \" simple accents for nroff and troff
-.if n \{\
-.    ds ' \&
-.    ds ` \&
-.    ds ^ \&
-.    ds , \&
-.    ds ~ ~
-.    ds /
-.\}
-.if t \{\
-.    ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
-.    ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
-.    ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
-.    ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
-.    ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
-.    ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
-.\}
-.    \" troff and (daisy-wheel) nroff accents
-.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
-.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
-.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
-.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
-.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
-.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
-.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
-.ds ae a\h'-(\w'a'u*4/10)'e
-.ds Ae A\h'-(\w'A'u*4/10)'E
-.    \" corrections for vroff
-.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
-.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
-.    \" for low resolution devices (crt and lpr)
-.if \n(.H>23 .if \n(.V>19 \
-\{\
-.    ds : e
-.    ds 8 ss
-.    ds o a
-.    ds d- d\h'-1'\(ga
-.    ds D- D\h'-1'\(hy
-.    ds th \o'bp'
-.    ds Th \o'LP'
-.    ds ae ae
-.    ds Ae AE
-.\}
-.rm #[ #] #H #V #F C
-.\" ========================================================================
-.\"
-.IX Title "AS 1"
-.TH AS 1 "2006-06-23" "binutils-2.17" "GNU Development Tools"
-.SH "NAME"
-AS \- the portable GNU assembler.
-.SH "SYNOPSIS"
-.IX Header "SYNOPSIS"
-as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
- [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
- [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
- [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR
- \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]
- [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]
- [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
- [\fB\-\-target\-help\fR] [\fItarget-options\fR]
- [\fB\-\-\fR|\fIfiles\fR ...]
-.PP
-\&\fITarget Alpha options:\fR
-   [\fB\-m\fR\fIcpu\fR]
-   [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
-   [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
-   [\fB\-F\fR] [\fB\-32addr\fR]
-.PP
-\&\fITarget \s-1ARC\s0 options:\fR
-   [\fB\-marc[5|6|7|8]\fR]
-   [\fB\-EB\fR|\fB\-EL\fR]
-.PP
-\&\fITarget \s-1ARM\s0 options:\fR
-   [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
-   [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
-   [\fB\-mfpu\fR=\fIfloating-point-format\fR]
-   [\fB\-mfloat\-abi\fR=\fIabi\fR]
-   [\fB\-meabi\fR=\fIver\fR]
-   [\fB\-mthumb\fR]
-   [\fB\-EB\fR|\fB\-EL\fR]
-   [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
-    \fB\-mapcs\-reentrant\fR]
-   [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
-.PP
-\&\fITarget \s-1CRIS\s0 options:\fR
-   [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
-   [\fB\-\-pic\fR] [\fB\-N\fR]
-   [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
-   [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
-.PP
-\&\fITarget D10V options:\fR
-   [\fB\-O\fR]
-.PP
-\&\fITarget D30V options:\fR
-   [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
-.PP
-\&\fITarget i386 options:\fR
-   [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR]
-.PP
-\&\fITarget i960 options:\fR
-   [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
-    \fB\-AKC\fR|\fB\-AMC\fR]
-   [\fB\-b\fR] [\fB\-no\-relax\fR]
-.PP
-\&\fITarget \s-1IA\-64\s0 options:\fR
-   [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
-   [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
-   [\fB\-mle\fR|\fBmbe\fR]
-   [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
-   [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
-   [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
-   [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
-.PP
-\&\fITarget \s-1IP2K\s0 options:\fR
-   [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
-.PP
-\&\fITarget M32C options:\fR
-   [\fB\-m32c\fR|\fB\-m16c\fR]
-.PP
-\&\fITarget M32R options:\fR
-   [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
-   \fB\-\-W[n]p\fR]
-.PP
-\&\fITarget M680X0 options:\fR
-   [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
-.PP
-\&\fITarget M68HC11 options:\fR
-   [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR]
-   [\fB\-mshort\fR|\fB\-mlong\fR]
-   [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
-   [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
-   [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
-   [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
-.PP
-\&\fITarget \s-1MCORE\s0 options:\fR
-   [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
-   [\fB\-mcpu=[210|340]\fR]
-.PP
-\&\fITarget \s-1MIPS\s0 options:\fR
-   [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
-   [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
-   [\fB\-non_shared\fR] [\fB\-xgot\fR]
-   [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
-   [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
-   [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
-   [\fB\-mips64\fR] [\fB\-mips64r2\fR]
-   [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
-   [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
-   [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
-   [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
-   [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
-   [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
-   [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
-   [\fB\-mmt\fR] [\fB\-mno\-mt\fR]
-   [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
-   [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
-.PP
-\&\fITarget \s-1MMIX\s0 options:\fR
-   [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
-   [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
-   [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
-   [\fB\-\-linker\-allocated\-gregs\fR]
-.PP
-\&\fITarget \s-1PDP11\s0 options:\fR
-   [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
-   [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
-   [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]  
-.PP
-\&\fITarget picoJava options:\fR
-   [\fB\-mb\fR|\fB\-me\fR]
-.PP
-\&\fITarget PowerPC options:\fR
-   [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
-    \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
-    \fB\-mbooke32\fR|\fB\-mbooke64\fR]
-   [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
-   [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
-   [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
-   [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
-   [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
-.PP
-\&\fITarget \s-1SPARC\s0 options:\fR
-   [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
-    \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
-   [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
-   [\fB\-32\fR|\fB\-64\fR]
-.PP
-\&\fITarget \s-1TIC54X\s0 options:\fR
- [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] 
- [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
-.PP
-\&\fITarget Z80 options:\fR
-  [\fB\-z80\fR] [\fB\-r800\fR]
-  [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
-  [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
-  [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
-  [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
-  [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
-  [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
-.PP
-\&\fITarget Xtensa options:\fR
- [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]
- [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
- [\fB\-\-[no\-]transform\fR]
- [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
-.SH "DESCRIPTION"
-.IX Header "DESCRIPTION"
-\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
-If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
-should find a fairly similar environment when you use it on another
-architecture.  Each version has much in common with the others,
-including object file formats, most assembler directives (often called
-\&\fIpseudo-ops\fR) and assembler syntax.
-.PP
-\&\fBas\fR is primarily intended to assemble the output of the
-\&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
-\&\f(CW\*(C`ld\*(C'\fR.  Nevertheless, we've tried to make \fBas\fR
-assemble correctly everything that other assemblers for the same
-machine would assemble.
-Any exceptions are documented explicitly.
-This doesn't mean \fBas\fR always uses the same syntax as another
-assembler for the same architecture; for example, we know of several
-incompatible versions of 680x0 assembly language syntax.
-.PP
-Each time you run \fBas\fR it assembles exactly one source
-program.  The source program is made up of one or more files.
-(The standard input is also a file.)
-.PP
-You give \fBas\fR a command line that has zero or more input file
-names.  The input files are read (from left file name to right).  A
-command line argument (in any position) that has no special meaning
-is taken to be an input file name.
-.PP
-If you give \fBas\fR no file names it attempts to read one input file
-from the \fBas\fR standard input, which is normally your terminal.  You
-may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
-to assemble.
-.PP
-Use \fB\-\-\fR if you need to explicitly name the standard input file
-in your command line.
-.PP
-If the source is empty, \fBas\fR produces a small, empty object
-file.
-.PP
-\&\fBas\fR may write warnings and error messages to the standard error
-file (usually your terminal).  This should not happen when  a compiler
-runs \fBas\fR automatically.  Warnings report an assumption made so
-that \fBas\fR could keep assembling a flawed program; errors report a
-grave problem that stops the assembly.
-.PP
-If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,
-you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
-The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
-by commas.  For example:
-.PP
-.Vb 1
-\&        gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
-.Ve
-.PP
-This passes two options to the assembler: \fB\-alh\fR (emit a listing to
-standard output with high-level and assembly source) and \fB\-L\fR (retain
-local symbols in the symbol table).
-.PP
-Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
-command-line options are automatically passed to the assembler by the compiler.
-(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
-precisely what options it passes to each compilation pass, including the
-assembler.)
-.SH "OPTIONS"
-.IX Header "OPTIONS"
-.IP "\fB@\fR\fIfile\fR" 4
-.IX Item "@file"
-Read command-line options from \fIfile\fR.  The options read are
-inserted in place of the original @\fIfile\fR option.  If \fIfile\fR
-does not exist, or cannot be read, then the option will be treated
-literally, and not removed.  
-.Sp
-Options in \fIfile\fR are separated by whitespace.  A whitespace
-character may be included in an option by surrounding the entire
-option in either single or double quotes.  Any character (including a
-backslash) may be included by prefixing the character to be included
-with a backslash.  The \fIfile\fR may itself contain additional
-@\fIfile\fR options; any such options will be processed recursively.
-.IP "\fB\-a[cdhlmns]\fR" 4
-.IX Item "-a[cdhlmns]"
-Turn on listings, in any of a variety of ways:
-.RS 4
-.IP "\fB\-ac\fR" 4
-.IX Item "-ac"
-omit false conditionals
-.IP "\fB\-ad\fR" 4
-.IX Item "-ad"
-omit debugging directives
-.IP "\fB\-ah\fR" 4
-.IX Item "-ah"
-include high-level source
-.IP "\fB\-al\fR" 4
-.IX Item "-al"
-include assembly
-.IP "\fB\-am\fR" 4
-.IX Item "-am"
-include macro expansions
-.IP "\fB\-an\fR" 4
-.IX Item "-an"
-omit forms processing
-.IP "\fB\-as\fR" 4
-.IX Item "-as"
-include symbols
-.IP "\fB=file\fR" 4
-.IX Item "=file"
-set the name of the listing file
-.RE
-.RS 4
-.Sp
-You may combine these options; for example, use \fB\-aln\fR for assembly
-listing without forms processing.  The \fB=file\fR option, if used, must be
-the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
-.RE
-.IP "\fB\-\-alternate\fR" 4
-.IX Item "--alternate"
-Begin in alternate macro mode, see \fBAltmacro,,\f(CB\*(C`.altmacro\*(C'\fB\fR.
-.IP "\fB\-D\fR" 4
-.IX Item "-D"
-Ignored.  This option is accepted for script compatibility with calls to
-other assemblers.
-.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
-.IX Item "--defsym sym=value"
-Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
-\&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR
-indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
-.IP "\fB\-f\fR" 4
-.IX Item "-f"
-\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
-compiler output).
-.IP "\fB\-g\fR" 4
-.IX Item "-g"
-.PD 0
-.IP "\fB\-\-gen\-debug\fR" 4
-.IX Item "--gen-debug"
-.PD
-Generate debugging information for each assembler source line using whichever
-debug format is preferred by the target.  This currently means either \s-1STABS\s0,
-\&\s-1ECOFF\s0 or \s-1DWARF2\s0.
-.IP "\fB\-\-gstabs\fR" 4
-.IX Item "--gstabs"
-Generate stabs debugging information for each assembler line.  This
-may help debugging assembler code, if the debugger can handle it.
-.IP "\fB\-\-gstabs+\fR" 4
-.IX Item "--gstabs+"
-Generate stabs debugging information for each assembler line, with \s-1GNU\s0
-extensions that probably only gdb can handle, and that could make other
-debuggers crash or refuse to read your program.  This
-may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is
-the location of the current working directory at assembling time.
-.IP "\fB\-\-gdwarf\-2\fR" 4
-.IX Item "--gdwarf-2"
-Generate \s-1DWARF2\s0 debugging information for each assembler line.  This
-may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this
-option is only supported by some targets, not all of them.
-.IP "\fB\-\-help\fR" 4
-.IX Item "--help"
-Print a summary of the command line options and exit.
-.IP "\fB\-\-target\-help\fR" 4
-.IX Item "--target-help"
-Print a summary of all target specific options and exit.
-.IP "\fB\-I\fR \fIdir\fR" 4
-.IX Item "-I dir"
-Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
-.IP "\fB\-J\fR" 4
-.IX Item "-J"
-Don't warn about signed overflow.
-.IP "\fB\-K\fR" 4
-.IX Item "-K"
-Issue warnings when difference tables altered for long displacements.
-.IP "\fB\-L\fR" 4
-.IX Item "-L"
-.PD 0
-.IP "\fB\-\-keep\-locals\fR" 4
-.IX Item "--keep-locals"
-.PD
-Keep (in the symbol table) local symbols.  On traditional a.out systems
-these start with \fBL\fR, but different systems have different local
-label prefixes.
-.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
-.IX Item "--listing-lhs-width=number"
-Set the maximum width, in words, of the output data column for an assembler
-listing to \fInumber\fR.
-.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
-.IX Item "--listing-lhs-width2=number"
-Set the maximum width, in words, of the output data column for continuation
-lines in an assembler listing to \fInumber\fR.
-.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
-.IX Item "--listing-rhs-width=number"
-Set the maximum width of an input source line, as displayed in a listing, to
-\&\fInumber\fR bytes.
-.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
-.IX Item "--listing-cont-lines=number"
-Set the maximum number of lines printed in a listing for a single line of input
-to \fInumber\fR + 1.
-.IP "\fB\-o\fR \fIobjfile\fR" 4
-.IX Item "-o objfile"
-Name the object-file output from \fBas\fR \fIobjfile\fR.
-.IP "\fB\-R\fR" 4
-.IX Item "-R"
-Fold the data section into the text section.
-.Sp
-Set the default size of \s-1GAS\s0's hash tables to a prime number close to
-\&\fInumber\fR.  Increasing this value can reduce the length of time it takes the
-assembler to perform its tasks, at the expense of increasing the assembler's
-memory requirements.  Similarly reducing this value can reduce the memory
-requirements at the expense of speed.
-.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
-.IX Item "--reduce-memory-overheads"
-This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
-assembly processes slower.  Currently this switch is a synonym for
-\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
-.IP "\fB\-\-statistics\fR" 4
-.IX Item "--statistics"
-Print the maximum space (in bytes) and total time (in seconds) used by
-assembly.
-.IP "\fB\-\-strip\-local\-absolute\fR" 4
-.IX Item "--strip-local-absolute"
-Remove local absolute symbols from the outgoing symbol table.
-.IP "\fB\-v\fR" 4
-.IX Item "-v"
-.PD 0
-.IP "\fB\-version\fR" 4
-.IX Item "-version"
-.PD
-Print the \fBas\fR version.
-.IP "\fB\-\-version\fR" 4
-.IX Item "--version"
-Print the \fBas\fR version and exit.
-.IP "\fB\-W\fR" 4
-.IX Item "-W"
-.PD 0
-.IP "\fB\-\-no\-warn\fR" 4
-.IX Item "--no-warn"
-.PD
-Suppress warning messages.
-.IP "\fB\-\-fatal\-warnings\fR" 4
-.IX Item "--fatal-warnings"
-Treat warnings as errors.
-.IP "\fB\-\-warn\fR" 4
-.IX Item "--warn"
-Don't suppress warning messages or treat them as errors.
-.IP "\fB\-w\fR" 4
-.IX Item "-w"
-Ignored.
-.IP "\fB\-x\fR" 4
-.IX Item "-x"
-Ignored.
-.IP "\fB\-Z\fR" 4
-.IX Item "-Z"
-Generate an object file even after errors.
-.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
-.IX Item "-- | files ..."
-Standard input, or source files to assemble.
-.PP
-The following options are available when as is configured for
-an \s-1ARC\s0 processor.
-.IP "\fB\-marc[5|6|7|8]\fR" 4
-.IX Item "-marc[5|6|7|8]"
-This option selects the core processor variant.
-.IP "\fB\-EB | \-EL\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.PP
-The following options are available when as is configured for the \s-1ARM\s0
-processor family.
-.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
-.IX Item "-mcpu=processor[+extension...]"
-Specify which \s-1ARM\s0 processor variant is the target.
-.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
-.IX Item "-march=architecture[+extension...]"
-Specify which \s-1ARM\s0 architecture variant is used by the target.
-.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
-.IX Item "-mfpu=floating-point-format"
-Select which Floating Point architecture is the target.
-.IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
-.IX Item "-mfloat-abi=abi"
-Select which floating point \s-1ABI\s0 is in use.
-.IP "\fB\-mthumb\fR" 4
-.IX Item "-mthumb"
-Enable Thumb only instruction decoding.
-.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
-.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
-Select which procedure calling convention is in use.
-.IP "\fB\-EB | \-EL\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.IP "\fB\-mthumb\-interwork\fR" 4
-.IX Item "-mthumb-interwork"
-Specify that the code has been generated with interworking between Thumb and
-\&\s-1ARM\s0 code in mind.
-.IP "\fB\-k\fR" 4
-.IX Item "-k"
-Specify that \s-1PIC\s0 code has been generated.
-.PP
-See the info pages for documentation of the CRIS-specific options.
-.PP
-The following options are available when as is configured for
-a D10V processor.
-.IP "\fB\-O\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.PP
-The following options are available when as is configured for a D30V
-processor.
-.IP "\fB\-O\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.IP "\fB\-n\fR" 4
-.IX Item "-n"
-Warn when nops are generated.
-.IP "\fB\-N\fR" 4
-.IX Item "-N"
-Warn when a nop after a 32\-bit multiply instruction is generated.
-.PP
-The following options are available when as is configured for the
-Intel 80960 processor.
-.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
-.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
-Specify which variant of the 960 architecture is the target.
-.IP "\fB\-b\fR" 4
-.IX Item "-b"
-Add code to collect statistics about branches taken.
-.IP "\fB\-no\-relax\fR" 4
-.IX Item "-no-relax"
-Do not alter compare-and-branch instructions for long displacements;
-error if necessary.
-.PP
-The following options are available when as is configured for the
-Ubicom \s-1IP2K\s0 series.
-.IP "\fB\-mip2022ext\fR" 4
-.IX Item "-mip2022ext"
-Specifies that the extended \s-1IP2022\s0 instructions are allowed.
-.IP "\fB\-mip2022\fR" 4
-.IX Item "-mip2022"
-Restores the default behaviour, which restricts the permitted instructions to
-just the basic \s-1IP2022\s0 ones.
-.PP
-The following options are available when as is configured for the
-Renesas M32C and M16C processors.
-.IP "\fB\-m32c\fR" 4
-.IX Item "-m32c"
-Assemble M32C instructions.
-.IP "\fB\-m16c\fR" 4
-.IX Item "-m16c"
-Assemble M16C instructions (the default).
-.PP
-The following options are available when as is configured for the
-Renesas M32R (formerly Mitsubishi M32R) series.
-.IP "\fB\-\-m32rx\fR" 4
-.IX Item "--m32rx"
-Specify which processor in the M32R family is the target.  The default
-is normally the M32R, but this option changes it to the M32RX.
-.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
-.IX Item "--warn-explicit-parallel-conflicts or --Wp"
-Produce warning messages when questionable parallel constructs are
-encountered. 
-.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
-.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
-Do not produce warning messages when questionable parallel constructs are 
-encountered. 
-.PP
-The following options are available when as is configured for the
-Motorola 68000 series.
-.IP "\fB\-l\fR" 4
-.IX Item "-l"
-Shorten references to undefined symbols, to one word instead of two.
-.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
-.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
-.PD 0
-.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
-.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
-.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
-.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
-.PD
-Specify what processor in the 68000 family is the target.  The default
-is normally the 68020, but this can be changed at configuration time.
-.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
-.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
-The target machine does (or does not) have a floating-point coprocessor.
-The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
-the basic 68000 is not compatible with the 68881, a combination of the
-two can be specified, since it's possible to do emulation of the
-coprocessor instructions with the main processor.
-.IP "\fB\-m68851 | \-mno\-68851\fR" 4
-.IX Item "-m68851 | -mno-68851"
-The target machine does (or does not) have a memory-management
-unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
-.PP
-For details about the \s-1PDP\-11\s0 machine dependent features options,
-see \fBPDP\-11\-Options\fR.
-.IP "\fB\-mpic | \-mno\-pic\fR" 4
-.IX Item "-mpic | -mno-pic"
-Generate position-independent (or position\-dependent) code.  The
-default is \fB\-mpic\fR.
-.IP "\fB\-mall\fR" 4
-.IX Item "-mall"
-.PD 0
-.IP "\fB\-mall\-extensions\fR" 4
-.IX Item "-mall-extensions"
-.PD
-Enable all instruction set extensions.  This is the default.
-.IP "\fB\-mno\-extensions\fR" 4
-.IX Item "-mno-extensions"
-Disable all instruction set extensions.
-.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
-.IX Item "-mextension | -mno-extension"
-Enable (or disable) a particular instruction set extension.
-.IP "\fB\-m\fR\fIcpu\fR" 4
-.IX Item "-mcpu"
-Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
-disable all other extensions.
-.IP "\fB\-m\fR\fImachine\fR" 4
-.IX Item "-mmachine"
-Enable the instruction set extensions supported by a particular machine
-model, and disable all other extensions.
-.PP
-The following options are available when as is configured for
-a picoJava processor.
-.IP "\fB\-mb\fR" 4
-.IX Item "-mb"
-Generate \*(L"big endian\*(R" format output.
-.IP "\fB\-ml\fR" 4
-.IX Item "-ml"
-Generate \*(L"little endian\*(R" format output.
-.PP
-The following options are available when as is configured for the
-Motorola 68HC11 or 68HC12 series.
-.IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4
-.IX Item "-m68hc11 | -m68hc12 | -m68hcs12"
-Specify what processor is the target.  The default is
-defined by the configuration option when building the assembler.
-.IP "\fB\-mshort\fR" 4
-.IX Item "-mshort"
-Specify to use the 16\-bit integer \s-1ABI\s0.
-.IP "\fB\-mlong\fR" 4
-.IX Item "-mlong"
-Specify to use the 32\-bit integer \s-1ABI\s0.  
-.IP "\fB\-mshort\-double\fR" 4
-.IX Item "-mshort-double"
-Specify to use the 32\-bit double \s-1ABI\s0.  
-.IP "\fB\-mlong\-double\fR" 4
-.IX Item "-mlong-double"
-Specify to use the 64\-bit double \s-1ABI\s0.  
-.IP "\fB\-\-force\-long\-branchs\fR" 4
-.IX Item "--force-long-branchs"
-Relative branches are turned into absolute ones. This concerns
-conditional branches, unconditional branches and branches to a
-sub routine.
-.IP "\fB\-S | \-\-short\-branchs\fR" 4
-.IX Item "-S | --short-branchs"
-Do not turn relative branchs into absolute ones
-when the offset is out of range.
-.IP "\fB\-\-strict\-direct\-mode\fR" 4
-.IX Item "--strict-direct-mode"
-Do not turn the direct addressing mode into extended addressing mode
-when the instruction does not support direct addressing mode.
-.IP "\fB\-\-print\-insn\-syntax\fR" 4
-.IX Item "--print-insn-syntax"
-Print the syntax of instruction in case of error.
-.IP "\fB\-\-print\-opcodes\fR" 4
-.IX Item "--print-opcodes"
-print the list of instructions with syntax and then exit.
-.IP "\fB\-\-generate\-example\fR" 4
-.IX Item "--generate-example"
-print an example of instruction for each possible instruction and then exit.
-This option is only useful for testing \fBas\fR.
-.PP
-The following options are available when \fBas\fR is configured
-for the \s-1SPARC\s0 architecture:
-.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
-.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
-.PD 0
-.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
-.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
-.PD
-Explicitly select a variant of the \s-1SPARC\s0 architecture.
-.Sp
-\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
-\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
-.Sp
-\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
-UltraSPARC extensions.
-.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
-.IX Item "-xarch=v8plus | -xarch=v8plusa"
-For compatibility with the Solaris v9 assembler.  These options are
-equivalent to \-Av8plus and \-Av8plusa, respectively.
-.IP "\fB\-bump\fR" 4
-.IX Item "-bump"
-Warn when the assembler switches to another architecture.
-.PP
-The following options are available when as is configured for the 'c54x
-architecture. 
-.IP "\fB\-mfar\-mode\fR" 4
-.IX Item "-mfar-mode"
-Enable extended addressing mode.  All addresses and relocations will assume
-extended addressing (usually 23 bits).
-.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4
-.IX Item "-mcpu=CPU_VERSION"
-Sets the \s-1CPU\s0 version being compiled for.
-.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4
-.IX Item "-merrors-to-file FILENAME"
-Redirect error output to a file, for broken systems which don't support such
-behaviour in the shell.
-.PP
-The following options are available when as is configured for
-a \s-1MIPS\s0 processor.
-.IP "\fB\-G\fR \fInum\fR" 4
-.IX Item "-G num"
-This option sets the largest size of an object that can be referenced
-implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
-use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Generate \*(L"big endian\*(R" format output.
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Generate \*(L"little endian\*(R" format output.
-.IP "\fB\-mips1\fR" 4
-.IX Item "-mips1"
-.PD 0
-.IP "\fB\-mips2\fR" 4
-.IX Item "-mips2"
-.IP "\fB\-mips3\fR" 4
-.IX Item "-mips3"
-.IP "\fB\-mips4\fR" 4
-.IX Item "-mips4"
-.IP "\fB\-mips5\fR" 4
-.IX Item "-mips5"
-.IP "\fB\-mips32\fR" 4
-.IX Item "-mips32"
-.IP "\fB\-mips32r2\fR" 4
-.IX Item "-mips32r2"
-.IP "\fB\-mips64\fR" 4
-.IX Item "-mips64"
-.IP "\fB\-mips64r2\fR" 4
-.IX Item "-mips64r2"
-.PD
-Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
-\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
-alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
-\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
-\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and
-\&\fB\-mips64r2\fR
-correspond to generic
-\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,
-and \fB\s-1MIPS64\s0 Release 2\fR
-\&\s-1ISA\s0 processors, respectively.
-.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
-.IX Item "-march=CPU"
-Generate code for a particular \s-1MIPS\s0 cpu.
-.IP "\fB\-mtune=\fR\fIcpu\fR" 4
-.IX Item "-mtune=cpu"
-Schedule and tune for a particular \s-1MIPS\s0 cpu.
-.IP "\fB\-mfix7000\fR" 4
-.IX Item "-mfix7000"
-.PD 0
-.IP "\fB\-mno\-fix7000\fR" 4
-.IX Item "-mno-fix7000"
-.PD
-Cause nops to be inserted if the read of the destination register
-of an mfhi or mflo instruction occurs in the following two instructions.
-.IP "\fB\-mdebug\fR" 4
-.IX Item "-mdebug"
-.PD 0
-.IP "\fB\-no\-mdebug\fR" 4
-.IX Item "-no-mdebug"
-.PD
-Cause stabs-style debugging output to go into an ECOFF-style .mdebug
-section instead of the standard \s-1ELF\s0 .stabs sections.
-.IP "\fB\-mpdr\fR" 4
-.IX Item "-mpdr"
-.PD 0
-.IP "\fB\-mno\-pdr\fR" 4
-.IX Item "-mno-pdr"
-.PD
-Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
-.IP "\fB\-mgp32\fR" 4
-.IX Item "-mgp32"
-.PD 0
-.IP "\fB\-mfp32\fR" 4
-.IX Item "-mfp32"
-.PD
-The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
-flags force a certain group of registers to be treated as 32 bits wide at
-all times.  \fB\-mgp32\fR controls the size of general-purpose registers
-and \fB\-mfp32\fR controls the size of floating-point registers.
-.IP "\fB\-mips16\fR" 4
-.IX Item "-mips16"
-.PD 0
-.IP "\fB\-no\-mips16\fR" 4
-.IX Item "-no-mips16"
-.PD
-Generate code for the \s-1MIPS\s0 16 processor.  This is equivalent to putting
-\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR
-turns off this option.
-.IP "\fB\-mips3d\fR" 4
-.IX Item "-mips3d"
-.PD 0
-.IP "\fB\-no\-mips3d\fR" 4
-.IX Item "-no-mips3d"
-.PD
-Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
-\&\fB\-no\-mips3d\fR turns off this option.
-.IP "\fB\-mdmx\fR" 4
-.IX Item "-mdmx"
-.PD 0
-.IP "\fB\-no\-mdmx\fR" 4
-.IX Item "-no-mdmx"
-.PD
-Generate code for the \s-1MDMX\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MDMX\s0 instructions.
-\&\fB\-no\-mdmx\fR turns off this option.
-.IP "\fB\-mdsp\fR" 4
-.IX Item "-mdsp"
-.PD 0
-.IP "\fB\-mno\-dsp\fR" 4
-.IX Item "-mno-dsp"
-.PD
-Generate code for the \s-1DSP\s0 Application Specific Extension.
-This tells the assembler to accept \s-1DSP\s0 instructions.
-\&\fB\-mno\-dsp\fR turns off this option.
-.IP "\fB\-mmt\fR" 4
-.IX Item "-mmt"
-.PD 0
-.IP "\fB\-mno\-mt\fR" 4
-.IX Item "-mno-mt"
-.PD
-Generate code for the \s-1MT\s0 Application Specific Extension.
-This tells the assembler to accept \s-1MT\s0 instructions.
-\&\fB\-mno\-mt\fR turns off this option.
-.IP "\fB\-\-construct\-floats\fR" 4
-.IX Item "--construct-floats"
-.PD 0
-.IP "\fB\-\-no\-construct\-floats\fR" 4
-.IX Item "--no-construct-floats"
-.PD
-The \fB\-\-no\-construct\-floats\fR option disables the construction of
-double width floating point constants by loading the two halves of the
-value into the two single width floating point registers that make up
-the double width register.  By default \fB\-\-construct\-floats\fR is
-selected, allowing construction of these floating point constants.
-.IP "\fB\-\-emulation=\fR\fIname\fR" 4
-.IX Item "--emulation=name"
-This option causes \fBas\fR to emulate \fBas\fR configured
-for some other target, in all respects, including output format (choosing
-between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
-debugging information or store symbol table information, and default
-endianness.  The available configuration names are: \fBmipsecoff\fR,
-\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
-\&\fBmipsbelf\fR.  The first two do not alter the default endianness from that
-of the primary target for which the assembler was configured; the others change
-the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
-in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
-selection in any case.
-.Sp
-This option is currently supported only when the primary target
-\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
-Furthermore, the primary target or others specified with
-\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
-the other format, if both are to be available.  For example, the Irix 5
-configuration includes support for both.
-.Sp
-Eventually, this option will support more configurations, with more
-fine-grained control over the assembler's behavior, and will be supported for
-more processors.
-.IP "\fB\-nocpp\fR" 4
-.IX Item "-nocpp"
-\&\fBas\fR ignores this option.  It is accepted for compatibility with
-the native tools.
-.IP "\fB\-\-trap\fR" 4
-.IX Item "--trap"
-.PD 0
-.IP "\fB\-\-no\-trap\fR" 4
-.IX Item "--no-trap"
-.IP "\fB\-\-break\fR" 4
-.IX Item "--break"
-.IP "\fB\-\-no\-break\fR" 4
-.IX Item "--no-break"
-.PD
-Control how to deal with multiplication overflow and division by zero.
-\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
-(and only work for Instruction Set Architecture level 2 and higher);
-\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
-break exception.
-.IP "\fB\-n\fR" 4
-.IX Item "-n"
-When this option is used, \fBas\fR will issue a warning every
-time it generates a nop instruction from a macro.
-.PP
-The following options are available when as is configured for
-an MCore processor.
-.IP "\fB\-jsri2bsr\fR" 4
-.IX Item "-jsri2bsr"
-.PD 0
-.IP "\fB\-nojsri2bsr\fR" 4
-.IX Item "-nojsri2bsr"
-.PD
-Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.
-The command line option \fB\-nojsri2bsr\fR can be used to disable it.
-.IP "\fB\-sifilter\fR" 4
-.IX Item "-sifilter"
-.PD 0
-.IP "\fB\-nosifilter\fR" 4
-.IX Item "-nosifilter"
-.PD
-Enable or disable the silicon filter behaviour.  By default this is disabled.
-The default can be overridden by the \fB\-sifilter\fR command line option.
-.IP "\fB\-relax\fR" 4
-.IX Item "-relax"
-Alter jump instructions for long displacements.
-.IP "\fB\-mcpu=[210|340]\fR" 4
-.IX Item "-mcpu=[210|340]"
-Select the cpu type on the target hardware.  This controls which instructions
-can be assembled.
-.IP "\fB\-EB\fR" 4
-.IX Item "-EB"
-Assemble for a big endian target.
-.IP "\fB\-EL\fR" 4
-.IX Item "-EL"
-Assemble for a little endian target.
-.PP
-See the info pages for documentation of the MMIX-specific options.
-.PP
-The following options are available when as is configured for
-an Xtensa processor.
-.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
-.IX Item "--text-section-literals | --no-text-section-literals"
-With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
-in the text section.  The default is
-\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
-separate section in the output file.  These options only affect literals
-referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for
-absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
-.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
-.IX Item "--absolute-literals | --no-absolute-literals"
-Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
-or PC-relative addressing.  The default is to assume absolute addressing
-if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing
-option.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.
-.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
-.IX Item "--target-align | --no-target-align"
-Enable or disable automatic alignment to reduce branch penalties at the
-expense of some code density.  The default is \fB\-\-target\-align\fR.
-.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
-.IX Item "--longcalls | --no-longcalls"
-Enable or disable transformation of call instructions to allow calls
-across a greater range of addresses.  The default is
-\&\fB\-\-no\-longcalls\fR.
-.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
-.IX Item "--transform | --no-transform"
-Enable or disable all assembler transformations of Xtensa instructions.
-The default is \fB\-\-transform\fR;
-\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
-instructions must be exactly as specified in the assembly source.
-.PP
-The following options are available when as is configured for
-a Z80 family processor.
-.IP "\fB\-z80\fR" 4
-.IX Item "-z80"
-Assemble for Z80 processor.
-.IP "\fB\-r800\fR" 4
-.IX Item "-r800"
-Assemble for R800 processor.
-.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
-.IX Item "-ignore-undocumented-instructions"
-.PD 0
-.IP "\fB\-Wnud\fR" 4
-.IX Item "-Wnud"
-.PD
-Assemble undocumented Z80 instructions that also work on R800 without warning.
-.IP "\fB\-ignore\-unportable\-instructions\fR" 4
-.IX Item "-ignore-unportable-instructions"
-.PD 0
-.IP "\fB\-Wnup\fR" 4
-.IX Item "-Wnup"
-.PD
-Assemble all undocumented Z80 instructions without warning.
-.IP "\fB\-warn\-undocumented\-instructions\fR" 4
-.IX Item "-warn-undocumented-instructions"
-.PD 0
-.IP "\fB\-Wud\fR" 4
-.IX Item "-Wud"
-.PD
-Issue a warning for undocumented Z80 instructions that also work on R800.
-.IP "\fB\-warn\-unportable\-instructions\fR" 4
-.IX Item "-warn-unportable-instructions"
-.PD 0
-.IP "\fB\-Wup\fR" 4
-.IX Item "-Wup"
-.PD
-Issue a warning for undocumented Z80 instructions that do notwork on R800.  
-.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
-.IX Item "-forbid-undocumented-instructions"
-.PD 0
-.IP "\fB\-Fud\fR" 4
-.IX Item "-Fud"
-.PD
-Treat all undocumented instructions as errors.
-.IP "\fB\-forbid\-unportable\-instructions\fR" 4
-.IX Item "-forbid-unportable-instructions"
-.PD 0
-.IP "\fB\-Fup\fR" 4
-.IX Item "-Fup"
-.PD
-Treat undocumented Z80 intructions that do notwork on R800 as errors.
-.SH "SEE ALSO"
-.IX Header "SEE ALSO"
-\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
-.SH "COPYRIGHT"
-.IX Header "COPYRIGHT"
-Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
-.PP
-Permission is granted to copy, distribute and/or modify this document
-under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
-or any later version published by the Free Software Foundation;
-with no Invariant Sections, with no Front-Cover Texts, and with no
-Back-Cover Texts.  A copy of the license is included in the
-section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
diff --git a/gas/doc/as.info b/gas/doc/as.info
deleted file mode 100644
index adf3ed4558bd..000000000000
--- a/gas/doc/as.info
+++ /dev/null
@@ -1,18352 +0,0 @@
-This is ../.././gas/doc/as.info, produced by makeinfo version 4.8 from
-../.././gas/doc/as.texinfo.
-
-START-INFO-DIR-ENTRY
-* As: (as).                     The GNU assembler.
-* Gas: (as).                    The GNU assembler.
-END-INFO-DIR-ENTRY
-
-   This file documents the GNU Assembler "as".
-
-   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
-Free Software Foundation, Inc.
-
-   Permission is granted to copy, distribute and/or modify this document
-under the terms of the GNU Free Documentation License, Version 1.1 or
-any later version published by the Free Software Foundation; with no
-Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
-Texts.  A copy of the license is included in the section entitled "GNU
-Free Documentation License".
-
-
-File: as.info,  Node: Top,  Next: Overview,  Up: (dir)
-
-Using as
-********
-
-This file is a user guide to the GNU assembler `as' version 2.17.
-
-   This document is distributed under the terms of the GNU Free
-Documentation License.  A copy of the license is included in the
-section entitled "GNU Free Documentation License".
-
-* Menu:
-
-* Overview::                    Overview
-* Invoking::                    Command-Line Options
-* Syntax::                      Syntax
-* Sections::                    Sections and Relocation
-* Symbols::                     Symbols
-* Expressions::                 Expressions
-* Pseudo Ops::                  Assembler Directives
-* Machine Dependencies::        Machine Dependent Features
-* Reporting Bugs::              Reporting Bugs
-* Acknowledgements::            Who Did What
-* GNU Free Documentation License::  GNU Free Documentation License
-* Index::                       Index
-
-
-File: as.info,  Node: Overview,  Next: Invoking,  Prev: Top,  Up: Top
-
-1 Overview
-**********
-
-Here is a brief summary of how to invoke `as'.  For details, *note
-Command-Line Options: Invoking.
-
-     as [-a[cdhlns][=FILE]] [-alternate] [-D]
-      [-defsym SYM=VAL] [-f] [-g] [-gstabs]
-      [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J]
-      [-K] [-L] [-listing-lhs-width=NUM]
-      [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
-      [-listing-cont-lines=NUM] [-keep-locals] [-o
-      OBJFILE] [-R] [-reduce-memory-overheads] [-statistics]
-      [-v] [-version] [-version] [-W] [-warn]
-      [-fatal-warnings] [-w] [-x] [-Z] [@FILE]
-      [-target-help] [TARGET-OPTIONS]
-      [-|FILES ...]
-
-     _Target Alpha options:_
-        [-mCPU]
-        [-mdebug | -no-mdebug]
-        [-relax] [-g] [-GSIZE]
-        [-F] [-32addr]
-
-     _Target ARC options:_
-        [-marc[5|6|7|8]]
-        [-EB|-EL]
-
-     _Target ARM options:_
-        [-mcpu=PROCESSOR[+EXTENSION...]]
-        [-march=ARCHITECTURE[+EXTENSION...]]
-        [-mfpu=FLOATING-POINT-FORMAT]
-        [-mfloat-abi=ABI]
-        [-meabi=VER]
-        [-mthumb]
-        [-EB|-EL]
-        [-mapcs-32|-mapcs-26|-mapcs-float|
-         -mapcs-reentrant]
-        [-mthumb-interwork] [-k]
-
-     _Target CRIS options:_
-        [-underscore | -no-underscore]
-        [-pic] [-N]
-        [-emulation=criself | -emulation=crisaout]
-        [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
-
-     _Target D10V options:_
-        [-O]
-
-     _Target D30V options:_
-        [-O|-n|-N]
-
-     _Target i386 options:_
-        [-32|-64] [-n]
-
-     _Target i960 options:_
-        [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
-         -AKC|-AMC]
-        [-b] [-no-relax]
-
-     _Target IA-64 options:_
-        [-mconstant-gp|-mauto-pic]
-        [-milp32|-milp64|-mlp64|-mp64]
-        [-mle|mbe]
-        [-mtune=itanium1|-mtune=itanium2]
-        [-munwind-check=warning|-munwind-check=error]
-        [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
-        [-x|-xexplicit] [-xauto] [-xdebug]
-
-     _Target IP2K options:_
-        [-mip2022|-mip2022ext]
-
-     _Target M32C options:_
-        [-m32c|-m16c]
-
-     _Target M32R options:_
-        [-m32rx|-[no-]warn-explicit-parallel-conflicts|
-        -W[n]p]
-
-     _Target M680X0 options:_
-        [-l] [-m68000|-m68010|-m68020|...]
-
-     _Target M68HC11 options:_
-        [-m68hc11|-m68hc12|-m68hcs12]
-        [-mshort|-mlong]
-        [-mshort-double|-mlong-double]
-        [-force-long-branchs] [-short-branchs]
-        [-strict-direct-mode] [-print-insn-syntax]
-        [-print-opcodes] [-generate-example]
-
-     _Target MCORE options:_
-        [-jsri2bsr] [-sifilter] [-relax]
-        [-mcpu=[210|340]]
-
-     _Target MIPS options:_
-        [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
-        [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
-        [-non_shared] [-xgot]
-        [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
-        [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
-        [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
-        [-mips64] [-mips64r2]
-        [-construct-floats] [-no-construct-floats]
-        [-trap] [-no-break] [-break] [-no-trap]
-        [-mfix7000] [-mno-fix7000]
-        [-mips16] [-no-mips16]
-        [-mips3d] [-no-mips3d]
-        [-mdmx] [-no-mdmx]
-        [-mdsp] [-mno-dsp]
-        [-mmt] [-mno-mt]
-        [-mdebug] [-no-mdebug]
-        [-mpdr] [-mno-pdr]
-
-     _Target MMIX options:_
-        [-fixed-special-register-names] [-globalize-symbols]
-        [-gnu-syntax] [-relax] [-no-predefined-symbols]
-        [-no-expand] [-no-merge-gregs] [-x]
-        [-linker-allocated-gregs]
-
-     _Target PDP11 options:_
-        [-mpic|-mno-pic] [-mall] [-mno-extensions]
-        [-mEXTENSION|-mno-EXTENSION]
-        [-mCPU] [-mMACHINE]
-
-     _Target picoJava options:_
-        [-mb|-me]
-
-     _Target PowerPC options:_
-        [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
-         -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
-         -mbooke32|-mbooke64]
-        [-mcom|-many|-maltivec] [-memb]
-        [-mregnames|-mno-regnames]
-        [-mrelocatable|-mrelocatable-lib]
-        [-mlittle|-mlittle-endian|-mbig|-mbig-endian]
-        [-msolaris|-mno-solaris]
-
-     _Target SPARC options:_
-        [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
-         -Av8plus|-Av8plusa|-Av9|-Av9a]
-        [-xarch=v8plus|-xarch=v8plusa] [-bump]
-        [-32|-64]
-
-     _Target TIC54X options:_
-      [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
-      [-merrors-to-file <FILENAME>|-me <FILENAME>]
-
-
-     _Target Z80 options:_
-       [-z80] [-r800]
-       [ -ignore-undocumented-instructions] [-Wnud]
-       [ -ignore-unportable-instructions] [-Wnup]
-       [ -warn-undocumented-instructions] [-Wud]
-       [ -warn-unportable-instructions] [-Wup]
-       [ -forbid-undocumented-instructions] [-Fud]
-       [ -forbid-unportable-instructions] [-Fup]
-
-
-     _Target Xtensa options:_
-      [-[no-]text-section-literals] [-[no-]absolute-literals]
-      [-[no-]target-align] [-[no-]longcalls]
-      [-[no-]transform]
-      [-rename-section OLDNAME=NEWNAME]
-
-`@FILE'
-     Read command-line options from FILE.  The options read are
-     inserted in place of the original @FILE option.  If FILE does not
-     exist, or cannot be read, then the option will be treated
-     literally, and not removed.
-
-     Options in FILE are separated by whitespace.  A whitespace
-     character may be included in an option by surrounding the entire
-     option in either single or double quotes.  Any character
-     (including a backslash) may be included by prefixing the character
-     to be included with a backslash.  The FILE may itself contain
-     additional @FILE options; any such options will be processed
-     recursively.
-
-`-a[cdhlmns]'
-     Turn on listings, in any of a variety of ways:
-
-    `-ac'
-          omit false conditionals
-
-    `-ad'
-          omit debugging directives
-
-    `-ah'
-          include high-level source
-
-    `-al'
-          include assembly
-
-    `-am'
-          include macro expansions
-
-    `-an'
-          omit forms processing
-
-    `-as'
-          include symbols
-
-    `=file'
-          set the name of the listing file
-
-     You may combine these options; for example, use `-aln' for assembly
-     listing without forms processing.  The `=file' option, if used,
-     must be the last one.  By itself, `-a' defaults to `-ahls'.
-
-`--alternate'
-     Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
-
-`-D'
-     Ignored.  This option is accepted for script compatibility with
-     calls to other assemblers.
-
-`--defsym SYM=VALUE'
-     Define the symbol SYM to be VALUE before assembling the input file.
-     VALUE must be an integer constant.  As in C, a leading `0x'
-     indicates a hexadecimal value, and a leading `0' indicates an
-     octal value.
-
-`-f'
-     "fast"--skip whitespace and comment preprocessing (assume source is
-     compiler output).
-
-`-g'
-`--gen-debug'
-     Generate debugging information for each assembler source line
-     using whichever debug format is preferred by the target.  This
-     currently means either STABS, ECOFF or DWARF2.
-
-`--gstabs'
-     Generate stabs debugging information for each assembler line.  This
-     may help debugging assembler code, if the debugger can handle it.
-
-`--gstabs+'
-     Generate stabs debugging information for each assembler line, with
-     GNU extensions that probably only gdb can handle, and that could
-     make other debuggers crash or refuse to read your program.  This
-     may help debugging assembler code.  Currently the only GNU
-     extension is the location of the current working directory at
-     assembling time.
-
-`--gdwarf-2'
-     Generate DWARF2 debugging information for each assembler line.
-     This may help debugging assembler code, if the debugger can handle
-     it.  Note--this option is only supported by some targets, not all
-     of them.
-
-`--help'
-     Print a summary of the command line options and exit.
-
-`--target-help'
-     Print a summary of all target specific options and exit.
-
-`-I DIR'
-     Add directory DIR to the search list for `.include' directives.
-
-`-J'
-     Don't warn about signed overflow.
-
-`-K'
-     Issue warnings when difference tables altered for long
-     displacements.
-
-`-L'
-`--keep-locals'
-     Keep (in the symbol table) local symbols.  On traditional a.out
-     systems these start with `L', but different systems have different
-     local label prefixes.
-
-`--listing-lhs-width=NUMBER'
-     Set the maximum width, in words, of the output data column for an
-     assembler listing to NUMBER.
-
-`--listing-lhs-width2=NUMBER'
-     Set the maximum width, in words, of the output data column for
-     continuation lines in an assembler listing to NUMBER.
-
-`--listing-rhs-width=NUMBER'
-     Set the maximum width of an input source line, as displayed in a
-     listing, to NUMBER bytes.
-
-`--listing-cont-lines=NUMBER'
-     Set the maximum number of lines printed in a listing for a single
-     line of input to NUMBER + 1.
-
-`-o OBJFILE'
-     Name the object-file output from `as' OBJFILE.
-
-`-R'
-     Fold the data section into the text section.
-
-     Set the default size of GAS's hash tables to a prime number close
-     to NUMBER.  Increasing this value can reduce the length of time it
-     takes the assembler to perform its tasks, at the expense of
-     increasing the assembler's memory requirements.  Similarly
-     reducing this value can reduce the memory requirements at the
-     expense of speed.
-
-`--reduce-memory-overheads'
-     This option reduces GAS's memory requirements, at the expense of
-     making the assembly processes slower.  Currently this switch is a
-     synonym for `--hash-size=4051', but in the future it may have
-     other effects as well.
-
-`--statistics'
-     Print the maximum space (in bytes) and total time (in seconds)
-     used by assembly.
-
-`--strip-local-absolute'
-     Remove local absolute symbols from the outgoing symbol table.
-
-`-v'
-`-version'
-     Print the `as' version.
-
-`--version'
-     Print the `as' version and exit.
-
-`-W'
-`--no-warn'
-     Suppress warning messages.
-
-`--fatal-warnings'
-     Treat warnings as errors.
-
-`--warn'
-     Don't suppress warning messages or treat them as errors.
-
-`-w'
-     Ignored.
-
-`-x'
-     Ignored.
-
-`-Z'
-     Generate an object file even after errors.
-
-`-- | FILES ...'
-     Standard input, or source files to assemble.
-
-
-   The following options are available when as is configured for an ARC
-processor.
-
-`-marc[5|6|7|8]'
-     This option selects the core processor variant.
-
-`-EB | -EL'
-     Select either big-endian (-EB) or little-endian (-EL) output.
-
-   The following options are available when as is configured for the ARM
-processor family.
-
-`-mcpu=PROCESSOR[+EXTENSION...]'
-     Specify which ARM processor variant is the target.
-
-`-march=ARCHITECTURE[+EXTENSION...]'
-     Specify which ARM architecture variant is used by the target.
-
-`-mfpu=FLOATING-POINT-FORMAT'
-     Select which Floating Point architecture is the target.
-
-`-mfloat-abi=ABI'
-     Select which floating point ABI is in use.
-
-`-mthumb'
-     Enable Thumb only instruction decoding.
-
-`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
-     Select which procedure calling convention is in use.
-
-`-EB | -EL'
-     Select either big-endian (-EB) or little-endian (-EL) output.
-
-`-mthumb-interwork'
-     Specify that the code has been generated with interworking between
-     Thumb and ARM code in mind.
-
-`-k'
-     Specify that PIC code has been generated.
-
-   See the info pages for documentation of the CRIS-specific options.
-
-   The following options are available when as is configured for a D10V
-processor.
-`-O'
-     Optimize output by parallelizing instructions.
-
-   The following options are available when as is configured for a D30V
-processor.
-`-O'
-     Optimize output by parallelizing instructions.
-
-`-n'
-     Warn when nops are generated.
-
-`-N'
-     Warn when a nop after a 32-bit multiply instruction is generated.
-
-   The following options are available when as is configured for the
-Intel 80960 processor.
-
-`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
-     Specify which variant of the 960 architecture is the target.
-
-`-b'
-     Add code to collect statistics about branches taken.
-
-`-no-relax'
-     Do not alter compare-and-branch instructions for long
-     displacements; error if necessary.
-
-
-   The following options are available when as is configured for the
-Ubicom IP2K series.
-
-`-mip2022ext'
-     Specifies that the extended IP2022 instructions are allowed.
-
-`-mip2022'
-     Restores the default behaviour, which restricts the permitted
-     instructions to just the basic IP2022 ones.
-
-
-   The following options are available when as is configured for the
-Renesas M32C and M16C processors.
-
-`-m32c'
-     Assemble M32C instructions.
-
-`-m16c'
-     Assemble M16C instructions (the default).
-
-
-   The following options are available when as is configured for the
-Renesas M32R (formerly Mitsubishi M32R) series.
-
-`--m32rx'
-     Specify which processor in the M32R family is the target.  The
-     default is normally the M32R, but this option changes it to the
-     M32RX.
-
-`--warn-explicit-parallel-conflicts or --Wp'
-     Produce warning messages when questionable parallel constructs are
-     encountered.
-
-`--no-warn-explicit-parallel-conflicts or --Wnp'
-     Do not produce warning messages when questionable parallel
-     constructs are encountered.
-
-
-   The following options are available when as is configured for the
-Motorola 68000 series.
-
-`-l'
-     Shorten references to undefined symbols, to one word instead of
-     two.
-
-`-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
-`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
-`| -m68333 | -m68340 | -mcpu32 | -m5200'
-     Specify what processor in the 68000 family is the target.  The
-     default is normally the 68020, but this can be changed at
-     configuration time.
-
-`-m68881 | -m68882 | -mno-68881 | -mno-68882'
-     The target machine does (or does not) have a floating-point
-     coprocessor.  The default is to assume a coprocessor for 68020,
-     68030, and cpu32.  Although the basic 68000 is not compatible with
-     the 68881, a combination of the two can be specified, since it's
-     possible to do emulation of the coprocessor instructions with the
-     main processor.
-
-`-m68851 | -mno-68851'
-     The target machine does (or does not) have a memory-management
-     unit coprocessor.  The default is to assume an MMU for 68020 and
-     up.
-
-
-   For details about the PDP-11 machine dependent features options, see
-*Note PDP-11-Options::.
-
-`-mpic | -mno-pic'
-     Generate position-independent (or position-dependent) code.  The
-     default is `-mpic'.
-
-`-mall'
-`-mall-extensions'
-     Enable all instruction set extensions.  This is the default.
-
-`-mno-extensions'
-     Disable all instruction set extensions.
-
-`-mEXTENSION | -mno-EXTENSION'
-     Enable (or disable) a particular instruction set extension.
-
-`-mCPU'
-     Enable the instruction set extensions supported by a particular
-     CPU, and disable all other extensions.
-
-`-mMACHINE'
-     Enable the instruction set extensions supported by a particular
-     machine model, and disable all other extensions.
-
-   The following options are available when as is configured for a
-picoJava processor.
-
-`-mb'
-     Generate "big endian" format output.
-
-`-ml'
-     Generate "little endian" format output.
-
-
-   The following options are available when as is configured for the
-Motorola 68HC11 or 68HC12 series.
-
-`-m68hc11 | -m68hc12 | -m68hcs12'
-     Specify what processor is the target.  The default is defined by
-     the configuration option when building the assembler.
-
-`-mshort'
-     Specify to use the 16-bit integer ABI.
-
-`-mlong'
-     Specify to use the 32-bit integer ABI.
-
-`-mshort-double'
-     Specify to use the 32-bit double ABI.
-
-`-mlong-double'
-     Specify to use the 64-bit double ABI.
-
-`--force-long-branchs'
-     Relative branches are turned into absolute ones. This concerns
-     conditional branches, unconditional branches and branches to a sub
-     routine.
-
-`-S | --short-branchs'
-     Do not turn relative branchs into absolute ones when the offset is
-     out of range.
-
-`--strict-direct-mode'
-     Do not turn the direct addressing mode into extended addressing
-     mode when the instruction does not support direct addressing mode.
-
-`--print-insn-syntax'
-     Print the syntax of instruction in case of error.
-
-`--print-opcodes'
-     print the list of instructions with syntax and then exit.
-
-`--generate-example'
-     print an example of instruction for each possible instruction and
-     then exit.  This option is only useful for testing `as'.
-
-
-   The following options are available when `as' is configured for the
-SPARC architecture:
-
-`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
-`-Av8plus | -Av8plusa | -Av9 | -Av9a'
-     Explicitly select a variant of the SPARC architecture.
-
-     `-Av8plus' and `-Av8plusa' select a 32 bit environment.  `-Av9'
-     and `-Av9a' select a 64 bit environment.
-
-     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
-     UltraSPARC extensions.
-
-`-xarch=v8plus | -xarch=v8plusa'
-     For compatibility with the Solaris v9 assembler.  These options are
-     equivalent to -Av8plus and -Av8plusa, respectively.
-
-`-bump'
-     Warn when the assembler switches to another architecture.
-
-   The following options are available when as is configured for the
-'c54x architecture.
-
-`-mfar-mode'
-     Enable extended addressing mode.  All addresses and relocations
-     will assume extended addressing (usually 23 bits).
-
-`-mcpu=CPU_VERSION'
-     Sets the CPU version being compiled for.
-
-`-merrors-to-file FILENAME'
-     Redirect error output to a file, for broken systems which don't
-     support such behaviour in the shell.
-
-   The following options are available when as is configured for a MIPS
-processor.
-
-`-G NUM'
-     This option sets the largest size of an object that can be
-     referenced implicitly with the `gp' register.  It is only accepted
-     for targets that use ECOFF format, such as a DECstation running
-     Ultrix.  The default value is 8.
-
-`-EB'
-     Generate "big endian" format output.
-
-`-EL'
-     Generate "little endian" format output.
-
-`-mips1'
-`-mips2'
-`-mips3'
-`-mips4'
-`-mips5'
-`-mips32'
-`-mips32r2'
-`-mips64'
-`-mips64r2'
-     Generate code for a particular MIPS Instruction Set Architecture
-     level.  `-mips1' is an alias for `-march=r3000', `-mips2' is an
-     alias for `-march=r6000', `-mips3' is an alias for `-march=r4000'
-     and `-mips4' is an alias for `-march=r8000'.  `-mips5', `-mips32',
-     `-mips32r2', `-mips64', and `-mips64r2' correspond to generic
-     `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64
-     Release 2' ISA processors, respectively.
-
-`-march=CPU'
-     Generate code for a particular MIPS cpu.
-
-`-mtune=CPU'
-     Schedule and tune for a particular MIPS cpu.
-
-`-mfix7000'
-`-mno-fix7000'
-     Cause nops to be inserted if the read of the destination register
-     of an mfhi or mflo instruction occurs in the following two
-     instructions.
-
-`-mdebug'
-`-no-mdebug'
-     Cause stabs-style debugging output to go into an ECOFF-style
-     .mdebug section instead of the standard ELF .stabs sections.
-
-`-mpdr'
-`-mno-pdr'
-     Control generation of `.pdr' sections.
-
-`-mgp32'
-`-mfp32'
-     The register sizes are normally inferred from the ISA and ABI, but
-     these flags force a certain group of registers to be treated as 32
-     bits wide at all times.  `-mgp32' controls the size of
-     general-purpose registers and `-mfp32' controls the size of
-     floating-point registers.
-
-`-mips16'
-`-no-mips16'
-     Generate code for the MIPS 16 processor.  This is equivalent to
-     putting `.set mips16' at the start of the assembly file.
-     `-no-mips16' turns off this option.
-
-`-mips3d'
-`-no-mips3d'
-     Generate code for the MIPS-3D Application Specific Extension.
-     This tells the assembler to accept MIPS-3D instructions.
-     `-no-mips3d' turns off this option.
-
-`-mdmx'
-`-no-mdmx'
-     Generate code for the MDMX Application Specific Extension.  This
-     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
-     off this option.
-
-`-mdsp'
-`-mno-dsp'
-     Generate code for the DSP Application Specific Extension.  This
-     tells the assembler to accept DSP instructions.  `-mno-dsp' turns
-     off this option.
-
-`-mmt'
-`-mno-mt'
-     Generate code for the MT Application Specific Extension.  This
-     tells the assembler to accept MT instructions.  `-mno-mt' turns
-     off this option.
-
-`--construct-floats'
-`--no-construct-floats'
-     The `--no-construct-floats' option disables the construction of
-     double width floating point constants by loading the two halves of
-     the value into the two single width floating point registers that
-     make up the double width register.  By default
-     `--construct-floats' is selected, allowing construction of these
-     floating point constants.
-
-`--emulation=NAME'
-     This option causes `as' to emulate `as' configured for some other
-     target, in all respects, including output format (choosing between
-     ELF and ECOFF only), handling of pseudo-opcodes which may generate
-     debugging information or store symbol table information, and
-     default endianness.  The available configuration names are:
-     `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf',
-     `mipsbelf'.  The first two do not alter the default endianness
-     from that of the primary target for which the assembler was
-     configured; the others change the default to little- or big-endian
-     as indicated by the `b' or `l' in the name.  Using `-EB' or `-EL'
-     will override the endianness selection in any case.
-
-     This option is currently supported only when the primary target
-     `as' is configured for is a MIPS ELF or ECOFF target.
-     Furthermore, the primary target or others specified with
-     `--enable-targets=...' at configuration time must include support
-     for the other format, if both are to be available.  For example,
-     the Irix 5 configuration includes support for both.
-
-     Eventually, this option will support more configurations, with more
-     fine-grained control over the assembler's behavior, and will be
-     supported for more processors.
-
-`-nocpp'
-     `as' ignores this option.  It is accepted for compatibility with
-     the native tools.
-
-`--trap'
-`--no-trap'
-`--break'
-`--no-break'
-     Control how to deal with multiplication overflow and division by
-     zero.  `--trap' or `--no-break' (which are synonyms) take a trap
-     exception (and only work for Instruction Set Architecture level 2
-     and higher); `--break' or `--no-trap' (also synonyms, and the
-     default) take a break exception.
-
-`-n'
-     When this option is used, `as' will issue a warning every time it
-     generates a nop instruction from a macro.
-
-   The following options are available when as is configured for an
-MCore processor.
-
-`-jsri2bsr'
-`-nojsri2bsr'
-     Enable or disable the JSRI to BSR transformation.  By default this
-     is enabled.  The command line option `-nojsri2bsr' can be used to
-     disable it.
-
-`-sifilter'
-`-nosifilter'
-     Enable or disable the silicon filter behaviour.  By default this
-     is disabled.  The default can be overridden by the `-sifilter'
-     command line option.
-
-`-relax'
-     Alter jump instructions for long displacements.
-
-`-mcpu=[210|340]'
-     Select the cpu type on the target hardware.  This controls which
-     instructions can be assembled.
-
-`-EB'
-     Assemble for a big endian target.
-
-`-EL'
-     Assemble for a little endian target.
-
-
-   See the info pages for documentation of the MMIX-specific options.
-
-   The following options are available when as is configured for an
-Xtensa processor.
-
-`--text-section-literals | --no-text-section-literals'
-     With `--text-section-literals', literal pools are interspersed in
-     the text section.  The default is `--no-text-section-literals',
-     which places literals in a separate section in the output file.
-     These options only affect literals referenced via PC-relative
-     `L32R' instructions; literals for absolute mode `L32R'
-     instructions are handled separately.
-
-`--absolute-literals | --no-absolute-literals'
-     Indicate to the assembler whether `L32R' instructions use absolute
-     or PC-relative addressing.  The default is to assume absolute
-     addressing if the Xtensa processor includes the absolute `L32R'
-     addressing option.  Otherwise, only the PC-relative `L32R' mode
-     can be used.
-
-`--target-align | --no-target-align'
-     Enable or disable automatic alignment to reduce branch penalties
-     at the expense of some code density.  The default is
-     `--target-align'.
-
-`--longcalls | --no-longcalls'
-     Enable or disable transformation of call instructions to allow
-     calls across a greater range of addresses.  The default is
-     `--no-longcalls'.
-
-`--transform | --no-transform'
-     Enable or disable all assembler transformations of Xtensa
-     instructions.  The default is `--transform'; `--no-transform'
-     should be used only in the rare cases when the instructions must
-     be exactly as specified in the assembly source.
-
-   The following options are available when as is configured for a Z80
-family processor.
-`-z80'
-     Assemble for Z80 processor.
-
-`-r800'
-     Assemble for R800 processor.
-
-`-ignore-undocumented-instructions'
-`-Wnud'
-     Assemble undocumented Z80 instructions that also work on R800
-     without warning.
-
-`-ignore-unportable-instructions'
-`-Wnup'
-     Assemble all undocumented Z80 instructions without warning.
-
-`-warn-undocumented-instructions'
-`-Wud'
-     Issue a warning for undocumented Z80 instructions that also work
-     on R800.
-
-`-warn-unportable-instructions'
-`-Wup'
-     Issue a warning for undocumented Z80 instructions that do notwork
-     on R800.
-
-`-forbid-undocumented-instructions'
-`-Fud'
-     Treat all undocumented instructions as errors.
-
-`-forbid-unportable-instructions'
-`-Fup'
-     Treat undocumented Z80 intructions that do notwork on R800 as
-     errors.
-
-* Menu:
-
-* Manual::                      Structure of this Manual
-* GNU Assembler::               The GNU Assembler
-* Object Formats::              Object File Formats
-* Command Line::                Command Line
-* Input Files::                 Input Files
-* Object::                      Output (Object) File
-* Errors::                      Error and Warning Messages
-
-
-File: as.info,  Node: Manual,  Next: GNU Assembler,  Up: Overview
-
-1.1 Structure of this Manual
-============================
-
-This manual is intended to describe what you need to know to use GNU
-`as'.  We cover the syntax expected in source files, including notation
-for symbols, constants, and expressions; the directives that `as'
-understands; and of course how to invoke `as'.
-
-   This manual also describes some of the machine-dependent features of
-various flavors of the assembler.
-
-   On the other hand, this manual is _not_ intended as an introduction
-to programming in assembly language--let alone programming in general!
-In a similar vein, we make no attempt to introduce the machine
-architecture; we do _not_ describe the instruction set, standard
-mnemonics, registers or addressing modes that are standard to a
-particular architecture.  You may want to consult the manufacturer's
-machine architecture manual for this information.
-
-
-File: as.info,  Node: GNU Assembler,  Next: Object Formats,  Prev: Manual,  Up: Overview
-
-1.2 The GNU Assembler
-=====================
-
-GNU `as' is really a family of assemblers.  If you use (or have used)
-the GNU assembler on one architecture, you should find a fairly similar
-environment when you use it on another architecture.  Each version has
-much in common with the others, including object file formats, most
-assembler directives (often called "pseudo-ops") and assembler syntax.
-
-   `as' is primarily intended to assemble the output of the GNU C
-compiler `gcc' for use by the linker `ld'.  Nevertheless, we've tried
-to make `as' assemble correctly everything that other assemblers for
-the same machine would assemble.  Any exceptions are documented
-explicitly (*note Machine Dependencies::).  This doesn't mean `as'
-always uses the same syntax as another assembler for the same
-architecture; for example, we know of several incompatible versions of
-680x0 assembly language syntax.
-
-   Unlike older assemblers, `as' is designed to assemble a source
-program in one pass of the source file.  This has a subtle impact on the
-`.org' directive (*note `.org': Org.).
-
-
-File: as.info,  Node: Object Formats,  Next: Command Line,  Prev: GNU Assembler,  Up: Overview
-
-1.3 Object File Formats
-=======================
-
-The GNU assembler can be configured to produce several alternative
-object file formats.  For the most part, this does not affect how you
-write assembly language programs; but directives for debugging symbols
-are typically different in different file formats.  *Note Symbol
-Attributes: Symbol Attributes.
-
-
-File: as.info,  Node: Command Line,  Next: Input Files,  Prev: Object Formats,  Up: Overview
-
-1.4 Command Line
-================
-
-After the program name `as', the command line may contain options and
-file names.  Options may appear in any order, and may be before, after,
-or between file names.  The order of file names is significant.
-
-   `--' (two hyphens) by itself names the standard input file
-explicitly, as one of the files for `as' to assemble.
-
-   Except for `--' any command line argument that begins with a hyphen
-(`-') is an option.  Each option changes the behavior of `as'.  No
-option changes the way another option works.  An option is a `-'
-followed by one or more letters; the case of the letter is important.
-All options are optional.
-
-   Some options expect exactly one file name to follow them.  The file
-name may either immediately follow the option's letter (compatible with
-older assemblers) or it may be the next command argument (GNU
-standard).  These two command lines are equivalent:
-
-     as -o my-object-file.o mumble.s
-     as -omy-object-file.o mumble.s
-
-
-File: as.info,  Node: Input Files,  Next: Object,  Prev: Command Line,  Up: Overview
-
-1.5 Input Files
-===============
-
-We use the phrase "source program", abbreviated "source", to describe
-the program input to one run of `as'.  The program may be in one or
-more files; how the source is partitioned into files doesn't change the
-meaning of the source.
-
-   The source program is a concatenation of the text in all the files,
-in the order specified.
-
-   Each time you run `as' it assembles exactly one source program.  The
-source program is made up of one or more files.  (The standard input is
-also a file.)
-
-   You give `as' a command line that has zero or more input file names.
-The input files are read (from left file name to right).  A command
-line argument (in any position) that has no special meaning is taken to
-be an input file name.
-
-   If you give `as' no file names it attempts to read one input file
-from the `as' standard input, which is normally your terminal.  You may
-have to type <ctl-D> to tell `as' there is no more program to assemble.
-
-   Use `--' if you need to explicitly name the standard input file in
-your command line.
-
-   If the source is empty, `as' produces a small, empty object file.
-
-Filenames and Line-numbers
---------------------------
-
-There are two ways of locating a line in the input file (or files) and
-either may be used in reporting error messages.  One way refers to a
-line number in a physical file; the other refers to a line number in a
-"logical" file.  *Note Error and Warning Messages: Errors.
-
-   "Physical files" are those files named in the command line given to
-`as'.
-
-   "Logical files" are simply names declared explicitly by assembler
-directives; they bear no relation to physical files.  Logical file
-names help error messages reflect the original source file, when `as'
-source is itself synthesized from other files.  `as' understands the
-`#' directives emitted by the `gcc' preprocessor.  See also *Note
-`.file': File.
-
-
-File: as.info,  Node: Object,  Next: Errors,  Prev: Input Files,  Up: Overview
-
-1.6 Output (Object) File
-========================
-
-Every time you run `as' it produces an output file, which is your
-assembly language program translated into numbers.  This file is the
-object file.  Its default name is `a.out'.  You can give it another
-name by using the `-o' option.  Conventionally, object file names end
-with `.o'.  The default name is used for historical reasons: older
-assemblers were capable of assembling self-contained programs directly
-into a runnable program.  (For some formats, this isn't currently
-possible, but it can be done for the `a.out' format.)
-
-   The object file is meant for input to the linker `ld'.  It contains
-assembled program code, information to help `ld' integrate the
-assembled program into a runnable file, and (optionally) symbolic
-information for the debugger.
-
-
-File: as.info,  Node: Errors,  Prev: Object,  Up: Overview
-
-1.7 Error and Warning Messages
-==============================
-
-`as' may write warnings and error messages to the standard error file
-(usually your terminal).  This should not happen when  a compiler runs
-`as' automatically.  Warnings report an assumption made so that `as'
-could keep assembling a flawed program; errors report a grave problem
-that stops the assembly.
-
-   Warning messages have the format
-
-     file_name:NNN:Warning Message Text
-
-(where NNN is a line number).  If a logical file name has been given
-(*note `.file': File.) it is used for the filename, otherwise the name
-of the current input file is used.  If a logical line number was given
-(*note `.line': Line.)  then it is used to calculate the number printed,
-otherwise the actual line in the current source file is printed.  The
-message text is intended to be self explanatory (in the grand Unix
-tradition).
-
-   Error messages have the format
-     file_name:NNN:FATAL:Error Message Text
-   The file name and line number are derived as for warning messages.
-The actual message text may be rather less explanatory because many of
-them aren't supposed to happen.
-
-
-File: as.info,  Node: Invoking,  Next: Syntax,  Prev: Overview,  Up: Top
-
-2 Command-Line Options
-**********************
-
-This chapter describes command-line options available in _all_ versions
-of the GNU assembler; *note Machine Dependencies::, for options specific
-to particular machine architectures.
-
-   If you are invoking `as' via the GNU C compiler, you can use the
-`-Wa' option to pass arguments through to the assembler.  The assembler
-arguments must be separated from each other (and the `-Wa') by commas.
-For example:
-
-     gcc -c -g -O -Wa,-alh,-L file.c
-
-This passes two options to the assembler: `-alh' (emit a listing to
-standard output with high-level and assembly source) and `-L' (retain
-local symbols in the symbol table).
-
-   Usually you do not need to use this `-Wa' mechanism, since many
-compiler command-line options are automatically passed to the assembler
-by the compiler.  (You can call the GNU compiler driver with the `-v'
-option to see precisely what options it passes to each compilation
-pass, including the assembler.)
-
-* Menu:
-
-* a::             -a[cdhlns] enable listings
-* alternate::     --alternate enable alternate macro syntax
-* D::             -D for compatibility
-* f::             -f to work faster
-* I::             -I for .include search path
-
-* K::             -K for difference tables
-
-* L::             -L to retain local labels
-* listing::       --listing-XXX to configure listing output
-* M::		  -M or --mri to assemble in MRI compatibility mode
-* MD::            --MD for dependency tracking
-* o::             -o to name the object file
-* R::             -R to join data and text sections
-* statistics::    --statistics to see statistics about assembly
-* traditional-format:: --traditional-format for compatible output
-* v::             -v to announce version
-* W::             -W, --no-warn, --warn, --fatal-warnings to control warnings
-* Z::             -Z to make object file even after errors
-
-
-File: as.info,  Node: a,  Next: alternate,  Up: Invoking
-
-2.1 Enable Listings: `-a[cdhlns]'
-=================================
-
-These options enable listing output from the assembler.  By itself,
-`-a' requests high-level, assembly, and symbols listing.  You can use
-other letters to select specific options for the list: `-ah' requests a
-high-level language listing, `-al' requests an output-program assembly
-listing, and `-as' requests a symbol table listing.  High-level
-listings require that a compiler debugging option like `-g' be used,
-and that assembly listings (`-al') be requested also.
-
-   Use the `-ac' option to omit false conditionals from a listing.  Any
-lines which are not assembled because of a false `.if' (or `.ifdef', or
-any other conditional), or a true `.if' followed by an `.else', will be
-omitted from the listing.
-
-   Use the `-ad' option to omit debugging directives from the listing.
-
-   Once you have specified one of these options, you can further control
-listing output and its appearance using the directives `.list',
-`.nolist', `.psize', `.eject', `.title', and `.sbttl'.  The `-an'
-option turns off all forms processing.  If you do not request listing
-output with one of the `-a' options, the listing-control directives
-have no effect.
-
-   The letters after `-a' may be combined into one option, _e.g._,
-`-aln'.
-
-   Note if the assembler source is coming from the standard input (eg
-because it is being created by `gcc' and the `-pipe' command line switch
-is being used) then the listing will not contain any comments or
-preprocessor directives.  This is because the listing code buffers
-input source lines from stdin only after they have been preprocessed by
-the assembler.  This reduces memory usage and makes the code more
-efficient.
-
-
-File: as.info,  Node: alternate,  Next: D,  Prev: a,  Up: Invoking
-
-2.2 `--alternate'
-=================
-
-Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
-
-
-File: as.info,  Node: D,  Next: f,  Prev: alternate,  Up: Invoking
-
-2.3 `-D'
-========
-
-This option has no effect whatsoever, but it is accepted to make it more
-likely that scripts written for other assemblers also work with `as'.
-
-
-File: as.info,  Node: f,  Next: I,  Prev: D,  Up: Invoking
-
-2.4 Work Faster: `-f'
-=====================
-
-`-f' should only be used when assembling programs written by a
-(trusted) compiler.  `-f' stops the assembler from doing whitespace and
-comment preprocessing on the input file(s) before assembling them.
-*Note Preprocessing: Preprocessing.
-
-     _Warning:_ if you use `-f' when the files actually need to be
-     preprocessed (if they contain comments, for example), `as' does
-     not work correctly.
-
-
-File: as.info,  Node: I,  Next: K,  Prev: f,  Up: Invoking
-
-2.5 `.include' Search Path: `-I' PATH
-=====================================
-
-Use this option to add a PATH to the list of directories `as' searches
-for files specified in `.include' directives (*note `.include':
-Include.).  You may use `-I' as many times as necessary to include a
-variety of paths.  The current working directory is always searched
-first; after that, `as' searches any `-I' directories in the same order
-as they were specified (left to right) on the command line.
-
-
-File: as.info,  Node: K,  Next: L,  Prev: I,  Up: Invoking
-
-2.6 Difference Tables: `-K'
-===========================
-
-`as' sometimes alters the code emitted for directives of the form
-`.word SYM1-SYM2'; *note `.word': Word.  You can use the `-K' option if
-you want a warning issued when this is done.
-
-
-File: as.info,  Node: L,  Next: listing,  Prev: K,  Up: Invoking
-
-2.7 Include Local Labels: `-L'
-==============================
-
-Labels beginning with `L' (upper case only) are called "local labels".
-*Note Symbol Names::.  Normally you do not see such labels when
-debugging, because they are intended for the use of programs (like
-compilers) that compose assembler programs, not for your notice.
-Normally both `as' and `ld' discard such labels, so you do not normally
-debug with them.
-
-   This option tells `as' to retain those `L...' symbols in the object
-file.  Usually if you do this you also tell the linker `ld' to preserve
-symbols whose names begin with `L'.
-
-   By default, a local label is any label beginning with `L', but each
-target is allowed to redefine the local label prefix.  On the HPPA
-local labels begin with `L$'.
-
-
-File: as.info,  Node: listing,  Next: M,  Prev: L,  Up: Invoking
-
-2.8 Configuring listing output: `--listing'
-===========================================
-
-The listing feature of the assembler can be enabled via the command
-line switch `-a' (*note a::).  This feature combines the input source
-file(s) with a hex dump of the corresponding locations in the output
-object file, and displays them as a listing file.  The format of this
-listing can be controlled by pseudo ops inside the assembler source
-(*note List:: *note Title:: *note Sbttl:: *note Psize:: *note Eject::)
-and also by the following switches:
-
-`--listing-lhs-width=`number''
-     Sets the maximum width, in words, of the first line of the hex
-     byte dump.  This dump appears on the left hand side of the listing
-     output.
-
-`--listing-lhs-width2=`number''
-     Sets the maximum width, in words, of any further lines of the hex
-     byte dump for a given input source line.  If this value is not
-     specified, it defaults to being the same as the value specified
-     for `--listing-lhs-width'.  If neither switch is used the default
-     is to one.
-
-`--listing-rhs-width=`number''
-     Sets the maximum width, in characters, of the source line that is
-     displayed alongside the hex dump.  The default value for this
-     parameter is 100.  The source line is displayed on the right hand
-     side of the listing output.
-
-`--listing-cont-lines=`number''
-     Sets the maximum number of continuation lines of hex dump that
-     will be displayed for a given single line of source input.  The
-     default value is 4.
-
-
-File: as.info,  Node: M,  Next: MD,  Prev: listing,  Up: Invoking
-
-2.9 Assemble in MRI Compatibility Mode: `-M'
-============================================
-
-The `-M' or `--mri' option selects MRI compatibility mode.  This
-changes the syntax and pseudo-op handling of `as' to make it compatible
-with the `ASM68K' or the `ASM960' (depending upon the configured
-target) assembler from Microtec Research.  The exact nature of the MRI
-syntax will not be documented here; see the MRI manuals for more
-information.  Note in particular that the handling of macros and macro
-arguments is somewhat different.  The purpose of this option is to
-permit assembling existing MRI assembler code using `as'.
-
-   The MRI compatibility is not complete.  Certain operations of the
-MRI assembler depend upon its object file format, and can not be
-supported using other object file formats.  Supporting these would
-require enhancing each object file format individually.  These are:
-
-   * global symbols in common section
-
-     The m68k MRI assembler supports common sections which are merged
-     by the linker.  Other object file formats do not support this.
-     `as' handles common sections by treating them as a single common
-     symbol.  It permits local symbols to be defined within a common
-     section, but it can not support global symbols, since it has no
-     way to describe them.
-
-   * complex relocations
-
-     The MRI assemblers support relocations against a negated section
-     address, and relocations which combine the start addresses of two
-     or more sections.  These are not support by other object file
-     formats.
-
-   * `END' pseudo-op specifying start address
-
-     The MRI `END' pseudo-op permits the specification of a start
-     address.  This is not supported by other object file formats.  The
-     start address may instead be specified using the `-e' option to
-     the linker, or in a linker script.
-
-   * `IDNT', `.ident' and `NAME' pseudo-ops
-
-     The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module
-     name to the output file.  This is not supported by other object
-     file formats.
-
-   * `ORG' pseudo-op
-
-     The m68k MRI `ORG' pseudo-op begins an absolute section at a given
-     address.  This differs from the usual `as' `.org' pseudo-op, which
-     changes the location within the current section.  Absolute
-     sections are not supported by other object file formats.  The
-     address of a section may be assigned within a linker script.
-
-   There are some other features of the MRI assembler which are not
-supported by `as', typically either because they are difficult or
-because they seem of little consequence.  Some of these may be
-supported in future releases.
-
-   * EBCDIC strings
-
-     EBCDIC strings are not supported.
-
-   * packed binary coded decimal
-
-     Packed binary coded decimal is not supported.  This means that the
-     `DC.P' and `DCB.P' pseudo-ops are not supported.
-
-   * `FEQU' pseudo-op
-
-     The m68k `FEQU' pseudo-op is not supported.
-
-   * `NOOBJ' pseudo-op
-
-     The m68k `NOOBJ' pseudo-op is not supported.
-
-   * `OPT' branch control options
-
-     The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL',
-     and `BRW'--are ignored.  `as' automatically relaxes all branches,
-     whether forward or backward, to an appropriate size, so these
-     options serve no purpose.
-
-   * `OPT' list control options
-
-     The following m68k `OPT' list control options are ignored: `C',
-     `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'.
-
-   * other `OPT' options
-
-     The following m68k `OPT' options are ignored: `NEST', `O', `OLD',
-     `OP', `P', `PCO', `PCR', `PCS', `R'.
-
-   * `OPT' `D' option is default
-
-     The m68k `OPT' `D' option is the default, unlike the MRI assembler.
-     `OPT NOD' may be used to turn it off.
-
-   * `XREF' pseudo-op.
-
-     The m68k `XREF' pseudo-op is ignored.
-
-   * `.debug' pseudo-op
-
-     The i960 `.debug' pseudo-op is not supported.
-
-   * `.extended' pseudo-op
-
-     The i960 `.extended' pseudo-op is not supported.
-
-   * `.list' pseudo-op.
-
-     The various options of the i960 `.list' pseudo-op are not
-     supported.
-
-   * `.optimize' pseudo-op
-
-     The i960 `.optimize' pseudo-op is not supported.
-
-   * `.output' pseudo-op
-
-     The i960 `.output' pseudo-op is not supported.
-
-   * `.setreal' pseudo-op
-
-     The i960 `.setreal' pseudo-op is not supported.
-
-
-
-File: as.info,  Node: MD,  Next: o,  Prev: M,  Up: Invoking
-
-2.10 Dependency Tracking: `--MD'
-================================
-
-`as' can generate a dependency file for the file it creates.  This file
-consists of a single rule suitable for `make' describing the
-dependencies of the main source file.
-
-   The rule is written to the file named in its argument.
-
-   This feature is used in the automatic updating of makefiles.
-
-
-File: as.info,  Node: o,  Next: R,  Prev: MD,  Up: Invoking
-
-2.11 Name the Object File: `-o'
-===============================
-
-There is always one object file output when you run `as'.  By default
-it has the name `a.out' (or `b.out', for Intel 960 targets only).  You
-use this option (which takes exactly one filename) to give the object
-file a different name.
-
-   Whatever the object file is called, `as' overwrites any existing
-file of the same name.
-
-
-File: as.info,  Node: R,  Next: statistics,  Prev: o,  Up: Invoking
-
-2.12 Join Data and Text Sections: `-R'
-======================================
-
-`-R' tells `as' to write the object file as if all data-section data
-lives in the text section.  This is only done at the very last moment:
-your binary data are the same, but data section parts are relocated
-differently.  The data section part of your object file is zero bytes
-long because all its bytes are appended to the text section.  (*Note
-Sections and Relocation: Sections.)
-
-   When you specify `-R' it would be possible to generate shorter
-address displacements (because we do not have to cross between text and
-data section).  We refrain from doing this simply for compatibility with
-older versions of `as'.  In future, `-R' may work this way.
-
-   When `as' is configured for COFF or ELF output, this option is only
-useful if you use sections named `.text' and `.data'.
-
-   `-R' is not supported for any of the HPPA targets.  Using `-R'
-generates a warning from `as'.
-
-
-File: as.info,  Node: statistics,  Next: traditional-format,  Prev: R,  Up: Invoking
-
-2.13 Display Assembly Statistics: `--statistics'
-================================================
-
-Use `--statistics' to display two statistics about the resources used by
-`as': the maximum amount of space allocated during the assembly (in
-bytes), and the total execution time taken for the assembly (in CPU
-seconds).
-
-
-File: as.info,  Node: traditional-format,  Next: v,  Prev: statistics,  Up: Invoking
-
-2.14 Compatible Output: `--traditional-format'
-==============================================
-
-For some targets, the output of `as' is different in some ways from the
-output of some existing assembler.  This switch requests `as' to use
-the traditional format instead.
-
-   For example, it disables the exception frame optimizations which
-`as' normally does by default on `gcc' output.
-
-
-File: as.info,  Node: v,  Next: W,  Prev: traditional-format,  Up: Invoking
-
-2.15 Announce Version: `-v'
-===========================
-
-You can find out what version of as is running by including the option
-`-v' (which you can also spell as `-version') on the command line.
-
-
-File: as.info,  Node: W,  Next: Z,  Prev: v,  Up: Invoking
-
-2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings'
-======================================================================
-
-`as' should never give a warning or error message when assembling
-compiler output.  But programs written by people often cause `as' to
-give a warning that a particular assumption was made.  All such
-warnings are directed to the standard error file.
-
-   If you use the `-W' and `--no-warn' options, no warnings are issued.
-This only affects the warning messages: it does not change any
-particular of how `as' assembles your file.  Errors, which stop the
-assembly, are still reported.
-
-   If you use the `--fatal-warnings' option, `as' considers files that
-generate warnings to be in error.
-
-   You can switch these options off again by specifying `--warn', which
-causes warnings to be output as usual.
-
-
-File: as.info,  Node: Z,  Prev: W,  Up: Invoking
-
-2.17 Generate Object File in Spite of Errors: `-Z'
-==================================================
-
-After an error message, `as' normally produces no output.  If for some
-reason you are interested in object file output even after `as' gives
-an error message on your program, use the `-Z' option.  If there are
-any errors, `as' continues anyways, and writes an object file after a
-final warning message of the form `N errors, M warnings, generating bad
-object file.'
-
-
-File: as.info,  Node: Syntax,  Next: Sections,  Prev: Invoking,  Up: Top
-
-3 Syntax
-********
-
-This chapter describes the machine-independent syntax allowed in a
-source file.  `as' syntax is similar to what many other assemblers use;
-it is inspired by the BSD 4.2 assembler, except that `as' does not
-assemble Vax bit-fields.
-
-* Menu:
-
-* Preprocessing::              Preprocessing
-* Whitespace::                  Whitespace
-* Comments::                    Comments
-* Symbol Intro::                Symbols
-* Statements::                  Statements
-* Constants::                   Constants
-
-
-File: as.info,  Node: Preprocessing,  Next: Whitespace,  Up: Syntax
-
-3.1 Preprocessing
-=================
-
-The `as' internal preprocessor:
-   * adjusts and removes extra whitespace.  It leaves one space or tab
-     before the keywords on a line, and turns any other whitespace on
-     the line into a single space.
-
-   * removes all comments, replacing them with a single space, or an
-     appropriate number of newlines.
-
-   * converts character constants into the appropriate numeric values.
-
-   It does not do macro processing, include file handling, or anything
-else you may get from your C compiler's preprocessor.  You can do
-include file processing with the `.include' directive (*note
-`.include': Include.).  You can use the GNU C compiler driver to get
-other "CPP" style preprocessing by giving the input file a `.S' suffix.
-*Note Options Controlling the Kind of Output: (gcc.info)Overall
-Options.
-
-   Excess whitespace, comments, and character constants cannot be used
-in the portions of the input text that are not preprocessed.
-
-   If the first line of an input file is `#NO_APP' or if you use the
-`-f' option, whitespace and comments are not removed from the input
-file.  Within an input file, you can ask for whitespace and comment
-removal in specific portions of the by putting a line that says `#APP'
-before the text that may contain whitespace or comments, and putting a
-line that says `#NO_APP' after this text.  This feature is mainly
-intend to support `asm' statements in compilers whose output is
-otherwise free of comments and whitespace.
-
-
-File: as.info,  Node: Whitespace,  Next: Comments,  Prev: Preprocessing,  Up: Syntax
-
-3.2 Whitespace
-==============
-
-"Whitespace" is one or more blanks or tabs, in any order.  Whitespace
-is used to separate symbols, and to make programs neater for people to
-read.  Unless within character constants (*note Character Constants:
-Characters.), any whitespace means the same as exactly one space.
-
-
-File: as.info,  Node: Comments,  Next: Symbol Intro,  Prev: Whitespace,  Up: Syntax
-
-3.3 Comments
-============
-
-There are two ways of rendering comments to `as'.  In both cases the
-comment is equivalent to one space.
-
-   Anything from `/*' through the next `*/' is a comment.  This means
-you may not nest these comments.
-
-     /*
-       The only way to include a newline ('\n') in a comment
-       is to use this sort of comment.
-     */
-
-     /* This sort of comment does not nest. */
-
-   Anything from the "line comment" character to the next newline is
-considered a comment and is ignored.  The line comment character is `;'
-on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA;
-`#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;'
-for picoJava; `#' for Motorola PowerPC; `!' for the Renesas / SuperH SH;
-`!' on the SPARC; `#' on the ip2k; `#' on the m32c; `#' on the m32r;
-`|' on the 680x0; `#' on the 68HC11 and 68HC12; `#' on the Vax; `;' for
-the Z80; `!' for the Z8000; `#' on the V850; `#' for Xtensa systems;
-see *Note Machine Dependencies::.
-
-   On some machines there are two different line comment characters.
-One character only begins a comment if it is the first non-whitespace
-character on a line, while the other always begins a comment.
-
-   The V850 assembler also supports a double dash as starting a comment
-that extends to the end of the line.
-
-   `--';
-
-   To be compatible with past assemblers, lines that begin with `#'
-have a special interpretation.  Following the `#' should be an absolute
-expression (*note Expressions::): the logical line number of the _next_
-line.  Then a string (*note Strings: Strings.) is allowed: if present
-it is a new logical file name.  The rest of the line, if any, should be
-whitespace.
-
-   If the first non-whitespace characters on the line are not numeric,
-the line is ignored.  (Just like a comment.)
-
-                               # This is an ordinary comment.
-     # 42-6 "new_file_name"    # New logical file name
-                               # This is logical line # 36.
-   This feature is deprecated, and may disappear from future versions
-of `as'.
-
-
-File: as.info,  Node: Symbol Intro,  Next: Statements,  Prev: Comments,  Up: Syntax
-
-3.4 Symbols
-===========
-
-A "symbol" is one or more characters chosen from the set of all letters
-(both upper and lower case), digits and the three characters `_.$'.  On
-most machines, you can also use `$' in symbol names; exceptions are
-noted in *Note Machine Dependencies::.  No symbol may begin with a
-digit.  Case is significant.  There is no length limit: all characters
-are significant.  Symbols are delimited by characters not in that set,
-or by the beginning of a file (since the source program must end with a
-newline, the end of a file is not a possible symbol delimiter).  *Note
-Symbols::.  
-
-
-File: as.info,  Node: Statements,  Next: Constants,  Prev: Symbol Intro,  Up: Syntax
-
-3.5 Statements
-==============
-
-A "statement" ends at a newline character (`\n') or line separator
-character.  (The line separator is usually `;', unless this conflicts
-with the comment character; *note Machine Dependencies::.)  The newline
-or separator character is considered part of the preceding statement.
-Newlines and separators within character constants are an exception:
-they do not end statements.
-
-It is an error to end any statement with end-of-file:  the last
-character of any input file should be a newline.
-
-   An empty statement is allowed, and may include whitespace.  It is
-ignored.
-
-   A statement begins with zero or more labels, optionally followed by a
-key symbol which determines what kind of statement it is.  The key
-symbol determines the syntax of the rest of the statement.  If the
-symbol begins with a dot `.' then the statement is an assembler
-directive: typically valid for any computer.  If the symbol begins with
-a letter the statement is an assembly language "instruction": it
-assembles into a machine language instruction.  Different versions of
-`as' for different computers recognize different instructions.  In
-fact, the same symbol may represent a different instruction in a
-different computer's assembly language.
-
-   A label is a symbol immediately followed by a colon (`:').
-Whitespace before a label or after a colon is permitted, but you may not
-have whitespace between a label's symbol and its colon. *Note Labels::.
-
-   For HPPA targets, labels need not be immediately followed by a
-colon, but the definition of a label must begin in column zero.  This
-also implies that only one label may be defined on each line.
-
-     label:     .directive    followed by something
-     another_label:           # This is an empty statement.
-                instruction   operand_1, operand_2, ...
-
-
-File: as.info,  Node: Constants,  Prev: Statements,  Up: Syntax
-
-3.6 Constants
-=============
-
-A constant is a number, written so that its value is known by
-inspection, without knowing any context.  Like this:
-     .byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
-     .ascii "Ring the bell\7"                  # A string constant.
-     .octa  0x123456789abcdef0123456789ABCDEF0 # A bignum.
-     .float 0f-314159265358979323846264338327\
-     95028841971.693993751E-40                 # - pi, a flonum.
-
-* Menu:
-
-* Characters::                  Character Constants
-* Numbers::                     Number Constants
-
-
-File: as.info,  Node: Characters,  Next: Numbers,  Up: Constants
-
-3.6.1 Character Constants
--------------------------
-
-There are two kinds of character constants.  A "character" stands for
-one character in one byte and its value may be used in numeric
-expressions.  String constants (properly called string _literals_) are
-potentially many bytes and their values may not be used in arithmetic
-expressions.
-
-* Menu:
-
-* Strings::                     Strings
-* Chars::                       Characters
-
-
-File: as.info,  Node: Strings,  Next: Chars,  Up: Characters
-
-3.6.1.1 Strings
-...............
-
-A "string" is written between double-quotes.  It may contain
-double-quotes or null characters.  The way to get special characters
-into a string is to "escape" these characters: precede them with a
-backslash `\' character.  For example `\\' represents one backslash:
-the first `\' is an escape which tells `as' to interpret the second
-character literally as a backslash (which prevents `as' from
-recognizing the second `\' as an escape character).  The complete list
-of escapes follows.
-
-`\b'
-     Mnemonic for backspace; for ASCII this is octal code 010.
-
-`\f'
-     Mnemonic for FormFeed; for ASCII this is octal code 014.
-
-`\n'
-     Mnemonic for newline; for ASCII this is octal code 012.
-
-`\r'
-     Mnemonic for carriage-Return; for ASCII this is octal code 015.
-
-`\t'
-     Mnemonic for horizontal Tab; for ASCII this is octal code 011.
-
-`\ DIGIT DIGIT DIGIT'
-     An octal character code.  The numeric code is 3 octal digits.  For
-     compatibility with other Unix systems, 8 and 9 are accepted as
-     digits: for example, `\008' has the value 010, and `\009' the
-     value 011.
-
-`\`x' HEX-DIGITS...'
-     A hex character code.  All trailing hex digits are combined.
-     Either upper or lower case `x' works.
-
-`\\'
-     Represents one `\' character.
-
-`\"'
-     Represents one `"' character.  Needed in strings to represent this
-     character, because an unescaped `"' would end the string.
-
-`\ ANYTHING-ELSE'
-     Any other character when escaped by `\' gives a warning, but
-     assembles as if the `\' was not present.  The idea is that if you
-     used an escape sequence you clearly didn't want the literal
-     interpretation of the following character.  However `as' has no
-     other interpretation, so `as' knows it is giving you the wrong
-     code and warns you of the fact.
-
-   Which characters are escapable, and what those escapes represent,
-varies widely among assemblers.  The current set is what we think the
-BSD 4.2 assembler recognizes, and is a subset of what most C compilers
-recognize.  If you are in doubt, do not use an escape sequence.
-
-
-File: as.info,  Node: Chars,  Prev: Strings,  Up: Characters
-
-3.6.1.2 Characters
-..................
-
-A single character may be written as a single quote immediately
-followed by that character.  The same escapes apply to characters as to
-strings.  So if you want to write the character backslash, you must
-write `'\\' where the first `\' escapes the second `\'.  As you can
-see, the quote is an acute accent, not a grave accent.  A newline
-immediately following an acute accent is taken as a literal character
-and does not count as the end of a statement.  The value of a character
-constant in a numeric expression is the machine's byte-wide code for
-that character.  `as' assumes your character code is ASCII: `'A' means
-65, `'B' means 66, and so on.
-
-
-File: as.info,  Node: Numbers,  Prev: Characters,  Up: Constants
-
-3.6.2 Number Constants
-----------------------
-
-`as' distinguishes three kinds of numbers according to how they are
-stored in the target machine.  _Integers_ are numbers that would fit
-into an `int' in the C language.  _Bignums_ are integers, but they are
-stored in more than 32 bits.  _Flonums_ are floating point numbers,
-described below.
-
-* Menu:
-
-* Integers::                    Integers
-* Bignums::                     Bignums
-* Flonums::                     Flonums
-
-
-File: as.info,  Node: Integers,  Next: Bignums,  Up: Numbers
-
-3.6.2.1 Integers
-................
-
-A binary integer is `0b' or `0B' followed by zero or more of the binary
-digits `01'.
-
-   An octal integer is `0' followed by zero or more of the octal digits
-(`01234567').
-
-   A decimal integer starts with a non-zero digit followed by zero or
-more digits (`0123456789').
-
-   A hexadecimal integer is `0x' or `0X' followed by one or more
-hexadecimal digits chosen from `0123456789abcdefABCDEF'.
-
-   Integers have the usual values.  To denote a negative integer, use
-the prefix operator `-' discussed under expressions (*note Prefix
-Operators: Prefix Ops.).
-
-
-File: as.info,  Node: Bignums,  Next: Flonums,  Prev: Integers,  Up: Numbers
-
-3.6.2.2 Bignums
-...............
-
-A "bignum" has the same syntax and semantics as an integer except that
-the number (or its negative) takes more than 32 bits to represent in
-binary.  The distinction is made because in some places integers are
-permitted while bignums are not.
-
-
-File: as.info,  Node: Flonums,  Prev: Bignums,  Up: Numbers
-
-3.6.2.3 Flonums
-...............
-
-A "flonum" represents a floating point number.  The translation is
-indirect: a decimal floating point number from the text is converted by
-`as' to a generic binary floating point number of more than sufficient
-precision.  This generic floating point number is converted to a
-particular computer's floating point format (or formats) by a portion
-of `as' specialized to that computer.
-
-   A flonum is written by writing (in order)
-   * The digit `0'.  (`0' is optional on the HPPA.)
-
-   * A letter, to tell `as' the rest of the number is a flonum.  `e' is
-     recommended.  Case is not important.
-
-     On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
-     letter must be one of the letters `DFPRSX' (in upper or lower
-     case).
-
-     On the ARC, the letter must be one of the letters `DFRS' (in upper
-     or lower case).
-
-     On the Intel 960 architecture, the letter must be one of the
-     letters `DFT' (in upper or lower case).
-
-     On the HPPA architecture, the letter must be `E' (upper case only).
-
-   * An optional sign: either `+' or `-'.
-
-   * An optional "integer part": zero or more decimal digits.
-
-   * An optional "fractional part": `.' followed by zero or more
-     decimal digits.
-
-   * An optional exponent, consisting of:
-
-        * An `E' or `e'.
-
-        * Optional sign: either `+' or `-'.
-
-        * One or more decimal digits.
-
-
-   At least one of the integer part or the fractional part must be
-present.  The floating point number has the usual base-10 value.
-
-   `as' does all processing using integers.  Flonums are computed
-independently of any floating point hardware in the computer running
-`as'.
-
-
-File: as.info,  Node: Sections,  Next: Symbols,  Prev: Syntax,  Up: Top
-
-4 Sections and Relocation
-*************************
-
-* Menu:
-
-* Secs Background::             Background
-* Ld Sections::                 Linker Sections
-* As Sections::                 Assembler Internal Sections
-* Sub-Sections::                Sub-Sections
-* bss::                         bss Section
-
-
-File: as.info,  Node: Secs Background,  Next: Ld Sections,  Up: Sections
-
-4.1 Background
-==============
-
-Roughly, a section is a range of addresses, with no gaps; all data "in"
-those addresses is treated the same for some particular purpose.  For
-example there may be a "read only" section.
-
-   The linker `ld' reads many object files (partial programs) and
-combines their contents to form a runnable program.  When `as' emits an
-object file, the partial program is assumed to start at address 0.
-`ld' assigns the final addresses for the partial program, so that
-different partial programs do not overlap.  This is actually an
-oversimplification, but it suffices to explain how `as' uses sections.
-
-   `ld' moves blocks of bytes of your program to their run-time
-addresses.  These blocks slide to their run-time addresses as rigid
-units; their length does not change and neither does the order of bytes
-within them.  Such a rigid unit is called a _section_.  Assigning
-run-time addresses to sections is called "relocation".  It includes the
-task of adjusting mentions of object-file addresses so they refer to
-the proper run-time addresses.  For the H8/300, and for the Renesas /
-SuperH SH, `as' pads sections if needed to ensure they end on a word
-(sixteen bit) boundary.
-
-   An object file written by `as' has at least three sections, any of
-which may be empty.  These are named "text", "data" and "bss" sections.
-
-   When it generates COFF or ELF output, `as' can also generate
-whatever other named sections you specify using the `.section'
-directive (*note `.section': Section.).  If you do not use any
-directives that place output in the `.text' or `.data' sections, these
-sections still exist, but are empty.
-
-   When `as' generates SOM or ELF output for the HPPA, `as' can also
-generate whatever other named sections you specify using the `.space'
-and `.subspace' directives.  See `HP9000 Series 800 Assembly Language
-Reference Manual' (HP 92432-90001) for details on the `.space' and
-`.subspace' assembler directives.
-
-   Additionally, `as' uses different names for the standard text, data,
-and bss sections when generating SOM output.  Program text is placed
-into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'.
-
-   Within the object file, the text section starts at address `0', the
-data section follows, and the bss section follows the data section.
-
-   When generating either SOM or ELF output files on the HPPA, the text
-section starts at address `0', the data section at address `0x4000000',
-and the bss section follows the data section.
-
-   To let `ld' know which data changes when the sections are relocated,
-and how to change that data, `as' also writes to the object file
-details of the relocation needed.  To perform relocation `ld' must
-know, each time an address in the object file is mentioned:
-   * Where in the object file is the beginning of this reference to an
-     address?
-
-   * How long (in bytes) is this reference?
-
-   * Which section does the address refer to?  What is the numeric
-     value of
-          (ADDRESS) - (START-ADDRESS OF SECTION)?
-
-   * Is the reference to an address "Program-Counter relative"?
-
-   In fact, every address `as' ever uses is expressed as
-     (SECTION) + (OFFSET INTO SECTION)
-   Further, most expressions `as' computes have this section-relative
-nature.  (For some object formats, such as SOM for the HPPA, some
-expressions are symbol-relative instead.)
-
-   In this manual we use the notation {SECNAME N} to mean "offset N
-into section SECNAME."
-
-   Apart from text, data and bss sections you need to know about the
-"absolute" section.  When `ld' mixes partial programs, addresses in the
-absolute section remain unchanged.  For example, address `{absolute 0}'
-is "relocated" to run-time address 0 by `ld'.  Although the linker
-never arranges two partial programs' data sections with overlapping
-addresses after linking, _by definition_ their absolute sections must
-overlap.  Address `{absolute 239}' in one part of a program is always
-the same address when the program is running as address `{absolute
-239}' in any other part of the program.
-
-   The idea of sections is extended to the "undefined" section.  Any
-address whose section is unknown at assembly time is by definition
-rendered {undefined U}--where U is filled in later.  Since numbers are
-always defined, the only way to generate an undefined address is to
-mention an undefined symbol.  A reference to a named common block would
-be such a symbol: its value is unknown at assembly time so it has
-section _undefined_.
-
-   By analogy the word _section_ is used to describe groups of sections
-in the linked program.  `ld' puts all partial programs' text sections
-in contiguous addresses in the linked program.  It is customary to
-refer to the _text section_ of a program, meaning all the addresses of
-all partial programs' text sections.  Likewise for data and bss
-sections.
-
-   Some sections are manipulated by `ld'; others are invented for use
-of `as' and have no meaning except during assembly.
-
-
-File: as.info,  Node: Ld Sections,  Next: As Sections,  Prev: Secs Background,  Up: Sections
-
-4.2 Linker Sections
-===================
-
-`ld' deals with just four kinds of sections, summarized below.
-
-*named sections*
-*text section*
-*data section*
-     These sections hold your program.  `as' and `ld' treat them as
-     separate but equal sections.  Anything you can say of one section
-     is true of another.  When the program is running, however, it is
-     customary for the text section to be unalterable.  The text
-     section is often shared among processes: it contains instructions,
-     constants and the like.  The data section of a running program is
-     usually alterable: for example, C variables would be stored in the
-     data section.
-
-*bss section*
-     This section contains zeroed bytes when your program begins
-     running.  It is used to hold uninitialized variables or common
-     storage.  The length of each partial program's bss section is
-     important, but because it starts out containing zeroed bytes there
-     is no need to store explicit zero bytes in the object file.  The
-     bss section was invented to eliminate those explicit zeros from
-     object files.
-
-*absolute section*
-     Address 0 of this section is always "relocated" to runtime address
-     0.  This is useful if you want to refer to an address that `ld'
-     must not change when relocating.  In this sense we speak of
-     absolute addresses being "unrelocatable": they do not change
-     during relocation.
-
-*undefined section*
-     This "section" is a catch-all for address references to objects
-     not in the preceding sections.
-
-   An idealized example of three relocatable sections follows.  The
-example uses the traditional section names `.text' and `.data'.  Memory
-addresses are on the horizontal axis.
-
-                           +-----+----+--+
-     partial program # 1:  |ttttt|dddd|00|
-                           +-----+----+--+
-
-                           text   data bss
-                           seg.   seg. seg.
-
-                           +---+---+---+
-     partial program # 2:  |TTT|DDD|000|
-                           +---+---+---+
-
-                           +--+---+-----+--+----+---+-----+~~
-     linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
-                           +--+---+-----+--+----+---+-----+~~
-
-         addresses:        0 ...
-
-
-File: as.info,  Node: As Sections,  Next: Sub-Sections,  Prev: Ld Sections,  Up: Sections
-
-4.3 Assembler Internal Sections
-===============================
-
-These sections are meant only for the internal use of `as'.  They have
-no meaning at run-time.  You do not really need to know about these
-sections for most purposes; but they can be mentioned in `as' warning
-messages, so it might be helpful to have an idea of their meanings to
-`as'.  These sections are used to permit the value of every expression
-in your assembly language program to be a section-relative address.
-
-ASSEMBLER-INTERNAL-LOGIC-ERROR!
-     An internal assembler logic error has been found.  This means
-     there is a bug in the assembler.
-
-expr section
-     The assembler stores complex expression internally as combinations
-     of symbols.  When it needs to represent an expression as a symbol,
-     it puts it in the expr section.
-
-
-File: as.info,  Node: Sub-Sections,  Next: bss,  Prev: As Sections,  Up: Sections
-
-4.4 Sub-Sections
-================
-
-Assembled bytes conventionally fall into two sections: text and data.
-You may have separate groups of data in named sections that you want to
-end up near to each other in the object file, even though they are not
-contiguous in the assembler source.  `as' allows you to use
-"subsections" for this purpose.  Within each section, there can be
-numbered subsections with values from 0 to 8192.  Objects assembled
-into the same subsection go into the object file together with other
-objects in the same subsection.  For example, a compiler might want to
-store constants in the text section, but might not want to have them
-interspersed with the program being assembled.  In this case, the
-compiler could issue a `.text 0' before each section of code being
-output, and a `.text 1' before each group of constants being output.
-
-Subsections are optional.  If you do not use subsections, everything
-goes in subsection number zero.
-
-   Each subsection is zero-padded up to a multiple of four bytes.
-(Subsections may be padded a different amount on different flavors of
-`as'.)
-
-   Subsections appear in your object file in numeric order, lowest
-numbered to highest.  (All this to be compatible with other people's
-assemblers.)  The object file contains no representation of
-subsections; `ld' and other programs that manipulate object files see
-no trace of them.  They just see all your text subsections as a text
-section, and all your data subsections as a data section.
-
-   To specify which subsection you want subsequent statements assembled
-into, use a numeric argument to specify it, in a `.text EXPRESSION' or
-a `.data EXPRESSION' statement.  When generating COFF output, you can
-also use an extra subsection argument with arbitrary named sections:
-`.section NAME, EXPRESSION'.  When generating ELF output, you can also
-use the `.subsection' directive (*note SubSection::) to specify a
-subsection: `.subsection EXPRESSION'.  EXPRESSION should be an absolute
-expression.  (*Note Expressions::.)  If you just say `.text' then
-`.text 0' is assumed.  Likewise `.data' means `.data 0'.  Assembly
-begins in `text 0'.  For instance:
-     .text 0     # The default subsection is text 0 anyway.
-     .ascii "This lives in the first text subsection. *"
-     .text 1
-     .ascii "But this lives in the second text subsection."
-     .data 0
-     .ascii "This lives in the data section,"
-     .ascii "in the first data subsection."
-     .text 0
-     .ascii "This lives in the first text section,"
-     .ascii "immediately following the asterisk (*)."
-
-   Each section has a "location counter" incremented by one for every
-byte assembled into that section.  Because subsections are merely a
-convenience restricted to `as' there is no concept of a subsection
-location counter.  There is no way to directly manipulate a location
-counter--but the `.align' directive changes it, and any label
-definition captures its current value.  The location counter of the
-section where statements are being assembled is said to be the "active"
-location counter.
-
-
-File: as.info,  Node: bss,  Prev: Sub-Sections,  Up: Sections
-
-4.5 bss Section
-===============
-
-The bss section is used for local common variable storage.  You may
-allocate address space in the bss section, but you may not dictate data
-to load into it before your program executes.  When your program starts
-running, all the contents of the bss section are zeroed bytes.
-
-   The `.lcomm' pseudo-op defines a symbol in the bss section; see
-*Note `.lcomm': Lcomm.
-
-   The `.comm' pseudo-op may be used to declare a common symbol, which
-is another form of uninitialized symbol; see *Note `.comm': Comm.
-
-   When assembling for a target which supports multiple sections, such
-as ELF or COFF, you may switch into the `.bss' section and define
-symbols as usual; see *Note `.section': Section.  You may only assemble
-zero values into the section.  Typically the section will only contain
-symbol definitions and `.skip' directives (*note `.skip': Skip.).
-
-
-File: as.info,  Node: Symbols,  Next: Expressions,  Prev: Sections,  Up: Top
-
-5 Symbols
-*********
-
-Symbols are a central concept: the programmer uses symbols to name
-things, the linker uses symbols to link, and the debugger uses symbols
-to debug.
-
-     _Warning:_ `as' does not place symbols in the object file in the
-     same order they were declared.  This may break some debuggers.
-
-* Menu:
-
-* Labels::                      Labels
-* Setting Symbols::             Giving Symbols Other Values
-* Symbol Names::                Symbol Names
-* Dot::                         The Special Dot Symbol
-* Symbol Attributes::           Symbol Attributes
-
-
-File: as.info,  Node: Labels,  Next: Setting Symbols,  Up: Symbols
-
-5.1 Labels
-==========
-
-A "label" is written as a symbol immediately followed by a colon `:'.
-The symbol then represents the current value of the active location
-counter, and is, for example, a suitable instruction operand.  You are
-warned if you use the same symbol to represent two different locations:
-the first definition overrides any other definitions.
-
-   On the HPPA, the usual form for a label need not be immediately
-followed by a colon, but instead must start in column zero.  Only one
-label may be defined on a single line.  To work around this, the HPPA
-version of `as' also provides a special directive `.label' for defining
-labels more flexibly.
-
-
-File: as.info,  Node: Setting Symbols,  Next: Symbol Names,  Prev: Labels,  Up: Symbols
-
-5.2 Giving Symbols Other Values
-===============================
-
-A symbol can be given an arbitrary value by writing a symbol, followed
-by an equals sign `=', followed by an expression (*note Expressions::).
-This is equivalent to using the `.set' directive.  *Note `.set': Set.
-In the same way, using a double equals sign `='`=' here represents an
-equivalent of the `.eqv' directive.  *Note `.eqv': Eqv.
-
-
-File: as.info,  Node: Symbol Names,  Next: Dot,  Prev: Setting Symbols,  Up: Symbols
-
-5.3 Symbol Names
-================
-
-Symbol names begin with a letter or with one of `._'.  On most
-machines, you can also use `$' in symbol names; exceptions are noted in
-*Note Machine Dependencies::.  That character may be followed by any
-string of digits, letters, dollar signs (unless otherwise noted in
-*Note Machine Dependencies::), and underscores.
-
-Case of letters is significant: `foo' is a different symbol name than
-`Foo'.
-
-   Each symbol has exactly one name.  Each name in an assembly language
-program refers to exactly one symbol.  You may use that symbol name any
-number of times in a program.
-
-Local Symbol Names
-------------------
-
-Local symbols help compilers and programmers use names temporarily.
-They create symbols which are guaranteed to be unique over the entire
-scope of the input source code and which can be referred to by a simple
-notation.  To define a local symbol, write a label of the form `N:'
-(where N represents any positive integer).  To refer to the most recent
-previous definition of that symbol write `Nb', using the same number as
-when you defined the label.  To refer to the next definition of a local
-label, write `Nf'-- The `b' stands for"backwards" and the `f' stands
-for "forwards".
-
-   There is no restriction on how you can use these labels, and you can
-reuse them too.  So that it is possible to repeatedly define the same
-local label (using the same number `N'), although you can only refer to
-the most recently defined local label of that number (for a backwards
-reference) or the next definition of a specific local label for a
-forward reference.  It is also worth noting that the first 10 local
-labels (`0:'...`9:') are implemented in a slightly more efficient
-manner than the others.
-
-   Here is an example:
-
-     1:        branch 1f
-     2:        branch 1b
-     1:        branch 2f
-     2:        branch 1b
-
-   Which is the equivalent of:
-
-     label_1:  branch label_3
-     label_2:  branch label_1
-     label_3:  branch label_4
-     label_4:  branch label_3
-
-   Local symbol names are only a notational device.  They are
-immediately transformed into more conventional symbol names before the
-assembler uses them.  The symbol names stored in the symbol table,
-appearing in error messages and optionally emitted to the object file.
-The names are constructed using these parts:
-
-`L'
-     All local labels begin with `L'. Normally both `as' and `ld'
-     forget symbols that start with `L'. These labels are used for
-     symbols you are never intended to see.  If you use the `-L' option
-     then `as' retains these symbols in the object file. If you also
-     instruct `ld' to retain these symbols, you may use them in
-     debugging.
-
-`NUMBER'
-     This is the number that was used in the local label definition.
-     So if the label is written `55:' then the number is `55'.
-
-`C-B'
-     This unusual character is included so you do not accidentally
-     invent a symbol of the same name.  The character has ASCII value
-     of `\002' (control-B).
-
-`_ordinal number_'
-     This is a serial number to keep the labels distinct.  The first
-     definition of `0:' gets the number `1'.  The 15th definition of
-     `0:' gets the number `15', and so on.  Likewise the first
-     definition of `1:' gets the number `1' and its 15th defintion gets
-     `15' as well.
-
-   So for example, the first `1:' is named `L1C-B1', the 44th `3:' is
-named `L3C-B44'.
-
-Dollar Local Labels
--------------------
-
-`as' also supports an even more local form of local labels called
-dollar labels.  These labels go out of scope (ie they become undefined)
-as soon as a non-local label is defined.  Thus they remain valid for
-only a small region of the input source code.  Normal local labels, by
-contrast, remain in scope for the entire file, or until they are
-redefined by another occurrence of the same local label.
-
-   Dollar labels are defined in exactly the same way as ordinary local
-labels, except that instead of being terminated by a colon, they are
-terminated by a dollar sign.  eg `55$'.
-
-   They can also be distinguished from ordinary local labels by their
-transformed name which uses ASCII character `\001' (control-A) as the
-magic character to distinguish them from ordinary labels.  Thus the 5th
-defintion of `6$' is named `L6C-A5'.
-
-
-File: as.info,  Node: Dot,  Next: Symbol Attributes,  Prev: Symbol Names,  Up: Symbols
-
-5.4 The Special Dot Symbol
-==========================
-
-The special symbol `.' refers to the current address that `as' is
-assembling into.  Thus, the expression `melvin: .long .' defines
-`melvin' to contain its own address.  Assigning a value to `.' is
-treated the same as a `.org' directive.  Thus, the expression `.=.+4'
-is the same as saying `.space 4'.
-
-
-File: as.info,  Node: Symbol Attributes,  Prev: Dot,  Up: Symbols
-
-5.5 Symbol Attributes
-=====================
-
-Every symbol has, as well as its name, the attributes "Value" and
-"Type".  Depending on output format, symbols can also have auxiliary
-attributes.
-
-   If you use a symbol without defining it, `as' assumes zero for all
-these attributes, and probably won't warn you.  This makes the symbol
-an externally defined symbol, which is generally what you would want.
-
-* Menu:
-
-* Symbol Value::                Value
-* Symbol Type::                 Type
-
-
-* a.out Symbols::               Symbol Attributes: `a.out'
-
-* COFF Symbols::                Symbol Attributes for COFF
-
-* SOM Symbols::                Symbol Attributes for SOM
-
-
-File: as.info,  Node: Symbol Value,  Next: Symbol Type,  Up: Symbol Attributes
-
-5.5.1 Value
------------
-
-The value of a symbol is (usually) 32 bits.  For a symbol which labels a
-location in the text, data, bss or absolute sections the value is the
-number of addresses from the start of that section to the label.
-Naturally for text, data and bss sections the value of a symbol changes
-as `ld' changes section base addresses during linking.  Absolute
-symbols' values do not change during linking: that is why they are
-called absolute.
-
-   The value of an undefined symbol is treated in a special way.  If it
-is 0 then the symbol is not defined in this assembler source file, and
-`ld' tries to determine its value from other files linked into the same
-program.  You make this kind of symbol simply by mentioning a symbol
-name without defining it.  A non-zero value represents a `.comm' common
-declaration.  The value is how much common storage to reserve, in bytes
-(addresses).  The symbol refers to the first address of the allocated
-storage.
-
-
-File: as.info,  Node: Symbol Type,  Next: a.out Symbols,  Prev: Symbol Value,  Up: Symbol Attributes
-
-5.5.2 Type
-----------
-
-The type attribute of a symbol contains relocation (section)
-information, any flag settings indicating that a symbol is external, and
-(optionally), other information for linkers and debuggers.  The exact
-format depends on the object-code output format in use.
-
-
-File: as.info,  Node: a.out Symbols,  Next: COFF Symbols,  Prev: Symbol Type,  Up: Symbol Attributes
-
-5.5.3 Symbol Attributes: `a.out'
---------------------------------
-
-* Menu:
-
-* Symbol Desc::                 Descriptor
-* Symbol Other::                Other
-
-
-File: as.info,  Node: Symbol Desc,  Next: Symbol Other,  Up: a.out Symbols
-
-5.5.3.1 Descriptor
-..................
-
-This is an arbitrary 16-bit value.  You may establish a symbol's
-descriptor value by using a `.desc' statement (*note `.desc': Desc.).
-A descriptor value means nothing to `as'.
-
-
-File: as.info,  Node: Symbol Other,  Prev: Symbol Desc,  Up: a.out Symbols
-
-5.5.3.2 Other
-.............
-
-This is an arbitrary 8-bit value.  It means nothing to `as'.
-
-
-File: as.info,  Node: COFF Symbols,  Next: SOM Symbols,  Prev: a.out Symbols,  Up: Symbol Attributes
-
-5.5.4 Symbol Attributes for COFF
---------------------------------
-
-The COFF format supports a multitude of auxiliary symbol attributes;
-like the primary symbol attributes, they are set between `.def' and
-`.endef' directives.
-
-5.5.4.1 Primary Attributes
-..........................
-
-The symbol name is set with `.def'; the value and type, respectively,
-with `.val' and `.type'.
-
-5.5.4.2 Auxiliary Attributes
-............................
-
-The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and
-`.weak' can generate auxiliary symbol table information for COFF.
-
-
-File: as.info,  Node: SOM Symbols,  Prev: COFF Symbols,  Up: Symbol Attributes
-
-5.5.5 Symbol Attributes for SOM
--------------------------------
-
-The SOM format for the HPPA supports a multitude of symbol attributes
-set with the `.EXPORT' and `.IMPORT' directives.
-
-   The attributes are described in `HP9000 Series 800 Assembly Language
-Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT'
-assembler directive documentation.
-
-
-File: as.info,  Node: Expressions,  Next: Pseudo Ops,  Prev: Symbols,  Up: Top
-
-6 Expressions
-*************
-
-An "expression" specifies an address or numeric value.  Whitespace may
-precede and/or follow an expression.
-
-   The result of an expression must be an absolute number, or else an
-offset into a particular section.  If an expression is not absolute,
-and there is not enough information when `as' sees the expression to
-know its section, a second pass over the source program might be
-necessary to interpret the expression--but the second pass is currently
-not implemented.  `as' aborts with an error message in this situation.
-
-* Menu:
-
-* Empty Exprs::                 Empty Expressions
-* Integer Exprs::               Integer Expressions
-
-
-File: as.info,  Node: Empty Exprs,  Next: Integer Exprs,  Up: Expressions
-
-6.1 Empty Expressions
-=====================
-
-An empty expression has no value: it is just whitespace or null.
-Wherever an absolute expression is required, you may omit the
-expression, and `as' assumes a value of (absolute) 0.  This is
-compatible with other assemblers.
-
-
-File: as.info,  Node: Integer Exprs,  Prev: Empty Exprs,  Up: Expressions
-
-6.2 Integer Expressions
-=======================
-
-An "integer expression" is one or more _arguments_ delimited by
-_operators_.
-
-* Menu:
-
-* Arguments::                   Arguments
-* Operators::                   Operators
-* Prefix Ops::                  Prefix Operators
-* Infix Ops::                   Infix Operators
-
-
-File: as.info,  Node: Arguments,  Next: Operators,  Up: Integer Exprs
-
-6.2.1 Arguments
----------------
-
-"Arguments" are symbols, numbers or subexpressions.  In other contexts
-arguments are sometimes called "arithmetic operands".  In this manual,
-to avoid confusing them with the "instruction operands" of the machine
-language, we use the term "argument" to refer to parts of expressions
-only, reserving the word "operand" to refer only to machine instruction
-operands.
-
-   Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
-text, data, bss, absolute, or undefined.  NNN is a signed, 2's
-complement 32 bit integer.
-
-   Numbers are usually integers.
-
-   A number can be a flonum or bignum.  In this case, you are warned
-that only the low order 32 bits are used, and `as' pretends these 32
-bits are an integer.  You may write integer-manipulating instructions
-that act on exotic constants, compatible with other assemblers.
-
-   Subexpressions are a left parenthesis `(' followed by an integer
-expression, followed by a right parenthesis `)'; or a prefix operator
-followed by an argument.
-
-
-File: as.info,  Node: Operators,  Next: Prefix Ops,  Prev: Arguments,  Up: Integer Exprs
-
-6.2.2 Operators
----------------
-
-"Operators" are arithmetic functions, like `+' or `%'.  Prefix
-operators are followed by an argument.  Infix operators appear between
-their arguments.  Operators may be preceded and/or followed by
-whitespace.
-
-
-File: as.info,  Node: Prefix Ops,  Next: Infix Ops,  Prev: Operators,  Up: Integer Exprs
-
-6.2.3 Prefix Operator
----------------------
-
-`as' has the following "prefix operators".  They each take one
-argument, which must be absolute.
-
-`-'
-     "Negation".  Two's complement negation.
-
-`~'
-     "Complementation".  Bitwise not.
-
-
-File: as.info,  Node: Infix Ops,  Prev: Prefix Ops,  Up: Integer Exprs
-
-6.2.4 Infix Operators
----------------------
-
-"Infix operators" take two arguments, one on either side.  Operators
-have precedence, but operations with equal precedence are performed left
-to right.  Apart from `+' or `-', both arguments must be absolute, and
-the result is absolute.
-
-  1. Highest Precedence
-
-    `*'
-          "Multiplication".
-
-    `/'
-          "Division".  Truncation is the same as the C operator `/'
-
-    `%'
-          "Remainder".
-
-    `<<'
-          "Shift Left".  Same as the C operator `<<'.
-
-    `>>'
-          "Shift Right".  Same as the C operator `>>'.
-
-  2. Intermediate precedence
-
-    `|'
-          "Bitwise Inclusive Or".
-
-    `&'
-          "Bitwise And".
-
-    `^'
-          "Bitwise Exclusive Or".
-
-    `!'
-          "Bitwise Or Not".
-
-  3. Low Precedence
-
-    `+'
-          "Addition".  If either argument is absolute, the result has
-          the section of the other argument.  You may not add together
-          arguments from different sections.
-
-    `-'
-          "Subtraction".  If the right argument is absolute, the result
-          has the section of the left argument.  If both arguments are
-          in the same section, the result is absolute.  You may not
-          subtract arguments from different sections.
-
-    `=='
-          "Is Equal To"
-
-    `<>'
-    `!='
-          "Is Not Equal To"
-
-    `<'
-          "Is Less Than"
-
-    `>'
-          "Is Greater Than"
-
-    `>='
-          "Is Greater Than Or Equal To"
-
-    `<='
-          "Is Less Than Or Equal To"
-
-          The comparison operators can be used as infix operators.  A
-          true results has a value of -1 whereas a false result has a
-          value of 0.   Note, these operators perform signed
-          comparisons.
-
-  4. Lowest Precedence
-
-    `&&'
-          "Logical And".
-
-    `||'
-          "Logical Or".
-
-          These two logical operations can be used to combine the
-          results of sub expressions.  Note, unlike the comparison
-          operators a true result returns a value of 1 but a false
-          results does still return 0.  Also note that the logical or
-          operator has a slightly lower precedence than logical and.
-
-
-   In short, it's only meaningful to add or subtract the _offsets_ in an
-address; you can only have a defined section in one of the two
-arguments.
-
-
-File: as.info,  Node: Pseudo Ops,  Next: Machine Dependencies,  Prev: Expressions,  Up: Top
-
-7 Assembler Directives
-**********************
-
-All assembler directives have names that begin with a period (`.').
-The rest of the name is letters, usually in lower case.
-
-   This chapter discusses directives that are available regardless of
-the target machine configuration for the GNU assembler.  Some machine
-configurations provide additional directives.  *Note Machine
-Dependencies::.
-
-* Menu:
-
-* Abort::                       `.abort'
-
-* ABORT::                       `.ABORT'
-
-* Align::                       `.align ABS-EXPR , ABS-EXPR'
-* Altmacro::                    `.altmacro'
-* Ascii::                       `.ascii "STRING"'...
-* Asciz::                       `.asciz "STRING"'...
-* Balign::                      `.balign ABS-EXPR , ABS-EXPR'
-* Byte::                        `.byte EXPRESSIONS'
-* Comm::                        `.comm SYMBOL , LENGTH '
-
-* CFI directives::		`.cfi_startproc', `.cfi_endproc', etc.
-
-* Data::                        `.data SUBSECTION'
-
-* Def::                         `.def NAME'
-
-* Desc::                        `.desc SYMBOL, ABS-EXPRESSION'
-
-* Dim::                         `.dim'
-
-* Double::                      `.double FLONUMS'
-* Eject::                       `.eject'
-* Else::                        `.else'
-* Elseif::                      `.elseif'
-* End::				`.end'
-
-* Endef::                       `.endef'
-
-* Endfunc::                     `.endfunc'
-* Endif::                       `.endif'
-* Equ::                         `.equ SYMBOL, EXPRESSION'
-* Equiv::                       `.equiv SYMBOL, EXPRESSION'
-* Eqv::                         `.eqv SYMBOL, EXPRESSION'
-* Err::				`.err'
-* Error::			`.error STRING'
-* Exitm::			`.exitm'
-* Extern::                      `.extern'
-* Fail::			`.fail'
-
-* File::                        `.file STRING'
-
-* Fill::                        `.fill REPEAT , SIZE , VALUE'
-* Float::                       `.float FLONUMS'
-* Func::                        `.func'
-* Global::                      `.global SYMBOL', `.globl SYMBOL'
-
-* Hidden::                      `.hidden NAMES'
-
-* hword::                       `.hword EXPRESSIONS'
-* Ident::                       `.ident'
-* If::                          `.if ABSOLUTE EXPRESSION'
-* Incbin::                      `.incbin "FILE"[,SKIP[,COUNT]]'
-* Include::                     `.include "FILE"'
-* Int::                         `.int EXPRESSIONS'
-
-* Internal::                    `.internal NAMES'
-
-* Irp::				`.irp SYMBOL,VALUES'...
-* Irpc::			`.irpc SYMBOL,VALUES'...
-* Lcomm::                       `.lcomm SYMBOL , LENGTH'
-* Lflags::                      `.lflags'
-
-* Line::                        `.line LINE-NUMBER'
-
-* Linkonce::			`.linkonce [TYPE]'
-* List::                        `.list'
-* Ln::                          `.ln LINE-NUMBER'
-
-* LNS directives::              `.file', `.loc', etc.
-
-* Long::                        `.long EXPRESSIONS'
-
-* Macro::			`.macro NAME ARGS'...
-* MRI::				`.mri VAL'
-* Noaltmacro::                  `.noaltmacro'
-* Nolist::                      `.nolist'
-* Octa::                        `.octa BIGNUMS'
-* Org::                         `.org NEW-LC , FILL'
-* P2align::                     `.p2align ABS-EXPR , ABS-EXPR'
-
-* PopSection::                  `.popsection'
-* Previous::                    `.previous'
-
-* Print::			`.print STRING'
-
-* Protected::                   `.protected NAMES'
-
-* Psize::                       `.psize LINES, COLUMNS'
-* Purgem::			`.purgem NAME'
-
-* PushSection::                 `.pushsection NAME'
-
-* Quad::                        `.quad BIGNUMS'
-* Rept::			`.rept COUNT'
-* Sbttl::                       `.sbttl "SUBHEADING"'
-
-* Scl::                         `.scl CLASS'
-
-* Section::                     `.section NAME'
-
-* Set::                         `.set SYMBOL, EXPRESSION'
-* Short::                       `.short EXPRESSIONS'
-* Single::                      `.single FLONUMS'
-
-* Size::                        `.size [NAME , EXPRESSION]'
-
-* Skip::                        `.skip SIZE , FILL'
-* Sleb128::			`.sleb128 EXPRESSIONS'
-* Space::                       `.space SIZE , FILL'
-
-* Stab::                        `.stabd, .stabn, .stabs'
-
-* String::                      `.string "STR"'
-* Struct::			`.struct EXPRESSION'
-
-* SubSection::                  `.subsection'
-* Symver::                      `.symver NAME,NAME2@NODENAME'
-
-
-* Tag::                         `.tag STRUCTNAME'
-
-* Text::                        `.text SUBSECTION'
-* Title::                       `.title "HEADING"'
-
-* Type::                        `.type <INT | NAME , TYPE DESCRIPTION>'
-
-* Uleb128::                     `.uleb128 EXPRESSIONS'
-
-* Val::                         `.val ADDR'
-
-
-* Version::                     `.version "STRING"'
-* VTableEntry::                 `.vtable_entry TABLE, OFFSET'
-* VTableInherit::               `.vtable_inherit CHILD, PARENT'
-
-* Warning::			`.warning STRING'
-* Weak::                        `.weak NAMES'
-* Weakref::                     `.weakref ALIAS, SYMBOL'
-* Word::                        `.word EXPRESSIONS'
-* Deprecated::                  Deprecated Directives
-
-
-File: as.info,  Node: Abort,  Next: ABORT,  Up: Pseudo Ops
-
-7.1 `.abort'
-============
-
-This directive stops the assembly immediately.  It is for compatibility
-with other assemblers.  The original idea was that the assembly
-language source would be piped into the assembler.  If the sender of
-the source quit, it could use this directive tells `as' to quit also.
-One day `.abort' will not be supported.
-
-
-File: as.info,  Node: ABORT,  Next: Align,  Prev: Abort,  Up: Pseudo Ops
-
-7.2 `.ABORT'
-============
-
-When producing COFF output, `as' accepts this directive as a synonym
-for `.abort'.
-
-
-File: as.info,  Node: Align,  Next: Altmacro,  Prev: ABORT,  Up: Pseudo Ops
-
-7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
-=========================================
-
-Pad the location counter (in the current subsection) to a particular
-storage boundary.  The first expression (which must be absolute) is the
-alignment required, as described below.
-
-   The second expression (also absolute) gives the fill value to be
-stored in the padding bytes.  It (and the comma) may be omitted.  If it
-is omitted, the padding bytes are normally zero.  However, on some
-systems, if the section is marked as containing code and the fill value
-is omitted, the space is filled with no-op instructions.
-
-   The third expression is also absolute, and is also optional.  If it
-is present, it is the maximum number of bytes that should be skipped by
-this alignment directive.  If doing the alignment would require
-skipping more bytes than the specified maximum, then the alignment is
-not done at all.  You can omit the fill value (the second argument)
-entirely by simply using two commas after the required alignment; this
-can be useful if you want the alignment to be filled with no-op
-instructions when appropriate.
-
-   The way the required alignment is specified varies from system to
-system.  For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
-s390, sparc, tic4x, tic80 and xtensa, the first expression is the
-alignment request in bytes.  For example `.align 8' advances the
-location counter until it is a multiple of 8.  If the location counter
-is already a multiple of 8, no change is needed.  For the tic54x, the
-first expression is the alignment request in words.
-
-   For other systems, including the i386 using a.out format, and the
-arm and strongarm, it is the number of low-order zero bits the location
-counter must have after advancement.  For example `.align 3' advances
-the location counter until it a multiple of 8.  If the location counter
-is already a multiple of 8, no change is needed.
-
-   This inconsistency is due to the different behaviors of the various
-native assemblers for these systems which GAS must emulate.  GAS also
-provides `.balign' and `.p2align' directives, described later, which
-have a consistent behavior across all architectures (but are specific
-to GAS).
-
-
-File: as.info,  Node: Ascii,  Next: Asciz,  Prev: Altmacro,  Up: Pseudo Ops
-
-7.4 `.ascii "STRING"'...
-========================
-
-`.ascii' expects zero or more string literals (*note Strings::)
-separated by commas.  It assembles each string (with no automatic
-trailing zero byte) into consecutive addresses.
-
-
-File: as.info,  Node: Asciz,  Next: Balign,  Prev: Ascii,  Up: Pseudo Ops
-
-7.5 `.asciz "STRING"'...
-========================
-
-`.asciz' is just like `.ascii', but each string is followed by a zero
-byte.  The "z" in `.asciz' stands for "zero".
-
-
-File: as.info,  Node: Balign,  Next: Byte,  Prev: Asciz,  Up: Pseudo Ops
-
-7.6 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
-==============================================
-
-Pad the location counter (in the current subsection) to a particular
-storage boundary.  The first expression (which must be absolute) is the
-alignment request in bytes.  For example `.balign 8' advances the
-location counter until it is a multiple of 8.  If the location counter
-is already a multiple of 8, no change is needed.
-
-   The second expression (also absolute) gives the fill value to be
-stored in the padding bytes.  It (and the comma) may be omitted.  If it
-is omitted, the padding bytes are normally zero.  However, on some
-systems, if the section is marked as containing code and the fill value
-is omitted, the space is filled with no-op instructions.
-
-   The third expression is also absolute, and is also optional.  If it
-is present, it is the maximum number of bytes that should be skipped by
-this alignment directive.  If doing the alignment would require
-skipping more bytes than the specified maximum, then the alignment is
-not done at all.  You can omit the fill value (the second argument)
-entirely by simply using two commas after the required alignment; this
-can be useful if you want the alignment to be filled with no-op
-instructions when appropriate.
-
-   The `.balignw' and `.balignl' directives are variants of the
-`.balign' directive.  The `.balignw' directive treats the fill pattern
-as a two byte word value.  The `.balignl' directives treats the fill
-pattern as a four byte longword value.  For example, `.balignw
-4,0x368d' will align to a multiple of 4.  If it skips two bytes, they
-will be filled in with the value 0x368d (the exact placement of the
-bytes depends upon the endianness of the processor).  If it skips 1 or
-3 bytes, the fill value is undefined.
-
-
-File: as.info,  Node: Byte,  Next: Comm,  Prev: Balign,  Up: Pseudo Ops
-
-7.7 `.byte EXPRESSIONS'
-=======================
-
-`.byte' expects zero or more expressions, separated by commas.  Each
-expression is assembled into the next byte.
-
-
-File: as.info,  Node: Comm,  Next: CFI directives,  Prev: Byte,  Up: Pseudo Ops
-
-7.8 `.comm SYMBOL , LENGTH '
-============================
-
-`.comm' declares a common symbol named SYMBOL.  When linking, a common
-symbol in one object file may be merged with a defined or common symbol
-of the same name in another object file.  If `ld' does not see a
-definition for the symbol-just one or more common symbols-then it will
-allocate LENGTH bytes of uninitialized memory.  LENGTH must be an
-absolute expression.  If `ld' sees multiple common symbols with the
-same name, and they do not all have the same size, it will allocate
-space using the largest size.
-
-   When using ELF, the `.comm' directive takes an optional third
-argument.  This is the desired alignment of the symbol, specified as a
-byte boundary (for example, an alignment of 16 means that the least
-significant 4 bits of the address should be zero).  The alignment must
-be an absolute expression, and it must be a power of two.  If `ld'
-allocates uninitialized memory for the common symbol, it will use the
-alignment when placing the symbol.  If no alignment is specified, `as'
-will set the alignment to the largest power of two less than or equal
-to the size of the symbol, up to a maximum of 16.
-
-   The syntax for `.comm' differs slightly on the HPPA.  The syntax is
-`SYMBOL .comm, LENGTH'; SYMBOL is optional.
-
-
-File: as.info,  Node: CFI directives,  Next: Data,  Prev: Comm,  Up: Pseudo Ops
-
-7.9 `.cfi_startproc'
-====================
-
-`.cfi_startproc' is used at the beginning of each function that should
-have an entry in `.eh_frame'. It initializes some internal data
-structures and emits architecture dependent initial CFI instructions.
-Don't forget to close the function by `.cfi_endproc'.
-
-7.10 `.cfi_endproc'
-===================
-
-`.cfi_endproc' is used at the end of a function where it closes its
-unwind entry previously opened by `.cfi_startproc'. and emits it to
-`.eh_frame'.
-
-7.11 `.cfi_def_cfa REGISTER, OFFSET'
-====================================
-
-`.cfi_def_cfa' defines a rule for computing CFA as: take address from
-REGISTER and add OFFSET to it.
-
-7.12 `.cfi_def_cfa_register REGISTER'
-=====================================
-
-`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
-REGISTER will be used instead of the old one. Offset remains the same.
-
-7.13 `.cfi_def_cfa_offset OFFSET'
-=================================
-
-`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
-remains the same, but OFFSET is new. Note that it is the absolute
-offset that will be added to a defined register to compute CFA address.
-
-7.14 `.cfi_adjust_cfa_offset OFFSET'
-====================================
-
-Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
-added/substracted from the previous offset.
-
-7.15 `.cfi_offset REGISTER, OFFSET'
-===================================
-
-Previous value of REGISTER is saved at offset OFFSET from CFA.
-
-7.16 `.cfi_rel_offset REGISTER, OFFSET'
-=======================================
-
-Previous value of REGISTER is saved at offset OFFSET from the current
-CFA register.  This is transformed to `.cfi_offset' using the known
-displacement of the CFA register from the CFA.  This is often easier to
-use, because the number will match the code it's annotating.
-
-7.17 `.cfi_signal_frame'
-========================
-
-Mark current function as signal trampoline.
-
-7.18 `.cfi_window_save'
-=======================
-
-SPARC register window has been saved.
-
-7.19 `.cfi_escape' EXPRESSION[, ...]
-====================================
-
-Allows the user to add arbitrary bytes to the unwind info.  One might
-use this to add OS-specific CFI opcodes, or generic CFI opcodes that
-GAS does not yet support.
-
-
-File: as.info,  Node: LNS directives,  Next: Long,  Prev: Ln,  Up: Pseudo Ops
-
-7.20 `.file FILENO FILENAME'
-============================
-
-When emitting dwarf2 line number information `.file' assigns filenames
-to the `.debug_line' file name table.  The FILENO operand should be a
-unique positive integer to use as the index of the entry in the table.
-The FILENAME operand is a C string literal.
-
-   The detail of filename indicies is exposed to the user because the
-filename table is shared with the `.debug_info' section of the dwarf2
-debugging information, and thus the user must know the exact indicies
-that table entries will have.
-
-7.21 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
-============================================
-
-The `.loc' directive will add row to the `.debug_line' line number
-matrix corresponding to the immediately following assembly instruction.
-The FILENO, LINENO, and optional COLUMN arguments will be applied to
-the `.debug_line' state machine before the row is added.
-
-   The OPTIONS are a sequence of the following tokens in any order:
-
-`basic_block'
-     This option will set the `basic_block' register in the
-     `.debug_line' state machine to `true'.
-
-`prologue_end'
-     This option will set the `prologue_end' register in the
-     `.debug_line' state machine to `true'.
-
-`epilogue_begin'
-     This option will set the `epilogue_begin' register in the
-     `.debug_line' state machine to `true'.
-
-`is_stmt VALUE'
-     This option will set the `is_stmt' register in the `.debug_line'
-     state machine to `value', which must be either 0 or 1.
-
-`isa VALUE'
-     This directive will set the `isa' register in the `.debug_line'
-     state machine to VALUE, which must be an unsigned integer.
-
-
-7.22 `.loc_mark_blocks ENABLE'
-==============================
-
-The `.loc_mark_blocks' directive makes the assembler emit an entry to
-the `.debug_line' line number matrix with the `basic_block' register in
-the state machine set whenever a code label is seen.  The ENABLE
-argument should be either 1 or 0, to enable or disable this function
-respectively.
-
-
-File: as.info,  Node: Data,  Next: Def,  Prev: CFI directives,  Up: Pseudo Ops
-
-7.23 `.data SUBSECTION'
-=======================
-
-`.data' tells `as' to assemble the following statements onto the end of
-the data subsection numbered SUBSECTION (which is an absolute
-expression).  If SUBSECTION is omitted, it defaults to zero.
-
-
-File: as.info,  Node: Def,  Next: Desc,  Prev: Data,  Up: Pseudo Ops
-
-7.24 `.def NAME'
-================
-
-Begin defining debugging information for a symbol NAME; the definition
-extends until the `.endef' directive is encountered.
-
-
-File: as.info,  Node: Desc,  Next: Dim,  Prev: Def,  Up: Pseudo Ops
-
-7.25 `.desc SYMBOL, ABS-EXPRESSION'
-===================================
-
-This directive sets the descriptor of the symbol (*note Symbol
-Attributes::) to the low 16 bits of an absolute expression.
-
-   The `.desc' directive is not available when `as' is configured for
-COFF output; it is only for `a.out' or `b.out' object format.  For the
-sake of compatibility, `as' accepts it, but produces no output, when
-configured for COFF.
-
-
-File: as.info,  Node: Dim,  Next: Double,  Prev: Desc,  Up: Pseudo Ops
-
-7.26 `.dim'
-===========
-
-This directive is generated by compilers to include auxiliary debugging
-information in the symbol table.  It is only permitted inside
-`.def'/`.endef' pairs.
-
-
-File: as.info,  Node: Double,  Next: Eject,  Prev: Dim,  Up: Pseudo Ops
-
-7.27 `.double FLONUMS'
-======================
-
-`.double' expects zero or more flonums, separated by commas.  It
-assembles floating point numbers.  The exact kind of floating point
-numbers emitted depends on how `as' is configured.  *Note Machine
-Dependencies::.
-
-
-File: as.info,  Node: Eject,  Next: Else,  Prev: Double,  Up: Pseudo Ops
-
-7.28 `.eject'
-=============
-
-Force a page break at this point, when generating assembly listings.
-
-
-File: as.info,  Node: Else,  Next: Elseif,  Prev: Eject,  Up: Pseudo Ops
-
-7.29 `.else'
-============
-
-`.else' is part of the `as' support for conditional assembly; *note
-`.if': If.  It marks the beginning of a section of code to be assembled
-if the condition for the preceding `.if' was false.
-
-
-File: as.info,  Node: Elseif,  Next: End,  Prev: Else,  Up: Pseudo Ops
-
-7.30 `.elseif'
-==============
-
-`.elseif' is part of the `as' support for conditional assembly; *note
-`.if': If.  It is shorthand for beginning a new `.if' block that would
-otherwise fill the entire `.else' section.
-
-
-File: as.info,  Node: End,  Next: Endef,  Prev: Elseif,  Up: Pseudo Ops
-
-7.31 `.end'
-===========
-
-`.end' marks the end of the assembly file.  `as' does not process
-anything in the file past the `.end' directive.
-
-
-File: as.info,  Node: Endef,  Next: Endfunc,  Prev: End,  Up: Pseudo Ops
-
-7.32 `.endef'
-=============
-
-This directive flags the end of a symbol definition begun with `.def'.
-
-
-File: as.info,  Node: Endfunc,  Next: Endif,  Prev: Endef,  Up: Pseudo Ops
-
-7.33 `.endfunc'
-===============
-
-`.endfunc' marks the end of a function specified with `.func'.
-
-
-File: as.info,  Node: Endif,  Next: Equ,  Prev: Endfunc,  Up: Pseudo Ops
-
-7.34 `.endif'
-=============
-
-`.endif' is part of the `as' support for conditional assembly; it marks
-the end of a block of code that is only assembled conditionally.  *Note
-`.if': If.
-
-
-File: as.info,  Node: Equ,  Next: Equiv,  Prev: Endif,  Up: Pseudo Ops
-
-7.35 `.equ SYMBOL, EXPRESSION'
-==============================
-
-This directive sets the value of SYMBOL to EXPRESSION.  It is
-synonymous with `.set'; *note `.set': Set.
-
-   The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.
-
-   The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'.  On the
-Z80 it is an eror if SYMBOL is already defined, but the symbol is not
-protected from later redefinition, compare *Note Equiv::.
-
-
-File: as.info,  Node: Equiv,  Next: Eqv,  Prev: Equ,  Up: Pseudo Ops
-
-7.36 `.equiv SYMBOL, EXPRESSION'
-================================
-
-The `.equiv' directive is like `.equ' and `.set', except that the
-assembler will signal an error if SYMBOL is already defined.  Note a
-symbol which has been referenced but not actually defined is considered
-to be undefined.
-
-   Except for the contents of the error message, this is roughly
-equivalent to
-     .ifdef SYM
-     .err
-     .endif
-     .equ SYM,VAL
-   plus it protects the symbol from later redefinition.
-
-
-File: as.info,  Node: Eqv,  Next: Err,  Prev: Equiv,  Up: Pseudo Ops
-
-7.37 `.eqv SYMBOL, EXPRESSION'
-==============================
-
-The `.eqv' directive is like `.equiv', but no attempt is made to
-evaluate the expression or any part of it immediately.  Instead each
-time the resulting symbol is used in an expression, a snapshot of its
-current value is taken.
-
-
-File: as.info,  Node: Err,  Next: Error,  Prev: Eqv,  Up: Pseudo Ops
-
-7.38 `.err'
-===========
-
-If `as' assembles a `.err' directive, it will print an error message
-and, unless the `-Z' option was used, it will not generate an object
-file.  This can be used to signal an error in conditionally compiled
-code.
-
-
-File: as.info,  Node: Error,  Next: Exitm,  Prev: Err,  Up: Pseudo Ops
-
-7.39 `.error "STRING"'
-======================
-
-Similarly to `.err', this directive emits an error, but you can specify
-a string that will be emitted as the error message.  If you don't
-specify the message, it defaults to `".error directive invoked in
-source file"'.  *Note Error and Warning Messages: Errors.
-
-      .error "This code has not been assembled and tested."
-
-
-File: as.info,  Node: Exitm,  Next: Extern,  Prev: Error,  Up: Pseudo Ops
-
-7.40 `.exitm'
-=============
-
-Exit early from the current macro definition.  *Note Macro::.
-
-
-File: as.info,  Node: Extern,  Next: Fail,  Prev: Exitm,  Up: Pseudo Ops
-
-7.41 `.extern'
-==============
-
-`.extern' is accepted in the source program--for compatibility with
-other assemblers--but it is ignored.  `as' treats all undefined symbols
-as external.
-
-
-File: as.info,  Node: Fail,  Next: File,  Prev: Extern,  Up: Pseudo Ops
-
-7.42 `.fail EXPRESSION'
-=======================
-
-Generates an error or a warning.  If the value of the EXPRESSION is 500
-or more, `as' will print a warning message.  If the value is less than
-500, `as' will print an error message.  The message will include the
-value of EXPRESSION.  This can occasionally be useful inside complex
-nested macros or conditional assembly.
-
-
-File: as.info,  Node: File,  Next: Fill,  Prev: Fail,  Up: Pseudo Ops
-
-7.43 `.file STRING'
-===================
-
-`.file' tells `as' that we are about to start a new logical file.
-STRING is the new file name.  In general, the filename is recognized
-whether or not it is surrounded by quotes `"'; but if you wish to
-specify an empty file name, you must give the quotes-`""'.  This
-statement may go away in future: it is only recognized to be compatible
-with old `as' programs.
-
-
-File: as.info,  Node: Fill,  Next: Float,  Prev: File,  Up: Pseudo Ops
-
-7.44 `.fill REPEAT , SIZE , VALUE'
-==================================
-
-REPEAT, SIZE and VALUE are absolute expressions.  This emits REPEAT
-copies of SIZE bytes.  REPEAT may be zero or more.  SIZE may be zero or
-more, but if it is more than 8, then it is deemed to have the value 8,
-compatible with other people's assemblers.  The contents of each REPEAT
-bytes is taken from an 8-byte number.  The highest order 4 bytes are
-zero.  The lowest order 4 bytes are VALUE rendered in the byte-order of
-an integer on the computer `as' is assembling for.  Each SIZE bytes in
-a repetition is taken from the lowest order SIZE bytes of this number.
-Again, this bizarre behavior is compatible with other people's
-assemblers.
-
-   SIZE and VALUE are optional.  If the second comma and VALUE are
-absent, VALUE is assumed zero.  If the first comma and following tokens
-are absent, SIZE is assumed to be 1.
-
-
-File: as.info,  Node: Float,  Next: Func,  Prev: Fill,  Up: Pseudo Ops
-
-7.45 `.float FLONUMS'
-=====================
-
-This directive assembles zero or more flonums, separated by commas.  It
-has the same effect as `.single'.  The exact kind of floating point
-numbers emitted depends on how `as' is configured.  *Note Machine
-Dependencies::.
-
-
-File: as.info,  Node: Func,  Next: Global,  Prev: Float,  Up: Pseudo Ops
-
-7.46 `.func NAME[,LABEL]'
-=========================
-
-`.func' emits debugging information to denote function NAME, and is
-ignored unless the file is assembled with debugging enabled.  Only
-`--gstabs[+]' is currently supported.  LABEL is the entry point of the
-function and if omitted NAME prepended with the `leading char' is used.
-`leading char' is usually `_' or nothing, depending on the target.  All
-functions are currently defined to have `void' return type.  The
-function must be terminated with `.endfunc'.
-
-
-File: as.info,  Node: Global,  Next: Hidden,  Prev: Func,  Up: Pseudo Ops
-
-7.47 `.global SYMBOL', `.globl SYMBOL'
-======================================
-
-`.global' makes the symbol visible to `ld'.  If you define SYMBOL in
-your partial program, its value is made available to other partial
-programs that are linked with it.  Otherwise, SYMBOL takes its
-attributes from a symbol of the same name from another file linked into
-the same program.
-
-   Both spellings (`.globl' and `.global') are accepted, for
-compatibility with other assemblers.
-
-   On the HPPA, `.global' is not always enough to make it accessible to
-other partial programs.  You may need the HPPA-only `.EXPORT' directive
-as well.  *Note HPPA Assembler Directives: HPPA Directives.
-
-
-File: as.info,  Node: Hidden,  Next: hword,  Prev: Global,  Up: Pseudo Ops
-
-7.48 `.hidden NAMES'
-====================
-
-This is one of the ELF visibility directives.  The other two are
-`.internal' (*note `.internal': Internal.) and `.protected' (*note
-`.protected': Protected.).
-
-   This directive overrides the named symbols default visibility (which
-is set by their binding: local, global or weak).  The directive sets
-the visibility to `hidden' which means that the symbols are not visible
-to other components.  Such symbols are always considered to be
-`protected' as well.
-
-
-File: as.info,  Node: hword,  Next: Ident,  Prev: Hidden,  Up: Pseudo Ops
-
-7.49 `.hword EXPRESSIONS'
-=========================
-
-This expects zero or more EXPRESSIONS, and emits a 16 bit number for
-each.
-
-   This directive is a synonym for `.short'; depending on the target
-architecture, it may also be a synonym for `.word'.
-
-
-File: as.info,  Node: Ident,  Next: If,  Prev: hword,  Up: Pseudo Ops
-
-7.50 `.ident'
-=============
-
-This directive is used by some assemblers to place tags in object
-files.  The behavior of this directive varies depending on the target.
-When using the a.out object file format, `as' simply accepts the
-directive for source-file compatibility with existing assemblers, but
-does not emit anything for it.  When using COFF, comments are emitted
-to the `.comment' or `.rdata' section, depending on the target.  When
-using ELF, comments are emitted to the `.comment' section.
-
-
-File: as.info,  Node: If,  Next: Incbin,  Prev: Ident,  Up: Pseudo Ops
-
-7.51 `.if ABSOLUTE EXPRESSION'
-==============================
-
-`.if' marks the beginning of a section of code which is only considered
-part of the source program being assembled if the argument (which must
-be an ABSOLUTE EXPRESSION) is non-zero.  The end of the conditional
-section of code must be marked by `.endif' (*note `.endif': Endif.);
-optionally, you may include code for the alternative condition, flagged
-by `.else' (*note `.else': Else.).  If you have several conditions to
-check, `.elseif' may be used to avoid nesting blocks if/else within
-each subsequent `.else' block.
-
-   The following variants of `.if' are also supported:
-`.ifdef SYMBOL'
-     Assembles the following section of code if the specified SYMBOL
-     has been defined.  Note a symbol which has been referenced but not
-     yet defined is considered to be undefined.
-
-`.ifb TEXT'
-     Assembles the following section of code if the operand is blank
-     (empty).
-
-`.ifc STRING1,STRING2'
-     Assembles the following section of code if the two strings are the
-     same.  The strings may be optionally quoted with single quotes.
-     If they are not quoted, the first string stops at the first comma,
-     and the second string stops at the end of the line.  Strings which
-     contain whitespace should be quoted.  The string comparison is
-     case sensitive.
-
-`.ifeq ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is zero.
-
-`.ifeqs STRING1,STRING2'
-     Another form of `.ifc'.  The strings must be quoted using double
-     quotes.
-
-`.ifge ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is greater
-     than or equal to zero.
-
-`.ifgt ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is greater
-     than zero.
-
-`.ifle ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is less
-     than or equal to zero.
-
-`.iflt ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is less
-     than zero.
-
-`.ifnb TEXT'
-     Like `.ifb', but the sense of the test is reversed: this assembles
-     the following section of code if the operand is non-blank
-     (non-empty).
-
-`.ifnc STRING1,STRING2.'
-     Like `.ifc', but the sense of the test is reversed: this assembles
-     the following section of code if the two strings are not the same.
-
-`.ifndef SYMBOL'
-`.ifnotdef SYMBOL'
-     Assembles the following section of code if the specified SYMBOL
-     has not been defined.  Both spelling variants are equivalent.
-     Note a symbol which has been referenced but not yet defined is
-     considered to be undefined.
-
-`.ifne ABSOLUTE EXPRESSION'
-     Assembles the following section of code if the argument is not
-     equal to zero (in other words, this is equivalent to `.if').
-
-`.ifnes STRING1,STRING2'
-     Like `.ifeqs', but the sense of the test is reversed: this
-     assembles the following section of code if the two strings are not
-     the same.
-
-
-File: as.info,  Node: Incbin,  Next: Include,  Prev: If,  Up: Pseudo Ops
-
-7.52 `.incbin "FILE"[,SKIP[,COUNT]]'
-====================================
-
-The `incbin' directive includes FILE verbatim at the current location.
-You can control the search paths used with the `-I' command-line option
-(*note Command-Line Options: Invoking.).  Quotation marks are required
-around FILE.
-
-   The SKIP argument skips a number of bytes from the start of the
-FILE.  The COUNT argument indicates the maximum number of bytes to
-read.  Note that the data is not aligned in any way, so it is the user's
-responsibility to make sure that proper alignment is provided both
-before and after the `incbin' directive.
-
-
-File: as.info,  Node: Include,  Next: Int,  Prev: Incbin,  Up: Pseudo Ops
-
-7.53 `.include "FILE"'
-======================
-
-This directive provides a way to include supporting files at specified
-points in your source program.  The code from FILE is assembled as if
-it followed the point of the `.include'; when the end of the included
-file is reached, assembly of the original file continues.  You can
-control the search paths used with the `-I' command-line option (*note
-Command-Line Options: Invoking.).  Quotation marks are required around
-FILE.
-
-
-File: as.info,  Node: Int,  Next: Internal,  Prev: Include,  Up: Pseudo Ops
-
-7.54 `.int EXPRESSIONS'
-=======================
-
-Expect zero or more EXPRESSIONS, of any section, separated by commas.
-For each expression, emit a number that, at run time, is the value of
-that expression.  The byte order and bit size of the number depends on
-what kind of target the assembly is for.
-
-
-File: as.info,  Node: Internal,  Next: Irp,  Prev: Int,  Up: Pseudo Ops
-
-7.55 `.internal NAMES'
-======================
-
-This is one of the ELF visibility directives.  The other two are
-`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note
-`.protected': Protected.).
-
-   This directive overrides the named symbols default visibility (which
-is set by their binding: local, global or weak).  The directive sets
-the visibility to `internal' which means that the symbols are
-considered to be `hidden' (i.e., not visible to other components), and
-that some extra, processor specific processing must also be performed
-upon the  symbols as well.
-
-
-File: as.info,  Node: Irp,  Next: Irpc,  Prev: Internal,  Up: Pseudo Ops
-
-7.56 `.irp SYMBOL,VALUES'...
-============================
-
-Evaluate a sequence of statements assigning different values to SYMBOL.
-The sequence of statements starts at the `.irp' directive, and is
-terminated by an `.endr' directive.  For each VALUE, SYMBOL is set to
-VALUE, and the sequence of statements is assembled.  If no VALUE is
-listed, the sequence of statements is assembled once, with SYMBOL set
-to the null string.  To refer to SYMBOL within the sequence of
-statements, use \SYMBOL.
-
-   For example, assembling
-
-             .irp    param,1,2,3
-             move    d\param,sp@-
-             .endr
-
-   is equivalent to assembling
-
-             move    d1,sp@-
-             move    d2,sp@-
-             move    d3,sp@-
-
-   For some caveats with the spelling of SYMBOL, see also the discussion
-at *Note Macro::.
-
-
-File: as.info,  Node: Irpc,  Next: Lcomm,  Prev: Irp,  Up: Pseudo Ops
-
-7.57 `.irpc SYMBOL,VALUES'...
-=============================
-
-Evaluate a sequence of statements assigning different values to SYMBOL.
-The sequence of statements starts at the `.irpc' directive, and is
-terminated by an `.endr' directive.  For each character in VALUE,
-SYMBOL is set to the character, and the sequence of statements is
-assembled.  If no VALUE is listed, the sequence of statements is
-assembled once, with SYMBOL set to the null string.  To refer to SYMBOL
-within the sequence of statements, use \SYMBOL.
-
-   For example, assembling
-
-             .irpc    param,123
-             move    d\param,sp@-
-             .endr
-
-   is equivalent to assembling
-
-             move    d1,sp@-
-             move    d2,sp@-
-             move    d3,sp@-
-
-   For some caveats with the spelling of SYMBOL, see also the discussion
-at *Note Macro::.
-
-
-File: as.info,  Node: Lcomm,  Next: Lflags,  Prev: Irpc,  Up: Pseudo Ops
-
-7.58 `.lcomm SYMBOL , LENGTH'
-=============================
-
-Reserve LENGTH (an absolute expression) bytes for a local common
-denoted by SYMBOL.  The section and value of SYMBOL are those of the
-new local common.  The addresses are allocated in the bss section, so
-that at run-time the bytes start off zeroed.  SYMBOL is not declared
-global (*note `.global': Global.), so is normally not visible to `ld'.
-
-   Some targets permit a third argument to be used with `.lcomm'.  This
-argument specifies the desired alignment of the symbol in the bss
-section.
-
-   The syntax for `.lcomm' differs slightly on the HPPA.  The syntax is
-`SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
-
-
-File: as.info,  Node: Lflags,  Next: Line,  Prev: Lcomm,  Up: Pseudo Ops
-
-7.59 `.lflags'
-==============
-
-`as' accepts this directive, for compatibility with other assemblers,
-but ignores it.
-
-
-File: as.info,  Node: Line,  Next: Linkonce,  Prev: Lflags,  Up: Pseudo Ops
-
-7.60 `.line LINE-NUMBER'
-========================
-
-   Change the logical line number.  LINE-NUMBER must be an absolute
-expression.  The next line has that logical line number.  Therefore any
-other statements on the current line (after a statement separator
-character) are reported as on logical line number LINE-NUMBER - 1.  One
-day `as' will no longer support this directive: it is recognized only
-for compatibility with existing assembler programs.
-
-   Even though this is a directive associated with the `a.out' or
-`b.out' object-code formats, `as' still recognizes it when producing
-COFF output, and treats `.line' as though it were the COFF `.ln' _if_
-it is found outside a `.def'/`.endef' pair.
-
-   Inside a `.def', `.line' is, instead, one of the directives used by
-compilers to generate auxiliary symbol information for debugging.
-
-
-File: as.info,  Node: Linkonce,  Next: List,  Prev: Line,  Up: Pseudo Ops
-
-7.61 `.linkonce [TYPE]'
-=======================
-
-Mark the current section so that the linker only includes a single copy
-of it.  This may be used to include the same section in several
-different object files, but ensure that the linker will only include it
-once in the final output file.  The `.linkonce' pseudo-op must be used
-for each instance of the section.  Duplicate sections are detected
-based on the section name, so it should be unique.
-
-   This directive is only supported by a few object file formats; as of
-this writing, the only object file format which supports it is the
-Portable Executable format used on Windows NT.
-
-   The TYPE argument is optional.  If specified, it must be one of the
-following strings.  For example:
-     .linkonce same_size
-   Not all types may be supported on all object file formats.
-
-`discard'
-     Silently discard duplicate sections.  This is the default.
-
-`one_only'
-     Warn if there are duplicate sections, but still keep only one copy.
-
-`same_size'
-     Warn if any of the duplicates have different sizes.
-
-`same_contents'
-     Warn if any of the duplicates do not have exactly the same
-     contents.
-
-
-File: as.info,  Node: Ln,  Next: LNS directives,  Prev: List,  Up: Pseudo Ops
-
-7.62 `.ln LINE-NUMBER'
-======================
-
-`.ln' is a synonym for `.line'.
-
-
-File: as.info,  Node: MRI,  Next: Noaltmacro,  Prev: Macro,  Up: Pseudo Ops
-
-7.63 `.mri VAL'
-===============
-
-If VAL is non-zero, this tells `as' to enter MRI mode.  If VAL is zero,
-this tells `as' to exit MRI mode.  This change affects code assembled
-until the next `.mri' directive, or until the end of the file.  *Note
-MRI mode: M.
-
-
-File: as.info,  Node: List,  Next: Ln,  Prev: Linkonce,  Up: Pseudo Ops
-
-7.64 `.list'
-============
-
-Control (in conjunction with the `.nolist' directive) whether or not
-assembly listings are generated.  These two directives maintain an
-internal counter (which is zero initially).   `.list' increments the
-counter, and `.nolist' decrements it.  Assembly listings are generated
-whenever the counter is greater than zero.
-
-   By default, listings are disabled.  When you enable them (with the
-`-a' command line option; *note Command-Line Options: Invoking.), the
-initial value of the listing counter is one.
-
-
-File: as.info,  Node: Long,  Next: Macro,  Prev: LNS directives,  Up: Pseudo Ops
-
-7.65 `.long EXPRESSIONS'
-========================
-
-`.long' is the same as `.int', *note `.int': Int.
-
-
-File: as.info,  Node: Macro,  Next: MRI,  Prev: Long,  Up: Pseudo Ops
-
-7.66 `.macro'
-=============
-
-The commands `.macro' and `.endm' allow you to define macros that
-generate assembly output.  For example, this definition specifies a
-macro `sum' that puts a sequence of numbers into memory:
-
-             .macro  sum from=0, to=5
-             .long   \from
-             .if     \to-\from
-             sum     "(\from+1)",\to
-             .endif
-             .endm
-
-With that definition, `SUM 0,5' is equivalent to this assembly input:
-
-             .long   0
-             .long   1
-             .long   2
-             .long   3
-             .long   4
-             .long   5
-
-`.macro MACNAME'
-`.macro MACNAME MACARGS ...'
-     Begin the definition of a macro called MACNAME.  If your macro
-     definition requires arguments, specify their names after the macro
-     name, separated by commas or spaces.  You can qualify the macro
-     argument to indicate whether all invocations must specify a
-     non-blank value (through `:`req''), or whether it takes all of the
-     remaining arguments (through `:`vararg'').  You can supply a
-     default value for any macro argument by following the name with
-     `=DEFLT'.  You cannot define two macros with the same MACNAME
-     unless it has been subject to the `.purgem' directive (*Note
-     Purgem::.) between the two definitions.  For example, these are
-     all valid `.macro' statements:
-
-    `.macro comm'
-          Begin the definition of a macro called `comm', which takes no
-          arguments.
-
-    `.macro plus1 p, p1'
-    `.macro plus1 p p1'
-          Either statement begins the definition of a macro called
-          `plus1', which takes two arguments; within the macro
-          definition, write `\p' or `\p1' to evaluate the arguments.
-
-    `.macro reserve_str p1=0 p2'
-          Begin the definition of a macro called `reserve_str', with two
-          arguments.  The first argument has a default value, but not
-          the second.  After the definition is complete, you can call
-          the macro either as `reserve_str A,B' (with `\p1' evaluating
-          to A and `\p2' evaluating to B), or as `reserve_str ,B' (with
-          `\p1' evaluating as the default, in this case `0', and `\p2'
-          evaluating to B).
-
-`.macro m p1:req, p2=0, p3:vararg'
-     Begin the definition of a macro called `m', with at least three
-     arguments.  The first argument must always have a value specified,
-     but not the second, which instead has a default value. The third
-     formal will get assigned all remaining arguments specified at
-     invocation time.
-
-     When you call a macro, you can specify the argument values either
-     by position, or by keyword.  For example, `sum 9,17' is equivalent
-     to `sum to=17, from=9'.
-
-     Note that since each of the MACARGS can be an identifier exactly
-     as any other one permitted by the target architecture, there may be
-     occasional problems if the target hand-crafts special meanings to
-     certain characters when they occur in a special position.  For
-     example, if colon (`:') is generally permitted to be part of a
-     symbol name, but the architecture specific code special-cases it
-     when occuring as the final character of a symbol (to denote a
-     label), then the macro parameter replacement code will have no way
-     of knowing that and consider the whole construct (including the
-     colon) an identifier, and check only this identifier for being the
-     subject to parameter substitution.  In this example, besides the
-     potential of just separating identifier and colon by white space,
-     using alternate macro syntax (*Note Altmacro::.) and ampersand
-     (`&') as the character to separate literal text from macro
-     parameters (or macro parameters from one another) would provide a
-     way to achieve the same effect:
-
-          	.altmacro
-          	.macro label l
-          l&:
-          	.endm
-
-     This applies identically to the identifiers used in `.irp' (*Note
-     Irp::.)  and `.irpc' (*Note Irpc::.).
-
-`.endm'
-     Mark the end of a macro definition.
-
-`.exitm'
-     Exit early from the current macro definition.
-
-`\@'
-     `as' maintains a counter of how many macros it has executed in
-     this pseudo-variable; you can copy that number to your output with
-     `\@', but _only within a macro definition_.
-
-`LOCAL NAME [ , ... ]'
-     _Warning: `LOCAL' is only available if you select "alternate macro
-     syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro':
-     Altmacro.
-
-
-File: as.info,  Node: Altmacro,  Next: Ascii,  Prev: Align,  Up: Pseudo Ops
-
-7.67 `.altmacro'
-================
-
-Enable alternate macro mode, enabling:
-
-`LOCAL NAME [ , ... ]'
-     One additional directive, `LOCAL', is available.  It is used to
-     generate a string replacement for each of the NAME arguments, and
-     replace any instances of NAME in each macro expansion.  The
-     replacement string is unique in the assembly, and different for
-     each separate macro expansion.  `LOCAL' allows you to write macros
-     that define symbols, without fear of conflict between separate
-     macro expansions.
-
-`String delimiters'
-     You can write strings delimited in these other ways besides
-     `"STRING"':
-
-    `'STRING''
-          You can delimit strings with single-quote charaters.
-
-    `<STRING>'
-          You can delimit strings with matching angle brackets.
-
-`single-character string escape'
-     To include any single character literally in a string (even if the
-     character would otherwise have some special meaning), you can
-     prefix the character with `!' (an exclamation mark).  For example,
-     you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
-     5.4!'.
-
-`Expression results as strings'
-     You can write `%EXPR' to evaluate the expression EXPR and use the
-     result as a string.
-
-
-File: as.info,  Node: Noaltmacro,  Next: Nolist,  Prev: MRI,  Up: Pseudo Ops
-
-7.68 `.noaltmacro'
-==================
-
-Disable alternate macro mode.  *Note Altmacro::
-
-
-File: as.info,  Node: Nolist,  Next: Octa,  Prev: Noaltmacro,  Up: Pseudo Ops
-
-7.69 `.nolist'
-==============
-
-Control (in conjunction with the `.list' directive) whether or not
-assembly listings are generated.  These two directives maintain an
-internal counter (which is zero initially).   `.list' increments the
-counter, and `.nolist' decrements it.  Assembly listings are generated
-whenever the counter is greater than zero.
-
-
-File: as.info,  Node: Octa,  Next: Org,  Prev: Nolist,  Up: Pseudo Ops
-
-7.70 `.octa BIGNUMS'
-====================
-
-This directive expects zero or more bignums, separated by commas.  For
-each bignum, it emits a 16-byte integer.
-
-   The term "octa" comes from contexts in which a "word" is two bytes;
-hence _octa_-word for 16 bytes.
-
-
-File: as.info,  Node: Org,  Next: P2align,  Prev: Octa,  Up: Pseudo Ops
-
-7.71 `.org NEW-LC , FILL'
-=========================
-
-Advance the location counter of the current section to NEW-LC.  NEW-LC
-is either an absolute expression or an expression with the same section
-as the current subsection.  That is, you can't use `.org' to cross
-sections: if NEW-LC has the wrong section, the `.org' directive is
-ignored.  To be compatible with former assemblers, if the section of
-NEW-LC is absolute, `as' issues a warning, then pretends the section of
-NEW-LC is the same as the current subsection.
-
-   `.org' may only increase the location counter, or leave it
-unchanged; you cannot use `.org' to move the location counter backwards.
-
-   Because `as' tries to assemble programs in one pass, NEW-LC may not
-be undefined.  If you really detest this restriction we eagerly await a
-chance to share your improved assembler.
-
-   Beware that the origin is relative to the start of the section, not
-to the start of the subsection.  This is compatible with other people's
-assemblers.
-
-   When the location counter (of the current subsection) is advanced,
-the intervening bytes are filled with FILL which should be an absolute
-expression.  If the comma and FILL are omitted, FILL defaults to zero.
-
-
-File: as.info,  Node: P2align,  Next: PopSection,  Prev: Org,  Up: Pseudo Ops
-
-7.72 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
-================================================
-
-Pad the location counter (in the current subsection) to a particular
-storage boundary.  The first expression (which must be absolute) is the
-number of low-order zero bits the location counter must have after
-advancement.  For example `.p2align 3' advances the location counter
-until it a multiple of 8.  If the location counter is already a
-multiple of 8, no change is needed.
-
-   The second expression (also absolute) gives the fill value to be
-stored in the padding bytes.  It (and the comma) may be omitted.  If it
-is omitted, the padding bytes are normally zero.  However, on some
-systems, if the section is marked as containing code and the fill value
-is omitted, the space is filled with no-op instructions.
-
-   The third expression is also absolute, and is also optional.  If it
-is present, it is the maximum number of bytes that should be skipped by
-this alignment directive.  If doing the alignment would require
-skipping more bytes than the specified maximum, then the alignment is
-not done at all.  You can omit the fill value (the second argument)
-entirely by simply using two commas after the required alignment; this
-can be useful if you want the alignment to be filled with no-op
-instructions when appropriate.
-
-   The `.p2alignw' and `.p2alignl' directives are variants of the
-`.p2align' directive.  The `.p2alignw' directive treats the fill
-pattern as a two byte word value.  The `.p2alignl' directives treats the
-fill pattern as a four byte longword value.  For example, `.p2alignw
-2,0x368d' will align to a multiple of 4.  If it skips two bytes, they
-will be filled in with the value 0x368d (the exact placement of the
-bytes depends upon the endianness of the processor).  If it skips 1 or
-3 bytes, the fill value is undefined.
-
-
-File: as.info,  Node: Previous,  Next: Print,  Prev: PopSection,  Up: Pseudo Ops
-
-7.73 `.previous'
-================
-
-This is one of the ELF section stack manipulation directives.  The
-others are `.section' (*note Section::), `.subsection' (*note
-SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
-(*note PopSection::).
-
-   This directive swaps the current section (and subsection) with most
-recently referenced section (and subsection) prior to this one.
-Multiple `.previous' directives in a row will flip between two sections
-(and their subsections).
-
-   In terms of the section stack, this directive swaps the current
-section with the top section on the section stack.
-
-
-File: as.info,  Node: PopSection,  Next: Previous,  Prev: P2align,  Up: Pseudo Ops
-
-7.74 `.popsection'
-==================
-
-This is one of the ELF section stack manipulation directives.  The
-others are `.section' (*note Section::), `.subsection' (*note
-SubSection::), `.pushsection' (*note PushSection::), and `.previous'
-(*note Previous::).
-
-   This directive replaces the current section (and subsection) with
-the top section (and subsection) on the section stack.  This section is
-popped off the stack.
-
-
-File: as.info,  Node: Print,  Next: Protected,  Prev: Previous,  Up: Pseudo Ops
-
-7.75 `.print STRING'
-====================
-
-`as' will print STRING on the standard output during assembly.  You
-must put STRING in double quotes.
-
-
-File: as.info,  Node: Protected,  Next: Psize,  Prev: Print,  Up: Pseudo Ops
-
-7.76 `.protected NAMES'
-=======================
-
-This is one of the ELF visibility directives.  The other two are
-`.hidden' (*note Hidden::) and `.internal' (*note Internal::).
-
-   This directive overrides the named symbols default visibility (which
-is set by their binding: local, global or weak).  The directive sets
-the visibility to `protected' which means that any references to the
-symbols from within the components that defines them must be resolved
-to the definition in that component, even if a definition in another
-component would normally preempt this.
-
-
-File: as.info,  Node: Psize,  Next: Purgem,  Prev: Protected,  Up: Pseudo Ops
-
-7.77 `.psize LINES , COLUMNS'
-=============================
-
-Use this directive to declare the number of lines--and, optionally, the
-number of columns--to use for each page, when generating listings.
-
-   If you do not use `.psize', listings use a default line-count of 60.
-You may omit the comma and COLUMNS specification; the default width is
-200 columns.
-
-   `as' generates formfeeds whenever the specified number of lines is
-exceeded (or whenever you explicitly request one, using `.eject').
-
-   If you specify LINES as `0', no formfeeds are generated save those
-explicitly specified with `.eject'.
-
-
-File: as.info,  Node: Purgem,  Next: PushSection,  Prev: Psize,  Up: Pseudo Ops
-
-7.78 `.purgem NAME'
-===================
-
-Undefine the macro NAME, so that later uses of the string will not be
-expanded.  *Note Macro::.
-
-
-File: as.info,  Node: PushSection,  Next: Quad,  Prev: Purgem,  Up: Pseudo Ops
-
-7.79 `.pushsection NAME , SUBSECTION'
-=====================================
-
-This is one of the ELF section stack manipulation directives.  The
-others are `.section' (*note Section::), `.subsection' (*note
-SubSection::), `.popsection' (*note PopSection::), and `.previous'
-(*note Previous::).
-
-   This directive pushes the current section (and subsection) onto the
-top of the section stack, and then replaces the current section and
-subsection with `name' and `subsection'.
-
-
-File: as.info,  Node: Quad,  Next: Rept,  Prev: PushSection,  Up: Pseudo Ops
-
-7.80 `.quad BIGNUMS'
-====================
-
-`.quad' expects zero or more bignums, separated by commas.  For each
-bignum, it emits an 8-byte integer.  If the bignum won't fit in 8
-bytes, it prints a warning message; and just takes the lowest order 8
-bytes of the bignum.  
-
-   The term "quad" comes from contexts in which a "word" is two bytes;
-hence _quad_-word for 8 bytes.
-
-
-File: as.info,  Node: Rept,  Next: Sbttl,  Prev: Quad,  Up: Pseudo Ops
-
-7.81 `.rept COUNT'
-==================
-
-Repeat the sequence of lines between the `.rept' directive and the next
-`.endr' directive COUNT times.
-
-   For example, assembling
-
-             .rept   3
-             .long   0
-             .endr
-
-   is equivalent to assembling
-
-             .long   0
-             .long   0
-             .long   0
-
-
-File: as.info,  Node: Sbttl,  Next: Scl,  Prev: Rept,  Up: Pseudo Ops
-
-7.82 `.sbttl "SUBHEADING"'
-==========================
-
-Use SUBHEADING as the title (third line, immediately after the title
-line) when generating assembly listings.
-
-   This directive affects subsequent pages, as well as the current page
-if it appears within ten lines of the top of a page.
-
-
-File: as.info,  Node: Scl,  Next: Section,  Prev: Sbttl,  Up: Pseudo Ops
-
-7.83 `.scl CLASS'
-=================
-
-Set the storage-class value for a symbol.  This directive may only be
-used inside a `.def'/`.endef' pair.  Storage class may flag whether a
-symbol is static or external, or it may record further symbolic
-debugging information.
-
-
-File: as.info,  Node: Section,  Next: Set,  Prev: Scl,  Up: Pseudo Ops
-
-7.84 `.section NAME'
-====================
-
-Use the `.section' directive to assemble the following code into a
-section named NAME.
-
-   This directive is only supported for targets that actually support
-arbitrarily named sections; on `a.out' targets, for example, it is not
-accepted, even with a standard `a.out' section name.
-
-COFF Version
-------------
-
-   For COFF targets, the `.section' directive is used in one of the
-following ways:
-
-     .section NAME[, "FLAGS"]
-     .section NAME[, SUBSEGMENT]
-
-   If the optional argument is quoted, it is taken as flags to use for
-the section.  Each flag is a single character.  The following flags are
-recognized:
-`b'
-     bss section (uninitialized data)
-
-`n'
-     section is not loaded
-
-`w'
-     writable section
-
-`d'
-     data section
-
-`r'
-     read-only section
-
-`x'
-     executable section
-
-`s'
-     shared section (meaningful for PE targets)
-
-`a'
-     ignored.  (For compatibility with the ELF version)
-
-   If no flags are specified, the default flags depend upon the section
-name.  If the section name is not recognized, the default will be for
-the section to be loaded and writable.  Note the `n' and `w' flags
-remove attributes from the section, rather than adding them, so if they
-are used on their own it will be as if no flags had been specified at
-all.
-
-   If the optional argument to the `.section' directive is not quoted,
-it is taken as a subsegment number (*note Sub-Sections::).
-
-ELF Version
------------
-
-   This is one of the ELF section stack manipulation directives.  The
-others are `.subsection' (*note SubSection::), `.pushsection' (*note
-PushSection::), `.popsection' (*note PopSection::), and `.previous'
-(*note Previous::).
-
-   For ELF targets, the `.section' directive is used like this:
-
-     .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
-
-   The optional FLAGS argument is a quoted string which may contain any
-combination of the following characters:
-`a'
-     section is allocatable
-
-`w'
-     section is writable
-
-`x'
-     section is executable
-
-`M'
-     section is mergeable
-
-`S'
-     section contains zero terminated strings
-
-`G'
-     section is a member of a section group
-
-`T'
-     section is used for thread-local-storage
-
-   The optional TYPE argument may contain one of the following
-constants:
-`@progbits'
-     section contains data
-
-`@nobits'
-     section does not contain data (i.e., section only occupies space)
-
-`@note'
-     section contains data which is used by things other than the
-     program
-
-`@init_array'
-     section contains an array of pointers to init functions
-
-`@fini_array'
-     section contains an array of pointers to finish functions
-
-`@preinit_array'
-     section contains an array of pointers to pre-init functions
-
-   Many targets only support the first three section types.
-
-   Note on targets where the `@' character is the start of a comment (eg
-ARM) then another character is used instead.  For example the ARM port
-uses the `%' character.
-
-   If FLAGS contains the `M' symbol then the TYPE argument must be
-specified as well as an extra argument - ENTSIZE - like this:
-
-     .section NAME , "FLAGS"M, @TYPE, ENTSIZE
-
-   Sections with the `M' flag but not `S' flag must contain fixed size
-constants, each ENTSIZE octets long. Sections with both `M' and `S'
-must contain zero terminated strings where each character is ENTSIZE
-bytes long. The linker may remove duplicates within sections with the
-same name, same entity size and same flags.  ENTSIZE must be an
-absolute expression.
-
-   If FLAGS contains the `G' symbol then the TYPE argument must be
-present along with an additional field like this:
-
-     .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
-
-   The GROUPNAME field specifies the name of the section group to which
-this particular section belongs.  The optional linkage field can
-contain:
-`comdat'
-     indicates that only one copy of this section should be retained
-
-`.gnu.linkonce'
-     an alias for comdat
-
-   Note - if both the M and G flags are present then the fields for the
-Merge flag should come first, like this:
-
-     .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
-
-   If no flags are specified, the default flags depend upon the section
-name.  If the section name is not recognized, the default will be for
-the section to have none of the above flags: it will not be allocated
-in memory, nor writable, nor executable.  The section will contain data.
-
-   For ELF targets, the assembler supports another type of `.section'
-directive for compatibility with the Solaris assembler:
-
-     .section "NAME"[, FLAGS...]
-
-   Note that the section name is quoted.  There may be a sequence of
-comma separated flags:
-`#alloc'
-     section is allocatable
-
-`#write'
-     section is writable
-
-`#execinstr'
-     section is executable
-
-`#tls'
-     section is used for thread local storage
-
-   This directive replaces the current section and subsection.  See the
-contents of the gas testsuite directory `gas/testsuite/gas/elf' for
-some examples of how this directive and the other section stack
-directives work.
-
-
-File: as.info,  Node: Set,  Next: Short,  Prev: Section,  Up: Pseudo Ops
-
-7.85 `.set SYMBOL, EXPRESSION'
-==============================
-
-Set the value of SYMBOL to EXPRESSION.  This changes SYMBOL's value and
-type to conform to EXPRESSION.  If SYMBOL was flagged as external, it
-remains flagged (*note Symbol Attributes::).
-
-   You may `.set' a symbol many times in the same assembly.
-
-   If you `.set' a global symbol, the value stored in the object file
-is the last value stored into it.
-
-   The syntax for `set' on the HPPA is `SYMBOL .set EXPRESSION'.
-
-   On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION'
-instead.
-
-
-File: as.info,  Node: Short,  Next: Single,  Prev: Set,  Up: Pseudo Ops
-
-7.86 `.short EXPRESSIONS'
-=========================
-
-`.short' is normally the same as `.word'.  *Note `.word': Word.
-
-   In some configurations, however, `.short' and `.word' generate
-numbers of different lengths; *note Machine Dependencies::.
-
-
-File: as.info,  Node: Single,  Next: Size,  Prev: Short,  Up: Pseudo Ops
-
-7.87 `.single FLONUMS'
-======================
-
-This directive assembles zero or more flonums, separated by commas.  It
-has the same effect as `.float'.  The exact kind of floating point
-numbers emitted depends on how `as' is configured.  *Note Machine
-Dependencies::.
-
-
-File: as.info,  Node: Size,  Next: Skip,  Prev: Single,  Up: Pseudo Ops
-
-7.88 `.size'
-============
-
-This directive is used to set the size associated with a symbol.
-
-COFF Version
-------------
-
-   For COFF targets, the `.size' directive is only permitted inside
-`.def'/`.endef' pairs.  It is used like this:
-
-     .size EXPRESSION
-
-ELF Version
------------
-
-   For ELF targets, the `.size' directive is used like this:
-
-     .size NAME , EXPRESSION
-
-   This directive sets the size associated with a symbol NAME.  The
-size in bytes is computed from EXPRESSION which can make use of label
-arithmetic.  This directive is typically used to set the size of
-function symbols.
-
-
-File: as.info,  Node: Sleb128,  Next: Space,  Prev: Skip,  Up: Pseudo Ops
-
-7.89 `.sleb128 EXPRESSIONS'
-===========================
-
-SLEB128 stands for "signed little endian base 128."  This is a compact,
-variable length representation of numbers used by the DWARF symbolic
-debugging format.  *Note `.uleb128': Uleb128.
-
-
-File: as.info,  Node: Skip,  Next: Sleb128,  Prev: Size,  Up: Pseudo Ops
-
-7.90 `.skip SIZE , FILL'
-========================
-
-This directive emits SIZE bytes, each of value FILL.  Both SIZE and
-FILL are absolute expressions.  If the comma and FILL are omitted, FILL
-is assumed to be zero.  This is the same as `.space'.
-
-
-File: as.info,  Node: Space,  Next: Stab,  Prev: Sleb128,  Up: Pseudo Ops
-
-7.91 `.space SIZE , FILL'
-=========================
-
-This directive emits SIZE bytes, each of value FILL.  Both SIZE and
-FILL are absolute expressions.  If the comma and FILL are omitted, FILL
-is assumed to be zero.  This is the same as `.skip'.
-
-     _Warning:_ `.space' has a completely different meaning for HPPA
-     targets; use `.block' as a substitute.  See `HP9000 Series 800
-     Assembly Language Reference Manual' (HP 92432-90001) for the
-     meaning of the `.space' directive.  *Note HPPA Assembler
-     Directives: HPPA Directives, for a summary.
-
-
-File: as.info,  Node: Stab,  Next: String,  Prev: Space,  Up: Pseudo Ops
-
-7.92 `.stabd, .stabn, .stabs'
-=============================
-
-There are three directives that begin `.stab'.  All emit symbols (*note
-Symbols::), for use by symbolic debuggers.  The symbols are not entered
-in the `as' hash table: they cannot be referenced elsewhere in the
-source file.  Up to five fields are required:
-
-STRING
-     This is the symbol's name.  It may contain any character except
-     `\000', so is more general than ordinary symbol names.  Some
-     debuggers used to code arbitrarily complex structures into symbol
-     names using this field.
-
-TYPE
-     An absolute expression.  The symbol's type is set to the low 8
-     bits of this expression.  Any bit pattern is permitted, but `ld'
-     and debuggers choke on silly bit patterns.
-
-OTHER
-     An absolute expression.  The symbol's "other" attribute is set to
-     the low 8 bits of this expression.
-
-DESC
-     An absolute expression.  The symbol's descriptor is set to the low
-     16 bits of this expression.
-
-VALUE
-     An absolute expression which becomes the symbol's value.
-
-   If a warning is detected while reading a `.stabd', `.stabn', or
-`.stabs' statement, the symbol has probably already been created; you
-get a half-formed symbol in your object file.  This is compatible with
-earlier assemblers!
-
-`.stabd TYPE , OTHER , DESC'
-     The "name" of the symbol generated is not even an empty string.
-     It is a null pointer, for compatibility.  Older assemblers used a
-     null pointer so they didn't waste space in object files with empty
-     strings.
-
-     The symbol's value is set to the location counter, relocatably.
-     When your program is linked, the value of this symbol is the
-     address of the location counter when the `.stabd' was assembled.
-
-`.stabn TYPE , OTHER , DESC , VALUE'
-     The name of the symbol is set to the empty string `""'.
-
-`.stabs STRING ,  TYPE , OTHER , DESC , VALUE'
-     All five fields are specified.
-
-
-File: as.info,  Node: String,  Next: Struct,  Prev: Stab,  Up: Pseudo Ops
-
-7.93 `.string' "STR"
-====================
-
-Copy the characters in STR to the object file.  You may specify more
-than one string to copy, separated by commas.  Unless otherwise
-specified for a particular machine, the assembler marks the end of each
-string with a 0 byte.  You can use any of the escape sequences
-described in *Note Strings: Strings.
-
-
-File: as.info,  Node: Struct,  Next: SubSection,  Prev: String,  Up: Pseudo Ops
-
-7.94 `.struct EXPRESSION'
-=========================
-
-Switch to the absolute section, and set the section offset to
-EXPRESSION, which must be an absolute expression.  You might use this
-as follows:
-             .struct 0
-     field1:
-             .struct field1 + 4
-     field2:
-             .struct field2 + 4
-     field3:
-   This would define the symbol `field1' to have the value 0, the symbol
-`field2' to have the value 4, and the symbol `field3' to have the value
-8.  Assembly would be left in the absolute section, and you would need
-to use a `.section' directive of some sort to change to some other
-section before further assembly.
-
-
-File: as.info,  Node: SubSection,  Next: Symver,  Prev: Struct,  Up: Pseudo Ops
-
-7.95 `.subsection NAME'
-=======================
-
-This is one of the ELF section stack manipulation directives.  The
-others are `.section' (*note Section::), `.pushsection' (*note
-PushSection::), `.popsection' (*note PopSection::), and `.previous'
-(*note Previous::).
-
-   This directive replaces the current subsection with `name'.  The
-current section is not changed.  The replaced subsection is put onto
-the section stack in place of the then current top of stack subsection.
-
-
-File: as.info,  Node: Symver,  Next: Tag,  Prev: SubSection,  Up: Pseudo Ops
-
-7.96 `.symver'
-==============
-
-Use the `.symver' directive to bind symbols to specific version nodes
-within a source file.  This is only supported on ELF platforms, and is
-typically used when assembling files to be linked into a shared library.
-There are cases where it may make sense to use this in objects to be
-bound into an application itself so as to override a versioned symbol
-from a shared library.
-
-   For ELF targets, the `.symver' directive can be used like this:
-     .symver NAME, NAME2@NODENAME
-   If the symbol NAME is defined within the file being assembled, the
-`.symver' directive effectively creates a symbol alias with the name
-NAME2@NODENAME, and in fact the main reason that we just don't try and
-create a regular alias is that the @ character isn't permitted in
-symbol names.  The NAME2 part of the name is the actual name of the
-symbol by which it will be externally referenced.  The name NAME itself
-is merely a name of convenience that is used so that it is possible to
-have definitions for multiple versions of a function within a single
-source file, and so that the compiler can unambiguously know which
-version of a function is being mentioned.  The NODENAME portion of the
-alias should be the name of a node specified in the version script
-supplied to the linker when building a shared library.  If you are
-attempting to override a versioned symbol from a shared library, then
-NODENAME should correspond to the nodename of the symbol you are trying
-to override.
-
-   If the symbol NAME is not defined within the file being assembled,
-all references to NAME will be changed to NAME2@NODENAME.  If no
-reference to NAME is made, NAME2@NODENAME will be removed from the
-symbol table.
-
-   Another usage of the `.symver' directive is:
-     .symver NAME, NAME2@@NODENAME
-   In this case, the symbol NAME must exist and be defined within the
-file being assembled. It is similar to NAME2@NODENAME. The difference
-is NAME2@@NODENAME will also be used to resolve references to NAME2 by
-the linker.
-
-   The third usage of the `.symver' directive is:
-     .symver NAME, NAME2@@@NODENAME
-   When NAME is not defined within the file being assembled, it is
-treated as NAME2@NODENAME. When NAME is defined within the file being
-assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
-
-
-File: as.info,  Node: Tag,  Next: Text,  Prev: Symver,  Up: Pseudo Ops
-
-7.97 `.tag STRUCTNAME'
-======================
-
-This directive is generated by compilers to include auxiliary debugging
-information in the symbol table.  It is only permitted inside
-`.def'/`.endef' pairs.  Tags are used to link structure definitions in
-the symbol table with instances of those structures.
-
-
-File: as.info,  Node: Text,  Next: Title,  Prev: Tag,  Up: Pseudo Ops
-
-7.98 `.text SUBSECTION'
-=======================
-
-Tells `as' to assemble the following statements onto the end of the
-text subsection numbered SUBSECTION, which is an absolute expression.
-If SUBSECTION is omitted, subsection number zero is used.
-
-
-File: as.info,  Node: Title,  Next: Type,  Prev: Text,  Up: Pseudo Ops
-
-7.99 `.title "HEADING"'
-=======================
-
-Use HEADING as the title (second line, immediately after the source
-file name and pagenumber) when generating assembly listings.
-
-   This directive affects subsequent pages, as well as the current page
-if it appears within ten lines of the top of a page.
-
-
-File: as.info,  Node: Type,  Next: Uleb128,  Prev: Title,  Up: Pseudo Ops
-
-7.100 `.type'
-=============
-
-This directive is used to set the type of a symbol.
-
-COFF Version
-------------
-
-   For COFF targets, this directive is permitted only within
-`.def'/`.endef' pairs.  It is used like this:
-
-     .type INT
-
-   This records the integer INT as the type attribute of a symbol table
-entry.
-
-ELF Version
------------
-
-   For ELF targets, the `.type' directive is used like this:
-
-     .type NAME , TYPE DESCRIPTION
-
-   This sets the type of symbol NAME to be either a function symbol or
-an object symbol.  There are five different syntaxes supported for the
-TYPE DESCRIPTION field, in order to provide compatibility with various
-other assemblers.  The syntaxes supported are:
-
-       .type <name>,#function
-       .type <name>,#object
-
-       .type <name>,@function
-       .type <name>,@object
-
-       .type <name>,%function
-       .type <name>,%object
-
-       .type <name>,"function"
-       .type <name>,"object"
-
-       .type <name> STT_FUNCTION
-       .type <name> STT_OBJECT
-
-
-File: as.info,  Node: Uleb128,  Next: Val,  Prev: Type,  Up: Pseudo Ops
-
-7.101 `.uleb128 EXPRESSIONS'
-============================
-
-ULEB128 stands for "unsigned little endian base 128."  This is a
-compact, variable length representation of numbers used by the DWARF
-symbolic debugging format.  *Note `.sleb128': Sleb128.
-
-
-File: as.info,  Node: Val,  Next: Version,  Prev: Uleb128,  Up: Pseudo Ops
-
-7.102 `.val ADDR'
-=================
-
-This directive, permitted only within `.def'/`.endef' pairs, records
-the address ADDR as the value attribute of a symbol table entry.
-
-
-File: as.info,  Node: Version,  Next: VTableEntry,  Prev: Val,  Up: Pseudo Ops
-
-7.103 `.version "STRING"'
-=========================
-
-This directive creates a `.note' section and places into it an ELF
-formatted note of type NT_VERSION.  The note's name is set to `string'.
-
-
-File: as.info,  Node: VTableEntry,  Next: VTableInherit,  Prev: Version,  Up: Pseudo Ops
-
-7.104 `.vtable_entry TABLE, OFFSET'
-===================================
-
-This directive finds or creates a symbol `table' and creates a
-`VTABLE_ENTRY' relocation for it with an addend of `offset'.
-
-
-File: as.info,  Node: VTableInherit,  Next: Warning,  Prev: VTableEntry,  Up: Pseudo Ops
-
-7.105 `.vtable_inherit CHILD, PARENT'
-=====================================
-
-This directive finds the symbol `child' and finds or creates the symbol
-`parent' and then creates a `VTABLE_INHERIT' relocation for the parent
-whose addend is the value of the child symbol.  As a special case the
-parent name of `0' is treated as refering the `*ABS*' section.
-
-
-File: as.info,  Node: Warning,  Next: Weak,  Prev: VTableInherit,  Up: Pseudo Ops
-
-7.106 `.warning "STRING"'
-=========================
-
-Similar to the directive `.error' (*note `.error "STRING"': Error.),
-but just emits a warning.
-
-
-File: as.info,  Node: Weak,  Next: Weakref,  Prev: Warning,  Up: Pseudo Ops
-
-7.107 `.weak NAMES'
-===================
-
-This directive sets the weak attribute on the comma separated list of
-symbol `names'.  If the symbols do not already exist, they will be
-created.
-
-   On COFF targets other than PE, weak symbols are a GNU extension.
-This directive sets the weak attribute on the comma separated list of
-symbol `names'.  If the symbols do not already exist, they will be
-created.
-
-   On the PE target, weak symbols are supported natively as weak
-aliases.  When a weak symbol is created that is not an alias, GAS
-creates an alternate symbol to hold the default value.
-
-
-File: as.info,  Node: Weakref,  Next: Word,  Prev: Weak,  Up: Pseudo Ops
-
-7.108 `.weakref ALIAS, TARGET'
-==============================
-
-This directive creates an alias to the target symbol that enables the
-symbol to be referenced with weak-symbol semantics, but without
-actually making it weak.  If direct references or definitions of the
-symbol are present, then the symbol will not be weak, but if all
-references to it are through weak references, the symbol will be marked
-as weak in the symbol table.
-
-   The effect is equivalent to moving all references to the alias to a
-separate assembly source file, renaming the alias to the symbol in it,
-declaring the symbol as weak there, and running a reloadable link to
-merge the object files resulting from the assembly of the new source
-file and the old source file that had the references to the alias
-removed.
-
-   The alias itself never makes to the symbol table, and is entirely
-handled within the assembler.
-
-
-File: as.info,  Node: Word,  Next: Deprecated,  Prev: Weakref,  Up: Pseudo Ops
-
-7.109 `.word EXPRESSIONS'
-=========================
-
-This directive expects zero or more EXPRESSIONS, of any section,
-separated by commas.
-
-   The size of the number emitted, and its byte order, depend on what
-target computer the assembly is for.
-
-     _Warning: Special Treatment to support Compilers_
-
-   Machines with a 32-bit address space, but that do less than 32-bit
-addressing, require the following special treatment.  If the machine of
-interest to you does 32-bit addressing (or doesn't require it; *note
-Machine Dependencies::), you can ignore this issue.
-
-   In order to assemble compiler output into something that works, `as'
-occasionally does strange things to `.word' directives.  Directives of
-the form `.word sym1-sym2' are often emitted by compilers as part of
-jump tables.  Therefore, when `as' assembles a directive of the form
-`.word sym1-sym2', and the difference between `sym1' and `sym2' does
-not fit in 16 bits, `as' creates a "secondary jump table", immediately
-before the next label.  This secondary jump table is preceded by a
-short-jump to the first byte after the secondary table.  This
-short-jump prevents the flow of control from accidentally falling into
-the new table.  Inside the table is a long-jump to `sym2'.  The
-original `.word' contains `sym1' minus the address of the long-jump to
-`sym2'.
-
-   If there were several occurrences of `.word sym1-sym2' before the
-secondary jump table, all of them are adjusted.  If there was a `.word
-sym3-sym4', that also did not fit in sixteen bits, a long-jump to
-`sym4' is included in the secondary jump table, and the `.word'
-directives are adjusted to contain `sym3' minus the address of the
-long-jump to `sym4'; and so on, for as many entries in the original
-jump table as necessary.
-
-
-File: as.info,  Node: Deprecated,  Prev: Word,  Up: Pseudo Ops
-
-7.110 Deprecated Directives
-===========================
-
-One day these directives won't work.  They are included for
-compatibility with older assemblers.
-.abort
-
-.line
-
-
-File: as.info,  Node: Machine Dependencies,  Next: Reporting Bugs,  Prev: Pseudo Ops,  Up: Top
-
-8 Machine Dependent Features
-****************************
-
-The machine instruction sets are (almost by definition) different on
-each machine where `as' runs.  Floating point representations vary as
-well, and `as' often supports a few additional directives or
-command-line options for compatibility with other assemblers on a
-particular platform.  Finally, some versions of `as' support special
-pseudo-instructions for branch optimization.
-
-   This chapter discusses most of these differences, though it does not
-include details on any machine's instruction set.  For details on that
-subject, see the hardware manufacturer's manual.
-
-* Menu:
-
-
-* Alpha-Dependent::		Alpha Dependent Features
-
-* ARC-Dependent::               ARC Dependent Features
-
-* ARM-Dependent::               ARM Dependent Features
-
-* BFIN-Dependent::		BFIN Dependent Features
-
-* CRIS-Dependent::              CRIS Dependent Features
-
-* D10V-Dependent::              D10V Dependent Features
-
-* D30V-Dependent::              D30V Dependent Features
-
-* H8/300-Dependent::            Renesas H8/300 Dependent Features
-
-* HPPA-Dependent::              HPPA Dependent Features
-
-* ESA/390-Dependent::           IBM ESA/390 Dependent Features
-
-* i386-Dependent::              Intel 80386 and AMD x86-64 Dependent Features
-
-* i860-Dependent::              Intel 80860 Dependent Features
-
-* i960-Dependent::              Intel 80960 Dependent Features
-
-* IA-64-Dependent::             Intel IA-64 Dependent Features
-
-* IP2K-Dependent::              IP2K Dependent Features
-
-* M32C-Dependent::              M32C Dependent Features
-
-* M32R-Dependent::              M32R Dependent Features
-
-* M68K-Dependent::              M680x0 Dependent Features
-
-* M68HC11-Dependent::           M68HC11 and 68HC12 Dependent Features
-
-* MIPS-Dependent::              MIPS Dependent Features
-
-* MMIX-Dependent::              MMIX Dependent Features
-
-* MSP430-Dependent::		MSP430 Dependent Features
-
-* SH-Dependent::                Renesas / SuperH SH Dependent Features
-* SH64-Dependent::              SuperH SH64 Dependent Features
-
-* PDP-11-Dependent::            PDP-11 Dependent Features
-
-* PJ-Dependent::                picoJava Dependent Features
-
-* PPC-Dependent::               PowerPC Dependent Features
-
-* Sparc-Dependent::             SPARC Dependent Features
-
-* TIC54X-Dependent::            TI TMS320C54x Dependent Features
-
-* V850-Dependent::              V850 Dependent Features
-
-* Xtensa-Dependent::            Xtensa Dependent Features
-
-* Z80-Dependent::               Z80 Dependent Features
-
-* Z8000-Dependent::             Z8000 Dependent Features
-
-* Vax-Dependent::               VAX Dependent Features
-
-
-File: as.info,  Node: Alpha-Dependent,  Next: ARC-Dependent,  Up: Machine Dependencies
-
-8.1 Alpha Dependent Features
-============================
-
-* Menu:
-
-* Alpha Notes::                Notes
-* Alpha Options::              Options
-* Alpha Syntax::               Syntax
-* Alpha Floating Point::       Floating Point
-* Alpha Directives::           Alpha Machine Directives
-* Alpha Opcodes::              Opcodes
-
-
-File: as.info,  Node: Alpha Notes,  Next: Alpha Options,  Up: Alpha-Dependent
-
-8.1.1 Notes
------------
-
-The documentation here is primarily for the ELF object format.  `as'
-also supports the ECOFF and EVAX formats, but features specific to
-these formats are not yet documented.
-
-
-File: as.info,  Node: Alpha Options,  Next: Alpha Syntax,  Prev: Alpha Notes,  Up: Alpha-Dependent
-
-8.1.2 Options
--------------
-
-`-mCPU'
-     This option specifies the target processor.  If an attempt is made
-     to assemble an instruction which will not execute on the target
-     processor, the assembler may either expand the instruction as a
-     macro or issue an error message.  This option is equivalent to the
-     `.arch' directive.
-
-     The following processor names are recognized: `21064', `21064a',
-     `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a',
-     `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6',
-     `ev67', `ev68'.  The special name `all' may be used to allow the
-     assembler to accept instructions valid for any Alpha processor.
-
-     In order to support existing practice in OSF/1 with respect to
-     `.arch', and existing practice within `MILO' (the Linux ARC
-     bootloader), the numbered processor names (e.g. 21064) enable the
-     processor-specific PALcode instructions, while the
-     "electro-vlasic" names (e.g. `ev4') do not.
-
-`-mdebug'
-`-no-mdebug'
-     Enables or disables the generation of `.mdebug' encapsulation for
-     stabs directives and procedure descriptors.  The default is to
-     automatically enable `.mdebug' when the first stabs directive is
-     seen.
-
-`-relax'
-     This option forces all relocations to be put into the object file,
-     instead of saving space and resolving some relocations at assembly
-     time.  Note that this option does not propagate all symbol
-     arithmetic into the object file, because not all symbol arithmetic
-     can be represented.  However, the option can still be useful in
-     specific applications.
-
-`-g'
-     This option is used when the compiler generates debug information.
-     When `gcc' is using `mips-tfile' to generate debug information
-     for ECOFF, local labels must be passed through to the object file.
-     Otherwise this option has no effect.
-
-`-GSIZE'
-     A local common symbol larger than SIZE is placed in `.bss', while
-     smaller symbols are placed in `.sbss'.
-
-`-F'
-`-32addr'
-     These options are ignored for backward compatibility.
-
-
-File: as.info,  Node: Alpha Syntax,  Next: Alpha Floating Point,  Prev: Alpha Options,  Up: Alpha-Dependent
-
-8.1.3 Syntax
-------------
-
-The assembler syntax closely follow the Alpha Reference Manual;
-assembler directives and general syntax closely follow the OSF/1 and
-OpenVMS syntax, with a few differences for ELF.
-
-* Menu:
-
-* Alpha-Chars::                Special Characters
-* Alpha-Regs::                 Register Names
-* Alpha-Relocs::               Relocations
-
-
-File: as.info,  Node: Alpha-Chars,  Next: Alpha-Regs,  Up: Alpha Syntax
-
-8.1.3.1 Special Characters
-..........................
-
-`#' is the line comment character.
-
-   `;' can be used instead of a newline to separate statements.
-
-
-File: as.info,  Node: Alpha-Regs,  Next: Alpha-Relocs,  Prev: Alpha-Chars,  Up: Alpha Syntax
-
-8.1.3.2 Register Names
-......................
-
-The 32 integer registers are referred to as `$N' or `$rN'.  In
-addition, registers 15, 28, 29, and 30 may be referred to by the
-symbols `$fp', `$at', `$gp', and `$sp' respectively.
-
-   The 32 floating-point registers are referred to as `$fN'.
-
-
-File: as.info,  Node: Alpha-Relocs,  Prev: Alpha-Regs,  Up: Alpha Syntax
-
-8.1.3.3 Relocations
-...................
-
-Some of these relocations are available for ECOFF, but mostly only for
-ELF.  They are modeled after the relocation format introduced in
-Digital Unix 4.0, but there are additions.
-
-   The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the
-relocation.  In some cases NUMBER is used to relate specific
-instructions.
-
-   The relocation is placed at the end of the instruction like so:
-
-     ldah  $0,a($29)    !gprelhigh
-     lda   $0,a($0)     !gprellow
-     ldq   $1,b($29)    !literal!100
-     ldl   $2,0($1)     !lituse_base!100
-
-`!literal'
-`!literal!N'
-     Used with an `ldq' instruction to load the address of a symbol
-     from the GOT.
-
-     A sequence number N is optional, and if present is used to pair
-     `lituse' relocations with this `literal' relocation.  The `lituse'
-     relocations are used by the linker to optimize the code based on
-     the final location of the symbol.
-
-     Note that these optimizations are dependent on the data flow of the
-     program.  Therefore, if _any_ `lituse' is paired with a `literal'
-     relocation, then _all_ uses of the register set by the `literal'
-     instruction must also be marked with `lituse' relocations.  This
-     is because the original `literal' instruction may be deleted or
-     transformed into another instruction.
-
-     Also note that there may be a one-to-many relationship between
-     `literal' and `lituse', but not a many-to-one.  That is, if there
-     are two code paths that load up the same address and feed the
-     value to a single use, then the use may not use a `lituse'
-     relocation.
-
-`!lituse_base!N'
-     Used with any memory format instruction (e.g. `ldl') to indicate
-     that the literal is used for an address load.  The offset field of
-     the instruction must be zero.  During relaxation, the code may be
-     altered to use a gp-relative load.
-
-`!lituse_jsr!N'
-     Used with a register branch format instruction (e.g. `jsr') to
-     indicate that the literal is used for a call.  During relaxation,
-     the code may be altered to use a direct branch (e.g. `bsr').
-
-`!lituse_jsrdirect!N'
-     Similar to `lituse_jsr', but also that this call cannot be vectored
-     through a PLT entry.  This is useful for functions with special
-     calling conventions which do not allow the normal call-clobbered
-     registers to be clobbered.
-
-`!lituse_bytoff!N'
-     Used with a byte mask instruction (e.g. `extbl') to indicate that
-     only the low 3 bits of the address are relevant.  During
-     relaxation, the code may be altered to use an immediate instead of
-     a register shift.
-
-`!lituse_addr!N'
-     Used with any other instruction to indicate that the original
-     address is in fact used, and the original `ldq' instruction may
-     not be altered or deleted.  This is useful in conjunction with
-     `lituse_jsr' to test whether a weak symbol is defined.
-
-          ldq  $27,foo($29)   !literal!1
-          beq  $27,is_undef   !lituse_addr!1
-          jsr  $26,($27),foo  !lituse_jsr!1
-
-`!lituse_tlsgd!N'
-     Used with a register branch format instruction to indicate that the
-     literal is the call to `__tls_get_addr' used to compute the
-     address of the thread-local storage variable whose descriptor was
-     loaded with `!tlsgd!N'.
-
-`!lituse_tlsldm!N'
-     Used with a register branch format instruction to indicate that the
-     literal is the call to `__tls_get_addr' used to compute the
-     address of the base of the thread-local storage block for the
-     current module.  The descriptor for the module must have been
-     loaded with `!tlsldm!N'.
-
-`!gpdisp!N'
-     Used with `ldah' and `lda' to load the GP from the current
-     address, a-la the `ldgp' macro.  The source register for the
-     `ldah' instruction must contain the address of the `ldah'
-     instruction.  There must be exactly one `lda' instruction paired
-     with the `ldah' instruction, though it may appear anywhere in the
-     instruction stream.  The immediate operands must be zero.
-
-          bsr  $26,foo
-          ldah $29,0($26)     !gpdisp!1
-          lda  $29,0($29)     !gpdisp!1
-
-`!gprelhigh'
-     Used with an `ldah' instruction to add the high 16 bits of a
-     32-bit displacement from the GP.
-
-`!gprellow'
-     Used with any memory format instruction to add the low 16 bits of a
-     32-bit displacement from the GP.
-
-`!gprel'
-     Used with any memory format instruction to add a 16-bit
-     displacement from the GP.
-
-`!samegp'
-     Used with any branch format instruction to skip the GP load at the
-     target address.  The referenced symbol must have the same GP as the
-     source object file, and it must be declared to either not use `$27'
-     or perform a standard GP load in the first two instructions via the
-     `.prologue' directive.
-
-`!tlsgd'
-`!tlsgd!N'
-     Used with an `lda' instruction to load the address of a TLS
-     descriptor for a symbol in the GOT.
-
-     The sequence number N is optional, and if present it used to pair
-     the descriptor load with both the `literal' loading the address of
-     the `__tls_get_addr' function and the `lituse_tlsgd' marking the
-     call to that function.
-
-     For proper relaxation, both the `tlsgd', `literal' and `lituse'
-     relocations must be in the same extended basic block.  That is,
-     the relocation with the lowest address must be executed first at
-     runtime.
-
-`!tlsldm'
-`!tlsldm!N'
-     Used with an `lda' instruction to load the address of a TLS
-     descriptor for the current module in the GOT.
-
-     Similar in other respects to `tlsgd'.
-
-`!gotdtprel'
-     Used with an `ldq' instruction to load the offset of the TLS
-     symbol within its module's thread-local storage block.  Also known
-     as the dynamic thread pointer offset or dtp-relative offset.
-
-`!dtprelhi'
-`!dtprello'
-`!dtprel'
-     Like `gprel' relocations except they compute dtp-relative offsets.
-
-`!gottprel'
-     Used with an `ldq' instruction to load the offset of the TLS
-     symbol from the thread pointer.  Also known as the tp-relative
-     offset.
-
-`!tprelhi'
-`!tprello'
-`!tprel'
-     Like `gprel' relocations except they compute tp-relative offsets.
-
-
-File: as.info,  Node: Alpha Floating Point,  Next: Alpha Directives,  Prev: Alpha Syntax,  Up: Alpha-Dependent
-
-8.1.4 Floating Point
---------------------
-
-The Alpha family uses both IEEE and VAX floating-point numbers.
-
-
-File: as.info,  Node: Alpha Directives,  Next: Alpha Opcodes,  Prev: Alpha Floating Point,  Up: Alpha-Dependent
-
-8.1.5 Alpha Assembler Directives
---------------------------------
-
-`as' for the Alpha supports many additional directives for
-compatibility with the native assembler.  This section describes them
-only briefly.
-
-   These are the additional directives in `as' for the Alpha:
-
-`.arch CPU'
-     Specifies the target processor.  This is equivalent to the `-mCPU'
-     command-line option.  *Note Options: Alpha Options, for a list of
-     values for CPU.
-
-`.ent FUNCTION[, N]'
-     Mark the beginning of FUNCTION.  An optional number may follow for
-     compatibility with the OSF/1 assembler, but is ignored.  When
-     generating `.mdebug' information, this will create a procedure
-     descriptor for the function.  In ELF, it will mark the symbol as a
-     function a-la the generic `.type' directive.
-
-`.end FUNCTION'
-     Mark the end of FUNCTION.  In ELF, it will set the size of the
-     symbol a-la the generic `.size' directive.
-
-`.mask MASK, OFFSET'
-     Indicate which of the integer registers are saved in the current
-     function's stack frame.  MASK is interpreted a bit mask in which
-     bit N set indicates that register N is saved.  The registers are
-     saved in a block located OFFSET bytes from the "canonical frame
-     address" (CFA) which is the value of the stack pointer on entry to
-     the function.  The registers are saved sequentially, except that
-     the return address register (normally `$26') is saved first.
-
-     This and the other directives that describe the stack frame are
-     currently only used when generating `.mdebug' information.  They
-     may in the future be used to generate DWARF2 `.debug_frame' unwind
-     information for hand written assembly.
-
-`.fmask MASK, OFFSET'
-     Indicate which of the floating-point registers are saved in the
-     current stack frame.  The MASK and OFFSET parameters are
-     interpreted as with `.mask'.
-
-`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
-     Describes the shape of the stack frame.  The frame pointer in use
-     is FRAMEREG; normally this is either `$fp' or `$sp'.  The frame
-     pointer is FRAMEOFFSET bytes below the CFA.  The return address is
-     initially located in RETREG until it is saved as indicated in
-     `.mask'.  For compatibility with OSF/1 an optional ARGOFFSET
-     parameter is accepted and ignored.  It is believed to indicate the
-     offset from the CFA to the saved argument registers.
-
-`.prologue N'
-     Indicate that the stack frame is set up and all registers have been
-     spilled.  The argument N indicates whether and how the function
-     uses the incoming "procedure vector" (the address of the called
-     function) in `$27'.  0 indicates that `$27' is not used; 1
-     indicates that the first two instructions of the function use `$27'
-     to perform a load of the GP register; 2 indicates that `$27' is
-     used in some non-standard way and so the linker cannot elide the
-     load of the procedure vector during relaxation.
-
-`.usepv FUNCTION, WHICH'
-     Used to indicate the use of the `$27' register, similar to
-     `.prologue', but without the other semantics of needing to be
-     inside an open `.ent'/`.end' block.
-
-     The WHICH argument should be either `no', indicating that `$27' is
-     not used, or `std', indicating that the first two instructions of
-     the function perform a GP load.
-
-     One might use this directive instead of `.prologue' if you are
-     also using dwarf2 CFI directives.
-
-`.gprel32 EXPRESSION'
-     Computes the difference between the address in EXPRESSION and the
-     GP for the current object file, and stores it in 4 bytes.  In
-     addition to being smaller than a full 8 byte address, this also
-     does not require a dynamic relocation when used in a shared
-     library.
-
-`.t_floating EXPRESSION'
-     Stores EXPRESSION as an IEEE double precision value.
-
-`.s_floating EXPRESSION'
-     Stores EXPRESSION as an IEEE single precision value.
-
-`.f_floating EXPRESSION'
-     Stores EXPRESSION as a VAX F format value.
-
-`.g_floating EXPRESSION'
-     Stores EXPRESSION as a VAX G format value.
-
-`.d_floating EXPRESSION'
-     Stores EXPRESSION as a VAX D format value.
-
-`.set FEATURE'
-     Enables or disables various assembler features.  Using the positive
-     name of the feature enables while using `noFEATURE' disables.
-
-    `at'
-          Indicates that macro expansions may clobber the "assembler
-          temporary" (`$at' or `$28') register.  Some macros may not be
-          expanded without this and will generate an error message if
-          `noat' is in effect.  When `at' is in effect, a warning will
-          be generated if `$at' is used by the programmer.
-
-    `macro'
-          Enables the expansion of macro instructions.  Note that
-          variants of real instructions, such as `br label' vs `br
-          $31,label' are considered alternate forms and not macros.
-
-    `move'
-    `reorder'
-    `volatile'
-          These control whether and how the assembler may re-order
-          instructions.  Accepted for compatibility with the OSF/1
-          assembler, but `as' does not do instruction scheduling, so
-          these features are ignored.
-
-   The following directives are recognized for compatibility with the
-OSF/1 assembler but are ignored.
-
-     .proc           .aproc
-     .reguse         .livereg
-     .option         .aent
-     .ugen           .eflag
-     .alias          .noalias
-
-
-File: as.info,  Node: Alpha Opcodes,  Prev: Alpha Directives,  Up: Alpha-Dependent
-
-8.1.6 Opcodes
--------------
-
-For detailed information on the Alpha machine instruction set, see the
-Alpha Architecture Handbook
-(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
-
-
-File: as.info,  Node: ARC-Dependent,  Next: ARM-Dependent,  Prev: Alpha-Dependent,  Up: Machine Dependencies
-
-8.2 ARC Dependent Features
-==========================
-
-* Menu:
-
-* ARC Options::              Options
-* ARC Syntax::               Syntax
-* ARC Floating Point::       Floating Point
-* ARC Directives::           ARC Machine Directives
-* ARC Opcodes::              Opcodes
-
-
-File: as.info,  Node: ARC Options,  Next: ARC Syntax,  Up: ARC-Dependent
-
-8.2.1 Options
--------------
-
-`-marc[5|6|7|8]'
-     This option selects the core processor variant.  Using `-marc' is
-     the same as `-marc6', which is also the default.
-
-    `arc5'
-          Base instruction set.
-
-    `arc6'
-          Jump-and-link (jl) instruction.  No requirement of an
-          instruction between setting flags and conditional jump.  For
-          example:
-
-                 mov.f r0,r1
-                 beq   foo
-
-    `arc7'
-          Break (brk) and sleep (sleep) instructions.
-
-    `arc8'
-          Software interrupt (swi) instruction.
-
-
-     Note: the `.option' directive can to be used to select a core
-     variant from within assembly code.
-
-`-EB'
-     This option specifies that the output generated by the assembler
-     should be marked as being encoded for a big-endian processor.
-
-`-EL'
-     This option specifies that the output generated by the assembler
-     should be marked as being encoded for a little-endian processor -
-     this is the default.
-
-
-
-File: as.info,  Node: ARC Syntax,  Next: ARC Floating Point,  Prev: ARC Options,  Up: ARC-Dependent
-
-8.2.2 Syntax
-------------
-
-* Menu:
-
-* ARC-Chars::                Special Characters
-* ARC-Regs::                 Register Names
-
-
-File: as.info,  Node: ARC-Chars,  Next: ARC-Regs,  Up: ARC Syntax
-
-8.2.2.1 Special Characters
-..........................
-
-*TODO*
-
-
-File: as.info,  Node: ARC-Regs,  Prev: ARC-Chars,  Up: ARC Syntax
-
-8.2.2.2 Register Names
-......................
-
-*TODO*
-
-
-File: as.info,  Node: ARC Floating Point,  Next: ARC Directives,  Prev: ARC Syntax,  Up: ARC-Dependent
-
-8.2.3 Floating Point
---------------------
-
-The ARC core does not currently have hardware floating point support.
-Software floating point support is provided by `GCC' and uses IEEE
-floating-point numbers.
-
-
-File: as.info,  Node: ARC Directives,  Next: ARC Opcodes,  Prev: ARC Floating Point,  Up: ARC-Dependent
-
-8.2.4 ARC Machine Directives
-----------------------------
-
-The ARC version of `as' supports the following additional machine
-directives:
-
-`.2byte EXPRESSIONS'
-     *TODO*
-
-`.3byte EXPRESSIONS'
-     *TODO*
-
-`.4byte EXPRESSIONS'
-     *TODO*
-
-`.extAuxRegister NAME,ADDRESS,MODE'
-     The ARCtangent A4 has extensible auxiliary register space.  The
-     auxiliary registers can be defined in the assembler source code by
-     using this directive.  The first parameter is the NAME of the new
-     auxiallry register.  The second parameter is the ADDRESS of the
-     register in the auxiliary register memory map for the variant of
-     the ARC.  The third parameter specifies the MODE in which the
-     register can be operated is and it can be one of:
-
-    `r          (readonly)'
-
-    `w          (write only)'
-
-    `r|w        (read or write)'
-
-     For example:
-
-            .extAuxRegister mulhi,0x12,w
-
-     This specifies an extension auxiliary register called _mulhi_
-     which is at address 0x12 in the memory space and which is only
-     writable.
-
-`.extCondCode SUFFIX,VALUE'
-     The condition codes on the ARCtangent A4 are extensible and can be
-     specified by means of this assembler directive.  They are specified
-     by the suffix and the value for the condition code.  They can be
-     used to specify extra condition codes with any values.  For
-     example:
-
-            .extCondCode is_busy,0x14
-
-             add.is_busy  r1,r2,r3
-             bis_busy     _main
-
-`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT'
-     Specifies an extension core register NAME for the application.
-     This allows a register NAME with a valid REGNUM between 0 and 60,
-     with the following as valid values for MODE
-
-    `_r_   (readonly)'
-
-    `_w_   (write only)'
-
-    `_r|w_ (read or write)'
-
-     The other parameter gives a description of the register having a
-     SHORTCUT in the pipeline.  The valid values are:
-
-    `can_shortcut'
-
-    `cannot_shortcut'
-
-     For example:
-
-            .extCoreRegister mlo,57,r,can_shortcut
-
-     This defines an extension core register mlo with the value 57 which
-     can shortcut the pipeline.
-
-`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS'
-     The ARCtangent A4 allows the user to specify extension
-     instructions.  The extension instructions are not macros.  The
-     assembler creates encodings for use of these instructions
-     according to the specification by the user.  The parameters are:
-
-    *NAME
-          Name of the extension instruction
-
-    *OPCODE
-          Opcode to be used. (Bits 27:31 in the encoding).  Valid values
-          0x10-0x1f or 0x03
-
-    *SUBOPCODE
-          Subopcode to be used.  Valid values are from 0x09-0x3f.
-          However the correct value also depends on SYNTAXCLASS
-
-    *SUFFIXCLASS
-          Determines the kinds of suffixes to be allowed.  Valid values
-          are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which
-          indicates the absence or presence of conditional suffixes and
-          flag setting by the extension instruction.  It is also
-          possible to specify that an instruction sets the flags and is
-          conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'.
-
-    *SYNTAXCLASS
-          Determines the syntax class for the instruction.  It can have
-          the following values:
-
-         ``SYNTAX_2OP':'
-               2 Operand Instruction
-
-         ``SYNTAX_3OP':'
-               3 Operand Instruction
-
-          In addition there could be modifiers for the syntax class as
-          described below:
-
-               Syntax Class Modifiers are:
-
-             - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP,
-               specifying that the first operand of a three-operand
-               instruction must be an immediate (i.e. the result is
-               discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it
-               with SYNTAX_3OP as given in the example below.  This
-               could usually be used to set the flags using specific
-               instructions and not retain results.
-
-             - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it
-               specifies that there is an implied immediate destination
-               operand which does not appear in the syntax.  For
-               example, if the source code contains an instruction like:
-
-                    inst r1,r2
-
-               it really means that the first argument is an implied
-               immediate (that is, the result is discarded).  This is
-               the same as though the source code were: inst 0,r1,r2.
-               You use OP1_IMM_IMPLIED by bitwise ORing it with
-               SYNTAX_20P.
-
-
-     For example, defining 64-bit multiplier with immediate operands:
-
-          .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
-                          SYNTAX_3OP|OP1_MUST_BE_IMM
-
-     The above specifies an extension instruction called mp64 which has
-     3 operands, sets the flags, can be used with a condition code, for
-     which the first operand is an immediate.  (Equivalent to
-     discarding the result of the operation).
-
-           .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
-
-     This describes a 2 operand instruction with an implicit first
-     immediate operand.  The result of this operation would be
-     discarded.
-
-`.half EXPRESSIONS'
-     *TODO*
-
-`.long EXPRESSIONS'
-     *TODO*
-
-`.option ARC|ARC5|ARC6|ARC7|ARC8'
-     The `.option' directive must be followed by the desired core
-     version. Again `arc' is an alias for `arc6'.
-
-     Note: the `.option' directive overrides the command line option
-     `-marc'; a warning is emitted when the version is not consistent
-     between the two - even for the implicit default core version
-     (arc6).
-
-`.short EXPRESSIONS'
-     *TODO*
-
-`.word EXPRESSIONS'
-     *TODO*
-
-
-
-File: as.info,  Node: ARC Opcodes,  Prev: ARC Directives,  Up: ARC-Dependent
-
-8.2.5 Opcodes
--------------
-
-For information on the ARC instruction set, see `ARC Programmers
-Reference Manual', ARC International (www.arc.com)
-
-
-File: as.info,  Node: ARM-Dependent,  Next: BFIN-Dependent,  Prev: ARC-Dependent,  Up: Machine Dependencies
-
-8.3 ARM Dependent Features
-==========================
-
-* Menu:
-
-* ARM Options::              Options
-* ARM Syntax::               Syntax
-* ARM Floating Point::       Floating Point
-* ARM Directives::           ARM Machine Directives
-* ARM Opcodes::              Opcodes
-* ARM Mapping Symbols::      Mapping Symbols
-
-
-File: as.info,  Node: ARM Options,  Next: ARM Syntax,  Up: ARM-Dependent
-
-8.3.1 Options
--------------
-
-`-mcpu=PROCESSOR[+EXTENSION...]'
-     This option specifies the target processor.  The assembler will
-     issue an error message if an attempt is made to assemble an
-     instruction which will not execute on the target processor.  The
-     following processor names are recognized: `arm1', `arm2', `arm250',
-     `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
-     `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
-     `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t',
-     `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
-     `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
-     `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
-     `arm920t', `arm922t', `arm940t', `arm9tdmi', `arm9e', `arm926e',
-     `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', `arm966e-r0',
-     `arm966e', `arm966e-s', `arm968e-s', `arm10t', `arm10tdmi',
-     `arm10e', `arm1020', `arm1020t', `arm1020e', `arm1022e',
-     `arm1026ej-s', `arm1136j-s', `arm1136jf-s', `arm1156t2-s',
-     `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', `mpcore',
-     `mpcorenovfp', `cortex-a8', `cortex-r4', `cortex-m3', `ep9312'
-     (ARM920 with Cirrus Maverick coprocessor), `i80200' (Intel XScale
-     processor) `iwmmxt' (Intel(r) XScale processor with Wireless
-     MMX(tm) technology coprocessor) and `xscale'.  The special name
-     `all' may be used to allow the assembler to accept instructions
-     valid for any ARM processor.
-
-     In addition to the basic instruction set, the assembler can be
-     told to accept various extension mnemonics that extend the
-     processor using the co-processor instruction space.  For example,
-     `-mcpu=arm920+maverick' is equivalent to specifying
-     `-mcpu=ep9312'.  The following extensions are currently supported:
-     `+maverick' `+iwmmxt' and `+xscale'.
-
-`-march=ARCHITECTURE[+EXTENSION...]'
-     This option specifies the target architecture.  The assembler will
-     issue an error message if an attempt is made to assemble an
-     instruction which will not execute on the target architecture.
-     The following architecture names are recognized: `armv1', `armv2',
-     `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm',
-     `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te',
-     `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk',
-     `armv7', `armv7a', `armv7r', `armv7m', `iwmmxt' and `xscale'.  If
-     both `-mcpu' and `-march' are specified, the assembler will use
-     the setting for `-mcpu'.
-
-     The architecture option can be extended with the same instruction
-     set extension options as the `-mcpu' option.
-
-`-mfpu=FLOATING-POINT-FORMAT'
-     This option specifies the floating point format to assemble for.
-     The assembler will issue an error message if an attempt is made to
-     assemble an instruction which will not execute on the target
-     floating point unit.  The following format options are recognized:
-     `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
-     `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
-     `vfp9', `vfpxd', `arm1020t', `arm1020e', `arm1136jf-s' and
-     `maverick'.
-
-     In addition to determining which instructions are assembled, this
-     option also affects the way in which the `.double' assembler
-     directive behaves when assembling little-endian code.
-
-     The default is dependent on the processor selected.  For
-     Architecture 5 or later, the default is to assembler for VFP
-     instructions; for earlier architectures the default is to assemble
-     for FPA instructions.
-
-`-mthumb'
-     This option specifies that the assembler should start assembling
-     Thumb instructions; that is, it should behave as though the file
-     starts with a `.code 16' directive.
-
-`-mthumb-interwork'
-     This option specifies that the output generated by the assembler
-     should be marked as supporting interworking.
-
-`-mapcs `[26|32]''
-     This option specifies that the output generated by the assembler
-     should be marked as supporting the indicated version of the Arm
-     Procedure.  Calling Standard.
-
-`-matpcs'
-     This option specifies that the output generated by the assembler
-     should be marked as supporting the Arm/Thumb Procedure Calling
-     Standard.  If enabled this option will cause the assembler to
-     create an empty debugging section in the object file called
-     .arm.atpcs.  Debuggers can use this to determine the ABI being
-     used by.
-
-`-mapcs-float'
-     This indicates the floating point variant of the APCS should be
-     used.  In this variant floating point arguments are passed in FP
-     registers rather than integer registers.
-
-`-mapcs-reentrant'
-     This indicates that the reentrant variant of the APCS should be
-     used.  This variant supports position independent code.
-
-`-mfloat-abi=ABI'
-     This option specifies that the output generated by the assembler
-     should be marked as using specified floating point ABI.  The
-     following values are recognized: `soft', `softfp' and `hard'.
-
-`-meabi=VER'
-     This option specifies which EABI version the produced object files
-     should conform to.  The following values are recognised: `gnu', `4'
-     and `5'.
-
-`-EB'
-     This option specifies that the output generated by the assembler
-     should be marked as being encoded for a big-endian processor.
-
-`-EL'
-     This option specifies that the output generated by the assembler
-     should be marked as being encoded for a little-endian processor.
-
-`-k'
-     This option specifies that the output of the assembler should be
-     marked as position-independent code (PIC).
-
-
-
-File: as.info,  Node: ARM Syntax,  Next: ARM Floating Point,  Prev: ARM Options,  Up: ARM-Dependent
-
-8.3.2 Syntax
-------------
-
-* Menu:
-
-* ARM-Chars::                Special Characters
-* ARM-Regs::                 Register Names
-
-
-File: as.info,  Node: ARM-Chars,  Next: ARM-Regs,  Up: ARM Syntax
-
-8.3.2.1 Special Characters
-..........................
-
-The presence of a `@' on a line indicates the start of a comment that
-extends to the end of the current line.  If a `#' appears as the first
-character of a line, the whole line is treated as a comment.
-
-   The `;' character can be used instead of a newline to separate
-statements.
-
-   Either `#' or `$' can be used to indicate immediate operands.
-
-   *TODO* Explain about /data modifier on symbols.
-
-
-File: as.info,  Node: ARM-Regs,  Prev: ARM-Chars,  Up: ARM Syntax
-
-8.3.2.2 Register Names
-......................
-
-*TODO* Explain about ARM register naming, and the predefined names.
-
-
-File: as.info,  Node: ARM Floating Point,  Next: ARM Directives,  Prev: ARM Syntax,  Up: ARM-Dependent
-
-8.3.3 Floating Point
---------------------
-
-The ARM family uses IEEE floating-point numbers.
-
-
-File: as.info,  Node: ARM Directives,  Next: ARM Opcodes,  Prev: ARM Floating Point,  Up: ARM-Dependent
-
-8.3.4 ARM Machine Directives
-----------------------------
-
-`.align EXPRESSION [, EXPRESSION]'
-     This is the generic .ALIGN directive.  For the ARM however if the
-     first argument is zero (ie no alignment is needed) the assembler
-     will behave as if the argument had been 2 (ie pad to the next four
-     byte boundary).  This is for compatibility with ARM's own
-     assembler.
-
-`NAME .req REGISTER NAME'
-     This creates an alias for REGISTER NAME called NAME.  For example:
-
-                  foo .req r0
-
-`.unreq ALIAS-NAME'
-     This undefines a register alias which was previously defined using
-     the `req' directive.  For example:
-
-                  foo .req r0
-                  .unreq foo
-
-     An error occurs if the name is undefined.  Note - this pseudo op
-     can be used to delete builtin in register name aliases (eg 'r0').
-     This should only be done if it is really necessary.
-
-`.code `[16|32]''
-     This directive selects the instruction set being generated. The
-     value 16 selects Thumb, with the value 32 selecting ARM.
-
-`.thumb'
-     This performs the same action as .CODE 16.
-
-`.arm'
-     This performs the same action as .CODE 32.
-
-`.force_thumb'
-     This directive forces the selection of Thumb instructions, even if
-     the target processor does not support those instructions
-
-`.thumb_func'
-     This directive specifies that the following symbol is the name of a
-     Thumb encoded function.  This information is necessary in order to
-     allow the assembler and linker to generate correct code for
-     interworking between Arm and Thumb instructions and should be used
-     even if interworking is not going to be performed.  The presence
-     of this directive also implies `.thumb'
-
-`.thumb_set'
-     This performs the equivalent of a `.set' directive in that it
-     creates a symbol which is an alias for another symbol (possibly
-     not yet defined).  This directive also has the added property in
-     that it marks the aliased symbol as being a thumb function entry
-     point, in the same way that the `.thumb_func' directive does.
-
-`.ltorg'
-     This directive causes the current contents of the literal pool to
-     be dumped into the current section (which is assumed to be the
-     .text section) at the current location (aligned to a word
-     boundary).  `GAS' maintains a separate literal pool for each
-     section and each sub-section.  The `.ltorg' directive will only
-     affect the literal pool of the current section and sub-section.
-     At the end of assembly all remaining, un-empty literal pools will
-     automatically be dumped.
-
-     Note - older versions of `GAS' would dump the current literal pool
-     any time a section change occurred.  This is no longer done, since
-     it prevents accurate control of the placement of literal pools.
-
-`.pool'
-     This is a synonym for .ltorg.
-
-`.unwind_fnstart'
-     Marks the start of a function with an unwind table entry.
-
-`.unwind_fnend'
-     Marks the end of a function with an unwind table entry.  The
-     unwind index table entry is created when this directive is
-     processed.
-
-     If no personality routine has been specified then standard
-     personality routine 0 or 1 will be used, depending on the number
-     of unwind opcodes required.
-
-`.cantunwind'
-     Prevents unwinding through the current function.  No personality
-     routine or exception table data is required or permitted.
-
-`.personality NAME'
-     Sets the personality routine for the current function to NAME.
-
-`.personalityindex INDEX'
-     Sets the personality routine for the current function to the EABI
-     standard routine number INDEX
-
-`.handlerdata'
-     Marks the end of the current function, and the start of the
-     exception table entry for that function.  Anything between this
-     directive and the `.fnend' directive will be added to the
-     exception table entry.
-
-     Must be preceded by a `.personality' or `.personalityindex'
-     directive.
-
-`.save REGLIST'
-     Generate unwinder annotations to restore the registers in REGLIST.
-     The format of REGLIST is the same as the corresponding
-     store-multiple instruction.
-
-     _core registers_
-            .save {r4, r5, r6, lr}
-            stmfd sp!, {r4, r5, r6, lr}
-     _FPA registers_
-            .save f4, 2
-            sfmfd f4, 2, [sp]!
-     _VFP registers_
-            .save {d8, d9, d10}
-            fstmdf sp!, {d8, d9, d10}
-     _iWMMXt registers_
-            .save {wr10, wr11}
-            wstrd wr11, [sp, #-8]!
-            wstrd wr10, [sp, #-8]!
-          or
-            .save wr11
-            wstrd wr11, [sp, #-8]!
-            .save wr10
-            wstrd wr10, [sp, #-8]!
-
-`.pad #COUNT'
-     Generate unwinder annotations for a stack adjustment of COUNT
-     bytes.  A positive value indicates the function prologue allocated
-     stack space by decrementing the stack pointer.
-
-`.movsp REG'
-     Tell the unwinder that REG contains the current stack pointer.
-
-`.setfp FPREG, SPREG [, #OFFSET]'
-     Make all unwinder annotations relaive to a frame pointer.  Without
-     this the unwinder will use offsets from the stack pointer.
-
-     The syntax of this directive is the same as the `sub' or `mov'
-     instruction used to set the frame pointer.  SPREG must be either
-     `sp' or mentioned in a previous `.movsp' directive.
-
-          .movsp ip
-          mov ip, sp
-          ...
-          .setfp fp, ip, #4
-          sub fp, ip, #4
-
-`.raw OFFSET, BYTE1, ...'
-     Insert one of more arbitary unwind opcode bytes, which are known
-     to adjust the stack pointer by OFFSET bytes.
-
-     For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
-     {r0}'
-
-`.cpu NAME'
-     Select the target processor.  Valid values for NAME are the same as
-     for the `-mcpu' commandline option.
-
-`.arch NAME'
-     Select the target architecture.  Valid values for NAME are the
-     same as for the `-march' commandline option.
-
-`.fpu NAME'
-     Select the floating point unit to assemble for.  Valid values for
-     NAME are the same as for the `-mfpu' commandline option.
-
-`.eabi_attribute TAG, VALUE'
-     Set the EABI object attribute number TAG to VALUE.  The value is
-     either a `number', `"string"', or `number, "string"' depending on
-     the tag.
-
-
-
-File: as.info,  Node: ARM Opcodes,  Next: ARM Mapping Symbols,  Prev: ARM Directives,  Up: ARM-Dependent
-
-8.3.5 Opcodes
--------------
-
-`as' implements all the standard ARM opcodes.  It also implements
-several pseudo opcodes, including several synthetic load instructions.
-
-`NOP'
-            nop
-
-     This pseudo op will always evaluate to a legal ARM instruction
-     that does nothing.  Currently it will evaluate to MOV r0, r0.
-
-`LDR'
-            ldr <register> , = <expression>
-
-     If expression evaluates to a numeric constant then a MOV or MVN
-     instruction will be used in place of the LDR instruction, if the
-     constant can be generated by either of these instructions.
-     Otherwise the constant will be placed into the nearest literal
-     pool (if it not already there) and a PC relative LDR instruction
-     will be generated.
-
-`ADR'
-            adr <register> <label>
-
-     This instruction will load the address of LABEL into the indicated
-     register.  The instruction will evaluate to a PC relative ADD or
-     SUB instruction depending upon where the label is located.  If the
-     label is out of range, or if it is not defined in the same file
-     (and section) as the ADR instruction, then an error will be
-     generated.  This instruction will not make use of the literal pool.
-
-`ADRL'
-            adrl <register> <label>
-
-     This instruction will load the address of LABEL into the indicated
-     register.  The instruction will evaluate to one or two PC relative
-     ADD or SUB instructions depending upon where the label is located.
-     If a second instruction is not needed a NOP instruction will be
-     generated in its place, so that this instruction is always 8 bytes
-     long.
-
-     If the label is out of range, or if it is not defined in the same
-     file (and section) as the ADRL instruction, then an error will be
-     generated.  This instruction will not make use of the literal pool.
-
-
-   For information on the ARM or Thumb instruction sets, see `ARM
-Software Development Toolkit Reference Manual', Advanced RISC Machines
-Ltd.
-
-
-File: as.info,  Node: ARM Mapping Symbols,  Prev: ARM Opcodes,  Up: ARM-Dependent
-
-8.3.6 Mapping Symbols
----------------------
-
-The ARM ELF specification requires that special symbols be inserted
-into object files to mark certain features:
-
-`$a'
-     At the start of a region of code containing ARM instructions.
-
-`$t'
-     At the start of a region of code containing THUMB instructions.
-
-`$d'
-     At the start of a region of data.
-
-
-   The assembler will automatically insert these symbols for you - there
-is no need to code them yourself.  Support for tagging symbols ($b, $f,
-$p and $m) which is also mentioned in the current ARM ELF specification
-is not implemented.  This is because they have been dropped from the
-new EABI and so tools cannot rely upon their presence.
-
-
-File: as.info,  Node: BFIN-Dependent,  Next: CRIS-Dependent,  Prev: ARM-Dependent,  Up: Machine Dependencies
-
-8.4 Blackfin Dependent Features
-===============================
-
-* Menu:
-
-* BFIN Syntax::			BFIN Syntax
-* BFIN Directives::		BFIN Directives
-
-
-File: as.info,  Node: BFIN Syntax,  Next: BFIN Directives,  Up: BFIN-Dependent
-
-8.4.1 Syntax
-------------
-
-`Special Characters'
-     Assembler input is free format and may appear anywhere on the line.
-     One instruction may extend across multiple lines or more than one
-     instruction may appear on the same line.  White space (space, tab,
-     comments or newline) may appear anywhere between tokens.  A token
-     must not have embedded spaces.  Tokens include numbers, register
-     names, keywords, user identifiers, and also some multicharacter
-     special symbols like "+=", "/*" or "||".
-
-`Instruction Delimiting'
-     A semicolon must terminate every instruction.  Sometimes a complete
-     instruction will consist of more than one operation.  There are two
-     cases where this occurs.  The first is when two general operations
-     are combined.  Normally a comma separates the different parts, as
-     in
-
-          a0= r3.h * r2.l, a1 = r3.l * r2.h ;
-
-     The second case occurs when a general instruction is combined with
-     one or two memory references for joint issue.  The latter portions
-     are set off by a "||" token.
-
-          a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
-
-`Register Names'
-     The assembler treats register names and instruction keywords in a
-     case insensitive manner.  User identifiers are case sensitive.
-     Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
-     assembler.
-
-     Register names are reserved and may not be used as program
-     identifiers.
-
-     Some operations (such as "Move Register") require a register pair.
-     Register pairs are always data registers and are denoted using a
-     colon, eg., R3:2.  The larger number must be written firsts.  Note
-     that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
-     R3:2, and R1:0.
-
-     Some instructions (such as -SP (Push Multiple)) require a group of
-     adjacent registers.  Adjacent registers are denoted in the syntax
-     by the range enclosed in parentheses and separated by a colon,
-     eg., (R7:3).  Again, the larger number appears first.
-
-     Portions of a particular register may be individually specified.
-     This is written with a dot (".") following the register name and
-     then a letter denoting the desired portion.  For 32-bit registers,
-     ".H" denotes the most significant ("High") portion.  ".L" denotes
-     the least-significant portion.  The subdivisions of the 40-bit
-     registers are described later.
-
-`Accumulators'
-     The set of 40-bit registers A1 and A0 that normally contain data
-     that is being manipulated.  Each accumulator can be accessed in
-     four ways.
-
-    `one 40-bit register'
-          The register will be referred to as A1 or A0.
-
-    `one 32-bit register'
-          The registers are designated as A1.W or A0.W.
-
-    `two 16-bit registers'
-          The registers are designated as A1.H, A1.L, A0.H or A0.L.
-
-    `one 8-bit register'
-          The registers are designated as A1.X or A0.X for the bits that
-          extend beyond bit 31.
-
-`Data Registers'
-     The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
-     that normally contain data for manipulation.  These are
-     abbreviated as D-register or Dreg.  Data registers can be accessed
-     as 32-bit registers or as two independent 16-bit registers.  The
-     least significant 16 bits of each register is called the "low"
-     half and is desginated with ".L" following the register name.  The
-     most significant 16 bits are called the "high" half and is
-     designated with ".H". following the name.
-
-             R7.L, r2.h, r4.L, R0.H
-
-`Pointer Registers'
-     The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
-     that normally contain byte addresses of data structures.  These are
-     abbreviated as P-register or Preg.
-
-          p2, p5, fp, sp
-
-`Stack Pointer SP'
-     The stack pointer contains the 32-bit address of the last occupied
-     byte location in the stack.  The stack grows by decrementing the
-     stack pointer.
-
-`Frame Pointer FP'
-     The frame pointer contains the 32-bit address of the previous frame
-     pointer in the stack.  It is located at the top of a frame.
-
-`Loop Top'
-     LT0 and LT1.  These registers contain the 32-bit address of the
-     top of a zero overhead loop.
-
-`Loop Count'
-     LC0 and LC1.  These registers contain the 32-bit counter of the
-     zero overhead loop executions.
-
-`Loop Bottom'
-     LB0 and LB1.  These registers contain the 32-bit address of the
-     bottom of a zero overhead loop.
-
-`Index Registers'
-     The set of 32-bit registers (I0, I1, I2, I3) that normally contain
-     byte addresses of data structures.  Abbreviated I-register or Ireg.
-
-`Modify Registers'
-     The set of 32-bit registers (M0, M1, M2, M3) that normally contain
-     offset values that are added and subracted to one of the index
-     registers.  Abbreviated as Mreg.
-
-`Length Registers'
-     The set of 32-bit registers (L0, L1, L2, L3) that normally contain
-     the length in bytes of the circular buffer.  Abbreviated as Lreg.
-     Clear the Lreg to disable circular addressing for the
-     corresponding Ireg.
-
-`Base Registers'
-     The set of 32-bit registers (B0, B1, B2, B3) that normally contain
-     the base address in bytes of the circular buffer.  Abbreviated as
-     Breg.
-
-`Floating Point'
-     The Blackfin family has no hardware floating point but the .float
-     directive generates ieee floating point numbers for use with
-     software floating point libraries.
-
-`Blackfin Opcodes'
-     For detailed information on the Blackfin machine instruction set,
-     see the Blackfin(r) Processor Instruction Set Reference.
-
-
-
-File: as.info,  Node: BFIN Directives,  Prev: BFIN Syntax,  Up: BFIN-Dependent
-
-8.4.2 Directives
-----------------
-
-The following directives are provided for compatibility with the VDSP
-assembler.
-
-`.byte2'
-     Initializes a four byte data object.
-
-`.byte4'
-     Initializes a two byte data object.
-
-`.db'
-     TBD
-
-`.dd'
-     TBD
-
-`.dw'
-     TBD
-
-`.var'
-     Define and initialize a 32 bit data object.
-
-
-File: as.info,  Node: CRIS-Dependent,  Next: D10V-Dependent,  Prev: BFIN-Dependent,  Up: Machine Dependencies
-
-8.5 CRIS Dependent Features
-===========================
-
-* Menu:
-
-* CRIS-Opts::              Command-line Options
-* CRIS-Expand::            Instruction expansion
-* CRIS-Symbols::           Symbols
-* CRIS-Syntax::            Syntax
-
-
-File: as.info,  Node: CRIS-Opts,  Next: CRIS-Expand,  Up: CRIS-Dependent
-
-8.5.1 Command-line Options
---------------------------
-
-The CRIS version of `as' has these machine-dependent command-line
-options.
-
-   The format of the generated object files can be either ELF or a.out,
-specified by the command-line options `--emulation=crisaout' and
-`--emulation=criself'.  The default is ELF (criself), unless `as' has
-been configured specifically for a.out by using the configuration name
-`cris-axis-aout'.
-
-   There are two different link-incompatible ELF object file variants
-for CRIS, for use in environments where symbols are expected to be
-prefixed by a leading `_' character and for environments without such a
-symbol prefix.  The variant used for GNU/Linux port has no symbol
-prefix.  Which variant to produce is specified by either of the options
-`--underscore' and `--no-underscore'.  The default is `--underscore'.
-Since symbols in CRIS a.out objects are expected to have a `_' prefix,
-specifying `--no-underscore' when generating a.out objects is an error.
-Besides the object format difference, the effect of this option is to
-parse register names differently (*note crisnous::).  The
-`--no-underscore' option makes a `$' register prefix mandatory.
-
-   The option `--pic' must be passed to `as' in order to recognize the
-symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
-crispic::).  This will also affect expansion of instructions.  The
-expansion with `--pic' will use PC-relative rather than (slightly
-faster) absolute addresses in those expansions.
-
-   The option `--march=ARCHITECTURE' specifies the recognized
-instruction set and recognized register names.  It also controls the
-architecture type of the object file.  Valid values for ARCHITECTURE
-are:
-`v0_v10'
-     All instructions and register names for any architecture variant
-     in the set v0...v10 are recognized.  This is the default if the
-     target is configured as cris-*.
-
-`v10'
-     Only instructions and register names for CRIS v10 (as found in
-     ETRAX 100 LX) are recognized.  This is the default if the target
-     is configured as crisv10-*.
-
-`v32'
-     Only instructions and register names for CRIS v32 (code name
-     Guinness) are recognized.  This is the default if the target is
-     configured as crisv32-*.  This value implies `--no-mul-bug-abort'.
-     (A subsequent `--mul-bug-abort' will turn it back on.)
-
-`common_v10_v32'
-     Only instructions with register names and addressing modes with
-     opcodes common to the v10 and v32 are recognized.
-
-   When `-N' is specified, `as' will emit a warning when a 16-bit
-branch instruction is expanded into a 32-bit multiple-instruction
-construct (*note CRIS-Expand::).
-
-   Some versions of the CRIS v10, for example in the Etrax 100 LX,
-contain a bug that causes destabilizing memory accesses when a multiply
-instruction is executed with certain values in the first operand just
-before a cache-miss.  When the `--mul-bug-abort' command line option is
-active (the default value), `as' will refuse to assemble a file
-containing a multiply instruction at a dangerous offset, one that could
-be the last on a cache-line, or is in a section with insufficient
-alignment.  This placement checking does not catch any case where the
-multiply instruction is dangerously placed because it is located in a
-delay-slot.  The `--mul-bug-abort' command line option turns off the
-checking.
-
-
-File: as.info,  Node: CRIS-Expand,  Next: CRIS-Symbols,  Prev: CRIS-Opts,  Up: CRIS-Dependent
-
-8.5.2 Instruction expansion
----------------------------
-
-`as' will silently choose an instruction that fits the operand size for
-`[register+constant]' operands.  For example, the offset `127' in
-`move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
-Similarly, `move.d [r2+32767],r1' will generate an instruction using a
-16-bit offset.  For symbolic expressions and constants that do not fit
-in 16 bits including the sign bit, a 32-bit offset is generated.
-
-   For branches, `as' will expand from a 16-bit branch instruction into
-a sequence of instructions that can reach a full 32-bit address.  Since
-this does not correspond to a single instruction, such expansions can
-optionally be warned about.  *Note CRIS-Opts::.
-
-   If the operand is found to fit the range, a `lapc' mnemonic will
-translate to a `lapcq' instruction.  Use `lapc.d' to force the 32-bit
-`lapc' instruction.
-
-   Similarly, the `addo' mnemonic will translate to the shortest
-fitting instruction of `addoq', `addo.w' and `addo.d', when used with a
-operand that is a constant known at assembly time.
-
-
-File: as.info,  Node: CRIS-Symbols,  Next: CRIS-Syntax,  Prev: CRIS-Expand,  Up: CRIS-Dependent
-
-8.5.3 Symbols
--------------
-
-Some symbols are defined by the assembler.  They're intended to be used
-in conditional assembly, for example:
-      .if ..asm.arch.cris.v32
-      CODE FOR CRIS V32
-      .elseif ..asm.arch.cris.common_v10_v32
-      CODE COMMON TO CRIS V32 AND CRIS V10
-      .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
-      CODE FOR V10
-      .else
-      .error "Code needs to be added here."
-      .endif
-
-   These symbols are defined in the assembler, reflecting command-line
-options, either when specified or the default.  They are always
-defined, to 0 or 1.
-`..asm.arch.cris.any_v0_v10'
-     This symbol is non-zero when `--march=v0_v10' is specified or the
-     default.
-
-`..asm.arch.cris.common_v10_v32'
-     Set according to the option `--march=common_v10_v32'.
-
-`..asm.arch.cris.v10'
-     Reflects the option `--march=v10'.
-
-`..asm.arch.cris.v32'
-     Corresponds to `--march=v10'.
-
-   Speaking of symbols, when a symbol is used in code, it can have a
-suffix modifying its value for use in position-independent code. *Note
-CRIS-Pic::.
-
-
-File: as.info,  Node: CRIS-Syntax,  Prev: CRIS-Symbols,  Up: CRIS-Dependent
-
-8.5.4 Syntax
-------------
-
-There are different aspects of the CRIS assembly syntax.
-
-* Menu:
-
-* CRIS-Chars::		        Special Characters
-* CRIS-Pic::			Position-Independent Code Symbols
-* CRIS-Regs::			Register Names
-* CRIS-Pseudos::		Assembler Directives
-
-
-File: as.info,  Node: CRIS-Chars,  Next: CRIS-Pic,  Up: CRIS-Syntax
-
-8.5.4.1 Special Characters
-..........................
-
-The character `#' is a line comment character.  It starts a comment if
-and only if it is placed at the beginning of a line.
-
-   A `;' character starts a comment anywhere on the line, causing all
-characters up to the end of the line to be ignored.
-
-   A `@' character is handled as a line separator equivalent to a
-logical new-line character (except in a comment), so separate
-instructions can be specified on a single line.
-
-
-File: as.info,  Node: CRIS-Pic,  Next: CRIS-Regs,  Prev: CRIS-Chars,  Up: CRIS-Syntax
-
-8.5.4.2 Symbols in position-independent code
-............................................
-
-When generating position-independent code (SVR4 PIC) for use in
-cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
-suffixes are used to specify what kind of run-time symbol lookup will
-be used, expressed in the object as different _relocation types_.
-Usually, all absolute symbol values must be located in a table, the
-_global offset table_, leaving the code position-independent;
-independent of values of global symbols and independent of the address
-of the code.  The suffix modifies the value of the symbol, into for
-example an index into the global offset table where the real symbol
-value is entered, or a PC-relative value, or a value relative to the
-start of the global offset table.  All symbol suffixes start with the
-character `:' (omitted in the list below).  Every symbol use in code or
-a read-only section must therefore have a PIC suffix to enable a useful
-shared library to be created.  Usually, these constructs must not be
-used with an additive constant offset as is usually allowed, i.e. no 4
-as in `symbol + 4' is allowed.  This restriction is checked at
-link-time, not at assembly-time.
-
-`GOT'
-     Attaching this suffix to a symbol in an instruction causes the
-     symbol to be entered into the global offset table.  The value is a
-     32-bit index for that symbol into the global offset table.  The
-     name of the corresponding relocation is `R_CRIS_32_GOT'.  Example:
-     `move.d [$r0+extsym:GOT],$r9'
-
-`GOT16'
-     Same as for `GOT', but the value is a 16-bit index into the global
-     offset table.  The corresponding relocation is `R_CRIS_16_GOT'.
-     Example: `move.d [$r0+asymbol:GOT16],$r10'
-
-`PLT'
-     This suffix is used for function symbols.  It causes a _procedure
-     linkage table_, an array of code stubs, to be created at the time
-     the shared object is created or linked against, together with a
-     global offset table entry.  The value is a pc-relative offset to
-     the corresponding stub code in the procedure linkage table.  This
-     arrangement causes the run-time symbol resolver to be called to
-     look up and set the value of the symbol the first time the
-     function is called (at latest; depending environment variables).
-     It is only safe to leave the symbol unresolved this way if all
-     references are function calls.  The name of the relocation is
-     `R_CRIS_32_PLT_PCREL'.  Example: `add.d fnname:PLT,$pc'
-
-`PLTG'
-     Like PLT, but the value is relative to the beginning of the global
-     offset table.  The relocation is `R_CRIS_32_PLT_GOTREL'.  Example:
-     `move.d fnname:PLTG,$r3'
-
-`GOTPLT'
-     Similar to `PLT', but the value of the symbol is a 32-bit index
-     into the global offset table.  This is somewhat of a mix between
-     the effect of the `GOT' and the `PLT' suffix; the difference to
-     `GOT' is that there will be a procedure linkage table entry
-     created, and that the symbol is assumed to be a function entry and
-     will be resolved by the run-time resolver as with `PLT'.  The
-     relocation is `R_CRIS_32_GOTPLT'.  Example: `jsr
-     [$r0+fnname:GOTPLT]'
-
-`GOTPLT16'
-     A variant of `GOTPLT' giving a 16-bit value.  Its relocation name
-     is `R_CRIS_16_GOTPLT'.  Example: `jsr [$r0+fnname:GOTPLT16]'
-
-`GOTOFF'
-     This suffix must only be attached to a local symbol, but may be
-     used in an expression adding an offset.  The value is the address
-     of the symbol relative to the start of the global offset table.
-     The relocation name is `R_CRIS_32_GOTREL'.  Example: `move.d
-     [$r0+localsym:GOTOFF],r3'
-
-
-File: as.info,  Node: CRIS-Regs,  Next: CRIS-Pseudos,  Prev: CRIS-Pic,  Up: CRIS-Syntax
-
-8.5.4.3 Register names
-......................
-
-A `$' character may always prefix a general or special register name in
-an instruction operand but is mandatory when the option
-`--no-underscore' is specified or when the `.syntax register_prefix'
-directive is in effect (*note crisnous::).  Register names are
-case-insensitive.
-
-
-File: as.info,  Node: CRIS-Pseudos,  Prev: CRIS-Regs,  Up: CRIS-Syntax
-
-8.5.4.4 Assembler Directives
-............................
-
-There are a few CRIS-specific pseudo-directives in addition to the
-generic ones.  *Note Pseudo Ops::.  Constants emitted by
-pseudo-directives are in little-endian order for CRIS.  There is no
-support for floating-point-specific directives for CRIS.
-
-`.dword EXPRESSIONS'
-     The `.dword' directive is a synonym for `.int', expecting zero or
-     more EXPRESSIONS, separated by commas.  For each expression, a
-     32-bit little-endian constant is emitted.
-
-`.syntax ARGUMENT'
-     The `.syntax' directive takes as ARGUMENT one of the following
-     case-sensitive choices.
-
-    `no_register_prefix'
-          The `.syntax no_register_prefix' directive makes a `$'
-          character prefix on all registers optional.  It overrides a
-          previous setting, including the corresponding effect of the
-          option `--no-underscore'.  If this directive is used when
-          ordinary symbols do not have a `_' character prefix, care
-          must be taken to avoid ambiguities whether an operand is a
-          register or a symbol; using symbols with names the same as
-          general or special registers then invoke undefined behavior.
-
-    `register_prefix'
-          This directive makes a `$' character prefix on all registers
-          mandatory.  It overrides a previous setting, including the
-          corresponding effect of the option `--underscore'.
-
-    `leading_underscore'
-          This is an assertion directive, emitting an error if the
-          `--no-underscore' option is in effect.
-
-    `no_leading_underscore'
-          This is the opposite of the `.syntax leading_underscore'
-          directive and emits an error if the option `--underscore' is
-          in effect.
-
-`.arch ARGUMENT'
-     This is an assertion directive, giving an error if the specified
-     ARGUMENT is not the same as the specified or default value for the
-     `--march=ARCHITECTURE' option (*note march-option::).
-
-
-
-File: as.info,  Node: D10V-Dependent,  Next: D30V-Dependent,  Prev: CRIS-Dependent,  Up: Machine Dependencies
-
-8.6 D10V Dependent Features
-===========================
-
-* Menu:
-
-* D10V-Opts::                   D10V Options
-* D10V-Syntax::                 Syntax
-* D10V-Float::                  Floating Point
-* D10V-Opcodes::                Opcodes
-
-
-File: as.info,  Node: D10V-Opts,  Next: D10V-Syntax,  Up: D10V-Dependent
-
-8.6.1 D10V Options
-------------------
-
-The Mitsubishi D10V version of `as' has a few machine dependent options.
-
-`-O'
-     The D10V can often execute two sub-instructions in parallel. When
-     this option is used, `as' will attempt to optimize its output by
-     detecting when instructions can be executed in parallel.
-
-`--nowarnswap'
-     To optimize execution performance, `as' will sometimes swap the
-     order of instructions. Normally this generates a warning. When
-     this option is used, no warning will be generated when
-     instructions are swapped.
-
-`--gstabs-packing'
-
-`--no-gstabs-packing'
-     `as' packs adjacent short instructions into a single packed
-     instruction. `--no-gstabs-packing' turns instruction packing off if
-     `--gstabs' is specified as well; `--gstabs-packing' (the default)
-     turns instruction packing on even when `--gstabs' is specified.
-
-
-File: as.info,  Node: D10V-Syntax,  Next: D10V-Float,  Prev: D10V-Opts,  Up: D10V-Dependent
-
-8.6.2 Syntax
-------------
-
-The D10V syntax is based on the syntax in Mitsubishi's D10V
-architecture manual.  The differences are detailed below.
-
-* Menu:
-
-* D10V-Size::                 Size Modifiers
-* D10V-Subs::                 Sub-Instructions
-* D10V-Chars::                Special Characters
-* D10V-Regs::                 Register Names
-* D10V-Addressing::           Addressing Modes
-* D10V-Word::                 @WORD Modifier
-
-
-File: as.info,  Node: D10V-Size,  Next: D10V-Subs,  Up: D10V-Syntax
-
-8.6.2.1 Size Modifiers
-......................
-
-The D10V version of `as' uses the instruction names in the D10V
-Architecture Manual.  However, the names in the manual are sometimes
-ambiguous.  There are instruction names that can assemble to a short or
-long form opcode.  How does the assembler pick the correct form?  `as'
-will always pick the smallest form if it can.  When dealing with a
-symbol that is not defined yet when a line is being assembled, it will
-always use the long form.  If you need to force the assembler to use
-either the short or long form of the instruction, you can append either
-`.s' (short) or `.l' (long) to it.  For example, if you are writing an
-assembly program and you want to do a branch to a symbol that is
-defined later in your program, you can write `bra.s   foo'.  Objdump
-and GDB will always append `.s' or `.l' to instructions which have both
-short and long forms.
-
-
-File: as.info,  Node: D10V-Subs,  Next: D10V-Chars,  Prev: D10V-Size,  Up: D10V-Syntax
-
-8.6.2.2 Sub-Instructions
-........................
-
-The D10V assembler takes as input a series of instructions, either
-one-per-line, or in the special two-per-line format described in the
-next section.  Some of these instructions will be short-form or
-sub-instructions.  These sub-instructions can be packed into a single
-instruction.  The assembler will do this automatically.  It will also
-detect when it should not pack instructions.  For example, when a label
-is defined, the next instruction will never be packaged with the
-previous one.  Whenever a branch and link instruction is called, it
-will not be packaged with the next instruction so the return address
-will be valid.  Nops are automatically inserted when necessary.
-
-   If you do not want the assembler automatically making these
-decisions, you can control the packaging and execution type (parallel
-or sequential) with the special execution symbols described in the next
-section.
-
-
-File: as.info,  Node: D10V-Chars,  Next: D10V-Regs,  Prev: D10V-Subs,  Up: D10V-Syntax
-
-8.6.2.3 Special Characters
-..........................
-
-`;' and `#' are the line comment characters.  Sub-instructions may be
-executed in order, in reverse-order, or in parallel.  Instructions
-listed in the standard one-per-line format will be executed
-sequentially.  To specify the executing order, use the following
-symbols:
-`->'
-     Sequential with instruction on the left first.
-
-`<-'
-     Sequential with instruction on the right first.
-
-`||'
-     Parallel
-   The D10V syntax allows either one instruction per line, one
-instruction per line with the execution symbol, or two instructions per
-line.  For example
-`abs       a1      ->      abs     r0'
-     Execute these sequentially.  The instruction on the right is in
-     the right container and is executed second.
-
-`abs       r0      <-      abs     a1'
-     Execute these reverse-sequentially.  The instruction on the right
-     is in the right container, and is executed first.
-
-`ld2w    r2,@r8+         ||      mac     a0,r0,r7'
-     Execute these in parallel.
-
-`ld2w    r2,@r8+         ||'
-`mac     a0,r0,r7'
-     Two-line format. Execute these in parallel.
-
-`ld2w    r2,@r8+'
-`mac     a0,r0,r7'
-     Two-line format. Execute these sequentially.  Assembler will put
-     them in the proper containers.
-
-`ld2w    r2,@r8+         ->'
-`mac     a0,r0,r7'
-     Two-line format. Execute these sequentially.  Same as above but
-     second instruction will always go into right container.
-   Since `$' has no special meaning, you may use it in symbol names.
-
-
-File: as.info,  Node: D10V-Regs,  Next: D10V-Addressing,  Prev: D10V-Chars,  Up: D10V-Syntax
-
-8.6.2.4 Register Names
-......................
-
-You can use the predefined symbols `r0' through `r15' to refer to the
-D10V registers.  You can also use `sp' as an alias for `r15'.  The
-accumulators are `a0' and `a1'.  There are special register-pair names
-that may optionally be used in opcodes that require even-numbered
-registers. Register names are not case sensitive.
-
-   Register Pairs
-`r0-r1'
-
-`r2-r3'
-
-`r4-r5'
-
-`r6-r7'
-
-`r8-r9'
-
-`r10-r11'
-
-`r12-r13'
-
-`r14-r15'
-
-   The D10V also has predefined symbols for these control registers and
-status bits:
-`psw'
-     Processor Status Word
-
-`bpsw'
-     Backup Processor Status Word
-
-`pc'
-     Program Counter
-
-`bpc'
-     Backup Program Counter
-
-`rpt_c'
-     Repeat Count
-
-`rpt_s'
-     Repeat Start address
-
-`rpt_e'
-     Repeat End address
-
-`mod_s'
-     Modulo Start address
-
-`mod_e'
-     Modulo End address
-
-`iba'
-     Instruction Break Address
-
-`f0'
-     Flag 0
-
-`f1'
-     Flag 1
-
-`c'
-     Carry flag
-
-
-File: as.info,  Node: D10V-Addressing,  Next: D10V-Word,  Prev: D10V-Regs,  Up: D10V-Syntax
-
-8.6.2.5 Addressing Modes
-........................
-
-`as' understands the following addressing modes for the D10V.  `RN' in
-the following refers to any of the numbered registers, but _not_ the
-control registers.
-`RN'
-     Register direct
-
-`@RN'
-     Register indirect
-
-`@RN+'
-     Register indirect with post-increment
-
-`@RN-'
-     Register indirect with post-decrement
-
-`@-SP'
-     Register indirect with pre-decrement
-
-`@(DISP, RN)'
-     Register indirect with displacement
-
-`ADDR'
-     PC relative address (for branch or rep).
-
-`#IMM'
-     Immediate data (the `#' is optional and ignored)
-
-
-File: as.info,  Node: D10V-Word,  Prev: D10V-Addressing,  Up: D10V-Syntax
-
-8.6.2.6 @WORD Modifier
-......................
-
-Any symbol followed by `@word' will be replaced by the symbol's value
-shifted right by 2.  This is used in situations such as loading a
-register with the address of a function (or any other code fragment).
-For example, if you want to load a register with the location of the
-function `main' then jump to that function, you could do it as follows:
-     ldi     r2, main@word
-     jmp     r2
-
-
-File: as.info,  Node: D10V-Float,  Next: D10V-Opcodes,  Prev: D10V-Syntax,  Up: D10V-Dependent
-
-8.6.3 Floating Point
---------------------
-
-The D10V has no hardware floating point, but the `.float' and `.double'
-directives generates IEEE floating-point numbers for compatibility with
-other development tools.
-
-
-File: as.info,  Node: D10V-Opcodes,  Prev: D10V-Float,  Up: D10V-Dependent
-
-8.6.4 Opcodes
--------------
-
-For detailed information on the D10V machine instruction set, see `D10V
-Architecture: A VLIW Microprocessor for Multimedia Applications'
-(Mitsubishi Electric Corp.).  `as' implements all the standard D10V
-opcodes.  The only changes are those described in the section on size
-modifiers
-
-
-File: as.info,  Node: D30V-Dependent,  Next: H8/300-Dependent,  Prev: D10V-Dependent,  Up: Machine Dependencies
-
-8.7 D30V Dependent Features
-===========================
-
-* Menu:
-
-* D30V-Opts::                   D30V Options
-* D30V-Syntax::                 Syntax
-* D30V-Float::                  Floating Point
-* D30V-Opcodes::                Opcodes
-
-
-File: as.info,  Node: D30V-Opts,  Next: D30V-Syntax,  Up: D30V-Dependent
-
-8.7.1 D30V Options
-------------------
-
-The Mitsubishi D30V version of `as' has a few machine dependent options.
-
-`-O'
-     The D30V can often execute two sub-instructions in parallel. When
-     this option is used, `as' will attempt to optimize its output by
-     detecting when instructions can be executed in parallel.
-
-`-n'
-     When this option is used, `as' will issue a warning every time it
-     adds a nop instruction.
-
-`-N'
-     When this option is used, `as' will issue a warning if it needs to
-     insert a nop after a 32-bit multiply before a load or 16-bit
-     multiply instruction.
-
-
-File: as.info,  Node: D30V-Syntax,  Next: D30V-Float,  Prev: D30V-Opts,  Up: D30V-Dependent
-
-8.7.2 Syntax
-------------
-
-The D30V syntax is based on the syntax in Mitsubishi's D30V
-architecture manual.  The differences are detailed below.
-
-* Menu:
-
-* D30V-Size::                 Size Modifiers
-* D30V-Subs::                 Sub-Instructions
-* D30V-Chars::                Special Characters
-* D30V-Guarded::              Guarded Execution
-* D30V-Regs::                 Register Names
-* D30V-Addressing::           Addressing Modes
-
-
-File: as.info,  Node: D30V-Size,  Next: D30V-Subs,  Up: D30V-Syntax
-
-8.7.2.1 Size Modifiers
-......................
-
-The D30V version of `as' uses the instruction names in the D30V
-Architecture Manual.  However, the names in the manual are sometimes
-ambiguous.  There are instruction names that can assemble to a short or
-long form opcode.  How does the assembler pick the correct form?  `as'
-will always pick the smallest form if it can.  When dealing with a
-symbol that is not defined yet when a line is being assembled, it will
-always use the long form.  If you need to force the assembler to use
-either the short or long form of the instruction, you can append either
-`.s' (short) or `.l' (long) to it.  For example, if you are writing an
-assembly program and you want to do a branch to a symbol that is
-defined later in your program, you can write `bra.s foo'.  Objdump and
-GDB will always append `.s' or `.l' to instructions which have both
-short and long forms.
-
-
-File: as.info,  Node: D30V-Subs,  Next: D30V-Chars,  Prev: D30V-Size,  Up: D30V-Syntax
-
-8.7.2.2 Sub-Instructions
-........................
-
-The D30V assembler takes as input a series of instructions, either
-one-per-line, or in the special two-per-line format described in the
-next section.  Some of these instructions will be short-form or
-sub-instructions.  These sub-instructions can be packed into a single
-instruction.  The assembler will do this automatically.  It will also
-detect when it should not pack instructions.  For example, when a label
-is defined, the next instruction will never be packaged with the
-previous one.  Whenever a branch and link instruction is called, it
-will not be packaged with the next instruction so the return address
-will be valid.  Nops are automatically inserted when necessary.
-
-   If you do not want the assembler automatically making these
-decisions, you can control the packaging and execution type (parallel
-or sequential) with the special execution symbols described in the next
-section.
-
-
-File: as.info,  Node: D30V-Chars,  Next: D30V-Guarded,  Prev: D30V-Subs,  Up: D30V-Syntax
-
-8.7.2.3 Special Characters
-..........................
-
-`;' and `#' are the line comment characters.  Sub-instructions may be
-executed in order, in reverse-order, or in parallel.  Instructions
-listed in the standard one-per-line format will be executed
-sequentially unless you use the `-O' option.
-
-   To specify the executing order, use the following symbols:
-`->'
-     Sequential with instruction on the left first.
-
-`<-'
-     Sequential with instruction on the right first.
-
-`||'
-     Parallel
-
-   The D30V syntax allows either one instruction per line, one
-instruction per line with the execution symbol, or two instructions per
-line.  For example
-`abs r2,r3 -> abs r4,r5'
-     Execute these sequentially.  The instruction on the right is in
-     the right container and is executed second.
-
-`abs r2,r3 <- abs r4,r5'
-     Execute these reverse-sequentially.  The instruction on the right
-     is in the right container, and is executed first.
-
-`abs r2,r3 || abs r4,r5'
-     Execute these in parallel.
-
-`ldw r2,@(r3,r4) ||'
-`mulx r6,r8,r9'
-     Two-line format. Execute these in parallel.
-
-`mulx a0,r8,r9'
-`stw r2,@(r3,r4)'
-     Two-line format. Execute these sequentially unless `-O' option is
-     used.  If the `-O' option is used, the assembler will determine if
-     the instructions could be done in parallel (the above two
-     instructions can be done in parallel), and if so, emit them as
-     parallel instructions.  The assembler will put them in the proper
-     containers.  In the above example, the assembler will put the
-     `stw' instruction in left container and the `mulx' instruction in
-     the right container.
-
-`stw r2,@(r3,r4) ->'
-`mulx a0,r8,r9'
-     Two-line format.  Execute the `stw' instruction followed by the
-     `mulx' instruction sequentially.  The first instruction goes in the
-     left container and the second instruction goes into right
-     container.  The assembler will give an error if the machine
-     ordering constraints are violated.
-
-`stw r2,@(r3,r4) <-'
-`mulx a0,r8,r9'
-     Same as previous example, except that the `mulx' instruction is
-     executed before the `stw' instruction.
-
-   Since `$' has no special meaning, you may use it in symbol names.
-
-
-File: as.info,  Node: D30V-Guarded,  Next: D30V-Regs,  Prev: D30V-Chars,  Up: D30V-Syntax
-
-8.7.2.4 Guarded Execution
-.........................
-
-`as' supports the full range of guarded execution directives for each
-instruction.  Just append the directive after the instruction proper.
-The directives are:
-
-`/tx'
-     Execute the instruction if flag f0 is true.
-
-`/fx'
-     Execute the instruction if flag f0 is false.
-
-`/xt'
-     Execute the instruction if flag f1 is true.
-
-`/xf'
-     Execute the instruction if flag f1 is false.
-
-`/tt'
-     Execute the instruction if both flags f0 and f1 are true.
-
-`/tf'
-     Execute the instruction if flag f0 is true and flag f1 is false.
-
-
-File: as.info,  Node: D30V-Regs,  Next: D30V-Addressing,  Prev: D30V-Guarded,  Up: D30V-Syntax
-
-8.7.2.5 Register Names
-......................
-
-You can use the predefined symbols `r0' through `r63' to refer to the
-D30V registers.  You can also use `sp' as an alias for `r63' and `link'
-as an alias for `r62'.  The accumulators are `a0' and `a1'.
-
-   The D30V also has predefined symbols for these control registers and
-status bits:
-`psw'
-     Processor Status Word
-
-`bpsw'
-     Backup Processor Status Word
-
-`pc'
-     Program Counter
-
-`bpc'
-     Backup Program Counter
-
-`rpt_c'
-     Repeat Count
-
-`rpt_s'
-     Repeat Start address
-
-`rpt_e'
-     Repeat End address
-
-`mod_s'
-     Modulo Start address
-
-`mod_e'
-     Modulo End address
-
-`iba'
-     Instruction Break Address
-
-`f0'
-     Flag 0
-
-`f1'
-     Flag 1
-
-`f2'
-     Flag 2
-
-`f3'
-     Flag 3
-
-`f4'
-     Flag 4
-
-`f5'
-     Flag 5
-
-`f6'
-     Flag 6
-
-`f7'
-     Flag 7
-
-`s'
-     Same as flag 4 (saturation flag)
-
-`v'
-     Same as flag 5 (overflow flag)
-
-`va'
-     Same as flag 6 (sticky overflow flag)
-
-`c'
-     Same as flag 7 (carry/borrow flag)
-
-`b'
-     Same as flag 7 (carry/borrow flag)
-
-
-File: as.info,  Node: D30V-Addressing,  Prev: D30V-Regs,  Up: D30V-Syntax
-
-8.7.2.6 Addressing Modes
-........................
-
-`as' understands the following addressing modes for the D30V.  `RN' in
-the following refers to any of the numbered registers, but _not_ the
-control registers.
-`RN'
-     Register direct
-
-`@RN'
-     Register indirect
-
-`@RN+'
-     Register indirect with post-increment
-
-`@RN-'
-     Register indirect with post-decrement
-
-`@-SP'
-     Register indirect with pre-decrement
-
-`@(DISP, RN)'
-     Register indirect with displacement
-
-`ADDR'
-     PC relative address (for branch or rep).
-
-`#IMM'
-     Immediate data (the `#' is optional and ignored)
-
-
-File: as.info,  Node: D30V-Float,  Next: D30V-Opcodes,  Prev: D30V-Syntax,  Up: D30V-Dependent
-
-8.7.3 Floating Point
---------------------
-
-The D30V has no hardware floating point, but the `.float' and `.double'
-directives generates IEEE floating-point numbers for compatibility with
-other development tools.
-
-
-File: as.info,  Node: D30V-Opcodes,  Prev: D30V-Float,  Up: D30V-Dependent
-
-8.7.4 Opcodes
--------------
-
-For detailed information on the D30V machine instruction set, see `D30V
-Architecture: A VLIW Microprocessor for Multimedia Applications'
-(Mitsubishi Electric Corp.).  `as' implements all the standard D30V
-opcodes.  The only changes are those described in the section on size
-modifiers
-
-
-File: as.info,  Node: H8/300-Dependent,  Next: HPPA-Dependent,  Prev: D30V-Dependent,  Up: Machine Dependencies
-
-8.8 H8/300 Dependent Features
-=============================
-
-* Menu:
-
-* H8/300 Options::              Options
-* H8/300 Syntax::               Syntax
-* H8/300 Floating Point::       Floating Point
-* H8/300 Directives::           H8/300 Machine Directives
-* H8/300 Opcodes::              Opcodes
-
-
-File: as.info,  Node: H8/300 Options,  Next: H8/300 Syntax,  Up: H8/300-Dependent
-
-8.8.1 Options
--------------
-
-`as' has no additional command-line options for the Renesas (formerly
-Hitachi) H8/300 family.
-
-
-File: as.info,  Node: H8/300 Syntax,  Next: H8/300 Floating Point,  Prev: H8/300 Options,  Up: H8/300-Dependent
-
-8.8.2 Syntax
-------------
-
-* Menu:
-
-* H8/300-Chars::                Special Characters
-* H8/300-Regs::                 Register Names
-* H8/300-Addressing::           Addressing Modes
-
-
-File: as.info,  Node: H8/300-Chars,  Next: H8/300-Regs,  Up: H8/300 Syntax
-
-8.8.2.1 Special Characters
-..........................
-
-`;' is the line comment character.
-
-   `$' can be used instead of a newline to separate statements.
-Therefore _you may not use `$' in symbol names_ on the H8/300.
-
-
-File: as.info,  Node: H8/300-Regs,  Next: H8/300-Addressing,  Prev: H8/300-Chars,  Up: H8/300 Syntax
-
-8.8.2.2 Register Names
-......................
-
-You can use predefined symbols of the form `rNh' and `rNl' to refer to
-the H8/300 registers as sixteen 8-bit general-purpose registers.  N is
-a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid
-register names.
-
-   You can also use the eight predefined symbols `rN' to refer to the
-H8/300 registers as 16-bit registers (you must use this form for
-addressing).
-
-   On the H8/300H, you can also use the eight predefined symbols `erN'
-(`er0' ... `er7') to refer to the 32-bit general purpose registers.
-
-   The two control registers are called `pc' (program counter; a 16-bit
-register, except on the H8/300H where it is 24 bits) and `ccr'
-(condition code register; an 8-bit register).  `r7' is used as the
-stack pointer, and can also be called `sp'.
-
-
-File: as.info,  Node: H8/300-Addressing,  Prev: H8/300-Regs,  Up: H8/300 Syntax
-
-8.8.2.3 Addressing Modes
-........................
-
-as understands the following addressing modes for the H8/300:
-`rN'
-     Register direct
-
-`@rN'
-     Register indirect
-
-`@(D, rN)'
-`@(D:16, rN)'
-`@(D:24, rN)'
-     Register indirect: 16-bit or 24-bit displacement D from register
-     N.  (24-bit displacements are only meaningful on the H8/300H.)
-
-`@rN+'
-     Register indirect with post-increment
-
-`@-rN'
-     Register indirect with pre-decrement
-
-``@'AA'
-``@'AA:8'
-``@'AA:16'
-``@'AA:24'
-     Absolute address `aa'.  (The address size `:24' only makes sense
-     on the H8/300H.)
-
-`#XX'
-`#XX:8'
-`#XX:16'
-`#XX:32'
-     Immediate data XX.  You may specify the `:8', `:16', or `:32' for
-     clarity, if you wish; but `as' neither requires this nor uses
-     it--the data size required is taken from context.
-
-``@'`@'AA'
-``@'`@'AA:8'
-     Memory indirect.  You may specify the `:8' for clarity, if you
-     wish; but `as' neither requires this nor uses it.
-
-
-File: as.info,  Node: H8/300 Floating Point,  Next: H8/300 Directives,  Prev: H8/300 Syntax,  Up: H8/300-Dependent
-
-8.8.3 Floating Point
---------------------
-
-The H8/300 family has no hardware floating point, but the `.float'
-directive generates IEEE floating-point numbers for compatibility with
-other development tools.
-
-
-File: as.info,  Node: H8/300 Directives,  Next: H8/300 Opcodes,  Prev: H8/300 Floating Point,  Up: H8/300-Dependent
-
-8.8.4 H8/300 Machine Directives
--------------------------------
-
-`as' has the following machine-dependent directives for the H8/300:
-
-`.h8300h'
-     Recognize and emit additional instructions for the H8/300H
-     variant, and also make `.int' emit 32-bit numbers rather than the
-     usual (16-bit) for the H8/300 family.
-
-`.h8300s'
-     Recognize and emit additional instructions for the H8S variant, and
-     also make `.int' emit 32-bit numbers rather than the usual (16-bit)
-     for the H8/300 family.
-
-`.h8300hn'
-     Recognize and emit additional instructions for the H8/300H variant
-     in normal mode, and also make `.int' emit 32-bit numbers rather
-     than the usual (16-bit) for the H8/300 family.
-
-`.h8300sn'
-     Recognize and emit additional instructions for the H8S variant in
-     normal mode, and also make `.int' emit 32-bit numbers rather than
-     the usual (16-bit) for the H8/300 family.
-
-   On the H8/300 family (including the H8/300H) `.word' directives
-generate 16-bit numbers.
-
-
-File: as.info,  Node: H8/300 Opcodes,  Prev: H8/300 Directives,  Up: H8/300-Dependent
-
-8.8.5 Opcodes
--------------
-
-For detailed information on the H8/300 machine instruction set, see
-`H8/300 Series Programming Manual'.  For information specific to the
-H8/300H, see `H8/300H Series Programming Manual' (Renesas).
-
-   `as' implements all the standard H8/300 opcodes.  No additional
-pseudo-instructions are needed on this family.
-
-   The following table summarizes the H8/300 opcodes, and their
-arguments.  Entries marked `*' are opcodes used only on the H8/300H.
-
-              Legend:
-                 Rs   source register
-                 Rd   destination register
-                 abs  absolute address
-                 imm  immediate data
-              disp:N  N-bit displacement from a register
-             pcrel:N  N-bit displacement relative to program counter
-
-        add.b #imm,rd              *  andc #imm,ccr
-        add.b rs,rd                   band #imm,rd
-        add.w rs,rd                   band #imm,@rd
-     *  add.w #imm,rd                 band #imm,@abs:8
-     *  add.l rs,rd                   bra  pcrel:8
-     *  add.l #imm,rd              *  bra  pcrel:16
-        adds #imm,rd                  bt   pcrel:8
-        addx #imm,rd               *  bt   pcrel:16
-        addx rs,rd                    brn  pcrel:8
-        and.b #imm,rd              *  brn  pcrel:16
-        and.b rs,rd                   bf   pcrel:8
-     *  and.w rs,rd                *  bf   pcrel:16
-     *  and.w #imm,rd                 bhi  pcrel:8
-     *  and.l #imm,rd              *  bhi  pcrel:16
-     *  and.l rs,rd                   bls  pcrel:8
-
-     *  bls  pcrel:16                 bld  #imm,rd
-        bcc  pcrel:8                  bld  #imm,@rd
-     *  bcc  pcrel:16                 bld  #imm,@abs:8
-        bhs  pcrel:8                  bnot #imm,rd
-     *  bhs  pcrel:16                 bnot #imm,@rd
-        bcs  pcrel:8                  bnot #imm,@abs:8
-     *  bcs  pcrel:16                 bnot rs,rd
-        blo  pcrel:8                  bnot rs,@rd
-     *  blo  pcrel:16                 bnot rs,@abs:8
-        bne  pcrel:8                  bor  #imm,rd
-     *  bne  pcrel:16                 bor  #imm,@rd
-        beq  pcrel:8                  bor  #imm,@abs:8
-     *  beq  pcrel:16                 bset #imm,rd
-        bvc  pcrel:8                  bset #imm,@rd
-     *  bvc  pcrel:16                 bset #imm,@abs:8
-        bvs  pcrel:8                  bset rs,rd
-     *  bvs  pcrel:16                 bset rs,@rd
-        bpl  pcrel:8                  bset rs,@abs:8
-     *  bpl  pcrel:16                 bsr  pcrel:8
-        bmi  pcrel:8                  bsr  pcrel:16
-     *  bmi  pcrel:16                 bst  #imm,rd
-        bge  pcrel:8                  bst  #imm,@rd
-     *  bge  pcrel:16                 bst  #imm,@abs:8
-        blt  pcrel:8                  btst #imm,rd
-     *  blt  pcrel:16                 btst #imm,@rd
-        bgt  pcrel:8                  btst #imm,@abs:8
-     *  bgt  pcrel:16                 btst rs,rd
-        ble  pcrel:8                  btst rs,@rd
-     *  ble  pcrel:16                 btst rs,@abs:8
-        bclr #imm,rd                  bxor #imm,rd
-        bclr #imm,@rd                 bxor #imm,@rd
-        bclr #imm,@abs:8              bxor #imm,@abs:8
-        bclr rs,rd                    cmp.b #imm,rd
-        bclr rs,@rd                   cmp.b rs,rd
-        bclr rs,@abs:8                cmp.w rs,rd
-        biand #imm,rd                 cmp.w rs,rd
-        biand #imm,@rd             *  cmp.w #imm,rd
-        biand #imm,@abs:8          *  cmp.l #imm,rd
-        bild #imm,rd               *  cmp.l rs,rd
-        bild #imm,@rd                 daa  rs
-        bild #imm,@abs:8              das  rs
-        bior #imm,rd                  dec.b rs
-        bior #imm,@rd              *  dec.w #imm,rd
-        bior #imm,@abs:8           *  dec.l #imm,rd
-        bist #imm,rd                  divxu.b rs,rd
-        bist #imm,@rd              *  divxu.w rs,rd
-        bist #imm,@abs:8           *  divxs.b rs,rd
-        bixor #imm,rd              *  divxs.w rs,rd
-        bixor #imm,@rd                eepmov
-        bixor #imm,@abs:8          *  eepmovw
-
-     *  exts.w rd                     mov.w rs,@abs:16
-     *  exts.l rd                  *  mov.l #imm,rd
-     *  extu.w rd                  *  mov.l rs,rd
-     *  extu.l rd                  *  mov.l @rs,rd
-        inc  rs                    *  mov.l @(disp:16,rs),rd
-     *  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
-     *  inc.l #imm,rd              *  mov.l @rs+,rd
-        jmp  @rs                   *  mov.l @abs:16,rd
-        jmp  abs                   *  mov.l @abs:24,rd
-        jmp  @@abs:8               *  mov.l rs,@rd
-        jsr  @rs                   *  mov.l rs,@(disp:16,rd)
-        jsr  abs                   *  mov.l rs,@(disp:24,rd)
-        jsr  @@abs:8               *  mov.l rs,@-rd
-        ldc  #imm,ccr              *  mov.l rs,@abs:16
-        ldc  rs,ccr                *  mov.l rs,@abs:24
-     *  ldc  @abs:16,ccr              movfpe @abs:16,rd
-     *  ldc  @abs:24,ccr              movtpe rs,@abs:16
-     *  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
-     *  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
-     *  ldc  @rs+,ccr              *  mulxs.b rs,rd
-     *  ldc  @rs,ccr               *  mulxs.w rs,rd
-     *  mov.b @(disp:24,rs),rd        neg.b rs
-     *  mov.b rs,@(disp:24,rd)     *  neg.w rs
-        mov.b @abs:16,rd           *  neg.l rs
-        mov.b rs,rd                   nop
-        mov.b @abs:8,rd               not.b rs
-        mov.b rs,@abs:8            *  not.w rs
-        mov.b rs,rd                *  not.l rs
-        mov.b #imm,rd                 or.b #imm,rd
-        mov.b @rs,rd                  or.b rs,rd
-        mov.b @(disp:16,rs),rd     *  or.w #imm,rd
-        mov.b @rs+,rd              *  or.w rs,rd
-        mov.b @abs:8,rd            *  or.l #imm,rd
-        mov.b rs,@rd               *  or.l rs,rd
-        mov.b rs,@(disp:16,rd)        orc  #imm,ccr
-        mov.b rs,@-rd                 pop.w rs
-        mov.b rs,@abs:8            *  pop.l rs
-        mov.w rs,@rd                  push.w rs
-     *  mov.w @(disp:24,rs),rd     *  push.l rs
-     *  mov.w rs,@(disp:24,rd)        rotl.b rs
-     *  mov.w @abs:24,rd           *  rotl.w rs
-     *  mov.w rs,@abs:24           *  rotl.l rs
-        mov.w rs,rd                   rotr.b rs
-        mov.w #imm,rd              *  rotr.w rs
-        mov.w @rs,rd               *  rotr.l rs
-        mov.w @(disp:16,rs),rd        rotxl.b rs
-        mov.w @rs+,rd              *  rotxl.w rs
-        mov.w @abs:16,rd           *  rotxl.l rs
-        mov.w rs,@(disp:16,rd)        rotxr.b rs
-        mov.w rs,@-rd              *  rotxr.w rs
-
-     *  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
-        bpt                        *  stc  ccr,@-rd
-        rte                        *  stc  ccr,@abs:16
-        rts                        *  stc  ccr,@abs:24
-        shal.b rs                     sub.b rs,rd
-     *  shal.w rs                     sub.w rs,rd
-     *  shal.l rs                  *  sub.w #imm,rd
-        shar.b rs                  *  sub.l rs,rd
-     *  shar.w rs                  *  sub.l #imm,rd
-     *  shar.l rs                     subs #imm,rd
-        shll.b rs                     subx #imm,rd
-     *  shll.w rs                     subx rs,rd
-     *  shll.l rs                  *  trapa #imm
-        shlr.b rs                     xor  #imm,rd
-     *  shlr.w rs                     xor  rs,rd
-     *  shlr.l rs                  *  xor.w #imm,rd
-        sleep                      *  xor.w rs,rd
-        stc  ccr,rd                *  xor.l #imm,rd
-     *  stc  ccr,@rs               *  xor.l rs,rd
-     *  stc  ccr,@(disp:16,rd)        xorc #imm,ccr
-
-   Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
-with variants using the suffixes `.b', `.w', and `.l' to specify the
-size of a memory operand.  `as' supports these suffixes, but does not
-require them; since one of the operands is always a register, `as' can
-deduce the correct size.
-
-   For example, since `r0' refers to a 16-bit register,
-     mov    r0,@foo
-is equivalent to
-     mov.w  r0,@foo
-
-   If you use the size suffixes, `as' issues a warning when the suffix
-and the register size do not match.
-
-
-File: as.info,  Node: HPPA-Dependent,  Next: ESA/390-Dependent,  Prev: H8/300-Dependent,  Up: Machine Dependencies
-
-8.9 HPPA Dependent Features
-===========================
-
-* Menu:
-
-* HPPA Notes::                Notes
-* HPPA Options::              Options
-* HPPA Syntax::               Syntax
-* HPPA Floating Point::       Floating Point
-* HPPA Directives::           HPPA Machine Directives
-* HPPA Opcodes::              Opcodes
-
-
-File: as.info,  Node: HPPA Notes,  Next: HPPA Options,  Up: HPPA-Dependent
-
-8.9.1 Notes
------------
-
-As a back end for GNU CC `as' has been throughly tested and should work
-extremely well.  We have tested it only minimally on hand written
-assembly code and no one has tested it much on the assembly output from
-the HP compilers.
-
-   The format of the debugging sections has changed since the original
-`as' port (version 1.3X) was released; therefore, you must rebuild all
-HPPA objects and libraries with the new assembler so that you can debug
-the final executable.
-
-   The HPPA `as' port generates a small subset of the relocations
-available in the SOM and ELF object file formats.  Additional relocation
-support will be added as it becomes necessary.
-
-
-File: as.info,  Node: HPPA Options,  Next: HPPA Syntax,  Prev: HPPA Notes,  Up: HPPA-Dependent
-
-8.9.2 Options
--------------
-
-`as' has no machine-dependent command-line options for the HPPA.
-
-
-File: as.info,  Node: HPPA Syntax,  Next: HPPA Floating Point,  Prev: HPPA Options,  Up: HPPA-Dependent
-
-8.9.3 Syntax
-------------
-
-The assembler syntax closely follows the HPPA instruction set reference
-manual; assembler directives and general syntax closely follow the HPPA
-assembly language reference manual, with a few noteworthy differences.
-
-   First, a colon may immediately follow a label definition.  This is
-simply for compatibility with how most assembly language programmers
-write code.
-
-   Some obscure expression parsing problems may affect hand written
-code which uses the `spop' instructions, or code which makes significant
-use of the `!' line separator.
-
-   `as' is much less forgiving about missing arguments and other
-similar oversights than the HP assembler.  `as' notifies you of missing
-arguments as syntax errors; this is regarded as a feature, not a bug.
-
-   Finally, `as' allows you to use an external symbol without
-explicitly importing the symbol.  _Warning:_ in the future this will be
-an error for HPPA targets.
-
-   Special characters for HPPA targets include:
-
-   `;' is the line comment character.
-
-   `!' can be used instead of a newline to separate statements.
-
-   Since `$' has no special meaning, you may use it in symbol names.
-
-
-File: as.info,  Node: HPPA Floating Point,  Next: HPPA Directives,  Prev: HPPA Syntax,  Up: HPPA-Dependent
-
-8.9.4 Floating Point
---------------------
-
-The HPPA family uses IEEE floating-point numbers.
-
-
-File: as.info,  Node: HPPA Directives,  Next: HPPA Opcodes,  Prev: HPPA Floating Point,  Up: HPPA-Dependent
-
-8.9.5 HPPA Assembler Directives
--------------------------------
-
-`as' for the HPPA supports many additional directives for compatibility
-with the native assembler.  This section describes them only briefly.
-For detailed information on HPPA-specific assembler directives, see
-`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
-
-   `as' does _not_ support the following assembler directives described
-in the HP manual:
-
-     .endm           .liston
-     .enter          .locct
-     .leave          .macro
-     .listoff
-
-   Beyond those implemented for compatibility, `as' supports one
-additional assembler directive for the HPPA: `.param'.  It conveys
-register argument locations for static functions.  Its syntax closely
-follows the `.export' directive.
-
-   These are the additional directives in `as' for the HPPA:
-
-`.block N'
-`.blockz N'
-     Reserve N bytes of storage, and initialize them to zero.
-
-`.call'
-     Mark the beginning of a procedure call.  Only the special case
-     with _no arguments_ is allowed.
-
-`.callinfo [ PARAM=VALUE, ... ]  [ FLAG, ... ]'
-     Specify a number of parameters and flags that define the
-     environment for a procedure.
-
-     PARAM may be any of `frame' (frame size), `entry_gr' (end of
-     general register range), `entry_fr' (end of float register range),
-     `entry_sr' (end of space register range).
-
-     The values for FLAG are `calls' or `caller' (proc has
-     subroutines), `no_calls' (proc does not call subroutines),
-     `save_rp' (preserve return pointer), `save_sp' (proc preserves
-     stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
-     (proc is interrupt routine).
-
-`.code'
-     Assemble into the standard section called `$TEXT$', subsection
-     `$CODE$'.
-
-`.copyright "STRING"'
-     In the SOM object format, insert STRING into the object code,
-     marked as a copyright string.
-
-`.copyright "STRING"'
-     In the ELF object format, insert STRING into the object code,
-     marked as a version string.
-
-`.enter'
-     Not yet supported; the assembler rejects programs containing this
-     directive.
-
-`.entry'
-     Mark the beginning of a procedure.
-
-`.exit'
-     Mark the end of a procedure.
-
-`.export NAME [ ,TYP ]  [ ,PARAM=R ]'
-     Make a procedure NAME available to callers.  TYP, if present, must
-     be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
-     `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
-
-     PARAM, if present, provides either relocation information for the
-     procedure arguments and result, or a privilege level.  PARAM may be
-     `argwN' (where N ranges from `0' to `3', and indicates one of four
-     one-word arguments); `rtnval' (the procedure's result); or
-     `priv_lev' (privilege level).  For arguments or the result, R
-     specifies how to relocate, and must be one of `no' (not
-     relocatable), `gr' (argument is in general register), `fr' (in
-     floating point register), or `fu' (upper half of float register).
-     For `priv_lev', R is an integer.
-
-`.half N'
-     Define a two-byte integer constant N; synonym for the portable
-     `as' directive `.short'.
-
-`.import NAME [ ,TYP ]'
-     Converse of `.export'; make a procedure available to call.  The
-     arguments use the same conventions as the first two arguments for
-     `.export'.
-
-`.label NAME'
-     Define NAME as a label for the current assembly location.
-
-`.leave'
-     Not yet supported; the assembler rejects programs containing this
-     directive.
-
-`.origin LC'
-     Advance location counter to LC. Synonym for the `as' portable
-     directive `.org'.
-
-`.param NAME [ ,TYP ]  [ ,PARAM=R ]'
-     Similar to `.export', but used for static procedures.
-
-`.proc'
-     Use preceding the first statement of a procedure.
-
-`.procend'
-     Use following the last statement of a procedure.
-
-`LABEL .reg EXPR'
-     Synonym for `.equ'; define LABEL with the absolute expression EXPR
-     as its value.
-
-`.space SECNAME [ ,PARAMS ]'
-     Switch to section SECNAME, creating a new section by that name if
-     necessary.  You may only use PARAMS when creating a new section,
-     not when switching to an existing one.  SECNAME may identify a
-     section by number rather than by name.
-
-     If specified, the list PARAMS declares attributes of the section,
-     identified by keywords.  The keywords recognized are `spnum=EXP'
-     (identify this section by the number EXP, an absolute expression),
-     `sort=EXP' (order sections according to this sort key when linking;
-     EXP is an absolute expression), `unloadable' (section contains no
-     loadable data), `notdefined' (this section defined elsewhere), and
-     `private' (data in this section not available to other programs).
-
-`.spnum SECNAM'
-     Allocate four bytes of storage, and initialize them with the
-     section number of the section named SECNAM.  (You can define the
-     section number with the HPPA `.space' directive.)
-
-`.string "STR"'
-     Copy the characters in the string STR to the object file.  *Note
-     Strings: Strings, for information on escape sequences you can use
-     in `as' strings.
-
-     _Warning!_ The HPPA version of `.string' differs from the usual
-     `as' definition: it does _not_ write a zero byte after copying STR.
-
-`.stringz "STR"'
-     Like `.string', but appends a zero byte after copying STR to object
-     file.
-
-`.subspa NAME [ ,PARAMS ]'
-`.nsubspa NAME [ ,PARAMS ]'
-     Similar to `.space', but selects a subsection NAME within the
-     current section.  You may only specify PARAMS when you create a
-     subsection (in the first instance of `.subspa' for this NAME).
-
-     If specified, the list PARAMS declares attributes of the
-     subsection, identified by keywords.  The keywords recognized are
-     `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
-     (alignment for beginning of this subsection; a power of two),
-     `access=EXPR' (value for "access rights" field), `sort=EXPR'
-     (sorting order for this subspace in link), `code_only' (subsection
-     contains only code), `unloadable' (subsection cannot be loaded
-     into memory), `comdat' (subsection is comdat), `common'
-     (subsection is common block), `dup_comm' (subsection may have
-     duplicate names), or `zero' (subsection is all zeros, do not write
-     in object file).
-
-     `.nsubspa' always creates a new subspace with the given name, even
-     if one with the same name already exists.
-
-     `comdat', `common' and `dup_comm' can be used to implement various
-     flavors of one-only support when using the SOM linker.  The SOM
-     linker only supports specific combinations of these flags.  The
-     details are not documented.  A brief description is provided here.
-
-     `comdat' provides a form of linkonce support.  It is useful for
-     both code and data subspaces.  A `comdat' subspace has a key symbol
-     marked by the `is_comdat' flag or `ST_COMDAT'.  Only the first
-     subspace for any given key is selected.  The key symbol becomes
-     universal in shared links.  This is similar to the behavior of
-     `secondary_def' symbols.
-
-     `common' provides Fortran named common support.  It is only useful
-     for data subspaces.  Symbols with the flag `is_common' retain this
-     flag in shared links.  Referencing a `is_common' symbol in a shared
-     library from outside the library doesn't work.  Thus, `is_common'
-     symbols must be output whenever they are needed.
-
-     `common' and `dup_comm' together provide Cobol common support.
-     The subspaces in this case must all be the same length.
-     Otherwise, this support is similar to the Fortran common support.
-
-     `dup_comm' by itself provides a type of one-only support for code.
-     Only the first `dup_comm' subspace is selected.  There is a rather
-     complex algorithm to compare subspaces.  Code symbols marked with
-     the `dup_common' flag are hidden.  This support was intended for
-     "C++ duplicate inlines".
-
-     A simplified technique is used to mark the flags of symbols based
-     on the flags of their subspace.  A symbol with the scope
-     SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
-     the corresponding settings of `comdat', `common' and `dup_comm'
-     from the subspace, respectively.  This avoids having to introduce
-     additional directives to mark these symbols.  The HP assembler
-     sets `is_common' from `common'.  However, it doesn't set the
-     `dup_common' from `dup_comm'.  It doesn't have `comdat' support.
-
-`.version "STR"'
-     Write STR as version identifier in object code.
-
-
-File: as.info,  Node: HPPA Opcodes,  Prev: HPPA Directives,  Up: HPPA-Dependent
-
-8.9.6 Opcodes
--------------
-
-For detailed information on the HPPA machine instruction set, see
-`PA-RISC Architecture and Instruction Set Reference Manual' (HP
-09740-90039).
-
-
-File: as.info,  Node: ESA/390-Dependent,  Next: i386-Dependent,  Prev: HPPA-Dependent,  Up: Machine Dependencies
-
-8.10 ESA/390 Dependent Features
-===============================
-
-* Menu:
-
-* ESA/390 Notes::                Notes
-* ESA/390 Options::              Options
-* ESA/390 Syntax::               Syntax
-* ESA/390 Floating Point::       Floating Point
-* ESA/390 Directives::           ESA/390 Machine Directives
-* ESA/390 Opcodes::              Opcodes
-
-
-File: as.info,  Node: ESA/390 Notes,  Next: ESA/390 Options,  Up: ESA/390-Dependent
-
-8.10.1 Notes
-------------
-
-The ESA/390 `as' port is currently intended to be a back-end for the
-GNU CC compiler.  It is not HLASM compatible, although it does support
-a subset of some of the HLASM directives.  The only supported binary
-file format is ELF; none of the usual MVS/VM/OE/USS object file
-formats, such as ESD or XSD, are supported.
-
-   When used with the GNU CC compiler, the ESA/390 `as' will produce
-correct, fully relocated, functional binaries, and has been used to
-compile and execute large projects.  However, many aspects should still
-be considered experimental; these include shared library support,
-dynamically loadable objects, and any relocation other than the 31-bit
-relocation.
-
-
-File: as.info,  Node: ESA/390 Options,  Next: ESA/390 Syntax,  Prev: ESA/390 Notes,  Up: ESA/390-Dependent
-
-8.10.2 Options
---------------
-
-`as' has no machine-dependent command-line options for the ESA/390.
-
-
-File: as.info,  Node: ESA/390 Syntax,  Next: ESA/390 Floating Point,  Prev: ESA/390 Options,  Up: ESA/390-Dependent
-
-8.10.3 Syntax
--------------
-
-The opcode/operand syntax follows the ESA/390 Principles of Operation
-manual; assembler directives and general syntax are loosely based on the
-prevailing AT&T/SVR4/ELF/Solaris style notation.  HLASM-style directives
-are _not_ supported for the most part, with the exception of those
-described herein.
-
-   A leading dot in front of directives is optional, and the case of
-directives is ignored; thus for example, .using and USING have the same
-effect.
-
-   A colon may immediately follow a label definition.  This is simply
-for compatibility with how most assembly language programmers write
-code.
-
-   `#' is the line comment character.
-
-   `;' can be used instead of a newline to separate statements.
-
-   Since `$' has no special meaning, you may use it in symbol names.
-
-   Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
-fp6.  By using thesse symbolic names, `as' can detect simple syntax
-errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
-r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
-for r3 and rpgt or r.pgt for r4.
-
-   `*' is the current location counter.  Unlike `.' it is always
-relative to the last USING directive.  Note that this means that
-expressions cannot use multiplication, as any occurrence of `*' will be
-interpreted as a location counter.
-
-   All labels are relative to the last USING.  Thus, branches to a label
-always imply the use of base+displacement.
-
-   Many of the usual forms of address constants / address literals are
-supported.  Thus,
-     	.using	*,r3
-     	L	r15,=A(some_routine)
-     	LM	r6,r7,=V(some_longlong_extern)
-     	A	r1,=F'12'
-     	AH	r0,=H'42'
-     	ME	r6,=E'3.1416'
-     	MD	r6,=D'3.14159265358979'
-     	O	r6,=XL4'cacad0d0'
-     	.ltorg
-   should all behave as expected: that is, an entry in the literal pool
-will be created (or reused if it already exists), and the instruction
-operands will be the displacement into the literal pool using the
-current base register (as last declared with the `.using' directive).
-
-
-File: as.info,  Node: ESA/390 Floating Point,  Next: ESA/390 Directives,  Prev: ESA/390 Syntax,  Up: ESA/390-Dependent
-
-8.10.4 Floating Point
----------------------
-
-The assembler generates only IEEE floating-point numbers.  The older
-floating point formats are not supported.
-
-
-File: as.info,  Node: ESA/390 Directives,  Next: ESA/390 Opcodes,  Prev: ESA/390 Floating Point,  Up: ESA/390-Dependent
-
-8.10.5 ESA/390 Assembler Directives
------------------------------------
-
-`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
-directives that are documented in the main part of this documentation.
-Several additional directives are supported in order to implement the
-ESA/390 addressing model.  The most important of these are `.using' and
-`.ltorg'
-
-   These are the additional directives in `as' for the ESA/390:
-
-`.dc'
-     A small subset of the usual DC directive is supported.
-
-`.drop REGNO'
-     Stop using REGNO as the base register.  The REGNO must have been
-     previously declared with a `.using' directive in the same section
-     as the current section.
-
-`.ebcdic STRING'
-     Emit the EBCDIC equivalent of the indicated string.  The emitted
-     string will be null terminated.  Note that the directives
-     `.string' etc. emit ascii strings by default.
-
-`EQU'
-     The standard HLASM-style EQU directive is not supported; however,
-     the standard `as' directive .equ can be used to the same effect.
-
-`.ltorg'
-     Dump the literal pool accumulated so far; begin a new literal pool.
-     The literal pool will be written in the current section; in order
-     to generate correct assembly, a `.using' must have been previously
-     specified in the same section.
-
-`.using EXPR,REGNO'
-     Use REGNO as the base register for all subsequent RX, RS, and SS
-     form instructions. The EXPR will be evaluated to obtain the base
-     address; usually, EXPR will merely be `*'.
-
-     This assembler allows two `.using' directives to be simultaneously
-     outstanding, one in the `.text' section, and one in another section
-     (typically, the `.data' section).  This feature allows dynamically
-     loaded objects to be implemented in a relatively straightforward
-     way.  A `.using' directive must always be specified in the `.text'
-     section; this will specify the base register that will be used for
-     branches in the `.text' section.  A second `.using' may be
-     specified in another section; this will specify the base register
-     that is used for non-label address literals.  When a second
-     `.using' is specified, then the subsequent `.ltorg' must be put in
-     the same section; otherwise an error will result.
-
-     Thus, for example, the following code uses `r3' to address branch
-     targets and `r4' to address the literal pool, which has been
-     written to the `.data' section.  The is, the constants
-     `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
-     the `.data' section.
-
-          .data
-          	.using  LITPOOL,r4
-          .text
-          	BASR	r3,0
-          	.using	*,r3
-                  B       START
-          	.long	LITPOOL
-          START:
-          	L	r4,4(,r3)
-          	L	r15,=A(some_routine)
-          	LTR	r15,r15
-          	BNE	LABEL
-          	AH	r0,=H'42'
-          LABEL:
-          	ME	r6,=E'3.1416'
-          .data
-          LITPOOL:
-          	.ltorg
-
-     Note that this dual-`.using' directive semantics extends and is
-     not compatible with HLASM semantics.  Note that this assembler
-     directive does not support the full range of HLASM semantics.
-
-
-
-File: as.info,  Node: ESA/390 Opcodes,  Prev: ESA/390 Directives,  Up: ESA/390-Dependent
-
-8.10.6 Opcodes
---------------
-
-For detailed information on the ESA/390 machine instruction set, see
-`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
-
-
-File: as.info,  Node: i386-Dependent,  Next: i860-Dependent,  Prev: ESA/390-Dependent,  Up: Machine Dependencies
-
-8.11 80386 Dependent Features
-=============================
-
-   The i386 version `as' supports both the original Intel 386
-architecture in both 16 and 32-bit mode as well as AMD x86-64
-architecture extending the Intel architecture to 64-bits.
-
-* Menu:
-
-* i386-Options::                Options
-* i386-Syntax::                 AT&T Syntax versus Intel Syntax
-* i386-Mnemonics::              Instruction Naming
-* i386-Regs::                   Register Naming
-* i386-Prefixes::               Instruction Prefixes
-* i386-Memory::                 Memory References
-* i386-Jumps::                  Handling of Jump Instructions
-* i386-Float::                  Floating Point
-* i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
-* i386-16bit::                  Writing 16-bit Code
-* i386-Arch::                   Specifying an x86 CPU architecture
-* i386-Bugs::                   AT&T Syntax bugs
-* i386-Notes::                  Notes
-
-
-File: as.info,  Node: i386-Options,  Next: i386-Syntax,  Up: i386-Dependent
-
-8.11.1 Options
---------------
-
-The i386 version of `as' has a few machine dependent options:
-
-`--32 | --64'
-     Select the word size, either 32 bits or 64 bits. Selecting 32-bit
-     implies Intel i386 architecture, while 64-bit implies AMD x86-64
-     architecture.
-
-     These options are only available with the ELF object file format,
-     and require that the necessary BFD support has been included (on a
-     32-bit platform you have to add -enable-64-bit-bfd to configure
-     enable 64-bit usage and use x86-64 as target platform).
-
-`-n'
-     By default, x86 GAS replaces multiple nop instructions used for
-     alignment within code sections with multi-byte nop instructions
-     such as leal 0(%esi,1),%esi.  This switch disables the
-     optimization.
-
-`--divide'
-     On SVR4-derived platforms, the character `/' is treated as a
-     comment character, which means that it cannot be used in
-     expressions.  The `--divide' option turns `/' into a normal
-     character.  This does not disable `/' at the beginning of a line
-     starting a comment, or affect using `#' for starting a comment.
-
-
-
-File: as.info,  Node: i386-Syntax,  Next: i386-Mnemonics,  Prev: i386-Options,  Up: i386-Dependent
-
-8.11.2 AT&T Syntax versus Intel Syntax
---------------------------------------
-
-`as' now supports assembly using Intel assembler syntax.
-`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
-the usual AT&T mode for compatibility with the output of `gcc'.  Either
-of these directives may have an optional argument, `prefix', or
-`noprefix' specifying whether registers require a `%' prefix.  AT&T
-System V/386 assembler syntax is quite different from Intel syntax.  We
-mention these differences because almost all 80386 documents use Intel
-syntax.  Notable differences between the two syntaxes are:
-
-   * AT&T immediate operands are preceded by `$'; Intel immediate
-     operands are undelimited (Intel `push 4' is AT&T `pushl $4').
-     AT&T register operands are preceded by `%'; Intel register operands
-     are undelimited.  AT&T absolute (as opposed to PC relative)
-     jump/call operands are prefixed by `*'; they are undelimited in
-     Intel syntax.
-
-   * AT&T and Intel syntax use the opposite order for source and
-     destination operands.  Intel `add eax, 4' is `addl $4, %eax'.  The
-     `source, dest' convention is maintained for compatibility with
-     previous Unix assemblers.  Note that instructions with more than
-     one source operand, such as the `enter' instruction, do _not_ have
-     reversed order.  *Note i386-Bugs::.
-
-   * In AT&T syntax the size of memory operands is determined from the
-     last character of the instruction mnemonic.  Mnemonic suffixes of
-     `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
-     (32-bit) and quadruple word (64-bit) memory references.  Intel
-     syntax accomplishes this by prefixing memory operands (_not_ the
-     instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
-     and `qword ptr'.  Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
-     %al' in AT&T syntax.
-
-   * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
-     $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
-     SECTION:OFFSET'.  Also, the far return instruction is `lret
-     $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
-     STACK-ADJUST'.
-
-   * The AT&T assembler does not provide support for multiple section
-     programs.  Unix style systems expect all programs to be single
-     sections.
-
-
-File: as.info,  Node: i386-Mnemonics,  Next: i386-Regs,  Prev: i386-Syntax,  Up: i386-Dependent
-
-8.11.3 Instruction Naming
--------------------------
-
-Instruction mnemonics are suffixed with one character modifiers which
-specify the size of operands.  The letters `b', `w', `l' and `q'
-specify byte, word, long and quadruple word operands.  If no suffix is
-specified by an instruction then `as' tries to fill in the missing
-suffix based on the destination register operand (the last one by
-convention).  Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
-also, `mov $1, %bx' is equivalent to `movw $1, bx'.  Note that this is
-incompatible with the AT&T Unix assembler which assumes that a missing
-mnemonic suffix implies long operand size.  (This incompatibility does
-not affect compiler output since compilers always explicitly specify
-the mnemonic suffix.)
-
-   Almost all instructions have the same names in AT&T and Intel format.
-There are a few exceptions.  The sign extend and zero extend
-instructions need two sizes to specify them.  They need a size to
-sign/zero extend _from_ and a size to zero extend _to_.  This is
-accomplished by using two instruction mnemonic suffixes in AT&T syntax.
-Base names for sign extend and zero extend are `movs...' and `movz...'
-in AT&T syntax (`movsx' and `movzx' in Intel syntax).  The instruction
-mnemonic suffixes are tacked on to this base name, the _from_ suffix
-before the _to_ suffix.  Thus, `movsbl %al, %edx' is AT&T syntax for
-"move sign extend _from_ %al _to_ %edx."  Possible suffixes, thus, are
-`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
-long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
-word), and `lq' (from long to quadruple word).
-
-   The Intel-syntax conversion instructions
-
-   * `cbw' -- sign-extend byte in `%al' to word in `%ax',
-
-   * `cwde' -- sign-extend word in `%ax' to long in `%eax',
-
-   * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
-
-   * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
-
-   * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
-     only),
-
-   * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
-     (x86-64 only),
-
-are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
-naming.  `as' accepts either naming for these instructions.
-
-   Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
-but are `call far' and `jump far' in Intel convention.
-
-
-File: as.info,  Node: i386-Regs,  Next: i386-Prefixes,  Prev: i386-Mnemonics,  Up: i386-Dependent
-
-8.11.4 Register Naming
-----------------------
-
-Register operands are always prefixed with `%'.  The 80386 registers
-consist of
-
-   * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
-     `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
-     (the stack pointer).
-
-   * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
-     `%si', `%bp', and `%sp'.
-
-   * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
-     `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
-     `%bx', `%cx', and `%dx')
-
-   * the 6 section registers `%cs' (code section), `%ds' (data
-     section), `%ss' (stack section), `%es', `%fs', and `%gs'.
-
-   * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.
-
-   * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
-     `%db7'.
-
-   * the 2 test registers `%tr6' and `%tr7'.
-
-   * the 8 floating point register stack `%st' or equivalently
-     `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
-     `%st(6)', and `%st(7)'.  These registers are overloaded by 8 MMX
-     registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
-     and `%mm7'.
-
-   * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
-     `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
-
-   The AMD x86-64 architecture extends the register set by:
-
-   * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
-     accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
-     frame pointer), `%rsp' (the stack pointer)
-
-   * the 8 extended registers `%r8'-`%r15'.
-
-   * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'
-
-   * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'
-
-   * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'
-
-   * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
-
-   * the 8 debug registers: `%db8'-`%db15'.
-
-   * the 8 SSE registers: `%xmm8'-`%xmm15'.
-
-
-File: as.info,  Node: i386-Prefixes,  Next: i386-Memory,  Prev: i386-Regs,  Up: i386-Dependent
-
-8.11.5 Instruction Prefixes
----------------------------
-
-Instruction prefixes are used to modify the following instruction.  They
-are used to repeat string instructions, to provide section overrides, to
-perform bus lock operations, and to change operand and address sizes.
-(Most instructions that normally operate on 32-bit operands will use
-16-bit operands if the instruction has an "operand size" prefix.)
-Instruction prefixes are best written on the same line as the
-instruction they act upon. For example, the `scas' (scan string)
-instruction is repeated with:
-
-             repne scas %es:(%edi),%al
-
-   You may also place prefixes on the lines immediately preceding the
-instruction, but this circumvents checks that `as' does with prefixes,
-and will not work with all prefixes.
-
-   Here is a list of instruction prefixes:
-
-   * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
-     These are automatically added by specifying using the
-     SECTION:MEMORY-OPERAND form for memory references.
-
-   * Operand/Address size prefixes `data16' and `addr16' change 32-bit
-     operands/addresses into 16-bit operands/addresses, while `data32'
-     and `addr32' change 16-bit ones (in a `.code16' section) into
-     32-bit operands/addresses.  These prefixes _must_ appear on the
-     same line of code as the instruction they modify. For example, in
-     a 16-bit `.code16' section, you might write:
-
-                  addr32 jmpl *(%ebx)
-
-   * The bus lock prefix `lock' inhibits interrupts during execution of
-     the instruction it precedes.  (This is only valid with certain
-     instructions; see a 80386 manual for details).
-
-   * The wait for coprocessor prefix `wait' waits for the coprocessor to
-     complete the current instruction.  This should never be needed for
-     the 80386/80387 combination.
-
-   * The `rep', `repe', and `repne' prefixes are added to string
-     instructions to make them repeat `%ecx' times (`%cx' times if the
-     current address size is 16-bits).  
-
-   * The `rex' family of prefixes is used by x86-64 to encode
-     extensions to i386 instruction set.  The `rex' prefix has four
-     bits -- an operand size overwrite (`64') used to change operand
-     size from 32-bit to 64-bit and X, Y and Z extensions bits used to
-     extend the register set.
-
-     You may write the `rex' prefixes directly. The `rex64xyz'
-     instruction emits `rex' prefix with all the bits set.  By omitting
-     the `64', `x', `y' or `z' you may write other prefixes as well.
-     Normally, there is no need to write the prefixes explicitly, since
-     gas will automatically generate them based on the instruction
-     operands.
-
-
-File: as.info,  Node: i386-Memory,  Next: i386-Jumps,  Prev: i386-Prefixes,  Up: i386-Dependent
-
-8.11.6 Memory References
-------------------------
-
-An Intel syntax indirect memory reference of the form
-
-     SECTION:[BASE + INDEX*SCALE + DISP]
-
-is translated into the AT&T syntax
-
-     SECTION:DISP(BASE, INDEX, SCALE)
-
-where BASE and INDEX are the optional 32-bit base and index registers,
-DISP is the optional displacement, and SCALE, taking the values 1, 2,
-4, and 8, multiplies INDEX to calculate the address of the operand.  If
-no SCALE is specified, SCALE is taken to be 1.  SECTION specifies the
-optional section register for the memory operand, and may override the
-default section register (see a 80386 manual for section register
-defaults). Note that section overrides in AT&T syntax _must_ be
-preceded by a `%'.  If you specify a section override which coincides
-with the default section register, `as' does _not_ output any section
-register override prefixes to assemble the given instruction.  Thus,
-section overrides can be specified to emphasize which section register
-is used for a given memory operand.
-
-   Here are some examples of Intel and AT&T style memory references:
-
-AT&T: `-4(%ebp)', Intel:  `[ebp - 4]'
-     BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
-     section is used (`%ss' for addressing with `%ebp' as the base
-     register).  INDEX, SCALE are both missing.
-
-AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
-     INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'.  All other
-     fields are missing.  The section register here defaults to `%ds'.
-
-AT&T: `foo(,1)'; Intel `[foo]'
-     This uses the value pointed to by `foo' as a memory operand.  Note
-     that BASE and INDEX are both missing, but there is only _one_ `,'.
-     This is a syntactic exception.
-
-AT&T: `%gs:foo'; Intel `gs:foo'
-     This selects the contents of the variable `foo' with section
-     register SECTION being `%gs'.
-
-   Absolute (as opposed to PC relative) call and jump operands must be
-prefixed with `*'.  If no `*' is specified, `as' always chooses PC
-relative addressing for jump/call labels.
-
-   Any instruction that has a memory operand, but no register operand,
-_must_ specify its size (byte, word, long, or quadruple) with an
-instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
-
-   The x86-64 architecture adds an RIP (instruction pointer relative)
-addressing.  This addressing mode is specified by using `rip' as a base
-register.  Only constant offsets are valid. For example:
-
-AT&T: `1234(%rip)', Intel: `[rip + 1234]'
-     Points to the address 1234 bytes past the end of the current
-     instruction.
-
-AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
-     Points to the `symbol' in RIP relative way, this is shorter than
-     the default absolute addressing.
-
-   Other addressing modes remain unchanged in x86-64 architecture,
-except registers used are 64-bit instead of 32-bit.
-
-
-File: as.info,  Node: i386-Jumps,  Next: i386-Float,  Prev: i386-Memory,  Up: i386-Dependent
-
-8.11.7 Handling of Jump Instructions
-------------------------------------
-
-Jump instructions are always optimized to use the smallest possible
-displacements.  This is accomplished by using byte (8-bit) displacement
-jumps whenever the target is sufficiently close.  If a byte displacement
-is insufficient a long displacement is used.  We do not support word
-(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
-instruction with the `data16' instruction prefix), since the 80386
-insists upon masking `%eip' to 16 bits after the word displacement is
-added. (See also *note i386-Arch::)
-
-   Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
-and `loopne' instructions only come in byte displacements, so that if
-you use these instructions (`gcc' does not use them) you may get an
-error message (and incorrect code).  The AT&T 80386 assembler tries to
-get around this problem by expanding `jcxz foo' to
-
-              jcxz cx_zero
-              jmp cx_nonzero
-     cx_zero: jmp foo
-     cx_nonzero:
-
-
-File: as.info,  Node: i386-Float,  Next: i386-SIMD,  Prev: i386-Jumps,  Up: i386-Dependent
-
-8.11.8 Floating Point
----------------------
-
-All 80387 floating point types except packed BCD are supported.  (BCD
-support may be added without much difficulty).  These data types are
-16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
-and extended (80-bit) precision floating point.  Each supported type
-has an instruction mnemonic suffix and a constructor associated with
-it.  Instruction mnemonic suffixes specify the operand's data type.
-Constructors build these data types into memory.
-
-   * Floating point constructors are `.float' or `.single', `.double',
-     and `.tfloat' for 32-, 64-, and 80-bit formats.  These correspond
-     to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
-     80-bit (ten byte) real.  The 80387 only supports this format via
-     the `fldt' (load 80-bit real to stack top) and `fstpt' (store
-     80-bit real and pop stack) instructions.
-
-   * Integer constructors are `.word', `.long' or `.int', and `.quad'
-     for the 16-, 32-, and 64-bit integer formats.  The corresponding
-     instruction mnemonic suffixes are `s' (single), `l' (long), and
-     `q' (quad).  As with the 80-bit real format, the 64-bit `q' format
-     is only present in the `fildq' (load quad integer to stack top)
-     and `fistpq' (store quad integer and pop stack) instructions.
-
-   Register to register operations should not use instruction mnemonic
-suffixes.  `fstl %st, %st(1)' will give a warning, and be assembled as
-if you wrote `fst %st, %st(1)', since all register to register
-operations use 80-bit floating point operands. (Contrast this with
-`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
-point format, then stores the result in the 4 byte location `mem')
-
-
-File: as.info,  Node: i386-SIMD,  Next: i386-16bit,  Prev: i386-Float,  Up: i386-Dependent
-
-8.11.9 Intel's MMX and AMD's 3DNow! SIMD Operations
----------------------------------------------------
-
-`as' supports Intel's MMX instruction set (SIMD instructions for
-integer data), available on Intel's Pentium MMX processors and Pentium
-II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
-probably others.  It also supports AMD's 3DNow!  instruction set (SIMD
-instructions for 32-bit floating point data) available on AMD's K6-2
-processor and possibly others in the future.
-
-   Currently, `as' does not support Intel's floating point SIMD, Katmai
-(KNI).
-
-   The eight 64-bit MMX operands, also used by 3DNow!, are called
-`%mm0', `%mm1', ... `%mm7'.  They contain eight 8-bit integers, four
-16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
-floating point values.  The MMX registers cannot be used at the same
-time as the floating point stack.
-
-   See Intel and AMD documentation, keeping in mind that the operand
-order in instructions is reversed from the Intel syntax.
-
-
-File: as.info,  Node: i386-16bit,  Next: i386-Arch,  Prev: i386-SIMD,  Up: i386-Dependent
-
-8.11.10 Writing 16-bit Code
----------------------------
-
-While `as' normally writes only "pure" 32-bit i386 code or 64-bit
-x86-64 code depending on the default configuration, it also supports
-writing code to run in real mode or in 16-bit protected mode code
-segments.  To do this, put a `.code16' or `.code16gcc' directive before
-the assembly language instructions to be run in 16-bit mode.  You can
-switch `as' back to writing normal 32-bit code with the `.code32'
-directive.
-
-   `.code16gcc' provides experimental support for generating 16-bit
-code from gcc, and differs from `.code16' in that `call', `ret',
-`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
-instructions default to 32-bit size.  This is so that the stack pointer
-is manipulated in the same way over function calls, allowing access to
-function parameters at the same stack offsets as in 32-bit mode.
-`.code16gcc' also automatically adds address size prefixes where
-necessary to use the 32-bit addressing modes that gcc generates.
-
-   The code which `as' generates in 16-bit mode will not necessarily
-run on a 16-bit pre-80386 processor.  To write code that runs on such a
-processor, you must refrain from using _any_ 32-bit constructs which
-require `as' to output address or operand size prefixes.
-
-   Note that writing 16-bit code instructions by explicitly specifying a
-prefix or an instruction mnemonic suffix within a 32-bit code section
-generates different machine instructions than those generated for a
-16-bit code segment.  In a 32-bit code section, the following code
-generates the machine opcode bytes `66 6a 04', which pushes the value
-`4' onto the stack, decrementing `%esp' by 2.
-
-             pushw $4
-
-   The same code in a 16-bit code section would generate the machine
-opcode bytes `6a 04' (ie. without the operand size prefix), which is
-correct since the processor default operand size is assumed to be 16
-bits in a 16-bit code section.
-
-
-File: as.info,  Node: i386-Bugs,  Next: i386-Notes,  Prev: i386-Arch,  Up: i386-Dependent
-
-8.11.11 AT&T Syntax bugs
-------------------------
-
-The UnixWare assembler, and probably other AT&T derived ix86 Unix
-assemblers, generate floating point instructions with reversed source
-and destination registers in certain cases.  Unfortunately, gcc and
-possibly many other programs use this reversed syntax, so we're stuck
-with it.
-
-   For example
-
-             fsub %st,%st(3)
-   results in `%st(3)' being updated to `%st - %st(3)' rather than the
-expected `%st(3) - %st'.  This happens with all the non-commutative
-arithmetic floating point operations with two register operands where
-the source register is `%st' and the destination register is `%st(i)'.
-
-
-File: as.info,  Node: i386-Arch,  Next: i386-Bugs,  Prev: i386-16bit,  Up: i386-Dependent
-
-8.11.12 Specifying CPU Architecture
------------------------------------
-
-`as' may be told to assemble for a particular CPU (sub-)architecture
-with the `.arch CPU_TYPE' directive.  This directive enables a warning
-when gas detects an instruction that is not supported on the CPU
-specified.  The choices for CPU_TYPE are:
-
-`i8086'        `i186'         `i286'         `i386'
-`i486'         `i586'         `i686'         `pentium'
-`pentiumpro'   `pentiumii'    `pentiumiii'   `pentium4'
-`k6'           `athlon'                      
-               `sledgehammer'                
-`.mmx' `.sse'                                
-`.sse2'                                      
-`.sse3'                                      
-`.3dnow'                                     
-
-   Apart from the warning, there are only two other effects on `as'
-operation;  Firstly, if you specify a CPU other than `i486', then shift
-by one instructions such as `sarl $1, %eax' will automatically use a
-two byte opcode sequence.  The larger three byte opcode sequence is
-used on the 486 (and when no architecture is specified) because it
-executes faster on the 486.  Note that you can explicitly request the
-two byte opcode by writing `sarl %eax'.  Secondly, if you specify
-`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
-offset conditional jumps will be promoted when necessary to a two
-instruction sequence consisting of a conditional jump of the opposite
-sense around an unconditional jump to the target.
-
-   Following the CPU architecture (but not a sub-architecture, which
-are those starting with a dot), you may specify `jumps' or `nojumps' to
-control automatic promotion of conditional jumps. `jumps' is the
-default, and enables jump promotion;  All external jumps will be of the
-long variety, and file-local jumps will be promoted as necessary.
-(*note i386-Jumps::)  `nojumps' leaves external conditional jumps as
-byte offset jumps, and warns about file-local conditional jumps that
-`as' promotes.  Unconditional jumps are treated as for `jumps'.
-
-   For example
-
-      .arch i8086,nojumps
-
-
-File: as.info,  Node: i386-Notes,  Prev: i386-Bugs,  Up: i386-Dependent
-
-8.11.13 Notes
--------------
-
-There is some trickery concerning the `mul' and `imul' instructions
-that deserves mention.  The 16-, 32-, 64- and 128-bit expanding
-multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
-can be output only in the one operand form.  Thus, `imul %ebx, %eax'
-does _not_ select the expanding multiply; the expanding multiply would
-clobber the `%edx' register, and this would confuse `gcc' output.  Use
-`imul %ebx' to get the 64-bit product in `%edx:%eax'.
-
-   We have added a two operand form of `imul' when the first operand is
-an immediate mode expression and the second operand is a register.
-This is just a shorthand, so that, multiplying `%eax' by 69, for
-example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
-%eax'.
-
-
-File: as.info,  Node: i860-Dependent,  Next: i960-Dependent,  Prev: i386-Dependent,  Up: Machine Dependencies
-
-8.12 Intel i860 Dependent Features
-==================================
-
-* Menu:
-
-* Notes-i860::                  i860 Notes
-* Options-i860::                i860 Command-line Options
-* Directives-i860::             i860 Machine Directives
-* Opcodes for i860::            i860 Opcodes
-
-
-File: as.info,  Node: Notes-i860,  Next: Options-i860,  Up: i860-Dependent
-
-8.12.1 i860 Notes
------------------
-
-This is a fairly complete i860 assembler which is compatible with the
-UNIX System V/860 Release 4 assembler. However, it does not currently
-support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
-
-   Like the SVR4/860 assembler, the output object format is ELF32.
-Currently, this is the only supported object format. If there is
-sufficient interest, other formats such as COFF may be implemented.
-
-   Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
-being the default.  One difference is that AT&T syntax requires the '%'
-prefix on register names while Intel syntax does not.  Another
-difference is in the specification of relocatable expressions.  The
-Intel syntax is `ha%expression' whereas the SVR4 syntax is
-`[expression]@ha' (and similarly for the "l" and "h" selectors).
-
-
-File: as.info,  Node: Options-i860,  Next: Directives-i860,  Prev: Notes-i860,  Up: i860-Dependent
-
-8.12.2 i860 Command-line Options
---------------------------------
-
-8.12.2.1 SVR4 compatibility options
-...................................
-
-`-V'
-     Print assembler version.
-
-`-Qy'
-     Ignored.
-
-`-Qn'
-     Ignored.
-
-8.12.2.2 Other options
-......................
-
-`-EL'
-     Select little endian output (this is the default).
-
-`-EB'
-     Select big endian output. Note that the i860 always reads
-     instructions as little endian data, so this option only effects
-     data and not instructions.
-
-`-mwarn-expand'
-     Emit a warning message if any pseudo-instruction expansions
-     occurred.  For example, a `or' instruction with an immediate
-     larger than 16-bits will be expanded into two instructions. This
-     is a very undesirable feature to rely on, so this flag can help
-     detect any code where it happens. One use of it, for instance, has
-     been to find and eliminate any place where `gcc' may emit these
-     pseudo-instructions.
-
-`-mxp'
-     Enable support for the i860XP instructions and control registers.
-     By default, this option is disabled so that only the base
-     instruction set (i.e., i860XR) is supported.
-
-`-mintel-syntax'
-     The i860 assembler defaults to AT&T/SVR4 syntax.  This option
-     enables the Intel syntax.
-
-
-File: as.info,  Node: Directives-i860,  Next: Opcodes for i860,  Prev: Options-i860,  Up: i860-Dependent
-
-8.12.3 i860 Machine Directives
-------------------------------
-
-`.dual'
-     Enter dual instruction mode. While this directive is supported, the
-     preferred way to use dual instruction mode is to explicitly code
-     the dual bit with the `d.' prefix.
-
-`.enddual'
-     Exit dual instruction mode. While this directive is supported, the
-     preferred way to use dual instruction mode is to explicitly code
-     the dual bit with the `d.' prefix.
-
-`.atmp'
-     Change the temporary register used when expanding pseudo
-     operations. The default register is `r31'.
-
-   The `.dual', `.enddual', and `.atmp' directives are available only
-in the Intel syntax mode.
-
-   Both syntaxes allow for the standard `.align' directive.  However,
-the Intel syntax additionally allows keywords for the alignment
-parameter: "`.align type'", where `type' is one of `.short', `.long',
-`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4,
-and 8, respectively.
-
-
-File: as.info,  Node: Opcodes for i860,  Prev: Directives-i860,  Up: i860-Dependent
-
-8.12.4 i860 Opcodes
--------------------
-
-All of the Intel i860XR and i860XP machine instructions are supported.
-Please see either _i860 Microprocessor Programmer's Reference Manual_
-or _i860 Microprocessor Architecture_ for more information.
-
-8.12.4.1 Other instruction support (pseudo-instructions)
-........................................................
-
-For compatibility with some other i860 assemblers, a number of
-pseudo-instructions are supported. While these are supported, they are
-a very undesirable feature that should be avoided - in particular, when
-they result in an expansion to multiple actual i860 instructions. Below
-are the pseudo-instructions that result in expansions.
-   * Load large immediate into general register:
-
-     The pseudo-instruction `mov imm,%rn' (where the immediate does not
-     fit within a signed 16-bit field) will be expanded into:
-          orh large_imm@h,%r0,%rn
-          or large_imm@l,%rn,%rn
-
-   * Load/store with relocatable address expression:
-
-     For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will
-     be expanded into:
-          orh addr_exp@ha,%rx,%r31
-          ld.l addr_exp@l(%r31),%rn
-
-     The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
-     fst.x', and `pst.x' as well.
-
-   * Signed large immediate with add/subtract:
-
-     If any of the arithmetic operations `adds, addu, subs, subu' are
-     used with an immediate larger than 16-bits (signed), then they
-     will be expanded.  For instance, the pseudo-instruction `adds
-     large_imm,%rx,%rn' expands to:
-          orh large_imm@h,%r0,%r31
-          or large_imm@l,%r31,%r31
-          adds %r31,%rx,%rn
-
-   * Unsigned large immediate with logical operations:
-
-     Logical operations (`or, andnot, or, xor') also result in
-     expansions.  The pseudo-instruction `or large_imm,%rx,%rn' results
-     in:
-          orh large_imm@h,%rx,%r31
-          or large_imm@l,%r31,%rn
-
-     Similarly for the others, except for `and' which expands to:
-          andnot (-1 - large_imm)@h,%rx,%r31
-          andnot (-1 - large_imm)@l,%r31,%rn
-
-
-File: as.info,  Node: i960-Dependent,  Next: IA-64-Dependent,  Prev: i860-Dependent,  Up: Machine Dependencies
-
-8.13 Intel 80960 Dependent Features
-===================================
-
-* Menu:
-
-* Options-i960::                i960 Command-line Options
-* Floating Point-i960::         Floating Point
-* Directives-i960::             i960 Machine Directives
-* Opcodes for i960::            i960 Opcodes
-
-
-File: as.info,  Node: Options-i960,  Next: Floating Point-i960,  Up: i960-Dependent
-
-8.13.1 i960 Command-line Options
---------------------------------
-
-`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
-     Select the 80960 architecture.  Instructions or features not
-     supported by the selected architecture cause fatal errors.
-
-     `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
-     Synonyms are provided for compatibility with other tools.
-
-     If you do not specify any of these options, `as' generates code
-     for any instruction or feature that is supported by _some_ version
-     of the 960 (even if this means mixing architectures!).  In
-     principle, `as' attempts to deduce the minimal sufficient
-     processor type if none is specified; depending on the object code
-     format, the processor type may be recorded in the object file.  If
-     it is critical that the `as' output match a specific architecture,
-     specify that architecture explicitly.
-
-`-b'
-     Add code to collect information about conditional branches taken,
-     for later optimization using branch prediction bits.  (The
-     conditional branch instructions have branch prediction bits in the
-     CA, CB, and CC architectures.)  If BR represents a conditional
-     branch instruction, the following represents the code generated by
-     the assembler when `-b' is specified:
-
-                  call    INCREMENT ROUTINE
-                  .word   0       # pre-counter
-          Label:  BR
-                  call    INCREMENT ROUTINE
-                  .word   0       # post-counter
-
-     The counter following a branch records the number of times that
-     branch was _not_ taken; the differenc between the two counters is
-     the number of times the branch _was_ taken.
-
-     A table of every such `Label' is also generated, so that the
-     external postprocessor `gbr960' (supplied by Intel) can locate all
-     the counters.  This table is always labeled `__BRANCH_TABLE__';
-     this is a local symbol to permit collecting statistics for many
-     separate object files.  The table is word aligned, and begins with
-     a two-word header.  The first word, initialized to 0, is used in
-     maintaining linked lists of branch tables.  The second word is a
-     count of the number of entries in the table, which follow
-     immediately: each is a word, pointing to one of the labels
-     illustrated above.
-
-           +------------+------------+------------+ ... +------------+
-           |            |            |            |     |            |
-           |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
-           |            |            |            |     |            |
-           +------------+------------+------------+ ... +------------+
-
-                         __BRANCH_TABLE__ layout
-
-     The first word of the header is used to locate multiple branch
-     tables, since each object file may contain one. Normally the links
-     are maintained with a call to an initialization routine, placed at
-     the beginning of each function in the file.  The GNU C compiler
-     generates these calls automatically when you give it a `-b' option.
-     For further details, see the documentation of `gbr960'.
-
-`-no-relax'
-     Normally, Compare-and-Branch instructions with targets that require
-     displacements greater than 13 bits (or that have external targets)
-     are replaced with the corresponding compare (or `chkbit') and
-     branch instructions.  You can use the `-no-relax' option to
-     specify that `as' should generate errors instead, if the target
-     displacement is larger than 13 bits.
-
-     This option does not affect the Compare-and-Jump instructions; the
-     code emitted for them is _always_ adjusted when necessary
-     (depending on displacement size), regardless of whether you use
-     `-no-relax'.
-
-
-File: as.info,  Node: Floating Point-i960,  Next: Directives-i960,  Prev: Options-i960,  Up: i960-Dependent
-
-8.13.2 Floating Point
----------------------
-
-`as' generates IEEE floating-point numbers for the directives `.float',
-`.double', `.extended', and `.single'.
-
-
-File: as.info,  Node: Directives-i960,  Next: Opcodes for i960,  Prev: Floating Point-i960,  Up: i960-Dependent
-
-8.13.3 i960 Machine Directives
-------------------------------
-
-`.bss SYMBOL, LENGTH, ALIGN'
-     Reserve LENGTH bytes in the bss section for a local SYMBOL,
-     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
-     must be positive absolute expressions.  This directive differs
-     from `.lcomm' only in that it permits you to specify an alignment.
-     *Note `.lcomm': Lcomm.
-
-`.extended FLONUMS'
-     `.extended' expects zero or more flonums, separated by commas; for
-     each flonum, `.extended' emits an IEEE extended-format (80-bit)
-     floating-point number.
-
-`.leafproc CALL-LAB, BAL-LAB'
-     You can use the `.leafproc' directive in conjunction with the
-     optimized `callj' instruction to enable faster calls of leaf
-     procedures.  If a procedure is known to call no other procedures,
-     you may define an entry point that skips procedure prolog code
-     (and that does not depend on system-supplied saved context), and
-     declare it as the BAL-LAB using `.leafproc'.  If the procedure
-     also has an entry point that goes through the normal prolog, you
-     can specify that entry point as CALL-LAB.
-
-     A `.leafproc' declaration is meant for use in conjunction with the
-     optimized call instruction `callj'; the directive records the data
-     needed later to choose between converting the `callj' into a `bal'
-     or a `call'.
-
-     CALL-LAB is optional; if only one argument is present, or if the
-     two arguments are identical, the single argument is assumed to be
-     the `bal' entry point.
-
-`.sysproc NAME, INDEX'
-     The `.sysproc' directive defines a name for a system procedure.
-     After you define it using `.sysproc', you can use NAME to refer to
-     the system procedure identified by INDEX when calling procedures
-     with the optimized call instruction `callj'.
-
-     Both arguments are required; INDEX must be between 0 and 31
-     (inclusive).
-
-
-File: as.info,  Node: Opcodes for i960,  Prev: Directives-i960,  Up: i960-Dependent
-
-8.13.4 i960 Opcodes
--------------------
-
-All Intel 960 machine instructions are supported; *note i960
-Command-line Options: Options-i960. for a discussion of selecting the
-instruction subset for a particular 960 architecture.
-
-   Some opcodes are processed beyond simply emitting a single
-corresponding instruction: `callj', and Compare-and-Branch or
-Compare-and-Jump instructions with target displacements larger than 13
-bits.
-
-* Menu:
-
-* callj-i960::                  `callj'
-* Compare-and-branch-i960::     Compare-and-Branch
-
-
-File: as.info,  Node: callj-i960,  Next: Compare-and-branch-i960,  Up: Opcodes for i960
-
-8.13.4.1 `callj'
-................
-
-You can write `callj' to have the assembler or the linker determine the
-most appropriate form of subroutine call: `call', `bal', or `calls'.
-If the assembly source contains enough information--a `.leafproc' or
-`.sysproc' directive defining the operand--then `as' translates the
-`callj'; if not, it simply emits the `callj', leaving it for the linker
-to resolve.
-
-
-File: as.info,  Node: Compare-and-branch-i960,  Prev: callj-i960,  Up: Opcodes for i960
-
-8.13.4.2 Compare-and-Branch
-...........................
-
-The 960 architectures provide combined Compare-and-Branch instructions
-that permit you to store the branch target in the lower 13 bits of the
-instruction word itself.  However, if you specify a branch target far
-enough away that its address won't fit in 13 bits, the assembler can
-either issue an error, or convert your Compare-and-Branch instruction
-into separate instructions to do the compare and the branch.
-
-   Whether `as' gives an error or expands the instruction depends on
-two choices you can make: whether you use the `-no-relax' option, and
-whether you use a "Compare and Branch" instruction or a "Compare and
-Jump" instruction.  The "Jump" instructions are _always_ expanded if
-necessary; the "Branch" instructions are expanded when necessary
-_unless_ you specify `-no-relax'--in which case `as' gives an error
-instead.
-
-   These are the Compare-and-Branch instructions, their "Jump" variants,
-and the instruction pairs they may expand into:
-
-             Compare and
-          Branch      Jump       Expanded to
-          ------    ------       ------------
-             bbc                 chkbit; bno
-             bbs                 chkbit; bo
-          cmpibe    cmpije       cmpi; be
-          cmpibg    cmpijg       cmpi; bg
-         cmpibge   cmpijge       cmpi; bge
-          cmpibl    cmpijl       cmpi; bl
-         cmpible   cmpijle       cmpi; ble
-         cmpibno   cmpijno       cmpi; bno
-         cmpibne   cmpijne       cmpi; bne
-          cmpibo    cmpijo       cmpi; bo
-          cmpobe    cmpoje       cmpo; be
-          cmpobg    cmpojg       cmpo; bg
-         cmpobge   cmpojge       cmpo; bge
-          cmpobl    cmpojl       cmpo; bl
-         cmpoble   cmpojle       cmpo; ble
-         cmpobne   cmpojne       cmpo; bne
-
-
-File: as.info,  Node: IA-64-Dependent,  Next: IP2K-Dependent,  Prev: i960-Dependent,  Up: Machine Dependencies
-
-8.14 IA-64 Dependent Features
-=============================
-
-* Menu:
-
-* IA-64 Options::              Options
-* IA-64 Syntax::               Syntax
-* IA-64 Opcodes::              Opcodes
-
-
-File: as.info,  Node: IA-64 Options,  Next: IA-64 Syntax,  Up: IA-64-Dependent
-
-8.14.1 Options
---------------
-
-`-mconstant-gp'
-     This option instructs the assembler to mark the resulting object
-     file as using the "constant GP" model.  With this model, it is
-     assumed that the entire program uses a single global pointer (GP)
-     value.  Note that this option does not in any fashion affect the
-     machine code emitted by the assembler.  All it does is turn on the
-     EF_IA_64_CONS_GP flag in the ELF file header.
-
-`-mauto-pic'
-     This option instructs the assembler to mark the resulting object
-     file as using the "constant GP without function descriptor" data
-     model.  This model is like the "constant GP" model, except that it
-     additionally does away with function descriptors.  What this means
-     is that the address of a function refers directly to the
-     function's code entry-point.  Normally, such an address would
-     refer to a function descriptor, which contains both the code
-     entry-point and the GP-value needed by the function.  Note that
-     this option does not in any fashion affect the machine code
-     emitted by the assembler.  All it does is turn on the
-     EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
-
-`-milp32'
-
-`-milp64'
-
-`-mlp64'
-
-`-mp64'
-     These options select the data model.  The assembler defaults to
-     `-mlp64' (LP64 data model).
-
-`-mle'
-
-`-mbe'
-     These options select the byte order.  The `-mle' option selects
-     little-endian byte order (default) and `-mbe' selects big-endian
-     byte order.  Note that IA-64 machine code always uses
-     little-endian byte order.
-
-`-mtune=itanium1'
-
-`-mtune=itanium2'
-     Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
-     is ITANIUM2.
-
-`-munwind-check=warning'
-
-`-munwind-check=error'
-     These options control what the assembler will do when performing
-     consistency checks on unwind directives.  `-munwind-check=warning'
-     will make the assembler issue a warning when an unwind directive
-     check fails.  This is the default.  `-munwind-check=error' will
-     make the assembler issue an error when an unwind directive check
-     fails.
-
-`-mhint.b=ok'
-
-`-mhint.b=warning'
-
-`-mhint.b=error'
-     These options control what the assembler will do when the `hint.b'
-     instruction is used.  `-mhint.b=ok' will make the assembler accept
-     `hint.b'.  `-mint.b=warning' will make the assembler issue a
-     warning when `hint.b' is used.  `-mhint.b=error' will make the
-     assembler treat `hint.b' as an error, which is the default.
-
-`-x'
-
-`-xexplicit'
-     These options turn on dependency violation checking.
-
-`-xauto'
-     This option instructs the assembler to automatically insert stop
-     bits where necessary to remove dependency violations.  This is the
-     default mode.
-
-`-xnone'
-     This option turns off dependency violation checking.
-
-`-xdebug'
-     This turns on debug output intended to help tracking down bugs in
-     the dependency violation checker.
-
-`-xdebugn'
-     This is a shortcut for -xnone -xdebug.
-
-`-xdebugx'
-     This is a shortcut for -xexplicit -xdebug.
-
-
-
-File: as.info,  Node: IA-64 Syntax,  Next: IA-64 Opcodes,  Prev: IA-64 Options,  Up: IA-64-Dependent
-
-8.14.2 Syntax
--------------
-
-The assembler syntax closely follows the IA-64 Assembly Language
-Reference Guide.
-
-* Menu:
-
-* IA-64-Chars::                Special Characters
-* IA-64-Regs::                 Register Names
-* IA-64-Bits::                 Bit Names
-
-
-File: as.info,  Node: IA-64-Chars,  Next: IA-64-Regs,  Up: IA-64 Syntax
-
-8.14.2.1 Special Characters
-...........................
-
-`//' is the line comment token.
-
-   `;' can be used instead of a newline to separate statements.
-
-
-File: as.info,  Node: IA-64-Regs,  Next: IA-64-Bits,  Prev: IA-64-Chars,  Up: IA-64 Syntax
-
-8.14.2.2 Register Names
-.......................
-
-The 128 integer registers are referred to as `rN'.  The 128
-floating-point registers are referred to as `fN'.  The 128 application
-registers are referred to as `arN'.  The 128 control registers are
-referred to as `crN'.  The 64 one-bit predicate registers are referred
-to as `pN'.  The 8 branch registers are referred to as `bN'.  In
-addition, the assembler defines a number of aliases: `gp' (`r1'), `sp'
-(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'),
-`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N').
-
-   For convenience, the assembler also defines aliases for all named
-application and control registers.  For example, `ar.bsp' refers to the
-register backing store pointer (`ar17').  Similarly, `cr.eoi' refers to
-the end-of-interrupt register (`cr67').
-
-
-File: as.info,  Node: IA-64-Bits,  Prev: IA-64-Regs,  Up: IA-64 Syntax
-
-8.14.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
-........................................................
-
-The assembler defines bit masks for each of the bits in the IA-64
-processor status register.  For example, `psr.ic' corresponds to a
-value of 0x2000.  These masks are primarily intended for use with the
-`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere
-else where an integer constant is expected.
-
-
-File: as.info,  Node: IA-64 Opcodes,  Prev: IA-64 Syntax,  Up: IA-64-Dependent
-
-8.14.3 Opcodes
---------------
-
-For detailed information on the IA-64 machine instruction set, see the
-IA-64 Architecture Handbook
-(http://developer.intel.com/design/itanium/arch_spec.htm).
-
-
-File: as.info,  Node: IP2K-Dependent,  Next: M32C-Dependent,  Prev: IA-64-Dependent,  Up: Machine Dependencies
-
-8.15 IP2K Dependent Features
-============================
-
-* Menu:
-
-* IP2K-Opts::                   IP2K Options
-
-
-File: as.info,  Node: IP2K-Opts,  Up: IP2K-Dependent
-
-8.15.1 IP2K Options
--------------------
-
-The Ubicom IP2K version of `as' has a few machine dependent options:
-
-`-mip2022ext'
-     `as' can assemble the extended IP2022 instructions, but it will
-     only do so if this is specifically allowed via this command line
-     option.
-
-`-mip2022'
-     This option restores the assembler's default behaviour of not
-     permitting the extended IP2022 instructions to be assembled.
-
-
-
-File: as.info,  Node: M32C-Dependent,  Next: M32R-Dependent,  Prev: IP2K-Dependent,  Up: Machine Dependencies
-
-8.16 M32C Dependent Features
-============================
-
-   `as' can assemble code for several different members of the Renesas
-M32C family.  Normally the default is to assemble code for the M16C
-microprocessor.  The `-m32c' option may be used to change the default
-to the M32C microprocessor.
-
-* Menu:
-
-* M32C-Opts::                   M32C Options
-* M32C-Modifiers::              Symbolic Operand Modifiers
-
-
-File: as.info,  Node: M32C-Opts,  Next: M32C-Modifiers,  Up: M32C-Dependent
-
-8.16.1 M32C Options
--------------------
-
-The Renesas M32C version of `as' has two machine-dependent options:
-
-`-m32c'
-     Assemble M32C instructions.
-
-`-m16c'
-     Assemble M16C instructions (default).
-
-
-
-File: as.info,  Node: M32C-Modifiers,  Prev: M32C-Opts,  Up: M32C-Dependent
-
-8.16.2 Symbolic Operand Modifiers
----------------------------------
-
-The assembler supports several modifiers when using symbol addresses in
-M32C instruction operands.  The general syntax is the following:
-
-     %modifier(symbol)
-
-`%dsp8'
-`%dsp16'
-     These modifiers override the assembler's assumptions about how big
-     a symbol's address is.  Normally, when it sees an operand like
-     `sym[a0]' it assumes `sym' may require the widest displacement
-     field (16 bits for `-m16c', 24 bits for `-m32c').  These modifiers
-     tell it to assume the address will fit in an 8 or 16 bit
-     (respectively) unsigned displacement.  Note that, of course, if it
-     doesn't actually fit you will get linker errors.  Example:
-
-          mov.w %dsp8(sym)[a0],r1
-          mov.b #0,%dsp8(sym)[a0]
-
-`%hi8'
-     This modifier allows you to load bits 16 through 23 of a 24 bit
-     address into an 8 bit register.  This is useful with, for example,
-     the M16C `smovf' instruction, which expects a 20 bit address in
-     `r1h' and `a0'.  Example:
-
-          mov.b #%hi8(sym),r1h
-          mov.w #%lo16(sym),a0
-          smovf.b
-
-`%lo16'
-     Likewise, this modifier allows you to load bits 0 through 15 of a
-     24 bit address into a 16 bit register.
-
-`%hi16'
-     This modifier allows you to load bits 16 through 31 of a 32 bit
-     address into a 16 bit register.  While the M32C family only has 24
-     bits of address space, it does support addresses in pairs of 16 bit
-     registers (like `a1a0' for the `lde' instruction).  This modifier
-     is for loading the upper half in such cases.  Example:
-
-          mov.w #%hi16(sym),a1
-          mov.w #%lo16(sym),a0
-          ...
-          lde.w [a1a0],r1
-
-
-
-File: as.info,  Node: M32R-Dependent,  Next: M68K-Dependent,  Prev: M32C-Dependent,  Up: Machine Dependencies
-
-8.17 M32R Dependent Features
-============================
-
-* Menu:
-
-* M32R-Opts::                   M32R Options
-* M32R-Directives::             M32R Directives
-* M32R-Warnings::               M32R Warnings
-
-
-File: as.info,  Node: M32R-Opts,  Next: M32R-Directives,  Up: M32R-Dependent
-
-8.17.1 M32R Options
--------------------
-
-The Renease M32R version of `as' has a few machine dependent options:
-
-`-m32rx'
-     `as' can assemble code for several different members of the
-     Renesas M32R family.  Normally the default is to assemble code for
-     the M32R microprocessor.  This option may be used to change the
-     default to the M32RX microprocessor, which adds some more
-     instructions to the basic M32R instruction set, and some
-     additional parameters to some of the original instructions.
-
-`-m32r2'
-     This option changes the target processor to the the M32R2
-     microprocessor.
-
-`-m32r'
-     This option can be used to restore the assembler's default
-     behaviour of assembling for the M32R microprocessor.  This can be
-     useful if the default has been changed by a previous command line
-     option.
-
-`-little'
-     This option tells the assembler to produce little-endian code and
-     data.  The default is dependent upon how the toolchain was
-     configured.
-
-`-EL'
-     This is a synonum for _-little_.
-
-`-big'
-     This option tells the assembler to produce big-endian code and
-     data.
-
-`-EB'
-     This is a synonum for _-big_.
-
-`-KPIC'
-     This option specifies that the output of the assembler should be
-     marked as position-independent code (PIC).
-
-`-parallel'
-     This option tells the assembler to attempts to combine two
-     sequential instructions into a single, parallel instruction, where
-     it is legal to do so.
-
-`-no-parallel'
-     This option disables a previously enabled _-parallel_ option.
-
-`-no-bitinst'
-     This option disables the support for the extended bit-field
-     instructions provided by the M32R2.  If this support needs to be
-     re-enabled the _-bitinst_ switch can be used to restore it.
-
-`-O'
-     This option tells the assembler to attempt to optimize the
-     instructions that it produces.  This includes filling delay slots
-     and converting sequential instructions into parallel ones.  This
-     option implies _-parallel_.
-
-`-warn-explicit-parallel-conflicts'
-     Instructs `as' to produce warning messages when questionable
-     parallel instructions are encountered.  This option is enabled by
-     default, but `gcc' disables it when it invokes `as' directly.
-     Questionable instructions are those whoes behaviour would be
-     different if they were executed sequentially.  For example the
-     code fragment `mv r1, r2 || mv r3, r1' produces a different result
-     from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
-     and then r2 into r1, whereas the later moves r2 into r1 and r3.
-
-`-Wp'
-     This is a shorter synonym for the
-     _-warn-explicit-parallel-conflicts_ option.
-
-`-no-warn-explicit-parallel-conflicts'
-     Instructs `as' not to produce warning messages when questionable
-     parallel instructions are encountered.
-
-`-Wnp'
-     This is a shorter synonym for the
-     _-no-warn-explicit-parallel-conflicts_ option.
-
-`-ignore-parallel-conflicts'
-     This option tells the assembler's to stop checking parallel
-     instructions for contraint violations.  This ability is provided
-     for hardware vendors testing chip designs and should not be used
-     under normal circumstances.
-
-`-no-ignore-parallel-conflicts'
-     This option restores the assembler's default behaviour of checking
-     parallel instructions to detect constraint violations.
-
-`-Ip'
-     This is a shorter synonym for the _-ignore-parallel-conflicts_
-     option.
-
-`-nIp'
-     This is a shorter synonym for the _-no-ignore-parallel-conflicts_
-     option.
-
-`-warn-unmatched-high'
-     This option tells the assembler to produce a warning message if a
-     `.high' pseudo op is encountered without a mathcing `.low' pseudo
-     op.  The presence of such an unmatches pseudo op usually indicates
-     a programming error.
-
-`-no-warn-unmatched-high'
-     Disables a previously enabled _-warn-unmatched-high_ option.
-
-`-Wuh'
-     This is a shorter synonym for the _-warn-unmatched-high_ option.
-
-`-Wnuh'
-     This is a shorter synonym for the _-no-warn-unmatched-high_ option.
-
-
-
-File: as.info,  Node: M32R-Directives,  Next: M32R-Warnings,  Prev: M32R-Opts,  Up: M32R-Dependent
-
-8.17.2 M32R Directives
-----------------------
-
-The Renease M32R version of `as' has a few architecture specific
-directives:
-
-`low EXPRESSION'
-     The `low' directive computes the value of its expression and
-     places the lower 16-bits of the result into the immediate-field of
-     the instruction.  For example:
-
-             or3   r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
-             add3, r0, r0, #low(fred)   ; compute r0 = r0 + low 16-bits of address of fred
-
-`high EXPRESSION'
-     The `high' directive computes the value of its expression and
-     places the upper 16-bits of the result into the immediate-field of
-     the instruction.  For example:
-
-             seth  r0, #high(0x12345678) ; compute r0 = 0x12340000
-             seth, r0, #high(fred)       ; compute r0 = upper 16-bits of address of fred
-
-`shigh EXPRESSION'
-     The `shigh' directive is very similar to the `high' directive.  It
-     also computes the value of its expression and places the upper
-     16-bits of the result into the immediate-field of the instruction.
-     The difference is that `shigh' also checks to see if the lower
-     16-bits could be interpreted as a signed number, and if so it
-     assumes that a borrow will occur from the upper-16 bits.  To
-     compensate for this the `shigh' directive pre-biases the upper 16
-     bit value by adding one to it.  For example:
-
-     For example:
-
-             seth  r0, #shigh(0x12345678) ; compute r0 = 0x12340000
-             seth  r0, #shigh(0x00008000) ; compute r0 = 0x00010000
-
-     In the second example the lower 16-bits are 0x8000.  If these are
-     treated as a signed value and sign extended to 32-bits then the
-     value becomes 0xffff8000.  If this value is then added to
-     0x00010000 then the result is 0x00008000.
-
-     This behaviour is to allow for the different semantics of the
-     `or3' and `add3' instructions.  The `or3' instruction treats its
-     16-bit immediate argument as unsigned whereas the `add3' treats
-     its 16-bit immediate as a signed value.  So for example:
-
-             seth  r0, #shigh(0x00008000)
-             add3  r0, r0, #low(0x00008000)
-
-     Produces the correct result in r0, whereas:
-
-             seth  r0, #shigh(0x00008000)
-             or3   r0, r0, #low(0x00008000)
-
-     Stores 0xffff8000 into r0.
-
-     Note - the `shigh' directive does not know where in the assembly
-     source code the lower 16-bits of the value are going set, so it
-     cannot check to make sure that an `or3' instruction is being used
-     rather than an `add3' instruction.  It is up to the programmer to
-     make sure that correct directives are used.
-
-`.m32r'
-     The directive performs a similar thing as the _-m32r_ command line
-     option.  It tells the assembler to only accept M32R instructions
-     from now on.  An instructions from later M32R architectures are
-     refused.
-
-`.m32rx'
-     The directive performs a similar thing as the _-m32rx_ command
-     line option.  It tells the assembler to start accepting the extra
-     instructions in the M32RX ISA as well as the ordinary M32R ISA.
-
-`.m32r2'
-     The directive performs a similar thing as the _-m32r2_ command
-     line option.  It tells the assembler to start accepting the extra
-     instructions in the M32R2 ISA as well as the ordinary M32R ISA.
-
-`.little'
-     The directive performs a similar thing as the _-little_ command
-     line option.  It tells the assembler to start producing
-     little-endian code and data.  This option should be used with care
-     as producing mixed-endian binary files is frought with danger.
-
-`.big'
-     The directive performs a similar thing as the _-big_ command line
-     option.  It tells the assembler to start producing big-endian code
-     and data.  This option should be used with care as producing
-     mixed-endian binary files is frought with danger.
-
-
-
-File: as.info,  Node: M32R-Warnings,  Prev: M32R-Directives,  Up: M32R-Dependent
-
-8.17.3 M32R Warnings
---------------------
-
-There are several warning and error messages that can be produced by
-`as' which are specific to the M32R:
-
-`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
-     This message is only produced if warnings for explicit parallel
-     conflicts have been enabled.  It indicates that the assembler has
-     encountered a parallel instruction in which the destination
-     register of the left hand instruction is used as an input register
-     in the right hand instruction.  For example in this code fragment
-     `mv r1, r2 || neg r3, r1' register r1 is the destination of the
-     move instruction and the input to the neg instruction.
-
-`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
-     This message is only produced if warnings for explicit parallel
-     conflicts have been enabled.  It indicates that the assembler has
-     encountered a parallel instruction in which the destination
-     register of the right hand instruction is used as an input
-     register in the left hand instruction.  For example in this code
-     fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
-     of the neg instruction and the input to the move instruction.
-
-`instruction `...' is for the M32RX only'
-     This message is produced when the assembler encounters an
-     instruction which is only supported by the M32Rx processor, and
-     the `-m32rx' command line flag has not been specified to allow
-     assembly of such instructions.
-
-`unknown instruction `...''
-     This message is produced when the assembler encounters an
-     instruction which it does not recognise.
-
-`only the NOP instruction can be issued in parallel on the m32r'
-     This message is produced when the assembler encounters a parallel
-     instruction which does not involve a NOP instruction and the
-     `-m32rx' command line flag has not been specified.  Only the M32Rx
-     processor is able to execute two instructions in parallel.
-
-`instruction `...' cannot be executed in parallel.'
-     This message is produced when the assembler encounters a parallel
-     instruction which is made up of one or two instructions which
-     cannot be executed in parallel.
-
-`Instructions share the same execution pipeline'
-     This message is produced when the assembler encounters a parallel
-     instruction whoes components both use the same execution pipeline.
-
-`Instructions write to the same destination register.'
-     This message is produced when the assembler encounters a parallel
-     instruction where both components attempt to modify the same
-     register.  For example these code fragments will produce this
-     message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
-     @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
-     r3, r4' (Both write to the condition bit)
-
-
-
-File: as.info,  Node: M68K-Dependent,  Next: M68HC11-Dependent,  Prev: M32R-Dependent,  Up: Machine Dependencies
-
-8.18 M680x0 Dependent Features
-==============================
-
-* Menu:
-
-* M68K-Opts::                   M680x0 Options
-* M68K-Syntax::                 Syntax
-* M68K-Moto-Syntax::            Motorola Syntax
-* M68K-Float::                  Floating Point
-* M68K-Directives::             680x0 Machine Directives
-* M68K-opcodes::                Opcodes
-
-
-File: as.info,  Node: M68K-Opts,  Next: M68K-Syntax,  Up: M68K-Dependent
-
-8.18.1 M680x0 Options
----------------------
-
-The Motorola 680x0 version of `as' has a few machine dependent options:
-
-`-march=ARCHITECTURE'
-     This option specifies a target architecture.  The following
-     architectures are recognized: `68000', `68010', `68020', `68030',
-     `68040', `68060', `cpu32', `isaa', `isaaplus', `isab' and `cfv4e'.
-
-`-mcpu=CPU'
-     This option specifies a target cpu.  When used in conjunction with
-     the `-march' option, the cpu must be within the specified
-     architecture.  Also, the generic features of the architecture are
-     used for instruction generation, rather than those of the specific
-     chip.
-
-`-m[no-]68851'
-
-`-m[no-]68881'
-
-`-m[no-]div'
-
-`-m[no-]usp'
-
-`-m[no-]float'
-
-`-m[no-]mac'
-
-`-m[no-]emac'
-     Enable or disable various architecture specific features.  If a
-     chip or architecture by default supports an option (for instance
-     `-march=isaaplus' includes the `-mdiv' option), explicitly
-     disabling the option will override the default.
-
-`-l'
-     You can use the `-l' option to shorten the size of references to
-     undefined symbols.  If you do not use the `-l' option, references
-     to undefined symbols are wide enough for a full `long' (32 bits).
-     (Since `as' cannot know where these symbols end up, `as' can only
-     allocate space for the linker to fill in later.  Since `as' does
-     not know how far away these symbols are, it allocates as much
-     space as it can.)  If you use this option, the references are only
-     one word wide (16 bits).  This may be useful if you want the
-     object file to be as small as possible, and you know that the
-     relevant symbols are always less than 17 bits away.
-
-`--register-prefix-optional'
-     For some configurations, especially those where the compiler
-     normally does not prepend an underscore to the names of user
-     variables, the assembler requires a `%' before any use of a
-     register name.  This is intended to let the assembler distinguish
-     between C variables and functions named `a0' through `a7', and so
-     on.  The `%' is always accepted, but is not required for certain
-     configurations, notably `sun3'.  The `--register-prefix-optional'
-     option may be used to permit omitting the `%' even for
-     configurations for which it is normally required.  If this is
-     done, it will generally be impossible to refer to C variables and
-     functions with the same names as register names.
-
-`--bitwise-or'
-     Normally the character `|' is treated as a comment character, which
-     means that it can not be used in expressions.  The `--bitwise-or'
-     option turns `|' into a normal character.  In this mode, you must
-     either use C style comments, or start comments with a `#' character
-     at the beginning of a line.
-
-`--base-size-default-16  --base-size-default-32'
-     If you use an addressing mode with a base register without
-     specifying the size, `as' will normally use the full 32 bit value.
-     For example, the addressing mode `%a0@(%d0)' is equivalent to
-     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
-     tell `as' to default to using the 16 bit value.  In this case,
-     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
-     `--base-size-default-32' option to restore the default behaviour.
-
-`--disp-size-default-16  --disp-size-default-32'
-     If you use an addressing mode with a displacement, and the value
-     of the displacement is not known, `as' will normally assume that
-     the value is 32 bits.  For example, if the symbol `disp' has not
-     been defined, `as' will assemble the addressing mode
-     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
-     the `--disp-size-default-16' option to tell `as' to instead assume
-     that the displacement is 16 bits.  In this case, `as' will
-     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
-     may use the `--disp-size-default-32' option to restore the default
-     behaviour.
-
-`--pcrel'
-     Always keep branches PC-relative.  In the M680x0 architecture all
-     branches are defined as PC-relative.  However, on some processors
-     they are limited to word displacements maximum.  When `as' needs a
-     long branch that is not available, it normally emits an absolute
-     jump instead.  This option disables this substitution.  When this
-     option is given and no long branches are available, only word
-     branches will be emitted.  An error message will be generated if a
-     word branch cannot reach its target.  This option has no effect on
-     68020 and other processors that have long branches.  *note Branch
-     Improvement: M68K-Branch.
-
-`-m68000'
-     `as' can assemble code for several different members of the
-     Motorola 680x0 family.  The default depends upon how `as' was
-     configured when it was built; normally, the default is to assemble
-     code for the 68020 microprocessor.  The following options may be
-     used to change the default.  These options control which
-     instructions and addressing modes are permitted.  The members of
-     the 680x0 family are very similar.  For detailed information about
-     the differences, see the Motorola manuals.
-
-    `-m68000'
-    `-m68ec000'
-    `-m68hc000'
-    `-m68hc001'
-    `-m68008'
-    `-m68302'
-    `-m68306'
-    `-m68307'
-    `-m68322'
-    `-m68356'
-          Assemble for the 68000. `-m68008', `-m68302', and so on are
-          synonyms for `-m68000', since the chips are the same from the
-          point of view of the assembler.
-
-    `-m68010'
-          Assemble for the 68010.
-
-    `-m68020'
-    `-m68ec020'
-          Assemble for the 68020.  This is normally the default.
-
-    `-m68030'
-    `-m68ec030'
-          Assemble for the 68030.
-
-    `-m68040'
-    `-m68ec040'
-          Assemble for the 68040.
-
-    `-m68060'
-    `-m68ec060'
-          Assemble for the 68060.
-
-    `-mcpu32'
-    `-m68330'
-    `-m68331'
-    `-m68332'
-    `-m68333'
-    `-m68334'
-    `-m68336'
-    `-m68340'
-    `-m68341'
-    `-m68349'
-    `-m68360'
-          Assemble for the CPU32 family of chips.
-
-    `-m5200'
-
-    `-m5202'
-
-    `-m5204'
-
-    `-m5206'
-
-    `-m5206e'
-
-    `-m521x'
-
-    `-m5249'
-
-    `-m528x'
-
-    `-m5307'
-
-    `-m5407'
-
-    `-m547x'
-
-    `-m548x'
-
-    `-mcfv4'
-
-    `-mcfv4e'
-          Assemble for the ColdFire family of chips.
-
-    `-m68881'
-    `-m68882'
-          Assemble 68881 floating point instructions.  This is the
-          default for the 68020, 68030, and the CPU32.  The 68040 and
-          68060 always support floating point instructions.
-
-    `-mno-68881'
-          Do not assemble 68881 floating point instructions.  This is
-          the default for 68000 and the 68010.  The 68040 and 68060
-          always support floating point instructions, even if this
-          option is used.
-
-    `-m68851'
-          Assemble 68851 MMU instructions.  This is the default for the
-          68020, 68030, and 68060.  The 68040 accepts a somewhat
-          different set of MMU instructions; `-m68851' and `-m68040'
-          should not be used together.
-
-    `-mno-68851'
-          Do not assemble 68851 MMU instructions.  This is the default
-          for the 68000, 68010, and the CPU32.  The 68040 accepts a
-          somewhat different set of MMU instructions.
-
-
-File: as.info,  Node: M68K-Syntax,  Next: M68K-Moto-Syntax,  Prev: M68K-Opts,  Up: M68K-Dependent
-
-8.18.2 Syntax
--------------
-
-This syntax for the Motorola 680x0 was developed at MIT.
-
-   The 680x0 version of `as' uses instructions names and syntax
-compatible with the Sun assembler.  Intervening periods are ignored;
-for example, `movl' is equivalent to `mov.l'.
-
-   In the following table APC stands for any of the address registers
-(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
-relative to the program counter (`%zpc'), a suppressed address register
-(`%za0' through `%za7'), or it may be omitted entirely.  The use of
-SIZE means one of `w' or `l', and it may be omitted, along with the
-leading colon, unless a scale is also specified.  The use of SCALE
-means one of `1', `2', `4', or `8', and it may always be omitted along
-with the leading colon.
-
-   The following addressing modes are understood:
-"Immediate"
-     `#NUMBER'
-
-"Data Register"
-     `%d0' through `%d7'
-
-"Address Register"
-     `%a0' through `%a7'
-     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
-     also known as `%fp', the Frame Pointer.
-
-"Address Register Indirect"
-     `%a0@' through `%a7@'
-
-"Address Register Postincrement"
-     `%a0@+' through `%a7@+'
-
-"Address Register Predecrement"
-     `%a0@-' through `%a7@-'
-
-"Indirect Plus Offset"
-     `APC@(NUMBER)'
-
-"Index"
-     `APC@(NUMBER,REGISTER:SIZE:SCALE)'
-
-     The NUMBER may be omitted.
-
-"Postindex"
-     `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
-
-     The ONUMBER or the REGISTER, but not both, may be omitted.
-
-"Preindex"
-     `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
-
-     The NUMBER may be omitted.  Omitting the REGISTER produces the
-     Postindex addressing mode.
-
-"Absolute"
-     `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.
-
-
-File: as.info,  Node: M68K-Moto-Syntax,  Next: M68K-Float,  Prev: M68K-Syntax,  Up: M68K-Dependent
-
-8.18.3 Motorola Syntax
-----------------------
-
-The standard Motorola syntax for this chip differs from the syntax
-already discussed (*note Syntax: M68K-Syntax.).  `as' can accept
-Motorola syntax for operands, even if MIT syntax is used for other
-operands in the same instruction.  The two kinds of syntax are fully
-compatible.
-
-   In the following table APC stands for any of the address registers
-(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
-relative to the program counter (`%zpc'), or a suppressed address
-register (`%za0' through `%za7').  The use of SIZE means one of `w' or
-`l', and it may always be omitted along with the leading dot.  The use
-of SCALE means one of `1', `2', `4', or `8', and it may always be
-omitted along with the leading asterisk.
-
-   The following additional addressing modes are understood:
-
-"Address Register Indirect"
-     `(%a0)' through `(%a7)'
-     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
-     also known as `%fp', the Frame Pointer.
-
-"Address Register Postincrement"
-     `(%a0)+' through `(%a7)+'
-
-"Address Register Predecrement"
-     `-(%a0)' through `-(%a7)'
-
-"Indirect Plus Offset"
-     `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
-
-     The NUMBER may also appear within the parentheses, as in
-     `(NUMBER,%A0)'.  When used with the PC, the NUMBER may be omitted
-     (with an address register, omitting the NUMBER produces Address
-     Register Indirect mode).
-
-"Index"
-     `NUMBER(APC,REGISTER.SIZE*SCALE)'
-
-     The NUMBER may be omitted, or it may appear within the
-     parentheses.  The APC may be omitted.  The REGISTER and the APC
-     may appear in either order.  If both APC and REGISTER are address
-     registers, and the SIZE and SCALE are omitted, then the first
-     register is taken as the base register, and the second as the
-     index register.
-
-"Postindex"
-     `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
-
-     The ONUMBER, or the REGISTER, or both, may be omitted.  Either the
-     NUMBER or the APC may be omitted, but not both.
-
-"Preindex"
-     `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
-
-     The NUMBER, or the APC, or the REGISTER, or any two of them, may
-     be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC
-     may appear in either order.  If both APC and REGISTER are address
-     registers, and the SIZE and SCALE are omitted, then the first
-     register is taken as the base register, and the second as the
-     index register.
-
-
-File: as.info,  Node: M68K-Float,  Next: M68K-Directives,  Prev: M68K-Moto-Syntax,  Up: M68K-Dependent
-
-8.18.4 Floating Point
----------------------
-
-Packed decimal (P) format floating literals are not supported.  Feel
-free to add the code!
-
-   The floating point formats generated by directives are these.
-
-`.float'
-     `Single' precision floating point constants.
-
-`.double'
-     `Double' precision floating point constants.
-
-`.extend'
-`.ldouble'
-     `Extended' precision (`long double') floating point constants.
-
-
-File: as.info,  Node: M68K-Directives,  Next: M68K-opcodes,  Prev: M68K-Float,  Up: M68K-Dependent
-
-8.18.5 680x0 Machine Directives
--------------------------------
-
-In order to be compatible with the Sun assembler the 680x0 assembler
-understands the following directives.
-
-`.data1'
-     This directive is identical to a `.data 1' directive.
-
-`.data2'
-     This directive is identical to a `.data 2' directive.
-
-`.even'
-     This directive is a special case of the `.align' directive; it
-     aligns the output to an even byte boundary.
-
-`.skip'
-     This directive is identical to a `.space' directive.
-
-`.arch NAME'
-     Select the target architecture and extension features.  Valid
-     valuse for NAME are the same as for the `-march' command line
-     option.  This directive cannot be specified after any instructions
-     have been assembled.  If it is given multiple times, or in
-     conjuction with the `-march' option, all uses must be for the same
-     architecture and extension set.
-
-`.cpu NAME'
-     Select the target cpu.  Valid valuse for NAME are the same as for
-     the `-mcpu' command line option.  This directive cannot be
-     specified after any instructions have been assembled.  If it is
-     given multiple times, or in conjuction with the `-mopt' option,
-     all uses must be for the same cpu.
-
-
-
-File: as.info,  Node: M68K-opcodes,  Prev: M68K-Directives,  Up: M68K-Dependent
-
-8.18.6 Opcodes
---------------
-
-* Menu:
-
-* M68K-Branch::                 Branch Improvement
-* M68K-Chars::                  Special Characters
-
-
-File: as.info,  Node: M68K-Branch,  Next: M68K-Chars,  Up: M68K-opcodes
-
-8.18.6.1 Branch Improvement
-...........................
-
-Certain pseudo opcodes are permitted for branch instructions.  They
-expand to the shortest branch instruction that reach the target.
-Generally these mnemonics are made by substituting `j' for `b' at the
-start of a Motorola mnemonic.
-
-   The following table summarizes the pseudo-operations.  A `*' flags
-cases that are more fully described after the table:
-
-               Displacement
-               +------------------------------------------------------------
-               |                68020           68000/10, not PC-relative OK
-     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
-               +------------------------------------------------------------
-          jbsr |bsrs    bsrw    bsrl            jsr
-           jra |bras    braw    bral            jmp
-     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
-     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
-          fjXX | N/A    fbXXw   fbXXl            N/A
-
-     XX: condition
-     NX: negative of condition XX
-                       `*'--see full description below
-         `**'--this expansion mode is disallowed by `--pcrel'
-
-`jbsr'
-`jra'
-     These are the simplest jump pseudo-operations; they always map to
-     one particular machine instruction, depending on the displacement
-     to the branch target.  This instruction will be a byte or word
-     branch is that is sufficient.  Otherwise, a long branch will be
-     emitted if available.  If no long branches are available and the
-     `--pcrel' option is not given, an absolute long jump will be
-     emitted instead.  If no long branches are available, the `--pcrel'
-     option is given, and a word branch cannot reach the target, an
-     error message is generated.
-
-     In addition to standard branch operands, `as' allows these
-     pseudo-operations to have all operands that are allowed for jsr
-     and jmp, substituting these instructions if the operand given is
-     not valid for a branch instruction.
-
-`jXX'
-     Here, `jXX' stands for an entire family of pseudo-operations,
-     where XX is a conditional branch or condition-code test.  The full
-     list of pseudo-ops in this family is:
-           jhi   jls   jcc   jcs   jne   jeq   jvc
-           jvs   jpl   jmi   jge   jlt   jgt   jle
-
-     Usually, each of these pseudo-operations expands to a single branch
-     instruction.  However, if a word branch is not sufficient, no long
-     branches are available, and the `--pcrel' option is not given, `as'
-     issues a longer code fragment in terms of NX, the opposite
-     condition to XX.  For example, under these conditions:
-              jXX foo
-     gives
-               bNXs oof
-               jmp foo
-           oof:
-
-`dbXX'
-     The full family of pseudo-operations covered here is
-           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
-           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
-           dbf    dbra   dbt
-
-     Motorola `dbXX' instructions allow word displacements only.  When
-     a word displacement is sufficient, each of these pseudo-operations
-     expands to the corresponding Motorola instruction.  When a word
-     displacement is not sufficient and long branches are available,
-     when the source reads `dbXX foo', `as' emits
-               dbXX oo1
-               bras oo2
-           oo1:bral foo
-           oo2:
-
-     If, however, long branches are not available and the `--pcrel'
-     option is not given, `as' emits
-               dbXX oo1
-               bras oo2
-           oo1:jmp foo
-           oo2:
-
-`fjXX'
-     This family includes
-           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
-           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
-           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
-           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
-           fjugt  fjule  fjult  fjun
-
-     Each of these pseudo-operations always expands to a single Motorola
-     coprocessor branch instruction, word or long.  All Motorola
-     coprocessor branch instructions allow both word and long
-     displacements.
-
-
-
-File: as.info,  Node: M68K-Chars,  Prev: M68K-Branch,  Up: M68K-opcodes
-
-8.18.6.2 Special Characters
-...........................
-
-The immediate character is `#' for Sun compatibility.  The line-comment
-character is `|' (unless the `--bitwise-or' option is used).  If a `#'
-appears at the beginning of a line, it is treated as a comment unless
-it looks like `# line file', in which case it is treated normally.
-
-
-File: as.info,  Node: M68HC11-Dependent,  Next: MIPS-Dependent,  Prev: M68K-Dependent,  Up: Machine Dependencies
-
-8.19 M68HC11 and M68HC12 Dependent Features
-===========================================
-
-* Menu:
-
-* M68HC11-Opts::                   M68HC11 and M68HC12 Options
-* M68HC11-Syntax::                 Syntax
-* M68HC11-Modifiers::              Symbolic Operand Modifiers
-* M68HC11-Directives::             Assembler Directives
-* M68HC11-Float::                  Floating Point
-* M68HC11-opcodes::                Opcodes
-
-
-File: as.info,  Node: M68HC11-Opts,  Next: M68HC11-Syntax,  Up: M68HC11-Dependent
-
-8.19.1 M68HC11 and M68HC12 Options
-----------------------------------
-
-The Motorola 68HC11 and 68HC12 version of `as' have a few machine
-dependent options.
-
-`-m68hc11'
-     This option switches the assembler in the M68HC11 mode. In this
-     mode, the assembler only accepts 68HC11 operands and mnemonics. It
-     produces code for the 68HC11.
-
-`-m68hc12'
-     This option switches the assembler in the M68HC12 mode. In this
-     mode, the assembler also accepts 68HC12 operands and mnemonics. It
-     produces code for the 68HC12. A few 68HC11 instructions are
-     replaced by some 68HC12 instructions as recommended by Motorola
-     specifications.
-
-`-m68hcs12'
-     This option switches the assembler in the M68HCS12 mode.  This
-     mode is similar to `-m68hc12' but specifies to assemble for the
-     68HCS12 series.  The only difference is on the assembling of the
-     `movb' and `movw' instruction when a PC-relative operand is used.
-
-`-mshort'
-     This option controls the ABI and indicates to use a 16-bit integer
-     ABI.  It has no effect on the assembled instructions.  This is the
-     default.
-
-`-mlong'
-     This option controls the ABI and indicates to use a 32-bit integer
-     ABI.
-
-`-mshort-double'
-     This option controls the ABI and indicates to use a 32-bit float
-     ABI.  This is the default.
-
-`-mlong-double'
-     This option controls the ABI and indicates to use a 64-bit float
-     ABI.
-
-`--strict-direct-mode'
-     You can use the `--strict-direct-mode' option to disable the
-     automatic translation of direct page mode addressing into extended
-     mode when the instruction does not support direct mode.  For
-     example, the `clr' instruction does not support direct page mode
-     addressing. When it is used with the direct page mode, `as' will
-     ignore it and generate an absolute addressing.  This option
-     prevents `as' from doing this, and the wrong usage of the direct
-     page mode will raise an error.
-
-`--short-branchs'
-     The `--short-branchs' option turns off the translation of relative
-     branches into absolute branches when the branch offset is out of
-     range. By default `as' transforms the relative branch (`bsr',
-     `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls',
-     `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when
-     the offset is out of the -128 .. 127 range.  In that case, the
-     `bsr' instruction is translated into a `jsr', the `bra'
-     instruction is translated into a `jmp' and the conditional branchs
-     instructions are inverted and followed by a `jmp'. This option
-     disables these translations and `as' will generate an error if a
-     relative branch is out of range. This option does not affect the
-     optimization associated to the `jbra', `jbsr' and `jbXX' pseudo
-     opcodes.
-
-`--force-long-branchs'
-     The `--force-long-branchs' option forces the translation of
-     relative branches into absolute branches. This option does not
-     affect the optimization associated to the `jbra', `jbsr' and
-     `jbXX' pseudo opcodes.
-
-`--print-insn-syntax'
-     You can use the `--print-insn-syntax' option to obtain the syntax
-     description of the instruction when an error is detected.
-
-`--print-opcodes'
-     The `--print-opcodes' option prints the list of all the
-     instructions with their syntax. The first item of each line
-     represents the instruction name and the rest of the line indicates
-     the possible operands for that instruction. The list is printed in
-     alphabetical order. Once the list is printed `as' exits.
-
-`--generate-example'
-     The `--generate-example' option is similar to `--print-opcodes'
-     but it generates an example for each instruction instead.
-
-
-File: as.info,  Node: M68HC11-Syntax,  Next: M68HC11-Modifiers,  Prev: M68HC11-Opts,  Up: M68HC11-Dependent
-
-8.19.2 Syntax
--------------
-
-In the M68HC11 syntax, the instruction name comes first and it may be
-followed by one or several operands (up to three). Operands are
-separated by comma (`,'). In the normal mode, `as' will complain if too
-many operands are specified for a given instruction. In the MRI mode
-(turned on with `-M' option), it will treat them as comments. Example:
-
-     inx
-     lda  #23
-     bset 2,x #4
-     brclr *bot #8 foo
-
-   The following addressing modes are understood for 68HC11 and 68HC12:
-"Immediate"
-     `#NUMBER'
-
-"Address Register"
-     `NUMBER,X', `NUMBER,Y'
-
-     The NUMBER may be omitted in which case 0 is assumed.
-
-"Direct Addressing mode"
-     `*SYMBOL', or `*DIGITS'
-
-"Absolute"
-     `SYMBOL', or `DIGITS'
-
-   The M68HC12 has other more complex addressing modes. All of them are
-supported and they are represented below:
-
-"Constant Offset Indexed Addressing Mode"
-     `NUMBER,REG'
-
-     The NUMBER may be omitted in which case 0 is assumed.  The
-     register can be either `X', `Y', `SP' or `PC'.  The assembler will
-     use the smaller post-byte definition according to the constant
-     value (5-bit constant offset, 9-bit constant offset or 16-bit
-     constant offset).  If the constant is not known by the assembler
-     it will use the 16-bit constant offset post-byte and the value
-     will be resolved at link time.
-
-"Offset Indexed Indirect"
-     `[NUMBER,REG]'
-
-     The register can be either `X', `Y', `SP' or `PC'.
-
-"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
-     `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+'
-
-     The number must be in the range `-8'..`+8' and must not be 0.  The
-     register can be either `X', `Y', `SP' or `PC'.
-
-"Accumulator Offset"
-     `ACC,REG'
-
-     The accumulator register can be either `A', `B' or `D'.  The
-     register can be either `X', `Y', `SP' or `PC'.
-
-"Accumulator D offset indexed-indirect"
-     `[D,REG]'
-
-     The register can be either `X', `Y', `SP' or `PC'.
-
-
-   For example:
-
-     ldab 1024,sp
-     ldd [10,x]
-     orab 3,+x
-     stab -2,y-
-     ldx a,pc
-     sty [d,sp]
-
-
-File: as.info,  Node: M68HC11-Modifiers,  Next: M68HC11-Directives,  Prev: M68HC11-Syntax,  Up: M68HC11-Dependent
-
-8.19.3 Symbolic Operand Modifiers
----------------------------------
-
-The assembler supports several modifiers when using symbol addresses in
-68HC11 and 68HC12 instruction operands.  The general syntax is the
-following:
-
-     %modifier(symbol)
-
-`%addr'
-     This modifier indicates to the assembler and linker to use the
-     16-bit physical address corresponding to the symbol.  This is
-     intended to be used on memory window systems to map a symbol in
-     the memory bank window.  If the symbol is in a memory expansion
-     part, the physical address corresponds to the symbol address
-     within the memory bank window.  If the symbol is not in a memory
-     expansion part, this is the symbol address (using or not using the
-     %addr modifier has no effect in that case).
-
-`%page'
-     This modifier indicates to use the memory page number corresponding
-     to the symbol.  If the symbol is in a memory expansion part, its
-     page number is computed by the linker as a number used to map the
-     page containing the symbol in the memory bank window.  If the
-     symbol is not in a memory expansion part, the page number is 0.
-
-`%hi'
-     This modifier indicates to use the 8-bit high part of the physical
-     address of the symbol.
-
-`%lo'
-     This modifier indicates to use the 8-bit low part of the physical
-     address of the symbol.
-
-
-   For example a 68HC12 call to a function `foo_example' stored in
-memory expansion part could be written as follows:
-
-     call %addr(foo_example),%page(foo_example)
-
-   and this is equivalent to
-
-     call foo_example
-
-   And for 68HC11 it could be written as follows:
-
-     ldab #%page(foo_example)
-     stab _page_switch
-     jsr  %addr(foo_example)
-
-
-File: as.info,  Node: M68HC11-Directives,  Next: M68HC11-Float,  Prev: M68HC11-Modifiers,  Up: M68HC11-Dependent
-
-8.19.4 Assembler Directives
----------------------------
-
-The 68HC11 and 68HC12 version of `as' have the following specific
-assembler directives:
-
-`.relax'
-     The relax directive is used by the `GNU Compiler' to emit a
-     specific relocation to mark a group of instructions for linker
-     relaxation.  The sequence of instructions within the group must be
-     known to the linker so that relaxation can be performed.
-
-`.mode [mshort|mlong|mshort-double|mlong-double]'
-     This directive specifies the ABI.  It overrides the `-mshort',
-     `-mlong', `-mshort-double' and `-mlong-double' options.
-
-`.far SYMBOL'
-     This directive marks the symbol as a `far' symbol meaning that it
-     uses a `call/rtc' calling convention as opposed to `jsr/rts'.
-     During a final link, the linker will identify references to the
-     `far' symbol and will verify the proper calling convention.
-
-`.interrupt SYMBOL'
-     This directive marks the symbol as an interrupt entry point.  This
-     information is then used by the debugger to correctly unwind the
-     frame across interrupts.
-
-`.xrefb SYMBOL'
-     This directive is defined for compatibility with the
-     `Specification for Motorola 8 and 16-Bit Assembly Language Input
-     Standard' and is ignored.
-
-
-
-File: as.info,  Node: M68HC11-Float,  Next: M68HC11-opcodes,  Prev: M68HC11-Directives,  Up: M68HC11-Dependent
-
-8.19.5 Floating Point
----------------------
-
-Packed decimal (P) format floating literals are not supported.  Feel
-free to add the code!
-
-   The floating point formats generated by directives are these.
-
-`.float'
-     `Single' precision floating point constants.
-
-`.double'
-     `Double' precision floating point constants.
-
-`.extend'
-`.ldouble'
-     `Extended' precision (`long double') floating point constants.
-
-
-File: as.info,  Node: M68HC11-opcodes,  Prev: M68HC11-Float,  Up: M68HC11-Dependent
-
-8.19.6 Opcodes
---------------
-
-* Menu:
-
-* M68HC11-Branch::                 Branch Improvement
-
-
-File: as.info,  Node: M68HC11-Branch,  Up: M68HC11-opcodes
-
-8.19.6.1 Branch Improvement
-...........................
-
-Certain pseudo opcodes are permitted for branch instructions.  They
-expand to the shortest branch instruction that reach the target.
-Generally these mnemonics are made by prepending `j' to the start of
-Motorola mnemonic. These pseudo opcodes are not affected by the
-`--short-branchs' or `--force-long-branchs' options.
-
-   The following table summarizes the pseudo-operations.
-
-                             Displacement Width
-          +-------------------------------------------------------------+
-          |                     Options                                 |
-          |    --short-branchs            --force-long-branchs          |
-          +--------------------------+----------------------------------+
-       Op |BYTE             WORD     | BYTE          WORD               |
-          +--------------------------+----------------------------------+
-      bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
-      bra | bra <pc-rel>    <error>  |               jmp <abs>          |
-     jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
-     jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
-      bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
-     jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
-          |                jmp <abs> |                                  |
-          +--------------------------+----------------------------------+
-     XX: condition
-     NX: negative of condition XX
-
-`jbsr'
-`jbra'
-     These are the simplest jump pseudo-operations; they always map to
-     one particular machine instruction, depending on the displacement
-     to the branch target.
-
-`jbXX'
-     Here, `jbXX' stands for an entire family of pseudo-operations,
-     where XX is a conditional branch or condition-code test.  The full
-     list of pseudo-ops in this family is:
-           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
-           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi
-
-     For the cases of non-PC relative displacements and long
-     displacements, `as' issues a longer code fragment in terms of NX,
-     the opposite condition to XX.  For example, for the non-PC
-     relative case:
-              jbXX foo
-     gives
-               bNXs oof
-               jmp foo
-           oof:
-
-
-
-File: as.info,  Node: MIPS-Dependent,  Next: MMIX-Dependent,  Prev: M68HC11-Dependent,  Up: Machine Dependencies
-
-8.20 MIPS Dependent Features
-============================
-
-   GNU `as' for MIPS architectures supports several different MIPS
-processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For
-information about the MIPS instruction set, see `MIPS RISC
-Architecture', by Kane and Heindrich (Prentice-Hall).  For an overview
-of MIPS assembly conventions, see "Appendix D: Assembly Language
-Programming" in the same work.
-
-* Menu:
-
-* MIPS Opts::   	Assembler options
-* MIPS Object:: 	ECOFF object code
-* MIPS Stabs::  	Directives for debugging information
-* MIPS ISA::    	Directives to override the ISA level
-* MIPS symbol sizes::   Directives to override the size of symbols
-* MIPS autoextend::	Directives for extending MIPS 16 bit instructions
-* MIPS insn::		Directive to mark data as an instruction
-* MIPS option stack::	Directives to save and restore options
-* MIPS ASE instruction generation overrides:: Directives to control
-  			generation of MIPS ASE instructions
-
-
-File: as.info,  Node: MIPS Opts,  Next: MIPS Object,  Up: MIPS-Dependent
-
-8.20.1 Assembler options
-------------------------
-
-The MIPS configurations of GNU `as' support these special options:
-
-`-G NUM'
-     This option sets the largest size of an object that can be
-     referenced implicitly with the `gp' register.  It is only accepted
-     for targets that use ECOFF format.  The default value is 8.
-
-`-EB'
-`-EL'
-     Any MIPS configuration of `as' can select big-endian or
-     little-endian output at run time (unlike the other GNU development
-     tools, which must be configured for one or the other).  Use `-EB'
-     to select big-endian output, and `-EL' for little-endian.
-
-`-mips1'
-`-mips2'
-`-mips3'
-`-mips4'
-`-mips5'
-`-mips32'
-`-mips32r2'
-`-mips64'
-`-mips64r2'
-     Generate code for a particular MIPS Instruction Set Architecture
-     level.  `-mips1' corresponds to the R2000 and R3000 processors,
-     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
-     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
-     `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to
-     generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64
-     RELEASE 2 ISA processors, respectively.  You can also switch
-     instruction sets during the assembly; see *Note Directives to
-     override the ISA level: MIPS ISA.
-
-`-mgp32'
-`-mfp32'
-     Some macros have different expansions for 32-bit and 64-bit
-     registers.  The register sizes are normally inferred from the ISA
-     and ABI, but these flags force a certain group of registers to be
-     treated as 32 bits wide at all times.  `-mgp32' controls the size
-     of general-purpose registers and `-mfp32' controls the size of
-     floating-point registers.
-
-     On some MIPS variants there is a 32-bit mode flag; when this flag
-     is set, 64-bit instructions generate a trap.  Also, some 32-bit
-     OSes only save the 32-bit registers on a context switch, so it is
-     essential never to use the 64-bit registers.
-
-`-mgp64'
-     Assume that 64-bit general purpose registers are available.  This
-     is provided in the interests of symmetry with -gp32.
-
-`-mips16'
-`-no-mips16'
-     Generate code for the MIPS 16 processor.  This is equivalent to
-     putting `.set mips16' at the start of the assembly file.
-     `-no-mips16' turns off this option.
-
-`-mips3d'
-`-no-mips3d'
-     Generate code for the MIPS-3D Application Specific Extension.
-     This tells the assembler to accept MIPS-3D instructions.
-     `-no-mips3d' turns off this option.
-
-`-mdmx'
-`-no-mdmx'
-     Generate code for the MDMX Application Specific Extension.  This
-     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
-     off this option.
-
-`-mdsp'
-`-mno-dsp'
-     Generate code for the DSP Application Specific Extension.  This
-     tells the assembler to accept DSP instructions.  `-mno-dsp' turns
-     off this option.
-
-`-mmt'
-`-mno-mt'
-     Generate code for the MT Application Specific Extension.  This
-     tells the assembler to accept MT instructions.  `-mno-mt' turns
-     off this option.
-
-`-mfix7000'
-`-mno-fix7000'
-     Cause nops to be inserted if the read of the destination register
-     of an mfhi or mflo instruction occurs in the following two
-     instructions.
-
-`-mfix-vr4120'
-`-no-mfix-vr4120'
-     Insert nops to work around certain VR4120 errata.  This option is
-     intended to be used on GCC-generated code: it is not designed to
-     catch all problems in hand-written assembler code.
-
-`-mfix-vr4130'
-`-no-mfix-vr4130'
-     Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
-
-`-m4010'
-`-no-m4010'
-     Generate code for the LSI R4010 chip.  This tells the assembler to
-     accept the R4010 specific instructions (`addciu', `ffc', etc.),
-     and to not schedule `nop' instructions around accesses to the `HI'
-     and `LO' registers.  `-no-m4010' turns off this option.
-
-`-m4650'
-`-no-m4650'
-     Generate code for the MIPS R4650 chip.  This tells the assembler
-     to accept the `mad' and `madu' instruction, and to not schedule
-     `nop' instructions around accesses to the `HI' and `LO' registers.
-     `-no-m4650' turns off this option.
-
-`-m3900'
-`-no-m3900'
-`-m4100'
-`-no-m4100'
-     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
-     This tells the assembler to accept instructions specific to that
-     chip, and to schedule for that chip's hazards.
-
-`-march=CPU'
-     Generate code for a particular MIPS cpu.  It is exactly equivalent
-     to `-mCPU', except that there are more value of CPU understood.
-     Valid CPU value are:
-
-          2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
-          vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
-          rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
-          10000, 12000, mips32-4k, sb1
-
-`-mtune=CPU'
-     Schedule and tune for a particular MIPS cpu.  Valid CPU values are
-     identical to `-march=CPU'.
-
-`-mabi=ABI'
-     Record which ABI the source code uses.  The recognized arguments
-     are: `32', `n32', `o64', `64' and `eabi'.
-
-`-msym32'
-`-mno-sym32'
-     Equivalent to adding `.set sym32' or `.set nosym32' to the
-     beginning of the assembler input.  *Note MIPS symbol sizes::.
-
-`-nocpp'
-     This option is ignored.  It is accepted for command-line
-     compatibility with other assemblers, which use it to turn off C
-     style preprocessing.  With GNU `as', there is no need for
-     `-nocpp', because the GNU assembler itself never runs the C
-     preprocessor.
-
-`--construct-floats'
-`--no-construct-floats'
-     The `--no-construct-floats' option disables the construction of
-     double width floating point constants by loading the two halves of
-     the value into the two single width floating point registers that
-     make up the double width register.  This feature is useful if the
-     processor support the FR bit in its status  register, and this bit
-     is known (by the programmer) to be set.  This bit prevents the
-     aliasing of the double width register by the single width
-     registers.
-
-     By default `--construct-floats' is selected, allowing construction
-     of these floating point constants.
-
-`--trap'
-`--no-break'
-     `as' automatically macro expands certain division and
-     multiplication instructions to check for overflow and division by
-     zero.  This option causes `as' to generate code to take a trap
-     exception rather than a break exception when an error is detected.
-     The trap instructions are only supported at Instruction Set
-     Architecture level 2 and higher.
-
-`--break'
-`--no-trap'
-     Generate code to take a break exception rather than a trap
-     exception when an error is detected.  This is the default.
-
-`-mpdr'
-`-mno-pdr'
-     Control generation of `.pdr' sections.  Off by default on IRIX, on
-     elsewhere.
-
-`-mshared'
-`-mno-shared'
-     When generating code using the Unix calling conventions (selected
-     by `-KPIC' or `-mcall_shared'), gas will normally generate code
-     which can go into a shared library.  The `-mno-shared' option
-     tells gas to generate code which uses the calling convention, but
-     can not go into a shared library.  The resulting code is slightly
-     more efficient.  This option only affects the handling of the
-     `.cpload' and `.cpsetup' pseudo-ops.
-
-
-File: as.info,  Node: MIPS Object,  Next: MIPS Stabs,  Prev: MIPS Opts,  Up: MIPS-Dependent
-
-8.20.2 MIPS ECOFF object code
------------------------------
-
-Assembling for a MIPS ECOFF target supports some additional sections
-besides the usual `.text', `.data' and `.bss'.  The additional sections
-are `.rdata', used for read-only data, `.sdata', used for small data,
-and `.sbss', used for small common objects.
-
-   When assembling for ECOFF, the assembler uses the `$gp' (`$28')
-register to form the address of a "small object".  Any object in the
-`.sdata' or `.sbss' sections is considered "small" in this sense.  For
-external objects, or for objects in the `.bss' section, you can use the
-`gcc' `-G' option to control the size of objects addressed via `$gp';
-the default value is 8, meaning that a reference to any object eight
-bytes or smaller uses `$gp'.  Passing `-G 0' to `as' prevents it from
-using the `$gp' register on the basis of object size (but the assembler
-uses `$gp' for objects in `.sdata' or `sbss' in any case).  The size of
-an object in the `.bss' section is set by the `.comm' or `.lcomm'
-directive that defines it.  The size of an external object may be set
-with the `.extern' directive.  For example, `.extern sym,4' declares
-that the object at `sym' is 4 bytes in length, whie leaving `sym'
-otherwise undefined.
-
-   Using small ECOFF objects requires linker support, and assumes that
-the `$gp' register is correctly initialized (normally done
-automatically by the startup code).  MIPS ECOFF assembly code must not
-modify the `$gp' register.
-
-
-File: as.info,  Node: MIPS Stabs,  Next: MIPS ISA,  Prev: MIPS Object,  Up: MIPS-Dependent
-
-8.20.3 Directives for debugging information
--------------------------------------------
-
-MIPS ECOFF `as' supports several directives used for generating
-debugging information which are not support by traditional MIPS
-assemblers.  These are `.def', `.endef', `.dim', `.file', `.scl',
-`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
-The debugging information generated by the three `.stab' directives can
-only be read by GDB, not by traditional MIPS debuggers (this
-enhancement is required to fully support C++ debugging).  These
-directives are primarily used by compilers, not assembly language
-programmers!
-
-
-File: as.info,  Node: MIPS symbol sizes,  Next: MIPS autoextend,  Prev: MIPS ISA,  Up: MIPS-Dependent
-
-8.20.4 Directives to override the size of symbols
--------------------------------------------------
-
-The n64 ABI allows symbols to have any 64-bit value.  Although this
-provides a great deal of flexibility, it means that some macros have
-much longer expansions than their 32-bit counterparts.  For example,
-the non-PIC expansion of `dla $4,sym' is usually:
-
-     lui     $4,%highest(sym)
-     lui     $1,%hi(sym)
-     daddiu  $4,$4,%higher(sym)
-     daddiu  $1,$1,%lo(sym)
-     dsll32  $4,$4,0
-     daddu   $4,$4,$1
-
-   whereas the 32-bit expansion is simply:
-
-     lui     $4,%hi(sym)
-     daddiu  $4,$4,%lo(sym)
-
-   n64 code is sometimes constructed in such a way that all symbolic
-constants are known to have 32-bit values, and in such cases, it's
-preferable to use the 32-bit expansion instead of the 64-bit expansion.
-
-   You can use the `.set sym32' directive to tell the assembler that,
-from this point on, all expressions of the form `SYMBOL' or `SYMBOL +
-OFFSET' have 32-bit values.  For example:
-
-     .set sym32
-     dla     $4,sym
-     lw      $4,sym+16
-     sw      $4,sym+0x8000($4)
-
-   will cause the assembler to treat `sym', `sym+16' and `sym+0x8000'
-as 32-bit values.  The handling of non-symbolic addresses is not
-affected.
-
-   The directive `.set nosym32' ends a `.set sym32' block and reverts
-to the normal behavior.  It is also possible to change the symbol size
-using the command-line options `-msym32' and `-mno-sym32'.
-
-   These options and directives are always accepted, but at present,
-they have no effect for anything other than n64.
-
-
-File: as.info,  Node: MIPS ISA,  Next: MIPS symbol sizes,  Prev: MIPS Stabs,  Up: MIPS-Dependent
-
-8.20.5 Directives to override the ISA level
--------------------------------------------
-
-GNU `as' supports an additional directive to change the MIPS
-Instruction Set Architecture level on the fly: `.set mipsN'.  N should
-be a number from 0 to 5, or 32, 32r2, 64 or 64r2.  The values other
-than 0 make the assembler accept instructions for the corresponding ISA
-level, from that point on in the assembly.  `.set mipsN' affects not
-only which instructions are permitted, but also how certain macros are
-expanded.  `.set mips0' restores the ISA level to its original level:
-either the level you selected with command line options, or the default
-for your configuration.  You can use this feature to permit specific
-R4000 instructions while assembling in 32 bit mode.  Use this directive
-with care!
-
-   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
-which it will assemble instructions for the MIPS 16 processor.  Use
-`.set nomips16' to return to normal 32 bit mode.
-
-   Traditional MIPS assemblers do not support this directive.
-
-
-File: as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS symbol sizes,  Up: MIPS-Dependent
-
-8.20.6 Directives for extending MIPS 16 bit instructions
---------------------------------------------------------
-
-By default, MIPS 16 instructions are automatically extended to 32 bits
-when necessary.  The directive `.set noautoextend' will turn this off.
-When `.set noautoextend' is in effect, any 32 bit instruction must be
-explicitly extended with the `.e' modifier (e.g., `li.e $4,1000').  The
-directive `.set autoextend' may be used to once again automatically
-extend instructions when necessary.
-
-   This directive is only meaningful when in MIPS 16 mode.  Traditional
-MIPS assemblers do not support this directive.
-
-
-File: as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent
-
-8.20.7 Directive to mark data as an instruction
------------------------------------------------
-
-The `.insn' directive tells `as' that the following data is actually
-instructions.  This makes a difference in MIPS 16 mode: when loading
-the address of a label which precedes instructions, `as' automatically
-adds 1 to the value, so that jumping to the loaded address will do the
-right thing.
-
-
-File: as.info,  Node: MIPS option stack,  Next: MIPS ASE instruction generation overrides,  Prev: MIPS insn,  Up: MIPS-Dependent
-
-8.20.8 Directives to save and restore options
----------------------------------------------
-
-The directives `.set push' and `.set pop' may be used to save and
-restore the current settings for all the options which are controlled
-by `.set'.  The `.set push' directive saves the current settings on a
-stack.  The `.set pop' directive pops the stack and restores the
-settings.
-
-   These directives can be useful inside an macro which must change an
-option such as the ISA level or instruction reordering but does not want
-to change the state of the code which invoked the macro.
-
-   Traditional MIPS assemblers do not support these directives.
-
-
-File: as.info,  Node: MIPS ASE instruction generation overrides,  Prev: MIPS option stack,  Up: MIPS-Dependent
-
-8.20.9 Directives to control generation of MIPS ASE instructions
-----------------------------------------------------------------
-
-The directive `.set mips3d' makes the assembler accept instructions
-from the MIPS-3D Application Specific Extension from that point on in
-the assembly.  The `.set nomips3d' directive prevents MIPS-3D
-instructions from being accepted.
-
-   The directive `.set mdmx' makes the assembler accept instructions
-from the MDMX Application Specific Extension from that point on in the
-assembly.  The `.set nomdmx' directive prevents MDMX instructions from
-being accepted.
-
-   The directive `.set dsp' makes the assembler accept instructions
-from the DSP Application Specific Extension from that point on in the
-assembly.  The `.set nodsp' directive prevents DSP instructions from
-being accepted.
-
-   The directive `.set mt' makes the assembler accept instructions from
-the MT Application Specific Extension from that point on in the
-assembly.  The `.set nomt' directive prevents MT instructions from
-being accepted.
-
-   Traditional MIPS assemblers do not support these directives.
-
-
-File: as.info,  Node: MMIX-Dependent,  Next: MSP430-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies
-
-8.21 MMIX Dependent Features
-============================
-
-* Menu:
-
-* MMIX-Opts::              Command-line Options
-* MMIX-Expand::            Instruction expansion
-* MMIX-Syntax::            Syntax
-* MMIX-mmixal::		   Differences to `mmixal' syntax and semantics
-
-
-File: as.info,  Node: MMIX-Opts,  Next: MMIX-Expand,  Up: MMIX-Dependent
-
-8.21.1 Command-line Options
----------------------------
-
-The MMIX version of `as' has some machine-dependent options.
-
-   When `--fixed-special-register-names' is specified, only the register
-names specified in *Note MMIX-Regs:: are recognized in the instructions
-`PUT' and `GET'.
-
-   You can use the `--globalize-symbols' to make all symbols global.
-This option is useful when splitting up a `mmixal' program into several
-files.
-
-   The `--gnu-syntax' turns off most syntax compatibility with
-`mmixal'.  Its usability is currently doubtful.
-
-   The `--relax' option is not fully supported, but will eventually make
-the object file prepared for linker relaxation.
-
-   If you want to avoid inadvertently calling a predefined symbol and
-would rather get an error, for example when using `as' with a compiler
-or other machine-generated code, specify `--no-predefined-syms'.  This
-turns off built-in predefined definitions of all such symbols,
-including rounding-mode symbols, segment symbols, `BIT' symbols, and
-`TRAP' symbols used in `mmix' "system calls".  It also turns off
-predefined special-register names, except when used in `PUT' and `GET'
-instructions.
-
-   By default, some instructions are expanded to fit the size of the
-operand or an external symbol (*note MMIX-Expand::).  By passing
-`--no-expand', no such expansion will be done, instead causing errors
-at link time if the operand does not fit.
-
-   The `mmixal' documentation (*note mmixsite::) specifies that global
-registers allocated with the `GREG' directive (*note MMIX-greg::) and
-initialized to the same non-zero value, will refer to the same global
-register.  This isn't strictly enforceable in `as' since the final
-addresses aren't known until link-time, but it will do an effort unless
-the `--no-merge-gregs' option is specified.  (Register merging isn't
-yet implemented in `ld'.)
-
-   `as' will warn every time it expands an instruction to fit an
-operand unless the option `-x' is specified.  It is believed that this
-behaviour is more useful than just mimicking `mmixal''s behaviour, in
-which instructions are only expanded if the `-x' option is specified,
-and assembly fails otherwise, when an instruction needs to be expanded.
-It needs to be kept in mind that `mmixal' is both an assembler and
-linker, while `as' will expand instructions that at link stage can be
-contracted.  (Though linker relaxation isn't yet implemented in `ld'.)
-The option `-x' also imples `--linker-allocated-gregs'.
-
-   If instruction expansion is enabled, `as' can expand a `PUSHJ'
-instruction into a series of instructions.  The shortest expansion is
-to not expand it, but just mark the call as redirectable to a stub,
-which `ld' creates at link-time, but only if the original `PUSHJ'
-instruction is found not to reach the target.  The stub consists of the
-necessary instructions to form a jump to the target.  This happens if
-`as' can assert that the `PUSHJ' instruction can reach such a stub.
-The option `--no-pushj-stubs' disables this shorter expansion, and the
-longer series of instructions is then created at assembly-time.  The
-option `--no-stubs' is a synonym, intended for compatibility with
-future releases, where generation of stubs for other instructions may
-be implemented.
-
-   Usually a two-operand-expression (*note GREG-base::) without a
-matching `GREG' directive is treated as an error by `as'.  When the
-option `--linker-allocated-gregs' is in effect, they are instead passed
-through to the linker, which will allocate as many global registers as
-is needed.
-
-
-File: as.info,  Node: MMIX-Expand,  Next: MMIX-Syntax,  Prev: MMIX-Opts,  Up: MMIX-Dependent
-
-8.21.2 Instruction expansion
-----------------------------
-
-When `as' encounters an instruction with an operand that is either not
-known or does not fit the operand size of the instruction, `as' (and
-`ld') will expand the instruction into a sequence of instructions
-semantically equivalent to the operand fitting the instruction.
-Expansion will take place for the following instructions:
-
-`GETA'
-     Expands to a sequence of four instructions: `SETL', `INCML',
-     `INCMH' and `INCH'.  The operand must be a multiple of four.
-
-Conditional branches
-     A branch instruction is turned into a branch with the complemented
-     condition and prediction bit over five instructions; four
-     instructions setting `$255' to the operand value, which like with
-     `GETA' must be a multiple of four, and a final `GO $255,$255,0'.
-
-`PUSHJ'
-     Similar to expansion for conditional branches; four instructions
-     set `$255' to the operand value, followed by a `PUSHGO
-     $255,$255,0'.
-
-`JMP'
-     Similar to conditional branches and `PUSHJ'.  The final instruction
-     is `GO $255,$255,0'.
-
-   The linker `ld' is expected to shrink these expansions for code
-assembled with `--relax' (though not currently implemented).
-
-
-File: as.info,  Node: MMIX-Syntax,  Next: MMIX-mmixal,  Prev: MMIX-Expand,  Up: MMIX-Dependent
-
-8.21.3 Syntax
--------------
-
-The assembly syntax is supposed to be upward compatible with that
-described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
-Volume 1'.  Draft versions of those chapters as well as other MMIX
-information is located at
-`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'.  Most code
-examples from the mmixal package located there should work unmodified
-when assembled and linked as single files, with a few noteworthy
-exceptions (*note MMIX-mmixal::).
-
-   Before an instruction is emitted, the current location is aligned to
-the next four-byte boundary.  If a label is defined at the beginning of
-the line, its value will be the aligned value.
-
-   In addition to the traditional hex-prefix `0x', a hexadecimal number
-can also be specified by the prefix character `#'.
-
-   After all operands to an MMIX instruction or directive have been
-specified, the rest of the line is ignored, treated as a comment.
-
-* Menu:
-
-* MMIX-Chars::		        Special Characters
-* MMIX-Symbols::		Symbols
-* MMIX-Regs::			Register Names
-* MMIX-Pseudos::		Assembler Directives
-
-
-File: as.info,  Node: MMIX-Chars,  Next: MMIX-Symbols,  Up: MMIX-Syntax
-
-8.21.3.1 Special Characters
-...........................
-
-The characters `*' and `#' are line comment characters; each start a
-comment at the beginning of a line, but only at the beginning of a
-line.  A `#' prefixes a hexadecimal number if found elsewhere on a line.
-
-   Two other characters, `%' and `!', each start a comment anywhere on
-the line.  Thus you can't use the `modulus' and `not' operators in
-expressions normally associated with these two characters.
-
-   A `;' is a line separator, treated as a new-line, so separate
-instructions can be specified on a single line.
-
-
-File: as.info,  Node: MMIX-Symbols,  Next: MMIX-Regs,  Prev: MMIX-Chars,  Up: MMIX-Syntax
-
-8.21.3.2 Symbols
-................
-
-The character `:' is permitted in identifiers.  There are two
-exceptions to it being treated as any other symbol character: if a
-symbol begins with `:', it means that the symbol is in the global
-namespace and that the current prefix should not be prepended to that
-symbol (*note MMIX-prefix::).  The `:' is then not considered part of
-the symbol.  For a symbol in the label position (first on a line), a `:'
-at the end of a symbol is silently stripped off.  A label is permitted,
-but not required, to be followed by a `:', as with many other assembly
-formats.
-
-   The character `@' in an expression, is a synonym for `.', the
-current location.
-
-   In addition to the common forward and backward local symbol formats
-(*note Symbol Names::), they can be specified with upper-case `B' and
-`F', as in `8B' and `9F'.  A local label defined for the current
-position is written with a `H' appended to the number:
-     3H LDB $0,$1,2
-   This and traditional local-label formats cannot be mixed: a label
-must be defined and referred to using the same format.
-
-   There's a minor caveat: just as for the ordinary local symbols, the
-local symbols are translated into ordinary symbols using control
-characters are to hide the ordinal number of the symbol.
-Unfortunately, these symbols are not translated back in error messages.
-Thus you may see confusing error messages when local symbols are used.
-Control characters `\003' (control-C) and `\004' (control-D) are used
-for the MMIX-specific local-symbol syntax.
-
-   The symbol `Main' is handled specially; it is always global.
-
-   By defining the symbols `__.MMIX.start..text' and
-`__.MMIX.start..data', the address of respectively the `.text' and
-`.data' segments of the final program can be defined, though when
-linking more than one object file, the code or data in the object file
-containing the symbol is not guaranteed to be start at that position;
-just the final executable.  *Note MMIX-loc::.
-
-
-File: as.info,  Node: MMIX-Regs,  Next: MMIX-Pseudos,  Prev: MMIX-Symbols,  Up: MMIX-Syntax
-
-8.21.3.3 Register names
-.......................
-
-Local and global registers are specified as `$0' to `$255'.  The
-recognized special register names are `rJ', `rA', `rB', `rC', `rD',
-`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
-`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
-`rWW', `rXX', `rYY' and `rZZ'.  A leading `:' is optional for special
-register names.
-
-   Local and global symbols can be equated to register names and used in
-place of ordinary registers.
-
-   Similarly for special registers, local and global symbols can be
-used.  Also, symbols equated from numbers and constant expressions are
-allowed in place of a special register, except when either of the
-options `--no-predefined-syms' and `--fixed-special-register-names' are
-specified.  Then only the special register names above are allowed for
-the instructions having a special register operand; `GET' and `PUT'.
-
-
-File: as.info,  Node: MMIX-Pseudos,  Prev: MMIX-Regs,  Up: MMIX-Syntax
-
-8.21.3.4 Assembler Directives
-.............................
-
-`LOC'
-     The `LOC' directive sets the current location to the value of the
-     operand field, which may include changing sections.  If the
-     operand is a constant, the section is set to either `.data' if the
-     value is `0x2000000000000000' or larger, else it is set to `.text'.
-     Within a section, the current location may only be changed to
-     monotonically higher addresses.  A LOC expression must be a
-     previously defined symbol or a "pure" constant.
-
-     An example, which sets the label PREV to the current location, and
-     updates the current location to eight bytes forward:
-          prev LOC @+8
-
-     When a LOC has a constant as its operand, a symbol
-     `__.MMIX.start..text' or `__.MMIX.start..data' is defined
-     depending on the address as mentioned above.  Each such symbol is
-     interpreted as special by the linker, locating the section at that
-     address.  Note that if multiple files are linked, the first object
-     file with that section will be mapped to that address (not
-     necessarily the file with the LOC definition).
-
-`LOCAL'
-     Example:
-           LOCAL external_symbol
-           LOCAL 42
-           .local asymbol
-
-     This directive-operation generates a link-time assertion that the
-     operand does not correspond to a global register.  The operand is
-     an expression that at link-time resolves to a register symbol or a
-     number.  A number is treated as the register having that number.
-     There is one restriction on the use of this directive: the
-     pseudo-directive must be placed in a section with contents, code
-     or data.
-
-`IS'
-     The `IS' directive:
-          asymbol IS an_expression
-     sets the symbol `asymbol' to `an_expression'.  A symbol may not be
-     set more than once using this directive.  Local labels may be set
-     using this directive, for example:
-          5H IS @+4
-
-`GREG'
-     This directive reserves a global register, gives it an initial
-     value and optionally gives it a symbolic name.  Some examples:
-
-          areg GREG
-          breg GREG data_value
-               GREG data_buffer
-               .greg creg, another_data_value
-
-     The symbolic register name can be used in place of a (non-special)
-     register.  If a value isn't provided, it defaults to zero.  Unless
-     the option `--no-merge-gregs' is specified, non-zero registers
-     allocated with this directive may be eliminated by `as'; another
-     register with the same value used in its place.  Any of the
-     instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
-     `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
-     `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
-     `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
-     have a value nearby an initial value in place of its second and
-     third operands.  Here, "nearby" is defined as within the range
-     0...255 from the initial value of such an allocated register.
-
-          buffer1 BYTE 0,0,0,0,0
-          buffer2 BYTE 0,0,0,0,0
-           ...
-           GREG buffer1
-           LDOU $42,buffer2
-     In the example above, the `Y' field of the `LDOUI' instruction
-     (LDOU with a constant Z) will be replaced with the global register
-     allocated for `buffer1', and the `Z' field will have the value 5,
-     the offset from `buffer1' to `buffer2'.  The result is equivalent
-     to this code:
-          buffer1 BYTE 0,0,0,0,0
-          buffer2 BYTE 0,0,0,0,0
-           ...
-          tmpreg GREG buffer1
-           LDOU $42,tmpreg,(buffer2-buffer1)
-
-     Global registers allocated with this directive are allocated in
-     order higher-to-lower within a file.  Other than that, the exact
-     order of register allocation and elimination is undefined.  For
-     example, the order is undefined when more than one file with such
-     directives are linked together.  With the options `-x' and
-     `--linker-allocated-gregs', `GREG' directives for two-operand
-     cases like the one mentioned above can be omitted.  Sufficient
-     global registers will then be allocated by the linker.
-
-`BYTE'
-     The `BYTE' directive takes a series of operands separated by a
-     comma.  If an operand is a string (*note Strings::), each
-     character of that string is emitted as a byte.  Other operands
-     must be constant expressions without forward references, in the
-     range 0...255.  If you need operands having expressions with
-     forward references, use `.byte' (*note Byte::).  An operand can be
-     omitted, defaulting to a zero value.
-
-`WYDE'
-`TETRA'
-`OCTA'
-     The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
-     four and eight bytes size respectively.  Before anything else
-     happens for the directive, the current location is aligned to the
-     respective constant-size boundary.  If a label is defined at the
-     beginning of the line, its value will be that after the alignment.
-     A single operand can be omitted, defaulting to a zero value
-     emitted for the directive.  Operands can be expressed as strings
-     (*note Strings::), in which case each character in the string is
-     emitted as a separate constant of the size indicated by the
-     directive.
-
-`PREFIX'
-     The `PREFIX' directive sets a symbol name prefix to be prepended to
-     all symbols (except local symbols, *note MMIX-Symbols::), that are
-     not prefixed with `:', until the next `PREFIX' directive.  Such
-     prefixes accumulate.  For example,
-           PREFIX a
-           PREFIX b
-          c IS 0
-     defines a symbol `abc' with the value 0.
-
-`BSPEC'
-`ESPEC'
-     A pair of `BSPEC' and `ESPEC' directives delimit a section of
-     special contents (without specified semantics).  Example:
-           BSPEC 42
-           TETRA 1,2,3
-           ESPEC
-     The single operand to `BSPEC' must be number in the range 0...255.
-     The `BSPEC' number 80 is used by the GNU binutils implementation.
-
-
-File: as.info,  Node: MMIX-mmixal,  Prev: MMIX-Syntax,  Up: MMIX-Dependent
-
-8.21.4 Differences to `mmixal'
-------------------------------
-
-The binutils `as' and `ld' combination has a few differences in
-function compared to `mmixal' (*note mmixsite::).
-
-   The replacement of a symbol with a GREG-allocated register (*note
-GREG-base::) is not handled the exactly same way in `as' as in
-`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
-where different registers with different offsets, eventually yielding
-the same address, are used in the first instruction.  This type of
-difference should however not affect the function of any program unless
-it has specific assumptions about the allocated register number.
-
-   Line numbers (in the `mmo' object format) are currently not
-supported.
-
-   Expression operator precedence is not that of mmixal: operator
-precedence is that of the C programming language.  It's recommended to
-use parentheses to explicitly specify wanted operator precedence
-whenever more than one type of operators are used.
-
-   The serialize unary operator `&', the fractional division operator
-`//', the logical not operator `!' and the modulus operator `%' are not
-available.
-
-   Symbols are not global by default, unless the option
-`--globalize-symbols' is passed.  Use the `.global' directive to
-globalize symbols (*note Global::).
-
-   Operand syntax is a bit stricter with `as' than `mmixal'.  For
-example, you can't say `addu 1,2,3', instead you must write `addu
-$1,$2,3'.
-
-   You can't LOC to a lower address than those already visited (i.e.
-"backwards").
-
-   A LOC directive must come before any emitted code.
-
-   Predefined symbols are visible as file-local symbols after use.  (In
-the ELF file, that is--the linked mmo file has no notion of a file-local
-symbol.)
-
-   Some mapping of constant expressions to sections in LOC expressions
-is attempted, but that functionality is easily confused and should be
-avoided unless compatibility with `mmixal' is required.  A LOC
-expression to `0x2000000000000000' or higher, maps to the `.data'
-section and lower addresses map to the `.text' section (*note
-MMIX-loc::).
-
-   The code and data areas are each contiguous.  Sparse programs with
-far-away LOC directives will take up the same amount of space as a
-contiguous program with zeros filled in the gaps between the LOC
-directives.  If you need sparse programs, you might try and get the
-wanted effect with a linker script and splitting up the code parts into
-sections (*note Section::).  Assembly code for this, to be compatible
-with `mmixal', would look something like:
-      .if 0
-      LOC away_expression
-      .else
-      .section away,"ax"
-      .fi
-   `as' will not execute the LOC directive and `mmixal' ignores the
-lines with `.'.  This construct can be used generally to help
-compatibility.
-
-   Symbols can't be defined twice-not even to the same value.
-
-   Instruction mnemonics are recognized case-insensitive, though the
-`IS' and `GREG' pseudo-operations must be specified in upper-case
-characters.
-
-   There's no unicode support.
-
-   The following is a list of programs in `mmix.tar.gz', available at
-`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last
-checked with the version dated 2001-08-25 (md5sum
-c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
-not assemble with `as':
-
-`silly.mms'
-     LOC to a previous address.
-
-`sim.mms'
-     Redefines symbol `Done'.
-
-`test.mms'
-     Uses the serial operator `&'.
-
-
-File: as.info,  Node: MSP430-Dependent,  Next: SH-Dependent,  Prev: MMIX-Dependent,  Up: Machine Dependencies
-
-8.22 MSP 430 Dependent Features
-===============================
-
-* Menu:
-
-* MSP430 Options::              Options
-* MSP430 Syntax::               Syntax
-* MSP430 Floating Point::       Floating Point
-* MSP430 Directives::           MSP 430 Machine Directives
-* MSP430 Opcodes::              Opcodes
-* MSP430 Profiling Capability::	Profiling Capability
-
-
-File: as.info,  Node: MSP430 Options,  Next: MSP430 Syntax,  Up: MSP430-Dependent
-
-8.22.1 Options
---------------
-
-`-m'
-     select the mpu arch. Currently has no effect.
-
-`-mP'
-     enables polymorph instructions handler.
-
-`-mQ'
-     enables relaxation at assembly time. DANGEROUS!
-
-
-
-File: as.info,  Node: MSP430 Syntax,  Next: MSP430 Floating Point,  Prev: MSP430 Options,  Up: MSP430-Dependent
-
-8.22.2 Syntax
--------------
-
-* Menu:
-
-* MSP430-Macros::		Macros
-* MSP430-Chars::                Special Characters
-* MSP430-Regs::                 Register Names
-* MSP430-Ext::			Assembler Extensions
-
-
-File: as.info,  Node: MSP430-Macros,  Next: MSP430-Chars,  Up: MSP430 Syntax
-
-8.22.2.1 Macros
-...............
-
-The macro syntax used on the MSP 430 is like that described in the MSP
-430 Family Assembler Specification.  Normal `as' macros should still
-work.
-
-   Additional built-in macros are:
-
-`llo(exp)'
-     Extracts least significant word from 32-bit expression 'exp'.
-
-`lhi(exp)'
-     Extracts most significant word from 32-bit expression 'exp'.
-
-`hlo(exp)'
-     Extracts 3rd word from 64-bit expression 'exp'.
-
-`hhi(exp)'
-     Extracts 4rd word from 64-bit expression 'exp'.
-
-
-   They normally being used as an immediate source operand.
-         mov	#llo(1), r10	;	== mov	#1, r10
-         mov	#lhi(1), r10	;	== mov	#0, r10
-
-
-File: as.info,  Node: MSP430-Chars,  Next: MSP430-Regs,  Prev: MSP430-Macros,  Up: MSP430 Syntax
-
-8.22.2.2 Special Characters
-...........................
-
-`;' is the line comment character.
-
-   The character `$' in jump instructions indicates current location and
-implemented only for TI syntax compatibility.
-
-
-File: as.info,  Node: MSP430-Regs,  Next: MSP430-Ext,  Prev: MSP430-Chars,  Up: MSP430 Syntax
-
-8.22.2.3 Register Names
-.......................
-
-General-purpose registers are represented by predefined symbols of the
-form `rN' (for global registers), where N represents a number between
-`0' and `15'.  The leading letters may be in either upper or lower
-case; for example, `r13' and `R7' are both valid register names.
-
-   Register names `PC', `SP' and `SR' cannot be used as register names
-and will be treated as variables. Use `r0', `r1', and `r2' instead.
-
-
-File: as.info,  Node: MSP430-Ext,  Prev: MSP430-Regs,  Up: MSP430 Syntax
-
-8.22.2.4 Assembler Extensions
-.............................
-
-`@rN'
-     As destination operand being treated as `0(rn)'
-
-`0(rN)'
-     As source operand being treated as `@rn'
-
-`jCOND +N'
-     Skips next N bytes followed by jump instruction and equivalent to
-     `jCOND $+N+2'
-
-
-   Also, there are some instructions, which cannot be found in other
-assemblers.  These are branch instructions, which has different opcodes
-upon jump distance.  They all got PC relative addressing mode.
-
-`beq label'
-     A polymorph instruction which is `jeq label' in case if jump
-     distance within allowed range for cpu's jump instruction. If not,
-     this unrolls into a sequence of
-            jne $+6
-            br  label
-
-`bne label'
-     A polymorph instruction which is `jne label' or `jeq +4; br label'
-
-`blt label'
-     A polymorph instruction which is `jl label' or `jge +4; br label'
-
-`bltn label'
-     A polymorph instruction which is `jn label' or `jn +2; jmp +4; br
-     label'
-
-`bltu label'
-     A polymorph instruction which is `jlo label' or `jhs +2; br label'
-
-`bge label'
-     A polymorph instruction which is `jge label' or `jl +4; br label'
-
-`bgeu label'
-     A polymorph instruction which is `jhs label' or `jlo +4; br label'
-
-`bgt label'
-     A polymorph instruction which is `jeq +2; jge label' or `jeq +6;
-     jl  +4; br label'
-
-`bgtu label'
-     A polymorph instruction which is `jeq +2; jhs label' or `jeq +6;
-     jlo +4; br label'
-
-`bleu label'
-     A polymorph instruction which is `jeq label; jlo label' or `jeq
-     +2; jhs +4; br label'
-
-`ble label'
-     A polymorph instruction which is `jeq label; jl  label' or `jeq
-     +2; jge +4; br label'
-
-`jump label'
-     A polymorph instruction which is `jmp label' or `br label'
-
-
-File: as.info,  Node: MSP430 Floating Point,  Next: MSP430 Directives,  Prev: MSP430 Syntax,  Up: MSP430-Dependent
-
-8.22.3 Floating Point
----------------------
-
-The MSP 430 family uses IEEE 32-bit floating-point numbers.
-
-
-File: as.info,  Node: MSP430 Directives,  Next: MSP430 Opcodes,  Prev: MSP430 Floating Point,  Up: MSP430-Dependent
-
-8.22.4 MSP 430 Machine Directives
----------------------------------
-
-`.file'
-     This directive is ignored; it is accepted for compatibility with
-     other MSP 430 assemblers.
-
-          _Warning:_ in other versions of the GNU assembler, `.file' is
-          used for the directive called `.app-file' in the MSP 430
-          support.
-
-`.line'
-     This directive is ignored; it is accepted for compatibility with
-     other MSP 430 assemblers.
-
-`.arch'
-     Currently this directive is ignored; it is accepted for
-     compatibility with other MSP 430 assemblers.
-
-`.profiler'
-     This directive instructs assembler to add new profile entry to the
-     object file.
-
-
-
-File: as.info,  Node: MSP430 Opcodes,  Next: MSP430 Profiling Capability,  Prev: MSP430 Directives,  Up: MSP430-Dependent
-
-8.22.5 Opcodes
---------------
-
-`as' implements all the standard MSP 430 opcodes.  No additional
-pseudo-instructions are needed on this family.
-
-   For information on the 430 machine instruction set, see `MSP430
-User's Manual, document slau049d', Texas Instrument, Inc.
-
-
-File: as.info,  Node: MSP430 Profiling Capability,  Prev: MSP430 Opcodes,  Up: MSP430-Dependent
-
-8.22.6 Profiling Capability
----------------------------
-
-It is a performance hit to use gcc's profiling approach for this tiny
-target.  Even more - jtag hardware facility does not perform any
-profiling functions.  However we've got gdb's built-in simulator where
-we can do anything.
-
-   We define new section `.profiler' which holds all profiling
-information.  We define new pseudo operation `.profiler' which will
-instruct assembler to add new profile entry to the object file. Profile
-should take place at the present address.
-
-   Pseudo operation format:
-
-   `.profiler flags,function_to_profile [, cycle_corrector, extra]'
-
-   where:
-
-          `flags' is a combination of the following characters:
-
-    `s'
-          function entry
-
-    `x'
-          function exit
-
-    `i'
-          function is in init section
-
-    `f'
-          function is in fini section
-
-    `l'
-          library call
-
-    `c'
-          libc standard call
-
-    `d'
-          stack value demand
-
-    `I'
-          interrupt service routine
-
-    `P'
-          prologue start
-
-    `p'
-          prologue end
-
-    `E'
-          epilogue start
-
-    `e'
-          epilogue end
-
-    `j'
-          long jump / sjlj unwind
-
-    `a'
-          an arbitrary code fragment
-
-    `t'
-          extra parameter saved (a constant value like frame size)
-
-`function_to_profile'
-     a function address
-
-`cycle_corrector'
-     a value which should be added to the cycle counter, zero if
-     omitted.
-
-`extra'
-     any extra parameter, zero if omitted.
-
-
-   For example:
-     .global fxx
-     .type fxx,@function
-     fxx:
-     .LFrameOffset_fxx=0x08
-     .profiler "scdP", fxx     ; function entry.
-     			  ; we also demand stack value to be saved
-       push r11
-       push r10
-       push r9
-       push r8
-     .profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
-     					  ; (this is a prologue end)
-     					  ; note, that spare var filled with
-     					  ; the farme size
-       mov r15,r8
-     ...
-     .profiler cdE,fxx         ; check stack
-       pop r8
-       pop r9
-       pop r10
-       pop r11
-     .profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
-       ret                     ; cause 'ret' insn takes 3 cycles
-
-
-File: as.info,  Node: PDP-11-Dependent,  Next: PJ-Dependent,  Prev: SH64-Dependent,  Up: Machine Dependencies
-
-8.23 PDP-11 Dependent Features
-==============================
-
-* Menu:
-
-* PDP-11-Options::		Options
-* PDP-11-Pseudos::		Assembler Directives
-* PDP-11-Syntax::		DEC Syntax versus BSD Syntax
-* PDP-11-Mnemonics::		Instruction Naming
-* PDP-11-Synthetic::		Synthetic Instructions
-
-
-File: as.info,  Node: PDP-11-Options,  Next: PDP-11-Pseudos,  Up: PDP-11-Dependent
-
-8.23.1 Options
---------------
-
-The PDP-11 version of `as' has a rich set of machine dependent options.
-
-8.23.1.1 Code Generation Options
-................................
-
-`-mpic | -mno-pic'
-     Generate position-independent (or position-dependent) code.
-
-     The default is to generate position-independent code.
-
-8.23.1.2 Instruction Set Extension Options
-..........................................
-
-These options enables or disables the use of extensions over the base
-line instruction set as introduced by the first PDP-11 CPU: the KA11.
-Most options come in two variants: a `-m'EXTENSION that enables
-EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.
-
-   The default is to enable all extensions.
-
-`-mall | -mall-extensions'
-     Enable all instruction set extensions.
-
-`-mno-extensions'
-     Disable all instruction set extensions.
-
-`-mcis | -mno-cis'
-     Enable (or disable) the use of the commercial instruction set,
-     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
-     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
-     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
-     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
-     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
-     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
-     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
-     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.
-
-`-mcsm | -mno-csm'
-     Enable (or disable) the use of the `CSM' instruction.
-
-`-meis | -mno-eis'
-     Enable (or disable) the use of the extended instruction set, which
-     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
-     `MUL', `RTT', `SOB' `SXT', and `XOR'.
-
-`-mfis | -mkev11'
-`-mno-fis | -mno-kev11'
-     Enable (or disable) the use of the KEV11 floating-point
-     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.
-
-`-mfpp | -mfpu | -mfp-11'
-`-mno-fpp | -mno-fpu | -mno-fp-11'
-     Enable (or disable) the use of FP-11 floating-point instructions:
-     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
-     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
-     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
-     `SUBF', and `TSTF'.
-
-`-mlimited-eis | -mno-limited-eis'
-     Enable (or disable) the use of the limited extended instruction
-     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.
-
-     The -mno-limited-eis options also implies -mno-eis.
-
-`-mmfpt | -mno-mfpt'
-     Enable (or disable) the use of the `MFPT' instruction.
-
-`-mmultiproc | -mno-multiproc'
-     Enable (or disable) the use of multiprocessor instructions:
-     `TSTSET' and `WRTLCK'.
-
-`-mmxps | -mno-mxps'
-     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.
-
-`-mspl | -mno-spl'
-     Enable (or disable) the use of the `SPL' instruction.
-
-     Enable (or disable) the use of the microcode instructions: `LDUB',
-     `MED', and `XFC'.
-
-8.23.1.3 CPU Model Options
-..........................
-
-These options enable the instruction set extensions supported by a
-particular CPU, and disables all other extensions.
-
-`-mka11'
-     KA11 CPU.  Base line instruction set only.
-
-`-mkb11'
-     KB11 CPU.  Enable extended instruction set and `SPL'.
-
-`-mkd11a'
-     KD11-A CPU.  Enable limited extended instruction set.
-
-`-mkd11b'
-     KD11-B CPU.  Base line instruction set only.
-
-`-mkd11d'
-     KD11-D CPU.  Base line instruction set only.
-
-`-mkd11e'
-     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.
-
-`-mkd11f | -mkd11h | -mkd11q'
-     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
-     instruction set, `MFPS', and `MTPS'.
-
-`-mkd11k'
-     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
-     `MFPS', `MFPT', `MTPS', and `XFC'.
-
-`-mkd11z'
-     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
-     `MFPT', `MTPS', and `SPL'.
-
-`-mf11'
-     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
-     `MTPS'.
-
-`-mj11'
-     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
-     `MTPS', `SPL', `TSTSET', and `WRTLCK'.
-
-`-mt11'
-     T11 CPU.  Enable limited extended instruction set, `MFPS', and
-     `MTPS'.
-
-8.23.1.4 Machine Model Options
-..............................
-
-These options enable the instruction set extensions supported by a
-particular machine model, and disables all other extensions.
-
-`-m11/03'
-     Same as `-mkd11f'.
-
-`-m11/04'
-     Same as `-mkd11d'.
-
-`-m11/05 | -m11/10'
-     Same as `-mkd11b'.
-
-`-m11/15 | -m11/20'
-     Same as `-mka11'.
-
-`-m11/21'
-     Same as `-mt11'.
-
-`-m11/23 | -m11/24'
-     Same as `-mf11'.
-
-`-m11/34'
-     Same as `-mkd11e'.
-
-`-m11/34a'
-     Ame as `-mkd11e' `-mfpp'.
-
-`-m11/35 | -m11/40'
-     Same as `-mkd11a'.
-
-`-m11/44'
-     Same as `-mkd11z'.
-
-`-m11/45 | -m11/50 | -m11/55 | -m11/70'
-     Same as `-mkb11'.
-
-`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
-     Same as `-mj11'.
-
-`-m11/60'
-     Same as `-mkd11k'.
-
-
-File: as.info,  Node: PDP-11-Pseudos,  Next: PDP-11-Syntax,  Prev: PDP-11-Options,  Up: PDP-11-Dependent
-
-8.23.2 Assembler Directives
----------------------------
-
-The PDP-11 version of `as' has a few machine dependent assembler
-directives.
-
-`.bss'
-     Switch to the `bss' section.
-
-`.even'
-     Align the location counter to an even number.
-
-
-File: as.info,  Node: PDP-11-Syntax,  Next: PDP-11-Mnemonics,  Prev: PDP-11-Pseudos,  Up: PDP-11-Dependent
-
-8.23.3 PDP-11 Assembly Language Syntax
---------------------------------------
-
-`as' supports both DEC syntax and BSD syntax.  The only difference is
-that in DEC syntax, a `#' character is used to denote an immediate
-constants, while in BSD syntax the character for this purpose is `$'.
-
-   eneral-purpose registers are named `r0' through `r7'.  Mnemonic
-alternatives for `r6' and `r7' are `sp' and `pc', respectively.
-
-   Floating-point registers are named `ac0' through `ac3', or
-alternatively `fr0' through `fr3'.
-
-   Comments are started with a `#' or a `/' character, and extend to
-the end of the line.  (FIXME: clash with immediates?)
-
-
-File: as.info,  Node: PDP-11-Mnemonics,  Next: PDP-11-Synthetic,  Prev: PDP-11-Syntax,  Up: PDP-11-Dependent
-
-8.23.4 Instruction Naming
--------------------------
-
-Some instructions have alternative names.
-
-`BCC'
-     `BHIS'
-
-`BCS'
-     `BLO'
-
-`L2DR'
-     `L2D'
-
-`L3DR'
-     `L3D'
-
-`SYS'
-     `TRAP'
-
-
-File: as.info,  Node: PDP-11-Synthetic,  Prev: PDP-11-Mnemonics,  Up: PDP-11-Dependent
-
-8.23.5 Synthetic Instructions
------------------------------
-
-The `JBR' and `J'CC synthetic instructions are not supported yet.
-
-
-File: as.info,  Node: PJ-Dependent,  Next: PPC-Dependent,  Prev: PDP-11-Dependent,  Up: Machine Dependencies
-
-8.24 picoJava Dependent Features
-================================
-
-* Menu:
-
-* PJ Options::              Options
-
-
-File: as.info,  Node: PJ Options,  Up: PJ-Dependent
-
-8.24.1 Options
---------------
-
-`as' has two additional command-line options for the picoJava
-architecture.
-`-ml'
-     This option selects little endian data output.
-
-`-mb'
-     This option selects big endian data output.
-
-
-File: as.info,  Node: PPC-Dependent,  Next: Sparc-Dependent,  Prev: PJ-Dependent,  Up: Machine Dependencies
-
-8.25 PowerPC Dependent Features
-===============================
-
-* Menu:
-
-* PowerPC-Opts::                Options
-* PowerPC-Pseudo::              PowerPC Assembler Directives
-
-
-File: as.info,  Node: PowerPC-Opts,  Next: PowerPC-Pseudo,  Up: PPC-Dependent
-
-8.25.1 Options
---------------
-
-The PowerPC chip family includes several successive levels, using the
-same core instruction set, but including a few additional instructions
-at each level.  There are exceptions to this however.  For details on
-what instructions each variant supports, please see the chip's
-architecture reference manual.
-
-   The following table lists all available PowerPC options.
-
-`-mpwrx | -mpwr2'
-     Generate code for POWER/2 (RIOS2).
-
-`-mpwr'
-     Generate code for POWER (RIOS1)
-
-`-m601'
-     Generate code for PowerPC 601.
-
-`-mppc, -mppc32, -m603, -m604'
-     Generate code for PowerPC 603/604.
-
-`-m403, -m405'
-     Generate code for PowerPC 403/405.
-
-`-m440'
-     Generate code for PowerPC 440.  BookE and some 405 instructions.
-
-`-m7400, -m7410, -m7450, -m7455'
-     Generate code for PowerPC 7400/7410/7450/7455.
-
-`-mppc64, -m620'
-     Generate code for PowerPC 620/625/630.
-
-`-mppc64bridge'
-     Generate code for PowerPC 64, including bridge insns.
-
-`-mbooke64'
-     Generate code for 64-bit BookE.
-
-`-mbooke, mbooke32'
-     Generate code for 32-bit BookE.
-
-`-me300'
-     Generate code for PowerPC e300 family.
-
-`-maltivec'
-     Generate code for processors with AltiVec instructions.
-
-`-mpower4'
-     Generate code for Power4 architecture.
-
-`-mpower5'
-     Generate code for Power5 architecture.
-
-`-mcom'
-     Generate code Power/PowerPC common instructions.
-
-`-many'
-     Generate code for any architecture (PWR/PWRX/PPC).
-
-`-mregnames'
-     Allow symbolic names for registers.
-
-`-mno-regnames'
-     Do not allow symbolic names for registers.
-
-`-mrelocatable'
-     Support for GCC's -mrelocatble option.
-
-`-mrelocatable-lib'
-     Support for GCC's -mrelocatble-lib option.
-
-`-memb'
-     Set PPC_EMB bit in ELF flags.
-
-`-mlittle, -mlittle-endian'
-     Generate code for a little endian machine.
-
-`-mbig, -mbig-endian'
-     Generate code for a big endian machine.
-
-`-msolaris'
-     Generate code for Solaris.
-
-`-mno-solaris'
-     Do not generate code for Solaris.
-
-
-File: as.info,  Node: PowerPC-Pseudo,  Prev: PowerPC-Opts,  Up: PPC-Dependent
-
-8.25.2 PowerPC Assembler Directives
------------------------------------
-
-A number of assembler directives are available for PowerPC.  The
-following table is far from complete.
-
-`.machine "string"'
-     This directive allows you to change the machine for which code is
-     generated.  `"string"' may be any of the -m cpu selection options
-     (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
-     `.machine "push"' saves the currently selected cpu, which may be
-     restored with `.machine "pop"'.
-
-
-File: as.info,  Node: SH-Dependent,  Next: SH64-Dependent,  Prev: MSP430-Dependent,  Up: Machine Dependencies
-
-8.26 Renesas / SuperH SH Dependent Features
-===========================================
-
-* Menu:
-
-* SH Options::              Options
-* SH Syntax::               Syntax
-* SH Floating Point::       Floating Point
-* SH Directives::           SH Machine Directives
-* SH Opcodes::              Opcodes
-
-
-File: as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent
-
-8.26.1 Options
---------------
-
-`as' has following command-line options for the Renesas (formerly
-Hitachi) / SuperH SH family.
-
-`--little'
-     Generate little endian code.
-
-`--big'
-     Generate big endian code.
-
-`--relax'
-     Alter jump instructions for long displacements.
-
-`--small'
-     Align sections to 4 byte boundaries, not 16.
-
-`--dsp'
-     Enable sh-dsp insns, and disable sh3e / sh4 insns.
-
-`--renesas'
-     Disable optimization with section symbol for compatibility with
-     Renesas assembler.
-
-`--allow-reg-prefix'
-     Allow '$' as a register name prefix.
-
-`--isa=sh4 | sh4a'
-     Specify the sh4 or sh4a instruction set.
-
-`--isa=dsp'
-     Enable sh-dsp insns, and disable sh3e / sh4 insns.
-
-`--isa=fp'
-     Enable sh2e, sh3e, sh4, and sh4a insn sets.
-
-`--isa=all'
-     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
-
-
-
-File: as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent
-
-8.26.2 Syntax
--------------
-
-* Menu:
-
-* SH-Chars::                Special Characters
-* SH-Regs::                 Register Names
-* SH-Addressing::           Addressing Modes
-
-
-File: as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax
-
-8.26.2.1 Special Characters
-...........................
-
-`!' is the line comment character.
-
-   You can use `;' instead of a newline to separate statements.
-
-   Since `$' has no special meaning, you may use it in symbol names.
-
-
-File: as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax
-
-8.26.2.2 Register Names
-.......................
-
-You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
-`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
-refer to the SH registers.
-
-   The SH also has these control registers:
-
-`pr'
-     procedure register (holds return address)
-
-`pc'
-     program counter
-
-`mach'
-`macl'
-     high and low multiply accumulator registers
-
-`sr'
-     status register
-
-`gbr'
-     global base register
-
-`vbr'
-     vector base register (for interrupt vectors)
-
-
-File: as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax
-
-8.26.2.3 Addressing Modes
-.........................
-
-`as' understands the following addressing modes for the SH.  `RN' in
-the following refers to any of the numbered registers, but _not_ the
-control registers.
-
-`RN'
-     Register direct
-
-`@RN'
-     Register indirect
-
-`@-RN'
-     Register indirect with pre-decrement
-
-`@RN+'
-     Register indirect with post-increment
-
-`@(DISP, RN)'
-     Register indirect with displacement
-
-`@(R0, RN)'
-     Register indexed
-
-`@(DISP, GBR)'
-     `GBR' offset
-
-`@(R0, GBR)'
-     GBR indexed
-
-`ADDR'
-`@(DISP, PC)'
-     PC relative address (for branch or for addressing memory).  The
-     `as' implementation allows you to use the simpler form ADDR
-     anywhere a PC relative address is called for; the alternate form
-     is supported for compatibility with other assemblers.
-
-`#IMM'
-     Immediate data
-
-
-File: as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent
-
-8.26.3 Floating Point
----------------------
-
-SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
-SH groups can use `.float' directive to generate IEEE floating-point
-numbers.
-
-   SH2E and SH3E support single-precision floating point calculations as
-well as entirely PCAPI compatible emulation of double-precision
-floating point calculations. SH2E and SH3E instructions are a subset of
-the floating point calculations conforming to the IEEE754 standard.
-
-   In addition to single-precision and double-precision floating-point
-operation capability, the on-chip FPU of SH4 has a 128-bit graphic
-engine that enables 32-bit floating-point data to be processed 128 bits
-at a time. It also supports 4 * 4 array operations and inner product
-operations. Also, a superscalar architecture is employed that enables
-simultaneous execution of two instructions (including FPU
-instructions), providing performance of up to twice that of
-conventional architectures at the same frequency.
-
-
-File: as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent
-
-8.26.4 SH Machine Directives
-----------------------------
-
-`uaword'
-`ualong'
-     `as' will issue a warning when a misaligned `.word' or `.long'
-     directive is used.  You may use `.uaword' or `.ualong' to indicate
-     that the value is intentionally misaligned.
-
-
-File: as.info,  Node: SH Opcodes,  Prev: SH Directives,  Up: SH-Dependent
-
-8.26.5 Opcodes
---------------
-
-For detailed information on the SH machine instruction set, see
-`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
-Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).
-
-   `as' implements all the standard SH opcodes.  No additional
-pseudo-instructions are needed on this family.  Note, however, that
-because `as' supports a simpler form of PC-relative addressing, you may
-simply write (for example)
-
-     mov.l  bar,r0
-
-where other assemblers might require an explicit displacement to `bar'
-from the program counter:
-
-     mov.l  @(DISP, PC)
-
-   Here is a summary of SH opcodes:
-
-     Legend:
-     Rn        a numbered register
-     Rm        another numbered register
-     #imm      immediate data
-     disp      displacement
-     disp8     8-bit displacement
-     disp12    12-bit displacement
-
-     add #imm,Rn                    lds.l @Rn+,PR
-     add Rm,Rn                      mac.w @Rm+,@Rn+
-     addc Rm,Rn                     mov #imm,Rn
-     addv Rm,Rn                     mov Rm,Rn
-     and #imm,R0                    mov.b Rm,@(R0,Rn)
-     and Rm,Rn                      mov.b Rm,@-Rn
-     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
-     bf disp8                       mov.b @(disp,Rm),R0
-     bra disp12                     mov.b @(disp,GBR),R0
-     bsr disp12                     mov.b @(R0,Rm),Rn
-     bt disp8                       mov.b @Rm+,Rn
-     clrmac                         mov.b @Rm,Rn
-     clrt                           mov.b R0,@(disp,Rm)
-     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
-     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
-     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
-     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
-     cmp/hi Rm,Rn                   mov.l Rm,@Rn
-     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
-     cmp/pl Rn                      mov.l @(disp,GBR),R0
-     cmp/pz Rn                      mov.l @(disp,PC),Rn
-     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
-     div0s Rm,Rn                    mov.l @Rm+,Rn
-     div0u                          mov.l @Rm,Rn
-     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
-     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
-     exts.w Rm,Rn                   mov.w Rm,@-Rn
-     extu.b Rm,Rn                   mov.w Rm,@Rn
-     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
-     jmp @Rn                        mov.w @(disp,GBR),R0
-     jsr @Rn                        mov.w @(disp,PC),Rn
-     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
-     ldc Rn,SR                      mov.w @Rm+,Rn
-     ldc Rn,VBR                     mov.w @Rm,Rn
-     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
-     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
-     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
-     lds Rn,MACH                    movt Rn
-     lds Rn,MACL                    muls Rm,Rn
-     lds Rn,PR                      mulu Rm,Rn
-     lds.l @Rn+,MACH                neg Rm,Rn
-     lds.l @Rn+,MACL                negc Rm,Rn
-
-     nop                            stc VBR,Rn
-     not Rm,Rn                      stc.l GBR,@-Rn
-     or #imm,R0                     stc.l SR,@-Rn
-     or Rm,Rn                       stc.l VBR,@-Rn
-     or.b #imm,@(R0,GBR)            sts MACH,Rn
-     rotcl Rn                       sts MACL,Rn
-     rotcr Rn                       sts PR,Rn
-     rotl Rn                        sts.l MACH,@-Rn
-     rotr Rn                        sts.l MACL,@-Rn
-     rte                            sts.l PR,@-Rn
-     rts                            sub Rm,Rn
-     sett                           subc Rm,Rn
-     shal Rn                        subv Rm,Rn
-     shar Rn                        swap.b Rm,Rn
-     shll Rn                        swap.w Rm,Rn
-     shll16 Rn                      tas.b @Rn
-     shll2 Rn                       trapa #imm
-     shll8 Rn                       tst #imm,R0
-     shlr Rn                        tst Rm,Rn
-     shlr16 Rn                      tst.b #imm,@(R0,GBR)
-     shlr2 Rn                       xor #imm,R0
-     shlr8 Rn                       xor Rm,Rn
-     sleep                          xor.b #imm,@(R0,GBR)
-     stc GBR,Rn                     xtrct Rm,Rn
-     stc SR,Rn
-
-
-File: as.info,  Node: SH64-Dependent,  Next: PDP-11-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies
-
-8.27 SuperH SH64 Dependent Features
-===================================
-
-* Menu:
-
-* SH64 Options::              Options
-* SH64 Syntax::               Syntax
-* SH64 Directives::           SH64 Machine Directives
-* SH64 Opcodes::              Opcodes
-
-
-File: as.info,  Node: SH64 Options,  Next: SH64 Syntax,  Up: SH64-Dependent
-
-8.27.1 Options
---------------
-
-`-isa=sh4 | sh4a'
-     Specify the sh4 or sh4a instruction set.
-
-`-isa=dsp'
-     Enable sh-dsp insns, and disable sh3e / sh4 insns.
-
-`-isa=fp'
-     Enable sh2e, sh3e, sh4, and sh4a insn sets.
-
-`-isa=all'
-     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
-
-`-isa=shmedia | -isa=shcompact'
-     Specify the default instruction set.  `SHmedia' specifies the
-     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
-     compatible with previous SH families.  The default depends on the
-     ABI selected; the default for the 64-bit ABI is SHmedia, and the
-     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
-     the ISA is specified, the default is 32-bit SHcompact.
-
-     Note that the `.mode' pseudo-op is not permitted if the ISA is not
-     specified on the command line.
-
-`-abi=32 | -abi=64'
-     Specify the default ABI.  If the ISA is specified and the ABI is
-     not, the default ABI depends on the ISA, with SHmedia defaulting
-     to 64-bit and SHcompact defaulting to 32-bit.
-
-     Note that the `.abi' pseudo-op is not permitted if the ABI is not
-     specified on the command line.  When the ABI is specified on the
-     command line, any `.abi' pseudo-ops in the source must match it.
-
-`-shcompact-const-crange'
-     Emit code-range descriptors for constants in SHcompact code
-     sections.
-
-`-no-mix'
-     Disallow SHmedia code in the same section as constants and
-     SHcompact code.
-
-`-no-expand'
-     Do not expand MOVI, PT, PTA or PTB instructions.
-
-`-expand-pt32'
-     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
-
-
-
-File: as.info,  Node: SH64 Syntax,  Next: SH64 Directives,  Prev: SH64 Options,  Up: SH64-Dependent
-
-8.27.2 Syntax
--------------
-
-* Menu:
-
-* SH64-Chars::                Special Characters
-* SH64-Regs::                 Register Names
-* SH64-Addressing::           Addressing Modes
-
-
-File: as.info,  Node: SH64-Chars,  Next: SH64-Regs,  Up: SH64 Syntax
-
-8.27.2.1 Special Characters
-...........................
-
-`!' is the line comment character.
-
-   You can use `;' instead of a newline to separate statements.
-
-   Since `$' has no special meaning, you may use it in symbol names.
-
-
-File: as.info,  Node: SH64-Regs,  Next: SH64-Addressing,  Prev: SH64-Chars,  Up: SH64 Syntax
-
-8.27.2.2 Register Names
-.......................
-
-You can use the predefined symbols `r0' through `r63' to refer to the
-SH64 general registers, `cr0' through `cr63' for control registers,
-`tr0' through `tr7' for target address registers, `fr0' through `fr63'
-for single-precision floating point registers, `dr0' through `dr62'
-(even numbered registers only) for double-precision floating point
-registers, `fv0' through `fv60' (multiples of four only) for
-single-precision floating point vectors, `fp0' through `fp62' (even
-numbered registers only) for single-precision floating point pairs,
-`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
-single-precision floating point registers, `pc' for the program
-counter, and `fpscr' for the floating point status and control register.
-
-   You can also refer to the control registers by the mnemonics `sr',
-`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
-`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.
-
-
-File: as.info,  Node: SH64-Addressing,  Prev: SH64-Regs,  Up: SH64 Syntax
-
-8.27.2.3 Addressing Modes
-.........................
-
-SH64 operands consist of either a register or immediate value.  The
-immediate value can be a constant or label reference (or portion of a
-label reference), as in this example:
-
-     	movi	4,r2
-     	pt	function, tr4
-     	movi	(function >> 16) & 65535,r0
-     	shori	function & 65535, r0
-     	ld.l	r0,4,r0
-
-   Instruction label references can reference labels in either SHmedia
-or SHcompact.  To differentiate between the two, labels in SHmedia
-sections will always have the least significant bit set (i.e. they will
-be odd), which SHcompact labels will have the least significant bit
-reset (i.e. they will be even).  If you need to reference the actual
-address of a label, you can use the `datalabel' modifier, as in this
-example:
-
-     	.long	function
-     	.long	datalabel function
-
-   In that example, the first longword may or may not have the least
-significant bit set depending on whether the label is an SHmedia label
-or an SHcompact label.  The second longword will be the actual address
-of the label, regardless of what type of label it is.
-
-
-File: as.info,  Node: SH64 Directives,  Next: SH64 Opcodes,  Prev: SH64 Syntax,  Up: SH64-Dependent
-
-8.27.3 SH64 Machine Directives
-------------------------------
-
-In addition to the SH directives, the SH64 provides the following
-directives:
-
-`.mode [shmedia|shcompact]'
-`.isa [shmedia|shcompact]'
-     Specify the ISA for the following instructions (the two directives
-     are equivalent).  Note that programs such as `objdump' rely on
-     symbolic labels to determine when such mode switches occur (by
-     checking the least significant bit of the label's address), so
-     such mode/isa changes should always be followed by a label (in
-     practice, this is true anyway).  Note that you cannot use these
-     directives if you didn't specify an ISA on the command line.
-
-`.abi [32|64]'
-     Specify the ABI for the following instructions.  Note that you
-     cannot use this directive unless you specified an ABI on the
-     command line, and the ABIs specified must match.
-
-`.uaquad'
-     Like .uaword and .ualong, this allows you to specify an
-     intentionally unaligned quadword (64 bit word).
-
-
-
-File: as.info,  Node: SH64 Opcodes,  Prev: SH64 Directives,  Up: SH64-Dependent
-
-8.27.4 Opcodes
---------------
-
-For detailed information on the SH64 machine instruction set, see
-`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
-
-   `as' implements all the standard SH64 opcodes.  In addition, the
-following pseudo-opcodes may be expanded into one or more alternate
-opcodes:
-
-`movi'
-     If the value doesn't fit into a standard `movi' opcode, `as' will
-     replace the `movi' with a sequence of `movi' and `shori' opcodes.
-
-`pt'
-     This expands to a sequence of `movi' and `shori' opcode, followed
-     by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
-     the label referenced.
-
-
-
-File: as.info,  Node: Sparc-Dependent,  Next: TIC54X-Dependent,  Prev: PPC-Dependent,  Up: Machine Dependencies
-
-8.28 SPARC Dependent Features
-=============================
-
-* Menu:
-
-* Sparc-Opts::                  Options
-* Sparc-Aligned-Data::		Option to enforce aligned data
-* Sparc-Float::                 Floating Point
-* Sparc-Directives::            Sparc Machine Directives
-
-
-File: as.info,  Node: Sparc-Opts,  Next: Sparc-Aligned-Data,  Up: Sparc-Dependent
-
-8.28.1 Options
---------------
-
-The SPARC chip family includes several successive levels, using the same
-core instruction set, but including a few additional instructions at
-each level.  There are exceptions to this however.  For details on what
-instructions each variant supports, please see the chip's architecture
-reference manual.
-
-   By default, `as' assumes the core instruction set (SPARC v6), but
-"bumps" the architecture level as needed: it switches to successively
-higher architectures as it encounters instructions that only exist in
-the higher levels.
-
-   If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
-passed sparclite by default, an option must be passed to enable the v9
-instructions.
-
-   GAS treats sparclite as being compatible with v8, unless an
-architecture is explicitly requested.  SPARC v9 is always incompatible
-with sparclite.
-
-`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
-`-Av8plus | -Av8plusa | -Av9 | -Av9a'
-     Use one of the `-A' options to select one of the SPARC
-     architectures explicitly.  If you select an architecture
-     explicitly, `as' reports a fatal error if it encounters an
-     instruction or feature requiring an incompatible or higher level.
-
-     `-Av8plus' and `-Av8plusa' select a 32 bit environment.
-
-     `-Av9' and `-Av9a' select a 64 bit environment and are not
-     available unless GAS is explicitly configured with 64 bit
-     environment support.
-
-     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
-     UltraSPARC extensions.
-
-`-xarch=v8plus | -xarch=v8plusa'
-     For compatibility with the Solaris v9 assembler.  These options are
-     equivalent to -Av8plus and -Av8plusa, respectively.
-
-`-bump'
-     Warn whenever it is necessary to switch to another level.  If an
-     architecture level is explicitly requested, GAS will not issue
-     warnings until that level is reached, and will then bump the level
-     as required (except between incompatible levels).
-
-`-32 | -64'
-     Select the word size, either 32 bits or 64 bits.  These options
-     are only available with the ELF object file format, and require
-     that the necessary BFD support has been included.
-
-
-File: as.info,  Node: Sparc-Aligned-Data,  Next: Sparc-Float,  Prev: Sparc-Opts,  Up: Sparc-Dependent
-
-8.28.2 Enforcing aligned data
------------------------------
-
-SPARC GAS normally permits data to be misaligned.  For example, it
-permits the `.long' pseudo-op to be used on a byte boundary.  However,
-the native SunOS and Solaris assemblers issue an error when they see
-misaligned data.
-
-   You can use the `--enforce-aligned-data' option to make SPARC GAS
-also issue an error about misaligned data, just as the SunOS and Solaris
-assemblers do.
-
-   The `--enforce-aligned-data' option is not the default because gcc
-issues misaligned data pseudo-ops when it initializes certain packed
-data structures (structures defined using the `packed' attribute).  You
-may have to assemble with GAS in order to initialize packed data
-structures in your own code.
-
-
-File: as.info,  Node: Sparc-Float,  Next: Sparc-Directives,  Prev: Sparc-Aligned-Data,  Up: Sparc-Dependent
-
-8.28.3 Floating Point
----------------------
-
-The Sparc uses IEEE floating-point numbers.
-
-
-File: as.info,  Node: Sparc-Directives,  Prev: Sparc-Float,  Up: Sparc-Dependent
-
-8.28.4 Sparc Machine Directives
--------------------------------
-
-The Sparc version of `as' supports the following additional machine
-directives:
-
-`.align'
-     This must be followed by the desired alignment in bytes.
-
-`.common'
-     This must be followed by a symbol name, a positive number, and
-     `"bss"'.  This behaves somewhat like `.comm', but the syntax is
-     different.
-
-`.half'
-     This is functionally identical to `.short'.
-
-`.nword'
-     On the Sparc, the `.nword' directive produces native word sized
-     value, ie. if assembling with -32 it is equivalent to `.word', if
-     assembling with -64 it is equivalent to `.xword'.
-
-`.proc'
-     This directive is ignored.  Any text following it on the same line
-     is also ignored.
-
-`.register'
-     This directive declares use of a global application or system
-     register.  It must be followed by a register name %g2, %g3, %g6 or
-     %g7, comma and the symbol name for that register.  If symbol name
-     is `#scratch', it is a scratch register, if it is `#ignore', it
-     just suppresses any errors about using undeclared global register,
-     but does not emit any information about it into the object file.
-     This can be useful e.g. if you save the register before use and
-     restore it after.
-
-`.reserve'
-     This must be followed by a symbol name, a positive number, and
-     `"bss"'.  This behaves somewhat like `.lcomm', but the syntax is
-     different.
-
-`.seg'
-     This must be followed by `"text"', `"data"', or `"data1"'.  It
-     behaves like `.text', `.data', or `.data 1'.
-
-`.skip'
-     This is functionally identical to the `.space' directive.
-
-`.word'
-     On the Sparc, the `.word' directive produces 32 bit values,
-     instead of the 16 bit values it produces on many other machines.
-
-`.xword'
-     On the Sparc V9 processor, the `.xword' directive produces 64 bit
-     values.
-
-
-File: as.info,  Node: TIC54X-Dependent,  Next: V850-Dependent,  Prev: Sparc-Dependent,  Up: Machine Dependencies
-
-8.29 TIC54X Dependent Features
-==============================
-
-* Menu:
-
-* TIC54X-Opts::              Command-line Options
-* TIC54X-Block::             Blocking
-* TIC54X-Env::               Environment Settings
-* TIC54X-Constants::         Constants Syntax
-* TIC54X-Subsyms::           String Substitution
-* TIC54X-Locals::            Local Label Syntax
-* TIC54X-Builtins::          Builtin Assembler Math Functions
-* TIC54X-Ext::               Extended Addressing Support
-* TIC54X-Directives::        Directives
-* TIC54X-Macros::            Macro Features
-* TIC54X-MMRegs::            Memory-mapped Registers
-
-
-File: as.info,  Node: TIC54X-Opts,  Next: TIC54X-Block,  Up: TIC54X-Dependent
-
-8.29.1 Options
---------------
-
-The TMS320C54x version of `as' has a few machine-dependent options.
-
-   You can use the `-mfar-mode' option to enable extended addressing
-mode.  All addresses will be assumed to be > 16 bits, and the
-appropriate relocation types will be used.  This option is equivalent
-to using the `.far_mode' directive in the assembly code.  If you do not
-use the `-mfar-mode' option, all references will be assumed to be 16
-bits.  This option may be abbreviated to `-mf'.
-
-   You can use the `-mcpu' option to specify a particular CPU.  This
-option is equivalent to using the `.version' directive in the assembly
-code.  For recognized CPU codes, see *Note `.version':
-TIC54X-Directives.  The default CPU version is `542'.
-
-   You can use the `-merrors-to-file' option to redirect error output
-to a file (this provided for those deficient environments which don't
-provide adequate output redirection).  This option may be abbreviated to
-`-me'.
-
-
-File: as.info,  Node: TIC54X-Block,  Next: TIC54X-Env,  Prev: TIC54X-Opts,  Up: TIC54X-Dependent
-
-8.29.2 Blocking
----------------
-
-A blocked section or memory block is guaranteed not to cross the
-blocking boundary (usually a page, or 128 words) if it is smaller than
-the blocking size, or to start on a page boundary if it is larger than
-the blocking size.
-
-
-File: as.info,  Node: TIC54X-Env,  Next: TIC54X-Constants,  Prev: TIC54X-Block,  Up: TIC54X-Dependent
-
-8.29.3 Environment Settings
----------------------------
-
-`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
-to the list of directories normally searched for source and include
-files.  `C54XDSP_DIR' will override `A_DIR'.
-
-
-File: as.info,  Node: TIC54X-Constants,  Next: TIC54X-Subsyms,  Prev: TIC54X-Env,  Up: TIC54X-Dependent
-
-8.29.4 Constants Syntax
------------------------
-
-The TIC54X version of `as' allows the following additional constant
-formats, using a suffix to indicate the radix:
-
-     Binary                  `000000B, 011000b'
-     Octal                   `10Q, 224q'
-     Hexadecimal             `45h, 0FH'
-
-
-File: as.info,  Node: TIC54X-Subsyms,  Next: TIC54X-Locals,  Prev: TIC54X-Constants,  Up: TIC54X-Dependent
-
-8.29.5 String Substitution
---------------------------
-
-A subset of allowable symbols (which we'll call subsyms) may be assigned
-arbitrary string values.  This is roughly equivalent to C preprocessor
-#define macros.  When `as' encounters one of these symbols, the symbol
-is replaced in the input stream by its string value.  Subsym names
-*must* begin with a letter.
-
-   Subsyms may be defined using the `.asg' and `.eval' directives
-(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives.
-
-   Expansion is recursive until a previously encountered symbol is
-seen, at which point substitution stops.
-
-   In this example, x is replaced with SYM2; SYM2 is replaced with
-SYM1, and SYM1 is replaced with x.  At this point, x has already been
-encountered and the substitution stops.
-
-      .asg   "x",SYM1
-      .asg   "SYM1",SYM2
-      .asg   "SYM2",x
-      add    x,a             ; final code assembled is "add  x, a"
-
-   Macro parameters are converted to subsyms; a side effect of this is
-the normal `as' '\ARG' dereferencing syntax is unnecessary.  Subsyms
-defined within a macro will have global scope, unless the `.var'
-directive is used to identify the subsym as a local macro variable
-*note `.var': TIC54X-Directives.
-
-   Substitution may be forced in situations where replacement might be
-ambiguous by placing colons on either side of the subsym.  The following
-code:
-
-      .eval  "10",x
-     LAB:X:  add     #x, a
-
-   When assembled becomes:
-
-     LAB10  add     #10, a
-
-   Smaller parts of the string assigned to a subsym may be accessed with
-the following syntax:
-
-``:SYMBOL(CHAR_INDEX):''
-     Evaluates to a single-character string, the character at
-     CHAR_INDEX.
-
-``:SYMBOL(START,LENGTH):''
-     Evaluates to a substring of SYMBOL beginning at START with length
-     LENGTH.
-
-
-File: as.info,  Node: TIC54X-Locals,  Next: TIC54X-Builtins,  Prev: TIC54X-Subsyms,  Up: TIC54X-Dependent
-
-8.29.6 Local Labels
--------------------
-
-Local labels may be defined in two ways:
-
-   * $N, where N is a decimal number between 0 and 9
-
-   * LABEL?, where LABEL is any legal symbol name.
-
-   Local labels thus defined may be redefined or automatically
-generated.  The scope of a local label is based on when it may be
-undefined or reset.  This happens when one of the following situations
-is encountered:
-
-   * .newblock directive *note `.newblock': TIC54X-Directives.
-
-   * The current section is changed (.sect, .text, or .data)
-
-   * Entering or leaving an included file
-
-   * The macro scope where the label was defined is exited
-
-
-File: as.info,  Node: TIC54X-Builtins,  Next: TIC54X-Ext,  Prev: TIC54X-Locals,  Up: TIC54X-Dependent
-
-8.29.7 Math Builtins
---------------------
-
-The following built-in functions may be used to generate a
-floating-point value.  All return a floating-point value except `$cvi',
-`$int', and `$sgn', which return an integer value.
-
-``$acos(EXPR)''
-     Returns the floating point arccosine of EXPR.
-
-``$asin(EXPR)''
-     Returns the floating point arcsine of EXPR.
-
-``$atan(EXPR)''
-     Returns the floating point arctangent of EXPR.
-
-``$atan2(EXPR1,EXPR2)''
-     Returns the floating point arctangent of EXPR1 / EXPR2.
-
-``$ceil(EXPR)''
-     Returns the smallest integer not less than EXPR as floating point.
-
-``$cosh(EXPR)''
-     Returns the floating point hyperbolic cosine of EXPR.
-
-``$cos(EXPR)''
-     Returns the floating point cosine of EXPR.
-
-``$cvf(EXPR)''
-     Returns the integer value EXPR converted to floating-point.
-
-``$cvi(EXPR)''
-     Returns the floating point value EXPR converted to integer.
-
-``$exp(EXPR)''
-     Returns the floating point value e ^ EXPR.
-
-``$fabs(EXPR)''
-     Returns the floating point absolute value of EXPR.
-
-``$floor(EXPR)''
-     Returns the largest integer that is not greater than EXPR as
-     floating point.
-
-``$fmod(EXPR1,EXPR2)''
-     Returns the floating point remainder of EXPR1 / EXPR2.
-
-``$int(EXPR)''
-     Returns 1 if EXPR evaluates to an integer, zero otherwise.
-
-``$ldexp(EXPR1,EXPR2)''
-     Returns the floating point value EXPR1 * 2 ^ EXPR2.
-
-``$log10(EXPR)''
-     Returns the base 10 logarithm of EXPR.
-
-``$log(EXPR)''
-     Returns the natural logarithm of EXPR.
-
-``$max(EXPR1,EXPR2)''
-     Returns the floating point maximum of EXPR1 and EXPR2.
-
-``$min(EXPR1,EXPR2)''
-     Returns the floating point minimum of EXPR1 and EXPR2.
-
-``$pow(EXPR1,EXPR2)''
-     Returns the floating point value EXPR1 ^ EXPR2.
-
-``$round(EXPR)''
-     Returns the nearest integer to EXPR as a floating point number.
-
-``$sgn(EXPR)''
-     Returns -1, 0, or 1 based on the sign of EXPR.
-
-``$sin(EXPR)''
-     Returns the floating point sine of EXPR.
-
-``$sinh(EXPR)''
-     Returns the floating point hyperbolic sine of EXPR.
-
-``$sqrt(EXPR)''
-     Returns the floating point square root of EXPR.
-
-``$tan(EXPR)''
-     Returns the floating point tangent of EXPR.
-
-``$tanh(EXPR)''
-     Returns the floating point hyperbolic tangent of EXPR.
-
-``$trunc(EXPR)''
-     Returns the integer value of EXPR truncated towards zero as
-     floating point.
-
-
-
-File: as.info,  Node: TIC54X-Ext,  Next: TIC54X-Directives,  Prev: TIC54X-Builtins,  Up: TIC54X-Dependent
-
-8.29.8 Extended Addressing
---------------------------
-
-The `LDX' pseudo-op is provided for loading the extended addressing bits
-of a label or address.  For example, if an address `_label' resides in
-extended program memory, the value of `_label' may be loaded as follows:
-      ldx     #_label,16,a    ; loads extended bits of _label
-      or      #_label,a       ; loads lower 16 bits of _label
-      bacc    a               ; full address is in accumulator A
-
-
-File: as.info,  Node: TIC54X-Directives,  Next: TIC54X-Macros,  Prev: TIC54X-Ext,  Up: TIC54X-Dependent
-
-8.29.9 Directives
------------------
-
-`.align [SIZE]'
-`.even'
-     Align the section program counter on the next boundary, based on
-     SIZE.  SIZE may be any power of 2.  `.even' is equivalent to
-     `.align' with a SIZE of 2.
-    `1'
-          Align SPC to word boundary
-
-    `2'
-          Align SPC to longword boundary (same as .even)
-
-    `128'
-          Align SPC to page boundary
-
-`.asg STRING, NAME'
-     Assign NAME the string STRING.  String replacement is performed on
-     STRING before assignment.
-
-`.eval STRING, NAME'
-     Evaluate the contents of string STRING and assign the result as a
-     string to the subsym NAME.  String replacement is performed on
-     STRING before assignment.
-
-`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
-     Reserve space for SYMBOL in the .bss section.  SIZE is in words.
-     If present, BLOCKING_FLAG indicates the allocated space should be
-     aligned on a page boundary if it would otherwise cross a page
-     boundary.  If present, ALIGNMENT_FLAG causes the assembler to
-     allocate SIZE on a long word boundary.
-
-`.byte VALUE [,...,VALUE_N]'
-`.ubyte VALUE [,...,VALUE_N]'
-`.char VALUE [,...,VALUE_N]'
-`.uchar VALUE [,...,VALUE_N]'
-     Place one or more bytes into consecutive words of the current
-     section.  The upper 8 bits of each word is zero-filled.  If a
-     label is used, it points to the word allocated for the first byte
-     encountered.
-
-`.clink ["SECTION_NAME"]'
-     Set STYP_CLINK flag for this section, which indicates to the
-     linker that if no symbols from this section are referenced, the
-     section should not be included in the link.  If SECTION_NAME is
-     omitted, the current section is used.
-
-`.c_mode'
-     TBD.
-
-`.copy "FILENAME" | FILENAME'
-`.include "FILENAME" | FILENAME'
-     Read source statements from FILENAME.  The normal include search
-     path is used.  Normally .copy will cause statements from the
-     included file to be printed in the assembly listing and .include
-     will not, but this distinction is not currently implemented.
-
-`.data'
-     Begin assembling code into the .data section.
-
-`.double VALUE [,...,VALUE_N]'
-`.ldouble VALUE [,...,VALUE_N]'
-`.float VALUE [,...,VALUE_N]'
-`.xfloat VALUE [,...,VALUE_N]'
-     Place an IEEE single-precision floating-point representation of
-     one or more floating-point values into the current section.  All
-     but `.xfloat' align the result on a longword boundary.  Values are
-     stored most-significant word first.
-
-`.drlist'
-`.drnolist'
-     Control printing of directives to the listing file.  Ignored.
-
-`.emsg STRING'
-`.mmsg STRING'
-`.wmsg STRING'
-     Emit a user-defined error, message, or warning, respectively.
-
-`.far_mode'
-     Use extended addressing when assembling statements.  This should
-     appear only once per file, and is equivalent to the -mfar-mode
-     option *note `-mfar-mode': TIC54X-Opts.
-
-`.fclist'
-`.fcnolist'
-     Control printing of false conditional blocks to the listing file.
-
-`.field VALUE [,SIZE]'
-     Initialize a bitfield of SIZE bits in the current section.  If
-     VALUE is relocatable, then SIZE must be 16.  SIZE defaults to 16
-     bits.  If VALUE does not fit into SIZE bits, the value will be
-     truncated.  Successive `.field' directives will pack starting at
-     the current word, filling the most significant bits first, and
-     aligning to the start of the next word if the field size does not
-     fit into the space remaining in the current word.  A `.align'
-     directive with an operand of 1 will force the next `.field'
-     directive to begin packing into a new word.  If a label is used, it
-     points to the word that contains the specified field.
-
-`.global SYMBOL [,...,SYMBOL_N]'
-`.def SYMBOL [,...,SYMBOL_N]'
-`.ref SYMBOL [,...,SYMBOL_N]'
-     `.def' nominally identifies a symbol defined in the current file
-     and availalbe to other files.  `.ref' identifies a symbol used in
-     the current file but defined elsewhere.  Both map to the standard
-     `.global' directive.
-
-`.half VALUE [,...,VALUE_N]'
-`.uhalf VALUE [,...,VALUE_N]'
-`.short VALUE [,...,VALUE_N]'
-`.ushort VALUE [,...,VALUE_N]'
-`.int VALUE [,...,VALUE_N]'
-`.uint VALUE [,...,VALUE_N]'
-`.word VALUE [,...,VALUE_N]'
-`.uword VALUE [,...,VALUE_N]'
-     Place one or more values into consecutive words of the current
-     section.  If a label is used, it points to the word allocated for
-     the first value encountered.
-
-`.label SYMBOL'
-     Define a special SYMBOL to refer to the load time address of the
-     current section program counter.
-
-`.length'
-`.width'
-     Set the page length and width of the output listing file.  Ignored.
-
-`.list'
-`.nolist'
-     Control whether the source listing is printed.  Ignored.
-
-`.long VALUE [,...,VALUE_N]'
-`.ulong VALUE [,...,VALUE_N]'
-`.xlong VALUE [,...,VALUE_N]'
-     Place one or more 32-bit values into consecutive words in the
-     current section.  The most significant word is stored first.
-     `.long' and `.ulong' align the result on a longword boundary;
-     `xlong' does not.
-
-`.loop [COUNT]'
-`.break [CONDITION]'
-`.endloop'
-     Repeatedly assemble a block of code.  `.loop' begins the block, and
-     `.endloop' marks its termination.  COUNT defaults to 1024, and
-     indicates the number of times the block should be repeated.
-     `.break' terminates the loop so that assembly begins after the
-     `.endloop' directive.  The optional CONDITION will cause the loop
-     to terminate only if it evaluates to zero.
-
-`MACRO_NAME .macro [PARAM1][,...PARAM_N]'
-`[.mexit]'
-`.endm'
-     See the section on macros for more explanation (*Note
-     TIC54X-Macros::.
-
-`.mlib "FILENAME" | FILENAME'
-     Load the macro library FILENAME.  FILENAME must be an archived
-     library (BFD ar-compatible) of text files, expected to contain
-     only macro definitions.   The standard include search path is used.
-
-`.mlist'
-
-`.mnolist'
-     Control whether to include macro and loop block expansions in the
-     listing output.  Ignored.
-
-`.mmregs'
-     Define global symbolic names for the 'c54x registers.  Supposedly
-     equivalent to executing `.set' directives for each register with
-     its memory-mapped value, but in reality is provided only for
-     compatibility and does nothing.
-
-`.newblock'
-     This directive resets any TIC54X local labels currently defined.
-     Normal `as' local labels are unaffected.
-
-`.option OPTION_LIST'
-     Set listing options.  Ignored.
-
-`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
-     Designate SECTION_NAME for blocking.  Blocking guarantees that a
-     section will start on a page boundary (128 words) if it would
-     otherwise cross a page boundary.  Only initialized sections may be
-     designated with this directive.  See also *Note TIC54X-Block::.
-
-`.sect "SECTION_NAME"'
-     Define a named initialized section and make it the current section.
-
-`SYMBOL .set "VALUE"'
-`SYMBOL .equ "VALUE"'
-     Equate a constant VALUE to a SYMBOL, which is placed in the symbol
-     table.  SYMBOL may not be previously defined.
-
-`.space SIZE_IN_BITS'
-`.bes SIZE_IN_BITS'
-     Reserve the given number of bits in the current section and
-     zero-fill them.  If a label is used with `.space', it points to the
-     *first* word reserved.  With `.bes', the label points to the
-     *last* word reserved.
-
-`.sslist'
-`.ssnolist'
-     Controls the inclusion of subsym replacement in the listing
-     output.  Ignored.
-
-`.string "STRING" [,...,"STRING_N"]'
-`.pstring "STRING" [,...,"STRING_N"]'
-     Place 8-bit characters from STRING into the current section.
-     `.string' zero-fills the upper 8 bits of each word, while
-     `.pstring' puts two characters into each word, filling the
-     most-significant bits first.  Unused space is zero-filled.  If a
-     label is used, it points to the first word initialized.
-
-`[STAG] .struct [OFFSET]'
-`[NAME_1] element [COUNT_1]'
-`[NAME_2] element [COUNT_2]'
-`[TNAME] .tag STAGX [TCOUNT]'
-`...'
-`[NAME_N] element [COUNT_N]'
-`[SSIZE] .endstruct'
-`LABEL .tag [STAG]'
-     Assign symbolic offsets to the elements of a structure.  STAG
-     defines a symbol to use to reference the structure.  OFFSET
-     indicates a starting value to use for the first element
-     encountered; otherwise it defaults to zero.  Each element can have
-     a named offset, NAME, which is a symbol assigned the value of the
-     element's offset into the structure.  If STAG is missing, these
-     become global symbols.  COUNT adjusts the offset that many times,
-     as if `element' were an array.  `element' may be one of `.byte',
-     `.word', `.long', `.float', or any equivalent of those, and the
-     structure offset is adjusted accordingly.  `.field' and `.string'
-     are also allowed; the size of `.field' is one bit, and `.string'
-     is considered to be one word in size.  Only element descriptors,
-     structure/union tags, `.align' and conditional assembly directives
-     are allowed within `.struct'/`.endstruct'.  `.align' aligns member
-     offsets to word boundaries only.  SSIZE, if provided, will always
-     be assigned the size of the structure.
-
-     The `.tag' directive, in addition to being used to define a
-     structure/union element within a structure, may be used to apply a
-     structure to a symbol.  Once applied to LABEL, the individual
-     structure elements may be applied to LABEL to produce the desired
-     offsets using LABEL as the structure base.
-
-`.tab'
-     Set the tab size in the output listing.  Ignored.
-
-`[UTAG] .union'
-`[NAME_1] element [COUNT_1]'
-`[NAME_2] element [COUNT_2]'
-`[TNAME] .tag UTAGX[,TCOUNT]'
-`...'
-`[NAME_N] element [COUNT_N]'
-`[USIZE] .endstruct'
-`LABEL .tag [UTAG]'
-     Similar to `.struct', but the offset after each element is reset to
-     zero, and the USIZE is set to the maximum of all defined elements.
-     Starting offset for the union is always zero.
-
-`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
-     Reserve space for variables in a named, uninitialized section
-     (similar to .bss).  `.usect' allows definitions sections
-     independent of .bss.  SYMBOL points to the first location reserved
-     by this allocation.  The symbol may be used as a variable name.
-     SIZE is the allocated size in words.  BLOCKING_FLAG indicates
-     whether to block this section on a page boundary (128 words)
-     (*note TIC54X-Block::).  ALIGNMENT FLAG indicates whether the
-     section should be longword-aligned.
-
-`.var SYM[,..., SYM_N]'
-     Define a subsym to be a local variable within a macro.  See *Note
-     TIC54X-Macros::.
-
-`.version VERSION'
-     Set which processor to build instructions for.  Though the
-     following values are accepted, the op is ignored.
-    `541'
-    `542'
-    `543'
-    `545'
-    `545LP'
-    `546LP'
-    `548'
-    `549'
-
-
-File: as.info,  Node: TIC54X-Macros,  Next: TIC54X-MMRegs,  Prev: TIC54X-Directives,  Up: TIC54X-Dependent
-
-8.29.10 Macros
---------------
-
-Macros do not require explicit dereferencing of arguments (i.e. \ARG).
-
-   During macro expansion, the macro parameters are converted to
-subsyms.  If the number of arguments passed the macro invocation
-exceeds the number of parameters defined, the last parameter is
-assigned the string equivalent of all remaining arguments.  If fewer
-arguments are given than parameters, the missing parameters are
-assigned empty strings.  To include a comma in an argument, you must
-enclose the argument in quotes.
-
-   The following built-in subsym functions allow examination of the
-string value of subsyms (or ordinary strings).  The arguments are
-strings unless otherwise indicated (subsyms passed as args will be
-replaced by the strings they represent).
-``$symlen(STR)''
-     Returns the length of STR.
-
-``$symcmp(STR1,STR2)''
-     Returns 0 if STR1 == STR2, non-zero otherwise.
-
-``$firstch(STR,CH)''
-     Returns index of the first occurrence of character constant CH in
-     STR.
-
-``$lastch(STR,CH)''
-     Returns index of the last occurrence of character constant CH in
-     STR.
-
-``$isdefed(SYMBOL)''
-     Returns zero if the symbol SYMBOL is not in the symbol table,
-     non-zero otherwise.
-
-``$ismember(SYMBOL,LIST)''
-     Assign the first member of comma-separated string LIST to SYMBOL;
-     LIST is reassigned the remainder of the list.  Returns zero if
-     LIST is a null string.  Both arguments must be subsyms.
-
-``$iscons(EXPR)''
-     Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal,
-     4 if a character, 5 if decimal, and zero if not an integer.
-
-``$isname(NAME)''
-     Returns 1 if NAME is a valid symbol name, zero otherwise.
-
-``$isreg(REG)''
-     Returns 1 if REG is a valid predefined register name (AR0-AR7
-     only).
-
-``$structsz(STAG)''
-     Returns the size of the structure or union represented by STAG.
-
-``$structacc(STAG)''
-     Returns the reference point of the structure or union represented
-     by STAG.   Always returns zero.
-
-
-
-File: as.info,  Node: TIC54X-MMRegs,  Prev: TIC54X-Macros,  Up: TIC54X-Dependent
-
-8.29.11 Memory-mapped Registers
--------------------------------
-
-The following symbols are recognized as memory-mapped registers:
-
-
-
-File: as.info,  Node: Z80-Dependent,  Next: Z8000-Dependent,  Prev: Xtensa-Dependent,  Up: Machine Dependencies
-
-8.30 Z80 Dependent Features
-===========================
-
-* Menu:
-
-* Z80 Options::              Options
-* Z80 Syntax::               Syntax
-* Z80 Floating Point::       Floating Point
-* Z80 Directives::           Z80 Machine Directives
-* Z80 Opcodes::              Opcodes
-
-
-File: as.info,  Node: Z80 Options,  Next: Z80 Syntax,  Up: Z80-Dependent
-
-8.30.1 Options
---------------
-
-The Zilog Z80 and Ascii R800 version of `as' have a few machine
-dependent options.
-`-z80'
-     Produce code for the Z80 processor. There are additional options to
-     request warnings and error messages for undocumented instructions.
-
-`-ignore-undocumented-instructions'
-`-Wnud'
-     Silently assemble undocumented Z80-instructions that have been
-     adopted as documented R800-instructions.
-
-`-ignore-unportable-instructions'
-`-Wnup'
-     Silently assemble all undocumented Z80-instructions.
-
-`-warn-undocumented-instructions'
-`-Wud'
-     Issue warnings for undocumented Z80-instructions that work on
-     R800, do not assemble other undocumented instructions without
-     warning.
-
-`-warn-unportable-instructions'
-`-Wup'
-     Issue warnings for other undocumented Z80-instructions, do not
-     treat any undocumented instructions as errors.
-
-`-forbid-undocumented-instructions'
-`-Fud'
-     Treat all undocumented z80-instructions as errors.
-
-`-forbid-unportable-instructions'
-`-Fup'
-     Treat undocumented z80-instructions that do not work on R800 as
-     errors.
-
-`-r800'
-     Produce code for the R800 processor. The assembler does not support
-     undocumented instructions for the R800.  In line with common
-     practice, `as' uses Z80 instriction names for the R800 processor,
-     as far as they exist.
-
-
-File: as.info,  Node: Z80 Syntax,  Next: Z80 Floating Point,  Prev: Z80 Options,  Up: Z80-Dependent
-
-8.30.2 Syntax
--------------
-
-The assembler syntax closely follows the 'Z80 family CPU User Manual' by
-Zilog.  In expressions a single `=' may be used as "is equal to"
-comparison operator.
-
-   Suffices can be used to indicate the radix of integer constants; `H'
-or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o'
-for octal, and `B' for binary.
-
-   The suffix `b' denotes a backreference to local label.
-
-* Menu:
-
-* Z80-Chars::                Special Characters
-* Z80-Regs::                 Register Names
-* Z80-Case::                 Case Sensitivity
-
-
-File: as.info,  Node: Z80-Chars,  Next: Z80-Regs,  Up: Z80 Syntax
-
-8.30.2.1 Special Characters
-...........................
-
-The semicolon `;' is the line comment character;
-
-   The dollar sign `$' can be used as a prefix for hexadecimal numbers
-and as a symbol denoting the current location counter.
-
-   A backslash `\' is an ordinary character for the Z80 assembler.
-
-   The single quote `'' must be followed by a closing quote. If there
-is one character inbetween, it is a character constant, otherwise it is
-a string constant.
-
-
-File: as.info,  Node: Z80-Regs,  Next: Z80-Case,  Prev: Z80-Chars,  Up: Z80 Syntax
-
-8.30.2.2 Register Names
-.......................
-
-The registers are referred to with the letters assigned to them by
-Zilog. In addition `as' recognises `ixl' and `ixh' as the least and
-most significant octet in `ix', and similarly `iyl' and  `iyh' as parts
-of `iy'.
-
-
-File: as.info,  Node: Z80-Case,  Prev: Z80-Regs,  Up: Z80 Syntax
-
-8.30.2.3 Case Sensitivity
-.........................
-
-Upper and lower case are equivalent in register names, opcodes,
-condition codes  and assembler directives.  The case of letters is
-significant in labels and symbol names. The case is also important to
-distinguish the suffix `b' for a backward reference to a local label
-from the suffix `B' for a number in binary notation.
-
-
-File: as.info,  Node: Z80 Floating Point,  Next: Z80 Directives,  Prev: Z80 Syntax,  Up: Z80-Dependent
-
-8.30.3 Floating Point
----------------------
-
-Floating-point numbers are not supported.
-
-
-File: as.info,  Node: Z80 Directives,  Next: Z80 Opcodes,  Prev: Z80 Floating Point,  Up: Z80-Dependent
-
-8.30.4 Z80 Assembler Directives
--------------------------------
-
-`as' for the Z80 supports some additional directives for compatibility
-with other assemblers.
-
-   These are the additional directives in `as' for the Z80:
-
-`db EXPRESSION|STRING[,EXPRESSION|STRING...]'
-`defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
-     For each STRING the characters are copied to the object file, for
-     each other EXPRESSION the value is stored in one byte.  A warning
-     is issued in case of an overflow.
-
-`dw EXPRESSION[,EXPRESSION...]'
-`defw EXPRESSION[,EXPRESSION...]'
-     For each EXPRESSION the value is stored in two bytes, ignoring
-     overflow.
-
-`d24 EXPRESSION[,EXPRESSION...]'
-`def24 EXPRESSION[,EXPRESSION...]'
-     For each EXPRESSION the value is stored in three bytes, ignoring
-     overflow.
-
-`d32 EXPRESSION[,EXPRESSION...]'
-`def32 EXPRESSION[,EXPRESSION...]'
-     For each EXPRESSION the value is stored in four bytes, ignoring
-     overflow.
-
-`ds COUNT[, VALUE]'
-`defs COUNT[, VALUE]'
-     Fill COUNT bytes in the object file with VALUE, if VALUE is
-     omitted it defaults to zero.
-
-`SYMBOL equ EXPRESSION'
-`SYMBOL defl EXPRESSION'
-     These directives set the value of SYMBOL to EXPRESSION. If `equ'
-     is used, it is an error if SYMBOL is already defined.  Symbols
-     defined with `equ' are not protected from redefinition.
-
-`set'
-     This is a normal instruction on Z80, and not an assembler
-     directive.
-
-`psect NAME'
-     A synonym for *Note Section::, no second argument should be given.
-
-
-
-File: as.info,  Node: Z80 Opcodes,  Prev: Z80 Directives,  Up: Z80-Dependent
-
-8.30.5 Opcodes
---------------
-
-In line with commmon practice Z80 mnonics are used for both the Z80 and
-the R800.
-
-   In many instructions it is possible to use one of the half index
-registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general
-purpose register. This yields instructions that are documented on the
-R800 and undocumented on the Z80.  Similarly `in f,(c)' is documented
-on the R800 and undocumented on the Z80.
-
-   The assembler also supports the following undocumented
-Z80-instructions, that have not been adopted in the R800 instruction
-set:
-`out (c),0'
-     Sends zero to the port pointed to by register c.
-
-`sli M'
-     Equivalent to `M = (M<<1)+1', the operand M can be any operand
-     that is valid for `sla'. One can use `sll' as a synonym for `sli'.
-
-`OP (ix+D), R'
-     This is equivalent to
-
-          ld R, (ix+D)
-          OPC R
-          ld (ix+D), R
-
-     The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc',
-     `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R'
-     may be any of `a', `b', `c', `d', `e', `h' and `l'.
-
-`OPC (iy+D), R'
-     As above, but with `iy' instead of `ix'.
-
-   The web site at `http://www.z80.info' is a good starting place to
-find more information on programming the Z80.
-
-
-File: as.info,  Node: Z8000-Dependent,  Next: Vax-Dependent,  Prev: Z80-Dependent,  Up: Machine Dependencies
-
-8.31 Z8000 Dependent Features
-=============================
-
-   The Z8000 as supports both members of the Z8000 family: the
-unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
-24 bit addresses.
-
-   When the assembler is in unsegmented mode (specified with the
-`unsegm' directive), an address takes up one word (16 bit) sized
-register.  When the assembler is in segmented mode (specified with the
-`segm' directive), a 24-bit address takes up a long (32 bit) register.
-*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
-of other Z8000 specific assembler directives.
-
-* Menu:
-
-* Z8000 Options::               Command-line options for the Z8000
-* Z8000 Syntax::                Assembler syntax for the Z8000
-* Z8000 Directives::            Special directives for the Z8000
-* Z8000 Opcodes::               Opcodes
-
-
-File: as.info,  Node: Z8000 Options,  Next: Z8000 Syntax,  Up: Z8000-Dependent
-
-8.31.1 Options
---------------
-
-`-z8001'
-     Generate segmented code by default.
-
-`-z8002'
-     Generate unsegmented code by default.
-
-
-File: as.info,  Node: Z8000 Syntax,  Next: Z8000 Directives,  Prev: Z8000 Options,  Up: Z8000-Dependent
-
-8.31.2 Syntax
--------------
-
-* Menu:
-
-* Z8000-Chars::                Special Characters
-* Z8000-Regs::                 Register Names
-* Z8000-Addressing::           Addressing Modes
-
-
-File: as.info,  Node: Z8000-Chars,  Next: Z8000-Regs,  Up: Z8000 Syntax
-
-8.31.2.1 Special Characters
-...........................
-
-`!' is the line comment character.
-
-   You can use `;' instead of a newline to separate statements.
-
-
-File: as.info,  Node: Z8000-Regs,  Next: Z8000-Addressing,  Prev: Z8000-Chars,  Up: Z8000 Syntax
-
-8.31.2.2 Register Names
-.......................
-
-The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can refer
-to different sized groups of registers by register number, with the
-prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
-64 bit registers.  You can also refer to the contents of the first
-eight (of the sixteen 16 bit registers) by bytes.  They are named `rlN'
-and `rhN'.
-
-_byte registers_
-     rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
-     rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
-
-_word registers_
-     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
-
-_long word registers_
-     rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
-
-_quad word registers_
-     rq0 rq4 rq8 rq12
-
-
-File: as.info,  Node: Z8000-Addressing,  Prev: Z8000-Regs,  Up: Z8000 Syntax
-
-8.31.2.3 Addressing Modes
-.........................
-
-as understands the following addressing modes for the Z8000:
-
-`rlN'
-`rhN'
-`rN'
-`rrN'
-`rqN'
-     Register direct:  8bit, 16bit, 32bit, and 64bit registers.
-
-`@rN'
-`@rrN'
-     Indirect register:  @rrN in segmented mode, @rN in unsegmented
-     mode.
-
-`ADDR'
-     Direct: the 16 bit or 24 bit address (depending on whether the
-     assembler is in segmented or unsegmented mode) of the operand is
-     in the instruction.
-
-`address(rN)'
-     Indexed: the 16 or 24 bit address is added to the 16 bit register
-     to produce the final address in memory of the operand.
-
-`rN(#IMM)'
-`rrN(#IMM)'
-     Base Address: the 16 or 24 bit register is added to the 16 bit sign
-     extended immediate displacement to produce the final address in
-     memory of the operand.
-
-`rN(rM)'
-`rrN(rM)'
-     Base Index: the 16 or 24 bit register rN or rrN is added to the
-     sign extended 16 bit index register rM to produce the final
-     address in memory of the operand.
-
-`#XX'
-     Immediate data XX.
-
-
-File: as.info,  Node: Z8000 Directives,  Next: Z8000 Opcodes,  Prev: Z8000 Syntax,  Up: Z8000-Dependent
-
-8.31.3 Assembler Directives for the Z8000
------------------------------------------
-
-The Z8000 port of as includes additional assembler directives, for
-compatibility with other Z8000 assemblers.  These do not begin with `.'
-(unlike the ordinary as directives).
-
-`segm'
-`.z8001'
-     Generate code for the segmented Z8001.
-
-`unsegm'
-`.z8002'
-     Generate code for the unsegmented Z8002.
-
-`name'
-     Synonym for `.file'
-
-`global'
-     Synonym for `.global'
-
-`wval'
-     Synonym for `.word'
-
-`lval'
-     Synonym for `.long'
-
-`bval'
-     Synonym for `.byte'
-
-`sval'
-     Assemble a string.  `sval' expects one string literal, delimited by
-     single quotes.  It assembles each byte of the string into
-     consecutive addresses.  You can use the escape sequence `%XX'
-     (where XX represents a two-digit hexadecimal number) to represent
-     the character whose ASCII value is XX.  Use this feature to
-     describe single quote and other characters that may not appear in
-     string literals as themselves.  For example, the C statement
-     `char *a = "he said \"it's 50% off\"";' is represented in Z8000
-     assembly language (shown with the assembler output in hex at the
-     left) as
-
-          68652073    sval    'he said %22it%27s 50%25 off%22%00'
-          61696420
-          22697427
-          73203530
-          25206F66
-          662200
-
-`rsect'
-     synonym for `.section'
-
-`block'
-     synonym for `.space'
-
-`even'
-     special case of `.align'; aligns output to even byte boundary.
-
-
-File: as.info,  Node: Z8000 Opcodes,  Prev: Z8000 Directives,  Up: Z8000-Dependent
-
-8.31.4 Opcodes
---------------
-
-For detailed information on the Z8000 machine instruction set, see
-`Z8000 Technical Manual'.
-
-   The following table summarizes the opcodes and their arguments:
-
-                 rs   16 bit source register
-                 rd   16 bit destination register
-                 rbs   8 bit source register
-                 rbd   8 bit destination register
-                 rrs   32 bit source register
-                 rrd   32 bit destination register
-                 rqs   64 bit source register
-                 rqd   64 bit destination register
-                 addr 16/24 bit address
-                 imm  immediate data
-
-     adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
-     adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
-     add rd,@rs              clrb rbd                dab rbd
-     add rd,addr             com @rd                 dbjnz rbd,disp7
-     add rd,addr(rs)         com addr                dec @rd,imm4m1
-     add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
-     add rd,rs               com rd                  dec addr,imm4m1
-     addb rbd,@rs            comb @rd                dec rd,imm4m1
-     addb rbd,addr           comb addr               decb @rd,imm4m1
-     addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
-     addb rbd,imm8           comb rbd                decb addr,imm4m1
-     addb rbd,rbs            comflg flags            decb rbd,imm4m1
-     addl rrd,@rs            cp @rd,imm16            di i2
-     addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
-     addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
-     addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
-     addl rrd,rrs            cp rd,addr              div rrd,imm16
-     and rd,@rs              cp rd,addr(rs)          div rrd,rs
-     and rd,addr             cp rd,imm16             divl rqd,@rs
-     and rd,addr(rs)         cp rd,rs                divl rqd,addr
-     and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
-     and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
-     andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
-     andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
-     andb rbd,addr(rs)       cpb rbd,addr            ei i2
-     andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
-     andb rbd,rbs            cpb rbd,imm8            ex rd,addr
-     bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
-     bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
-     bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
-     bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
-     bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
-     bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
-     bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
-     bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
-     bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
-     bitb rbd,rs             cpl rrd,@rs             ext8f imm8
-     bpt                     cpl rrd,addr            exts rrd
-     call @rd                cpl rrd,addr(rs)        extsb rd
-     call addr               cpl rrd,imm32           extsl rqd
-     call addr(rd)           cpl rrd,rrs             halt
-     calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
-     clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
-     clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
-     clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
-     clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
-     clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
-     inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
-     inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
-     incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
-     incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
-     incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
-     incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
-     ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
-     indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
-     inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
-     inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
-     iret                    ldib @rd,@rs,rr         neg addr(rd)
-     jp cc,@rd               ldir @rd,@rs,rr         neg rd
-     jp cc,addr              ldirb @rd,@rs,rr        negb @rd
-     jp cc,addr(rd)          ldk rd,imm4             negb addr
-     jr cc,disp8             ldl @rd,rrs             negb addr(rd)
-     ld @rd,imm16            ldl addr(rd),rrs        negb rbd
-     ld @rd,rs               ldl addr,rrs            nop
-     ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
-     ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
-     ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
-     ld addr,rs              ldl rrd,addr            or rd,imm16
-     ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
-     ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
-     ld rd,@rs               ldl rrd,rrs             orb rbd,addr
-     ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
-     ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
-     ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
-     ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
-     ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
-     ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
-     lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
-     lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
-     lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
-     lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
-     ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
-     ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
-     ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
-     ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
-     ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
-     ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
-     ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
-     ldb rbd,@rs             mbit                    popl addr,@rs
-     ldb rbd,addr            mreq rd                 popl rrd,@rs
-     ldb rbd,addr(rs)        mres                    push @rd,@rs
-     ldb rbd,imm8            mset                    push @rd,addr
-     ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
-     ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
-     push @rd,rs             set addr,imm4           subl rrd,imm32
-     pushl @rd,@rs           set rd,imm4             subl rrd,rrs
-     pushl @rd,addr          set rd,rs               tcc cc,rd
-     pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
-     pushl @rd,rrs           setb addr(rd),imm4      test @rd
-     res @rd,imm4            setb addr,imm4          test addr
-     res addr(rd),imm4       setb rbd,imm4           test addr(rd)
-     res addr,imm4           setb rbd,rs             test rd
-     res rd,imm4             setflg imm4             testb @rd
-     res rd,rs               sinb rbd,imm16          testb addr
-     resb @rd,imm4           sinb rd,imm16           testb addr(rd)
-     resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
-     resb addr,imm4          sindb @rd,@rs,rba       testl @rd
-     resb rbd,imm4           sinib @rd,@rs,ra        testl addr
-     resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
-     resflg imm4             sla rd,imm8             testl rrd
-     ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
-     rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
-     rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
-     rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
-     rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
-     rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
-     rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
-     rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
-     rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
-     rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
-     rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
-     rsvd36                  sra rd,imm8             tset rd
-     rsvd38                  srab rbd,imm8           tsetb @rd
-     rsvd78                  sral rrd,imm8           tsetb addr
-     rsvd7e                  srl rd,imm8             tsetb addr(rd)
-     rsvd9d                  srlb rbd,imm8           tsetb rbd
-     rsvd9f                  srll rrd,imm8           xor rd,@rs
-     rsvdb9                  sub rd,@rs              xor rd,addr
-     rsvdbf                  sub rd,addr             xor rd,addr(rs)
-     sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
-     sbcb rbd,rbs            sub rd,imm16            xor rd,rs
-     sc imm8                 sub rd,rs               xorb rbd,@rs
-     sda rd,rs               subb rbd,@rs            xorb rbd,addr
-     sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
-     sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
-     sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
-     sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
-     sdll rrd,rs             subl rrd,@rs
-     set @rd,imm4            subl rrd,addr
-     set addr(rd),imm4       subl rrd,addr(rs)
-
-
-File: as.info,  Node: Vax-Dependent,  Prev: Z8000-Dependent,  Up: Machine Dependencies
-
-8.32 VAX Dependent Features
-===========================
-
-* Menu:
-
-* VAX-Opts::                    VAX Command-Line Options
-* VAX-float::                   VAX Floating Point
-* VAX-directives::              Vax Machine Directives
-* VAX-opcodes::                 VAX Opcodes
-* VAX-branch::                  VAX Branch Improvement
-* VAX-operands::                VAX Operands
-* VAX-no::                      Not Supported on VAX
-
-
-File: as.info,  Node: VAX-Opts,  Next: VAX-float,  Up: Vax-Dependent
-
-8.32.1 VAX Command-Line Options
--------------------------------
-
-The Vax version of `as' accepts any of the following options, gives a
-warning message that the option was ignored and proceeds.  These
-options are for compatibility with scripts designed for other people's
-assemblers.
-
-``-D' (Debug)'
-``-S' (Symbol Table)'
-``-T' (Token Trace)'
-     These are obsolete options used to debug old assemblers.
-
-``-d' (Displacement size for JUMPs)'
-     This option expects a number following the `-d'.  Like options
-     that expect filenames, the number may immediately follow the `-d'
-     (old standard) or constitute the whole of the command line
-     argument that follows `-d' (GNU standard).
-
-``-V' (Virtualize Interpass Temporary File)'
-     Some other assemblers use a temporary file.  This option commanded
-     them to keep the information in active memory rather than in a
-     disk file.  `as' always does this, so this option is redundant.
-
-``-J' (JUMPify Longer Branches)'
-     Many 32-bit computers permit a variety of branch instructions to
-     do the same job.  Some of these instructions are short (and fast)
-     but have a limited range; others are long (and slow) but can
-     branch anywhere in virtual memory.  Often there are 3 flavors of
-     branch: short, medium and long.  Some other assemblers would emit
-     short and medium branches, unless told by this option to emit
-     short and long branches.
-
-``-t' (Temporary File Directory)'
-     Some other assemblers may use a temporary file, and this option
-     takes a filename being the directory to site the temporary file.
-     Since `as' does not use a temporary disk file, this option makes
-     no difference.  `-t' needs exactly one filename.
-
-   The Vax version of the assembler accepts additional options when
-compiled for VMS:
-
-`-h N'
-     External symbol or section (used for global variables) names are
-     not case sensitive on VAX/VMS and always mapped to upper case.
-     This is contrary to the C language definition which explicitly
-     distinguishes upper and lower case.  To implement a standard
-     conforming C compiler, names must be changed (mapped) to preserve
-     the case information.  The default mapping is to convert all lower
-     case characters to uppercase and adding an underscore followed by
-     a 6 digit hex value, representing a 24 digit binary value.  The
-     one digits in the binary value represent which characters are
-     uppercase in the original symbol name.
-
-     The `-h N' option determines how we map names.  This takes several
-     values.  No `-h' switch at all allows case hacking as described
-     above.  A value of zero (`-h0') implies names should be upper
-     case, and inhibits the case hack.  A value of 2 (`-h2') implies
-     names should be all lower case, with no case hack.  A value of 3
-     (`-h3') implies that case should be preserved.  The value 1 is
-     unused.  The `-H' option directs `as' to display every mapped
-     symbol during assembly.
-
-     Symbols whose names include a dollar sign `$' are exceptions to the
-     general name mapping.  These symbols are normally only used to
-     reference VMS library names.  Such symbols are always mapped to
-     upper case.
-
-`-+'
-     The `-+' option causes `as' to truncate any symbol name larger
-     than 31 characters.  The `-+' option also prevents some code
-     following the `_main' symbol normally added to make the object
-     file compatible with Vax-11 "C".
-
-`-1'
-     This option is ignored for backward compatibility with `as'
-     version 1.x.
-
-`-H'
-     The `-H' option causes `as' to print every symbol which was
-     changed by case mapping.
-
-
-File: as.info,  Node: VAX-float,  Next: VAX-directives,  Prev: VAX-Opts,  Up: Vax-Dependent
-
-8.32.2 VAX Floating Point
--------------------------
-
-Conversion of flonums to floating point is correct, and compatible with
-previous assemblers.  Rounding is towards zero if the remainder is
-exactly half the least significant bit.
-
-   `D', `F', `G' and `H' floating point formats are understood.
-
-   Immediate floating literals (_e.g._ `S`$6.9') are rendered
-correctly.  Again, rounding is towards zero in the boundary case.
-
-   The `.float' directive produces `f' format numbers.  The `.double'
-directive produces `d' format numbers.
-
-
-File: as.info,  Node: VAX-directives,  Next: VAX-opcodes,  Prev: VAX-float,  Up: Vax-Dependent
-
-8.32.3 Vax Machine Directives
------------------------------
-
-The Vax version of the assembler supports four directives for
-generating Vax floating point constants.  They are described in the
-table below.
-
-`.dfloat'
-     This expects zero or more flonums, separated by commas, and
-     assembles Vax `d' format 64-bit floating point constants.
-
-`.ffloat'
-     This expects zero or more flonums, separated by commas, and
-     assembles Vax `f' format 32-bit floating point constants.
-
-`.gfloat'
-     This expects zero or more flonums, separated by commas, and
-     assembles Vax `g' format 64-bit floating point constants.
-
-`.hfloat'
-     This expects zero or more flonums, separated by commas, and
-     assembles Vax `h' format 128-bit floating point constants.
-
-
-
-File: as.info,  Node: VAX-opcodes,  Next: VAX-branch,  Prev: VAX-directives,  Up: Vax-Dependent
-
-8.32.4 VAX Opcodes
-------------------
-
-All DEC mnemonics are supported.  Beware that `case...' instructions
-have exactly 3 operands.  The dispatch table that follows the `case...'
-instruction should be made with `.word' statements.  This is compatible
-with all unix assemblers we know of.
-
-
-File: as.info,  Node: VAX-branch,  Next: VAX-operands,  Prev: VAX-opcodes,  Up: Vax-Dependent
-
-8.32.5 VAX Branch Improvement
------------------------------
-
-Certain pseudo opcodes are permitted.  They are for branch
-instructions.  They expand to the shortest branch instruction that
-reaches the target.  Generally these mnemonics are made by substituting
-`j' for `b' at the start of a DEC mnemonic.  This feature is included
-both for compatibility and to help compilers.  If you do not need this
-feature, avoid these opcodes.  Here are the mnemonics, and the code
-they can expand into.
-
-`jbsb'
-     `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
-    (byte displacement)
-          `bsbb ...'
-
-    (word displacement)
-          `bsbw ...'
-
-    (long displacement)
-          `jsb ...'
-
-`jbr'
-`jr'
-     Unconditional branch.
-    (byte displacement)
-          `brb ...'
-
-    (word displacement)
-          `brw ...'
-
-    (long displacement)
-          `jmp ...'
-
-`jCOND'
-     COND may be any one of the conditional branches `neq', `nequ',
-     `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
-     `gequ', `cc', `lssu', `cs'.  COND may also be one of the bit tests
-     `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
-     `lbc'.  NOTCOND is the opposite condition to COND.
-    (byte displacement)
-          `bCOND ...'
-
-    (word displacement)
-          `bNOTCOND foo ; brw ... ; foo:'
-
-    (long displacement)
-          `bNOTCOND foo ; jmp ... ; foo:'
-
-`jacbX'
-     X may be one of `b d f g h l w'.
-    (word displacement)
-          `OPCODE ...'
-
-    (long displacement)
-               OPCODE ..., foo ;
-               brb bar ;
-               foo: jmp ... ;
-               bar:
-
-`jaobYYY'
-     YYY may be one of `lss leq'.
-
-`jsobZZZ'
-     ZZZ may be one of `geq gtr'.
-    (byte displacement)
-          `OPCODE ...'
-
-    (word displacement)
-               OPCODE ..., foo ;
-               brb bar ;
-               foo: brw DESTINATION ;
-               bar:
-
-    (long displacement)
-               OPCODE ..., foo ;
-               brb bar ;
-               foo: jmp DESTINATION ;
-               bar:
-
-`aobleq'
-`aoblss'
-`sobgeq'
-`sobgtr'
-
-    (byte displacement)
-          `OPCODE ...'
-
-    (word displacement)
-               OPCODE ..., foo ;
-               brb bar ;
-               foo: brw DESTINATION ;
-               bar:
-
-    (long displacement)
-               OPCODE ..., foo ;
-               brb bar ;
-               foo: jmp DESTINATION ;
-               bar:
-
-
-File: as.info,  Node: VAX-operands,  Next: VAX-no,  Prev: VAX-branch,  Up: Vax-Dependent
-
-8.32.6 VAX Operands
--------------------
-
-The immediate character is `$' for Unix compatibility, not `#' as DEC
-writes it.
-
-   The indirect character is `*' for Unix compatibility, not `@' as DEC
-writes it.
-
-   The displacement sizing character is ``' (an accent grave) for Unix
-compatibility, not `^' as DEC writes it.  The letter preceding ``' may
-have either case.  `G' is not understood, but all other letters (`b i l
-s w') are understood.
-
-   Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'.  Upper
-and lower case letters are equivalent.
-
-   For instance
-     tstb *w`$4(r5)
-
-   Any expression is permitted in an operand.  Operands are comma
-separated.
-
-
-File: as.info,  Node: VAX-no,  Prev: VAX-operands,  Up: Vax-Dependent
-
-8.32.7 Not Supported on VAX
----------------------------
-
-Vax bit fields can not be assembled with `as'.  Someone can add the
-required code if they really need it.
-
-
-File: as.info,  Node: V850-Dependent,  Next: Xtensa-Dependent,  Prev: TIC54X-Dependent,  Up: Machine Dependencies
-
-8.33 v850 Dependent Features
-============================
-
-* Menu:
-
-* V850 Options::              Options
-* V850 Syntax::               Syntax
-* V850 Floating Point::       Floating Point
-* V850 Directives::           V850 Machine Directives
-* V850 Opcodes::              Opcodes
-
-
-File: as.info,  Node: V850 Options,  Next: V850 Syntax,  Up: V850-Dependent
-
-8.33.1 Options
---------------
-
-`as' supports the following additional command-line options for the
-V850 processor family:
-
-`-wsigned_overflow'
-     Causes warnings to be produced when signed immediate values
-     overflow the space available for then within their opcodes.  By
-     default this option is disabled as it is possible to receive
-     spurious warnings due to using exact bit patterns as immediate
-     constants.
-
-`-wunsigned_overflow'
-     Causes warnings to be produced when unsigned immediate values
-     overflow the space available for then within their opcodes.  By
-     default this option is disabled as it is possible to receive
-     spurious warnings due to using exact bit patterns as immediate
-     constants.
-
-`-mv850'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850 processor.  This allows the linker to detect
-     attempts to link such code with code assembled for other
-     processors.
-
-`-mv850e'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850E processor.  This allows the linker to detect
-     attempts to link such code with code assembled for other
-     processors.
-
-`-mv850e1'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850E1 processor.  This allows the linker to
-     detect attempts to link such code with code assembled for other
-     processors.
-
-`-mv850any'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850 processor but support instructions that are
-     specific to the extended variants of the process.  This allows the
-     production of binaries that contain target specific code, but
-     which are also intended to be used in a generic fashion.  For
-     example libgcc.a contains generic routines used by the code
-     produced by GCC for all versions of the v850 architecture,
-     together with support routines only used by the V850E architecture.
-
-`-mrelax'
-     Enables relaxation.  This allows the .longcall and .longjump pseudo
-     ops to be used in the assembler source code.  These ops label
-     sections of code which are either a long function call or a long
-     branch.  The assembler will then flag these sections of code and
-     the linker will attempt to relax them.
-
-
-
-File: as.info,  Node: V850 Syntax,  Next: V850 Floating Point,  Prev: V850 Options,  Up: V850-Dependent
-
-8.33.2 Syntax
--------------
-
-* Menu:
-
-* V850-Chars::                Special Characters
-* V850-Regs::                 Register Names
-
-
-File: as.info,  Node: V850-Chars,  Next: V850-Regs,  Up: V850 Syntax
-
-8.33.2.1 Special Characters
-...........................
-
-`#' is the line comment character.
-
-
-File: as.info,  Node: V850-Regs,  Prev: V850-Chars,  Up: V850 Syntax
-
-8.33.2.2 Register Names
-.......................
-
-`as' supports the following names for registers:
-`general register 0'
-     r0, zero
-
-`general register 1'
-     r1
-
-`general register 2'
-     r2, hp 
-
-`general register 3'
-     r3, sp 
-
-`general register 4'
-     r4, gp 
-
-`general register 5'
-     r5, tp
-
-`general register 6'
-     r6
-
-`general register 7'
-     r7
-
-`general register 8'
-     r8
-
-`general register 9'
-     r9
-
-`general register 10'
-     r10
-
-`general register 11'
-     r11
-
-`general register 12'
-     r12
-
-`general register 13'
-     r13
-
-`general register 14'
-     r14
-
-`general register 15'
-     r15
-
-`general register 16'
-     r16
-
-`general register 17'
-     r17
-
-`general register 18'
-     r18
-
-`general register 19'
-     r19
-
-`general register 20'
-     r20
-
-`general register 21'
-     r21
-
-`general register 22'
-     r22
-
-`general register 23'
-     r23
-
-`general register 24'
-     r24
-
-`general register 25'
-     r25
-
-`general register 26'
-     r26
-
-`general register 27'
-     r27
-
-`general register 28'
-     r28
-
-`general register 29'
-     r29 
-
-`general register 30'
-     r30, ep 
-
-`general register 31'
-     r31, lp 
-
-`system register 0'
-     eipc 
-
-`system register 1'
-     eipsw 
-
-`system register 2'
-     fepc 
-
-`system register 3'
-     fepsw 
-
-`system register 4'
-     ecr 
-
-`system register 5'
-     psw 
-
-`system register 16'
-     ctpc 
-
-`system register 17'
-     ctpsw 
-
-`system register 18'
-     dbpc 
-
-`system register 19'
-     dbpsw 
-
-`system register 20'
-     ctbp
-
-
-File: as.info,  Node: V850 Floating Point,  Next: V850 Directives,  Prev: V850 Syntax,  Up: V850-Dependent
-
-8.33.3 Floating Point
----------------------
-
-The V850 family uses IEEE floating-point numbers.
-
-
-File: as.info,  Node: V850 Directives,  Next: V850 Opcodes,  Prev: V850 Floating Point,  Up: V850-Dependent
-
-8.33.4 V850 Machine Directives
-------------------------------
-
-`.offset <EXPRESSION>'
-     Moves the offset into the current section to the specified amount.
-
-`.section "name", <type>'
-     This is an extension to the standard .section directive.  It sets
-     the current section to be <type> and creates an alias for this
-     section called "name".
-
-`.v850'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850 processor.  This allows the linker to detect
-     attempts to link such code with code assembled for other
-     processors.
-
-`.v850e'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850E processor.  This allows the linker to detect
-     attempts to link such code with code assembled for other
-     processors.
-
-`.v850e1'
-     Specifies that the assembled code should be marked as being
-     targeted at the V850E1 processor.  This allows the linker to
-     detect attempts to link such code with code assembled for other
-     processors.
-
-
-
-File: as.info,  Node: V850 Opcodes,  Prev: V850 Directives,  Up: V850-Dependent
-
-8.33.5 Opcodes
---------------
-
-`as' implements all the standard V850 opcodes.
-
-   `as' also implements the following pseudo ops:
-
-`hi0()'
-     Computes the higher 16 bits of the given expression and stores it
-     into the immediate operand field of the given instruction.  For
-     example:
-
-     `mulhi hi0(here - there), r5, r6'
-
-     computes the difference between the address of labels 'here' and
-     'there', takes the upper 16 bits of this difference, shifts it
-     down 16 bits and then mutliplies it by the lower 16 bits in
-     register 5, putting the result into register 6.
-
-`lo()'
-     Computes the lower 16 bits of the given expression and stores it
-     into the immediate operand field of the given instruction.  For
-     example:
-
-     `addi lo(here - there), r5, r6'
-
-     computes the difference between the address of labels 'here' and
-     'there', takes the lower 16 bits of this difference and adds it to
-     register 5, putting the result into register 6.
-
-`hi()'
-     Computes the higher 16 bits of the given expression and then adds
-     the value of the most significant bit of the lower 16 bits of the
-     expression and stores the result into the immediate operand field
-     of the given instruction.  For example the following code can be
-     used to compute the address of the label 'here' and store it into
-     register 6:
-
-     `movhi hi(here), r0, r6'     `movea lo(here), r6, r6'
-
-     The reason for this special behaviour is that movea performs a sign
-     extension on its immediate operand.  So for example if the address
-     of 'here' was 0xFFFFFFFF then without the special behaviour of the
-     hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
-     then the movea instruction would takes its immediate operand,
-     0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
-     into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
-     With the hi() pseudo op adding in the top bit of the lo() pseudo
-     op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
-     0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
-     the right value.
-
-`hilo()'
-     Computes the 32 bit value of the given expression and stores it
-     into the immediate operand field of the given instruction (which
-     must be a mov instruction).  For example:
-
-     `mov hilo(here), r6'
-
-     computes the absolute address of label 'here' and puts the result
-     into register 6.
-
-`sdaoff()'
-     Computes the offset of the named variable from the start of the
-     Small Data Area (whoes address is held in register 4, the GP
-     register) and stores the result as a 16 bit signed value in the
-     immediate operand field of the given instruction.  For example:
-
-     `ld.w sdaoff(_a_variable)[gp],r6'
-
-     loads the contents of the location pointed to by the label
-     '_a_variable' into register 6, provided that the label is located
-     somewhere within +/- 32K of the address held in the GP register.
-     [Note the linker assumes that the GP register contains a fixed
-     address set to the address of the label called '__gp'.  This can
-     either be set up automatically by the linker, or specifically set
-     by using the `--defsym __gp=<value>' command line option].
-
-`tdaoff()'
-     Computes the offset of the named variable from the start of the
-     Tiny Data Area (whoes address is held in register 30, the EP
-     register) and stores the result as a 4,5, 7 or 8 bit unsigned
-     value in the immediate operand field of the given instruction.
-     For example:
-
-     `sld.w tdaoff(_a_variable)[ep],r6'
-
-     loads the contents of the location pointed to by the label
-     '_a_variable' into register 6, provided that the label is located
-     somewhere within +256 bytes of the address held in the EP
-     register.  [Note the linker assumes that the EP register contains
-     a fixed address set to the address of the label called '__ep'.
-     This can either be set up automatically by the linker, or
-     specifically set by using the `--defsym __ep=<value>' command line
-     option].
-
-`zdaoff()'
-     Computes the offset of the named variable from address 0 and
-     stores the result as a 16 bit signed value in the immediate
-     operand field of the given instruction.  For example:
-
-     `movea zdaoff(_a_variable),zero,r6'
-
-     puts the address of the label '_a_variable' into register 6,
-     assuming that the label is somewhere within the first 32K of
-     memory.  (Strictly speaking it also possible to access the last
-     32K of memory as well, as the offsets are signed).
-
-`ctoff()'
-     Computes the offset of the named variable from the start of the
-     Call Table Area (whoes address is helg in system register 20, the
-     CTBP register) and stores the result a 6 or 16 bit unsigned value
-     in the immediate field of then given instruction or piece of data.
-     For example:
-
-     `callt ctoff(table_func1)'
-
-     will put the call the function whoes address is held in the call
-     table at the location labeled 'table_func1'.
-
-`.longcall `name''
-     Indicates that the following sequence of instructions is a long
-     call to function `name'.  The linker will attempt to shorten this
-     call sequence if `name' is within a 22bit offset of the call.  Only
-     valid if the `-mrelax' command line switch has been enabled.
-
-`.longjump `name''
-     Indicates that the following sequence of instructions is a long
-     jump to label `name'.  The linker will attempt to shorten this code
-     sequence if `name' is within a 22bit offset of the jump.  Only
-     valid if the `-mrelax' command line switch has been enabled.
-
-
-   For information on the V850 instruction set, see `V850 Family
-32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
-Ltd.
-
-
-File: as.info,  Node: Xtensa-Dependent,  Next: Z80-Dependent,  Prev: V850-Dependent,  Up: Machine Dependencies
-
-8.34 Xtensa Dependent Features
-==============================
-
-   This chapter covers features of the GNU assembler that are specific
-to the Xtensa architecture.  For details about the Xtensa instruction
-set, please consult the `Xtensa Instruction Set Architecture (ISA)
-Reference Manual'.
-
-* Menu:
-
-* Xtensa Options::              Command-line Options.
-* Xtensa Syntax::               Assembler Syntax for Xtensa Processors.
-* Xtensa Optimizations::        Assembler Optimizations.
-* Xtensa Relaxation::           Other Automatic Transformations.
-* Xtensa Directives::           Directives for Xtensa Processors.
-
-
-File: as.info,  Node: Xtensa Options,  Next: Xtensa Syntax,  Up: Xtensa-Dependent
-
-8.34.1 Command Line Options
----------------------------
-
-The Xtensa version of the GNU assembler supports these special options:
-
-`--text-section-literals | --no-text-section-literals'
-     Control the treatment of literal pools.  The default is
-     `--no-text-section-literals', which places literals in a separate
-     section in the output file.  This allows the literal pool to be
-     placed in a data RAM/ROM.  With `--text-section-literals', the
-     literals are interspersed in the text section in order to keep
-     them as close as possible to their references.  This may be
-     necessary for large assembly files, where the literals would
-     otherwise be out of range of the `L32R' instructions in the text
-     section.  These options only affect literals referenced via
-     PC-relative `L32R' instructions; literals for absolute mode `L32R'
-     instructions are handled separately.
-
-`--absolute-literals | --no-absolute-literals'
-     Indicate to the assembler whether `L32R' instructions use absolute
-     or PC-relative addressing.  If the processor includes the absolute
-     addressing option, the default is to use absolute `L32R'
-     relocations.  Otherwise, only the PC-relative `L32R' relocations
-     can be used.
-
-`--target-align | --no-target-align'
-     Enable or disable automatic alignment to reduce branch penalties
-     at some expense in code size.  *Note Automatic Instruction
-     Alignment: Xtensa Automatic Alignment.  This optimization is
-     enabled by default.  Note that the assembler will always align
-     instructions like `LOOP' that have fixed alignment requirements.
-
-`--longcalls | --no-longcalls'
-     Enable or disable transformation of call instructions to allow
-     calls across a greater range of addresses.  *Note Function Call
-     Relaxation: Xtensa Call Relaxation.  This option should be used
-     when call targets can potentially be out of range.  It may degrade
-     both code size and performance, but the linker can generally
-     optimize away the unnecessary overhead when a call ends up within
-     range.  The default is `--no-longcalls'.
-
-`--transform | --no-transform'
-     Enable or disable all assembler transformations of Xtensa
-     instructions, including both relaxation and optimization.  The
-     default is `--transform'; `--no-transform' should only be used in
-     the rare cases when the instructions must be exactly as specified
-     in the assembly source.  Using `--no-transform' causes out of range
-     instruction operands to be errors.
-
-`--rename-section OLDNAME=NEWNAME'
-     Rename the OLDNAME section to NEWNAME.  This option can be used
-     multiple times to rename multiple sections.
-
-
-File: as.info,  Node: Xtensa Syntax,  Next: Xtensa Optimizations,  Prev: Xtensa Options,  Up: Xtensa-Dependent
-
-8.34.2 Assembler Syntax
------------------------
-
-Block comments are delimited by `/*' and `*/'.  End of line comments
-may be introduced with either `#' or `//'.
-
-   Instructions consist of a leading opcode or macro name followed by
-whitespace and an optional comma-separated list of operands:
-
-     OPCODE [OPERAND, ...]
-
-   Instructions must be separated by a newline or semicolon.
-
-   FLIX instructions, which bundle multiple opcodes together in a single
-instruction, are specified by enclosing the bundled opcodes inside
-braces:
-
-     {
-     [FORMAT]
-     OPCODE0 [OPERANDS]
-     OPCODE1 [OPERANDS]
-     OPCODE2 [OPERANDS]
-     ...
-     }
-
-   The opcodes in a FLIX instruction are listed in the same order as the
-corresponding instruction slots in the TIE format declaration.
-Directives and labels are not allowed inside the braces of a FLIX
-instruction.  A particular TIE format name can optionally be specified
-immediately after the opening brace, but this is usually unnecessary.
-The assembler will automatically search for a format that can encode the
-specified opcodes, so the format name need only be specified in rare
-cases where there is more than one applicable format and where it
-matters which of those formats is used.  A FLIX instruction can also be
-specified on a single line by separating the opcodes with semicolons:
-
-     { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
-
-   The assembler can automatically bundle opcodes into FLIX
-instructions.  It encodes the opcodes in order, one at a time, choosing
-the smallest format where each opcode can be encoded and filling unused
-instruction slots with no-ops.
-
-* Menu:
-
-* Xtensa Opcodes::              Opcode Naming Conventions.
-* Xtensa Registers::            Register Naming.
-
-
-File: as.info,  Node: Xtensa Opcodes,  Next: Xtensa Registers,  Up: Xtensa Syntax
-
-8.34.2.1 Opcode Names
-.....................
-
-See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
-for a complete list of opcodes and descriptions of their semantics.
-
-   If an opcode name is prefixed with an underscore character (`_'),
-`as' will not transform that instruction in any way.  The underscore
-prefix disables both optimization (*note Xtensa Optimizations: Xtensa
-Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
-Relaxation.) for that particular instruction.  Only use the underscore
-prefix when it is essential to select the exact opcode produced by the
-assembler.  Using this feature unnecessarily makes the code less
-efficient by disabling assembler optimization and less flexible by
-disabling relaxation.
-
-   Note that this special handling of underscore prefixes only applies
-to Xtensa opcodes, not to either built-in macros or user-defined macros.
-When an underscore prefix is used with a macro (e.g., `_MOV'), it
-refers to a different macro.  The assembler generally provides built-in
-macros both with and without the underscore prefix, where the underscore
-versions behave as if the underscore carries through to the instructions
-in the macros.  For example, `_MOV' may expand to `_MOV.N'.
-
-   The underscore prefix only applies to individual instructions, not to
-series of instructions.  For example, if a series of instructions have
-underscore prefixes, the assembler will not transform the individual
-instructions, but it may insert other instructions between them (e.g.,
-to align a `LOOP' instruction).  To prevent the assembler from
-modifying a series of instructions as a whole, use the `no-transform'
-directive.  *Note transform: Transform Directive.
-
-
-File: as.info,  Node: Xtensa Registers,  Prev: Xtensa Opcodes,  Up: Xtensa Syntax
-
-8.34.2.2 Register Names
-.......................
-
-The assembly syntax for a register file entry is the "short" name for a
-TIE register file followed by the index into that register file.  For
-example, the general-purpose `AR' register file has a short name of
-`a', so these registers are named `a0'...`a15'.  As a special feature,
-`sp' is also supported as a synonym for `a1'.  Additional registers may
-be added by processor configuration options and by designer-defined TIE
-extensions.  An initial `$' character is optional in all register names.
-
-
-File: as.info,  Node: Xtensa Optimizations,  Next: Xtensa Relaxation,  Prev: Xtensa Syntax,  Up: Xtensa-Dependent
-
-8.34.3 Xtensa Optimizations
----------------------------
-
-The optimizations currently supported by `as' are generation of density
-instructions where appropriate and automatic branch target alignment.
-
-* Menu:
-
-* Density Instructions::        Using Density Instructions.
-* Xtensa Automatic Alignment::  Automatic Instruction Alignment.
-
-
-File: as.info,  Node: Density Instructions,  Next: Xtensa Automatic Alignment,  Up: Xtensa Optimizations
-
-8.34.3.1 Using Density Instructions
-...................................
-
-The Xtensa instruction set has a code density option that provides
-16-bit versions of some of the most commonly used opcodes.  Use of these
-opcodes can significantly reduce code size.  When possible, the
-assembler automatically translates instructions from the core Xtensa
-instruction set into equivalent instructions from the Xtensa code
-density option.  This translation can be disabled by using underscore
-prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
-`--no-transform' command-line option (*note Command Line Options:
-Xtensa Options.), or by using the `no-transform' directive (*note
-transform: Transform Directive.).
-
-   It is a good idea _not_ to use the density instructions directly.
-The assembler will automatically select dense instructions where
-possible.  If you later need to use an Xtensa processor without the code
-density option, the same assembly code will then work without
-modification.
-
-
-File: as.info,  Node: Xtensa Automatic Alignment,  Prev: Density Instructions,  Up: Xtensa Optimizations
-
-8.34.3.2 Automatic Instruction Alignment
-........................................
-
-The Xtensa assembler will automatically align certain instructions, both
-to optimize performance and to satisfy architectural requirements.
-
-   As an optimization to improve performance, the assembler attempts to
-align branch targets so they do not cross instruction fetch boundaries.
-(Xtensa processors can be configured with either 32-bit or 64-bit
-instruction fetch widths.)  An instruction immediately following a call
-is treated as a branch target in this context, because it will be the
-target of a return from the call.  This alignment has the potential to
-reduce branch penalties at some expense in code size.  The assembler
-will not attempt to align labels with the prefixes `.Ln' and `.LM',
-since these labels are used for debugging information and are not
-typically branch targets.  This optimization is enabled by default.
-You can disable it with the `--no-target-align' command-line option
-(*note Command Line Options: Xtensa Options.).
-
-   The target alignment optimization is done without adding instructions
-that could increase the execution time of the program.  If there are
-density instructions in the code preceding a target, the assembler can
-change the target alignment by widening some of those instructions to
-the equivalent 24-bit instructions.  Extra bytes of padding can be
-inserted immediately following unconditional jump and return
-instructions.  This approach is usually successful in aligning many,
-but not all, branch targets.
-
-   The `LOOP' family of instructions must be aligned such that the
-first instruction in the loop body does not cross an instruction fetch
-boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be
-on either a 1 or 2 mod 4 byte boundary).  The assembler knows about
-this restriction and inserts the minimal number of 2 or 3 byte no-op
-instructions to satisfy it.  When no-op instructions are added, any
-label immediately preceding the original loop will be moved in order to
-refer to the loop instruction, not the newly generated no-op
-instruction.  To preserve binary compatibility across processors with
-different fetch widths, the assembler conservatively assumes a 32-bit
-fetch width when aligning `LOOP' instructions (except if the first
-instruction in the loop is a 64-bit instruction).
-
-   Similarly, the `ENTRY' instruction must be aligned on a 0 mod 4 byte
-boundary.  The assembler satisfies this requirement by inserting zero
-bytes when required.  In addition, labels immediately preceding the
-`ENTRY' instruction will be moved to the newly aligned instruction
-location.
-
-
-File: as.info,  Node: Xtensa Relaxation,  Next: Xtensa Directives,  Prev: Xtensa Optimizations,  Up: Xtensa-Dependent
-
-8.34.4 Xtensa Relaxation
-------------------------
-
-When an instruction operand is outside the range allowed for that
-particular instruction field, `as' can transform the code to use a
-functionally-equivalent instruction or sequence of instructions.  This
-process is known as "relaxation".  This is typically done for branch
-instructions because the distance of the branch targets is not known
-until assembly-time.  The Xtensa assembler offers branch relaxation and
-also extends this concept to function calls, `MOVI' instructions and
-other instructions with immediate fields.
-
-* Menu:
-
-* Xtensa Branch Relaxation::        Relaxation of Branches.
-* Xtensa Call Relaxation::          Relaxation of Function Calls.
-* Xtensa Immediate Relaxation::     Relaxation of other Immediate Fields.
-
-
-File: as.info,  Node: Xtensa Branch Relaxation,  Next: Xtensa Call Relaxation,  Up: Xtensa Relaxation
-
-8.34.4.1 Conditional Branch Relaxation
-......................................
-
-When the target of a branch is too far away from the branch itself,
-i.e., when the offset from the branch to the target is too large to fit
-in the immediate field of the branch instruction, it may be necessary to
-replace the branch with a branch around a jump.  For example,
-
-         beqz    a2, L
-
-   may result in:
-
-         bnez.n  a2, M
-         j L
-     M:
-
-   (The `BNEZ.N' instruction would be used in this example only if the
-density option is available.  Otherwise, `BNEZ' would be used.)
-
-   This relaxation works well because the unconditional jump instruction
-has a much larger offset range than the various conditional branches.
-However, an error will occur if a branch target is beyond the range of a
-jump instruction.  `as' cannot relax unconditional jumps.  Similarly,
-an error will occur if the original input contains an unconditional
-jump to a target that is out of range.
-
-   Branch relaxation is enabled by default.  It can be disabled by using
-underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
-`--no-transform' command-line option (*note Command Line Options:
-Xtensa Options.), or the `no-transform' directive (*note transform:
-Transform Directive.).
-
-
-File: as.info,  Node: Xtensa Call Relaxation,  Next: Xtensa Immediate Relaxation,  Prev: Xtensa Branch Relaxation,  Up: Xtensa Relaxation
-
-8.34.4.2 Function Call Relaxation
-.................................
-
-Function calls may require relaxation because the Xtensa immediate call
-instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a
-PC-relative offset of only 512 Kbytes in either direction.  For larger
-programs, it may be necessary to use indirect calls (`CALLX0',
-`CALLX4', `CALLX8' and `CALLX12') where the target address is specified
-in a register.  The Xtensa assembler can automatically relax immediate
-call instructions into indirect call instructions.  This relaxation is
-done by loading the address of the called function into the callee's
-return address register and then using a `CALLX' instruction.  So, for
-example:
-
-         call8 func
-
-   might be relaxed to:
-
-         .literal .L1, func
-         l32r    a8, .L1
-         callx8  a8
-
-   Because the addresses of targets of function calls are not generally
-known until link-time, the assembler must assume the worst and relax all
-the calls to functions in other source files, not just those that really
-will be out of range.  The linker can recognize calls that were
-unnecessarily relaxed, and it will remove the overhead introduced by the
-assembler for those cases where direct calls are sufficient.
-
-   Call relaxation is disabled by default because it can have a negative
-effect on both code size and performance, although the linker can
-usually eliminate the unnecessary overhead.  If a program is too large
-and some of the calls are out of range, function call relaxation can be
-enabled using the `--longcalls' command-line option or the `longcalls'
-directive (*note longcalls: Longcalls Directive.).
-
-
-File: as.info,  Node: Xtensa Immediate Relaxation,  Prev: Xtensa Call Relaxation,  Up: Xtensa Relaxation
-
-8.34.4.3 Other Immediate Field Relaxation
-.........................................
-
-The assembler normally performs the following other relaxations.  They
-can be disabled by using underscore prefixes (*note Opcode Names:
-Xtensa Opcodes.), the `--no-transform' command-line option (*note
-Command Line Options: Xtensa Options.), or the `no-transform' directive
-(*note transform: Transform Directive.).
-
-   The `MOVI' machine instruction can only materialize values in the
-range from -2048 to 2047.  Values outside this range are best
-materialized with `L32R' instructions.  Thus:
-
-         movi a0, 100000
-
-   is assembled into the following machine code:
-
-         .literal .L1, 100000
-         l32r a0, .L1
-
-   The `L8UI' machine instruction can only be used with immediate
-offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine
-instructions can only be used with offsets from 0 to 510.  The `L32I'
-machine instruction can only be used with offsets from 0 to 1020.  A
-load offset outside these ranges can be materalized with an `L32R'
-instruction if the destination register of the load is different than
-the source address register.  For example:
-
-         l32i a1, a0, 2040
-
-   is translated to:
-
-         .literal .L1, 2040
-         l32r a1, .L1
-         addi a1, a0, a1
-         l32i a1, a1, 0
-
-If the load destination and source address register are the same, an
-out-of-range offset causes an error.
-
-   The Xtensa `ADDI' instruction only allows immediate operands in the
-range from -128 to 127.  There are a number of alternate instruction
-sequences for the `ADDI' operation.  First, if the immediate is 0, the
-`ADDI' will be turned into a `MOV.N' instruction (or the equivalent
-`OR' instruction if the code density option is not available).  If the
-`ADDI' immediate is outside of the range -128 to 127, but inside the
-range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI'
-sequence will be used.  Finally, if the immediate is outside of this
-range and a free register is available, an `L32R'/`ADD' sequence will
-be used with a literal allocated from the literal pool.
-
-   For example:
-
-         addi    a5, a6, 0
-         addi    a5, a6, 512
-         addi    a5, a6, 513
-         addi    a5, a6, 50000
-
-   is assembled into the following:
-
-         .literal .L1, 50000
-         mov.n   a5, a6
-         addmi   a5, a6, 0x200
-         addmi   a5, a6, 0x200
-         addi    a5, a5, 1
-         l32r    a5, .L1
-         add     a5, a6, a5
-
-
-File: as.info,  Node: Xtensa Directives,  Prev: Xtensa Relaxation,  Up: Xtensa-Dependent
-
-8.34.5 Directives
------------------
-
-The Xtensa assember supports a region-based directive syntax:
-
-         .begin DIRECTIVE [OPTIONS]
-         ...
-         .end DIRECTIVE
-
-   All the Xtensa-specific directives that apply to a region of code use
-this syntax.
-
-   The directive applies to code between the `.begin' and the `.end'.
-The state of the option after the `.end' reverts to what it was before
-the `.begin'.  A nested `.begin'/`.end' region can further change the
-state of the directive without having to be aware of its outer state.
-For example, consider:
-
-         .begin no-transform
-     L:  add a0, a1, a2
-         .begin transform
-     M:  add a0, a1, a2
-         .end transform
-     N:  add a0, a1, a2
-         .end no-transform
-
-   The `ADD' opcodes at `L' and `N' in the outer `no-transform' region
-both result in `ADD' machine instructions, but the assembler selects an
-`ADD.N' instruction for the `ADD' at `M' in the inner `transform'
-region.
-
-   The advantage of this style is that it works well inside macros
-which can preserve the context of their callers.
-
-   The following directives are available:
-
-* Menu:
-
-* Schedule Directive::         Enable instruction scheduling.
-* Longcalls Directive::        Use Indirect Calls for Greater Range.
-* Transform Directive::        Disable All Assembler Transformations.
-* Literal Directive::          Intermix Literals with Instructions.
-* Literal Position Directive:: Specify Inline Literal Pool Locations.
-* Literal Prefix Directive::   Specify Literal Section Name Prefix.
-* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
-
-
-File: as.info,  Node: Schedule Directive,  Next: Longcalls Directive,  Up: Xtensa Directives
-
-8.34.5.1 schedule
-.................
-
-The `schedule' directive is recognized only for compatibility with
-Tensilica's assembler.
-
-         .begin [no-]schedule
-         .end [no-]schedule
-
-   This directive is ignored and has no effect on `as'.
-
-
-File: as.info,  Node: Longcalls Directive,  Next: Transform Directive,  Prev: Schedule Directive,  Up: Xtensa Directives
-
-8.34.5.2 longcalls
-..................
-
-The `longcalls' directive enables or disables function call relaxation.
-*Note Function Call Relaxation: Xtensa Call Relaxation.
-
-         .begin [no-]longcalls
-         .end [no-]longcalls
-
-   Call relaxation is disabled by default unless the `--longcalls'
-command-line option is specified.  The `longcalls' directive overrides
-the default determined by the command-line options.
-
-
-File: as.info,  Node: Transform Directive,  Next: Literal Directive,  Prev: Longcalls Directive,  Up: Xtensa Directives
-
-8.34.5.3 transform
-..................
-
-This directive enables or disables all assembler transformation,
-including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
-optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
-
-         .begin [no-]transform
-         .end [no-]transform
-
-   Transformations are enabled by default unless the `--no-transform'
-option is used.  The `transform' directive overrides the default
-determined by the command-line options.  An underscore opcode prefix,
-disabling transformation of that opcode, always takes precedence over
-both directives and command-line flags.
-
-
-File: as.info,  Node: Literal Directive,  Next: Literal Position Directive,  Prev: Transform Directive,  Up: Xtensa Directives
-
-8.34.5.4 literal
-................
-
-The `.literal' directive is used to define literal pool data, i.e.,
-read-only 32-bit data accessed via `L32R' instructions.
-
-         .literal LABEL, VALUE[, VALUE...]
-
-   This directive is similar to the standard `.word' directive, except
-that the actual location of the literal data is determined by the
-assembler and linker, not by the position of the `.literal' directive.
-Using this directive gives the assembler freedom to locate the literal
-data in the most appropriate place and possibly to combine identical
-literals.  For example, the code:
-
-         entry sp, 40
-         .literal .L1, sym
-         l32r    a4, .L1
-
-   can be used to load a pointer to the symbol `sym' into register
-`a4'.  The value of `sym' will not be placed between the `ENTRY' and
-`L32R' instructions; instead, the assembler puts the data in a literal
-pool.
-
-   Literal pools for absolute mode `L32R' instructions (*note Absolute
-Literals Directive::) are placed in a separate `.lit4' section.  By
-default literal pools for PC-relative mode `L32R' instructions are
-placed in a separate `.literal' section; however, when using the
-`--text-section-literals' option (*note Command Line Options: Xtensa
-Options.), the literal pools are placed in the current section.  These
-text section literal pools are created automatically before `ENTRY'
-instructions and manually after `.literal_position' directives (*note
-literal_position: Literal Position Directive.).  If there are no
-preceding `ENTRY' instructions, explicit `.literal_position' directives
-must be used to place the text section literal pools; otherwise, `as'
-will report an error.
-
-
-File: as.info,  Node: Literal Position Directive,  Next: Literal Prefix Directive,  Prev: Literal Directive,  Up: Xtensa Directives
-
-8.34.5.5 literal_position
-.........................
-
-When using `--text-section-literals' to place literals inline in the
-section being assembled, the `.literal_position' directive can be used
-to mark a potential location for a literal pool.
-
-         .literal_position
-
-   The `.literal_position' directive is ignored when the
-`--text-section-literals' option is not used or when `L32R'
-instructions use the absolute addressing mode.
-
-   The assembler will automatically place text section literal pools
-before `ENTRY' instructions, so the `.literal_position' directive is
-only needed to specify some other location for a literal pool.  You may
-need to add an explicit jump instruction to skip over an inline literal
-pool.
-
-   For example, an interrupt vector does not begin with an `ENTRY'
-instruction so the assembler will be unable to automatically find a good
-place to put a literal pool.  Moreover, the code for the interrupt
-vector must be at a specific starting address, so the literal pool
-cannot come before the start of the code.  The literal pool for the
-vector must be explicitly positioned in the middle of the vector (before
-any uses of the literals, due to the negative offsets used by
-PC-relative `L32R' instructions).  The `.literal_position' directive
-can be used to do this.  In the following code, the literal for `M'
-will automatically be aligned correctly and is placed after the
-unconditional jump.
-
-         .global M
-     code_start:
-         j continue
-         .literal_position
-         .align 4
-     continue:
-         movi    a4, M
-
-
-File: as.info,  Node: Literal Prefix Directive,  Next: Absolute Literals Directive,  Prev: Literal Position Directive,  Up: Xtensa Directives
-
-8.34.5.6 literal_prefix
-.......................
-
-The `literal_prefix' directive allows you to specify different sections
-to hold literals from different portions of an assembly file.  With
-this directive, a single assembly file can be used to generate code
-into multiple sections, including literals generated by the assembler.
-
-         .begin literal_prefix [NAME]
-         .end literal_prefix
-
-   By default the assembler places literal pools in sections separate
-from the instructions, using the default literal section names of
-`.literal' for PC-relative mode `L32R' instructions and `.lit4' for
-absolute mode `L32R' instructions (*note Absolute Literals
-Directive::).  The `literal_prefix' directive causes different literal
-sections to be used for the code inside the delimited region.  The new
-literal sections are determined by including NAME as a prefix to the
-default literal section names.  If the NAME argument is omitted, the
-literal sections revert to the defaults.  This directive has no effect
-when using the `--text-section-literals' option (*note Command Line
-Options: Xtensa Options.).
-
-   Except for two special cases, the assembler determines the new
-literal sections by simply prepending NAME to the default section names,
-resulting in `NAME.literal' and `NAME.lit4' sections.  The
-`literal_prefix' directive is often used with the name of the current
-text section as the prefix argument.  To facilitate this usage, the
-assembler uses special case rules when it recognizes NAME as a text
-section name.  First, if NAME ends with `.text', that suffix is not
-included in the literal section name.  For example, if NAME is
-`.iram0.text', then the literal sections will be `.iram0.literal' and
-`.iram0.lit4'.  Second, if NAME begins with `.gnu.linkonce.t.', then
-the literal section names are formed by replacing the `.t' substring
-with `.literal' and `.lit4'.  For example, if NAME is
-`.gnu.linkonce.t.func', the literal sections will be
-`.gnu.linkonce.literal.func' and `.gnu.linkonce.lit4.func'.
-
-
-File: as.info,  Node: Absolute Literals Directive,  Prev: Literal Prefix Directive,  Up: Xtensa Directives
-
-8.34.5.7 absolute-literals
-..........................
-
-The `absolute-literals' and `no-absolute-literals' directives control
-the absolute vs. PC-relative mode for `L32R' instructions.  These are
-relevant only for Xtensa configurations that include the absolute
-addressing option for `L32R' instructions.
-
-         .begin [no-]absolute-literals
-         .end [no-]absolute-literals
-
-   These directives do not change the `L32R' mode--they only cause the
-assembler to emit the appropriate kind of relocation for `L32R'
-instructions and to place the literal values in the appropriate section.
-To change the `L32R' mode, the program must write the `LITBASE' special
-register.  It is the programmer's responsibility to keep track of the
-mode and indicate to the assembler which mode is used in each region of
-code.
-
-   If the Xtensa configuration includes the absolute `L32R' addressing
-option, the default is to assume absolute `L32R' addressing unless the
-`--no-absolute-literals' command-line option is specified.  Otherwise,
-the default is to assume PC-relative `L32R' addressing.  The
-`absolute-literals' directive can then be used to override the default
-determined by the command-line options.
-
-
-File: as.info,  Node: Reporting Bugs,  Next: Acknowledgements,  Prev: Machine Dependencies,  Up: Top
-
-9 Reporting Bugs
-****************
-
-Your bug reports play an essential role in making `as' reliable.
-
-   Reporting a bug may help you by bringing a solution to your problem,
-or it may not.  But in any case the principal function of a bug report
-is to help the entire community by making the next version of `as' work
-better.  Bug reports are your contribution to the maintenance of `as'.
-
-   In order for a bug report to serve its purpose, you must include the
-information that enables us to fix the bug.
-
-* Menu:
-
-* Bug Criteria::                Have you found a bug?
-* Bug Reporting::               How to report bugs
-
-
-File: as.info,  Node: Bug Criteria,  Next: Bug Reporting,  Up: Reporting Bugs
-
-9.1 Have You Found a Bug?
-=========================
-
-If you are not sure whether you have found a bug, here are some
-guidelines:
-
-   * If the assembler gets a fatal signal, for any input whatever, that
-     is a `as' bug.  Reliable assemblers never crash.
-
-   * If `as' produces an error message for valid input, that is a bug.
-
-   * If `as' does not produce an error message for invalid input, that
-     is a bug.  However, you should note that your idea of "invalid
-     input" might be our idea of "an extension" or "support for
-     traditional practice".
-
-   * If you are an experienced user of assemblers, your suggestions for
-     improvement of `as' are welcome in any case.
-
-
-File: as.info,  Node: Bug Reporting,  Prev: Bug Criteria,  Up: Reporting Bugs
-
-9.2 How to Report Bugs
-======================
-
-A number of companies and individuals offer support for GNU products.
-If you obtained `as' from a support organization, we recommend you
-contact that organization first.
-
-   You can find contact information for many support companies and
-individuals in the file `etc/SERVICE' in the GNU Emacs distribution.
-
-   In any event, we also recommend that you send bug reports for `as'
-to `bug-binutils@gnu.org'.
-
-   The fundamental principle of reporting bugs usefully is this:
-*report all the facts*.  If you are not sure whether to state a fact or
-leave it out, state it!
-
-   Often people omit facts because they think they know what causes the
-problem and assume that some details do not matter.  Thus, you might
-assume that the name of a symbol you use in an example does not matter.
-Well, probably it does not, but one cannot be sure.  Perhaps the bug
-is a stray memory reference which happens to fetch from the location
-where that name is stored in memory; perhaps, if the name were
-different, the contents of that location would fool the assembler into
-doing the right thing despite the bug.  Play it safe and give a
-specific, complete example.  That is the easiest thing for you to do,
-and the most helpful.
-
-   Keep in mind that the purpose of a bug report is to enable us to fix
-the bug if it is new to us.  Therefore, always write your bug reports
-on the assumption that the bug has not been reported previously.
-
-   Sometimes people give a few sketchy facts and ask, "Does this ring a
-bell?"  This cannot help us fix a bug, so it is basically useless.  We
-respond by asking for enough details to enable us to investigate.  You
-might as well expedite matters by sending them to begin with.
-
-   To enable us to fix the bug, you should include all these things:
-
-   * The version of `as'.  `as' announces it if you start it with the
-     `--version' argument.
-
-     Without this, we will not know whether there is any point in
-     looking for the bug in the current version of `as'.
-
-   * Any patches you may have applied to the `as' source.
-
-   * The type of machine you are using, and the operating system name
-     and version number.
-
-   * What compiler (and its version) was used to compile `as'--e.g.
-     "`gcc-2.7'".
-
-   * The command arguments you gave the assembler to assemble your
-     example and observe the bug.  To guarantee you will not omit
-     something important, list them all.  A copy of the Makefile (or
-     the output from make) is sufficient.
-
-     If we were to try to guess the arguments, we would probably guess
-     wrong and then we might not encounter the bug.
-
-   * A complete input file that will reproduce the bug.  If the bug is
-     observed when the assembler is invoked via a compiler, send the
-     assembler source, not the high level language source.  Most
-     compilers will produce the assembler source when run with the `-S'
-     option.  If you are using `gcc', use the options `-v
-     --save-temps'; this will save the assembler source in a file with
-     an extension of `.s', and also show you exactly how `as' is being
-     run.
-
-   * A description of what behavior you observe that you believe is
-     incorrect.  For example, "It gets a fatal signal."
-
-     Of course, if the bug is that `as' gets a fatal signal, then we
-     will certainly notice it.  But if the bug is incorrect output, we
-     might not notice unless it is glaringly wrong.  You might as well
-     not give us a chance to make a mistake.
-
-     Even if the problem you experience is a fatal signal, you should
-     still say so explicitly.  Suppose something strange is going on,
-     such as, your copy of `as' is out of synch, or you have
-     encountered a bug in the C library on your system.  (This has
-     happened!)  Your copy might crash and ours would not.  If you told
-     us to expect a crash, then when ours fails to crash, we would know
-     that the bug was not happening for us.  If you had not told us to
-     expect a crash, then we would not be able to draw any conclusion
-     from our observations.
-
-   * If you wish to suggest changes to the `as' source, send us context
-     diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
-     Always send diffs from the old file to the new file.  If you even
-     discuss something in the `as' source, refer to it by context, not
-     by line number.
-
-     The line numbers in our development sources will not match those
-     in your sources.  Your line numbers would convey no useful
-     information to us.
-
-   Here are some things that are not necessary:
-
-   * A description of the envelope of the bug.
-
-     Often people who encounter a bug spend a lot of time investigating
-     which changes to the input file will make the bug go away and which
-     changes will not affect it.
-
-     This is often time consuming and not very useful, because the way
-     we will find the bug is by running a single example under the
-     debugger with breakpoints, not by pure deduction from a series of
-     examples.  We recommend that you save your time for something else.
-
-     Of course, if you can find a simpler example to report _instead_
-     of the original one, that is a convenience for us.  Errors in the
-     output will be easier to spot, running under the debugger will take
-     less time, and so on.
-
-     However, simplification is not vital; if you do not want to do
-     this, report the bug anyway and send us the entire test case you
-     used.
-
-   * A patch for the bug.
-
-     A patch for the bug does help us if it is a good one.  But do not
-     omit the necessary information, such as the test case, on the
-     assumption that a patch is all we need.  We might see problems
-     with your patch and decide to fix the problem another way, or we
-     might not understand it at all.
-
-     Sometimes with a program as complicated as `as' it is very hard to
-     construct an example that will make the program follow a certain
-     path through the code.  If you do not send us the example, we will
-     not be able to construct one, so we will not be able to verify
-     that the bug is fixed.
-
-     And if we cannot understand what bug you are trying to fix, or why
-     your patch should be an improvement, we will not install it.  A
-     test case will help us to understand.
-
-   * A guess about what the bug is or what it depends on.
-
-     Such guesses are usually wrong.  Even we cannot guess right about
-     such things without first using the debugger to find the facts.
-
-
-File: as.info,  Node: Acknowledgements,  Next: GNU Free Documentation License,  Prev: Reporting Bugs,  Up: Top
-
-10 Acknowledgements
-*******************
-
-If you have contributed to GAS and your name isn't listed here, it is
-not meant as a slight.  We just don't know about it.  Send mail to the
-maintainer, and we'll correct the situation.  Currently the maintainer
-is Ken Raeburn (email address `raeburn@cygnus.com').
-
-   Dean Elsner wrote the original GNU assembler for the VAX.(1)
-
-   Jay Fenlason maintained GAS for a while, adding support for
-GDB-specific debug information and the 68k series machines, most of the
-preprocessing pass, and extensive changes in `messages.c',
-`input-file.c', `write.c'.
-
-   K. Richard Pixley maintained GAS for a while, adding various
-enhancements and many bug fixes, including merging support for several
-processors, breaking GAS up to handle multiple object file format back
-ends (including heavy rewrite, testing, an integration of the coff and
-b.out back ends), adding configuration including heavy testing and
-verification of cross assemblers and file splits and renaming,
-converted GAS to strictly ANSI C including full prototypes, added
-support for m680[34]0 and cpu32, did considerable work on i960
-including a COFF port (including considerable amounts of reverse
-engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
-hp300hpux host ports, updated "know" assertions and made them work,
-much other reorganization, cleanup, and lint.
-
-   Ken Raeburn wrote the high-level BFD interface code to replace most
-of the code in format-specific I/O modules.
-
-   The original VMS support was contributed by David L. Kashtan.  Eric
-Youngdale has done much work with it since.
-
-   The Intel 80386 machine description was written by Eliot Dresselhaus.
-
-   Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
-
-   The Motorola 88k machine description was contributed by Devon Bowen
-of Buffalo University and Torbjorn Granlund of the Swedish Institute of
-Computer Science.
-
-   Keith Knowles at the Open Software Foundation wrote the original
-MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
-support (which hasn't been merged in yet).  Ralph Campbell worked with
-the MIPS code to support a.out format.
-
-   Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
-tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
-Steve Chamberlain of Cygnus Support.  Steve also modified the COFF back
-end to use BFD for some low-level operations, for use with the H8/300
-and AMD 29k targets.
-
-   John Gilmore built the AMD 29000 support, added `.include' support,
-and simplified the configuration of which versions accept which
-directives.  He updated the 68k machine description so that Motorola's
-opcodes always produced fixed-size instructions (e.g., `jsr'), while
-synthetic instructions remained shrinkable (`jbsr').  John fixed many
-bugs, including true tested cross-compilation support, and one bug in
-relaxation that took a week and required the proverbial one-bit fix.
-
-   Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
-syntax for the 68k, completed support for some COFF targets (68k, i386
-SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
-wrote the initial RS/6000 and PowerPC assembler, and made a few other
-minor patches.
-
-   Steve Chamberlain made GAS able to generate listings.
-
-   Hewlett-Packard contributed support for the HP9000/300.
-
-   Jeff Law wrote GAS and BFD support for the native HPPA object format
-(SOM) along with a fairly extensive HPPA testsuite (for both SOM and
-ELF object formats).  This work was supported by both the Center for
-Software Science at the University of Utah and Cygnus Support.
-
-   Support for ELF format files has been worked on by Mark Eichin of
-Cygnus Support (original, incomplete implementation for SPARC), Pete
-Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
-Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
-Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
-
-   Linas Vepstas added GAS support for the ESA/390 "IBM 370"
-architecture.
-
-   Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
-GAS and BFD support for openVMS/Alpha.
-
-   Timothy Wall, Michael Hayes, and Greg Smart contributed to the
-various tic* flavors.
-
-   David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
-Tensilica, Inc. added support for Xtensa processors.
-
-   Several engineers at Cygnus Support have also provided many small
-bug fixes and configuration enhancements.
-
-   Many others have contributed large or small bugfixes and
-enhancements.  If you have contributed significant work and are not
-mentioned on this list, and want to be, let us know.  Some of the
-history has been lost; we are not intentionally leaving anyone out.
-
-   ---------- Footnotes ----------
-
-   (1) Any more details?
-
-
-File: as.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Acknowledgements,  Up: Top
-
-Appendix A GNU Free Documentation License
-*****************************************
-
-                        Version 1.1, March 2000
-
-     Copyright (C) 2000, 2003 Free Software Foundation, Inc.
-     51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
-
-     Everyone is permitted to copy and distribute verbatim copies
-     of this license document, but changing it is not allowed.
-
-
-  0. PREAMBLE
-
-     The purpose of this License is to make a manual, textbook, or other
-     written document "free" in the sense of freedom: to assure everyone
-     the effective freedom to copy and redistribute it, with or without
-     modifying it, either commercially or noncommercially.  Secondarily,
-     this License preserves for the author and publisher a way to get
-     credit for their work, while not being considered responsible for
-     modifications made by others.
-
-     This License is a kind of "copyleft", which means that derivative
-     works of the document must themselves be free in the same sense.
-     It complements the GNU General Public License, which is a copyleft
-     license designed for free software.
-
-     We have designed this License in order to use it for manuals for
-     free software, because free software needs free documentation: a
-     free program should come with manuals providing the same freedoms
-     that the software does.  But this License is not limited to
-     software manuals; it can be used for any textual work, regardless
-     of subject matter or whether it is published as a printed book.
-     We recommend this License principally for works whose purpose is
-     instruction or reference.
-
-
-  1. APPLICABILITY AND DEFINITIONS
-
-     This License applies to any manual or other work that contains a
-     notice placed by the copyright holder saying it can be distributed
-     under the terms of this License.  The "Document", below, refers to
-     any such manual or work.  Any member of the public is a licensee,
-     and is addressed as "you."
-
-     A "Modified Version" of the Document means any work containing the
-     Document or a portion of it, either copied verbatim, or with
-     modifications and/or translated into another language.
-
-     A "Secondary Section" is a named appendix or a front-matter
-     section of the Document that deals exclusively with the
-     relationship of the publishers or authors of the Document to the
-     Document's overall subject (or to related matters) and contains
-     nothing that could fall directly within that overall subject.
-     (For example, if the Document is in part a textbook of
-     mathematics, a Secondary Section may not explain any mathematics.)
-     The relationship could be a matter of historical connection with
-     the subject or with related matters, or of legal, commercial,
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-
-     The "Invariant Sections" are certain Secondary Sections whose
-     titles are designated, as being those of Invariant Sections, in
-     the notice that says that the Document is released under this
-     License.
-
-     The "Cover Texts" are certain short passages of text that are
-     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
-     that says that the Document is released under this License.
-
-     A "Transparent" copy of the Document means a machine-readable copy,
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-     processors for output purposes only.
-
-     The "Title Page" means, for a printed book, the title page itself,
-     plus such following pages as are needed to hold, legibly, the
-     material this License requires to appear in the title page.  For
-     works in formats which do not have any title page as such, "Title
-     Page" means the text near the most prominent appearance of the
-     work's title, preceding the beginning of the body of the text.
-
-  2. VERBATIM COPYING
-
-     You may copy and distribute the Document in any medium, either
-     commercially or noncommercially, provided that this License, the
-     copyright notices, and the license notice saying this License
-     applies to the Document are reproduced in all copies, and that you
-     add no other conditions whatsoever to those of this License.  You
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-     or further copying of the copies you make or distribute.  However,
-     you may accept compensation in exchange for copies.  If you
-     distribute a large enough number of copies you must also follow
-     the conditions in section 3.
-
-     You may also lend copies, under the same conditions stated above,
-     and you may publicly display copies.
-
-  3. COPYING IN QUANTITY
-
-     If you publish printed copies of the Document numbering more than
-     100, and the Document's license notice requires Cover Texts, you
-     must enclose the copies in covers that carry, clearly and legibly,
-     all these Cover Texts: Front-Cover Texts on the front cover, and
-     Back-Cover Texts on the back cover.  Both covers must also clearly
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-     satisfy these conditions, can be treated as verbatim copying in
-     other respects.
-
-     If the required texts for either cover are too voluminous to fit
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-     adjacent pages.
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-     If you publish or distribute Opaque copies of the Document
-     numbering more than 100, you must either include a
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-     of the Document, free of added material, which the general
-     network-using public has access to download anonymously at no
-     charge using public-standard network protocols.  If you use the
-     latter option, you must take reasonably prudent steps, when you
-     begin distribution of Opaque copies in quantity, to ensure that
-     this Transparent copy will remain thus accessible at the stated
-     location until at least one year after the last time you
-     distribute an Opaque copy (directly or through your agents or
-     retailers) of that edition to the public.
-
-     It is requested, but not required, that you contact the authors of
-     the Document well before redistributing any large number of
-     copies, to give them a chance to provide you with an updated
-     version of the Document.
-
-  4. MODIFICATIONS
-
-     You may copy and distribute a Modified Version of the Document
-     under the conditions of sections 2 and 3 above, provided that you
-     release the Modified Version under precisely this License, with
-     the Modified Version filling the role of the Document, thus
-     licensing distribution and modification of the Modified Version to
-     whoever possesses a copy of it.  In addition, you must do these
-     things in the Modified Version:
-
-     A. Use in the Title Page (and on the covers, if any) a title
-     distinct    from that of the Document, and from those of previous
-     versions    (which should, if there were any, be listed in the
-     History section    of the Document).  You may use the same title
-     as a previous version    if the original publisher of that version
-     gives permission.
-     B. List on the Title Page, as authors, one or more persons or
-     entities    responsible for authorship of the modifications in the
-     Modified    Version, together with at least five of the principal
-     authors of the    Document (all of its principal authors, if it
-     has less than five).
-     C. State on the Title page the name of the publisher of the
-     Modified Version, as the publisher.
-     D. Preserve all the copyright notices of the Document.
-     E. Add an appropriate copyright notice for your modifications
-     adjacent to the other copyright notices.
-     F. Include, immediately after the copyright notices, a license
-     notice    giving the public permission to use the Modified Version
-     under the    terms of this License, in the form shown in the
-     Addendum below.
-     G. Preserve in that license notice the full lists of Invariant
-     Sections    and required Cover Texts given in the Document's
-     license notice.
-     H. Include an unaltered copy of this License.
-     I. Preserve the section entitled "History", and its title, and add
-     to    it an item stating at least the title, year, new authors, and
-       publisher of the Modified Version as given on the Title Page.
-     If    there is no section entitled "History" in the Document,
-     create one    stating the title, year, authors, and publisher of
-     the Document as    given on its Title Page, then add an item
-     describing the Modified    Version as stated in the previous
-     sentence.
-     J. Preserve the network location, if any, given in the Document for
-       public access to a Transparent copy of the Document, and
-     likewise    the network locations given in the Document for
-     previous versions    it was based on.  These may be placed in the
-     "History" section.     You may omit a network location for a work
-     that was published at    least four years before the Document
-     itself, or if the original    publisher of the version it refers
-     to gives permission.
-     K. In any section entitled "Acknowledgements" or "Dedications",
-     preserve the section's title, and preserve in the section all the
-      substance and tone of each of the contributor acknowledgements
-     and/or dedications given therein.
-     L. Preserve all the Invariant Sections of the Document,
-     unaltered in their text and in their titles.  Section numbers
-     or the equivalent are not considered part of the section titles.
-     M. Delete any section entitled "Endorsements."  Such a section
-     may not be included in the Modified Version.
-     N. Do not retitle any existing section as "Endorsements"    or to
-     conflict in title with any Invariant Section.
-
-     If the Modified Version includes new front-matter sections or
-     appendices that qualify as Secondary Sections and contain no
-     material copied from the Document, you may at your option
-     designate some or all of these sections as invariant.  To do this,
-     add their titles to the list of Invariant Sections in the Modified
-     Version's license notice.  These titles must be distinct from any
-     other section titles.
-
-     You may add a section entitled "Endorsements", provided it contains
-     nothing but endorsements of your Modified Version by various
-     parties-for example, statements of peer review or that the text has
-     been approved by an organization as the authoritative definition
-     of a standard.
-
-     You may add a passage of up to five words as a Front-Cover Text,
-     and a passage of up to 25 words as a Back-Cover Text, to the end
-     of the list of Cover Texts in the Modified Version.  Only one
-     passage of Front-Cover Text and one of Back-Cover Text may be
-     added by (or through arrangements made by) any one entity.  If the
-     Document already includes a cover text for the same cover,
-     previously added by you or by arrangement made by the same entity
-     you are acting on behalf of, you may not add another; but you may
-     replace the old one, on explicit permission from the previous
-     publisher that added the old one.
-
-     The author(s) and publisher(s) of the Document do not by this
-     License give permission to use their names for publicity for or to
-     assert or imply endorsement of any Modified Version.
-
-  5. COMBINING DOCUMENTS
-
-     You may combine the Document with other documents released under
-     this License, under the terms defined in section 4 above for
-     modified versions, provided that you include in the combination
-     all of the Invariant Sections of all of the original documents,
-     unmodified, and list them all as Invariant Sections of your
-     combined work in its license notice.
-
-     The combined work need only contain one copy of this License, and
-     multiple identical Invariant Sections may be replaced with a single
-     copy.  If there are multiple Invariant Sections with the same name
-     but different contents, make the title of each such section unique
-     by adding at the end of it, in parentheses, the name of the
-     original author or publisher of that section if known, or else a
-     unique number.  Make the same adjustment to the section titles in
-     the list of Invariant Sections in the license notice of the
-     combined work.
-
-     In the combination, you must combine any sections entitled
-     "History" in the various original documents, forming one section
-     entitled "History"; likewise combine any sections entitled
-     "Acknowledgements", and any sections entitled "Dedications."  You
-     must delete all sections entitled "Endorsements."
-
-  6. COLLECTIONS OF DOCUMENTS
-
-     You may make a collection consisting of the Document and other
-     documents released under this License, and replace the individual
-     copies of this License in the various documents with a single copy
-     that is included in the collection, provided that you follow the
-     rules of this License for verbatim copying of each of the
-     documents in all other respects.
-
-     You may extract a single document from such a collection, and
-     distribute it individually under this License, provided you insert
-     a copy of this License into the extracted document, and follow
-     this License in all other respects regarding verbatim copying of
-     that document.
-
-  7. AGGREGATION WITH INDEPENDENT WORKS
-
-     A compilation of the Document or its derivatives with other
-     separate and independent documents or works, in or on a volume of
-     a storage or distribution medium, does not as a whole count as a
-     Modified Version of the Document, provided no compilation
-     copyright is claimed for the compilation.  Such a compilation is
-     called an "aggregate", and this License does not apply to the
-     other self-contained works thus compiled with the Document, on
-     account of their being thus compiled, if they are not themselves
-     derivative works of the Document.
-
-     If the Cover Text requirement of section 3 is applicable to these
-     copies of the Document, then if the Document is less than one
-     quarter of the entire aggregate, the Document's Cover Texts may be
-     placed on covers that surround only the Document within the
-     aggregate.  Otherwise they must appear on covers around the whole
-     aggregate.
-
-  8. TRANSLATION
-
-     Translation is considered a kind of modification, so you may
-     distribute translations of the Document under the terms of section
-     4.  Replacing Invariant Sections with translations requires special
-     permission from their copyright holders, but you may include
-     translations of some or all Invariant Sections in addition to the
-     original versions of these Invariant Sections.  You may include a
-     translation of this License provided that you also include the
-     original English version of this License.  In case of a
-     disagreement between the translation and the original English
-     version of this License, the original English version will prevail.
-
-  9. TERMINATION
-
-     You may not copy, modify, sublicense, or distribute the Document
-     except as expressly provided for under this License.  Any other
-     attempt to copy, modify, sublicense or distribute the Document is
-     void, and will automatically terminate your rights under this
-     License.  However, parties who have received copies, or rights,
-     from you under this License will not have their licenses
-     terminated so long as such parties remain in full compliance.
-
- 10. FUTURE REVISIONS OF THIS LICENSE
-
-     The Free Software Foundation may publish new, revised versions of
-     the GNU Free Documentation License from time to time.  Such new
-     versions will be similar in spirit to the present version, but may
-     differ in detail to address new problems or concerns.  See
-     http://www.gnu.org/copyleft/.
-
-     Each version of the License is given a distinguishing version
-     number.  If the Document specifies that a particular numbered
-     version of this License "or any later version" applies to it, you
-     have the option of following the terms and conditions either of
-     that specified version or of any later version that has been
-     published (not as a draft) by the Free Software Foundation.  If
-     the Document does not specify a version number of this License,
-     you may choose any version ever published (not as a draft) by the
-     Free Software Foundation.
-
-
-ADDENDUM: How to use this License for your documents
-====================================================
-
-To use this License in a document you have written, include a copy of
-the License in the document and put the following copyright and license
-notices just after the title page:
-
-     Copyright (C)  YEAR  YOUR NAME.
-     Permission is granted to copy, distribute and/or modify this document
-     under the terms of the GNU Free Documentation License, Version 1.1
-     or any later version published by the Free Software Foundation;
-     with the Invariant Sections being LIST THEIR TITLES, with the
-     Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.
-     A copy of the license is included in the section entitled "GNU
-     Free Documentation License."
-
-   If you have no Invariant Sections, write "with no Invariant Sections"
-instead of saying which ones are invariant.  If you have no Front-Cover
-Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being
-LIST"; likewise for Back-Cover Texts.
-
-   If your document contains nontrivial examples of program code, we
-recommend releasing these examples in parallel under your choice of
-free software license, such as the GNU General Public License, to
-permit their use in free software.
-
-
-File: as.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
-
-Index
-*****
-
-
-* Menu:
-
-* #:                                     Comments.            (line  38)
-* #APP:                                  Preprocessing.       (line  27)
-* #NO_APP:                               Preprocessing.       (line  27)
-* $ in symbol names <1>:                 SH64-Chars.          (line  10)
-* $ in symbol names <2>:                 SH-Chars.            (line  10)
-* $ in symbol names <3>:                 D30V-Chars.          (line  63)
-* $ in symbol names:                     D10V-Chars.          (line  46)
-* $a:                                    ARM Mapping Symbols. (line   9)
-* $acos math builtin, TIC54X:            TIC54X-Builtins.     (line  10)
-* $asin math builtin, TIC54X:            TIC54X-Builtins.     (line  13)
-* $atan math builtin, TIC54X:            TIC54X-Builtins.     (line  16)
-* $atan2 math builtin, TIC54X:           TIC54X-Builtins.     (line  19)
-* $ceil math builtin, TIC54X:            TIC54X-Builtins.     (line  22)
-* $cos math builtin, TIC54X:             TIC54X-Builtins.     (line  28)
-* $cosh math builtin, TIC54X:            TIC54X-Builtins.     (line  25)
-* $cvf math builtin, TIC54X:             TIC54X-Builtins.     (line  31)
-* $cvi math builtin, TIC54X:             TIC54X-Builtins.     (line  34)
-* $d:                                    ARM Mapping Symbols. (line  15)
-* $exp math builtin, TIC54X:             TIC54X-Builtins.     (line  37)
-* $fabs math builtin, TIC54X:            TIC54X-Builtins.     (line  40)
-* $firstch subsym builtin, TIC54X:       TIC54X-Macros.       (line  26)
-* $floor math builtin, TIC54X:           TIC54X-Builtins.     (line  43)
-* $fmod math builtin, TIC54X:            TIC54X-Builtins.     (line  47)
-* $int math builtin, TIC54X:             TIC54X-Builtins.     (line  50)
-* $iscons subsym builtin, TIC54X:        TIC54X-Macros.       (line  43)
-* $isdefed subsym builtin, TIC54X:       TIC54X-Macros.       (line  34)
-* $ismember subsym builtin, TIC54X:      TIC54X-Macros.       (line  38)
-* $isname subsym builtin, TIC54X:        TIC54X-Macros.       (line  47)
-* $isreg subsym builtin, TIC54X:         TIC54X-Macros.       (line  50)
-* $lastch subsym builtin, TIC54X:        TIC54X-Macros.       (line  30)
-* $ldexp math builtin, TIC54X:           TIC54X-Builtins.     (line  53)
-* $log math builtin, TIC54X:             TIC54X-Builtins.     (line  59)
-* $log10 math builtin, TIC54X:           TIC54X-Builtins.     (line  56)
-* $max math builtin, TIC54X:             TIC54X-Builtins.     (line  62)
-* $min math builtin, TIC54X:             TIC54X-Builtins.     (line  65)
-* $pow math builtin, TIC54X:             TIC54X-Builtins.     (line  68)
-* $round math builtin, TIC54X:           TIC54X-Builtins.     (line  71)
-* $sgn math builtin, TIC54X:             TIC54X-Builtins.     (line  74)
-* $sin math builtin, TIC54X:             TIC54X-Builtins.     (line  77)
-* $sinh math builtin, TIC54X:            TIC54X-Builtins.     (line  80)
-* $sqrt math builtin, TIC54X:            TIC54X-Builtins.     (line  83)
-* $structacc subsym builtin, TIC54X:     TIC54X-Macros.       (line  57)
-* $structsz subsym builtin, TIC54X:      TIC54X-Macros.       (line  54)
-* $symcmp subsym builtin, TIC54X:        TIC54X-Macros.       (line  23)
-* $symlen subsym builtin, TIC54X:        TIC54X-Macros.       (line  20)
-* $t:                                    ARM Mapping Symbols. (line  12)
-* $tan math builtin, TIC54X:             TIC54X-Builtins.     (line  86)
-* $tanh math builtin, TIC54X:            TIC54X-Builtins.     (line  89)
-* $trunc math builtin, TIC54X:           TIC54X-Builtins.     (line  92)
-* -+ option, VAX/VMS:                    VAX-Opts.            (line  71)
-* --:                                    Command Line.        (line  10)
-* --32 option, i386:                     i386-Options.        (line   8)
-* --32 option, x86-64:                   i386-Options.        (line   8)
-* --64 option, i386:                     i386-Options.        (line   8)
-* --64 option, x86-64:                   i386-Options.        (line   8)
-* --absolute-literals:                   Xtensa Options.      (line  22)
-* --allow-reg-prefix:                    SH Options.          (line   9)
-* --alternate:                           alternate.           (line   6)
-* --base-size-default-16:                M68K-Opts.           (line  70)
-* --base-size-default-32:                M68K-Opts.           (line  70)
-* --big:                                 SH Options.          (line   9)
-* --bitwise-or option, M680x0:           M68K-Opts.           (line  63)
-* --disp-size-default-16:                M68K-Opts.           (line  79)
-* --disp-size-default-32:                M68K-Opts.           (line  79)
-* --divide option, i386:                 i386-Options.        (line  24)
-* --dsp:                                 SH Options.          (line   9)
-* --emulation=crisaout command line option, CRIS: CRIS-Opts.  (line   9)
-* --emulation=criself command line option, CRIS: CRIS-Opts.   (line   9)
-* --enforce-aligned-data:                Sparc-Aligned-Data.  (line  11)
-* --fatal-warnings:                      W.                   (line  16)
-* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
-                                                              (line   8)
-* --force-long-branchs:                  M68HC11-Opts.        (line  69)
-* --generate-example:                    M68HC11-Opts.        (line  86)
-* --globalize-symbols command line option, MMIX: MMIX-Opts.   (line  12)
-* --gnu-syntax command line option, MMIX: MMIX-Opts.          (line  16)
-* --hash-size=NUMBER:                    Overview.            (line 297)
-* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
-                                                              (line  67)
-* --listing-cont-lines:                  listing.             (line  33)
-* --listing-lhs-width:                   listing.             (line  15)
-* --listing-lhs-width2:                  listing.             (line  20)
-* --listing-rhs-width:                   listing.             (line  27)
-* --little:                              SH Options.          (line   9)
-* --longcalls:                           Xtensa Options.      (line  36)
-* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts.  (line  33)
-* --MD:                                  MD.                  (line   6)
-* --mul-bug-abort command line option, CRIS: CRIS-Opts.       (line  61)
-* --no-absolute-literals:                Xtensa Options.      (line  22)
-* --no-expand command line option, MMIX: MMIX-Opts.           (line  31)
-* --no-longcalls:                        Xtensa Options.      (line  36)
-* --no-merge-gregs command line option, MMIX: MMIX-Opts.      (line  36)
-* --no-mul-bug-abort command line option, CRIS: CRIS-Opts.    (line  61)
-* --no-predefined-syms command line option, MMIX: MMIX-Opts.  (line  22)
-* --no-pushj-stubs command line option, MMIX: MMIX-Opts.      (line  54)
-* --no-stubs command line option, MMIX:  MMIX-Opts.           (line  54)
-* --no-target-align:                     Xtensa Options.      (line  29)
-* --no-text-section-literals:            Xtensa Options.      (line   9)
-* --no-transform:                        Xtensa Options.      (line  45)
-* --no-underscore command line option, CRIS: CRIS-Opts.       (line  15)
-* --no-warn:                             W.                   (line  11)
-* --pcrel:                               M68K-Opts.           (line  91)
-* --pic command line option, CRIS:       CRIS-Opts.           (line  27)
-* --print-insn-syntax:                   M68HC11-Opts.        (line  75)
-* --print-opcodes:                       M68HC11-Opts.        (line  79)
-* --register-prefix-optional option, M680x0: M68K-Opts.       (line  50)
-* --relax:                               SH Options.          (line   9)
-* --relax command line option, MMIX:     MMIX-Opts.           (line  19)
-* --rename-section:                      Xtensa Options.      (line  53)
-* --renesas:                             SH Options.          (line   9)
-* --short-branchs:                       M68HC11-Opts.        (line  54)
-* --small:                               SH Options.          (line   9)
-* --statistics:                          statistics.          (line   6)
-* --strict-direct-mode:                  M68HC11-Opts.        (line  44)
-* --target-align:                        Xtensa Options.      (line  29)
-* --text-section-literals:               Xtensa Options.      (line   9)
-* --traditional-format:                  traditional-format.  (line   6)
-* --transform:                           Xtensa Options.      (line  45)
-* --underscore command line option, CRIS: CRIS-Opts.          (line  15)
-* --warn:                                W.                   (line  19)
-* -1 option, VAX/VMS:                    VAX-Opts.            (line  77)
-* -32addr command line option, Alpha:    Alpha Options.       (line  50)
-* -a:                                    a.                   (line   6)
-* -A options, i960:                      Options-i960.        (line   6)
-* -ac:                                   a.                   (line   6)
-* -ad:                                   a.                   (line   6)
-* -ah:                                   a.                   (line   6)
-* -al:                                   a.                   (line   6)
-* -an:                                   a.                   (line   6)
-* -as:                                   a.                   (line   6)
-* -Asparclet:                            Sparc-Opts.          (line  25)
-* -Asparclite:                           Sparc-Opts.          (line  25)
-* -Av6:                                  Sparc-Opts.          (line  25)
-* -Av8:                                  Sparc-Opts.          (line  25)
-* -Av9:                                  Sparc-Opts.          (line  25)
-* -Av9a:                                 Sparc-Opts.          (line  25)
-* -b option, i960:                       Options-i960.        (line  22)
-* -big option, M32R:                     M32R-Opts.           (line  35)
-* -construct-floats:                     MIPS Opts.           (line 157)
-* -D:                                    D.                   (line   6)
-* -D, ignored on VAX:                    VAX-Opts.            (line  11)
-* -d, VAX option:                        VAX-Opts.            (line  16)
-* -eabi= command line option, ARM:       ARM Options.         (line 107)
-* -EB command line option, ARC:          ARC Options.         (line  31)
-* -EB command line option, ARM:          ARM Options.         (line 112)
-* -EB option (MIPS):                     MIPS Opts.           (line  13)
-* -EB option, M32R:                      M32R-Opts.           (line  39)
-* -EL command line option, ARC:          ARC Options.         (line  35)
-* -EL command line option, ARM:          ARM Options.         (line 116)
-* -EL option (MIPS):                     MIPS Opts.           (line  13)
-* -EL option, M32R:                      M32R-Opts.           (line  32)
-* -f:                                    f.                   (line   6)
-* -F command line option, Alpha:         Alpha Options.       (line  50)
-* -G command line option, Alpha:         Alpha Options.       (line  46)
-* -g command line option, Alpha:         Alpha Options.       (line  40)
-* -G option (MIPS):                      MIPS Opts.           (line   8)
-* -H option, VAX/VMS:                    VAX-Opts.            (line  81)
-* -h option, VAX/VMS:                    VAX-Opts.            (line  45)
-* -I PATH:                               I.                   (line   6)
-* -ignore-parallel-conflicts option, M32RX: M32R-Opts.        (line  87)
-* -Ip option, M32RX:                     M32R-Opts.           (line  97)
-* -J, ignored on VAX:                    VAX-Opts.            (line  27)
-* -K:                                    K.                   (line   6)
-* -k command line option, ARM:           ARM Options.         (line 120)
-* -KPIC option, M32R:                    M32R-Opts.           (line  42)
-* -L:                                    L.                   (line   6)
-* -l option, M680x0:                     M68K-Opts.           (line  38)
-* -little option, M32R:                  M32R-Opts.           (line  27)
-* -M:                                    M.                   (line   6)
-* -m11/03:                               PDP-11-Options.      (line 140)
-* -m11/04:                               PDP-11-Options.      (line 143)
-* -m11/05:                               PDP-11-Options.      (line 146)
-* -m11/10:                               PDP-11-Options.      (line 146)
-* -m11/15:                               PDP-11-Options.      (line 149)
-* -m11/20:                               PDP-11-Options.      (line 149)
-* -m11/21:                               PDP-11-Options.      (line 152)
-* -m11/23:                               PDP-11-Options.      (line 155)
-* -m11/24:                               PDP-11-Options.      (line 155)
-* -m11/34:                               PDP-11-Options.      (line 158)
-* -m11/34a:                              PDP-11-Options.      (line 161)
-* -m11/35:                               PDP-11-Options.      (line 164)
-* -m11/40:                               PDP-11-Options.      (line 164)
-* -m11/44:                               PDP-11-Options.      (line 167)
-* -m11/45:                               PDP-11-Options.      (line 170)
-* -m11/50:                               PDP-11-Options.      (line 170)
-* -m11/53:                               PDP-11-Options.      (line 173)
-* -m11/55:                               PDP-11-Options.      (line 170)
-* -m11/60:                               PDP-11-Options.      (line 176)
-* -m11/70:                               PDP-11-Options.      (line 170)
-* -m11/73:                               PDP-11-Options.      (line 173)
-* -m11/83:                               PDP-11-Options.      (line 173)
-* -m11/84:                               PDP-11-Options.      (line 173)
-* -m11/93:                               PDP-11-Options.      (line 173)
-* -m11/94:                               PDP-11-Options.      (line 173)
-* -m16c option, M16C:                    M32C-Opts.           (line  12)
-* -m32c option, M32C:                    M32C-Opts.           (line   9)
-* -m32r option, M32R:                    M32R-Opts.           (line  21)
-* -m32rx option, M32R2:                  M32R-Opts.           (line  17)
-* -m32rx option, M32RX:                  M32R-Opts.           (line   9)
-* -m68000 and related options:           M68K-Opts.           (line 103)
-* -m68hc11:                              M68HC11-Opts.        (line   9)
-* -m68hc12:                              M68HC11-Opts.        (line  14)
-* -m68hcs12:                             M68HC11-Opts.        (line  21)
-* -m[no-]68851 command line option, M680x0: M68K-Opts.        (line  20)
-* -m[no-]68881 command line option, M680x0: M68K-Opts.        (line  20)
-* -m[no-]div command line option, M680x0: M68K-Opts.          (line  20)
-* -m[no-]emac command line option, M680x0: M68K-Opts.         (line  20)
-* -m[no-]float command line option, M680x0: M68K-Opts.        (line  20)
-* -m[no-]mac command line option, M680x0: M68K-Opts.          (line  20)
-* -m[no-]usp command line option, M680x0: M68K-Opts.          (line  20)
-* -mall:                                 PDP-11-Options.      (line  26)
-* -mall-extensions:                      PDP-11-Options.      (line  26)
-* -mapcs command line option, ARM:       ARM Options.         (line  80)
-* -mapcs-float command line option, ARM: ARM Options.         (line  93)
-* -mapcs-reentrant command line option, ARM: ARM Options.     (line  98)
-* -marc[5|6|7|8] command line option, ARC: ARC Options.       (line   6)
-* -march= command line option, ARM:      ARM Options.         (line  37)
-* -march= command line option, M680x0:   M68K-Opts.           (line   8)
-* -matpcs command line option, ARM:      ARM Options.         (line  85)
-* -mcis:                                 PDP-11-Options.      (line  32)
-* -mconstant-gp command line option, IA-64: IA-64 Options.    (line   6)
-* -mCPU command line option, Alpha:      Alpha Options.       (line   6)
-* -mcpu option, cpu:                     TIC54X-Opts.         (line  15)
-* -mcpu= command line option, ARM:       ARM Options.         (line   6)
-* -mcpu= command line option, M680x0:    M68K-Opts.           (line  13)
-* -mcsm:                                 PDP-11-Options.      (line  43)
-* -mdebug command line option, Alpha:    Alpha Options.       (line  25)
-* -me option, stderr redirect:           TIC54X-Opts.         (line  20)
-* -meis:                                 PDP-11-Options.      (line  46)
-* -merrors-to-file option, stderr redirect: TIC54X-Opts.      (line  20)
-* -mf option, far-mode:                  TIC54X-Opts.         (line   8)
-* -mf11:                                 PDP-11-Options.      (line 122)
-* -mfar-mode option, far-mode:           TIC54X-Opts.         (line   8)
-* -mfis:                                 PDP-11-Options.      (line  51)
-* -mfloat-abi= command line option, ARM: ARM Options.         (line 102)
-* -mfp-11:                               PDP-11-Options.      (line  56)
-* -mfpp:                                 PDP-11-Options.      (line  56)
-* -mfpu:                                 PDP-11-Options.      (line  56)
-* -mfpu= command line option, ARM:       ARM Options.         (line  52)
-* -mip2022 option, IP2K:                 IP2K-Opts.           (line  14)
-* -mip2022ext option, IP2022:            IP2K-Opts.           (line   9)
-* -mj11:                                 PDP-11-Options.      (line 126)
-* -mka11:                                PDP-11-Options.      (line  92)
-* -mkb11:                                PDP-11-Options.      (line  95)
-* -mkd11a:                               PDP-11-Options.      (line  98)
-* -mkd11b:                               PDP-11-Options.      (line 101)
-* -mkd11d:                               PDP-11-Options.      (line 104)
-* -mkd11e:                               PDP-11-Options.      (line 107)
-* -mkd11f:                               PDP-11-Options.      (line 110)
-* -mkd11h:                               PDP-11-Options.      (line 110)
-* -mkd11k:                               PDP-11-Options.      (line 114)
-* -mkd11q:                               PDP-11-Options.      (line 110)
-* -mkd11z:                               PDP-11-Options.      (line 118)
-* -mkev11:                               PDP-11-Options.      (line  51)
-* -mlimited-eis:                         PDP-11-Options.      (line  64)
-* -mlong:                                M68HC11-Opts.        (line  32)
-* -mlong-double:                         M68HC11-Opts.        (line  40)
-* -mmfpt:                                PDP-11-Options.      (line  70)
-* -mmicrocode:                           PDP-11-Options.      (line  83)
-* -mmutiproc:                            PDP-11-Options.      (line  73)
-* -mmxps:                                PDP-11-Options.      (line  77)
-* -mno-cis:                              PDP-11-Options.      (line  32)
-* -mno-csm:                              PDP-11-Options.      (line  43)
-* -mno-eis:                              PDP-11-Options.      (line  46)
-* -mno-extensions:                       PDP-11-Options.      (line  29)
-* -mno-fis:                              PDP-11-Options.      (line  51)
-* -mno-fp-11:                            PDP-11-Options.      (line  56)
-* -mno-fpp:                              PDP-11-Options.      (line  56)
-* -mno-fpu:                              PDP-11-Options.      (line  56)
-* -mno-kev11:                            PDP-11-Options.      (line  51)
-* -mno-limited-eis:                      PDP-11-Options.      (line  64)
-* -mno-mfpt:                             PDP-11-Options.      (line  70)
-* -mno-microcode:                        PDP-11-Options.      (line  83)
-* -mno-mutiproc:                         PDP-11-Options.      (line  73)
-* -mno-mxps:                             PDP-11-Options.      (line  77)
-* -mno-pic:                              PDP-11-Options.      (line  11)
-* -mno-spl:                              PDP-11-Options.      (line  80)
-* -mno-sym32:                            MIPS Opts.           (line 145)
-* -mpic:                                 PDP-11-Options.      (line  11)
-* -mrelax command line option, V850:     V850 Options.        (line  51)
-* -mshort:                               M68HC11-Opts.        (line  27)
-* -mshort-double:                        M68HC11-Opts.        (line  36)
-* -mspl:                                 PDP-11-Options.      (line  80)
-* -msym32:                               MIPS Opts.           (line 145)
-* -mt11:                                 PDP-11-Options.      (line 130)
-* -mthumb command line option, ARM:      ARM Options.         (line  71)
-* -mthumb-interwork command line option, ARM: ARM Options.    (line  76)
-* -mv850 command line option, V850:      V850 Options.        (line  23)
-* -mv850any command line option, V850:   V850 Options.        (line  41)
-* -mv850e command line option, V850:     V850 Options.        (line  29)
-* -mv850e1 command line option, V850:    V850 Options.        (line  35)
-* -N command line option, CRIS:          CRIS-Opts.           (line  57)
-* -nIp option, M32RX:                    M32R-Opts.           (line 101)
-* -no-bitinst, M32R2:                    M32R-Opts.           (line  54)
-* -no-construct-floats:                  MIPS Opts.           (line 157)
-* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts.     (line  93)
-* -no-mdebug command line option, Alpha: Alpha Options.       (line  25)
-* -no-parallel option, M32RX:            M32R-Opts.           (line  51)
-* -no-relax option, i960:                Options-i960.        (line  66)
-* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
-                                                              (line  79)
-* -no-warn-unmatched-high option, M32R:  M32R-Opts.           (line 111)
-* -nocpp ignored (MIPS):                 MIPS Opts.           (line 148)
-* -o:                                    o.                   (line   6)
-* -O option, M32RX:                      M32R-Opts.           (line  59)
-* -parallel option, M32RX:               M32R-Opts.           (line  46)
-* -R:                                    R.                   (line   6)
-* -r800 command line option, Z80:        Z80 Options.         (line  41)
-* -relax command line option, Alpha:     Alpha Options.       (line  32)
-* -S, ignored on VAX:                    VAX-Opts.            (line  11)
-* -t, ignored on VAX:                    VAX-Opts.            (line  36)
-* -T, ignored on VAX:                    VAX-Opts.            (line  11)
-* -v:                                    v.                   (line   6)
-* -V, redundant on VAX:                  VAX-Opts.            (line  22)
-* -version:                              v.                   (line   6)
-* -W:                                    W.                   (line  11)
-* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line  65)
-* -warn-unmatched-high option, M32R:     M32R-Opts.           (line 105)
-* -Wnp option, M32RX:                    M32R-Opts.           (line  83)
-* -Wnuh option, M32RX:                   M32R-Opts.           (line 117)
-* -Wp option, M32RX:                     M32R-Opts.           (line  75)
-* -wsigned_overflow command line option, V850: V850 Options.  (line   9)
-* -Wuh option, M32RX:                    M32R-Opts.           (line 114)
-* -wunsigned_overflow command line option, V850: V850 Options.
-                                                              (line  16)
-* -x command line option, MMIX:          MMIX-Opts.           (line  44)
-* -z80 command line option, Z80:         Z80 Options.         (line   8)
-* -z8001 command line option, Z8000:     Z8000 Options.       (line   6)
-* -z8002 command line option, Z8000:     Z8000 Options.       (line   9)
-* . (symbol):                            Dot.                 (line   6)
-* .arch directive, ARM:                  ARM Directives.      (line 164)
-* .big directive, M32RX:                 M32R-Directives.     (line  88)
-* .cantunwind directive, ARM:            ARM Directives.      (line  87)
-* .cpu directive, ARM:                   ARM Directives.      (line 160)
-* .eabi_attribute directive, ARM:        ARM Directives.      (line 172)
-* .fnend directive, ARM:                 ARM Directives.      (line  78)
-* .fnstart directive, ARM:               ARM Directives.      (line  75)
-* .fpu directive, ARM:                   ARM Directives.      (line 168)
-* .handlerdata directive, ARM:           ARM Directives.      (line  98)
-* .insn:                                 MIPS insn.           (line   6)
-* .little directive, M32RX:              M32R-Directives.     (line  82)
-* .ltorg directive, ARM:                 ARM Directives.      (line  58)
-* .m32r directive, M32R:                 M32R-Directives.     (line  66)
-* .m32r2 directive, M32R2:               M32R-Directives.     (line  77)
-* .m32rx directive, M32RX:               M32R-Directives.     (line  72)
-* .movsp directive, ARM:                 ARM Directives.      (line 136)
-* .o:                                    Object.              (line   6)
-* .pad directive, ARM:                   ARM Directives.      (line 131)
-* .param on HPPA:                        HPPA Directives.     (line  19)
-* .personality directive, ARM:           ARM Directives.      (line  91)
-* .personalityindex directive, ARM:      ARM Directives.      (line  94)
-* .pool directive, ARM:                  ARM Directives.      (line  72)
-* .save directive, ARM:                  ARM Directives.      (line 107)
-* .set autoextend:                       MIPS autoextend.     (line   6)
-* .set dsp:                              MIPS ASE instruction generation overrides.
-                                                              (line  16)
-* .set mdmx:                             MIPS ASE instruction generation overrides.
-                                                              (line  11)
-* .set mips3d:                           MIPS ASE instruction generation overrides.
-                                                              (line   6)
-* .set mipsN:                            MIPS ISA.            (line   6)
-* .set mt:                               MIPS ASE instruction generation overrides.
-                                                              (line  21)
-* .set noautoextend:                     MIPS autoextend.     (line   6)
-* .set nodsp:                            MIPS ASE instruction generation overrides.
-                                                              (line  16)
-* .set nomdmx:                           MIPS ASE instruction generation overrides.
-                                                              (line  11)
-* .set nomips3d:                         MIPS ASE instruction generation overrides.
-                                                              (line   6)
-* .set nomt:                             MIPS ASE instruction generation overrides.
-                                                              (line  21)
-* .set nosym32:                          MIPS symbol sizes.   (line   6)
-* .set pop:                              MIPS option stack.   (line   6)
-* .set push:                             MIPS option stack.   (line   6)
-* .set sym32:                            MIPS symbol sizes.   (line   6)
-* .setfp directive, ARM:                 ARM Directives.      (line 139)
-* .unwind_raw directive, ARM:            ARM Directives.      (line 153)
-* .v850 directive, V850:                 V850 Directives.     (line  14)
-* .v850e directive, V850:                V850 Directives.     (line  20)
-* .v850e1 directive, V850:               V850 Directives.     (line  26)
-* .z8001:                                Z8000 Directives.    (line  11)
-* .z8002:                                Z8000 Directives.    (line  15)
-* 16-bit code, i386:                     i386-16bit.          (line   6)
-* 2byte directive, ARC:                  ARC Directives.      (line   9)
-* 3byte directive, ARC:                  ARC Directives.      (line  12)
-* 3DNow!, i386:                          i386-SIMD.           (line   6)
-* 3DNow!, x86-64:                        i386-SIMD.           (line   6)
-* 430 support:                           MSP430-Dependent.    (line   6)
-* 4byte directive, ARC:                  ARC Directives.      (line  15)
-* : (label):                             Statements.          (line  30)
-* @word modifier, D10V:                  D10V-Word.           (line   6)
-* \" (doublequote character):            Strings.             (line  43)
-* \\ (\ character):                      Strings.             (line  40)
-* \b (backspace character):              Strings.             (line  15)
-* \DDD (octal character code):           Strings.             (line  30)
-* \f (formfeed character):               Strings.             (line  18)
-* \n (newline character):                Strings.             (line  21)
-* \r (carriage return character):        Strings.             (line  24)
-* \t (tab):                              Strings.             (line  27)
-* \XD... (hex character code):           Strings.             (line  36)
-* _ opcode prefix:                       Xtensa Opcodes.      (line   9)
-* a.out:                                 Object.              (line   6)
-* a.out symbol attributes:               a.out Symbols.       (line   6)
-* A_DIR environment variable, TIC54X:    TIC54X-Env.          (line   6)
-* ABI options, SH64:                     SH64 Options.        (line  29)
-* ABORT directive:                       ABORT.               (line   6)
-* abort directive:                       Abort.               (line   6)
-* absolute section:                      Ld Sections.         (line  29)
-* absolute-literals directive:           Absolute Literals Directive.
-                                                              (line   6)
-* ADDI instructions, relaxation:         Xtensa Immediate Relaxation.
-                                                              (line  43)
-* addition, permitted arguments:         Infix Ops.           (line  44)
-* addresses:                             Expressions.         (line   6)
-* addresses, format of:                  Secs Background.     (line  68)
-* addressing modes, D10V:                D10V-Addressing.     (line   6)
-* addressing modes, D30V:                D30V-Addressing.     (line   6)
-* addressing modes, H8/300:              H8/300-Addressing.   (line   6)
-* addressing modes, M680x0:              M68K-Syntax.         (line  21)
-* addressing modes, M68HC11:             M68HC11-Syntax.      (line  17)
-* addressing modes, SH:                  SH-Addressing.       (line   6)
-* addressing modes, SH64:                SH64-Addressing.     (line   6)
-* addressing modes, Z8000:               Z8000-Addressing.    (line   6)
-* ADR reg,<label> pseudo op, ARM:        ARM Opcodes.         (line  25)
-* ADRL reg,<label> pseudo op, ARM:       ARM Opcodes.         (line  35)
-* advancing location counter:            Org.                 (line   6)
-* align directive:                       Align.               (line   6)
-* align directive, ARM:                  ARM Directives.      (line   6)
-* align directive, SPARC:                Sparc-Directives.    (line   9)
-* align directive, TIC54X:               TIC54X-Directives.   (line   6)
-* alignment of branch targets:           Xtensa Automatic Alignment.
-                                                              (line   6)
-* alignment of ENTRY instructions:       Xtensa Automatic Alignment.
-                                                              (line   6)
-* alignment of LOOP instructions:        Xtensa Automatic Alignment.
-                                                              (line   6)
-* Alpha floating point (IEEE):           Alpha Floating Point.
-                                                              (line   6)
-* Alpha line comment character:          Alpha-Chars.         (line   6)
-* Alpha line separator:                  Alpha-Chars.         (line   8)
-* Alpha notes:                           Alpha Notes.         (line   6)
-* Alpha options:                         Alpha Options.       (line   6)
-* Alpha registers:                       Alpha-Regs.          (line   6)
-* Alpha relocations:                     Alpha-Relocs.        (line   6)
-* Alpha support:                         Alpha-Dependent.     (line   6)
-* Alpha Syntax:                          Alpha Options.       (line  54)
-* Alpha-only directives:                 Alpha Directives.    (line  10)
-* altered difference tables:             Word.                (line  12)
-* alternate syntax for the 680x0:        M68K-Moto-Syntax.    (line   6)
-* ARC floating point (IEEE):             ARC Floating Point.  (line   6)
-* ARC machine directives:                ARC Directives.      (line   6)
-* ARC opcodes:                           ARC Opcodes.         (line   6)
-* ARC options (none):                    ARC Options.         (line   6)
-* ARC register names:                    ARC-Regs.            (line   6)
-* ARC special characters:                ARC-Chars.           (line   6)
-* ARC support:                           ARC-Dependent.       (line   6)
-* arc5 arc5, ARC:                        ARC Options.         (line  10)
-* arc6 arc6, ARC:                        ARC Options.         (line  13)
-* arc7 arc7, ARC:                        ARC Options.         (line  21)
-* arc8 arc8, ARC:                        ARC Options.         (line  24)
-* arch directive, i386:                  i386-Arch.           (line   6)
-* arch directive, M680x0:                M68K-Directives.     (line  22)
-* arch directive, x86-64:                i386-Arch.           (line   6)
-* architecture options, i960:            Options-i960.        (line   6)
-* architecture options, IP2022:          IP2K-Opts.           (line   9)
-* architecture options, IP2K:            IP2K-Opts.           (line  14)
-* architecture options, M16C:            M32C-Opts.           (line  12)
-* architecture options, M32C:            M32C-Opts.           (line   9)
-* architecture options, M32R:            M32R-Opts.           (line  21)
-* architecture options, M32R2:           M32R-Opts.           (line  17)
-* architecture options, M32RX:           M32R-Opts.           (line   9)
-* architecture options, M680x0:          M68K-Opts.           (line 103)
-* Architecture variant option, CRIS:     CRIS-Opts.           (line  33)
-* architectures, PowerPC:                PowerPC-Opts.        (line   6)
-* architectures, SPARC:                  Sparc-Opts.          (line   6)
-* arguments for addition:                Infix Ops.           (line  44)
-* arguments for subtraction:             Infix Ops.           (line  49)
-* arguments in expressions:              Arguments.           (line   6)
-* arithmetic functions:                  Operators.           (line   6)
-* arithmetic operands:                   Arguments.           (line   6)
-* arm directive, ARM:                    ARM Directives.      (line  36)
-* ARM floating point (IEEE):             ARM Floating Point.  (line   6)
-* ARM identifiers:                       ARM-Chars.           (line  15)
-* ARM immediate character:               ARM-Chars.           (line  13)
-* ARM line comment character:            ARM-Chars.           (line   6)
-* ARM line separator:                    ARM-Chars.           (line  10)
-* ARM machine directives:                ARM Directives.      (line   6)
-* ARM opcodes:                           ARM Opcodes.         (line   6)
-* ARM options (none):                    ARM Options.         (line   6)
-* ARM register names:                    ARM-Regs.            (line   6)
-* ARM support:                           ARM-Dependent.       (line   6)
-* ascii directive:                       Ascii.               (line   6)
-* asciz directive:                       Asciz.               (line   6)
-* asg directive, TIC54X:                 TIC54X-Directives.   (line  20)
-* assembler bugs, reporting:             Bug Reporting.       (line   6)
-* assembler crash:                       Bug Criteria.        (line   9)
-* assembler directive .arch, CRIS:       CRIS-Pseudos.        (line  45)
-* assembler directive .dword, CRIS:      CRIS-Pseudos.        (line  12)
-* assembler directive .far, M68HC11:     M68HC11-Directives.  (line  20)
-* assembler directive .interrupt, M68HC11: M68HC11-Directives.
-                                                              (line  26)
-* assembler directive .mode, M68HC11:    M68HC11-Directives.  (line  16)
-* assembler directive .relax, M68HC11:   M68HC11-Directives.  (line  10)
-* assembler directive .syntax, CRIS:     CRIS-Pseudos.        (line  17)
-* assembler directive .xrefb, M68HC11:   M68HC11-Directives.  (line  31)
-* assembler directive BSPEC, MMIX:       MMIX-Pseudos.        (line 131)
-* assembler directive BYTE, MMIX:        MMIX-Pseudos.        (line  97)
-* assembler directive ESPEC, MMIX:       MMIX-Pseudos.        (line 131)
-* assembler directive GREG, MMIX:        MMIX-Pseudos.        (line  50)
-* assembler directive IS, MMIX:          MMIX-Pseudos.        (line  42)
-* assembler directive LOC, MMIX:         MMIX-Pseudos.        (line   7)
-* assembler directive LOCAL, MMIX:       MMIX-Pseudos.        (line  28)
-* assembler directive OCTA, MMIX:        MMIX-Pseudos.        (line 108)
-* assembler directive PREFIX, MMIX:      MMIX-Pseudos.        (line 120)
-* assembler directive TETRA, MMIX:       MMIX-Pseudos.        (line 108)
-* assembler directive WYDE, MMIX:        MMIX-Pseudos.        (line 108)
-* assembler directives, CRIS:            CRIS-Pseudos.        (line   6)
-* assembler directives, M68HC11:         M68HC11-Directives.  (line   6)
-* assembler directives, M68HC12:         M68HC11-Directives.  (line   6)
-* assembler directives, MMIX:            MMIX-Pseudos.        (line   6)
-* assembler internal logic error:        As Sections.         (line  13)
-* assembler version:                     v.                   (line   6)
-* assembler, and linker:                 Secs Background.     (line  10)
-* assembly listings, enabling:           a.                   (line   6)
-* assigning values to symbols <1>:       Equ.                 (line   6)
-* assigning values to symbols:           Setting Symbols.     (line   6)
-* atmp directive, i860:                  Directives-i860.     (line  16)
-* att_syntax pseudo op, i386:            i386-Syntax.         (line   6)
-* att_syntax pseudo op, x86-64:          i386-Syntax.         (line   6)
-* attributes, symbol:                    Symbol Attributes.   (line   6)
-* auxiliary attributes, COFF symbols:    COFF Symbols.        (line  19)
-* auxiliary symbol information, COFF:    Dim.                 (line   6)
-* Av7:                                   Sparc-Opts.          (line  25)
-* backslash (\\):                        Strings.             (line  40)
-* backspace (\b):                        Strings.             (line  15)
-* balign directive:                      Balign.              (line   6)
-* balignl directive:                     Balign.              (line  27)
-* balignw directive:                     Balign.              (line  27)
-* bes directive, TIC54X:                 TIC54X-Directives.   (line 197)
-* BFIN directives:                       BFIN Directives.     (line   6)
-* BFIN syntax:                           BFIN Syntax.         (line   6)
-* big endian output, MIPS:               Overview.            (line 606)
-* big endian output, PJ:                 Overview.            (line 513)
-* big-endian output, MIPS:               MIPS Opts.           (line  13)
-* bignums:                               Bignums.             (line   6)
-* binary constants, TIC54X:              TIC54X-Constants.    (line   8)
-* binary files, including:               Incbin.              (line   6)
-* binary integers:                       Integers.            (line   6)
-* bit names, IA-64:                      IA-64-Bits.          (line   6)
-* bitfields, not supported on VAX:       VAX-no.              (line   6)
-* Blackfin support:                      BFIN-Dependent.      (line   6)
-* block:                                 Z8000 Directives.    (line  55)
-* branch improvement, M680x0:            M68K-Branch.         (line   6)
-* branch improvement, M68HC11:           M68HC11-Branch.      (line   6)
-* branch improvement, VAX:               VAX-branch.          (line   6)
-* branch instructions, relaxation:       Xtensa Branch Relaxation.
-                                                              (line   6)
-* branch recording, i960:                Options-i960.        (line  22)
-* branch statistics table, i960:         Options-i960.        (line  40)
-* branch target alignment:               Xtensa Automatic Alignment.
-                                                              (line   6)
-* break directive, TIC54X:               TIC54X-Directives.   (line 143)
-* BSD syntax:                            PDP-11-Syntax.       (line   6)
-* bss directive, i960:                   Directives-i960.     (line   6)
-* bss directive, TIC54X:                 TIC54X-Directives.   (line  29)
-* bss section <1>:                       bss.                 (line   6)
-* bss section:                           Ld Sections.         (line  20)
-* bug criteria:                          Bug Criteria.        (line   6)
-* bug reports:                           Bug Reporting.       (line   6)
-* bugs in assembler:                     Reporting Bugs.      (line   6)
-* Built-in symbols, CRIS:                CRIS-Symbols.        (line   6)
-* builtin math functions, TIC54X:        TIC54X-Builtins.     (line   6)
-* builtin subsym functions, TIC54X:      TIC54X-Macros.       (line  16)
-* bus lock prefixes, i386:               i386-Prefixes.       (line  36)
-* bval:                                  Z8000 Directives.    (line  30)
-* byte directive:                        Byte.                (line   6)
-* byte directive, TIC54X:                TIC54X-Directives.   (line  36)
-* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env.       (line   6)
-* c_mode directive, TIC54X:              TIC54X-Directives.   (line  51)
-* call instructions, i386:               i386-Mnemonics.      (line  51)
-* call instructions, relaxation:         Xtensa Call Relaxation.
-                                                              (line   6)
-* call instructions, x86-64:             i386-Mnemonics.      (line  51)
-* callj, i960 pseudo-opcode:             callj-i960.          (line   6)
-* carriage return (\r):                  Strings.             (line  24)
-* case sensitivity, Z80:                 Z80-Case.            (line   6)
-* cfi_endproc directive:                 CFI directives.      (line  14)
-* cfi_startproc directive:               CFI directives.      (line   6)
-* char directive, TIC54X:                TIC54X-Directives.   (line  36)
-* character constant, Z80:               Z80-Chars.           (line  13)
-* character constants:                   Characters.          (line   6)
-* character escape codes:                Strings.             (line  15)
-* character escapes, Z80:                Z80-Chars.           (line  11)
-* character, single:                     Chars.               (line   6)
-* characters used in symbols:            Symbol Intro.        (line   6)
-* clink directive, TIC54X:               TIC54X-Directives.   (line  45)
-* code directive, ARM:                   ARM Directives.      (line  29)
-* code16 directive, i386:                i386-16bit.          (line   6)
-* code16gcc directive, i386:             i386-16bit.          (line   6)
-* code32 directive, i386:                i386-16bit.          (line   6)
-* code64 directive, i386:                i386-16bit.          (line   6)
-* code64 directive, x86-64:              i386-16bit.          (line   6)
-* COFF auxiliary symbol information:     Dim.                 (line   6)
-* COFF structure debugging:              Tag.                 (line   6)
-* COFF symbol attributes:                COFF Symbols.        (line   6)
-* COFF symbol descriptor:                Desc.                (line   6)
-* COFF symbol storage class:             Scl.                 (line   6)
-* COFF symbol type:                      Type.                (line  11)
-* COFF symbols, debugging:               Def.                 (line   6)
-* COFF value attribute:                  Val.                 (line   6)
-* COMDAT:                                Linkonce.            (line   6)
-* comm directive:                        Comm.                (line   6)
-* command line conventions:              Command Line.        (line   6)
-* command line options, V850:            V850 Options.        (line   9)
-* command-line options ignored, VAX:     VAX-Opts.            (line   6)
-* comments:                              Comments.            (line   6)
-* comments, M680x0:                      M68K-Chars.          (line   6)
-* comments, removed by preprocessor:     Preprocessing.       (line  11)
-* common directive, SPARC:               Sparc-Directives.    (line  12)
-* common sections:                       Linkonce.            (line   6)
-* common variable storage:               bss.                 (line   6)
-* compare and jump expansions, i960:     Compare-and-branch-i960.
-                                                              (line  13)
-* compare/branch instructions, i960:     Compare-and-branch-i960.
-                                                              (line   6)
-* comparison expressions:                Infix Ops.           (line  55)
-* conditional assembly:                  If.                  (line   6)
-* constant, single character:            Chars.               (line   6)
-* constants:                             Constants.           (line   6)
-* constants, bignum:                     Bignums.             (line   6)
-* constants, character:                  Characters.          (line   6)
-* constants, converted by preprocessor:  Preprocessing.       (line  14)
-* constants, floating point:             Flonums.             (line   6)
-* constants, integer:                    Integers.            (line   6)
-* constants, number:                     Numbers.             (line   6)
-* constants, string:                     Strings.             (line   6)
-* constants, TIC54X:                     TIC54X-Constants.    (line   6)
-* conversion instructions, i386:         i386-Mnemonics.      (line  32)
-* conversion instructions, x86-64:       i386-Mnemonics.      (line  32)
-* coprocessor wait, i386:                i386-Prefixes.       (line  40)
-* copy directive, TIC54X:                TIC54X-Directives.   (line  54)
-* cpu directive, M680x0:                 M68K-Directives.     (line  30)
-* crash of assembler:                    Bug Criteria.        (line   9)
-* CRIS --emulation=crisaout command line option: CRIS-Opts.   (line   9)
-* CRIS --emulation=criself command line option: CRIS-Opts.    (line   9)
-* CRIS --march=ARCHITECTURE command line option: CRIS-Opts.   (line  33)
-* CRIS --mul-bug-abort command line option: CRIS-Opts.        (line  61)
-* CRIS --no-mul-bug-abort command line option: CRIS-Opts.     (line  61)
-* CRIS --no-underscore command line option: CRIS-Opts.        (line  15)
-* CRIS --pic command line option:        CRIS-Opts.           (line  27)
-* CRIS --underscore command line option: CRIS-Opts.           (line  15)
-* CRIS -N command line option:           CRIS-Opts.           (line  57)
-* CRIS architecture variant option:      CRIS-Opts.           (line  33)
-* CRIS assembler directive .arch:        CRIS-Pseudos.        (line  45)
-* CRIS assembler directive .dword:       CRIS-Pseudos.        (line  12)
-* CRIS assembler directive .syntax:      CRIS-Pseudos.        (line  17)
-* CRIS assembler directives:             CRIS-Pseudos.        (line   6)
-* CRIS built-in symbols:                 CRIS-Symbols.        (line   6)
-* CRIS instruction expansion:            CRIS-Expand.         (line   6)
-* CRIS line comment characters:          CRIS-Chars.          (line   6)
-* CRIS options:                          CRIS-Opts.           (line   6)
-* CRIS position-independent code:        CRIS-Opts.           (line  27)
-* CRIS pseudo-op .arch:                  CRIS-Pseudos.        (line  45)
-* CRIS pseudo-op .dword:                 CRIS-Pseudos.        (line  12)
-* CRIS pseudo-op .syntax:                CRIS-Pseudos.        (line  17)
-* CRIS pseudo-ops:                       CRIS-Pseudos.        (line   6)
-* CRIS register names:                   CRIS-Regs.           (line   6)
-* CRIS support:                          CRIS-Dependent.      (line   6)
-* CRIS symbols in position-independent code: CRIS-Pic.        (line   6)
-* ctbp register, V850:                   V850-Regs.           (line 131)
-* ctoff pseudo-op, V850:                 V850 Opcodes.        (line 111)
-* ctpc register, V850:                   V850-Regs.           (line 119)
-* ctpsw register, V850:                  V850-Regs.           (line 122)
-* current address:                       Dot.                 (line   6)
-* current address, advancing:            Org.                 (line   6)
-* D10V @word modifier:                   D10V-Word.           (line   6)
-* D10V addressing modes:                 D10V-Addressing.     (line   6)
-* D10V floating point:                   D10V-Float.          (line   6)
-* D10V line comment character:           D10V-Chars.          (line   6)
-* D10V opcode summary:                   D10V-Opcodes.        (line   6)
-* D10V optimization:                     Overview.            (line 391)
-* D10V options:                          D10V-Opts.           (line   6)
-* D10V registers:                        D10V-Regs.           (line   6)
-* D10V size modifiers:                   D10V-Size.           (line   6)
-* D10V sub-instruction ordering:         D10V-Chars.          (line   6)
-* D10V sub-instructions:                 D10V-Subs.           (line   6)
-* D10V support:                          D10V-Dependent.      (line   6)
-* D10V syntax:                           D10V-Syntax.         (line   6)
-* D30V addressing modes:                 D30V-Addressing.     (line   6)
-* D30V floating point:                   D30V-Float.          (line   6)
-* D30V Guarded Execution:                D30V-Guarded.        (line   6)
-* D30V line comment character:           D30V-Chars.          (line   6)
-* D30V nops:                             Overview.            (line 399)
-* D30V nops after 32-bit multiply:       Overview.            (line 402)
-* D30V opcode summary:                   D30V-Opcodes.        (line   6)
-* D30V optimization:                     Overview.            (line 396)
-* D30V options:                          D30V-Opts.           (line   6)
-* D30V registers:                        D30V-Regs.           (line   6)
-* D30V size modifiers:                   D30V-Size.           (line   6)
-* D30V sub-instruction ordering:         D30V-Chars.          (line   6)
-* D30V sub-instructions:                 D30V-Subs.           (line   6)
-* D30V support:                          D30V-Dependent.      (line   6)
-* D30V syntax:                           D30V-Syntax.         (line   6)
-* data alignment on SPARC:               Sparc-Aligned-Data.  (line   6)
-* data and text sections, joining:       R.                   (line   6)
-* data directive:                        Data.                (line   6)
-* data directive, TIC54X:                TIC54X-Directives.   (line  61)
-* data section:                          Ld Sections.         (line   9)
-* data1 directive, M680x0:               M68K-Directives.     (line   9)
-* data2 directive, M680x0:               M68K-Directives.     (line  12)
-* datalabel, SH64:                       SH64-Addressing.     (line  16)
-* dbpc register, V850:                   V850-Regs.           (line 125)
-* dbpsw register, V850:                  V850-Regs.           (line 128)
-* debuggers, and symbol order:           Symbols.             (line  10)
-* debugging COFF symbols:                Def.                 (line   6)
-* DEC syntax:                            PDP-11-Syntax.       (line   6)
-* decimal integers:                      Integers.            (line  12)
-* def directive:                         Def.                 (line   6)
-* def directive, TIC54X:                 TIC54X-Directives.   (line 103)
-* density instructions:                  Density Instructions.
-                                                              (line   6)
-* dependency tracking:                   MD.                  (line   6)
-* deprecated directives:                 Deprecated.          (line   6)
-* desc directive:                        Desc.                (line   6)
-* descriptor, of a.out symbol:           Symbol Desc.         (line   6)
-* dfloat directive, VAX:                 VAX-directives.      (line  10)
-* difference tables altered:             Word.                (line  12)
-* difference tables, warning:            K.                   (line   6)
-* differences, mmixal:                   MMIX-mmixal.         (line   6)
-* dim directive:                         Dim.                 (line   6)
-* directives and instructions:           Statements.          (line  19)
-* directives for PowerPC:                PowerPC-Pseudo.      (line   6)
-* directives, BFIN:                      BFIN Directives.     (line   6)
-* directives, M32R:                      M32R-Directives.     (line   6)
-* directives, M680x0:                    M68K-Directives.     (line   6)
-* directives, machine independent:       Pseudo Ops.          (line   6)
-* directives, Xtensa:                    Xtensa Directives.   (line   6)
-* directives, Z8000:                     Z8000 Directives.    (line   6)
-* displacement sizing character, VAX:    VAX-operands.        (line  12)
-* dollar local symbols:                  Symbol Names.        (line  91)
-* dot (symbol):                          Dot.                 (line   6)
-* double directive:                      Double.              (line   6)
-* double directive, i386:                i386-Float.          (line  14)
-* double directive, M680x0:              M68K-Float.          (line  14)
-* double directive, M68HC11:             M68HC11-Float.       (line  14)
-* double directive, TIC54X:              TIC54X-Directives.   (line  64)
-* double directive, VAX:                 VAX-float.           (line  15)
-* double directive, x86-64:              i386-Float.          (line  14)
-* doublequote (\"):                      Strings.             (line  43)
-* drlist directive, TIC54X:              TIC54X-Directives.   (line  73)
-* drnolist directive, TIC54X:            TIC54X-Directives.   (line  73)
-* dual directive, i860:                  Directives-i860.     (line   6)
-* ECOFF sections:                        MIPS Object.         (line   6)
-* ecr register, V850:                    V850-Regs.           (line 113)
-* eight-byte integer:                    Quad.                (line   9)
-* eipc register, V850:                   V850-Regs.           (line 101)
-* eipsw register, V850:                  V850-Regs.           (line 104)
-* eject directive:                       Eject.               (line   6)
-* ELF symbol type:                       Type.                (line  22)
-* else directive:                        Else.                (line   6)
-* elseif directive:                      Elseif.              (line   6)
-* empty expressions:                     Empty Exprs.         (line   6)
-* emsg directive, TIC54X:                TIC54X-Directives.   (line  77)
-* emulation:                             Overview.            (line 697)
-* end directive:                         End.                 (line   6)
-* enddual directive, i860:               Directives-i860.     (line  11)
-* endef directive:                       Endef.               (line   6)
-* endfunc directive:                     Endfunc.             (line   6)
-* endianness, MIPS:                      Overview.            (line 606)
-* endianness, PJ:                        Overview.            (line 513)
-* endif directive:                       Endif.               (line   6)
-* endloop directive, TIC54X:             TIC54X-Directives.   (line 143)
-* endm directive:                        Macro.               (line  96)
-* endm directive, TIC54X:                TIC54X-Directives.   (line 153)
-* endstruct directive, TIC54X:           TIC54X-Directives.   (line 217)
-* endunion directive, TIC54X:            TIC54X-Directives.   (line 251)
-* ENTRY instructions, alignment:         Xtensa Automatic Alignment.
-                                                              (line   6)
-* environment settings, TIC54X:          TIC54X-Env.          (line   6)
-* EOF, newline must precede:             Statements.          (line  13)
-* ep register, V850:                     V850-Regs.           (line  95)
-* equ directive:                         Equ.                 (line   6)
-* equ directive, TIC54X:                 TIC54X-Directives.   (line 192)
-* equiv directive:                       Equiv.               (line   6)
-* eqv directive:                         Eqv.                 (line   6)
-* err directive:                         Err.                 (line   6)
-* error directive:                       Error.               (line   6)
-* error messages:                        Errors.              (line   6)
-* error on valid input:                  Bug Criteria.        (line  12)
-* errors, caused by warnings:            W.                   (line  16)
-* errors, continuing after:              Z.                   (line   6)
-* ESA/390 floating point (IEEE):         ESA/390 Floating Point.
-                                                              (line   6)
-* ESA/390 support:                       ESA/390-Dependent.   (line   6)
-* ESA/390 Syntax:                        ESA/390 Options.     (line   8)
-* ESA/390-only directives:               ESA/390 Directives.  (line  12)
-* escape codes, character:               Strings.             (line  15)
-* eval directive, TIC54X:                TIC54X-Directives.   (line  24)
-* even:                                  Z8000 Directives.    (line  58)
-* even directive, M680x0:                M68K-Directives.     (line  15)
-* even directive, TIC54X:                TIC54X-Directives.   (line   6)
-* exitm directive:                       Macro.               (line  99)
-* expr (internal section):               As Sections.         (line  17)
-* expression arguments:                  Arguments.           (line   6)
-* expressions:                           Expressions.         (line   6)
-* expressions, comparison:               Infix Ops.           (line  55)
-* expressions, empty:                    Empty Exprs.         (line   6)
-* expressions, integer:                  Integer Exprs.       (line   6)
-* extAuxRegister directive, ARC:         ARC Directives.      (line  18)
-* extCondCode directive, ARC:            ARC Directives.      (line  41)
-* extCoreRegister directive, ARC:        ARC Directives.      (line  53)
-* extend directive M680x0:               M68K-Float.          (line  17)
-* extend directive M68HC11:              M68HC11-Float.       (line  17)
-* extended directive, i960:              Directives-i960.     (line  13)
-* extern directive:                      Extern.              (line   6)
-* extInstruction directive, ARC:         ARC Directives.      (line  78)
-* fail directive:                        Fail.                (line   6)
-* far_mode directive, TIC54X:            TIC54X-Directives.   (line  82)
-* faster processing (-f):                f.                   (line   6)
-* fatal signal:                          Bug Criteria.        (line   9)
-* fclist directive, TIC54X:              TIC54X-Directives.   (line  87)
-* fcnolist directive, TIC54X:            TIC54X-Directives.   (line  87)
-* fepc register, V850:                   V850-Regs.           (line 107)
-* fepsw register, V850:                  V850-Regs.           (line 110)
-* ffloat directive, VAX:                 VAX-directives.      (line  14)
-* field directive, TIC54X:               TIC54X-Directives.   (line  91)
-* file directive <1>:                    File.                (line   6)
-* file directive:                        LNS directives.      (line   6)
-* file directive, MSP 430:               MSP430 Directives.   (line   6)
-* file name, logical:                    File.                (line   6)
-* files, including:                      Include.             (line   6)
-* files, input:                          Input Files.         (line   6)
-* fill directive:                        Fill.                (line   6)
-* filling memory <1>:                    Space.               (line   6)
-* filling memory:                        Skip.                (line   6)
-* FLIX syntax:                           Xtensa Syntax.       (line   6)
-* float directive:                       Float.               (line   6)
-* float directive, i386:                 i386-Float.          (line  14)
-* float directive, M680x0:               M68K-Float.          (line  11)
-* float directive, M68HC11:              M68HC11-Float.       (line  11)
-* float directive, TIC54X:               TIC54X-Directives.   (line  64)
-* float directive, VAX:                  VAX-float.           (line  15)
-* float directive, x86-64:               i386-Float.          (line  14)
-* floating point numbers:                Flonums.             (line   6)
-* floating point numbers (double):       Double.              (line   6)
-* floating point numbers (single) <1>:   Single.              (line   6)
-* floating point numbers (single):       Float.               (line   6)
-* floating point, Alpha (IEEE):          Alpha Floating Point.
-                                                              (line   6)
-* floating point, ARC (IEEE):            ARC Floating Point.  (line   6)
-* floating point, ARM (IEEE):            ARM Floating Point.  (line   6)
-* floating point, D10V:                  D10V-Float.          (line   6)
-* floating point, D30V:                  D30V-Float.          (line   6)
-* floating point, ESA/390 (IEEE):        ESA/390 Floating Point.
-                                                              (line   6)
-* floating point, H8/300 (IEEE):         H8/300 Floating Point.
-                                                              (line   6)
-* floating point, HPPA (IEEE):           HPPA Floating Point. (line   6)
-* floating point, i386:                  i386-Float.          (line   6)
-* floating point, i960 (IEEE):           Floating Point-i960. (line   6)
-* floating point, M680x0:                M68K-Float.          (line   6)
-* floating point, M68HC11:               M68HC11-Float.       (line   6)
-* floating point, MSP 430 (IEEE):        MSP430 Floating Point.
-                                                              (line   6)
-* floating point, SH (IEEE):             SH Floating Point.   (line   6)
-* floating point, SPARC (IEEE):          Sparc-Float.         (line   6)
-* floating point, V850 (IEEE):           V850 Floating Point. (line   6)
-* floating point, VAX:                   VAX-float.           (line   6)
-* floating point, x86-64:                i386-Float.          (line   6)
-* floating point, Z80:                   Z80 Floating Point.  (line   6)
-* flonums:                               Flonums.             (line   6)
-* force_thumb directive, ARM:            ARM Directives.      (line  39)
-* format of error messages:              Errors.              (line  24)
-* format of warning messages:            Errors.              (line  12)
-* formfeed (\f):                         Strings.             (line  18)
-* func directive:                        Func.                (line   6)
-* functions, in expressions:             Operators.           (line   6)
-* gbr960, i960 postprocessor:            Options-i960.        (line  40)
-* gfloat directive, VAX:                 VAX-directives.      (line  18)
-* global:                                Z8000 Directives.    (line  21)
-* global directive:                      Global.              (line   6)
-* global directive, TIC54X:              TIC54X-Directives.   (line 103)
-* gp register, MIPS:                     MIPS Object.         (line  11)
-* gp register, V850:                     V850-Regs.           (line  17)
-* grouping data:                         Sub-Sections.        (line   6)
-* H8/300 addressing modes:               H8/300-Addressing.   (line   6)
-* H8/300 floating point (IEEE):          H8/300 Floating Point.
-                                                              (line   6)
-* H8/300 line comment character:         H8/300-Chars.        (line   6)
-* H8/300 line separator:                 H8/300-Chars.        (line   8)
-* H8/300 machine directives (none):      H8/300 Directives.   (line   6)
-* H8/300 opcode summary:                 H8/300 Opcodes.      (line   6)
-* H8/300 options (none):                 H8/300 Options.      (line   6)
-* H8/300 registers:                      H8/300-Regs.         (line   6)
-* H8/300 size suffixes:                  H8/300 Opcodes.      (line 163)
-* H8/300 support:                        H8/300-Dependent.    (line   6)
-* H8/300H, assembling for:               H8/300 Directives.   (line   8)
-* half directive, ARC:                   ARC Directives.      (line 156)
-* half directive, SPARC:                 Sparc-Directives.    (line  17)
-* half directive, TIC54X:                TIC54X-Directives.   (line 111)
-* hex character code (\XD...):           Strings.             (line  36)
-* hexadecimal integers:                  Integers.            (line  15)
-* hexadecimal prefix, Z80:               Z80-Chars.           (line   8)
-* hfloat directive, VAX:                 VAX-directives.      (line  22)
-* hi pseudo-op, V850:                    V850 Opcodes.        (line  33)
-* hi0 pseudo-op, V850:                   V850 Opcodes.        (line  10)
-* hidden directive:                      Hidden.              (line   6)
-* high directive, M32R:                  M32R-Directives.     (line  18)
-* hilo pseudo-op, V850:                  V850 Opcodes.        (line  55)
-* HPPA directives not supported:         HPPA Directives.     (line  11)
-* HPPA floating point (IEEE):            HPPA Floating Point. (line   6)
-* HPPA Syntax:                           HPPA Options.        (line   8)
-* HPPA-only directives:                  HPPA Directives.     (line  24)
-* hword directive:                       hword.               (line   6)
-* i370 support:                          ESA/390-Dependent.   (line   6)
-* i386 16-bit code:                      i386-16bit.          (line   6)
-* i386 arch directive:                   i386-Arch.           (line   6)
-* i386 att_syntax pseudo op:             i386-Syntax.         (line   6)
-* i386 conversion instructions:          i386-Mnemonics.      (line  32)
-* i386 floating point:                   i386-Float.          (line   6)
-* i386 immediate operands:               i386-Syntax.         (line  15)
-* i386 instruction naming:               i386-Mnemonics.      (line   6)
-* i386 instruction prefixes:             i386-Prefixes.       (line   6)
-* i386 intel_syntax pseudo op:           i386-Syntax.         (line   6)
-* i386 jump optimization:                i386-Jumps.          (line   6)
-* i386 jump, call, return:               i386-Syntax.         (line  38)
-* i386 jump/call operands:               i386-Syntax.         (line  15)
-* i386 memory references:                i386-Memory.         (line   6)
-* i386 mul, imul instructions:           i386-Notes.          (line   6)
-* i386 options:                          i386-Options.        (line   6)
-* i386 register operands:                i386-Syntax.         (line  15)
-* i386 registers:                        i386-Regs.           (line   6)
-* i386 sections:                         i386-Syntax.         (line  44)
-* i386 size suffixes:                    i386-Syntax.         (line  29)
-* i386 source, destination operands:     i386-Syntax.         (line  22)
-* i386 support:                          i386-Dependent.      (line   6)
-* i386 syntax compatibility:             i386-Syntax.         (line   6)
-* i80306 support:                        i386-Dependent.      (line   6)
-* i860 machine directives:               Directives-i860.     (line   6)
-* i860 opcodes:                          Opcodes for i860.    (line   6)
-* i860 support:                          i860-Dependent.      (line   6)
-* i960 architecture options:             Options-i960.        (line   6)
-* i960 branch recording:                 Options-i960.        (line  22)
-* i960 callj pseudo-opcode:              callj-i960.          (line   6)
-* i960 compare and jump expansions:      Compare-and-branch-i960.
-                                                              (line  13)
-* i960 compare/branch instructions:      Compare-and-branch-i960.
-                                                              (line   6)
-* i960 floating point (IEEE):            Floating Point-i960. (line   6)
-* i960 machine directives:               Directives-i960.     (line   6)
-* i960 opcodes:                          Opcodes for i960.    (line   6)
-* i960 options:                          Options-i960.        (line   6)
-* i960 support:                          i960-Dependent.      (line   6)
-* IA-64 line comment character:          IA-64-Chars.         (line   6)
-* IA-64 line separator:                  IA-64-Chars.         (line   8)
-* IA-64 options:                         IA-64 Options.       (line   6)
-* IA-64 Processor-status-Register bit names: IA-64-Bits.      (line   6)
-* IA-64 registers:                       IA-64-Regs.          (line   6)
-* IA-64 support:                         IA-64-Dependent.     (line   6)
-* IA-64 Syntax:                          IA-64 Options.       (line  96)
-* ident directive:                       Ident.               (line   6)
-* identifiers, ARM:                      ARM-Chars.           (line  15)
-* identifiers, MSP 430:                  MSP430-Chars.        (line   8)
-* if directive:                          If.                  (line   6)
-* ifb directive:                         If.                  (line  21)
-* ifc directive:                         If.                  (line  25)
-* ifdef directive:                       If.                  (line  16)
-* ifeq directive:                        If.                  (line  33)
-* ifeqs directive:                       If.                  (line  36)
-* ifge directive:                        If.                  (line  40)
-* ifgt directive:                        If.                  (line  44)
-* ifle directive:                        If.                  (line  48)
-* iflt directive:                        If.                  (line  52)
-* ifnb directive:                        If.                  (line  56)
-* ifnc directive:                        If.                  (line  61)
-* ifndef directive:                      If.                  (line  65)
-* ifne directive:                        If.                  (line  72)
-* ifnes directive:                       If.                  (line  76)
-* ifnotdef directive:                    If.                  (line  65)
-* immediate character, ARM:              ARM-Chars.           (line  13)
-* immediate character, M680x0:           M68K-Chars.          (line   6)
-* immediate character, VAX:              VAX-operands.        (line   6)
-* immediate fields, relaxation:          Xtensa Immediate Relaxation.
-                                                              (line   6)
-* immediate operands, i386:              i386-Syntax.         (line  15)
-* immediate operands, x86-64:            i386-Syntax.         (line  15)
-* imul instruction, i386:                i386-Notes.          (line   6)
-* imul instruction, x86-64:              i386-Notes.          (line   6)
-* incbin directive:                      Incbin.              (line   6)
-* include directive:                     Include.             (line   6)
-* include directive search path:         I.                   (line   6)
-* indirect character, VAX:               VAX-operands.        (line   9)
-* infix operators:                       Infix Ops.           (line   6)
-* inhibiting interrupts, i386:           i386-Prefixes.       (line  36)
-* input:                                 Input Files.         (line   6)
-* input file linenumbers:                Input Files.         (line  35)
-* instruction expansion, CRIS:           CRIS-Expand.         (line   6)
-* instruction expansion, MMIX:           MMIX-Expand.         (line   6)
-* instruction naming, i386:              i386-Mnemonics.      (line   6)
-* instruction naming, x86-64:            i386-Mnemonics.      (line   6)
-* instruction prefixes, i386:            i386-Prefixes.       (line   6)
-* instruction set, M680x0:               M68K-opcodes.        (line   6)
-* instruction set, M68HC11:              M68HC11-opcodes.     (line   6)
-* instruction summary, D10V:             D10V-Opcodes.        (line   6)
-* instruction summary, D30V:             D30V-Opcodes.        (line   6)
-* instruction summary, H8/300:           H8/300 Opcodes.      (line   6)
-* instruction summary, SH:               SH Opcodes.          (line   6)
-* instruction summary, SH64:             SH64 Opcodes.        (line   6)
-* instruction summary, Z8000:            Z8000 Opcodes.       (line   6)
-* instructions and directives:           Statements.          (line  19)
-* int directive:                         Int.                 (line   6)
-* int directive, H8/300:                 H8/300 Directives.   (line   6)
-* int directive, i386:                   i386-Float.          (line  21)
-* int directive, TIC54X:                 TIC54X-Directives.   (line 111)
-* int directive, x86-64:                 i386-Float.          (line  21)
-* integer expressions:                   Integer Exprs.       (line   6)
-* integer, 16-byte:                      Octa.                (line   6)
-* integer, 8-byte:                       Quad.                (line   9)
-* integers:                              Integers.            (line   6)
-* integers, 16-bit:                      hword.               (line   6)
-* integers, 32-bit:                      Int.                 (line   6)
-* integers, binary:                      Integers.            (line   6)
-* integers, decimal:                     Integers.            (line  12)
-* integers, hexadecimal:                 Integers.            (line  15)
-* integers, octal:                       Integers.            (line   9)
-* integers, one byte:                    Byte.                (line   6)
-* intel_syntax pseudo op, i386:          i386-Syntax.         (line   6)
-* intel_syntax pseudo op, x86-64:        i386-Syntax.         (line   6)
-* internal assembler sections:           As Sections.         (line   6)
-* internal directive:                    Internal.            (line   6)
-* invalid input:                         Bug Criteria.        (line  14)
-* invocation summary:                    Overview.            (line   6)
-* IP2K architecture options:             IP2K-Opts.           (line   9)
-* IP2K options:                          IP2K-Opts.           (line   6)
-* IP2K support:                          IP2K-Dependent.      (line   6)
-* irp directive:                         Irp.                 (line   6)
-* irpc directive:                        Irpc.                (line   6)
-* ISA options, SH64:                     SH64 Options.        (line   6)
-* joining text and data sections:        R.                   (line   6)
-* jump instructions, i386:               i386-Mnemonics.      (line  51)
-* jump instructions, x86-64:             i386-Mnemonics.      (line  51)
-* jump optimization, i386:               i386-Jumps.          (line   6)
-* jump optimization, x86-64:             i386-Jumps.          (line   6)
-* jump/call operands, i386:              i386-Syntax.         (line  15)
-* jump/call operands, x86-64:            i386-Syntax.         (line  15)
-* L16SI instructions, relaxation:        Xtensa Immediate Relaxation.
-                                                              (line  23)
-* L16UI instructions, relaxation:        Xtensa Immediate Relaxation.
-                                                              (line  23)
-* L32I instructions, relaxation:         Xtensa Immediate Relaxation.
-                                                              (line  23)
-* L8UI instructions, relaxation:         Xtensa Immediate Relaxation.
-                                                              (line  23)
-* label (:):                             Statements.          (line  30)
-* label directive, TIC54X:               TIC54X-Directives.   (line 123)
-* labels:                                Labels.              (line   6)
-* lcomm directive:                       Lcomm.               (line   6)
-* ld:                                    Object.              (line  15)
-* ldouble directive M680x0:              M68K-Float.          (line  17)
-* ldouble directive M68HC11:             M68HC11-Float.       (line  17)
-* ldouble directive, TIC54X:             TIC54X-Directives.   (line  64)
-* LDR reg,=<label> pseudo op, ARM:       ARM Opcodes.         (line  15)
-* leafproc directive, i960:              Directives-i960.     (line  18)
-* length directive, TIC54X:              TIC54X-Directives.   (line 127)
-* length of symbols:                     Symbol Intro.        (line  14)
-* lflags directive (ignored):            Lflags.              (line   6)
-* line comment character:                Comments.            (line  19)
-* line comment character, Alpha:         Alpha-Chars.         (line   6)
-* line comment character, ARM:           ARM-Chars.           (line   6)
-* line comment character, D10V:          D10V-Chars.          (line   6)
-* line comment character, D30V:          D30V-Chars.          (line   6)
-* line comment character, H8/300:        H8/300-Chars.        (line   6)
-* line comment character, IA-64:         IA-64-Chars.         (line   6)
-* line comment character, M680x0:        M68K-Chars.          (line   6)
-* line comment character, MSP 430:       MSP430-Chars.        (line   6)
-* line comment character, SH:            SH-Chars.            (line   6)
-* line comment character, SH64:          SH64-Chars.          (line   6)
-* line comment character, V850:          V850-Chars.          (line   6)
-* line comment character, Z80:           Z80-Chars.           (line   6)
-* line comment character, Z8000:         Z8000-Chars.         (line   6)
-* line comment characters, CRIS:         CRIS-Chars.          (line   6)
-* line comment characters, MMIX:         MMIX-Chars.          (line   6)
-* line directive:                        Line.                (line   6)
-* line directive, MSP 430:               MSP430 Directives.   (line  14)
-* line numbers, in input files:          Input Files.         (line  35)
-* line numbers, in warnings/errors:      Errors.              (line  16)
-* line separator character:              Statements.          (line   6)
-* line separator, Alpha:                 Alpha-Chars.         (line   8)
-* line separator, ARM:                   ARM-Chars.           (line  10)
-* line separator, H8/300:                H8/300-Chars.        (line   8)
-* line separator, IA-64:                 IA-64-Chars.         (line   8)
-* line separator, SH:                    SH-Chars.            (line   8)
-* line separator, SH64:                  SH64-Chars.          (line   8)
-* line separator, Z8000:                 Z8000-Chars.         (line   8)
-* lines starting with #:                 Comments.            (line  38)
-* linker:                                Object.              (line  15)
-* linker, and assembler:                 Secs Background.     (line  10)
-* linkonce directive:                    Linkonce.            (line   6)
-* list directive:                        List.                (line   6)
-* list directive, TIC54X:                TIC54X-Directives.   (line 131)
-* listing control, turning off:          Nolist.              (line   6)
-* listing control, turning on:           List.                (line   6)
-* listing control: new page:             Eject.               (line   6)
-* listing control: paper size:           Psize.               (line   6)
-* listing control: subtitle:             Sbttl.               (line   6)
-* listing control: title line:           Title.               (line   6)
-* listings, enabling:                    a.                   (line   6)
-* literal directive:                     Literal Directive.   (line   6)
-* literal_position directive:            Literal Position Directive.
-                                                              (line   6)
-* literal_prefix directive:              Literal Prefix Directive.
-                                                              (line   6)
-* little endian output, MIPS:            Overview.            (line 609)
-* little endian output, PJ:              Overview.            (line 516)
-* little-endian output, MIPS:            MIPS Opts.           (line  13)
-* ln directive:                          Ln.                  (line   6)
-* lo pseudo-op, V850:                    V850 Opcodes.        (line  22)
-* loc directive:                         LNS directives.      (line  19)
-* loc_mark_blocks directive:             LNS directives.      (line  50)
-* local common symbols:                  Lcomm.               (line   6)
-* local labels, retaining in output:     L.                   (line   6)
-* local symbol names:                    Symbol Names.        (line  22)
-* location counter:                      Dot.                 (line   6)
-* location counter, advancing:           Org.                 (line   6)
-* location counter, Z80:                 Z80-Chars.           (line   8)
-* logical file name:                     File.                (line   6)
-* logical line number:                   Line.                (line   6)
-* logical line numbers:                  Comments.            (line  38)
-* long directive:                        Long.                (line   6)
-* long directive, ARC:                   ARC Directives.      (line 159)
-* long directive, i386:                  i386-Float.          (line  21)
-* long directive, TIC54X:                TIC54X-Directives.   (line 135)
-* long directive, x86-64:                i386-Float.          (line  21)
-* longcall pseudo-op, V850:              V850 Opcodes.        (line 123)
-* longcalls directive:                   Longcalls Directive. (line   6)
-* longjump pseudo-op, V850:              V850 Opcodes.        (line 129)
-* loop directive, TIC54X:                TIC54X-Directives.   (line 143)
-* LOOP instructions, alignment:          Xtensa Automatic Alignment.
-                                                              (line   6)
-* low directive, M32R:                   M32R-Directives.     (line   9)
-* lp register, V850:                     V850-Regs.           (line  98)
-* lval:                                  Z8000 Directives.    (line  27)
-* M16C architecture option:              M32C-Opts.           (line  12)
-* M32C architecture option:              M32C-Opts.           (line   9)
-* M32C modifiers:                        M32C-Modifiers.      (line   6)
-* M32C options:                          M32C-Opts.           (line   6)
-* M32C support:                          M32C-Dependent.      (line   6)
-* M32R architecture options:             M32R-Opts.           (line   9)
-* M32R directives:                       M32R-Directives.     (line   6)
-* M32R options:                          M32R-Opts.           (line   6)
-* M32R support:                          M32R-Dependent.      (line   6)
-* M32R warnings:                         M32R-Warnings.       (line   6)
-* M680x0 addressing modes:               M68K-Syntax.         (line  21)
-* M680x0 architecture options:           M68K-Opts.           (line 103)
-* M680x0 branch improvement:             M68K-Branch.         (line   6)
-* M680x0 directives:                     M68K-Directives.     (line   6)
-* M680x0 floating point:                 M68K-Float.          (line   6)
-* M680x0 immediate character:            M68K-Chars.          (line   6)
-* M680x0 line comment character:         M68K-Chars.          (line   6)
-* M680x0 opcodes:                        M68K-opcodes.        (line   6)
-* M680x0 options:                        M68K-Opts.           (line   6)
-* M680x0 pseudo-opcodes:                 M68K-Branch.         (line   6)
-* M680x0 size modifiers:                 M68K-Syntax.         (line   8)
-* M680x0 support:                        M68K-Dependent.      (line   6)
-* M680x0 syntax:                         M68K-Syntax.         (line   8)
-* M68HC11 addressing modes:              M68HC11-Syntax.      (line  17)
-* M68HC11 and M68HC12 support:           M68HC11-Dependent.   (line   6)
-* M68HC11 assembler directive .far:      M68HC11-Directives.  (line  20)
-* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line  26)
-* M68HC11 assembler directive .mode:     M68HC11-Directives.  (line  16)
-* M68HC11 assembler directive .relax:    M68HC11-Directives.  (line  10)
-* M68HC11 assembler directive .xrefb:    M68HC11-Directives.  (line  31)
-* M68HC11 assembler directives:          M68HC11-Directives.  (line   6)
-* M68HC11 branch improvement:            M68HC11-Branch.      (line   6)
-* M68HC11 floating point:                M68HC11-Float.       (line   6)
-* M68HC11 modifiers:                     M68HC11-Modifiers.   (line   6)
-* M68HC11 opcodes:                       M68HC11-opcodes.     (line   6)
-* M68HC11 options:                       M68HC11-Opts.        (line   6)
-* M68HC11 pseudo-opcodes:                M68HC11-Branch.      (line   6)
-* M68HC11 syntax:                        M68HC11-Syntax.      (line   6)
-* M68HC12 assembler directives:          M68HC11-Directives.  (line   6)
-* machine dependencies:                  Machine Dependencies.
-                                                              (line   6)
-* machine directives, ARC:               ARC Directives.      (line   6)
-* machine directives, ARM:               ARM Directives.      (line   6)
-* machine directives, H8/300 (none):     H8/300 Directives.   (line   6)
-* machine directives, i860:              Directives-i860.     (line   6)
-* machine directives, i960:              Directives-i960.     (line   6)
-* machine directives, MSP 430:           MSP430 Directives.   (line   6)
-* machine directives, SH:                SH Directives.       (line   6)
-* machine directives, SH64:              SH64 Directives.     (line   9)
-* machine directives, SPARC:             Sparc-Directives.    (line   6)
-* machine directives, TIC54X:            TIC54X-Directives.   (line   6)
-* machine directives, V850:              V850 Directives.     (line   6)
-* machine directives, VAX:               VAX-directives.      (line   6)
-* machine independent directives:        Pseudo Ops.          (line   6)
-* machine instructions (not covered):    Manual.              (line  14)
-* machine-independent syntax:            Syntax.              (line   6)
-* macro directive:                       Macro.               (line  28)
-* macro directive, TIC54X:               TIC54X-Directives.   (line 153)
-* macros:                                Macro.               (line   6)
-* macros, count executed:                Macro.               (line 101)
-* Macros, MSP 430:                       MSP430-Macros.       (line   6)
-* macros, TIC54X:                        TIC54X-Macros.       (line   6)
-* make rules:                            MD.                  (line   6)
-* manual, structure and purpose:         Manual.              (line   6)
-* math builtins, TIC54X:                 TIC54X-Builtins.     (line   6)
-* Maximum number of continuation lines:  listing.             (line  33)
-* memory references, i386:               i386-Memory.         (line   6)
-* memory references, x86-64:             i386-Memory.         (line   6)
-* memory-mapped registers, TIC54X:       TIC54X-MMRegs.       (line   6)
-* merging text and data sections:        R.                   (line   6)
-* messages from assembler:               Errors.              (line   6)
-* minus, permitted arguments:            Infix Ops.           (line  49)
-* MIPS architecture options:             MIPS Opts.           (line  20)
-* MIPS big-endian output:                MIPS Opts.           (line  13)
-* MIPS debugging directives:             MIPS Stabs.          (line   6)
-* MIPS DSP instruction generation override: MIPS ASE instruction generation overrides.
-                                                              (line  16)
-* MIPS ECOFF sections:                   MIPS Object.         (line   6)
-* MIPS endianness:                       Overview.            (line 606)
-* MIPS ISA:                              Overview.            (line 612)
-* MIPS ISA override:                     MIPS ISA.            (line   6)
-* MIPS little-endian output:             MIPS Opts.           (line  13)
-* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides.
-                                                              (line  11)
-* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides.
-                                                              (line   6)
-* MIPS MT instruction generation override: MIPS ASE instruction generation overrides.
-                                                              (line  21)
-* MIPS option stack:                     MIPS option stack.   (line   6)
-* MIPS processor:                        MIPS-Dependent.      (line   6)
-* MIT:                                   M68K-Syntax.         (line   6)
-* mlib directive, TIC54X:                TIC54X-Directives.   (line 159)
-* mlist directive, TIC54X:               TIC54X-Directives.   (line 164)
-* MMIX assembler directive BSPEC:        MMIX-Pseudos.        (line 131)
-* MMIX assembler directive BYTE:         MMIX-Pseudos.        (line  97)
-* MMIX assembler directive ESPEC:        MMIX-Pseudos.        (line 131)
-* MMIX assembler directive GREG:         MMIX-Pseudos.        (line  50)
-* MMIX assembler directive IS:           MMIX-Pseudos.        (line  42)
-* MMIX assembler directive LOC:          MMIX-Pseudos.        (line   7)
-* MMIX assembler directive LOCAL:        MMIX-Pseudos.        (line  28)
-* MMIX assembler directive OCTA:         MMIX-Pseudos.        (line 108)
-* MMIX assembler directive PREFIX:       MMIX-Pseudos.        (line 120)
-* MMIX assembler directive TETRA:        MMIX-Pseudos.        (line 108)
-* MMIX assembler directive WYDE:         MMIX-Pseudos.        (line 108)
-* MMIX assembler directives:             MMIX-Pseudos.        (line   6)
-* MMIX line comment characters:          MMIX-Chars.          (line   6)
-* MMIX options:                          MMIX-Opts.           (line   6)
-* MMIX pseudo-op BSPEC:                  MMIX-Pseudos.        (line 131)
-* MMIX pseudo-op BYTE:                   MMIX-Pseudos.        (line  97)
-* MMIX pseudo-op ESPEC:                  MMIX-Pseudos.        (line 131)
-* MMIX pseudo-op GREG:                   MMIX-Pseudos.        (line  50)
-* MMIX pseudo-op IS:                     MMIX-Pseudos.        (line  42)
-* MMIX pseudo-op LOC:                    MMIX-Pseudos.        (line   7)
-* MMIX pseudo-op LOCAL:                  MMIX-Pseudos.        (line  28)
-* MMIX pseudo-op OCTA:                   MMIX-Pseudos.        (line 108)
-* MMIX pseudo-op PREFIX:                 MMIX-Pseudos.        (line 120)
-* MMIX pseudo-op TETRA:                  MMIX-Pseudos.        (line 108)
-* MMIX pseudo-op WYDE:                   MMIX-Pseudos.        (line 108)
-* MMIX pseudo-ops:                       MMIX-Pseudos.        (line   6)
-* MMIX register names:                   MMIX-Regs.           (line   6)
-* MMIX support:                          MMIX-Dependent.      (line   6)
-* mmixal differences:                    MMIX-mmixal.         (line   6)
-* mmregs directive, TIC54X:              TIC54X-Directives.   (line 170)
-* mmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
-* MMX, i386:                             i386-SIMD.           (line   6)
-* MMX, x86-64:                           i386-SIMD.           (line   6)
-* mnemonic suffixes, i386:               i386-Syntax.         (line  29)
-* mnemonic suffixes, x86-64:             i386-Syntax.         (line  29)
-* mnemonics for opcodes, VAX:            VAX-opcodes.         (line   6)
-* mnemonics, D10V:                       D10V-Opcodes.        (line   6)
-* mnemonics, D30V:                       D30V-Opcodes.        (line   6)
-* mnemonics, H8/300:                     H8/300 Opcodes.      (line   6)
-* mnemonics, SH:                         SH Opcodes.          (line   6)
-* mnemonics, SH64:                       SH64 Opcodes.        (line   6)
-* mnemonics, Z8000:                      Z8000 Opcodes.       (line   6)
-* mnolist directive, TIC54X:             TIC54X-Directives.   (line 164)
-* Motorola syntax for the 680x0:         M68K-Moto-Syntax.    (line   6)
-* MOVI instructions, relaxation:         Xtensa Immediate Relaxation.
-                                                              (line  12)
-* MRI compatibility mode:                M.                   (line   6)
-* mri directive:                         MRI.                 (line   6)
-* MRI mode, temporarily:                 MRI.                 (line   6)
-* MSP 430 floating point (IEEE):         MSP430 Floating Point.
-                                                              (line   6)
-* MSP 430 identifiers:                   MSP430-Chars.        (line   8)
-* MSP 430 line comment character:        MSP430-Chars.        (line   6)
-* MSP 430 machine directives:            MSP430 Directives.   (line   6)
-* MSP 430 macros:                        MSP430-Macros.       (line   6)
-* MSP 430 opcodes:                       MSP430 Opcodes.      (line   6)
-* MSP 430 options (none):                MSP430 Options.      (line   6)
-* MSP 430 profiling capability:          MSP430 Profiling Capability.
-                                                              (line   6)
-* MSP 430 register names:                MSP430-Regs.         (line   6)
-* MSP 430 support:                       MSP430-Dependent.    (line   6)
-* MSP430 Assembler Extensions:           MSP430-Ext.          (line   6)
-* mul instruction, i386:                 i386-Notes.          (line   6)
-* mul instruction, x86-64:               i386-Notes.          (line   6)
-* name:                                  Z8000 Directives.    (line  18)
-* named section:                         Section.             (line   6)
-* named sections:                        Ld Sections.         (line   8)
-* names, symbol:                         Symbol Names.        (line   6)
-* naming object file:                    o.                   (line   6)
-* new page, in listings:                 Eject.               (line   6)
-* newblock directive, TIC54X:            TIC54X-Directives.   (line 176)
-* newline (\n):                          Strings.             (line  21)
-* newline, required at file end:         Statements.          (line  13)
-* no-absolute-literals directive:        Absolute Literals Directive.
-                                                              (line   6)
-* no-longcalls directive:                Longcalls Directive. (line   6)
-* no-schedule directive:                 Schedule Directive.  (line   6)
-* no-transform directive:                Transform Directive. (line   6)
-* nolist directive:                      Nolist.              (line   6)
-* nolist directive, TIC54X:              TIC54X-Directives.   (line 131)
-* NOP pseudo op, ARM:                    ARM Opcodes.         (line   9)
-* notes for Alpha:                       Alpha Notes.         (line   6)
-* null-terminated strings:               Asciz.               (line   6)
-* number constants:                      Numbers.             (line   6)
-* number of macros executed:             Macro.               (line 101)
-* numbered subsections:                  Sub-Sections.        (line   6)
-* numbers, 16-bit:                       hword.               (line   6)
-* numeric values:                        Expressions.         (line   6)
-* nword directive, SPARC:                Sparc-Directives.    (line  20)
-* object file:                           Object.              (line   6)
-* object file format:                    Object Formats.      (line   6)
-* object file name:                      o.                   (line   6)
-* object file, after errors:             Z.                   (line   6)
-* obsolescent directives:                Deprecated.          (line   6)
-* octa directive:                        Octa.                (line   6)
-* octal character code (\DDD):           Strings.             (line  30)
-* octal integers:                        Integers.            (line   9)
-* offset directive, V850:                V850 Directives.     (line   6)
-* opcode mnemonics, VAX:                 VAX-opcodes.         (line   6)
-* opcode names, Xtensa:                  Xtensa Opcodes.      (line   6)
-* opcode summary, D10V:                  D10V-Opcodes.        (line   6)
-* opcode summary, D30V:                  D30V-Opcodes.        (line   6)
-* opcode summary, H8/300:                H8/300 Opcodes.      (line   6)
-* opcode summary, SH:                    SH Opcodes.          (line   6)
-* opcode summary, SH64:                  SH64 Opcodes.        (line   6)
-* opcode summary, Z8000:                 Z8000 Opcodes.       (line   6)
-* opcodes for ARC:                       ARC Opcodes.         (line   6)
-* opcodes for ARM:                       ARM Opcodes.         (line   6)
-* opcodes for MSP 430:                   MSP430 Opcodes.      (line   6)
-* opcodes for V850:                      V850 Opcodes.        (line   6)
-* opcodes, i860:                         Opcodes for i860.    (line   6)
-* opcodes, i960:                         Opcodes for i960.    (line   6)
-* opcodes, M680x0:                       M68K-opcodes.        (line   6)
-* opcodes, M68HC11:                      M68HC11-opcodes.     (line   6)
-* operand delimiters, i386:              i386-Syntax.         (line  15)
-* operand delimiters, x86-64:            i386-Syntax.         (line  15)
-* operand notation, VAX:                 VAX-operands.        (line   6)
-* operands in expressions:               Arguments.           (line   6)
-* operator precedence:                   Infix Ops.           (line  11)
-* operators, in expressions:             Operators.           (line   6)
-* operators, permitted arguments:        Infix Ops.           (line   6)
-* optimization, D10V:                    Overview.            (line 391)
-* optimization, D30V:                    Overview.            (line 396)
-* optimizations:                         Xtensa Optimizations.
-                                                              (line   6)
-* option directive, ARC:                 ARC Directives.      (line 162)
-* option directive, TIC54X:              TIC54X-Directives.   (line 180)
-* option summary:                        Overview.            (line   6)
-* options for Alpha:                     Alpha Options.       (line   6)
-* options for ARC (none):                ARC Options.         (line   6)
-* options for ARM (none):                ARM Options.         (line   6)
-* options for i386:                      i386-Options.        (line   6)
-* options for IA-64:                     IA-64 Options.       (line   6)
-* options for MSP430 (none):             MSP430 Options.      (line   6)
-* options for PDP-11:                    PDP-11-Options.      (line   6)
-* options for PowerPC:                   PowerPC-Opts.        (line   6)
-* options for SPARC:                     Sparc-Opts.          (line   6)
-* options for V850 (none):               V850 Options.        (line   6)
-* options for VAX/VMS:                   VAX-Opts.            (line  42)
-* options for x86-64:                    i386-Options.        (line   6)
-* options for Z80:                       Z80 Options.         (line   6)
-* options, all versions of assembler:    Invoking.            (line   6)
-* options, command line:                 Command Line.        (line  13)
-* options, CRIS:                         CRIS-Opts.           (line   6)
-* options, D10V:                         D10V-Opts.           (line   6)
-* options, D30V:                         D30V-Opts.           (line   6)
-* options, H8/300 (none):                H8/300 Options.      (line   6)
-* options, i960:                         Options-i960.        (line   6)
-* options, IP2K:                         IP2K-Opts.           (line   6)
-* options, M32C:                         M32C-Opts.           (line   6)
-* options, M32R:                         M32R-Opts.           (line   6)
-* options, M680x0:                       M68K-Opts.           (line   6)
-* options, M68HC11:                      M68HC11-Opts.        (line   6)
-* options, MMIX:                         MMIX-Opts.           (line   6)
-* options, PJ:                           PJ Options.          (line   6)
-* options, SH:                           SH Options.          (line   6)
-* options, SH64:                         SH64 Options.        (line   6)
-* options, TIC54X:                       TIC54X-Opts.         (line   6)
-* options, Z8000:                        Z8000 Options.       (line   6)
-* org directive:                         Org.                 (line   6)
-* other attribute, of a.out symbol:      Symbol Other.        (line   6)
-* output file:                           Object.              (line   6)
-* p2align directive:                     P2align.             (line   6)
-* p2alignl directive:                    P2align.             (line  28)
-* p2alignw directive:                    P2align.             (line  28)
-* padding the location counter:          Align.               (line   6)
-* padding the location counter given a power of two: P2align. (line   6)
-* padding the location counter given number of bytes: Balign. (line   6)
-* page, in listings:                     Eject.               (line   6)
-* paper size, for listings:              Psize.               (line   6)
-* paths for .include:                    I.                   (line   6)
-* patterns, writing in memory:           Fill.                (line   6)
-* PDP-11 comments:                       PDP-11-Syntax.       (line  16)
-* PDP-11 floating-point register syntax: PDP-11-Syntax.       (line  13)
-* PDP-11 general-purpose register syntax: PDP-11-Syntax.      (line  10)
-* PDP-11 instruction naming:             PDP-11-Mnemonics.    (line   6)
-* PDP-11 support:                        PDP-11-Dependent.    (line   6)
-* PDP-11 syntax:                         PDP-11-Syntax.       (line   6)
-* PIC code generation for ARM:           ARM Options.         (line 120)
-* PIC code generation for M32R:          M32R-Opts.           (line  42)
-* PJ endianness:                         Overview.            (line 513)
-* PJ options:                            PJ Options.          (line   6)
-* PJ support:                            PJ-Dependent.        (line   6)
-* plus, permitted arguments:             Infix Ops.           (line  44)
-* popsection directive:                  PopSection.          (line   6)
-* Position-independent code, CRIS:       CRIS-Opts.           (line  27)
-* Position-independent code, symbols in, CRIS: CRIS-Pic.      (line   6)
-* PowerPC architectures:                 PowerPC-Opts.        (line   6)
-* PowerPC directives:                    PowerPC-Pseudo.      (line   6)
-* PowerPC options:                       PowerPC-Opts.        (line   6)
-* PowerPC support:                       PPC-Dependent.       (line   6)
-* precedence of operators:               Infix Ops.           (line  11)
-* precision, floating point:             Flonums.             (line   6)
-* prefix operators:                      Prefix Ops.          (line   6)
-* prefixes, i386:                        i386-Prefixes.       (line   6)
-* preprocessing:                         Preprocessing.       (line   6)
-* preprocessing, turning on and off:     Preprocessing.       (line  27)
-* previous directive:                    Previous.            (line   6)
-* primary attributes, COFF symbols:      COFF Symbols.        (line  13)
-* print directive:                       Print.               (line   6)
-* proc directive, SPARC:                 Sparc-Directives.    (line  25)
-* profiler directive, MSP 430:           MSP430 Directives.   (line  22)
-* profiling capability for MSP 430:      MSP430 Profiling Capability.
-                                                              (line   6)
-* protected directive:                   Protected.           (line   6)
-* pseudo-op .arch, CRIS:                 CRIS-Pseudos.        (line  45)
-* pseudo-op .dword, CRIS:                CRIS-Pseudos.        (line  12)
-* pseudo-op .syntax, CRIS:               CRIS-Pseudos.        (line  17)
-* pseudo-op BSPEC, MMIX:                 MMIX-Pseudos.        (line 131)
-* pseudo-op BYTE, MMIX:                  MMIX-Pseudos.        (line  97)
-* pseudo-op ESPEC, MMIX:                 MMIX-Pseudos.        (line 131)
-* pseudo-op GREG, MMIX:                  MMIX-Pseudos.        (line  50)
-* pseudo-op IS, MMIX:                    MMIX-Pseudos.        (line  42)
-* pseudo-op LOC, MMIX:                   MMIX-Pseudos.        (line   7)
-* pseudo-op LOCAL, MMIX:                 MMIX-Pseudos.        (line  28)
-* pseudo-op OCTA, MMIX:                  MMIX-Pseudos.        (line 108)
-* pseudo-op PREFIX, MMIX:                MMIX-Pseudos.        (line 120)
-* pseudo-op TETRA, MMIX:                 MMIX-Pseudos.        (line 108)
-* pseudo-op WYDE, MMIX:                  MMIX-Pseudos.        (line 108)
-* pseudo-opcodes, M680x0:                M68K-Branch.         (line   6)
-* pseudo-opcodes, M68HC11:               M68HC11-Branch.      (line   6)
-* pseudo-ops for branch, VAX:            VAX-branch.          (line   6)
-* pseudo-ops, CRIS:                      CRIS-Pseudos.        (line   6)
-* pseudo-ops, machine independent:       Pseudo Ops.          (line   6)
-* pseudo-ops, MMIX:                      MMIX-Pseudos.        (line   6)
-* psize directive:                       Psize.               (line   6)
-* PSR bits:                              IA-64-Bits.          (line   6)
-* pstring directive, TIC54X:             TIC54X-Directives.   (line 209)
-* psw register, V850:                    V850-Regs.           (line 116)
-* purgem directive:                      Purgem.              (line   6)
-* purpose of GNU assembler:              GNU Assembler.       (line  12)
-* pushsection directive:                 PushSection.         (line   6)
-* quad directive:                        Quad.                (line   6)
-* quad directive, i386:                  i386-Float.          (line  21)
-* quad directive, x86-64:                i386-Float.          (line  21)
-* real-mode code, i386:                  i386-16bit.          (line   6)
-* ref directive, TIC54X:                 TIC54X-Directives.   (line 103)
-* register directive, SPARC:             Sparc-Directives.    (line  29)
-* register names, Alpha:                 Alpha-Regs.          (line   6)
-* register names, ARC:                   ARC-Regs.            (line   6)
-* register names, ARM:                   ARM-Regs.            (line   6)
-* register names, CRIS:                  CRIS-Regs.           (line   6)
-* register names, H8/300:                H8/300-Regs.         (line   6)
-* register names, IA-64:                 IA-64-Regs.          (line   6)
-* register names, MMIX:                  MMIX-Regs.           (line   6)
-* register names, MSP 430:               MSP430-Regs.         (line   6)
-* register names, V850:                  V850-Regs.           (line   6)
-* register names, VAX:                   VAX-operands.        (line  17)
-* register names, Xtensa:                Xtensa Registers.    (line   6)
-* register names, Z80:                   Z80-Regs.            (line   6)
-* register operands, i386:               i386-Syntax.         (line  15)
-* register operands, x86-64:             i386-Syntax.         (line  15)
-* registers, D10V:                       D10V-Regs.           (line   6)
-* registers, D30V:                       D30V-Regs.           (line   6)
-* registers, i386:                       i386-Regs.           (line   6)
-* registers, SH:                         SH-Regs.             (line   6)
-* registers, SH64:                       SH64-Regs.           (line   6)
-* registers, TIC54X memory-mapped:       TIC54X-MMRegs.       (line   6)
-* registers, x86-64:                     i386-Regs.           (line   6)
-* registers, Z8000:                      Z8000-Regs.          (line   6)
-* relaxation:                            Xtensa Relaxation.   (line   6)
-* relaxation of ADDI instructions:       Xtensa Immediate Relaxation.
-                                                              (line  43)
-* relaxation of branch instructions:     Xtensa Branch Relaxation.
-                                                              (line   6)
-* relaxation of call instructions:       Xtensa Call Relaxation.
-                                                              (line   6)
-* relaxation of immediate fields:        Xtensa Immediate Relaxation.
-                                                              (line   6)
-* relaxation of L16SI instructions:      Xtensa Immediate Relaxation.
-                                                              (line  23)
-* relaxation of L16UI instructions:      Xtensa Immediate Relaxation.
-                                                              (line  23)
-* relaxation of L32I instructions:       Xtensa Immediate Relaxation.
-                                                              (line  23)
-* relaxation of L8UI instructions:       Xtensa Immediate Relaxation.
-                                                              (line  23)
-* relaxation of MOVI instructions:       Xtensa Immediate Relaxation.
-                                                              (line  12)
-* relocation:                            Sections.            (line   6)
-* relocation example:                    Ld Sections.         (line  40)
-* relocations, Alpha:                    Alpha-Relocs.        (line   6)
-* repeat prefixes, i386:                 i386-Prefixes.       (line  44)
-* reporting bugs in assembler:           Reporting Bugs.      (line   6)
-* rept directive:                        Rept.                (line   6)
-* req directive, ARM:                    ARM Directives.      (line  13)
-* reserve directive, SPARC:              Sparc-Directives.    (line  39)
-* return instructions, i386:             i386-Syntax.         (line  38)
-* return instructions, x86-64:           i386-Syntax.         (line  38)
-* REX prefixes, i386:                    i386-Prefixes.       (line  46)
-* rsect:                                 Z8000 Directives.    (line  52)
-* sblock directive, TIC54X:              TIC54X-Directives.   (line 183)
-* sbttl directive:                       Sbttl.               (line   6)
-* schedule directive:                    Schedule Directive.  (line   6)
-* scl directive:                         Scl.                 (line   6)
-* sdaoff pseudo-op, V850:                V850 Opcodes.        (line  65)
-* search path for .include:              I.                   (line   6)
-* sect directive, MSP 430:               MSP430 Directives.   (line  18)
-* sect directive, TIC54X:                TIC54X-Directives.   (line 189)
-* section directive (COFF version):      Section.             (line  16)
-* section directive (ELF version):       Section.             (line  67)
-* section directive, V850:               V850 Directives.     (line   9)
-* section override prefixes, i386:       i386-Prefixes.       (line  23)
-* Section Stack <1>:                     SubSection.          (line   6)
-* Section Stack <2>:                     Section.             (line  62)
-* Section Stack <3>:                     PushSection.         (line   6)
-* Section Stack <4>:                     PopSection.          (line   6)
-* Section Stack:                         Previous.            (line   6)
-* section-relative addressing:           Secs Background.     (line  68)
-* sections:                              Sections.            (line   6)
-* sections in messages, internal:        As Sections.         (line   6)
-* sections, i386:                        i386-Syntax.         (line  44)
-* sections, named:                       Ld Sections.         (line   8)
-* sections, x86-64:                      i386-Syntax.         (line  44)
-* seg directive, SPARC:                  Sparc-Directives.    (line  44)
-* segm:                                  Z8000 Directives.    (line  10)
-* set directive:                         Set.                 (line   6)
-* set directive, TIC54X:                 TIC54X-Directives.   (line 192)
-* SH addressing modes:                   SH-Addressing.       (line   6)
-* SH floating point (IEEE):              SH Floating Point.   (line   6)
-* SH line comment character:             SH-Chars.            (line   6)
-* SH line separator:                     SH-Chars.            (line   8)
-* SH machine directives:                 SH Directives.       (line   6)
-* SH opcode summary:                     SH Opcodes.          (line   6)
-* SH options:                            SH Options.          (line   6)
-* SH registers:                          SH-Regs.             (line   6)
-* SH support:                            SH-Dependent.        (line   6)
-* SH64 ABI options:                      SH64 Options.        (line  29)
-* SH64 addressing modes:                 SH64-Addressing.     (line   6)
-* SH64 ISA options:                      SH64 Options.        (line   6)
-* SH64 line comment character:           SH64-Chars.          (line   6)
-* SH64 line separator:                   SH64-Chars.          (line   8)
-* SH64 machine directives:               SH64 Directives.     (line   9)
-* SH64 opcode summary:                   SH64 Opcodes.        (line   6)
-* SH64 options:                          SH64 Options.        (line   6)
-* SH64 registers:                        SH64-Regs.           (line   6)
-* SH64 support:                          SH64-Dependent.      (line   6)
-* shigh directive, M32R:                 M32R-Directives.     (line  26)
-* short directive:                       Short.               (line   6)
-* short directive, ARC:                  ARC Directives.      (line 171)
-* short directive, TIC54X:               TIC54X-Directives.   (line 111)
-* SIMD, i386:                            i386-SIMD.           (line   6)
-* SIMD, x86-64:                          i386-SIMD.           (line   6)
-* single character constant:             Chars.               (line   6)
-* single directive:                      Single.              (line   6)
-* single directive, i386:                i386-Float.          (line  14)
-* single directive, x86-64:              i386-Float.          (line  14)
-* single quote, Z80:                     Z80-Chars.           (line  13)
-* sixteen bit integers:                  hword.               (line   6)
-* sixteen byte integer:                  Octa.                (line   6)
-* size directive (COFF version):         Size.                (line  11)
-* size directive (ELF version):          Size.                (line  19)
-* size modifiers, D10V:                  D10V-Size.           (line   6)
-* size modifiers, D30V:                  D30V-Size.           (line   6)
-* size modifiers, M680x0:                M68K-Syntax.         (line   8)
-* size prefixes, i386:                   i386-Prefixes.       (line  27)
-* size suffixes, H8/300:                 H8/300 Opcodes.      (line 163)
-* sizes operands, i386:                  i386-Syntax.         (line  29)
-* sizes operands, x86-64:                i386-Syntax.         (line  29)
-* skip directive:                        Skip.                (line   6)
-* skip directive, M680x0:                M68K-Directives.     (line  19)
-* skip directive, SPARC:                 Sparc-Directives.    (line  48)
-* sleb128 directive:                     Sleb128.             (line   6)
-* small objects, MIPS ECOFF:             MIPS Object.         (line  11)
-* SOM symbol attributes:                 SOM Symbols.         (line   6)
-* source program:                        Input Files.         (line   6)
-* source, destination operands; i386:    i386-Syntax.         (line  22)
-* source, destination operands; x86-64:  i386-Syntax.         (line  22)
-* sp register:                           Xtensa Registers.    (line   6)
-* sp register, V850:                     V850-Regs.           (line  14)
-* space directive:                       Space.               (line   6)
-* space directive, TIC54X:               TIC54X-Directives.   (line 197)
-* space used, maximum for assembly:      statistics.          (line   6)
-* SPARC architectures:                   Sparc-Opts.          (line   6)
-* SPARC data alignment:                  Sparc-Aligned-Data.  (line   6)
-* SPARC floating point (IEEE):           Sparc-Float.         (line   6)
-* SPARC machine directives:              Sparc-Directives.    (line   6)
-* SPARC options:                         Sparc-Opts.          (line   6)
-* SPARC support:                         Sparc-Dependent.     (line   6)
-* special characters, ARC:               ARC-Chars.           (line   6)
-* special characters, M680x0:            M68K-Chars.          (line   6)
-* special purpose registers, MSP 430:    MSP430-Regs.         (line  11)
-* sslist directive, TIC54X:              TIC54X-Directives.   (line 204)
-* ssnolist directive, TIC54X:            TIC54X-Directives.   (line 204)
-* stabd directive:                       Stab.                (line  38)
-* stabn directive:                       Stab.                (line  48)
-* stabs directive:                       Stab.                (line  51)
-* stabX directives:                      Stab.                (line   6)
-* standard assembler sections:           Secs Background.     (line  27)
-* standard input, as input file:         Command Line.        (line  10)
-* statement separator character:         Statements.          (line   6)
-* statement separator, Alpha:            Alpha-Chars.         (line   8)
-* statement separator, ARM:              ARM-Chars.           (line  10)
-* statement separator, H8/300:           H8/300-Chars.        (line   8)
-* statement separator, IA-64:            IA-64-Chars.         (line   8)
-* statement separator, SH:               SH-Chars.            (line   8)
-* statement separator, SH64:             SH64-Chars.          (line   8)
-* statement separator, Z8000:            Z8000-Chars.         (line   8)
-* statements, structure of:              Statements.          (line   6)
-* statistics, about assembly:            statistics.          (line   6)
-* stopping the assembly:                 Abort.               (line   6)
-* string constants:                      Strings.             (line   6)
-* string directive:                      String.              (line   6)
-* string directive on HPPA:              HPPA Directives.     (line 137)
-* string directive, TIC54X:              TIC54X-Directives.   (line 209)
-* string literals:                       Ascii.               (line   6)
-* string, copying to object file:        String.              (line   6)
-* struct directive:                      Struct.              (line   6)
-* struct directive, TIC54X:              TIC54X-Directives.   (line 217)
-* structure debugging, COFF:             Tag.                 (line   6)
-* sub-instruction ordering, D10V:        D10V-Chars.          (line   6)
-* sub-instruction ordering, D30V:        D30V-Chars.          (line   6)
-* sub-instructions, D10V:                D10V-Subs.           (line   6)
-* sub-instructions, D30V:                D30V-Subs.           (line   6)
-* subexpressions:                        Arguments.           (line  24)
-* subsection directive:                  SubSection.          (line   6)
-* subsym builtins, TIC54X:               TIC54X-Macros.       (line  16)
-* subtitles for listings:                Sbttl.               (line   6)
-* subtraction, permitted arguments:      Infix Ops.           (line  49)
-* summary of options:                    Overview.            (line   6)
-* support:                               HPPA-Dependent.      (line   6)
-* supporting files, including:           Include.             (line   6)
-* suppressing warnings:                  W.                   (line  11)
-* sval:                                  Z8000 Directives.    (line  33)
-* symbol attributes:                     Symbol Attributes.   (line   6)
-* symbol attributes, a.out:              a.out Symbols.       (line   6)
-* symbol attributes, COFF:               COFF Symbols.        (line   6)
-* symbol attributes, SOM:                SOM Symbols.         (line   6)
-* symbol descriptor, COFF:               Desc.                (line   6)
-* symbol modifiers <1>:                  M68HC11-Modifiers.   (line  12)
-* symbol modifiers:                      M32C-Modifiers.      (line  11)
-* symbol names:                          Symbol Names.        (line   6)
-* symbol names, $ in <1>:                SH64-Chars.          (line  10)
-* symbol names, $ in <2>:                SH-Chars.            (line  10)
-* symbol names, $ in <3>:                D30V-Chars.          (line  63)
-* symbol names, $ in:                    D10V-Chars.          (line  46)
-* symbol names, local:                   Symbol Names.        (line  22)
-* symbol names, temporary:               Symbol Names.        (line  22)
-* symbol storage class (COFF):           Scl.                 (line   6)
-* symbol type:                           Symbol Type.         (line   6)
-* symbol type, COFF:                     Type.                (line  11)
-* symbol type, ELF:                      Type.                (line  22)
-* symbol value:                          Symbol Value.        (line   6)
-* symbol value, setting:                 Set.                 (line   6)
-* symbol values, assigning:              Setting Symbols.     (line   6)
-* symbol versioning:                     Symver.              (line   6)
-* symbol, common:                        Comm.                (line   6)
-* symbol, making visible to linker:      Global.              (line   6)
-* symbolic debuggers, information for:   Stab.                (line   6)
-* symbols:                               Symbols.             (line   6)
-* Symbols in position-independent code, CRIS: CRIS-Pic.       (line   6)
-* symbols with uppercase, VAX/VMS:       VAX-Opts.            (line  42)
-* symbols, assigning values to:          Equ.                 (line   6)
-* Symbols, built-in, CRIS:               CRIS-Symbols.        (line   6)
-* Symbols, CRIS, built-in:               CRIS-Symbols.        (line   6)
-* symbols, local common:                 Lcomm.               (line   6)
-* symver directive:                      Symver.              (line   6)
-* syntax compatibility, i386:            i386-Syntax.         (line   6)
-* syntax compatibility, x86-64:          i386-Syntax.         (line   6)
-* syntax, BFIN:                          BFIN Syntax.         (line   6)
-* syntax, D10V:                          D10V-Syntax.         (line   6)
-* syntax, D30V:                          D30V-Syntax.         (line   6)
-* syntax, M32C:                          M32C-Modifiers.      (line   6)
-* syntax, M680x0:                        M68K-Syntax.         (line   8)
-* syntax, M68HC11 <1>:                   M68HC11-Modifiers.   (line   6)
-* syntax, M68HC11:                       M68HC11-Syntax.      (line   6)
-* syntax, machine-independent:           Syntax.              (line   6)
-* syntax, Xtensa assembler:              Xtensa Syntax.       (line   6)
-* sysproc directive, i960:               Directives-i960.     (line  37)
-* tab (\t):                              Strings.             (line  27)
-* tab directive, TIC54X:                 TIC54X-Directives.   (line 248)
-* tag directive:                         Tag.                 (line   6)
-* tag directive, TIC54X:                 TIC54X-Directives.   (line 217)
-* tdaoff pseudo-op, V850:                V850 Opcodes.        (line  81)
-* temporary symbol names:                Symbol Names.        (line  22)
-* text and data sections, joining:       R.                   (line   6)
-* text directive:                        Text.                (line   6)
-* text section:                          Ld Sections.         (line   9)
-* tfloat directive, i386:                i386-Float.          (line  14)
-* tfloat directive, x86-64:              i386-Float.          (line  14)
-* thumb directive, ARM:                  ARM Directives.      (line  33)
-* Thumb support:                         ARM-Dependent.       (line   6)
-* thumb_func directive, ARM:             ARM Directives.      (line  43)
-* thumb_set directive, ARM:              ARM Directives.      (line  51)
-* TIC54X builtin math functions:         TIC54X-Builtins.     (line   6)
-* TIC54X machine directives:             TIC54X-Directives.   (line   6)
-* TIC54X memory-mapped registers:        TIC54X-MMRegs.       (line   6)
-* TIC54X options:                        TIC54X-Opts.         (line   6)
-* TIC54X subsym builtins:                TIC54X-Macros.       (line  16)
-* TIC54X support:                        TIC54X-Dependent.    (line   6)
-* TIC54X-specific macros:                TIC54X-Macros.       (line   6)
-* time, total for assembly:              statistics.          (line   6)
-* title directive:                       Title.               (line   6)
-* tp register, V850:                     V850-Regs.           (line  20)
-* transform directive:                   Transform Directive. (line   6)
-* trusted compiler:                      f.                   (line   6)
-* turning preprocessing on and off:      Preprocessing.       (line  27)
-* type directive (COFF version):         Type.                (line  11)
-* type directive (ELF version):          Type.                (line  22)
-* type of a symbol:                      Symbol Type.         (line   6)
-* ualong directive, SH:                  SH Directives.       (line   6)
-* uaword directive, SH:                  SH Directives.       (line   6)
-* ubyte directive, TIC54X:               TIC54X-Directives.   (line  36)
-* uchar directive, TIC54X:               TIC54X-Directives.   (line  36)
-* uhalf directive, TIC54X:               TIC54X-Directives.   (line 111)
-* uint directive, TIC54X:                TIC54X-Directives.   (line 111)
-* uleb128 directive:                     Uleb128.             (line   6)
-* ulong directive, TIC54X:               TIC54X-Directives.   (line 135)
-* undefined section:                     Ld Sections.         (line  36)
-* union directive, TIC54X:               TIC54X-Directives.   (line 251)
-* unreq directive, ARM:                  ARM Directives.      (line  18)
-* unsegm:                                Z8000 Directives.    (line  14)
-* usect directive, TIC54X:               TIC54X-Directives.   (line 263)
-* ushort directive, TIC54X:              TIC54X-Directives.   (line 111)
-* uword directive, TIC54X:               TIC54X-Directives.   (line 111)
-* V850 command line options:             V850 Options.        (line   9)
-* V850 floating point (IEEE):            V850 Floating Point. (line   6)
-* V850 line comment character:           V850-Chars.          (line   6)
-* V850 machine directives:               V850 Directives.     (line   6)
-* V850 opcodes:                          V850 Opcodes.        (line   6)
-* V850 options (none):                   V850 Options.        (line   6)
-* V850 register names:                   V850-Regs.           (line   6)
-* V850 support:                          V850-Dependent.      (line   6)
-* val directive:                         Val.                 (line   6)
-* value attribute, COFF:                 Val.                 (line   6)
-* value of a symbol:                     Symbol Value.        (line   6)
-* var directive, TIC54X:                 TIC54X-Directives.   (line 273)
-* VAX bitfields not supported:           VAX-no.              (line   6)
-* VAX branch improvement:                VAX-branch.          (line   6)
-* VAX command-line options ignored:      VAX-Opts.            (line   6)
-* VAX displacement sizing character:     VAX-operands.        (line  12)
-* VAX floating point:                    VAX-float.           (line   6)
-* VAX immediate character:               VAX-operands.        (line   6)
-* VAX indirect character:                VAX-operands.        (line   9)
-* VAX machine directives:                VAX-directives.      (line   6)
-* VAX opcode mnemonics:                  VAX-opcodes.         (line   6)
-* VAX operand notation:                  VAX-operands.        (line   6)
-* VAX register names:                    VAX-operands.        (line  17)
-* VAX support:                           Vax-Dependent.       (line   6)
-* Vax-11 C compatibility:                VAX-Opts.            (line  42)
-* VAX/VMS options:                       VAX-Opts.            (line  42)
-* version directive:                     Version.             (line   6)
-* version directive, TIC54X:             TIC54X-Directives.   (line 277)
-* version of assembler:                  v.                   (line   6)
-* versions of symbols:                   Symver.              (line   6)
-* visibility <1>:                        Protected.           (line   6)
-* visibility <2>:                        Internal.            (line   6)
-* visibility:                            Hidden.              (line   6)
-* VMS (VAX) options:                     VAX-Opts.            (line  42)
-* vtable_entry directive:                VTableEntry.         (line   6)
-* vtable_inherit directive:              VTableInherit.       (line   6)
-* warning directive:                     Warning.             (line   6)
-* warning for altered difference tables: K.                   (line   6)
-* warning messages:                      Errors.              (line   6)
-* warnings, causing error:               W.                   (line  16)
-* warnings, M32R:                        M32R-Warnings.       (line   6)
-* warnings, suppressing:                 W.                   (line  11)
-* warnings, switching on:                W.                   (line  19)
-* weak directive:                        Weak.                (line   6)
-* weakref directive:                     Weakref.             (line   6)
-* whitespace:                            Whitespace.          (line   6)
-* whitespace, removed by preprocessor:   Preprocessing.       (line   7)
-* wide floating point directives, VAX:   VAX-directives.      (line  10)
-* width directive, TIC54X:               TIC54X-Directives.   (line 127)
-* Width of continuation lines of disassembly output: listing. (line  20)
-* Width of first line disassembly output: listing.            (line  15)
-* Width of source line output:           listing.             (line  27)
-* wmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
-* word directive:                        Word.                (line   6)
-* word directive, ARC:                   ARC Directives.      (line 174)
-* word directive, H8/300:                H8/300 Directives.   (line   6)
-* word directive, i386:                  i386-Float.          (line  21)
-* word directive, SPARC:                 Sparc-Directives.    (line  51)
-* word directive, TIC54X:                TIC54X-Directives.   (line 111)
-* word directive, x86-64:                i386-Float.          (line  21)
-* writing patterns in memory:            Fill.                (line   6)
-* wval:                                  Z8000 Directives.    (line  24)
-* x86-64 arch directive:                 i386-Arch.           (line   6)
-* x86-64 att_syntax pseudo op:           i386-Syntax.         (line   6)
-* x86-64 conversion instructions:        i386-Mnemonics.      (line  32)
-* x86-64 floating point:                 i386-Float.          (line   6)
-* x86-64 immediate operands:             i386-Syntax.         (line  15)
-* x86-64 instruction naming:             i386-Mnemonics.      (line   6)
-* x86-64 intel_syntax pseudo op:         i386-Syntax.         (line   6)
-* x86-64 jump optimization:              i386-Jumps.          (line   6)
-* x86-64 jump, call, return:             i386-Syntax.         (line  38)
-* x86-64 jump/call operands:             i386-Syntax.         (line  15)
-* x86-64 memory references:              i386-Memory.         (line   6)
-* x86-64 options:                        i386-Options.        (line   6)
-* x86-64 register operands:              i386-Syntax.         (line  15)
-* x86-64 registers:                      i386-Regs.           (line   6)
-* x86-64 sections:                       i386-Syntax.         (line  44)
-* x86-64 size suffixes:                  i386-Syntax.         (line  29)
-* x86-64 source, destination operands:   i386-Syntax.         (line  22)
-* x86-64 support:                        i386-Dependent.      (line   6)
-* x86-64 syntax compatibility:           i386-Syntax.         (line   6)
-* xfloat directive, TIC54X:              TIC54X-Directives.   (line  64)
-* xlong directive, TIC54X:               TIC54X-Directives.   (line 135)
-* Xtensa architecture:                   Xtensa-Dependent.    (line   6)
-* Xtensa assembler syntax:               Xtensa Syntax.       (line   6)
-* Xtensa directives:                     Xtensa Directives.   (line   6)
-* Xtensa opcode names:                   Xtensa Opcodes.      (line   6)
-* Xtensa register names:                 Xtensa Registers.    (line   6)
-* xword directive, SPARC:                Sparc-Directives.    (line  55)
-* Z80 $:                                 Z80-Chars.           (line   8)
-* Z80 ':                                 Z80-Chars.           (line  13)
-* Z80 floating point:                    Z80 Floating Point.  (line   6)
-* Z80 line comment character:            Z80-Chars.           (line   6)
-* Z80 options:                           Z80 Options.         (line   6)
-* Z80 registers:                         Z80-Regs.            (line   6)
-* Z80 support:                           Z80-Dependent.       (line   6)
-* Z80 Syntax:                            Z80 Options.         (line  47)
-* Z80, \:                                Z80-Chars.           (line  11)
-* Z80, case sensitivity:                 Z80-Case.            (line   6)
-* Z80-only directives:                   Z80 Directives.      (line   9)
-* Z800 addressing modes:                 Z8000-Addressing.    (line   6)
-* Z8000 directives:                      Z8000 Directives.    (line   6)
-* Z8000 line comment character:          Z8000-Chars.         (line   6)
-* Z8000 line separator:                  Z8000-Chars.         (line   8)
-* Z8000 opcode summary:                  Z8000 Opcodes.       (line   6)
-* Z8000 options:                         Z8000 Options.       (line   6)
-* Z8000 registers:                       Z8000-Regs.          (line   6)
-* Z8000 support:                         Z8000-Dependent.     (line   6)
-* zdaoff pseudo-op, V850:                V850 Opcodes.        (line  99)
-* zero register, V850:                   V850-Regs.           (line   7)
-* zero-terminated strings:               Asciz.               (line   6)
-
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-
-End Tag Table
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 6daaed028c7b..b6f7f3217177 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -1,6 +1,6 @@
 \input texinfo @c                               -*-Texinfo-*-
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004, 2005
+@c  2001, 2002, 2003, 2004, 2005, 2006, 2007
 @c  Free Software Foundation, Inc.
 @c UPDATE!!  On future updates--
 @c   (1)   check for new machine-dep cmdline options in
@@ -22,7 +22,7 @@
 @c man begin NAME
 @c ---
 @include asconfig.texi
-@include gasver.texi
+@include bfdver.texi
 @c ---
 @c man end
 @c ---
@@ -96,11 +96,12 @@ END-INFO-DIR-ENTRY
 @finalout
 @syncodeindex ky cp
 
-@ifinfo
+@copying
 This file documents the GNU Assembler "@value{AS}".
 
 @c man begin COPYRIGHT
-Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
+2006, 2007 Free Software Foundation, Inc.
 
 Permission is granted to copy, distribute and/or modify this document
 under the terms of the GNU Free Documentation License, Version 1.1
@@ -110,15 +111,7 @@ Back-Cover Texts.  A copy of the license is included in the
 section entitled ``GNU Free Documentation License''.
 
 @c man end
-
-@ignore
-Permission is granted to process this file through Tex and print the
-results, provided the printed document carries copying permission
-notice identical to this one except for the removal of this paragraph
-(this paragraph not being relevant to the printed manual).
-
-@end ignore
-@end ifinfo
+@end copying
 
 @titlepage
 @title Using @value{AS}
@@ -126,11 +119,15 @@ notice identical to this one except for the removal of this paragraph
 @ifclear GENERIC
 @subtitle for the @value{TARGET} family
 @end ifclear
+@ifset VERSION_PACKAGE
+@sp 1
+@subtitle @value{VERSION_PACKAGE}
+@end ifset
 @sp 1
 @subtitle Version @value{VERSION}
 @sp 1
 @sp 13
-The Free Software Foundation Inc.  thanks The Nice Computer
+The Free Software Foundation Inc.@: thanks The Nice Computer
 Company of Australia for loaning Dean Elsner to write the
 first (Vax) version of @command{as} for Project @sc{gnu}.
 The proprietors, management and staff of TNCCA thank FSF for
@@ -153,7 +150,8 @@ done.
 @end tex
 
 @vskip 0pt plus 1filll
-Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,
+2006, 2007 Free Software Foundation, Inc.
 
       Permission is granted to copy, distribute and/or modify this document
       under the terms of the GNU Free Documentation License, Version 1.1
@@ -163,13 +161,17 @@ Copyright @copyright{} 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Fr
       section entitled ``GNU Free Documentation License''.
 
 @end titlepage
+@contents
 
 @ifnottex
 @node Top
 @top Using @value{AS}
 
-This file is a user guide to the @sc{gnu} assembler @command{@value{AS}} version
-@value{VERSION}.
+This file is a user guide to the @sc{gnu} assembler @command{@value{AS}}
+@ifset VERSION_PACKAGE
+@value{VERSION_PACKAGE}
+@end ifset
+version @value{VERSION}.
 @ifclear GENERIC
 This version of the file describes @command{@value{AS}} configured to generate
 code for @value{TARGET} architectures.
@@ -191,7 +193,7 @@ section entitled ``GNU Free Documentation License''.
 * Reporting Bugs::              Reporting Bugs
 * Acknowledgements::            Who Did What
 * GNU Free Documentation License::  GNU Free Documentation License
-* Index::                       Index
+* AS Index::                    AS Index
 @end menu
 @end ifnottex
 
@@ -209,7 +211,7 @@ code for @value{TARGET} architectures.
 @cindex option summary
 @cindex summary of options
 Here is a brief summary of how to invoke @command{@value{AS}}.  For details,
-@pxref{Invoking,,Command-Line Options}.
+see @ref{Invoking,,Command-Line Options}.
 
 @c man title AS the portable GNU assembler.
 
@@ -296,6 +298,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 
 @emph{Target i386 options:}
    [@b{--32}|@b{--64}] [@b{-n}]
+   [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] 
 @end ifset
 @ifset I960
 
@@ -343,7 +346,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-m68hc11}|@b{-m68hc12}|@b{-m68hcs12}]
    [@b{-mshort}|@b{-mlong}]
    [@b{-mshort-double}|@b{-mlong-double}]
-   [@b{--force-long-branchs}] [@b{--short-branchs}]
+   [@b{--force-long-branches}] [@b{--short-branches}]
    [@b{--strict-direct-mode}] [@b{--print-insn-syntax}]
    [@b{--print-opcodes}] [@b{--generate-example}]
 @end ifset
@@ -358,7 +361,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @emph{Target MIPS options:}
    [@b{-nocpp}] [@b{-EL}] [@b{-EB}] [@b{-O}[@var{optimization level}]]
    [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}]
-   [@b{-non_shared}] [@b{-xgot}]
+   [@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}]
    [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}]
    [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}]
    [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}]
@@ -367,9 +370,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mips16}] [@b{-no-mips16}]
+   [@b{-msmartmips}] [@b{-mno-smartmips}]
    [@b{-mips3d}] [@b{-no-mips3d}]
    [@b{-mdmx}] [@b{-no-mdmx}]
    [@b{-mdsp}] [@b{-mno-dsp}]
+   [@b{-mdspr2}] [@b{-mno-dspr2}]
    [@b{-mmt}] [@b{-mno-mt}]
    [@b{-mdebug}] [@b{-no-mdebug}]
    [@b{-mpdr}] [@b{-mno-pdr}]
@@ -487,7 +492,10 @@ listing without forms processing.  The @samp{=file} option, if used, must be
 the last one.  By itself, @samp{-a} defaults to @samp{-ahls}.
 
 @item --alternate
-Begin in alternate macro mode, see @ref{Altmacro,,@code{.altmacro}}.
+Begin in alternate macro mode.
+@ifclear man
+@xref{Altmacro,,@code{.altmacro}}.
+@end ifclear
 
 @item -D
 Ignored.  This option is accepted for script compatibility with calls to
@@ -496,7 +504,9 @@ other assemblers.
 @item --defsym @var{sym}=@var{value}
 Define the symbol @var{sym} to be @var{value} before assembling the input file.
 @var{value} must be an integer constant.  As in C, a leading @samp{0x}
-indicates a hexadecimal value, and a leading @samp{0} indicates an octal value.
+indicates a hexadecimal value, and a leading @samp{0} indicates an octal
+value.  The value of the symbol can be overridden inside a source file via the
+use of a @code{.set} pseudo-op.
 
 @item -f
 ``fast''---skip whitespace and comment preprocessing (assume source is
@@ -546,9 +556,12 @@ Issue warnings when difference tables altered for long displacements.
 
 @item -L
 @itemx --keep-locals
-Keep (in the symbol table) local symbols.  On traditional a.out systems
-these start with @samp{L}, but different systems have different local
-label prefixes.
+Keep (in the symbol table) local symbols.  These symbols start with
+system-specific local label prefixes, typically @samp{.L} for ELF systems
+or @samp{L} for traditional a.out systems.
+@ifclear man
+@xref{Symbol Names}.
+@end ifclear
 
 @item --listing-lhs-width=@var{number}
 Set the maximum width, in words, of the output data column for an assembler
@@ -866,13 +879,13 @@ Specify to use the 32-bit double ABI.
 @item -mlong-double
 Specify to use the 64-bit double ABI.  
 
-@item --force-long-branchs
+@item --force-long-branches
 Relative branches are turned into absolute ones. This concerns
 conditional branches, unconditional branches and branches to a
 sub routine.
 
-@item -S | --short-branchs
-Do not turn relative branchs into absolute ones
+@item -S | --short-branches
+Do not turn relative branches into absolute ones
 when the offset is out of range.
 
 @item --strict-direct-mode
@@ -1006,6 +1019,12 @@ Generate code for the MIPS 16 processor.  This is equivalent to putting
 @code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -msmartmips
+@itemx -mno-smartmips
+Enables the SmartMIPS extension to the MIPS32 instruction set. This is
+equivalent to putting @code{.set smartmips} at the start of the assembly file.
+@samp{-mno-smartmips} turns off this option.
+
 @item -mips3d
 @itemx -no-mips3d
 Generate code for the MIPS-3D Application Specific Extension.
@@ -1020,10 +1039,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
@@ -1173,13 +1199,13 @@ Assemble all undocumented Z80 instructions without warning.
 Issue a warning for undocumented Z80 instructions that also work on R800.
 @item  -warn-unportable-instructions 
 @itemx -Wup
-Issue a warning for undocumented Z80 instructions that do notwork on R800.  
+Issue a warning for undocumented Z80 instructions that do not work on R800.  
 @item  -forbid-undocumented-instructions 
 @itemx -Fud
 Treat all undocumented instructions as errors.
 @item  -forbid-unportable-instructions 
 @itemx -Fup
-Treat undocumented Z80 intructions that do notwork on R800 as errors.
+Treat undocumented Z80 instructions that do not work on R800 as errors.
 @end table
 @end ifset
 
@@ -1504,7 +1530,8 @@ because many of them aren't supposed to happen.
 
 @cindex options, all versions of assembler
 This chapter describes command-line options available in @emph{all}
-versions of the @sc{gnu} assembler; @pxref{Machine Dependencies}, for options specific
+versions of the @sc{gnu} assembler; see @ref{Machine Dependencies},
+for options specific
 @ifclear GENERIC
 to the @value{TARGET} target.
 @end ifclear
@@ -1549,7 +1576,7 @@ assembler.)
 * K::             -K for difference tables
 @end ifset
 
-* L::             -L to retain local labels
+* L::             -L to retain local symbols
 * listing::       --listing-XXX to configure listing output
 * M::		  -M or --mri to assemble in MRI compatibility mode
 * MD::            --MD for dependency tracking
@@ -1604,7 +1631,8 @@ listing-control directives have no effect.
 The letters after @samp{-a} may be combined into one option,
 @emph{e.g.}, @samp{-aln}.
 
-Note if the assembler source is coming from the standard input (eg because it
+Note if the assembler source is coming from the standard input (e.g.,
+because it
 is being created by @code{@value{GCC}} and the @samp{-pipe} command line switch
 is being used) then the listing will not contain any comments or preprocessor
 directives.  This is because the listing code buffers input source lines from
@@ -1674,33 +1702,28 @@ alteration on other platforms.
 @ifset DIFF-TBL-KLUGE
 @cindex difference tables, warning
 @cindex warning for altered difference tables
-@command{@value{AS}} sometimes alters the code emitted for directives of the form
-@samp{.word @var{sym1}-@var{sym2}}; @pxref{Word,,@code{.word}}.
+@command{@value{AS}} sometimes alters the code emitted for directives of the
+form @samp{.word @var{sym1}-@var{sym2}}.  @xref{Word,,@code{.word}}.
 You can use the @samp{-K} option if you want a warning issued when this
 is done.
 @end ifset
 
 @node L
-@section Include Local Labels: @option{-L}
+@section Include Local Symbols: @option{-L}
 
 @kindex -L
-@cindex local labels, retaining in output
-Labels beginning with @samp{L} (upper case only) are called @dfn{local
-labels}. @xref{Symbol Names}.  Normally you do not see such labels when
-debugging, because they are intended for the use of programs (like
-compilers) that compose assembler programs, not for your notice.
-Normally both @command{@value{AS}} and @code{@value{LD}} discard such labels, so you do not
-normally debug with them.
-
-This option tells @command{@value{AS}} to retain those @samp{L@dots{}} symbols
+@cindex local symbols, retaining in output
+Symbols beginning with system-specific local label prefixes, typically
+@samp{.L} for ELF systems or @samp{L} for traditional a.out systems, are
+called @dfn{local symbols}.  @xref{Symbol Names}.  Normally you do not see
+such symbols when debugging, because they are intended for the use of
+programs (like compilers) that compose assembler programs, not for your
+notice.  Normally both @command{@value{AS}} and @code{@value{LD}} discard
+such symbols, so you do not normally debug with them.
+
+This option tells @command{@value{AS}} to retain those local symbols
 in the object file.  Usually if you do this you also tell the linker
-@code{@value{LD}} to preserve symbols whose names begin with @samp{L}.
-
-By default, a local label is any label beginning with @samp{L}, but each
-target is allowed to redefine the local label prefix.
-@ifset HPPA
-On the HPPA local labels begin with @samp{L$}.
-@end ifset
+@code{@value{LD}} to preserve those symbols.
 
 @node listing
 @section Configuring listing output: @option{--listing}
@@ -1708,9 +1731,11 @@ On the HPPA local labels begin with @samp{L$}.
 The listing feature of the assembler can be enabled via the command line switch
 @samp{-a} (@pxref{a}).  This feature combines the input source file(s) with a
 hex dump of the corresponding locations in the output object file, and displays
-them as a listing file.  The format of this listing can be controlled by pseudo
-ops inside the assembler source (@pxref{List} @pxref{Title} @pxref{Sbttl}
-@pxref{Psize} @pxref{Eject}) and also by the following switches:
+them as a listing file.  The format of this listing can be controlled by
+directives inside the assembler source (i.e., @code{.list} (@pxref{List}),
+@code{.title} (@pxref{Title}), @code{.sbttl} (@pxref{Sbttl}),
+@code{.psize} (@pxref{Psize}), and
+@code{.eject} (@pxref{Eject}) and also by the following switches:
 
 @table @gcctabopt
 @item --listing-lhs-width=@samp{number}
@@ -2072,7 +2097,7 @@ anything else you may get from your C compiler's preprocessor.  You can
 do include file processing with the @code{.include} directive
 (@pxref{Include,,@code{.include}}).  You can use the @sc{gnu} C compiler driver
 to get other ``CPP'' style preprocessing by giving the input file a
-@samp{.S} suffix.  @xref{Overall Options,, Options Controlling the Kind of
+@samp{.S} suffix.  @xref{Overall Options, ,Options Controlling the Kind of
 Output, gcc.info, Using GNU CC}.
 
 Excess whitespace, comments, and character constants
@@ -2209,7 +2234,7 @@ extends to the end of the line.
 To be compatible with past assemblers, lines that begin with @samp{#} have a
 special interpretation.  Following the @samp{#} should be an absolute
 expression (@pxref{Expressions}): the logical line number of the @emph{next}
-line.  Then a string (@pxref{Strings,, Strings}) is allowed: if present it is a
+line.  Then a string (@pxref{Strings, ,Strings}) is allowed: if present it is a
 new logical file name.  The rest of the line, if any, should be whitespace.
 
 If the first non-whitespace characters on the line are not numeric,
@@ -2284,8 +2309,8 @@ constants are an exception: they do not end statements.
 @end ifclear
 @ifset GENERIC
 A @dfn{statement} ends at a newline character (@samp{\n}) or line
-separator character.  (The line separator is usually @samp{;}, unless
-this conflicts with the comment character; @pxref{Machine Dependencies}.)  The
+separator character.  (The line separator is usually @samp{;}, unless this
+conflicts with the comment character; see @ref{Machine Dependencies}.)  The
 newline or separator character is considered part of the preceding
 statement.  Newlines and separators within character constants are an
 exception: they do not end statements.
@@ -2670,7 +2695,7 @@ independently of any floating point hardware in the computer running
 @cindex bit fields
 @cindex constants, bit field
 You can also define numeric constants as @dfn{bit fields}.
-specify two numbers separated by a colon---
+Specify two numbers separated by a colon---
 @example
 @var{mask}:@var{value}
 @end example
@@ -3069,8 +3094,8 @@ You
 can also use the @code{.subsection} directive (@pxref{SubSection})
 to specify a subsection: @samp{.subsection @var{expression}}.
 @end ifset
-@var{Expression} should be an absolute expression.
-(@xref{Expressions}.)  If you just say @samp{.text} then @samp{.text 0}
+@var{Expression} should be an absolute expression
+(@pxref{Expressions}).  If you just say @samp{.text} then @samp{.text 0}
 is assumed.  Likewise @samp{.data} means @samp{.data 0}.  Assembly
 begins in @code{text 0}.  For instance:
 @smallexample
@@ -3109,7 +3134,7 @@ The @code{.lcomm} pseudo-op defines a symbol in the bss section; see
 @ref{Lcomm,,@code{.lcomm}}.
 
 The @code{.comm} pseudo-op may be used to declare a common symbol, which is
-another form of uninitialized symbol; see @xref{Comm,,@code{.comm}}.
+another form of uninitialized symbol; see @ref{Comm,,@code{.comm}}.
 
 @ifset GENERIC
 When assembling for a target which supports multiple sections, such as ELF or
@@ -3180,8 +3205,8 @@ equals sign @samp{=}@samp{=} here represents an equivalent of the
 Symbol names begin with a letter or with one of @samp{._}.  On most
 machines, you can also use @code{$} in symbol names; exceptions are
 noted in @ref{Machine Dependencies}.  That character may be followed by any
-string of digits, letters, dollar signs (unless otherwise noted in
-@ref{Machine Dependencies}), and underscores.
+string of digits, letters, dollar signs (unless otherwise noted for a
+particular target machine), and underscores.
 @end ifclear
 @ifset SPECIAL-SYMS
 @ifset H8
@@ -3203,16 +3228,32 @@ in a program.
 
 @cindex local symbol names
 @cindex symbol names, local
+A local symbol is any symbol beginning with certain local label prefixes.
+By default, the local label prefix is @samp{.L} for ELF systems or
+@samp{L} for traditional a.out systems, but each target may have its own
+set of local label prefixes.
+@ifset HPPA
+On the HPPA local symbols begin with @samp{L$}.
+@end ifset
+
+Local symbols are defined and used within the assembler, but they are
+normally not saved in object files.  Thus, they are not visible when debugging.
+You may use the @samp{-L} option (@pxref{L, ,Include Local Symbols:
+@option{-L}}) to retain the local symbols in the object files.
+
+@subheading Local Labels
+
+@cindex local labels
 @cindex temporary symbol names
 @cindex symbol names, temporary
-Local symbols help compilers and programmers use names temporarily.
+Local labels help compilers and programmers use names temporarily.
 They create symbols which are guaranteed to be unique over the entire scope of
 the input source code and which can be referred to by a simple notation.
-To define a local symbol, write a label of the form @samp{@b{N}:} (where @b{N}
+To define a local label, write a label of the form @samp{@b{N}:} (where @b{N}
 represents any positive integer).  To refer to the most recent previous
-definition of that symbol write @samp{@b{N}b}, using the same number as when
+definition of that label write @samp{@b{N}b}, using the same number as when
 you defined the label.  To refer to the next definition of a local label, write
-@samp{@b{N}f}--- The @samp{b} stands for``backwards'' and the @samp{f} stands
+@samp{@b{N}f}---the @samp{b} stands for ``backwards'' and the @samp{f} stands
 for ``forwards''.
 
 There is no restriction on how you can use these labels, and you can reuse them
@@ -3241,16 +3282,17 @@ label_3:  branch label_4
 label_4:  branch label_3
 @end smallexample
 
-Local symbol names are only a notational device.  They are immediately
+Local label names are only a notational device.  They are immediately
 transformed into more conventional symbol names before the assembler uses them.
-The symbol names stored in the symbol table, appearing in error messages and
-optionally emitted to the object file.  The names are constructed using these
-parts:
+The symbol names are stored in the symbol table, appear in error messages, and
+are optionally emitted to the object file.  The names are constructed using
+these parts:
 
 @table @code
-@item L
-All local labels begin with @samp{L}. Normally both @command{@value{AS}} and
-@code{@value{LD}} forget symbols that start with @samp{L}. These labels are
+@item @emph{local label prefix}
+All local symbols begin with the system-specific local label prefix.
+Normally both @command{@value{AS}} and @code{@value{LD}} forget symbols
+that start with the local label prefix.  These labels are
 used for symbols you are never intended to see.  If you use the
 @samp{-L} option then @command{@value{AS}} retains these symbols in the
 object file. If you also instruct @code{@value{LD}} to retain these symbols,
@@ -3268,30 +3310,30 @@ of the same name.  The character has ASCII value of @samp{\002} (control-B).
 This is a serial number to keep the labels distinct.  The first definition of
 @samp{0:} gets the number @samp{1}.  The 15th definition of @samp{0:} gets the 
 number @samp{15}, and so on.  Likewise the first definition of @samp{1:} gets
-the number @samp{1} and its 15th defintion gets @samp{15} as well.
+the number @samp{1} and its 15th definition gets @samp{15} as well.
 @end table
 
-So for example, the first @code{1:} is named @code{L1@kbd{C-B}1}, the 44th
-@code{3:} is named @code{L3@kbd{C-B}44}.
+So for example, the first @code{1:} may be named @code{.L1@kbd{C-B}1}, and
+the 44th @code{3:} may be named @code{.L3@kbd{C-B}44}.
 
 @subheading Dollar Local Labels
 @cindex dollar local symbols
 
 @code{@value{AS}} also supports an even more local form of local labels called
-dollar labels.  These labels go out of scope (ie they become undefined) as soon
-as a non-local label is defined.  Thus they remain valid for only a small
+dollar labels.  These labels go out of scope (i.e., they become undefined) as
+soon as a non-local label is defined.  Thus they remain valid for only a small
 region of the input source code.  Normal local labels, by contrast, remain in
 scope for the entire file, or until they are redefined by another occurrence of
 the same local label.
 
 Dollar labels are defined in exactly the same way as ordinary local labels,
 except that instead of being terminated by a colon, they are terminated by a
-dollar sign.  eg @samp{@b{55$}}.
+dollar sign, e.g., @samp{@b{55$}}.
 
 They can also be distinguished from ordinary local labels by their transformed
-name which uses ASCII character @samp{\001} (control-A) as the magic character
-to distinguish them from ordinary labels.  Thus the 5th defintion of @samp{6$}
-is named @samp{L6@kbd{C-A}5}.
+names which use ASCII character @samp{\001} (control-A) as the magic character
+to distinguish them from ordinary labels.  For example, the fifth definition of
+@samp{6$} may be named @samp{.L6@kbd{C-A}5}.
 
 @node Dot
 @section The Special Dot Symbol
@@ -3722,14 +3764,14 @@ Some machine configurations provide additional directives.
 @end ifset
 @ifclear GENERIC
 @ifset machine-directives
-@xref{Machine Dependencies} for additional directives.
+@xref{Machine Dependencies}, for additional directives.
 @end ifset
 @end ifclear
 
 @menu
 * Abort::                       @code{.abort}
 @ifset COFF
-* ABORT::                       @code{.ABORT}
+* ABORT (COFF)::                       @code{.ABORT}
 @end ifset
 
 * Align::                       @code{.align @var{abs-expr} , @var{abs-expr}}
@@ -3740,7 +3782,7 @@ Some machine configurations provide additional directives.
 * Byte::                        @code{.byte @var{expressions}}
 * Comm::                        @code{.comm @var{symbol} , @var{length} }
 
-* CFI directives::		@code{.cfi_startproc}, @code{.cfi_endproc}, etc.
+* CFI directives::		@code{.cfi_startproc [simple]}, @code{.cfi_endproc}, etc.
 
 * Data::                        @code{.data @var{subsection}}
 @ifset COFF
@@ -3818,8 +3860,8 @@ Some machine configurations provide additional directives.
 * Noaltmacro::                  @code{.noaltmacro}
 * Nolist::                      @code{.nolist}
 * Octa::                        @code{.octa @var{bignums}}
-* Org::                         @code{.org @var{new-lc} , @var{fill}}
-* P2align::                     @code{.p2align @var{abs-expr} , @var{abs-expr}}
+* Org::                         @code{.org @var{new-lc}, @var{fill}}
+* P2align::                     @code{.p2align @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
 @ifset ELF
 * PopSection::                  @code{.popsection}
 * Previous::                    @code{.previous}
@@ -3837,6 +3879,7 @@ Some machine configurations provide additional directives.
 @end ifset
 
 * Quad::                        @code{.quad @var{bignums}}
+* Reloc::			@code{.reloc @var{offset}, @var{reloc_name}[, @var{expression}]}
 * Rept::			@code{.rept @var{count}}
 * Sbttl::                       @code{.sbttl "@var{subheading}"}
 @ifset COFF
@@ -3907,8 +3950,8 @@ of the source quit, it could use this directive tells @command{@value{AS}} to
 quit also.  One day @code{.abort} will not be supported.
 
 @ifset COFF
-@node ABORT
-@section @code{.ABORT}
+@node ABORT (COFF)
+@section @code{.ABORT} (COFF)
 
 @cindex @code{ABORT} directive
 When producing COFF output, @command{@value{AS}} accepts this directive as a
@@ -4058,19 +4101,40 @@ The syntax for @code{.comm} differs slightly on the HPPA.  The syntax is
 @end ifset
 
 @node CFI directives
-@section @code{.cfi_startproc}
+@section @code{.cfi_startproc [simple]}
 @cindex @code{cfi_startproc} directive
 @code{.cfi_startproc} is used at the beginning of each function that
 should have an entry in @code{.eh_frame}. It initializes some internal
-data structures and emits architecture dependent initial CFI instructions.
-Don't forget to close the function by 
+data structures. Don't forget to close the function by
 @code{.cfi_endproc}.
 
+Unless @code{.cfi_startproc} is used along with parameter @code{simple} 
+it also emits some architecture dependent initial CFI instructions.
+ 
 @section @code{.cfi_endproc}
 @cindex @code{cfi_endproc} directive
 @code{.cfi_endproc} is used at the end of a function where it closes its
 unwind entry previously opened by
-@code{.cfi_startproc}. and emits it to @code{.eh_frame}.
+@code{.cfi_startproc}, and emits it to @code{.eh_frame}.
+
+@section @code{.cfi_personality @var{encoding} [, @var{exp}]}
+@code{.cfi_personality} defines personality routine and its encoding.
+@var{encoding} must be a constant determining how the personality
+should be encoded.  If it is 255 (@code{DW_EH_PE_omit}), second
+argument is not present, otherwise second argument should be
+a constant or a symbol name.  When using indirect encodings,
+the symbol provided should be the location where personality
+can be loaded from, not the personality routine itself.
+The default after @code{.cfi_startproc} is @code{.cfi_personality 0xff},
+no personality routine.
+
+@section @code{.cfi_lsda @var{encoding} [, @var{exp}]}
+@code{.cfi_lsda} defines LSDA and its encoding.
+@var{encoding} must be a constant determining how the LSDA
+should be encoded.  If it is 255 (@code{DW_EH_PE_omit}), second
+argument is not present, otherwise second argument should be a constant
+or a symbol name.  The default after @code{.cfi_startproc} is @code{.cfi_lsda 0xff},
+no LSDA.
 
 @section @code{.cfi_def_cfa @var{register}, @var{offset}}
 @code{.cfi_def_cfa} defines a rule for computing CFA as: @i{take 
@@ -4102,6 +4166,31 @@ using the known displacement of the CFA register from the CFA.
 This is often easier to use, because the number will match the
 code it's annotating.
 
+@section @code{.cfi_register @var{register1}, @var{register2}}
+Previous value of @var{register1} is saved in register @var{register2}.
+
+@section @code{.cfi_restore @var{register}}
+@code{.cfi_restore} says that the rule for @var{register} is now the 
+same as it was at the beginning of the function, after all initial 
+instruction added by @code{.cfi_startproc} were executed.
+
+@section @code{.cfi_undefined @var{register}}
+From now on the previous value of @var{register} can't be restored anymore.
+
+@section @code{.cfi_same_value @var{register}}
+Current value of @var{register} is the same like in the previous frame, 
+i.e. no restoration needed.
+
+@section @code{.cfi_remember_state}, 
+First save all current rules for all registers by @code{.cfi_remember_state}, 
+then totally screw them up by subsequent @code{.cfi_*} directives and when 
+everything is hopelessly bad, use @code{.cfi_restore_state} to restore 
+the previous saved state.
+
+@section @code{.cfi_return_column @var{register}}
+Change return column @var{register}, i.e. the return address is either 
+directly in @var{register} or can be accessed by rules for @var{register}.
+
 @section @code{.cfi_signal_frame}
 Mark current function as signal trampoline.
 
@@ -4121,9 +4210,9 @@ to the @code{.debug_line} file name table.  The @var{fileno} operand should
 be a unique positive integer to use as the index of the entry in the table.
 The @var{filename} operand is a C string literal.
 
-The detail of filename indicies is exposed to the user because the filename
+The detail of filename indices is exposed to the user because the filename
 table is shared with the @code{.debug_info} section of the dwarf2 debugging
-information, and thus the user must know the exact indicies that table
+information, and thus the user must know the exact indices that table
 entries will have.
 
 @section @code{.loc @var{fileno} @var{lineno} [@var{column}] [@var{options}]}
@@ -4262,7 +4351,7 @@ Force a page break at this point, when generating assembly listings.
 
 @cindex @code{else} directive
 @code{.else} is part of the @command{@value{AS}} support for conditional
-assembly; @pxref{If,,@code{.if}}.  It marks the beginning of a section
+assembly; see @ref{If,,@code{.if}}.  It marks the beginning of a section
 of code to be assembled if the condition for the preceding @code{.if}
 was false.
 
@@ -4271,7 +4360,7 @@ was false.
 
 @cindex @code{elseif} directive
 @code{.elseif} is part of the @command{@value{AS}} support for conditional
-assembly; @pxref{If,,@code{.if}}.  It is shorthand for beginning a new
+assembly; see @ref{If,,@code{.if}}.  It is shorthand for beginning a new
 @code{.if} block that would otherwise fill the entire @code{.else} section.
 
 @node End
@@ -4316,7 +4405,7 @@ conditionally.  @xref{If,,@code{.if}}.
 @cindex assigning values to symbols
 @cindex symbols, assigning values to
 This directive sets the value of @var{symbol} to @var{expression}.
-It is synonymous with @samp{.set}; @pxref{Set,,@code{.set}}.
+It is synonymous with @samp{.set}; see @ref{Set,,@code{.set}}.
 
 @ifset HPPA
 The syntax for @code{equ} on the HPPA is 
@@ -4327,8 +4416,8 @@ The syntax for @code{equ} on the HPPA is
 The syntax for @code{equ} on the Z80 is 
 @samp{@var{symbol} equ @var{expression}}. 
 On the Z80 it is an eror if @var{symbol} is already defined,
-but the symbol is not protected from later redefinition, 
-compare @xref{Equiv}.
+but the symbol is not protected from later redefinition. 
+Compare @ref{Equiv}.
 @end ifset
 
 @node Equiv
@@ -4484,7 +4573,7 @@ compatibility with other assemblers.
 @ifset HPPA
 On the HPPA, @code{.global} is not always enough to make it accessible to other
 partial programs.  You may need the HPPA-only @code{.EXPORT} directive as well.
-@xref{HPPA Directives,, HPPA Assembler Directives}.
+@xref{HPPA Directives, ,HPPA Assembler Directives}.
 @end ifset
 
 @ifset ELF
@@ -4721,8 +4810,7 @@ is equivalent to assembling
         move    d3,sp@@-
 @end example
 
-For some caveats with the spelling of @var{symbol}, see also the discussion
-at @xref{Macro}.
+For some caveats with the spelling of @var{symbol}, see also @ref{Macro}.
 
 @node Irpc
 @section @code{.irpc @var{symbol},@var{values}}@dots{}
@@ -4907,7 +4995,7 @@ the initial value of the listing counter is one.
 @section @code{.long @var{expressions}}
 
 @cindex @code{long} directive
-@code{.long} is the same as @samp{.int}, @pxref{Int,,@code{.int}}.
+@code{.long} is the same as @samp{.int}.  @xref{Int,,@code{.int}}.
 
 @ignore
 @c no one seems to know what this is for or whether this description is
@@ -4971,7 +5059,7 @@ indicate whether all invocations must specify a non-blank value (through
 (through @samp{:@code{vararg}}).  You can supply a default value for any
 macro argument by following the name with @samp{=@var{deflt}}.  You
 cannot define two macros with the same @var{macname} unless it has been
-subject to the @code{.purgem} directive (@xref{Purgem}.) between the two
+subject to the @code{.purgem} directive (@pxref{Purgem}) between the two
 definitions.  For example, these are all valid @code{.macro} statements:
 
 @table @code
@@ -4979,7 +5067,7 @@ definitions.  For example, these are all valid @code{.macro} statements:
 Begin the definition of a macro called @code{comm}, which takes no
 arguments.
 
-@item .macro plus1 p, p1
+@item  .macro plus1 p, p1
 @itemx .macro plus1 p p1
 Either statement begins the definition of a macro called @code{plus1},
 which takes two arguments; within the macro definition, write
@@ -4993,7 +5081,6 @@ After the definition is complete, you can call the macro either as
 @var{a} and @samp{\p2} evaluating to @var{b}), or as @samp{reserve_str
 ,@var{b}} (with @samp{\p1} evaluating as the default, in this case
 @samp{0}, and @samp{\p2} evaluating to @var{b}).
-@end table
 
 @item .macro m p1:req, p2=0, p3:vararg
 Begin the definition of a macro called @code{m}, with at least three
@@ -5005,21 +5092,72 @@ When you call a macro, you can specify the argument values either by
 position, or by keyword.  For example, @samp{sum 9,17} is equivalent to
 @samp{sum to=17, from=9}.
 
+@end table
+
 Note that since each of the @var{macargs} can be an identifier exactly
 as any other one permitted by the target architecture, there may be
 occasional problems if the target hand-crafts special meanings to certain
-characters when they occur in a special position.  For example, if colon
+characters when they occur in a special position.  For example, if the colon
 (@code{:}) is generally permitted to be part of a symbol name, but the
-architecture specific code special-cases it when occuring as the final
+architecture specific code special-cases it when occurring as the final
 character of a symbol (to denote a label), then the macro parameter
 replacement code will have no way of knowing that and consider the whole
 construct (including the colon) an identifier, and check only this
-identifier for being the subject to parameter substitution.  In this
-example, besides the potential of just separating identifier and colon
-by white space, using alternate macro syntax (@xref{Altmacro}.) and
-ampersand (@code{&}) as the character to separate literal text from macro
-parameters (or macro parameters from one another) would provide a way to
-achieve the same effect:
+identifier for being the subject to parameter substitution.  So for example
+this macro definition:
+
+@example
+	.macro label l
+\l:
+	.endm
+@end example
+
+might not work as expected.  Invoking @samp{label foo} might not create a label
+called @samp{foo} but instead just insert the text @samp{\l:} into the
+assembler source, probably generating an error about an unrecognised
+identifier.
+
+Similarly problems might occur with the period character (@samp{.})
+which is often allowed inside opcode names (and hence identifier names).  So
+for example constructing a macro to build an opcode from a base name and a
+length specifier like this:
+
+@example
+	.macro opcode base length
+        \base.\length
+	.endm
+@end example
+
+and invoking it as @samp{opcode store l} will not create a @samp{store.l}
+instruction but instead generate some kind of error as the assembler tries to
+interpret the text @samp{\base.\length}.
+
+There are several possible ways around this problem:
+
+@table @code
+@item Insert white space
+If it is possible to use white space characters then this is the simplest
+solution.  eg:
+
+@example
+	.macro label l
+\l :
+	.endm
+@end example
+
+@item Use @samp{\()}
+The string @samp{\()} can be used to separate the end of a macro argument from
+the following text.  eg:
+
+@example
+	.macro opcode base length
+        \base\().\length
+	.endm
+@end example
+
+@item Use the alternate macro syntax mode
+In the alternative macro syntax mode the ampersand character (@samp{&}) can be
+used as a separator.  eg:
 
 @example
 	.altmacro
@@ -5027,9 +5165,11 @@ achieve the same effect:
 l&:
 	.endm
 @end example
+@end table
 
-This applies identically to the identifiers used in @code{.irp} (@xref{Irp}.)
-and @code{.irpc} (@xref{Irpc}.).
+Note: this problem of correctly identifying string parameters to pseudo ops
+also applies to the identifiers used in @code{.irp} (@pxref{Irp}) 
+and @code{.irpc} (@pxref{Irpc}) as well.
 
 @item .endm
 @cindex @code{endm} directive
@@ -5071,7 +5211,7 @@ You can write strings delimited in these other ways besides
 
 @table @code
 @item '@var{string}'
-You can delimit strings with single-quote charaters.
+You can delimit strings with single-quote characters.
 
 @item <@var{string}>
 You can delimit strings with matching angle brackets.
@@ -5090,7 +5230,7 @@ and use the result as a string.
 
 @node Noaltmacro
 @section @code{.noaltmacro}
-Disable alternate macro mode.  @ref{Altmacro}
+Disable alternate macro mode.  @xref{Altmacro}.
 
 @node Nolist
 @section @code{.nolist}
@@ -5314,6 +5454,20 @@ warning message; and just takes the lowest order 16 bytes of the bignum.
 @cindex integer, 16-byte
 @end ifset
 
+@node Reloc
+@section @code{.reloc @var{offset}, @var{reloc_name}[, @var{expression}]}
+
+@cindex @code{reloc} directive
+Generate a relocation at @var{offset} of type @var{reloc_name} with value
+@var{expression}.  If @var{offset} is a number, the relocation is generated in
+the current section.  If @var{offset} is an expression that resolves to a
+symbol plus offset, the relocation is generated in the given symbol's section.
+@var{expression}, if present, must resolve to a symbol plus addend or to an
+absolute value, but note that not all targets support an addend.  e.g. ELF REL
+targets such as i386 store an addend in the section contents rather than in the
+relocation.  This low level interface does not support addends stored in the
+section.
+
 @node Rept
 @section @code{.rept @var{count}}
 
@@ -5487,7 +5641,7 @@ ARM) then another character is used instead.  For example the ARM port uses the
 @code{%} character.
 
 If @var{flags} contains the @code{M} symbol then the @var{type} argument must
-be specified as well as an extra argument - @var{entsize} - like this:
+be specified as well as an extra argument---@var{entsize}---like this:
 
 @smallexample
 .section @var{name} , "@var{flags}"M, @@@var{type}, @var{entsize}
@@ -5516,7 +5670,7 @@ indicates that only one copy of this section should be retained
 an alias for comdat
 @end table
 
-Note - if both the @var{M} and @var{G} flags are present then the fields for
+Note: if both the @var{M} and @var{G} flags are present then the fields for
 the Merge flag should come first, like this:
 
 @smallexample
@@ -5589,7 +5743,7 @@ On Z80 @code{set} is a real instruction, use
 @xref{Word,,@code{.word}}.
 
 In some configurations, however, @code{.short} and @code{.word} generate
-numbers of different lengths; @pxref{Machine Dependencies}.
+numbers of different lengths.  @xref{Machine Dependencies}.
 @end ifset
 @ifclear GENERIC
 @ifset W16
@@ -5672,7 +5826,7 @@ symbols.
 @cindex @code{sleb128} directive
 @var{sleb128} stands for ``signed little endian base 128.''  This is a 
 compact, variable length representation of numbers used by the DWARF
-symbolic debugging format.  @xref{Uleb128,@code{.uleb128}}.
+symbolic debugging format.  @xref{Uleb128, ,@code{.uleb128}}.
 
 @ifclear no-space-dir
 @node Skip
@@ -5964,9 +6118,21 @@ For ELF targets, the @code{.type} directive is used like this:
 This sets the type of symbol @var{name} to be either a
 function symbol or an object symbol.  There are five different syntaxes
 supported for the @var{type description} field, in order to provide
-compatibility with various other assemblers.  The syntaxes supported are:
+compatibility with various other assemblers.
+
+Because some of the characters used in these syntaxes (such as @samp{@@} and
+@samp{#}) are comment characters for some architectures, some of the syntaxes
+below do not work on all architectures.  The first variant will be accepted by
+the GNU assembler on all architectures so that variant should be used for
+maximum portability, if you do not need to assemble your code with other
+assemblers.
+
+The syntaxes supported are:
 
 @smallexample
+  .type <name> STT_FUNCTION
+  .type <name> STT_OBJECT
+
   .type <name>,#function
   .type <name>,#object
 
@@ -5978,9 +6144,6 @@ compatibility with various other assemblers.  The syntaxes supported are:
   
   .type <name>,"function"
   .type <name>,"object"
-  
-  .type <name> STT_FUNCTION
-  .type <name> STT_OBJECT
 @end smallexample
 @end ifset
 @end ifset
@@ -5991,7 +6154,7 @@ compatibility with various other assemblers.  The syntaxes supported are:
 @cindex @code{uleb128} directive
 @var{uleb128} stands for ``unsigned little endian base 128.''  This is a 
 compact, variable length representation of numbers used by the DWARF
-symbolic debugging format.  @xref{Sleb128,@code{.sleb128}}.
+symbolic debugging format.  @xref{Sleb128, ,@code{.sleb128}}.
 
 @ifset COFF
 @node Val
@@ -6034,7 +6197,7 @@ This directive finds or creates a symbol @code{table} and creates a
 This directive finds the symbol @code{child} and finds or creates the symbol
 @code{parent} and then creates a @code{VTABLE_INHERIT} relocation for the
 parent whose addend is the value of the child symbol.  As a special case the
-parent name of @code{0} is treated as refering the @code{*ABS*} section.
+parent name of @code{0} is treated as referring to the @code{*ABS*} section.
 @end ifset
 
 @node Warning
@@ -6182,9 +6345,15 @@ subject, see the hardware manufacturer's manual.
 @ifset ARM
 * ARM-Dependent::               ARM Dependent Features
 @end ifset
+@ifset AVR
+* AVR-Dependent::               AVR Dependent Features
+@end ifset
 @ifset BFIN
 * BFIN-Dependent::		BFIN Dependent Features
 @end ifset
+@ifset CR16
+* CR16-Dependent::              CR16 Dependent Features
+@end ifset
 @ifset CRIS
 * CRIS-Dependent::              CRIS Dependent Features
 @end ifset
@@ -6298,10 +6467,18 @@ subject, see the hardware manufacturer's manual.
 @include c-arm.texi
 @end ifset
 
+@ifset AVR
+@include c-avr.texi
+@end ifset
+
 @ifset BFIN
 @include c-bfin.texi
 @end ifset
 
+@ifset CR16
+@include c-cr16.texi
+@end ifset
+
 @ifset CRIS
 @include c-cris.texi
 @end ifset
@@ -6508,8 +6685,10 @@ You can find contact information for many support companies and
 individuals in the file @file{etc/SERVICE} in the @sc{gnu} Emacs
 distribution.
 
+@ifset BUGURL
 In any event, we also recommend that you send bug reports for @command{@value{AS}}
-to @samp{bug-binutils@@gnu.org}.
+to @value{BUGURL}.
+@end ifset
 
 The fundamental principle of reporting bugs usefully is this:
 @strong{report all the facts}.  If you are not sure whether to state a
@@ -6583,7 +6762,7 @@ make a mistake.
 
 Even if the problem you experience is a fatal signal, you should still say so
 explicitly.  Suppose something strange is going on, such as, your copy of
-@command{@value{AS}} is out of synch, or you have encountered a bug in the C
+@command{@value{AS}} is out of sync, or you have encountered a bug in the C
 library on your system.  (This has happened!)  Your copy might crash and ours
 would not.  If you told us to expect a crash, then when ours fails to crash, we
 would know that the bug was not happening for us.  If you had not told us to
@@ -6736,7 +6915,7 @@ Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic*
 flavors.
 
 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from Tensilica,
-Inc. added support for Xtensa processors.
+Inc.@: added support for Xtensa processors.
 
 Several engineers at Cygnus Support have also provided many small bug fixes and
 configuration enhancements.
@@ -6748,12 +6927,11 @@ intentionally leaving anyone out.
 
 @include fdl.texi
 
-@node Index
-@unnumbered Index
+@node AS Index
+@unnumbered AS Index
 
 @printindex cp
 
-@contents
 @bye
 @c Local Variables:
 @c fill-column: 79
diff --git a/gas/doc/asconfig.texi b/gas/doc/asconfig.texi
deleted file mode 100644
index 150685f38fb3..000000000000
--- a/gas/doc/asconfig.texi
+++ /dev/null
@@ -1,90 +0,0 @@
-@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
-@c 2003, 2005
-@c Free Software Foundation, Inc.
-@c This file is part of the documentation for the GAS manual
-
-@c Configuration settings for all-inclusive version of manual
-
-@c switches:------------------------------------------------------------
-@c Properties of the manual
-@c ========================
-@c Discuss all architectures?
-@set ALL-ARCH
-@c A generic form of manual (not tailored to specific target)?
-@set GENERIC
-@c Include text on assembler internals?
-@clear INTERNALS
-@c Many object formats supported in this config?
-@set MULTI-OBJ
-
-@c Object formats of interest
-@c ==========================
-@set AOUT
-@set COFF
-@set ELF
-@set SOM
-
-@c CPUs of interest
-@c ================
-@set ALPHA
-@set ARC
-@set ARM
-@set BFIN
-@set CRIS
-@set D10V
-@set D30V
-@set H8/300
-@set HPPA
-@set I370
-@set I80386
-@set I860
-@set I960
-@set IA64
-@set IP2K
-@set M32C
-@set M32R
-@set xc16x
-@set M68HC11
-@set M680X0
-@set MCORE
-@set MIPS
-@set MMIX
-@set MS1
-@set MSP430
-@set PDP11
-@set PJ
-@set PPC
-@set SH
-@set SPARC
-@set TIC54X
-@set V850
-@set VAX
-@set XTENSA
-@set Z80
-@set Z8000
-
-@c Does this version of the assembler use the difference-table kluge?
-@set DIFF-TBL-KLUGE
-
-@c Do all machines described use IEEE floating point?
-@clear IEEEFLOAT
-
-@c Is a word 32 bits, or 16?
-@clear W32
-@set W16
-
-@c Do symbols have different characters than usual?
-@clear SPECIAL-SYMS
-
-@c strings:------------------------------------------------------------
-@c Name of the assembler:
-@set AS as
-@c Name of C compiler:
-@set GCC gcc
-@c Name of linker:
-@set LD ld
-@c Text for target machine (best not used in generic case; but just in case...)
-@set TARGET machine specific
-@c Name of object format NOT SET in generic version
-@clear OBJ-NAME
-@set top_srcdir ../.././gas
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 04544d1e4951..7f8ed6eb4007 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -230,7 +230,7 @@ Determines the kinds of suffixes to be allowed.  Valid values are
 @code{SUFFIX_FLAG} which indicates the absence or presence of
 conditional suffixes and flag setting by the extension instruction.
 It is also possible to specify that an instruction sets the flags and
-is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
+is condtional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
 
 @item @var{syntaxclass}
 Determines the syntax class for the instruction.  It can have the
@@ -251,7 +251,7 @@ Syntax Class Modifiers are:
 
 @item @code{OP1_MUST_BE_IMM}:
 Modifies syntax class SYNTAX_3OP,  specifying that the first operand
-of a three-operand instruction must be an immediate (i.e. the result
+of a three-operand instruction must be an immediate (i.e., the result
 is discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it with
 SYNTAX_3OP as given in the example below.  This could usually be used
 to set the flags using specific instructions and not retain results. 
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index ca0998bea669..8fc2972e5750 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -155,9 +155,9 @@ names are recognized:
 @code{armv6z},
 @code{armv6zk},
 @code{armv7},
-@code{armv7a},
-@code{armv7r},
-@code{armv7m},
+@code{armv7-a},
+@code{armv7-r},
+@code{armv7-m},
 @code{iwmmxt}
 and
 @code{xscale}.
@@ -254,7 +254,7 @@ and
 @item -meabi=@var{ver}
 This option specifies which EABI version the produced object files should
 conform to.
-The following values are recognised:
+The following values are recognized:
 @code{gnu},
 @code{4}
 and
@@ -284,6 +284,7 @@ as position-independent code (PIC).
 @menu
 * ARM-Chars::                Special Characters
 * ARM-Regs::                 Register Names
+* ARM-Relocations::	     Relocations
 @end menu
 
 @node ARM-Chars
@@ -323,7 +324,46 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 @cindex ARM floating point (@sc{ieee})
 The ARM family uses @sc{ieee} floating-point numbers.
 
+@node ARM-Relocations
+@subsection ARM relocation generation
+
+@cindex data relocations, ARM
+@cindex ARM data relocations
+Specific data relocations can be generated by putting the relocation name
+in parentheses after the symbol name.  For example:
+
+@smallexample
+        .word foo(TARGET1)
+@end smallexample
+
+This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
+@var{foo}.
+The following relocations are supported:
+@code{GOT},
+@code{GOTOFF},
+@code{TARGET1},
+@code{TARGET2},
+@code{SBREL},
+@code{TLSGD},
+@code{TLSLDM},
+@code{TLSLDO},
+@code{GOTTPOFF}
+and
+@code{TPOFF}.
+
+For compatibility with older toolchains the assembler also accepts
+@code{(PLT)} after branch targets.  This will generate the deprecated
+@samp{R_ARM_PLT32} relocation.
 
+@cindex MOVW and MOVT relocations, ARM
+Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
+by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
+respectively.  For example to load the 32-bit address of foo into r0:
+
+@smallexample
+        MOVW r0, #:lower16:foo
+        MOVT r0, #:upper16:foo
+@end smallexample
 
 @node ARM Directives
 @section ARM Machine Directives
@@ -351,7 +391,7 @@ example:
 @cindex @code{unreq} directive, ARM
 @item .unreq @var{alias-name}
 This undefines a register alias which was previously defined using the
-@code{req} directive.  For example:
+@code{req}, @code{dn} or @code{qn} directives.  For example:
 
 @smallexample
         foo .req r0
@@ -362,6 +402,36 @@ An error occurs if the name is undefined.  Note - this pseudo op can
 be used to delete builtin in register name aliases (eg 'r0').  This
 should only be done if it is really necessary.
 
+@cindex @code{dn} and @code{qn} directives, ARM
+@item @var{name} .dn @var{register name} [@var{.type}] [@var{[index]}]
+@item @var{name} .qn @var{register name} [@var{.type}] [@var{[index]}]
+
+The @code{dn} and @code{qn} directives are used to create typed
+and/or indexed register aliases for use in Advanced SIMD Extension
+(Neon) instructions.  The former should be used to create aliases
+of double-precision registers, and the latter to create aliases of
+quad-precision registers.
+
+If these directives are used to create typed aliases, those aliases can
+be used in Neon instructions instead of writing types after the mnemonic
+or after each operand.  For example:
+
+@smallexample
+        x .dn d2.f32
+        y .dn d3.f32
+        z .dn d4.f32[1]
+        vmul x,y,z
+@end smallexample
+
+This is equivalent to writing the following:
+
+@smallexample
+        vmul.f32 d2,d3,d4[1]
+@end smallexample
+
+Aliases created using @code{dn} or @code{qn} can be destroyed using
+@code{unreq}.
+
 @cindex @code{code} directive, ARM
 @item .code @code{[16|32]}
 This directive selects the instruction set being generated. The value 16
@@ -389,6 +459,9 @@ between Arm and Thumb instructions and should be used even if
 interworking is not going to be performed.  The presence of this
 directive also implies @code{.thumb}
 
+This directive is not neccessary when generating EABI objects.  On these
+targets the encoding is implicit when generating Thumb code.
+
 @cindex @code{thumb_set} directive, ARM
 @item .thumb_set
 This performs the equivalent of a @code{.set} directive in that it
@@ -466,7 +539,7 @@ instruction.
   sfmfd f4, 2, [sp]!
 @exdent @emph{VFP registers}
   .save @{d8, d9, d10@}
-  fstmdf sp!, @{d8, d9, d10@}
+  fstmdx sp!, @{d8, d9, d10@}
 @exdent @emph{iWMMXt registers}
   .save @{wr10, wr11@}
   wstrd wr11, [sp, #-8]!
@@ -478,6 +551,26 @@ or
   wstrd wr10, [sp, #-8]!
 @end smallexample
 
+@cindex @code{.vsave} directive, ARM
+@item .vsave @var{vfp-reglist}
+Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
+using FLDMD.  Also works for VFPv3 registers
+that are to be restored using VLDM.
+The format of @var{vfp-reglist} is the same as the corresponding store-multiple
+instruction.
+
+@smallexample
+@exdent @emph{VFP registers}
+  .vsave @{d8, d9, d10@}
+  fstmdd sp!, @{d8, d9, d10@}
+@exdent @emph{VFPv3 registers}
+  .vsave @{d15, d16, d17@}
+  vstm sp!, @{d15, d16, d17@}
+@end smallexample
+
+Since FLDMX and FSTMX are now deprecated, this directive should be
+used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
+
 @cindex @code{.pad} directive, ARM
 @item .pad #@var{count}
 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
@@ -485,8 +578,10 @@ A positive value indicates the function prologue allocated stack space by
 decrementing the stack pointer.
 
 @cindex @code{.movsp} directive, ARM
-@item .movsp @var{reg}
-Tell the unwinder that @var{reg} contains the current stack pointer.
+@item .movsp @var{reg} [, #@var{offset}]
+Tell the unwinder that @var{reg} contains an offset from the current
+stack pointer.  If @var{offset} is not specified then it is assumed to be
+zero.
 
 @cindex @code{.setfp} directive, ARM
 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
@@ -523,6 +618,12 @@ for the @option{-mcpu} commandline option.
 Select the target architecture.  Valid values for @var{name} are the same as
 for the @option{-march} commandline option.
 
+@cindex @code{.object_arch} directive, ARM
+@item .object_arch @var{name}
+Override the architecture recorded in the EABI object attribute section.
+Valid values for @var{name} are the same as for the @code{.arch} directive.
+Typically this is useful when code uses runtime detection of CPU features.
+
 @cindex @code{.fpu} directive, ARM
 @item .fpu @var{name}
 Select the floating point unit to assemble for.  Valid values for @var{name}
diff --git a/gas/doc/c-avr.texi b/gas/doc/c-avr.texi
new file mode 100644
index 000000000000..9bf743d77d35
--- /dev/null
+++ b/gas/doc/c-avr.texi
@@ -0,0 +1,364 @@
+@c Copyright 2006
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node AVR-Dependent
+@chapter AVR Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter AVR Dependent Features
+@end ifclear
+
+@cindex AVR support
+@menu
+* AVR Options::              Options
+* AVR Syntax::               Syntax
+* AVR Opcodes::              Opcodes
+@end menu
+
+@node AVR Options
+@section Options
+@cindex AVR options (none)
+@cindex options for AVR (none)
+
+@table @code
+
+@cindex @code{-mmcu=} command line option, AVR
+@item -mmcu=@var{mcu}
+Specify ATMEL AVR instruction set or MCU type.
+
+Instruction set avr1 is for the minimal AVR core, not supported by the C
+compiler, only for assembler programs (MCU types: at90s1200, attiny10,
+attiny11, attiny12, attiny15, attiny28).
+
+Instruction set avr2 (default) is for the classic AVR core with up to
+8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
+attiny26, at90s2333, at90s2343, at90s4414, at90s4433, at90s4434,
+at90s8515, at90c8534, at90s8535, at86rf401, attiny13, attiny2313,
+attiny261, attiny461, attiny861, attiny24, attiny44, attiny84, attiny25,
+attiny45, attiny85).
+
+Instruction set avr3 is for the classic AVR core with up to 128K program
+memory space (MCU types: atmega103, atmega603, at43usb320, at43usb355,
+at76c711).
+
+Instruction set avr4 is for the enhanced AVR core with up to 8K program
+memory space (MCU types: atmega48, atmega8, atmega83, atmega85, atmega88,
+atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm3).
+
+Instruction set avr5 is for the enhanced AVR core with up to 128K program
+memory space (MCU types: atmega16, atmega161, atmega162, atmega163,
+atmega164p, atmega165, atmega165p, atmega168, atmega169, atmega169p, 
+atmega32, atmega323, atmega324p, atmega325, atmega325p, atmega329, 
+atmega329p, atmega3250, atmega3250p, atmega3290, atmega3290p, atmega406, 
+atmega64, atmega640, atmega644, atmega644p, atmega128, atmega1280, 
+atmega1281, atmega645, atmega649, atmega6450, atmega6490, atmega16hva, 
+at90can32, at90can64, at90can128, at90usb82, at90usb162, at90usb646, 
+at90usb647, at90usb1286, at90usb1287, at94k).
+
+Instruction set avr6 is for the enhanced AVR core with 256K program
+memory space (MCU types: atmega2560, atmega2561).
+
+@cindex @code{-mall-opcodes} command line option, AVR
+@item -mall-opcodes
+Accept all AVR opcodes, even if not supported by @code{-mmcu}.
+
+@cindex @code{-mno-skip-bug} command line option, AVR
+@item -mno-skip-bug
+This option disable warnings for skipping two-word instructions.
+
+@cindex @code{-mno-wrap} command line option, AVR
+@item -mno-wrap
+This option reject @code{rjmp/rcall} instructions with 8K wrap-around.
+
+@end table
+
+
+@node AVR Syntax
+@section Syntax
+@menu
+* AVR-Chars::                Special Characters
+* AVR-Regs::                 Register Names
+* AVR-Modifiers::            Relocatable Expression Modifiers
+@end menu
+
+@node AVR-Chars
+@subsection Special Characters
+
+@cindex line comment character, AVR
+@cindex AVR line comment character
+
+The presence of a @samp{;} on a line indicates the start of a comment
+that extends to the end of the current line.  If a @samp{#} appears as
+the first character of a line, the whole line is treated as a comment.
+
+@cindex line separator, AVR
+@cindex statement separator, AVR
+@cindex AVR line separator
+
+The @samp{$} character can be used instead of a newline to separate
+statements.
+
+@node AVR-Regs
+@subsection Register Names
+
+@cindex AVR register names
+@cindex register names, AVR
+
+The AVR has 32 x 8-bit general purpose working registers @samp{r0},
+@samp{r1}, ... @samp{r31}.
+Six of the 32 registers can be used as three 16-bit indirect address
+register pointers for Data Space addressing. One of the these address
+pointers can also be used as an address pointer for look up tables in
+Flash program memory. These added function registers are the 16-bit
+@samp{X}, @samp{Y} and @samp{Z} - registers.
+
+@smallexample
+X = @r{r26:r27}
+Y = @r{r28:r29}
+Z = @r{r30:r31}
+@end smallexample
+
+@node AVR-Modifiers
+@subsection Relocatable Expression Modifiers
+
+@cindex AVR modifiers
+@cindex syntax, AVR
+
+The assembler supports several modifiers when using relocatable addresses
+in AVR instruction operands.  The general syntax is the following:
+
+@smallexample
+modifier(relocatable-expression)
+@end smallexample
+
+@table @code
+@cindex symbol modifiers
+
+@item lo8
+
+This modifier allows you to use bits 0 through 7 of
+an address expression as 8 bit relocatable expression.
+
+@item hi8
+
+This modifier allows you to use bits 7 through 15 of an address expression
+as 8 bit relocatable expression.  This is useful with, for example, the
+AVR @samp{ldi} instruction and @samp{lo8} modifier.
+
+For example
+
+@smallexample
+ldi r26, lo8(sym+10)
+ldi r27, hi8(sym+10)
+@end smallexample
+
+@item hh8
+
+This modifier allows you to use bits 16 through 23 of
+an address expression as 8 bit relocatable expression.
+Also, can be useful for loading 32 bit constants.
+
+@item hlo8
+
+Synonym of @samp{hh8}.
+
+@item hhi8
+
+This modifier allows you to use bits 24 through 31 of
+an expression as 8 bit expression. This is useful with, for example, the
+AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8},
+@samp{hhi8}, modifier.
+
+For example
+
+@smallexample
+ldi r26, lo8(285774925)
+ldi r27, hi8(285774925)
+ldi r28, hlo8(285774925)
+ldi r29, hhi8(285774925)
+; r29,r28,r27,r26 = 285774925
+@end smallexample
+
+@item pm_lo8
+
+This modifier allows you to use bits 0 through 7 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory. The using of @samp{pm_lo8} similar
+to @samp{lo8}.
+
+@item pm_hi8
+
+This modifier allows you to use bits 8 through 15 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory.
+
+@item pm_hh8
+
+This modifier allows you to use bits 15 through 23 of
+an address expression as 8 bit relocatable expression.
+This modifier useful for addressing data or code from
+Flash/Program memory.
+
+@end table
+
+@node AVR Opcodes
+@section Opcodes
+
+@cindex AVR opcode summary
+@cindex opcode summary, AVR
+@cindex mnemonics, AVR
+@cindex instruction summary, AVR
+For detailed information on the AVR machine instruction set, see
+@url{www.atmel.com/products/AVR}.
+
+@code{@value{AS}} implements all the standard AVR opcodes.
+The following table summarizes the AVR opcodes, and their arguments.
+
+@smallexample
+@i{Legend:}
+   r   @r{any register}
+   d   @r{`ldi' register (r16-r31)}
+   v   @r{`movw' even register (r0, r2, ..., r28, r30)}
+   a   @r{`fmul' register (r16-r23)}
+   w   @r{`adiw' register (r24,r26,r28,r30)}
+   e   @r{pointer registers (X,Y,Z)}
+   b   @r{base pointer register and displacement ([YZ]+disp)}
+   z   @r{Z pointer register (for [e]lpm Rd,Z[+])}
+   M   @r{immediate value from 0 to 255}
+   n   @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible}
+   s   @r{immediate value from 0 to 7}
+   P   @r{Port address value from 0 to 63. (in, out)}
+   p   @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)}
+   K   @r{immediate value from 0 to 63 (used in `adiw', `sbiw')}
+   i   @r{immediate value}
+   l   @r{signed pc relative offset from -64 to 63}
+   L   @r{signed pc relative offset from -2048 to 2047}
+   h   @r{absolute code address (call, jmp)}
+   S   @r{immediate value from 0 to 7 (S = s << 4)}
+   ?   @r{use this opcode entry if no parameters, else use next opcode entry}
+
+1001010010001000   clc  
+1001010011011000   clh  
+1001010011111000   cli  
+1001010010101000   cln  
+1001010011001000   cls  
+1001010011101000   clt  
+1001010010111000   clv  
+1001010010011000   clz  
+1001010000001000   sec  
+1001010001011000   seh  
+1001010001111000   sei  
+1001010000101000   sen  
+1001010001001000   ses  
+1001010001101000   set  
+1001010000111000   sev  
+1001010000011000   sez  
+100101001SSS1000   bclr    S
+100101000SSS1000   bset    S
+1001010100001001   icall
+1001010000001001   ijmp 
+1001010111001000   lpm     ?
+1001000ddddd010+   lpm     r,z
+1001010111011000   elpm    ?
+1001000ddddd011+   elpm    r,z
+0000000000000000   nop  
+1001010100001000   ret  
+1001010100011000   reti 
+1001010110001000   sleep
+1001010110011000   break
+1001010110101000   wdr  
+1001010111101000   spm  
+000111rdddddrrrr   adc     r,r
+000011rdddddrrrr   add     r,r
+001000rdddddrrrr   and     r,r
+000101rdddddrrrr   cp      r,r
+000001rdddddrrrr   cpc     r,r
+000100rdddddrrrr   cpse    r,r
+001001rdddddrrrr   eor     r,r
+001011rdddddrrrr   mov     r,r
+100111rdddddrrrr   mul     r,r
+001010rdddddrrrr   or      r,r
+000010rdddddrrrr   sbc     r,r
+000110rdddddrrrr   sub     r,r
+001001rdddddrrrr   clr     r
+000011rdddddrrrr   lsl     r
+000111rdddddrrrr   rol     r
+001000rdddddrrrr   tst     r
+0111KKKKddddKKKK   andi    d,M
+0111KKKKddddKKKK   cbr     d,n
+1110KKKKddddKKKK   ldi     d,M
+11101111dddd1111   ser     d
+0110KKKKddddKKKK   ori     d,M
+0110KKKKddddKKKK   sbr     d,M
+0011KKKKddddKKKK   cpi     d,M
+0100KKKKddddKKKK   sbci    d,M
+0101KKKKddddKKKK   subi    d,M
+1111110rrrrr0sss   sbrc    r,s
+1111111rrrrr0sss   sbrs    r,s
+1111100ddddd0sss   bld     r,s
+1111101ddddd0sss   bst     r,s
+10110PPdddddPPPP   in      r,P
+10111PPrrrrrPPPP   out     P,r
+10010110KKddKKKK   adiw    w,K
+10010111KKddKKKK   sbiw    w,K
+10011000pppppsss   cbi     p,s
+10011010pppppsss   sbi     p,s
+10011001pppppsss   sbic    p,s
+10011011pppppsss   sbis    p,s
+111101lllllll000   brcc    l
+111100lllllll000   brcs    l
+111100lllllll001   breq    l
+111101lllllll100   brge    l
+111101lllllll101   brhc    l
+111100lllllll101   brhs    l
+111101lllllll111   brid    l
+111100lllllll111   brie    l
+111100lllllll000   brlo    l
+111100lllllll100   brlt    l
+111100lllllll010   brmi    l
+111101lllllll001   brne    l
+111101lllllll010   brpl    l
+111101lllllll000   brsh    l
+111101lllllll110   brtc    l
+111100lllllll110   brts    l
+111101lllllll011   brvc    l
+111100lllllll011   brvs    l
+111101lllllllsss   brbc    s,l
+111100lllllllsss   brbs    s,l
+1101LLLLLLLLLLLL   rcall   L
+1100LLLLLLLLLLLL   rjmp    L
+1001010hhhhh111h   call    h
+1001010hhhhh110h   jmp     h
+1001010rrrrr0101   asr     r
+1001010rrrrr0000   com     r
+1001010rrrrr1010   dec     r
+1001010rrrrr0011   inc     r
+1001010rrrrr0110   lsr     r
+1001010rrrrr0001   neg     r
+1001000rrrrr1111   pop     r
+1001001rrrrr1111   push    r
+1001010rrrrr0111   ror     r
+1001010rrrrr0010   swap    r
+00000001ddddrrrr   movw    v,v
+00000010ddddrrrr   muls    d,d
+000000110ddd0rrr   mulsu   a,a
+000000110ddd1rrr   fmul    a,a
+000000111ddd0rrr   fmuls   a,a
+000000111ddd1rrr   fmulsu  a,a
+1001001ddddd0000   sts     i,r
+1001000ddddd0000   lds     r,i
+10o0oo0dddddbooo   ldd     r,b
+100!000dddddee-+   ld      r,e
+10o0oo1rrrrrbooo   std     b,r
+100!001rrrrree-+   st      e,r
+1001010100011001   eicall  
+1001010000011001   eijmp   
+@end smallexample
diff --git a/gas/doc/c-bfin.texi b/gas/doc/c-bfin.texi
index dcf649a2b890..0b8ae1d9f3e4 100644
--- a/gas/doc/c-bfin.texi
+++ b/gas/doc/c-bfin.texi
@@ -97,9 +97,9 @@ The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
 normally contain data for manipulation.  These are abbreviated as 
 D-register or Dreg.  Data registers can be accessed as 32-bit registers
 or as two independent 16-bit registers.  The least significant 16 bits
-of each register is called the "low" half and is desginated with ".L"
+of each register is called the "low" half and is designated with ".L"
 following the register name.  The most significant 16 bits are called
-the "high" half and is designated with ".H". following the name.
+the "high" half and is designated with ".H" following the name.
 
 @smallexample
    R7.L, r2.h, r4.L, R0.H
diff --git a/gas/doc/c-cr16.texi b/gas/doc/c-cr16.texi
new file mode 100644
index 000000000000..4748d5679ec4
--- /dev/null
+++ b/gas/doc/c-cr16.texi
@@ -0,0 +1,80 @@
+@c Copyright 2007 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node CR16-Dependent
+@chapter CR16 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter CR16 Dependent Features
+@end ifclear
+
+@cindex CR16 support
+@menu
+* CR16 Operand Qualifiers::     CR16 Machine Operand Qualifiers
+@end menu
+
+@node CR16 Operand Qualifiers
+@section CR16 Operand Qualifiers
+@cindex CR16 Operand Qualifiers
+
+The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.  
+
+Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
+
+@table @code
+@item  s 
+- @code{Specifies expression operand type as small}
+@item  m 
+- @code{Specifies expression operand type as medium}
+@item  l 
+- @code{Specifies expression operand type as large}
+@item  c 
+- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
+@end table
+
+CR16 target operand qualifiers and its size (in bits):
+
+@table @samp
+@item Immediate Operand
+- s ---- 4 bits
+@item 
+- m ---- 16 bits, for movb and movw instructions.
+@item 
+- m ---- 20 bits, movd instructions.
+@item 
+- l ---- 32 bits
+
+@item Absolute Operand
+- s ---- Illegal specifier for this operand.
+@item  
+- m ---- 20 bits, movd instructions.
+
+@item Displacement Operand
+- s ---- 8 bits
+@item
+- m ---- 16 bits
+@item 
+- l ---- 24 bits
+@end table
+
+For example:
+@example
+1   @code{movw $_myfun@@c,r1}
+
+    This loads the address of _myfun, shifted right by 1, into r1.
+
+2   @code{movd $_myfun@@c,(r2,r1)}
+
+    This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
+                
+3   @code{_myfun_ptr:}
+    @code{.long _myfun@@c}
+    @code{loadd _myfun_ptr, (r1,r0)}
+    @code{jal (r1,r0)}
+
+    This .long directive, the address of _myfunc, shifted right by 1 at link time.
+@end example
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 81039c4dbe72..48b251a25fc0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -76,6 +76,49 @@ character, which means that it cannot be used in expressions.  The
 not disable @samp{/} at the beginning of a line starting a comment, or
 affect using @samp{#} for starting a comment.
 
+@cindex @samp{-march=} option, i386
+@cindex @samp{-march=} option, x86-64
+@item -march=@var{CPU}
+This option specifies an instruction set architecture for generating
+instructions.  The following architectures are recognized:
+@code{i8086},
+@code{i186},
+@code{i286},
+@code{i386},
+@code{i486},
+@code{i586},
+@code{i686},
+@code{pentium},
+@code{pentiumpro},
+@code{pentiumii},
+@code{pentiumiii},
+@code{pentium4},
+@code{prescott},
+@code{nocona},
+@code{core},
+@code{core2},
+@code{k6},
+@code{k6_2},
+@code{athlon},
+@code{sledgehammer},
+@code{opteron},
+@code{k8},
+@code{generic32} and
+@code{generic64}.
+
+This option only affects instructions generated by the assembler. The
+@code{.arch} directive will take precedent.
+
+@cindex @samp{-mtune=} option, i386
+@cindex @samp{-mtune=} option, x86-64
+@item -mtune=@var{CPU}
+This option specifies a processor to optimize for. When used in
+conjunction with the @option{-march} option, only instructions
+of the processor specified by the @option{-march} option will be
+generated.
+
+Valid @var{CPU} values are identical to @option{-march=@var{CPU}}.
+
 @end table
 
 @node i386-Syntax
@@ -604,7 +647,7 @@ then stores the result in the 4 byte location @samp{mem})
 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
 instructions for integer data), available on Intel's Pentium MMX
 processors and Pentium II processors, AMD's K6 and K6-2 processors,
-Cyrix' M2 processor, and probably others.  It also supports AMD's 3DNow!
+Cyrix' M2 processor, and probably others.  It also supports AMD's 3DNow!@:
 instruction set (SIMD instructions for 32-bit floating point data)
 available on AMD's K6-2 processor and possibly others in the future.
 
@@ -667,7 +710,7 @@ value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
 @end smallexample
 
 The same code in a 16-bit code section would generate the machine
-opcode bytes @samp{6a 04} (ie. without the operand size prefix), which
+opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
 is correct since the processor default operand size is assumed to be 16
 bits in a 16-bit code section.
 
@@ -709,8 +752,13 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
-@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
-@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
+@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
+@item @samp{amdfam10}
+@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8} 
+@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
+@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
+@item @samp{.sse4a} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock}
+@item @samp{.pacifica} @tab @samp{.svme} @tab @samp{.abm}
 @end multitable
 
 Apart from the warning, there are only two other effects on
diff --git a/gas/doc/c-i960.texi b/gas/doc/c-i960.texi
index 5dca1cf9c111..4d75bdfb8f7b 100644
--- a/gas/doc/c-i960.texi
+++ b/gas/doc/c-i960.texi
@@ -69,7 +69,7 @@ Label:  @var{BR}
 @end smallexample
 
 The counter following a branch records the number of times that branch
-was @emph{not} taken; the differenc between the two counters is the
+was @emph{not} taken; the difference between the two counters is the
 number of times the branch @emph{was} taken.
 
 @cindex @code{gbr960}, i960 postprocessor
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi
index 30cd355aede3..218ed250a018 100644
--- a/gas/doc/c-m32r.texi
+++ b/gas/doc/c-m32r.texi
@@ -65,7 +65,7 @@ configured.
 
 @item -EL
 @cindex @code{-EL} option, M32R
-This is a synonum for @emph{-little}.
+This is a synonym for @emph{-little}.
 
 @item -big
 @cindex @code{-big} option, M32R
@@ -110,7 +110,7 @@ implies @emph{-parallel}.
 Instructs @code{@value{AS}} to produce warning messages when
 questionable parallel instructions are encountered.  This option is
 enabled by default, but @code{@value{GCC}} disables it when it invokes
-@code{@value{AS}} directly.  Questionable instructions are those whoes
+@code{@value{AS}} directly.  Questionable instructions are those whose
 behaviour would be different if they were executed sequentially.  For
 example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
 different result from @samp{mv r1, r2 \n mv r3, r1} since the former
@@ -135,7 +135,7 @@ option.
 @item -ignore-parallel-conflicts
 @cindex @samp{-ignore-parallel-conflicts} option, M32RX
 This option tells the assembler's to stop checking parallel
-instructions for contraint violations.  This ability is provided for
+instructions for constraint violations.  This ability is provided for
 hardware vendors testing chip designs and should not be used under
 normal circumstances.
 
@@ -157,8 +157,8 @@ option.
 @item -warn-unmatched-high
 @cindex @samp{-warn-unmatched-high} option, M32R
 This option tells the assembler to produce a warning message if a
-@code{.high} pseudo op is encountered without a mathcing @code{.low}
-pseudo op.  The presence of such an unmatches pseudo op usually
+@code{.high} pseudo op is encountered without a matching @code{.low}
+pseudo op.  The presence of such an unmatched pseudo op usually
 indicates a programming error.
 
 @item -no-warn-unmatched-high
@@ -280,14 +280,14 @@ instructions in the M32R2 ISA as well as the ordinary M32R ISA.
 The directive performs a similar thing as the @emph{-little} command
 line option.  It tells the assembler to start producing little-endian
 code and data.  This option should be used with care as producing
-mixed-endian binary files is frought with danger.
+mixed-endian binary files is fraught with danger.
 
 @cindex @code{.big} directive, M32RX
 @item .big
 The directive performs a similar thing as the @emph{-big} command
 line option.  It tells the assembler to start producing big-endian
 code and data.  This option should be used with care as producing
-mixed-endian binary files is frought with danger.
+mixed-endian binary files is fraught with danger.
 
 @end table
 
@@ -328,7 +328,7 @@ instructions.
 
 @item unknown instruction @samp{...}
 This message is produced when the assembler encounters an instruction
-which it does not recognise.
+which it does not recognize.
 
 @item only the NOP instruction can be issued in parallel on the m32r
 This message is produced when the assembler encounters a parallel
diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi
index a41d6fcac07d..e79182386e9f 100644
--- a/gas/doc/c-m68hc11.texi
+++ b/gas/doc/c-m68hc11.texi
@@ -82,9 +82,9 @@ mode addressing. When it is used with the direct page mode,
 This option prevents @code{@value{AS}} from doing this, and the wrong
 usage of the direct page mode will raise an error.
 
-@cindex @samp{--short-branchs}
-@item --short-branchs
-The @samp{--short-branchs} option turns off the translation of
+@cindex @samp{--short-branches}
+@item --short-branches
+The @samp{--short-branches} option turns off the translation of
 relative branches into absolute branches when the branch offset is
 out of range. By default @code{@value{AS}} transforms the relative
 branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
@@ -93,15 +93,15 @@ branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
 an absolute branch when the offset is out of the -128 .. 127 range.
 In that case, the @samp{bsr} instruction is translated into a
 @samp{jsr}, the @samp{bra} instruction is translated into a
-@samp{jmp} and the conditional branchs instructions are inverted and
+@samp{jmp} and the conditional branches instructions are inverted and
 followed by a @samp{jmp}. This option disables these translations
 and @code{@value{AS}} will generate an error if a relative branch
 is out of range. This option does not affect the optimization
 associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
 
-@cindex @samp{--force-long-branchs}
-@item --force-long-branchs
-The @samp{--force-long-branchs} option forces the translation of
+@cindex @samp{--force-long-branches}
+@item --force-long-branches
+The @samp{--force-long-branches} option forces the translation of
 relative branches into absolute branches. This option does not affect
 the optimization associated to the @samp{jbra}, @samp{jbsr} and
 @samp{jbXX} pseudo opcodes. 
@@ -382,7 +382,7 @@ Certain pseudo opcodes are permitted for branch instructions.
 They expand to the shortest branch instruction that reach the
 target. Generally these mnemonics are made by prepending @samp{j} to
 the start of Motorola mnemonic. These pseudo opcodes are not affected
-by the @samp{--short-branchs} or @samp{--force-long-branchs} options.
+by the @samp{--short-branches} or @samp{--force-long-branches} options.
 
 The following table summarizes the pseudo-operations.
 
@@ -390,7 +390,7 @@ The following table summarizes the pseudo-operations.
                         Displacement Width
      +-------------------------------------------------------------+
      |                     Options                                 |
-     |    --short-branchs            --force-long-branchs          |
+     |    --short-branches           --force-long-branches         |
      +--------------------------+----------------------------------+
   Op |BYTE             WORD     | BYTE          WORD               |
      +--------------------------+----------------------------------+
diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi
index d4da2a1ea452..3176f94dcbd9 100644
--- a/gas/doc/c-m68k.texi
+++ b/gas/doc/c-m68k.texi
@@ -45,7 +45,8 @@ architectures are recognized:
 @code{cpu32},
 @code{isaa},
 @code{isaaplus},
-@code{isab} and
+@code{isab},
+@code{isac} and
 @code{cfv4e}.
 
 
@@ -284,7 +285,7 @@ The following addressing modes are understood:
 
 @item Address Register
 @samp{%a0} through @samp{%a7}@*
-@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer.  @code{%a6}
+@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer.  @code{%a6}
 is also known as @samp{%fp}, the Frame Pointer.
 
 @item Address Register Indirect
@@ -346,7 +347,7 @@ The following additional addressing modes are understood:
 @table @dfn
 @item Address Register Indirect
 @samp{(%a0)} through @samp{(%a7)}@* 
-@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer.  @code{%a6}
+@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer.  @code{%a6}
 is also known as @samp{%fp}, the Frame Pointer.
 
 @item Address Register Postincrement
@@ -445,11 +446,11 @@ This directive is identical to a @code{.space} directive.
 
 @cindex @code{arch} directive, M680x0
 @item .arch @var{name}
-Select the target architecture and extension features.  Valid valuse
+Select the target architecture and extension features.  Valid values
 for @var{name} are the same as for the @option{-march} command line
 option.  This directive cannot be specified after
 any instructions have been assembled.  If it is given multiple times,
-or in conjuction with the @option{-march} option, all uses must be for
+or in conjunction with the @option{-march} option, all uses must be for
 the same architecture and extension set.
 
 @cindex @code{cpu} directive, M680x0
@@ -458,7 +459,7 @@ Select the target cpu.  Valid valuse
 for @var{name} are the same as for the @option{-mcpu} command line
 option.  This directive cannot be specified after
 any instructions have been assembled.  If it is given multiple times,
-or in conjuction with the @option{-mopt} option, all uses must be for
+or in conjunction with the @option{-mopt} option, all uses must be for
 the same cpu.
 
 @end table
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 3c70ff29bc08..f92cb0098d55 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -60,6 +60,18 @@ little-endian output at run time (unlike the other @sc{gnu} development
 tools, which must be configured for one or the other).  Use @samp{-EB}
 to select big-endian output, and @samp{-EL} for little-endian.
 
+@item -KPIC
+@cindex PIC selection, MIPS
+@cindex @option{-KPIC} option, MIPS
+Generate SVR4-style PIC.  This option tells the assembler to generate
+SVR4-style position-independent macro expansions.  It also tells the
+assembler to mark the output file as PIC.
+
+@item -mvxworks-pic
+@cindex @option{-mvxworks-pic} option, MIPS
+Generate VxWorks PIC.  This option tells the assembler to generate
+VxWorks-style position-independent macro expansions.
+
 @cindex MIPS architecture options
 @item -mips1
 @itemx -mips2
@@ -91,21 +103,38 @@ flags force a certain group of registers to be treated as 32 bits wide at
 all times.  @samp{-mgp32} controls the size of general-purpose registers
 and @samp{-mfp32} controls the size of floating-point registers.
 
+The @code{.set gp=32} and @code{.set fp=32} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
+
 On some MIPS variants there is a 32-bit mode flag; when this flag is
 set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only
 save the 32-bit registers on a context switch, so it is essential never
 to use the 64-bit registers.
 
 @item -mgp64
-Assume that 64-bit general purpose registers are available.  This is
-provided in the interests of symmetry with -gp32.
+@itemx -mfp64
+Assume that 64-bit registers are available.  This is provided in the
+interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
+
+The @code{.set gp=64} and @code{.set fp=64} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
 
 @item -mips16
 @itemx -no-mips16
 Generate code for the MIPS 16 processor.  This is equivalent to putting
-@samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
+@code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -msmartmips
+@itemx -mno-smartmips
+Enables the SmartMIPS extensions to the MIPS32 instruction set, which
+provides a number of new instructions which target smartcard and
+cryptographic applications.  This is equivalent to putting
+@code{.set smartmips} at the start of the assembly file.
+@samp{-mno-smartmips} turns off this option.
+
 @item -mips3d
 @itemx -no-mips3d
 Generate code for the MIPS-3D Application Specific Extension.
@@ -120,10 +149,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
@@ -202,8 +238,34 @@ rm7000,
 rm9000,
 10000,
 12000,
-mips32-4k,
-sb1
+4kc,
+4km,
+4kp,
+4ksc,
+4kec,
+4kem,
+4kep,
+4ksd,
+m4k,
+m4kp,
+24kc,
+24kf,
+24kx,
+24kec,
+24kef,
+24kex,
+34kc,
+34kf,
+34kx,
+74kc,
+74kf,
+74kx,
+5kc,
+5kf,
+20kc,
+25kf,
+sb1,
+sb1a
 @end quotation
 
 @item -mtune=@var{cpu}
@@ -391,13 +453,21 @@ assembly.  @code{.set mips@var{n}} affects not only which instructions
 are permitted, but also how certain macros are expanded.  @code{.set
 mips0} restores the @sc{isa} level to its original level: either the
 level you selected with command line options, or the default for your
-configuration.  You can use this feature to permit specific @sc{r4000}
+configuration.  You can use this feature to permit specific @sc{mips3}
 instructions while assembling in 32 bit mode.  Use this directive with
 care!
 
-The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
+@cindex MIPS CPU override
+@kindex @code{.set arch=@var{cpu}}
+The @code{.set arch=@var{cpu}} directive provides even finer control.
+It changes the effective CPU target and allows the assembler to use
+instructions specific to a particular CPU.  All CPUs supported by the
+@samp{-march} command line option are also selectable by this directive.
+The original value is restored by @code{.set arch=default}.
+
+The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
 in which it will assemble instructions for the MIPS 16 processor.  Use
-@samp{.set nomips16} to return to normal 32 bit mode.
+@code{.set nomips16} to return to normal 32 bit mode.
 
 Traditional @sc{mips} assemblers do not support this directive.
 
@@ -407,10 +477,10 @@ Traditional @sc{mips} assemblers do not support this directive.
 @kindex @code{.set autoextend}
 @kindex @code{.set noautoextend}
 By default, MIPS 16 instructions are automatically extended to 32 bits
-when necessary.  The directive @samp{.set noautoextend} will turn this
-off.  When @samp{.set noautoextend} is in effect, any 32 bit instruction
-must be explicitly extended with the @samp{.e} modifier (e.g.,
-@samp{li.e $4,1000}).  The directive @samp{.set autoextend} may be used
+when necessary.  The directive @code{.set noautoextend} will turn this
+off.  When @code{.set noautoextend} is in effect, any 32 bit instruction
+must be explicitly extended with the @code{.e} modifier (e.g.,
+@code{li.e $4,1000}).  The directive @code{.set autoextend} may be used
 to once again automatically extend instructions when necessary.
 
 This directive is only meaningful when in MIPS 16 mode.  Traditional
@@ -455,6 +525,15 @@ from the MIPS-3D Application Specific Extension from that point on
 in the assembly.  The @code{.set nomips3d} directive prevents MIPS-3D
 instructions from being accepted.
 
+@cindex SmartMIPS instruction generation override
+@kindex @code{.set smartmips}
+@kindex @code{.set nosmartmips}
+The directive @code{.set smartmips} makes the assembler accept
+instructions from the SmartMIPS Application Specific Extension to the
+MIPS32 @sc{isa} from that point on in the assembly.  The
+@code{.set nosmartmips} directive prevents SmartMIPS instructions from
+being accepted.
+
 @cindex MIPS MDMX instruction generation override
 @kindex @code{.set mdmx}
 @kindex @code{.set nomdmx}
@@ -463,13 +542,22 @@ from the MDMX Application Specific Extension from that point on
 in the assembly.  The @code{.set nomdmx} directive prevents MDMX
 instructions from being accepted.
 
-@cindex MIPS DSP instruction generation override
+@cindex MIPS DSP Release 1 instruction generation override
 @kindex @code{.set dsp}
 @kindex @code{.set nodsp}
 The directive @code{.set dsp} makes the assembler accept instructions
-from the DSP Application Specific Extension from that point on
-in the assembly.  The @code{.set nodsp} directive prevents DSP
-instructions from being accepted.
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly.  The @code{.set nodsp} directive prevents DSP
+Release 1 instructions from being accepted.
+
+@cindex MIPS DSP Release 2 instruction generation override
+@kindex @code{.set dspr2}
+@kindex @code{.set nodspr2}
+The directive @code{.set dspr2} makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly.  This dirctive implies @code{.set dsp}.  The
+@code{.set nodspr2} directive prevents DSP Release 2 instructions from
+being accepted.
 
 @cindex MIPS MT instruction generation override
 @kindex @code{.set mt}
diff --git a/gas/doc/c-mmix.texi b/gas/doc/c-mmix.texi
index 8e47fa4a9799..257e3a69d8a6 100644
--- a/gas/doc/c-mmix.texi
+++ b/gas/doc/c-mmix.texi
@@ -530,7 +530,7 @@ Operand syntax is a bit stricter with @code{@value{AS}} than
 must write @code{addu $1,$2,3}.
 
 You can't LOC to a lower address than those already visited
-(i.e. ``backwards'').
+(i.e., ``backwards'').
 
 A LOC directive must come before any emitted code.
 
diff --git a/gas/doc/c-pdp11.texi b/gas/doc/c-pdp11.texi
index d714b28343a6..78f2cf41f635 100644
--- a/gas/doc/c-pdp11.texi
+++ b/gas/doc/c-pdp11.texi
@@ -311,7 +311,7 @@ an immediate constants, while in BSD syntax the character for this
 purpose is @code{$}.
 
 @cindex PDP-11 general-purpose register syntax
-eneral-purpose registers are named @code{r0} through @code{r7}.
+general-purpose registers are named @code{r0} through @code{r7}.
 Mnemonic alternatives for @code{r6} and @code{r7} are @code{sp} and
 @code{pc}, respectively.
 
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index 4c9c096c055e..a41e1dd5f9ab 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -1,4 +1,4 @@
-@c Copyright 2001, 2002, 2003, 2005
+@c Copyright 2001, 2002, 2003, 2005, 2006
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -58,6 +58,12 @@ Generate code for PowerPC 7400/7410/7450/7455.
 @item -mppc64, -m620
 Generate code for PowerPC 620/625/630.
 
+@item -me500, -me500x2
+Generate code for Motorola e500 core complex.
+
+@item -mspe
+Generate code for Motorola SPE instructions.
+
 @item -mppc64bridge
 Generate code for PowerPC 64, including bridge insns.
 
@@ -79,6 +85,12 @@ Generate code for Power4 architecture.
 @item -mpower5
 Generate code for Power5 architecture.
 
+@item -mpower6
+Generate code for Power6 architecture.
+
+@item -mcell
+Generate code for Cell Broadband Engine architecture.
+
 @item -mcom
 Generate code Power/PowerPC common instructions.
 
@@ -92,10 +104,10 @@ Allow symbolic names for registers.
 Do not allow symbolic names for registers.
 
 @item -mrelocatable
-Support for GCC's -mrelocatble option.
+Support for GCC's -mrelocatable option.
 
 @item -mrelocatable-lib
-Support for GCC's -mrelocatble-lib option.
+Support for GCC's -mrelocatable-lib option.
 
 @item -memb
 Set PPC_EMB bit in ELF flags.
diff --git a/gas/doc/c-tic54x.texi b/gas/doc/c-tic54x.texi
index 374def39e633..85b2fdad1517 100644
--- a/gas/doc/c-tic54x.texi
+++ b/gas/doc/c-tic54x.texi
@@ -32,7 +32,7 @@
 
 @cindex options, TIC54X
 @cindex TIC54X options
-The TMS320C54x version of @code{@value{AS}} has a few machine-dependent options.
+The TMS320C54X version of @code{@value{AS}} has a few machine-dependent options.
 
 @cindex @samp{-mfar-mode} option, far-mode
 @cindex @samp{-mf} option, far-mode
@@ -450,7 +450,7 @@ points to the word that contains the specified field.
 @itemx .def @var{symbol} [,...,@var{symbol_n}]
 @itemx .ref @var{symbol} [,...,@var{symbol_n}]
 @code{.def} nominally identifies a symbol defined in the current file
-and availalbe to other files.  @code{.ref} identifies a symbol used in
+and available to other files.  @code{.ref} identifies a symbol used in
 the current file but defined elsewhere.  Both map to the standard
 @code{.global} directive.
 
@@ -685,7 +685,7 @@ values are accepted, the op is ignored.
 
 @cindex TIC54X-specific macros
 @cindex macros, TIC54X
-Macros do not require explicit dereferencing of arguments (i.e. \ARG).  
+Macros do not require explicit dereferencing of arguments (i.e., \ARG).  
 
 During macro expansion, the macro parameters are converted to subsyms.
 If the number of arguments passed the macro invocation exceeds the
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 445be057ef35..d899d5df2a22 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -267,7 +267,7 @@ the immediate operand field of the given instruction.  For example:
 
 computes the difference between the address of labels 'here' and
 'there', takes the upper 16 bits of this difference, shifts it down 16
-bits and then mutliplies it by the lower 16 bits in register 5, putting
+bits and then multiplies it by the lower 16 bits in register 5, putting
 the result into register 6. 
 
 @cindex @code{lo} pseudo-op, V850
diff --git a/gas/doc/c-xtensa.texi b/gas/doc/c-xtensa.texi
index 33035ad8b483..0ef8996e028e 100644
--- a/gas/doc/c-xtensa.texi
+++ b/gas/doc/c-xtensa.texi
@@ -37,8 +37,8 @@ special options:
 @kindex --text-section-literals
 @kindex --no-text-section-literals
 Control the treatment of literal pools.  The default is
-@samp{--no-@-text-@-section-@-literals}, which places literals in a
-separate section in the output file.  This allows the literal pool to be
+@samp{--no-@-text-@-section-@-literals}, which places literals in
+separate sections in the output file.  This allows the literal pool to be
 placed in a data RAM/ROM.  With @samp{--text-@-section-@-literals}, the
 literals are interspersed in the text section in order to keep them as
 close as possible to their references.  This may be necessary for large
@@ -46,6 +46,7 @@ assembly files, where the literals would otherwise be out of range of the
 @code{L32R} instructions in the text section.  These options only affect
 literals referenced via PC-relative @code{L32R} instructions; literals
 for absolute mode @code{L32R} instructions are handled separately.
+@xref{Literal Directive, ,literal}.
 
 @item --absolute-literals | --no-absolute-literals
 @kindex --absolute-literals
@@ -115,13 +116,17 @@ instruction, are specified by enclosing the bundled opcodes inside
 braces:
 
 @smallexample
+@group
 @{
 [@var{format}]
 @var{opcode0} [@var{operands}]
+@end group
 @var{opcode1} [@var{operands}]
+@group
 @var{opcode2} [@var{operands}]
 @dots{}
 @}
+@end group
 @end smallexample
 
 The opcodes in a FLIX instruction are listed in the same order as the
@@ -236,10 +241,8 @@ density option, the same assembly code will then work without modification.
 @node Xtensa Automatic Alignment
 @subsection Automatic Instruction Alignment
 @cindex alignment of @code{LOOP} instructions
-@cindex alignment of @code{ENTRY} instructions
 @cindex alignment of branch targets
 @cindex @code{LOOP} instructions, alignment
-@cindex @code{ENTRY} instructions, alignment
 @cindex branch target alignment
 
 The Xtensa assembler will automatically align certain instructions, both
@@ -282,11 +285,9 @@ different fetch widths, the assembler conservatively assumes a 32-bit
 fetch width when aligning @code{LOOP} instructions (except if the first
 instruction in the loop is a 64-bit instruction).
 
-Similarly, the @code{ENTRY} instruction must be aligned on a 0 mod 4
-byte boundary.  The assembler satisfies this requirement by inserting
-zero bytes when required.  In addition, labels immediately preceding the
-@code{ENTRY} instruction will be moved to the newly aligned instruction
-location.
+Previous versions of the assembler automatically aligned @code{ENTRY}
+instructions to 4-byte boundaries, but that alignment is now the
+programmer's responsibility.
 
 @node Xtensa Relaxation
 @section Xtensa Relaxation
@@ -325,9 +326,11 @@ replace the branch with a branch around a jump.  For example,
 may result in:
 
 @smallexample
+@group
     bnez.n  a2, M
     j L
 M:
+@end group
 @end smallexample
 
 (The @code{BNEZ.N} instruction would be used in this example only if the
@@ -369,9 +372,11 @@ and then using a @code{CALLX} instruction.  So, for example:
 might be relaxed to:
 
 @smallexample
+@group
     .literal .L1, func
     l32r    a8, .L1
     callx8  a8
+@end group
 @end smallexample
 
 Because the addresses of targets of function calls are not generally
@@ -412,8 +417,10 @@ materialized with @code{L32R} instructions.  Thus:
 is assembled into the following machine code:
 
 @smallexample
+@group
     .literal .L1, 100000
     l32r a0, .L1
+@end group
 @end smallexample
 
 @cindex @code{L8UI} instructions, relaxation
@@ -428,7 +435,7 @@ The @code{L8UI} machine instruction can only be used with immediate
 offsets in the range from 0 to 255. The @code{L16SI} and @code{L16UI}
 machine instructions can only be used with offsets from 0 to 510.  The
 @code{L32I} machine instruction can only be used with offsets from 0 to
-1020.  A load offset outside these ranges can be materalized with
+1020.  A load offset outside these ranges can be materialized with
 an @code{L32R} instruction if the destination register of the load
 is different than the source address register.  For example:
 
@@ -439,10 +446,14 @@ is different than the source address register.  For example:
 is translated to:
 
 @smallexample
+@group
     .literal .L1, 2040
     l32r a1, .L1
+@end group
+@group
     addi a1, a0, a1
     l32i a1, a1, 0
+@end group
 @end smallexample
 
 @noindent
@@ -466,22 +477,30 @@ with a literal allocated from the literal pool.
 For example:
 
 @smallexample
+@group
     addi    a5, a6, 0
     addi    a5, a6, 512
+@end group
+@group
     addi    a5, a6, 513
     addi    a5, a6, 50000
+@end group
 @end smallexample
 
 is assembled into the following:
 
 @smallexample
+@group
     .literal .L1, 50000
     mov.n   a5, a6
+@end group
     addmi   a5, a6, 0x200
     addmi   a5, a6, 0x200
     addi    a5, a5, 1
+@group
     l32r    a5, .L1
     add     a5, a6, a5
+@end group
 @end smallexample
 
 @node Xtensa Directives
@@ -489,12 +508,14 @@ is assembled into the following:
 @cindex Xtensa directives
 @cindex directives, Xtensa
 
-The Xtensa assember supports a region-based directive syntax:
+The Xtensa assembler supports a region-based directive syntax:
 
 @smallexample
+@group
     .begin @var{directive} [@var{options}]
     @dots{}
     .end @var{directive}
+@end group
 @end smallexample
 
 All the Xtensa-specific directives that apply to a region of code use
@@ -508,13 +529,17 @@ change the state of the directive without having to be aware of its
 outer state.  For example, consider:
 
 @smallexample
+@group
     .begin no-transform
 L:  add a0, a1, a2
+@end group
     .begin transform
 M:  add a0, a1, a2
     .end transform
+@group
 N:  add a0, a1, a2
     .end no-transform
+@end group
 @end smallexample
 
 The @code{ADD} opcodes at @code{L} and @code{N} in the outer
@@ -545,8 +570,10 @@ The @code{schedule} directive is recognized only for compatibility with
 Tensilica's assembler.
 
 @smallexample
+@group
     .begin [no-]schedule
     .end [no-]schedule
+@end group
 @end smallexample
 
 This directive is ignored and has no effect on @command{@value{AS}}.
@@ -560,8 +587,10 @@ The @code{longcalls} directive enables or disables function call
 relaxation.  @xref{Xtensa Call Relaxation, ,Function Call Relaxation}.
 
 @smallexample
+@group
     .begin [no-]longcalls
     .end [no-]longcalls
+@end group
 @end smallexample
 
 Call relaxation is disabled by default unless the @samp{--longcalls}
@@ -578,8 +607,10 @@ including relaxation (@pxref{Xtensa Relaxation, ,Xtensa Relaxation}) and
 optimization (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}).
 
 @smallexample
+@group
     .begin [no-]transform
     .end [no-]transform
+@end group
 @end smallexample
 
 Transformations are enabled by default unless the @samp{--no-transform}
@@ -607,9 +638,11 @@ the literal data in the most appropriate place and possibly to combine
 identical literals.  For example, the code:
 
 @smallexample
+@group
     entry sp, 40
     .literal .L1, sym
     l32r    a4, .L1
+@end group
 @end smallexample
 
 can be used to load a pointer to the symbol @code{sym} into register
@@ -617,13 +650,14 @@ can be used to load a pointer to the symbol @code{sym} into register
 @code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
 the data in a literal pool.
 
-Literal pools for absolute mode @code{L32R} instructions
-(@pxref{Absolute Literals Directive}) are placed in a separate
-@code{.lit4} section.  By default literal pools for PC-relative mode
-@code{L32R} instructions are placed in a separate @code{.literal}
-section; however, when using the @samp{--text-@-section-@-literals}
+Literal pools are placed by default in separate literal sections;
+however, when using the @samp{--text-@-section-@-literals}
 option (@pxref{Xtensa Options, ,Command Line Options}), the literal
-pools are placed in the current section.  These text section literal
+pools for PC-relative mode @code{L32R} instructions
+are placed in the current section.@footnote{Literals for the
+@code{.init} and @code{.fini} sections are always placed in separate
+sections, even when @samp{--text-@-section-@-literals} is enabled.}
+These text section literal
 pools are created automatically before @code{ENTRY} instructions and
 manually after @samp{.literal_position} directives (@pxref{Literal
 Position Directive, ,literal_position}).  If there are no preceding
@@ -631,6 +665,46 @@ Position Directive, ,literal_position}).  If there are no preceding
 must be used to place the text section literal pools; otherwise,
 @command{@value{AS}} will report an error.
 
+When literals are placed in separate sections, the literal section names
+are derived from the names of the sections where the literals are
+defined.  The base literal section names are @code{.literal} for
+PC-relative mode @code{L32R} instructions and @code{.lit4} for absolute
+mode @code{L32R} instructions (@pxref{Absolute Literals Directive,
+,absolute-literals}).  These base names are used for literals defined in
+the default @code{.text} section.  For literals defined in other
+sections or within the scope of a @code{literal_prefix} directive
+(@pxref{Literal Prefix Directive, ,literal_prefix}), the following rules
+determine the literal section name:
+
+@enumerate
+@item
+If the current section is a member of a section group, the literal
+section name includes the group name as a suffix to the base
+@code{.literal} or @code{.lit4} name, with a period to separate the base
+name and group name.  The literal section is also made a member of the
+group.
+
+@item
+If the current section name (or @code{literal_prefix} value) begins with
+``@code{.gnu.linkonce.@var{kind}.}'', the literal section name is formed
+by replacing ``@code{.@var{kind}}'' with the base @code{.literal} or
+@code{.lit4} name.  For example, for literals defined in a section named
+@code{.gnu.linkonce.t.func}, the literal section will be
+@code{.gnu.linkonce.literal.func} or @code{.gnu.linkonce.lit4.func}.
+
+@item
+If the current section name (or @code{literal_prefix} value) ends with
+@code{.text}, the literal section name is formed by replacing that
+suffix with the base @code{.literal} or @code{.lit4} name.  For example,
+for literals defined in a section named @code{.iram0.text}, the literal
+section will be @code{.iram0.literal} or @code{.iram0.lit4}.
+
+@item
+If none of the preceding conditions apply, the literal section name is
+formed by adding the base @code{.literal} or @code{.lit4} name as a
+suffix to the current section name (or @code{literal_prefix} value).
+@end enumerate
+
 @node Literal Position Directive
 @subsection literal_position
 @cindex @code{literal_position} directive
@@ -666,58 +740,43 @@ for @samp{M} will automatically be aligned correctly and is placed after
 the unconditional jump.
 
 @smallexample
+@group
     .global M
 code_start:
+@end group
     j continue
     .literal_position
     .align 4
+@group
 continue:
     movi    a4, M
+@end group
 @end smallexample
 
 @node Literal Prefix Directive
 @subsection literal_prefix
 @cindex @code{literal_prefix} directive
 
-The @code{literal_prefix} directive allows you to specify different
-sections to hold literals from different portions of an assembly file.
-With this directive, a single assembly file can be used to generate code
-into multiple sections, including literals generated by the assembler.
+The @code{literal_prefix} directive allows you to override the default
+literal section names, which are derived from the names of the sections
+where the literals are defined.
 
 @smallexample
+@group
     .begin literal_prefix [@var{name}]
     .end literal_prefix
+@end group
 @end smallexample
 
-By default the assembler places literal pools in sections separate from
-the instructions, using the default literal section names of
-@code{.literal} for PC-relative mode @code{L32R} instructions and
-@code{.lit4} for absolute mode @code{L32R} instructions (@pxref{Absolute
-Literals Directive}).  The @code{literal_prefix} directive causes
-different literal sections to be used for the code inside the delimited
-region.  The new literal sections are determined by including @var{name}
-as a prefix to the default literal section names.  If the @var{name}
+For literals defined within the delimited region, the literal section
+names are derived from the @var{name} argument instead of the name of
+the current section.  The rules used to derive the literal section names
+do not change.  @xref{Literal Directive, ,literal}.  If the @var{name}
 argument is omitted, the literal sections revert to the defaults.  This
 directive has no effect when using the
 @samp{--text-@-section-@-literals} option (@pxref{Xtensa Options,
 ,Command Line Options}).
 
-Except for two special cases, the assembler determines the new literal
-sections by simply prepending @var{name} to the default section names,
-resulting in @code{@var{name}.literal} and @code{@var{name}.lit4}
-sections.  The @code{literal_prefix} directive is often used with the
-name of the current text section as the prefix argument.  To facilitate
-this usage, the assembler uses special case rules when it recognizes
-@var{name} as a text section name.  First, if @var{name} ends with
-@code{.text}, that suffix is not included in the literal section name.
-For example, if @var{name} is @code{.iram0.text}, then the literal
-sections will be @code{.iram0.literal} and @code{.iram0.lit4}.  Second,
-if @var{name} begins with @code{.gnu.linkonce.t.}, then the literal
-section names are formed by replacing the @code{.t} substring with
-@code{.literal} and @code{.lit4}.  For example, if @var{name} is
-@code{.gnu.linkonce.t.func}, the literal sections will be
-@code{.gnu.linkonce.literal.func} and @code{.gnu.linkonce.lit4.func}.
-
 @node Absolute Literals Directive
 @subsection absolute-literals
 @cindex @code{absolute-literals} directive
@@ -729,8 +788,10 @@ instructions.  These are relevant only for Xtensa configurations that
 include the absolute addressing option for @code{L32R} instructions.
 
 @smallexample
+@group
     .begin [no-]absolute-literals
     .end [no-]absolute-literals
+@end group
 @end smallexample
 
 These directives do not change the @code{L32R} mode---they only cause
diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
index 76e8410840a4..c52268a8cfbb 100644
--- a/gas/doc/c-z80.texi
+++ b/gas/doc/c-z80.texi
@@ -59,7 +59,7 @@ Treat undocumented z80-instructions that do not work on R800 as errors.
 @item -r800
 Produce code for the R800 processor. The assembler does not support
 undocumented instructions for the R800.
-In line with common practice, @code{@value{AS}} uses Z80 instriction names
+In line with common practice, @code{@value{AS}} uses Z80 instruction names
 for the R800 processor, as far as they exist.
 @end table
 
@@ -105,7 +105,7 @@ A backslash @samp{\} is an ordinary character for the Z80 assembler.
 @cindex single quote, Z80
 @cindex Z80 '
 The single quote @samp{'} must be followed by a closing quote. If there
-is one character inbetween, it is a character constant, otherwise it is
+is one character in between, it is a character constant, otherwise it is
 a string constant.
 
 @node Z80-Regs
@@ -114,7 +114,7 @@ a string constant.
 @cindex register names, Z80
 
 The registers are referred to with the letters assigned to them by
-Zilog. In addition @command{@value{AS}} recognises @samp{ixl} and 
+Zilog. In addition @command{@value{AS}} recognizes @samp{ixl} and 
 @samp{ixh} as the least and most significant octet in @samp{ix}, and
 similarly @samp{iyl} and  @samp{iyh} as parts of @samp{iy}. 
 
@@ -171,7 +171,7 @@ overflow.
 @item ds @var{count}[, @var{value}]
 @itemx defs @var{count}[, @var{value}]
 @c Synonyms for @code{ds.b}, 
-@c which should have been described elsewhre
+@c which should have been described elsewhere
 Fill @var{count} bytes in the object file with @var{value}, if
 @var{value} is omitted it defaults to zero.
 
@@ -188,7 +188,7 @@ This is a normal instruction on Z80, and not an assembler directive.
 A synonym for @xref{Section}, no second argument should be given. 
 @ignore
 
-The following attributes will possibly be recognised in the future
+The following attributes will possibly be recognized in the future
 @table @code
 @item abs
 The section is to be absolute. @code{@value{AS}} will issue an error
@@ -212,7 +212,7 @@ The section is marked as read only.
 
 @node Z80 Opcodes
 @section Opcodes
-In line with commmon practice Z80 mnonics are used for both the Z80 and
+In line with common practice, Z80 mnemonics are used for both the Z80 and
 the R800. 
 
 In many instructions it is possible to use one of the half index
diff --git a/gas/doc/gasver.texi b/gas/doc/gasver.texi
deleted file mode 100644
index 11d1801d6e65..000000000000
--- a/gas/doc/gasver.texi
+++ /dev/null
@@ -1 +0,0 @@
-@set VERSION 2.17
diff --git a/gas/doc/internals.texi b/gas/doc/internals.texi
index dffdb1e04fa9..c63a2dbd7705 100644
--- a/gas/doc/internals.texi
+++ b/gas/doc/internals.texi
@@ -1,6 +1,6 @@
 \input texinfo
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004, 2005
+@c  2001, 2002, 2003, 2004, 2005, 2006
 @c  Free Software Foundation, Inc.
 @setfilename internals.info
 @node Top
@@ -838,7 +838,7 @@ GAS will call @code{md_parse_option} whenever @code{getopt} returns an
 unrecognized code, presumably indicating a special code value which appears in
 @code{md_longopts}.  This function should return non-zero if it handled the
 option and zero otherwise.  There is no need to print a message about an option
-not being recognised.  This will be handled by the generic code.
+not being recognized.  This will be handled by the generic code.
 
 GAS will call @code{md_show_usage} when a usage message is printed; it should
 print a description of the machine specific options. @code{md_after_pase_args},
@@ -891,7 +891,7 @@ If this macro is defined, GAS will use it instead of @code{comment_chars}.
 @cindex tc_symbol_chars
 If this macro is defined, it is a pointer to a null terminated list of
 characters which may appear in an operand.  GAS already assumes that all
-alphanumberic characters, and @samp{$}, @samp{.}, and @samp{_} may appear in an
+alphanumeric characters, and @samp{$}, @samp{.}, and @samp{_} may appear in an
 operand (see @samp{symbol_chars} in @file{app.c}).  This macro may be defined
 to treat additional characters as appearing in an operand.  This affects the
 way in which GAS removes whitespace before passing the string to
@@ -1279,7 +1279,7 @@ absolute symbol.  If undefined, @code{TC_FORCE_RELOCATION} will be used.
 @cindex TC_FORCE_RELOCATION_LOCAL
 Like @code{TC_FORCE_RELOCATION}, but used only for fixup expressions against a
 symbol in the current section.  If undefined, fixups that are not
-@code{fx_pcrel} or @code{fx_plt} or for which @code{TC_FORCE_RELOCATION}
+@code{fx_pcrel} or for which @code{TC_FORCE_RELOCATION}
 returns non-zero, will emit relocs.
 
 @item TC_FORCE_RELOCATION_SUB_SAME (@var{fix}, @var{seg})
@@ -1609,7 +1609,7 @@ symbol's flags.
 
 @item obj_clear_weak_hook
 @cindex obj_clear_weak_hook
-If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after clearning
+If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after cleaning
 the @code{weakrefd} flag, but before modifying any other flags.
 
 @item obj_frob_file
@@ -1844,10 +1844,6 @@ Returns non-zero if any warnings or errors, respectively, have been printed
 during this invocation.
 @end deftypefun
 
-@deftypefun @{@} void as_perror (const char *@var{gripe}, const char *@var{filename})
-Displays a BFD or system error, then clears the error status.
-@end deftypefun
-
 @deftypefun  @{@} void as_tsktsk (const char *@var{format}, ...)
 @deftypefunx @{@} void as_warn (const char *@var{format}, ...)
 @deftypefunx @{@} void as_bad (const char *@var{format}, ...)
diff --git a/gas/dw2gencfi.c b/gas/dw2gencfi.c
index bfa5d5cf45a6..97e12377e76b 100644
--- a/gas/dw2gencfi.c
+++ b/gas/dw2gencfi.c
@@ -21,6 +21,7 @@
 
 #include "as.h"
 #include "dw2gencfi.h"
+#include "subsegs.h"
 
 
 /* We re-use DWARF2_LINE_MIN_INSN_LENGTH for the code alignment field
@@ -87,6 +88,10 @@ struct fde_entry
   symbolS *end_address;
   struct cfi_insn_data *data;
   struct cfi_insn_data **last;
+  unsigned char per_encoding;
+  unsigned char lsda_encoding;
+  expressionS personality;
+  expressionS lsda;
   unsigned int return_column;
   unsigned int signal_frame;
 };
@@ -97,15 +102,13 @@ struct cie_entry
   symbolS *start_address;
   unsigned int return_column;
   unsigned int signal_frame;
+  unsigned char per_encoding;
+  unsigned char lsda_encoding;
+  expressionS personality;
   struct cfi_insn_data *first, *last;
 };
 
 
-/* Current open FDE entry.  */
-static struct fde_entry *cur_fde_data;
-static symbolS *last_address;
-static offsetT cur_cfa_offset;
-
 /* List of FDE entries.  */
 static struct fde_entry *all_fde_data;
 static struct fde_entry **last_fde_data = &all_fde_data;
@@ -120,7 +123,14 @@ struct cfa_save_data
   offsetT cfa_offset;
 };
 
-static struct cfa_save_data *cfa_save_stack;
+/* Current open FDE entry.  */
+struct frch_cfi_data
+{
+  struct fde_entry *cur_fde_data;
+  symbolS *last_address;
+  offsetT cur_cfa_offset;
+  struct cfa_save_data *cfa_save_stack;
+};
 
 /* Construct a new FDE structure and add it to the end of the fde list.  */
 
@@ -129,12 +139,15 @@ alloc_fde_entry (void)
 {
   struct fde_entry *fde = xcalloc (1, sizeof (struct fde_entry));
 
-  cur_fde_data = fde;
+  frchain_now->frch_cfi_data = xcalloc (1, sizeof (struct frch_cfi_data));
+  frchain_now->frch_cfi_data->cur_fde_data = fde;
   *last_fde_data = fde;
   last_fde_data = &fde->next;
 
   fde->last = &fde->data;
   fde->return_column = DWARF2_DEFAULT_RETURN_COLUMN;
+  fde->per_encoding = DW_EH_PE_omit;
+  fde->lsda_encoding = DW_EH_PE_omit;
 
   return fde;
 }
@@ -149,6 +162,7 @@ static struct cfi_insn_data *
 alloc_cfi_insn_data (void)
 {
   struct cfi_insn_data *insn = xcalloc (1, sizeof (struct cfi_insn_data));
+  struct fde_entry *cur_fde_data = frchain_now->frch_cfi_data->cur_fde_data;
 
   *cur_fde_data->last = insn;
   cur_fde_data->last = &insn->next;
@@ -163,7 +177,7 @@ cfi_new_fde (symbolS *label)
 {
   struct fde_entry *fde = alloc_fde_entry ();
   fde->start_address = label;
-  last_address = label;
+  frchain_now->frch_cfi_data->last_address = label;
 }
 
 /* End the currently open FDE.  */
@@ -171,8 +185,9 @@ cfi_new_fde (symbolS *label)
 void 
 cfi_end_fde (symbolS *label)
 {
-  cur_fde_data->end_address = label;
-  cur_fde_data = NULL;
+  frchain_now->frch_cfi_data->cur_fde_data->end_address = label;
+  free (frchain_now->frch_cfi_data);
+  frchain_now->frch_cfi_data = NULL;
 }
 
 /* Set the return column for the current FDE.  */
@@ -180,7 +195,7 @@ cfi_end_fde (symbolS *label)
 void
 cfi_set_return_column (unsigned regno)
 {
-  cur_fde_data->return_column = regno;
+  frchain_now->frch_cfi_data->cur_fde_data->return_column = regno;
 }
 
 /* Universal functions to store new instructions.  */
@@ -239,10 +254,10 @@ cfi_add_advance_loc (symbolS *label)
   struct cfi_insn_data *insn = alloc_cfi_insn_data ();
 
   insn->insn = DW_CFA_advance_loc;
-  insn->u.ll.lab1 = last_address;
+  insn->u.ll.lab1 = frchain_now->frch_cfi_data->last_address;
   insn->u.ll.lab2 = label;
 
-  last_address = label;
+  frchain_now->frch_cfi_data->last_address = label;
 }
 
 /* Add a DW_CFA_offset record to the CFI data.  */
@@ -252,6 +267,7 @@ cfi_add_CFA_offset (unsigned regno, offsetT offset)
 {
   unsigned int abs_data_align;
 
+  assert (DWARF2_CIE_DATA_ALIGNMENT != 0);
   cfi_add_CFA_insn_reg_offset (DW_CFA_offset, regno, offset);
 
   abs_data_align = (DWARF2_CIE_DATA_ALIGNMENT < 0
@@ -266,7 +282,7 @@ void
 cfi_add_CFA_def_cfa (unsigned regno, offsetT offset)
 {
   cfi_add_CFA_insn_reg_offset (DW_CFA_def_cfa, regno, offset);
-  cur_cfa_offset = offset;
+  frchain_now->frch_cfi_data->cur_cfa_offset = offset;
 }
 
 /* Add a DW_CFA_register record to the CFI data.  */
@@ -291,7 +307,7 @@ void
 cfi_add_CFA_def_cfa_offset (offsetT offset)
 {
   cfi_add_CFA_insn_offset (DW_CFA_def_cfa_offset, offset);
-  cur_cfa_offset = offset;
+  frchain_now->frch_cfi_data->cur_cfa_offset = offset;
 }
 
 void
@@ -320,9 +336,9 @@ cfi_add_CFA_remember_state (void)
   cfi_add_CFA_insn (DW_CFA_remember_state);
 
   p = xmalloc (sizeof (*p));
-  p->cfa_offset = cur_cfa_offset;
-  p->next = cfa_save_stack;
-  cfa_save_stack = p;
+  p->cfa_offset = frchain_now->frch_cfi_data->cur_cfa_offset;
+  p->next = frchain_now->frch_cfi_data->cfa_save_stack;
+  frchain_now->frch_cfi_data->cfa_save_stack = p;
 }
 
 void
@@ -332,11 +348,11 @@ cfi_add_CFA_restore_state (void)
 
   cfi_add_CFA_insn (DW_CFA_restore_state);
 
-  p = cfa_save_stack;
+  p = frchain_now->frch_cfi_data->cfa_save_stack;
   if (p)
     {
-      cur_cfa_offset = p->cfa_offset;
-      cfa_save_stack = p->next;
+      frchain_now->frch_cfi_data->cur_cfa_offset = p->cfa_offset;
+      frchain_now->frch_cfi_data->cfa_save_stack = p->next;
       free (p);
     }
   else
@@ -350,6 +366,8 @@ static void dot_cfi (int);
 static void dot_cfi_escape (int);
 static void dot_cfi_startproc (int);
 static void dot_cfi_endproc (int);
+static void dot_cfi_personality (int);
+static void dot_cfi_lsda (int);
 
 /* Fake CFI type; outside the byte range of any real CFI insn.  */
 #define CFI_adjust_cfa_offset	0x100
@@ -378,6 +396,8 @@ const pseudo_typeS cfi_pseudo_table[] =
     { "cfi_window_save", dot_cfi, DW_CFA_GNU_window_save },
     { "cfi_escape", dot_cfi_escape, 0 },
     { "cfi_signal_frame", dot_cfi, CFI_signal_frame },
+    { "cfi_personality", dot_cfi_personality, 0 },
+    { "cfi_lsda", dot_cfi_lsda, 0 },
     { NULL, NULL, 0 }
   };
 
@@ -448,7 +468,7 @@ dot_cfi (int arg)
   offsetT offset;
   unsigned reg1, reg2;
 
-  if (!cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
       ignore_rest_of_line ();
@@ -456,8 +476,9 @@ dot_cfi (int arg)
     }
 
   /* If the last address was not at the current PC, advance to current.  */
-  if (symbol_get_frag (last_address) != frag_now
-      || S_GET_VALUE (last_address) != frag_now_fix ())
+  if (symbol_get_frag (frchain_now->frch_cfi_data->last_address) != frag_now
+      || S_GET_VALUE (frchain_now->frch_cfi_data->last_address)
+	 != frag_now_fix ())
     cfi_add_advance_loc (symbol_temp_new_now ());
 
   switch (arg)
@@ -473,7 +494,8 @@ dot_cfi (int arg)
       reg1 = cfi_parse_reg ();
       cfi_parse_separator ();
       offset = cfi_parse_const ();
-      cfi_add_CFA_offset (reg1, offset - cur_cfa_offset);
+      cfi_add_CFA_offset (reg1,
+			  offset - frchain_now->frch_cfi_data->cur_cfa_offset);
       break;
 
     case DW_CFA_def_cfa:
@@ -502,7 +524,8 @@ dot_cfi (int arg)
 
     case CFI_adjust_cfa_offset:
       offset = cfi_parse_const ();
-      cfi_add_CFA_def_cfa_offset (cur_cfa_offset + offset);
+      cfi_add_CFA_def_cfa_offset (frchain_now->frch_cfi_data->cur_cfa_offset
+				  + offset);
       break;
 
     case DW_CFA_restore:
@@ -552,7 +575,7 @@ dot_cfi (int arg)
       break;
 
     case CFI_signal_frame:
-      cur_fde_data->signal_frame = 1;
+      frchain_now->frch_cfi_data->cur_fde_data->signal_frame = 1;
       break;
 
     default:
@@ -568,7 +591,7 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
   struct cfi_escape_data *head, **tail, *e;
   struct cfi_insn_data *insn;
 
-  if (!cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
       ignore_rest_of_line ();
@@ -576,8 +599,9 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
     }
 
   /* If the last address was not at the current PC, advance to current.  */
-  if (symbol_get_frag (last_address) != frag_now
-      || S_GET_VALUE (last_address) != frag_now_fix ())
+  if (symbol_get_frag (frchain_now->frch_cfi_data->last_address) != frag_now
+      || S_GET_VALUE (frchain_now->frch_cfi_data->last_address)
+	 != frag_now_fix ())
     cfi_add_advance_loc (symbol_temp_new_now ());
 
   tail = &head;
@@ -600,11 +624,153 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
 }
 
 static void
+dot_cfi_personality (int ignored ATTRIBUTE_UNUSED)
+{
+  struct fde_entry *fde;
+  offsetT encoding;
+
+  if (frchain_now->frch_cfi_data == NULL)
+    {
+      as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde = frchain_now->frch_cfi_data->cur_fde_data;
+  encoding = get_absolute_expression ();
+  if (encoding == DW_EH_PE_omit)
+    {
+      demand_empty_rest_of_line ();
+      fde->per_encoding = encoding;
+      return;
+    }
+
+  if ((encoding & 0xff) != encoding
+      || ((encoding & 0x70) != 0
+#if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
+	  && (encoding & 0x70) != DW_EH_PE_pcrel
+#endif
+	  )
+	 /* leb128 can be handled, but does something actually need it?  */
+      || (encoding & 7) == DW_EH_PE_uleb128
+      || (encoding & 7) > DW_EH_PE_udata8)
+    {
+      as_bad (_("invalid or unsupported encoding in .cfi_personality"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if (*input_line_pointer++ != ',')
+    {
+      as_bad (_(".cfi_personality requires encoding and symbol arguments"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  expression_and_evaluate (&fde->personality);
+  switch (fde->personality.X_op)
+    {
+    case O_symbol:
+      break;
+    case O_constant:
+      if ((encoding & 0x70) == DW_EH_PE_pcrel)
+	encoding = DW_EH_PE_omit;
+      break;
+    default:
+      encoding = DW_EH_PE_omit;
+      break;
+    }
+
+  fde->per_encoding = encoding;
+
+  if (encoding == DW_EH_PE_omit)
+    {
+      as_bad (_("wrong second argument to .cfi_personality"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+static void
+dot_cfi_lsda (int ignored ATTRIBUTE_UNUSED)
+{
+  struct fde_entry *fde;
+  offsetT encoding;
+
+  if (frchain_now->frch_cfi_data == NULL)
+    {
+      as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde = frchain_now->frch_cfi_data->cur_fde_data;
+  encoding = get_absolute_expression ();
+  if (encoding == DW_EH_PE_omit)
+    {
+      demand_empty_rest_of_line ();
+      fde->lsda_encoding = encoding;
+      return;
+    }
+
+  if ((encoding & 0xff) != encoding
+      || ((encoding & 0x70) != 0
+#if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
+	  && (encoding & 0x70) != DW_EH_PE_pcrel
+#endif
+	  )
+	 /* leb128 can be handled, but does something actually need it?  */
+      || (encoding & 7) == DW_EH_PE_uleb128
+      || (encoding & 7) > DW_EH_PE_udata8)
+    {
+      as_bad (_("invalid or unsupported encoding in .cfi_lsda"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if (*input_line_pointer++ != ',')
+    {
+      as_bad (_(".cfi_lsda requires encoding and symbol arguments"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  fde->lsda_encoding = encoding;
+
+  expression_and_evaluate (&fde->lsda);
+  switch (fde->lsda.X_op)
+    {
+    case O_symbol:
+      break;
+    case O_constant:
+      if ((encoding & 0x70) == DW_EH_PE_pcrel)
+	encoding = DW_EH_PE_omit;
+      break;
+    default:
+      encoding = DW_EH_PE_omit;
+      break;
+    }
+
+  fde->lsda_encoding = encoding;
+
+  if (encoding == DW_EH_PE_omit)
+    {
+      as_bad (_("wrong second argument to .cfi_lsda"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+static void
 dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
 {
   int simple = 0;
 
-  if (cur_fde_data)
+  if (frchain_now->frch_cfi_data != NULL)
     {
       as_bad (_("previous CFI entry not closed (missing .cfi_endproc)"));
       ignore_rest_of_line ();
@@ -631,7 +797,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
     }
   demand_empty_rest_of_line ();
 
-  cur_cfa_offset = 0;
+  frchain_now->frch_cfi_data->cur_cfa_offset = 0;
   if (!simple)
     tc_cfi_frame_initial_instructions ();
 }
@@ -639,7 +805,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
 static void
 dot_cfi_endproc (int ignored ATTRIBUTE_UNUSED)
 {
-  if (! cur_fde_data)
+  if (frchain_now->frch_cfi_data == NULL)
     {
       as_bad (_(".cfi_endproc without corresponding .cfi_startproc"));
       ignore_rest_of_line ();
@@ -714,18 +880,18 @@ output_cfi_insn (struct cfi_insn_data *insn)
 	      out_one (DW_CFA_advance_loc + scaled);
 	    else if (delta <= 0xFF)
 	      {
-	        out_one (DW_CFA_advance_loc1);
-	        out_one (delta);
+		out_one (DW_CFA_advance_loc1);
+		out_one (delta);
 	      }
 	    else if (delta <= 0xFFFF)
 	      {
-	        out_one (DW_CFA_advance_loc2);
-	        out_two (delta);
+		out_one (DW_CFA_advance_loc2);
+		out_two (delta);
 	      }
 	    else
 	      {
-	        out_one (DW_CFA_advance_loc4);
-	        out_four (delta);
+		out_one (DW_CFA_advance_loc4);
+		out_four (delta);
 	      }
 	  }
 	else
@@ -850,12 +1016,33 @@ output_cfi_insn (struct cfi_insn_data *insn)
     }
 }
 
+static offsetT
+encoding_size (unsigned char encoding)
+{
+  if (encoding == DW_EH_PE_omit)
+    return 0;
+  switch (encoding & 0x7)
+    {
+    case 0:
+      return bfd_get_arch_size (stdoutput) == 64 ? 8 : 4;
+    case DW_EH_PE_udata2:
+      return 2;
+    case DW_EH_PE_udata4:
+      return 4;
+    case DW_EH_PE_udata8:
+      return 8;
+    default:
+      abort ();
+    }
+}
+
 static void
 output_cie (struct cie_entry *cie)
 {
   symbolS *after_size_address, *end_address;
   expressionS exp;
   struct cfi_insn_data *i;
+  offsetT augmentation_size;
 
   cie->start_address = symbol_temp_new_now ();
   after_size_address = symbol_temp_make ();
@@ -871,6 +1058,10 @@ output_cie (struct cie_entry *cie)
   out_four (0);					/* CIE id.  */
   out_one (DW_CIE_VERSION);			/* Version.  */
   out_one ('z');				/* Augmentation.  */
+  if (cie->per_encoding != DW_EH_PE_omit)
+    out_one ('P');
+  if (cie->lsda_encoding != DW_EH_PE_omit)
+    out_one ('L');
   out_one ('R');
   if (cie->signal_frame)
     out_one ('S');
@@ -881,7 +1072,32 @@ output_cie (struct cie_entry *cie)
     out_one (cie->return_column);
   else
     out_uleb128 (cie->return_column);
-  out_uleb128 (1);				/* Augmentation size.  */
+  augmentation_size = 1 + (cie->lsda_encoding != DW_EH_PE_omit);
+  if (cie->per_encoding != DW_EH_PE_omit)
+    augmentation_size += 1 + encoding_size (cie->per_encoding);
+  out_uleb128 (augmentation_size);		/* Augmentation size.  */
+  if (cie->per_encoding != DW_EH_PE_omit)
+    {
+      offsetT size = encoding_size (cie->per_encoding);
+      out_one (cie->per_encoding);
+      exp = cie->personality;
+      if ((cie->per_encoding & 0x70) == DW_EH_PE_pcrel)
+	{
+#ifdef DIFF_EXPR_OK
+	  exp.X_op = O_subtract;
+	  exp.X_op_symbol = symbol_temp_new_now ();
+	  emit_expr (&exp, size);
+#elif defined (tc_cfi_emit_pcrel_expr)
+	  tc_cfi_emit_pcrel_expr (&exp, size);
+#else
+	  abort ();
+#endif
+	}
+      else
+	emit_expr (&exp, size);
+    }
+  if (cie->lsda_encoding != DW_EH_PE_omit)
+    out_one (cie->lsda_encoding);
 #if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
   out_one (DW_EH_PE_pcrel | DW_EH_PE_sdata4);
 #else
@@ -902,6 +1118,7 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
 {
   symbolS *after_size_address, *end_address;
   expressionS exp;
+  offsetT augmentation_size;
 
   after_size_address = symbol_temp_make ();
   end_address = symbol_temp_make ();
@@ -917,7 +1134,7 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
   exp.X_op_symbol = cie->start_address;
   emit_expr (&exp, 4);				/* CIE offset.  */
 
-#ifdef DIFF_EXPR_OK  
+#ifdef DIFF_EXPR_OK
   exp.X_add_symbol = fde->start_address;
   exp.X_op_symbol = symbol_temp_new_now ();
   emit_expr (&exp, 4);				/* Code offset.  */
@@ -937,7 +1154,27 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
   exp.X_op_symbol = fde->start_address;		/* Code length.  */
   emit_expr (&exp, 4);
 
-  out_uleb128 (0);				/* Augmentation size.  */
+  augmentation_size = encoding_size (fde->lsda_encoding);
+  out_uleb128 (augmentation_size);		/* Augmentation size.  */
+
+  if (fde->lsda_encoding != DW_EH_PE_omit)
+    {
+      exp = fde->lsda;
+      if ((fde->lsda_encoding & 0x70) == DW_EH_PE_pcrel)
+	{
+#ifdef DIFF_EXPR_OK
+	  exp.X_op = O_subtract;
+	  exp.X_op_symbol = symbol_temp_new_now ();
+	  emit_expr (&exp, augmentation_size);
+#elif defined (tc_cfi_emit_pcrel_expr)
+	  tc_cfi_emit_pcrel_expr (&exp, augmentation_size);
+#else
+	  abort ();
+#endif
+	}
+      else
+	emit_expr (&exp, augmentation_size);
+    }
 
   for (; first; first = first->next)
     output_cfi_insn (first);
@@ -955,8 +1192,31 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
   for (cie = cie_root; cie; cie = cie->next)
     {
       if (cie->return_column != fde->return_column
-	  || cie->signal_frame != fde->signal_frame)
+	  || cie->signal_frame != fde->signal_frame
+	  || cie->per_encoding != fde->per_encoding
+	  || cie->lsda_encoding != fde->lsda_encoding)
 	continue;
+      if (cie->per_encoding != DW_EH_PE_omit)
+	{
+	  if (cie->personality.X_op != fde->personality.X_op
+	      || cie->personality.X_add_number
+		 != fde->personality.X_add_number)
+	    continue;
+	  switch (cie->personality.X_op)
+	    {
+	    case O_constant:
+	      if (cie->personality.X_unsigned != fde->personality.X_unsigned)
+		continue;
+	      break;
+	    case O_symbol:
+	      if (cie->personality.X_add_symbol
+		  != fde->personality.X_add_symbol)
+		continue;
+	      break;
+	    default:
+	      abort ();
+	    }
+	}
       for (i = cie->first, j = fde->data;
 	   i != cie->last && j != NULL;
 	   i = i->next, j = j->next)
@@ -1029,6 +1289,9 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
   cie_root = cie;
   cie->return_column = fde->return_column;
   cie->signal_frame = fde->signal_frame;
+  cie->per_encoding = fde->per_encoding;
+  cie->lsda_encoding = fde->lsda_encoding;
+  cie->personality = fde->personality;
   cie->first = fde->data;
 
   for (i = cie->first; i ; i = i->next)
@@ -1052,12 +1315,6 @@ cfi_finish (void)
   struct fde_entry *fde;
   int save_flag_traditional_format;
 
-  if (cur_fde_data)
-    {
-      as_bad (_("open CFI at the end of file; missing .cfi_endproc directive"));
-      cur_fde_data->end_address = cur_fde_data->start_address;
-    }
-
   if (all_fde_data == 0)
     return;
 
@@ -1077,6 +1334,12 @@ cfi_finish (void)
       struct cfi_insn_data *first;
       struct cie_entry *cie;
 
+      if (fde->end_address == NULL)
+	{
+	  as_bad (_("open CFI at the end of file; missing .cfi_endproc directive"));
+	  fde->end_address = fde->start_address;
+	}
+
       cie = select_cie_for_fde (fde, &first);
       output_fde (fde, cie, first, fde->next == NULL ? EH_FRAME_ALIGNMENT : 2);
     }
diff --git a/gas/dwarf2dbg.c b/gas/dwarf2dbg.c
index 16666fa4f28d..671a9b030d4b 100644
--- a/gas/dwarf2dbg.c
+++ b/gas/dwarf2dbg.c
@@ -28,7 +28,6 @@
 	      [epilogue_begin] [is_stmt VALUE] [isa VALUE]
 */
 
-#include "ansidecl.h"
 #include "as.h"
 #include "safe-ctype.h"
 
@@ -46,6 +45,29 @@
 #include "dwarf2dbg.h"
 #include <filenames.h>
 
+#ifdef HAVE_DOS_BASED_FILE_SYSTEM
+/* We need to decide which character to use as a directory separator.
+   Just because HAVE_DOS_BASED_FILE_SYSTEM is defined, it does not
+   necessarily mean that the backslash character is the one to use.
+   Some environments, eg Cygwin, can support both naming conventions.
+   So we use the heuristic that we only need to use the backslash if
+   the path is an absolute path starting with a DOS style drive
+   selector.  eg C: or D:  */
+# define INSERT_DIR_SEPARATOR(string, offset) \
+  do \
+    { \
+      if (offset > 1 \
+          && string[0] != 0 \
+          && string[1] == ':') \
+       string [offset] = '\\'; \
+      else \
+       string [offset] = '/'; \
+    } \
+  while (0)
+#else
+# define INSERT_DIR_SEPARATOR(string, offset) string[offset] = '/'
+#endif
+
 #ifndef DWARF2_FORMAT
 # define DWARF2_FORMAT() dwarf2_format_32bit
 #endif
@@ -66,6 +88,13 @@
 #define DL_FILES	1
 #define DL_BODY		2
 
+/* If linker relaxation might change offsets in the code, the DWARF special
+   opcodes and variable-length operands cannot be used.  If this macro is
+   nonzero, use the DW_LNS_fixed_advance_pc opcode instead.  */
+#ifndef DWARF2_USE_FIXED_ADVANCE_PC
+# define DWARF2_USE_FIXED_ADVANCE_PC	0
+#endif
+
 /* First special line opcde - leave room for the standard opcodes.
    Note: If you want to change this, you'll have to update the
    "standard_opcode_lengths" table that is emitted below in
@@ -169,22 +198,22 @@ static void out_two (int);
 static void out_four (int);
 static void out_abbrev (int, int);
 static void out_uleb128 (addressT);
-static offsetT get_frag_fix (fragS *);
+static void out_sleb128 (addressT);
+static offsetT get_frag_fix (fragS *, segT);
 static void out_set_addr (symbolS *);
 static int size_inc_line_addr (int, addressT);
 static void emit_inc_line_addr (int, addressT, char *, int);
 static void out_inc_line_addr (int, addressT);
+static void out_fixed_inc_line_addr (int, symbolS *, symbolS *);
 static void relax_inc_line_addr (int, symbolS *, symbolS *);
 static void process_entries (segT, struct line_entry *);
 static void out_file_list (void);
 static void out_debug_line (segT);
 static void out_debug_aranges (segT, segT);
 static void out_debug_abbrev (segT);
-static void out_debug_info (segT, segT, segT);
 
 #ifndef TC_DWARF2_EMIT_OFFSET
-# define TC_DWARF2_EMIT_OFFSET  generic_dwarf2_emit_offset
-static void generic_dwarf2_emit_offset (symbolS *, unsigned int);
+#define TC_DWARF2_EMIT_OFFSET  generic_dwarf2_emit_offset
 
 /* Create an offset to .dwarf2_*.  */
 
@@ -569,7 +598,7 @@ dwarf2_directive_loc (int dummy ATTRIBUTE_UNUSED)
 	  char *cp = (char *) alloca (dir_len + 1 + file_len + 1);
 
 	  memcpy (cp, dirs[files[filenum].dir], dir_len);
-	  cp[dir_len] = '/';
+	  INSERT_DIR_SEPARATOR (cp, dir_len);
 	  memcpy (cp + dir_len + 1, files[filenum].filename, file_len);
 	  cp[dir_len + file_len + 1] = '\0';
 	  listing_source_file (cp);
@@ -670,27 +699,18 @@ dwarf2_directive_loc_mark_labels (int dummy ATTRIBUTE_UNUSED)
 static struct frag *
 first_frag_for_seg (segT seg)
 {
-  frchainS *f, *first = NULL;
-
-  for (f = frchain_root; f; f = f->frch_next)
-    if (f->frch_seg == seg
-	&& (! first || first->frch_subseg > f->frch_subseg))
-      first = f;
-
-  return first ? first->frch_root : NULL;
+  return seg_info (seg)->frchainP->frch_root;
 }
 
 static struct frag *
 last_frag_for_seg (segT seg)
 {
-  frchainS *f, *last = NULL;
+  frchainS *f = seg_info (seg)->frchainP;
 
-  for (f = frchain_root; f; f = f->frch_next)
-    if (f->frch_seg == seg
-	&& (! last || last->frch_subseg < f->frch_subseg))
-      last= f;
+  while (f->frch_next != NULL)
+    f = f->frch_next;
 
-  return last ? last->frch_last : NULL;
+  return f->frch_last;
 }
 
 /* Emit a single byte into the current segment.  */
@@ -733,6 +753,14 @@ out_uleb128 (addressT value)
   output_leb128 (frag_more (sizeof_leb128 (value, 0)), value, 0);
 }
 
+/* Emit a signed "little-endian base 128" number.  */
+
+static void
+out_sleb128 (addressT value)
+{
+  output_leb128 (frag_more (sizeof_leb128 (value, 1)), value, 1);
+}
+
 /* Emit a tuple for .debug_abbrev.  */
 
 static inline void
@@ -745,7 +773,7 @@ out_abbrev (int name, int form)
 /* Get the size of a fragment.  */
 
 static offsetT
-get_frag_fix (fragS *frag)
+get_frag_fix (fragS *frag, segT seg)
 {
   frchainS *fr;
 
@@ -755,7 +783,7 @@ get_frag_fix (fragS *frag)
   /* If a fragment is the last in the chain, special measures must be
      taken to find its size before relaxation, since it may be pending
      on some subsegment chain.  */
-  for (fr = frchain_root; fr; fr = fr->frch_next)
+  for (fr = seg_info (seg)->frchainP; fr; fr = fr->frch_next)
     if (fr->frch_last == frag)
       return (char *) obstack_next_free (&fr->frch_obstack) - frag->fr_literal;
 
@@ -966,6 +994,45 @@ out_inc_line_addr (int line_delta, addressT addr_delta)
   emit_inc_line_addr (line_delta, addr_delta, frag_more (len), len);
 }
 
+/* Write out an alternative form of line and address skips using
+   DW_LNS_fixed_advance_pc opcodes.  This uses more space than the default
+   line and address information, but it helps support linker relaxation that
+   changes the code offsets.  */
+
+static void
+out_fixed_inc_line_addr (int line_delta, symbolS *to_sym, symbolS *from_sym)
+{
+  expressionS expr;
+
+  /* INT_MAX is a signal that this is actually a DW_LNE_end_sequence.  */
+  if (line_delta == INT_MAX)
+    {
+      out_opcode (DW_LNS_fixed_advance_pc);
+      expr.X_op = O_subtract;
+      expr.X_add_symbol = to_sym;
+      expr.X_op_symbol = from_sym;
+      expr.X_add_number = 0;
+      emit_expr (&expr, 2);
+
+      out_opcode (DW_LNS_extended_op);
+      out_byte (1);
+      out_opcode (DW_LNE_end_sequence);
+      return;
+    }
+
+  out_opcode (DW_LNS_advance_line);
+  out_sleb128 (line_delta);
+
+  out_opcode (DW_LNS_fixed_advance_pc);
+  expr.X_op = O_subtract;
+  expr.X_add_symbol = to_sym;
+  expr.X_op_symbol = from_sym;
+  expr.X_add_number = 0;
+  emit_expr (&expr, 2);
+
+  out_opcode (DW_LNS_copy);
+}
+
 /* Generate a variant frag that we can use to relax address/line
    increments between fragments of the target segment.  */
 
@@ -1116,6 +1183,8 @@ process_entries (segT seg, struct line_entry *e)
 	  out_set_addr (lab);
 	  out_inc_line_addr (line_delta, 0);
 	}
+      else if (DWARF2_USE_FIXED_ADVANCE_PC)
+	out_fixed_inc_line_addr (line_delta, lab, last_lab);
       else if (frag == last_frag)
 	out_inc_line_addr (line_delta, frag_ofs - last_frag_ofs);
       else
@@ -1134,8 +1203,13 @@ process_entries (segT seg, struct line_entry *e)
 
   /* Emit a DW_LNE_end_sequence for the end of the section.  */
   frag = last_frag_for_seg (seg);
-  frag_ofs = get_frag_fix (frag);
-  if (frag == last_frag)
+  frag_ofs = get_frag_fix (frag, seg);
+  if (DWARF2_USE_FIXED_ADVANCE_PC)
+    {
+      lab = symbol_temp_new (seg, frag_ofs, frag);
+      out_fixed_inc_line_addr (INT_MAX, lab, last_lab);
+    }
+  else if (frag == last_frag)
     out_inc_line_addr (INT_MAX, frag_ofs - last_frag_ofs);
   else
     {
@@ -1277,6 +1351,54 @@ out_debug_line (segT line_seg)
   symbol_set_value_now (line_end);
 }
 
+static void
+out_debug_ranges (segT ranges_seg)
+{
+  unsigned int addr_size = sizeof_address;
+  struct line_seg *s;
+  expressionS expr;
+  unsigned int i;
+
+  subseg_set (ranges_seg, 0);
+
+  /* Base Address Entry.  */
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0xff);
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+
+  /* Range List Entry.  */
+  for (s = all_segs; s; s = s->next)
+    {
+      fragS *frag;
+      symbolS *beg, *end;
+
+      frag = first_frag_for_seg (s->seg);
+      beg = symbol_temp_new (s->seg, 0, frag);
+      s->text_start = beg;
+
+      frag = last_frag_for_seg (s->seg);
+      end = symbol_temp_new (s->seg, get_frag_fix (frag, s->seg), frag);
+      s->text_end = end;
+
+      expr.X_op = O_symbol;
+      expr.X_add_symbol = beg;
+      expr.X_add_number = 0;
+      emit_expr (&expr, addr_size);
+
+      expr.X_op = O_symbol;
+      expr.X_add_symbol = end;
+      expr.X_add_number = 0;
+      emit_expr (&expr, addr_size);
+    }
+
+  /* End of Range Entry.   */
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+  for (i = 0; i < addr_size; i++) 
+    out_byte (0);
+}
+
 /* Emit data for .debug_aranges.  */
 
 static void
@@ -1332,7 +1454,7 @@ out_debug_aranges (segT aranges_seg, segT info_seg)
       s->text_start = beg;
 
       frag = last_frag_for_seg (s->seg);
-      end = symbol_temp_new (s->seg, get_frag_fix (frag), frag);
+      end = symbol_temp_new (s->seg, get_frag_fix (frag, s->seg), frag);
       s->text_end = end;
 
       expr.X_op = O_symbol;
@@ -1369,6 +1491,13 @@ out_debug_abbrev (segT abbrev_seg)
       out_abbrev (DW_AT_low_pc, DW_FORM_addr);
       out_abbrev (DW_AT_high_pc, DW_FORM_addr);
     }
+  else
+    {
+      if (DWARF2_FORMAT () == dwarf2_format_32bit)
+	out_abbrev (DW_AT_ranges, DW_FORM_data4);
+      else
+	out_abbrev (DW_AT_ranges, DW_FORM_data8);
+    }
   out_abbrev (DW_AT_name, DW_FORM_string);
   out_abbrev (DW_AT_comp_dir, DW_FORM_string);
   out_abbrev (DW_AT_producer, DW_FORM_string);
@@ -1382,7 +1511,7 @@ out_debug_abbrev (segT abbrev_seg)
 /* Emit a description of this compilation unit for .debug_info.  */
 
 static void
-out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
+out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg, segT ranges_seg)
 {
   char producer[128];
   char *comp_dir;
@@ -1445,8 +1574,7 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
   /* ??? sizeof_offset */
   TC_DWARF2_EMIT_OFFSET (section_symbol (line_seg), 4);
 
-  /* These two attributes may only be emitted if all of the code is
-     contiguous.  Multiple sections are not that.  */
+  /* These two attributes are emitted if all of the code is contiguous.  */
   if (all_segs->next == NULL)
     {
       /* DW_AT_low_pc */
@@ -1461,6 +1589,12 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
       expr.X_add_number = 0;
       emit_expr (&expr, sizeof_address);
     }
+  else
+    {
+      /* This attribute is emitted if the code is disjoint.  */
+      /* DW_AT_ranges.  */
+      TC_DWARF2_EMIT_OFFSET (section_symbol (ranges_seg), sizeof_offset);
+    }
 
   /* DW_AT_name.  We don't have the actual file name that was present
      on the command line, so assume files[1] is the main input file.
@@ -1473,7 +1607,7 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
       len = strlen (dirs[files[1].dir]);
       p = frag_more (len + 1);
       memcpy (p, dirs[files[1].dir], len);
-      p[len] = '/';
+      INSERT_DIR_SEPARATOR (p, len);
     }
   len = strlen (files[1].filename) + 1;
   p = frag_more (len);
@@ -1551,6 +1685,7 @@ dwarf2_finish (void)
     {
       segT abbrev_seg;
       segT aranges_seg;
+      segT ranges_seg;
 
       assert (all_segs);
       
@@ -1567,8 +1702,19 @@ dwarf2_finish (void)
 
       record_alignment (aranges_seg, ffs (2 * sizeof_address) - 1);
 
+      if (all_segs->next == NULL)
+	ranges_seg = NULL;
+      else
+	{
+	  ranges_seg = subseg_new (".debug_ranges", 0);
+	  bfd_set_section_flags (stdoutput, ranges_seg, 
+				 SEC_READONLY | SEC_DEBUGGING);
+	  record_alignment (ranges_seg, ffs (2 * sizeof_address) - 1);
+	  out_debug_ranges (ranges_seg);
+	}
+
       out_debug_aranges (aranges_seg, info_seg);
       out_debug_abbrev (abbrev_seg);
-      out_debug_info (info_seg, abbrev_seg, line_seg);
+      out_debug_info (info_seg, abbrev_seg, line_seg, ranges_seg);
     }
 }
diff --git a/gas/ecoff.c b/gas/ecoff.c
index 45116e86db0d..2f9f71f8ebe6 100644
--- a/gas/ecoff.c
+++ b/gas/ecoff.c
@@ -1,6 +1,6 @@
 /* ECOFF debugging support.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005
+   2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    This file was put together by Ian Lance Taylor <ian@cygnus.com>.  A
@@ -2778,7 +2778,7 @@ ecoff_directive_val (int ignore ATTRIBUTE_UNUSED)
   expression (&exp);
   if (exp.X_op != O_constant && exp.X_op != O_symbol)
     {
-      as_bad (_(".val expression is too copmlex"));
+      as_bad (_(".val expression is too complex"));
       demand_empty_rest_of_line ();
       return;
     }
diff --git a/gas/expr.c b/gas/expr.c
index 69f0aaccdb64..11f2942672cf 100644
--- a/gas/expr.c
+++ b/gas/expr.c
@@ -1,6 +1,6 @@
 /* expr.c -operands, expressions-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,7 +25,6 @@
    (It also gives smaller files to re-compile.)
    Here, "operand"s are of expressions, not instructions.  */
 
-#include <string.h>
 #define min(a, b)       ((a) < (b) ? (a) : (b))
 
 #include "as.h"
@@ -1003,11 +1002,6 @@ operand (expressionS *expressionP, enum expr_mode mode)
     case '-':
     case '+':
       {
-	/* Do not accept ++e or --e as +(+e) or -(-e)
-	   Disabled, since the preprocessor removes whitespace.  */
-	if (0 && (c == '-' || c == '+') && *input_line_pointer == c)
-	  goto target_op;
-	
 	operand (expressionP, mode);
 	if (expressionP->X_op == O_constant)
 	  {
@@ -1291,7 +1285,6 @@ operand (expressionS *expressionP, enum expr_mode mode)
 	}
       else
 	{
-	target_op:
 	  /* Let the target try to parse it.  Success is indicated by changing
 	     the X_op field to something other than O_absent and pointing
 	     input_line_pointer past the expression.  If it can't parse the
@@ -1552,11 +1545,7 @@ operator (int *num_chars)
 
     case '+':
     case '-':
-      /* Do not allow a++b and a--b to be a + (+b) and a - (-b)
-	 Disabled, since the preprocessor removes whitespace.  */
-      if (1 || input_line_pointer[1] != c)
-	return op_encoding[c];
-      return O_illegal;
+      return op_encoding[c];
 
     case '<':
       switch (input_line_pointer[1])
@@ -1647,7 +1636,7 @@ expr (int rankarg,		/* Larger # is higher rank.  */
   operatorT op_right;
   int op_chars;
 
-  know (rank >= 0);
+  know (rankarg >= 0);
 
   /* Save the value of dot for the fixup code.  */
   if (rank == 0)
@@ -1796,7 +1785,9 @@ expr (int rankarg,		/* Larger # is higher rank.  */
 	    case O_bit_or_not:		resultP->X_add_number |= ~v; break;
 	    case O_bit_exclusive_or:	resultP->X_add_number ^= v; break;
 	    case O_bit_and:		resultP->X_add_number &= v; break;
-	    case O_add:			resultP->X_add_number += v; break;
+	      /* Constant + constant (O_add) is handled by the
+		 previous if statement for constant + X, so is omitted
+		 here.  */
 	    case O_subtract:		resultP->X_add_number -= v; break;
 	    case O_eq:
 	      resultP->X_add_number =
diff --git a/gas/frags.c b/gas/frags.c
index b08ef502cbf7..adb9b1986301 100644
--- a/gas/frags.c
+++ b/gas/frags.c
@@ -389,9 +389,9 @@ frag_append_1_char (int datum)
    not already accounted for in the frag FR_ADDRESS.  */
 
 bfd_boolean
-frag_offset_fixed_p (fragS *frag1, fragS *frag2, bfd_vma *offset)
+frag_offset_fixed_p (const fragS *frag1, const fragS *frag2, bfd_vma *offset)
 {
-  fragS *frag;
+  const fragS *frag;
   bfd_vma off;
 
   /* Start with offset initialised to difference between the two frags.
diff --git a/gas/frags.h b/gas/frags.h
index 880446763a4e..66630dbd164b 100644
--- a/gas/frags.h
+++ b/gas/frags.h
@@ -148,6 +148,6 @@ char *frag_var (relax_stateT type,
 		offsetT offset,
 		char *opcode);
 
-bfd_boolean frag_offset_fixed_p (fragS *, fragS *, bfd_vma *);
+bfd_boolean frag_offset_fixed_p (const fragS *, const fragS *, bfd_vma *);
 
 #endif /* FRAGS_H */
diff --git a/gas/gdbinit.in b/gas/gdbinit.in
index e946726ec676..fb1046da531a 100644
--- a/gas/gdbinit.in
+++ b/gas/gdbinit.in
@@ -6,7 +6,6 @@ break as_warn_where
 break as_bad
 break as_bad_where
 break as_fatal
-break as_perror
 break as_assert
 break as_abort
 
diff --git a/gas/input-file.c b/gas/input-file.c
index 343f0494087c..0907bad37c86 100644
--- a/gas/input-file.c
+++ b/gas/input-file.c
@@ -1,6 +1,6 @@
 /* input_file.c - Deal with Input Files -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1999, 2000, 2001,
-   2002, 2003, 2005
+   2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -25,9 +25,6 @@
    What we lose in "efficiency" we gain in modularity.
    Note we don't need to #include the "as.h" file. No common coupling!  */
 
-#include <stdio.h>
-#include <string.h>
-#include <errno.h>
 #include "as.h"
 #include "input-file.h"
 #include "safe-ctype.h"
@@ -143,8 +140,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 
   if (f_in == NULL)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't open %s for reading"), file_name);
+      as_bad (_("can't open %s for reading: %s"),
+	      file_name, xstrerror (errno));
       return;
     }
 
@@ -152,8 +149,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 
   if (ferror (f_in))
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't open %s for reading"), file_name);
+      as_bad (_("can't read from %s: %s"),
+	      file_name, xstrerror (errno));
 
       fclose (f_in);
       f_in = NULL;
@@ -166,8 +163,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
       c = getc (f_in);
       if (c == 'N')
 	{
-	  fgets (buf, 80, f_in);
-	  if (!strncmp (buf, "O_APP", 5) && ISSPACE (buf[5]))
+	  if (fgets (buf, sizeof (buf), f_in)
+	      && !strncmp (buf, "O_APP", 5) && ISSPACE (buf[5]))
 	    preprocess = 0;
 	  if (!strchr (buf, '\n'))
 	    ungetc ('#', f_in);	/* It was longer.  */
@@ -176,8 +173,8 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
 	}
       else if (c == 'A')
 	{
-	  fgets (buf, 80, f_in);
-	  if (!strncmp (buf, "PP", 2) && ISSPACE (buf[2]))
+	  if (fgets (buf, sizeof (buf), f_in)
+	      && !strncmp (buf, "PP", 2) && ISSPACE (buf[2]))
 	    preprocess = 1;
 	  if (!strchr (buf, '\n'))
 	    ungetc ('#', f_in);
@@ -215,8 +212,7 @@ input_file_get (char *buf, int buflen)
   size = fread (buf, sizeof (char), buflen, f_in);
   if (size < 0)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't read from %s"), file_name);
+      as_bad (_("can't read from %s: %s"), file_name, xstrerror (errno));
       size = 0;
     }
   return size;
@@ -242,8 +238,7 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
     size = fread (where, sizeof (char), BUFFER_SIZE, f_in);
   if (size < 0)
     {
-      bfd_set_error (bfd_error_system_call);
-      as_perror (_("Can't read from %s"), file_name);
+      as_bad (_("can't read from %s: %s"), file_name, xstrerror (errno));
       size = 0;
     }
   if (size)
@@ -251,10 +246,8 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
   else
     {
       if (fclose (f_in))
-	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("Can't close %s"), file_name);
-	}
+	as_warn (_("can't close %s: %s"), file_name, xstrerror (errno));
+
       f_in = (FILE *) 0;
       return_value = 0;
     }
diff --git a/gas/input-file.h b/gas/input-file.h
index bc8289e4e444..0628716b6403 100644
--- a/gas/input-file.h
+++ b/gas/input-file.h
@@ -1,5 +1,6 @@
 /* input_file.h header for input-file.c
-   Copyright 1987, 1992, 1993, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 2000, 2003, 2005, 2006
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -51,8 +52,8 @@
  *
  * input_file_close ()			Closes opened file.
  *
- * All errors are reported (using as_perror) so caller doesn't have to think
- * about I/O errors. No I/O errors are fatal: an end-of-file may be faked.
+ * All errors are reported so caller doesn't have to think
+ * about I/O errors.
  */
 
 char *input_file_give_next_buffer (char *where);
diff --git a/gas/input-scrub.c b/gas/input-scrub.c
index 8562ee25dff3..5698a6dc22a2 100644
--- a/gas/input-scrub.c
+++ b/gas/input-scrub.c
@@ -1,6 +1,6 @@
 /* input_scrub.c - Break up input buffers into whole numbers of lines.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   2000, 2001, 2003
+   2000, 2001, 2003, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -20,7 +20,6 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <errno.h>		/* Need this to make errno declaration right */
 #include "as.h"
 #include "input-file.h"
 #include "sb.h"
@@ -57,6 +56,10 @@
 #define BEFORE_SIZE (1)
 #define AFTER_SIZE  (1)
 
+#ifndef TC_EOL_IN_INSN
+#define TC_EOL_IN_INSN(P) 0
+#endif
+
 static char *buffer_start;	/*->1st char of full buffer area.  */
 static char *partial_where;	/*->after last full line in buffer.  */
 static int partial_size;	/* >=0. Number of chars in partial line in buffer.  */
@@ -342,8 +345,9 @@ input_scrub_next_buffer (char **bufp)
   if (limit)
     {
       register char *p;		/* Find last newline.  */
-
-      for (p = limit - 1; *p != '\n'; --p)
+      /* Terminate the buffer to avoid confusing TC_EOL_IN_INSN.  */
+      *limit = '\0';
+      for (p = limit - 1; *p != '\n' || TC_EOL_IN_INSN (p); --p)
 	;
       ++p;
 
@@ -369,7 +373,9 @@ input_scrub_next_buffer (char **bufp)
 	      return NULL;
 	    }
 
-	  for (p = limit - 1; *p != '\n'; --p)
+	  /* Terminate the buffer to avoid confusing TC_EOL_IN_INSN.  */
+	  *limit = '\0';
+	  for (p = limit - 1; *p != '\n' || TC_EOL_IN_INSN (p); --p)
 	    ;
 	  ++p;
 	}
@@ -429,13 +435,34 @@ bump_line_counters (void)
    Returns nonzero if the filename actually changes.  */
 
 int
-new_logical_line (char *fname, /* DON'T destroy it!  We point to it!  */
-		  int line_number)
+new_logical_line_flags (char *fname, /* DON'T destroy it!  We point to it!  */
+			int line_number,
+			int flags)
 {
+  switch (flags)
+    {
+    case 0:
+      break;
+    case 1:
+      if (line_number != -1)
+	abort ();
+      break;
+    case 1 << 1:
+    case 1 << 2:
+      /* FIXME: we could check that include nesting is correct.  */
+      break;
+    default:
+      abort ();
+    }
+
   if (line_number >= 0)
     logical_input_line = line_number;
-  else if (line_number == -2 && logical_input_line > 0)
-    --logical_input_line;
+  else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
+    {
+      logical_input_file = physical_input_file;
+      logical_input_line = physical_input_line;
+      fname = NULL;
+    }
 
   if (fname
       && (logical_input_file == NULL
@@ -447,6 +474,13 @@ new_logical_line (char *fname, /* DON'T destroy it!  We point to it!  */
   else
     return 0;
 }
+
+int
+new_logical_line (char *fname, int line_number)
+{
+  return new_logical_line_flags (fname, line_number, 0);
+}
+
 
 /* Return the current file name and line number.
    namep should be char * const *, but there are compilers which screw
diff --git a/gas/itbl-lex.c b/gas/itbl-lex.c
deleted file mode 100644
index 1180eac13a02..000000000000
--- a/gas/itbl-lex.c
+++ /dev/null
@@ -1,1713 +0,0 @@
-/* A lexical scanner generated by flex */
-
-/* Scanner skeleton version:
- * $Header: /cvs/src/src/gas/Attic/itbl-lex.c,v 1.1.16.1 2006/04/16 18:36:43 drow Exp $
- */
-
-#define FLEX_SCANNER
-#define YY_FLEX_MAJOR_VERSION 2
-#define YY_FLEX_MINOR_VERSION 5
-
-#include <stdio.h>
-#include <errno.h>
-
-/* cfront 1.2 defines "c_plusplus" instead of "__cplusplus" */
-#ifdef c_plusplus
-#ifndef __cplusplus
-#define __cplusplus
-#endif
-#endif
-
-
-#ifdef __cplusplus
-
-#include <stdlib.h>
-#ifndef _WIN32
-#include <unistd.h>
-#endif
-
-/* Use prototypes in function declarations. */
-#define YY_USE_PROTOS
-
-/* The "const" storage-class-modifier is valid. */
-#define YY_USE_CONST
-
-#else	/* ! __cplusplus */
-
-#if __STDC__
-
-#define YY_USE_PROTOS
-#define YY_USE_CONST
-
-#endif	/* __STDC__ */
-#endif	/* ! __cplusplus */
-
-#ifdef __TURBOC__
- #pragma warn -rch
- #pragma warn -use
-#include <io.h>
-#include <stdlib.h>
-#define YY_USE_CONST
-#define YY_USE_PROTOS
-#endif
-
-#ifdef YY_USE_CONST
-#define yyconst const
-#else
-#define yyconst
-#endif
-
-
-#ifdef YY_USE_PROTOS
-#define YY_PROTO(proto) proto
-#else
-#define YY_PROTO(proto) ()
-#endif
-
-
-/* Returned upon end-of-file. */
-#define YY_NULL 0
-
-/* Promotes a possibly negative, possibly signed char to an unsigned
- * integer for use as an array index.  If the signed char is negative,
- * we want to instead treat it as an 8-bit unsigned char, hence the
- * double cast.
- */
-#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
-
-/* Enter a start condition.  This macro really ought to take a parameter,
- * but we do it the disgusting crufty way forced on us by the ()-less
- * definition of BEGIN.
- */
-#define BEGIN yy_start = 1 + 2 *
-
-/* Translate the current start state into a value that can be later handed
- * to BEGIN to return to the state.  The YYSTATE alias is for lex
- * compatibility.
- */
-#define YY_START ((yy_start - 1) / 2)
-#define YYSTATE YY_START
-
-/* Action number for EOF rule of a given start state. */
-#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
-
-/* Special action meaning "start processing a new file". */
-#define YY_NEW_FILE yyrestart( yyin )
-
-#define YY_END_OF_BUFFER_CHAR 0
-
-/* Size of default input buffer. */
-#define YY_BUF_SIZE 16384
-
-typedef struct yy_buffer_state *YY_BUFFER_STATE;
-
-extern int yyleng;
-extern FILE *yyin, *yyout;
-
-#define EOB_ACT_CONTINUE_SCAN 0
-#define EOB_ACT_END_OF_FILE 1
-#define EOB_ACT_LAST_MATCH 2
-
-/* The funky do-while in the following #define is used to turn the definition
- * int a single C statement (which needs a semi-colon terminator).  This
- * avoids problems with code like:
- *
- * 	if ( condition_holds )
- *		yyless( 5 );
- *	else
- *		do_something_else();
- *
- * Prior to using the do-while the compiler would get upset at the
- * "else" because it interpreted the "if" statement as being all
- * done when it reached the ';' after the yyless() call.
- */
-
-/* Return all but the first 'n' matched characters back to the input stream. */
-
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-		*yy_cp = yy_hold_char; \
-		YY_RESTORE_YY_MORE_OFFSET \
-		yy_c_buf_p = yy_cp = yy_bp + n - YY_MORE_ADJ; \
-		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
-		} \
-	while ( 0 )
-
-#define unput(c) yyunput( c, yytext_ptr )
-
-/* The following is because we cannot portably get our hands on size_t
- * (without autoconf's help, which isn't available because we want
- * flex-generated scanners to compile on their own).
- */
-typedef unsigned int yy_size_t;
-
-
-struct yy_buffer_state
-	{
-	FILE *yy_input_file;
-
-	char *yy_ch_buf;		/* input buffer */
-	char *yy_buf_pos;		/* current position in input buffer */
-
-	/* Size of input buffer in bytes, not including room for EOB
-	 * characters.
-	 */
-	yy_size_t yy_buf_size;
-
-	/* Number of characters read into yy_ch_buf, not including EOB
-	 * characters.
-	 */
-	int yy_n_chars;
-
-	/* Whether we "own" the buffer - i.e., we know we created it,
-	 * and can realloc() it to grow it, and should free() it to
-	 * delete it.
-	 */
-	int yy_is_our_buffer;
-
-	/* Whether this is an "interactive" input source; if so, and
-	 * if we're using stdio for input, then we want to use getc()
-	 * instead of fread(), to make sure we stop fetching input after
-	 * each newline.
-	 */
-	int yy_is_interactive;
-
-	/* Whether we're considered to be at the beginning of a line.
-	 * If so, '^' rules will be active on the next match, otherwise
-	 * not.
-	 */
-	int yy_at_bol;
-
-	/* Whether to try to fill the input buffer when we reach the
-	 * end of it.
-	 */
-	int yy_fill_buffer;
-
-	int yy_buffer_status;
-#define YY_BUFFER_NEW 0
-#define YY_BUFFER_NORMAL 1
-	/* When an EOF's been seen but there's still some text to process
-	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
-	 * shouldn't try reading from the input source any more.  We might
-	 * still have a bunch of tokens to match, though, because of
-	 * possible backing-up.
-	 *
-	 * When we actually see the EOF, we change the status to "new"
-	 * (via yyrestart()), so that the user can continue scanning by
-	 * just pointing yyin at a new input file.
-	 */
-#define YY_BUFFER_EOF_PENDING 2
-	};
-
-static YY_BUFFER_STATE yy_current_buffer = 0;
-
-/* We provide macros for accessing buffer states in case in the
- * future we want to put the buffer states in a more general
- * "scanner state".
- */
-#define YY_CURRENT_BUFFER yy_current_buffer
-
-
-/* yy_hold_char holds the character lost when yytext is formed. */
-static char yy_hold_char;
-
-static int yy_n_chars;		/* number of characters read into yy_ch_buf */
-
-
-int yyleng;
-
-/* Points to current character in buffer. */
-static char *yy_c_buf_p = (char *) 0;
-static int yy_init = 1;		/* whether we need to initialize */
-static int yy_start = 0;	/* start state number */
-
-/* Flag which is used to allow yywrap()'s to do buffer switches
- * instead of setting up a fresh yyin.  A bit of a hack ...
- */
-static int yy_did_buffer_switch_on_eof;
-
-void yyrestart YY_PROTO(( FILE *input_file ));
-
-void yy_switch_to_buffer YY_PROTO(( YY_BUFFER_STATE new_buffer ));
-void yy_load_buffer_state YY_PROTO(( void ));
-YY_BUFFER_STATE yy_create_buffer YY_PROTO(( FILE *file, int size ));
-void yy_delete_buffer YY_PROTO(( YY_BUFFER_STATE b ));
-void yy_init_buffer YY_PROTO(( YY_BUFFER_STATE b, FILE *file ));
-void yy_flush_buffer YY_PROTO(( YY_BUFFER_STATE b ));
-#define YY_FLUSH_BUFFER yy_flush_buffer( yy_current_buffer )
-
-YY_BUFFER_STATE yy_scan_buffer YY_PROTO(( char *base, yy_size_t size ));
-YY_BUFFER_STATE yy_scan_string YY_PROTO(( yyconst char *yy_str ));
-YY_BUFFER_STATE yy_scan_bytes YY_PROTO(( yyconst char *bytes, int len ));
-
-static void *yy_flex_alloc YY_PROTO(( yy_size_t ));
-static void *yy_flex_realloc YY_PROTO(( void *, yy_size_t ));
-static void yy_flex_free YY_PROTO(( void * ));
-
-#define yy_new_buffer yy_create_buffer
-
-#define yy_set_interactive(is_interactive) \
-	{ \
-	if ( ! yy_current_buffer ) \
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
-	yy_current_buffer->yy_is_interactive = is_interactive; \
-	}
-
-#define yy_set_bol(at_bol) \
-	{ \
-	if ( ! yy_current_buffer ) \
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
-	yy_current_buffer->yy_at_bol = at_bol; \
-	}
-
-#define YY_AT_BOL() (yy_current_buffer->yy_at_bol)
-
-typedef unsigned char YY_CHAR;
-FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
-typedef int yy_state_type;
-extern char *yytext;
-#define yytext_ptr yytext
-
-static yy_state_type yy_get_previous_state YY_PROTO(( void ));
-static yy_state_type yy_try_NUL_trans YY_PROTO(( yy_state_type current_state ));
-static int yy_get_next_buffer YY_PROTO(( void ));
-static void yy_fatal_error YY_PROTO(( yyconst char msg[] ));
-
-/* Done after the current pattern has been matched and before the
- * corresponding action - sets up yytext.
- */
-#define YY_DO_BEFORE_ACTION \
-	yytext_ptr = yy_bp; \
-	yyleng = (int) (yy_cp - yy_bp); \
-	yy_hold_char = *yy_cp; \
-	*yy_cp = '\0'; \
-	yy_c_buf_p = yy_cp;
-
-#define YY_NUM_RULES 15
-#define YY_END_OF_BUFFER 16
-static yyconst short int yy_accept[60] =
-    {   0,
-        0,    0,   16,   14,   13,   12,   11,    8,    8,   10,
-       10,   10,   10,   10,   10,   10,   10,   10,   10,   10,
-       10,    8,    0,   10,   10,   10,   10,   10,   10,   10,
-       10,   10,   10,   10,   10,   10,    7,    9,   10,   10,
-       10,   10,   10,   10,   10,   10,   10,   10,   10,   10,
-        5,    1,    2,    3,   10,    6,   10,    4,    0
-    } ;
-
-static yyconst int yy_ec[256] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    4,    1,    1,    5,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    6,    7,    7,
-        7,    7,    7,    7,    7,    7,    7,    1,    8,    1,
-        1,    1,    1,    1,    9,   10,   11,   12,   13,   10,
-       14,   15,   16,   15,   15,   15,   17,   18,   15,   15,
-       15,   19,   20,   15,   15,   15,   15,   15,   15,   15,
-        1,    1,    1,    1,   15,    1,   21,   10,   22,   23,
-
-       24,   10,   25,   15,   26,   15,   15,   15,   27,   28,
-       15,   29,   15,   30,   31,   15,   15,   15,   15,   32,
-       15,   15,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1
-    } ;
-
-static yyconst int yy_meta[33] =
-    {   0,
-        1,    1,    1,    1,    1,    2,    2,    1,    2,    2,
-        2,    2,    2,    3,    3,    3,    3,    3,    3,    3,
-        2,    2,    2,    2,    3,    3,    3,    3,    3,    3,
-        3,    3
-    } ;
-
-static yyconst short int yy_base[62] =
-    {   0,
-        0,    0,   83,   84,   84,   84,   84,   27,   29,   70,
-        0,   62,   61,   60,   20,   55,   47,   46,   45,   12,
-       35,   37,    0,    0,   62,   60,   59,   58,   53,   49,
-       45,   43,   42,   41,   37,   32,    0,    0,   43,   44,
-       43,   42,   42,   36,   23,   27,   26,   25,   25,   20,
-        0,    0,    0,    0,   35,    0,   23,    0,   84,   58,
-       43
-    } ;
-
-static yyconst short int yy_def[62] =
-    {   0,
-       59,    1,   59,   59,   59,   59,   59,   59,   59,   60,
-       60,   60,   60,   60,   60,   60,   60,   60,   60,   60,
-       60,   59,   61,   60,   60,   60,   60,   60,   60,   60,
-       60,   60,   60,   60,   60,   60,   60,   61,   60,   60,
-       60,   60,   60,   60,   60,   60,   60,   60,   60,   60,
-       60,   60,   60,   60,   60,   60,   60,   60,    0,   59,
-       59
-    } ;
-
-static yyconst short int yy_nxt[117] =
-    {   0,
-        4,    5,    6,    5,    7,    8,    9,    7,   10,   11,
-       12,   13,   11,   14,   11,   15,   11,   11,   11,   11,
-       16,   17,   18,   11,   19,   20,   11,   11,   21,   11,
-       11,   11,   22,   22,   22,   22,   29,   30,   35,   36,
-       37,   37,   22,   22,   38,   58,   58,   56,   57,   54,
-       53,   52,   51,   56,   55,   54,   53,   52,   23,   24,
-       24,   51,   50,   49,   48,   47,   46,   45,   44,   43,
-       42,   41,   40,   39,   34,   33,   32,   31,   28,   27,
-       26,   25,   59,    3,   59,   59,   59,   59,   59,   59,
-       59,   59,   59,   59,   59,   59,   59,   59,   59,   59,
-
-       59,   59,   59,   59,   59,   59,   59,   59,   59,   59,
-       59,   59,   59,   59,   59,   59
-    } ;
-
-static yyconst short int yy_chk[117] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    8,    8,    9,    9,   15,   15,   20,   20,
-       21,   21,   22,   22,   61,   57,   55,   50,   49,   48,
-       47,   46,   45,   44,   43,   42,   41,   40,    8,   60,
-       60,   39,   36,   35,   34,   33,   32,   31,   30,   29,
-       28,   27,   26,   25,   19,   18,   17,   16,   14,   13,
-       12,   10,    3,   59,   59,   59,   59,   59,   59,   59,
-       59,   59,   59,   59,   59,   59,   59,   59,   59,   59,
-
-       59,   59,   59,   59,   59,   59,   59,   59,   59,   59,
-       59,   59,   59,   59,   59,   59
-    } ;
-
-static yy_state_type yy_last_accepting_state;
-static char *yy_last_accepting_cpos;
-
-/* The intent behind this definition is that it'll catch
- * any uses of REJECT which flex missed.
- */
-#define REJECT reject_used_but_not_detected
-#define yymore() yymore_used_but_not_detected
-#define YY_MORE_ADJ 0
-#define YY_RESTORE_YY_MORE_OFFSET
-char *yytext;
-#line 1 "itbl-lex.l"
-#define INITIAL 0
-/* itbl-lex.l
-   Copyright 1997, 1998, 2001, 2002, 2005 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful, 
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-#line 22 "itbl-lex.l"
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-
-#include "itbl-lex.h"
-#include <itbl-parse.h>
-
-#ifdef DEBUG
-#define DBG(x) printf x
-#define MDBG(x) printf x
-#else
-#define DBG(x)
-#define MDBG(x)
-#endif
-
-int insntbl_line = 1;
-#line 446 "itbl-lex.c"
-
-/* Macros after this point can all be overridden by user definitions in
- * section 1.
- */
-
-#ifndef YY_SKIP_YYWRAP
-#ifdef __cplusplus
-extern "C" int yywrap YY_PROTO(( void ));
-#else
-extern int yywrap YY_PROTO(( void ));
-#endif
-#endif
-
-#ifndef YY_NO_UNPUT
-static void yyunput YY_PROTO(( int c, char *buf_ptr ));
-#endif
-
-#ifndef yytext_ptr
-static void yy_flex_strncpy YY_PROTO(( char *, yyconst char *, int ));
-#endif
-
-#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen YY_PROTO(( yyconst char * ));
-#endif
-
-#ifndef YY_NO_INPUT
-#ifdef __cplusplus
-static int yyinput YY_PROTO(( void ));
-#else
-static int input YY_PROTO(( void ));
-#endif
-#endif
-
-#if YY_STACK_USED
-static int yy_start_stack_ptr = 0;
-static int yy_start_stack_depth = 0;
-static int *yy_start_stack = 0;
-#ifndef YY_NO_PUSH_STATE
-static void yy_push_state YY_PROTO(( int new_state ));
-#endif
-#ifndef YY_NO_POP_STATE
-static void yy_pop_state YY_PROTO(( void ));
-#endif
-#ifndef YY_NO_TOP_STATE
-static int yy_top_state YY_PROTO(( void ));
-#endif
-
-#else
-#define YY_NO_PUSH_STATE 1
-#define YY_NO_POP_STATE 1
-#define YY_NO_TOP_STATE 1
-#endif
-
-#ifdef YY_MALLOC_DECL
-YY_MALLOC_DECL
-#else
-#if __STDC__
-#ifndef __cplusplus
-#include <stdlib.h>
-#endif
-#else
-/* Just try to get by without declaring the routines.  This will fail
- * miserably on non-ANSI systems for which sizeof(size_t) != sizeof(int)
- * or sizeof(void*) != sizeof(int).
- */
-#endif
-#endif
-
-/* Amount of stuff to slurp up with each read. */
-#ifndef YY_READ_BUF_SIZE
-#define YY_READ_BUF_SIZE 8192
-#endif
-
-/* Copy whatever the last rule matched to the standard output. */
-
-#ifndef ECHO
-/* This used to be an fputs(), but since the string might contain NUL's,
- * we now use fwrite().
- */
-#define ECHO (void) fwrite( yytext, yyleng, 1, yyout )
-#endif
-
-/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
- * is returned in "result".
- */
-#ifndef YY_INPUT
-#define YY_INPUT(buf,result,max_size) \
-	if ( yy_current_buffer->yy_is_interactive ) \
-		{ \
-		int c = '*', n; \
-		for ( n = 0; n < max_size && \
-			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
-			buf[n] = (char) c; \
-		if ( c == '\n' ) \
-			buf[n++] = (char) c; \
-		if ( c == EOF && ferror( yyin ) ) \
-			YY_FATAL_ERROR( "input in flex scanner failed" ); \
-		result = n; \
-		} \
-	else \
-		{ \
-		errno=0; \
-		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
-			{ \
-			if( errno != EINTR) \
-				{ \
-				YY_FATAL_ERROR( "input in flex scanner failed" ); \
-				break; \
-				} \
-			errno=0; \
-			clearerr(yyin); \
-			} \
-		}
-#endif
-
-/* No semi-colon after return; correct usage is to write "yyterminate();" -
- * we don't want an extra ';' after the "return" because that will cause
- * some compilers to complain about unreachable statements.
- */
-#ifndef yyterminate
-#define yyterminate() return YY_NULL
-#endif
-
-/* Number of entries by which start-condition stack grows. */
-#ifndef YY_START_STACK_INCR
-#define YY_START_STACK_INCR 25
-#endif
-
-/* Report a fatal error. */
-#ifndef YY_FATAL_ERROR
-#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
-#endif
-
-/* Default declaration of generated scanner - a define so the user can
- * easily add parameters.
- */
-#ifndef YY_DECL
-#define YY_DECL int yylex YY_PROTO(( void ))
-#endif
-
-/* Code executed at the beginning of each rule, after yytext and yyleng
- * have been set up.
- */
-#ifndef YY_USER_ACTION
-#define YY_USER_ACTION
-#endif
-
-/* Code executed at the end of each rule. */
-#ifndef YY_BREAK
-#define YY_BREAK break;
-#endif
-
-#define YY_RULE_SETUP \
-	YY_USER_ACTION
-
-YY_DECL
-	{
-	register yy_state_type yy_current_state;
-	register char *yy_cp, *yy_bp;
-	register int yy_act;
-
-#line 45 "itbl-lex.l"
-
-
-#line 611 "itbl-lex.c"
-
-	if ( yy_init )
-		{
-		yy_init = 0;
-
-#ifdef YY_USER_INIT
-		YY_USER_INIT;
-#endif
-
-		if ( ! yy_start )
-			yy_start = 1;	/* first start state */
-
-		if ( ! yyin )
-			yyin = stdin;
-
-		if ( ! yyout )
-			yyout = stdout;
-
-		if ( ! yy_current_buffer )
-			yy_current_buffer =
-				yy_create_buffer( yyin, YY_BUF_SIZE );
-
-		yy_load_buffer_state();
-		}
-
-	while ( 1 )		/* loops until end-of-file is reached */
-		{
-		yy_cp = yy_c_buf_p;
-
-		/* Support of yytext. */
-		*yy_cp = yy_hold_char;
-
-		/* yy_bp points to the position in yy_ch_buf of the start of
-		 * the current run.
-		 */
-		yy_bp = yy_cp;
-
-		yy_current_state = yy_start;
-yy_match:
-		do
-			{
-			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
-			if ( yy_accept[yy_current_state] )
-				{
-				yy_last_accepting_state = yy_current_state;
-				yy_last_accepting_cpos = yy_cp;
-				}
-			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-				{
-				yy_current_state = (int) yy_def[yy_current_state];
-				if ( yy_current_state >= 60 )
-					yy_c = yy_meta[(unsigned int) yy_c];
-				}
-			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-			++yy_cp;
-			}
-		while ( yy_base[yy_current_state] != 84 );
-
-yy_find_action:
-		yy_act = yy_accept[yy_current_state];
-		if ( yy_act == 0 )
-			{ /* have to back up */
-			yy_cp = yy_last_accepting_cpos;
-			yy_current_state = yy_last_accepting_state;
-			yy_act = yy_accept[yy_current_state];
-			}
-
-		YY_DO_BEFORE_ACTION;
-
-
-do_action:	/* This label is used only to access EOF actions. */
-
-
-		switch ( yy_act )
-	{ /* beginning of action switch */
-			case 0: /* must back up */
-			/* undo the effects of YY_DO_BEFORE_ACTION */
-			*yy_cp = yy_hold_char;
-			yy_cp = yy_last_accepting_cpos;
-			yy_current_state = yy_last_accepting_state;
-			goto yy_find_action;
-
-case 1:
-YY_RULE_SETUP
-#line 47 "itbl-lex.l"
-{
-    return CREG;
-  }
-	YY_BREAK
-case 2:
-YY_RULE_SETUP
-#line 50 "itbl-lex.l"
-{
-    return DREG;
-  }
-	YY_BREAK
-case 3:
-YY_RULE_SETUP
-#line 53 "itbl-lex.l"
-{
-    return GREG;
-  }
-	YY_BREAK
-case 4:
-YY_RULE_SETUP
-#line 56 "itbl-lex.l"
-{
-    return IMMED;
-  }
-	YY_BREAK
-case 5:
-YY_RULE_SETUP
-#line 59 "itbl-lex.l"
-{
-    return ADDR;
-  }
-	YY_BREAK
-case 6:
-YY_RULE_SETUP
-#line 62 "itbl-lex.l"
-{
-    return INSN;
-  }
-	YY_BREAK
-case 7:
-YY_RULE_SETUP
-#line 65 "itbl-lex.l"
-{
-    yytext[yyleng] = 0;
-    yylval.processor = strtoul (yytext+1, 0, 0);
-    return PNUM;
-  }
-	YY_BREAK
-case 8:
-YY_RULE_SETUP
-#line 70 "itbl-lex.l"
-{
-    yytext[yyleng] = 0;
-    yylval.num = strtoul (yytext, 0, 0);
-    return NUM;
-  }
-	YY_BREAK
-case 9:
-YY_RULE_SETUP
-#line 75 "itbl-lex.l"
-{
-    yytext[yyleng] = 0;
-    yylval.num = strtoul (yytext, 0, 0);
-    return NUM;
-  }
-	YY_BREAK
-case 10:
-YY_RULE_SETUP
-#line 80 "itbl-lex.l"
-{
-    yytext[yyleng] = 0;
-    yylval.str = strdup (yytext);
-    return ID;
-  }
-	YY_BREAK
-case 11:
-YY_RULE_SETUP
-#line 85 "itbl-lex.l"
-{
-    int c;
-    while ((c = input ()) !=  EOF) 
-      {
-        if (c ==  '\n') 
-    	{
-    		unput (c);
-    		break;
-    	}
-      }
-  }
-	YY_BREAK
-case 12:
-YY_RULE_SETUP
-#line 96 "itbl-lex.l"
-{ 
-    insntbl_line++; 
-    MDBG (("in lex, NL = %d (x%x)\n", NL, NL));
-    return NL; 
-  }
-	YY_BREAK
-case 13:
-YY_RULE_SETUP
-#line 101 "itbl-lex.l"
-{ 
-  }
-	YY_BREAK
-case 14:
-YY_RULE_SETUP
-#line 103 "itbl-lex.l"
-{
-    MDBG (("char = %x, %d\n", yytext[0], yytext[0]));
-    return yytext[0];
-  }
-	YY_BREAK
-case 15:
-YY_RULE_SETUP
-#line 107 "itbl-lex.l"
-ECHO;
-	YY_BREAK
-#line 815 "itbl-lex.c"
-case YY_STATE_EOF(INITIAL):
-	yyterminate();
-
-	case YY_END_OF_BUFFER:
-		{
-		/* Amount of text matched not including the EOB char. */
-		int yy_amount_of_matched_text = (int) (yy_cp - yytext_ptr) - 1;
-
-		/* Undo the effects of YY_DO_BEFORE_ACTION. */
-		*yy_cp = yy_hold_char;
-		YY_RESTORE_YY_MORE_OFFSET
-
-		if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_NEW )
-			{
-			/* We're scanning a new file or input source.  It's
-			 * possible that this happened because the user
-			 * just pointed yyin at a new source and called
-			 * yylex().  If so, then we have to assure
-			 * consistency between yy_current_buffer and our
-			 * globals.  Here is the right place to do so, because
-			 * this is the first action (other than possibly a
-			 * back-up) that will match for the new input source.
-			 */
-			yy_n_chars = yy_current_buffer->yy_n_chars;
-			yy_current_buffer->yy_input_file = yyin;
-			yy_current_buffer->yy_buffer_status = YY_BUFFER_NORMAL;
-			}
-
-		/* Note that here we test for yy_c_buf_p "<=" to the position
-		 * of the first EOB in the buffer, since yy_c_buf_p will
-		 * already have been incremented past the NUL character
-		 * (since all states make transitions on EOB to the
-		 * end-of-buffer state).  Contrast this with the test
-		 * in input().
-		 */
-		if ( yy_c_buf_p <= &yy_current_buffer->yy_ch_buf[yy_n_chars] )
-			{ /* This was really a NUL. */
-			yy_state_type yy_next_state;
-
-			yy_c_buf_p = yytext_ptr + yy_amount_of_matched_text;
-
-			yy_current_state = yy_get_previous_state();
-
-			/* Okay, we're now positioned to make the NUL
-			 * transition.  We couldn't have
-			 * yy_get_previous_state() go ahead and do it
-			 * for us because it doesn't know how to deal
-			 * with the possibility of jamming (and we don't
-			 * want to build jamming into it because then it
-			 * will run more slowly).
-			 */
-
-			yy_next_state = yy_try_NUL_trans( yy_current_state );
-
-			yy_bp = yytext_ptr + YY_MORE_ADJ;
-
-			if ( yy_next_state )
-				{
-				/* Consume the NUL. */
-				yy_cp = ++yy_c_buf_p;
-				yy_current_state = yy_next_state;
-				goto yy_match;
-				}
-
-			else
-				{
-				yy_cp = yy_c_buf_p;
-				goto yy_find_action;
-				}
-			}
-
-		else switch ( yy_get_next_buffer() )
-			{
-			case EOB_ACT_END_OF_FILE:
-				{
-				yy_did_buffer_switch_on_eof = 0;
-
-				if ( yywrap() )
-					{
-					/* Note: because we've taken care in
-					 * yy_get_next_buffer() to have set up
-					 * yytext, we can now set up
-					 * yy_c_buf_p so that if some total
-					 * hoser (like flex itself) wants to
-					 * call the scanner after we return the
-					 * YY_NULL, it'll still work - another
-					 * YY_NULL will get returned.
-					 */
-					yy_c_buf_p = yytext_ptr + YY_MORE_ADJ;
-
-					yy_act = YY_STATE_EOF(YY_START);
-					goto do_action;
-					}
-
-				else
-					{
-					if ( ! yy_did_buffer_switch_on_eof )
-						YY_NEW_FILE;
-					}
-				break;
-				}
-
-			case EOB_ACT_CONTINUE_SCAN:
-				yy_c_buf_p =
-					yytext_ptr + yy_amount_of_matched_text;
-
-				yy_current_state = yy_get_previous_state();
-
-				yy_cp = yy_c_buf_p;
-				yy_bp = yytext_ptr + YY_MORE_ADJ;
-				goto yy_match;
-
-			case EOB_ACT_LAST_MATCH:
-				yy_c_buf_p =
-				&yy_current_buffer->yy_ch_buf[yy_n_chars];
-
-				yy_current_state = yy_get_previous_state();
-
-				yy_cp = yy_c_buf_p;
-				yy_bp = yytext_ptr + YY_MORE_ADJ;
-				goto yy_find_action;
-			}
-		break;
-		}
-
-	default:
-		YY_FATAL_ERROR(
-			"fatal flex scanner internal error--no action found" );
-	} /* end of action switch */
-		} /* end of scanning one token */
-	} /* end of yylex */
-
-
-/* yy_get_next_buffer - try to read in a new buffer
- *
- * Returns a code representing an action:
- *	EOB_ACT_LAST_MATCH -
- *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
- *	EOB_ACT_END_OF_FILE - end of file
- */
-
-static int yy_get_next_buffer()
-	{
-	register char *dest = yy_current_buffer->yy_ch_buf;
-	register char *source = yytext_ptr;
-	register int number_to_move, i;
-	int ret_val;
-
-	if ( yy_c_buf_p > &yy_current_buffer->yy_ch_buf[yy_n_chars + 1] )
-		YY_FATAL_ERROR(
-		"fatal flex scanner internal error--end of buffer missed" );
-
-	if ( yy_current_buffer->yy_fill_buffer == 0 )
-		{ /* Don't try to fill the buffer, so this is an EOF. */
-		if ( yy_c_buf_p - yytext_ptr - YY_MORE_ADJ == 1 )
-			{
-			/* We matched a single character, the EOB, so
-			 * treat this as a final EOF.
-			 */
-			return EOB_ACT_END_OF_FILE;
-			}
-
-		else
-			{
-			/* We matched some text prior to the EOB, first
-			 * process it.
-			 */
-			return EOB_ACT_LAST_MATCH;
-			}
-		}
-
-	/* Try to read more data. */
-
-	/* First move last chars to start of buffer. */
-	number_to_move = (int) (yy_c_buf_p - yytext_ptr) - 1;
-
-	for ( i = 0; i < number_to_move; ++i )
-		*(dest++) = *(source++);
-
-	if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_EOF_PENDING )
-		/* don't do the read, it's not guaranteed to return an EOF,
-		 * just force an EOF
-		 */
-		yy_current_buffer->yy_n_chars = yy_n_chars = 0;
-
-	else
-		{
-		int num_to_read =
-			yy_current_buffer->yy_buf_size - number_to_move - 1;
-
-		while ( num_to_read <= 0 )
-			{ /* Not enough room in the buffer - grow it. */
-#ifdef YY_USES_REJECT
-			YY_FATAL_ERROR(
-"input buffer overflow, can't enlarge buffer because scanner uses REJECT" );
-#else
-
-			/* just a shorter name for the current buffer */
-			YY_BUFFER_STATE b = yy_current_buffer;
-
-			int yy_c_buf_p_offset =
-				(int) (yy_c_buf_p - b->yy_ch_buf);
-
-			if ( b->yy_is_our_buffer )
-				{
-				int new_size = b->yy_buf_size * 2;
-
-				if ( new_size <= 0 )
-					b->yy_buf_size += b->yy_buf_size / 8;
-				else
-					b->yy_buf_size *= 2;
-
-				b->yy_ch_buf = (char *)
-					/* Include room in for 2 EOB chars. */
-					yy_flex_realloc( (void *) b->yy_ch_buf,
-							 b->yy_buf_size + 2 );
-				}
-			else
-				/* Can't grow it, we don't own it. */
-				b->yy_ch_buf = 0;
-
-			if ( ! b->yy_ch_buf )
-				YY_FATAL_ERROR(
-				"fatal error - scanner input buffer overflow" );
-
-			yy_c_buf_p = &b->yy_ch_buf[yy_c_buf_p_offset];
-
-			num_to_read = yy_current_buffer->yy_buf_size -
-						number_to_move - 1;
-#endif
-			}
-
-		if ( num_to_read > YY_READ_BUF_SIZE )
-			num_to_read = YY_READ_BUF_SIZE;
-
-		/* Read in more data. */
-		YY_INPUT( (&yy_current_buffer->yy_ch_buf[number_to_move]),
-			yy_n_chars, num_to_read );
-
-		yy_current_buffer->yy_n_chars = yy_n_chars;
-		}
-
-	if ( yy_n_chars == 0 )
-		{
-		if ( number_to_move == YY_MORE_ADJ )
-			{
-			ret_val = EOB_ACT_END_OF_FILE;
-			yyrestart( yyin );
-			}
-
-		else
-			{
-			ret_val = EOB_ACT_LAST_MATCH;
-			yy_current_buffer->yy_buffer_status =
-				YY_BUFFER_EOF_PENDING;
-			}
-		}
-
-	else
-		ret_val = EOB_ACT_CONTINUE_SCAN;
-
-	yy_n_chars += number_to_move;
-	yy_current_buffer->yy_ch_buf[yy_n_chars] = YY_END_OF_BUFFER_CHAR;
-	yy_current_buffer->yy_ch_buf[yy_n_chars + 1] = YY_END_OF_BUFFER_CHAR;
-
-	yytext_ptr = &yy_current_buffer->yy_ch_buf[0];
-
-	return ret_val;
-	}
-
-
-/* yy_get_previous_state - get the state just before the EOB char was reached */
-
-static yy_state_type yy_get_previous_state()
-	{
-	register yy_state_type yy_current_state;
-	register char *yy_cp;
-
-	yy_current_state = yy_start;
-
-	for ( yy_cp = yytext_ptr + YY_MORE_ADJ; yy_cp < yy_c_buf_p; ++yy_cp )
-		{
-		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
-		if ( yy_accept[yy_current_state] )
-			{
-			yy_last_accepting_state = yy_current_state;
-			yy_last_accepting_cpos = yy_cp;
-			}
-		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-			{
-			yy_current_state = (int) yy_def[yy_current_state];
-			if ( yy_current_state >= 60 )
-				yy_c = yy_meta[(unsigned int) yy_c];
-			}
-		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-		}
-
-	return yy_current_state;
-	}
-
-
-/* yy_try_NUL_trans - try to make a transition on the NUL character
- *
- * synopsis
- *	next_state = yy_try_NUL_trans( current_state );
- */
-
-#ifdef YY_USE_PROTOS
-static yy_state_type yy_try_NUL_trans( yy_state_type yy_current_state )
-#else
-static yy_state_type yy_try_NUL_trans( yy_current_state )
-yy_state_type yy_current_state;
-#endif
-	{
-	register int yy_is_jam;
-	register char *yy_cp = yy_c_buf_p;
-
-	register YY_CHAR yy_c = 1;
-	if ( yy_accept[yy_current_state] )
-		{
-		yy_last_accepting_state = yy_current_state;
-		yy_last_accepting_cpos = yy_cp;
-		}
-	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-		{
-		yy_current_state = (int) yy_def[yy_current_state];
-		if ( yy_current_state >= 60 )
-			yy_c = yy_meta[(unsigned int) yy_c];
-		}
-	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-	yy_is_jam = (yy_current_state == 59);
-
-	return yy_is_jam ? 0 : yy_current_state;
-	}
-
-
-#ifndef YY_NO_UNPUT
-#ifdef YY_USE_PROTOS
-static void yyunput( int c, register char *yy_bp )
-#else
-static void yyunput( c, yy_bp )
-int c;
-register char *yy_bp;
-#endif
-	{
-	register char *yy_cp = yy_c_buf_p;
-
-	/* undo effects of setting up yytext */
-	*yy_cp = yy_hold_char;
-
-	if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
-		{ /* need to shift things up to make room */
-		/* +2 for EOB chars. */
-		register int number_to_move = yy_n_chars + 2;
-		register char *dest = &yy_current_buffer->yy_ch_buf[
-					yy_current_buffer->yy_buf_size + 2];
-		register char *source =
-				&yy_current_buffer->yy_ch_buf[number_to_move];
-
-		while ( source > yy_current_buffer->yy_ch_buf )
-			*--dest = *--source;
-
-		yy_cp += (int) (dest - source);
-		yy_bp += (int) (dest - source);
-		yy_current_buffer->yy_n_chars =
-			yy_n_chars = yy_current_buffer->yy_buf_size;
-
-		if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
-			YY_FATAL_ERROR( "flex scanner push-back overflow" );
-		}
-
-	*--yy_cp = (char) c;
-
-
-	yytext_ptr = yy_bp;
-	yy_hold_char = *yy_cp;
-	yy_c_buf_p = yy_cp;
-	}
-#endif	/* ifndef YY_NO_UNPUT */
-
-
-#ifdef __cplusplus
-static int yyinput()
-#else
-static int input()
-#endif
-	{
-	int c;
-
-	*yy_c_buf_p = yy_hold_char;
-
-	if ( *yy_c_buf_p == YY_END_OF_BUFFER_CHAR )
-		{
-		/* yy_c_buf_p now points to the character we want to return.
-		 * If this occurs *before* the EOB characters, then it's a
-		 * valid NUL; if not, then we've hit the end of the buffer.
-		 */
-		if ( yy_c_buf_p < &yy_current_buffer->yy_ch_buf[yy_n_chars] )
-			/* This was really a NUL. */
-			*yy_c_buf_p = '\0';
-
-		else
-			{ /* need more input */
-			int offset = yy_c_buf_p - yytext_ptr;
-			++yy_c_buf_p;
-
-			switch ( yy_get_next_buffer() )
-				{
-				case EOB_ACT_LAST_MATCH:
-					/* This happens because yy_g_n_b()
-					 * sees that we've accumulated a
-					 * token and flags that we need to
-					 * try matching the token before
-					 * proceeding.  But for input(),
-					 * there's no matching to consider.
-					 * So convert the EOB_ACT_LAST_MATCH
-					 * to EOB_ACT_END_OF_FILE.
-					 */
-
-					/* Reset buffer status. */
-					yyrestart( yyin );
-
-					/* fall through */
-
-				case EOB_ACT_END_OF_FILE:
-					{
-					if ( yywrap() )
-						return EOF;
-
-					if ( ! yy_did_buffer_switch_on_eof )
-						YY_NEW_FILE;
-#ifdef __cplusplus
-					return yyinput();
-#else
-					return input();
-#endif
-					}
-
-				case EOB_ACT_CONTINUE_SCAN:
-					yy_c_buf_p = yytext_ptr + offset;
-					break;
-				}
-			}
-		}
-
-	c = *(unsigned char *) yy_c_buf_p;	/* cast for 8-bit char's */
-	*yy_c_buf_p = '\0';	/* preserve yytext */
-	yy_hold_char = *++yy_c_buf_p;
-
-
-	return c;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yyrestart( FILE *input_file )
-#else
-void yyrestart( input_file )
-FILE *input_file;
-#endif
-	{
-	if ( ! yy_current_buffer )
-		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE );
-
-	yy_init_buffer( yy_current_buffer, input_file );
-	yy_load_buffer_state();
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_switch_to_buffer( YY_BUFFER_STATE new_buffer )
-#else
-void yy_switch_to_buffer( new_buffer )
-YY_BUFFER_STATE new_buffer;
-#endif
-	{
-	if ( yy_current_buffer == new_buffer )
-		return;
-
-	if ( yy_current_buffer )
-		{
-		/* Flush out information for old buffer. */
-		*yy_c_buf_p = yy_hold_char;
-		yy_current_buffer->yy_buf_pos = yy_c_buf_p;
-		yy_current_buffer->yy_n_chars = yy_n_chars;
-		}
-
-	yy_current_buffer = new_buffer;
-	yy_load_buffer_state();
-
-	/* We don't actually know whether we did this switch during
-	 * EOF (yywrap()) processing, but the only time this flag
-	 * is looked at is after yywrap() is called, so it's safe
-	 * to go ahead and always set it.
-	 */
-	yy_did_buffer_switch_on_eof = 1;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_load_buffer_state( void )
-#else
-void yy_load_buffer_state()
-#endif
-	{
-	yy_n_chars = yy_current_buffer->yy_n_chars;
-	yytext_ptr = yy_c_buf_p = yy_current_buffer->yy_buf_pos;
-	yyin = yy_current_buffer->yy_input_file;
-	yy_hold_char = *yy_c_buf_p;
-	}
-
-
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_create_buffer( FILE *file, int size )
-#else
-YY_BUFFER_STATE yy_create_buffer( file, size )
-FILE *file;
-int size;
-#endif
-	{
-	YY_BUFFER_STATE b;
-
-	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_buf_size = size;
-
-	/* yy_ch_buf has to be 2 characters longer than the size given because
-	 * we need to put in 2 end-of-buffer characters.
-	 */
-	b->yy_ch_buf = (char *) yy_flex_alloc( b->yy_buf_size + 2 );
-	if ( ! b->yy_ch_buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_is_our_buffer = 1;
-
-	yy_init_buffer( b, file );
-
-	return b;
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_delete_buffer( YY_BUFFER_STATE b )
-#else
-void yy_delete_buffer( b )
-YY_BUFFER_STATE b;
-#endif
-	{
-	if ( ! b )
-		return;
-
-	if ( b == yy_current_buffer )
-		yy_current_buffer = (YY_BUFFER_STATE) 0;
-
-	if ( b->yy_is_our_buffer )
-		yy_flex_free( (void *) b->yy_ch_buf );
-
-	yy_flex_free( (void *) b );
-	}
-
-
-#ifndef _WIN32
-#include <unistd.h>
-#else
-#ifndef YY_ALWAYS_INTERACTIVE
-#ifndef YY_NEVER_INTERACTIVE
-extern int isatty YY_PROTO(( int ));
-#endif
-#endif
-#endif
-
-#ifdef YY_USE_PROTOS
-void yy_init_buffer( YY_BUFFER_STATE b, FILE *file )
-#else
-void yy_init_buffer( b, file )
-YY_BUFFER_STATE b;
-FILE *file;
-#endif
-
-
-	{
-	yy_flush_buffer( b );
-
-	b->yy_input_file = file;
-	b->yy_fill_buffer = 1;
-
-#if YY_ALWAYS_INTERACTIVE
-	b->yy_is_interactive = 1;
-#else
-#if YY_NEVER_INTERACTIVE
-	b->yy_is_interactive = 0;
-#else
-	b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
-#endif
-#endif
-	}
-
-
-#ifdef YY_USE_PROTOS
-void yy_flush_buffer( YY_BUFFER_STATE b )
-#else
-void yy_flush_buffer( b )
-YY_BUFFER_STATE b;
-#endif
-
-	{
-	if ( ! b )
-		return;
-
-	b->yy_n_chars = 0;
-
-	/* We always need two end-of-buffer characters.  The first causes
-	 * a transition to the end-of-buffer state.  The second causes
-	 * a jam in that state.
-	 */
-	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
-	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
-
-	b->yy_buf_pos = &b->yy_ch_buf[0];
-
-	b->yy_at_bol = 1;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	if ( b == yy_current_buffer )
-		yy_load_buffer_state();
-	}
-
-
-#ifndef YY_NO_SCAN_BUFFER
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_buffer( char *base, yy_size_t size )
-#else
-YY_BUFFER_STATE yy_scan_buffer( base, size )
-char *base;
-yy_size_t size;
-#endif
-	{
-	YY_BUFFER_STATE b;
-
-	if ( size < 2 ||
-	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
-	     base[size-1] != YY_END_OF_BUFFER_CHAR )
-		/* They forgot to leave room for the EOB's. */
-		return 0;
-
-	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
-
-	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
-	b->yy_buf_pos = b->yy_ch_buf = base;
-	b->yy_is_our_buffer = 0;
-	b->yy_input_file = 0;
-	b->yy_n_chars = b->yy_buf_size;
-	b->yy_is_interactive = 0;
-	b->yy_at_bol = 1;
-	b->yy_fill_buffer = 0;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	yy_switch_to_buffer( b );
-
-	return b;
-	}
-#endif
-
-
-#ifndef YY_NO_SCAN_STRING
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_string( yyconst char *yy_str )
-#else
-YY_BUFFER_STATE yy_scan_string( yy_str )
-yyconst char *yy_str;
-#endif
-	{
-	int len;
-	for ( len = 0; yy_str[len]; ++len )
-		;
-
-	return yy_scan_bytes( yy_str, len );
-	}
-#endif
-
-
-#ifndef YY_NO_SCAN_BYTES
-#ifdef YY_USE_PROTOS
-YY_BUFFER_STATE yy_scan_bytes( yyconst char *bytes, int len )
-#else
-YY_BUFFER_STATE yy_scan_bytes( bytes, len )
-yyconst char *bytes;
-int len;
-#endif
-	{
-	YY_BUFFER_STATE b;
-	char *buf;
-	yy_size_t n;
-	int i;
-
-	/* Get memory for full buffer, including space for trailing EOB's. */
-	n = len + 2;
-	buf = (char *) yy_flex_alloc( n );
-	if ( ! buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
-
-	for ( i = 0; i < len; ++i )
-		buf[i] = bytes[i];
-
-	buf[len] = buf[len+1] = YY_END_OF_BUFFER_CHAR;
-
-	b = yy_scan_buffer( buf, n );
-	if ( ! b )
-		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
-
-	/* It's okay to grow etc. this buffer, and we should throw it
-	 * away when we're done.
-	 */
-	b->yy_is_our_buffer = 1;
-
-	return b;
-	}
-#endif
-
-
-#ifndef YY_NO_PUSH_STATE
-#ifdef YY_USE_PROTOS
-static void yy_push_state( int new_state )
-#else
-static void yy_push_state( new_state )
-int new_state;
-#endif
-	{
-	if ( yy_start_stack_ptr >= yy_start_stack_depth )
-		{
-		yy_size_t new_size;
-
-		yy_start_stack_depth += YY_START_STACK_INCR;
-		new_size = yy_start_stack_depth * sizeof( int );
-
-		if ( ! yy_start_stack )
-			yy_start_stack = (int *) yy_flex_alloc( new_size );
-
-		else
-			yy_start_stack = (int *) yy_flex_realloc(
-					(void *) yy_start_stack, new_size );
-
-		if ( ! yy_start_stack )
-			YY_FATAL_ERROR(
-			"out of memory expanding start-condition stack" );
-		}
-
-	yy_start_stack[yy_start_stack_ptr++] = YY_START;
-
-	BEGIN(new_state);
-	}
-#endif
-
-
-#ifndef YY_NO_POP_STATE
-static void yy_pop_state()
-	{
-	if ( --yy_start_stack_ptr < 0 )
-		YY_FATAL_ERROR( "start-condition stack underflow" );
-
-	BEGIN(yy_start_stack[yy_start_stack_ptr]);
-	}
-#endif
-
-
-#ifndef YY_NO_TOP_STATE
-static int yy_top_state()
-	{
-	return yy_start_stack[yy_start_stack_ptr - 1];
-	}
-#endif
-
-#ifndef YY_EXIT_FAILURE
-#define YY_EXIT_FAILURE 2
-#endif
-
-#ifdef YY_USE_PROTOS
-static void yy_fatal_error( yyconst char msg[] )
-#else
-static void yy_fatal_error( msg )
-char msg[];
-#endif
-	{
-	(void) fprintf( stderr, "%s\n", msg );
-	exit( YY_EXIT_FAILURE );
-	}
-
-
-
-/* Redefine yyless() so it works in section 3 code. */
-
-#undef yyless
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-		yytext[yyleng] = yy_hold_char; \
-		yy_c_buf_p = yytext + n; \
-		yy_hold_char = *yy_c_buf_p; \
-		*yy_c_buf_p = '\0'; \
-		yyleng = n; \
-		} \
-	while ( 0 )
-
-
-/* Internal utility routines. */
-
-#ifndef yytext_ptr
-#ifdef YY_USE_PROTOS
-static void yy_flex_strncpy( char *s1, yyconst char *s2, int n )
-#else
-static void yy_flex_strncpy( s1, s2, n )
-char *s1;
-yyconst char *s2;
-int n;
-#endif
-	{
-	register int i;
-	for ( i = 0; i < n; ++i )
-		s1[i] = s2[i];
-	}
-#endif
-
-#ifdef YY_NEED_STRLEN
-#ifdef YY_USE_PROTOS
-static int yy_flex_strlen( yyconst char *s )
-#else
-static int yy_flex_strlen( s )
-yyconst char *s;
-#endif
-	{
-	register int n;
-	for ( n = 0; s[n]; ++n )
-		;
-
-	return n;
-	}
-#endif
-
-
-#ifdef YY_USE_PROTOS
-static void *yy_flex_alloc( yy_size_t size )
-#else
-static void *yy_flex_alloc( size )
-yy_size_t size;
-#endif
-	{
-	return (void *) malloc( size );
-	}
-
-#ifdef YY_USE_PROTOS
-static void *yy_flex_realloc( void *ptr, yy_size_t size )
-#else
-static void *yy_flex_realloc( ptr, size )
-void *ptr;
-yy_size_t size;
-#endif
-	{
-	/* The cast to (char *) in the following accommodates both
-	 * implementations that use char* generic pointers, and those
-	 * that use void* generic pointers.  It works with the latter
-	 * because both ANSI C and C++ allow castless assignment from
-	 * any pointer type to void*, and deal with argument conversions
-	 * as though doing an assignment.
-	 */
-	return (void *) realloc( (char *) ptr, size );
-	}
-
-#ifdef YY_USE_PROTOS
-static void yy_flex_free( void *ptr )
-#else
-static void yy_flex_free( ptr )
-void *ptr;
-#endif
-	{
-	free( ptr );
-	}
-
-#if YY_MAIN
-int main()
-	{
-	yylex();
-	return 0;
-	}
-#endif
-#line 107 "itbl-lex.l"
-
-
-#ifndef yywrap
-int 
-yywrap () 
-  { 
-    return 1; 
-  }
-#endif
diff --git a/gas/itbl-lex.l b/gas/itbl-lex.l
index aceeac4f9f03..185f956ecead 100644
--- a/gas/itbl-lex.l
+++ b/gas/itbl-lex.l
@@ -1,5 +1,6 @@
 /* itbl-lex.l
-   Copyright 1997, 1998, 2001, 2002, 2005 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2001, 2002, 2005, 2006
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,10 +20,7 @@
    02110-1301, USA.  */
 
 %{
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
-
+#include "as.h"
 #include "itbl-lex.h"
 #include <itbl-parse.h>
 
diff --git a/gas/itbl-ops.c b/gas/itbl-ops.c
index bd1f6473f45c..41fa0335e1b8 100644
--- a/gas/itbl-ops.c
+++ b/gas/itbl-ops.c
@@ -1,5 +1,5 @@
 /* itbl-ops.c
-   Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005
+   Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -89,9 +89,7 @@
  *
  */
 
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
+#include "as.h"
 #include "itbl-ops.h"
 #include <itbl-parse.h>
 
@@ -147,12 +145,7 @@ struct itbl_entry {
 
 static int itbl_num_opcodes = 0;
 /* Array of entries for each processor and entry type */
-static struct itbl_entry *entries[e_nprocs][e_ntypes] = {
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0},
-  {0, 0, 0, 0, 0, 0}
-};
+static struct itbl_entry *entries[e_nprocs][e_ntypes];
 
 /* local prototypes */
 static unsigned long build_opcode (struct itbl_entry *e);
@@ -253,8 +246,6 @@ itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
 /* Interfaces for assembler and disassembler */
 
 #ifndef STAND_ALONE
-#include "as.h"
-#include "symbols.h"
 static void append_insns_as_macros (void);
 
 /* Initialize for gas.  */
diff --git a/gas/itbl-ops.h b/gas/itbl-ops.h
index 47dc8b295b19..d9dbf7c3ca47 100644
--- a/gas/itbl-ops.h
+++ b/gas/itbl-ops.h
@@ -1,5 +1,5 @@
 /* itbl-ops.h
-   Copyright 1997, 1999, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1997, 1999, 2000, 2003, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -20,14 +20,6 @@
 
 /* External functions, constants and defines for itbl support */
 
-#include "ansidecl.h"
-
-/* Include file notes: "expr.h" needed before targ-*.h,
- * "targ-env.h" includes the chain of target dependant headers,
- * "targ-cpu.h" has the HAVE_ITBL_CPU define, and
- * as.h includes them all */
-#include "as.h"
-
 #ifdef HAVE_ITBL_CPU
 #include "itbl-cpu.h"
 #endif
@@ -77,7 +69,7 @@ typedef enum
 typedef enum
   {
     e_p0,
-    e_nprocs = NUMBER_OF_PROCESSORS,
+    e_nprocs = ITBL_NUMBER_OF_PROCESSORS,
     e_invproc			/* invalid processor */
   } e_processor;
 
diff --git a/gas/itbl-parse.c b/gas/itbl-parse.c
deleted file mode 100644
index 0fd788f0521f..000000000000
--- a/gas/itbl-parse.c
+++ /dev/null
@@ -1,1842 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.1.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Written by Richard Stallman by simplifying the original so called
-   ``semantic'' parser.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
-
-/* Identify Bison output.  */
-#define YYBISON 1
-
-/* Bison version.  */
-#define YYBISON_VERSION "2.1"
-
-/* Skeleton name.  */
-#define YYSKELETON_NAME "yacc.c"
-
-/* Pure parsers.  */
-#define YYPURE 0
-
-/* Using locations.  */
-#define YYLSP_NEEDED 0
-
-
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     DREG = 258,
-     CREG = 259,
-     GREG = 260,
-     IMMED = 261,
-     ADDR = 262,
-     INSN = 263,
-     NUM = 264,
-     ID = 265,
-     NL = 266,
-     PNUM = 267
-   };
-#endif
-/* Tokens.  */
-#define DREG 258
-#define CREG 259
-#define GREG 260
-#define IMMED 261
-#define ADDR 262
-#define INSN 263
-#define NUM 264
-#define ID 265
-#define NL 266
-#define PNUM 267
-
-
-
-
-/* Copy the first part of user declarations.  */
-#line 21 "itbl-parse.y"
-
-
-/* 
-
-Yacc grammar for instruction table entries.
-
-=======================================================================
-Original Instruction table specification document:
-
-	    MIPS Coprocessor Table Specification
-	    ====================================
-
-This document describes the format of the MIPS coprocessor table.  The
-table specifies a list of valid functions, data registers and control
-registers that can be used in coprocessor instructions.  This list,
-together with the coprocessor instruction classes listed below,
-specifies the complete list of coprocessor instructions that will
-be recognized and assembled by the GNU assembler.  In effect,
-this makes the GNU assembler table-driven, where the table is
-specified by the programmer.
-
-The table is an ordinary text file that the GNU assembler reads when
-it starts.  Using the information in the table, the assembler
-generates an internal list of valid coprocessor registers and
-functions.  The assembler uses this internal list in addition to the
-standard MIPS registers and instructions which are built-in to the 
-assembler during code generation.
-
-To specify the coprocessor table when invoking the GNU assembler, use
-the command line option "--itbl file", where file is the
-complete name of the table, including path and extension.
-
-Examples:
-
-	    gas -t cop.tbl test.s -o test.o
-	    gas -t /usr/local/lib/cop.tbl test.s -o test.o
-	    gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
-
-Only one table may be supplied during a single invocation of
-the assembler.
-
-
-Instruction classes
-===================
-
-Below is a list of the valid coprocessor instruction classes for
-any given coprocessor "z".  These instructions are already recognized
-by the assembler, and are listed here only for reference.
-
-Class   format	    	    	      instructions
--------------------------------------------------
-Class1:
-	op base rt offset
-	    	    	    	    	    	    	    LWCz rt,offset (base)
-	    	    	    	    	    	    	    SWCz rt,offset (base)
-Class2:
-	COPz sub rt rd 0
-	    	    	    	    	    	    	    MTCz rt,rd
-	    	    	    	    	    	    	    MFCz rt,rd
-	    	    	    	    	    	    	    CTCz rt,rd
-	    	    	    	    	    	    	    CFCz rt,rd
-Class3:
-	COPz CO cofun
-	    	    	    	    	    	    	    COPz cofun
-Class4:
-	COPz BC br offset
-	    	    	    	    	    	    	    BCzT offset
-	    	    	    	    	    	    	    BCzF offset
-Class5:
-	COPz sub rt rd 0
-	    	    	    	    	    	    	    DMFCz rt,rd
-	    	    	    	    	    	    	    DMTCz rt,rd
-Class6:
-	op base rt offset
-	    	    	    	    	    	    	    LDCz rt,offset (base)
-	    	    	    	    	    	    	    SDCz rt,offset (base)
-Class7:
-	COPz BC br offset
-	    	    	    	    	    	    	    BCzTL offset
-	    	    	    	    	    	    	    BCzFL offset
-
-The coprocessor table defines coprocessor-specific registers that can
-be used with all of the above classes of instructions, where
-appropriate.  It also defines additional coprocessor-specific
-functions for Class3 (COPz cofun) instructions, Thus, the table allows
-the programmer to use convenient mnemonics and operands for these
-functions, instead of the COPz mmenmonic and cofun operand.
-
-The names of the MIPS general registers and their aliases are defined
-by the assembler and will be recognized as valid register names by the
-assembler when used (where allowed) in coprocessor instructions.
-However, the names and values of all coprocessor data and control
-register mnemonics must be specified in the coprocessor table.
-
-
-Table Grammar
-=============
-
-Here is the grammar for the coprocessor table:
-
-	    table -> entry*
-
-	    entry -> [z entrydef] [comment] '\n'
-
-	    entrydef -> type name val
-	    entrydef -> 'insn' name val funcdef ; type of entry (instruction)
-
-	    z -> 'p'['0'..'3']	    	     ; processor number 
-	    type -> ['dreg' | 'creg' | 'greg' ]	     ; type of entry (register)
-	; 'dreg', 'creg' or 'greg' specifies a data, control, or general
-	;	    register mnemonic, respectively
-	    name -> [ltr|dec]*	    	     ; mnemonic of register/function
-	    val -> [dec|hex]	    	     ; register/function number (integer constant)
-
-	    funcdef -> frange flags fields
-	    	    	    	; bitfield range for opcode
-	    	    	    	; list of fields' formats
-	    fields -> field*
-	    field -> [','] ftype frange flags
-	    flags -> ['*' flagexpr]
-	    flagexpr -> '[' flagexpr ']'
-	    flagexpr -> val '|' flagexpr 
-	    ftype -> [ type | 'immed' | 'addr' ]
-	; 'immed' specifies an immediate value; see grammar for "val" above
-	    	; 'addr' specifies a C identifier; name of symbol to be resolved at 
-	;	    link time
-	    frange -> ':' val '-' val	; starting to ending bit positions, where
-	    	    	    	; where 0 is least significant bit
-	    frange -> (null)	    	; default range of 31-0 will be assumed
-
-	    comment -> [';'|'#'] [char]*
-	    char -> any printable character
-	    ltr -> ['a'..'z'|'A'..'Z'] 
-	    dec -> ['0'..'9']*	    	    	    	    	     ; value in decimal
-	    hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']*	; value in hexadecimal 
-
-
-Examples
-========
-
-Example 1:
-
-The table:
-
-	    p1 dreg d1 1	     ; data register "d1" for COP1 has value 1
-	    p1 creg c3 3	     ; ctrl register "c3" for COP1 has value 3
-	    p3 func fill 0x1f:24-20	      ; function "fill" for COP3 has value 31 and 
-	    	    	; no fields
-
-will allow the assembler to accept the following coprocessor instructions:
-
-	    LWC1 d1,0x100 ($2)
-	    fill
-
-Here, the general purpose register "$2", and instruction "LWC1", are standard 
-mnemonics built-in to the MIPS assembler.  
-
-
-Example 2:
-
-The table:
-
-	    p3 dreg d3 3	     ; data register "d3" for COP3 has value 3
-	    p3 creg c2 22	     ; control register "c2" for COP3 has value 22
-	    p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0 
-	    	; function "fee" for COP3 has value 31, and 3 fields 
-	    	; consisting of a data register, a control register, 
-	    	; and an immediate value.
-
-will allow the assembler to accept the following coprocessor instruction:
-
-	    fee d3,c2,0x1
-
-and will emit the object code:
-
-	    31-26  25 24-20 19-18  17-13 12-8  7-0
-	    COPz   CO fun	    	      dreg  creg  immed
-	    010011 1  11111 00	     00011 10110 00000001 
-
-	    0x4ff07601
-
-
-Example 3:
-
-The table:
-
-	    p3 dreg d3 3	     ; data register "d3" for COP3 has value 3
-	    p3 creg c2 22	     ; control register "c2" for COP3 has value 22
-	    p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
-
-will allow the assembler to accept the following coprocessor
-instruction:
-
-	    fuu d3,c2
-
-and will emit the object code:
-
-	    31-26  25 24-20 19-18  17-13 12-8  7-0
-	    COPz   CO fun	    	      dreg  creg  
-	    010011 1  11111 00	     00011 10110 00000001 
-
-	    0x4ff07601
-
-In this way, the programmer can force arbitrary bits of an instruction
-to have predefined values.
-
-=======================================================================
-Additional notes:
-
-Encoding of ranges:
-To handle more than one bit position range within an instruction,
-use 0s to mask out the ranges which don't apply.
-May decide to modify the syntax to allow commas separate multiple 
-ranges within an instruction (range','range).
-
-Changes in grammar:
-	The number of parms argument to the function entry
-was deleted from the original format such that we now count the fields.
-
-----
-FIXME! should really change lexical analyzer 
-to recognize 'dreg' etc. in context sensitive way.
-Currently function names or mnemonics may be incorrectly parsed as keywords
-
-FIXME! hex is ambiguous with any digit
-
-*/
-
-#include <stdio.h>
-#include "itbl-lex.h"
-#include "itbl-ops.h"
-
-/* #define DEBUG */
-
-#ifdef DEBUG
-#ifndef DBG_LVL
-#define DBG_LVL 1
-#endif
-#else
-#define DBG_LVL 0
-#endif
-
-#if DBG_LVL >= 1
-#define DBG(x) printf x
-#else
-#define DBG(x) 
-#endif
-
-#if DBG_LVL >= 2
-#define DBGL2(x) printf x
-#else
-#define DBGL2(x) 
-#endif
-
-static int sbit, ebit;
-static struct itbl_entry *insn=0;
-static int yyerror PARAMS ((const char *));
-
-
-
-/* Enabling traces.  */
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
-
-/* Enabling verbose error messages.  */
-#ifdef YYERROR_VERBOSE
-# undef YYERROR_VERBOSE
-# define YYERROR_VERBOSE 1
-#else
-# define YYERROR_VERBOSE 0
-#endif
-
-/* Enabling the token table.  */
-#ifndef YYTOKEN_TABLE
-# define YYTOKEN_TABLE 0
-#endif
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 282 "itbl-parse.y"
-typedef union YYSTYPE {
-    char *str;
-    int num;
-    int processor;
-    unsigned long val;
-  } YYSTYPE;
-/* Line 196 of yacc.c.  */
-#line 376 "itbl-parse.c"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-
-
-/* Copy the second part of user declarations.  */
-
-
-/* Line 219 of yacc.c.  */
-#line 388 "itbl-parse.c"
-
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
-#endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
-# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
-#endif
-
-#ifndef YY_
-# if YYENABLE_NLS
-#  if ENABLE_NLS
-#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
-#   define YY_(msgid) dgettext ("bison-runtime", msgid)
-#  endif
-# endif
-# ifndef YY_
-#  define YY_(msgid) msgid
-# endif
-#endif
-
-#if ! defined (yyoverflow) || YYERROR_VERBOSE
-
-/* The parser invokes alloca or malloc; define the necessary symbols.  */
-
-# ifdef YYSTACK_USE_ALLOCA
-#  if YYSTACK_USE_ALLOCA
-#   ifdef __GNUC__
-#    define YYSTACK_ALLOC __builtin_alloca
-#   else
-#    define YYSTACK_ALLOC alloca
-#    if defined (__STDC__) || defined (__cplusplus)
-#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     define YYINCLUDED_STDLIB_H
-#    endif
-#   endif
-#  endif
-# endif
-
-# ifdef YYSTACK_ALLOC
-   /* Pacify GCC's `empty if-body' warning. */
-#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-    /* The OS might guarantee only one guard page at the bottom of the stack,
-       and a page size can be as small as 4096 bytes.  So we cannot safely
-       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
-       to allow for a few compiler-allocated temporary stack slots.  */
-#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
-#  endif
-# else
-#  define YYSTACK_ALLOC YYMALLOC
-#  define YYSTACK_FREE YYFREE
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
-#  endif
-#  ifdef __cplusplus
-extern "C" {
-#  endif
-#  ifndef YYMALLOC
-#   define YYMALLOC malloc
-#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifndef YYFREE
-#   define YYFREE free
-#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void free (void *); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifdef __cplusplus
-}
-#  endif
-# endif
-#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
-
-
-#if (! defined (yyoverflow) \
-     && (! defined (__cplusplus) \
-	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
-
-/* A type that is properly aligned for any stack member.  */
-union yyalloc
-{
-  short int yyss;
-  YYSTYPE yyvs;
-  };
-
-/* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
-
-/* The size of an array large to enough to hold all stacks, each with
-   N elements.  */
-# define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
-      + YYSTACK_GAP_MAXIMUM)
-
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined (__GNUC__) && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)		\
-      do					\
-	{					\
-	  YYSIZE_T yyi;				\
-	  for (yyi = 0; yyi < (Count); yyi++)	\
-	    (To)[yyi] = (From)[yyi];		\
-	}					\
-      while (0)
-#  endif
-# endif
-
-/* Relocate STACK from its old location to the new one.  The
-   local variables YYSIZE and YYSTACKSIZE give the old and new number of
-   elements in the stack, and YYPTR gives the new location of the
-   stack.  Advance YYPTR to a properly aligned location for the next
-   stack.  */
-# define YYSTACK_RELOCATE(Stack)					\
-    do									\
-      {									\
-	YYSIZE_T yynewbytes;						\
-	YYCOPY (&yyptr->Stack, Stack, yysize);				\
-	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-	yyptr += yynewbytes / sizeof (*yyptr);				\
-      }									\
-    while (0)
-
-#endif
-
-#if defined (__STDC__) || defined (__cplusplus)
-   typedef signed char yysigned_char;
-#else
-   typedef short int yysigned_char;
-#endif
-
-/* YYFINAL -- State number of the termination state. */
-#define YYFINAL  9
-/* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   46
-
-/* YYNTOKENS -- Number of terminals. */
-#define YYNTOKENS  20
-/* YYNNTS -- Number of nonterminals. */
-#define YYNNTS  15
-/* YYNRULES -- Number of rules. */
-#define YYNRULES  29
-/* YYNRULES -- Number of states. */
-#define YYNSTATES  51
-
-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
-#define YYUNDEFTOK  2
-#define YYMAXUTOK   267
-
-#define YYTRANSLATE(YYX)						\
-  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
-static const unsigned char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,    17,     2,    13,    19,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,    18,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,    15,     2,    16,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,    14,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
-       5,     6,     7,     8,     9,    10,    11,    12
-};
-
-#if YYDEBUG
-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-   YYRHS.  */
-static const unsigned char yyprhs[] =
-{
-       0,     0,     3,     5,     8,     9,    15,    16,    26,    28,
-      31,    35,    38,    39,    41,    43,    45,    49,    53,    57,
-      59,    62,    63,    68,    69,    71,    73,    75,    77,    79
-};
-
-/* YYRHS -- A `-1'-separated list of the rules' RHS. */
-static const yysigned_char yyrhs[] =
-{
-      21,     0,    -1,    22,    -1,    23,    22,    -1,    -1,    31,
-      32,    33,    34,    11,    -1,    -1,    31,     8,    33,    34,
-      30,    29,    24,    25,    11,    -1,    11,    -1,     1,    11,
-      -1,    13,    27,    25,    -1,    27,    25,    -1,    -1,    32,
-      -1,     7,    -1,     6,    -1,    26,    30,    29,    -1,     9,
-      14,    28,    -1,    15,    28,    16,    -1,     9,    -1,    17,
-      28,    -1,    -1,    18,     9,    19,     9,    -1,    -1,    12,
-      -1,     3,    -1,     4,    -1,     5,    -1,    10,    -1,     9,
-      -1
-};
-
-/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
-static const unsigned short int yyrline[] =
-{
-       0,   299,   299,   303,   304,   308,   315,   314,   323,   324,
-     328,   329,   330,   334,   339,   344,   352,   361,   365,   369,
-     376,   382,   388,   395,   402,   410,   415,   420,   428,   444
-};
-#endif
-
-#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
-/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
-   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
-static const char *const yytname[] =
-{
-  "$end", "error", "$undefined", "DREG", "CREG", "GREG", "IMMED", "ADDR",
-  "INSN", "NUM", "ID", "NL", "PNUM", "','", "'|'", "'['", "']'", "'*'",
-  "':'", "'-'", "$accept", "insntbl", "entrys", "entry", "@1",
-  "fieldspecs", "ftype", "fieldspec", "flagexpr", "flags", "range", "pnum",
-  "regtype", "name", "value", 0
-};
-#endif
-
-# ifdef YYPRINT
-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-   token YYLEX-NUM.  */
-static const unsigned short int yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,   266,   267,    44,   124,    91,    93,    42,    58,    45
-};
-# endif
-
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
-static const unsigned char yyr1[] =
-{
-       0,    20,    21,    22,    22,    23,    24,    23,    23,    23,
-      25,    25,    25,    26,    26,    26,    27,    28,    28,    28,
-      29,    29,    30,    30,    31,    32,    32,    32,    33,    34
-};
-
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
-static const unsigned char yyr2[] =
-{
-       0,     2,     1,     2,     0,     5,     0,     9,     1,     2,
-       3,     2,     0,     1,     1,     1,     3,     3,     3,     1,
-       2,     0,     4,     0,     1,     1,     1,     1,     1,     1
-};
-
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
-   means the default is an error.  */
-static const unsigned char yydefact[] =
-{
-       0,     0,     8,    24,     0,     2,     0,     0,     9,     1,
-       3,    25,    26,    27,     0,     0,    28,     0,     0,    29,
-      23,     0,     0,    21,     5,     0,     0,     6,     0,    19,
-       0,    20,    12,    22,     0,     0,    15,    14,     0,     0,
-      23,    12,    13,    17,    18,    12,     7,    21,    11,    10,
-      16
-};
-
-/* YYDEFGOTO[NTERM-NUM]. */
-static const yysigned_char yydefgoto[] =
-{
-      -1,     4,     5,     6,    32,    39,    40,    41,    31,    27,
-      23,     7,    42,    17,    20
-};
-
-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-   STATE-NUM.  */
-#define YYPACT_NINF -16
-static const yysigned_char yypact[] =
-{
-       0,    -9,   -16,   -16,    10,   -16,     0,    12,   -16,   -16,
-     -16,   -16,   -16,   -16,     3,     3,   -16,     9,     9,   -16,
-      11,     8,    19,    15,   -16,    14,    -6,   -16,    25,    21,
-      -6,   -16,     1,   -16,    -6,    20,   -16,   -16,    18,    26,
-      11,     1,   -16,   -16,   -16,     1,   -16,    15,   -16,   -16,
-     -16
-};
-
-/* YYPGOTO[NTERM-NUM].  */
-static const yysigned_char yypgoto[] =
-{
-     -16,   -16,    32,   -16,   -16,   -15,   -16,     2,    -3,    -8,
-       4,   -16,    34,    27,    28
-};
-
-/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
-   positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -5
-static const yysigned_char yytable[] =
-{
-      -4,     1,     8,    29,    11,    12,    13,    36,    37,    30,
-       9,     2,     3,    16,    38,    11,    12,    13,    19,    24,
-      14,    11,    12,    13,    36,    37,    48,    35,    25,    22,
-      49,    43,    26,    28,    33,    34,    44,    46,    10,    50,
-      45,    15,    18,     0,    47,     0,    21
-};
-
-static const yysigned_char yycheck[] =
-{
-       0,     1,    11,     9,     3,     4,     5,     6,     7,    15,
-       0,    11,    12,    10,    13,     3,     4,     5,     9,    11,
-       8,     3,     4,     5,     6,     7,    41,    30,     9,    18,
-      45,    34,    17,    19,     9,    14,    16,    11,     6,    47,
-      38,     7,    15,    -1,    40,    -1,    18
-};
-
-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-   symbol of state STATE-NUM.  */
-static const unsigned char yystos[] =
-{
-       0,     1,    11,    12,    21,    22,    23,    31,    11,     0,
-      22,     3,     4,     5,     8,    32,    10,    33,    33,     9,
-      34,    34,    18,    30,    11,     9,    17,    29,    19,     9,
-      15,    28,    24,     9,    14,    28,     6,     7,    13,    25,
-      26,    27,    32,    28,    16,    27,    11,    30,    25,    25,
-      29
-};
-
-#define yyerrok		(yyerrstatus = 0)
-#define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		(-2)
-#define YYEOF		0
-
-#define YYACCEPT	goto yyacceptlab
-#define YYABORT		goto yyabortlab
-#define YYERROR		goto yyerrorlab
-
-
-/* Like YYERROR except do call yyerror.  This remains here temporarily
-   to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
-
-#define YYFAIL		goto yyerrlab
-
-#define YYRECOVERING()  (!!yyerrstatus)
-
-#define YYBACKUP(Token, Value)					\
-do								\
-  if (yychar == YYEMPTY && yylen == 1)				\
-    {								\
-      yychar = (Token);						\
-      yylval = (Value);						\
-      yytoken = YYTRANSLATE (yychar);				\
-      YYPOPSTACK;						\
-      goto yybackup;						\
-    }								\
-  else								\
-    {								\
-      yyerror (YY_("syntax error: cannot back up")); \
-      YYERROR;							\
-    }								\
-while (0)
-
-
-#define YYTERROR	1
-#define YYERRCODE	256
-
-
-/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
-   If N is 0, then set CURRENT to the empty location which ends
-   the previous symbol: RHS[0] (always defined).  */
-
-#define YYRHSLOC(Rhs, K) ((Rhs)[K])
-#ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)				\
-    do									\
-      if (N)								\
-	{								\
-	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
-	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
-	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
-	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
-	}								\
-      else								\
-	{								\
-	  (Current).first_line   = (Current).last_line   =		\
-	    YYRHSLOC (Rhs, 0).last_line;				\
-	  (Current).first_column = (Current).last_column =		\
-	    YYRHSLOC (Rhs, 0).last_column;				\
-	}								\
-    while (0)
-#endif
-
-
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
-
-#ifndef YY_LOCATION_PRINT
-# if YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)			\
-     fprintf (File, "%d.%d-%d.%d",			\
-              (Loc).first_line, (Loc).first_column,	\
-              (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
-#endif
-
-
-/* YYLEX -- calling `yylex' with the right arguments.  */
-
-#ifdef YYLEX_PARAM
-# define YYLEX yylex (YYLEX_PARAM)
-#else
-# define YYLEX yylex ()
-#endif
-
-/* Enable debugging if requested.  */
-#if YYDEBUG
-
-# ifndef YYFPRINTF
-#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYFPRINTF fprintf
-# endif
-
-# define YYDPRINTF(Args)			\
-do {						\
-  if (yydebug)					\
-    YYFPRINTF Args;				\
-} while (0)
-
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
-do {								\
-  if (yydebug)							\
-    {								\
-      YYFPRINTF (stderr, "%s ", Title);				\
-      yysymprint (stderr,					\
-                  Type, Value);	\
-      YYFPRINTF (stderr, "\n");					\
-    }								\
-} while (0)
-
-/*------------------------------------------------------------------.
-| yy_stack_print -- Print the state stack from its BOTTOM up to its |
-| TOP (included).                                                   |
-`------------------------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_stack_print (short int *bottom, short int *top)
-#else
-static void
-yy_stack_print (bottom, top)
-    short int *bottom;
-    short int *top;
-#endif
-{
-  YYFPRINTF (stderr, "Stack now");
-  for (/* Nothing. */; bottom <= top; ++bottom)
-    YYFPRINTF (stderr, " %d", *bottom);
-  YYFPRINTF (stderr, "\n");
-}
-
-# define YY_STACK_PRINT(Bottom, Top)				\
-do {								\
-  if (yydebug)							\
-    yy_stack_print ((Bottom), (Top));				\
-} while (0)
-
-
-/*------------------------------------------------.
-| Report that the YYRULE is going to be reduced.  |
-`------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_reduce_print (int yyrule)
-#else
-static void
-yy_reduce_print (yyrule)
-    int yyrule;
-#endif
-{
-  int yyi;
-  unsigned long int yylno = yyrline[yyrule];
-  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
-             yyrule - 1, yylno);
-  /* Print the symbols being reduced, and their result.  */
-  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
-    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
-  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
-}
-
-# define YY_REDUCE_PRINT(Rule)		\
-do {					\
-  if (yydebug)				\
-    yy_reduce_print (Rule);		\
-} while (0)
-
-/* Nonzero means print parse trace.  It is left uninitialized so that
-   multiple parsers can coexist.  */
-int yydebug;
-#else /* !YYDEBUG */
-# define YYDPRINTF(Args)
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
-# define YY_STACK_PRINT(Bottom, Top)
-# define YY_REDUCE_PRINT(Rule)
-#endif /* !YYDEBUG */
-
-
-/* YYINITDEPTH -- initial size of the parser's stacks.  */
-#ifndef	YYINITDEPTH
-# define YYINITDEPTH 200
-#endif
-
-/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
-   if the built-in stack extension method is used).
-
-   Do not make this value too large; the results are undefined if
-   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
-   evaluated with infinite-precision integer arithmetic.  */
-
-#ifndef YYMAXDEPTH
-# define YYMAXDEPTH 10000
-#endif
-
-
-
-#if YYERROR_VERBOSE
-
-# ifndef yystrlen
-#  if defined (__GLIBC__) && defined (_STRING_H)
-#   define yystrlen strlen
-#  else
-/* Return the length of YYSTR.  */
-static YYSIZE_T
-#   if defined (__STDC__) || defined (__cplusplus)
-yystrlen (const char *yystr)
-#   else
-yystrlen (yystr)
-     const char *yystr;
-#   endif
-{
-  const char *yys = yystr;
-
-  while (*yys++ != '\0')
-    continue;
-
-  return yys - yystr - 1;
-}
-#  endif
-# endif
-
-# ifndef yystpcpy
-#  if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
-#   define yystpcpy stpcpy
-#  else
-/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
-   YYDEST.  */
-static char *
-#   if defined (__STDC__) || defined (__cplusplus)
-yystpcpy (char *yydest, const char *yysrc)
-#   else
-yystpcpy (yydest, yysrc)
-     char *yydest;
-     const char *yysrc;
-#   endif
-{
-  char *yyd = yydest;
-  const char *yys = yysrc;
-
-  while ((*yyd++ = *yys++) != '\0')
-    continue;
-
-  return yyd - 1;
-}
-#  endif
-# endif
-
-# ifndef yytnamerr
-/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
-   quotes and backslashes, so that it's suitable for yyerror.  The
-   heuristic is that double-quoting is unnecessary unless the string
-   contains an apostrophe, a comma, or backslash (other than
-   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
-   null, do not copy; instead, return the length of what the result
-   would have been.  */
-static YYSIZE_T
-yytnamerr (char *yyres, const char *yystr)
-{
-  if (*yystr == '"')
-    {
-      size_t yyn = 0;
-      char const *yyp = yystr;
-
-      for (;;)
-	switch (*++yyp)
-	  {
-	  case '\'':
-	  case ',':
-	    goto do_not_strip_quotes;
-
-	  case '\\':
-	    if (*++yyp != '\\')
-	      goto do_not_strip_quotes;
-	    /* Fall through.  */
-	  default:
-	    if (yyres)
-	      yyres[yyn] = *yyp;
-	    yyn++;
-	    break;
-
-	  case '"':
-	    if (yyres)
-	      yyres[yyn] = '\0';
-	    return yyn;
-	  }
-    do_not_strip_quotes: ;
-    }
-
-  if (! yyres)
-    return yystrlen (yystr);
-
-  return yystpcpy (yyres, yystr) - yyres;
-}
-# endif
-
-#endif /* YYERROR_VERBOSE */
-
-
-
-#if YYDEBUG
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yysymprint (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (yytype < YYNTOKENS)
-    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-  else
-    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-
-
-# ifdef YYPRINT
-  if (yytype < YYNTOKENS)
-    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
-# endif
-  switch (yytype)
-    {
-      default:
-        break;
-    }
-  YYFPRINTF (yyoutput, ")");
-}
-
-#endif /* ! YYDEBUG */
-/*-----------------------------------------------.
-| Release the memory associated to this symbol.  |
-`-----------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yydestruct (yymsg, yytype, yyvaluep)
-    const char *yymsg;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (!yymsg)
-    yymsg = "Deleting";
-  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
-
-  switch (yytype)
-    {
-
-      default:
-        break;
-    }
-}
-
-
-/* Prevent warnings from -Wmissing-prototypes.  */
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM);
-# else
-int yyparse ();
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void);
-#else
-int yyparse ();
-#endif
-#endif /* ! YYPARSE_PARAM */
-
-
-
-/* The look-ahead symbol.  */
-int yychar;
-
-/* The semantic value of the look-ahead symbol.  */
-YYSTYPE yylval;
-
-/* Number of syntax errors so far.  */
-int yynerrs;
-
-
-
-/*----------.
-| yyparse.  |
-`----------*/
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM)
-# else
-int yyparse (YYPARSE_PARAM)
-  void *YYPARSE_PARAM;
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int
-yyparse (void)
-#else
-int
-yyparse ()
-    ;
-#endif
-#endif
-{
-  
-  int yystate;
-  int yyn;
-  int yyresult;
-  /* Number of tokens to shift before error messages enabled.  */
-  int yyerrstatus;
-  /* Look-ahead token as an internal (translated) token number.  */
-  int yytoken = 0;
-
-  /* Three stacks and their tools:
-     `yyss': related to states,
-     `yyvs': related to semantic values,
-     `yyls': related to locations.
-
-     Refer to the stacks thru separate pointers, to allow yyoverflow
-     to reallocate them elsewhere.  */
-
-  /* The state stack.  */
-  short int yyssa[YYINITDEPTH];
-  short int *yyss = yyssa;
-  short int *yyssp;
-
-  /* The semantic value stack.  */
-  YYSTYPE yyvsa[YYINITDEPTH];
-  YYSTYPE *yyvs = yyvsa;
-  YYSTYPE *yyvsp;
-
-
-
-#define YYPOPSTACK   (yyvsp--, yyssp--)
-
-  YYSIZE_T yystacksize = YYINITDEPTH;
-
-  /* The variables used to return semantic value and location from the
-     action routines.  */
-  YYSTYPE yyval;
-
-
-  /* When reducing, the number of symbols on the RHS of the reduced
-     rule.  */
-  int yylen;
-
-  YYDPRINTF ((stderr, "Starting parse\n"));
-
-  yystate = 0;
-  yyerrstatus = 0;
-  yynerrs = 0;
-  yychar = YYEMPTY;		/* Cause a token to be read.  */
-
-  /* Initialize stack pointers.
-     Waste one element of value and location stack
-     so that they stay on the same level as the state stack.
-     The wasted elements are never initialized.  */
-
-  yyssp = yyss;
-  yyvsp = yyvs;
-
-  goto yysetstate;
-
-/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate.  |
-`------------------------------------------------------------*/
- yynewstate:
-  /* In all cases, when you get here, the value and location stacks
-     have just been pushed. so pushing a state here evens the stacks.
-     */
-  yyssp++;
-
- yysetstate:
-  *yyssp = yystate;
-
-  if (yyss + yystacksize - 1 <= yyssp)
-    {
-      /* Get the current used size of the three stacks, in elements.  */
-      YYSIZE_T yysize = yyssp - yyss + 1;
-
-#ifdef yyoverflow
-      {
-	/* Give user a chance to reallocate the stack. Use copies of
-	   these so that the &'s don't force the real ones into
-	   memory.  */
-	YYSTYPE *yyvs1 = yyvs;
-	short int *yyss1 = yyss;
-
-
-	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  This used to be a
-	   conditional around just the two extra args, but that might
-	   be undefined if yyoverflow is a macro.  */
-	yyoverflow (YY_("memory exhausted"),
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-
-		    &yystacksize);
-
-	yyss = yyss1;
-	yyvs = yyvs1;
-      }
-#else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
-      goto yyexhaustedlab;
-# else
-      /* Extend the stack our own way.  */
-      if (YYMAXDEPTH <= yystacksize)
-	goto yyexhaustedlab;
-      yystacksize *= 2;
-      if (YYMAXDEPTH < yystacksize)
-	yystacksize = YYMAXDEPTH;
-
-      {
-	short int *yyss1 = yyss;
-	union yyalloc *yyptr =
-	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-	if (! yyptr)
-	  goto yyexhaustedlab;
-	YYSTACK_RELOCATE (yyss);
-	YYSTACK_RELOCATE (yyvs);
-
-#  undef YYSTACK_RELOCATE
-	if (yyss1 != yyssa)
-	  YYSTACK_FREE (yyss1);
-      }
-# endif
-#endif /* no yyoverflow */
-
-      yyssp = yyss + yysize - 1;
-      yyvsp = yyvs + yysize - 1;
-
-
-      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-		  (unsigned long int) yystacksize));
-
-      if (yyss + yystacksize - 1 <= yyssp)
-	YYABORT;
-    }
-
-  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
-
-  goto yybackup;
-
-/*-----------.
-| yybackup.  |
-`-----------*/
-yybackup:
-
-/* Do appropriate processing given the current state.  */
-/* Read a look-ahead token if we need one and don't already have one.  */
-/* yyresume: */
-
-  /* First try to decide what to do without reference to look-ahead token.  */
-
-  yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
-    goto yydefault;
-
-  /* Not known => get a look-ahead token if don't already have one.  */
-
-  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
-  if (yychar == YYEMPTY)
-    {
-      YYDPRINTF ((stderr, "Reading a token: "));
-      yychar = YYLEX;
-    }
-
-  if (yychar <= YYEOF)
-    {
-      yychar = yytoken = YYEOF;
-      YYDPRINTF ((stderr, "Now at end of input.\n"));
-    }
-  else
-    {
-      yytoken = YYTRANSLATE (yychar);
-      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
-    }
-
-  /* If the proper action on seeing token YYTOKEN is to reduce or to
-     detect an error, take that action.  */
-  yyn += yytoken;
-  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
-    goto yydefault;
-  yyn = yytable[yyn];
-  if (yyn <= 0)
-    {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-	goto yyerrlab;
-      yyn = -yyn;
-      goto yyreduce;
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  /* Shift the look-ahead token.  */
-  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
-
-  /* Discard the token being shifted unless it is eof.  */
-  if (yychar != YYEOF)
-    yychar = YYEMPTY;
-
-  *++yyvsp = yylval;
-
-
-  /* Count tokens shifted since error; after three, turn off error
-     status.  */
-  if (yyerrstatus)
-    yyerrstatus--;
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-----------------------------------------------------------.
-| yydefault -- do the default action for the current state.  |
-`-----------------------------------------------------------*/
-yydefault:
-  yyn = yydefact[yystate];
-  if (yyn == 0)
-    goto yyerrlab;
-  goto yyreduce;
-
-
-/*-----------------------------.
-| yyreduce -- Do a reduction.  |
-`-----------------------------*/
-yyreduce:
-  /* yyn is the number of a rule to reduce with.  */
-  yylen = yyr2[yyn];
-
-  /* If YYLEN is nonzero, implement the default value of the action:
-     `$$ = $1'.
-
-     Otherwise, the following line sets YYVAL to garbage.
-     This behavior is undocumented and Bison
-     users should not rely upon it.  Assigning to YYVAL
-     unconditionally makes the parser a bit smaller, and it avoids a
-     GCC warning that YYVAL may be used uninitialized.  */
-  yyval = yyvsp[1-yylen];
-
-
-  YY_REDUCE_PRINT (yyn);
-  switch (yyn)
-    {
-        case 5:
-#line 309 "itbl-parse.y"
-    {
-	    DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n", 
-	    	    insntbl_line, (yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val)));
-	    itbl_add_reg ((yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val));
-	  }
-    break;
-
-  case 6:
-#line 315 "itbl-parse.y"
-    {
-	    DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
-	    	    insntbl_line, (yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val)));
-	    DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, (yyvsp[0].val)));
-	    insn=itbl_add_insn ((yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val), sbit, ebit, (yyvsp[0].val));
-	  }
-    break;
-
-  case 7:
-#line 322 "itbl-parse.y"
-    {}
-    break;
-
-  case 13:
-#line 335 "itbl-parse.y"
-    {
-	    DBGL2 (("ftype\n"));
-	    (yyval.num) = (yyvsp[0].num);
-	  }
-    break;
-
-  case 14:
-#line 340 "itbl-parse.y"
-    {
-	    DBGL2 (("addr\n"));
-	    (yyval.num) = ADDR;
-	  }
-    break;
-
-  case 15:
-#line 345 "itbl-parse.y"
-    {
-	    DBGL2 (("immed\n"));
-	    (yyval.num) = IMMED;
-	  }
-    break;
-
-  case 16:
-#line 353 "itbl-parse.y"
-    {
-	    DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n", 
-	    	    insntbl_line, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val)));
-	    itbl_add_operand (insn, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val));
-	  }
-    break;
-
-  case 17:
-#line 362 "itbl-parse.y"
-    {
-	    (yyval.val) = (yyvsp[-2].num) | (yyvsp[0].val);
-	  }
-    break;
-
-  case 18:
-#line 366 "itbl-parse.y"
-    {
-	    (yyval.val) = (yyvsp[-1].val);
-	  }
-    break;
-
-  case 19:
-#line 370 "itbl-parse.y"
-    {
-	    (yyval.val) = (yyvsp[0].num);
-	  }
-    break;
-
-  case 20:
-#line 377 "itbl-parse.y"
-    {
-	    DBGL2 (("flags=%d\n", (yyvsp[0].val)));
-	    (yyval.val) = (yyvsp[0].val);
-	  }
-    break;
-
-  case 21:
-#line 382 "itbl-parse.y"
-    {
-	    (yyval.val) = 0;
-	  }
-    break;
-
-  case 22:
-#line 389 "itbl-parse.y"
-    {
-	    DBGL2 (("range %d %d\n", (yyvsp[-2].num), (yyvsp[0].num)));
-	    sbit = (yyvsp[-2].num);
-	    ebit = (yyvsp[0].num);
-	  }
-    break;
-
-  case 23:
-#line 395 "itbl-parse.y"
-    {
-	    sbit = 31;
-	    ebit = 0;
-	  }
-    break;
-
-  case 24:
-#line 403 "itbl-parse.y"
-    {
-	    DBGL2 (("pnum=%d\n",(yyvsp[0].num)));
-	    (yyval.num) = (yyvsp[0].num);
-	  }
-    break;
-
-  case 25:
-#line 411 "itbl-parse.y"
-    {
-	    DBGL2 (("dreg\n"));
-	    (yyval.num) = DREG;
-	  }
-    break;
-
-  case 26:
-#line 416 "itbl-parse.y"
-    {
-	    DBGL2 (("creg\n"));
-	    (yyval.num) = CREG;
-	  }
-    break;
-
-  case 27:
-#line 421 "itbl-parse.y"
-    {
-	    DBGL2 (("greg\n"));
-	    (yyval.num) = GREG;
-	  }
-    break;
-
-  case 28:
-#line 429 "itbl-parse.y"
-    {
-	    DBGL2 (("name=%s\n",(yyvsp[0].str)));
-	    (yyval.str) = (yyvsp[0].str); 
-	  }
-    break;
-
-  case 29:
-#line 445 "itbl-parse.y"
-    {
-	    DBGL2 (("val=x%x\n",(yyvsp[0].num)));
-	    (yyval.val) = (yyvsp[0].num);
-	  }
-    break;
-
-
-      default: break;
-    }
-
-/* Line 1126 of yacc.c.  */
-#line 1565 "itbl-parse.c"
-
-  yyvsp -= yylen;
-  yyssp -= yylen;
-
-
-  YY_STACK_PRINT (yyss, yyssp);
-
-  *++yyvsp = yyval;
-
-
-  /* Now `shift' the result of the reduction.  Determine what state
-     that goes to, based on the state we popped back to and the rule
-     number reduced by.  */
-
-  yyn = yyr1[yyn];
-
-  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
-  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
-    yystate = yytable[yystate];
-  else
-    yystate = yydefgoto[yyn - YYNTOKENS];
-
-  goto yynewstate;
-
-
-/*------------------------------------.
-| yyerrlab -- here on detecting error |
-`------------------------------------*/
-yyerrlab:
-  /* If not already recovering from an error, report this error.  */
-  if (!yyerrstatus)
-    {
-      ++yynerrs;
-#if YYERROR_VERBOSE
-      yyn = yypact[yystate];
-
-      if (YYPACT_NINF < yyn && yyn < YYLAST)
-	{
-	  int yytype = YYTRANSLATE (yychar);
-	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-	  YYSIZE_T yysize = yysize0;
-	  YYSIZE_T yysize1;
-	  int yysize_overflow = 0;
-	  char *yymsg = 0;
-#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
-	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-	  int yyx;
-
-#if 0
-	  /* This is so xgettext sees the translatable formats that are
-	     constructed on the fly.  */
-	  YY_("syntax error, unexpected %s");
-	  YY_("syntax error, unexpected %s, expecting %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-#endif
-	  char *yyfmt;
-	  char const *yyf;
-	  static char const yyunexpected[] = "syntax error, unexpected %s";
-	  static char const yyexpecting[] = ", expecting %s";
-	  static char const yyor[] = " or %s";
-	  char yyformat[sizeof yyunexpected
-			+ sizeof yyexpecting - 1
-			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-			   * (sizeof yyor - 1))];
-	  char const *yyprefix = yyexpecting;
-
-	  /* Start YYX at -YYN if negative to avoid negative indexes in
-	     YYCHECK.  */
-	  int yyxbegin = yyn < 0 ? -yyn : 0;
-
-	  /* Stay within bounds of both yycheck and yytname.  */
-	  int yychecklim = YYLAST - yyn;
-	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-	  int yycount = 1;
-
-	  yyarg[0] = yytname[yytype];
-	  yyfmt = yystpcpy (yyformat, yyunexpected);
-
-	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-	      {
-		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-		  {
-		    yycount = 1;
-		    yysize = yysize0;
-		    yyformat[sizeof yyunexpected - 1] = '\0';
-		    break;
-		  }
-		yyarg[yycount++] = yytname[yyx];
-		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-		yysize_overflow |= yysize1 < yysize;
-		yysize = yysize1;
-		yyfmt = yystpcpy (yyfmt, yyprefix);
-		yyprefix = yyor;
-	      }
-
-	  yyf = YY_(yyformat);
-	  yysize1 = yysize + yystrlen (yyf);
-	  yysize_overflow |= yysize1 < yysize;
-	  yysize = yysize1;
-
-	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
-	    yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg)
-	    {
-	      /* Avoid sprintf, as that infringes on the user's name space.
-		 Don't have undefined behavior even if the translation
-		 produced a string with the wrong number of "%s"s.  */
-	      char *yyp = yymsg;
-	      int yyi = 0;
-	      while ((*yyp = *yyf))
-		{
-		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-		    {
-		      yyp += yytnamerr (yyp, yyarg[yyi++]);
-		      yyf += 2;
-		    }
-		  else
-		    {
-		      yyp++;
-		      yyf++;
-		    }
-		}
-	      yyerror (yymsg);
-	      YYSTACK_FREE (yymsg);
-	    }
-	  else
-	    {
-	      yyerror (YY_("syntax error"));
-	      goto yyexhaustedlab;
-	    }
-	}
-      else
-#endif /* YYERROR_VERBOSE */
-	yyerror (YY_("syntax error"));
-    }
-
-
-
-  if (yyerrstatus == 3)
-    {
-      /* If just tried and failed to reuse look-ahead token after an
-	 error, discard it.  */
-
-      if (yychar <= YYEOF)
-        {
-	  /* Return failure if at end of input.  */
-	  if (yychar == YYEOF)
-	    YYABORT;
-        }
-      else
-	{
-	  yydestruct ("Error: discarding", yytoken, &yylval);
-	  yychar = YYEMPTY;
-	}
-    }
-
-  /* Else will try to reuse look-ahead token after shifting the error
-     token.  */
-  goto yyerrlab1;
-
-
-/*---------------------------------------------------.
-| yyerrorlab -- error raised explicitly by YYERROR.  |
-`---------------------------------------------------*/
-yyerrorlab:
-
-  /* Pacify compilers like GCC when the user code never invokes
-     YYERROR and the label yyerrorlab therefore never appears in user
-     code.  */
-  if (0)
-     goto yyerrorlab;
-
-yyvsp -= yylen;
-  yyssp -= yylen;
-  yystate = *yyssp;
-  goto yyerrlab1;
-
-
-/*-------------------------------------------------------------.
-| yyerrlab1 -- common code for both syntax error and YYERROR.  |
-`-------------------------------------------------------------*/
-yyerrlab1:
-  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
-
-  for (;;)
-    {
-      yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
-	{
-	  yyn += YYTERROR;
-	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-	    {
-	      yyn = yytable[yyn];
-	      if (0 < yyn)
-		break;
-	    }
-	}
-
-      /* Pop the current state because it cannot handle the error token.  */
-      if (yyssp == yyss)
-	YYABORT;
-
-
-      yydestruct ("Error: popping", yystos[yystate], yyvsp);
-      YYPOPSTACK;
-      yystate = *yyssp;
-      YY_STACK_PRINT (yyss, yyssp);
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  *++yyvsp = yylval;
-
-
-  /* Shift the error token. */
-  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-------------------------------------.
-| yyacceptlab -- YYACCEPT comes here.  |
-`-------------------------------------*/
-yyacceptlab:
-  yyresult = 0;
-  goto yyreturn;
-
-/*-----------------------------------.
-| yyabortlab -- YYABORT comes here.  |
-`-----------------------------------*/
-yyabortlab:
-  yyresult = 1;
-  goto yyreturn;
-
-#ifndef yyoverflow
-/*-------------------------------------------------.
-| yyexhaustedlab -- memory exhaustion comes here.  |
-`-------------------------------------------------*/
-yyexhaustedlab:
-  yyerror (YY_("memory exhausted"));
-  yyresult = 2;
-  /* Fall through.  */
-#endif
-
-yyreturn:
-  if (yychar != YYEOF && yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-		 yytoken, &yylval);
-  while (yyssp != yyss)
-    {
-      yydestruct ("Cleanup: popping",
-		  yystos[*yyssp], yyvsp);
-      YYPOPSTACK;
-    }
-#ifndef yyoverflow
-  if (yyss != yyssa)
-    YYSTACK_FREE (yyss);
-#endif
-  return yyresult;
-}
-
-
-#line 450 "itbl-parse.y"
-
-
-static int
-yyerror (msg)
-     const char *msg;
-{
-  printf ("line %d: %s\n", insntbl_line, msg);
-  return 0;
-}
-
diff --git a/gas/itbl-parse.h b/gas/itbl-parse.h
deleted file mode 100644
index 9fd500831b79..000000000000
--- a/gas/itbl-parse.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.1.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     DREG = 258,
-     CREG = 259,
-     GREG = 260,
-     IMMED = 261,
-     ADDR = 262,
-     INSN = 263,
-     NUM = 264,
-     ID = 265,
-     NL = 266,
-     PNUM = 267
-   };
-#endif
-/* Tokens.  */
-#define DREG 258
-#define CREG 259
-#define GREG 260
-#define IMMED 261
-#define ADDR 262
-#define INSN 263
-#define NUM 264
-#define ID 265
-#define NL 266
-#define PNUM 267
-
-
-
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 282 "itbl-parse.y"
-typedef union YYSTYPE {
-    char *str;
-    int num;
-    int processor;
-    unsigned long val;
-  } YYSTYPE;
-/* Line 1447 of yacc.c.  */
-#line 69 "itbl-parse.h"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-extern YYSTYPE yylval;
-
-
-
diff --git a/gas/itbl-parse.y b/gas/itbl-parse.y
index a7a52dfabff9..ff48657fb365 100644
--- a/gas/itbl-parse.y
+++ b/gas/itbl-parse.y
@@ -1,5 +1,5 @@
 /* itbl-parse.y
-   Copyright 1997, 2002, 2003, 2005 Free Software Foundation, Inc.
+   Copyright 1997, 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -246,7 +246,7 @@ FIXME! hex is ambiguous with any digit
 
 */
 
-#include <stdio.h>
+#include "as.h"
 #include "itbl-lex.h"
 #include "itbl-ops.h"
 
@@ -274,7 +274,7 @@ FIXME! hex is ambiguous with any digit
 
 static int sbit, ebit;
 static struct itbl_entry *insn=0;
-static int yyerror PARAMS ((const char *));
+static int yyerror (const char *);
 
 %}
 
diff --git a/gas/listing.c b/gas/listing.c
index 61ef6f55e40f..1b55cbf63989 100644
--- a/gas/listing.c
+++ b/gas/listing.c
@@ -1,6 +1,6 @@
 /* listing.c - maintain assembly listings
    Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2005
+   2001, 2002, 2003, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -946,15 +946,6 @@ listing_listing (char *name ATTRIBUTE_UNUSED)
   buffer = xmalloc (listing_rhs_width);
   data_buffer = xmalloc (MAX_BYTES);
   eject = 1;
-  list = head;
-
-  while (list != (list_info_type *) NULL && 0)
-    {
-      if (list->next)
-	list->frag = list->next->frag;
-      list = list->next;
-    }
-
   list = head->next;
 
   while (list)
@@ -1085,8 +1076,7 @@ listing_print (char *name)
 	using_stdout = 0;
       else
 	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("can't open list file: %s"), name);
+	  as_warn (_("can't open %s: %s"), name, xstrerror (errno));
 	  list_file = stdout;
 	  using_stdout = 1;
 	}
@@ -1104,10 +1094,7 @@ listing_print (char *name)
   if (! using_stdout)
     {
       if (fclose (list_file) == EOF)
-	{
-	  bfd_set_error (bfd_error_system_call);
-	  as_perror (_("error closing list file: %s"), name);
-	}
+	as_warn (_("can't close %s: %s"), name, xstrerror (errno));
     }
 
   if (last_open_file)
diff --git a/gas/m68k-parse.c b/gas/m68k-parse.c
deleted file mode 100644
index 5258dda60c53..000000000000
--- a/gas/m68k-parse.c
+++ /dev/null
@@ -1,2672 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.1.  */
-
-/* Skeleton parser for Yacc-like parsing with Bison,
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* Written by Richard Stallman by simplifying the original so called
-   ``semantic'' parser.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
-
-/* Identify Bison output.  */
-#define YYBISON 1
-
-/* Bison version.  */
-#define YYBISON_VERSION "2.1"
-
-/* Skeleton name.  */
-#define YYSKELETON_NAME "yacc.c"
-
-/* Pure parsers.  */
-#define YYPURE 0
-
-/* Using locations.  */
-#define YYLSP_NEEDED 0
-
-
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     DR = 258,
-     AR = 259,
-     FPR = 260,
-     FPCR = 261,
-     LPC = 262,
-     ZAR = 263,
-     ZDR = 264,
-     LZPC = 265,
-     CREG = 266,
-     INDEXREG = 267,
-     EXPR = 268
-   };
-#endif
-/* Tokens.  */
-#define DR 258
-#define AR 259
-#define FPR 260
-#define FPCR 261
-#define LPC 262
-#define ZAR 263
-#define ZDR 264
-#define LZPC 265
-#define CREG 266
-#define INDEXREG 267
-#define EXPR 268
-
-
-
-
-/* Copy the first part of user declarations.  */
-#line 28 "m68k-parse.y"
-
-
-#include "as.h"
-#include "tc-m68k.h"
-#include "m68k-parse.h"
-#include "safe-ctype.h"
-
-/* Remap normal yacc parser interface names (yyparse, yylex, yyerror,
-   etc), as well as gratuitously global symbol names If other parser
-   generators (bison, byacc, etc) produce additional global names that
-   conflict at link time, then those parser generators need to be
-   fixed instead of adding those names to this list.  */
-
-#define	yymaxdepth m68k_maxdepth
-#define	yyparse	m68k_parse
-#define	yylex	m68k_lex
-#define	yyerror	m68k_error
-#define	yylval	m68k_lval
-#define	yychar	m68k_char
-#define	yydebug	m68k_debug
-#define	yypact	m68k_pact	
-#define	yyr1	m68k_r1			
-#define	yyr2	m68k_r2			
-#define	yydef	m68k_def		
-#define	yychk	m68k_chk		
-#define	yypgo	m68k_pgo		
-#define	yyact	m68k_act		
-#define	yyexca	m68k_exca
-#define yyerrflag m68k_errflag
-#define yynerrs	m68k_nerrs
-#define	yyps	m68k_ps
-#define	yypv	m68k_pv
-#define	yys	m68k_s
-#define	yy_yys	m68k_yys
-#define	yystate	m68k_state
-#define	yytmp	m68k_tmp
-#define	yyv	m68k_v
-#define	yy_yyv	m68k_yyv
-#define	yyval	m68k_val
-#define	yylloc	m68k_lloc
-#define yyreds	m68k_reds		/* With YYDEBUG defined */
-#define yytoks	m68k_toks		/* With YYDEBUG defined */
-#define yylhs	m68k_yylhs
-#define yylen	m68k_yylen
-#define yydefred m68k_yydefred
-#define yydgoto	m68k_yydgoto
-#define yysindex m68k_yysindex
-#define yyrindex m68k_yyrindex
-#define yygindex m68k_yygindex
-#define yytable	 m68k_yytable
-#define yycheck	 m68k_yycheck
-
-#ifndef YYDEBUG
-#define YYDEBUG 1
-#endif
-
-/* Internal functions.  */
-
-static enum m68k_register m68k_reg_parse (char **);
-static int yylex (void);
-static void yyerror (const char *);
-
-/* The parser sets fields pointed to by this global variable.  */
-static struct m68k_op *op;
-
-
-
-/* Enabling traces.  */
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
-
-/* Enabling verbose error messages.  */
-#ifdef YYERROR_VERBOSE
-# undef YYERROR_VERBOSE
-# define YYERROR_VERBOSE 1
-#else
-# define YYERROR_VERBOSE 0
-#endif
-
-/* Enabling the token table.  */
-#ifndef YYTOKEN_TABLE
-# define YYTOKEN_TABLE 0
-#endif
-
-#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
-#line 96 "m68k-parse.y"
-typedef union YYSTYPE {
-  struct m68k_indexreg indexreg;
-  enum m68k_register reg;
-  struct m68k_exp exp;
-  unsigned long mask;
-  int onereg;
-  int trailing_ampersand;
-} YYSTYPE;
-/* Line 196 of yacc.c.  */
-#line 187 "m68k-parse.c"
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-
-
-/* Copy the second part of user declarations.  */
-
-
-/* Line 219 of yacc.c.  */
-#line 199 "m68k-parse.c"
-
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
-#endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
-# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-# define YYSIZE_T size_t
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
-#endif
-
-#ifndef YY_
-# if YYENABLE_NLS
-#  if ENABLE_NLS
-#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
-#   define YY_(msgid) dgettext ("bison-runtime", msgid)
-#  endif
-# endif
-# ifndef YY_
-#  define YY_(msgid) msgid
-# endif
-#endif
-
-#if ! defined (yyoverflow) || YYERROR_VERBOSE
-
-/* The parser invokes alloca or malloc; define the necessary symbols.  */
-
-# ifdef YYSTACK_USE_ALLOCA
-#  if YYSTACK_USE_ALLOCA
-#   ifdef __GNUC__
-#    define YYSTACK_ALLOC __builtin_alloca
-#   else
-#    define YYSTACK_ALLOC alloca
-#    if defined (__STDC__) || defined (__cplusplus)
-#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     define YYINCLUDED_STDLIB_H
-#    endif
-#   endif
-#  endif
-# endif
-
-# ifdef YYSTACK_ALLOC
-   /* Pacify GCC's `empty if-body' warning. */
-#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-    /* The OS might guarantee only one guard page at the bottom of the stack,
-       and a page size can be as small as 4096 bytes.  So we cannot safely
-       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
-       to allow for a few compiler-allocated temporary stack slots.  */
-#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
-#  endif
-# else
-#  define YYSTACK_ALLOC YYMALLOC
-#  define YYSTACK_FREE YYFREE
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
-#  endif
-#  ifdef __cplusplus
-extern "C" {
-#  endif
-#  ifndef YYMALLOC
-#   define YYMALLOC malloc
-#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifndef YYFREE
-#   define YYFREE free
-#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
-	&& (defined (__STDC__) || defined (__cplusplus)))
-void free (void *); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifdef __cplusplus
-}
-#  endif
-# endif
-#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
-
-
-#if (! defined (yyoverflow) \
-     && (! defined (__cplusplus) \
-	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
-
-/* A type that is properly aligned for any stack member.  */
-union yyalloc
-{
-  short int yyss;
-  YYSTYPE yyvs;
-  };
-
-/* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
-
-/* The size of an array large to enough to hold all stacks, each with
-   N elements.  */
-# define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
-      + YYSTACK_GAP_MAXIMUM)
-
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined (__GNUC__) && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)		\
-      do					\
-	{					\
-	  YYSIZE_T yyi;				\
-	  for (yyi = 0; yyi < (Count); yyi++)	\
-	    (To)[yyi] = (From)[yyi];		\
-	}					\
-      while (0)
-#  endif
-# endif
-
-/* Relocate STACK from its old location to the new one.  The
-   local variables YYSIZE and YYSTACKSIZE give the old and new number of
-   elements in the stack, and YYPTR gives the new location of the
-   stack.  Advance YYPTR to a properly aligned location for the next
-   stack.  */
-# define YYSTACK_RELOCATE(Stack)					\
-    do									\
-      {									\
-	YYSIZE_T yynewbytes;						\
-	YYCOPY (&yyptr->Stack, Stack, yysize);				\
-	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-	yyptr += yynewbytes / sizeof (*yyptr);				\
-      }									\
-    while (0)
-
-#endif
-
-#if defined (__STDC__) || defined (__cplusplus)
-   typedef signed char yysigned_char;
-#else
-   typedef short int yysigned_char;
-#endif
-
-/* YYFINAL -- State number of the termination state. */
-#define YYFINAL  44
-/* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   215
-
-/* YYNTOKENS -- Number of terminals. */
-#define YYNTOKENS  27
-/* YYNNTS -- Number of nonterminals. */
-#define YYNNTS  21
-/* YYNRULES -- Number of rules. */
-#define YYNRULES  89
-/* YYNRULES -- Number of states. */
-#define YYNSTATES  180
-
-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
-#define YYUNDEFTOK  2
-#define YYMAXUTOK   268
-
-#define YYTRANSLATE(YYX)						\
-  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
-static const unsigned char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,    17,     2,     2,    14,     2,
-      18,    19,     2,    20,    22,    21,     2,    26,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-      15,     2,    16,     2,    25,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,    23,     2,    24,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
-       5,     6,     7,     8,     9,    10,    11,    12,    13
-};
-
-#if YYDEBUG
-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-   YYRHS.  */
-static const unsigned short int yyprhs[] =
-{
-       0,     0,     3,     5,     8,    11,    12,    14,    17,    20,
-      22,    24,    26,    28,    30,    32,    35,    38,    40,    44,
-      49,    54,    60,    66,    71,    75,    79,    83,    91,    99,
-     106,   112,   119,   125,   132,   138,   144,   149,   159,   167,
-     176,   183,   194,   203,   214,   223,   232,   235,   239,   243,
-     249,   256,   267,   277,   288,   290,   292,   294,   296,   298,
-     300,   302,   304,   306,   308,   310,   312,   314,   316,   317,
-     319,   321,   323,   324,   327,   328,   331,   332,   335,   337,
-     341,   345,   347,   349,   353,   357,   361,   363,   365,   367
-};
-
-/* YYRHS -- A `-1'-separated list of the rules' RHS. */
-static const yysigned_char yyrhs[] =
-{
-      28,     0,    -1,    30,    -1,    31,    29,    -1,    32,    29,
-      -1,    -1,    14,    -1,    15,    15,    -1,    16,    16,    -1,
-       3,    -1,     4,    -1,     5,    -1,     6,    -1,    11,    -1,
-      13,    -1,    17,    13,    -1,    14,    13,    -1,    44,    -1,
-      18,     4,    19,    -1,    18,     4,    19,    20,    -1,    21,
-      18,     4,    19,    -1,    18,    13,    22,    38,    19,    -1,
-      18,    38,    22,    13,    19,    -1,    13,    18,    38,    19,
-      -1,    18,     7,    19,    -1,    18,     8,    19,    -1,    18,
-      10,    19,    -1,    18,    13,    22,    38,    22,    33,    19,
-      -1,    18,    13,    22,    38,    22,    40,    19,    -1,    18,
-      13,    22,    34,    41,    19,    -1,    18,    34,    22,    13,
-      19,    -1,    13,    18,    38,    22,    33,    19,    -1,    18,
-      38,    22,    33,    19,    -1,    13,    18,    38,    22,    40,
-      19,    -1,    18,    38,    22,    40,    19,    -1,    13,    18,
-      34,    41,    19,    -1,    18,    34,    41,    19,    -1,    18,
-      23,    13,    41,    24,    22,    33,    42,    19,    -1,    18,
-      23,    13,    41,    24,    42,    19,    -1,    18,    23,    38,
-      24,    22,    33,    42,    19,    -1,    18,    23,    38,    24,
-      42,    19,    -1,    18,    23,    13,    22,    38,    22,    33,
-      24,    42,    19,    -1,    18,    23,    38,    22,    33,    24,
-      42,    19,    -1,    18,    23,    13,    22,    38,    22,    40,
-      24,    42,    19,    -1,    18,    23,    38,    22,    40,    24,
-      42,    19,    -1,    18,    23,    43,    34,    41,    24,    42,
-      19,    -1,    39,    25,    -1,    39,    25,    20,    -1,    39,
-      25,    21,    -1,    39,    25,    18,    13,    19,    -1,    39,
-      25,    18,    43,    33,    19,    -1,    39,    25,    18,    13,
-      19,    25,    18,    43,    33,    19,    -1,    39,    25,    18,
-      13,    19,    25,    18,    13,    19,    -1,    39,    25,    18,
-      43,    33,    19,    25,    18,    13,    19,    -1,    12,    -1,
-      35,    -1,    12,    -1,    36,    -1,    36,    -1,     4,    -1,
-       8,    -1,     3,    -1,     9,    -1,     4,    -1,     7,    -1,
-      37,    -1,    10,    -1,     8,    -1,    -1,    38,    -1,     7,
-      -1,    10,    -1,    -1,    22,    38,    -1,    -1,    22,    13,
-      -1,    -1,    13,    22,    -1,    46,    -1,    46,    26,    45,
-      -1,    47,    26,    45,    -1,    47,    -1,    46,    -1,    46,
-      26,    45,    -1,    47,    26,    45,    -1,    47,    21,    47,
-      -1,     3,    -1,     4,    -1,     5,    -1,     6,    -1
-};
-
-/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
-static const unsigned short int yyrline[] =
-{
-       0,   121,   121,   122,   126,   135,   136,   143,   148,   153,
-     158,   163,   168,   173,   178,   183,   188,   193,   206,   211,
-     216,   221,   231,   241,   251,   256,   261,   266,   273,   284,
-     291,   297,   304,   310,   321,   331,   338,   344,   352,   359,
-     366,   372,   380,   387,   399,   410,   423,   431,   439,   447,
-     457,   464,   472,   479,   493,   494,   507,   508,   520,   521,
-     522,   528,   529,   535,   536,   543,   544,   545,   552,   555,
-     561,   562,   569,   572,   582,   586,   596,   600,   609,   610,
-     614,   626,   630,   631,   635,   642,   652,   656,   660,   664
-};
-#endif
-
-#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
-/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
-   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
-static const char *const yytname[] =
-{
-  "$end", "error", "$undefined", "DR", "AR", "FPR", "FPCR", "LPC", "ZAR",
-  "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'&'", "'<'", "'>'", "'#'",
-  "'('", "')'", "'+'", "'-'", "','", "'['", "']'", "'@'", "'/'", "$accept",
-  "operand", "optional_ampersand", "generic_operand", "motorola_operand",
-  "mit_operand", "zireg", "zdireg", "zadr", "zdr", "apc", "zapc",
-  "optzapc", "zpc", "optczapc", "optcexpr", "optexprc", "reglist",
-  "ireglist", "reglistpair", "reglistreg", 0
-};
-#endif
-
-# ifdef YYPRINT
-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-   token YYLEX-NUM.  */
-static const unsigned short int yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,   266,   267,   268,    38,    60,    62,    35,    40,    41,
-      43,    45,    44,    91,    93,    64,    47
-};
-# endif
-
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
-static const unsigned char yyr1[] =
-{
-       0,    27,    28,    28,    28,    29,    29,    30,    30,    30,
-      30,    30,    30,    30,    30,    30,    30,    30,    31,    31,
-      31,    31,    31,    31,    31,    31,    31,    31,    31,    31,
-      31,    31,    31,    31,    31,    31,    31,    31,    31,    31,
-      31,    31,    31,    31,    31,    31,    32,    32,    32,    32,
-      32,    32,    32,    32,    33,    33,    34,    34,    35,    35,
-      35,    36,    36,    37,    37,    38,    38,    38,    39,    39,
-      40,    40,    41,    41,    42,    42,    43,    43,    44,    44,
-      44,    45,    45,    45,    45,    46,    47,    47,    47,    47
-};
-
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
-static const unsigned char yyr2[] =
-{
-       0,     2,     1,     2,     2,     0,     1,     2,     2,     1,
-       1,     1,     1,     1,     1,     2,     2,     1,     3,     4,
-       4,     5,     5,     4,     3,     3,     3,     7,     7,     6,
-       5,     6,     5,     6,     5,     5,     4,     9,     7,     8,
-       6,    10,     8,    10,     8,     8,     2,     3,     3,     5,
-       6,    10,     9,    10,     1,     1,     1,     1,     1,     1,
-       1,     1,     1,     1,     1,     1,     1,     1,     0,     1,
-       1,     1,     0,     2,     0,     2,     0,     2,     1,     3,
-       3,     1,     1,     3,     3,     3,     1,     1,     1,     1
-};
-
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
-   means the default is an error.  */
-static const unsigned char yydefact[] =
-{
-      68,    86,    87,    88,    89,    64,    67,    66,    13,    14,
-       0,     0,     0,     0,     0,     0,     0,     2,     5,     5,
-      65,    69,     0,    17,    78,     0,     0,    16,     7,     8,
-      15,    61,    63,    64,    67,    62,    66,    56,     0,    76,
-      72,    57,     0,     0,     1,     6,     3,     4,    46,     0,
-       0,     0,    63,    72,     0,    18,    24,    25,    26,     0,
-      72,     0,     0,     0,     0,     0,     0,    76,    47,    48,
-      86,    87,    88,    89,    79,    82,    81,    85,    80,     0,
-       0,    23,     0,    19,    72,     0,    77,     0,     0,    74,
-      72,     0,    73,    36,    59,    70,    60,    71,    54,     0,
-       0,    55,    58,     0,    20,     0,     0,     0,     0,    35,
-       0,     0,     0,    21,     0,    73,    74,     0,     0,     0,
-       0,     0,    30,    22,    32,    34,    49,    77,     0,    83,
-      84,    31,    33,    29,     0,     0,     0,     0,     0,    74,
-      74,    75,    74,    40,    74,     0,    50,    27,    28,     0,
-       0,    74,    38,     0,     0,     0,     0,     0,    76,     0,
-      74,    74,     0,    42,    44,    39,    45,     0,     0,     0,
-       0,     0,    37,    52,     0,     0,    41,    43,    51,    53
-};
-
-/* YYDEFGOTO[NTERM-NUM]. */
-static const yysigned_char yydefgoto[] =
-{
-      -1,    16,    46,    17,    18,    19,   100,    40,   101,   102,
-      20,    92,    22,   103,    64,   120,    62,    23,    74,    75,
-      76
-};
-
-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-   STATE-NUM.  */
-#define YYPACT_NINF -98
-static const short int yypact[] =
-{
-      89,    14,     9,    31,    35,   -98,   -98,   -98,   -98,     0,
-      36,    42,    28,    56,    63,    67,    90,   -98,    75,    75,
-     -98,   -98,    86,   -98,    96,   -15,   123,   -98,   -98,   -98,
-     -98,   -98,    97,   115,   119,   -98,   120,   -98,   122,    16,
-     126,   -98,   127,   157,   -98,   -98,   -98,   -98,    19,   154,
-     154,   154,   -98,   140,    29,   144,   -98,   -98,   -98,   123,
-     141,    99,    18,    70,   147,   105,   148,   152,   -98,   -98,
-     -98,   -98,   -98,   -98,   -98,   142,   -13,   -98,   -98,   146,
-     150,   -98,   133,   -98,   140,    60,   146,   149,   133,   153,
-     140,   151,   -98,   -98,   -98,   -98,   -98,   -98,   -98,   155,
-     158,   -98,   -98,   159,   -98,    62,   143,   154,   154,   -98,
-     160,   161,   162,   -98,   133,   163,   164,   165,   166,   116,
-     168,   167,   -98,   -98,   -98,   -98,   169,   -98,   173,   -98,
-     -98,   -98,   -98,   -98,   174,   176,   133,   116,   177,   175,
-     175,   -98,   175,   -98,   175,   170,   178,   -98,   -98,   180,
-     181,   175,   -98,   171,   179,   182,   183,   187,   186,   189,
-     175,   175,   190,   -98,   -98,   -98,   -98,    79,   143,   195,
-     191,   192,   -98,   -98,   193,   194,   -98,   -98,   -98,   -98
-};
-
-/* YYPGOTO[NTERM-NUM].  */
-static const short int yypgoto[] =
-{
-     -98,   -98,   196,   -98,   -98,   -98,   -81,     6,   -98,    -9,
-     -98,     2,   -98,   -78,   -38,   -97,   -67,   -98,   -48,   172,
-      12
-};
-
-/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
-   positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -64
-static const short int yytable[] =
-{
-     106,   110,    21,    78,   111,    41,    50,   117,    50,   -10,
-     118,    51,    25,   108,    -9,    80,    42,    41,    26,   138,
-      52,    31,    87,     5,     6,   128,     7,    35,    54,    60,
-      37,   -11,    53,   134,   -63,   -12,   135,    67,   142,    68,
-      69,    61,   154,   155,    29,   156,   112,   157,    81,    27,
-      41,    82,   121,    41,   162,   149,   151,    28,   150,   129,
-     130,    85,    77,   170,   171,    84,    31,    32,    90,    30,
-      33,    34,    35,    36,    52,    37,    38,     5,     6,   113,
-       7,   126,   114,    91,   127,    43,    39,   174,   115,    45,
-      44,   168,     1,     2,     3,     4,     5,     6,   173,     7,
-       8,   127,     9,    10,    11,    12,    13,    14,    31,    94,
-      15,    48,    95,    96,    35,    97,    55,    98,    99,    31,
-      94,    88,    49,    89,    96,    35,    31,    52,    98,   141,
-       5,     6,    35,     7,    56,    37,    31,    94,    57,    58,
-      95,    96,    35,    97,    59,    98,    31,    94,    63,    65,
-      52,    96,    35,     5,     6,    98,     7,    70,    71,    72,
-      73,    66,    79,    86,    83,   105,    93,   104,   107,   109,
-     122,     0,    24,   116,   123,   119,     0,   124,   125,   131,
-     132,   133,     0,     0,   141,   136,   137,   143,   158,   139,
-     140,   144,   146,   147,   145,   148,   152,   153,   163,   167,
-       0,   164,   165,   159,   160,   161,   166,   169,   175,   172,
-     176,   177,   178,   179,     0,    47
-};
-
-static const short int yycheck[] =
-{
-      67,    82,     0,    51,    82,    14,    21,    88,    21,     0,
-      88,    26,     0,    26,     0,    53,    14,    26,    18,   116,
-       4,     3,    60,     7,     8,   106,    10,     9,    26,    13,
-      12,     0,    26,   114,    25,     0,   114,    18,   119,    20,
-      21,    39,   139,   140,    16,   142,    84,   144,    19,    13,
-      59,    22,    90,    62,   151,   136,   137,    15,   136,   107,
-     108,    59,    50,   160,   161,    59,     3,     4,    62,    13,
-       7,     8,     9,    10,     4,    12,    13,     7,     8,    19,
-      10,    19,    22,    13,    22,    18,    23,   168,    86,    14,
-       0,   158,     3,     4,     5,     6,     7,     8,    19,    10,
-      11,    22,    13,    14,    15,    16,    17,    18,     3,     4,
-      21,    25,     7,     8,     9,    10,    19,    12,    13,     3,
-       4,    22,    26,    24,     8,     9,     3,     4,    12,    13,
-       7,     8,     9,    10,    19,    12,     3,     4,    19,    19,
-       7,     8,     9,    10,    22,    12,     3,     4,    22,    22,
-       4,     8,     9,     7,     8,    12,    10,     3,     4,     5,
-       6,     4,    22,    22,    20,    13,    19,    19,    26,    19,
-      19,    -1,     0,    24,    19,    22,    -1,    19,    19,    19,
-      19,    19,    -1,    -1,    13,    22,    22,    19,    18,    24,
-      24,    24,    19,    19,    25,    19,    19,    22,    19,    13,
-      -1,    19,    19,    25,    24,    24,    19,    18,    13,    19,
-      19,    19,    19,    19,    -1,    19
-};
-
-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-   symbol of state STATE-NUM.  */
-static const unsigned char yystos[] =
-{
-       0,     3,     4,     5,     6,     7,     8,    10,    11,    13,
-      14,    15,    16,    17,    18,    21,    28,    30,    31,    32,
-      37,    38,    39,    44,    46,    47,    18,    13,    15,    16,
-      13,     3,     4,     7,     8,     9,    10,    12,    13,    23,
-      34,    36,    38,    18,     0,    14,    29,    29,    25,    26,
-      21,    26,     4,    34,    38,    19,    19,    19,    19,    22,
-      13,    38,    43,    22,    41,    22,     4,    18,    20,    21,
-       3,     4,     5,     6,    45,    46,    47,    47,    45,    22,
-      41,    19,    22,    20,    34,    38,    22,    41,    22,    24,
-      34,    13,    38,    19,     4,     7,     8,    10,    12,    13,
-      33,    35,    36,    40,    19,    13,    43,    26,    26,    19,
-      33,    40,    41,    19,    22,    38,    24,    33,    40,    22,
-      42,    41,    19,    19,    19,    19,    19,    22,    33,    45,
-      45,    19,    19,    19,    33,    40,    22,    22,    42,    24,
-      24,    13,    33,    19,    24,    25,    19,    19,    19,    33,
-      40,    33,    19,    22,    42,    42,    42,    42,    18,    25,
-      24,    24,    42,    19,    19,    19,    19,    13,    43,    18,
-      42,    42,    19,    19,    33,    13,    19,    19,    19,    19
-};
-
-#define yyerrok		(yyerrstatus = 0)
-#define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		(-2)
-#define YYEOF		0
-
-#define YYACCEPT	goto yyacceptlab
-#define YYABORT		goto yyabortlab
-#define YYERROR		goto yyerrorlab
-
-
-/* Like YYERROR except do call yyerror.  This remains here temporarily
-   to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
-
-#define YYFAIL		goto yyerrlab
-
-#define YYRECOVERING()  (!!yyerrstatus)
-
-#define YYBACKUP(Token, Value)					\
-do								\
-  if (yychar == YYEMPTY && yylen == 1)				\
-    {								\
-      yychar = (Token);						\
-      yylval = (Value);						\
-      yytoken = YYTRANSLATE (yychar);				\
-      YYPOPSTACK;						\
-      goto yybackup;						\
-    }								\
-  else								\
-    {								\
-      yyerror (YY_("syntax error: cannot back up")); \
-      YYERROR;							\
-    }								\
-while (0)
-
-
-#define YYTERROR	1
-#define YYERRCODE	256
-
-
-/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
-   If N is 0, then set CURRENT to the empty location which ends
-   the previous symbol: RHS[0] (always defined).  */
-
-#define YYRHSLOC(Rhs, K) ((Rhs)[K])
-#ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)				\
-    do									\
-      if (N)								\
-	{								\
-	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
-	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
-	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
-	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
-	}								\
-      else								\
-	{								\
-	  (Current).first_line   = (Current).last_line   =		\
-	    YYRHSLOC (Rhs, 0).last_line;				\
-	  (Current).first_column = (Current).last_column =		\
-	    YYRHSLOC (Rhs, 0).last_column;				\
-	}								\
-    while (0)
-#endif
-
-
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
-
-#ifndef YY_LOCATION_PRINT
-# if YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)			\
-     fprintf (File, "%d.%d-%d.%d",			\
-              (Loc).first_line, (Loc).first_column,	\
-              (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
-#endif
-
-
-/* YYLEX -- calling `yylex' with the right arguments.  */
-
-#ifdef YYLEX_PARAM
-# define YYLEX yylex (YYLEX_PARAM)
-#else
-# define YYLEX yylex ()
-#endif
-
-/* Enable debugging if requested.  */
-#if YYDEBUG
-
-# ifndef YYFPRINTF
-#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYFPRINTF fprintf
-# endif
-
-# define YYDPRINTF(Args)			\
-do {						\
-  if (yydebug)					\
-    YYFPRINTF Args;				\
-} while (0)
-
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
-do {								\
-  if (yydebug)							\
-    {								\
-      YYFPRINTF (stderr, "%s ", Title);				\
-      yysymprint (stderr,					\
-                  Type, Value);	\
-      YYFPRINTF (stderr, "\n");					\
-    }								\
-} while (0)
-
-/*------------------------------------------------------------------.
-| yy_stack_print -- Print the state stack from its BOTTOM up to its |
-| TOP (included).                                                   |
-`------------------------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_stack_print (short int *bottom, short int *top)
-#else
-static void
-yy_stack_print (bottom, top)
-    short int *bottom;
-    short int *top;
-#endif
-{
-  YYFPRINTF (stderr, "Stack now");
-  for (/* Nothing. */; bottom <= top; ++bottom)
-    YYFPRINTF (stderr, " %d", *bottom);
-  YYFPRINTF (stderr, "\n");
-}
-
-# define YY_STACK_PRINT(Bottom, Top)				\
-do {								\
-  if (yydebug)							\
-    yy_stack_print ((Bottom), (Top));				\
-} while (0)
-
-
-/*------------------------------------------------.
-| Report that the YYRULE is going to be reduced.  |
-`------------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yy_reduce_print (int yyrule)
-#else
-static void
-yy_reduce_print (yyrule)
-    int yyrule;
-#endif
-{
-  int yyi;
-  unsigned long int yylno = yyrline[yyrule];
-  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
-             yyrule - 1, yylno);
-  /* Print the symbols being reduced, and their result.  */
-  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
-    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
-  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
-}
-
-# define YY_REDUCE_PRINT(Rule)		\
-do {					\
-  if (yydebug)				\
-    yy_reduce_print (Rule);		\
-} while (0)
-
-/* Nonzero means print parse trace.  It is left uninitialized so that
-   multiple parsers can coexist.  */
-int yydebug;
-#else /* !YYDEBUG */
-# define YYDPRINTF(Args)
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
-# define YY_STACK_PRINT(Bottom, Top)
-# define YY_REDUCE_PRINT(Rule)
-#endif /* !YYDEBUG */
-
-
-/* YYINITDEPTH -- initial size of the parser's stacks.  */
-#ifndef	YYINITDEPTH
-# define YYINITDEPTH 200
-#endif
-
-/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
-   if the built-in stack extension method is used).
-
-   Do not make this value too large; the results are undefined if
-   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
-   evaluated with infinite-precision integer arithmetic.  */
-
-#ifndef YYMAXDEPTH
-# define YYMAXDEPTH 10000
-#endif
-
-
-
-#if YYERROR_VERBOSE
-
-# ifndef yystrlen
-#  if defined (__GLIBC__) && defined (_STRING_H)
-#   define yystrlen strlen
-#  else
-/* Return the length of YYSTR.  */
-static YYSIZE_T
-#   if defined (__STDC__) || defined (__cplusplus)
-yystrlen (const char *yystr)
-#   else
-yystrlen (yystr)
-     const char *yystr;
-#   endif
-{
-  const char *yys = yystr;
-
-  while (*yys++ != '\0')
-    continue;
-
-  return yys - yystr - 1;
-}
-#  endif
-# endif
-
-# ifndef yystpcpy
-#  if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
-#   define yystpcpy stpcpy
-#  else
-/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
-   YYDEST.  */
-static char *
-#   if defined (__STDC__) || defined (__cplusplus)
-yystpcpy (char *yydest, const char *yysrc)
-#   else
-yystpcpy (yydest, yysrc)
-     char *yydest;
-     const char *yysrc;
-#   endif
-{
-  char *yyd = yydest;
-  const char *yys = yysrc;
-
-  while ((*yyd++ = *yys++) != '\0')
-    continue;
-
-  return yyd - 1;
-}
-#  endif
-# endif
-
-# ifndef yytnamerr
-/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
-   quotes and backslashes, so that it's suitable for yyerror.  The
-   heuristic is that double-quoting is unnecessary unless the string
-   contains an apostrophe, a comma, or backslash (other than
-   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
-   null, do not copy; instead, return the length of what the result
-   would have been.  */
-static YYSIZE_T
-yytnamerr (char *yyres, const char *yystr)
-{
-  if (*yystr == '"')
-    {
-      size_t yyn = 0;
-      char const *yyp = yystr;
-
-      for (;;)
-	switch (*++yyp)
-	  {
-	  case '\'':
-	  case ',':
-	    goto do_not_strip_quotes;
-
-	  case '\\':
-	    if (*++yyp != '\\')
-	      goto do_not_strip_quotes;
-	    /* Fall through.  */
-	  default:
-	    if (yyres)
-	      yyres[yyn] = *yyp;
-	    yyn++;
-	    break;
-
-	  case '"':
-	    if (yyres)
-	      yyres[yyn] = '\0';
-	    return yyn;
-	  }
-    do_not_strip_quotes: ;
-    }
-
-  if (! yyres)
-    return yystrlen (yystr);
-
-  return yystpcpy (yyres, yystr) - yyres;
-}
-# endif
-
-#endif /* YYERROR_VERBOSE */
-
-
-
-#if YYDEBUG
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yysymprint (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (yytype < YYNTOKENS)
-    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-  else
-    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-
-
-# ifdef YYPRINT
-  if (yytype < YYNTOKENS)
-    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
-# endif
-  switch (yytype)
-    {
-      default:
-        break;
-    }
-  YYFPRINTF (yyoutput, ")");
-}
-
-#endif /* ! YYDEBUG */
-/*-----------------------------------------------.
-| Release the memory associated to this symbol.  |
-`-----------------------------------------------*/
-
-#if defined (__STDC__) || defined (__cplusplus)
-static void
-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yydestruct (yymsg, yytype, yyvaluep)
-    const char *yymsg;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  /* Pacify ``unused variable'' warnings.  */
-  (void) yyvaluep;
-
-  if (!yymsg)
-    yymsg = "Deleting";
-  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
-
-  switch (yytype)
-    {
-
-      default:
-        break;
-    }
-}
-
-
-/* Prevent warnings from -Wmissing-prototypes.  */
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM);
-# else
-int yyparse ();
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void);
-#else
-int yyparse ();
-#endif
-#endif /* ! YYPARSE_PARAM */
-
-
-
-/* The look-ahead symbol.  */
-int yychar;
-
-/* The semantic value of the look-ahead symbol.  */
-YYSTYPE yylval;
-
-/* Number of syntax errors so far.  */
-int yynerrs;
-
-
-
-/*----------.
-| yyparse.  |
-`----------*/
-
-#ifdef YYPARSE_PARAM
-# if defined (__STDC__) || defined (__cplusplus)
-int yyparse (void *YYPARSE_PARAM)
-# else
-int yyparse (YYPARSE_PARAM)
-  void *YYPARSE_PARAM;
-# endif
-#else /* ! YYPARSE_PARAM */
-#if defined (__STDC__) || defined (__cplusplus)
-int
-yyparse (void)
-#else
-int
-yyparse ()
-    ;
-#endif
-#endif
-{
-  
-  int yystate;
-  int yyn;
-  int yyresult;
-  /* Number of tokens to shift before error messages enabled.  */
-  int yyerrstatus;
-  /* Look-ahead token as an internal (translated) token number.  */
-  int yytoken = 0;
-
-  /* Three stacks and their tools:
-     `yyss': related to states,
-     `yyvs': related to semantic values,
-     `yyls': related to locations.
-
-     Refer to the stacks thru separate pointers, to allow yyoverflow
-     to reallocate them elsewhere.  */
-
-  /* The state stack.  */
-  short int yyssa[YYINITDEPTH];
-  short int *yyss = yyssa;
-  short int *yyssp;
-
-  /* The semantic value stack.  */
-  YYSTYPE yyvsa[YYINITDEPTH];
-  YYSTYPE *yyvs = yyvsa;
-  YYSTYPE *yyvsp;
-
-
-
-#define YYPOPSTACK   (yyvsp--, yyssp--)
-
-  YYSIZE_T yystacksize = YYINITDEPTH;
-
-  /* The variables used to return semantic value and location from the
-     action routines.  */
-  YYSTYPE yyval;
-
-
-  /* When reducing, the number of symbols on the RHS of the reduced
-     rule.  */
-  int yylen;
-
-  YYDPRINTF ((stderr, "Starting parse\n"));
-
-  yystate = 0;
-  yyerrstatus = 0;
-  yynerrs = 0;
-  yychar = YYEMPTY;		/* Cause a token to be read.  */
-
-  /* Initialize stack pointers.
-     Waste one element of value and location stack
-     so that they stay on the same level as the state stack.
-     The wasted elements are never initialized.  */
-
-  yyssp = yyss;
-  yyvsp = yyvs;
-
-  goto yysetstate;
-
-/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate.  |
-`------------------------------------------------------------*/
- yynewstate:
-  /* In all cases, when you get here, the value and location stacks
-     have just been pushed. so pushing a state here evens the stacks.
-     */
-  yyssp++;
-
- yysetstate:
-  *yyssp = yystate;
-
-  if (yyss + yystacksize - 1 <= yyssp)
-    {
-      /* Get the current used size of the three stacks, in elements.  */
-      YYSIZE_T yysize = yyssp - yyss + 1;
-
-#ifdef yyoverflow
-      {
-	/* Give user a chance to reallocate the stack. Use copies of
-	   these so that the &'s don't force the real ones into
-	   memory.  */
-	YYSTYPE *yyvs1 = yyvs;
-	short int *yyss1 = yyss;
-
-
-	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  This used to be a
-	   conditional around just the two extra args, but that might
-	   be undefined if yyoverflow is a macro.  */
-	yyoverflow (YY_("memory exhausted"),
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-
-		    &yystacksize);
-
-	yyss = yyss1;
-	yyvs = yyvs1;
-      }
-#else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
-      goto yyexhaustedlab;
-# else
-      /* Extend the stack our own way.  */
-      if (YYMAXDEPTH <= yystacksize)
-	goto yyexhaustedlab;
-      yystacksize *= 2;
-      if (YYMAXDEPTH < yystacksize)
-	yystacksize = YYMAXDEPTH;
-
-      {
-	short int *yyss1 = yyss;
-	union yyalloc *yyptr =
-	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-	if (! yyptr)
-	  goto yyexhaustedlab;
-	YYSTACK_RELOCATE (yyss);
-	YYSTACK_RELOCATE (yyvs);
-
-#  undef YYSTACK_RELOCATE
-	if (yyss1 != yyssa)
-	  YYSTACK_FREE (yyss1);
-      }
-# endif
-#endif /* no yyoverflow */
-
-      yyssp = yyss + yysize - 1;
-      yyvsp = yyvs + yysize - 1;
-
-
-      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-		  (unsigned long int) yystacksize));
-
-      if (yyss + yystacksize - 1 <= yyssp)
-	YYABORT;
-    }
-
-  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
-
-  goto yybackup;
-
-/*-----------.
-| yybackup.  |
-`-----------*/
-yybackup:
-
-/* Do appropriate processing given the current state.  */
-/* Read a look-ahead token if we need one and don't already have one.  */
-/* yyresume: */
-
-  /* First try to decide what to do without reference to look-ahead token.  */
-
-  yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
-    goto yydefault;
-
-  /* Not known => get a look-ahead token if don't already have one.  */
-
-  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
-  if (yychar == YYEMPTY)
-    {
-      YYDPRINTF ((stderr, "Reading a token: "));
-      yychar = YYLEX;
-    }
-
-  if (yychar <= YYEOF)
-    {
-      yychar = yytoken = YYEOF;
-      YYDPRINTF ((stderr, "Now at end of input.\n"));
-    }
-  else
-    {
-      yytoken = YYTRANSLATE (yychar);
-      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
-    }
-
-  /* If the proper action on seeing token YYTOKEN is to reduce or to
-     detect an error, take that action.  */
-  yyn += yytoken;
-  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
-    goto yydefault;
-  yyn = yytable[yyn];
-  if (yyn <= 0)
-    {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-	goto yyerrlab;
-      yyn = -yyn;
-      goto yyreduce;
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  /* Shift the look-ahead token.  */
-  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
-
-  /* Discard the token being shifted unless it is eof.  */
-  if (yychar != YYEOF)
-    yychar = YYEMPTY;
-
-  *++yyvsp = yylval;
-
-
-  /* Count tokens shifted since error; after three, turn off error
-     status.  */
-  if (yyerrstatus)
-    yyerrstatus--;
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-----------------------------------------------------------.
-| yydefault -- do the default action for the current state.  |
-`-----------------------------------------------------------*/
-yydefault:
-  yyn = yydefact[yystate];
-  if (yyn == 0)
-    goto yyerrlab;
-  goto yyreduce;
-
-
-/*-----------------------------.
-| yyreduce -- Do a reduction.  |
-`-----------------------------*/
-yyreduce:
-  /* yyn is the number of a rule to reduce with.  */
-  yylen = yyr2[yyn];
-
-  /* If YYLEN is nonzero, implement the default value of the action:
-     `$$ = $1'.
-
-     Otherwise, the following line sets YYVAL to garbage.
-     This behavior is undocumented and Bison
-     users should not rely upon it.  Assigning to YYVAL
-     unconditionally makes the parser a bit smaller, and it avoids a
-     GCC warning that YYVAL may be used uninitialized.  */
-  yyval = yyvsp[1-yylen];
-
-
-  YY_REDUCE_PRINT (yyn);
-  switch (yyn)
-    {
-        case 3:
-#line 123 "m68k-parse.y"
-    {
-		  op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
-		}
-    break;
-
-  case 4:
-#line 127 "m68k-parse.y"
-    {
-		  op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
-		}
-    break;
-
-  case 5:
-#line 135 "m68k-parse.y"
-    { (yyval.trailing_ampersand) = 0; }
-    break;
-
-  case 6:
-#line 137 "m68k-parse.y"
-    { (yyval.trailing_ampersand) = 1; }
-    break;
-
-  case 7:
-#line 144 "m68k-parse.y"
-    {
-		  op->mode = LSH;
-		}
-    break;
-
-  case 8:
-#line 149 "m68k-parse.y"
-    {
-		  op->mode = RSH;
-		}
-    break;
-
-  case 9:
-#line 154 "m68k-parse.y"
-    {
-		  op->mode = DREG;
-		  op->reg = (yyvsp[0].reg);
-		}
-    break;
-
-  case 10:
-#line 159 "m68k-parse.y"
-    {
-		  op->mode = AREG;
-		  op->reg = (yyvsp[0].reg);
-		}
-    break;
-
-  case 11:
-#line 164 "m68k-parse.y"
-    {
-		  op->mode = FPREG;
-		  op->reg = (yyvsp[0].reg);
-		}
-    break;
-
-  case 12:
-#line 169 "m68k-parse.y"
-    {
-		  op->mode = CONTROL;
-		  op->reg = (yyvsp[0].reg);
-		}
-    break;
-
-  case 13:
-#line 174 "m68k-parse.y"
-    {
-		  op->mode = CONTROL;
-		  op->reg = (yyvsp[0].reg);
-		}
-    break;
-
-  case 14:
-#line 179 "m68k-parse.y"
-    {
-		  op->mode = ABSL;
-		  op->disp = (yyvsp[0].exp);
-		}
-    break;
-
-  case 15:
-#line 184 "m68k-parse.y"
-    {
-		  op->mode = IMMED;
-		  op->disp = (yyvsp[0].exp);
-		}
-    break;
-
-  case 16:
-#line 189 "m68k-parse.y"
-    {
-		  op->mode = IMMED;
-		  op->disp = (yyvsp[0].exp);
-		}
-    break;
-
-  case 17:
-#line 194 "m68k-parse.y"
-    {
-		  op->mode = REGLST;
-		  op->mask = (yyvsp[0].mask);
-		}
-    break;
-
-  case 18:
-#line 207 "m68k-parse.y"
-    {
-		  op->mode = AINDR;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 19:
-#line 212 "m68k-parse.y"
-    {
-		  op->mode = AINC;
-		  op->reg = (yyvsp[-2].reg);
-		}
-    break;
-
-  case 20:
-#line 217 "m68k-parse.y"
-    {
-		  op->mode = ADEC;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 21:
-#line 222 "m68k-parse.y"
-    {
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-3].exp);
-		  if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
-		      || (yyvsp[-1].reg) == ZPC)
-		    op->mode = BASE;
-		  else
-		    op->mode = DISP;
-		}
-    break;
-
-  case 22:
-#line 232 "m68k-parse.y"
-    {
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-1].exp);
-		  if (((yyvsp[-3].reg) >= ZADDR0 && (yyvsp[-3].reg) <= ZADDR7)
-		      || (yyvsp[-3].reg) == ZPC)
-		    op->mode = BASE;
-		  else
-		    op->mode = DISP;
-		}
-    break;
-
-  case 23:
-#line 242 "m68k-parse.y"
-    {
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-3].exp);
-		  if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
-		      || (yyvsp[-1].reg) == ZPC)
-		    op->mode = BASE;
-		  else
-		    op->mode = DISP;
-		}
-    break;
-
-  case 24:
-#line 252 "m68k-parse.y"
-    {
-		  op->mode = DISP;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 25:
-#line 257 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 26:
-#line 262 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 27:
-#line 267 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->index = (yyvsp[-1].indexreg);
-		}
-    break;
-
-  case 28:
-#line 274 "m68k-parse.y"
-    {
-		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
-		    yyerror (_("syntax error"));
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->index.reg = (yyvsp[-3].reg);
-		  op->index.size = SIZE_UNSPEC;
-		  op->index.scale = 1;
-		}
-    break;
-
-  case 29:
-#line 285 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-4].exp);
-		  op->index = (yyvsp[-2].indexreg);
-		}
-    break;
-
-  case 30:
-#line 292 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->disp = (yyvsp[-1].exp);
-		  op->index = (yyvsp[-3].indexreg);
-		}
-    break;
-
-  case 31:
-#line 298 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->index = (yyvsp[-1].indexreg);
-		}
-    break;
-
-  case 32:
-#line 305 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->index = (yyvsp[-1].indexreg);
-		}
-    break;
-
-  case 33:
-#line 311 "m68k-parse.y"
-    {
-		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
-		    yyerror (_("syntax error"));
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->index.reg = (yyvsp[-3].reg);
-		  op->index.size = SIZE_UNSPEC;
-		  op->index.scale = 1;
-		}
-    break;
-
-  case 34:
-#line 322 "m68k-parse.y"
-    {
-		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
-		    yyerror (_("syntax error"));
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->index.reg = (yyvsp[-3].reg);
-		  op->index.size = SIZE_UNSPEC;
-		  op->index.scale = 1;
-		}
-    break;
-
-  case 35:
-#line 332 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->disp = (yyvsp[-4].exp);
-		  op->index = (yyvsp[-2].indexreg);
-		}
-    break;
-
-  case 36:
-#line 339 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-1].reg);
-		  op->index = (yyvsp[-2].indexreg);
-		}
-    break;
-
-  case 37:
-#line 345 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-5].reg);
-		  op->disp = (yyvsp[-6].exp);
-		  op->index = (yyvsp[-2].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 38:
-#line 353 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-4].exp);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 39:
-#line 360 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-5].reg);
-		  op->index = (yyvsp[-2].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 40:
-#line 367 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-3].reg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 41:
-#line 373 "m68k-parse.y"
-    {
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-5].reg);
-		  op->disp = (yyvsp[-7].exp);
-		  op->index = (yyvsp[-3].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 42:
-#line 381 "m68k-parse.y"
-    {
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-5].reg);
-		  op->index = (yyvsp[-3].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 43:
-#line 388 "m68k-parse.y"
-    {
-		  if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
-		    yyerror (_("syntax error"));
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-7].exp);
-		  op->index.reg = (yyvsp[-5].reg);
-		  op->index.size = SIZE_UNSPEC;
-		  op->index.scale = 1;
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 44:
-#line 400 "m68k-parse.y"
-    {
-		  if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
-		    yyerror (_("syntax error"));
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->index.reg = (yyvsp[-5].reg);
-		  op->index.size = SIZE_UNSPEC;
-		  op->index.scale = 1;
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 45:
-#line 411 "m68k-parse.y"
-    {
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-3].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->index = (yyvsp[-4].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 46:
-#line 424 "m68k-parse.y"
-    {
-		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if ((yyvsp[-1].reg) < ADDR0 || (yyvsp[-1].reg) > ADDR7)
-		    yyerror (_("syntax error"));
-		  op->mode = AINDR;
-		  op->reg = (yyvsp[-1].reg);
-		}
-    break;
-
-  case 47:
-#line 432 "m68k-parse.y"
-    {
-		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
-		    yyerror (_("syntax error"));
-		  op->mode = AINC;
-		  op->reg = (yyvsp[-2].reg);
-		}
-    break;
-
-  case 48:
-#line 440 "m68k-parse.y"
-    {
-		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
-		    yyerror (_("syntax error"));
-		  op->mode = ADEC;
-		  op->reg = (yyvsp[-2].reg);
-		}
-    break;
-
-  case 49:
-#line 448 "m68k-parse.y"
-    {
-		  op->reg = (yyvsp[-4].reg);
-		  op->disp = (yyvsp[-1].exp);
-		  if (((yyvsp[-4].reg) >= ZADDR0 && (yyvsp[-4].reg) <= ZADDR7)
-		      || (yyvsp[-4].reg) == ZPC)
-		    op->mode = BASE;
-		  else
-		    op->mode = DISP;
-		}
-    break;
-
-  case 50:
-#line 458 "m68k-parse.y"
-    {
-		  op->mode = BASE;
-		  op->reg = (yyvsp[-5].reg);
-		  op->disp = (yyvsp[-2].exp);
-		  op->index = (yyvsp[-1].indexreg);
-		}
-    break;
-
-  case 51:
-#line 465 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-9].reg);
-		  op->disp = (yyvsp[-6].exp);
-		  op->index = (yyvsp[-1].indexreg);
-		  op->odisp = (yyvsp[-2].exp);
-		}
-    break;
-
-  case 52:
-#line 473 "m68k-parse.y"
-    {
-		  op->mode = POST;
-		  op->reg = (yyvsp[-8].reg);
-		  op->disp = (yyvsp[-5].exp);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 53:
-#line 480 "m68k-parse.y"
-    {
-		  op->mode = PRE;
-		  op->reg = (yyvsp[-9].reg);
-		  op->disp = (yyvsp[-6].exp);
-		  op->index = (yyvsp[-5].indexreg);
-		  op->odisp = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 55:
-#line 495 "m68k-parse.y"
-    {
-		  (yyval.indexreg).reg = (yyvsp[0].reg);
-		  (yyval.indexreg).size = SIZE_UNSPEC;
-		  (yyval.indexreg).scale = 1;
-		}
-    break;
-
-  case 57:
-#line 509 "m68k-parse.y"
-    {
-		  (yyval.indexreg).reg = (yyvsp[0].reg);
-		  (yyval.indexreg).size = SIZE_UNSPEC;
-		  (yyval.indexreg).scale = 1;
-		}
-    break;
-
-  case 68:
-#line 552 "m68k-parse.y"
-    {
-		  (yyval.reg) = ZADDR0;
-		}
-    break;
-
-  case 72:
-#line 569 "m68k-parse.y"
-    {
-		  (yyval.reg) = ZADDR0;
-		}
-    break;
-
-  case 73:
-#line 573 "m68k-parse.y"
-    {
-		  (yyval.reg) = (yyvsp[0].reg);
-		}
-    break;
-
-  case 74:
-#line 582 "m68k-parse.y"
-    {
-		  (yyval.exp).exp.X_op = O_absent;
-		  (yyval.exp).size = SIZE_UNSPEC;
-		}
-    break;
-
-  case 75:
-#line 587 "m68k-parse.y"
-    {
-		  (yyval.exp) = (yyvsp[0].exp);
-		}
-    break;
-
-  case 76:
-#line 596 "m68k-parse.y"
-    {
-		  (yyval.exp).exp.X_op = O_absent;
-		  (yyval.exp).size = SIZE_UNSPEC;
-		}
-    break;
-
-  case 77:
-#line 601 "m68k-parse.y"
-    {
-		  (yyval.exp) = (yyvsp[-1].exp);
-		}
-    break;
-
-  case 79:
-#line 611 "m68k-parse.y"
-    {
-		  (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
-		}
-    break;
-
-  case 80:
-#line 615 "m68k-parse.y"
-    {
-		  (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
-		}
-    break;
-
-  case 81:
-#line 627 "m68k-parse.y"
-    {
-		  (yyval.mask) = 1 << (yyvsp[0].onereg);
-		}
-    break;
-
-  case 83:
-#line 632 "m68k-parse.y"
-    {
-		  (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
-		}
-    break;
-
-  case 84:
-#line 636 "m68k-parse.y"
-    {
-		  (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
-		}
-    break;
-
-  case 85:
-#line 643 "m68k-parse.y"
-    {
-		  if ((yyvsp[-2].onereg) <= (yyvsp[0].onereg))
-		    (yyval.mask) = (1 << ((yyvsp[0].onereg) + 1)) - 1 - ((1 << (yyvsp[-2].onereg)) - 1);
-		  else
-		    (yyval.mask) = (1 << ((yyvsp[-2].onereg) + 1)) - 1 - ((1 << (yyvsp[0].onereg)) - 1);
-		}
-    break;
-
-  case 86:
-#line 653 "m68k-parse.y"
-    {
-		  (yyval.onereg) = (yyvsp[0].reg) - DATA0;
-		}
-    break;
-
-  case 87:
-#line 657 "m68k-parse.y"
-    {
-		  (yyval.onereg) = (yyvsp[0].reg) - ADDR0 + 8;
-		}
-    break;
-
-  case 88:
-#line 661 "m68k-parse.y"
-    {
-		  (yyval.onereg) = (yyvsp[0].reg) - FP0 + 16;
-		}
-    break;
-
-  case 89:
-#line 665 "m68k-parse.y"
-    {
-		  if ((yyvsp[0].reg) == FPI)
-		    (yyval.onereg) = 24;
-		  else if ((yyvsp[0].reg) == FPS)
-		    (yyval.onereg) = 25;
-		  else
-		    (yyval.onereg) = 26;
-		}
-    break;
-
-
-      default: break;
-    }
-
-/* Line 1126 of yacc.c.  */
-#line 1986 "m68k-parse.c"
-
-  yyvsp -= yylen;
-  yyssp -= yylen;
-
-
-  YY_STACK_PRINT (yyss, yyssp);
-
-  *++yyvsp = yyval;
-
-
-  /* Now `shift' the result of the reduction.  Determine what state
-     that goes to, based on the state we popped back to and the rule
-     number reduced by.  */
-
-  yyn = yyr1[yyn];
-
-  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
-  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
-    yystate = yytable[yystate];
-  else
-    yystate = yydefgoto[yyn - YYNTOKENS];
-
-  goto yynewstate;
-
-
-/*------------------------------------.
-| yyerrlab -- here on detecting error |
-`------------------------------------*/
-yyerrlab:
-  /* If not already recovering from an error, report this error.  */
-  if (!yyerrstatus)
-    {
-      ++yynerrs;
-#if YYERROR_VERBOSE
-      yyn = yypact[yystate];
-
-      if (YYPACT_NINF < yyn && yyn < YYLAST)
-	{
-	  int yytype = YYTRANSLATE (yychar);
-	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-	  YYSIZE_T yysize = yysize0;
-	  YYSIZE_T yysize1;
-	  int yysize_overflow = 0;
-	  char *yymsg = 0;
-#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
-	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-	  int yyx;
-
-#if 0
-	  /* This is so xgettext sees the translatable formats that are
-	     constructed on the fly.  */
-	  YY_("syntax error, unexpected %s");
-	  YY_("syntax error, unexpected %s, expecting %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-#endif
-	  char *yyfmt;
-	  char const *yyf;
-	  static char const yyunexpected[] = "syntax error, unexpected %s";
-	  static char const yyexpecting[] = ", expecting %s";
-	  static char const yyor[] = " or %s";
-	  char yyformat[sizeof yyunexpected
-			+ sizeof yyexpecting - 1
-			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-			   * (sizeof yyor - 1))];
-	  char const *yyprefix = yyexpecting;
-
-	  /* Start YYX at -YYN if negative to avoid negative indexes in
-	     YYCHECK.  */
-	  int yyxbegin = yyn < 0 ? -yyn : 0;
-
-	  /* Stay within bounds of both yycheck and yytname.  */
-	  int yychecklim = YYLAST - yyn;
-	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-	  int yycount = 1;
-
-	  yyarg[0] = yytname[yytype];
-	  yyfmt = yystpcpy (yyformat, yyunexpected);
-
-	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-	      {
-		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-		  {
-		    yycount = 1;
-		    yysize = yysize0;
-		    yyformat[sizeof yyunexpected - 1] = '\0';
-		    break;
-		  }
-		yyarg[yycount++] = yytname[yyx];
-		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-		yysize_overflow |= yysize1 < yysize;
-		yysize = yysize1;
-		yyfmt = yystpcpy (yyfmt, yyprefix);
-		yyprefix = yyor;
-	      }
-
-	  yyf = YY_(yyformat);
-	  yysize1 = yysize + yystrlen (yyf);
-	  yysize_overflow |= yysize1 < yysize;
-	  yysize = yysize1;
-
-	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
-	    yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg)
-	    {
-	      /* Avoid sprintf, as that infringes on the user's name space.
-		 Don't have undefined behavior even if the translation
-		 produced a string with the wrong number of "%s"s.  */
-	      char *yyp = yymsg;
-	      int yyi = 0;
-	      while ((*yyp = *yyf))
-		{
-		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-		    {
-		      yyp += yytnamerr (yyp, yyarg[yyi++]);
-		      yyf += 2;
-		    }
-		  else
-		    {
-		      yyp++;
-		      yyf++;
-		    }
-		}
-	      yyerror (yymsg);
-	      YYSTACK_FREE (yymsg);
-	    }
-	  else
-	    {
-	      yyerror (YY_("syntax error"));
-	      goto yyexhaustedlab;
-	    }
-	}
-      else
-#endif /* YYERROR_VERBOSE */
-	yyerror (YY_("syntax error"));
-    }
-
-
-
-  if (yyerrstatus == 3)
-    {
-      /* If just tried and failed to reuse look-ahead token after an
-	 error, discard it.  */
-
-      if (yychar <= YYEOF)
-        {
-	  /* Return failure if at end of input.  */
-	  if (yychar == YYEOF)
-	    YYABORT;
-        }
-      else
-	{
-	  yydestruct ("Error: discarding", yytoken, &yylval);
-	  yychar = YYEMPTY;
-	}
-    }
-
-  /* Else will try to reuse look-ahead token after shifting the error
-     token.  */
-  goto yyerrlab1;
-
-
-/*---------------------------------------------------.
-| yyerrorlab -- error raised explicitly by YYERROR.  |
-`---------------------------------------------------*/
-yyerrorlab:
-
-  /* Pacify compilers like GCC when the user code never invokes
-     YYERROR and the label yyerrorlab therefore never appears in user
-     code.  */
-  if (0)
-     goto yyerrorlab;
-
-yyvsp -= yylen;
-  yyssp -= yylen;
-  yystate = *yyssp;
-  goto yyerrlab1;
-
-
-/*-------------------------------------------------------------.
-| yyerrlab1 -- common code for both syntax error and YYERROR.  |
-`-------------------------------------------------------------*/
-yyerrlab1:
-  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
-
-  for (;;)
-    {
-      yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
-	{
-	  yyn += YYTERROR;
-	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-	    {
-	      yyn = yytable[yyn];
-	      if (0 < yyn)
-		break;
-	    }
-	}
-
-      /* Pop the current state because it cannot handle the error token.  */
-      if (yyssp == yyss)
-	YYABORT;
-
-
-      yydestruct ("Error: popping", yystos[yystate], yyvsp);
-      YYPOPSTACK;
-      yystate = *yyssp;
-      YY_STACK_PRINT (yyss, yyssp);
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  *++yyvsp = yylval;
-
-
-  /* Shift the error token. */
-  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-------------------------------------.
-| yyacceptlab -- YYACCEPT comes here.  |
-`-------------------------------------*/
-yyacceptlab:
-  yyresult = 0;
-  goto yyreturn;
-
-/*-----------------------------------.
-| yyabortlab -- YYABORT comes here.  |
-`-----------------------------------*/
-yyabortlab:
-  yyresult = 1;
-  goto yyreturn;
-
-#ifndef yyoverflow
-/*-------------------------------------------------.
-| yyexhaustedlab -- memory exhaustion comes here.  |
-`-------------------------------------------------*/
-yyexhaustedlab:
-  yyerror (YY_("memory exhausted"));
-  yyresult = 2;
-  /* Fall through.  */
-#endif
-
-yyreturn:
-  if (yychar != YYEOF && yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-		 yytoken, &yylval);
-  while (yyssp != yyss)
-    {
-      yydestruct ("Cleanup: popping",
-		  yystos[*yyssp], yyvsp);
-      YYPOPSTACK;
-    }
-#ifndef yyoverflow
-  if (yyss != yyssa)
-    YYSTACK_FREE (yyss);
-#endif
-  return yyresult;
-}
-
-
-#line 675 "m68k-parse.y"
-
-
-/* The string to parse is stored here, and modified by yylex.  */
-
-static char *str;
-
-/* The original string pointer.  */
-
-static char *strorig;
-
-/* If *CCP could be a register, return the register number and advance
-   *CCP.  Otherwise don't change *CCP, and return 0.  */
-
-static enum m68k_register
-m68k_reg_parse (ccp)
-     register char **ccp;
-{
-  char *start = *ccp;
-  char c;
-  char *p;
-  symbolS *symbolp;
-
-  if (flag_reg_prefix_optional)
-    {
-      if (*start == REGISTER_PREFIX)
-	start++;
-      p = start;
-    }
-  else
-    {
-      if (*start != REGISTER_PREFIX)
-	return 0;
-      p = start + 1;
-    }
-
-  if (! is_name_beginner (*p))
-    return 0;
-
-  p++;
-  while (is_part_of_name (*p) && *p != '.' && *p != ':' && *p != '*')
-    p++;
-
-  c = *p;
-  *p = 0;
-  symbolp = symbol_find (start);
-  *p = c;
-
-  if (symbolp != NULL && S_GET_SEGMENT (symbolp) == reg_section)
-    {
-      *ccp = p;
-      return S_GET_VALUE (symbolp);
-    }
-
-  /* In MRI mode, something like foo.bar can be equated to a register
-     name.  */
-  while (flag_mri && c == '.')
-    {
-      ++p;
-      while (is_part_of_name (*p) && *p != '.' && *p != ':' && *p != '*')
-	p++;
-      c = *p;
-      *p = '\0';
-      symbolp = symbol_find (start);
-      *p = c;
-      if (symbolp != NULL && S_GET_SEGMENT (symbolp) == reg_section)
-	{
-	  *ccp = p;
-	  return S_GET_VALUE (symbolp);
-	}
-    }
-
-  return 0;
-}
-
-/* The lexer.  */
-
-static int
-yylex ()
-{
-  enum m68k_register reg;
-  char *s;
-  int parens;
-  int c = 0;
-  int tail = 0;
-  char *hold;
-
-  if (*str == ' ')
-    ++str;
-
-  if (*str == '\0')
-    return 0;
-
-  /* Various special characters are just returned directly.  */
-  switch (*str)
-    {
-    case '@':
-      /* In MRI mode, this can be the start of an octal number.  */
-      if (flag_mri)
-	{
-	  if (ISDIGIT (str[1])
-	      || ((str[1] == '+' || str[1] == '-')
-		  && ISDIGIT (str[2])))
-	    break;
-	}
-      /* Fall through.  */
-    case '#':
-    case '&':
-    case ',':
-    case ')':
-    case '/':
-    case '[':
-    case ']':
-    case '<':
-    case '>':
-      return *str++;
-    case '+':
-      /* It so happens that a '+' can only appear at the end of an
-	 operand, or if it is trailed by an '&'(see mac load insn).
-	 If it appears anywhere else, it must be a unary.  */
-      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
-	return *str++;
-      break;
-    case '-':
-      /* A '-' can only appear in -(ar), rn-rn, or ar@-.  If it
-         appears anywhere else, it must be a unary minus on an
-         expression, unless it it trailed by a '&'(see mac load insn).  */
-      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
-	return *str++;
-      s = str + 1;
-      if (*s == '(')
-	++s;
-      if (m68k_reg_parse (&s) != 0)
-	return *str++;
-      break;
-    case '(':
-      /* A '(' can only appear in `(reg)', `(expr,...', `([', `@(', or
-         `)('.  If it appears anywhere else, it must be starting an
-         expression.  */
-      if (str[1] == '['
-	  || (str > strorig
-	      && (str[-1] == '@'
-		  || str[-1] == ')')))
-	return *str++;
-      s = str + 1;
-      if (m68k_reg_parse (&s) != 0)
-	return *str++;
-      /* Check for the case of '(expr,...' by scanning ahead.  If we
-         find a comma outside of balanced parentheses, we return '('.
-         If we find an unbalanced right parenthesis, then presumably
-         the '(' really starts an expression.  */
-      parens = 0;
-      for (s = str + 1; *s != '\0'; s++)
-	{
-	  if (*s == '(')
-	    ++parens;
-	  else if (*s == ')')
-	    {
-	      if (parens == 0)
-		break;
-	      --parens;
-	    }
-	  else if (*s == ',' && parens == 0)
-	    {
-	      /* A comma can not normally appear in an expression, so
-		 this is a case of '(expr,...'.  */
-	      return *str++;
-	    }
-	}
-    }
-
-  /* See if it's a register.  */
-
-  reg = m68k_reg_parse (&str);
-  if (reg != 0)
-    {
-      int ret;
-
-      yylval.reg = reg;
-
-      if (reg >= DATA0 && reg <= DATA7)
-	ret = DR;
-      else if (reg >= ADDR0 && reg <= ADDR7)
-	ret = AR;
-      else if (reg >= FP0 && reg <= FP7)
-	return FPR;
-      else if (reg == FPI
-	       || reg == FPS
-	       || reg == FPC)
-	return FPCR;
-      else if (reg == PC)
-	return LPC;
-      else if (reg >= ZDATA0 && reg <= ZDATA7)
-	ret = ZDR;
-      else if (reg >= ZADDR0 && reg <= ZADDR7)
-	ret = ZAR;
-      else if (reg == ZPC)
-	return LZPC;
-      else
-	return CREG;
-
-      /* If we get here, we have a data or address register.  We
-	 must check for a size or scale; if we find one, we must
-	 return INDEXREG.  */
-
-      s = str;
-
-      if (*s != '.' && *s != ':' && *s != '*')
-	return ret;
-
-      yylval.indexreg.reg = reg;
-
-      if (*s != '.' && *s != ':')
-	yylval.indexreg.size = SIZE_UNSPEC;
-      else
-	{
-	  ++s;
-	  switch (*s)
-	    {
-	    case 'w':
-	    case 'W':
-	      yylval.indexreg.size = SIZE_WORD;
-	      ++s;
-	      break;
-	    case 'l':
-	    case 'L':
-	      yylval.indexreg.size = SIZE_LONG;
-	      ++s;
-	      break;
-	    default:
-	      yyerror (_("illegal size specification"));
-	      yylval.indexreg.size = SIZE_UNSPEC;
-	      break;
-	    }
-	}
-
-      yylval.indexreg.scale = 1;
-
-      if (*s == '*' || *s == ':')
-	{
-	  expressionS scale;
-
-	  ++s;
-
-	  hold = input_line_pointer;
-	  input_line_pointer = s;
-	  expression (&scale);
-	  s = input_line_pointer;
-	  input_line_pointer = hold;
-
-	  if (scale.X_op != O_constant)
-	    yyerror (_("scale specification must resolve to a number"));
-	  else
-	    {
-	      switch (scale.X_add_number)
-		{
-		case 1:
-		case 2:
-		case 4:
-		case 8:
-		  yylval.indexreg.scale = scale.X_add_number;
-		  break;
-		default:
-		  yyerror (_("invalid scale value"));
-		  break;
-		}
-	    }
-	}
-
-      str = s;
-
-      return INDEXREG;
-    }
-
-  /* It must be an expression.  Before we call expression, we need to
-     look ahead to see if there is a size specification.  We must do
-     that first, because otherwise foo.l will be treated as the symbol
-     foo.l, rather than as the symbol foo with a long size
-     specification.  The grammar requires that all expressions end at
-     the end of the operand, or with ',', '(', ']', ')'.  */
-
-  parens = 0;
-  for (s = str; *s != '\0'; s++)
-    {
-      if (*s == '(')
-	{
-	  if (parens == 0
-	      && s > str
-	      && (s[-1] == ')' || ISALNUM (s[-1])))
-	    break;
-	  ++parens;
-	}
-      else if (*s == ')')
-	{
-	  if (parens == 0)
-	    break;
-	  --parens;
-	}
-      else if (parens == 0
-	       && (*s == ',' || *s == ']'))
-	break;
-    }
-
-  yylval.exp.size = SIZE_UNSPEC;
-  if (s <= str + 2
-      || (s[-2] != '.' && s[-2] != ':'))
-    tail = 0;
-  else
-    {
-      switch (s[-1])
-	{
-	case 's':
-	case 'S':
-	case 'b':
-	case 'B':
-	  yylval.exp.size = SIZE_BYTE;
-	  break;
-	case 'w':
-	case 'W':
-	  yylval.exp.size = SIZE_WORD;
-	  break;
-	case 'l':
-	case 'L':
-	  yylval.exp.size = SIZE_LONG;
-	  break;
-	default:
-	  break;
-	}
-      if (yylval.exp.size != SIZE_UNSPEC)
-	tail = 2;
-    }
-
-#ifdef OBJ_ELF
-  {
-    /* Look for @PLTPC, etc.  */
-    char *cp;
-
-    yylval.exp.pic_reloc = pic_none;
-    cp = s - tail;
-    if (cp - 6 > str && cp[-6] == '@')
-      {
-	if (strncmp (cp - 6, "@PLTPC", 6) == 0)
-	  {
-	    yylval.exp.pic_reloc = pic_plt_pcrel;
-	    tail += 6;
-	  }
-	else if (strncmp (cp - 6, "@GOTPC", 6) == 0)
-	  {
-	    yylval.exp.pic_reloc = pic_got_pcrel;
-	    tail += 6;
-	  }
-      }
-    else if (cp - 4 > str && cp[-4] == '@')
-      {
-	if (strncmp (cp - 4, "@PLT", 4) == 0)
-	  {
-	    yylval.exp.pic_reloc = pic_plt_off;
-	    tail += 4;
-	  }
-	else if (strncmp (cp - 4, "@GOT", 4) == 0)
-	  {
-	    yylval.exp.pic_reloc = pic_got_off;
-	    tail += 4;
-	  }
-      }
-  }
-#endif
-
-  if (tail != 0)
-    {
-      c = s[-tail];
-      s[-tail] = 0;
-    }
-
-  hold = input_line_pointer;
-  input_line_pointer = str;
-  expression (&yylval.exp.exp);
-  str = input_line_pointer;
-  input_line_pointer = hold;
-
-  if (tail != 0)
-    {
-      s[-tail] = c;
-      str = s;
-    }
-
-  return EXPR;
-}
-
-/* Parse an m68k operand.  This is the only function which is called
-   from outside this file.  */
-
-int
-m68k_ip_op (s, oparg)
-     char *s;
-     struct m68k_op *oparg;
-{
-  memset (oparg, 0, sizeof *oparg);
-  oparg->error = NULL;
-  oparg->index.reg = ZDATA0;
-  oparg->index.scale = 1;
-  oparg->disp.exp.X_op = O_absent;
-  oparg->odisp.exp.X_op = O_absent;
-
-  str = strorig = s;
-  op = oparg;
-
-  return yyparse ();
-}
-
-/* The error handler.  */
-
-static void
-yyerror (s)
-     const char *s;
-{
-  op->error = s;
-}
-
-
diff --git a/gas/macro.c b/gas/macro.c
index af98bada6a86..d7d470b764eb 100644
--- a/gas/macro.c
+++ b/gas/macro.c
@@ -1,6 +1,6 @@
 /* macro.c - macro support for gas
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2005 Free Software Foundation, Inc.
+   2004, 2005, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -22,47 +22,11 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include "config.h"
-
-#ifndef __GNUC__
-# if HAVE_ALLOCA_H
-#  include <alloca.h>
-# else
-#  ifdef _AIX
-/* Indented so that pre-ansi C compilers will ignore it, rather than
-   choke on it.  Some versions of AIX require this to be the first
-   thing in the file.  */
- #pragma alloca
-#  else
-#   ifndef alloca /* predefined by HP cc +Olibcalls */
-#    if !defined (__STDC__) && !defined (__hpux)
-extern char *alloca ();
-#    else
-extern void *alloca ();
-#    endif /* __STDC__, __hpux */
-#   endif /* alloca */
-#  endif /* _AIX */
-# endif /* HAVE_ALLOCA_H */
-#endif /* __GNUC__ */
-
-#include <stdio.h>
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#include <strings.h>
-#endif
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
 #include "as.h"
-#include "libiberty.h"
 #include "safe-ctype.h"
 #include "sb.h"
-#include "hash.h"
 #include "macro.h"
 
-#include "asintl.h"
-
 /* The routines in this file handle macro definition and expansion.
    They are called by gas.  */
 
@@ -1025,7 +989,6 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
   sb t;
   formal_entry *ptr;
   formal_entry *f;
-  int is_positional = 0;
   int is_keyword = 0;
   int narg = 0;
   const char *err = NULL;
@@ -1116,8 +1079,6 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	}
       else
 	{
-	  /* This is a positional arg.  */
-	  is_positional = 1;
 	  if (is_keyword)
 	    {
 	      err = _("can't mix positional and keyword arguments");
@@ -1364,8 +1325,14 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
     }
   else
     {
+      bfd_boolean in_quotes = FALSE;
+
       if (irpc && in->ptr[idx] == '"')
-	++idx;
+	{
+	  in_quotes = TRUE;
+	  ++idx;
+	}
+
       while (idx < in->len)
 	{
 	  if (!irpc)
@@ -1376,6 +1343,9 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 		{
 		  int nxt;
 
+		  if (irpc)
+		    in_quotes = ! in_quotes;
+	  
 		  nxt = sb_skip_white (idx + 1, in);
 		  if (nxt >= in->len)
 		    {
@@ -1387,12 +1357,13 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 	      sb_add_char (&f.actual, in->ptr[idx]);
 	      ++idx;
 	    }
+
 	  err = macro_expand_body (&sub, out, &f, h, 0);
 	  if (err != NULL)
 	    break;
 	  if (!irpc)
 	    idx = sb_skip_comma (idx, in);
-	  else
+	  else if (! in_quotes)
 	    idx = sb_skip_white (idx, in);
 	}
     }
diff --git a/gas/macro.h b/gas/macro.h
index 4fdaa52d0974..104aeae6f02c 100644
--- a/gas/macro.h
+++ b/gas/macro.h
@@ -1,5 +1,5 @@
 /* macro.h - header file for macro support for gas
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004, 2006
    Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
@@ -26,9 +26,6 @@
 
 #define MACRO_H
 
-#include "ansidecl.h"
-#include "sb.h"
-
 /* Structures used to store macros.
 
    Each macro knows its name and included text.  It gets built with a
diff --git a/gas/messages.c b/gas/messages.c
index b1b94cdf7c6e..c8788dcc32d5 100644
--- a/gas/messages.c
+++ b/gas/messages.c
@@ -1,6 +1,6 @@
 /* messages.c - error reporter -
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001,
-   2003, 2004, 2005
+   2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -116,24 +116,6 @@ as_show_where (void)
     fprintf (stderr, "%s:%u: ", file, line);
 }
 
-/* Like perror(3), but with more info.  */
-
-void
-as_perror (const char *gripe,		/* Unpunctuated error theme.  */
-	   const char *filename)
-{
-  const char *errtxt;
-  int saved_errno = errno;
-
-  as_show_where ();
-  fprintf (stderr, gripe, filename);
-  errno = saved_errno;
-  errtxt = bfd_errmsg (bfd_get_error ());
-  fprintf (stderr, ": %s\n", errtxt);
-  errno = 0;
-  bfd_set_error (bfd_error_no_error);
-}
-
 /* Send to stderr a string as a warning, and locate warning
    in input file(s).
    Please only use this for when we have some recovery action.
@@ -474,6 +456,24 @@ as_internal_value_out_of_range (char *    prefix,
   if (prefix == NULL)
     prefix = "";
 
+  if (val >= min && val <= max)
+    {
+      addressT right = max & -max;
+
+      if (max <= 1)
+	abort ();
+
+      /* xgettext:c-format  */
+      err = _("%s out of domain (%d is not a multiple of %d)");
+      if (bad)
+	as_bad_where (file, line, err,
+		      prefix, (int) val, (int) right);
+      else
+	as_warn_where (file, line, err,
+		       prefix, (int) val, (int) right);
+      return;
+    }
+
   if (   val < HEX_MAX_THRESHOLD
       && min < HEX_MAX_THRESHOLD
       && max < HEX_MAX_THRESHOLD
diff --git a/gas/output-file.c b/gas/output-file.c
index f94359ab6b0a..9603dc4f38a0 100644
--- a/gas/output-file.c
+++ b/gas/output-file.c
@@ -1,6 +1,6 @@
 /* output-file.c -  Deal with the output file
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1996, 1998, 1999, 2001,
-   2003, 2004, 2005 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -19,17 +19,13 @@
    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include <stdio.h>
-
 #include "as.h"
-
 #include "output-file.h"
 
 #ifndef TARGET_MACH
 #define TARGET_MACH 0
 #endif
 
-#include "bfd.h"
 bfd *stdoutput;
 
 void
@@ -40,11 +36,12 @@ output_file_create (char *name)
 
   else if (!(stdoutput = bfd_openw (name, TARGET_FORMAT)))
     {
-      if (bfd_get_error () == bfd_error_invalid_target)
-	as_perror (_("Selected target format '%s' unknown"), TARGET_FORMAT);
+      bfd_error_type err = bfd_get_error ();
+
+      if (err == bfd_error_invalid_target)
+	as_fatal (_("selected target format '%s' unknown"), TARGET_FORMAT);
       else
-	as_perror (_("FATAL: can't create %s"), name);
-      exit (EXIT_FAILURE);
+	as_fatal (_("can't create %s: %s"), name, bfd_errmsg (err));
     }
 
   bfd_set_format (stdoutput, bfd_object);
@@ -56,12 +53,19 @@ output_file_create (char *name)
 void
 output_file_close (char *filename)
 {
+  bfd_boolean res;
+
+  if (stdoutput == NULL)
+    return;
+    
   /* Close the bfd.  */
-  if (bfd_close (stdoutput) == 0)
-    {
-      bfd_perror (filename);
-      as_perror (_("FATAL: can't close %s\n"), filename);
-      exit (EXIT_FAILURE);
-    }
-  stdoutput = NULL;		/* Trust nobody!  */
+  res = bfd_close (stdoutput);
+
+  /* Prevent an infinite loop - if the close failed we will call as_fatal
+     which will call xexit() which may call this function again...  */
+  stdoutput = NULL;
+
+  if (! res)
+    as_fatal (_("can't close %s: %s"), filename,
+	      bfd_errmsg (bfd_get_error ()));
 }
diff --git a/gas/po/Make-in b/gas/po/Make-in
index be09b4cd788b..86ff3143b988 100644
--- a/gas/po/Make-in
+++ b/gas/po/Make-in
@@ -16,6 +16,7 @@ SHELL = /bin/sh
 srcdir = @srcdir@
 top_srcdir = @top_srcdir@
 VPATH = @srcdir@
+top_builddir = @top_builddir@
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -72,7 +73,7 @@ INSTOBJEXT = @INSTOBJEXT@
 	$(MSGFMT) -o $@ $<
 
 .po.gmo:
-	file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \
+	file=`echo $* | sed 's,.*/,,'`.gmo \
 	  && rm -f $$file && $(GMSGFMT) -o $$file $<
 
 .po.cat:
diff --git a/gas/po/POTFILES.in b/gas/po/POTFILES.in
index 3a173a536ff3..4215a09c7e86 100644
--- a/gas/po/POTFILES.in
+++ b/gas/po/POTFILES.in
@@ -24,8 +24,6 @@ config/obj-elf.c
 config/obj-elf.h
 config/obj-evax.c
 config/obj-evax.h
-config/obj-ieee.c
-config/obj-ieee.h
 config/obj-som.c
 config/obj-som.h
 config/tc-alpha.c
@@ -38,6 +36,8 @@ config/tc-avr.c
 config/tc-avr.h
 config/tc-bfin.c
 config/tc-bfin.h
+config/tc-cr16.c
+config/tc-cr16.h
 config/tc-cris.c
 config/tc-cris.h
 config/tc-crx.c
@@ -78,6 +78,8 @@ config/tc-m68k.c
 config/tc-m68k.h
 config/tc-mcore.c
 config/tc-mcore.h
+config/tc-mep.c
+config/tc-mep.h
 config/tc-mips.c
 config/tc-mips.h
 config/tc-mmix.c
@@ -102,12 +104,16 @@ config/tc-ppc.c
 config/tc-ppc.h
 config/tc-s390.c
 config/tc-s390.h
+config/tc-score.c
+config/tc-score.h
 config/tc-sh64.c
 config/tc-sh64.h
 config/tc-sh.c
 config/tc-sh.h
 config/tc-sparc.c
 config/tc-sparc.h
+config/tc-spu.c
+config/tc-spu.h
 config/tc-tic30.c
 config/tc-tic30.h
 config/tc-tic54x.c
diff --git a/gas/po/es.gmo b/gas/po/es.gmo
deleted file mode 100644
index f391e490b221..000000000000
--- a/gas/po/es.gmo
+++ /dev/null
diff --git a/gas/po/fr.gmo b/gas/po/fr.gmo
deleted file mode 100644
index 63ada106f5a9..000000000000
--- a/gas/po/fr.gmo
+++ /dev/null
diff --git a/gas/po/gas.pot b/gas/po/gas.pot
index 122a678aa4a0..575f36ef47b0 100644
--- a/gas/po/gas.pot
+++ b/gas/po/gas.pot
@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2005-10-25 08:41+0930\n"
+"POT-Creation-Date: 2007-07-02 15:56+0930\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -16,64 +16,64 @@ msgstr ""
 "Content-Type: text/plain; charset=CHARSET\n"
 "Content-Transfer-Encoding: 8bit\n"
 
-#: app.c:470 app.c:484
+#: app.c:473 app.c:487
 msgid "end of file in comment"
 msgstr ""
 
-#: app.c:560 app.c:605
+#: app.c:559 app.c:604
 #, c-format
 msgid "end of file in string; '%c' inserted"
 msgstr ""
 
-#: app.c:631
+#: app.c:630
 #, c-format
 msgid "unknown escape '\\%c' in string; ignored"
 msgstr ""
 
-#: app.c:786
+#: app.c:793
 msgid "end of file not at end of a line; newline inserted"
 msgstr ""
 
-#: app.c:945
+#: app.c:949
 msgid "end of file in multiline comment"
 msgstr ""
 
-#: app.c:1010
+#: app.c:1014
 msgid "end of file after a one-character quote; \\0 inserted"
 msgstr ""
 
-#: app.c:1018
+#: app.c:1022
 msgid "end of file in escape character"
 msgstr ""
 
-#: app.c:1030
+#: app.c:1034
 msgid "missing close quote; (assumed)"
 msgstr ""
 
-#: app.c:1098 app.c:1152 app.c:1163 app.c:1228
+#: app.c:1102 app.c:1156 app.c:1167 app.c:1241
 msgid "end of file in comment; newline inserted"
 msgstr ""
 
-#: as.c:161
+#: as.c:158
 msgid "missing emulation mode name"
 msgstr ""
 
-#: as.c:176
+#: as.c:173
 #, c-format
 msgid "unrecognized emulation name `%s'"
 msgstr ""
 
-#: as.c:223
+#: as.c:220
 #, c-format
 msgid "GNU assembler version %s (%s) using BFD version %s\n"
 msgstr ""
 
-#: as.c:230
+#: as.c:227
 #, c-format
 msgid "Usage: %s [option...] [asmfile...]\n"
 msgstr ""
 
-#: as.c:232
+#: as.c:229
 #, c-format
 msgid ""
 "Options:\n"
@@ -89,131 +89,131 @@ msgid ""
 "                      \t  =FILE  list to FILE (must be last sub-option)\n"
 msgstr ""
 
-#: as.c:245
+#: as.c:242
 #, c-format
 msgid "  --alternate             initially turn on alternate macro syntax\n"
 msgstr ""
 
-#: as.c:247
+#: as.c:244
 #, c-format
 msgid "  -D                      produce assembler debugging messages\n"
 msgstr ""
 
-#: as.c:249
+#: as.c:246
 #, c-format
 msgid "  --defsym SYM=VAL        define symbol SYM to given value\n"
 msgstr ""
 
-#: as.c:265
+#: as.c:262
 #, c-format
 msgid "                          emulate output (default %s)\n"
 msgstr ""
 
-#: as.c:270
+#: as.c:267
 #, c-format
 msgid "  --execstack             require executable stack for this object\n"
 msgstr ""
 
-#: as.c:272
+#: as.c:269
 #, c-format
 msgid ""
 "  --noexecstack           don't require executable stack for this object\n"
 msgstr ""
 
-#: as.c:275
+#: as.c:272
 #, c-format
 msgid "  -f                      skip whitespace and comment preprocessing\n"
 msgstr ""
 
-#: as.c:277
+#: as.c:274
 #, c-format
 msgid "  -g --gen-debug          generate debugging information\n"
 msgstr ""
 
-#: as.c:279
+#: as.c:276
 #, c-format
 msgid "  --gstabs                generate STABS debugging information\n"
 msgstr ""
 
-#: as.c:281
+#: as.c:278
 #, c-format
 msgid ""
 "  --gstabs+               generate STABS debug info with GNU extensions\n"
 msgstr ""
 
-#: as.c:283
+#: as.c:280
 #, c-format
 msgid "  --gdwarf-2              generate DWARF2 debugging information\n"
 msgstr ""
 
-#: as.c:285
+#: as.c:282
 #, c-format
 msgid "  --hash-size=<value>     set the hash table size close to <value>\n"
 msgstr ""
 
-#: as.c:287
+#: as.c:284
 #, c-format
 msgid "  --help                  show this message and exit\n"
 msgstr ""
 
-#: as.c:289
+#: as.c:286
 #, c-format
 msgid "  --target-help           show target specific options\n"
 msgstr ""
 
-#: as.c:291
+#: as.c:288
 #, c-format
 msgid ""
 "  -I DIR                  add DIR to search list for .include directives\n"
 msgstr ""
 
-#: as.c:293
+#: as.c:290
 #, c-format
 msgid "  -J                      don't warn about signed overflow\n"
 msgstr ""
 
-#: as.c:295
+#: as.c:292
 #, c-format
 msgid ""
 "  -K                      warn when differences altered for long "
 "displacements\n"
 msgstr ""
 
-#: as.c:297
+#: as.c:294
 #, c-format
 msgid "  -L,--keep-locals        keep local symbols (e.g. starting with `L')\n"
 msgstr ""
 
-#: as.c:299
+#: as.c:296
 #, c-format
 msgid "  -M,--mri                assemble in MRI compatibility mode\n"
 msgstr ""
 
-#: as.c:301
+#: as.c:298
 #, c-format
 msgid ""
 "  --MD FILE               write dependency information in FILE (default "
 "none)\n"
 msgstr ""
 
-#: as.c:303
+#: as.c:300
 #, c-format
 msgid "  -nocpp                  ignored\n"
 msgstr ""
 
-#: as.c:305
+#: as.c:302
 #, c-format
 msgid ""
 "  -o OBJFILE              name the object-file output OBJFILE (default a."
 "out)\n"
 msgstr ""
 
-#: as.c:307
+#: as.c:304
 #, c-format
 msgid "  -R                      fold data section into text section\n"
 msgstr ""
 
-#: as.c:309
+#: as.c:306
 #, c-format
 msgid ""
 "  --reduce-memory-overheads \n"
@@ -221,44 +221,44 @@ msgid ""
 "                          assembly times\n"
 msgstr ""
 
-#: as.c:313
+#: as.c:310
 #, c-format
 msgid ""
 "  --statistics            print various measured statistics from execution\n"
 msgstr ""
 
-#: as.c:315
+#: as.c:312
 #, c-format
 msgid "  --strip-local-absolute  strip local absolute symbols\n"
 msgstr ""
 
-#: as.c:317
+#: as.c:314
 #, c-format
 msgid ""
 "  --traditional-format    Use same format as native assembler when possible\n"
 msgstr ""
 
-#: as.c:319
+#: as.c:316
 #, c-format
 msgid "  --version               print assembler version number and exit\n"
 msgstr ""
 
-#: as.c:321
+#: as.c:318
 #, c-format
 msgid "  -W  --no-warn           suppress warnings\n"
 msgstr ""
 
-#: as.c:323
+#: as.c:320
 #, c-format
 msgid "  --warn                  don't suppress warnings\n"
 msgstr ""
 
-#: as.c:325
+#: as.c:322
 #, c-format
 msgid "  --fatal-warnings        treat warnings as errors\n"
 msgstr ""
 
-#: as.c:327
+#: as.c:324
 #, c-format
 msgid ""
 "  --itbl INSTTBL          extend instruction set to include instructions\n"
@@ -266,22 +266,22 @@ msgid ""
 "INSTTBL\n"
 msgstr ""
 
-#: as.c:330
+#: as.c:327
 #, c-format
 msgid "  -w                      ignored\n"
 msgstr ""
 
-#: as.c:332
+#: as.c:329
 #, c-format
 msgid "  -X                      ignored\n"
 msgstr ""
 
-#: as.c:334
+#: as.c:331
 #, c-format
 msgid "  -Z                      generate object file even after errors\n"
 msgstr ""
 
-#: as.c:336
+#: as.c:333
 #, c-format
 msgid ""
 "  --listing-lhs-width     set the width in words of the output data column "
@@ -289,7 +289,7 @@ msgid ""
 "                          the listing\n"
 msgstr ""
 
-#: as.c:339
+#: as.c:336
 #, c-format
 msgid ""
 "  --listing-lhs-width2    set the width in words of the continuation lines\n"
@@ -298,124 +298,129 @@ msgid ""
 "                          the width of the first line\n"
 msgstr ""
 
-#: as.c:343
+#: as.c:340
 #, c-format
 msgid ""
 "  --listing-rhs-width     set the max width in characters of the lines from\n"
 "                          the source file\n"
 msgstr ""
 
-#: as.c:346
+#: as.c:343
 #, c-format
 msgid ""
 "  --listing-cont-lines    set the maximum number of continuation lines used\n"
 "                          for the output data column of the listing\n"
 msgstr ""
 
-#: as.c:353
+#: as.c:346
+#, c-format
+msgid "  @FILE                   read options from FILE\n"
+msgstr ""
+
+#: as.c:354
 #, c-format
 msgid "Report bugs to %s\n"
 msgstr ""
 
-#: as.c:553
+#: as.c:554
 #, c-format
 msgid "unrecognized option -%c%s"
 msgstr ""
 
 #. This output is intended to follow the GNU standards document.
-#: as.c:591
+#: as.c:592
 #, c-format
 msgid "GNU assembler %s\n"
 msgstr ""
 
-#: as.c:592
+#: as.c:593
 #, c-format
-msgid "Copyright 2005 Free Software Foundation, Inc.\n"
+msgid "Copyright 2007 Free Software Foundation, Inc.\n"
 msgstr ""
 
-#: as.c:593
+#: as.c:594
 #, c-format
 msgid ""
 "This program is free software; you may redistribute it under the terms of\n"
 "the GNU General Public License.  This program has absolutely no warranty.\n"
 msgstr ""
 
-#: as.c:596
+#: as.c:597
 #, c-format
 msgid "This assembler was configured for a target of `%s'.\n"
 msgstr ""
 
-#: as.c:603
+#: as.c:604
 msgid "multiple emulation names specified"
 msgstr ""
 
-#: as.c:605
+#: as.c:606
 msgid "emulations not handled in this configuration"
 msgstr ""
 
-#: as.c:610
+#: as.c:611
 #, c-format
 msgid "alias = %s\n"
 msgstr ""
 
-#: as.c:611
+#: as.c:612
 #, c-format
 msgid "canonical = %s\n"
 msgstr ""
 
-#: as.c:612
+#: as.c:613
 #, c-format
 msgid "cpu-type = %s\n"
 msgstr ""
 
-#: as.c:614
+#: as.c:615
 #, c-format
 msgid "format = %s\n"
 msgstr ""
 
-#: as.c:617
+#: as.c:618
 #, c-format
 msgid "bfd-target = %s\n"
 msgstr ""
 
-#: as.c:630
+#: as.c:631
 msgid "bad defsym; format is --defsym name=value"
 msgstr ""
 
-#: as.c:650
+#: as.c:651
 msgid "no file name following -t option"
 msgstr ""
 
-#: as.c:665
+#: as.c:666
 #, c-format
 msgid "failed to read instruction table %s\n"
 msgstr ""
 
-#: as.c:832
+#: as.c:833
 #, c-format
 msgid "invalid listing option `%c'"
 msgstr ""
 
-#: as.c:885
+#: as.c:886
 msgid "--hash-size needs a numeric argument"
 msgstr ""
 
-#: as.c:910
+#: as.c:911
 #, c-format
 msgid "%s: total time in assembly: %ld.%06ld\n"
 msgstr ""
 
-#: as.c:913
+#: as.c:914
 #, c-format
 msgid "%s: data size %ld\n"
 msgstr ""
 
-#: as.c:1175
+#: as.c:1222
 #, c-format
 msgid "%d warnings, treating warnings as errors"
 msgstr ""
 
-#: as.h:200
+#: as.h:237
 #, c-format
 msgid "Case value %ld unexpected at line %d of file \"%s\"\n"
 msgstr ""
@@ -424,71 +429,71 @@ msgstr ""
 #. * We have a GROSS internal error.
 #. * This should never happen.
 #.
-#: atof-generic.c:419 config/tc-m68k.c:3118
+#: atof-generic.c:417 config/tc-m68k.c:3342
 msgid "failed sanity check"
 msgstr ""
 
-#: cond.c:82
+#: cond.c:83
 msgid "invalid identifier for \".ifdef\""
 msgstr ""
 
-#: cond.c:149
+#: cond.c:150
 msgid "non-constant expression in \".if\" statement"
 msgstr ""
 
-#: cond.c:276
+#: cond.c:277
 msgid "bad format for ifc or ifnc"
 msgstr ""
 
-#: cond.c:306
+#: cond.c:307
 msgid "\".elseif\" without matching \".if\""
 msgstr ""
 
-#: cond.c:310
+#: cond.c:311
 msgid "\".elseif\" after \".else\""
 msgstr ""
 
-#: cond.c:313 cond.c:419
+#: cond.c:314 cond.c:420
 msgid "here is the previous \"else\""
 msgstr ""
 
-#: cond.c:316 cond.c:422
+#: cond.c:317 cond.c:423
 msgid "here is the previous \"if\""
 msgstr ""
 
-#: cond.c:345
+#: cond.c:346
 msgid "non-constant expression in \".elseif\" statement"
 msgstr ""
 
-#: cond.c:383
+#: cond.c:384
 msgid "\".endif\" without \".if\""
 msgstr ""
 
-#: cond.c:412
+#: cond.c:413
 msgid "\".else\" without matching \".if\""
 msgstr ""
 
-#: cond.c:416
+#: cond.c:417
 msgid "duplicate \"else\""
 msgstr ""
 
-#: cond.c:467
+#: cond.c:468
 msgid ".ifeqs syntax error"
 msgstr ""
 
-#: cond.c:548
+#: cond.c:549
 msgid "end of macro inside conditional"
 msgstr ""
 
-#: cond.c:550
+#: cond.c:551
 msgid "end of file inside conditional"
 msgstr ""
 
-#: cond.c:553
+#: cond.c:554
 msgid "here is the start of the unterminated conditional"
 msgstr ""
 
-#: cond.c:557
+#: cond.c:558
 msgid "here is the \"else\" of the unterminated conditional"
 msgstr ""
 
@@ -502,7 +507,7 @@ msgstr ""
 msgid "Attempt to put an undefined symbol into set %s"
 msgstr ""
 
-#: config/obj-aout.c:116 config/obj-coff.c:1328
+#: config/obj-aout.c:116 config/obj-coff.c:1340
 #, c-format
 msgid "Symbol `%s' can not be both weak and common"
 msgstr ""
@@ -513,82 +518,82 @@ msgid "Inserting \"%s\" into structure table failed: %s"
 msgstr ""
 
 #. Zero is used as an end marker in the file.
-#: config/obj-coff.c:354
+#: config/obj-coff.c:366
 msgid "Line numbers must be positive integers\n"
 msgstr ""
 
-#: config/obj-coff.c:386
+#: config/obj-coff.c:398
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:428 ecoff.c:3240
+#: config/obj-coff.c:440 ecoff.c:3240
 msgid ".loc outside of .text"
 msgstr ""
 
-#: config/obj-coff.c:435
+#: config/obj-coff.c:447
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:516
+#: config/obj-coff.c:528
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:555
+#: config/obj-coff.c:567
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:594
+#: config/obj-coff.c:606
 #, c-format
 msgid "`%s' symbol without preceding function"
 msgstr ""
 
-#: config/obj-coff.c:681
+#: config/obj-coff.c:693
 #, c-format
 msgid "unexpected storage class %d"
 msgstr ""
 
-#: config/obj-coff.c:790
+#: config/obj-coff.c:802
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:810
+#: config/obj-coff.c:822
 msgid "badly formed .dim directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:859
+#: config/obj-coff.c:871
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:874
+#: config/obj-coff.c:886
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:891
+#: config/obj-coff.c:903
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:909
+#: config/obj-coff.c:921
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr ""
 
-#: config/obj-coff.c:922
+#: config/obj-coff.c:934
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:941
+#: config/obj-coff.c:953
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1108
+#: config/obj-coff.c:1120
 msgid "badly formed .weak directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:1286
+#: config/obj-coff.c:1298
 msgid "mismatched .eb"
 msgstr ""
 
-#: config/obj-coff.c:1307
+#: config/obj-coff.c:1319
 #, c-format
 msgid "C_EFCN symbol for %s out of scope"
 msgstr ""
@@ -596,28 +601,28 @@ msgstr ""
 #. STYP_INFO
 #. STYP_LIB
 #. STYP_OVER
-#: config/obj-coff.c:1533
+#: config/obj-coff.c:1591
 #, c-format
 msgid "unsupported section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1538 config/tc-ppc.c:4610
+#: config/obj-coff.c:1595 config/tc-ppc.c:4617
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1568 config/tc-ppc.c:4628 config/tc-tic54x.c:4287
-#: read.c:2551
+#: config/obj-coff.c:1623 config/tc-ppc.c:4635 config/tc-tic54x.c:4285
+#: read.c:2750
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr ""
 
-#: config/obj-coff.c:1579
+#: config/obj-coff.c:1634
 #, c-format
 msgid "Ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-coff.c:1710
+#: config/obj-coff.c:1765
 #, c-format
 msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
 msgstr ""
@@ -630,192 +635,173 @@ msgstr ""
 msgid "Can't set register masks"
 msgstr ""
 
-#: config/obj-elf.c:318 config/tc-sparc.c:3973 config/tc-v850.c:451
+#: config/obj-elf.c:322 config/tc-sparc.c:4053 config/tc-v850.c:450
 #, c-format
 msgid "bad .common segment %s"
 msgstr ""
 
-#: config/obj-elf.c:596
+#: config/obj-elf.c:600
 #, c-format
 msgid "setting incorrect section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:601
+#: config/obj-elf.c:605
 #, c-format
 msgid "ignoring incorrect section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:638
+#: config/obj-elf.c:647
 #, c-format
 msgid "setting incorrect section attributes for %s"
 msgstr ""
 
-#: config/obj-elf.c:690
+#: config/obj-elf.c:699
 #, c-format
 msgid "ignoring changed section type for %s"
 msgstr ""
 
-#: config/obj-elf.c:702
+#: config/obj-elf.c:711
 #, c-format
 msgid "ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-elf.c:704
+#: config/obj-elf.c:713
 #, c-format
 msgid "ignoring changed section entity size for %s"
 msgstr ""
 
-#: config/obj-elf.c:757
+#: config/obj-elf.c:766
 msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
 msgstr ""
 
-#: config/obj-elf.c:794
+#: config/obj-elf.c:803
 msgid "unrecognized section attribute"
 msgstr ""
 
-#: config/obj-elf.c:822 read.c:2535
+#: config/obj-elf.c:831 read.c:2734
 msgid "unrecognized section type"
 msgstr ""
 
-#: config/obj-elf.c:852
+#: config/obj-elf.c:861
 msgid "missing name"
 msgstr ""
 
-#: config/obj-elf.c:963
+#: config/obj-elf.c:972
 msgid "invalid merge entity size"
 msgstr ""
 
-#: config/obj-elf.c:970
+#: config/obj-elf.c:979
 msgid "entity size for SHF_MERGE not specified"
 msgstr ""
 
-#: config/obj-elf.c:990
+#: config/obj-elf.c:999
 msgid "group name for SHF_GROUP not specified"
 msgstr ""
 
-#: config/obj-elf.c:1003
+#: config/obj-elf.c:1012
 msgid "character following name is not '#'"
 msgstr ""
 
-#: config/obj-elf.c:1118
+#: config/obj-elf.c:1127
 msgid ".previous without corresponding .section; ignored"
 msgstr ""
 
-#: config/obj-elf.c:1144
+#: config/obj-elf.c:1153
 msgid ".popsection without corresponding .pushsection; ignored"
 msgstr ""
 
-#: config/obj-elf.c:1196
+#: config/obj-elf.c:1205
 msgid "expected comma after name in .symver"
 msgstr ""
 
-#: config/obj-elf.c:1220
+#: config/obj-elf.c:1229
 #, c-format
 msgid "missing version name in `%s' for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1231
+#: config/obj-elf.c:1240
 #, c-format
 msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1461
+#: config/obj-elf.c:1470
 msgid "expected quoted string"
 msgstr ""
 
-#: config/obj-elf.c:1481
+#: config/obj-elf.c:1490
 #, c-format
 msgid "expected comma after name `%s' in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:1490
+#: config/obj-elf.c:1499
 msgid "missing expression in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:1577
+#: config/obj-elf.c:1586
 #, c-format
 msgid "unrecognized symbol type \"%s\""
 msgstr ""
 
-#: config/obj-elf.c:1745
+#: config/obj-elf.c:1754
 msgid ".size expression too complicated to fix up"
 msgstr ""
 
-#: config/obj-elf.c:1777
+#: config/obj-elf.c:1786
 #, c-format
 msgid ""
 "invalid attempt to declare external version name as default in symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:1838 ecoff.c:3598
+#: config/obj-elf.c:1847 ecoff.c:3598
 #, c-format
 msgid "symbol `%s' can not be both weak and common"
 msgstr ""
 
-#: config/obj-elf.c:1945
+#: config/obj-elf.c:1954
 #, c-format
 msgid "assuming all members of group `%s' are COMDAT"
 msgstr ""
 
-#: config/obj-elf.c:1967
+#: config/obj-elf.c:1976
 #, c-format
 msgid "can't create group: %s"
 msgstr ""
 
-#: config/obj-elf.c:2076
+#: config/obj-elf.c:2086
 #, c-format
 msgid "failed to set up debugging information: %s"
 msgstr ""
 
-#: config/obj-elf.c:2096
+#: config/obj-elf.c:2106
 #, c-format
 msgid "can't start writing .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.c:2104
+#: config/obj-elf.c:2114
 #, c-format
 msgid "could not write .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.h:140
-#, c-format
-msgid "can't allocate ELF private section data: %s"
-msgstr ""
-
-#: config/obj-ieee.c:69
-#, c-format
-msgid "Out of step\n"
-msgstr ""
-
-#: config/obj-ieee.c:449
-msgid "too many sections"
-msgstr ""
-
-#: config/obj-ieee.c:511
-#, c-format
-msgid "FATAL: Can't create %s"
-msgstr ""
-
 #: config/obj-som.c:129
 msgid "Only one .version pseudo-op per file!"
 msgstr ""
 
-#: config/obj-som.c:146 config/obj-som.c:191
+#: config/obj-som.c:146 config/obj-som.c:188
 msgid "Expected quoted string"
 msgstr ""
 
-#: config/obj-som.c:155
+#: config/obj-som.c:153
 #, c-format
-msgid "FATAL: Attaching version header %s"
+msgid "attaching version header %s: %s"
 msgstr ""
 
-#: config/obj-som.c:174
+#: config/obj-som.c:171
 msgid "Only one .copyright pseudo-op per file!"
 msgstr ""
 
-#: config/obj-som.c:200
+#: config/obj-som.c:195
 #, c-format
-msgid "FATAL: Attaching copyright header %s"
+msgid "attaching copyright header %s: %s"
 msgstr ""
 
 #: config/tc-alpha.c:592
@@ -887,8 +873,8 @@ msgstr ""
 msgid "opcode `%s' not supported for target %s"
 msgstr ""
 
-#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1221
-#: config/tc-msp430.c:1870
+#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1321
+#: config/tc-msp430.c:1868
 #, c-format
 msgid "unknown opcode `%s'"
 msgstr ""
@@ -968,17 +954,17 @@ msgstr ""
 msgid "sequence number in use for !tlsgd!%ld"
 msgstr ""
 
-#: config/tc-alpha.c:1823 config/tc-arc.c:294 config/tc-mn10200.c:889
-#: config/tc-mn10300.c:2600 config/tc-ppc.c:1476 config/tc-s390.c:614
-#: config/tc-v850.c:1573
+#: config/tc-alpha.c:1823 config/tc-arc.c:292 config/tc-mn10200.c:888
+#: config/tc-mn10300.c:2604 config/tc-ppc.c:1541 config/tc-s390.c:615
+#: config/tc-v850.c:1588
 msgid "operand"
 msgstr ""
 
-#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:585
-#: config/tc-d30v.c:573 config/tc-mn10200.c:1133 config/tc-mn10300.c:1893
-#: config/tc-ppc.c:2348 config/tc-ppc.c:2565 config/tc-ppc.c:2577
-#: config/tc-s390.c:1230 config/tc-s390.c:1330 config/tc-s390.c:1459
-#: config/tc-v850.c:1747 config/tc-v850.c:1770 config/tc-v850.c:1973
+#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:584
+#: config/tc-d30v.c:572 config/tc-mn10200.c:1132 config/tc-mn10300.c:1892
+#: config/tc-ppc.c:2402 config/tc-ppc.c:2619 config/tc-ppc.c:2631
+#: config/tc-s390.c:1231 config/tc-s390.c:1331 config/tc-s390.c:1460
+#: config/tc-v850.c:1762 config/tc-v850.c:1785 config/tc-v850.c:1988
 msgid "too many fixups"
 msgstr ""
 
@@ -994,17 +980,17 @@ msgstr ""
 msgid "can not resolve expression"
 msgstr ""
 
-#: config/tc-alpha.c:3275 config/tc-ppc.c:1781 config/tc-ppc.c:4373
+#: config/tc-alpha.c:3275 config/tc-ppc.c:1840 config/tc-ppc.c:4380
 #, c-format
 msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-alpha.c:3304 config/tc-sparc.c:3843 config/tc-v850.c:246
+#: config/tc-alpha.c:3304 config/tc-sparc.c:3923 config/tc-v850.c:245
 msgid "Ignoring attempt to re-define symbol"
 msgstr ""
 
-#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4410
-#: config/tc-sparc.c:3851
+#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4417
+#: config/tc-sparc.c:3931
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
@@ -1033,7 +1019,7 @@ msgstr ""
 msgid ".fmask outside of .ent"
 msgstr ""
 
-#: config/tc-alpha.c:3547 ecoff.c:3204
+#: config/tc-alpha.c:3547 config/tc-score.c:5886 ecoff.c:3204
 msgid ".mask outside of .ent"
 msgstr ""
 
@@ -1045,7 +1031,8 @@ msgstr ""
 msgid "bad .mask directive"
 msgstr ""
 
-#: config/tc-alpha.c:3590 config/tc-mips.c:14022 ecoff.c:3168
+#: config/tc-alpha.c:3590 config/tc-mips.c:14589 config/tc-score.c:6029
+#: ecoff.c:3168
 msgid ".frame outside of .ent"
 msgstr ""
 
@@ -1134,7 +1121,7 @@ msgstr ""
 msgid "No symbol after .code_address"
 msgstr ""
 
-#: config/tc-alpha.c:4226
+#: config/tc-alpha.c:4226 config/tc-score.c:5892
 msgid "Bad .mask directive"
 msgstr ""
 
@@ -1168,7 +1155,7 @@ msgstr ""
 msgid "Alignment too large: %d. assumed"
 msgstr ""
 
-#: config/tc-alpha.c:4497 config/tc-d30v.c:2083
+#: config/tc-alpha.c:4497 config/tc-d30v.c:2082
 msgid "Alignment negative: 0 assumed"
 msgstr ""
 
@@ -1191,15 +1178,16 @@ msgstr ""
 msgid "internal error: can't hash macro `%s': %s"
 msgstr ""
 
-#: config/tc-alpha.c:4998 config/tc-i960.c:710 config/tc-xtensa.c:5112
-#: config/tc-xtensa.c:5181 config/tc-xtensa.c:5227
+#: config/tc-alpha.c:4998 config/tc-arm.c:6012 config/tc-arm.c:6024
+#: config/tc-i960.c:708 config/tc-xtensa.c:5161 config/tc-xtensa.c:5239
+#: config/tc-xtensa.c:5285 config/tc-z80.c:1893
 msgid "syntax error"
 msgstr ""
 
-#: config/tc-alpha.c:5067 config/tc-h8300.c:2055 config/tc-hppa.c:4041
-#: config/tc-i860.c:1059 config/tc-m68hc11.c:558 config/tc-m68k.c:4524
-#: config/tc-ns32k.c:1945 config/tc-or32.c:579 config/tc-sparc.c:2944
-#: config/tc-z8k.c:1310
+#: config/tc-alpha.c:5067 config/tc-h8300.c:2053 config/tc-hppa.c:1381
+#: config/tc-i860.c:1057 config/tc-m68hc11.c:560 config/tc-m68k.c:4654
+#: config/tc-ns32k.c:1943 config/tc-or32.c:580 config/tc-sparc.c:2998
+#: config/tc-spu.c:748 config/tc-z8k.c:1332
 msgid "Bad call to MD_ATOF()"
 msgstr ""
 
@@ -1241,7 +1229,7 @@ msgstr ""
 msgid "type %d reloc done?\n"
 msgstr ""
 
-#: config/tc-alpha.c:5420 config/tc-alpha.c:5427 config/tc-mips.c:8657
+#: config/tc-alpha.c:5420 config/tc-alpha.c:5427
 msgid "Used $at without \".set noat\""
 msgstr ""
 
@@ -1250,12 +1238,12 @@ msgstr ""
 msgid "!samegp reloc against symbol without .prologue: %s"
 msgstr ""
 
-#: config/tc-alpha.c:5626 config/tc-xtensa.c:5739
+#: config/tc-alpha.c:5626 config/tc-xtensa.c:5795
 #, c-format
 msgid "cannot represent `%s' relocation in object file"
 msgstr ""
 
-#: config/tc-alpha.c:5632 config/tc-xtensa.c:5747
+#: config/tc-alpha.c:5632 config/tc-xtensa.c:5803
 #, c-format
 msgid "internal error? cannot generate `%s' relocation"
 msgstr ""
@@ -1265,555 +1253,722 @@ msgstr ""
 msgid "frame reg expected, using $%d."
 msgstr ""
 
-#: config/tc-arc.c:1077 config/tc-ip2k.c:249
+#: config/tc-arc.c:1076 config/tc-ip2k.c:248
 msgid "md_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-arc.c:1088
+#: config/tc-arc.c:1087
 msgid "md_convert_frag\n"
 msgstr ""
 
 #. We can't actually support subtracting a symbol.
-#: config/tc-arc.c:1288 config/tc-arm.c:1021 config/tc-arm.c:5764
-#: config/tc-arm.c:5815 config/tc-arm.c:6614 config/tc-arm.c:7256
-#: config/tc-arm.c:7284 config/tc-arm.c:7536 config/tc-arm.c:7553
-#: config/tc-arm.c:7674 config/tc-avr.c:970 config/tc-cris.c:3928
-#: config/tc-d10v.c:1539 config/tc-d30v.c:1938 config/tc-mips.c:3794
-#: config/tc-mips.c:4902 config/tc-mips.c:5834 config/tc-mips.c:6428
-#: config/tc-msp430.c:1979 config/tc-ppc.c:5562 config/tc-v850.c:2274
-#: config/tc-xstormy16.c:484
+#: config/tc-arc.c:1287 config/tc-arm.c:1522 config/tc-arm.c:8104
+#: config/tc-arm.c:8155 config/tc-arm.c:8388 config/tc-arm.c:9111
+#: config/tc-arm.c:9915 config/tc-arm.c:9943 config/tc-arm.c:10200
+#: config/tc-arm.c:10217 config/tc-arm.c:10339 config/tc-avr.c:1052
+#: config/tc-cris.c:3984 config/tc-d10v.c:1536 config/tc-d30v.c:1937
+#: config/tc-mips.c:4176 config/tc-mips.c:5300 config/tc-mips.c:6239
+#: config/tc-mips.c:6831 config/tc-msp430.c:1976 config/tc-ppc.c:5585
+#: config/tc-spu.c:961 config/tc-spu.c:985 config/tc-v850.c:2303
+#: config/tc-xstormy16.c:484 config/tc-xtensa.c:5597 config/tc-xtensa.c:11559
 msgid "expression too complex"
 msgstr ""
 
-#: config/tc-arm.c:352
+#: config/tc-arm.c:483
 msgid "ARM register expected"
 msgstr ""
 
-#: config/tc-arm.c:353
+#: config/tc-arm.c:484
 msgid "bad or missing co-processor number"
 msgstr ""
 
-#: config/tc-arm.c:354
+#: config/tc-arm.c:485
 msgid "co-processor register expected"
 msgstr ""
 
-#: config/tc-arm.c:355
+#: config/tc-arm.c:486
 msgid "FPA register expected"
 msgstr ""
 
-#: config/tc-arm.c:356
+#: config/tc-arm.c:487
 msgid "VFP single precision register expected"
 msgstr ""
 
-#: config/tc-arm.c:357
-msgid "VFP double precision register expected"
+#: config/tc-arm.c:488
+msgid "VFP/Neon double precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:489
+msgid "Neon quad precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:490
+msgid "VFP single or double precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:491
+msgid "Neon double or quad precision register expected"
 msgstr ""
 
-#: config/tc-arm.c:358
+#: config/tc-arm.c:492
+msgid "VFP single, double or Neon quad precision register expected"
+msgstr ""
+
+#: config/tc-arm.c:493
 msgid "VFP system register expected"
 msgstr ""
 
-#: config/tc-arm.c:359
+#: config/tc-arm.c:494
 msgid "Maverick MVF register expected"
 msgstr ""
 
-#: config/tc-arm.c:360
+#: config/tc-arm.c:495
 msgid "Maverick MVD register expected"
 msgstr ""
 
-#: config/tc-arm.c:361
+#: config/tc-arm.c:496
 msgid "Maverick MVFX register expected"
 msgstr ""
 
-#: config/tc-arm.c:362
+#: config/tc-arm.c:497
 msgid "Maverick MVDX register expected"
 msgstr ""
 
-#: config/tc-arm.c:363
+#: config/tc-arm.c:498
 msgid "Maverick MVAX register expected"
 msgstr ""
 
-#: config/tc-arm.c:364
+#: config/tc-arm.c:499
 msgid "Maverick DSPSC register expected"
 msgstr ""
 
-#: config/tc-arm.c:365
+#: config/tc-arm.c:500
 msgid "iWMMXt data register expected"
 msgstr ""
 
-#: config/tc-arm.c:366
+#: config/tc-arm.c:501 config/tc-arm.c:5821
 msgid "iWMMXt control register expected"
 msgstr ""
 
-#: config/tc-arm.c:367
+#: config/tc-arm.c:502
 msgid "iWMMXt scalar register expected"
 msgstr ""
 
-#: config/tc-arm.c:368
+#: config/tc-arm.c:503
 msgid "XScale accumulator register expected"
 msgstr ""
 
-#: config/tc-arm.c:499
+#. For score5u : div/mul will pop warning message, mmu/alw/asw will pop error message.
+#: config/tc-arm.c:652 config/tc-score.c:47
 msgid "bad arguments to instruction"
 msgstr ""
 
-#: config/tc-arm.c:500
+#: config/tc-arm.c:653 config/tc-score.c:48
 msgid "r15 not allowed here"
 msgstr ""
 
-#: config/tc-arm.c:501
+#: config/tc-arm.c:654
 msgid "instruction cannot be conditional"
 msgstr ""
 
-#: config/tc-arm.c:502
+#: config/tc-arm.c:655
 msgid "registers may not be the same"
 msgstr ""
 
-#: config/tc-arm.c:503
+#: config/tc-arm.c:656
 msgid "lo register required"
 msgstr ""
 
-#: config/tc-arm.c:504
+#: config/tc-arm.c:657
 msgid "instruction not supported in Thumb16 mode"
 msgstr ""
 
-#: config/tc-arm.c:640
+#: config/tc-arm.c:658
+msgid "instruction does not accept this addressing mode"
+msgstr ""
+
+#: config/tc-arm.c:659
+msgid "branch must be last instruction in IT block"
+msgstr ""
+
+#: config/tc-arm.c:660
+msgid "instruction not allowed in IT block"
+msgstr ""
+
+#: config/tc-arm.c:661
+msgid "selected FPU does not support instruction"
+msgstr ""
+
+#: config/tc-arm.c:803
 msgid "immediate expression requires a # prefix"
 msgstr ""
 
-#: config/tc-arm.c:666 expr.c:1302 read.c:2228
+#: config/tc-arm.c:830 config/tc-score.c:5675 expr.c:1298 read.c:2435
 msgid "bad expression"
 msgstr ""
 
-#: config/tc-arm.c:677 config/tc-i860.c:1005 config/tc-sparc.c:2844
+#: config/tc-arm.c:841 config/tc-i860.c:1003 config/tc-sparc.c:2898
 msgid "bad segment"
 msgstr ""
 
-#: config/tc-arm.c:693 config/tc-arm.c:3230 config/tc-i960.c:1302
+#: config/tc-arm.c:858 config/tc-arm.c:4346 config/tc-i960.c:1300
+#: config/tc-score.c:985
 msgid "invalid constant"
 msgstr ""
 
-#: config/tc-arm.c:754
+#: config/tc-arm.c:919 config/tc-score.c:4749
 msgid "bad call to MD_ATOF()"
 msgstr ""
 
-#: config/tc-arm.c:821
+#: config/tc-arm.c:986
 msgid "expected #constant"
 msgstr ""
 
-#: config/tc-arm.c:953
+#: config/tc-arm.c:1147
+#, c-format
+msgid "unexpected character `%c' in type specifier"
+msgstr ""
+
+#: config/tc-arm.c:1164
+#, c-format
+msgid "bad size %d in type specifier"
+msgstr ""
+
+#: config/tc-arm.c:1214
+msgid "only one type should be specified for operand"
+msgstr ""
+
+#: config/tc-arm.c:1220
+msgid "vector type expected"
+msgstr ""
+
+#: config/tc-arm.c:1292
+msgid "can't redefine type for operand"
+msgstr ""
+
+#: config/tc-arm.c:1303
+msgid "only D registers may be indexed"
+msgstr ""
+
+#: config/tc-arm.c:1309
+msgid "can't change index for operand"
+msgstr ""
+
+#: config/tc-arm.c:1325 config/tc-arm.c:3947
+msgid "constant expression required"
+msgstr ""
+
+#: config/tc-arm.c:1369
+msgid "register operand expected, but got scalar"
+msgstr ""
+
+#: config/tc-arm.c:1402
+msgid "scalar must have an index"
+msgstr ""
+
+#: config/tc-arm.c:1407 config/tc-arm.c:13097 config/tc-arm.c:13145
+#: config/tc-arm.c:13547
+msgid "scalar index out of range"
+msgstr ""
+
+#: config/tc-arm.c:1454
 msgid "bad range in register list"
 msgstr ""
 
-#: config/tc-arm.c:961 config/tc-arm.c:970 config/tc-arm.c:1011
+#: config/tc-arm.c:1462 config/tc-arm.c:1471 config/tc-arm.c:1512
 #, c-format
 msgid "Warning: duplicated register (r%d) in register list"
 msgstr ""
 
-#: config/tc-arm.c:973
+#: config/tc-arm.c:1474
 msgid "Warning: register range not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:984
+#: config/tc-arm.c:1485
 msgid "missing `}'"
 msgstr ""
 
-#: config/tc-arm.c:1000
+#: config/tc-arm.c:1501
 msgid "invalid register mask"
 msgstr ""
 
-#: config/tc-arm.c:1091 config/tc-arm.c:1126 config/tc-h8300.c:991
-#: config/tc-mips.c:9797 config/tc-mips.c:9827
+#: config/tc-arm.c:1583
+msgid "expecting {"
+msgstr ""
+
+#: config/tc-arm.c:1638 config/tc-arm.c:1682
+msgid "register out of range in list"
+msgstr ""
+
+#: config/tc-arm.c:1654 config/tc-arm.c:1699 config/tc-h8300.c:989
+#: config/tc-mips.c:10168 config/tc-mips.c:10190
 msgid "invalid register list"
 msgstr ""
 
-#: config/tc-arm.c:1097 config/tc-arm.c:2402 config/tc-arm.c:2535
+#: config/tc-arm.c:1660 config/tc-arm.c:3412 config/tc-arm.c:3545
 msgid "register list not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:1118
+#: config/tc-arm.c:1691
 msgid "register range not in ascending order"
 msgstr ""
 
-#: config/tc-arm.c:1151
+#: config/tc-arm.c:1724
 msgid "non-contiguous register range"
 msgstr ""
 
-#: config/tc-arm.c:1199
+#: config/tc-arm.c:1850
+msgid "don't use Rn-Rm syntax with non-unit stride"
+msgstr ""
+
+#: config/tc-arm.c:1905
+msgid "error parsing element/structure list"
+msgstr ""
+
+#: config/tc-arm.c:1911
+msgid "expected }"
+msgstr ""
+
+#: config/tc-arm.c:1967
 #, c-format
 msgid "ignoring attempt to redefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1204
+#: config/tc-arm.c:1972
 #, c-format
 msgid "ignoring redefinition of register alias '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1248
+#: config/tc-arm.c:2000
+msgid "attempt to redefine typed alias"
+msgstr ""
+
+#: config/tc-arm.c:2038
 #, c-format
 msgid "unknown register '%s' -- .req ignored"
 msgstr ""
 
-#: config/tc-arm.c:1291
+#: config/tc-arm.c:2121
+msgid "bad type for register"
+msgstr ""
+
+#: config/tc-arm.c:2132
+msgid "expression must be constant"
+msgstr ""
+
+#: config/tc-arm.c:2149
+msgid "can't redefine the type of a register alias"
+msgstr ""
+
+#: config/tc-arm.c:2156
+msgid "you must specify a single type only"
+msgstr ""
+
+#: config/tc-arm.c:2169
+msgid "can't redefine the index of a scalar alias"
+msgstr ""
+
+#: config/tc-arm.c:2177
+msgid "scalar index must be constant"
+msgstr ""
+
+#: config/tc-arm.c:2186
+msgid "expecting ]"
+msgstr ""
+
+#: config/tc-arm.c:2223
 msgid "invalid syntax for .req directive"
 msgstr ""
 
-#: config/tc-arm.c:1317
+#: config/tc-arm.c:2229
+msgid "invalid syntax for .dn directive"
+msgstr ""
+
+#: config/tc-arm.c:2235
+msgid "invalid syntax for .qn directive"
+msgstr ""
+
+#: config/tc-arm.c:2261
 msgid "invalid syntax for .unreq directive"
 msgstr ""
 
-#: config/tc-arm.c:1323
+#: config/tc-arm.c:2267
 #, c-format
 msgid "unknown register alias '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1325
+#: config/tc-arm.c:2269
 #, c-format
 msgid "ignoring attempt to undefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-arm.c:1456
+#: config/tc-arm.c:2402
 msgid "selected processor does not support THUMB opcodes"
 msgstr ""
 
-#: config/tc-arm.c:1470
+#: config/tc-arm.c:2416
 msgid "selected processor does not support ARM opcodes"
 msgstr ""
 
-#: config/tc-arm.c:1483
+#: config/tc-arm.c:2429
 #, c-format
 msgid "invalid instruction size selected (%d)"
 msgstr ""
 
-#: config/tc-arm.c:1515
+#: config/tc-arm.c:2461
 #, c-format
 msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
 msgstr ""
 
-#: config/tc-arm.c:1571
+#: config/tc-arm.c:2517
 #, c-format
 msgid "expected comma after name \"%s\""
 msgstr ""
 
-#: config/tc-arm.c:1621 config/tc-m32r.c:589
+#: config/tc-arm.c:2567 config/tc-m32r.c:588
 #, c-format
 msgid "symbol `%s' already defined"
 msgstr ""
 
-#: config/tc-arm.c:1655
+#: config/tc-arm.c:2601
 #, c-format
 msgid "unrecognized syntax mode \"%s\""
 msgstr ""
 
-#: config/tc-arm.c:1675
+#: config/tc-arm.c:2622
 #, c-format
 msgid "alignment too large: %d assumed"
 msgstr ""
 
-#: config/tc-arm.c:1678
+#: config/tc-arm.c:2625
 msgid "alignment negative. 0 assumed."
 msgstr ""
 
-#: config/tc-arm.c:1816
+#: config/tc-arm.c:2772
 msgid "literal pool overflow"
 msgstr ""
 
-#: config/tc-arm.c:1972 config/tc-arm.c:3888
+#: config/tc-arm.c:2928 config/tc-arm.c:5756
 msgid "unrecognized relocation suffix"
 msgstr ""
 
-#: config/tc-arm.c:1985
+#: config/tc-arm.c:2941
 msgid "(plt) is only valid on branch targets"
 msgstr ""
 
-#: config/tc-arm.c:1991 config/tc-s390.c:1128 config/tc-s390.c:1742
-#: config/tc-xtensa.c:1601
+#: config/tc-arm.c:2947 config/tc-s390.c:1129 config/tc-s390.c:1743
+#: config/tc-xtensa.c:1545
 #, c-format
 msgid "%s relocations do not fit in %d bytes"
 msgstr ""
 
-#: config/tc-arm.c:2039 dwarf2dbg.c:659
+#: config/tc-arm.c:2995 dwarf2dbg.c:689
 msgid "expected 0 or 1"
 msgstr ""
 
-#: config/tc-arm.c:2043
+#: config/tc-arm.c:2999
 msgid "missing comma"
 msgstr ""
 
-#: config/tc-arm.c:2098
+#: config/tc-arm.c:3054
 msgid "dupicate .handlerdata directive"
 msgstr ""
 
-#: config/tc-arm.c:2169
+#: config/tc-arm.c:3125
 msgid "personality routine specified for cantunwind frame"
 msgstr ""
 
-#: config/tc-arm.c:2183
+#: config/tc-arm.c:3139
 msgid "duplicate .personalityindex directive"
 msgstr ""
 
-#: config/tc-arm.c:2190
+#: config/tc-arm.c:3146
 msgid "bad personality routine number"
 msgstr ""
 
-#: config/tc-arm.c:2209
+#: config/tc-arm.c:3165
 msgid "duplicate .personality directive"
 msgstr ""
 
-#: config/tc-arm.c:2232 config/tc-arm.c:2354
+#: config/tc-arm.c:3188 config/tc-arm.c:3316 config/tc-arm.c:3364
 msgid "expected register list"
 msgstr ""
 
-#: config/tc-arm.c:2310
+#: config/tc-arm.c:3270
 msgid "expected , <constant>"
 msgstr ""
 
-#: config/tc-arm.c:2319
+#: config/tc-arm.c:3279
 msgid "number of registers must be in the range [1:4]"
 msgstr ""
 
-#: config/tc-arm.c:2416 config/tc-arm.c:2549
+#: config/tc-arm.c:3426 config/tc-arm.c:3559
 msgid "bad register range"
 msgstr ""
 
-#: config/tc-arm.c:2602
+#: config/tc-arm.c:3613
 msgid "register expected"
 msgstr ""
 
-#: config/tc-arm.c:2612
+#: config/tc-arm.c:3623
 msgid "FPA .unwind_save does not take a register list"
 msgstr ""
 
-#: config/tc-arm.c:2625
+#: config/tc-arm.c:3641
 msgid ".unwind_save does not support this kind of register"
 msgstr ""
 
-#: config/tc-arm.c:2650
+#: config/tc-arm.c:3677
 msgid "SP and PC not permitted in .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2655
+#: config/tc-arm.c:3682
 msgid "unexpected .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2679
+#: config/tc-arm.c:3706
 msgid "stack increment must be multiple of 4"
 msgstr ""
 
-#: config/tc-arm.c:2708
+#: config/tc-arm.c:3735
 msgid "expected <reg>, <reg>"
 msgstr ""
 
-#: config/tc-arm.c:2726
+#: config/tc-arm.c:3753
 msgid "register must be either sp or set by a previousunwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:2762
+#: config/tc-arm.c:3789
 msgid "expected <offset>, <opcode>"
 msgstr ""
 
-#: config/tc-arm.c:2774
+#: config/tc-arm.c:3801
 msgid "unwind opcode too long"
 msgstr ""
 
-#: config/tc-arm.c:2779
+#: config/tc-arm.c:3806
 msgid "invalid unwind opcode"
 msgstr ""
 
-#: config/tc-arm.c:2829
-msgid "expected numeric constant"
-msgstr ""
-
-#: config/tc-arm.c:2838
-msgid "expected comma"
-msgstr ""
-
-#: config/tc-arm.c:2877
-msgid "bad string constant"
-msgstr ""
-
-#: config/tc-arm.c:2881
-msgid "expected <tag> , <value>"
-msgstr ""
-
-#: config/tc-arm.c:2957
-msgid "constant expression required"
-msgstr ""
-
-#: config/tc-arm.c:2963 config/tc-arm.c:6472 config/tc-arm.c:11799
-#: config/tc-arm.c:11824 config/tc-arm.c:11832 config/tc-z8k.c:1122
-#: config/tc-z8k.c:1132
+#: config/tc-arm.c:3953 config/tc-arm.c:4816 config/tc-arm.c:8391
+#: config/tc-arm.c:8873 config/tc-arm.c:11671 config/tc-arm.c:18619
+#: config/tc-arm.c:18644 config/tc-arm.c:18652 config/tc-z8k.c:1144
+#: config/tc-z8k.c:1154
 msgid "immediate value out of range"
 msgstr ""
 
-#: config/tc-arm.c:3058
+#: config/tc-arm.c:4100
 msgid "invalid FPA immediate expression"
 msgstr ""
 
-#: config/tc-arm.c:3108 config/tc-arm.c:3116
+#: config/tc-arm.c:4224 config/tc-arm.c:4232
 msgid "shift expression expected"
 msgstr ""
 
-#: config/tc-arm.c:3130
+#: config/tc-arm.c:4246
 msgid "'LSL' or 'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:3138
+#: config/tc-arm.c:4254
 msgid "'LSL' required"
 msgstr ""
 
-#: config/tc-arm.c:3146
+#: config/tc-arm.c:4262
 msgid "'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:3218 config/tc-arm.c:4349 config/tc-v850.c:1844
-#: config/tc-v850.c:1865
+#: config/tc-arm.c:4334 config/tc-arm.c:4810 config/tc-arm.c:6382
+#: config/tc-v850.c:1859 config/tc-v850.c:1880
 msgid "constant expression expected"
 msgstr ""
 
-#: config/tc-arm.c:3225
+#: config/tc-arm.c:4341
 msgid "invalid rotation"
 msgstr ""
 
-#: config/tc-arm.c:3340 config/tc-arm.c:3640
+#: config/tc-arm.c:4501 config/tc-arm.c:4646
+msgid "unknown group relocation"
+msgstr ""
+
+#: config/tc-arm.c:4614
+msgid "alignment must be constant"
+msgstr ""
+
+#: config/tc-arm.c:4677
+msgid "this group relocation is not allowed on this instruction"
+msgstr ""
+
+#: config/tc-arm.c:4689 config/tc-arm.c:5080
 msgid "']' expected"
 msgstr ""
 
-#: config/tc-arm.c:3358
+#: config/tc-arm.c:4707
 msgid "'}' expected at end of 'option' field"
 msgstr ""
 
-#: config/tc-arm.c:3363
+#: config/tc-arm.c:4712
 msgid "cannot combine index with option"
 msgstr ""
 
-#: config/tc-arm.c:3376
+#: config/tc-arm.c:4725
 msgid "cannot combine pre- and post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:3472
+#: config/tc-arm.c:4886
 msgid "flag for {c}psr instruction expected"
 msgstr ""
 
-#: config/tc-arm.c:3497
+#: config/tc-arm.c:4911
 msgid "unrecognized CPS flag"
 msgstr ""
 
-#: config/tc-arm.c:3504
+#: config/tc-arm.c:4918
 msgid "missing CPS flags"
 msgstr ""
 
-#: config/tc-arm.c:3527 config/tc-arm.c:3533
+#: config/tc-arm.c:4941 config/tc-arm.c:4947
 msgid "valid endian specifiers are be or le"
 msgstr ""
 
-#: config/tc-arm.c:3555
+#: config/tc-arm.c:4969
 msgid "missing rotation field after comma"
 msgstr ""
 
-#: config/tc-arm.c:3570
+#: config/tc-arm.c:4984
 msgid "rotation can only be 0, 8, 16, or 24"
 msgstr ""
 
-#: config/tc-arm.c:3590
+#: config/tc-arm.c:5004
 msgid "condition required"
 msgstr ""
 
-#: config/tc-arm.c:3632
+#: config/tc-arm.c:5042 config/tc-arm.c:6877
+msgid "'[' expected"
+msgstr ""
+
+#: config/tc-arm.c:5055
+msgid "',' expected"
+msgstr ""
+
+#: config/tc-arm.c:5072
 msgid "invalid shift"
 msgstr ""
 
-#: config/tc-arm.c:3929
+#: config/tc-arm.c:5145
+msgid "can't use Neon quad register here"
+msgstr ""
+
+#: config/tc-arm.c:5211
+msgid "expected <Rm> or <Dm> or <Qm> operand"
+msgstr ""
+
+#: config/tc-arm.c:5291
+msgid "parse error"
+msgstr ""
+
+#: config/tc-arm.c:5301 read.c:2092
+msgid "expected comma"
+msgstr ""
+
+#: config/tc-arm.c:5591 config/tc-arm.c:5661
+msgid "immediate value is out of range"
+msgstr ""
+
+#: config/tc-arm.c:5806
 msgid "iWMMXt data or control register expected"
 msgstr ""
 
-#: config/tc-arm.c:4051
+#: config/tc-arm.c:6038 config/tc-score.c:56
 msgid "garbage following instruction"
 msgstr ""
 
-#: config/tc-arm.c:4185
+#: config/tc-arm.c:6125
+msgid "D register out of range for selected VFP version"
+msgstr ""
+
+#: config/tc-arm.c:6204
 msgid "instruction does not accept preindexed addressing"
 msgstr ""
 
 #. unindexed - only for coprocessor
-#: config/tc-arm.c:4201 config/tc-arm.c:5857
+#: config/tc-arm.c:6220 config/tc-arm.c:8197
 msgid "instruction does not accept unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:4209
+#: config/tc-arm.c:6228
 msgid "destination register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:4210
+#: config/tc-arm.c:6229
 msgid "source register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:4256
+#: config/tc-arm.c:6275
 msgid "instruction does not accept scaled register index"
 msgstr ""
 
-#: config/tc-arm.c:4295
+#: config/tc-arm.c:6315
 msgid "instruction does not support unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:4310
+#: config/tc-arm.c:6330
 msgid "pc may not be used with write-back"
 msgstr ""
 
-#: config/tc-arm.c:4315
+#: config/tc-arm.c:6335
 msgid "instruction does not support writeback"
 msgstr ""
 
-#: config/tc-arm.c:4344
+#: config/tc-arm.c:6377
 msgid "invalid pseudo operation"
 msgstr ""
 
-#: config/tc-arm.c:4390
+#: config/tc-arm.c:6423
 msgid "literal pool insertion failed"
 msgstr ""
 
-#: config/tc-arm.c:4448
+#: config/tc-arm.c:6481
 msgid "Rn must not overlap other operands"
 msgstr ""
 
-#: config/tc-arm.c:4534 config/tc-arm.c:4553 config/tc-arm.c:4566
-#: config/tc-arm.c:6360 config/tc-arm.c:6380 config/tc-arm.c:6394
+#: config/tc-arm.c:6581 config/tc-arm.c:6600 config/tc-arm.c:6613
+#: config/tc-arm.c:8740 config/tc-arm.c:8760 config/tc-arm.c:8774
 msgid "bit-field extends past end of register"
 msgstr ""
 
-#: config/tc-arm.c:4595
+#: config/tc-arm.c:6642
 msgid "the only suffix valid here is '(plt)'"
 msgstr ""
 
-#: config/tc-arm.c:4627
+#: config/tc-arm.c:6695
 msgid "use of r15 in blx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4645
+#: config/tc-arm.c:6718
 msgid "use of r15 in bx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4657 config/tc-arm.c:6508
+#: config/tc-arm.c:6730 config/tc-arm.c:8912
 msgid "use of r15 in bxj is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:4761 config/tc-arm.c:4770
+#: config/tc-arm.c:6844 config/tc-arm.c:6853
 msgid "writeback of base register is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4764
+#: config/tc-arm.c:6847
 msgid "writeback of base register when in register list is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4774
+#: config/tc-arm.c:6857
 msgid "if writeback register is in list, it must be the lowest reg in the list"
 msgstr ""
 
-#: config/tc-arm.c:4789
+#: config/tc-arm.c:6872
 msgid "first destination register must be even"
 msgstr ""
 
-#: config/tc-arm.c:4792 config/tc-arm.c:4849
+#: config/tc-arm.c:6875 config/tc-arm.c:6942
 msgid "can only load two consecutive registers"
 msgstr ""
 
@@ -1821,863 +1976,1052 @@ msgstr ""
 #. have been called in the first place.
 #. If op 2 were present and equal to PC, this function wouldn't
 #. have been called in the first place.
-#: config/tc-arm.c:4793 config/tc-arm.c:4852 config/tc-arm.c:5299
-#: config/tc-arm.c:6886
+#: config/tc-arm.c:6876 config/tc-arm.c:6945 config/tc-arm.c:7467
+#: config/tc-arm.c:9390
 msgid "r14 not allowed here"
 msgstr ""
 
-#: config/tc-arm.c:4794
-msgid "'[' expected"
-msgstr ""
-
-#: config/tc-arm.c:4807
+#: config/tc-arm.c:6890
 msgid "base register written back, and overlaps second destination register"
 msgstr ""
 
-#: config/tc-arm.c:4815
+#: config/tc-arm.c:6898
 msgid "index register overlaps destination register"
 msgstr ""
 
-#: config/tc-arm.c:4829 config/tc-arm.c:5272 config/tc-arm.c:6706
-#: config/tc-arm.c:7581
-msgid "instruction does not accept this addressing mode"
-msgstr ""
-
-#: config/tc-arm.c:4835 config/tc-arm.c:5281
+#: config/tc-arm.c:6928 config/tc-arm.c:7449
 msgid "offset must be zero in ARM encoding"
 msgstr ""
 
-#: config/tc-arm.c:4846 config/tc-arm.c:5293
+#: config/tc-arm.c:6939 config/tc-arm.c:7461
 msgid "even register required"
 msgstr ""
 
-#: config/tc-arm.c:4877 config/tc-arm.c:4908
+#: config/tc-arm.c:6970 config/tc-arm.c:7001
 msgid "this instruction requires a post-indexed address"
 msgstr ""
 
-#: config/tc-arm.c:4935
-msgid "rd and rm should be different in mla"
+#: config/tc-arm.c:7028
+msgid "Rd and Rm should be different in mla"
+msgstr ""
+
+#: config/tc-arm.c:7052 config/tc-arm.c:9648
+msgid ":lower16: not allowed this instruction"
+msgstr ""
+
+#: config/tc-arm.c:7054
+msgid ":upper16: not allowed instruction"
+msgstr ""
+
+#: config/tc-arm.c:7073
+msgid "operand 1 must be FPSCR"
 msgstr ""
 
-#: config/tc-arm.c:4967 config/tc-arm.c:7121
+#: config/tc-arm.c:7106 config/tc-arm.c:9757
 msgid "'CPSR' or 'SPSR' expected"
 msgstr ""
 
-#: config/tc-arm.c:5000
-msgid "rd and rm should be different in mul"
+#: config/tc-arm.c:7143
+msgid "Rd and Rm should be different in mul"
 msgstr ""
 
-#: config/tc-arm.c:5021
+#: config/tc-arm.c:7164
 msgid "rdhi, rdlo and rm must all be different"
 msgstr ""
 
-#: config/tc-arm.c:5083
+#: config/tc-arm.c:7226
 msgid "'[' expected after PLD mnemonic"
 msgstr ""
 
-#: config/tc-arm.c:5085
+#: config/tc-arm.c:7228 config/tc-arm.c:7243
 msgid "post-indexed expression used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5087
+#: config/tc-arm.c:7230 config/tc-arm.c:7245
 msgid "writeback used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5089
+#: config/tc-arm.c:7232 config/tc-arm.c:7247
 msgid "unindexed addressing used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5188 config/tc-arm.c:7492
-msgid "source1 and dest must be same register"
+#: config/tc-arm.c:7241
+msgid "'[' expected after PLI mnemonic"
 msgstr ""
 
-#: config/tc-arm.c:5238 config/tc-arm.c:7178
+#: config/tc-arm.c:7394 config/tc-arm.c:9837
 msgid "rdhi and rdlo must be different"
 msgstr ""
 
-#: config/tc-arm.c:5296
+#: config/tc-arm.c:7420
+msgid "SRS base register must be r13"
+msgstr ""
+
+#: config/tc-arm.c:7464
 msgid "can only store two consecutive registers"
 msgstr ""
 
-#: config/tc-arm.c:5391 config/tc-arm.c:5408
+#: config/tc-arm.c:7559 config/tc-arm.c:7576
 msgid "only two consecutive VFP SP registers allowed here"
 msgstr ""
 
-#: config/tc-arm.c:5436 config/tc-arm.c:5451
+#: config/tc-arm.c:7604 config/tc-arm.c:7619
 msgid "this addressing mode requires base-register writeback"
 msgstr ""
 
-#: config/tc-arm.c:5529
+#: config/tc-arm.c:7794
 msgid "this instruction does not support indexing"
 msgstr ""
 
-#: config/tc-arm.c:5552
+#: config/tc-arm.c:7818
 msgid "only r15 allowed here"
 msgstr ""
 
-#: config/tc-arm.c:5757
+#: config/tc-arm.c:7953
+msgid "immediate operand requires iWMMXt2"
+msgstr ""
+
+#: config/tc-arm.c:8097
 msgid "shift by register not allowed in thumb mode"
 msgstr ""
 
-#: config/tc-arm.c:5769 config/tc-arm.c:11339
+#: config/tc-arm.c:8109 config/tc-arm.c:18126
 msgid "shift expression is too large"
 msgstr ""
 
-#: config/tc-arm.c:5795
-msgid "Thumb does not support the ldr =N pseudo-operation"
+#: config/tc-arm.c:8135
+msgid "Instruction does not support =N addresses"
 msgstr ""
 
-#: config/tc-arm.c:5800
+#: config/tc-arm.c:8140
 msgid "cannot use register index with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5801
+#: config/tc-arm.c:8141
 msgid "cannot use register index with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5803
+#: config/tc-arm.c:8143
 msgid "Thumb does not support negative register indexing"
 msgstr ""
 
-#: config/tc-arm.c:5805
+#: config/tc-arm.c:8145
 msgid "Thumb does not support register post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:5807
+#: config/tc-arm.c:8147
 msgid "Thumb does not support register indexing with writeback"
 msgstr ""
 
-#: config/tc-arm.c:5809
+#: config/tc-arm.c:8149
 msgid "Thumb supports only LSL in shifted register indexing"
 msgstr ""
 
-#: config/tc-arm.c:5818
+#: config/tc-arm.c:8158 config/tc-arm.c:12899
 msgid "shift out of range"
 msgstr ""
 
-#: config/tc-arm.c:5826
+#: config/tc-arm.c:8166
 msgid "cannot use writeback with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5828
+#: config/tc-arm.c:8168
 msgid "cannot use writeback with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5847
+#: config/tc-arm.c:8187
 msgid "cannot use post-indexing with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:5848
+#: config/tc-arm.c:8188
 msgid "cannot use post-indexing with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:5975
+#: config/tc-arm.c:8315
 msgid "PC not allowed as destination"
 msgstr ""
 
-#: config/tc-arm.c:6093 config/tc-arm.c:6234 config/tc-arm.c:6326
-#: config/tc-arm.c:7092
+#: config/tc-arm.c:8386
+msgid "only SUBS PC, LR, #const allowed"
+msgstr ""
+
+#: config/tc-arm.c:8459 config/tc-arm.c:8600 config/tc-arm.c:8692
+#: config/tc-arm.c:9712
 msgid "shift must be constant"
 msgstr ""
 
-#: config/tc-arm.c:6120 config/tc-arm.c:6249 config/tc-arm.c:6341
-#: config/tc-arm.c:7105
+#: config/tc-arm.c:8486 config/tc-arm.c:8615 config/tc-arm.c:8707
+#: config/tc-arm.c:9725
 msgid "unshifted register required"
 msgstr ""
 
-#: config/tc-arm.c:6135 config/tc-arm.c:6352 config/tc-arm.c:7165
+#: config/tc-arm.c:8501 config/tc-arm.c:8718 config/tc-arm.c:9824
 msgid "dest must overlap one source register"
 msgstr ""
 
-#: config/tc-arm.c:6252
+#: config/tc-arm.c:8618
 msgid "dest and source1 must be the same register"
 msgstr ""
 
-#: config/tc-arm.c:6537
+#: config/tc-arm.c:8869
+msgid "instruction is always unconditional"
+msgstr ""
+
+#: config/tc-arm.c:8951
+msgid "selected processor does not support 'A' form of this instruction"
+msgstr ""
+
+#: config/tc-arm.c:8954
 msgid "Thumb does not support the 2-argument form of this instruction"
 msgstr ""
 
-#: config/tc-arm.c:6616
-msgid "Thumb load/store multiple does not support {reglist}^"
+#: config/tc-arm.c:9053
+msgid "SP not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:6633 config/tc-arm.c:6649 config/tc-arm.c:6680
-#, c-format
-msgid "value stored for r%d is UNPREDICTABLE"
+#: config/tc-arm.c:9058
+msgid "LR and PC should not both be in register list"
 msgstr ""
 
-#: config/tc-arm.c:6643
-msgid "SP should not be in register list"
+#: config/tc-arm.c:9062
+msgid "base register should not be in register list when written back"
 msgstr ""
 
-#: config/tc-arm.c:6647
-msgid "PC should not be in register list"
+#: config/tc-arm.c:9068
+msgid "PC not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:6656 config/tc-arm.c:7311
-msgid "LR and PC should not both be in register list"
+#: config/tc-arm.c:9071 config/tc-arm.c:9137 config/tc-arm.c:9177
+#, c-format
+msgid "value stored for r%d is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:6659
-msgid "base register should not be in register list when written back"
+#: config/tc-arm.c:9113
+msgid "Thumb load/store multiple does not support {reglist}^"
+msgstr ""
+
+#: config/tc-arm.c:9170
+msgid "Thumb-2 instruction only valid in unified syntax"
 msgstr ""
 
-#: config/tc-arm.c:6677 config/tc-arm.c:6687
+#: config/tc-arm.c:9174 config/tc-arm.c:9184
 msgid "this instruction will write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:6690
+#: config/tc-arm.c:9187
 msgid "this instruction will not write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:6719
+#: config/tc-arm.c:9216
 msgid "r14 not allowed as first register when second register is omitted"
 msgstr ""
 
-#: config/tc-arm.c:6809 config/tc-arm.c:6822 config/tc-arm.c:6858
+#: config/tc-arm.c:9313 config/tc-arm.c:9326 config/tc-arm.c:9362
 msgid "Thumb does not support this addressing mode"
 msgstr ""
 
-#: config/tc-arm.c:6826
+#: config/tc-arm.c:9330
 msgid "byte or halfword not valid for base register"
 msgstr ""
 
-#: config/tc-arm.c:6829
+#: config/tc-arm.c:9333
 msgid "r15 based store not allowed"
 msgstr ""
 
-#: config/tc-arm.c:6831
+#: config/tc-arm.c:9335
 msgid "invalid base register for register offset"
 msgstr ""
 
-#: config/tc-arm.c:7032
+#: config/tc-arm.c:9633
 msgid "only lo regs allowed with immediate"
 msgstr ""
 
-#: config/tc-arm.c:7130
-msgid "Thumb encoding does not support an immediate here"
+#: config/tc-arm.c:9653
+msgid ":upper16: not allowed this instruction"
 msgstr ""
 
-#: config/tc-arm.c:7200
-msgid "Thumb does not support NOP with hints"
+#: config/tc-arm.c:9747 config/tc-arm.c:9779 config/tc-arm.c:9785
+msgid "selected processor does not support requested special purpose register"
 msgstr ""
 
-#: config/tc-arm.c:7282
-msgid "push/pop do not support {reglist}^"
+#: config/tc-arm.c:9753
+#, c-format
+msgid ""
+"selected processor does not support requested special purpose register %x"
 msgstr ""
 
-#: config/tc-arm.c:7301
-msgid "SP not allowed in register list"
+#: config/tc-arm.c:9774
+msgid "Thumb encoding does not support an immediate here"
 msgstr ""
 
-#: config/tc-arm.c:7305
-msgid "PC not allowed in register list"
+#: config/tc-arm.c:9859
+msgid "Thumb does not support NOP with hints"
+msgstr ""
+
+#: config/tc-arm.c:9941
+msgid "push/pop do not support {reglist}^"
 msgstr ""
 
-#: config/tc-arm.c:7328
+#: config/tc-arm.c:9964
 msgid "invalid register list to push/pop instruction"
 msgstr ""
 
-#: config/tc-arm.c:7513
+#: config/tc-arm.c:10156
+msgid "source1 and dest must be same register"
+msgstr ""
+
+#: config/tc-arm.c:10177
 msgid "ror #imm not supported"
 msgstr ""
 
-#: config/tc-arm.c:7638
+#: config/tc-arm.c:10302
 msgid "Thumb encoding does not support rotation"
 msgstr ""
 
-#: config/tc-arm.c:7656
+#: config/tc-arm.c:10321
+msgid "instruction requires register index"
+msgstr ""
+
+#: config/tc-arm.c:10323
 msgid "PC is not a valid index register"
 msgstr ""
 
-#: config/tc-arm.c:7658
+#: config/tc-arm.c:10325
 msgid "instruction does not allow shifted index"
 msgstr ""
 
-#: config/tc-arm.c:7660
-msgid "instruction requires shifted index"
+#: config/tc-arm.c:10744
+msgid "invalid instruction shape"
+msgstr ""
+
+#: config/tc-arm.c:10986
+msgid "types specified in both the mnemonic and operands"
+msgstr ""
+
+#: config/tc-arm.c:11023
+msgid "operand types can't be inferred"
+msgstr ""
+
+#: config/tc-arm.c:11029
+msgid "type specifier has the wrong number of parts"
+msgstr ""
+
+#: config/tc-arm.c:11084
+msgid "operand size must match register width"
+msgstr ""
+
+#: config/tc-arm.c:11095
+msgid "bad type in Neon instruction"
+msgstr ""
+
+#: config/tc-arm.c:11106
+msgid "inconsistent types in Neon instruction"
+msgstr ""
+
+#: config/tc-arm.c:12155
+msgid "scalar out of range for multiply instruction"
+msgstr ""
+
+#: config/tc-arm.c:12319 config/tc-arm.c:12331
+msgid "immediate out of range for insert"
+msgstr ""
+
+#: config/tc-arm.c:12343 config/tc-arm.c:13245
+msgid "immediate out of range for shift"
+msgstr ""
+
+#: config/tc-arm.c:12400 config/tc-arm.c:12427 config/tc-arm.c:12745
+#: config/tc-arm.c:13191
+msgid "immediate out of range"
+msgstr ""
+
+#: config/tc-arm.c:12464
+msgid "immediate out of range for narrowing operation"
+msgstr ""
+
+#: config/tc-arm.c:12584
+msgid "operands 0 and 1 must be the same register"
+msgstr ""
+
+#: config/tc-arm.c:12719
+msgid "operand size must be specified for immediate VMOV"
+msgstr ""
+
+#: config/tc-arm.c:12729
+msgid "immediate has bits set outside the operand size"
+msgstr ""
+
+#: config/tc-arm.c:12925
+msgid "elements must be smaller than reversal region"
 msgstr ""
 
-#: config/tc-arm.c:7943 config/tc-arm.c:8015
+#: config/tc-arm.c:13096 config/tc-arm.c:13144
+msgid "bad type for scalar"
+msgstr ""
+
+#: config/tc-arm.c:13208 config/tc-arm.c:13216
+msgid "VFP registers must be adjacent"
+msgstr ""
+
+#: config/tc-arm.c:13357
+msgid "bad list length for table lookup"
+msgstr ""
+
+#: config/tc-arm.c:13387
+msgid "writeback (!) must be used for VLDMDB and VSTMDB"
+msgstr ""
+
+#: config/tc-arm.c:13390
+msgid "register list must contain at least 1 and at most 16 registers"
+msgstr ""
+
+#: config/tc-arm.c:13467
+msgid "bad alignment"
+msgstr ""
+
+#: config/tc-arm.c:13484
+msgid "bad list type for instruction"
+msgstr ""
+
+#: config/tc-arm.c:13526
+msgid "unsupported alignment for instruction"
+msgstr ""
+
+#: config/tc-arm.c:13545 config/tc-arm.c:13639 config/tc-arm.c:13650
+#: config/tc-arm.c:13660 config/tc-arm.c:13674
+msgid "bad list length"
+msgstr ""
+
+#: config/tc-arm.c:13550
+msgid "stride of 2 unavailable when element size is 8"
+msgstr ""
+
+#: config/tc-arm.c:13583 config/tc-arm.c:13658
+msgid "can't use alignment with this instruction"
+msgstr ""
+
+#: config/tc-arm.c:13722
+msgid "post-index must be a register"
+msgstr ""
+
+#: config/tc-arm.c:13724
+msgid "bad register for post-index"
+msgstr ""
+
+#: config/tc-arm.c:14011 config/tc-arm.c:14097
 msgid "conditional infixes are deprecated in unified syntax"
 msgstr ""
 
-#: config/tc-arm.c:8047
+#: config/tc-arm.c:14130
 #, c-format
 msgid "bad instruction `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8063 config/tc-arm.c:8126
+#: config/tc-arm.c:14136
+msgid "s suffix on comparison instruction is deprecated"
+msgstr ""
+
+#: config/tc-arm.c:14155 config/tc-arm.c:14236
 #, c-format
 msgid "selected processor does not support `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8069
+#: config/tc-arm.c:14161
 msgid "Thumb does not support conditional execution"
 msgstr ""
 
-#: config/tc-arm.c:8080
+#: config/tc-arm.c:14184
 msgid "incorrect condition in IT block"
 msgstr ""
 
-#: config/tc-arm.c:8088
+#: config/tc-arm.c:14190
 msgid "thumb conditional instrunction not in IT block"
 msgstr ""
 
-#: config/tc-arm.c:8108
+#: config/tc-arm.c:14210
 #, c-format
 msgid "cannot honor width suffix -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:8131
+#: config/tc-arm.c:14241
 #, c-format
 msgid "width suffixes are invalid in ARM mode -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:10340
+#: config/tc-arm.c:14265
+#, c-format
+msgid "attempt to use an ARM instruction on a Thumb-only processor -- `%s'"
+msgstr ""
+
+#: config/tc-arm.c:16992
 msgid "alignments greater than 32 bytes not supported in .text sections."
 msgstr ""
 
-#: config/tc-arm.c:10634
+#: config/tc-arm.c:17286
 msgid "handerdata in cantunwind frame"
 msgstr ""
 
-#: config/tc-arm.c:10651
+#: config/tc-arm.c:17303
 msgid "too many unwind opcodes for personality routine 0"
 msgstr ""
 
-#: config/tc-arm.c:10683
+#: config/tc-arm.c:17335
 msgid "too many unwind opcodes"
 msgstr ""
 
-#: config/tc-arm.c:11085 config/tc-arm.c:11365
+#: config/tc-arm.c:17869 config/tc-arm.c:18153
 #, c-format
 msgid "undefined symbol %s used as an immediate value"
 msgstr ""
 
-#: config/tc-arm.c:11099 config/tc-arm.c:11394
+#: config/tc-arm.c:17883 config/tc-arm.c:18192
 #, c-format
 msgid "invalid constant (%lx) after fixup"
 msgstr ""
 
-#: config/tc-arm.c:11136
+#: config/tc-arm.c:17920
 #, c-format
 msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
 msgstr ""
 
-#: config/tc-arm.c:11168 config/tc-arm.c:11193
+#: config/tc-arm.c:17955 config/tc-arm.c:17980
 msgid "invalid literal constant: pool needs to be closer"
 msgstr ""
 
-#: config/tc-arm.c:11171 config/tc-arm.c:11209
+#: config/tc-arm.c:17958 config/tc-arm.c:17996
 #, c-format
 msgid "bad immediate value for offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:11195
+#: config/tc-arm.c:17982
 #, c-format
-msgid "bad immediate value for half-word offset (%ld)"
+msgid "bad immediate value for 8-bit offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:11250
+#: config/tc-arm.c:18037
 msgid "offset not a multiple of 4"
 msgstr ""
 
-#: config/tc-arm.c:11257 config/tc-arm.c:11272 config/tc-arm.c:11287
-#: config/tc-arm.c:11298 config/tc-arm.c:11321 config/tc-pj.c:499
-#: config/tc-sh.c:4084
+#: config/tc-arm.c:18044 config/tc-arm.c:18059 config/tc-arm.c:18074
+#: config/tc-arm.c:18085 config/tc-arm.c:18108 config/tc-pj.c:499
+#: config/tc-sh.c:4214
 msgid "offset out of range"
 msgstr ""
 
-#: config/tc-arm.c:11410
+#: config/tc-arm.c:18208
 msgid "invalid smc expression"
 msgstr ""
 
-#: config/tc-arm.c:11421 config/tc-arm.c:11430
+#: config/tc-arm.c:18219 config/tc-arm.c:18228
 msgid "invalid swi expression"
 msgstr ""
 
-#: config/tc-arm.c:11440
+#: config/tc-arm.c:18238
 msgid "invalid expression in load/store multiple"
 msgstr ""
 
-#: config/tc-arm.c:11455
+#: config/tc-arm.c:18268
 msgid "misaligned branch destination"
 msgstr ""
 
-#: config/tc-arm.c:11459 config/tc-arm.c:11479 config/tc-arm.c:11497
-#: config/tc-arm.c:11510 config/tc-arm.c:11523 config/tc-arm.c:11562
-#: config/tc-arm.c:11587
+#: config/tc-arm.c:18272 config/tc-arm.c:18309 config/tc-arm.c:18323
+#: config/tc-arm.c:18336 config/tc-arm.c:18375 config/tc-arm.c:18400
 msgid "branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:11475
-msgid "misaligned BLX destination"
-msgstr ""
-
-#: config/tc-arm.c:11536
+#: config/tc-arm.c:18349
 msgid "conditional branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:11657
+#: config/tc-arm.c:18477
 msgid "rel31 relocation overflow"
 msgstr ""
 
-#: config/tc-arm.c:11669 config/tc-arm.c:11694
+#: config/tc-arm.c:18489 config/tc-arm.c:18512
 msgid "co-processor offset out of range"
 msgstr ""
 
-#: config/tc-arm.c:11710
+#: config/tc-arm.c:18529
 #, c-format
 msgid "invalid offset, target not word aligned (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11716 config/tc-arm.c:11725 config/tc-arm.c:11733
-#: config/tc-arm.c:11741 config/tc-arm.c:11749
+#: config/tc-arm.c:18536 config/tc-arm.c:18545 config/tc-arm.c:18553
+#: config/tc-arm.c:18561 config/tc-arm.c:18569
 #, c-format
 msgid "invalid offset, value too big (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11790
+#: config/tc-arm.c:18610
 msgid "invalid Hi register with immediate"
 msgstr ""
 
-#: config/tc-arm.c:11806
+#: config/tc-arm.c:18626
 msgid "invalid immediate for stack address calculation"
 msgstr ""
 
-#: config/tc-arm.c:11814
+#: config/tc-arm.c:18634
 #, c-format
 msgid "invalid immediate for address calculation (value = 0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11844
+#: config/tc-arm.c:18664
 #, c-format
 msgid "invalid immediate: %ld is too large"
 msgstr ""
 
-#: config/tc-arm.c:11856
+#: config/tc-arm.c:18676
 #, c-format
 msgid "invalid shift value: %ld"
 msgstr ""
 
-#: config/tc-arm.c:11875
+#: config/tc-arm.c:18703
+msgid "offset too big"
+msgstr ""
+
+#: config/tc-arm.c:18755
+#, c-format
+msgid "the offset 0x%08lX is not representable"
+msgstr ""
+
+#: config/tc-arm.c:18795
+#, c-format
+msgid "bad offset 0x%08lX (only 12 bits available for the magnitude)"
+msgstr ""
+
+#: config/tc-arm.c:18834
+#, c-format
+msgid "bad offset 0x%08lX (only 8 bits available for the magnitude)"
+msgstr ""
+
+#: config/tc-arm.c:18874
+#, c-format
+msgid "bad offset 0x%08lX (must be word-aligned)"
+msgstr ""
+
+#: config/tc-arm.c:18879
+#, c-format
+msgid "bad offset 0x%08lX (must be an 8-bit number of words)"
+msgstr ""
+
+#: config/tc-arm.c:18905 config/tc-score.c:5480
 #, c-format
 msgid "bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-arm.c:11943
+#: config/tc-arm.c:19008
 msgid "literal referenced across section boundary"
 msgstr ""
 
-#: config/tc-arm.c:11973
+#: config/tc-arm.c:19068
 msgid "internal relocation (type: IMMEDIATE) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:11978
+#: config/tc-arm.c:19073
 msgid "ADRL used for a symbol not defined in the same file"
 msgstr ""
 
-#: config/tc-arm.c:11987
+#: config/tc-arm.c:19088
 #, c-format
 msgid "undefined local label `%s'"
 msgstr ""
 
-#: config/tc-arm.c:11993
+#: config/tc-arm.c:19094
 msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:12014 config/tc-cris.c:3869 config/tc-mcore.c:1995
-#: config/tc-mmix.c:2888 config/tc-ns32k.c:2284
+#: config/tc-arm.c:19115 config/tc-cris.c:3925 config/tc-mcore.c:1992
+#: config/tc-mmix.c:2887 config/tc-ns32k.c:2282 config/tc-score.c:5571
 msgid "<unknown>"
 msgstr ""
 
-#: config/tc-arm.c:12017 config/tc-arm.c:12038
+#: config/tc-arm.c:19118 config/tc-arm.c:19139 config/tc-score.c:5573
 #, c-format
 msgid "cannot represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-arm.c:12254
+#: config/tc-arm.c:19373
 #, c-format
 msgid "%s: unexpected function type: %d"
 msgstr ""
 
-#: config/tc-arm.c:12331
+#: config/tc-arm.c:19463 config/tc-score.c:6592 config/tc-score.c:6608
+#: config/tc-score.c:6613
 msgid "virtual memory exhausted"
 msgstr ""
 
-#: config/tc-arm.c:12357
+#: config/tc-arm.c:19496
 msgid "use of old and new-style options to set CPU type"
 msgstr ""
 
-#: config/tc-arm.c:12367
+#: config/tc-arm.c:19506
 msgid "use of old and new-style options to set FPU type"
 msgstr ""
 
-#: config/tc-arm.c:12441
+#: config/tc-arm.c:19581
 msgid "hard-float conflicts with specified fpu"
 msgstr ""
 
-#: config/tc-arm.c:12633
+#: config/tc-arm.c:19764
 msgid "generate PIC code"
 msgstr ""
 
-#: config/tc-arm.c:12634
+#: config/tc-arm.c:19765
 msgid "assemble Thumb code"
 msgstr ""
 
-#: config/tc-arm.c:12635
+#: config/tc-arm.c:19766
 msgid "support ARM/Thumb interworking"
 msgstr ""
 
-#: config/tc-arm.c:12637
+#: config/tc-arm.c:19768
 msgid "code uses 32-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:12638
+#: config/tc-arm.c:19769
 msgid "code uses 26-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:12639
+#: config/tc-arm.c:19770
 msgid "floating point args are in fp regs"
 msgstr ""
 
-#: config/tc-arm.c:12641
+#: config/tc-arm.c:19772
 msgid "re-entrant code"
 msgstr ""
 
-#: config/tc-arm.c:12642
+#: config/tc-arm.c:19773
 msgid "code is ATPCS conformant"
 msgstr ""
 
-#: config/tc-arm.c:12643
+#: config/tc-arm.c:19774
 msgid "assemble for big-endian"
 msgstr ""
 
-#: config/tc-arm.c:12644
+#: config/tc-arm.c:19775
 msgid "assemble for little-endian"
 msgstr ""
 
 #. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:12648
+#: config/tc-arm.c:19779
 msgid "use frame pointer"
 msgstr ""
 
-#: config/tc-arm.c:12649
+#: config/tc-arm.c:19780
 msgid "use stack size checking"
 msgstr ""
 
 #. DON'T add any new processors to this list -- we want the whole list
 #. to go away...  Add them to the processors table instead.
-#: config/tc-arm.c:12653 config/tc-arm.c:12654
+#: config/tc-arm.c:19796 config/tc-arm.c:19797
 msgid "use -mcpu=arm1"
 msgstr ""
 
-#: config/tc-arm.c:12655 config/tc-arm.c:12656
+#: config/tc-arm.c:19798 config/tc-arm.c:19799
 msgid "use -mcpu=arm2"
 msgstr ""
 
-#: config/tc-arm.c:12657 config/tc-arm.c:12658
+#: config/tc-arm.c:19800 config/tc-arm.c:19801
 msgid "use -mcpu=arm250"
 msgstr ""
 
-#: config/tc-arm.c:12659 config/tc-arm.c:12660
+#: config/tc-arm.c:19802 config/tc-arm.c:19803
 msgid "use -mcpu=arm3"
 msgstr ""
 
-#: config/tc-arm.c:12661 config/tc-arm.c:12662
+#: config/tc-arm.c:19804 config/tc-arm.c:19805
 msgid "use -mcpu=arm6"
 msgstr ""
 
-#: config/tc-arm.c:12663 config/tc-arm.c:12664
+#: config/tc-arm.c:19806 config/tc-arm.c:19807
 msgid "use -mcpu=arm600"
 msgstr ""
 
-#: config/tc-arm.c:12665 config/tc-arm.c:12666
+#: config/tc-arm.c:19808 config/tc-arm.c:19809
 msgid "use -mcpu=arm610"
 msgstr ""
 
-#: config/tc-arm.c:12667 config/tc-arm.c:12668
+#: config/tc-arm.c:19810 config/tc-arm.c:19811
 msgid "use -mcpu=arm620"
 msgstr ""
 
-#: config/tc-arm.c:12669 config/tc-arm.c:12670
+#: config/tc-arm.c:19812 config/tc-arm.c:19813
 msgid "use -mcpu=arm7"
 msgstr ""
 
-#: config/tc-arm.c:12671 config/tc-arm.c:12672
+#: config/tc-arm.c:19814 config/tc-arm.c:19815
 msgid "use -mcpu=arm70"
 msgstr ""
 
-#: config/tc-arm.c:12673 config/tc-arm.c:12674
+#: config/tc-arm.c:19816 config/tc-arm.c:19817
 msgid "use -mcpu=arm700"
 msgstr ""
 
-#: config/tc-arm.c:12675 config/tc-arm.c:12676
+#: config/tc-arm.c:19818 config/tc-arm.c:19819
 msgid "use -mcpu=arm700i"
 msgstr ""
 
-#: config/tc-arm.c:12677 config/tc-arm.c:12678
+#: config/tc-arm.c:19820 config/tc-arm.c:19821
 msgid "use -mcpu=arm710"
 msgstr ""
 
-#: config/tc-arm.c:12679 config/tc-arm.c:12680
+#: config/tc-arm.c:19822 config/tc-arm.c:19823
 msgid "use -mcpu=arm710c"
 msgstr ""
 
-#: config/tc-arm.c:12681 config/tc-arm.c:12682
+#: config/tc-arm.c:19824 config/tc-arm.c:19825
 msgid "use -mcpu=arm720"
 msgstr ""
 
-#: config/tc-arm.c:12683 config/tc-arm.c:12684
+#: config/tc-arm.c:19826 config/tc-arm.c:19827
 msgid "use -mcpu=arm7d"
 msgstr ""
 
-#: config/tc-arm.c:12685 config/tc-arm.c:12686
+#: config/tc-arm.c:19828 config/tc-arm.c:19829
 msgid "use -mcpu=arm7di"
 msgstr ""
 
-#: config/tc-arm.c:12687 config/tc-arm.c:12688
+#: config/tc-arm.c:19830 config/tc-arm.c:19831
 msgid "use -mcpu=arm7m"
 msgstr ""
 
-#: config/tc-arm.c:12689 config/tc-arm.c:12690
+#: config/tc-arm.c:19832 config/tc-arm.c:19833
 msgid "use -mcpu=arm7dm"
 msgstr ""
 
-#: config/tc-arm.c:12691 config/tc-arm.c:12692
+#: config/tc-arm.c:19834 config/tc-arm.c:19835
 msgid "use -mcpu=arm7dmi"
 msgstr ""
 
-#: config/tc-arm.c:12693 config/tc-arm.c:12694
+#: config/tc-arm.c:19836 config/tc-arm.c:19837
 msgid "use -mcpu=arm7100"
 msgstr ""
 
-#: config/tc-arm.c:12695 config/tc-arm.c:12696
+#: config/tc-arm.c:19838 config/tc-arm.c:19839
 msgid "use -mcpu=arm7500"
 msgstr ""
 
-#: config/tc-arm.c:12697 config/tc-arm.c:12698
+#: config/tc-arm.c:19840 config/tc-arm.c:19841
 msgid "use -mcpu=arm7500fe"
 msgstr ""
 
-#: config/tc-arm.c:12699 config/tc-arm.c:12700 config/tc-arm.c:12701
-#: config/tc-arm.c:12702
+#: config/tc-arm.c:19842 config/tc-arm.c:19843 config/tc-arm.c:19844
+#: config/tc-arm.c:19845
 msgid "use -mcpu=arm7tdmi"
 msgstr ""
 
-#: config/tc-arm.c:12703 config/tc-arm.c:12704
+#: config/tc-arm.c:19846 config/tc-arm.c:19847
 msgid "use -mcpu=arm710t"
 msgstr ""
 
-#: config/tc-arm.c:12705 config/tc-arm.c:12706
+#: config/tc-arm.c:19848 config/tc-arm.c:19849
 msgid "use -mcpu=arm720t"
 msgstr ""
 
-#: config/tc-arm.c:12707 config/tc-arm.c:12708
+#: config/tc-arm.c:19850 config/tc-arm.c:19851
 msgid "use -mcpu=arm740t"
 msgstr ""
 
-#: config/tc-arm.c:12709 config/tc-arm.c:12710
+#: config/tc-arm.c:19852 config/tc-arm.c:19853
 msgid "use -mcpu=arm8"
 msgstr ""
 
-#: config/tc-arm.c:12711 config/tc-arm.c:12712
+#: config/tc-arm.c:19854 config/tc-arm.c:19855
 msgid "use -mcpu=arm810"
 msgstr ""
 
-#: config/tc-arm.c:12713 config/tc-arm.c:12714
+#: config/tc-arm.c:19856 config/tc-arm.c:19857
 msgid "use -mcpu=arm9"
 msgstr ""
 
-#: config/tc-arm.c:12715 config/tc-arm.c:12716
+#: config/tc-arm.c:19858 config/tc-arm.c:19859
 msgid "use -mcpu=arm9tdmi"
 msgstr ""
 
-#: config/tc-arm.c:12717 config/tc-arm.c:12718
+#: config/tc-arm.c:19860 config/tc-arm.c:19861
 msgid "use -mcpu=arm920"
 msgstr ""
 
-#: config/tc-arm.c:12719 config/tc-arm.c:12720
+#: config/tc-arm.c:19862 config/tc-arm.c:19863
 msgid "use -mcpu=arm940"
 msgstr ""
 
-#: config/tc-arm.c:12721
+#: config/tc-arm.c:19864
 msgid "use -mcpu=strongarm"
 msgstr ""
 
-#: config/tc-arm.c:12723
+#: config/tc-arm.c:19866
 msgid "use -mcpu=strongarm110"
 msgstr ""
 
-#: config/tc-arm.c:12725
+#: config/tc-arm.c:19868
 msgid "use -mcpu=strongarm1100"
 msgstr ""
 
-#: config/tc-arm.c:12727
+#: config/tc-arm.c:19870
 msgid "use -mcpu=strongarm1110"
 msgstr ""
 
-#: config/tc-arm.c:12728
+#: config/tc-arm.c:19871
 msgid "use -mcpu=xscale"
 msgstr ""
 
-#: config/tc-arm.c:12729
+#: config/tc-arm.c:19872
 msgid "use -mcpu=iwmmxt"
 msgstr ""
 
-#: config/tc-arm.c:12730
+#: config/tc-arm.c:19873
 msgid "use -mcpu=all"
 msgstr ""
 
 #. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:12733 config/tc-arm.c:12734
+#: config/tc-arm.c:19876 config/tc-arm.c:19877
 msgid "use -march=armv2"
 msgstr ""
 
-#: config/tc-arm.c:12735 config/tc-arm.c:12736
+#: config/tc-arm.c:19878 config/tc-arm.c:19879
 msgid "use -march=armv2a"
 msgstr ""
 
-#: config/tc-arm.c:12737 config/tc-arm.c:12738
+#: config/tc-arm.c:19880 config/tc-arm.c:19881
 msgid "use -march=armv3"
 msgstr ""
 
-#: config/tc-arm.c:12739 config/tc-arm.c:12740
+#: config/tc-arm.c:19882 config/tc-arm.c:19883
 msgid "use -march=armv3m"
 msgstr ""
 
-#: config/tc-arm.c:12741 config/tc-arm.c:12742
+#: config/tc-arm.c:19884 config/tc-arm.c:19885
 msgid "use -march=armv4"
 msgstr ""
 
-#: config/tc-arm.c:12743 config/tc-arm.c:12744
+#: config/tc-arm.c:19886 config/tc-arm.c:19887
 msgid "use -march=armv4t"
 msgstr ""
 
-#: config/tc-arm.c:12745 config/tc-arm.c:12746
+#: config/tc-arm.c:19888 config/tc-arm.c:19889
 msgid "use -march=armv5"
 msgstr ""
 
-#: config/tc-arm.c:12747 config/tc-arm.c:12748
+#: config/tc-arm.c:19890 config/tc-arm.c:19891
 msgid "use -march=armv5t"
 msgstr ""
 
-#: config/tc-arm.c:12749 config/tc-arm.c:12750
+#: config/tc-arm.c:19892 config/tc-arm.c:19893
 msgid "use -march=armv5te"
 msgstr ""
 
 #. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:12753
+#: config/tc-arm.c:19896
 msgid "use -mfpu=fpe"
 msgstr ""
 
-#: config/tc-arm.c:12754
+#: config/tc-arm.c:19897
 msgid "use -mfpu=fpa10"
 msgstr ""
 
-#: config/tc-arm.c:12755
+#: config/tc-arm.c:19898
 msgid "use -mfpu=fpa11"
 msgstr ""
 
-#: config/tc-arm.c:12757
+#: config/tc-arm.c:19900
 msgid "use either -mfpu=softfpa or -mfpu=softvfp"
 msgstr ""
 
-#: config/tc-arm.c:12986
+#: config/tc-arm.c:20161
 msgid "invalid architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:13000
+#: config/tc-arm.c:20175
 msgid "missing architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:13013
+#: config/tc-arm.c:20188
 #, c-format
 msgid "unknown architectural extnsion `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13037
+#: config/tc-arm.c:20212
 #, c-format
 msgid "missing cpu name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13062 config/tc-arm.c:13389
+#: config/tc-arm.c:20237 config/tc-arm.c:20622
 #, c-format
 msgid "unknown cpu `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13080
+#: config/tc-arm.c:20255
 #, c-format
 msgid "missing architecture name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:13097 config/tc-arm.c:13423
+#: config/tc-arm.c:20272 config/tc-arm.c:20656 config/tc-arm.c:20687
 #, c-format
 msgid "unknown architecture `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13113 config/tc-arm.c:13454
+#: config/tc-arm.c:20288 config/tc-arm.c:20718
 #, c-format
 msgid "unknown floating point format `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13129
+#: config/tc-arm.c:20304
 #, c-format
 msgid "unknown floating point abi `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13145
+#: config/tc-arm.c:20320
 #, c-format
 msgid "unknown EABI `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:13152
+#: config/tc-arm.c:20327
 msgid "<cpu name>\t  assemble for CPU <cpu name>"
 msgstr ""
 
-#: config/tc-arm.c:13154
+#: config/tc-arm.c:20329
 msgid "<arch name>\t  assemble for architecture <arch name>"
 msgstr ""
 
-#: config/tc-arm.c:13156
+#: config/tc-arm.c:20331
 msgid "<fpu name>\t  assemble for FPU architecture <fpu name>"
 msgstr ""
 
-#: config/tc-arm.c:13158
+#: config/tc-arm.c:20333
 msgid "<abi>\t  assemble for floating point ABI <abi>"
 msgstr ""
 
-#: config/tc-arm.c:13161
+#: config/tc-arm.c:20336
 msgid "<ver>\t  assemble for eabi version <ver>"
 msgstr ""
 
-#: config/tc-arm.c:13202 config/tc-arm.c:13224
+#: config/tc-arm.c:20378 config/tc-arm.c:20398 config/tc-arm.c:20420
 #, c-format
 msgid "option `-%c%s' is deprecated: %s"
 msgstr ""
 
-#: config/tc-arm.c:13245
+#: config/tc-arm.c:20441
 #, c-format
 msgid " ARM-specific assembler options:\n"
 msgstr ""
 
-#: config/tc-arm.c:13256
+#: config/tc-arm.c:20452
 #, c-format
 msgid "  -EB                     assemble code for a big-endian cpu\n"
 msgstr ""
 
-#: config/tc-arm.c:13261
+#: config/tc-arm.c:20457
 #, c-format
 msgid "  -EL                     assemble code for a little-endian cpu\n"
 msgstr ""
 
-#: config/tc-avr.c:209
+#: config/tc-avr.c:258
 #, c-format
 msgid "Known MCU names:"
 msgstr ""
 
-#: config/tc-avr.c:275
+#: config/tc-avr.c:324
 #, c-format
 msgid ""
 "AVR options:\n"
@@ -2691,7 +3035,7 @@ msgid ""
 "                   or immediate microcontroller name.\n"
 msgstr ""
 
-#: config/tc-avr.c:285
+#: config/tc-avr.c:334
 #, c-format
 msgid ""
 "  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
@@ -2701,562 +3045,719 @@ msgid ""
 "                   (default for avr3, avr5)\n"
 msgstr ""
 
-#: config/tc-avr.c:329 config/tc-msp430.c:749
+#: config/tc-avr.c:378 config/tc-msp430.c:747
 #, c-format
 msgid "unknown MCU: %s\n"
 msgstr ""
 
-#: config/tc-avr.c:338
+#: config/tc-avr.c:387
 #, c-format
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr ""
 
-#: config/tc-avr.c:385 config/tc-crx.c:491 config/tc-d10v.c:278
-#: config/tc-d30v.c:312 config/tc-mips.c:10241 config/tc-mmix.c:2264
-#: config/tc-mn10200.c:342 config/tc-msp430.c:873 config/tc-pj.c:342
-#: config/tc-ppc.c:5211 config/tc-sh.c:2986 config/tc-v850.c:1199
+#: config/tc-avr.c:434 config/tc-cr16.c:670 config/tc-crx.c:491
+#: config/tc-d10v.c:277 config/tc-d30v.c:311 config/tc-mips.c:10769
+#: config/tc-mmix.c:2263 config/tc-mn10200.c:341 config/tc-msp430.c:871
+#: config/tc-pj.c:342 config/tc-ppc.c:5206 config/tc-sh.c:3076
+#: config/tc-v850.c:1198
 msgid "bad call to md_atof"
 msgstr ""
 
-#: config/tc-avr.c:447
+#: config/tc-avr.c:501
 msgid "constant value required"
 msgstr ""
 
-#: config/tc-avr.c:450
+#: config/tc-avr.c:504
 #, c-format
 msgid "number must be less than %d"
 msgstr ""
 
-#: config/tc-avr.c:476 config/tc-avr.c:583
+#: config/tc-avr.c:530 config/tc-avr.c:665
 #, c-format
 msgid "constant out of 8-bit range: %d"
 msgstr ""
 
-#: config/tc-avr.c:488 config/tc-d10v.c:498 config/tc-d30v.c:490
-#: config/tc-h8300.c:451 config/tc-mcore.c:665 config/tc-mmix.c:489
-#: config/tc-mn10200.c:1078 config/tc-mn10300.c:1820 config/tc-msp430.c:457
-#: config/tc-or32.c:306 config/tc-ppc.c:2382 config/tc-s390.c:1220
-#: config/tc-sh64.c:2213 config/tc-sh.c:1272 config/tc-v850.c:1952
-#: config/tc-z8k.c:328
+#: config/tc-avr.c:542 config/tc-d10v.c:497 config/tc-d30v.c:489
+#: config/tc-h8300.c:449 config/tc-mcore.c:662 config/tc-mmix.c:488
+#: config/tc-mn10200.c:1077 config/tc-mn10300.c:1819 config/tc-msp430.c:455
+#: config/tc-or32.c:307 config/tc-ppc.c:2436 config/tc-s390.c:1221
+#: config/tc-sh64.c:2213 config/tc-sh.c:1359 config/tc-v850.c:1967
+#: config/tc-z80.c:575 config/tc-z8k.c:350
 msgid "missing operand"
 msgstr ""
 
-#: config/tc-avr.c:536 read.c:3345
+#: config/tc-avr.c:598 config/tc-score.c:974 read.c:3560
 msgid "illegal expression"
 msgstr ""
 
-#: config/tc-avr.c:562 config/tc-avr.c:1282
+#: config/tc-avr.c:627 config/tc-avr.c:1386
 msgid "`)' required"
 msgstr ""
 
-#: config/tc-avr.c:638
+#: config/tc-avr.c:648
+msgid "expression dangerous with linker stubs"
+msgstr ""
+
+#: config/tc-avr.c:720
 msgid "register r16-r23 required"
 msgstr ""
 
-#: config/tc-avr.c:644
+#: config/tc-avr.c:726
 msgid "register number above 15 required"
 msgstr ""
 
-#: config/tc-avr.c:650
+#: config/tc-avr.c:732
 msgid "even register number required"
 msgstr ""
 
-#: config/tc-avr.c:656
+#: config/tc-avr.c:738
 msgid "register r24, r26, r28 or r30 required"
 msgstr ""
 
-#: config/tc-avr.c:662
+#: config/tc-avr.c:744
 msgid "register name or number from 0 to 31 required"
 msgstr ""
 
-#: config/tc-avr.c:680
+#: config/tc-avr.c:762
 msgid "pointer register (X, Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:687
+#: config/tc-avr.c:769
 msgid "cannot both predecrement and postincrement"
 msgstr ""
 
-#: config/tc-avr.c:695
+#: config/tc-avr.c:777
 msgid "addressing mode not supported"
 msgstr ""
 
-#: config/tc-avr.c:701
+#: config/tc-avr.c:783
 msgid "can't predecrement"
 msgstr ""
 
-#: config/tc-avr.c:704
+#: config/tc-avr.c:786
 msgid "pointer register Z required"
 msgstr ""
 
-#: config/tc-avr.c:722
+#: config/tc-avr.c:804
 msgid "pointer register (Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:826
+#: config/tc-avr.c:908
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: config/tc-avr.c:878
+#: config/tc-avr.c:960
 msgid "`,' required"
 msgstr ""
 
-#: config/tc-avr.c:896
+#: config/tc-avr.c:978
 msgid "undefined combination of operands"
 msgstr ""
 
-#: config/tc-avr.c:905
+#: config/tc-avr.c:987
 msgid "skipping two-word instruction"
 msgstr ""
 
-#: config/tc-avr.c:997 config/tc-avr.c:1013 config/tc-avr.c:1135
-#: config/tc-msp430.c:2012 config/tc-msp430.c:2030
+#: config/tc-avr.c:1079 config/tc-avr.c:1095 config/tc-avr.c:1209
+#: config/tc-msp430.c:2009 config/tc-msp430.c:2027
 #, c-format
 msgid "odd address operand: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1005 config/tc-avr.c:1024 config/tc-avr.c:1046
-#: config/tc-avr.c:1053 config/tc-avr.c:1060 config/tc-d10v.c:538
-#: config/tc-d30v.c:589 config/tc-msp430.c:2020 config/tc-msp430.c:2035
-#: config/tc-msp430.c:2045
+#: config/tc-avr.c:1087 config/tc-avr.c:1106 config/tc-avr.c:1128
+#: config/tc-avr.c:1135 config/tc-avr.c:1142 config/tc-d10v.c:537
+#: config/tc-d30v.c:588 config/tc-msp430.c:2017 config/tc-msp430.c:2032
+#: config/tc-msp430.c:2042
 #, c-format
 msgid "operand out of range: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1144 config/tc-d10v.c:1622 config/tc-d30v.c:2060
-#: config/tc-msp430.c:2063
+#: config/tc-avr.c:1218 config/tc-d10v.c:1619 config/tc-d30v.c:2059
+#: config/tc-msp430.c:2060
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr ""
 
-#: config/tc-avr.c:1158
+#: config/tc-avr.c:1232
 msgid "only constant expression allowed"
 msgstr ""
 
 #. xgettext:c-format.
-#: config/tc-avr.c:1192 config/tc-bfin.c:689 config/tc-d10v.c:1494
-#: config/tc-d30v.c:1804 config/tc-mn10200.c:814 config/tc-mn10300.c:2308
-#: config/tc-msp430.c:2098 config/tc-or32.c:1019 config/tc-ppc.c:6064
-#: config/tc-v850.c:2190
+#: config/tc-avr.c:1292 config/tc-bfin.c:771 config/tc-d10v.c:1491
+#: config/tc-d30v.c:1803 config/tc-mn10200.c:813 config/tc-mn10300.c:2311
+#: config/tc-msp430.c:2095 config/tc-or32.c:1017 config/tc-ppc.c:6085
+#: config/tc-spu.c:884 config/tc-spu.c:1071 config/tc-v850.c:2219
+#: config/tc-z80.c:2017
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr ""
 
-#: config/tc-avr.c:1215 config/tc-d10v.c:1782 config/tc-d10v.c:1796
-#: config/tc-h8300.c:1868 config/tc-mcore.c:884 config/tc-msp430.c:1862
-#: config/tc-pj.c:254 config/tc-sh.c:2457 config/tc-z8k.c:1194
+#: config/tc-avr.c:1315 config/tc-h8300.c:1866 config/tc-mcore.c:881
+#: config/tc-msp430.c:1860 config/tc-pj.c:254 config/tc-sh.c:2544
+#: config/tc-z8k.c:1216
 msgid "can't find opcode "
 msgstr ""
 
-#: config/tc-avr.c:1232
+#: config/tc-avr.c:1332
 #, c-format
 msgid "illegal opcode %s for mcu %s"
 msgstr ""
 
-#: config/tc-avr.c:1241
+#: config/tc-avr.c:1341
 msgid "garbage at end of line"
 msgstr ""
 
-#: config/tc-avr.c:1309 config/tc-avr.c:1316
+#: config/tc-avr.c:1413 config/tc-avr.c:1420
 #, c-format
 msgid "illegal %srelocation size: %d"
 msgstr ""
 
-#: config/tc-bfin.c:263
+#: config/tc-bfin.c:338
 #, c-format
 msgid " BFIN specific command line options:\n"
 msgstr ""
 
-#: config/tc-bfin.c:646 config/tc-fr30.c:358 config/tc-frv.c:1600
-#: config/tc-i960.c:1756 config/tc-ip2k.c:371 config/tc-m32c.c:912
-#: config/tc-m32r.c:2143 config/tc-openrisc.c:376 config/tc-xstormy16.c:631
+#: config/tc-bfin.c:728 config/tc-fr30.c:357 config/tc-frv.c:1599
+#: config/tc-i960.c:1754 config/tc-ip2k.c:370 config/tc-m32c.c:1236
+#: config/tc-m32r.c:2142 config/tc-mep.c:1713 config/tc-openrisc.c:375
+#: config/tc-xc16x.c:258 config/tc-xstormy16.c:631
 msgid "Bad call to md_atof()"
 msgstr ""
 
-#: config/tc-cris.c:532 config/tc-m68hc11.c:2794
+#: config/tc-cr16.c:159 read.c:4266
+msgid "using a bit field width of zero"
+msgstr ""
+
+#: config/tc-cr16.c:167 read.c:4274
+#, c-format
+msgid "field width \"%s\" too complex for a bitfield"
+msgstr ""
+
+#: config/tc-cr16.c:176 read.c:4282
+#, c-format
+msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
+msgstr ""
+
+#: config/tc-cr16.c:198 read.c:4304
+#, c-format
+msgid "field value \"%s\" too complex for a bitfield"
+msgstr ""
+
+#: config/tc-cr16.c:379
+#, c-format
+msgid "Unknown register pair - index relative mode: `%d'"
+msgstr ""
+
+#: config/tc-cr16.c:558 config/tc-crx.c:344 config/tc-mn10200.c:800
+#: write.c:959
+#, c-format
+msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
+msgstr ""
+
+#: config/tc-cr16.c:574 config/tc-crx.c:360
+#, c-format
+msgid "internal error: reloc %d (`%s') not supported by object file format"
+msgstr ""
+
+#: config/tc-cr16.c:762 config/tc-cr16.c:785 config/tc-cris.c:1181
+#: config/tc-crx.c:582 config/tc-crx.c:609 config/tc-crx.c:627
+msgid "Virtual memory exhausted"
+msgstr ""
+
+#: config/tc-cr16.c:770 config/tc-crx.c:619 config/tc-crx.c:637
+#: config/tc-i386.c:1230 config/tc-i386.c:1252 config/tc-m68k.c:4387
+#, c-format
+msgid "Internal Error:  Can't hash %s: %s"
+msgstr ""
+
+#: config/tc-cr16.c:796 config/tc-cris.c:1215 config/tc-crx.c:592
+#, c-format
+msgid "Can't hash `%s': %s\n"
+msgstr ""
+
+#: config/tc-cr16.c:797 config/tc-cris.c:1216 config/tc-crx.c:593
+msgid "(unknown reason)"
+msgstr ""
+
+#. Missing or bad expr becomes absolute 0.
+#: config/tc-cr16.c:847 config/tc-crx.c:665 config/tc-i386.c:4865
+#, c-format
+msgid "missing or invalid displacement expression `%s' taken as 0"
+msgstr ""
+
+#: config/tc-cr16.c:959
+#, c-format
+msgid "operand %d: illegal use expression: `%s`"
+msgstr ""
+
+#: config/tc-cr16.c:1016 config/tc-crx.c:1173
+#, c-format
+msgid "Unknown register: `%d'"
+msgstr ""
+
+#. Issue a error message when register is illegal.
+#: config/tc-cr16.c:1024 config/tc-crx.c:1181
+#, c-format
+msgid "Illegal register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1095 config/tc-cr16.c:1170 config/tc-crx.c:803
+#: config/tc-crx.c:823 config/tc-crx.c:838
+#, c-format
+msgid "Illegal register `%s' in Instruction `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1123 config/tc-cr16.c:1134
+#, c-format
+msgid "Illegal register pair `%s' in Instruction `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1159 config/tc-i960.c:835
+msgid "unmatched '['"
+msgstr ""
+
+#: config/tc-cr16.c:1165 config/tc-i960.c:842
+msgid "garbage after index spec ignored"
+msgstr ""
+
+#: config/tc-cr16.c:1313 config/tc-crx.c:982
+#, c-format
+msgid "Illegal operands (whitespace): `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1325 config/tc-cr16.c:1332 config/tc-cr16.c:1349
+#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
+#: config/tc-crx.c:1810
+#, c-format
+msgid "Missing matching brackets : `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1381 config/tc-crx.c:1044
+#, c-format
+msgid "Unknown exception: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1468 config/tc-crx.c:1140
+#, c-format
+msgid "Illegal `cinv' parameter: `%c'"
+msgstr ""
+
+#: config/tc-cr16.c:1490 config/tc-cr16.c:1529
+#, c-format
+msgid "Unknown register pair: `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1498
+#, c-format
+msgid "Illegal register pair (`%s') in Instruction: `%s'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1537
+#, c-format
+msgid "Illegal index register pair (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1576
+#, c-format
+msgid "Unknown processor register : `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1584
+#, c-format
+msgid "Illegal processor register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:1632
+#, c-format
+msgid "Unknown processor register (32 bit) : `%d'"
+msgstr ""
+
+#. Issue a error message when register  pair is illegal.
+#: config/tc-cr16.c:1640
+#, c-format
+msgid "Illegal 32 bit - processor register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-cr16.c:2004 config/tc-crx.c:1708 config/tc-crx.c:1725
+#, c-format
+msgid "Same src/dest register is used (`r%d'), result is undefined"
+msgstr ""
+
+#: config/tc-cr16.c:2025
+msgid "RA register is saved twice."
+msgstr ""
+
+#: config/tc-cr16.c:2029
+#, c-format
+msgid "`%s' Illegal use of registers."
+msgstr ""
+
+#: config/tc-cr16.c:2043
+#, c-format
+msgid "`%s' Illegal count-register combination."
+msgstr ""
+
+#: config/tc-cr16.c:2049
+#, c-format
+msgid "`%s' Illegal use of register."
+msgstr ""
+
+#: config/tc-cr16.c:2058 config/tc-crx.c:1717
+#, c-format
+msgid "`%s' has undefined result"
+msgstr ""
+
+#: config/tc-cr16.c:2066
+#, c-format
+msgid "Same src/dest register is used (`r%d'),result is undefined"
+msgstr ""
+
+#: config/tc-cr16.c:2237 config/tc-crx.c:1622
+msgid "Incorrect number of operands"
+msgstr ""
+
+#: config/tc-cr16.c:2239 config/tc-crx.c:1624
+#, c-format
+msgid "Illegal type of operand (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2245 config/tc-crx.c:1630
+#, c-format
+msgid "Operand out of range (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2248 config/tc-crx.c:1633
+#, c-format
+msgid "Operand has odd displacement (arg %d)"
+msgstr ""
+
+#: config/tc-cr16.c:2251 config/tc-cr16.c:2282 config/tc-crx.c:1646
+#: config/tc-crx.c:1677
+#, c-format
+msgid "Illegal operand (arg %d)"
+msgstr ""
+
+#. Give an error if a frag containing code is not aligned to a 2-byte
+#. boundary.
+#: config/tc-cr16.c:2351 config/tc-cr16.h:71 config/tc-crx.c:1999
+#: config/tc-crx.h:76
+msgid "instruction address is not a multiple of 2"
+msgstr ""
+
+#: config/tc-cr16.c:2428 config/tc-cris.c:1529 config/tc-cris.c:1537
+#: config/tc-crx.c:2035 config/tc-dlx.c:685 config/tc-hppa.c:3261
+#: config/tc-i860.c:490 config/tc-i860.c:507 config/tc-i860.c:987
+#: config/tc-sparc.c:1431 config/tc-sparc.c:1439
+#, c-format
+msgid "Unknown opcode: `%s'"
+msgstr ""
+
+#: config/tc-cris.c:547 config/tc-m68hc11.c:2796
 #, c-format
 msgid "internal inconsistency problem in %s: fr_symbol %lx"
 msgstr ""
 
-#: config/tc-cris.c:536 config/tc-m68hc11.c:2798 config/tc-msp430.c:2289
+#: config/tc-cris.c:551 config/tc-m68hc11.c:2800 config/tc-msp430.c:2286
 #, c-format
 msgid "internal inconsistency problem in %s: resolved symbol"
 msgstr ""
 
-#: config/tc-cris.c:546 config/tc-m68hc11.c:2804
+#: config/tc-cris.c:561 config/tc-m68hc11.c:2806
 #, c-format
 msgid "internal inconsistency problem in %s: fr_subtype %d"
 msgstr ""
 
-#: config/tc-cris.c:872
+#: config/tc-cris.c:901
 msgid "Relaxation to long branches for .arch common_v10_v32 not implemented"
 msgstr ""
 
-#: config/tc-cris.c:902
+#: config/tc-cris.c:931
 msgid "Complicated LAPC target operand is not a multiple of two.  Use LAPC.D"
 msgstr ""
 
-#: config/tc-cris.c:907
+#: config/tc-cris.c:936
 #, c-format
 msgid ""
 "Internal error found in md_convert_frag: offset %ld.  Please report this."
 msgstr ""
 
-#: config/tc-cris.c:932
+#: config/tc-cris.c:961
 #, c-format
 msgid "internal inconsistency in %s: bdapq no symbol"
 msgstr ""
 
-#: config/tc-cris.c:945
+#: config/tc-cris.c:974
 #, c-format
 msgid "internal inconsistency in %s: bdap.w with no symbol"
 msgstr ""
 
-#: config/tc-cris.c:969
+#: config/tc-cris.c:998
 msgid "section alignment must be >= 4 bytes to check MULS/MULU safeness"
 msgstr ""
 
-#: config/tc-cris.c:978
+#: config/tc-cris.c:1007
 msgid "dangerous MULS/MULU location; give it higher alignment"
 msgstr ""
 
-#: config/tc-cris.c:1083
+#: config/tc-cris.c:1112
 msgid ""
 "Out-of-range .word offset handling is not implemented for .arch "
 "common_v10_v32"
 msgstr ""
 
-#: config/tc-cris.c:1148 config/tc-crx.c:582 config/tc-crx.c:609
-#: config/tc-crx.c:627
-msgid "Virtual memory exhausted"
-msgstr ""
-
-#: config/tc-cris.c:1182 config/tc-crx.c:592
-#, c-format
-msgid "Can't hash `%s': %s\n"
-msgstr ""
-
-#: config/tc-cris.c:1183 config/tc-crx.c:593
-msgid "(unknown reason)"
-msgstr ""
-
-#: config/tc-cris.c:1187
+#: config/tc-cris.c:1220
 #, c-format
 msgid "Buggy opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-cris.c:1493 config/tc-cris.c:1501 config/tc-crx.c:2029
-#: config/tc-dlx.c:685 config/tc-hppa.c:1625 config/tc-i860.c:492
-#: config/tc-i860.c:509 config/tc-i860.c:989 config/tc-sparc.c:1417
-#: config/tc-sparc.c:1425
-#, c-format
-msgid "Unknown opcode: `%s'"
-msgstr ""
-
-#: config/tc-cris.c:1599
+#: config/tc-cris.c:1635
 #, c-format
 msgid "Immediate value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1615
+#: config/tc-cris.c:1651
 #, c-format
 msgid "Immediate value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1667
+#: config/tc-cris.c:1703
 #, c-format
 msgid "Immediate value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1682
+#: config/tc-cris.c:1718
 #, c-format
 msgid "Immediate value not in 6 bit unsigned range: %ld"
 msgstr ""
 
 #. Others have a generic warning.
-#: config/tc-cris.c:1790
+#: config/tc-cris.c:1826
 #, c-format
 msgid "Unimplemented register `%s' specified"
 msgstr ""
 
 #. We've come to the end of instructions with this
 #. opcode, so it must be an error.
-#: config/tc-cris.c:2033
+#: config/tc-cris.c:2069
 msgid "Illegal operands"
 msgstr ""
 
-#: config/tc-cris.c:2074 config/tc-cris.c:2114
+#: config/tc-cris.c:2110 config/tc-cris.c:2150
 #, c-format
 msgid "Immediate value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2084 config/tc-cris.c:2135
+#: config/tc-cris.c:2120 config/tc-cris.c:2171
 #, c-format
 msgid "Immediate value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2119
+#: config/tc-cris.c:2155
 #, c-format
 msgid "Immediate value not in 8 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2124
+#: config/tc-cris.c:2160
 #, c-format
 msgid "Immediate value not in 8 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2140
+#: config/tc-cris.c:2176
 #, c-format
 msgid "Immediate value not in 16 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2145
+#: config/tc-cris.c:2181
 #, c-format
 msgid "Immediate value not in 16 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2167
+#: config/tc-cris.c:2203
 msgid "PIC relocation size does not match operand size"
 msgstr ""
 
-#: config/tc-cris.c:3304
+#: config/tc-cris.c:3346
 msgid "Calling gen_cond_branch_32 for .arch common_v10_v32\n"
 msgstr ""
 
-#: config/tc-cris.c:3308
+#: config/tc-cris.c:3350
 msgid "32-bit conditional branch generated"
 msgstr ""
 
-#: config/tc-cris.c:3367
+#: config/tc-cris.c:3411
 msgid "Complex expression not supported"
 msgstr ""
 
 #. FIXME:  Is this function mentioned in the internals.texi manual?  If
 #. not, add it.
-#: config/tc-cris.c:3490
+#: config/tc-cris.c:3537
 msgid "Bad call to md_atof () - floating point formats are not supported"
 msgstr ""
 
-#: config/tc-cris.c:3531
+#: config/tc-cris.c:3578
 msgid "PC-relative relocation must be trivially resolved"
 msgstr ""
 
-#: config/tc-cris.c:3584
+#: config/tc-cris.c:3631
 #, c-format
 msgid "Value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3595
+#: config/tc-cris.c:3642
 #, c-format
 msgid "Value not in 16 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3606
+#: config/tc-cris.c:3653
 #, c-format
 msgid "Value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3614
+#: config/tc-cris.c:3661
 #, c-format
 msgid "Value not in 8 bit signed range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3625
+#: config/tc-cris.c:3672
 #, c-format
 msgid "Value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3633
+#: config/tc-cris.c:3680
 #, c-format
 msgid "Value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3641
+#: config/tc-cris.c:3688
 #, c-format
 msgid "Value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3649
+#: config/tc-cris.c:3696
 #, c-format
 msgid "Value not in 6 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:3695
+#: config/tc-cris.c:3742
 #, c-format
 msgid "Please use --help to see usage and options for this assembler.\n"
 msgstr ""
 
-#: config/tc-cris.c:3707
+#: config/tc-cris.c:3754
 msgid "--no-underscore is invalid with a.out format"
 msgstr ""
 
-#: config/tc-cris.c:3727
+#: config/tc-cris.c:3778
 #, c-format
 msgid "invalid <arch> in --march=<arch>: %s"
 msgstr ""
 
-#: config/tc-cris.c:3821
+#: config/tc-cris.c:3877
 msgid ""
 "Semantics error.  This type of operand can not be relocated, it must be an "
 "assembly-time constant"
 msgstr ""
 
-#: config/tc-cris.c:3870
+#: config/tc-cris.c:3926
 #, c-format
 msgid "Cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
 #. The messages are formatted to line up with the generic options.
-#: config/tc-cris.c:3883
+#: config/tc-cris.c:3939
 #, c-format
 msgid "CRIS-specific options:\n"
 msgstr ""
 
-#: config/tc-cris.c:3885
+#: config/tc-cris.c:3941
 msgid ""
 "  -h, -H                  Don't execute, print this help text.  Deprecated.\n"
 msgstr ""
 
-#: config/tc-cris.c:3887
+#: config/tc-cris.c:3943
 msgid "  -N                      Warn when branches are expanded to jumps.\n"
 msgstr ""
 
-#: config/tc-cris.c:3889
+#: config/tc-cris.c:3945
 msgid ""
 "  --underscore            User symbols are normally prepended with "
 "underscore.\n"
 msgstr ""
 
-#: config/tc-cris.c:3891
+#: config/tc-cris.c:3947
 msgid "                          Registers will not need any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3893
+#: config/tc-cris.c:3949
 msgid "  --no-underscore         User symbols do not have any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3895
+#: config/tc-cris.c:3951
 msgid "                          Registers will require a `$'-prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3897
+#: config/tc-cris.c:3953
 msgid "  --pic\t\t\tEnable generation of position-independent code.\n"
 msgstr ""
 
-#: config/tc-cris.c:3899
+#: config/tc-cris.c:3955
 msgid ""
 "  --march=<arch>\t\tGenerate code for <arch>.  Valid choices for <arch>\n"
 "\t\t\t\tare v0_v10, v10, v32 and common_v10_v32.\n"
 msgstr ""
 
-#: config/tc-cris.c:3920
+#: config/tc-cris.c:3976
 msgid "Invalid relocation"
 msgstr ""
 
-#: config/tc-cris.c:3957
+#: config/tc-cris.c:4013
 msgid "Invalid pc-relative relocation"
 msgstr ""
 
-#: config/tc-cris.c:4002
+#: config/tc-cris.c:4058
 #, c-format
 msgid "Adjusted signed .word (%ld) overflows: `switch'-statement too large."
 msgstr ""
 
-#: config/tc-cris.c:4032
+#: config/tc-cris.c:4088
 #, c-format
 msgid ".syntax %s requires command-line option `--underscore'"
 msgstr ""
 
-#: config/tc-cris.c:4041
+#: config/tc-cris.c:4097
 #, c-format
 msgid ".syntax %s requires command-line option `--no-underscore'"
 msgstr ""
 
-#: config/tc-cris.c:4078
+#: config/tc-cris.c:4134
 msgid "Unknown .syntax operand"
 msgstr ""
 
-#: config/tc-cris.c:4088
+#: config/tc-cris.c:4144
 msgid "Pseudodirective .file is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-cris.c:4100
+#: config/tc-cris.c:4156
 msgid "Pseudodirective .loc is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-cris.c:4243
+#: config/tc-cris.c:4299
 msgid "unknown operand to .arch"
 msgstr ""
 
-#: config/tc-cris.c:4252
+#: config/tc-cris.c:4308
 msgid ".arch <arch> requires a matching --march=... option"
 msgstr ""
 
-#: config/tc-crx.c:344 config/tc-mn10200.c:801 write.c:2209
-#, c-format
-msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
-msgstr ""
-
-#: config/tc-crx.c:360
-#, c-format
-msgid "internal error: reloc %d (`%s') not supported by object file format"
-msgstr ""
-
-#: config/tc-crx.c:619 config/tc-crx.c:637 config/tc-i386.c:953
-#: config/tc-i386.c:976 config/tc-m68k.c:4149
-#, c-format
-msgid "Internal Error:  Can't hash %s: %s"
-msgstr ""
-
-#. Missing or bad expr becomes absolute 0.
-#: config/tc-crx.c:665 config/tc-i386.c:4259
-#, c-format
-msgid "missing or invalid displacement expression `%s' taken as 0"
-msgstr ""
-
-#: config/tc-crx.c:803 config/tc-crx.c:823 config/tc-crx.c:838
-#, c-format
-msgid "Illegal register `%s' in Instruction `%s'"
-msgstr ""
-
 #: config/tc-crx.c:866
 #, c-format
 msgid "Illegal Scale - `%d'"
 msgstr ""
 
-#: config/tc-crx.c:982
-#, c-format
-msgid "Illegal operands (whitespace): `%s'"
-msgstr ""
-
-#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
-#: config/tc-crx.c:1804
-#, c-format
-msgid "Missing matching brackets : `%s'"
-msgstr ""
-
-#: config/tc-crx.c:1044
-#, c-format
-msgid "Unknown exception: `%s'"
-msgstr ""
-
-#: config/tc-crx.c:1140
-#, c-format
-msgid "Illegal `cinv' parameter: `%c'"
-msgstr ""
-
-#: config/tc-crx.c:1173
-#, c-format
-msgid "Unknown register: `%d'"
-msgstr ""
-
-#. Issue a error message when register is illegal.
-#: config/tc-crx.c:1181
-#, c-format
-msgid "Illegal register (`%s') in Instruction: `%s'"
-msgstr ""
-
 #: config/tc-crx.c:1310
 #, c-format
 msgid "Illegal Co-processor register in Instruction `%s' "
@@ -3267,110 +3768,70 @@ msgstr ""
 msgid "Illegal Co-processor special register in Instruction `%s' "
 msgstr ""
 
-#: config/tc-crx.c:1616
-msgid "Incorrect number of operands"
-msgstr ""
-
-#: config/tc-crx.c:1618
-#, c-format
-msgid "Illegal type of operand (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1624
-#, c-format
-msgid "Operand out of range (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1627
-#, c-format
-msgid "Operand has odd displacement (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1630
+#: config/tc-crx.c:1636
 #, c-format
 msgid "Invalid DISPU4 operand value (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1633
+#: config/tc-crx.c:1639
 #, c-format
 msgid "Invalid CST4 operand value (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1636
+#: config/tc-crx.c:1642
 #, c-format
 msgid "Operand value is not within upper 64 KB (arg %d)"
 msgstr ""
 
-#: config/tc-crx.c:1640 config/tc-crx.c:1671
-#, c-format
-msgid "Illegal operand (arg %d)"
-msgstr ""
-
-#: config/tc-crx.c:1702 config/tc-crx.c:1719
-#, c-format
-msgid "Same src/dest register is used (`r%d'), result is undefined"
-msgstr ""
-
-#: config/tc-crx.c:1711
-#, c-format
-msgid "`%s' has undefined result"
-msgstr ""
-
-#: config/tc-crx.c:1773
+#: config/tc-crx.c:1779
 msgid "Invalid Register in Register List"
 msgstr ""
 
-#: config/tc-crx.c:1827
+#: config/tc-crx.c:1833
 #, c-format
 msgid "Illegal register `%s' in cop-register list"
 msgstr ""
 
-#: config/tc-crx.c:1835
+#: config/tc-crx.c:1841
 #, c-format
 msgid "Illegal register `%s' in cop-special-register list"
 msgstr ""
 
-#: config/tc-crx.c:1854
+#: config/tc-crx.c:1860
 #, c-format
 msgid "Illegal register `%s' in user register list"
 msgstr ""
 
-#: config/tc-crx.c:1873
+#: config/tc-crx.c:1879
 #, c-format
 msgid "Illegal register `%s' in register list"
 msgstr ""
 
-#: config/tc-crx.c:1879
+#: config/tc-crx.c:1885
 #, c-format
 msgid "Maximum %d bits may be set in `mask16' operand"
 msgstr ""
 
-#: config/tc-crx.c:1888
+#: config/tc-crx.c:1894
 #, c-format
 msgid "rest of line ignored; first ignored character is `%c'"
 msgstr ""
 
-#: config/tc-crx.c:1896
+#: config/tc-crx.c:1902
 #, c-format
 msgid "Illegal `mask16' operand, operation is undefined - `%s'"
 msgstr ""
 
 #. HI can't be specified without LO (and vise-versa).
-#: config/tc-crx.c:1902
+#: config/tc-crx.c:1908
 msgid "HI/LO registers should be specified together"
 msgstr ""
 
-#: config/tc-crx.c:1908
+#: config/tc-crx.c:1914
 msgid "HI/LO registers should be specified without additional registers"
 msgstr ""
 
-#. Give an error if a frag containing code is not aligned to a 2-byte
-#. boundary.
-#: config/tc-crx.c:1993 config/tc-crx.h:76
-msgid "instruction address is not a multiple of 2"
-msgstr ""
-
-#: config/tc-d10v.c:217
+#: config/tc-d10v.c:216
 #, c-format
 msgid ""
 "D10V options:\n"
@@ -3381,140 +3842,144 @@ msgid ""
 "                        instructions together.\n"
 msgstr ""
 
-#: config/tc-d10v.c:496 config/tc-d30v.c:488 config/tc-mn10200.c:1075
-#: config/tc-mn10300.c:1817 config/tc-ppc.c:2380 config/tc-s390.c:1218
-#: config/tc-v850.c:1949
+#: config/tc-d10v.c:495 config/tc-d30v.c:487 config/tc-mn10200.c:1074
+#: config/tc-mn10300.c:1816 config/tc-ppc.c:2434 config/tc-s390.c:1219
+#: config/tc-v850.c:1964 config/tc-z80.c:422
 msgid "illegal operand"
 msgstr ""
 
-#: config/tc-d10v.c:608
+#: config/tc-d10v.c:607
 msgid "operand is not an immediate"
 msgstr ""
 
-#: config/tc-d10v.c:626
+#: config/tc-d10v.c:625
 #, c-format
 msgid "operand out of range: %lu"
 msgstr ""
 
-#: config/tc-d10v.c:684
+#: config/tc-d10v.c:683
 msgid "Instruction must be executed in parallel with another instruction."
 msgstr ""
 
-#: config/tc-d10v.c:738 config/tc-d10v.c:746
+#: config/tc-d10v.c:737 config/tc-d10v.c:745
 #, c-format
 msgid "packing conflict: %s must dispatch sequentially"
 msgstr ""
 
-#: config/tc-d10v.c:845
+#: config/tc-d10v.c:844
 #, c-format
 msgid "resource conflict (R%d)"
 msgstr ""
 
-#: config/tc-d10v.c:848
+#: config/tc-d10v.c:847
 #, c-format
 msgid "resource conflict (A%d)"
 msgstr ""
 
-#: config/tc-d10v.c:850
+#: config/tc-d10v.c:849
 msgid "resource conflict (PSW)"
 msgstr ""
 
-#: config/tc-d10v.c:852
+#: config/tc-d10v.c:851
 msgid "resource conflict (C flag)"
 msgstr ""
 
-#: config/tc-d10v.c:854
+#: config/tc-d10v.c:853
 msgid "resource conflict (F flag)"
 msgstr ""
 
-#: config/tc-d10v.c:1004
+#: config/tc-d10v.c:1003
 msgid "Instruction must be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1007
+#: config/tc-d10v.c:1006
 msgid "Long instructions may not be combined."
 msgstr ""
 
-#: config/tc-d10v.c:1040
+#: config/tc-d10v.c:1039
 msgid "One of these instructions may not be executed in parallel."
 msgstr ""
 
-#: config/tc-d10v.c:1044 config/tc-d30v.c:1071
+#: config/tc-d10v.c:1043 config/tc-d30v.c:1070
 msgid "Two IU instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1046 config/tc-d10v.c:1054 config/tc-d10v.c:1068
-#: config/tc-d10v.c:1083 config/tc-d30v.c:1072 config/tc-d30v.c:1081
+#: config/tc-d10v.c:1045 config/tc-d10v.c:1053 config/tc-d10v.c:1067
+#: config/tc-d10v.c:1082 config/tc-d30v.c:1071 config/tc-d30v.c:1080
 msgid "Swapping instruction order"
 msgstr ""
 
-#: config/tc-d10v.c:1052 config/tc-d30v.c:1078
+#: config/tc-d10v.c:1051 config/tc-d30v.c:1077
 msgid "Two MU instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1072 config/tc-d30v.c:1098
+#: config/tc-d10v.c:1071 config/tc-d30v.c:1097
 msgid "IU instruction may not be in the left container"
 msgstr ""
 
-#: config/tc-d10v.c:1074 config/tc-d10v.c:1089
+#: config/tc-d10v.c:1073 config/tc-d10v.c:1088
 msgid ""
 "Instruction in R container is squashed by flow control instruction in L "
 "container."
 msgstr ""
 
-#: config/tc-d10v.c:1087 config/tc-d30v.c:1109
+#: config/tc-d10v.c:1086 config/tc-d30v.c:1108
 msgid "MU instruction may not be in the right container"
 msgstr ""
 
-#: config/tc-d10v.c:1093 config/tc-d30v.c:1121
+#: config/tc-d10v.c:1092 config/tc-d30v.c:1120
 msgid "unknown execution type passed to write_2_short()"
 msgstr ""
 
-#: config/tc-d10v.c:1221 config/tc-d10v.c:1394
+#: config/tc-d10v.c:1220 config/tc-d10v.c:1393
 msgid "bad opcode or operands"
 msgstr ""
 
-#: config/tc-d10v.c:1296 config/tc-m68k.c:4625
+#: config/tc-d10v.c:1295
 msgid "value out of range"
 msgstr ""
 
-#: config/tc-d10v.c:1370
+#: config/tc-d10v.c:1369
 msgid "illegal operand - register name found where none expected"
 msgstr ""
 
-#: config/tc-d10v.c:1405
+#: config/tc-d10v.c:1404
 msgid "Register number must be EVEN"
 msgstr ""
 
-#: config/tc-d10v.c:1408
+#: config/tc-d10v.c:1407
 msgid "Unsupported use of sp"
 msgstr ""
 
-#: config/tc-d10v.c:1427
+#: config/tc-d10v.c:1426
 #, c-format
 msgid "cr%ld is a reserved control register"
 msgstr ""
 
-#: config/tc-d10v.c:1466 config/tc-d30v.c:1430
+#: config/tc-d10v.c:1599
 #, c-format
-msgid "unknown opcode: %s"
+msgid "line %d: rep or repi must include at least 4 instructions"
+msgstr ""
+
+#: config/tc-d10v.c:1779
+msgid "can't find previous opcode "
 msgstr ""
 
-#: config/tc-d10v.c:1602
+#: config/tc-d10v.c:1791
 #, c-format
-msgid "line %d: rep or repi must include at least 4 instructions"
+msgid "could not assemble: %s"
 msgstr ""
 
-#: config/tc-d10v.c:1810 config/tc-d10v.c:1832 config/tc-d30v.c:1777
+#: config/tc-d10v.c:1806 config/tc-d10v.c:1828 config/tc-d30v.c:1776
 msgid "Unable to mix instructions as specified"
 msgstr ""
 
-#: config/tc-d30v.c:150
+#: config/tc-d30v.c:149
 #, c-format
 msgid "Register name %s conflicts with symbol of the same name"
 msgstr ""
 
-#: config/tc-d30v.c:240
+#: config/tc-d30v.c:239
 #, c-format
 msgid ""
 "\n"
@@ -3528,126 +3993,131 @@ msgid ""
 "-C                      Opposite of -C.  -c is the default.\n"
 msgstr ""
 
-#: config/tc-d30v.c:402
+#: config/tc-d30v.c:401
 msgid "unexpected 12-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:409
+#: config/tc-d30v.c:408
 msgid "unexpected 18-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:659
+#: config/tc-d30v.c:658
 #, c-format
 msgid "%s NOP inserted"
 msgstr ""
 
-#: config/tc-d30v.c:660
+#: config/tc-d30v.c:659
 msgid "sequential"
 msgstr ""
 
-#: config/tc-d30v.c:660
+#: config/tc-d30v.c:659
 msgid "parallel"
 msgstr ""
 
-#: config/tc-d30v.c:1067
+#: config/tc-d30v.c:1066
 msgid "Instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d30v.c:1080
+#: config/tc-d30v.c:1079
 #, c-format
 msgid "Executing %s in IU may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1087
+#: config/tc-d30v.c:1086
 #, c-format
 msgid "Executing %s in IU may not work in parallel execution"
 msgstr ""
 
-#: config/tc-d30v.c:1100
+#: config/tc-d30v.c:1099
 #, c-format
 msgid "special left instruction `%s' kills instruction `%s' in right container"
 msgstr ""
 
-#: config/tc-d30v.c:1111
+#: config/tc-d30v.c:1110
 #, c-format
 msgid "Executing %s in reverse serial with %s may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1114
+#: config/tc-d30v.c:1113
 #, c-format
 msgid "Executing %s in IU in reverse serial may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1303
+#: config/tc-d30v.c:1302
 msgid "Odd numbered register used as target of multi-register instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1367 config/tc-d30v.c:1402
+#: config/tc-d30v.c:1366 config/tc-d30v.c:1401
 #, c-format
 msgid "unknown condition code: %s"
 msgstr ""
 
-#: config/tc-d30v.c:1395
+#: config/tc-d30v.c:1394
 #, c-format
 msgid "cmpu doesn't support condition code %s"
 msgstr ""
 
-#: config/tc-d30v.c:1441
+#: config/tc-d30v.c:1429
+#, c-format
+msgid "unknown opcode: %s"
+msgstr ""
+
+#: config/tc-d30v.c:1440
 #, c-format
 msgid "operands for opcode `%s' do not match any valid format"
 msgstr ""
 
-#: config/tc-d30v.c:1656 config/tc-d30v.c:1673
+#: config/tc-d30v.c:1655 config/tc-d30v.c:1672
 msgid "Cannot assemble instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1658
+#: config/tc-d30v.c:1657
 msgid "First opcode is long.  Unable to mix instructions as specified."
 msgstr ""
 
-#: config/tc-d30v.c:1727
+#: config/tc-d30v.c:1726
 msgid "word of NOPs added between word multiply and load"
 msgstr ""
 
-#: config/tc-d30v.c:1729
+#: config/tc-d30v.c:1728
 msgid "word of NOPs added between word multiply and 16-bit multiply"
 msgstr ""
 
-#: config/tc-d30v.c:1761
+#: config/tc-d30v.c:1760
 msgid "Instruction uses long version, so it cannot be mixed as specified"
 msgstr ""
 
-#: config/tc-d30v.c:1888
+#: config/tc-d30v.c:1887
 #, c-format
 msgid "value too large to fit in %d bits"
 msgstr ""
 
-#: config/tc-d30v.c:1949
+#: config/tc-d30v.c:1948
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1952
+#: config/tc-d30v.c:1951
 #, c-format
 msgid "line %d: unable to place value %lx into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1960
+#: config/tc-d30v.c:1959
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1963
+#: config/tc-d30v.c:1962
 #, c-format
 msgid "line %d: unable to place value %lx into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1971
+#: config/tc-d30v.c:1970
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a quad"
 msgstr ""
 
-#: config/tc-d30v.c:2079
+#: config/tc-d30v.c:2078
 #, c-format
 msgid "Alignment too large: %d assumed"
 msgstr ""
@@ -3661,8 +4131,8 @@ msgid ".endfunc missing for previous .proc"
 msgstr ""
 
 #. Probably a memory allocation problem?  Give up now.
-#: config/tc-dlx.c:297 config/tc-hppa.c:1489 config/tc-mips.c:1415
-#: config/tc-mips.c:1467 config/tc-or32.c:210 config/tc-sparc.c:855
+#: config/tc-dlx.c:297 config/tc-hppa.c:8306 config/tc-mips.c:1764
+#: config/tc-mips.c:1816 config/tc-or32.c:211 config/tc-sparc.c:869
 msgid "Broken assembler.  No assembly attempted."
 msgstr ""
 
@@ -3681,7 +4151,7 @@ msgstr ""
 msgid "Expression Error for operand modifier %%hi/%%lo\n"
 msgstr ""
 
-#: config/tc-dlx.c:634 config/tc-or32.c:873
+#: config/tc-dlx.c:634 config/tc-or32.c:871
 #, c-format
 msgid "Invalid expression after %%%%\n"
 msgstr ""
@@ -3718,7 +4188,7 @@ msgstr ""
 msgid "failed general register sanity check."
 msgstr ""
 
-#: config/tc-dlx.c:1175 config/tc-or32.c:835
+#: config/tc-dlx.c:1175 config/tc-or32.c:833
 #, c-format
 msgid "label \"$%d\" redefined"
 msgstr ""
@@ -3727,314 +4197,315 @@ msgstr ""
 msgid "Invalid expression after # number\n"
 msgstr ""
 
-#: config/tc-fr30.c:83
+#: config/tc-fr30.c:82
 #, c-format
 msgid " FR30 specific command line options:\n"
 msgstr ""
 
-#: config/tc-fr30.c:136
+#: config/tc-fr30.c:135
 #, c-format
 msgid "Instruction %s not allowed in a delay slot."
 msgstr ""
 
-#: config/tc-frv.c:461
+#: config/tc-frv.c:460
 #, c-format
 msgid "FRV specific command line options:\n"
 msgstr ""
 
-#: config/tc-frv.c:462
+#: config/tc-frv.c:461
 #, c-format
 msgid "-G n         Data >= n bytes is in small data area\n"
 msgstr ""
 
-#: config/tc-frv.c:463
+#: config/tc-frv.c:462
 #, c-format
 msgid "-mgpr-32     Note 32 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:464
+#: config/tc-frv.c:463
 #, c-format
 msgid "-mgpr-64     Note 64 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:465
+#: config/tc-frv.c:464
 #, c-format
 msgid "-mfpr-32     Note 32 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:466
+#: config/tc-frv.c:465
 #, c-format
 msgid "-mfpr-64     Note 64 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:467
+#: config/tc-frv.c:466
 #, c-format
 msgid "-msoft-float Note software fp is used\n"
 msgstr ""
 
-#: config/tc-frv.c:468
+#: config/tc-frv.c:467
 #, c-format
 msgid "-mdword      Note stack is aligned to a 8 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:469
+#: config/tc-frv.c:468
 #, c-format
 msgid "-mno-dword   Note stack is aligned to a 4 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:470
+#: config/tc-frv.c:469
 #, c-format
 msgid "-mdouble     Note fp double insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:471
+#: config/tc-frv.c:470
 #, c-format
 msgid "-mmedia      Note media insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:472
+#: config/tc-frv.c:471
 #, c-format
 msgid "-mmuladd     Note multiply add/subtract insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:473
+#: config/tc-frv.c:472
 #, c-format
 msgid "-mpack       Note instructions are packed\n"
 msgstr ""
 
-#: config/tc-frv.c:474
+#: config/tc-frv.c:473
 #, c-format
 msgid "-mno-pack    Do not allow instructions to be packed\n"
 msgstr ""
 
-#: config/tc-frv.c:475
+#: config/tc-frv.c:474
 #, c-format
 msgid "-mpic        Note small position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:476
+#: config/tc-frv.c:475
 #, c-format
 msgid "-mPIC        Note large position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:477
+#: config/tc-frv.c:476
 #, c-format
 msgid "-mlibrary-pic Compile library for large position indepedent code\n"
 msgstr ""
 
-#: config/tc-frv.c:478
+#: config/tc-frv.c:477
 #, c-format
 msgid "-mfdpic      Assemble for the FDPIC ABI\n"
 msgstr ""
 
-#: config/tc-frv.c:479
+#: config/tc-frv.c:478
 #, c-format
 msgid "-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"
 msgstr ""
 
-#: config/tc-frv.c:480
+#: config/tc-frv.c:479
 #, c-format
 msgid "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
 msgstr ""
 
-#: config/tc-frv.c:481
+#: config/tc-frv.c:480
 #, c-format
 msgid "             Record the cpu type\n"
 msgstr ""
 
-#: config/tc-frv.c:482
+#: config/tc-frv.c:481
 #, c-format
 msgid "-mtomcat-stats Print out stats for tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:483
+#: config/tc-frv.c:482
 #, c-format
 msgid "-mtomcat-debug Debug tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:1187
+#: config/tc-frv.c:1186
 msgid "VLIW packing used for -mno-pack"
 msgstr ""
 
-#: config/tc-frv.c:1197
+#: config/tc-frv.c:1196
 msgid "Instruction not supported by this architecture"
 msgstr ""
 
-#: config/tc-frv.c:1207
+#: config/tc-frv.c:1206
 msgid "VLIW packing constraint violation"
 msgstr ""
 
-#: config/tc-frv.c:1874
+#: config/tc-frv.c:1873
 #, c-format
 msgid "Relocation %s is not safe for %s"
 msgstr ""
 
-#: config/tc-h8300.c:78 config/tc-h8300.c:87 config/tc-h8300.c:97
-#: config/tc-h8300.c:107 config/tc-h8300.c:117 config/tc-h8300.c:128
-#: config/tc-h8300.c:195 config/tc-hppa.c:1449 config/tc-hppa.c:6926
-#: config/tc-hppa.c:6932 config/tc-hppa.c:6938 config/tc-hppa.c:6944
-#: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2725
+#: config/tc-h8300.c:76 config/tc-h8300.c:85 config/tc-h8300.c:95
+#: config/tc-h8300.c:105 config/tc-h8300.c:115 config/tc-h8300.c:126
+#: config/tc-h8300.c:193 config/tc-hppa.c:6839 config/tc-hppa.c:6845
+#: config/tc-hppa.c:6851 config/tc-hppa.c:6857 config/tc-hppa.c:8264
+#: config/tc-mn10300.c:1222 config/tc-mn10300.c:1227 config/tc-mn10300.c:2729
+#: config/tc-xc16x.c:79 config/tc-xc16x.c:86 config/tc-xc16x.c:93
 msgid "could not set architecture and machine"
 msgstr ""
 
-#: config/tc-h8300.c:397 config/tc-h8300.c:405
+#: config/tc-h8300.c:395 config/tc-h8300.c:403
 msgid "Reg not valid for H8/300"
 msgstr ""
 
-#: config/tc-h8300.c:486
+#: config/tc-h8300.c:484
 msgid "invalid operand size requested"
 msgstr ""
 
-#: config/tc-h8300.c:585
+#: config/tc-h8300.c:583
 msgid "Invalid register list for ldm/stm\n"
 msgstr ""
 
-#: config/tc-h8300.c:611 config/tc-h8300.c:616 config/tc-h8300.c:623
+#: config/tc-h8300.c:609 config/tc-h8300.c:614 config/tc-h8300.c:621
 msgid "mismatch between register and suffix"
 msgstr ""
 
-#: config/tc-h8300.c:650
+#: config/tc-h8300.c:648
 msgid "address too high for vector table jmp/jsr"
 msgstr ""
 
-#: config/tc-h8300.c:677 config/tc-h8300.c:789 config/tc-h8300.c:799
+#: config/tc-h8300.c:675 config/tc-h8300.c:787 config/tc-h8300.c:797
 msgid "Wrong size pointer register for architecture."
 msgstr ""
 
-#: config/tc-h8300.c:736 config/tc-h8300.c:744 config/tc-h8300.c:773
+#: config/tc-h8300.c:734 config/tc-h8300.c:742 config/tc-h8300.c:771
 msgid "expected @(exp, reg16)"
 msgstr ""
 
-#: config/tc-h8300.c:762
+#: config/tc-h8300.c:760
 msgid "expected .L, .W or .B for register in indexed addressing mode"
 msgstr ""
 
-#: config/tc-h8300.c:956
+#: config/tc-h8300.c:954
 msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""
 msgstr ""
 
-#: config/tc-h8300.c:974 config/tc-h8300.c:983
+#: config/tc-h8300.c:972 config/tc-h8300.c:981
 msgid "expected register"
 msgstr ""
 
-#: config/tc-h8300.c:999
+#: config/tc-h8300.c:997
 msgid "expected closing paren"
 msgstr ""
 
-#: config/tc-h8300.c:1058
+#: config/tc-h8300.c:1056
 #, c-format
 msgid "can't use high part of register in operand %d"
 msgstr ""
 
-#: config/tc-h8300.c:1215
+#: config/tc-h8300.c:1213
 #, c-format
 msgid "Opcode `%s' with these operand types not available in %s mode"
 msgstr ""
 
-#: config/tc-h8300.c:1224
+#: config/tc-h8300.c:1222
 msgid "mismatch between opcode size and operand size"
 msgstr ""
 
-#: config/tc-h8300.c:1260
+#: config/tc-h8300.c:1258
 #, c-format
 msgid "operand %s0x%lx out of range."
 msgstr ""
 
-#: config/tc-h8300.c:1356
+#: config/tc-h8300.c:1354
 msgid "Can't work out size of operand.\n"
 msgstr ""
 
-#: config/tc-h8300.c:1405
+#: config/tc-h8300.c:1403
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300 mode"
 msgstr ""
 
-#: config/tc-h8300.c:1410
+#: config/tc-h8300.c:1408
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300H mode"
 msgstr ""
 
-#: config/tc-h8300.c:1416
+#: config/tc-h8300.c:1414
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300S mode"
 msgstr ""
 
-#: config/tc-h8300.c:1477 config/tc-h8300.c:1497
+#: config/tc-h8300.c:1475 config/tc-h8300.c:1495
 msgid "Need #1 or #2 here"
 msgstr ""
 
-#: config/tc-h8300.c:1492
+#: config/tc-h8300.c:1490
 msgid "#4 not valid on H8/300."
 msgstr ""
 
-#: config/tc-h8300.c:1598 config/tc-h8300.c:1680
+#: config/tc-h8300.c:1596 config/tc-h8300.c:1678
 #, c-format
 msgid "branch operand has odd offset (%lx)\n"
 msgstr ""
 
-#: config/tc-h8300.c:1718
+#: config/tc-h8300.c:1716
 msgid "destination operand must be 16 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1727
+#: config/tc-h8300.c:1725
 msgid "source operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1735
+#: config/tc-h8300.c:1733
 msgid "destination operand must be 16bit absolute address"
 msgstr ""
 
-#: config/tc-h8300.c:1742
+#: config/tc-h8300.c:1740
 msgid "destination operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1750
+#: config/tc-h8300.c:1748
 msgid "source operand must be 16bit absolute address"
 msgstr ""
 
 #. This seems more sane than saying "too many operands".  We'll
 #. get here only if the trailing trash starts with a comma.
 #. Types or values of args don't match.
-#: config/tc-h8300.c:1758 config/tc-mmix.c:473 config/tc-mmix.c:485
-#: config/tc-mmix.c:2526 config/tc-mmix.c:2550 config/tc-mmix.c:2823
-#: config/tc-or32.c:527
+#: config/tc-h8300.c:1756 config/tc-mmix.c:472 config/tc-mmix.c:484
+#: config/tc-mmix.c:2525 config/tc-mmix.c:2549 config/tc-mmix.c:2822
+#: config/tc-or32.c:528
 msgid "invalid operands"
 msgstr ""
 
-#: config/tc-h8300.c:1789
+#: config/tc-h8300.c:1787
 msgid "operand/size mis-match"
 msgstr ""
 
-#: config/tc-h8300.c:1885 config/tc-mips.c:9358 config/tc-sh64.c:2795
-#: config/tc-sh.c:2838 config/tc-z8k.c:1204
+#: config/tc-h8300.c:1883 config/tc-mips.c:9767 config/tc-sh64.c:2795
+#: config/tc-sh.c:2925 config/tc-z8k.c:1226
 msgid "unknown opcode"
 msgstr ""
 
-#: config/tc-h8300.c:1918
+#: config/tc-h8300.c:1916
 msgid "invalid operand in ldm"
 msgstr ""
 
-#: config/tc-h8300.c:1927
+#: config/tc-h8300.c:1925
 msgid "invalid operand in stm"
 msgstr ""
 
-#: config/tc-h8300.c:2093
+#: config/tc-h8300.c:2091
 #, c-format
 msgid "call to tc_aout_fix_to_chars \n"
 msgstr ""
 
-#: config/tc-h8300.c:2102
+#: config/tc-h8300.c:2100 config/tc-xc16x.c:389
 #, c-format
 msgid "call to md_convert_frag \n"
 msgstr ""
 
-#: config/tc-h8300.c:2146
+#: config/tc-h8300.c:2144 config/tc-xc16x.c:293
 #, c-format
 msgid "call tomd_estimate_size_before_relax \n"
 msgstr ""
 
-#: config/tc-h8300.c:2197 config/tc-mcore.c:2282 config/tc-pj.c:538
-#: config/tc-sh.c:4270
+#: config/tc-h8300.c:2195 config/tc-mcore.c:2265 config/tc-pj.c:538
+#: config/tc-sh.c:4401 config/tc-xc16x.c:357
 #, c-format
 msgid "Cannot represent relocation type %s"
 msgstr ""
@@ -4043,619 +4514,625 @@ msgstr ""
 #. IGNORE is used to suppress the error message.
 #. Variant of CHECK_FIELD for use in md_apply_fix and other places where
 #. the current file and line number are not valid.
-#: config/tc-hppa.c:1176 config/tc-hppa.c:1190
+#: config/tc-hppa.c:1015 config/tc-hppa.c:1029
 #, c-format
 msgid "Field out of range [%d..%d] (%d)."
 msgstr ""
 
 #. Simple alignment checking for FIELD against ALIGN (a power of two).
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1204
+#: config/tc-hppa.c:1043
 #, c-format
 msgid "Field not properly aligned [%d] (%d)."
 msgstr ""
 
-#: config/tc-hppa.c:1233
+#: config/tc-hppa.c:1092
 msgid "Missing .exit\n"
 msgstr ""
 
-#: config/tc-hppa.c:1236
+#: config/tc-hppa.c:1095
 msgid "Missing .procend\n"
 msgstr ""
 
-#: config/tc-hppa.c:1422
+#: config/tc-hppa.c:1277
 #, c-format
 msgid "Invalid field selector.  Assuming F%%."
 msgstr ""
 
-#: config/tc-hppa.c:1455
-msgid "-R option not supported on this target."
-msgstr ""
-
-#: config/tc-hppa.c:1471 config/tc-sparc.c:811 config/tc-sparc.c:847
-#, c-format
-msgid "Internal error: can't hash `%s': %s\n"
+#: config/tc-hppa.c:1304
+msgid "Bad segment in expression."
 msgstr ""
 
-#: config/tc-hppa.c:1479 config/tc-i860.c:238
+#: config/tc-hppa.c:1329
 #, c-format
-msgid "internal error: losing opcode: `%s' \"%s\"\n"
-msgstr ""
-
-#: config/tc-hppa.c:1550 config/tc-hppa.c:7065 config/tc-hppa.c:7122
-msgid "Missing function name for .PROC (corrupted label chain)"
-msgstr ""
-
-#: config/tc-hppa.c:1553 config/tc-hppa.c:7125
-msgid "Missing function name for .PROC"
+msgid "Invalid Nullification: (%c)"
 msgstr ""
 
-#: config/tc-hppa.c:1857
-msgid "Invalid Indexed Load Completer."
+#: config/tc-hppa.c:1438
+msgid "Cannot handle fixup"
 msgstr ""
 
-#: config/tc-hppa.c:1862
-msgid "Invalid Indexed Load Completer Syntax."
+#: config/tc-hppa.c:1736
+#, c-format
+msgid "  -Q                      ignored\n"
 msgstr ""
 
-#: config/tc-hppa.c:1896
-msgid "Invalid Short Load/Store Completer."
+#: config/tc-hppa.c:1740
+#, c-format
+msgid "  -c                      print a warning if a comment is found\n"
 msgstr ""
 
-#: config/tc-hppa.c:1956 config/tc-hppa.c:1961
-msgid "Invalid Store Bytes Short Completer"
+#: config/tc-hppa.c:1806
+#, c-format
+msgid "no hppa_fixup entry for fixup type 0x%x"
 msgstr ""
 
-#: config/tc-hppa.c:2272 config/tc-hppa.c:2278
-msgid "Invalid left/right combination completer"
+#: config/tc-hppa.c:1985
+msgid "Unknown relocation encountered in md_apply_fix."
 msgstr ""
 
-#: config/tc-hppa.c:2327 config/tc-hppa.c:2334
-msgid "Invalid permutation completer"
+#: config/tc-hppa.c:2173 config/tc-hppa.c:2198
+#, c-format
+msgid "Undefined register: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2434
+#: config/tc-hppa.c:2232
 #, c-format
-msgid "Invalid Add Condition: %s"
+msgid "Non-absolute symbol: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2445 config/tc-hppa.c:2455
-msgid "Invalid Add and Branch Condition"
+#: config/tc-hppa.c:2247
+#, c-format
+msgid "Undefined absolute constant: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:2476 config/tc-hppa.c:2613
-msgid "Invalid Compare/Subtract Condition"
+#: config/tc-hppa.c:2278 config/tc-hppa.c:5697
+msgid "could not update architecture and machine"
 msgstr ""
 
-#: config/tc-hppa.c:2516
+#: config/tc-hppa.c:2316
 #, c-format
-msgid "Invalid Bit Branch Condition: %c"
+msgid "Invalid FP Compare Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2601
+#: config/tc-hppa.c:2371
 #, c-format
-msgid "Invalid Compare/Subtract Condition: %s"
+msgid "Invalid FTEST completer: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2628
-msgid "Invalid Compare and Branch Condition"
+#: config/tc-hppa.c:2437 config/tc-hppa.c:2474
+#, c-format
+msgid "Invalid FP Operand Format: %3s"
 msgstr ""
 
-#: config/tc-hppa.c:2724
-msgid "Invalid Logical Instruction Condition."
+#: config/tc-hppa.c:2609
+msgid "Bad segment (should be absolute)."
 msgstr ""
 
-#: config/tc-hppa.c:2779
-msgid "Invalid Shift/Extract/Deposit Condition."
+#: config/tc-hppa.c:2635
+#, c-format
+msgid "Invalid argument location: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:2891
-msgid "Invalid Unit Instruction Condition."
+#: config/tc-hppa.c:2664
+#, c-format
+msgid "Invalid argument description: %d"
 msgstr ""
 
-#: config/tc-hppa.c:3270 config/tc-hppa.c:3302 config/tc-hppa.c:3333
-#: config/tc-hppa.c:3363
-msgid "Branch to unaligned address"
+#: config/tc-hppa.c:3490
+msgid "Invalid Indexed Load Completer."
 msgstr ""
 
-#: config/tc-hppa.c:3541
-msgid "Invalid SFU identifier"
+#: config/tc-hppa.c:3495
+msgid "Invalid Indexed Load Completer Syntax."
 msgstr ""
 
-#: config/tc-hppa.c:3591
-msgid "Invalid COPR identifier"
+#: config/tc-hppa.c:3529
+msgid "Invalid Short Load/Store Completer."
 msgstr ""
 
-#: config/tc-hppa.c:3720
-msgid "Invalid Floating Point Operand Format."
+#: config/tc-hppa.c:3589 config/tc-hppa.c:3594
+msgid "Invalid Store Bytes Short Completer"
 msgstr ""
 
-#: config/tc-hppa.c:3837 config/tc-hppa.c:3857 config/tc-hppa.c:3877
-#: config/tc-hppa.c:3897 config/tc-hppa.c:3917
-msgid "Invalid register for single precision fmpyadd or fmpysub"
+#: config/tc-hppa.c:3905 config/tc-hppa.c:3911
+msgid "Invalid left/right combination completer"
 msgstr ""
 
-#: config/tc-hppa.c:3968 config/tc-hppa.c:4928
-msgid "could not update architecture and machine"
+#: config/tc-hppa.c:3960 config/tc-hppa.c:3967
+msgid "Invalid permutation completer"
 msgstr ""
 
-#: config/tc-hppa.c:3985
+#: config/tc-hppa.c:4067
 #, c-format
-msgid "Invalid operands %s"
+msgid "Invalid Add Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:4103
-msgid "Cannot handle fixup"
+#: config/tc-hppa.c:4078 config/tc-hppa.c:4088
+msgid "Invalid Add and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4404
-#, c-format
-msgid "  -Q                      ignored\n"
+#: config/tc-hppa.c:4109 config/tc-hppa.c:4246
+msgid "Invalid Compare/Subtract Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4408
+#: config/tc-hppa.c:4149
 #, c-format
-msgid "  -c                      print a warning if a comment is found\n"
+msgid "Invalid Bit Branch Condition: %c"
 msgstr ""
 
-#: config/tc-hppa.c:4479
+#: config/tc-hppa.c:4234
 #, c-format
-msgid "no hppa_fixup entry for fixup type 0x%x"
+msgid "Invalid Compare/Subtract Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:4650
-msgid "Unknown relocation encountered in md_apply_fix."
+#: config/tc-hppa.c:4261
+msgid "Invalid Compare and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:4792 config/tc-hppa.c:4817
-#, c-format
-msgid "Undefined register: '%s'."
+#: config/tc-hppa.c:4357
+msgid "Invalid Logical Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4851
-#, c-format
-msgid "Non-absolute symbol: '%s'."
+#: config/tc-hppa.c:4412
+msgid "Invalid Shift/Extract/Deposit Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4866
-#, c-format
-msgid "Undefined absolute constant: '%s'."
+#: config/tc-hppa.c:4524
+msgid "Invalid Unit Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:4967
-#, c-format
-msgid "Invalid FP Compare Condition: %s"
+#: config/tc-hppa.c:4999 config/tc-hppa.c:5031 config/tc-hppa.c:5062
+#: config/tc-hppa.c:5092
+msgid "Branch to unaligned address"
 msgstr ""
 
-#: config/tc-hppa.c:5023
-#, c-format
-msgid "Invalid FTEST completer: %s"
+#: config/tc-hppa.c:5270
+msgid "Invalid SFU identifier"
 msgstr ""
 
-#: config/tc-hppa.c:5090 config/tc-hppa.c:5128
-#, c-format
-msgid "Invalid FP Operand Format: %3s"
+#: config/tc-hppa.c:5320
+msgid "Invalid COPR identifier"
 msgstr ""
 
-#: config/tc-hppa.c:5207
-msgid "Bad segment in expression."
+#: config/tc-hppa.c:5449
+msgid "Invalid Floating Point Operand Format."
 msgstr ""
 
-#: config/tc-hppa.c:5266
-msgid "Bad segment (should be absolute)."
+#: config/tc-hppa.c:5566 config/tc-hppa.c:5586 config/tc-hppa.c:5606
+#: config/tc-hppa.c:5626 config/tc-hppa.c:5646
+msgid "Invalid register for single precision fmpyadd or fmpysub"
 msgstr ""
 
-#: config/tc-hppa.c:5309
+#: config/tc-hppa.c:5714
 #, c-format
-msgid "Invalid argument location: %s\n"
+msgid "Invalid operands %s"
 msgstr ""
 
-#: config/tc-hppa.c:5340
-#, c-format
-msgid "Invalid argument description: %d"
+#: config/tc-hppa.c:5769 config/tc-hppa.c:6975 config/tc-hppa.c:7030
+msgid "Missing function name for .PROC (corrupted label chain)"
 msgstr ""
 
-#: config/tc-hppa.c:5363
-#, c-format
-msgid "Invalid Nullification: (%c)"
+#: config/tc-hppa.c:5772 config/tc-hppa.c:7033
+msgid "Missing function name for .PROC"
 msgstr ""
 
-#: config/tc-hppa.c:5960
+#: config/tc-hppa.c:5831
 msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff"
 msgstr ""
 
-#: config/tc-hppa.c:6076
+#: config/tc-hppa.c:5927
 #, c-format
 msgid "Invalid .CALL argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6198
+#: config/tc-hppa.c:6061
 msgid ".callinfo is not within a procedure definition"
 msgstr ""
 
-#: config/tc-hppa.c:6218
+#: config/tc-hppa.c:6081
 #, c-format
 msgid "FRAME parameter must be a multiple of 8: %d\n"
 msgstr ""
 
-#: config/tc-hppa.c:6237
+#: config/tc-hppa.c:6100
 msgid "Value for ENTRY_GR must be in the range 3..18\n"
 msgstr ""
 
-#: config/tc-hppa.c:6249
+#: config/tc-hppa.c:6112
 msgid "Value for ENTRY_FR must be in the range 12..21\n"
 msgstr ""
 
-#: config/tc-hppa.c:6259
+#: config/tc-hppa.c:6122
 msgid "Value for ENTRY_SR must be 3\n"
 msgstr ""
 
-#: config/tc-hppa.c:6315
+#: config/tc-hppa.c:6178
 #, c-format
 msgid "Invalid .CALLINFO argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6427
+#: config/tc-hppa.c:6288
 msgid "The .ENTER pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6443
+#: config/tc-hppa.c:6304
 msgid "Misplaced .entry. Ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6447
+#: config/tc-hppa.c:6308
 msgid "Missing .callinfo."
 msgstr ""
 
-#: config/tc-hppa.c:6513
+#: config/tc-hppa.c:6372
 msgid ".REG expression must be a register"
 msgstr ""
 
-#: config/tc-hppa.c:6529
+#: config/tc-hppa.c:6388
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr ""
 
-#: config/tc-hppa.c:6540
+#: config/tc-hppa.c:6399
 msgid ".REG must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6542
+#: config/tc-hppa.c:6401
 msgid ".EQU must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6595
+#: config/tc-hppa.c:6463
+#, c-format
+msgid "Symbol '%s' could not be created."
+msgstr ""
+
+#: config/tc-hppa.c:6467
+msgid "No memory for symbol name."
+msgstr ""
+
+#: config/tc-hppa.c:6516
 msgid ".EXIT must appear within a procedure"
 msgstr ""
 
-#: config/tc-hppa.c:6599
+#: config/tc-hppa.c:6520
 msgid "Missing .callinfo"
 msgstr ""
 
-#: config/tc-hppa.c:6603
+#: config/tc-hppa.c:6524
 msgid "No .ENTRY for this .EXIT"
 msgstr ""
 
-#: config/tc-hppa.c:6630
+#: config/tc-hppa.c:6564
 #, c-format
-msgid "Cannot define export symbol: %s\n"
+msgid "Using ENTRY rather than CODE in export directive for %s"
 msgstr ""
 
-#: config/tc-hppa.c:6688
+#: config/tc-hppa.c:6681
 #, c-format
-msgid "Using ENTRY rather than CODE in export directive for %s"
+msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
 msgstr ""
 
-#: config/tc-hppa.c:6805
+#: config/tc-hppa.c:6705
 #, c-format
-msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
+msgid "Cannot define export symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:6887
+#: config/tc-hppa.c:6802
 msgid "Missing label name on .LABEL"
 msgstr ""
 
-#: config/tc-hppa.c:6892
+#: config/tc-hppa.c:6807
 msgid "extra .LABEL arguments ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6909
+#: config/tc-hppa.c:6823
 msgid "The .LEAVE pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6948
+#: config/tc-hppa.c:6861
 msgid "Unrecognized .LEVEL argument\n"
 msgstr ""
 
-#: config/tc-hppa.c:6984
+#: config/tc-hppa.c:6895
 #, c-format
 msgid "Cannot define static symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7019
+#: config/tc-hppa.c:6929
 msgid "Nested procedures"
 msgstr ""
 
-#: config/tc-hppa.c:7029
+#: config/tc-hppa.c:6939
 msgid "Cannot allocate unwind descriptor\n"
 msgstr ""
 
-#: config/tc-hppa.c:7129
+#: config/tc-hppa.c:7037
 msgid "misplaced .procend"
 msgstr ""
 
-#: config/tc-hppa.c:7132
+#: config/tc-hppa.c:7040
 msgid "Missing .callinfo for this procedure"
 msgstr ""
 
-#: config/tc-hppa.c:7135
+#: config/tc-hppa.c:7043
 msgid "Missing .EXIT for a .ENTRY"
 msgstr ""
 
-#: config/tc-hppa.c:7173
+#: config/tc-hppa.c:7080
 msgid "Not in a space.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7176
+#: config/tc-hppa.c:7083
 msgid "Not in a subspace.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7267
+#: config/tc-hppa.c:7172
 msgid "Invalid .SPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7314
+#: config/tc-hppa.c:7218
 msgid "Can't change spaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7443
+#: config/tc-hppa.c:7346
 #, c-format
 msgid "Undefined space: '%s' Assuming space number = 0."
 msgstr ""
 
-#: config/tc-hppa.c:7467
+#: config/tc-hppa.c:7369
 msgid "Must be in a space before changing or declaring subspaces.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7471
+#: config/tc-hppa.c:7373
 msgid "Can't change subspaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7507
+#: config/tc-hppa.c:7409
 msgid "Parameters of an existing subspace can't be modified"
 msgstr ""
 
-#: config/tc-hppa.c:7559
+#: config/tc-hppa.c:7461
 msgid "Alignment must be a power of 2"
 msgstr ""
 
-#: config/tc-hppa.c:7606
+#: config/tc-hppa.c:7508
 msgid "FIRST not supported as a .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7608
+#: config/tc-hppa.c:7510
 msgid "Invalid .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7797
+#: config/tc-hppa.c:7699
 #, c-format
 msgid "Internal error: Unable to find containing space for %s."
 msgstr ""
 
-#: config/tc-hppa.c:7837
+#: config/tc-hppa.c:7737
 #, c-format
 msgid "Out of memory: could not allocate new space chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7926
+#: config/tc-hppa.c:7825
 #, c-format
 msgid "Out of memory: could not allocate new subspace chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:8662
+#: config/tc-hppa.c:8270
+msgid "-R option not supported on this target."
+msgstr ""
+
+#: config/tc-hppa.c:8287 config/tc-sparc.c:825 config/tc-sparc.c:861
 #, c-format
-msgid "Symbol '%s' could not be created."
+msgid "Internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:8666
-msgid "No memory for symbol name."
+#: config/tc-hppa.c:8296 config/tc-i860.c:236
+#, c-format
+msgid "internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-i386.c:721
+#: config/tc-i386.c:983
 #, c-format
 msgid "%s shortened to %s"
 msgstr ""
 
-#: config/tc-i386.c:777
+#: config/tc-i386.c:1053
 msgid "same type of prefix used twice"
 msgstr ""
 
-#: config/tc-i386.c:795
+#: config/tc-i386.c:1066
 msgid "64bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:799
+#: config/tc-i386.c:1070
 msgid "32bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:832
+#: config/tc-i386.c:1101
 msgid "bad argument to syntax directive."
 msgstr ""
 
-#: config/tc-i386.c:884
+#: config/tc-i386.c:1161
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:889
+#: config/tc-i386.c:1166
 msgid "missing cpu architecture"
 msgstr ""
 
-#: config/tc-i386.c:903
+#: config/tc-i386.c:1180
 #, c-format
 msgid "no such architecture modifier: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:919 config/tc-i386.c:5342
+#: config/tc-i386.c:1196 config/tc-i386.c:6133 config/tc-i386.c:6167
 msgid "Unknown architecture"
 msgstr ""
 
-#: config/tc-i386.c:1247
+#: config/tc-i386.c:1528
 #, c-format
 msgid "unknown relocation (%u)"
 msgstr ""
 
-#: config/tc-i386.c:1249
+#: config/tc-i386.c:1530
 #, c-format
 msgid "%u-byte relocation cannot be applied to %u-byte field"
 msgstr ""
 
-#: config/tc-i386.c:1253
+#: config/tc-i386.c:1534
 msgid "non-pc-relative relocation for pc-relative field"
 msgstr ""
 
-#: config/tc-i386.c:1258
+#: config/tc-i386.c:1539
 msgid "relocated field and relocation type differ in signedness"
 msgstr ""
 
-#: config/tc-i386.c:1267
+#: config/tc-i386.c:1548
 msgid "there are no unsigned pc-relative relocations"
 msgstr ""
 
-#: config/tc-i386.c:1275
+#: config/tc-i386.c:1556
 #, c-format
 msgid "cannot do %u byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-i386.c:1292
+#: config/tc-i386.c:1573
 #, c-format
 msgid "cannot do %s %u byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:1496 config/tc-i386.c:2527
+#: config/tc-i386.c:1790 config/tc-i386.c:2963
 #, c-format
 msgid "ambiguous operand size for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1544
+#: config/tc-i386.c:1838
 #, c-format
-msgid "can't use register '%%%s' as operand %d in '%s'."
+msgid "can't use register '%s%s' as operand %d in '%s'."
 msgstr ""
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:1573
+#: config/tc-i386.c:1870
 #, c-format
 msgid "translating to `%sp'"
 msgstr ""
 
-#: config/tc-i386.c:1618
+#: config/tc-i386.c:1915
 #, c-format
-msgid "can't encode register '%%%s' in an instruction requiring REX prefix."
+msgid "can't encode register '%s%s' in an instruction requiring REX prefix."
 msgstr ""
 
-#: config/tc-i386.c:1659 config/tc-i386.c:1767
+#: config/tc-i386.c:1955 config/tc-i386.c:2063
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1670 config/tc-i386.c:1799
+#: config/tc-i386.c:1966 config/tc-i386.c:2095
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr ""
 
-#: config/tc-i386.c:1677
+#: config/tc-i386.c:1973
 msgid "expecting prefix; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1679
+#: config/tc-i386.c:1975
 msgid "expecting mnemonic; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1695 config/tc-i386.c:1818
+#: config/tc-i386.c:1991 config/tc-i386.c:2114
 #, c-format
 msgid "`%s' is only supported in 64-bit mode"
 msgstr ""
 
-#: config/tc-i386.c:1696 config/tc-i386.c:1817
+#: config/tc-i386.c:1992 config/tc-i386.c:2113
 #, c-format
 msgid "`%s' is not supported in 64-bit mode"
 msgstr ""
 
-#: config/tc-i386.c:1707
+#: config/tc-i386.c:2003
 #, c-format
 msgid "redundant %s prefix"
 msgstr ""
 
-#: config/tc-i386.c:1824
+#: config/tc-i386.c:2120
 #, c-format
 msgid "`%s' is not supported on `%s%s'"
 msgstr ""
 
-#: config/tc-i386.c:1831
+#: config/tc-i386.c:2127
 msgid "use .code16 to ensure correct addressing mode"
 msgstr ""
 
-#: config/tc-i386.c:1844
+#: config/tc-i386.c:2140
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1878
+#: config/tc-i386.c:2172
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1892
+#: config/tc-i386.c:2186
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1895
+#: config/tc-i386.c:2189
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1904
+#: config/tc-i386.c:2198
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1931
+#: config/tc-i386.c:2225
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr ""
 
-#: config/tc-i386.c:1954
+#: config/tc-i386.c:2248
 msgid "expecting operand after ','; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1959
+#: config/tc-i386.c:2253
 msgid "expecting operand before ','; got nothing"
 msgstr ""
 
 #. We found no match.
-#: config/tc-i386.c:2336
+#: config/tc-i386.c:2741
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:2347
+#: config/tc-i386.c:2752
 #, c-format
 msgid "indirect %s without `*'"
 msgstr ""
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:2355
+#: config/tc-i386.c:2760
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr ""
 
-#: config/tc-i386.c:2384 config/tc-i386.c:2399
+#: config/tc-i386.c:2794 config/tc-i386.c:2809
 #, c-format
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr ""
 
-#: config/tc-i386.c:2509
+#. We have to know the operand size for crc32.
+#: config/tc-i386.c:2862
+#, c-format
+msgid "ambiguous memory operand size for `%s`"
+msgstr ""
+
+#: config/tc-i386.c:2944
 msgid ""
 "no instruction mnemonic suffix given and no register operands; can't size "
 "instruction"
@@ -4663,385 +5140,444 @@ msgstr ""
 
 #. Prohibit these changes in the 64bit mode, since the
 #. lowering is more complicated.
-#: config/tc-i386.c:2610 config/tc-i386.c:2669 config/tc-i386.c:2686
-#: config/tc-i386.c:2718 config/tc-i386.c:2751
+#: config/tc-i386.c:3068 config/tc-i386.c:3131 config/tc-i386.c:3150
+#: config/tc-i386.c:3183 config/tc-i386.c:3217
 #, c-format
-msgid "Incorrect register `%%%s' used with `%c' suffix"
+msgid "Incorrect register `%s%s' used with `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2618 config/tc-i386.c:2676 config/tc-i386.c:2758
+#: config/tc-i386.c:3076 config/tc-i386.c:3138 config/tc-i386.c:3224
 #, c-format
-msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
+msgid "using `%s%s' instead of `%s%s' due to `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2633 config/tc-i386.c:2654 config/tc-i386.c:2705
-#: config/tc-i386.c:2736
+#: config/tc-i386.c:3093 config/tc-i386.c:3115 config/tc-i386.c:3169
+#: config/tc-i386.c:3201
 #, c-format
-msgid "`%%%s' not allowed with `%s%c'"
+msgid "`%s%s' not allowed with `%s%c'"
 msgstr ""
 
-#: config/tc-i386.c:2799
+#: config/tc-i386.c:3267
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr ""
 
-#: config/tc-i386.c:2832
+#: config/tc-i386.c:3301
 #, c-format
 msgid ""
 "no instruction mnemonic suffix given; can't determine immediate size %x %c"
 msgstr ""
 
-#. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2881
+#: config/tc-i386.c:3339
 #, c-format
-msgid "translating to `%s %%%s,%%%s'"
+msgid "the last operand of `%s' must be `%sxmm0'"
 msgstr ""
 
-#. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2888
+#: config/tc-i386.c:3342
 #, c-format
-msgid "translating to `%s %%%s'"
+msgid "the first operand of `%s' must be `%sxmm0'"
 msgstr ""
 
-#: config/tc-i386.c:2906
+#: config/tc-i386.c:3379
 #, c-format
 msgid "you can't `pop %%cs'"
 msgstr ""
 
-#: config/tc-i386.c:2927
+#. Reversed arguments on faddp, fsubp, etc.
+#: config/tc-i386.c:3401
+#, c-format
+msgid "translating to `%s %s%s,%s%s'"
+msgstr ""
+
+#. Extraneous `l' suffix on fp insn.
+#: config/tc-i386.c:3408
+#, c-format
+msgid "translating to `%s %s%s'"
+msgstr ""
+
+#: config/tc-i386.c:3436
 #, c-format
 msgid "segment override on `%s' is ineffectual"
 msgstr ""
 
-#: config/tc-i386.c:3236 config/tc-i386.c:3330 config/tc-i386.c:3375
+#: config/tc-i386.c:3777 config/tc-i386.c:3871 config/tc-i386.c:3916
 msgid "skipping prefixes on this instruction"
 msgstr ""
 
-#: config/tc-i386.c:3395
+#: config/tc-i386.c:3936
 msgid "16-bit jump out of range"
 msgstr ""
 
-#: config/tc-i386.c:3404
+#: config/tc-i386.c:3945
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3897
+#: config/tc-i386.c:4501
 #, c-format
 msgid "@%s reloc is not supported with %d-bit output format"
 msgstr ""
 
-#: config/tc-i386.c:3986
-msgid "only 1 or 2 immediate operands are allowed"
+#: config/tc-i386.c:4585
+#, c-format
+msgid "at most %d immediate operands are allowed"
 msgstr ""
 
-#: config/tc-i386.c:4007 config/tc-i386.c:4218
+#: config/tc-i386.c:4607 config/tc-i386.c:4824
 #, c-format
 msgid "junk `%s' after expression"
 msgstr ""
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:4016
+#: config/tc-i386.c:4616
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-i386.c:4041 config/tc-i386.c:4277
+#: config/tc-i386.c:4642 config/tc-i386.c:4883
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr ""
 
-#: config/tc-i386.c:4088
+#: config/tc-i386.c:4648
+#, c-format
+msgid "illegal immediate register operand %s"
+msgstr ""
+
+#: config/tc-i386.c:4691
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4097
+#: config/tc-i386.c:4700
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr ""
 
-#: config/tc-i386.c:4236
+#: config/tc-i386.c:4723
+#, c-format
+msgid "at most %d displacement operands are allowed"
+msgstr ""
+
+#: config/tc-i386.c:4842
 #, c-format
 msgid "bad expression used with @%s"
 msgstr ""
 
-#: config/tc-i386.c:4386
+#: config/tc-i386.c:4990
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4390
+#: config/tc-i386.c:4994
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4464
+#: config/tc-i386.c:5066
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4479
+#: config/tc-i386.c:5081
 #, c-format
 msgid "junk `%s' after register"
 msgstr ""
 
-#: config/tc-i386.c:4488 config/tc-i386.c:4603 config/tc-i386.c:4641
+#: config/tc-i386.c:5090 config/tc-i386.c:5206 config/tc-i386.c:5247
 #, c-format
 msgid "bad register name `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4496
+#: config/tc-i386.c:5098
 msgid "immediate operand illegal with absolute jump"
 msgstr ""
 
-#: config/tc-i386.c:4518
+#: config/tc-i386.c:5120
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4596
+#: config/tc-i386.c:5198
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4620
+#: config/tc-i386.c:5223
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4627
+#: config/tc-i386.c:5231
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr ""
 
-#: config/tc-i386.c:4634
+#: config/tc-i386.c:5239
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr ""
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:4675
+#: config/tc-i386.c:5281
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4850
+#: config/tc-i386.c:5457
 msgid "long jump required"
 msgstr ""
 
-#: config/tc-i386.c:5127
+#: config/tc-i386.c:5512
+msgid "jump target out of range"
+msgstr ""
+
+#: config/tc-i386.c:5757
 msgid "Bad call to md_atof ()"
 msgstr ""
 
-#: config/tc-i386.c:5294
+#: config/tc-i386.c:6012
 msgid "No compiled in support for x86_64"
 msgstr ""
 
-#: config/tc-i386.c:5315
+#: config/tc-i386.c:6041 config/tc-i386.c:6057
+#, c-format
+msgid "Invalid -march= option: `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6062 config/tc-i386.c:6074
+#, c-format
+msgid "Invalid -mtune= option: `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6088
 #, c-format
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
 "  -k                      ignored\n"
-"  -n                      Do not optimize code alignment\n"
-"  -q                      quieten some warnings\n"
-"  -s                      ignored\n"
 msgstr ""
 
-#: config/tc-i386.c:5323
+#: config/tc-i386.c:6093
 #, c-format
 msgid ""
 "  -n                      Do not optimize code alignment\n"
 "  -q                      quieten some warnings\n"
 msgstr ""
 
-#: config/tc-i386.c:5425 config/tc-s390.c:1861
+#: config/tc-i386.c:6097
+#, c-format
+msgid "  -s                      ignored\n"
+msgstr ""
+
+#: config/tc-i386.c:6101
+#, c-format
+msgid "  --32/--64               generate 32bit/64bit code\n"
+msgstr ""
+
+#: config/tc-i386.c:6105
+#, c-format
+msgid "  --divide                do not treat `/' as a comment character\n"
+msgstr ""
+
+#: config/tc-i386.c:6108
+#, c-format
+msgid "  --divide                ignored\n"
+msgstr ""
+
+#: config/tc-i386.c:6111
+#, c-format
+msgid ""
+"  -march=CPU/-mtune=CPU   generate code/optimize for CPU, where CPU is one "
+"of:\n"
+"                           i386, i486, pentium, pentiumpro, pentium4, "
+"nocona,\n"
+"                           core, core2, k6, athlon, k8, generic32, "
+"generic64\n"
+msgstr ""
+
+#: config/tc-i386.c:6251 config/tc-s390.c:1862
 msgid "GOT already in symbol table"
 msgstr ""
 
-#: config/tc-i386.c:5568
+#: config/tc-i386.c:6400
 #, c-format
 msgid "can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-i386.c:5586
+#: config/tc-i386.c:6418
 #, c-format
 msgid "can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:5657 config/tc-s390.c:2307
+#: config/tc-i386.c:6497 config/tc-s390.c:2308
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-i386.c:5912
+#: config/tc-i386.c:6749
 #, c-format
 msgid "invalid operand for '%s' ('%s' unexpected)"
 msgstr ""
 
-#: config/tc-i386.c:5924
+#: config/tc-i386.c:6761
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr ""
 
 #. See the comments in intel_bracket_expr.
-#: config/tc-i386.c:5935
+#: config/tc-i386.c:6772
 #, c-format
 msgid "Treating `%s' as memory reference"
 msgstr ""
 
-#: config/tc-i386.c:6247
+#: config/tc-i386.c:7088
 #, c-format
 msgid "Unknown operand modifier `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6262
+#: config/tc-i386.c:7103
 msgid "Conflicting operand modifiers"
 msgstr ""
 
-#: config/tc-i386.c:6311
+#: config/tc-i386.c:7152
 msgid "Invalid operand to `OFFSET'"
 msgstr ""
 
-#: config/tc-i386.c:6384
+#: config/tc-i386.c:7225
 #, c-format
 msgid "`[%.*s]' taken to mean just `%.*s'"
 msgstr ""
 
-#: config/tc-i386.c:6474
+#: config/tc-i386.c:7316
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr ""
 
-#: config/tc-i386.c:6478
+#: config/tc-i386.c:7321
 msgid "Extra segment override ignored"
 msgstr ""
 
-#: config/tc-i386.c:6512 config/tc-i386.c:6681
+#: config/tc-i386.c:7355 config/tc-i386.c:7517
 msgid "Register scaling only allowed in memory operands"
 msgstr ""
 
-#: config/tc-i386.c:6534 config/tc-i386.c:6658
+#: config/tc-i386.c:7377 config/tc-i386.c:7493
 #, c-format
 msgid "Syntax error: Expecting a constant, got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6562
+#: config/tc-i386.c:7405
 msgid "Too many register references in memory operand"
 msgstr ""
 
-#: config/tc-i386.c:6573
-msgid "Using register names in OFFSET expressions is deprecated"
-msgstr ""
-
-#: config/tc-i386.c:6586
+#: config/tc-i386.c:7421
 msgid "Invalid use of register"
 msgstr ""
 
-#: config/tc-i386.c:6731
+#: config/tc-i386.c:7570
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr ""
 
-#: config/tc-i386.c:6748
+#: config/tc-i386.c:7586
 #, c-format
 msgid "Unexpected token `%s'"
 msgstr ""
 
-#: config/tc-i386.c:6910
+#: config/tc-i386.c:7744
 msgid "`:' expected"
 msgstr ""
 
-#: config/tc-i386.c:6935
+#: config/tc-i386.c:7769
 #, c-format
 msgid "Unrecognized token `%s'"
 msgstr ""
 
-#: config/tc-i386.c:7070
+#: config/tc-i386.c:7904
 msgid "Bad .section directive: want a,l,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-i386.c:7073
+#: config/tc-i386.c:7907
 msgid "Bad .section directive: want a,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-i386.c:7092
+#: config/tc-i386.c:7926
 msgid ".largecomm supported only in 64bit mode, producing .comm"
 msgstr ""
 
-#: config/tc-i860.c:124
+#: config/tc-i860.c:122
 msgid "Directive .dual available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:134
+#: config/tc-i860.c:132
 msgid "Directive .enddual available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:147
+#: config/tc-i860.c:145
 msgid "Directive .atmp available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:169 config/tc-i860.c:173
+#: config/tc-i860.c:167 config/tc-i860.c:171
 msgid "Unknown temporary pseudo register"
 msgstr ""
 
-#: config/tc-i860.c:229 config/tc-mips.c:1412
+#: config/tc-i860.c:227 config/tc-mips.c:1761
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-i860.c:249
+#: config/tc-i860.c:247
 msgid "Defective assembler.  No assembly attempted."
 msgstr ""
 
-#: config/tc-i860.c:395 config/tc-i860.c:940 config/tc-m68k.c:3443
-#: config/tc-m68k.c:3475 config/tc-sparc.c:2657
+#: config/tc-i860.c:393 config/tc-i860.c:938 config/tc-m68k.c:3667
+#: config/tc-m68k.c:3699 config/tc-sparc.c:2711
 msgid "failed sanity check."
 msgstr ""
 
-#: config/tc-i860.c:402
+#: config/tc-i860.c:400
 #, c-format
 msgid "Expanded opcode after delayed branch: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:406
+#: config/tc-i860.c:404
 #, c-format
 msgid "Expanded opcode in dual mode: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:410
+#: config/tc-i860.c:408
 #, c-format
 msgid "An instruction was expanded (%s)"
 msgstr ""
 
-#: config/tc-i860.c:676
+#: config/tc-i860.c:674
 msgid "Pipelined instruction: fsrc1 = fdest"
 msgstr ""
 
-#: config/tc-i860.c:879 config/tc-i860.c:886 config/tc-i860.c:893
+#: config/tc-i860.c:877 config/tc-i860.c:884 config/tc-i860.c:891
 msgid "Assembler does not yet support PIC"
 msgstr ""
 
-#: config/tc-i860.c:957
+#: config/tc-i860.c:955
 #, c-format
 msgid "Illegal operands for %s"
 msgstr ""
 
-#: config/tc-i860.c:974
+#: config/tc-i860.c:972
 #, c-format
 msgid "'d.%s' must be 8-byte aligned"
 msgstr ""
 
-#: config/tc-i860.c:982
+#: config/tc-i860.c:980
 #, c-format
 msgid "Prefix 'd.' invalid for instruction `%s'"
 msgstr ""
 
-#: config/tc-i860.c:1088
+#: config/tc-i860.c:1086
 msgid "i860_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-i860.c:1187
+#: config/tc-i860.c:1185
 #, c-format
 msgid ""
 "  -EL\t\t\t  generate code for little endian mode (default)\n"
@@ -5052,42 +5588,42 @@ msgid ""
 msgstr ""
 
 #. SVR4 compatibility flags.
-#: config/tc-i860.c:1195
+#: config/tc-i860.c:1193
 #, c-format
 msgid ""
 "  -V\t\t\t  print assembler version number\n"
 "  -Qy, -Qn\t\t  ignored\n"
 msgstr ""
 
-#: config/tc-i860.c:1258
+#: config/tc-i860.c:1256
 msgid "This immediate requires 0 MOD 2 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1261
+#: config/tc-i860.c:1259
 msgid "This immediate requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1264
+#: config/tc-i860.c:1262
 msgid "This immediate requires 0 MOD 8 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1267
+#: config/tc-i860.c:1265
 msgid "This immediate requires 0 MOD 16 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1362
+#: config/tc-i860.c:1360
 msgid "5-bit immediate too large"
 msgstr ""
 
-#: config/tc-i860.c:1365
+#: config/tc-i860.c:1363
 msgid "5-bit field must be absolute"
 msgstr ""
 
-#: config/tc-i860.c:1410 config/tc-i860.c:1433
+#: config/tc-i860.c:1408 config/tc-i860.c:1431
 msgid "A branch offset requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1454
+#: config/tc-i860.c:1452
 #, c-format
 msgid "Unrecognized fix-up (0x%08lx)"
 msgstr ""
@@ -5096,95 +5632,87 @@ msgstr ""
 msgid "i860_convert_frag\n"
 msgstr ""
 
-#: config/tc-i960.c:488
+#: config/tc-i960.c:486
 #, c-format
 msgid "Hashing returned \"%s\"."
 msgstr ""
 
-#: config/tc-i960.c:584 config/tc-i960.c:1114
+#: config/tc-i960.c:582 config/tc-i960.c:1112
 msgid "expression syntax error"
 msgstr ""
 
-#: config/tc-i960.c:620
+#: config/tc-i960.c:618
 msgid "attempt to branch into different segment"
 msgstr ""
 
-#: config/tc-i960.c:624
+#: config/tc-i960.c:622
 #, c-format
 msgid "target of %s instruction must be a label"
 msgstr ""
 
-#: config/tc-i960.c:734
+#: config/tc-i960.c:732
 msgid "unaligned register"
 msgstr ""
 
-#: config/tc-i960.c:756
+#: config/tc-i960.c:754
 msgid "no such sfr in this architecture"
 msgstr ""
 
-#: config/tc-i960.c:794
+#: config/tc-i960.c:792
 msgid "illegal literal"
 msgstr ""
 
-#: config/tc-i960.c:837
-msgid "unmatched '['"
-msgstr ""
-
-#: config/tc-i960.c:844
-msgid "garbage after index spec ignored"
-msgstr ""
-
-#: config/tc-i960.c:944
+#: config/tc-i960.c:942
 msgid "invalid index register"
 msgstr ""
 
-#: config/tc-i960.c:967
+#: config/tc-i960.c:965
 msgid "invalid scale factor"
 msgstr ""
 
-#: config/tc-i960.c:1191
+#: config/tc-i960.c:1189
 msgid "architecture of opcode conflicts with that of earlier instruction(s)"
 msgstr ""
 
-#: config/tc-i960.c:1425 config/tc-xtensa.c:11295
+#: config/tc-i960.c:1423 config/tc-xtensa.c:11325
 msgid "too many operands"
 msgstr ""
 
 #. We never moved: there was no opcode either!
-#: config/tc-i960.c:1473
+#: config/tc-i960.c:1471
 msgid "missing opcode"
 msgstr ""
 
-#: config/tc-i960.c:1613
+#: config/tc-i960.c:1611
 msgid "branch prediction invalid on this opcode"
 msgstr ""
 
-#: config/tc-i960.c:1651
+#: config/tc-i960.c:1649
 #, c-format
 msgid "invalid opcode, \"%s\"."
 msgstr ""
 
-#: config/tc-i960.c:1653
+#: config/tc-i960.c:1651
 #, c-format
 msgid "improper number of operands.  expecting %d, got %d"
 msgstr ""
 
-#: config/tc-i960.c:1810
+#: config/tc-i960.c:1808
 #, c-format
 msgid "Fixup of %ld too large for field width of %d"
 msgstr ""
 
-#: config/tc-i960.c:1920
+#: config/tc-i960.c:1918
 #, c-format
 msgid "invalid architecture %s"
 msgstr ""
 
-#: config/tc-i960.c:1940
+#: config/tc-i960.c:1938
 #, c-format
 msgid "I960 options:\n"
 msgstr ""
 
-#: config/tc-i960.c:1943
+#: config/tc-i960.c:1941
 #, c-format
 msgid ""
 "\n"
@@ -5196,153 +5724,153 @@ msgid ""
 "\t\t\tlong displacements\n"
 msgstr ""
 
-#: config/tc-i960.c:2207
+#: config/tc-i960.c:2205
 msgid "should have 1 or 2 operands"
 msgstr ""
 
-#: config/tc-i960.c:2215 config/tc-i960.c:2230
+#: config/tc-i960.c:2213 config/tc-i960.c:2228
 #, c-format
 msgid "Redefining leafproc %s"
 msgstr ""
 
-#: config/tc-i960.c:2260
+#: config/tc-i960.c:2258
 msgid "should have two operands"
 msgstr ""
 
-#: config/tc-i960.c:2270
+#: config/tc-i960.c:2268
 msgid "'entry_num' must be absolute number in [0,31]"
 msgstr ""
 
-#: config/tc-i960.c:2278
+#: config/tc-i960.c:2276
 #, c-format
 msgid "Redefining entrynum for sysproc %s"
 msgstr ""
 
 #. Should not happen: see block comment above.
-#: config/tc-i960.c:2378
+#: config/tc-i960.c:2376
 #, c-format
 msgid "Trying to 'bal' to %s"
 msgstr ""
 
-#: config/tc-i960.c:2388
+#: config/tc-i960.c:2386
 msgid "Looks like a proc, but can't tell what kind.\n"
 msgstr ""
 
-#: config/tc-i960.c:2407
+#: config/tc-i960.c:2405
 msgid "big endian mode is not supported"
 msgstr ""
 
-#: config/tc-i960.c:2409
+#: config/tc-i960.c:2407
 #, c-format
 msgid "ignoring unrecognized .endian type `%s'"
 msgstr ""
 
-#: config/tc-i960.c:2454
+#: config/tc-i960.c:2452
 msgid "can't use COBR format with external label"
 msgstr ""
 
-#: config/tc-i960.c:2629
+#: config/tc-i960.c:2627
 msgid "option --link-relax is only supported in b.out format"
 msgstr ""
 
-#: config/tc-i960.c:2656
+#: config/tc-i960.c:2654
 #, c-format
 msgid "No 'bal' entry point for leafproc %s"
 msgstr ""
 
-#: config/tc-ia64.c:1008
+#: config/tc-ia64.c:1030
 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ia64.c:1151
+#: config/tc-ia64.c:1173
 msgid "Unwind directive not followed by an instruction."
 msgstr ""
 
-#: config/tc-ia64.c:5114
+#: config/tc-ia64.c:5123
 msgid "Register name expected"
 msgstr ""
 
-#: config/tc-ia64.c:5119 config/tc-ia64.c:5435
+#: config/tc-ia64.c:5128 config/tc-ia64.c:5444
 msgid "Comma expected"
 msgstr ""
 
-#: config/tc-ia64.c:5127
+#: config/tc-ia64.c:5136
 msgid "Register value annotation ignored"
 msgstr ""
 
-#: config/tc-ia64.c:5168
+#: config/tc-ia64.c:5177
 msgid "Directive invalid within a bundle"
 msgstr ""
 
-#: config/tc-ia64.c:5261
+#: config/tc-ia64.c:5270
 msgid "Missing predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:5267
+#: config/tc-ia64.c:5276
 msgid "Unrecognized predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:5314
+#: config/tc-ia64.c:5323
 msgid "Bad register range"
 msgstr ""
 
-#: config/tc-ia64.c:5323
+#: config/tc-ia64.c:5332
 msgid "Predicate register expected"
 msgstr ""
 
-#: config/tc-ia64.c:5328
+#: config/tc-ia64.c:5337
 msgid "Duplicate predicate register ignored"
 msgstr ""
 
-#: config/tc-ia64.c:5346
+#: config/tc-ia64.c:5355
 msgid "Predicate source and target required"
 msgstr ""
 
-#: config/tc-ia64.c:5348 config/tc-ia64.c:5360
+#: config/tc-ia64.c:5357 config/tc-ia64.c:5369
 msgid "Use of p0 is not valid in this context"
 msgstr ""
 
-#: config/tc-ia64.c:5355
+#: config/tc-ia64.c:5364
 msgid "At least two PR arguments expected"
 msgstr ""
 
-#: config/tc-ia64.c:5369
+#: config/tc-ia64.c:5378
 msgid "At least one PR argument expected"
 msgstr ""
 
-#: config/tc-ia64.c:5405
+#: config/tc-ia64.c:5414
 #, c-format
 msgid "Inserting \"%s\" into entry hint table failed: %s"
 msgstr ""
 
 #. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:5881
+#: config/tc-ia64.c:5890
 msgid "62-bit relocation not yet implemented"
 msgstr ""
 
 #. XXX technically, this is wrong: we should not be issuing warning
 #. messages until we're sure this instruction pattern is going to
 #. be used!
-#: config/tc-ia64.c:5954
+#: config/tc-ia64.c:5974
 msgid "lower 16 bits of mask ignored"
 msgstr ""
 
-#: config/tc-ia64.c:6569
+#: config/tc-ia64.c:6589
 msgid "Value truncated to 62 bits"
 msgstr ""
 
 #. Give an error if a frag containing code is not aligned to a 16 byte
 #. boundary.
-#: config/tc-ia64.c:6707 config/tc-ia64.h:171
+#: config/tc-ia64.c:6727 config/tc-ia64.h:171
 msgid "instruction address is not a multiple of 16"
 msgstr ""
 
-#: config/tc-ia64.c:7249
+#: config/tc-ia64.c:7277
 #, c-format
 msgid "Unrecognized option '-x%s'"
 msgstr ""
 
-#: config/tc-ia64.c:7277
+#: config/tc-ia64.c:7305
 msgid ""
 "IA-64 options:\n"
 "  --mconstant-gp\t  mark output file as using the constant-GP model\n"
@@ -5368,370 +5896,370 @@ msgid ""
 "\t\t\t  dependency violation checking\n"
 msgstr ""
 
-#: config/tc-ia64.c:7307
+#: config/tc-ia64.c:7335
 msgid "--gstabs is not supported for ia64"
 msgstr ""
 
-#: config/tc-ia64.c:7641 config/tc-mips.c:1401
+#: config/tc-ia64.c:7640 config/tc-mips.c:1750
 msgid "Could not set architecture and machine"
 msgstr ""
 
-#: config/tc-ia64.c:7767
+#: config/tc-ia64.c:7766
 msgid "Explicit stops are ignored in auto mode"
 msgstr ""
 
-#: config/tc-ia64.c:7789
+#: config/tc-ia64.c:7788
 msgid "Found '{' after explicit switch to automatic mode"
 msgstr ""
 
-#: config/tc-ia64.c:8392
+#: config/tc-ia64.c:8393
 #, c-format
 msgid "Unhandled dependency %s for %s (%s), note %d"
 msgstr ""
 
-#: config/tc-ia64.c:9667
+#: config/tc-ia64.c:9669
 #, c-format
 msgid "Unrecognized dependency specifier %d\n"
 msgstr ""
 
-#: config/tc-ia64.c:10561
+#: config/tc-ia64.c:10566
 msgid "Only the first path encountering the conflict is reported"
 msgstr ""
 
-#: config/tc-ia64.c:10564
+#: config/tc-ia64.c:10569
 msgid "This is the location of the conflicting usage"
 msgstr ""
 
-#: config/tc-ia64.c:11788
+#: config/tc-ia64.c:11793
 msgid "Can't add stop bit to mark end of instruction group"
 msgstr ""
 
-#: config/tc-ia64.c:11888 read.c:1440 read.c:2206 read.c:2846 read.c:3173
-#: read.c:3204
+#: config/tc-ia64.c:11893 config/tc-score.c:6398 read.c:1442 read.c:2413
+#: read.c:3042 read.c:3375 read.c:3419
 msgid "expected symbol name"
 msgstr ""
 
-#: config/tc-ia64.c:11898 read.c:2216 read.c:2856 read.c:3188 stabs.c:466
+#: config/tc-ia64.c:11903 read.c:2423 read.c:3052 read.c:3403 stabs.c:466
 #, c-format
 msgid "expected comma after \"%s\""
 msgstr ""
 
-#: config/tc-ia64.c:11940
+#: config/tc-ia64.c:11945
 #, c-format
 msgid "`%s' is already the alias of %s `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:11950
+#: config/tc-ia64.c:11955
 #, c-format
 msgid "%s `%s' already has an alias `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:11961
+#: config/tc-ia64.c:11966
 #, c-format
 msgid "inserting \"%s\" into %s alias hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:11969
+#: config/tc-ia64.c:11974
 #, c-format
 msgid "inserting \"%s\" into %s name hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:11988
+#: config/tc-ia64.c:11993
 #, c-format
 msgid "symbol `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ia64.c:12010
+#: config/tc-ia64.c:12015
 #, c-format
 msgid "section `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ip2k.c:158
+#: config/tc-ip2k.c:157
 #, c-format
 msgid "IP2K specific command line options:\n"
 msgstr ""
 
-#: config/tc-ip2k.c:159
+#: config/tc-ip2k.c:158
 #, c-format
 msgid "  -mip2022               restrict to IP2022 insns \n"
 msgstr ""
 
-#: config/tc-ip2k.c:160
+#: config/tc-ip2k.c:159
 #, c-format
 msgid "  -mip2022ext            permit extended IP2022 insn\n"
 msgstr ""
 
-#: config/tc-ip2k.c:274
+#: config/tc-ip2k.c:273
 msgid "md_pcrel_from\n"
 msgstr ""
 
-#: config/tc-m32c.c:128
+#: config/tc-m32c.c:137
 #, c-format
 msgid " M32C specific command line options:\n"
 msgstr ""
 
 #. Pretend that we do not recognise this option.
-#: config/tc-m32r.c:332
+#: config/tc-m32r.c:331
 msgid "Unrecognised option: -hidden"
 msgstr ""
 
-#: config/tc-m32r.c:359 config/tc-sparc.c:593
+#: config/tc-m32r.c:358 config/tc-sparc.c:595
 msgid "Unrecognized option following -K"
 msgstr ""
 
-#: config/tc-m32r.c:374
+#: config/tc-m32r.c:373
 #, c-format
 msgid " M32R specific command line options:\n"
 msgstr ""
 
-#: config/tc-m32r.c:376
+#: config/tc-m32r.c:375
 #, c-format
 msgid ""
 "  -m32r                   disable support for the m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:378
+#: config/tc-m32r.c:377
 #, c-format
 msgid "  -m32rx                  support the extended m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:380
+#: config/tc-m32r.c:379
 #, c-format
 msgid "  -m32r2                  support the extended m32r2 instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:382
+#: config/tc-m32r.c:381
 #, c-format
 msgid "  -EL,-little             produce little endian code and data\n"
 msgstr ""
 
-#: config/tc-m32r.c:384
+#: config/tc-m32r.c:383
 #, c-format
 msgid "  -EB,-big                produce big endian code and data\n"
 msgstr ""
 
-#: config/tc-m32r.c:386
+#: config/tc-m32r.c:385
 #, c-format
 msgid "  -parallel               try to combine instructions in parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:388
+#: config/tc-m32r.c:387
 #, c-format
 msgid "  -no-parallel            disable -parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:390
+#: config/tc-m32r.c:389
 #, c-format
 msgid ""
 "  -no-bitinst             disallow the M32R2's extended bit-field "
 "instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:392
+#: config/tc-m32r.c:391
 #, c-format
 msgid "  -O                      try to optimize code.  Implies -parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:395
+#: config/tc-m32r.c:394
 #, c-format
 msgid ""
 "  -warn-explicit-parallel-conflicts     warn when parallel instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:397
+#: config/tc-m32r.c:396
 #, c-format
 msgid "                                         might violate contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:399
+#: config/tc-m32r.c:398
 #, c-format
 msgid "  -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:401
+#: config/tc-m32r.c:400
 #, c-format
 msgid ""
 "                                         instructions might violate "
 "contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:403
+#: config/tc-m32r.c:402
 #, c-format
 msgid ""
 "  -Wp                     synonym for -warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:405
+#: config/tc-m32r.c:404
 #, c-format
 msgid ""
 "  -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:407
+#: config/tc-m32r.c:406
 #, c-format
 msgid ""
 "  -ignore-parallel-conflicts            do not check parallel instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:409
+#: config/tc-m32r.c:408
 #, c-format
 msgid "                                         fo contraint violations\n"
 msgstr ""
 
-#: config/tc-m32r.c:411
+#: config/tc-m32r.c:410
 #, c-format
 msgid ""
 "  -no-ignore-parallel-conflicts         check parallel instructions for\n"
 msgstr ""
 
-#: config/tc-m32r.c:413
+#: config/tc-m32r.c:412
 #, c-format
 msgid "                                         contraint violations\n"
 msgstr ""
 
-#: config/tc-m32r.c:415
+#: config/tc-m32r.c:414
 #, c-format
 msgid "  -Ip                     synonym for -ignore-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:417
+#: config/tc-m32r.c:416
 #, c-format
 msgid "  -nIp                    synonym for -no-ignore-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:420
+#: config/tc-m32r.c:419
 #, c-format
 msgid ""
 "  -warn-unmatched-high    warn when an (s)high reloc has no matching low "
 "reloc\n"
 msgstr ""
 
-#: config/tc-m32r.c:422
+#: config/tc-m32r.c:421
 #, c-format
 msgid "  -no-warn-unmatched-high do not warn about missing low relocs\n"
 msgstr ""
 
-#: config/tc-m32r.c:424
+#: config/tc-m32r.c:423
 #, c-format
 msgid "  -Wuh                    synonym for -warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:426
+#: config/tc-m32r.c:425
 #, c-format
 msgid "  -Wnuh                   synonym for -no-warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:429
+#: config/tc-m32r.c:428
 #, c-format
 msgid "  -KPIC                   generate PIC\n"
 msgstr ""
 
-#: config/tc-m32r.c:850
+#: config/tc-m32r.c:849
 msgid "instructions write to the same destination register."
 msgstr ""
 
-#: config/tc-m32r.c:858
+#: config/tc-m32r.c:857
 msgid "Instructions do not use parallel execution pipelines."
 msgstr ""
 
-#: config/tc-m32r.c:866
+#: config/tc-m32r.c:865
 msgid "Instructions share the same execution pipeline"
 msgstr ""
 
-#: config/tc-m32r.c:931 config/tc-m32r.c:1045
+#: config/tc-m32r.c:930 config/tc-m32r.c:1044
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:943 config/tc-m32r.c:1057 config/tc-m32r.c:1241
+#: config/tc-m32r.c:942 config/tc-m32r.c:1056 config/tc-m32r.c:1240
 #, c-format
 msgid "instruction '%s' is for the M32R2 only"
 msgstr ""
 
-#: config/tc-m32r.c:956 config/tc-m32r.c:1070 config/tc-m32r.c:1254
+#: config/tc-m32r.c:955 config/tc-m32r.c:1069 config/tc-m32r.c:1253
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:965 config/tc-m32r.c:1077 config/tc-m32r.c:1261
+#: config/tc-m32r.c:964 config/tc-m32r.c:1076 config/tc-m32r.c:1260
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr ""
 
-#: config/tc-m32r.c:974 config/tc-m32r.c:1086
+#: config/tc-m32r.c:973 config/tc-m32r.c:1085
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr ""
 
-#: config/tc-m32r.c:1029 config/tc-m32r.c:1111 config/tc-m32r.c:1318
+#: config/tc-m32r.c:1028 config/tc-m32r.c:1110 config/tc-m32r.c:1317
 msgid "internal error: lookup/get operands failed"
 msgstr ""
 
-#: config/tc-m32r.c:1096
+#: config/tc-m32r.c:1095
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr ""
 
-#: config/tc-m32r.c:1125
+#: config/tc-m32r.c:1124
 #, c-format
 msgid ""
 "%s: output of 1st instruction is the same as an input to 2nd instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1129
+#: config/tc-m32r.c:1128
 #, c-format
 msgid ""
 "%s: output of 2nd instruction is the same as an input to 1st instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1493 config/tc-ppc.c:1773 config/tc-ppc.c:4365
+#: config/tc-m32r.c:1492 config/tc-ppc.c:1832 config/tc-ppc.c:4372
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1503
+#: config/tc-m32r.c:1502
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1517 config/tc-ppc.c:1795 config/tc-ppc.c:2952
-#: config/tc-ppc.c:4389
+#: config/tc-m32r.c:1516 config/tc-ppc.c:1854 config/tc-ppc.c:2993
+#: config/tc-ppc.c:4396
 msgid "ignoring bad alignment"
 msgstr ""
 
-#: config/tc-m32r.c:1529 config/tc-ppc.c:1832 config/tc-v850.c:323
+#: config/tc-m32r.c:1528 config/tc-ppc.c:1891 config/tc-v850.c:322
 msgid "Common alignment not a power of 2"
 msgstr ""
 
-#: config/tc-m32r.c:1544 config/tc-ppc.c:1806 config/tc-ppc.c:4401
+#: config/tc-m32r.c:1543 config/tc-ppc.c:1865 config/tc-ppc.c:4408
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr ""
 
-#: config/tc-m32r.c:1553
+#: config/tc-m32r.c:1552
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-m32r.c:1789
+#: config/tc-m32r.c:1788
 msgid "Addend to unresolved symbol not on word boundary."
 msgstr ""
 
-#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:749
+#: config/tc-m32r.c:1929 config/tc-m32r.c:1982 config/tc-sh.c:747
 msgid "Invalid PIC expression."
 msgstr ""
 
-#: config/tc-m32r.c:2074
+#: config/tc-m32r.c:2073
 msgid "Unmatched high/shigh reloc"
 msgstr ""
 
-#: config/tc-m32r.c:2334 config/tc-sparc.c:3524
+#: config/tc-m32r.c:2333 config/tc-sparc.c:3604
 #, c-format
 msgid "internal error: can't export reloc type %d (`%s')"
 msgstr ""
 
-#: config/tc-m68hc11.c:369
+#: config/tc-m68hc11.c:371
 #, c-format
 msgid ""
 "Motorola 68HC11/68HC12/68HCS12 options:\n"
@@ -5741,8 +6269,8 @@ msgid ""
 "  -mlong                  use 32-bit int ABI\n"
 "  -mshort-double          use 32-bit double ABI\n"
 "  -mlong-double           use 64-bit double ABI (default)\n"
-"  --force-long-branchs    always turn relative branchs into absolute ones\n"
-"  -S,--short-branchs      do not turn relative branchs into absolute ones\n"
+"  --force-long-branches   always turn relative branches into absolute ones\n"
+"  -S,--short-branches     do not turn relative branches into absolute ones\n"
 "                          when the offset is out of range\n"
 "  --strict-direct-mode    do not turn the direct mode into extended mode\n"
 "                          when the instruction does not support direct mode\n"
@@ -5752,56 +6280,56 @@ msgid ""
 "                          (used for testing)\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:415
+#: config/tc-m68hc11.c:417
 #, c-format
 msgid "Default target `%s' is not supported."
 msgstr ""
 
 #. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:433
+#: config/tc-m68hc11.c:435
 #, c-format
 msgid "Name   # Modes  Min ops  Max ops  Modes mask  # Used\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:499
+#: config/tc-m68hc11.c:501
 #, c-format
 msgid "Option `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:721
+#: config/tc-m68hc11.c:723
 msgid "#<imm8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:730
+#: config/tc-m68hc11.c:732
 msgid "#<imm16>"
 msgstr ""
 
-#: config/tc-m68hc11.c:739 config/tc-m68hc11.c:748
+#: config/tc-m68hc11.c:741 config/tc-m68hc11.c:750
 msgid "<imm8>,X"
 msgstr ""
 
-#: config/tc-m68hc11.c:775
+#: config/tc-m68hc11.c:777
 msgid "*<abs8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:787
+#: config/tc-m68hc11.c:789
 msgid "#<mask>"
 msgstr ""
 
-#: config/tc-m68hc11.c:797
+#: config/tc-m68hc11.c:799
 #, c-format
 msgid "symbol%d"
 msgstr ""
 
-#: config/tc-m68hc11.c:799
+#: config/tc-m68hc11.c:801
 msgid "<abs>"
 msgstr ""
 
-#: config/tc-m68hc11.c:818
+#: config/tc-m68hc11.c:820
 msgid "<label>"
 msgstr ""
 
-#: config/tc-m68hc11.c:834
+#: config/tc-m68hc11.c:836
 #, c-format
 msgid ""
 "# Example of `%s' instructions\n"
@@ -5809,862 +6337,902 @@ msgid ""
 "_start:\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:881
+#: config/tc-m68hc11.c:883
 #, c-format
 msgid "Instruction `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:886
+#: config/tc-m68hc11.c:888
 #, c-format
 msgid "Instruction formats for `%s':"
 msgstr ""
 
-#: config/tc-m68hc11.c:1016
+#: config/tc-m68hc11.c:1018
 #, c-format
 msgid "Immediate operand is not allowed for operand %d."
 msgstr ""
 
-#: config/tc-m68hc11.c:1060
+#: config/tc-m68hc11.c:1062
 msgid "Indirect indexed addressing is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1080
+#: config/tc-m68hc11.c:1082
 msgid "Spurious `,' or bad indirect register addressing mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1102
+#: config/tc-m68hc11.c:1104
 msgid "Missing second register or offset for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1112
+#: config/tc-m68hc11.c:1114
 msgid "Missing second register for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1128
+#: config/tc-m68hc11.c:1130
 msgid "Missing `]' to close indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1173
+#: config/tc-m68hc11.c:1175
 msgid "Illegal operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1178
+#: config/tc-m68hc11.c:1180
 msgid "Missing operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1231
+#: config/tc-m68hc11.c:1233
 msgid "Pre-increment mode is not valid for 68HC11"
 msgstr ""
 
-#: config/tc-m68hc11.c:1244
+#: config/tc-m68hc11.c:1246
 msgid "Wrong register in register indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1252
+#: config/tc-m68hc11.c:1254
 msgid "Missing `]' to close register indirect operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1272
+#: config/tc-m68hc11.c:1274
 msgid "Post-decrement mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1280
+#: config/tc-m68hc11.c:1282
 msgid "Post-increment mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1298
+#: config/tc-m68hc11.c:1300
 msgid "Invalid indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1390
+#: config/tc-m68hc11.c:1392
 #, c-format
 msgid "Trap id `%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:1394
+#: config/tc-m68hc11.c:1396
 msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
 msgstr ""
 
-#: config/tc-m68hc11.c:1401
+#: config/tc-m68hc11.c:1403
 #, c-format
 msgid "Operand out of 8-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1408
+#: config/tc-m68hc11.c:1410
 msgid "The trap id must be a constant."
 msgstr ""
 
-#: config/tc-m68hc11.c:1443
+#: config/tc-m68hc11.c:1445
 #, c-format
 msgid "Operand `%x' not recognized in fixup8."
 msgstr ""
 
-#: config/tc-m68hc11.c:1460 config/tc-m68hc11.c:1509
+#: config/tc-m68hc11.c:1462 config/tc-m68hc11.c:1511
 #, c-format
 msgid "Operand out of 16-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1492 config/tc-m68hc11.c:1525
+#: config/tc-m68hc11.c:1494 config/tc-m68hc11.c:1527
 #, c-format
 msgid "Operand `%x' not recognized in fixup16."
 msgstr ""
 
-#: config/tc-m68hc11.c:1542
+#: config/tc-m68hc11.c:1544
 #, c-format
 msgid "Unexpected branch conversion with `%x'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1633 config/tc-m68hc11.c:1771
+#: config/tc-m68hc11.c:1635 config/tc-m68hc11.c:1773
 #, c-format
 msgid "Operand out of range for a relative branch: `%ld'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1739
+#: config/tc-m68hc11.c:1741
 msgid "Invalid register for dbcc/tbcc instruction."
 msgstr ""
 
-#: config/tc-m68hc11.c:1827
+#: config/tc-m68hc11.c:1829
 #, c-format
 msgid "Increment/decrement value is out of range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1838
+#: config/tc-m68hc11.c:1840
 msgid "Expecting a register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1853
+#: config/tc-m68hc11.c:1855
 msgid "Invalid register for post/pre increment."
 msgstr ""
 
-#: config/tc-m68hc11.c:1883
+#: config/tc-m68hc11.c:1885
 msgid "Invalid register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1890
+#: config/tc-m68hc11.c:1892
 #, c-format
 msgid "Offset out of 16-bit range: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:1895
+#: config/tc-m68hc11.c:1897
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:2001
+#: config/tc-m68hc11.c:2003
 msgid "Expecting register D for indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2003
+#: config/tc-m68hc11.c:2005
 msgid "Indexed indirect mode is not allowed for movb/movw."
 msgstr ""
 
-#: config/tc-m68hc11.c:2020
+#: config/tc-m68hc11.c:2022
 msgid "Invalid accumulator register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2045
+#: config/tc-m68hc11.c:2047
 msgid "Invalid indexed register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2053
+#: config/tc-m68hc11.c:2055
 msgid "Addressing mode not implemented yet."
 msgstr ""
 
-#: config/tc-m68hc11.c:2066
+#: config/tc-m68hc11.c:2068
 msgid "Invalid source register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2068
+#: config/tc-m68hc11.c:2070
 msgid "Invalid source register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2073
+#: config/tc-m68hc11.c:2075
 msgid "Invalid destination register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2075
+#: config/tc-m68hc11.c:2077
 msgid "Invalid destination register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2171
+#: config/tc-m68hc11.c:2173
 msgid "Invalid indexed register, expecting register X."
 msgstr ""
 
-#: config/tc-m68hc11.c:2173
+#: config/tc-m68hc11.c:2175
 msgid "Invalid indexed register, expecting register Y."
 msgstr ""
 
-#: config/tc-m68hc11.c:2479
+#: config/tc-m68hc11.c:2481
 msgid "No instruction or missing opcode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2544
+#: config/tc-m68hc11.c:2546
 #, c-format
 msgid "Opcode `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:2566
+#: config/tc-m68hc11.c:2568
 #, c-format
 msgid "Garbage at end of instruction: `%s'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2589
+#: config/tc-m68hc11.c:2591
 #, c-format
 msgid "Invalid operand for `%s'"
 msgstr ""
 
-#: config/tc-m68hc11.c:2640
+#: config/tc-m68hc11.c:2642
 #, c-format
 msgid "Invalid mode: %s\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:2700
+#: config/tc-m68hc11.c:2702
 msgid "bad .relax format"
 msgstr ""
 
-#: config/tc-m68hc11.c:2744
+#: config/tc-m68hc11.c:2746
 #, c-format
 msgid "Relocation %d is not supported by object file format."
 msgstr ""
 
-#: config/tc-m68hc11.c:3023
+#: config/tc-m68hc11.c:3025
 msgid "bra or bsr with undefined symbol."
 msgstr ""
 
-#: config/tc-m68hc11.c:3126 config/tc-m68hc11.c:3183
+#: config/tc-m68hc11.c:3128 config/tc-m68hc11.c:3185
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:3242
+#: config/tc-m68hc11.c:3244
 msgid "Expression too complex."
 msgstr ""
 
-#: config/tc-m68hc11.c:3275
+#: config/tc-m68hc11.c:3277
 msgid "Value out of 16-bit range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3293
+#: config/tc-m68hc11.c:3295
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr ""
 
-#: config/tc-m68hc11.c:3300
+#: config/tc-m68hc11.c:3302
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3313
+#: config/tc-m68hc11.c:3315
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld"
 msgstr ""
 
-#: config/tc-m68hc11.c:3329
+#: config/tc-m68hc11.c:3331
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr ""
 
-#: config/tc-m68k.c:696
-msgid "no matching ColdFire architectures found"
-msgstr ""
-
-#: config/tc-m68k.c:710
-msgid " or "
-msgstr ""
-
-#: config/tc-m68k.c:715
-msgid ", or "
-msgstr ""
-
-#: config/tc-m68k.c:732
-msgid ", or aliases"
-msgstr ""
-
-#: config/tc-m68k.c:843
+#: config/tc-m68k.c:1009
 #, c-format
 msgid "Can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-m68k.c:845
+#: config/tc-m68k.c:1011
 #, c-format
 msgid "Can not do %d byte pc-relative pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:850
+#: config/tc-m68k.c:1016
 #, c-format
 msgid "Can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-m68k.c:852
+#: config/tc-m68k.c:1018
 #, c-format
 msgid "Can not do %d byte pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:915
+#: config/tc-m68k.c:1083
 #, c-format
 msgid "Unable to produce reloc against symbol '%s'"
 msgstr ""
 
-#: config/tc-m68k.c:959 config/tc-vax.c:3435
+#: config/tc-m68k.c:1127 config/tc-vax.c:2366
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr ""
 
-#: config/tc-m68k.c:1050 config/tc-vax.c:1890
+#: config/tc-m68k.c:1226 config/tc-vax.c:1876
 msgid "No operator"
 msgstr ""
 
-#: config/tc-m68k.c:1080 config/tc-vax.c:1907
+#: config/tc-m68k.c:1256 config/tc-vax.c:1892
 msgid "Unknown operator"
 msgstr ""
 
-#: config/tc-m68k.c:1944
+#: config/tc-m68k.c:2143
 msgid "invalid instruction for this architecture; needs "
 msgstr ""
 
-#: config/tc-m68k.c:1950
+#: config/tc-m68k.c:2147
 msgid "ColdFire ISA_A"
 msgstr ""
 
-#: config/tc-m68k.c:1958
+#: config/tc-m68k.c:2150
 msgid "ColdFire hardware divide"
 msgstr ""
 
-#: config/tc-m68k.c:1966
+#: config/tc-m68k.c:2153
 msgid "ColdFire ISA_A+"
 msgstr ""
 
-#: config/tc-m68k.c:1974
+#: config/tc-m68k.c:2156
 msgid "ColdFire ISA_B"
 msgstr ""
 
-#: config/tc-m68k.c:1982
+#: config/tc-m68k.c:2159
 msgid "ColdFire fpu"
 msgstr ""
 
-#: config/tc-m68k.c:1989
-msgid "fpu (68040, 68060 or 68881/68882)"
+#: config/tc-m68k.c:2162
+msgid "M68K fpu"
 msgstr ""
 
-#: config/tc-m68k.c:1992
-msgid "mmu (68030 or 68851)"
+#: config/tc-m68k.c:2165
+msgid "M68K mmu"
 msgstr ""
 
-#: config/tc-m68k.c:1995
+#: config/tc-m68k.c:2168
 msgid "68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:1998
+#: config/tc-m68k.c:2171
 msgid "68000 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2001
+#: config/tc-m68k.c:2174
 msgid "68010 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2029
+#: config/tc-m68k.c:2227
 msgid "operands mismatch"
 msgstr ""
 
-#: config/tc-m68k.c:2090 config/tc-m68k.c:2096 config/tc-m68k.c:2102
-#: config/tc-mmix.c:2488 config/tc-mmix.c:2512
+#: config/tc-m68k.c:2290 config/tc-m68k.c:2296 config/tc-m68k.c:2302
+#: config/tc-mmix.c:2487 config/tc-mmix.c:2511
 msgid "operand out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2159
+#: config/tc-m68k.c:2359
 #, c-format
 msgid "Bignum too big for %c format; truncated"
 msgstr ""
 
-#: config/tc-m68k.c:2236
+#: config/tc-m68k.c:2436
 msgid "displacement too large for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2347
+#: config/tc-m68k.c:2547
 msgid ""
 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2352
+#: config/tc-m68k.c:2552
 msgid "invalid index size for coldfire"
 msgstr ""
 
-#: config/tc-m68k.c:2405
+#: config/tc-m68k.c:2605
 msgid "Forcing byte displacement"
 msgstr ""
 
-#: config/tc-m68k.c:2407
+#: config/tc-m68k.c:2607
 msgid "byte displacement out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2455 config/tc-m68k.c:2493
+#: config/tc-m68k.c:2655 config/tc-m68k.c:2693
 msgid "invalid operand mode for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2479 config/tc-m68k.c:2513
+#: config/tc-m68k.c:2679 config/tc-m68k.c:2713
 msgid ":b not permitted; defaulting to :w"
 msgstr ""
 
-#: config/tc-m68k.c:2590
+#: config/tc-m68k.c:2790
 msgid "unsupported byte value; use a different suffix"
 msgstr ""
 
-#: config/tc-m68k.c:2605
+#: config/tc-m68k.c:2805
 msgid "unknown/incorrect operand"
 msgstr ""
 
-#: config/tc-m68k.c:2648 config/tc-m68k.c:2656 config/tc-m68k.c:2663
-#: config/tc-m68k.c:2670
+#: config/tc-m68k.c:2848 config/tc-m68k.c:2856 config/tc-m68k.c:2863
+#: config/tc-m68k.c:2870
 msgid "out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2716
-msgid "Can't use long branches on 68000/68010/5200"
+#: config/tc-m68k.c:2942
+msgid "Can't use long branches on this architecture"
 msgstr ""
 
-#: config/tc-m68k.c:2833
+#: config/tc-m68k.c:3047
 msgid "Expression out of range, using 0"
 msgstr ""
 
-#: config/tc-m68k.c:3014 config/tc-m68k.c:3030
+#: config/tc-m68k.c:3238 config/tc-m68k.c:3254
 msgid "Floating point register in register list"
 msgstr ""
 
-#: config/tc-m68k.c:3020
+#: config/tc-m68k.c:3244
 msgid "Wrong register in floating-point reglist"
 msgstr ""
 
-#: config/tc-m68k.c:3036
+#: config/tc-m68k.c:3260
 msgid "incorrect register in reglist"
 msgstr ""
 
-#: config/tc-m68k.c:3042
+#: config/tc-m68k.c:3266
 msgid "wrong register in floating-point reglist"
 msgstr ""
 
 #. ERROR.
-#: config/tc-m68k.c:3505
+#: config/tc-m68k.c:3729
 msgid "Extra )"
 msgstr ""
 
 #. ERROR.
-#: config/tc-m68k.c:3516
+#: config/tc-m68k.c:3740
 msgid "Missing )"
 msgstr ""
 
-#: config/tc-m68k.c:3533
+#: config/tc-m68k.c:3757
 msgid "Missing operand"
 msgstr ""
 
-#: config/tc-m68k.c:3890
+#: config/tc-m68k.c:4074
+#, c-format
+msgid "unrecognized default cpu `%s'"
+msgstr ""
+
+#: config/tc-m68k.c:4128
 #, c-format
 msgid "%s -- statement `%s' ignored"
 msgstr ""
 
-#: config/tc-m68k.c:3939
+#: config/tc-m68k.c:4177
 #, c-format
 msgid "Don't know how to figure width of %c in md_assemble()"
 msgstr ""
 
-#: config/tc-m68k.c:4108
+#: config/tc-m68k.c:4346
 #, c-format
 msgid "Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"
 msgstr ""
 
-#: config/tc-m68k.c:4159 config/tc-m68k.c:4198
+#: config/tc-m68k.c:4397 config/tc-m68k.c:4436
 #, c-format
 msgid "Internal Error: Can't find %s in hash table"
 msgstr ""
 
-#: config/tc-m68k.c:4162 config/tc-m68k.c:4201
+#: config/tc-m68k.c:4400 config/tc-m68k.c:4439
 #, c-format
 msgid "Internal Error: Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-m68k.c:4282
-msgid "architecture not yet selected: defaulting to 68020"
+#: config/tc-m68k.c:4564
+#, c-format
+msgid "text label `%s' aligned to odd boundary"
 msgstr ""
 
-#: config/tc-m68k.c:4342
+#: config/tc-m68k.c:4764
 #, c-format
-msgid "unrecognized default cpu `%s' ???"
+msgid "value %ld out of range"
 msgstr ""
 
-#: config/tc-m68k.c:4353
-msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
+#: config/tc-m68k.c:4778
+msgid "invalid byte branch offset"
 msgstr ""
 
-#: config/tc-m68k.c:4370
-msgid "options for 68881 and no-68881 both given"
+#: config/tc-m68k.c:4814
+msgid "short branch with zero offset: use :w"
 msgstr ""
 
-#: config/tc-m68k.c:4373
-msgid "options for 68851 and no-68851 both given"
+#: config/tc-m68k.c:4839
+msgid "Conversion of PC relative BSR to absolute JSR"
 msgstr ""
 
-#: config/tc-m68k.c:4434
-#, c-format
-msgid "text label `%s' aligned to odd boundary"
+#: config/tc-m68k.c:4850
+msgid "Conversion of PC relative branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4638
-msgid "invalid byte branch offset"
+#: config/tc-m68k.c:4867 config/tc-m68k.c:4928
+msgid "Conversion of PC relative conditional branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4674
-msgid "short branch with zero offset: use :w"
+#: config/tc-m68k.c:4908
+msgid "Conversion of DBcc to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4698
-msgid "Tried to convert PC relative BSR to absolute JSR"
+#: config/tc-m68k.c:4992
+msgid "Conversion of PC relative displacement to absolute"
 msgstr ""
 
-#: config/tc-m68k.c:4708 config/tc-m68k.c:5054
+#: config/tc-m68k.c:5204
 msgid "Tried to convert PC relative branch to absolute jump"
 msgstr ""
 
-#: config/tc-m68k.c:4724 config/tc-m68k.c:4783 config/tc-m68k.c:4847
-msgid "Tried to convert PC relative conditional branch to absolute jump"
-msgstr ""
-
-#: config/tc-m68k.c:4764
-msgid "Tried to convert DBcc to absolute jump"
-msgstr ""
-
-#: config/tc-m68k.c:5098 config/tc-m68k.c:5109 config/tc-m68k.c:5149
+#: config/tc-m68k.c:5248 config/tc-m68k.c:5259 config/tc-m68k.c:5299
 msgid "expression out of range: defaulting to 1"
 msgstr ""
 
-#: config/tc-m68k.c:5141
+#: config/tc-m68k.c:5291
 msgid "expression out of range: defaulting to 0"
 msgstr ""
 
-#: config/tc-m68k.c:5182 config/tc-m68k.c:5194
+#: config/tc-m68k.c:5332 config/tc-m68k.c:5344
 #, c-format
 msgid "Can't deal with expression; defaulting to %ld"
 msgstr ""
 
-#: config/tc-m68k.c:5208
+#: config/tc-m68k.c:5358
 msgid "expression doesn't fit in BYTE"
 msgstr ""
 
-#: config/tc-m68k.c:5212
+#: config/tc-m68k.c:5362
 msgid "expression doesn't fit in WORD"
 msgstr ""
 
-#: config/tc-m68k.c:5299
+#: config/tc-m68k.c:5449
 #, c-format
 msgid "%s: unrecognized processor name"
 msgstr ""
 
-#: config/tc-m68k.c:5363
+#: config/tc-m68k.c:5510
 msgid "bad coprocessor id"
 msgstr ""
 
-#: config/tc-m68k.c:5369
+#: config/tc-m68k.c:5516
 msgid "unrecognized fopt option"
 msgstr ""
 
-#: config/tc-m68k.c:5502
+#: config/tc-m68k.c:5649
 #, c-format
 msgid "option `%s' may not be negated"
 msgstr ""
 
-#: config/tc-m68k.c:5513
+#: config/tc-m68k.c:5660
 #, c-format
 msgid "option `%s' not recognized"
 msgstr ""
 
-#: config/tc-m68k.c:5542
+#: config/tc-m68k.c:5689
 msgid "bad format of OPT NEST=depth"
 msgstr ""
 
-#: config/tc-m68k.c:5598
+#: config/tc-m68k.c:5745
 msgid "missing label"
 msgstr ""
 
-#: config/tc-m68k.c:5622 config/tc-m68k.c:5651
+#: config/tc-m68k.c:5769 config/tc-m68k.c:5798
 msgid "bad register list"
 msgstr ""
 
-#: config/tc-m68k.c:5624
+#: config/tc-m68k.c:5771
 #, c-format
 msgid "bad register list: %s"
 msgstr ""
 
-#: config/tc-m68k.c:5722
+#: config/tc-m68k.c:5869
 msgid "restore without save"
 msgstr ""
 
-#: config/tc-m68k.c:5876 config/tc-m68k.c:6246
+#: config/tc-m68k.c:6023 config/tc-m68k.c:6393
 msgid "syntax error in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5921
+#: config/tc-m68k.c:6068
 msgid "missing condition code in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5992
+#: config/tc-m68k.c:6139
 #, c-format
 msgid ""
 "Condition <%c%c> in structured control directive can not be encoded correctly"
 msgstr ""
 
-#: config/tc-m68k.c:6288
+#: config/tc-m68k.c:6435
 msgid "missing then"
 msgstr ""
 
-#: config/tc-m68k.c:6369
+#: config/tc-m68k.c:6516
 msgid "else without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6402
+#: config/tc-m68k.c:6549
 msgid "endi without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6442
+#: config/tc-m68k.c:6589
 msgid "break outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6480
+#: config/tc-m68k.c:6627
 msgid "next outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6531
+#: config/tc-m68k.c:6678
 msgid "missing ="
 msgstr ""
 
-#: config/tc-m68k.c:6569
+#: config/tc-m68k.c:6716
 msgid "missing to or downto"
 msgstr ""
 
-#: config/tc-m68k.c:6605 config/tc-m68k.c:6639 config/tc-m68k.c:6853
+#: config/tc-m68k.c:6752 config/tc-m68k.c:6786 config/tc-m68k.c:7000
 msgid "missing do"
 msgstr ""
 
-#: config/tc-m68k.c:6740
+#: config/tc-m68k.c:6887
 msgid "endf without for"
 msgstr ""
 
-#: config/tc-m68k.c:6794
+#: config/tc-m68k.c:6941
 msgid "until without repeat"
 msgstr ""
 
-#: config/tc-m68k.c:6888
+#: config/tc-m68k.c:7035
 msgid "endw without while"
 msgstr ""
 
-#: config/tc-m68k.c:7050
+#: config/tc-m68k.c:7068 config/tc-m68k.c:7096
+msgid "already assembled instructions"
+msgstr ""
+
+#: config/tc-m68k.c:7173
+#, c-format
+msgid "`%s' is deprecated, use `%s'"
+msgstr ""
+
+#: config/tc-m68k.c:7192
+#, c-format
+msgid "cpu `%s' unrecognized"
+msgstr ""
+
+#: config/tc-m68k.c:7198
+#, c-format
+msgid "already selected `%s' processor"
+msgstr ""
+
+#: config/tc-m68k.c:7218
+#, c-format
+msgid "architecture `%s' unrecognized"
+msgstr ""
+
+#: config/tc-m68k.c:7224
+#, c-format
+msgid "already selected `%s' architecture"
+msgstr ""
+
+#: config/tc-m68k.c:7247
 #, c-format
-msgid "unrecognized architecture specification `%s'"
+msgid "extension `%s' unrecognized"
 msgstr ""
 
-#: config/tc-m68k.c:7143
+#: config/tc-m68k.c:7365
+#, c-format
+msgid "option `-A%s' is deprecated: use `-%s'"
+msgstr ""
+
+#: config/tc-m68k.c:7398
+msgid "architecture features both enabled and disabled"
+msgstr ""
+
+#: config/tc-m68k.c:7425
+msgid "selected processor does not have all features of selected architecture"
+msgstr ""
+
+#: config/tc-m68k.c:7434
+msgid "m68k and cf features both selected"
+msgstr ""
+
+#: config/tc-m68k.c:7446
+msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
+msgstr ""
+
+#: config/tc-m68k.c:7480
 #, c-format
 msgid ""
-"680X0 options:\n"
-"-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
-"-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
-"-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
-"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
-"\t\t\tspecify variant of 680X0 architecture [default %s]\n"
-"-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
-"\t\t\ttarget has/lacks floating-point coprocessor\n"
-"\t\t\t[default yes for 68020, 68030, and cpu32]\n"
+"-march=<arch>\t\tset architecture\n"
+"-mcpu=<cpu>\t\tset cpu [default %s]\n"
 msgstr ""
 
-#: config/tc-m68k.c:7155
+#: config/tc-m68k.c:7485
+#, c-format
+msgid "-m[no-]%-16s enable/disable%s architecture extension\n"
+msgstr ""
+
+#: config/tc-m68k.c:7491
 #, c-format
 msgid ""
-"-m68851 | -mno-68851\n"
-"\t\t\ttarget has/lacks memory-management unit coprocessor\n"
-"\t\t\t[default yes for 68020 and up]\n"
+"-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
 "-pic, -k\t\tgenerate position independent code\n"
 "-S\t\t\tturn jbsr into jsr\n"
 "--pcrel                 never turn PC-relative branches into absolute jumps\n"
 "--register-prefix-optional\n"
 "\t\t\trecognize register names without prefix character\n"
 "--bitwise-or\t\tdo not treat `|' as a comment character\n"
-msgstr ""
-
-#: config/tc-m68k.c:7165
-#, c-format
-msgid ""
 "--base-size-default-16\tbase reg without size is 16 bits\n"
 "--base-size-default-32\tbase reg without size is 32 bits (default)\n"
 "--disp-size-default-16\tdisplacement with unknown size is 16 bits\n"
 "--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n"
 msgstr ""
 
-#: config/tc-m68k.c:7200
+#: config/tc-m68k.c:7505
+#, c-format
+msgid "Architecture variants are: "
+msgstr ""
+
+#: config/tc-m68k.c:7514
+#, c-format
+msgid "Processor variants are: "
+msgstr ""
+
+#: config/tc-m68k.c:7521 config/tc-xtensa.c:6029
+#, c-format
+msgid "\n"
+msgstr ""
+
+#: config/tc-m68k.c:7552
 #, c-format
 msgid "Error %s in %s\n"
 msgstr ""
 
-#: config/tc-m68k.c:7204
+#: config/tc-m68k.c:7556
 #, c-format
 msgid "Opcode(%d.%s): "
 msgstr ""
 
-#: config/tc-mcore.c:524
+#: config/tc-m68k.c:7715
+msgid "Not a defined coldfire architecture"
+msgstr ""
+
+#: config/tc-mcore.c:521
 #, c-format
 msgid "register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:606
+#: config/tc-mcore.c:603
 #, c-format
 msgid "control register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:642
+#: config/tc-mcore.c:639
 msgid "bad/missing psr specifier"
 msgstr ""
 
-#: config/tc-mcore.c:692
+#: config/tc-mcore.c:689
 msgid "more than 65K literal pools"
 msgstr ""
 
-#: config/tc-mcore.c:746
+#: config/tc-mcore.c:743
 msgid "missing ']'"
 msgstr ""
 
-#: config/tc-mcore.c:785
+#: config/tc-mcore.c:782
 msgid "operand must be a constant"
 msgstr ""
 
-#: config/tc-mcore.c:787
+#: config/tc-mcore.c:784
 #, c-format
 msgid "operand must be absolute in range %u..%u, not %ld"
 msgstr ""
 
-#: config/tc-mcore.c:822
+#: config/tc-mcore.c:819
 msgid "operand must be a multiple of 4"
 msgstr ""
 
-#: config/tc-mcore.c:829
+#: config/tc-mcore.c:826
 msgid "operand must be a multiple of 2"
 msgstr ""
 
-#: config/tc-mcore.c:843 config/tc-mcore.c:1359 config/tc-mcore.c:1413
+#: config/tc-mcore.c:840 config/tc-mcore.c:1356 config/tc-mcore.c:1410
 msgid "base register expected"
 msgstr ""
 
-#: config/tc-mcore.c:891
+#: config/tc-mcore.c:888
 #, c-format
 msgid "unknown opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:934
+#: config/tc-mcore.c:931
 msgid "invalid register: r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:983 config/tc-mcore.c:1564
+#: config/tc-mcore.c:980 config/tc-mcore.c:1561
 msgid "M340 specific opcode used when assembling for M210"
 msgstr ""
 
-#: config/tc-mcore.c:1001 config/tc-mcore.c:1041 config/tc-mcore.c:1060
-#: config/tc-mcore.c:1079 config/tc-mcore.c:1107 config/tc-mcore.c:1136
-#: config/tc-mcore.c:1173 config/tc-mcore.c:1208 config/tc-mcore.c:1227
-#: config/tc-mcore.c:1246 config/tc-mcore.c:1280 config/tc-mcore.c:1305
-#: config/tc-mcore.c:1362 config/tc-mcore.c:1416 config/tc-mcore.c:1452
-#: config/tc-mcore.c:1511 config/tc-mcore.c:1533 config/tc-mcore.c:1556
+#: config/tc-mcore.c:998 config/tc-mcore.c:1038 config/tc-mcore.c:1057
+#: config/tc-mcore.c:1076 config/tc-mcore.c:1104 config/tc-mcore.c:1133
+#: config/tc-mcore.c:1170 config/tc-mcore.c:1205 config/tc-mcore.c:1224
+#: config/tc-mcore.c:1243 config/tc-mcore.c:1277 config/tc-mcore.c:1302
+#: config/tc-mcore.c:1359 config/tc-mcore.c:1413 config/tc-mcore.c:1449
+#: config/tc-mcore.c:1508 config/tc-mcore.c:1530 config/tc-mcore.c:1553
 msgid "second operand missing"
 msgstr ""
 
-#: config/tc-mcore.c:1017
+#: config/tc-mcore.c:1014
 msgid "destination register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1038
+#: config/tc-mcore.c:1035
 msgid "source register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1102 config/tc-mcore.c:1159
+#: config/tc-mcore.c:1099 config/tc-mcore.c:1156
 msgid "immediate is not a power of two"
 msgstr ""
 
-#: config/tc-mcore.c:1130
+#: config/tc-mcore.c:1127
 msgid "translating bgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1167
+#: config/tc-mcore.c:1164
 msgid "translating mgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1199
+#: config/tc-mcore.c:1196
 msgid "translating bmaski to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1275
+#: config/tc-mcore.c:1272
 #, c-format
 msgid "displacement too large (%d)"
 msgstr ""
 
-#: config/tc-mcore.c:1289
+#: config/tc-mcore.c:1286
 msgid "Invalid register: r0 and r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:1320
+#: config/tc-mcore.c:1317
 msgid "bad starting register: r0 and r15 invalid"
 msgstr ""
 
-#: config/tc-mcore.c:1333
+#: config/tc-mcore.c:1330
 msgid "ending register must be r15"
 msgstr ""
 
-#: config/tc-mcore.c:1353
+#: config/tc-mcore.c:1350
 msgid "bad base register: must be r0"
 msgstr ""
 
-#: config/tc-mcore.c:1371
+#: config/tc-mcore.c:1368
 msgid "first register must be r4"
 msgstr ""
 
-#: config/tc-mcore.c:1382
+#: config/tc-mcore.c:1379
 msgid "last register must be r7"
 msgstr ""
 
-#: config/tc-mcore.c:1419
+#: config/tc-mcore.c:1416
 msgid "reg-reg expected"
 msgstr ""
 
-#: config/tc-mcore.c:1530
+#: config/tc-mcore.c:1527
 msgid "second operand must be 1"
 msgstr ""
 
-#: config/tc-mcore.c:1551
+#: config/tc-mcore.c:1548
 msgid "zero used as immediate value"
 msgstr ""
 
-#: config/tc-mcore.c:1578
+#: config/tc-mcore.c:1575
 msgid "duplicated psr bit specifier"
 msgstr ""
 
-#: config/tc-mcore.c:1584
+#: config/tc-mcore.c:1581
 msgid "`af' must appear alone"
 msgstr ""
 
-#: config/tc-mcore.c:1591
+#: config/tc-mcore.c:1588
 #, c-format
 msgid "unimplemented opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:1600
+#: config/tc-mcore.c:1597
 #, c-format
 msgid "ignoring operands: %s "
 msgstr ""
 
-#: config/tc-mcore.c:1665
+#: config/tc-mcore.c:1662
 msgid "Bad call to MD_NTOF()"
 msgstr ""
 
-#: config/tc-mcore.c:1736
+#: config/tc-mcore.c:1733
 #, c-format
 msgid "unrecognised cpu type '%s'"
 msgstr ""
 
-#: config/tc-mcore.c:1754
+#: config/tc-mcore.c:1751
 #, c-format
 msgid ""
 "MCORE specific options:\n"
@@ -6675,671 +7243,763 @@ msgid ""
 "  -EL                     assemble for a little endian system\n"
 msgstr ""
 
-#: config/tc-mcore.c:1772
+#: config/tc-mcore.c:1769
 msgid "failed sanity check: short_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1782
+#: config/tc-mcore.c:1779
 msgid "failed sanity check: long_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1808
+#: config/tc-mcore.c:1805
 #, c-format
 msgid "odd displacement at %x"
 msgstr ""
 
-#: config/tc-mcore.c:1990
+#: config/tc-mcore.c:1987
 msgid "unknown"
 msgstr ""
 
-#: config/tc-mcore.c:2017
+#: config/tc-mcore.c:2014
 #, c-format
 msgid "odd distance branch (0x%lx bytes)"
 msgstr ""
 
-#: config/tc-mcore.c:2021
+#: config/tc-mcore.c:2018
 #, c-format
 msgid "pcrel for branch to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2041
+#: config/tc-mcore.c:2038
 #, c-format
 msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2053
+#: config/tc-mcore.c:2050
 #, c-format
 msgid "pcrel for loopt too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2263
+#: config/tc-mcore.c:2246
 #, c-format
 msgid "Can not do %d byte %srelocation"
 msgstr ""
 
-#: config/tc-mcore.c:2265
+#: config/tc-mcore.c:2248
 msgid "pc-relative"
 msgstr ""
 
+#: config/tc-mep.c:300
+#, c-format
+msgid ""
+"MeP specific command line options:\n"
+"  -EB                     assemble for a big endian system (default)\n"
+"  -EL                     assemble for a little endian system\n"
+"  -mconfig=<name>         specify a chip configuration to use\n"
+"  -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n"
+"  -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n"
+"  -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n"
+"                          enable/disable the given opcodes\n"
+"\n"
+"  If -mconfig is given, the other -m options modify it.  Otherwise,\n"
+"  if no -m options are given, all core opcodes are enabled;\n"
+"  if any enabling -m options are given, only those are enabled;\n"
+"  if only disabling -m options are given, only those are disabled.\n"
+msgstr ""
+
+#. There are no insns in the queue and a plus is present.
+#. This is a syntax error.  Let's not tolerate this.
+#. We can relax this later if necessary.
+#: config/tc-mep.c:1007
+msgid "Invalid use of parallelization operator."
+msgstr ""
+
+#: config/tc-mep.c:1049
+msgid "Leading plus sign not allowed in core mode"
+msgstr ""
+
+#: config/tc-mep.c:1530
+#, c-format
+msgid "Don't know how to relocate plain operands of type %s"
+msgstr ""
+
+#: config/tc-mep.c:1540
+#, c-format
+msgid "Perhaps you are missing %%tpoff()?"
+msgstr ""
+
+#: config/tc-mep.c:1646
+msgid "Unmatched high relocation"
+msgstr ""
+
+#: config/tc-mep.c:1772
+msgid "Bad .section directive: want a,v,w,x,M,S in string"
+msgstr ""
+
+#: config/tc-mep.c:1830
+msgid ".vliw unavailable when VLIW is disabled."
+msgstr ""
+
 #. Prototypes for static functions.
-#: config/tc-mips.c:957
+#: config/tc-mips.c:988
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr ""
 
-#: config/tc-mips.c:1443
+#: config/tc-mips.c:1745
+msgid "-G may not be used in position-independent code"
+msgstr ""
+
+#: config/tc-mips.c:1792
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr ""
 
-#: config/tc-mips.c:1451
+#: config/tc-mips.c:1800
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr ""
 
-#: config/tc-mips.c:1652
+#: config/tc-mips.c:1972
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr ""
 
-#: config/tc-mips.c:2327 config/tc-mips.c:13480
+#: config/tc-mips.c:2681 config/tc-mips.c:14040
 msgid "extended instruction in delay slot"
 msgstr ""
 
-#: config/tc-mips.c:2391 config/tc-mips.c:2401
+#: config/tc-mips.c:2745 config/tc-mips.c:2752
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2394 config/tc-mips.c:2404
+#: config/tc-mips.c:2762 config/tc-mips.c:3524
+#, c-format
+msgid "branch to misaligned address (0x%lx)"
+msgstr ""
+
+#: config/tc-mips.c:2767 config/tc-mips.c:3527
 #, c-format
-msgid "jump address range overflow (0x%lx)"
+msgid "branch address range overflow (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2893
+#: config/tc-mips.c:3252
 msgid ""
 "Macro instruction expanded into multiple instructions in a branch delay slot"
 msgstr ""
 
-#: config/tc-mips.c:2896
+#: config/tc-mips.c:3255
 msgid "Macro instruction expanded into multiple instructions"
 msgstr ""
 
-#: config/tc-mips.c:3414 config/tc-mips.c:7338 config/tc-mips.c:7362
-#: config/tc-mips.c:7435 config/tc-mips.c:7458
+#: config/tc-mips.c:3796 config/tc-mips.c:7741 config/tc-mips.c:7765
+#: config/tc-mips.c:7838 config/tc-mips.c:7861
 msgid "operand overflow"
 msgstr ""
 
-#: config/tc-mips.c:3433 config/tc-mips.c:4033 config/tc-mips.c:6734
-#: config/tc-mips.c:7525
+#: config/tc-mips.c:3815 config/tc-mips.c:4415 config/tc-mips.c:7137
+#: config/tc-mips.c:7928
 msgid "Macro used $at after \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:3462
+#: config/tc-mips.c:3844
 msgid "unsupported large constant"
 msgstr ""
 
-#: config/tc-mips.c:3464
+#: config/tc-mips.c:3846
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr ""
 
-#: config/tc-mips.c:3597 config/tc-mips.c:5844 config/tc-mips.c:6438
+#: config/tc-mips.c:3979 config/tc-mips.c:6249 config/tc-mips.c:6841
 #, c-format
 msgid "Number (0x%s) larger than 32 bits"
 msgstr ""
 
-#: config/tc-mips.c:3617
+#: config/tc-mips.c:3999
 msgid "Number larger than 64 bits"
 msgstr ""
 
-#: config/tc-mips.c:3911 config/tc-mips.c:3939 config/tc-mips.c:3977
-#: config/tc-mips.c:4022 config/tc-mips.c:6053 config/tc-mips.c:6092
-#: config/tc-mips.c:6131 config/tc-mips.c:6553 config/tc-mips.c:6605
+#: config/tc-mips.c:4293 config/tc-mips.c:4321 config/tc-mips.c:4359
+#: config/tc-mips.c:4404 config/tc-mips.c:6458 config/tc-mips.c:6497
+#: config/tc-mips.c:6536 config/tc-mips.c:6956 config/tc-mips.c:7008
+#: config/tc-score.c:4239
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:4328 config/tc-mips.c:4394 config/tc-mips.c:4482
-#: config/tc-mips.c:4529 config/tc-mips.c:4590 config/tc-mips.c:4638
-#: config/tc-mips.c:7619 config/tc-mips.c:7626 config/tc-mips.c:7633
-#: config/tc-mips.c:7740
+#: config/tc-mips.c:4726 config/tc-mips.c:4792 config/tc-mips.c:4880
+#: config/tc-mips.c:4927 config/tc-mips.c:4988 config/tc-mips.c:5036
+#: config/tc-mips.c:8022 config/tc-mips.c:8029 config/tc-mips.c:8036
+#: config/tc-mips.c:8143
 msgid "Unsupported large constant"
 msgstr ""
 
 #. result is always true
-#: config/tc-mips.c:4360
+#: config/tc-mips.c:4758
 #, c-format
 msgid "Branch %s is always true"
 msgstr ""
 
-#: config/tc-mips.c:4601 config/tc-mips.c:4649 config/tc-mips.c:8309
+#: config/tc-mips.c:4999 config/tc-mips.c:5047 config/tc-mips.c:8808
 #, c-format
 msgid "Improper position (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:4607 config/tc-mips.c:8376
+#: config/tc-mips.c:5005 config/tc-mips.c:8875
 #, c-format
 msgid "Improper extract size (%lu, position %lu)"
 msgstr ""
 
-#: config/tc-mips.c:4655 config/tc-mips.c:8340
+#: config/tc-mips.c:5053 config/tc-mips.c:8839
 #, c-format
 msgid "Improper insert size (%lu, position %lu)"
 msgstr ""
 
-#: config/tc-mips.c:4692 config/tc-mips.c:4789
+#: config/tc-mips.c:5090 config/tc-mips.c:5187
 msgid "Divide by zero."
 msgstr ""
 
-#: config/tc-mips.c:4875
+#: config/tc-mips.c:5273
 msgid "dla used to load 32-bit register"
 msgstr ""
 
-#: config/tc-mips.c:4878
+#: config/tc-mips.c:5276
 msgid "la used to load 64-bit address"
 msgstr ""
 
-#: config/tc-mips.c:4990
+#: config/tc-mips.c:5388 config/tc-z80.c:700
 msgid "offset too large"
 msgstr ""
 
-#: config/tc-mips.c:5162 config/tc-mips.c:5441
+#: config/tc-mips.c:5562 config/tc-mips.c:5841
 msgid "PIC code offset overflow (max 32 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:5487
+#: config/tc-mips.c:5887
 msgid "MIPS PIC call to register other than $25"
 msgstr ""
 
-#: config/tc-mips.c:5493 config/tc-mips.c:5504 config/tc-mips.c:5628
-#: config/tc-mips.c:5639
+#: config/tc-mips.c:5893 config/tc-mips.c:5904 config/tc-mips.c:6026
+#: config/tc-mips.c:6037
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5498 config/tc-mips.c:5633
+#: config/tc-mips.c:5898 config/tc-mips.c:6031
 msgid "No .frame pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5704 config/tc-mips.c:5792 config/tc-mips.c:6338
-#: config/tc-mips.c:6369 config/tc-mips.c:6387 config/tc-mips.c:7037
+#: config/tc-mips.c:6052
+msgid "Non-PIC jump used in PIC library"
+msgstr ""
+
+#: config/tc-mips.c:6104 config/tc-mips.c:6195 config/tc-mips.c:6741
+#: config/tc-mips.c:6772 config/tc-mips.c:6790 config/tc-mips.c:7440
 msgid "opcode not supported on this processor"
 msgstr ""
 
-#: config/tc-mips.c:6903 config/tc-mips.c:6934 config/tc-mips.c:6985
-#: config/tc-mips.c:7015
+#: config/tc-mips.c:7306 config/tc-mips.c:7337 config/tc-mips.c:7388
+#: config/tc-mips.c:7418
 msgid "Improper rotate count"
 msgstr ""
 
-#: config/tc-mips.c:7070
+#: config/tc-mips.c:7473
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr ""
 
-#: config/tc-mips.c:7216
+#: config/tc-mips.c:7619
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr ""
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:7521
+#: config/tc-mips.c:7924
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr ""
 
-#: config/tc-mips.c:7771
+#: config/tc-mips.c:8174
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7799 config/tc-mips.c:8430
+#: config/tc-mips.c:8206 config/tc-mips.c:8929
 #, c-format
 msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7876
+#: config/tc-mips.c:8284
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:7883
+#: config/tc-mips.c:8291
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8000
+#: config/tc-mips.c:8473 config/tc-mips.c:9806
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr ""
 
-#: config/tc-mips.c:8031 config/tc-mips.c:8045 config/tc-mips.c:8059
-#: config/tc-mips.c:8073 config/tc-mips.c:8100 config/tc-mips.c:8147
+#: config/tc-mips.c:8506
+#, c-format
+msgid "BALIGN immediate not 1 or 3 (%lu)"
+msgstr ""
+
+#: config/tc-mips.c:8519 config/tc-mips.c:8532 config/tc-mips.c:8545
+#: config/tc-mips.c:8558 config/tc-mips.c:8584 config/tc-mips.c:8628
 #, c-format
 msgid "DSP immediate not in range 0..%d (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8092 config/tc-mips.c:8120
+#: config/tc-mips.c:8576 config/tc-mips.c:8603
 msgid "Invalid dsp acc register"
 msgstr ""
 
-#: config/tc-mips.c:8131 config/tc-mips.c:8165 config/tc-mips.c:8184
+#: config/tc-mips.c:8614 config/tc-mips.c:8645 config/tc-mips.c:8662
 #, c-format
 msgid "DSP immediate not in range %ld..%ld (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8200 config/tc-mips.c:8214
+#: config/tc-mips.c:8675
+#, c-format
+msgid "MT usermode bit not 0 or 1 (%lu)"
+msgstr ""
+
+#: config/tc-mips.c:8686
 #, c-format
-msgid "MT immediate not in range 0..%d (%lu)"
+msgid "MT load high bit not 0 or 1 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8233 config/tc-mips.c:8246
+#: config/tc-mips.c:8703 config/tc-mips.c:8716
 msgid "Invalid dsp/smartmips acc register"
 msgstr ""
 
-#: config/tc-mips.c:8395 config/tc-mips.c:8899
+#: config/tc-mips.c:8781
+#, c-format
+msgid "Illegal %s number (%lu, 0x%lx)"
+msgstr ""
+
+#: config/tc-mips.c:8894 config/tc-mips.c:9315
 msgid "absolute expression required"
 msgstr ""
 
-#: config/tc-mips.c:8418 config/tc-mips.c:8579
+#: config/tc-mips.c:8917
 #, c-format
 msgid "Invalid register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:8426
+#: config/tc-mips.c:8925
 msgid "Invalid coprocessor 0 register number"
 msgstr ""
 
-#: config/tc-mips.c:8447
+#: config/tc-mips.c:8946
 #, c-format
 msgid "Improper shift amount (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8470 config/tc-mips.c:9731 config/tc-mips.c:9844
+#: config/tc-mips.c:8969 config/tc-mips.c:10119 config/tc-mips.c:10372
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8485
+#: config/tc-mips.c:8984
 #, c-format
-msgid "Illegal break code (%lu)"
+msgid "Code for %s not in range 0..1023 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8496
+#: config/tc-mips.c:8996
 #, c-format
-msgid "Illegal lower break code (%lu)"
+msgid "Lower code for %s not in range 0..1023 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8507
+#: config/tc-mips.c:9008
 #, c-format
-msgid "Illegal 20-bit code (%lu)"
+msgid "Code for %s not in range 0..1048575 (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8519
+#: config/tc-mips.c:9021
 #, c-format
 msgid "Coproccesor code > 25 bits (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8532
+#: config/tc-mips.c:9035
 #, c-format
 msgid "Illegal 19-bit code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8543
+#: config/tc-mips.c:9048
 #, c-format
 msgid "Invalid performance register (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8754
+#: config/tc-mips.c:9188
 #, c-format
 msgid "Invalid MDMX Immediate (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8794
-#, c-format
-msgid "Invalid float register number (%d)"
-msgstr ""
-
-#: config/tc-mips.c:8810
+#: config/tc-mips.c:9226
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr ""
 
-#: config/tc-mips.c:8849
+#: config/tc-mips.c:9265
 #, c-format
 msgid "Bad element selector %ld"
 msgstr ""
 
-#: config/tc-mips.c:8857
+#: config/tc-mips.c:9273
 #, c-format
 msgid "Expecting ']' found '%s'"
 msgstr ""
 
-#: config/tc-mips.c:8963
+#: config/tc-mips.c:9379
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr ""
 
-#: config/tc-mips.c:9084
+#: config/tc-mips.c:9499
 msgid "Can't use floating point insn in this section"
 msgstr ""
 
-#: config/tc-mips.c:9145
+#: config/tc-mips.c:9560
 msgid "expression out of range"
 msgstr ""
 
-#: config/tc-mips.c:9185
+#: config/tc-mips.c:9600
 msgid "lui expression not in range 0..65535"
 msgstr ""
 
-#: config/tc-mips.c:9209
-#, c-format
-msgid "Invalid condition code register $fcc%d"
-msgstr ""
-
-#: config/tc-mips.c:9214
+#: config/tc-mips.c:9621
 #, c-format
 msgid "Condition code register should be even for %s, was %d"
 msgstr ""
 
-#: config/tc-mips.c:9219
+#: config/tc-mips.c:9626
 #, c-format
 msgid "Condition code register should be 0 or 4 for %s, was %d"
 msgstr ""
 
-#: config/tc-mips.c:9245
+#: config/tc-mips.c:9652
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr ""
 
-#: config/tc-mips.c:9257 config/tc-mips.c:9274
+#: config/tc-mips.c:9664 config/tc-mips.c:9681
 #, c-format
 msgid "bad byte vector index (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:9285
+#: config/tc-mips.c:9692
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr ""
 
-#: config/tc-mips.c:9296 config/tc-mips.c:9301 config/tc-mips.c:9869
+#: config/tc-mips.c:9703 config/tc-mips.c:9708 config/tc-mips.c:10397
 msgid "illegal operands"
 msgstr ""
 
-#: config/tc-mips.c:9367
+#: config/tc-mips.c:9776 config/tc-score.c:2418
 msgid "unrecognized opcode"
 msgstr ""
 
-#: config/tc-mips.c:9504
-#, c-format
-msgid "invalid register number (%d)"
-msgstr ""
-
-#: config/tc-mips.c:9595
+#: config/tc-mips.c:9983
 msgid "used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:9763
+#: config/tc-mips.c:10155 config/tc-mips.c:10236 config/tc-mips.c:10251
 msgid "can't parse register list"
 msgstr ""
 
-#: config/tc-mips.c:9987
+#: config/tc-mips.c:10224
+msgid "more than one frame size in list"
+msgstr ""
+
+#: config/tc-mips.c:10279
+msgid "unexpected register in list"
+msgstr ""
+
+#: config/tc-mips.c:10289
+msgid "arg/static registers overlap"
+msgstr ""
+
+#: config/tc-mips.c:10307
+msgid "invalid arg register list"
+msgstr ""
+
+#: config/tc-mips.c:10316 config/tc-mips.c:10339
+msgid "invalid static register list"
+msgstr ""
+
+#: config/tc-mips.c:10346
+msgid "missing frame size"
+msgstr ""
+
+#: config/tc-mips.c:10349
+msgid "invalid frame size"
+msgstr ""
+
+#: config/tc-mips.c:10515
 msgid "extended operand requested but not required"
 msgstr ""
 
-#: config/tc-mips.c:9989
+#: config/tc-mips.c:10517
 msgid "invalid unextended operand value"
 msgstr ""
 
-#: config/tc-mips.c:10017
+#: config/tc-mips.c:10545
 msgid "operand value out of range for instruction"
 msgstr ""
 
-#: config/tc-mips.c:10469
+#: config/tc-mips.c:11007
 #, c-format
 msgid "A different %s was already specified, is now %s"
 msgstr ""
 
-#: config/tc-mips.c:10689
+#: config/tc-mips.c:11242
 msgid "-call_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10696 config/tc-mips.c:10725 config/tc-mips.c:11834
-#: config/tc-mips.c:12060
-msgid "-G may not be used with SVR4 PIC code"
-msgstr ""
-
-#: config/tc-mips.c:10705
+#: config/tc-mips.c:11252
 msgid "-non_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10736
+#: config/tc-mips.c:11278
 msgid "-32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10745
+#: config/tc-mips.c:11287
 msgid "-n32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10754
+#: config/tc-mips.c:11296
 msgid "-64 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10759 config/tc-mips.c:10796
+#: config/tc-mips.c:11301 config/tc-mips.c:11338
 msgid "No compiled in support for 64 bit object file format"
 msgstr ""
 
-#: config/tc-mips.c:10783
+#: config/tc-mips.c:11325
 msgid "-mabi is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10803
+#: config/tc-mips.c:11345
 #, c-format
 msgid "invalid abi -mabi=%s"
 msgstr ""
 
-#: config/tc-mips.c:10877
+#: config/tc-mips.c:11423
 msgid "-G not supported in this configuration."
 msgstr ""
 
-#: config/tc-mips.c:10903
+#: config/tc-mips.c:11449
 #, c-format
 msgid "-%s conflicts with the other architecture options, which imply -%s"
 msgstr ""
 
-#: config/tc-mips.c:10934
+#: config/tc-mips.c:11480
 msgid "-mgp64 used with a 32-bit processor"
 msgstr ""
 
-#: config/tc-mips.c:10936
+#: config/tc-mips.c:11482
 msgid "-mgp32 used with a 64-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10938
+#: config/tc-mips.c:11484
 msgid "-mgp64 used with a 32-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10968
+#: config/tc-mips.c:11522
+msgid "-mfp64 used with a 32-bit fpu"
+msgstr ""
+
+#: config/tc-mips.c:11525
+msgid "-mfp64 used with a 32-bit ABI"
+msgstr ""
+
+#: config/tc-mips.c:11529
+msgid "-mfp32 used with a 64-bit ABI"
+msgstr ""
+
+#: config/tc-mips.c:11543
 msgid "trap exception not supported at ISA 1"
 msgstr ""
 
-#: config/tc-mips.c:11229
-msgid "Cannot branch to undefined symbol."
+#: config/tc-mips.c:11553
+msgid "-mfp32 used with -mips3d"
 msgstr ""
 
-#: config/tc-mips.c:11236
-msgid "Cannot branch to symbol in another section."
+#: config/tc-mips.c:11559
+msgid "-mfp32 used with -mdmx"
 msgstr ""
 
-#: config/tc-mips.c:11245
-msgid "Pretending global symbol used as branch target is local."
+#: config/tc-mips.c:11632
+msgid "PC relative MIPS16 instruction references a different section"
 msgstr ""
 
-#: config/tc-mips.c:11402 config/tc-sparc.c:3229 config/tc-sparc.c:3236
-#: config/tc-sparc.c:3243 config/tc-sparc.c:3250 config/tc-sparc.c:3257
-#: config/tc-sparc.c:3266 config/tc-sparc.c:3277 config/tc-sparc.c:3299
-#: config/tc-sparc.c:3323 write.c:861 write.c:933
+#: config/tc-mips.c:11923 config/tc-sparc.c:3283 config/tc-sparc.c:3290
+#: config/tc-sparc.c:3297 config/tc-sparc.c:3304 config/tc-sparc.c:3311
+#: config/tc-sparc.c:3320 config/tc-sparc.c:3331 config/tc-sparc.c:3353
+#: config/tc-sparc.c:3377 write.c:1096
 msgid "relocation overflow"
 msgstr ""
 
-#: config/tc-mips.c:11412
+#: config/tc-mips.c:11933
 #, c-format
-msgid "Branch to odd address (%lx)"
+msgid "Branch to misaligned address (%lx)"
 msgstr ""
 
-#: config/tc-mips.c:11461
+#: config/tc-mips.c:11980
 msgid "Branch out of range"
 msgstr ""
 
-#: config/tc-mips.c:11540
+#: config/tc-mips.c:12055
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr ""
 
-#: config/tc-mips.c:11543
+#: config/tc-mips.c:12058
 msgid "Alignment negative: 0 assumed."
 msgstr ""
 
-#: config/tc-mips.c:11780
+#: config/tc-mips.c:12302
 #, c-format
 msgid "%s: no such section"
 msgstr ""
 
-#: config/tc-mips.c:11829
+#: config/tc-mips.c:12351
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ""
 
-#: config/tc-mips.c:11840
+#: config/tc-mips.c:12356 config/tc-mips.c:12648
+msgid "-G may not be used with SVR4 PIC code"
+msgstr ""
+
+#: config/tc-mips.c:12362
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr ""
 
-#: config/tc-mips.c:11893
+#: config/tc-mips.c:12415
 msgid "`noreorder' must be set before `nomacro'"
 msgstr ""
 
-#: config/tc-mips.c:11952
+#: config/tc-mips.c:12532
 #, c-format
 msgid "unknown architecture %s"
 msgstr ""
 
-#: config/tc-mips.c:11965 config/tc-mips.c:11995
+#: config/tc-mips.c:12545 config/tc-mips.c:12575
 #, c-format
 msgid "unknown ISA level %s"
 msgstr ""
 
-#: config/tc-mips.c:11973
+#: config/tc-mips.c:12553
 #, c-format
 msgid "unknown ISA or architecture %s"
 msgstr ""
 
-#: config/tc-mips.c:12023
+#: config/tc-mips.c:12603
 msgid ".set pop with no .set push"
 msgstr ""
 
-#: config/tc-mips.c:12044
+#: config/tc-mips.c:12632
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr ""
 
-#: config/tc-mips.c:12102
+#: config/tc-mips.c:12690
 msgid ".cpload not in noreorder section"
 msgstr ""
 
-#: config/tc-mips.c:12171 config/tc-mips.c:12190
+#: config/tc-mips.c:12758 config/tc-mips.c:12777
 msgid "missing argument separator ',' for .cpsetup"
 msgstr ""
 
-#: config/tc-mips.c:12380
+#: config/tc-mips.c:12971 config/tc-score.c:6323
 msgid "Unsupported use of .gpword"
 msgstr ""
 
-#: config/tc-mips.c:12416
+#: config/tc-mips.c:13011
 msgid "Unsupported use of .gpdword"
 msgstr ""
 
-#: config/tc-mips.c:12548
-msgid "expected `$'"
-msgstr ""
-
-#: config/tc-mips.c:12556
-msgid "Bad register number"
-msgstr ""
-
-#: config/tc-mips.c:12604
-msgid "Unrecognized register name"
-msgstr ""
-
-#: config/tc-mips.c:12837
+#: config/tc-mips.c:13356
 msgid "unsupported PC relative reference to different section"
 msgstr ""
 
-#: config/tc-mips.c:12950 config/tc-xtensa.c:1593 config/tc-xtensa.c:1804
+#: config/tc-mips.c:13469 config/tc-xtensa.c:1537 config/tc-xtensa.c:1772
 msgid "unsupported relocation"
 msgstr ""
 
-#: config/tc-mips.c:13158
+#: config/tc-mips.c:13719
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-mips.c:13244
+#: config/tc-mips.c:13804
 msgid "relaxed out-of-range branch into a jump"
 msgstr ""
 
-#: config/tc-mips.c:13766
+#: config/tc-mips.c:14334
 msgid "missing .end at end of assembly"
 msgstr ""
 
-#: config/tc-mips.c:13781
+#: config/tc-mips.c:14349 config/tc-score.c:5929
 msgid "expected simple number"
 msgstr ""
 
-#: config/tc-mips.c:13807
+#: config/tc-mips.c:14375 config/tc-score.c:5955
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr ""
 
-#: config/tc-mips.c:13809
+#: config/tc-mips.c:14377 config/tc-score.c:5956
 msgid "invalid number"
 msgstr ""
 
-#: config/tc-mips.c:13882
+#: config/tc-mips.c:14450 config/tc-score.c:6105
 msgid ".end not in text section"
 msgstr ""
 
-#: config/tc-mips.c:13886
+#: config/tc-mips.c:14454 config/tc-score.c:6108
 msgid ".end directive without a preceding .ent directive."
 msgstr ""
 
-#: config/tc-mips.c:13895
+#: config/tc-mips.c:14463 config/tc-score.c:6116
 msgid ".end symbol does not match .ent symbol."
 msgstr ""
 
-#: config/tc-mips.c:13902
+#: config/tc-mips.c:14470 config/tc-score.c:6121
 msgid ".end directive missing or unknown symbol"
 msgstr ""
 
-#: config/tc-mips.c:13978
+#: config/tc-mips.c:14545 config/tc-score.c:5994
 msgid ".ent or .aent not in text section."
 msgstr ""
 
-#: config/tc-mips.c:13981
+#: config/tc-mips.c:14548 config/tc-score.c:5996
 msgid "missing .end"
 msgstr ""
 
-#: config/tc-mips.c:14033
+#: config/tc-mips.c:14600
 msgid "Bad .frame directive"
 msgstr ""
 
-#: config/tc-mips.c:14065
+#: config/tc-mips.c:14632
 msgid ".mask/.fmask outside of .ent"
 msgstr ""
 
-#: config/tc-mips.c:14072
+#: config/tc-mips.c:14639
 msgid "Bad .mask/.fmask directive"
 msgstr ""
 
-#: config/tc-mips.c:14337
+#: config/tc-mips.c:14934
 #, c-format
 msgid ""
 "MIPS options:\n"
@@ -7350,7 +8010,7 @@ msgid ""
 "\t\t\timplicitly with the gp register [default 8]\n"
 msgstr ""
 
-#: config/tc-mips.c:14344
+#: config/tc-mips.c:14941
 #, c-format
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
@@ -7365,7 +8025,7 @@ msgid ""
 "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14363
+#: config/tc-mips.c:14960
 #, c-format
 msgid ""
 "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
@@ -7373,35 +8033,48 @@ msgid ""
 "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14376
+#: config/tc-mips.c:14973
 #, c-format
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14379
+#: config/tc-mips.c:14976
+#, c-format
+msgid ""
+"-msmartmips\t\tgenerate smartmips instructions\n"
+"-mno-smartmips\t\tdo not generate smartmips instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14979
 #, c-format
 msgid ""
 "-mdsp\t\t\tgenerate DSP instructions\n"
 "-mno-dsp\t\tdo not generate DSP instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14382
+#: config/tc-mips.c:14982
+#, c-format
+msgid ""
+"-mdspr2\t\t\tgenerate DSP R2 instructions\n"
+"-mno-dspr2\t\tdo not generate DSP R2 instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14985
 #, c-format
 msgid ""
 "-mmt\t\t\tgenerate MT instructions\n"
 "-mno-mt\t\t\tdo not generate MT instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14385
+#: config/tc-mips.c:14988
 #, c-format
 msgid ""
 "-mfix-vr4120\t\twork around certain VR4120 errata\n"
 "-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n"
 "-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n"
 "-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n"
-"-mno-shared\t\toptimize output for executables\n"
 "-msym32\t\t\tassume all symbols have 32-bit values\n"
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
@@ -7410,19 +8083,20 @@ msgid ""
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
 msgstr ""
 
-#: config/tc-mips.c:14398
+#: config/tc-mips.c:15000
 #, c-format
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
+"-mvxworks-pic\t\tgenerate VxWorks position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
 "-xgot\t\t\tassume a 32 bit GOT\n"
 "-mpdr, -mno-pdr\t\tenable/disable creation of .pdr sections\n"
 "-mshared, -mno-shared   disable/enable .cpload optimization for\n"
-"                        non-shared code\n"
+"                        position dependent (non shared) code\n"
 "-mabi=ABI\t\tcreate ABI conformant object file for:\n"
 msgstr ""
 
-#: config/tc-mips.c:14417
+#: config/tc-mips.c:15020
 #, c-format
 msgid ""
 "-32\t\t\tcreate o32 ABI object file (default)\n"
@@ -7430,54 +8104,54 @@ msgid ""
 "-64\t\t\tcreate 64 ABI object file\n"
 msgstr ""
 
-#: config/tc-mmix.c:694
+#: config/tc-mmix.c:693
 #, c-format
 msgid " MMIX-specific command line options:\n"
 msgstr ""
 
-#: config/tc-mmix.c:695
+#: config/tc-mmix.c:694
 #, c-format
 msgid ""
 "  -fixed-special-register-names\n"
 "                          Allow only the original special register names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:698
+#: config/tc-mmix.c:697
 #, c-format
 msgid "  -globalize-symbols      Make all symbols global.\n"
 msgstr ""
 
-#: config/tc-mmix.c:700
+#: config/tc-mmix.c:699
 #, c-format
 msgid "  -gnu-syntax             Turn off mmixal syntax compatibility.\n"
 msgstr ""
 
-#: config/tc-mmix.c:702
+#: config/tc-mmix.c:701
 #, c-format
 msgid "  -relax                  Create linker relaxable code.\n"
 msgstr ""
 
-#: config/tc-mmix.c:704
+#: config/tc-mmix.c:703
 #, c-format
 msgid ""
 "  -no-predefined-syms     Do not provide mmixal built-in constants.\n"
 "                          Implies -fixed-special-register-names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:707
+#: config/tc-mmix.c:706
 #, c-format
 msgid ""
 "  -no-expand              Do not expand GETA, branches, PUSHJ or JUMP\n"
 "                          into multiple instructions.\n"
 msgstr ""
 
-#: config/tc-mmix.c:710
+#: config/tc-mmix.c:709
 #, c-format
 msgid ""
 "  -no-merge-gregs         Do not merge GREG definitions with nearby values.\n"
 msgstr ""
 
-#: config/tc-mmix.c:712
+#: config/tc-mmix.c:711
 #, c-format
 msgid ""
 "  -linker-allocated-gregs If there's no suitable GREG definition for "
@@ -7485,7 +8159,7 @@ msgid ""
 "resolve.\n"
 msgstr ""
 
-#: config/tc-mmix.c:715
+#: config/tc-mmix.c:714
 #, c-format
 msgid ""
 "  -x                      Do not warn when an operand to GETA, a branch,\n"
@@ -7494,185 +8168,185 @@ msgid ""
 "                          -linker-allocated-gregs."
 msgstr ""
 
-#: config/tc-mmix.c:841
+#: config/tc-mmix.c:840
 #, c-format
 msgid "unknown opcode: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:963 config/tc-mmix.c:978
+#: config/tc-mmix.c:962 config/tc-mmix.c:977
 msgid "specified location wasn't TETRA-aligned"
 msgstr ""
 
-#: config/tc-mmix.c:965 config/tc-mmix.c:980 config/tc-mmix.c:4124
-#: config/tc-mmix.c:4140
+#: config/tc-mmix.c:964 config/tc-mmix.c:979 config/tc-mmix.c:4125
+#: config/tc-mmix.c:4141
 msgid "unaligned data at an absolute location is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:1090
+#: config/tc-mmix.c:1089
 #, c-format
 msgid "invalid operand to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1112 config/tc-mmix.c:1139 config/tc-mmix.c:1172
-#: config/tc-mmix.c:1180 config/tc-mmix.c:1197 config/tc-mmix.c:1225
-#: config/tc-mmix.c:1246 config/tc-mmix.c:1271 config/tc-mmix.c:1319
-#: config/tc-mmix.c:1417 config/tc-mmix.c:1442 config/tc-mmix.c:1474
-#: config/tc-mmix.c:1506 config/tc-mmix.c:1536 config/tc-mmix.c:1589
-#: config/tc-mmix.c:1606 config/tc-mmix.c:1633 config/tc-mmix.c:1661
-#: config/tc-mmix.c:1688 config/tc-mmix.c:1714 config/tc-mmix.c:1730
-#: config/tc-mmix.c:1756 config/tc-mmix.c:1772 config/tc-mmix.c:1788
-#: config/tc-mmix.c:1851 config/tc-mmix.c:1867
+#: config/tc-mmix.c:1111 config/tc-mmix.c:1138 config/tc-mmix.c:1171
+#: config/tc-mmix.c:1179 config/tc-mmix.c:1196 config/tc-mmix.c:1224
+#: config/tc-mmix.c:1245 config/tc-mmix.c:1270 config/tc-mmix.c:1318
+#: config/tc-mmix.c:1416 config/tc-mmix.c:1441 config/tc-mmix.c:1473
+#: config/tc-mmix.c:1505 config/tc-mmix.c:1535 config/tc-mmix.c:1588
+#: config/tc-mmix.c:1605 config/tc-mmix.c:1632 config/tc-mmix.c:1660
+#: config/tc-mmix.c:1687 config/tc-mmix.c:1713 config/tc-mmix.c:1729
+#: config/tc-mmix.c:1755 config/tc-mmix.c:1771 config/tc-mmix.c:1787
+#: config/tc-mmix.c:1850 config/tc-mmix.c:1866
 #, c-format
 msgid "invalid operands to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1844
+#: config/tc-mmix.c:1843
 #, c-format
 msgid "unsupported operands to %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1969
+#: config/tc-mmix.c:1968
 msgid "internal: mmix_prefix_name but empty prefix"
 msgstr ""
 
-#: config/tc-mmix.c:2013
+#: config/tc-mmix.c:2012
 #, c-format
 msgid "too many GREG registers allocated (max %d)"
 msgstr ""
 
-#: config/tc-mmix.c:2071
+#: config/tc-mmix.c:2070
 msgid "BSPEC already active.  Nesting is not supported."
 msgstr ""
 
-#: config/tc-mmix.c:2080
+#: config/tc-mmix.c:2079
 msgid "invalid BSPEC expression"
 msgstr ""
 
-#: config/tc-mmix.c:2096
+#: config/tc-mmix.c:2095
 #, c-format
 msgid "can't create section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2101
+#: config/tc-mmix.c:2100
 #, c-format
 msgid "can't set section flags for section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2122
+#: config/tc-mmix.c:2121
 msgid "ESPEC without preceding BSPEC"
 msgstr ""
 
-#: config/tc-mmix.c:2151
+#: config/tc-mmix.c:2150
 msgid "missing local expression"
 msgstr ""
 
-#: config/tc-mmix.c:2389
+#: config/tc-mmix.c:2388
 msgid "operand out of range, instruction expanded"
 msgstr ""
 
 #. The BFD_RELOC_MMIX_LOCAL-specific message is supposed to be
 #. user-friendly, though a little bit non-substantial.
-#: config/tc-mmix.c:2640
+#: config/tc-mmix.c:2639
 msgid "directive LOCAL must be placed in code or data"
 msgstr ""
 
-#: config/tc-mmix.c:2641
+#: config/tc-mmix.c:2640
 msgid "internal confusion: relocation in a section without contents"
 msgstr ""
 
-#: config/tc-mmix.c:2755
+#: config/tc-mmix.c:2754
 msgid "internal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:2803
+#: config/tc-mmix.c:2802
 msgid "no suitable GREG definition for operands"
 msgstr ""
 
-#: config/tc-mmix.c:2862
+#: config/tc-mmix.c:2861
 msgid "operands were not reducible at assembly-time"
 msgstr ""
 
-#: config/tc-mmix.c:2889
+#: config/tc-mmix.c:2888
 #, c-format
 msgid "cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
-#: config/tc-mmix.c:2909
+#: config/tc-mmix.c:2908
 #, c-format
 msgid "internal: unhandled label %s"
 msgstr ""
 
-#: config/tc-mmix.c:2939
+#: config/tc-mmix.c:2938
 msgid "[0-9]H labels may not appear alone on a line"
 msgstr ""
 
-#: config/tc-mmix.c:2948
+#: config/tc-mmix.c:2947
 msgid "[0-9]H labels do not mix with dot-pseudos"
 msgstr ""
 
-#: config/tc-mmix.c:3036
+#: config/tc-mmix.c:3035
 msgid "invalid characters in input"
 msgstr ""
 
-#: config/tc-mmix.c:3140
+#: config/tc-mmix.c:3141
 msgid "empty label field for IS"
 msgstr ""
 
-#: config/tc-mmix.c:3466
+#: config/tc-mmix.c:3467
 #, c-format
 msgid "internal: unexpected relax type %d:%d"
 msgstr ""
 
-#: config/tc-mmix.c:3488
+#: config/tc-mmix.c:3489
 msgid "BSPEC without ESPEC."
 msgstr ""
 
-#: config/tc-mmix.c:3688
+#: config/tc-mmix.c:3689
 msgid "GREG expression too complicated"
 msgstr ""
 
-#: config/tc-mmix.c:3703
+#: config/tc-mmix.c:3704
 msgid "internal: GREG expression not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:3752
+#: config/tc-mmix.c:3753
 msgid "register section has contents\n"
 msgstr ""
 
-#: config/tc-mmix.c:3879
+#: config/tc-mmix.c:3880
 msgid "section change from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3900
+#: config/tc-mmix.c:3901
 msgid "directive LOC from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3911
+#: config/tc-mmix.c:3912
 msgid "invalid LOC expression"
 msgstr ""
 
-#: config/tc-mmix.c:3936 config/tc-mmix.c:3962
+#: config/tc-mmix.c:3937 config/tc-mmix.c:3963
 msgid "LOC expression stepping backwards is not supported"
 msgstr ""
 
 #. We will only get here in rare cases involving #NO_APP,
 #. where the unterminated string is not recognized by the
 #. preformatting pass.
-#: config/tc-mmix.c:4046 config/tc-mmix.c:4206
+#: config/tc-mmix.c:4047 config/tc-mmix.c:4207 config/tc-z80.c:1691
 msgid "unterminated string"
 msgstr ""
 
-#: config/tc-mmix.c:4063
+#: config/tc-mmix.c:4064
 msgid "BYTE expression not a pure number"
 msgstr ""
 
 #. Note that mmixal does not allow negative numbers in
 #. BYTE sequences, so neither should we.
-#: config/tc-mmix.c:4072
+#: config/tc-mmix.c:4073
 msgid "BYTE expression not in the range 0..255"
 msgstr ""
 
-#: config/tc-mmix.c:4122 config/tc-mmix.c:4138
+#: config/tc-mmix.c:4123 config/tc-mmix.c:4139
 msgid "data item with alignment larger than location"
 msgstr ""
 
@@ -7682,82 +8356,82 @@ msgstr ""
 msgid "`&' serial number operator is not supported"
 msgstr ""
 
-#: config/tc-mn10200.c:305
+#: config/tc-mn10200.c:304
 #, c-format
 msgid ""
 "MN10200 options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2135
-#: config/tc-s390.c:1557 config/tc-v850.c:1621
+#: config/tc-mn10200.c:930 config/tc-mn10300.c:1391 config/tc-ppc.c:2189
+#: config/tc-s390.c:1558 config/tc-v850.c:1636
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr ""
 
-#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2614
-#: config/tc-s390.c:1472 config/tc-v850.c:2026
+#: config/tc-mn10200.c:1173 config/tc-mn10300.c:1964 config/tc-ppc.c:2668
+#: config/tc-s390.c:1473 config/tc-v850.c:2041
 #, c-format
 msgid "junk at end of line: `%s'"
 msgstr ""
 
-#: config/tc-mn10300.c:695
+#: config/tc-mn10300.c:694
 #, c-format
 msgid ""
-"MN10300 options:\n"
+"MN10300 assembler options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10300.c:1361 config/tc-sh.c:778 read.c:3871
+#: config/tc-mn10300.c:1360 config/tc-sh.c:776 config/tc-z80.c:671 read.c:4194
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr ""
 
-#: config/tc-mn10300.c:1409
+#: config/tc-mn10300.c:1408
 msgid "Invalid opcode/operands"
 msgstr ""
 
-#: config/tc-mn10300.c:1936
+#: config/tc-mn10300.c:1935
 msgid "Invalid register specification."
 msgstr ""
 
-#: config/tc-mn10300.c:2518
+#: config/tc-mn10300.c:2522
 #, c-format
 msgid "Bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-msp430.c:552
+#: config/tc-msp430.c:550
 msgid ".profiler pseudo requires at least two operands."
 msgstr ""
 
-#: config/tc-msp430.c:611
+#: config/tc-msp430.c:609
 msgid "unknown profiling flag - ignored."
 msgstr ""
 
-#: config/tc-msp430.c:627
+#: config/tc-msp430.c:625
 msgid "ambigious flags combination - '.profiler' directive ignored."
 msgstr ""
 
-#: config/tc-msp430.c:637
+#: config/tc-msp430.c:635
 msgid "profiling in absolute section? Hm..."
 msgstr ""
 
-#: config/tc-msp430.c:726
+#: config/tc-msp430.c:724
 #, c-format
 msgid "Known MCU names:\n"
 msgstr ""
 
-#: config/tc-msp430.c:729
+#: config/tc-msp430.c:727
 #, c-format
 msgid "\t %s\n"
 msgstr ""
 
-#: config/tc-msp430.c:755
+#: config/tc-msp430.c:753
 #, c-format
 msgid "redefinition of mcu type %s' to %s'"
 msgstr ""
 
-#: config/tc-msp430.c:798
+#: config/tc-msp430.c:796
 #, c-format
 msgid ""
 "MSP430 options:\n"
@@ -7785,322 +8459,322 @@ msgid ""
 "                  msp430x447  msp430x448  msp430x449\n"
 msgstr ""
 
-#: config/tc-msp430.c:821
+#: config/tc-msp430.c:819
 #, c-format
 msgid ""
 "  -mQ - enable relaxation at assembly time. DANGEROUS!\n"
 "  -mP - enable polymorph instructions\n"
 msgstr ""
 
-#: config/tc-msp430.c:1011
+#: config/tc-msp430.c:1009
 #, c-format
 msgid "value %d out of range. Use #lo() or #hi()"
 msgstr ""
 
-#: config/tc-msp430.c:1099
+#: config/tc-msp430.c:1097
 #, c-format
 msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
 msgstr ""
 
-#: config/tc-msp430.c:1150
+#: config/tc-msp430.c:1148
 #, c-format
 msgid "Registers cannot be used within immediate expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:1152
+#: config/tc-msp430.c:1150
 #, c-format
 msgid "unknown operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1174 config/tc-msp430.c:1309
+#: config/tc-msp430.c:1172 config/tc-msp430.c:1307
 #, c-format
 msgid "value out of range: %d"
 msgstr ""
 
-#: config/tc-msp430.c:1185
+#: config/tc-msp430.c:1183
 #, c-format
 msgid "Registers cannot be used within absolute expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:1187 config/tc-msp430.c:1330
+#: config/tc-msp430.c:1185 config/tc-msp430.c:1328
 #, c-format
 msgid "unknown expression in operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1201 config/tc-msp430.c:1208
+#: config/tc-msp430.c:1199 config/tc-msp430.c:1206
 #, c-format
 msgid "unknown addressing mode %s"
 msgstr ""
 
-#: config/tc-msp430.c:1216
+#: config/tc-msp430.c:1214
 #, c-format
 msgid "Bad register name r%s"
 msgstr ""
 
-#: config/tc-msp430.c:1228
+#: config/tc-msp430.c:1226
 #, c-format
 msgid "MSP430 does not have %d registers"
 msgstr ""
 
-#: config/tc-msp430.c:1248
+#: config/tc-msp430.c:1246
 msgid "')' required"
 msgstr ""
 
-#: config/tc-msp430.c:1261
+#: config/tc-msp430.c:1259
 #, c-format
 msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
 msgstr ""
 
-#: config/tc-msp430.c:1270
+#: config/tc-msp430.c:1268
 #, c-format
 msgid "unknown operator (r%s substituded as a register name"
 msgstr ""
 
-#: config/tc-msp430.c:1282 config/tc-msp430.c:1293
+#: config/tc-msp430.c:1280 config/tc-msp430.c:1291
 #, c-format
 msgid "unknown operator %s"
 msgstr ""
 
-#: config/tc-msp430.c:1287
+#: config/tc-msp430.c:1285
 msgid "r2 should not be used in indexed addressing mode"
 msgstr ""
 
-#: config/tc-msp430.c:1328
+#: config/tc-msp430.c:1326
 #, c-format
 msgid "Registers cannot be used as a prefix of indexed expression [%s]"
 msgstr ""
 
 #. Unreachable.
-#: config/tc-msp430.c:1377
+#: config/tc-msp430.c:1375
 #, c-format
 msgid "unknown addressing mode for operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1402
+#: config/tc-msp430.c:1400
 #, c-format
 msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
 msgstr ""
 
-#: config/tc-msp430.c:1412
+#: config/tc-msp430.c:1410
 msgid "this addressing mode is not applicable for destination operand"
 msgstr ""
 
-#: config/tc-msp430.c:1456
+#: config/tc-msp430.c:1454
 #, c-format
 msgid "instruction %s requires %d operand(s)"
 msgstr ""
 
-#: config/tc-msp430.c:1709
+#: config/tc-msp430.c:1707
 #, c-format
 msgid "Even number required. Rounded to %d"
 msgstr ""
 
-#: config/tc-msp430.c:1720
+#: config/tc-msp430.c:1718
 #, c-format
 msgid "Wrong displacement  %d"
 msgstr ""
 
-#: config/tc-msp430.c:1737
+#: config/tc-msp430.c:1735
 msgid "instruction requires label sans '$'"
 msgstr ""
 
-#: config/tc-msp430.c:1742
+#: config/tc-msp430.c:1740
 msgid "instruction requires label or value in range -511:512"
 msgstr ""
 
-#: config/tc-msp430.c:1749 config/tc-msp430.c:1793 config/tc-msp430.c:1832
+#: config/tc-msp430.c:1747 config/tc-msp430.c:1791 config/tc-msp430.c:1830
 msgid "instruction requires label"
 msgstr ""
 
-#: config/tc-msp430.c:1757 config/tc-msp430.c:1799
+#: config/tc-msp430.c:1755 config/tc-msp430.c:1797
 msgid "polymorphs are not enabled. Use -mP option to enable."
 msgstr ""
 
-#: config/tc-msp430.c:1836
+#: config/tc-msp430.c:1834
 msgid "Ilegal instruction or not implmented opcode."
 msgstr ""
 
-#: config/tc-msp430.c:2187
+#: config/tc-msp430.c:2184
 #, c-format
 msgid "internal inconsistency problem in %s: insn %04lx"
 msgstr ""
 
-#: config/tc-msp430.c:2217 config/tc-msp430.c:2240
+#: config/tc-msp430.c:2214 config/tc-msp430.c:2237
 #, c-format
 msgid "internal inconsistency problem in %s: ext. insn %04lx"
 msgstr ""
 
-#: config/tc-msp430.c:2252
+#: config/tc-msp430.c:2249
 #, c-format
 msgid "internal inconsistency problem in %s:  %lx"
 msgstr ""
 
-#: config/tc-ns32k.c:441
+#: config/tc-ns32k.c:439
 msgid "Invalid syntax in PC-relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:465
+#: config/tc-ns32k.c:463
 msgid "Invalid syntax in External addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:546
+#: config/tc-ns32k.c:544
 msgid "Invalid syntax in Memory Relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:613
+#: config/tc-ns32k.c:611
 msgid "Invalid scaled-indexed mode, use (b,w,d,q)"
 msgstr ""
 
-#: config/tc-ns32k.c:618
+#: config/tc-ns32k.c:616
 msgid "Syntax in scaled-indexed mode, use [Rn:m] where n=[0..7] m={b,w,d,q}"
 msgstr ""
 
-#: config/tc-ns32k.c:623
+#: config/tc-ns32k.c:621
 msgid "Scaled-indexed addressing mode combined with scaled-index"
 msgstr ""
 
-#: config/tc-ns32k.c:634
+#: config/tc-ns32k.c:632
 msgid "Invalid or illegal addressing mode combined with scaled-index"
 msgstr ""
 
-#: config/tc-ns32k.c:757
+#: config/tc-ns32k.c:755
 msgid "Premature end of suffix -- Defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:770
+#: config/tc-ns32k.c:768
 msgid "Bad suffix after ':' use {b|w|d} Defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:815
+#: config/tc-ns32k.c:813
 msgid "Very short instr to option, ie you can't do it on a NULLstr"
 msgstr ""
 
-#: config/tc-ns32k.c:865
+#: config/tc-ns32k.c:863
 msgid "No such entry in list. (cpu/mmu register)"
 msgstr ""
 
-#: config/tc-ns32k.c:922
+#: config/tc-ns32k.c:920
 msgid "Internal consistency error.  check ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:946
+#: config/tc-ns32k.c:944
 msgid "Address of immediate operand"
 msgstr ""
 
-#: config/tc-ns32k.c:947
+#: config/tc-ns32k.c:945
 msgid "Invalid immediate write operand."
 msgstr ""
 
-#: config/tc-ns32k.c:1077
+#: config/tc-ns32k.c:1075
 msgid "Bad opcode-table-option, check in file ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1110
+#: config/tc-ns32k.c:1108
 msgid "No such opcode"
 msgstr ""
 
-#: config/tc-ns32k.c:1185
+#: config/tc-ns32k.c:1183
 msgid "Bad suffix, defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:1212
+#: config/tc-ns32k.c:1210
 msgid "Too many operands passed to instruction"
 msgstr ""
 
 #. Check error in default.
-#: config/tc-ns32k.c:1224
+#: config/tc-ns32k.c:1222
 msgid "Wrong numbers of operands in default, check ns32k-opcodes.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1227
+#: config/tc-ns32k.c:1225
 msgid "Wrong number of operands"
 msgstr ""
 
-#: config/tc-ns32k.c:1300
+#: config/tc-ns32k.c:1298
 #, c-format
 msgid "Can not do %d byte pc-relative relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1303
+#: config/tc-ns32k.c:1301
 #, c-format
 msgid "Can not do %d byte relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1395
+#: config/tc-ns32k.c:1393
 #, c-format
 msgid "value of %ld out of byte displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1405
+#: config/tc-ns32k.c:1403
 #, c-format
 msgid "value of %ld out of word displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1420
+#: config/tc-ns32k.c:1418
 #, c-format
 msgid "value of %ld out of double word displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1441
+#: config/tc-ns32k.c:1439
 #, c-format
 msgid "Internal logic error.  line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1489
+#: config/tc-ns32k.c:1487
 #, c-format
 msgid "Internal logic error. line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1590
+#: config/tc-ns32k.c:1588
 msgid "Bit field out of range"
 msgstr ""
 
-#: config/tc-ns32k.c:1690
+#: config/tc-ns32k.c:1688
 msgid "iif convert internal pcrel/binary"
 msgstr ""
 
-#: config/tc-ns32k.c:1707
+#: config/tc-ns32k.c:1705
 msgid "Bignum too big for long"
 msgstr ""
 
-#: config/tc-ns32k.c:1784
+#: config/tc-ns32k.c:1782
 msgid "iif convert internal pcrel/pointer"
 msgstr ""
 
-#: config/tc-ns32k.c:1789
+#: config/tc-ns32k.c:1787
 msgid "Internal logic error in iif.iifP[n].type"
 msgstr ""
 
 #. We cant relax this case.
-#: config/tc-ns32k.c:1825
+#: config/tc-ns32k.c:1823
 msgid "Can't relax difference"
 msgstr ""
 
-#: config/tc-ns32k.c:1866
-msgid "Displacement to large for :d"
+#: config/tc-ns32k.c:1864
+msgid "Displacement too large for :d"
 msgstr ""
 
-#: config/tc-ns32k.c:1879
+#: config/tc-ns32k.c:1877
 msgid "Internal logic error in iif.iifP[].type"
 msgstr ""
 
 #. Fatal.
-#: config/tc-ns32k.c:1911
+#: config/tc-ns32k.c:1909
 #, c-format
 msgid "Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-ns32k.c:2181
+#: config/tc-ns32k.c:2179
 #, c-format
 msgid "invalid architecture option -m%s, ignored"
 msgstr ""
 
-#: config/tc-ns32k.c:2194
+#: config/tc-ns32k.c:2192
 #, c-format
 msgid "invalid default displacement size \"%s\". Defaulting to %d."
 msgstr ""
 
-#: config/tc-ns32k.c:2210
+#: config/tc-ns32k.c:2208
 #, c-format
 msgid ""
 "NS32K options:\n"
@@ -8108,45 +8782,45 @@ msgid ""
 "--disp-size-default=<1|2|4>\n"
 msgstr ""
 
-#: config/tc-ns32k.c:2285
+#: config/tc-ns32k.c:2283
 #, c-format
 msgid "Cannot find relocation type for symbol %s, code %d"
 msgstr ""
 
-#: config/tc-or32.c:360
+#: config/tc-or32.c:361
 #, c-format
 msgid "unknown opcode1: `%s'"
 msgstr ""
 
-#: config/tc-or32.c:366
+#: config/tc-or32.c:367
 #, c-format
 msgid "unknown opcode2 `%s'."
 msgstr ""
 
-#: config/tc-or32.c:403
+#: config/tc-or32.c:404
 #, c-format
 msgid "instruction not allowed: %s"
 msgstr ""
 
-#: config/tc-or32.c:406
+#: config/tc-or32.c:407
 #, c-format
 msgid "too many operands: %s"
 msgstr ""
 
-#: config/tc-or32.c:490
+#: config/tc-or32.c:491
 msgid "call/jmp target out of range (1)"
 msgstr ""
 
-#: config/tc-or32.c:674
+#: config/tc-or32.c:672
 msgid "call/jmp target out of range (2)"
 msgstr ""
 
-#: config/tc-or32.c:693
+#: config/tc-or32.c:691
 #, c-format
 msgid "bad relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-or32.c:885
+#: config/tc-or32.c:883
 msgid "invalid register in & expression"
 msgstr ""
 
@@ -8154,7 +8828,7 @@ msgstr ""
 msgid "Low order bits truncated in immediate float operand"
 msgstr ""
 
-#: config/tc-pdp11.c:679
+#: config/tc-pdp11.c:679 config/tc-z80.c:1890 config/tc-z80.c:1903
 #, c-format
 msgid "Unknown instruction '%s'"
 msgstr ""
@@ -8180,8 +8854,8 @@ msgid ""
 "-big\t\t\tgenerate big endian code\n"
 msgstr ""
 
-#: config/tc-pj.c:431 config/tc-sh.c:3955 config/tc-sh.c:3962
-#: config/tc-sh.c:3969 config/tc-sh.c:3976
+#: config/tc-pj.c:431 config/tc-sh.c:4086 config/tc-sh.c:4093
+#: config/tc-sh.c:4100 config/tc-sh.c:4107
 msgid "pcrel too far"
 msgstr ""
 
@@ -8193,17 +8867,17 @@ msgstr ""
 msgid "estimate size\n"
 msgstr ""
 
-#: config/tc-ppc.c:991
+#: config/tc-ppc.c:979
 #, c-format
 msgid "%s unsupported"
 msgstr ""
 
-#: config/tc-ppc.c:1057 config/tc-s390.c:417 config/tc-s390.c:424
+#: config/tc-ppc.c:1045 config/tc-s390.c:418 config/tc-s390.c:425
 #, c-format
 msgid "invalid switch -m%s"
 msgstr ""
 
-#: config/tc-ppc.c:1094
+#: config/tc-ppc.c:1081
 #, c-format
 msgid ""
 "PowerPC options:\n"
@@ -8221,7 +8895,7 @@ msgid ""
 "\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"
 msgstr ""
 
-#: config/tc-ppc.c:1108
+#: config/tc-ppc.c:1095
 #, c-format
 msgid ""
 "-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n"
@@ -8230,11 +8904,13 @@ msgid ""
 "-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n"
 "-mpower4\t\tgenerate code for Power4 architecture\n"
 "-mpower5\t\tgenerate code for Power5 architecture\n"
+"-mpower6\t\tgenerate code for Power6 architecture\n"
+"-mcell\t\t\tgenerate code for Cell Broadband Engine architecture\n"
 "-mcom\t\t\tgenerate code Power/PowerPC common instructions\n"
 "-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"
 msgstr ""
 
-#: config/tc-ppc.c:1117
+#: config/tc-ppc.c:1106
 #, c-format
 msgid ""
 "-maltivec\t\tgenerate code for AltiVec\n"
@@ -8245,7 +8921,7 @@ msgid ""
 "-mno-regnames\t\tDo not allow symbolic names for registers\n"
 msgstr ""
 
-#: config/tc-ppc.c:1125
+#: config/tc-ppc.c:1114
 #, c-format
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
@@ -8261,251 +8937,276 @@ msgid ""
 "-Qy, -Qn\t\tignored\n"
 msgstr ""
 
-#: config/tc-ppc.c:1162
+#: config/tc-ppc.c:1151
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
 msgstr ""
 
-#: config/tc-ppc.c:1188
+#: config/tc-ppc.c:1177
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr ""
 
-#: config/tc-ppc.c:1285 config/tc-s390.c:519
+#: config/tc-ppc.c:1256
 #, c-format
-msgid "Internal assembler error for instruction %s"
+msgid "powerpc_operands[%d].bitm invalid"
+msgstr ""
+
+#: config/tc-ppc.c:1263
+#, c-format
+msgid "powerpc_operands[%d] duplicates powerpc_operands[%d]"
+msgstr ""
+
+#: config/tc-ppc.c:1281
+#, c-format
+msgid "mask trims opcode bits for %s"
+msgstr ""
+
+#: config/tc-ppc.c:1290
+#, c-format
+msgid "operand index error for %s"
+msgstr ""
+
+#: config/tc-ppc.c:1302
+#, c-format
+msgid "operand %d overlap in %s"
+msgstr ""
+
+#: config/tc-ppc.c:1344
+#, c-format
+msgid "duplicate instruction %s"
 msgstr ""
 
-#: config/tc-ppc.c:1309
+#: config/tc-ppc.c:1368
 #, c-format
-msgid "Internal assembler error for macro %s"
+msgid "duplicate macro %s"
 msgstr ""
 
-#: config/tc-ppc.c:1640
+#: config/tc-ppc.c:1702
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr ""
 
-#: config/tc-ppc.c:1707
+#: config/tc-ppc.c:1768
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr ""
 
-#: config/tc-ppc.c:1814
+#: config/tc-ppc.c:1873
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-ppc.c:1896
+#: config/tc-ppc.c:1953
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr ""
 
-#: config/tc-ppc.c:1945
+#: config/tc-ppc.c:2002
 msgid "TOC section size exceeds 64k"
 msgstr ""
 
-#: config/tc-ppc.c:2027
+#: config/tc-ppc.c:2083
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:2041
+#: config/tc-ppc.c:2097
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2320
+#: config/tc-ppc.c:2374
 msgid "[tocv] symbol is not a toc symbol"
 msgstr ""
 
-#: config/tc-ppc.c:2331
+#: config/tc-ppc.c:2385
 msgid "Unimplemented toc32 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2336
+#: config/tc-ppc.c:2390
 msgid "Unimplemented toc64 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2340
+#: config/tc-ppc.c:2394
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr ""
 
-#: config/tc-ppc.c:2558
+#: config/tc-ppc.c:2612
 msgid "unsupported relocation for DS offset field"
 msgstr ""
 
-#: config/tc-ppc.c:2602
+#: config/tc-ppc.c:2656
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2645 config/tc-ppc.h:111
+#: config/tc-ppc.c:2699 config/tc-ppc.h:92
 msgid "instruction address is not a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:2756
+#: config/tc-ppc.c:2808
 msgid "wrong number of operands"
 msgstr ""
 
-#: config/tc-ppc.c:2812
+#: config/tc-ppc.c:2862
 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ppc.c:2927
+#: config/tc-ppc.c:2968
 msgid "missing size"
 msgstr ""
 
-#: config/tc-ppc.c:2936
+#: config/tc-ppc.c:2977
 msgid "negative size"
 msgstr ""
 
-#: config/tc-ppc.c:2973
+#: config/tc-ppc.c:3014
 msgid "missing real symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:2994
+#: config/tc-ppc.c:3035
 msgid "attempt to redefine symbol"
 msgstr ""
 
-#: config/tc-ppc.c:3241
+#: config/tc-ppc.c:3277
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr ""
 
-#: config/tc-ppc.c:3318
+#: config/tc-ppc.c:3351
 msgid "missing rename string"
 msgstr ""
 
-#: config/tc-ppc.c:3349 config/tc-ppc.c:3904 read.c:3064
+#: config/tc-ppc.c:3381 config/tc-ppc.c:3923 read.c:3260
 msgid "missing value"
 msgstr ""
 
-#: config/tc-ppc.c:3367
+#: config/tc-ppc.c:3399
 msgid "illegal .stabx expression; zero assumed"
 msgstr ""
 
-#: config/tc-ppc.c:3399
+#: config/tc-ppc.c:3431
 msgid "missing class"
 msgstr ""
 
-#: config/tc-ppc.c:3408
+#: config/tc-ppc.c:3440
 msgid "missing type"
 msgstr ""
 
-#: config/tc-ppc.c:3489
+#: config/tc-ppc.c:3520
 msgid "missing symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:3683
+#: config/tc-ppc.c:3710
 msgid "nested .bs blocks"
 msgstr ""
 
-#: config/tc-ppc.c:3716
+#: config/tc-ppc.c:3742
 msgid ".es without preceding .bs"
 msgstr ""
 
-#: config/tc-ppc.c:3896
+#: config/tc-ppc.c:3915
 msgid "non-constant byte count"
 msgstr ""
 
-#: config/tc-ppc.c:3944
+#: config/tc-ppc.c:3962
 msgid ".tc not in .toc section"
 msgstr ""
 
-#: config/tc-ppc.c:3963
+#: config/tc-ppc.c:3981
 msgid ".tc with no label"
 msgstr ""
 
-#: config/tc-ppc.c:4055
+#: config/tc-ppc.c:4072
 msgid ".machine stack overflow"
 msgstr ""
 
-#: config/tc-ppc.c:4062
+#: config/tc-ppc.c:4079
 msgid ".machine stack underflow"
 msgstr ""
 
-#: config/tc-ppc.c:4069
+#: config/tc-ppc.c:4086
 #, c-format
 msgid "invalid machine `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:4123
+#: config/tc-ppc.c:4137
 msgid "No previous section to return to. Directive ignored."
 msgstr ""
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:4540
+#: config/tc-ppc.c:4547
 msgid "Unsupported section attribute -- 'a'"
 msgstr ""
 
-#: config/tc-ppc.c:4729
+#: config/tc-ppc.c:4731
 msgid "bad symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4822
+#: config/tc-ppc.c:4823
 msgid "Unrecognized symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4912
+#: config/tc-ppc.c:4911
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr ""
 
-#: config/tc-ppc.c:4925
+#: config/tc-ppc.c:4924
 msgid ".ef with no preceding .function"
 msgstr ""
 
-#: config/tc-ppc.c:5053
+#: config/tc-ppc.c:5052
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr ""
 
-#: config/tc-ppc.c:5357
+#: config/tc-ppc.c:5345
 msgid "symbol in .toc does not match any .tc"
 msgstr ""
 
-#: config/tc-ppc.c:5686 config/tc-s390.c:2092 config/tc-v850.c:2314
+#: config/tc-ppc.c:5709 config/tc-s390.c:2093 config/tc-v850.c:2343
 #: config/tc-xstormy16.c:538
 msgid "unresolved expression that must be resolved"
 msgstr ""
 
-#: config/tc-ppc.c:5689
+#: config/tc-ppc.c:5712
 #, c-format
 msgid "unsupported relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5762
+#: config/tc-ppc.c:5785
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5767
+#: config/tc-ppc.c:5790
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr ""
 
-#: config/tc-ppc.c:5949
+#: config/tc-ppc.c:5972
 #, c-format
 msgid "Unable to handle reference to symbol %s"
 msgstr ""
 
-#: config/tc-ppc.c:5952
+#: config/tc-ppc.c:5975
 msgid "Unable to resolve expression"
 msgstr ""
 
-#: config/tc-ppc.c:5979
+#: config/tc-ppc.c:6002
 msgid "must branch to an address a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:5983
+#: config/tc-ppc.c:6006
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr ""
 
-#: config/tc-ppc.c:6014
+#: config/tc-ppc.c:6037
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr ""
 
-#: config/tc-s390.c:460
+#: config/tc-s390.c:461
 #, c-format
 msgid ""
 "        S390 options:\n"
@@ -8516,80 +9217,375 @@ msgid ""
 "        -m64              Set file format to 64 bit format\n"
 msgstr ""
 
-#: config/tc-s390.c:467
+#: config/tc-s390.c:468
 #, c-format
 msgid ""
 "        -V                print assembler version number\n"
 "        -Qy, -Qn          ignored\n"
 msgstr ""
 
-#: config/tc-s390.c:503
+#: config/tc-s390.c:504
 #, c-format
 msgid "Internal assembler error for instruction format %s"
 msgstr ""
 
-#: config/tc-s390.c:766
+#: config/tc-s390.c:520
+#, c-format
+msgid "Internal assembler error for instruction %s"
+msgstr ""
+
+#: config/tc-s390.c:767
 #, c-format
 msgid "identifier+constant@%s means identifier@%s+constant"
 msgstr ""
 
-#: config/tc-s390.c:849
+#: config/tc-s390.c:850
 msgid "Can't handle O_big in s390_exp_compare"
 msgstr ""
 
-#: config/tc-s390.c:933
+#: config/tc-s390.c:934
 msgid "Invalid suffix for literal pool entry"
 msgstr ""
 
-#: config/tc-s390.c:990
+#: config/tc-s390.c:991
 msgid "Big number is too big"
 msgstr ""
 
-#: config/tc-s390.c:1138
+#: config/tc-s390.c:1139
 msgid "relocation not applicable"
 msgstr ""
 
-#: config/tc-s390.c:1326
+#: config/tc-s390.c:1327
 msgid "invalid operand suffix"
 msgstr ""
 
-#: config/tc-s390.c:1349
+#: config/tc-s390.c:1350
 msgid "syntax error; missing '(' after displacement"
 msgstr ""
 
-#: config/tc-s390.c:1365 config/tc-s390.c:1409 config/tc-s390.c:1439
+#: config/tc-s390.c:1366 config/tc-s390.c:1410 config/tc-s390.c:1440
 msgid "syntax error; expected ,"
 msgstr ""
 
-#: config/tc-s390.c:1397
+#: config/tc-s390.c:1398
 msgid "syntax error; missing ')' after base register"
 msgstr ""
 
-#: config/tc-s390.c:1426
+#: config/tc-s390.c:1427
 msgid "syntax error; ')' not allowed here"
 msgstr ""
 
-#: config/tc-s390.c:1619 config/tc-s390.c:1642 config/tc-s390.c:1655
+#: config/tc-s390.c:1620 config/tc-s390.c:1643 config/tc-s390.c:1656
 msgid "Invalid .insn format\n"
 msgstr ""
 
-#: config/tc-s390.c:1627
+#: config/tc-s390.c:1628
 #, c-format
 msgid "Unrecognized opcode format: `%s'"
 msgstr ""
 
-#: config/tc-s390.c:1658
+#: config/tc-s390.c:1659
 msgid "second operand of .insn not a constant\n"
 msgstr ""
 
-#: config/tc-s390.c:1661
+#: config/tc-s390.c:1662
 msgid "missing comma after insn constant\n"
 msgstr ""
 
-#: config/tc-s390.c:2095
+#: config/tc-s390.c:2096
 msgid "unsupported relocation type"
 msgstr ""
 
+#: config/tc-score.c:49
+msgid "instruction is not conditional"
+msgstr ""
+
+#: config/tc-score.c:50
+msgid "acc0 expected"
+msgstr ""
+
+#: config/tc-score.c:51
+msgid "div / mul are reserved instructions"
+msgstr ""
+
+#: config/tc-score.c:52
+msgid "This architecture doesn't support mmu"
+msgstr ""
+
+#: config/tc-score.c:53
+msgid "This architecture doesn't support atomic instruction"
+msgstr ""
+
+#: config/tc-score.c:54
+msgid "the label length is longer than 1024"
+msgstr ""
+
+#: config/tc-score.c:238
+msgid "S+core register expected"
+msgstr ""
+
+#: config/tc-score.c:239
+msgid "S+core special-register expected"
+msgstr ""
+
+#: config/tc-score.c:240
+msgid "S+core co-processor register expected"
+msgstr ""
+
+#: config/tc-score.c:858 config/tc-score.c:1758
+msgid "Using temp register(r1)"
+msgstr ""
+
+#: config/tc-score.c:877
+#, c-format
+msgid "register expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:1263 config/tc-score.c:1270 config/tc-score.c:2645
+#: config/tc-score.c:2650 config/tc-score.c:2928 config/tc-score.c:2933
+#, c-format
+msgid "invalid constant: %d bit expression not in range %d..%d"
+msgstr ""
+
+#: config/tc-score.c:1310
+msgid "invalid constant: bit expression not defined"
+msgstr ""
+
+#: config/tc-score.c:1772
+#, c-format
+msgid "low register(r0-r15)expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:1867
+#, c-format
+msgid "high register(r16-r31)expected, not '%.100s'"
+msgstr ""
+
+#: config/tc-score.c:2099
+#, c-format
+msgid "Fix data dependency: %s %s -- %s %s  (insert %d nop!/%d)"
+msgstr ""
+
+#: config/tc-score.c:2118
+#, c-format
+msgid "Fix data dependency: %s %s -- %s %s  (insert 1 pflush/%d)"
+msgstr ""
+
+#: config/tc-score.c:2134 config/tc-score.c:2141
+#, c-format
+msgid "data dependency: %s %s -- %s %s  (%d/%d bubble)"
+msgstr ""
+
+#: config/tc-score.c:2431 config/tc-score.c:5662
+#, c-format
+msgid "%s -- `%s'"
+msgstr ""
+
+#: config/tc-score.c:2588
+msgid "address offset must be half word alignment"
+msgstr ""
+
+#: config/tc-score.c:2596
+msgid "address offset must be word alignment"
+msgstr ""
+
+#: config/tc-score.c:2738 config/tc-score.c:2885
+msgid "register same as write-back base"
+msgstr ""
+
+#: config/tc-score.c:2855
+msgid "pre-indexed expression expected"
+msgstr ""
+
+#: config/tc-score.c:2865 config/tc-score.c:3223 config/tc-score.c:3239
+#: config/tc-score.c:3310 config/tc-score.c:3353 config/tc-score.c:3475
+#: config/tc-score.c:3549 config/tc-score.c:3603 config/tc-score.c:3649
+msgid "missing ]"
+msgstr ""
+
+#: config/tc-score.c:3466
+msgid "base register nums are over 3 bit"
+msgstr ""
+
+#: config/tc-score.c:3543 config/tc-score.c:3594
+msgid "missing +"
+msgstr ""
+
+#: config/tc-score.c:3587
+#, c-format
+msgid "%s register same as write-back base"
+msgstr ""
+
+#: config/tc-score.c:3589
+msgid "destination"
+msgstr ""
+
+#: config/tc-score.c:3589
+msgid "source"
+msgstr ""
+
+#: config/tc-score.c:3993
+msgid "li rd label isn't correct instruction form"
+msgstr ""
+
+#: config/tc-score.c:4506 config/tc-score.c:4535 config/tc-score.c:4561
+msgid "lacking label  "
+msgstr ""
+
+#: config/tc-score.c:4513
+msgid "invalid constant: 25 bit expression not in range -2^24..2^24"
+msgstr ""
+
+#: config/tc-score.c:4541
+msgid "invalid constant: 12 bit expression not in range -2^11..2^11"
+msgstr ""
+
+#: config/tc-score.c:4567
+msgid "invalid constant: 20 bit expression not in range -2^19..2^19"
+msgstr ""
+
+#: config/tc-score.c:4600
+msgid "lacking label"
+msgstr ""
+
+#: config/tc-score.c:4605
+msgid "invalid constant: 9 bit expression not in range -2^8..2^8"
+msgstr ""
+
+#: config/tc-score.c:5344
+#, c-format
+msgid " branch relocation truncate (0x%x) [-2^8 ~ 2^8]"
+msgstr ""
+
+#: config/tc-score.c:5361 config/tc-score.c:5391
+#, c-format
+msgid " branch relocation truncate (0x%x) [-2^19 ~ 2^19]"
+msgstr ""
+
+#: config/tc-score.c:5415
+#, c-format
+msgid " branch relocation truncate (0x%x)  [-2^8 ~ 2^8]"
+msgstr ""
+
+#: config/tc-score.c:5581
+#, c-format
+msgid "cannot represent %s relocation in this object file format1"
+msgstr ""
+
+#: config/tc-score.c:5640
+msgid "pce instruction error (16 bit || 16 bit)'"
+msgstr ""
+
+#: config/tc-score.c:5770
+#, c-format
+msgid "Sunplus-v2-0-0-20060510\n"
+msgstr ""
+
+#: config/tc-score.c:5786
+#, c-format
+msgid " Score-specific assembler options:\n"
+msgstr ""
+
+#: config/tc-score.c:5788
+#, c-format
+msgid "        -EB\t\tassemble code for a big-endian cpu\n"
+msgstr ""
+
+#: config/tc-score.c:5793
+#, c-format
+msgid "        -EL\t\tassemble code for a little-endian cpu\n"
+msgstr ""
+
+#: config/tc-score.c:5797
+#, c-format
+msgid "        -FIXDD\t\tassemble code for fix data dependency\n"
+msgstr ""
+
+#: config/tc-score.c:5799
+#, c-format
+msgid ""
+"        -NWARN\t\tassemble code for no warning message for fix data "
+"dependency\n"
+msgstr ""
+
+#: config/tc-score.c:5801
+#, c-format
+msgid "        -SCORE5\t\tassemble code for target is SCORE5\n"
+msgstr ""
+
+#: config/tc-score.c:5803
+#, c-format
+msgid "        -SCORE5U\tassemble code for target is SCORE5U\n"
+msgstr ""
+
+#: config/tc-score.c:5805
+#, c-format
+msgid ""
+"        -SCORE7\t\tassemble code for target is SCORE7, this is default "
+"setting\n"
+msgstr ""
+
+#: config/tc-score.c:5807
+#, c-format
+msgid ""
+"        -USE_R1\t\tassemble code for no warning message when using temp "
+"register r1\n"
+msgstr ""
+
+#: config/tc-score.c:5809
+#, c-format
+msgid "        -KPIC\t\tassemble code for PIC\n"
+msgstr ""
+
+#: config/tc-score.c:5811
+#, c-format
+msgid "        -O0\t\tassembler will not perform any optimizations\n"
+msgstr ""
+
+#: config/tc-score.c:5813
+#, c-format
+msgid ""
+"        -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"
+msgstr ""
+
+#: config/tc-score.c:5815
+#, c-format
+msgid "        -V \t\tSunplus release version \n"
+msgstr ""
+
+#: config/tc-score.c:6415 read.c:1459
+msgid "missing size expression"
+msgstr ""
+
+#: config/tc-score.c:6421
+#, c-format
+msgid "BSS length (%d) < 0 ignored"
+msgstr ""
+
+#: config/tc-score.c:6436 read.c:2277
+#, c-format
+msgid "error setting flags for \".sbss\": %s"
+msgstr ""
+
+#: config/tc-score.c:6450 config/tc-sparc.c:3797
+msgid "missing alignment"
+msgstr ""
+
+#: config/tc-score.c:6487
+#, c-format
+msgid "alignment too large; %d assumed"
+msgstr ""
+
+#: config/tc-score.c:6492 read.c:2338
+msgid "alignment negative; 0 assumed"
+msgstr ""
+
+#: config/tc-score.c:6559 config/tc-z80.c:289 ecoff.c:3355 read.c:1478
+#: read.c:1591 read.c:2455 read.c:3002 read.c:3387 symbols.c:326 symbols.c:432
+#, c-format
+msgid "symbol `%s' is already defined"
+msgstr ""
+
 #: config/tc-sh64.c:568
 msgid "This operand must be constant at assembly time"
 msgstr ""
@@ -8672,7 +9668,7 @@ msgstr ""
 
 #: config/tc-sh64.c:1536
 #, c-format
-msgid "invalid operand, not an 16-bit unsigned value: %d"
+msgid "invalid operand, not a 16-bit unsigned value: %d"
 msgstr ""
 
 #: config/tc-sh64.c:1542
@@ -8759,212 +9755,212 @@ msgstr ""
 msgid "-expand-pt32 invalid together with -no-expand"
 msgstr ""
 
-#: config/tc-sh64.c:3201
+#: config/tc-sh64.c:3199
 msgid ""
 "SHmedia code not allowed in same section as constants and SHcompact code"
 msgstr ""
 
-#: config/tc-sh64.c:3219
+#: config/tc-sh64.c:3217
 msgid "No segment info for current section"
 msgstr ""
 
-#: config/tc-sh64.c:3258
+#: config/tc-sh64.c:3256
 msgid "duplicate datalabel operator ignored"
 msgstr ""
 
-#: config/tc-sh64.c:3328
+#: config/tc-sh64.c:3326
 msgid "Invalid DataLabel expression"
 msgstr ""
 
-#: config/tc-sh.c:65
+#: config/tc-sh.c:63
 msgid "directive .big encountered when option -big required"
 msgstr ""
 
-#: config/tc-sh.c:75
+#: config/tc-sh.c:73
 msgid "directive .little encountered when option -little required"
 msgstr ""
 
-#: config/tc-sh.c:1277
+#: config/tc-sh.c:1364
 msgid "misplaced PIC operand"
 msgstr ""
 
-#: config/tc-sh.c:1315
+#: config/tc-sh.c:1402
 msgid "illegal double indirection"
 msgstr ""
 
-#: config/tc-sh.c:1324
+#: config/tc-sh.c:1411
 msgid "illegal register after @-"
 msgstr ""
 
-#: config/tc-sh.c:1340
+#: config/tc-sh.c:1427
 msgid "must be @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1364
+#: config/tc-sh.c:1451
 msgid "syntax error in @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1369
+#: config/tc-sh.c:1456
 msgid "syntax error in @(r0...)"
 msgstr ""
 
-#: config/tc-sh.c:1414
+#: config/tc-sh.c:1501
 msgid "Deprecated syntax."
 msgstr ""
 
-#: config/tc-sh.c:1426 config/tc-sh.c:1431
+#: config/tc-sh.c:1513 config/tc-sh.c:1518
 msgid "syntax error in @(disp,[Rn, gbr, pc])"
 msgstr ""
 
-#: config/tc-sh.c:1436
+#: config/tc-sh.c:1523
 msgid "expecting )"
 msgstr ""
 
-#: config/tc-sh.c:1444
+#: config/tc-sh.c:1531
 msgid "illegal register after @"
 msgstr ""
 
-#: config/tc-sh.c:2115
+#: config/tc-sh.c:2202
 #, c-format
 msgid "unhandled %d\n"
 msgstr ""
 
-#: config/tc-sh.c:2281
+#: config/tc-sh.c:2368
 #, c-format
 msgid "Invalid register: 'r%d'"
 msgstr ""
 
-#: config/tc-sh.c:2385
+#: config/tc-sh.c:2472
 #, c-format
 msgid "failed for %d\n"
 msgstr ""
 
-#: config/tc-sh.c:2498 config/tc-sh.c:2894
+#: config/tc-sh.c:2585 config/tc-sh.c:2984
 msgid "invalid operands for opcode"
 msgstr ""
 
-#: config/tc-sh.c:2503
+#: config/tc-sh.c:2590
 msgid "insn can't be combined with parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2510 config/tc-sh.c:2521 config/tc-sh.c:2553
+#: config/tc-sh.c:2597 config/tc-sh.c:2608 config/tc-sh.c:2640
 msgid "multiple movx specifications"
 msgstr ""
 
-#: config/tc-sh.c:2515 config/tc-sh.c:2537 config/tc-sh.c:2576
+#: config/tc-sh.c:2602 config/tc-sh.c:2624 config/tc-sh.c:2663
 msgid "multiple movy specifications"
 msgstr ""
 
-#: config/tc-sh.c:2524 config/tc-sh.c:2557
+#: config/tc-sh.c:2611 config/tc-sh.c:2644
 msgid "invalid movx address register"
 msgstr ""
 
-#: config/tc-sh.c:2526
+#: config/tc-sh.c:2613
 msgid "insn cannot be combined with non-nopy"
 msgstr ""
 
-#: config/tc-sh.c:2540 config/tc-sh.c:2596
+#: config/tc-sh.c:2627 config/tc-sh.c:2683
 msgid "invalid movy address register"
 msgstr ""
 
-#: config/tc-sh.c:2542
+#: config/tc-sh.c:2629
 msgid "insn cannot be combined with non-nopx"
 msgstr ""
 
-#: config/tc-sh.c:2555
+#: config/tc-sh.c:2642
 msgid "previous movy requires nopx"
 msgstr ""
 
-#: config/tc-sh.c:2563 config/tc-sh.c:2568
+#: config/tc-sh.c:2650 config/tc-sh.c:2655
 msgid "invalid movx dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2578
+#: config/tc-sh.c:2665
 msgid "previous movx requires nopy"
 msgstr ""
 
-#: config/tc-sh.c:2587 config/tc-sh.c:2592
+#: config/tc-sh.c:2674 config/tc-sh.c:2679
 msgid "invalid movy dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2602
+#: config/tc-sh.c:2689
 msgid "dsp immediate shift value not constant"
 msgstr ""
 
-#: config/tc-sh.c:2616 config/tc-sh.c:2642
+#: config/tc-sh.c:2703 config/tc-sh.c:2729
 msgid "multiple parallel processing specifications"
 msgstr ""
 
-#: config/tc-sh.c:2635
+#: config/tc-sh.c:2722
 msgid "multiple condition specifications"
 msgstr ""
 
-#: config/tc-sh.c:2673
+#: config/tc-sh.c:2760
 msgid "insn cannot be combined with pmuls"
 msgstr ""
 
-#: config/tc-sh.c:2689
+#: config/tc-sh.c:2776
 msgid "bad combined pmuls output operand"
 msgstr ""
 
-#: config/tc-sh.c:2699
+#: config/tc-sh.c:2786
 msgid "destination register is same for parallel insns"
 msgstr ""
 
-#: config/tc-sh.c:2708
+#: config/tc-sh.c:2795
 msgid "condition not followed by conditionalizable insn"
 msgstr ""
 
-#: config/tc-sh.c:2718
+#: config/tc-sh.c:2805
 msgid "unrecognized characters at end of parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2834
+#: config/tc-sh.c:2921
 msgid "opcode not valid for this cpu variant"
 msgstr ""
 
-#: config/tc-sh.c:2867
+#: config/tc-sh.c:2954
 msgid "Delayed branches not available on SH1"
 msgstr ""
 
-#: config/tc-sh.c:2899
+#: config/tc-sh.c:2989
 #, c-format
 msgid "excess operands: '%s'"
 msgstr ""
 
-#: config/tc-sh.c:3026
+#: config/tc-sh.c:3116
 msgid ".uses pseudo-op seen when not relaxing"
 msgstr ""
 
-#: config/tc-sh.c:3032
+#: config/tc-sh.c:3122
 msgid "bad .uses format"
 msgstr ""
 
-#: config/tc-sh.c:3130
+#: config/tc-sh.c:3224
 msgid "Invalid combination: --isa=SHcompact with --isa=SHmedia"
 msgstr ""
 
-#: config/tc-sh.c:3136
+#: config/tc-sh.c:3230
 msgid "Invalid combination: --isa=SHmedia with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:3138
+#: config/tc-sh.c:3232
 msgid "Invalid combination: --abi=64 with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:3179
+#: config/tc-sh.c:3273
 msgid "Invalid combination: --abi=32 with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:3185
+#: config/tc-sh.c:3279
 msgid "Invalid combination: --abi=64 with --abi=32"
 msgstr ""
 
-#: config/tc-sh.c:3187
+#: config/tc-sh.c:3281
 msgid "Invalid combination: --isa=SHcompact with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:3221
+#: config/tc-sh.c:3315
 #, c-format
 msgid ""
 "SH options:\n"
@@ -8981,7 +9977,7 @@ msgid ""
 "    | fp"
 msgstr ""
 
-#: config/tc-sh.c:3247
+#: config/tc-sh.c:3341
 #, c-format
 msgid ""
 "--isa=[shmedia\t\tset as the default instruction set for SH64\n"
@@ -8990,7 +9986,7 @@ msgid ""
 "    | SHcompact]\n"
 msgstr ""
 
-#: config/tc-sh.c:3252
+#: config/tc-sh.c:3346
 #, c-format
 msgid ""
 "--abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
@@ -9004,89 +10000,89 @@ msgid ""
 "\t\t\tto 32 bits only\n"
 msgstr ""
 
-#: config/tc-sh.c:3336
+#: config/tc-sh.c:3445
 msgid ".uses does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:3355
+#: config/tc-sh.c:3464
 msgid "can't find fixup pointed to by .uses"
 msgstr ""
 
-#: config/tc-sh.c:3375
+#: config/tc-sh.c:3484
 msgid ".uses target does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:3452
+#: config/tc-sh.c:3561
 msgid "displacement overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3455
+#: config/tc-sh.c:3564
 #, c-format
 msgid "displacement to defined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3459
+#: config/tc-sh.c:3568
 #, c-format
 msgid "displacement to undefined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3532
+#: config/tc-sh.c:3641
 msgid "displacement overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3535
+#: config/tc-sh.c:3644
 #, c-format
 msgid "displacement to defined symbol %s overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3539
+#: config/tc-sh.c:3648
 #, c-format
 msgid "displacement to undefined symbol %s overflows 8-bit field "
 msgstr ""
 
-#: config/tc-sh.c:3556
+#: config/tc-sh.c:3665
 #, c-format
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr ""
 
-#: config/tc-sh.c:3622 config/tc-sh.c:3669 config/tc-sparc.c:4234
-#: config/tc-sparc.c:4259
+#: config/tc-sh.c:3731 config/tc-sh.c:3778 config/tc-sparc.c:4314
+#: config/tc-sparc.c:4339
 msgid "misaligned data"
 msgstr ""
 
-#: config/tc-sh.c:4076
+#: config/tc-sh.c:4206
 msgid "misaligned offset"
 msgstr ""
 
-#: config/tc-sparc.c:288
+#: config/tc-sparc.c:286
 msgid "Invalid default architecture, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:292 config/tc-sparc.c:495
+#: config/tc-sparc.c:290 config/tc-sparc.c:497
 msgid "Bad opcode table, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:487
+#: config/tc-sparc.c:489
 #, c-format
 msgid "invalid architecture -xarch=%s"
 msgstr ""
 
-#: config/tc-sparc.c:489
+#: config/tc-sparc.c:491
 #, c-format
 msgid "invalid architecture -A%s"
 msgstr ""
 
-#: config/tc-sparc.c:556
+#: config/tc-sparc.c:558
 #, c-format
 msgid "No compiled in support for %d bit object file format"
 msgstr ""
 
-#: config/tc-sparc.c:634
+#: config/tc-sparc.c:636
 #, c-format
 msgid "SPARC options:\n"
 msgstr ""
 
-#: config/tc-sparc.c:663
+#: config/tc-sparc.c:665
 #, c-format
 msgid ""
 "\n"
@@ -9098,24 +10094,24 @@ msgid ""
 "-no-relax\t\tavoid changing any jumps and branches\n"
 msgstr ""
 
-#: config/tc-sparc.c:671
+#: config/tc-sparc.c:673
 #, c-format
 msgid "-k\t\t\tgenerate PIC\n"
 msgstr ""
 
-#: config/tc-sparc.c:675
+#: config/tc-sparc.c:677
 #, c-format
 msgid ""
 "-32\t\t\tcreate 32 bit object file\n"
 "-64\t\t\tcreate 64 bit object file\n"
 msgstr ""
 
-#: config/tc-sparc.c:678
+#: config/tc-sparc.c:680
 #, c-format
 msgid "\t\t\t[default is %d]\n"
 msgstr ""
 
-#: config/tc-sparc.c:680
+#: config/tc-sparc.c:682
 #, c-format
 msgid ""
 "-TSO\t\t\tuse Total Store Ordering\n"
@@ -9123,12 +10119,12 @@ msgid ""
 "-RMO\t\t\tuse Relaxed Memory Ordering\n"
 msgstr ""
 
-#: config/tc-sparc.c:684
+#: config/tc-sparc.c:686
 #, c-format
 msgid "\t\t\t[default is %s]\n"
 msgstr ""
 
-#: config/tc-sparc.c:686
+#: config/tc-sparc.c:688
 #, c-format
 msgid ""
 "-KPIC\t\t\tgenerate PIC\n"
@@ -9142,7 +10138,7 @@ msgid ""
 "-s\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-sparc.c:698
+#: config/tc-sparc.c:700
 #, c-format
 msgid ""
 "-EL\t\t\tgenerate code for a little endian machine\n"
@@ -9151,1172 +10147,1181 @@ msgid ""
 "                        instructions and little endian data.\n"
 msgstr ""
 
-#: config/tc-sparc.c:819
+#: config/tc-sparc.c:833
 #, c-format
 msgid "Internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-sparc.c:838
+#: config/tc-sparc.c:852
 #, c-format
 msgid "Internal error: can't find opcode `%s' for `%s'\n"
 msgstr ""
 
-#: config/tc-sparc.c:984
+#: config/tc-sparc.c:998
 msgid "Support for 64-bit arithmetic not compiled in."
 msgstr ""
 
-#: config/tc-sparc.c:1031
+#: config/tc-sparc.c:1045
 msgid "set: number not in 0..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1038
+#: config/tc-sparc.c:1052
 msgid "set: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1098
+#: config/tc-sparc.c:1112
 msgid "setsw: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1147
+#: config/tc-sparc.c:1161
 msgid "setx: temporary register same as destination register"
 msgstr ""
 
-#: config/tc-sparc.c:1218
+#: config/tc-sparc.c:1232
 msgid "setx: illegal temporary register g0"
 msgstr ""
 
-#: config/tc-sparc.c:1316
+#: config/tc-sparc.c:1330
 msgid "FP branch in delay slot"
 msgstr ""
 
-#: config/tc-sparc.c:1331
+#: config/tc-sparc.c:1345
 msgid "FP branch preceded by FP instruction; NOP inserted"
 msgstr ""
 
-#: config/tc-sparc.c:1371
+#: config/tc-sparc.c:1385
 msgid "failed special case insn sanity check"
 msgstr ""
 
-#: config/tc-sparc.c:1461
+#: config/tc-sparc.c:1475
 msgid ": invalid membar mask name"
 msgstr ""
 
-#: config/tc-sparc.c:1477
+#: config/tc-sparc.c:1491
 msgid ": invalid membar mask expression"
 msgstr ""
 
-#: config/tc-sparc.c:1482
+#: config/tc-sparc.c:1496
 msgid ": invalid membar mask number"
 msgstr ""
 
-#: config/tc-sparc.c:1497
+#: config/tc-sparc.c:1511
 msgid ": invalid siam mode expression"
 msgstr ""
 
-#: config/tc-sparc.c:1502
+#: config/tc-sparc.c:1516
 msgid ": invalid siam mode number"
 msgstr ""
 
-#: config/tc-sparc.c:1518
+#: config/tc-sparc.c:1532
 msgid ": invalid prefetch function name"
 msgstr ""
 
-#: config/tc-sparc.c:1526
+#: config/tc-sparc.c:1540
 msgid ": invalid prefetch function expression"
 msgstr ""
 
-#: config/tc-sparc.c:1531
+#: config/tc-sparc.c:1545
 msgid ": invalid prefetch function number"
 msgstr ""
 
-#: config/tc-sparc.c:1559 config/tc-sparc.c:1571
+#: config/tc-sparc.c:1573 config/tc-sparc.c:1585
 msgid ": unrecognizable privileged register"
 msgstr ""
 
-#: config/tc-sparc.c:1595 config/tc-sparc.c:1620
+#: config/tc-sparc.c:1609 config/tc-sparc.c:1621
+msgid ": unrecognizable hyperprivileged register"
+msgstr ""
+
+#: config/tc-sparc.c:1645 config/tc-sparc.c:1670
 msgid ": unrecognizable v9a or v9b ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1600
+#: config/tc-sparc.c:1650
 msgid ": rd on write only ancillary state register"
 msgstr ""
 
 #. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1608
+#: config/tc-sparc.c:1658
 msgid ": unrecognizable v9a ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1644
+#: config/tc-sparc.c:1694
 msgid ": asr number must be between 16 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1652
+#: config/tc-sparc.c:1702
 msgid ": asr number must be between 0 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1662
+#: config/tc-sparc.c:1712
 #, c-format
 msgid ": expecting %asrN"
 msgstr ""
 
-#: config/tc-sparc.c:1844 config/tc-sparc.c:1882 config/tc-sparc.c:2289
-#: config/tc-sparc.c:2325
+#: config/tc-sparc.c:1898 config/tc-sparc.c:1936 config/tc-sparc.c:2343
+#: config/tc-sparc.c:2379
 #, c-format
 msgid "Illegal operands: %%%s requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:1850
+#: config/tc-sparc.c:1904
 #, c-format
 msgid ""
 "Illegal operands: %%%s cannot be used together with other relocs in the insn "
 "()"
 msgstr ""
 
-#: config/tc-sparc.c:1861
+#: config/tc-sparc.c:1915
 #, c-format
 msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
 msgstr ""
 
-#: config/tc-sparc.c:2068
+#: config/tc-sparc.c:2122
 msgid "detected global register use not covered by .register pseudo-op"
 msgstr ""
 
-#: config/tc-sparc.c:2139
+#: config/tc-sparc.c:2193
 msgid ": There are only 64 f registers; [0-63]"
 msgstr ""
 
-#: config/tc-sparc.c:2141 config/tc-sparc.c:2159
+#: config/tc-sparc.c:2195 config/tc-sparc.c:2213
 msgid ": There are only 32 f registers; [0-31]"
 msgstr ""
 
-#: config/tc-sparc.c:2151
+#: config/tc-sparc.c:2205
 msgid ": There are only 32 single precision f registers; [0-31]"
 msgstr ""
 
-#: config/tc-sparc.c:2337
+#: config/tc-sparc.c:2391
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2447
+#: config/tc-sparc.c:2501
 #, c-format
 msgid "Illegal operands: Can't add non-constant expression to %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2457
+#: config/tc-sparc.c:2511
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics involving %%%s() of a relocatable "
 "symbol"
 msgstr ""
 
-#: config/tc-sparc.c:2475
+#: config/tc-sparc.c:2529
 msgid ": PC-relative operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2482
+#: config/tc-sparc.c:2536
 msgid ": TLS operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2515
+#: config/tc-sparc.c:2569
 msgid ": invalid ASI name"
 msgstr ""
 
-#: config/tc-sparc.c:2523
+#: config/tc-sparc.c:2577
 msgid ": invalid ASI expression"
 msgstr ""
 
-#: config/tc-sparc.c:2528
+#: config/tc-sparc.c:2582
 msgid ": invalid ASI number"
 msgstr ""
 
-#: config/tc-sparc.c:2625
+#: config/tc-sparc.c:2679
 msgid "OPF immediate operand out of range (0-0x1ff)"
 msgstr ""
 
-#: config/tc-sparc.c:2630
+#: config/tc-sparc.c:2684
 msgid "non-immediate OPF operand, ignored"
 msgstr ""
 
-#: config/tc-sparc.c:2649
+#: config/tc-sparc.c:2703
 msgid ": invalid cpreg name"
 msgstr ""
 
-#: config/tc-sparc.c:2678
+#: config/tc-sparc.c:2732
 #, c-format
 msgid "Illegal operands%s"
 msgstr ""
 
-#: config/tc-sparc.c:2712
+#: config/tc-sparc.c:2766
 #, c-format
 msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
 msgstr ""
 
-#: config/tc-sparc.c:2748
+#: config/tc-sparc.c:2802
 #, c-format
 msgid "Architecture mismatch on \"%s\"."
 msgstr ""
 
-#: config/tc-sparc.c:2749
+#: config/tc-sparc.c:2803
 #, c-format
 msgid " (Requires %s; requested architecture is %s.)"
 msgstr ""
 
-#: config/tc-sparc.c:3369
+#: config/tc-sparc.c:3423
 #, c-format
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-sparc.c:3679
+#: config/tc-sparc.c:3759
 msgid "Expected comma after name"
 msgstr ""
 
-#: config/tc-sparc.c:3688
+#: config/tc-sparc.c:3768
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr ""
 
-#: config/tc-sparc.c:3700
+#: config/tc-sparc.c:3780
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr ""
 
-#: config/tc-sparc.c:3717
-msgid "missing alignment"
-msgstr ""
-
-#: config/tc-sparc.c:3728
+#: config/tc-sparc.c:3808
 #, c-format
 msgid "alignment too large; assuming %d"
 msgstr ""
 
-#: config/tc-sparc.c:3734 config/tc-sparc.c:3885
+#: config/tc-sparc.c:3814 config/tc-sparc.c:3965
 msgid "negative alignment"
 msgstr ""
 
-#: config/tc-sparc.c:3744 config/tc-sparc.c:3908 read.c:1313 read.c:2143
+#: config/tc-sparc.c:3824 config/tc-sparc.c:3988 read.c:1315 read.c:2350
 msgid "alignment not a power of 2"
 msgstr ""
 
-#: config/tc-sparc.c:3822 config/tc-v850.c:223
+#: config/tc-sparc.c:3902 config/tc-v850.c:222
 msgid "Expected comma after symbol-name"
 msgstr ""
 
-#: config/tc-sparc.c:3832
+#: config/tc-sparc.c:3912
 #, c-format
 msgid ".COMMon length (%lu) out of range ignored"
 msgstr ""
 
-#: config/tc-sparc.c:3865
+#: config/tc-sparc.c:3945
 msgid "Expected comma after common length"
 msgstr ""
 
-#: config/tc-sparc.c:3879
+#: config/tc-sparc.c:3959
 #, c-format
 msgid "alignment too large; assuming %ld"
 msgstr ""
 
-#: config/tc-sparc.c:4025
+#: config/tc-sparc.c:4105
 msgid "Unknown segment type"
 msgstr ""
 
-#: config/tc-sparc.c:4104 config/tc-sparc.c:4114
+#: config/tc-sparc.c:4184 config/tc-sparc.c:4194
 #, c-format
 msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
 msgstr ""
 
-#: config/tc-sparc.c:4132
+#: config/tc-sparc.c:4212
 msgid "redefinition of global register"
 msgstr ""
 
-#: config/tc-sparc.c:4143
+#: config/tc-sparc.c:4223
 #, c-format
 msgid "Register symbol %s already defined."
 msgstr ""
 
-#: config/tc-sparc.c:4352
+#: config/tc-sparc.c:4432
 #, c-format
 msgid "Illegal operands: %%r_plt in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4362
+#: config/tc-sparc.c:4442
 #, c-format
 msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4399
+#: config/tc-sparc.c:4479 config/tc-vax.c:3312
 #, c-format
 msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
 msgstr ""
 
-#: config/tc-sparc.c:4407 config/tc-sparc.c:4438 config/tc-sparc.c:4447
+#: config/tc-sparc.c:4487 config/tc-sparc.c:4518 config/tc-sparc.c:4527
+#: config/tc-vax.c:3320 config/tc-vax.c:3351 config/tc-vax.c:3360
 #, c-format
 msgid "Illegal operands: %%r_%s%d requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:4456
+#: config/tc-sparc.c:4536 config/tc-vax.c:3369
 #, c-format
 msgid "Illegal operands: garbage after %%r_%s%d()"
 msgstr ""
 
-#: config/tc-sparc.h:46
+#: config/tc-sparc.h:60
 msgid "sparc convert_frag\n"
 msgstr ""
 
-#: config/tc-sparc.h:48
+#: config/tc-sparc.h:62 config/tc-z80.h:53
 msgid "estimate_size_before_relax called"
 msgstr ""
 
+#: config/tc-spu.c:126
+#, c-format
+msgid "Can't hash instruction '%s':%s"
+msgstr ""
+
+#: config/tc-spu.c:180
+msgid ""
+"SPU options:\n"
+"  --apuasm\t\t  emulate behaviour of apuasm\n"
+msgstr ""
+
+#: config/tc-spu.c:286
+#, c-format
+msgid "Invalid mnemonic '%s'"
+msgstr ""
+
+#: config/tc-spu.c:292
+#, c-format
+msgid "'%s' is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:324
+#, c-format
+msgid "Error in argument %d.  Expecting:  \"%s\""
+msgstr ""
+
+#: config/tc-spu.c:335
+msgid "Mixing register syntax, with and without '$'."
+msgstr ""
+
+#: config/tc-spu.c:341
+#, c-format
+msgid "Treating '%-*s' as a symbol."
+msgstr ""
+
+#: config/tc-spu.c:551
+msgid "'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:553
+msgid "'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher."
+msgstr ""
+
+#: config/tc-spu.c:596
+#, c-format
+msgid "Using old style, %%lo(expr), please change to PPC style, expr@l."
+msgstr ""
+
+#: config/tc-spu.c:602
+#, c-format
+msgid "Using old style, %%hi(expr), please change to PPC style, expr@h."
+msgstr ""
+
+#: config/tc-spu.c:672 config/tc-spu.c:675
+#, c-format
+msgid "Constant expression %d out of range, [%d, %d]."
+msgstr ""
+
+#: config/tc-spu.c:860
+msgid "Relaxation should never occur"
+msgstr ""
+
+#: config/tc-spu.h:83
+msgid "spu convert_frag\n"
+msgstr ""
+
 #. Only word (et al.), align, or conditionals are allowed within
 #. .struct/.union.
-#: config/tc-tic54x.c:222
+#: config/tc-tic54x.c:220
 msgid "pseudo-op illegal within .struct/.union"
 msgstr ""
 
-#: config/tc-tic54x.c:347
+#: config/tc-tic54x.c:345
 #, c-format
 msgid "C54x-specific command line  options:\n"
 msgstr ""
 
-#: config/tc-tic54x.c:348
+#: config/tc-tic54x.c:346
 #, c-format
 msgid "-mfar-mode | -mf          Use extended addressing\n"
 msgstr ""
 
-#: config/tc-tic54x.c:349
+#: config/tc-tic54x.c:347
 #, c-format
 msgid "-mcpu=<CPU version>       Specify the CPU version\n"
 msgstr ""
 
-#: config/tc-tic54x.c:350
+#: config/tc-tic54x.c:348
 #, c-format
 msgid "-merrors-to-file <filename>\n"
 msgstr ""
 
-#: config/tc-tic54x.c:351
+#: config/tc-tic54x.c:349
 #, c-format
 msgid "-me <filename>            Redirect errors to a file\n"
 msgstr ""
 
-#: config/tc-tic54x.c:473
+#: config/tc-tic54x.c:471
 msgid "Comma and symbol expected for '.asg STRING, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:527
+#: config/tc-tic54x.c:525
 msgid "Unterminated string after absolute expression"
 msgstr ""
 
-#: config/tc-tic54x.c:535
+#: config/tc-tic54x.c:533
 msgid "Comma and symbol expected for '.eval EXPR, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:547
+#: config/tc-tic54x.c:545
 msgid "symbols assigned with .eval must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:805
+#: config/tc-tic54x.c:803
 msgid "Offset on nested structures is ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:856
+#: config/tc-tic54x.c:854
 #, c-format
 msgid ".end%s without preceding .%s"
 msgstr ""
 
-#: config/tc-tic54x.c:923
+#: config/tc-tic54x.c:921
 #, c-format
 msgid "Unrecognized struct/union tag '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:925
+#: config/tc-tic54x.c:923
 msgid ".tag requires a structure tag"
 msgstr ""
 
-#: config/tc-tic54x.c:931
+#: config/tc-tic54x.c:929
 msgid "Label required for .tag"
 msgstr ""
 
-#: config/tc-tic54x.c:950
+#: config/tc-tic54x.c:948
 #, c-format
 msgid ".tag target '%s' undefined"
 msgstr ""
 
-#: config/tc-tic54x.c:1013
+#: config/tc-tic54x.c:1011
 #, c-format
 msgid ".field count '%d' out of range (1 <= X <= 32)"
 msgstr ""
 
-#: config/tc-tic54x.c:1041
+#: config/tc-tic54x.c:1039
 #, c-format
 msgid "Unrecognized field type '%c'"
 msgstr ""
 
 #. Disallow .byte with a non constant expression that will
 #. require relocation.
-#: config/tc-tic54x.c:1178
+#: config/tc-tic54x.c:1176
 msgid "Relocatable values require at least WORD storage"
 msgstr ""
 
-#: config/tc-tic54x.c:1240
+#: config/tc-tic54x.c:1238
 msgid "Use of .def/.ref is deprecated.  Use .global instead"
 msgstr ""
 
-#: config/tc-tic54x.c:1439
+#: config/tc-tic54x.c:1437
 msgid ".space/.bes repeat count is negative, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1444
+#: config/tc-tic54x.c:1442
 msgid ".space/.bes repeat count is zero, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1522
+#: config/tc-tic54x.c:1520
 msgid "Missing size argument"
 msgstr ""
 
-#: config/tc-tic54x.c:1659
+#: config/tc-tic54x.c:1657
 msgid "CPU version has already been set"
 msgstr ""
 
-#: config/tc-tic54x.c:1663
+#: config/tc-tic54x.c:1661
 #, c-format
 msgid "Unrecognized version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:1669
+#: config/tc-tic54x.c:1667
 msgid "Changing of CPU version on the fly not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:1805
+#: config/tc-tic54x.c:1803
 msgid "p2align not supported on this target"
 msgstr ""
 
-#: config/tc-tic54x.c:1818
+#: config/tc-tic54x.c:1816
 msgid "Argument to .even ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1865
+#: config/tc-tic54x.c:1863
 msgid "Invalid field size, must be from 1 to 32"
 msgstr ""
 
-#: config/tc-tic54x.c:1878
+#: config/tc-tic54x.c:1876
 msgid "field size must be 16 when value is relocatable"
 msgstr ""
 
-#: config/tc-tic54x.c:1893
+#: config/tc-tic54x.c:1891
 msgid "field value truncated"
 msgstr ""
 
-#: config/tc-tic54x.c:2002 config/tc-tic54x.c:2319
+#: config/tc-tic54x.c:2000 config/tc-tic54x.c:2317
 #, c-format
 msgid "Unrecognized section '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2011
+#: config/tc-tic54x.c:2009
 msgid "Current section is unitialized, section name required for .clink"
 msgstr ""
 
-#: config/tc-tic54x.c:2225
+#: config/tc-tic54x.c:2223
 msgid "ENDLOOP without corresponding LOOP"
 msgstr ""
 
-#: config/tc-tic54x.c:2269
+#: config/tc-tic54x.c:2267
 msgid "Mixing of normal and extended addressing not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:2275
+#: config/tc-tic54x.c:2273
 msgid "Extended addressing not supported on the specified CPU"
 msgstr ""
 
-#: config/tc-tic54x.c:2325
+#: config/tc-tic54x.c:2323
 msgid ".sblock may be used for initialized sections only"
 msgstr ""
 
-#: config/tc-tic54x.c:2356
+#: config/tc-tic54x.c:2354
 msgid "Symbol missing for .set/.equ"
 msgstr ""
 
-#: config/tc-tic54x.c:2415
+#: config/tc-tic54x.c:2413
 msgid ".var may only be used within a macro definition"
 msgstr ""
 
-#: config/tc-tic54x.c:2423
+#: config/tc-tic54x.c:2421
 msgid "Substitution symbols must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:2517
+#: config/tc-tic54x.c:2515
 #, c-format
-msgid "Can't open macro library file '%s' for reading."
+msgid "can't open macro library file '%s' for reading: %s"
 msgstr ""
 
-#: config/tc-tic54x.c:2524
+#: config/tc-tic54x.c:2522
 #, c-format
 msgid "File '%s' not in macro archive format"
 msgstr ""
 
-#: config/tc-tic54x.c:2656
+#: config/tc-tic54x.c:2654
 #, c-format
 msgid "Bad COFF version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2665
+#: config/tc-tic54x.c:2663
 #, c-format
 msgid "Bad CPU version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2678 config/tc-tic54x.c:2681
+#: config/tc-tic54x.c:2676 config/tc-tic54x.c:2679
 #, c-format
 msgid "Can't redirect stderr to the file '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2809
+#: config/tc-tic54x.c:2807
 #, c-format
 msgid "Undefined substitution symbol '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3466
+#: config/tc-tic54x.c:3464
 msgid "Badly formed address expression"
 msgstr ""
 
-#: config/tc-tic54x.c:3730
+#: config/tc-tic54x.c:3728
 #, c-format
 msgid "Invalid dmad syntax '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3796
+#: config/tc-tic54x.c:3794
 #, c-format
 msgid ""
 "Use the .mmregs directive to use memory-mapped register names such as '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3849
+#: config/tc-tic54x.c:3847
 msgid "Address mode *+ARx is write-only. Results of reading are undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:3869
+#: config/tc-tic54x.c:3867
 #, c-format
 msgid "Unrecognized indirect address format \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:3908
+#: config/tc-tic54x.c:3906
 #, c-format
 msgid "Operand '%s' out of range (%d <= x <= %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:3928
+#: config/tc-tic54x.c:3926
 msgid "Error in relocation handling"
 msgstr ""
 
-#: config/tc-tic54x.c:3949 config/tc-tic54x.c:4013 config/tc-tic54x.c:4045
+#: config/tc-tic54x.c:3947 config/tc-tic54x.c:4011 config/tc-tic54x.c:4043
 #, c-format
 msgid "Unrecognized condition code \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:3966
+#: config/tc-tic54x.c:3964
 #, c-format
 msgid "Condition \"%s\" does not match preceding group"
 msgstr ""
 
-#: config/tc-tic54x.c:3974
+#: config/tc-tic54x.c:3972
 #, c-format
 msgid ""
 "Condition \"%s\" uses a different accumulator from a preceding condition"
 msgstr ""
 
-#: config/tc-tic54x.c:3981
+#: config/tc-tic54x.c:3979
 msgid "Only one comparison conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:3986
+#: config/tc-tic54x.c:3984
 msgid "Only one overflow conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:3994
+#: config/tc-tic54x.c:3992
 #, c-format
 msgid "Duplicate %s conditional"
 msgstr ""
 
-#: config/tc-tic54x.c:4029
+#: config/tc-tic54x.c:4027
 msgid "Invalid auxiliary register (use AR0-AR7)"
 msgstr ""
 
-#: config/tc-tic54x.c:4065
+#: config/tc-tic54x.c:4063
 msgid "lk addressing modes are invalid for memory-mapped register addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:4073
+#: config/tc-tic54x.c:4071
 msgid ""
 "Address mode *+ARx is not allowed in memory-mapped register addressing.  "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:4099
+#: config/tc-tic54x.c:4097
 msgid ""
 "Destination accumulator for each part of this parallel instruction must be "
 "different"
 msgstr ""
 
-#: config/tc-tic54x.c:4148
+#: config/tc-tic54x.c:4146
 #, c-format
 msgid "Memory mapped register \"%s\" out of range"
 msgstr ""
 
-#: config/tc-tic54x.c:4187
+#: config/tc-tic54x.c:4185
 msgid "Invalid operand (use 1, 2, or 3)"
 msgstr ""
 
-#: config/tc-tic54x.c:4212
+#: config/tc-tic54x.c:4210
 msgid "A status register or status bit name is required"
 msgstr ""
 
-#: config/tc-tic54x.c:4222
+#: config/tc-tic54x.c:4220
 #, c-format
 msgid "Unrecognized status bit \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4245
+#: config/tc-tic54x.c:4243
 #, c-format
 msgid "Invalid status register \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4257
+#: config/tc-tic54x.c:4255
 #, c-format
 msgid "Operand \"%s\" out of range (use 1 or 2)"
 msgstr ""
 
-#: config/tc-tic54x.c:4465
+#: config/tc-tic54x.c:4463
 #, c-format
 msgid "Unrecognized instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4494
+#: config/tc-tic54x.c:4492
 #, c-format
 msgid "Unrecognized operand list '%s' for instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4526
+#: config/tc-tic54x.c:4524
 #, c-format
 msgid "Unrecognized parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4577
+#: config/tc-tic54x.c:4575
 #, c-format
 msgid "Invalid operand (s) for parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4580
+#: config/tc-tic54x.c:4578
 #, c-format
 msgid "Unrecognized parallel instruction combination \"%s || %s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4817
+#: config/tc-tic54x.c:4815
 #, c-format
 msgid "%s symbol recursion stopped at second appearance of '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4857
+#: config/tc-tic54x.c:4855
 msgid "Unrecognized substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4862
+#: config/tc-tic54x.c:4860
 msgid "Missing '(' after substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4876
+#: config/tc-tic54x.c:4874
 msgid "Expecting second argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4889 config/tc-tic54x.c:4939
+#: config/tc-tic54x.c:4887 config/tc-tic54x.c:4937
 msgid "Extra junk in function call, expecting ')'"
 msgstr ""
 
-#: config/tc-tic54x.c:4915
+#: config/tc-tic54x.c:4913
 msgid "Function expects two arguments"
 msgstr ""
 
-#: config/tc-tic54x.c:4928
+#: config/tc-tic54x.c:4926
 msgid "Expecting character constant argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4934
+#: config/tc-tic54x.c:4932
 msgid "Both arguments must be substitution symbols"
 msgstr ""
 
-#: config/tc-tic54x.c:4987
+#: config/tc-tic54x.c:4985
 #, c-format
 msgid "Invalid subscript (use 1 to %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:4997
+#: config/tc-tic54x.c:4995
 #, c-format
 msgid "Invalid length (use 0 to %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5007
+#: config/tc-tic54x.c:5005
 msgid "Missing ')' in subscripted substitution symbol expression"
 msgstr ""
 
-#: config/tc-tic54x.c:5027
+#: config/tc-tic54x.c:5025
 msgid "Missing forced substitution terminator ':'"
 msgstr ""
 
-#: config/tc-tic54x.c:5182
+#: config/tc-tic54x.c:5180
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left)"
 msgstr ""
 
-#: config/tc-tic54x.c:5223
+#: config/tc-tic54x.c:5221
 #, c-format
 msgid "Unrecognized parallel instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:5235
+#: config/tc-tic54x.c:5233
 #, c-format
 msgid "Instruction '%s' requires an LP cpu version"
 msgstr ""
 
-#: config/tc-tic54x.c:5242
+#: config/tc-tic54x.c:5240
 #, c-format
 msgid "Instruction '%s' requires far mode addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:5254
+#: config/tc-tic54x.c:5252
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left). Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5264
+#: config/tc-tic54x.c:5262
 msgid ""
 "Instructions which cause PC discontinuity are not allowed in a delay slot. "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5275
+#: config/tc-tic54x.c:5273
 #, c-format
 msgid "'%s' is not repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5279
+#: config/tc-tic54x.c:5277
 msgid ""
 "Instructions using long offset modifiers or absolute addresses are not "
 "repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5459
+#: config/tc-tic54x.c:5457
 #, c-format
 msgid "Unsupported relocation size %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5602
+#: config/tc-tic54x.c:5600
 msgid "non-absolute value used with .space/.bes"
 msgstr ""
 
-#: config/tc-tic54x.c:5606
+#: config/tc-tic54x.c:5604
 #, c-format
 msgid "negative value ignored in %s"
 msgstr ""
 
-#: config/tc-tic54x.c:5695
+#: config/tc-tic54x.c:5693
 #, c-format
 msgid "attempt to .space/.bes backwards? (%ld)"
 msgstr ""
 
-#: config/tc-tic54x.c:5729
+#: config/tc-tic54x.c:5727
 #, c-format
 msgid "Invalid label '%s'"
 msgstr ""
 
-#: config/tc-v850.c:234
+#: config/tc-v850.c:233
 #, c-format
 msgid ".COMMon length (%d.) < 0! Ignored."
 msgstr ""
 
-#: config/tc-v850.c:255
+#: config/tc-v850.c:254
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
 msgstr ""
 
-#: config/tc-v850.c:281
+#: config/tc-v850.c:280
 msgid "Common alignment negative; 0 assumed"
 msgstr ""
 
-#: config/tc-v850.c:939
+#: config/tc-v850.c:938
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr ""
 
-#: config/tc-v850.c:940
+#: config/tc-v850.c:939
 msgid "internal failure in parse_register_list"
 msgstr ""
 
-#: config/tc-v850.c:956
+#: config/tc-v850.c:955
 msgid "constant expression or register list expected"
 msgstr ""
 
-#: config/tc-v850.c:961 config/tc-v850.c:974 config/tc-v850.c:993
+#: config/tc-v850.c:960 config/tc-v850.c:973 config/tc-v850.c:992
 msgid "high bits set in register list expression"
 msgstr ""
 
-#: config/tc-v850.c:1032 config/tc-v850.c:1095
+#: config/tc-v850.c:1031 config/tc-v850.c:1094
 msgid "illegal register included in list"
 msgstr ""
 
-#: config/tc-v850.c:1038
+#: config/tc-v850.c:1037
 msgid "system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1043
+#: config/tc-v850.c:1042
 msgid "PSW cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1050
+#: config/tc-v850.c:1049
 msgid "High value system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1074
+#: config/tc-v850.c:1073
 msgid "second register should follow dash in register list"
 msgstr ""
 
-#: config/tc-v850.c:1119
+#: config/tc-v850.c:1118
 #, c-format
 msgid " V850 options:\n"
 msgstr ""
 
-#: config/tc-v850.c:1120
+#: config/tc-v850.c:1119
 #, c-format
 msgid "  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1121
+#: config/tc-v850.c:1120
 #, c-format
 msgid ""
 "  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1122
+#: config/tc-v850.c:1121
 #, c-format
 msgid "  -mv850                    The code is targeted at the v850\n"
 msgstr ""
 
-#: config/tc-v850.c:1123
+#: config/tc-v850.c:1122
 #, c-format
 msgid "  -mv850e                   The code is targeted at the v850e\n"
 msgstr ""
 
-#: config/tc-v850.c:1124
+#: config/tc-v850.c:1123
 #, c-format
 msgid "  -mv850e1                  The code is targeted at the v850e1\n"
 msgstr ""
 
-#: config/tc-v850.c:1125
+#: config/tc-v850.c:1124
 #, c-format
 msgid ""
 "  -mv850any                 The code is generic, despite any processor "
 "specific instructions\n"
 msgstr ""
 
-#: config/tc-v850.c:1126
+#: config/tc-v850.c:1125
 #, c-format
 msgid "  -mrelax                   Enable relaxation\n"
 msgstr ""
 
-#: config/tc-v850.c:1308
+#: config/tc-v850.c:1323
 #, c-format
 msgid "Unable to determine default target processor from string: %s"
 msgstr ""
 
-#: config/tc-v850.c:1343
+#: config/tc-v850.c:1358
 msgid "lo() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1360
+#: config/tc-v850.c:1375
 msgid "ctoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1382
+#: config/tc-v850.c:1397
 msgid "sdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1404
+#: config/tc-v850.c:1419
 msgid "zdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1437
+#: config/tc-v850.c:1452
 msgid "tdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1642
+#: config/tc-v850.c:1657
 msgid "Target processor does not support this instruction."
 msgstr ""
 
-#: config/tc-v850.c:1731 config/tc-v850.c:1760 config/tc-v850.c:1940
+#: config/tc-v850.c:1746 config/tc-v850.c:1775 config/tc-v850.c:1955
 msgid "immediate operand is too large"
 msgstr ""
 
-#: config/tc-v850.c:1742
+#: config/tc-v850.c:1757
 msgid "AAARG -> unhandled constant reloc"
 msgstr ""
 
-#: config/tc-v850.c:1785
+#: config/tc-v850.c:1800
 msgid "invalid register name"
 msgstr ""
 
-#: config/tc-v850.c:1789
+#: config/tc-v850.c:1804
 msgid "register r0 cannot be used here"
 msgstr ""
 
-#: config/tc-v850.c:1800
+#: config/tc-v850.c:1815
 msgid "invalid system register name"
 msgstr ""
 
-#: config/tc-v850.c:1812
+#: config/tc-v850.c:1827
 msgid "expected EP register"
 msgstr ""
 
-#: config/tc-v850.c:1828
+#: config/tc-v850.c:1843
 msgid "invalid condition code name"
 msgstr ""
 
-#: config/tc-v850.c:1848 config/tc-v850.c:1852
+#: config/tc-v850.c:1863 config/tc-v850.c:1867
 msgid "constant too big to fit into instruction"
 msgstr ""
 
-#: config/tc-v850.c:1905
+#: config/tc-v850.c:1920
 msgid "syntax error: value is missing before the register name"
 msgstr ""
 
-#: config/tc-v850.c:1907
+#: config/tc-v850.c:1922
 msgid "syntax error: register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1920
+#: config/tc-v850.c:1935
 msgid "syntax error: system register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1924
+#: config/tc-v850.c:1939
 msgid "syntax error: condition code not expected"
 msgstr ""
 
-#: config/tc-v850.c:1958
+#: config/tc-v850.c:1973 config/tc-xtensa.c:11545
 msgid "invalid operand"
 msgstr ""
 
-#: config/tc-vax.c:290
-#, c-format
-msgid "VIP_BEGIN error:%s"
-msgstr ""
-
-#: config/tc-vax.c:461
-#, c-format
-msgid "Ignoring statement due to \"%s\""
-msgstr ""
-
-#: config/tc-vax.c:480
-#, c-format
-msgid "Aborting because statement has \"%s\""
-msgstr ""
-
-#: config/tc-vax.c:527
-msgid "Can't relocate expression"
-msgstr ""
-
-#: config/tc-vax.c:630
-msgid "Bignum not permitted in short literal. Immediate mode assumed."
-msgstr ""
-
-#: config/tc-vax.c:639
-msgid "Can't do flonum short literal: immediate mode used."
-msgstr ""
-
-#: config/tc-vax.c:684
-#, c-format
-msgid "A bignum/flonum may not be a displacement: 0x%lx used"
-msgstr ""
-
-#: config/tc-vax.c:1007
-#, c-format
-msgid "Short literal overflow(%ld.), immediate mode assumed."
-msgstr ""
-
-#: config/tc-vax.c:1016
-#, c-format
-msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
-msgstr ""
-
-#: config/tc-vax.c:1081
-msgid "Length specification ignored. Address mode 9F used"
-msgstr ""
-
-#: config/tc-vax.c:1142
-msgid "Invalid operand:  immediate value used as base address."
-msgstr ""
-
-#: config/tc-vax.c:1144
-msgid "Invalid operand:  immediate value used as address."
-msgstr ""
-
-#: config/tc-vax.c:1169
-msgid "Symbol used as immediate operand in PIC mode."
-msgstr ""
-
-#: config/tc-vax.c:1942
-msgid "odd number of bytes in operand description"
-msgstr ""
-
-#: config/tc-vax.c:1958
-msgid "Bad operand"
-msgstr ""
-
-#: config/tc-vax.c:1963
-msgid "Not enough operands"
-msgstr ""
-
-#: config/tc-vax.c:1970
-msgid "Too many operands"
-msgstr ""
-
-#: config/tc-vax.c:2533
+#: config/tc-vax.c:1343
 msgid "no '[' to match ']'"
 msgstr ""
 
-#: config/tc-vax.c:2553
+#: config/tc-vax.c:1359
 msgid "bad register in []"
 msgstr ""
 
-#: config/tc-vax.c:2555
+#: config/tc-vax.c:1361
 msgid "[PC] index banned"
 msgstr ""
 
-#: config/tc-vax.c:2590
+#: config/tc-vax.c:1397
 msgid "no '(' to match ')'"
 msgstr ""
 
-#: config/tc-vax.c:2730
+#: config/tc-vax.c:1513
 msgid "invalid branch operand"
 msgstr ""
 
-#: config/tc-vax.c:2759
+#: config/tc-vax.c:1540
 msgid "address prohibits @"
 msgstr ""
 
-#: config/tc-vax.c:2761
+#: config/tc-vax.c:1542
 msgid "address prohibits #"
 msgstr ""
 
-#: config/tc-vax.c:2765
+#: config/tc-vax.c:1546
 msgid "address prohibits -()"
 msgstr ""
 
-#: config/tc-vax.c:2767
+#: config/tc-vax.c:1548
 msgid "address prohibits ()+"
 msgstr ""
 
-#: config/tc-vax.c:2770
+#: config/tc-vax.c:1551
 msgid "address prohibits ()"
 msgstr ""
 
-#: config/tc-vax.c:2772
+#: config/tc-vax.c:1553
 msgid "address prohibits []"
 msgstr ""
 
-#: config/tc-vax.c:2774
+#: config/tc-vax.c:1555
 msgid "address prohibits register"
 msgstr ""
 
-#: config/tc-vax.c:2776
+#: config/tc-vax.c:1557
 msgid "address prohibits displacement length specifier"
 msgstr ""
 
-#: config/tc-vax.c:2806
+#: config/tc-vax.c:1585
 msgid "invalid operand of S^#"
 msgstr ""
 
-#: config/tc-vax.c:2823
+#: config/tc-vax.c:1598
 msgid "S^# needs expression"
 msgstr ""
 
-#: config/tc-vax.c:2830
+#: config/tc-vax.c:1605
 msgid "S^# may only read-access"
 msgstr ""
 
-#: config/tc-vax.c:2855
+#: config/tc-vax.c:1628
 msgid "invalid operand of -()"
 msgstr ""
 
-#: config/tc-vax.c:2861
+#: config/tc-vax.c:1634
 msgid "-(PC) unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2863
+#: config/tc-vax.c:1636
 msgid "[]index same as -()register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2899
+#: config/tc-vax.c:1668
 msgid "invalid operand of ()+"
 msgstr ""
 
-#: config/tc-vax.c:2905
+#: config/tc-vax.c:1674
 msgid "(PC)+ unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2907
+#: config/tc-vax.c:1676
 msgid "[]index same as ()+register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2932
+#: config/tc-vax.c:1699
 msgid "# conflicts length"
 msgstr ""
 
-#: config/tc-vax.c:2934
+#: config/tc-vax.c:1701
 msgid "# bars register"
 msgstr ""
 
-#: config/tc-vax.c:2956
+#: config/tc-vax.c:1721
 msgid "writing or modifying # is unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2986
+#: config/tc-vax.c:1747
 msgid "length not needed"
 msgstr ""
 
-#: config/tc-vax.c:2993
+#: config/tc-vax.c:1754
 msgid "can't []index a register, because it has no address"
 msgstr ""
 
-#: config/tc-vax.c:2995
+#: config/tc-vax.c:1756
 msgid "a register has no address"
 msgstr ""
 
-#: config/tc-vax.c:3006
+#: config/tc-vax.c:1765
 msgid "PC part of operand unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:3281
+#: config/tc-vax.c:1921
+msgid "odd number of bytes in operand description"
+msgstr ""
+
+#: config/tc-vax.c:1935
+msgid "Bad operand"
+msgstr ""
+
+#: config/tc-vax.c:1940
+msgid "Not enough operands"
+msgstr ""
+
+#: config/tc-vax.c:1947
+msgid "Too many operands"
+msgstr ""
+
+#: config/tc-vax.c:2217
 msgid "SYMBOL TABLE not implemented"
 msgstr ""
 
-#: config/tc-vax.c:3285
+#: config/tc-vax.c:2221
 msgid "TOKEN TRACE not implemented"
 msgstr ""
 
-#: config/tc-vax.c:3289
+#: config/tc-vax.c:2225
 #, c-format
 msgid "Displacement length %s ignored!"
 msgstr ""
 
-#: config/tc-vax.c:3293
+#: config/tc-vax.c:2229
 #, c-format
 msgid "I don't need or use temp. file \"%s\"."
 msgstr ""
 
-#: config/tc-vax.c:3297
+#: config/tc-vax.c:2233
 msgid "I don't use an interpass file! -V ignored"
 msgstr ""
 
-#: config/tc-vax.c:3354
+#: config/tc-vax.c:2290
 #, c-format
 msgid ""
 "VAX options:\n"
@@ -10328,7 +11333,7 @@ msgid ""
 "-V\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-vax.c:3363
+#: config/tc-vax.c:2299
 #, c-format
 msgid ""
 "VMS options:\n"
@@ -10340,6 +11345,69 @@ msgid ""
 "-v\"VERSION\"\t\tcode being assembled was produced by compiler \"VERSION\"\n"
 msgstr ""
 
+#: config/tc-vax.c:2464
+#, c-format
+msgid "Ignoring statement due to \"%s\""
+msgstr ""
+
+#: config/tc-vax.c:2481
+#, c-format
+msgid "Aborting because statement has \"%s\""
+msgstr ""
+
+#: config/tc-vax.c:2526
+msgid "Can't relocate expression"
+msgstr ""
+
+#: config/tc-vax.c:2629
+msgid "Bignum not permitted in short literal. Immediate mode assumed."
+msgstr ""
+
+#: config/tc-vax.c:2638
+msgid "Can't do flonum short literal: immediate mode used."
+msgstr ""
+
+#: config/tc-vax.c:2685
+#, c-format
+msgid "A bignum/flonum may not be a displacement: 0x%lx used"
+msgstr ""
+
+#: config/tc-vax.c:2996
+#, c-format
+msgid "Short literal overflow(%ld.), immediate mode assumed."
+msgstr ""
+
+#: config/tc-vax.c:3005
+#, c-format
+msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
+msgstr ""
+
+#: config/tc-vax.c:3070
+msgid "Length specification ignored. Address mode 9F used"
+msgstr ""
+
+#: config/tc-vax.c:3128
+msgid "Invalid operand:  immediate value used as base address."
+msgstr ""
+
+#: config/tc-vax.c:3130
+msgid "Invalid operand:  immediate value used as address."
+msgstr ""
+
+#: config/tc-vax.c:3155
+msgid "Symbol used as immediate operand in PIC mode."
+msgstr ""
+
+#: config/tc-vax.c:3258
+#, c-format
+msgid "VIP_BEGIN error:%s"
+msgstr ""
+
+#: config/tc-xc16x.c:211
+#, c-format
+msgid " XC16X specific command line options:\n"
+msgstr ""
+
 #: config/tc-xstormy16.c:78
 #, c-format
 msgid " XSTORMY16 specific command line options:\n"
@@ -10350,715 +11418,740 @@ msgstr ""
 msgid "internal error: can't install fix for reloc type %d (`%s')"
 msgstr ""
 
-#: config/tc-xtensa.c:590
+#: config/tc-xtensa.c:602
 msgid "illegal range of target hardware versions"
 msgstr ""
 
-#: config/tc-xtensa.c:738
+#: config/tc-xtensa.c:751
 msgid "--density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:741
+#: config/tc-xtensa.c:754
 msgid "--no-density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:750
+#: config/tc-xtensa.c:763
 msgid "--generics is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:753
+#: config/tc-xtensa.c:766
 msgid "--no-generics is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:756
+#: config/tc-xtensa.c:769
 msgid "--relax is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:759
+#: config/tc-xtensa.c:772
 msgid "--no-relax is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:776
+#: config/tc-xtensa.c:789
 msgid "--absolute-literals option not supported in this Xtensa configuration"
 msgstr ""
 
-#: config/tc-xtensa.c:849
+#: config/tc-xtensa.c:862
 msgid "prefer-l32r conflicts with prefer-const16"
 msgstr ""
 
-#: config/tc-xtensa.c:855
+#: config/tc-xtensa.c:868
 msgid "prefer-const16 conflicts with prefer-l32r"
 msgstr ""
 
-#: config/tc-xtensa.c:863 config/tc-xtensa.c:872 config/tc-xtensa.c:876
+#: config/tc-xtensa.c:876 config/tc-xtensa.c:885 config/tc-xtensa.c:889
 msgid "invalid target hardware version"
 msgstr ""
 
-#: config/tc-xtensa.c:1078
+#: config/tc-xtensa.c:1064
 msgid "unmatched end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1107
+#: config/tc-xtensa.c:1093
 msgid ".begin directive with no matching .end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1148
+#: config/tc-xtensa.c:1134
 msgid "[no-]generics is deprecated; use [no-]transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1153
+#: config/tc-xtensa.c:1139
 msgid "[no-]relax is deprecated; use [no-]transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1166
+#: config/tc-xtensa.c:1152
 #, c-format
 msgid "directive %s cannot be negated"
 msgstr ""
 
-#: config/tc-xtensa.c:1172
+#: config/tc-xtensa.c:1158
 msgid "unknown directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1194 config/tc-xtensa.c:1300 config/tc-xtensa.c:1573
-#: config/tc-xtensa.c:5496
+#: config/tc-xtensa.c:1179 config/tc-xtensa.c:1275 config/tc-xtensa.c:1517
+#: config/tc-xtensa.c:5545
 msgid "directives are not valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:1206
+#: config/tc-xtensa.c:1191
 msgid ".begin literal is deprecated; use .literal instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1220
+#: config/tc-xtensa.c:1205
 msgid "cannot set literal_prefix inside literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:1263
+#: config/tc-xtensa.c:1238
 msgid ".begin [no-]density is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1270 config/tc-xtensa.c:1320
+#: config/tc-xtensa.c:1245 config/tc-xtensa.c:1295
 msgid "Xtensa absolute literals option not supported; ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1313
+#: config/tc-xtensa.c:1288
 msgid ".end [no-]density is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1338
+#: config/tc-xtensa.c:1313
 #, c-format
 msgid "does not match begin %s%s at %s:%d"
 msgstr ""
 
-#: config/tc-xtensa.c:1393
+#: config/tc-xtensa.c:1368
 msgid ".literal_position inside literal directive; ignoring"
 msgstr ""
 
-#: config/tc-xtensa.c:1413
+#: config/tc-xtensa.c:1388
 msgid ".literal not allowed inside .begin literal region"
 msgstr ""
 
-#: config/tc-xtensa.c:1449
+#: config/tc-xtensa.c:1424
 msgid "expected comma or colon after symbol name; rest of line ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1542
+#: config/tc-xtensa.c:1486
 msgid "fall through frequency must be greater than 0"
 msgstr ""
 
-#: config/tc-xtensa.c:1550
+#: config/tc-xtensa.c:1494
 msgid "branch target frequency must be greater than 0"
 msgstr ""
 
-#: config/tc-xtensa.c:1598
+#: config/tc-xtensa.c:1542
 #, c-format
 msgid "opcode-specific %s relocation used outside an instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:1751 config/tc-xtensa.c:1768
+#: config/tc-xtensa.c:1721 config/tc-xtensa.c:1738
 #, c-format
 msgid "bad register name: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1757
+#: config/tc-xtensa.c:1727
 #, c-format
 msgid "bad register number: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1836
+#: config/tc-xtensa.c:1804
 msgid "register number out of range"
 msgstr ""
 
-#: config/tc-xtensa.c:1920
+#: config/tc-xtensa.c:1888
 msgid "extra comma"
 msgstr ""
 
-#: config/tc-xtensa.c:1922
+#: config/tc-xtensa.c:1890
 msgid "extra colon"
 msgstr ""
 
-#: config/tc-xtensa.c:1924
+#: config/tc-xtensa.c:1892
 msgid "missing argument"
 msgstr ""
 
-#: config/tc-xtensa.c:1926
+#: config/tc-xtensa.c:1894
 msgid "missing comma or colon"
 msgstr ""
 
-#: config/tc-xtensa.c:1983
+#: config/tc-xtensa.c:1951
 msgid "incorrect register number, ignoring"
 msgstr ""
 
-#: config/tc-xtensa.c:1990
+#: config/tc-xtensa.c:1958
 msgid "too many arguments"
 msgstr ""
 
-#: config/tc-xtensa.c:2063
+#: config/tc-xtensa.c:2031
 #, c-format
 msgid "cannot encode opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:2157
+#: config/tc-xtensa.c:2125
 #, c-format
 msgid "not enough operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:2164
+#: config/tc-xtensa.c:2132
 #, c-format
 msgid "too many operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:2219
+#: config/tc-xtensa.c:2183
 #, c-format
 msgid "invalid register '%s' for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2226
+#: config/tc-xtensa.c:2190
 #, c-format
 msgid "invalid register number (%ld) for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2295
+#: config/tc-xtensa.c:2258
 #, c-format
 msgid "invalid register number (%ld) for '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:2685
+#: config/tc-xtensa.c:2649
 #, c-format
 msgid "operand %d of '%s' has out of range value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2691
+#: config/tc-xtensa.c:2655
 #, c-format
 msgid "operand %d of '%s' has invalid value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2739
+#: config/tc-xtensa.c:2703
 #, c-format
 msgid "internal error: unknown option name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:3791
+#: config/tc-xtensa.c:3778
 msgid "INSTR_LABEL_DEF not supported yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3820
+#: config/tc-xtensa.c:3807
 msgid "can't handle generation of literal/labels yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3824
+#: config/tc-xtensa.c:3811
 msgid "can't handle undefined OP TYPE"
 msgstr ""
 
-#: config/tc-xtensa.c:3885
+#: config/tc-xtensa.c:3872
 #, c-format
 msgid "found %d operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:3892
+#: config/tc-xtensa.c:3879
 #, c-format
 msgid "found too many (%d) operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:4029
+#: config/tc-xtensa.c:4016
 msgid "invalid immediate"
 msgstr ""
 
-#: config/tc-xtensa.c:4140
+#: config/tc-xtensa.c:4130
 #, c-format
 msgid "invalid relocation for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4150
+#: config/tc-xtensa.c:4140
 #, c-format
 msgid "invalid expression for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4160
+#: config/tc-xtensa.c:4150
 #, c-format
 msgid "invalid relocation in instruction slot %i"
 msgstr ""
 
-#: config/tc-xtensa.c:4167
+#: config/tc-xtensa.c:4157
 #, c-format
 msgid "undefined symbol for opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:4608
+#: config/tc-xtensa.c:4612
 msgid "opcode 'NOP.N' unavailable in this configuration"
 msgstr ""
 
-#: config/tc-xtensa.c:4668
+#: config/tc-xtensa.c:4672
 msgid "get_expanded_loop_offset: invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:4751
+#: config/tc-xtensa.c:4804
 #, c-format
 msgid "assembly state not set for first frag in section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:4804
+#: config/tc-xtensa.c:4857
 #, c-format
 msgid "unaligned branch target: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4843
+#: config/tc-xtensa.c:4896
 #, c-format
 msgid "unaligned loop: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4867
+#: config/tc-xtensa.c:4920
 msgid "unexpected fix"
 msgstr ""
 
-#: config/tc-xtensa.c:4878 config/tc-xtensa.c:4882
+#: config/tc-xtensa.c:4931 config/tc-xtensa.c:4935
 msgid "undecodable fix"
 msgstr ""
 
-#: config/tc-xtensa.c:5012
+#: config/tc-xtensa.c:5061
 msgid "labels are not valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:5032
+#: config/tc-xtensa.c:5081
 msgid "invalid last instruction for a zero-overhead loop"
 msgstr ""
 
-#: config/tc-xtensa.c:5097
+#: config/tc-xtensa.c:5146
 msgid "extra opening brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5107
+#: config/tc-xtensa.c:5156
 msgid "extra closing brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5125
+#: config/tc-xtensa.c:5183
 msgid "missing closing brace"
 msgstr ""
 
-#: config/tc-xtensa.c:5205
+#: config/tc-xtensa.c:5263
 #, c-format
 msgid "unknown opcode or format name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5211
+#: config/tc-xtensa.c:5269
 msgid "format names only valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:5216
+#: config/tc-xtensa.c:5274
 #, c-format
 msgid "multiple formats specified for one bundle; using '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5271
+#: config/tc-xtensa.c:5323
 msgid "entry instruction with stack decrement < 16"
 msgstr ""
 
-#: config/tc-xtensa.c:5275
-msgid "entry instruction with non-constant decrement"
-msgstr ""
-
-#: config/tc-xtensa.c:5330
+#: config/tc-xtensa.c:5376
 msgid "unaligned entry instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:5389
+#: config/tc-xtensa.c:5438
 msgid "bad instruction format"
 msgstr ""
 
-#: config/tc-xtensa.c:5392
+#: config/tc-xtensa.c:5441
 msgid "invalid relocation"
 msgstr ""
 
-#: config/tc-xtensa.c:5403
+#: config/tc-xtensa.c:5452
 #, c-format
 msgid "invalid relocation for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:5415
+#: config/tc-xtensa.c:5464
 #, c-format
 msgid "invalid relocation for operand %d of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5572
+#: config/tc-xtensa.c:5628
 msgid "cannot represent subtraction with an offset"
 msgstr ""
 
-#: config/tc-xtensa.c:5660
+#: config/tc-xtensa.c:5716
 #, c-format
 msgid "unhandled local relocation fix %s"
 msgstr ""
 
-#: config/tc-xtensa.c:5968
+#: config/tc-xtensa.c:6023
 msgid "couldn't find a valid instruction format"
 msgstr ""
 
-#: config/tc-xtensa.c:5969
+#: config/tc-xtensa.c:6024
 #, c-format
 msgid "    ops were: "
 msgstr ""
 
-#: config/tc-xtensa.c:5971
+#: config/tc-xtensa.c:6026
 #, c-format
 msgid " %s;"
 msgstr ""
 
-#: config/tc-xtensa.c:5974
-#, c-format
-msgid "\n"
-msgstr ""
-
-#: config/tc-xtensa.c:5982
+#: config/tc-xtensa.c:6037
 #, c-format
 msgid "format '%s' allows %d slots, but there are %d opcodes"
 msgstr ""
 
-#: config/tc-xtensa.c:5993 config/tc-xtensa.c:6091
+#: config/tc-xtensa.c:6048 config/tc-xtensa.c:6146
 msgid "illegal resource usage in bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:6178
+#: config/tc-xtensa.c:6233
 #, c-format
 msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"
 msgstr ""
 
-#: config/tc-xtensa.c:6183
+#: config/tc-xtensa.c:6238
 #, c-format
 msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"
 msgstr ""
 
-#: config/tc-xtensa.c:6188
+#: config/tc-xtensa.c:6243
 #, c-format
-msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"
 msgstr ""
 
-#: config/tc-xtensa.c:6193
+#: config/tc-xtensa.c:6248
 #, c-format
 msgid ""
-"opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"
+"opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"
 msgstr ""
 
-#: config/tc-xtensa.c:6209
+#: config/tc-xtensa.c:6264
 msgid "multiple branches or jumps in the same bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:6664
+#: config/tc-xtensa.c:6712
 msgid "cannot assemble into a literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:6666
+#: config/tc-xtensa.c:6714
 msgid "..."
 msgstr ""
 
-#: config/tc-xtensa.c:7175
+#: config/tc-xtensa.c:7258
 msgid ""
 "instruction sequence (write a0, branch, retw) may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7285
+#: config/tc-xtensa.c:7370
 msgid "branching or jumping to a loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7384
+#: config/tc-xtensa.c:7452
 msgid "loop end too close to another loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7393
+#: config/tc-xtensa.c:7461
 #, c-format
 msgid "fr_var %lu < length %d"
 msgstr ""
 
-#: config/tc-xtensa.c:7564
+#: config/tc-xtensa.c:7620
 msgid ""
 "loop containing less than three instructions may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:7636
+#: config/tc-xtensa.c:7692
 msgid "undecodable instruction in instruction frag"
 msgstr ""
 
-#: config/tc-xtensa.c:7745
+#: config/tc-xtensa.c:7802
 msgid "invalid empty loop"
 msgstr ""
 
-#: config/tc-xtensa.c:7750
+#: config/tc-xtensa.c:7807
 msgid "loop target does not follow loop instruction in section"
 msgstr ""
 
-#: config/tc-xtensa.c:8287
+#: config/tc-xtensa.c:8380
 msgid "bad relaxation state"
 msgstr ""
 
-#: config/tc-xtensa.c:8345
+#: config/tc-xtensa.c:8438
 #, c-format
 msgid "fr_var (%ld) < length (%d)"
 msgstr ""
 
-#: config/tc-xtensa.c:8846
+#: config/tc-xtensa.c:8945
 msgid "internal error: relaxation failed"
 msgstr ""
 
-#: config/tc-xtensa.c:8852
+#: config/tc-xtensa.c:8951
 msgid "internal error: relaxation requires too many steps"
 msgstr ""
 
-#: config/tc-xtensa.c:9027
+#: config/tc-xtensa.c:9127
 msgid "invalid relaxation fragment result"
 msgstr ""
 
-#: config/tc-xtensa.c:9107
+#: config/tc-xtensa.c:9206
 msgid "unable to widen instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:9250
+#: config/tc-xtensa.c:9346
 msgid "multiple literals in expansion"
 msgstr ""
 
-#: config/tc-xtensa.c:9254
+#: config/tc-xtensa.c:9350
 msgid "no registered fragment for literal"
 msgstr ""
 
-#: config/tc-xtensa.c:9256
+#: config/tc-xtensa.c:9352
 msgid "number of literal tokens != 1"
 msgstr ""
 
-#: config/tc-xtensa.c:9400 config/tc-xtensa.c:9406
+#: config/tc-xtensa.c:9482 config/tc-xtensa.c:9488
 #, c-format
 msgid "unresolved loop target symbol: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:9512
+#: config/tc-xtensa.c:9594
 #, c-format
 msgid "invalid expression evaluation type %d"
 msgstr ""
 
-#: config/tc-xtensa.c:9534
+#: config/tc-xtensa.c:9611
 msgid "loop too long for LOOP instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:9805
+#: config/tc-xtensa.c:9881
 #, c-format
 msgid "fixes not all moved from %s"
 msgstr ""
 
-#: config/tc-xtensa.c:9947
+#: config/tc-xtensa.c:10012
 msgid ""
 "literal pool location required for text-section-literals; specify with ."
 "literal_position"
 msgstr ""
 
-#: config/tc-xtensa.c:10456
-#, c-format
-msgid "could not create section %s"
-msgstr ""
-
-#: config/tc-xtensa.c:10458
-#, c-format
-msgid "invalid flag combination on section %s"
-msgstr ""
-
-#: config/tc-xtensa.c:10844
+#: config/tc-xtensa.c:10941
 msgid "too many operands in instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:11078
-#, c-format
-msgid "invalid symbolic operand %d on '%s'"
+#: config/tc-xtensa.c:11152
+msgid "invalid symbolic operand"
 msgstr ""
 
-#: config/tc-xtensa.c:11147 config/tc-xtensa.c:11221
+#: config/tc-xtensa.c:11213
 msgid "operand number mismatch"
 msgstr ""
 
-#: config/tc-xtensa.c:11150
-msgid "cannot encode opcode"
-msgstr ""
-
-#: config/tc-xtensa.c:11225
+#: config/tc-xtensa.c:11217
 #, c-format
 msgid "cannot encode opcode \"%s\" in the given format \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:11250
+#: config/tc-xtensa.c:11242
 #, c-format
 msgid "xtensa-isa failure: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:11283
+#: config/tc-xtensa.c:11313
 msgid "invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:11289
+#: config/tc-xtensa.c:11319
 msgid "too few operands"
 msgstr ""
 
-#: config/tc-xtensa.c:11416 config/tc-xtensa.c:11424
+#: config/tc-xtensa.c:11434 config/tc-xtensa.c:11440
 msgid "out of memory"
 msgstr ""
 
-#: config/tc-xtensa.c:11536
-msgid "instruction with constant operands does not fit"
+#: config/tc-xtensa.c:11551
+msgid "symbolic operand not allowed"
+msgstr ""
+
+#: config/tc-xtensa.c:11588
+msgid "cannot decode instruction format"
+msgstr ""
+
+#: config/tc-xtensa.c:11732
+msgid "ignoring extra '-rename-section' delimiter ':'"
 msgstr ""
 
-#: config/tc-xtensa.c:11545 config/tc-xtensa.c:11566
+#: config/tc-xtensa.c:11737
 #, c-format
-msgid "invalid operand %d on '%s'"
+msgid "ignoring invalid '-rename-section' specification: '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:11557
-msgid "invalid subtract operand"
+#: config/tc-xtensa.c:11748
+#, c-format
+msgid "section %s renamed multiple times"
 msgstr ""
 
-#: config/tc-xtensa.c:11571
+#: config/tc-xtensa.c:11750
 #, c-format
-msgid "invalid expression for operand %d on '%s'"
+msgid "multiple sections remapped to output section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:11601
-msgid "cannot decode instruction format"
+#: config/tc-z80.c:244
+msgid "-- unterminated string"
 msgstr ""
 
-#: config/tc-xtensa.c:11760
-msgid "ignoring extra '-rename-section' delimiter ':'"
+#: config/tc-z80.c:314
+msgid "floating point numbers are not implemented"
 msgstr ""
 
-#: config/tc-xtensa.c:11765
-#, c-format
-msgid "ignoring invalid '-rename-section' specification: '%s'"
+#: config/tc-z80.c:493 config/tc-z80.c:499
+msgid "mismatched parentheses"
+msgstr ""
+
+#: config/tc-z80.c:553
+msgid "bad offset expression syntax"
+msgstr ""
+
+#: config/tc-z80.c:577
+msgid "bad expression syntax"
+msgstr ""
+
+#: config/tc-z80.c:690
+msgid "cannot make a relative jump to an absolute location"
+msgstr ""
+
+#: config/tc-z80.c:702 config/tc-z80.c:1960
+msgid "overflow"
+msgstr ""
+
+#: config/tc-z80.c:1070 config/tc-z80.c:1113 config/tc-z80.c:1157
+#: config/tc-z80.c:1277 config/tc-z80.c:1331 config/tc-z80.c:1600
+msgid "bad intruction syntax"
+msgstr ""
+
+#: config/tc-z80.c:1203
+msgid "condition code invalid for jr"
+msgstr ""
+
+#: config/tc-z80.c:1225
+msgid "bad instruction syntax"
+msgstr ""
+
+#: config/tc-z80.c:1704
+msgid "parentheses ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:11776
+#: config/tc-z80.c:1909 read.c:3501
 #, c-format
-msgid "section %s renamed multiple times"
+msgid "junk at end of line, first unrecognized character is `%c'"
+msgstr ""
+
+#: config/tc-z80.c:1935 config/tc-z8k.c:1513 config/tc-z8k.c:1576
+msgid "relative jump out of range"
+msgstr ""
+
+#: config/tc-z80.c:1952
+msgid "index offset  out of range"
 msgstr ""
 
-#: config/tc-xtensa.c:11778
+#: config/tc-z80.c:1994 config/tc-z8k.c:1584
 #, c-format
-msgid "multiple sections remapped to output section %s"
+msgid "md_apply_fix: unknown r_type 0x%x\n"
 msgstr ""
 
-#: config/tc-z8k.c:268
+#: config/tc-z8k.c:282
 #, c-format
 msgid "register rr%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:270
+#: config/tc-z8k.c:284
 #, c-format
 msgid "register rr%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:280
+#: config/tc-z8k.c:296
 #, c-format
 msgid "register rh%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:290
+#: config/tc-z8k.c:308
 #, c-format
 msgid "register rl%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:301
+#: config/tc-z8k.c:321
 #, c-format
 msgid "register rq%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:303
+#: config/tc-z8k.c:323
 #, c-format
 msgid "register rq%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:313
+#: config/tc-z8k.c:335
 #, c-format
 msgid "register r%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:354
+#: config/tc-z8k.c:376
 #, c-format
 msgid "expected %c"
 msgstr ""
 
-#: config/tc-z8k.c:369
+#: config/tc-z8k.c:391
 #, c-format
 msgid "register is wrong size for a word %s"
 msgstr ""
 
-#: config/tc-z8k.c:383
+#: config/tc-z8k.c:405
 #, c-format
 msgid "register is wrong size for address %s"
 msgstr ""
 
-#: config/tc-z8k.c:517
+#: config/tc-z8k.c:539
 #, c-format
 msgid "unknown interrupt %s"
 msgstr ""
 
 #. No interrupt type specified, opcode won't do anything.
-#: config/tc-z8k.c:540
+#: config/tc-z8k.c:562
 msgid "opcode has no effect"
 msgstr ""
 
-#: config/tc-z8k.c:651
+#: config/tc-z8k.c:673
 msgid "Missing ) in ra(rb)"
 msgstr ""
 
-#: config/tc-z8k.c:731 config/tc-z8k.c:770
+#: config/tc-z8k.c:753 config/tc-z8k.c:792
 #, c-format
 msgid "invalid condition code '%s'"
 msgstr ""
 
-#: config/tc-z8k.c:743
+#: config/tc-z8k.c:765
 #, c-format
 msgid "invalid flag '%s'"
 msgstr ""
 
-#: config/tc-z8k.c:897 config/tc-z8k.c:903
+#: config/tc-z8k.c:919 config/tc-z8k.c:925
 msgid "invalid indirect register size"
 msgstr ""
 
-#: config/tc-z8k.c:920 config/tc-z8k.c:1068 config/tc-z8k.c:1073
+#: config/tc-z8k.c:942 config/tc-z8k.c:1090 config/tc-z8k.c:1095
 msgid "invalid control register name"
 msgstr ""
 
-#: config/tc-z8k.c:1057
+#: config/tc-z8k.c:1079
 msgid "immediate must be 1 or 2"
 msgstr ""
 
-#: config/tc-z8k.c:1060
+#: config/tc-z8k.c:1082
 msgid "immediate 1 or 2 expected"
 msgstr ""
 
-#: config/tc-z8k.c:1091
+#: config/tc-z8k.c:1113
 msgid "can't use R0 here"
 msgstr ""
 
-#: config/tc-z8k.c:1249
+#: config/tc-z8k.c:1271
 msgid "Can't find opcode to match operands"
 msgstr ""
 
-#: config/tc-z8k.c:1348
+#: config/tc-z8k.c:1370
 #, c-format
 msgid "invalid architecture -z%s"
 msgstr ""
 
-#: config/tc-z8k.c:1368
+#: config/tc-z8k.c:1390
 #, c-format
 msgid ""
 " Z8K options:\n"
@@ -11067,33 +12160,24 @@ msgid ""
 "  -linkrelax              create linker relaxable code\n"
 msgstr ""
 
-#: config/tc-z8k.c:1380
+#: config/tc-z8k.c:1402
 #, c-format
 msgid "call to md_convert_frag\n"
 msgstr ""
 
-#: config/tc-z8k.c:1487 config/tc-z8k.c:1527 config/tc-z8k.c:1550
+#: config/tc-z8k.c:1509 config/tc-z8k.c:1549 config/tc-z8k.c:1572
 msgid "cannot branch to odd address"
 msgstr ""
 
-#: config/tc-z8k.c:1491 config/tc-z8k.c:1554
-msgid "relative jump out of range"
-msgstr ""
-
-#: config/tc-z8k.c:1509
+#: config/tc-z8k.c:1531
 msgid "relative address out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1530
+#: config/tc-z8k.c:1552
 msgid "relative call out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1562
-#, c-format
-msgid "md_apply_fix: unknown r_type 0x%x\n"
-msgstr ""
-
-#: config/tc-z8k.c:1574
+#: config/tc-z8k.c:1596
 #, c-format
 msgid "call to md_estimate_size_before_relax\n"
 msgstr ""
@@ -11108,67 +12192,91 @@ msgstr ""
 msgid "can't close `%s'"
 msgstr ""
 
-#: dw2gencfi.c:258
+#: dw2gencfi.c:276
 #, c-format
 msgid "register save offset not a multiple of %u"
 msgstr ""
 
-#: dw2gencfi.c:341
+#: dw2gencfi.c:359
 msgid "CFI state restore without previous remember"
 msgstr ""
 
-#: dw2gencfi.c:387
+#: dw2gencfi.c:411
 msgid "missing separator"
 msgstr ""
 
-#: dw2gencfi.c:409 dw2gencfi.c:427
+#: dw2gencfi.c:433 dw2gencfi.c:451
 msgid "bad register expression"
 msgstr ""
 
-#: dw2gencfi.c:449 dw2gencfi.c:551
+#: dw2gencfi.c:473 dw2gencfi.c:596 dw2gencfi.c:634 dw2gencfi.c:704
 msgid "CFI instruction used without previous .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:587
+#: dw2gencfi.c:658
+msgid "invalid or unsupported encoding in .cfi_personality"
+msgstr ""
+
+#: dw2gencfi.c:665
+msgid ".cfi_personality requires encoding and symbol arguments"
+msgstr ""
+
+#: dw2gencfi.c:688
+msgid "wrong second argument to .cfi_personality"
+msgstr ""
+
+#: dw2gencfi.c:728
+msgid "invalid or unsupported encoding in .cfi_lsda"
+msgstr ""
+
+#: dw2gencfi.c:735
+msgid ".cfi_lsda requires encoding and symbol arguments"
+msgstr ""
+
+#: dw2gencfi.c:760
+msgid "wrong second argument to .cfi_lsda"
+msgstr ""
+
+#: dw2gencfi.c:775
 msgid "previous CFI entry not closed (missing .cfi_endproc)"
 msgstr ""
 
-#: dw2gencfi.c:622
+#: dw2gencfi.c:810
 msgid ".cfi_endproc without corresponding .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:1031
+#: dw2gencfi.c:1339
 msgid "open CFI at the end of file; missing .cfi_endproc directive"
 msgstr ""
 
-#: dwarf2dbg.c:523 dwarf2dbg.c:549
+#: dwarf2dbg.c:553 dwarf2dbg.c:579
 msgid "file number less than one"
 msgstr ""
 
-#: dwarf2dbg.c:529
+#: dwarf2dbg.c:559
 #, c-format
 msgid "file number %ld already allocated"
 msgstr ""
 
-#: dwarf2dbg.c:554 dwarf2dbg.c:1169
+#: dwarf2dbg.c:584 dwarf2dbg.c:1244
 #, c-format
 msgid "unassigned file number %ld"
 msgstr ""
 
-#: dwarf2dbg.c:622
+#: dwarf2dbg.c:652
 msgid "is_stmt value not 0 or 1"
 msgstr ""
 
-#: dwarf2dbg.c:634
+#: dwarf2dbg.c:664
 msgid "isa number less than zero"
 msgstr ""
 
-#: dwarf2dbg.c:640
+#: dwarf2dbg.c:670
 #, c-format
 msgid "unknown .loc sub-directive `%s'"
 msgstr ""
 
-#: dwarf2dbg.c:1234 dwarf2dbg.c:1428
+#: dwarf2dbg.c:1309 dwarf2dbg.c:1558
 msgid "internal error: unknown dwarf2 format"
 msgstr ""
 
@@ -11285,7 +12393,7 @@ msgid ".val pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
 #: ecoff.c:2781
-msgid ".val expression is too copmlex"
+msgid ".val expression is too complex"
 msgstr ""
 
 #: ecoff.c:2811
@@ -11325,12 +12433,6 @@ msgstr ""
 msgid ".loc before .file"
 msgstr ""
 
-#: ecoff.c:3355 read.c:1473 read.c:1579 read.c:2256 read.c:2803 symbols.c:327
-#: symbols.c:423
-#, c-format
-msgid "symbol `%s' is already defined"
-msgstr ""
-
 #: ecoff.c:3368
 msgid "bad .weakext directive"
 msgstr ""
@@ -11368,92 +12470,92 @@ msgstr ""
 msgid "GP prologue size exceeds field size, using 0 instead"
 msgstr ""
 
-#: expr.c:82 read.c:3351
+#: expr.c:81 read.c:3566
 msgid "bignum invalid"
 msgstr ""
 
-#: expr.c:84 read.c:3353 read.c:3702 read.c:4550
+#: expr.c:83 read.c:3568 read.c:4025 read.c:4873
 msgid "floating point number invalid"
 msgstr ""
 
-#: expr.c:203
+#: expr.c:202
 msgid "bad floating-point constant: exponent overflow"
 msgstr ""
 
-#: expr.c:207
+#: expr.c:206
 #, c-format
 msgid "bad floating-point constant: unknown error code=%d"
 msgstr ""
 
-#: expr.c:383
+#: expr.c:385
 msgid ""
 "a bignum with underscores may not have more than 8 hex digits in any word"
 msgstr ""
 
-#: expr.c:406
+#: expr.c:408
 msgid "a bignum with underscores must have exactly 4 words"
 msgstr ""
 
 #. Either not seen or not defined.
 #. @@ Should print out the original string instead of
 #. the parsed number.
-#: expr.c:529
+#: expr.c:531
 #, c-format
 msgid "backward ref to unknown label \"%d:\""
 msgstr ""
 
-#: expr.c:647
+#: expr.c:649
 msgid "character constant too large"
 msgstr ""
 
-#: expr.c:893
+#: expr.c:895
 #, c-format
 msgid "expr.c(operand): bad atof_generic return val %d"
 msgstr ""
 
-#: expr.c:954
+#: expr.c:956
 #, c-format
 msgid "missing '%c'"
 msgstr ""
 
-#: expr.c:965 read.c:4034
+#: expr.c:967 read.c:4357
 msgid "EBCDIC constants are not supported"
 msgstr ""
 
-#: expr.c:1082
+#: expr.c:1079
 #, c-format
 msgid "Unary operator %c ignored because bad operand follows"
 msgstr ""
 
-#: expr.c:1128 expr.c:1153
+#: expr.c:1125 expr.c:1150
 msgid "syntax error in .startof. or .sizeof."
 msgstr ""
 
-#: expr.c:1665
+#: expr.c:1661
 msgid "missing operand; zero assumed"
 msgstr ""
 
-#: expr.c:1700
+#: expr.c:1696
 msgid "left operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1702
+#: expr.c:1698
 msgid "left operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1711
+#: expr.c:1707
 msgid "right operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1713
+#: expr.c:1709
 msgid "right operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1769 symbols.c:1207
+#: expr.c:1768 symbols.c:1349
 msgid "division by zero"
 msgstr ""
 
-#: expr.c:1867
+#: expr.c:1868
 msgid "operation combines symbols in different segments"
 msgstr ""
 
@@ -11482,34 +12584,34 @@ msgstr ""
 #. line here (assuming of course that we actually have a line of
 #. input to read), so that it can be displayed in the listing
 #. that is produced at the end of the assembly.
-#: input-file.c:141 input-scrub.c:238 listing.c:332
+#: input-file.c:138 input-scrub.c:241 listing.c:332
 msgid "{standard input}"
 msgstr ""
 
-#: input-file.c:147 input-file.c:156
+#: input-file.c:143
 #, c-format
-msgid "Can't open %s for reading"
+msgid "can't open %s for reading: %s"
 msgstr ""
 
-#: input-file.c:219 input-file.c:246
+#: input-file.c:152 input-file.c:215 input-file.c:241
 #, c-format
-msgid "Can't read from %s"
+msgid "can't read from %s: %s"
 msgstr ""
 
-#: input-file.c:256
+#: input-file.c:249 listing.c:1097 output-file.c:69
 #, c-format
-msgid "Can't close %s"
+msgid "can't close %s: %s"
 msgstr ""
 
-#: input-scrub.c:263
+#: input-scrub.c:266
 msgid "macros nested too deeply"
 msgstr ""
 
-#: input-scrub.c:365 input-scrub.c:387
+#: input-scrub.c:369 input-scrub.c:393
 msgid "partial line at end of file ignored"
 msgstr ""
 
-#: itbl-ops.c:338
+#: itbl-ops.c:329
 #, c-format
 msgid "Unable to allocate memory for new instructions\n"
 msgstr ""
@@ -11522,255 +12624,246 @@ msgstr ""
 msgid "Error:"
 msgstr ""
 
-#: listing.c:1089
-#, c-format
-msgid "can't open list file: %s"
-msgstr ""
-
-#: listing.c:1109
+#: listing.c:1079
 #, c-format
-msgid "error closing list file: %s"
+msgid "can't open %s: %s"
 msgstr ""
 
-#: listing.c:1182
+#: listing.c:1169
 msgid "strange paper height, set to no form"
 msgstr ""
 
-#: listing.c:1246
+#: listing.c:1233
 msgid "new line in title"
 msgstr ""
 
 #. Turns the next expression into a string.
-#: macro.c:436
+#: macro.c:371
 #, no-c-format
 msgid "% operator needs absolute expression"
 msgstr ""
 
-#: macro.c:558
+#: macro.c:521
 #, c-format
 msgid "Missing parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:568
+#: macro.c:531
 #, c-format
 msgid "`%s' is not a valid parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:585
+#: macro.c:548
 #, c-format
 msgid "Pointless default value for required parameter `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:597
+#: macro.c:560
 #, c-format
 msgid "A parameter named `%s' already exists for macro `%s'"
 msgstr ""
 
-#: macro.c:634
+#: macro.c:597
 #, c-format
 msgid "Reserved word `%s' used as parameter in macro `%s'"
 msgstr ""
 
-#: macro.c:672
+#: macro.c:635
 #, c-format
 msgid "unexpected end of file in macro `%s' definition"
 msgstr ""
 
-#: macro.c:684
+#: macro.c:647
 #, c-format
 msgid "missing `)' after formals in macro definition `%s'"
 msgstr ""
 
-#: macro.c:699
+#: macro.c:662
 msgid "Missing macro name"
 msgstr ""
 
-#: macro.c:708
+#: macro.c:671
 #, c-format
 msgid "Bad parameter list for macro `%s'"
 msgstr ""
 
-#: macro.c:714
+#: macro.c:677
 #, c-format
 msgid "Macro `%s' was already defined"
 msgstr ""
 
-#: macro.c:837 macro.c:839
+#: macro.c:800 macro.c:802
 msgid "missing `)'"
 msgstr ""
 
-#: macro.c:934
+#: macro.c:897
 #, c-format
 msgid "`%s' was already used as parameter (or another local) name"
 msgstr ""
 
-#: macro.c:1093
+#: macro.c:1055
 msgid "confusion in formal parameters"
 msgstr ""
 
-#: macro.c:1100
+#: macro.c:1062
 #, c-format
 msgid "Parameter named `%s' does not exist for macro `%s'"
 msgstr ""
 
-#: macro.c:1108
+#: macro.c:1070
 #, c-format
 msgid "Value for parameter `%s' of macro `%s' was already specified"
 msgstr ""
 
-#: macro.c:1124
+#: macro.c:1084
 msgid "can't mix positional and keyword arguments"
 msgstr ""
 
-#: macro.c:1135
+#: macro.c:1095
 msgid "too many positional arguments"
 msgstr ""
 
-#: macro.c:1183
+#: macro.c:1143
 #, c-format
 msgid "Missing value for required parameter `%s' of macro `%s'"
 msgstr ""
 
-#: macro.c:1320
+#: macro.c:1280
 #, c-format
 msgid "Attempt to purge non-existant macro `%s'"
 msgstr ""
 
-#: macro.c:1339
+#: macro.c:1299
 msgid "unexpected end of file in irp or irpc"
 msgstr ""
 
-#: macro.c:1347
+#: macro.c:1307
 msgid "missing model parameter"
 msgstr ""
 
-#: messages.c:104
+#: messages.c:82
 #, c-format
 msgid "Assembler messages:\n"
 msgstr ""
 
-#: messages.c:206
+#: messages.c:166
 #, c-format
 msgid "Warning: "
 msgstr ""
 
-#: messages.c:307
+#: messages.c:267
 #, c-format
 msgid "Error: "
 msgstr ""
 
-#: messages.c:402 messages.c:422
+#: messages.c:362 messages.c:382
 #, c-format
 msgid "Fatal error: "
 msgstr ""
 
-#: messages.c:437
+#: messages.c:397
 #, c-format
 msgid "Internal error!\n"
 msgstr ""
 
-#: messages.c:439
+#: messages.c:399
 #, c-format
 msgid "Assertion failure in %s at %s line %d.\n"
 msgstr ""
 
-#: messages.c:442
+#: messages.c:402
 #, c-format
 msgid "Assertion failure at %s line %d.\n"
 msgstr ""
 
-#: messages.c:443 messages.c:460
+#: messages.c:403 messages.c:420
 #, c-format
 msgid "Please report this bug.\n"
 msgstr ""
 
-#: messages.c:455
+#: messages.c:415
 #, c-format
 msgid "Internal error, aborting at %s line %d in %s\n"
 msgstr ""
 
-#: messages.c:458
+#: messages.c:418
 #, c-format
 msgid "Internal error, aborting at %s line %d\n"
 msgstr ""
 
-#: messages.c:507
+#: messages.c:467
+#, c-format
+msgid "%s out of domain (%d is not a multiple of %d)"
+msgstr ""
+
+#: messages.c:485
 #, c-format
 msgid "%s out of range (%d is not between %d and %d)"
 msgstr ""
 
 #. xgettext:c-format.
-#: messages.c:530
+#: messages.c:508
 #, c-format
 msgid "%s out of range (0x%s is not between 0x%s and 0x%s)"
 msgstr ""
 
-#: output-file.c:39
+#: output-file.c:35
 #, c-format
 msgid "can't open a bfd on stdout %s"
 msgstr ""
 
-#: output-file.c:44
-#, c-format
-msgid "Selected target format '%s' unknown"
-msgstr ""
-
-#: output-file.c:46
+#: output-file.c:42
 #, c-format
-msgid "FATAL: can't create %s"
+msgid "selected target format '%s' unknown"
 msgstr ""
 
-#: output-file.c:63
+#: output-file.c:44
 #, c-format
-msgid "FATAL: can't close %s\n"
+msgid "can't create %s: %s"
 msgstr ""
 
-#: read.c:450
+#: read.c:458
 msgid "bad or irreducible absolute expression"
 msgstr ""
 
-#: read.c:476
+#: read.c:484
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr ""
 
-#: read.c:896
+#: read.c:894
 #, c-format
 msgid "unknown pseudo-op: `%s'"
 msgstr ""
 
-#: read.c:983
+#: read.c:981
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr ""
 
-#: read.c:1214
+#: read.c:1216
 msgid ".abort detected.  Abandoning ship."
 msgstr ""
 
-#: read.c:1232 read.c:2406
+#: read.c:1234 read.c:2605
 msgid "ignoring fill value in absolute section"
 msgstr ""
 
-#: read.c:1322
+#: read.c:1324
 #, c-format
 msgid "alignment too large: %u assumed"
 msgstr ""
 
-#: read.c:1354
+#: read.c:1356
 msgid "expected fill pattern missing"
 msgstr ""
 
-#: read.c:1457
-msgid "missing size expression"
-msgstr ""
-
-#: read.c:1463
+#: read.c:1465
 #, c-format
 msgid "size (%ld) out of range, ignored"
 msgstr ""
 
-#: read.c:1483
+#: read.c:1494
 #, c-format
 msgid "size of \"%s\" is already %ld; not changing to %ld"
 msgstr ""
@@ -11784,309 +12877,314 @@ msgstr ""
 #. We do not want to barf on this, especially since such files are used
 #. in the GCC and GDB testsuites.  So we check for negative line numbers
 #. rather than non-positive line numbers.
-#: read.c:1712
+#: read.c:1744
 #, c-format
 msgid "line numbers must be positive; line number %d rejected"
 msgstr ""
 
-#: read.c:1739
+#: read.c:1781
+#, c-format
+msgid "incompatible flag %i in line directive"
+msgstr ""
+
+#: read.c:1793
+#, c-format
+msgid "unsupported flag %i in line directive"
+msgstr ""
+
+#: read.c:1832
 msgid "start address not supported"
 msgstr ""
 
-#: read.c:1748
+#: read.c:1841
 msgid ".err encountered"
 msgstr ""
 
-#: read.c:1764
+#: read.c:1857
 msgid ".error directive invoked in source file"
 msgstr ""
 
-#: read.c:1765
+#: read.c:1858
 msgid ".warning directive invoked in source file"
 msgstr ""
 
-#: read.c:1771
+#: read.c:1864
 #, c-format
 msgid "%s argument must be a string"
 msgstr ""
 
-#: read.c:1803 read.c:1805
+#: read.c:1896 read.c:1898
 #, c-format
 msgid ".fail %ld encountered"
 msgstr ""
 
-#: read.c:1841
+#: read.c:1934
 #, c-format
 msgid ".fill size clamped to %d"
 msgstr ""
 
-#: read.c:1846
+#: read.c:1939
 msgid "size negative; .fill ignored"
 msgstr ""
 
-#: read.c:1852
+#: read.c:1945
 msgid "repeat < 0; .fill ignored"
 msgstr ""
 
-#: read.c:2010
+#: read.c:2083
+msgid "expected numeric constant"
+msgstr ""
+
+#: read.c:2139
+msgid "bad string constant"
+msgstr ""
+
+#: read.c:2143
+msgid "expected <tag> , <value>"
+msgstr ""
+
+#: read.c:2217
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr ""
 
-#: read.c:2022
+#: read.c:2229
 msgid ".linkonce is not supported for this object file format"
 msgstr ""
 
-#: read.c:2044
+#: read.c:2251
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr ""
 
-#: read.c:2070
-#, c-format
-msgid "error setting flags for \".sbss\": %s"
-msgstr ""
-
-#: read.c:2117
+#: read.c:2324
 msgid "expected alignment after size"
 msgstr ""
 
-#: read.c:2131
-msgid "alignment negative; 0 assumed"
-msgstr ""
-
-#: read.c:2340
+#: read.c:2539
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr ""
 
-#: read.c:2401
+#: read.c:2600
 #, c-format
 msgid "invalid segment \"%s\""
 msgstr ""
 
-#: read.c:2409
+#: read.c:2608
 msgid "only constant offsets supported in absolute section"
 msgstr ""
 
-#: read.c:2448
+#: read.c:2647
 msgid "MRI style ORG pseudo-op not supported"
 msgstr ""
 
-#: read.c:2601
+#: read.c:2800
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr ""
 
-#: read.c:2615
+#: read.c:2814
 msgid "absolute sections are not supported"
 msgstr ""
 
-#: read.c:2630
+#: read.c:2829
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr ""
 
-#: read.c:2694
+#: read.c:2893
 #, c-format
 msgid ".end%c encountered without preceeding %s"
 msgstr ""
 
-#: read.c:2724
+#: read.c:2923
 #, c-format
 msgid "%s without %s"
 msgstr ""
 
-#: read.c:2951
+#: read.c:3147
 msgid "unsupported variable size or fill value"
 msgstr ""
 
-#: read.c:2979
+#: read.c:3175
 msgid ".space repeat count is zero, ignored"
 msgstr ""
 
-#: read.c:2981
+#: read.c:3177
 msgid ".space repeat count is negative, ignored"
 msgstr ""
 
-#: read.c:3010
+#: read.c:3206
 msgid "space allocation too complex in absolute section"
 msgstr ""
 
-#: read.c:3016
+#: read.c:3212
 msgid "space allocation too complex in common section"
 msgstr ""
 
-#: read.c:3103 read.c:4276
+#: read.c:3299 read.c:4599
 #, c-format
 msgid "bad floating literal: %s"
 msgstr ""
 
-#: read.c:3243
+#: read.c:3458
 #, c-format
 msgid "%s: would close weakref loop: %s"
 msgstr ""
 
-#: read.c:3286
-#, c-format
-msgid "junk at end of line, first unrecognized character is `%c'"
-msgstr ""
-
-#: read.c:3289
+#: read.c:3504
 #, c-format
 msgid "junk at end of line, first unrecognized character valued 0x%x"
 msgstr ""
 
-#: read.c:3347
+#: read.c:3562
 msgid "missing expression"
 msgstr ""
 
-#: read.c:3408
+#: read.c:3624
 #, c-format
 msgid "`%s' can't be equated to common symbol '%s'"
 msgstr ""
 
-#: read.c:3536
+#: read.c:3752
 msgid "rva without symbol"
 msgstr ""
 
-#: read.c:3658
-msgid "attempt to store value in absolute section"
+#: read.c:3809
+msgid "missing or bad offset expression"
 msgstr ""
 
-#: read.c:3696 read.c:4544
-msgid "zero assumed for missing expression"
+#: read.c:3830
+msgid "missing reloc type"
 msgstr ""
 
-#: read.c:3708 read.c:4556 write.c:265
-msgid "register value used as expression"
+#: read.c:3842
+msgid "unrecognized reloc type"
 msgstr ""
 
-#. Leading bits contain both 0s & 1s.
-#: read.c:3786
-#, c-format
-msgid "value 0x%lx truncated to 0x%lx"
+#: read.c:3858
+msgid "bad reloc expression"
 msgstr ""
 
-#: read.c:3802
-#, c-format
-msgid "bignum truncated to %d bytes"
+#: read.c:3981
+msgid "attempt to store value in absolute section"
 msgstr ""
 
-#: read.c:3943
-msgid "using a bit field width of zero"
+#: read.c:4019 read.c:4867
+msgid "zero assumed for missing expression"
 msgstr ""
 
-#: read.c:3951
-#, c-format
-msgid "field width \"%s\" too complex for a bitfield"
+#: read.c:4031 read.c:4879 write.c:260
+msgid "register value used as expression"
 msgstr ""
 
-#: read.c:3959
+#. Leading bits contain both 0s & 1s.
+#: read.c:4109
 #, c-format
-msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
+msgid "value 0x%lx truncated to 0x%lx"
 msgstr ""
 
-#: read.c:3981
+#: read.c:4125
 #, c-format
-msgid "field value \"%s\" too complex for a bitfield"
+msgid "bignum truncated to %d bytes"
 msgstr ""
 
-#: read.c:4107 read.c:4298
+#: read.c:4430 read.c:4621
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr ""
 
-#: read.c:4156
+#: read.c:4479
 #, c-format
 msgid "unknown floating type type '%c'"
 msgstr ""
 
-#: read.c:4178
+#: read.c:4501
 msgid "floating point constant too large"
 msgstr ""
 
-#: read.c:4670
+#: read.c:4993
 msgid "strings must be placed into a section"
 msgstr ""
 
-#: read.c:4720
+#: read.c:5043
 msgid "expected <nn>"
 msgstr ""
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4753 read.c:4839
+#: read.c:5076 read.c:5162
 msgid "unterminated string; newline inserted"
 msgstr ""
 
-#: read.c:4847
+#: read.c:5170
 msgid "bad escaped character in string"
 msgstr ""
 
-#: read.c:4872
+#: read.c:5195
 msgid "expected address expression"
 msgstr ""
 
-#: read.c:4891
+#: read.c:5214
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr ""
 
-#: read.c:4894
+#: read.c:5217
 msgid "some symbol undefined; zero assumed"
 msgstr ""
 
-#: read.c:4930
+#: read.c:5253
 msgid "this string may not contain '\\0'"
 msgstr ""
 
-#: read.c:4966
+#: read.c:5289
 msgid "missing string"
 msgstr ""
 
-#: read.c:5053
+#: read.c:5376
 #, c-format
 msgid ".incbin count zero, ignoring `%s'"
 msgstr ""
 
-#: read.c:5079
+#: read.c:5402
 #, c-format
 msgid "file not found: %s"
 msgstr ""
 
-#: read.c:5093
+#: read.c:5416
 #, c-format
 msgid "seek to end of .incbin file failed `%s'"
 msgstr ""
 
-#: read.c:5104
+#: read.c:5427
 #, c-format
 msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
 msgstr ""
 
-#: read.c:5111
+#: read.c:5434
 #, c-format
 msgid "could not skip to %ld in file `%s'"
 msgstr ""
 
-#: read.c:5120
+#: read.c:5443
 #, c-format
 msgid "truncated file `%s', %ld of %ld bytes read"
 msgstr ""
 
-#: read.c:5278
+#: read.c:5601
 msgid "missing .func"
 msgstr ""
 
-#: read.c:5295
+#: read.c:5618
 msgid ".endfunc missing for previous .func"
 msgstr ""
 
-#: read.c:5418
+#: read.c:5741
 #, c-format
 msgid "missing closing `%c'"
 msgstr ""
 
-#: read.c:5420
+#: read.c:5743
 msgid "stray `\\'"
 msgstr ""
 
@@ -12107,187 +13205,203 @@ msgstr ""
 msgid "comma missing in .xstabs"
 msgstr ""
 
-#: symbols.c:278
+#: symbols.c:277
 #, c-format
 msgid "cannot define symbol `%s' in absolute section"
 msgstr ""
 
-#: symbols.c:409
+#: symbols.c:417
 #, c-format
 msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
 msgstr ""
 
-#: symbols.c:483 symbols.c:490
+#: symbols.c:494 symbols.c:501
 #, c-format
 msgid "inserting \"%s\" into symbol table failed: %s"
 msgstr ""
 
-#: symbols.c:864 symbols.c:868
+#: symbols.c:957 symbols.c:961
 #, c-format
 msgid "undefined symbol `%s' in operation"
 msgstr ""
 
-#: symbols.c:875
+#: symbols.c:968
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s'"
 msgstr ""
 
-#: symbols.c:879
+#: symbols.c:972
 #, c-format
 msgid "invalid section for operation on `%s'"
 msgstr ""
 
-#: symbols.c:887 symbols.c:890
+#: symbols.c:980 symbols.c:983
 #, c-format
 msgid "undefined symbol `%s' in operation setting `%s'"
 msgstr ""
 
-#: symbols.c:897
+#: symbols.c:989
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:901
+#: symbols.c:992
 #, c-format
 msgid "invalid section for operation on `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:951
+#: symbols.c:1042
 #, c-format
 msgid "symbol definition loop encountered at `%s'"
 msgstr ""
 
-#: symbols.c:1209
+#: symbols.c:1069
+#, c-format
+msgid "cannot convert expression symbol %s to complex relocation"
+msgstr ""
+
+#: symbols.c:1351
 #, c-format
 msgid "division by zero when setting `%s'"
 msgstr ""
 
-#: symbols.c:1291 write.c:1545
+#: symbols.c:1432 write.c:1805
 #, c-format
 msgid "can't resolve value for symbol `%s'"
 msgstr ""
 
-#: symbols.c:1738
+#: symbols.c:1882
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr ""
 
-#: symbols.c:1775
+#: symbols.c:1911
 #, c-format
 msgid "attempt to get value of unresolved symbol `%s'"
 msgstr ""
 
-#: symbols.c:2045
+#: symbols.c:2184
 msgid "section symbols are already global"
 msgstr ""
 
-#: symbols.c:2150
+#: symbols.c:2289
 #, c-format
 msgid "Accessing function `%s' as thread-local object"
 msgstr ""
 
-#: symbols.c:2154
+#: symbols.c:2293
 #, c-format
 msgid "Accessing `%s' as thread-local object"
 msgstr ""
 
-#: write.c:164
+#: write.c:159
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr ""
 
-#: write.c:440
+#: write.c:436
 #, c-format
 msgid "attempt to .org/.space backwards? (%ld)"
 msgstr ""
 
-#: write.c:691
+#: write.c:664
+msgid "invalid offset expression"
+msgstr ""
+
+#: write.c:686
+msgid "invalid reloc expression"
+msgstr ""
+
+#: write.c:1039
+#, c-format
+msgid "value of %s too large for field of %d bytes at %s"
+msgstr ""
+
+#: write.c:1051
 #, c-format
-msgid "Local symbol `%s' can't be equated to undefined symbol `%s'"
+msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr ""
 
-#: write.c:865 write.c:937
+#: write.c:1099
 msgid "relocation out of range"
 msgstr ""
 
-#: write.c:868 write.c:940
+#: write.c:1102
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr ""
 
-#: write.c:920
+#: write.c:1166
 msgid "internal error: fixup not contained within frag"
 msgstr ""
 
-#: write.c:1026 write.c:1050
+#: write.c:1219
+msgid "reloc not within (fixed part of) section"
+msgstr ""
+
+#: write.c:1286 write.c:1307
 #, c-format
-msgid "FATAL: Can't write %s"
+msgid "can't write %s: %s"
 msgstr ""
 
-#: write.c:1082
+#: write.c:1337
 msgid "cannot write to output file"
 msgstr ""
 
-#: write.c:1223
+#: write.c:1487
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file"
 msgstr ""
 
-#: write.c:1230
+#: write.c:1494
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated"
 msgstr ""
 
-#: write.c:1464
+#: write.c:1729
 #, c-format
 msgid "%s: global symbols not supported in common sections"
 msgstr ""
 
-#: write.c:1478
+#: write.c:1743
 #, c-format
 msgid "local label `%s' is not defined"
 msgstr ""
 
-#: write.c:1498
+#: write.c:1763
 #, c-format
 msgid "Local symbol `%s' can't be equated to common symbol `%s'"
 msgstr ""
 
-#: write.c:1768
+#: write.c:2028
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr ""
 
-#: write.c:1900
+#: write.c:2186
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ""
 
-#: write.c:1976
+#: write.c:2275
+msgid "padding added"
+msgstr ""
+
+#: write.c:2325
 msgid "attempt to move .org backwards"
 msgstr ""
 
-#: write.c:2004
+#: write.c:2353
 msgid ".space specifies non-absolute value"
 msgstr ""
 
-#: write.c:2011
+#: write.c:2368
 msgid ".space or .fill with negative value, ignored"
 msgstr ""
 
-#: write.c:2067
+#: write.c:2439
 #, c-format
 msgid ""
 "Infinite loop encountered whilst attempting to compute the addresses of "
 "symbols in section %s"
 msgstr ""
-
-#: write.c:2289
-#, c-format
-msgid "value of %s too large for field of %d bytes at %s"
-msgstr ""
-
-#: write.c:2301
-#, c-format
-msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
-msgstr ""
diff --git a/gas/po/rw.gmo b/gas/po/rw.gmo
deleted file mode 100644
index 35ffd398da00..000000000000
--- a/gas/po/rw.gmo
+++ /dev/null
diff --git a/gas/po/tr.gmo b/gas/po/tr.gmo
deleted file mode 100644
index fe95cfbeb132..000000000000
--- a/gas/po/tr.gmo
+++ /dev/null
diff --git a/gas/read.c b/gas/read.c
index 0485d72dec67..0098d7691b3a 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -1,6 +1,6 @@
 /* read.c - read a source file -
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
@@ -38,7 +38,6 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
 #include "sb.h"
 #include "macro.h"
 #include "obstack.h"
-#include "listing.h"
 #include "ecoff.h"
 #include "dw2gencfi.h"
 
@@ -214,6 +213,10 @@ static void do_align (int, char *, int, int);
 static void s_align (int, int);
 static void s_altmacro (int);
 static void s_bad_end (int);
+#ifdef OBJ_ELF
+static void s_gnu_attribute (int);
+#endif
+static void s_reloc (int);
 static int hex_float (int, char *);
 static segT get_known_segmented_expression (expressionS * expP);
 static void pobegin (void);
@@ -330,7 +333,7 @@ static const pseudo_typeS potable[] = {
 /* extend  */
   {"extern", s_ignore, 0},	/* We treat all undef as ext.  */
   {"appfile", s_app_file, 1},
-  {"appline", s_app_line, 0},
+  {"appline", s_app_line, 1},
   {"fail", s_fail, 0},
   {"file", s_app_file, 0},
   {"fill", s_fill, 0},
@@ -339,6 +342,9 @@ static const pseudo_typeS potable[] = {
   {"func", s_func, 0},
   {"global", s_globl, 0},
   {"globl", s_globl, 0},
+#ifdef OBJ_ELF
+  {"gnu_attribute", s_gnu_attribute, 0},
+#endif
   {"hword", cons, 2},
   {"if", s_if, (int) O_ne},
   {"ifb", s_ifb, 1},
@@ -365,6 +371,7 @@ static const pseudo_typeS potable[] = {
   {"irepc", s_irp, 1},
   {"lcomm", s_lcomm, 0},
   {"lflags", listing_flags, 0},	/* Listing flags.  */
+  {"linefile", s_app_line, 0},
   {"linkonce", s_linkonce, 0},
   {"list", listing_list, 1},	/* Turn listing on.  */
   {"llen", listing_psize, 1},
@@ -391,6 +398,7 @@ static const pseudo_typeS potable[] = {
   {"psize", listing_psize, 0},	/* Set paper size.  */
   {"purgem", s_purgem, 0},
   {"quad", cons, 8},
+  {"reloc", s_reloc, 0},
   {"rep", s_rept, 0},
   {"rept", s_rept, 0},
   {"rva", s_rva, 4},
@@ -605,8 +613,6 @@ read_a_source_file (char *name)
 
       last_eol = NULL;
 #endif
-      know (buffer_limit[-1] == '\n');	/* Must have a sentinel.  */
-
       while (input_line_pointer < buffer_limit)
 	{
 	  /* We have more of this buffer to parse.  */
@@ -695,19 +701,11 @@ read_a_source_file (char *name)
 
 	     Depending on what compiler is used, the order of these tests
 	     may vary to catch most common case 1st.
-	     Each test is independent of all other tests at the (top) level.
-	     PLEASE make a compiler that doesn't use this assembler.
-	     It is crufty to waste a compiler's time encoding things for this
-	     assembler, which then wastes more time decoding it.
-	     (And communicating via (linear) files is silly!
-	     If you must pass stuff, please pass a tree!)  */
-	  if ((c = *input_line_pointer++) == '\t'
-	      || c == ' '
-	      || c == '\f'
-	      || c == 0)
+	     Each test is independent of all other tests at the (top)
+	     level.  */
+	  do
 	    c = *input_line_pointer++;
-
-	  know (c != ' ');	/* No further leading whitespace.  */
+	  while (c == '\t' || c == ' ' || c == '\f');
 
 #ifndef NO_LISTING
 	  /* If listing is on, and we are expanding a macro, then give
@@ -1008,10 +1006,14 @@ read_a_source_file (char *name)
 	      unsigned int new_length;
 	      char *tmp_buf = 0;
 
-	      bump_line_counters ();
 	      s = input_line_pointer;
 	      if (strncmp (s, "APP\n", 4))
-		continue;	/* We ignore it */
+		{
+		  /* We ignore it.  */
+		  ignore_rest_of_line ();
+		  continue;
+		}
+	      bump_line_counters ();
 	      s += 4;
 
 	      sb_new (&sbuf);
@@ -1110,7 +1112,7 @@ read_a_source_file (char *name)
 	    continue;
 #endif
 	  input_line_pointer--;
-	  /* Report unknown char as ignored.  */
+	  /* Report unknown char as error.  */
 	  demand_empty_rest_of_line ();
 	}
 
@@ -1279,7 +1281,7 @@ s_align (int arg, int bytes_p)
   unsigned int align_limit = ALIGN_LIMIT;
   unsigned int align;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   offsetT fill = 0;
   int max;
   int fill_p;
@@ -1423,7 +1425,7 @@ s_comm_internal (int param,
   offsetT temp, size;
   symbolS *symbolP = NULL;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   expressionS exp;
 
   if (flag_mri)
@@ -1478,10 +1480,7 @@ s_comm_internal (int param,
 	  ignore_rest_of_line ();
 	  goto out;
 	}
-      /* This could be avoided when the symbol wasn't used so far, but
-	 the comment in struc-symbol.h says this flag isn't reliable.  */
-      if (1 || !symbol_used_p (symbolP))
-	symbolP = symbol_clone (symbolP, 1);
+      symbolP = symbol_clone (symbolP, 1);
       S_SET_SEGMENT (symbolP, undefined_section);
       S_SET_VALUE (symbolP, 0);
       symbol_set_frag (symbolP, &zero_address_frag);
@@ -1538,7 +1537,7 @@ s_mri_common (int small ATTRIBUTE_UNUSED)
   symbolS *sym;
   offsetT align;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (!flag_mri)
     {
@@ -1681,11 +1680,8 @@ s_app_file (int appfile)
   /* Some assemblers tolerate immediately following '"'.  */
   if ((s = demand_copy_string (&length)) != 0)
     {
-      /* If this is a fake .appfile, a fake newline was inserted into
-	 the buffer.  Passing -2 to new_logical_line tells it to
-	 account for it.  */
       int may_omit
-	= (!new_logical_line (s, appfile ? -2 : -1) && appfile);
+	= (!new_logical_line_flags (s, -1, 1) && appfile);
 
       /* In MRI mode, the preprocessor may have inserted an extraneous
 	 backquote.  */
@@ -1700,18 +1696,40 @@ s_app_file (int appfile)
     }
 }
 
+static int
+get_linefile_number (int *flag)
+{
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer < '0' || *input_line_pointer > '9')
+    return 0;
+
+  *flag = get_absolute_expression ();
+
+  return 1;
+}
+
 /* Handle the .appline pseudo-op.  This is automatically generated by
    do_scrub_chars when a preprocessor # line comment is seen.  This
    default definition may be overridden by the object or CPU specific
    pseudo-ops.  */
 
 void
-s_app_line (int ignore ATTRIBUTE_UNUSED)
+s_app_line (int appline)
 {
+  char *file = NULL;
   int l;
 
   /* The given number is that of the next line.  */
-  l = get_absolute_expression () - 1;
+  if (appline)
+    l = get_absolute_expression ();
+  else if (!get_linefile_number (&l))
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+
+  l--;
 
   if (l < -1)
     /* Some of the back ends can't deal with non-positive line numbers.
@@ -1727,13 +1745,74 @@ s_app_line (int ignore ATTRIBUTE_UNUSED)
 	     l + 1);
   else
     {
-      new_logical_line ((char *) NULL, l);
+      int flags = 0;
+      int length = 0;
+
+      if (!appline)
+	{
+	  SKIP_WHITESPACE ();
+
+	  if (*input_line_pointer == '"')
+	    file = demand_copy_string (&length);
+
+	  if (file)
+	    {
+	      int this_flag;
+
+	      while (get_linefile_number (&this_flag))
+		switch (this_flag)
+		  {
+		    /* From GCC's cpp documentation:
+		       1: start of a new file.
+		       2: returning to a file after having included
+		          another file.
+		       3: following text comes from a system header file.
+		       4: following text should be treated as extern "C".
+
+		       4 is nonsensical for the assembler; 3, we don't
+		       care about, so we ignore it just in case a
+		       system header file is included while
+		       preprocessing assembly.  So 1 and 2 are all we
+		       care about, and they are mutually incompatible.
+		       new_logical_line_flags() demands this.  */
+		  case 1:
+		  case 2:
+		    if (flags && flags != (1 << this_flag))
+		      as_warn (_("incompatible flag %i in line directive"),
+			       this_flag);
+		    else
+		      flags |= 1 << this_flag;
+		    break;
+
+		  case 3:
+		  case 4:
+		    /* We ignore these.  */
+		    break;
+
+		  default:
+		    as_warn (_("unsupported flag %i in line directive"),
+			     this_flag);
+		    break;
+		  }
+
+	      if (!is_end_of_line[(unsigned char)*input_line_pointer])
+		file = 0;
+	    }
+	}
+
+      if (appline || file)
+	{
+	  new_logical_line_flags (file, l, flags);
 #ifdef LISTING
-      if (listing)
-	listing_source_line (l);
+	  if (listing)
+	    listing_source_line (l);
 #endif
+	}
     }
-  demand_empty_rest_of_line ();
+  if (appline || file)
+    demand_empty_rest_of_line ();
+  else
+    ignore_rest_of_line ();
 }
 
 /* Handle the .end pseudo-op.  Actually, the real work is done in
@@ -1807,7 +1886,7 @@ s_fail (int ignore ATTRIBUTE_UNUSED)
 {
   offsetT temp;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -1929,7 +2008,7 @@ s_globl (int ignore ATTRIBUTE_UNUSED)
   int c;
   symbolS *symbolP;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -1960,6 +2039,120 @@ s_globl (int ignore ATTRIBUTE_UNUSED)
     mri_comment_end (stop, stopc);
 }
 
+#ifdef OBJ_ELF
+#define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
+
+static inline int
+skip_past_char (char ** str, char c)
+{
+  if (**str == c)
+    {
+      (*str)++;
+      return 0;
+    }
+  else
+    return -1;
+}
+#define skip_past_comma(str) skip_past_char (str, ',')
+
+/* Parse an attribute directive for VENDOR.  */
+void
+s_vendor_attribute (int vendor)
+{
+  expressionS exp;
+  int type;
+  int tag;
+  unsigned int i = 0;
+  char *s = NULL;
+  char saved_char;
+
+  expression (& exp);
+  if (exp.X_op != O_constant)
+    goto bad;
+
+  tag = exp.X_add_number;
+  type = _bfd_elf_obj_attrs_arg_type (stdoutput, vendor, tag);
+
+  if (skip_past_comma (&input_line_pointer) == -1)
+    goto bad;
+  if (type & 1)
+    {
+      expression (& exp);
+      if (exp.X_op != O_constant)
+	{
+	  as_bad (_("expected numeric constant"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      i = exp.X_add_number;
+    }
+  if (type == 3
+      && skip_past_comma (&input_line_pointer) == -1)
+    {
+      as_bad (_("expected comma"));
+      ignore_rest_of_line ();
+      return;
+    }
+  if (type & 2)
+    {
+      skip_whitespace(input_line_pointer);
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      input_line_pointer++;
+      s = input_line_pointer;
+      while (*input_line_pointer && *input_line_pointer != '"')
+	input_line_pointer++;
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      saved_char = *input_line_pointer;
+      *input_line_pointer = 0;
+    }
+  else
+    {
+      s = NULL;
+      saved_char = 0;
+    }
+
+  switch (type)
+    {
+    case 3:
+      bfd_elf_add_obj_attr_compat (stdoutput, vendor, i, s);
+      break;
+    case 2:
+      bfd_elf_add_obj_attr_string (stdoutput, vendor, tag, s);
+      break;
+    case 1:
+      bfd_elf_add_obj_attr_int (stdoutput, vendor, tag, i);
+      break;
+    default:
+      abort ();
+    }
+
+  if (s)
+    {
+      *input_line_pointer = saved_char;
+      input_line_pointer++;
+    }
+  demand_empty_rest_of_line ();
+  return;
+bad_string:
+  as_bad (_("bad string constant"));
+  ignore_rest_of_line ();
+  return;
+bad:
+  as_bad (_("expected <tag> , <value>"));
+  ignore_rest_of_line ();
+}
+
+/* Parse a .gnu_attribute directive.  */
+
+static void
+s_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
+{
+  s_vendor_attribute (OBJ_ATTR_GNU);
+}
+#endif /* OBJ_ELF */
+
 /* Handle the MRI IRP and IRPC pseudo-ops.  */
 
 void
@@ -2812,10 +3005,7 @@ assign_symbol (char *name, int mode)
       /* If the symbol is volatile, copy the symbol and replace the
 	 original with the copy, so that previous uses of the symbol will
 	 retain the value of the symbol at the point of use.  */
-      else if (S_IS_VOLATILE (symbolP)
-	  /* This could be avoided when the symbol wasn't used so far, but
-	     the comment in struc-symbol.h says this flag isn't reliable.  */
-	  && (1 || symbol_used_p (symbolP)))
+      else if (S_IS_VOLATILE (symbolP))
 	symbolP = symbol_clone (symbolP, 1);
     }
 
@@ -2881,7 +3071,7 @@ s_space (int mult)
   expressionS val;
   char *p = 0;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
   int bytes;
 
 #ifdef md_flush_pending_output
@@ -3057,7 +3247,7 @@ s_float_space (int float_type)
   int flen;
   char temp[MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT];
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
@@ -3134,11 +3324,17 @@ void
 s_struct (int ignore ATTRIBUTE_UNUSED)
 {
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   if (flag_mri)
     stop = mri_comment_field (&stopc);
   abs_section_offset = get_absolute_expression ();
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  /* The ELF backend needs to know that we are changing sections, so
+     that .previous works correctly. */
+  if (IS_ELF)
+    obj_elf_section_change_hook ();
+#endif
   subseg_set (absolute_section, 0);
   demand_empty_rest_of_line ();
   if (flag_mri)
@@ -3186,17 +3382,14 @@ s_weakref (int ignore ATTRIBUTE_UNUSED)
 
   if (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
     {
-      if(!S_IS_VOLATILE (symbolP))
+      if (!S_IS_VOLATILE (symbolP))
 	{
 	  as_bad (_("symbol `%s' is already defined"), name);
 	  *end_name = delim;
 	  ignore_rest_of_line ();
 	  return;
 	}
-      /* This could be avoided when the symbol wasn't used so far, but
-	 the comment in struc-symbol.h says this flag isn't reliable.  */
-      if (1 || !symbol_used_p (symbolP))
-	symbolP = symbol_clone (symbolP, 1);
+      symbolP = symbol_clone (symbolP, 1);
       S_CLEAR_VOLATILE (symbolP);
     }
 
@@ -3408,6 +3601,7 @@ pseudo_set (symbolS *symbolP)
       S_SET_SEGMENT (symbolP, reg_section);
       S_SET_VALUE (symbolP, (valueT) exp.X_add_number);
       set_zero_frag (symbolP);
+      symbol_get_value_expression (symbolP)->X_op = O_register;
       break;
 
     case O_symbol:
@@ -3514,7 +3708,7 @@ cons_worker (register int nbytes,	/* 1=.byte, 2=.word, 4=.long.  */
   int c;
   expressionS exp;
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
 #ifdef md_flush_pending_output
   md_flush_pending_output ();
@@ -3588,6 +3782,113 @@ s_rva (int size)
   cons_worker (size, 1);
 }
 
+/* .reloc offset, reloc_name, symbol+addend.  */
+
+void
+s_reloc (int ignore ATTRIBUTE_UNUSED)
+{
+  char *stop = NULL;
+  char stopc = 0;
+  expressionS exp;
+  char *r_name;
+  int c;
+  struct reloc_list *reloc;
+
+  reloc = xmalloc (sizeof (*reloc));
+
+  if (flag_mri)
+    stop = mri_comment_field (&stopc);
+
+  expression (&exp);
+  switch (exp.X_op)
+    {
+    case O_illegal:
+    case O_absent:
+    case O_big:
+    case O_register:
+      as_bad (_("missing or bad offset expression"));
+      goto err_out;
+    case O_constant:
+      exp.X_add_symbol = section_symbol (now_seg);
+      exp.X_op = O_symbol;
+      /* Fall thru */
+    case O_symbol:
+      if (exp.X_add_number == 0)
+	{
+	  reloc->u.a.offset_sym = exp.X_add_symbol;
+	  break;
+	}
+      /* Fall thru */
+    default:
+      reloc->u.a.offset_sym = make_expr_symbol (&exp);
+      break;
+    }
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("missing reloc type"));
+      goto err_out;
+    }
+
+  ++input_line_pointer;
+  SKIP_WHITESPACE ();
+  r_name = input_line_pointer;
+  c = get_symbol_end ();
+  reloc->u.a.howto = bfd_reloc_name_lookup (stdoutput, r_name);
+  *input_line_pointer = c;
+  if (reloc->u.a.howto == NULL)
+    {
+      as_bad (_("unrecognized reloc type"));
+      goto err_out;
+    }
+
+  exp.X_op = O_absent;
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer == ',')
+    {
+      ++input_line_pointer;
+      expression_and_evaluate (&exp);
+    }
+  switch (exp.X_op)
+    {
+    case O_illegal:
+    case O_big:
+    case O_register:
+      as_bad (_("bad reloc expression"));
+    err_out:
+      ignore_rest_of_line ();
+      free (reloc);
+      if (flag_mri)
+	mri_comment_end (stop, stopc);
+      return;
+    case O_absent:
+      reloc->u.a.sym = NULL;
+      reloc->u.a.addend = 0;
+      break;
+    case O_constant:
+      reloc->u.a.sym = NULL;
+      reloc->u.a.addend = exp.X_add_number;
+      break;
+    case O_symbol:
+      reloc->u.a.sym = exp.X_add_symbol;
+      reloc->u.a.addend = exp.X_add_number;
+      break;
+    default:
+      reloc->u.a.sym = make_expr_symbol (&exp);
+      reloc->u.a.addend = 0;
+      break;
+    }
+
+  as_where (&reloc->file, &reloc->line);
+  reloc->next = reloc_list;
+  reloc_list = reloc;
+
+  demand_empty_rest_of_line ();
+  if (flag_mri)
+    mri_comment_end (stop, stopc);
+}
+
 /* Put the contents of expression EXP into the object file using
    NBYTES bytes.  If need_pass_2 is 1, this does nothing.  */
 
@@ -5010,7 +5311,7 @@ void
 equals (char *sym_name, int reassign)
 {
   char *stop = NULL;
-  char stopc;
+  char stopc = 0;
 
   input_line_pointer++;
   if (*input_line_pointer == '=')
diff --git a/gas/read.h b/gas/read.h
index a18272d8882c..6ac153b6d492 100644
--- a/gas/read.h
+++ b/gas/read.h
@@ -185,4 +185,5 @@ extern void stringer (int append_zero);
 extern void s_xstab (int what);
 extern void s_rva (int);
 extern void s_incbin (int);
+extern void s_vendor_attribute (int);
 extern void s_weakref (int);
diff --git a/gas/sb.c b/gas/sb.c
index ecd772c30c02..5fa0bc669eb3 100644
--- a/gas/sb.c
+++ b/gas/sb.c
@@ -1,5 +1,5 @@
 /* sb.c - string buffer manipulation routines
-   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -21,19 +21,8 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
-#include "config.h"
-#include <stdio.h>
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
-#include <string.h>
-#else
-#include <strings.h>
-#endif
-#include "libiberty.h"
-#include "sb.h"
 #include "as.h"
+#include "sb.h"
 
 /* These routines are about manipulating strings.
 
@@ -56,7 +45,10 @@ static void sb_check (sb *, int);
 static int string_count[sb_max_power_two];
 
 /* Free list of sb structures.  */
-static sb_list_vector free_list;
+static struct
+{
+  sb_element *size[sb_max_power_two];
+} free_list;
 
 /* Initializes an sb.  */
 
@@ -66,8 +58,7 @@ sb_build (sb *ptr, int size)
   /* See if we can find one to allocate.  */
   sb_element *e;
 
-  if (size > sb_max_power_two)
-    abort ();
+  assert (size < sb_max_power_two);
 
   e = free_list.size[size];
   if (!e)
diff --git a/gas/sb.h b/gas/sb.h
index 5732688315f7..5a886f9845f3 100644
--- a/gas/sb.h
+++ b/gas/sb.h
@@ -1,5 +1,5 @@
 /* sb.h - header file for string buffer manipulation routines
-   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003, 2006 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -25,9 +25,6 @@
 
 #define SB_H
 
-#include <stdio.h>
-#include "ansidecl.h"
-
 /* String blocks
 
    I had a couple of choices when deciding upon this data structure.
@@ -70,14 +67,6 @@ typedef struct le
 }
 sb_element;
 
-/* The free list.  */
-
-typedef struct
-{
-  sb_element *size[sb_max_power_two];
-}
-sb_list_vector;
-
 extern void sb_new (sb *);
 extern void sb_kill (sb *);
 extern void sb_add_sb (sb *, sb *);
diff --git a/gas/subsegs.c b/gas/subsegs.c
index 9401d61a834c..00947649d68e 100644
--- a/gas/subsegs.c
+++ b/gas/subsegs.c
@@ -1,6 +1,6 @@
 /* subsegs.c - subsegments -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -27,20 +27,12 @@
 #include "subsegs.h"
 #include "obstack.h"
 
-frchainS *frchain_root, *frchain_now;
+frchainS *frchain_now;
 
 static struct obstack frchains;
 
-/* Gas segment information for bfd_abs_section_ptr and
-   bfd_und_section_ptr.  */
-static segment_info_type *abs_seg_info;
-static segment_info_type *und_seg_info;
-
-static void subseg_set_rest (segT, subsegT);
-
 static fragS dummy_frag;
 
-static frchainS absolute_frchain;
 
 void
 subsegs_begin (void)
@@ -50,16 +42,8 @@ subsegs_begin (void)
   obstack_alignment_mask (&frchains) = __alignof__ (frchainS) - 1;
 #endif
 
-  frchain_root = NULL;
   frchain_now = NULL;		/* Warn new_subseg() that we are booting.  */
-
   frag_now = &dummy_frag;
-
-  absolute_frchain.frch_seg = absolute_section;
-  absolute_frchain.frch_subseg = 0;
-  absolute_frchain.fix_root = absolute_frchain.fix_tail = 0;
-  absolute_frchain.frch_frag_now = &zero_address_frag;
-  absolute_frchain.frch_root = absolute_frchain.frch_last = &zero_address_frag;
 }
 
 /*
@@ -75,37 +59,25 @@ subsegs_begin (void)
 void
 subseg_change (register segT seg, register int subseg)
 {
-  segment_info_type *seginfo;
+  segment_info_type *seginfo = seg_info (seg);
   now_seg = seg;
   now_subseg = subseg;
 
-  if (now_seg == absolute_section)
-    return;
-
-  seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
   if (! seginfo)
     {
-      seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-      memset ((PTR) seginfo, 0, sizeof (*seginfo));
-      seginfo->fix_root = NULL;
-      seginfo->fix_tail = NULL;
+      seginfo = xcalloc (1, sizeof (*seginfo));
       seginfo->bfd_section = seg;
-      seginfo->sym = 0;
-      if (seg == bfd_abs_section_ptr)
-	abs_seg_info = seginfo;
-      else if (seg == bfd_und_section_ptr)
-	und_seg_info = seginfo;
-      else
-	bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
+      bfd_set_section_userdata (stdoutput, seg, seginfo);
     }
 }
 
 static void
 subseg_set_rest (segT seg, subsegT subseg)
 {
-  register frchainS *frcP;	/* crawl frchain chain */
-  register frchainS **lastPP;	/* address of last pointer */
+  frchainS *frcP;		/* crawl frchain chain */
+  frchainS **lastPP;		/* address of last pointer */
   frchainS *newP;		/* address of new frchain */
+  segment_info_type *seginfo;
 
   mri_common_symbol = NULL;
 
@@ -113,72 +85,26 @@ subseg_set_rest (segT seg, subsegT subseg)
     frchain_now->frch_frag_now = frag_now;
 
   assert (frchain_now == 0
-	  || now_seg == undefined_section
-	  || now_seg == absolute_section
 	  || frchain_now->frch_last == frag_now);
 
   subseg_change (seg, (int) subseg);
 
-  if (seg == absolute_section)
-    {
-      frchain_now = &absolute_frchain;
-      frag_now = &zero_address_frag;
-      return;
-    }
+  seginfo = seg_info (seg);
 
-  assert (frchain_now == 0
-	  || now_seg == undefined_section
-	  || frchain_now->frch_last == frag_now);
-
-  /*
-   * Attempt to find or make a frchain for that sub seg.
-   * Crawl along chain of frchainSs, begins @ frchain_root.
-   * If we need to make a frchainS, link it into correct
-   * position of chain rooted in frchain_root.
-   */
-  for (frcP = *(lastPP = &frchain_root);
-       frcP && frcP->frch_seg <= seg;
+  /* Attempt to find or make a frchain for that subsection.
+     We keep the list sorted by subsection number.  */
+  for (frcP = *(lastPP = &seginfo->frchainP);
+       frcP != NULL;
        frcP = *(lastPP = &frcP->frch_next))
+    if (frcP->frch_subseg >= subseg)
+      break;
+
+  if (frcP == NULL || frcP->frch_subseg != subseg)
     {
-      if (frcP->frch_seg == seg
-	  && frcP->frch_subseg >= subseg)
-	{
-	  break;
-	}
-    }
-  /*
-   * frcP:		Address of the 1st frchainS in correct segment with
-   *		frch_subseg >= subseg.
-   *		We want to either use this frchainS, or we want
-   *		to insert a new frchainS just before it.
-   *
-   *		If frcP==NULL, then we are at the end of the chain
-   *		of frchainS-s. A NULL frcP means we fell off the end
-   *		of the chain looking for a
-   *		frch_subseg >= subseg, so we
-   *		must make a new frchainS.
-   *
-   *		If we ever maintain a pointer to
-   *		the last frchainS in the chain, we change that pointer
-   *		ONLY when frcP==NULL.
-   *
-   * lastPP:	Address of the pointer with value frcP;
-   *		Never NULL.
-   *		May point to frchain_root.
-   *
-   */
-  if (!frcP
-      || (frcP->frch_seg > seg
-	  || frcP->frch_subseg > subseg))	/* Kinky logic only works with 2 segments.  */
-    {
-      /*
-       * This should be the only code that creates a frchainS.
-       */
-      segment_info_type *seginfo;
+      /* This should be the only code that creates a frchainS.  */
 
-      newP = (frchainS *) obstack_alloc (&frchains, sizeof (frchainS));
+      newP = obstack_alloc (&frchains, sizeof (frchainS));
       newP->frch_subseg = subseg;
-      newP->frch_seg = seg;
       newP->fix_root = NULL;
       newP->fix_tail = NULL;
       obstack_begin (&newP->frch_obstack, chunksize);
@@ -187,21 +113,15 @@ subseg_set_rest (segT seg, subsegT subseg)
 #endif
       newP->frch_frag_now = frag_alloc (&newP->frch_obstack);
       newP->frch_frag_now->fr_type = rs_fill;
+      newP->frch_cfi_data = NULL;
 
       newP->frch_root = newP->frch_last = newP->frch_frag_now;
 
       *lastPP = newP;
-      newP->frch_next = frcP;	/* perhaps NULL */
-
-      seginfo = seg_info (seg);
-      if (seginfo && (!seginfo->frchainP || seginfo->frchainP == frcP))
-	seginfo->frchainP = newP;
-
+      newP->frch_next = frcP;
       frcP = newP;
     }
-  /*
-   * Here with frcP pointing to the frchainS for subseg.
-   */
+
   frchain_now = frcP;
   frag_now = frcP->frch_frag_now;
 
@@ -221,7 +141,6 @@ subseg_set_rest (segT seg, subsegT subseg)
  * Out:	now_subseg, now_seg updated.
  *	Frchain_now points to the (possibly new) struct frchain for this
  *	sub-segment.
- *	Frchain_root updated if needed.
  */
 
 segT
@@ -244,32 +163,13 @@ subseg_get (const char *segname, int force_new)
   else
     secptr = bfd_make_section_anyway (stdoutput, segname);
 
-#ifdef obj_sec_set_private_data
-  obj_sec_set_private_data (stdoutput, secptr);
-#endif
-
   seginfo = seg_info (secptr);
   if (! seginfo)
     {
-      /* Check whether output_section is set first because secptr may
-	 be bfd_abs_section_ptr.  */
-      if (secptr->output_section != secptr)
-	secptr->output_section = secptr;
-      seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-      memset ((PTR) seginfo, 0, sizeof (*seginfo));
-      seginfo->fix_root = NULL;
-      seginfo->fix_tail = NULL;
+      secptr->output_section = secptr;
+      seginfo = xcalloc (1, sizeof (*seginfo));
       seginfo->bfd_section = secptr;
-      if (secptr == bfd_abs_section_ptr)
-	abs_seg_info = seginfo;
-      else if (secptr == bfd_und_section_ptr)
-	und_seg_info = seginfo;
-      else
-	bfd_set_section_userdata (stdoutput, secptr, (PTR) seginfo);
-      seginfo->frchainP = NULL;
-      seginfo->lineno_list_head = seginfo->lineno_list_tail = NULL;
-      seginfo->sym = NULL;
-      seginfo->dot = NULL;
+      bfd_set_section_userdata (stdoutput, secptr, seginfo);
     }
   return secptr;
 }
@@ -278,13 +178,9 @@ segT
 subseg_new (const char *segname, subsegT subseg)
 {
   segT secptr;
-  segment_info_type *seginfo;
 
   secptr = subseg_get (segname, 0);
   subseg_set_rest (secptr, subseg);
-  seginfo = seg_info (secptr);
-  if (! seginfo->frchainP)
-    seginfo->frchainP = frchain_now;
   return secptr;
 }
 
@@ -294,13 +190,9 @@ segT
 subseg_force_new (const char *segname, subsegT subseg)
 {
   segT secptr;
-  segment_info_type *seginfo;
 
   secptr = subseg_get (segname, 1);
   subseg_set_rest (secptr, subseg);
-  seginfo = seg_info (secptr);
-  if (! seginfo->frchainP)
-    seginfo->frchainP = frchain_now;
   return secptr;
 }
 
@@ -316,19 +208,6 @@ subseg_set (segT secptr, subsegT subseg)
 #define obj_sec_sym_ok_for_reloc(SEC)	0
 #endif
 
-/* Get the gas information we are storing for a section.  */
-
-segment_info_type *
-seg_info (segT sec)
-{
-  if (sec == bfd_abs_section_ptr)
-    return abs_seg_info;
-  else if (sec == bfd_und_section_ptr)
-    return und_seg_info;
-  else
-    return (segment_info_type *) bfd_get_section_userdata (stdoutput, sec);
-}
-
 symbolS *
 section_symbol (segT sec)
 {
@@ -418,28 +297,33 @@ void
 subsegs_print_statistics (FILE *file)
 {
   frchainS *frchp;
+  asection *s;
+
   fprintf (file, "frag chains:\n");
-  for (frchp = frchain_root; frchp; frchp = frchp->frch_next)
+  for (s = stdoutput->sections; s; s = s->next)
     {
-      int count = 0;
-      fragS *fragp;
+      segment_info_type *seginfo;
 
-      /* If frch_subseg is non-zero, it's probably been chained onto
-	 the end of a previous subsection.  Don't count it again.  */
-      if (frchp->frch_subseg != 0)
+      /* Skip gas-internal sections.  */
+      if (segment_name (s)[0] == '*')
 	continue;
 
-      /* Skip gas-internal sections.  */
-      if (segment_name (frchp->frch_seg)[0] == '*')
+      seginfo = seg_info (s);
+      if (!seginfo)
 	continue;
 
-      for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
+      for (frchp = seginfo->frchainP; frchp; frchp = frchp->frch_next)
 	{
-	  count++;
+	  int count = 0;
+	  fragS *fragp;
+
+	  for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
+	    count++;
+
+	  fprintf (file, "\n");
+	  fprintf (file, "\t%p %-10s\t%10d frags\n", (void *) frchp,
+		   segment_name (s), count);
 	}
-      fprintf (file, "\n");
-      fprintf (file, "\t%p %-10s\t%10d frags\n", (void *) frchp,
-	       segment_name (frchp->frch_seg), count);
     }
 }
 
diff --git a/gas/subsegs.h b/gas/subsegs.h
index 23ab4f9cf48e..54a5a6ab2cc6 100644
--- a/gas/subsegs.h
+++ b/gas/subsegs.h
@@ -1,6 +1,6 @@
 /* subsegs.h -> subsegs.c
-   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2003, 2005
-   Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2003, 2005,
+   2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -40,24 +40,23 @@
 
 #include "obstack.h"
 
+struct frch_cfi_data;
+
 struct frchain			/* control building of a frag chain */
 {				/* FRCH = FRagment CHain control */
   struct frag *frch_root;	/* 1st struct frag in chain, or NULL */
   struct frag *frch_last;	/* last struct frag in chain, or NULL */
   struct frchain *frch_next;	/* next in chain of struct frchain-s */
-  segT frch_seg;		/* SEG_TEXT or SEG_DATA.  */
   subsegT frch_subseg;		/* subsegment number of this chain */
   fixS *fix_root;		/* Root of fixups for this subsegment.  */
   fixS *fix_tail;		/* Last fixup for this subsegment.  */
   struct obstack frch_obstack;	/* for objects in this frag chain */
   fragS *frch_frag_now;		/* frag_now for this subsegment */
+  struct frch_cfi_data *frch_cfi_data;
 };
 
 typedef struct frchain frchainS;
 
-/* All subsegments' chains hang off here.  NULL means no frchains yet.  */
-extern frchainS *frchain_root;
-
 /* Frchain we are assembling into now.  That is, the current segment's
    frag chain, even if it contains no (complete) frags.  */
 extern frchainS *frchain_now;
@@ -109,7 +108,10 @@ typedef struct segment_info_struct {
 #endif
 } segment_info_type;
 
-extern segment_info_type *seg_info (segT);
+
+#define seg_info(sec) \
+  ((segment_info_type *) bfd_get_section_userdata (stdoutput, sec))
+
 extern symbolS *section_symbol (segT);
 
 extern void subsegs_print_statistics (FILE *);
diff --git a/gas/symbols.c b/gas/symbols.c
index 5935a7477ae0..816395ff22d9 100644
--- a/gas/symbols.c
+++ b/gas/symbols.c
@@ -1,6 +1,6 @@
 /* symbols.c -symbol table-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -144,8 +144,7 @@ symbol_create (const char *name, /* It is copied, the caller can destroy/modify.
 
   symbolP->bsym = bfd_make_empty_symbol (stdoutput);
   if (symbolP->bsym == NULL)
-    as_perror ("%s", "bfd_make_empty_symbol");
-  symbolP->bsym->udata.p = (PTR) symbolP;
+    as_fatal ("bfd_make_empty_symbol: %s", bfd_errmsg (bfd_get_error ()));
   S_SET_NAME (symbolP, preserved_copy_of_name);
 
   S_SET_SEGMENT (symbolP, segment);
@@ -336,10 +335,7 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 	       || S_IS_COMMON (symbolP)
 	       || S_IS_VOLATILE (symbolP))
 	{
-	  if (S_IS_VOLATILE (symbolP)
-	      /* This could be avoided when the symbol wasn't used so far, but
-		 the comment in struc-symbol.h says this flag isn't reliable.  */
-	      && (1 || !symbol_used_p (symbolP)))
+	  if (S_IS_VOLATILE (symbolP))
 	    {
 	      symbolP = symbol_clone (symbolP, 1);
 	      S_SET_VALUE (symbolP, 0);
@@ -567,18 +563,15 @@ symbol_clone (symbolS *orgsymP, int replace)
     orgsymP = local_symbol_convert ((struct local_symbol *) orgsymP);
   bsymorg = orgsymP->bsym;
 
-  know (S_IS_DEFINED (orgsymP));
-
   newsymP = obstack_alloc (&notes, sizeof (*newsymP));
   *newsymP = *orgsymP;
   bsymnew = bfd_make_empty_symbol (bfd_asymbol_bfd (bsymorg));
   if (bsymnew == NULL)
-    as_perror ("%s", "bfd_make_empty_symbol");
+    as_fatal ("bfd_make_empty_symbol: %s", bfd_errmsg (bfd_get_error ()));
   newsymP->bsym = bsymnew;
   bsymnew->name = bsymorg->name;
   bsymnew->flags =  bsymorg->flags;
   bsymnew->section =  bsymorg->section;
-  bsymnew->udata.p = (PTR) newsymP;
   bfd_copy_private_symbol_data (bfd_asymbol_bfd (bsymorg), bsymorg,
 				bfd_asymbol_bfd (bsymnew), bsymnew);
 
@@ -603,11 +596,13 @@ symbol_clone (symbolS *orgsymP, int replace)
 	symbol_lastP = newsymP;
       else if (orgsymP->sy_next)
 	orgsymP->sy_next->sy_previous = newsymP;
-      orgsymP->sy_next = NULL;
+      orgsymP->sy_previous = orgsymP->sy_next = orgsymP;
       debug_verify_symchain (symbol_rootP, symbol_lastP);
 
       symbol_table_insert (newsymP);
     }
+  else
+    newsymP->sy_previous = newsymP->sy_next = newsymP;
 
   return newsymP;
 }
@@ -884,6 +879,69 @@ verify_symbol_chain (symbolS *rootP, symbolS *lastP)
   assert (lastP == symbolP);
 }
 
+#ifdef OBJ_COMPLEX_RELC
+
+static int
+use_complex_relocs_for (symbolS * symp)
+{
+  switch (symp->sy_value.X_op)
+    {
+    case O_constant:
+      return 0;
+
+    case O_symbol:
+    case O_symbol_rva:
+    case O_uminus:
+    case O_bit_not:
+    case O_logical_not:
+      if (  (S_IS_COMMON (symp->sy_value.X_add_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+	  &&
+	      (S_IS_DEFINED (symp->sy_value.X_add_symbol)
+	   && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section))
+	return 0;
+      break;
+
+    case O_multiply:
+    case O_divide:
+    case O_modulus:
+    case O_left_shift:
+    case O_right_shift:
+    case O_bit_inclusive_or:
+    case O_bit_or_not:
+    case O_bit_exclusive_or:
+    case O_bit_and:
+    case O_add:
+    case O_subtract:
+    case O_eq:
+    case O_ne:
+    case O_lt:
+    case O_le:
+    case O_ge:
+    case O_gt:
+    case O_logical_and:
+    case O_logical_or:
+
+      if (  (S_IS_COMMON (symp->sy_value.X_add_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+	  && 
+	    (S_IS_COMMON (symp->sy_value.X_op_symbol)
+	   || S_IS_LOCAL (symp->sy_value.X_op_symbol))
+
+	  && S_IS_DEFINED (symp->sy_value.X_add_symbol)
+	  && S_IS_DEFINED (symp->sy_value.X_op_symbol)
+	  && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section
+	  && S_GET_SEGMENT (symp->sy_value.X_op_symbol) != expr_section)
+	return 0;
+      break;
+      
+    default:
+      break;
+    }
+  return 1;
+}
+#endif
+
 static void
 report_op_error (symbolS *symp, symbolS *left, symbolS *right)
 {
@@ -986,6 +1044,53 @@ resolve_symbol_value (symbolS *symp)
       final_val = 0;
       resolved = 1;
     }
+#ifdef OBJ_COMPLEX_RELC
+  else if (final_seg == expr_section
+	   && use_complex_relocs_for (symp))
+    {
+      symbolS * relc_symbol = NULL;
+      char * relc_symbol_name = NULL;
+
+      relc_symbol_name = symbol_relc_make_expr (& symp->sy_value);
+
+      /* For debugging, print out conversion input & output.  */
+#ifdef DEBUG_SYMS
+      print_expr (& symp->sy_value);
+      if (relc_symbol_name)
+	fprintf (stderr, "-> relc symbol: %s\n", relc_symbol_name);
+#endif
+
+      if (relc_symbol_name != NULL)
+	relc_symbol = symbol_new (relc_symbol_name, undefined_section,
+				  0, & zero_address_frag);
+
+      if (relc_symbol == NULL)
+	{
+	  as_bad (_("cannot convert expression symbol %s to complex relocation"),
+		  S_GET_NAME (symp));
+	  resolved = 0;
+	}
+      else
+	{
+	  symbol_table_insert (relc_symbol);
+
+ 	  /* S_CLEAR_EXTERNAL (relc_symbol); */
+	  if (symp->bsym->flags & BSF_SRELC)
+	    relc_symbol->bsym->flags |= BSF_SRELC;
+	  else
+	    relc_symbol->bsym->flags |= BSF_RELC;	  
+	  /* symp->bsym->flags |= BSF_RELC; */
+	  copy_symbol_attributes (symp, relc_symbol);
+	  symp->sy_value.X_op = O_symbol;
+	  symp->sy_value.X_add_symbol = relc_symbol;
+	  symp->sy_value.X_add_number = 0;
+	  resolved = 1;
+	}
+
+      final_seg = undefined_section;
+      goto exit_dont_set_value;
+    }
+#endif
   else
     {
       symbolS *add_symbol, *op_symbol;
@@ -1016,6 +1121,9 @@ resolve_symbol_value (symbolS *symp)
 	  final_val += symp->sy_frag->fr_address / OCTETS_PER_BYTE;
 	  if (final_seg == expr_section)
 	    final_seg = absolute_section;
+	  /* Fall through.  */
+
+	case O_register:
 	  resolved = 1;
 	  break;
 
@@ -1083,8 +1191,9 @@ resolve_symbol_value (symbolS *symp)
 	      symp->sy_resolving = 0;
 	      goto exit_dont_set_value;
 	    }
-	  else if (finalize_syms && final_seg == expr_section
-		   && seg_left != expr_section)
+	  else if (finalize_syms
+		   && ((final_seg == expr_section && seg_left != expr_section)
+		       || symbol_shadow_p (symp)))
 	    {
 	      /* If the symbol is an expression symbol, do similarly
 		 as for undefined and common syms above.  Handles
@@ -1292,7 +1401,6 @@ resolve_symbol_value (symbolS *symp)
 		      && symbol_resolved_p (op_symbol));
 	  break;
 
-	case O_register:
 	case O_big:
 	case O_illegal:
 	  /* Give an error (below) if not in expr_section.  We don't
@@ -1839,6 +1947,10 @@ copy_symbol_attributes (symbolS *dest, symbolS *src)
 #ifdef OBJ_COPY_SYMBOL_ATTRIBUTES
   OBJ_COPY_SYMBOL_ATTRIBUTES (dest, src);
 #endif
+
+#ifdef TC_COPY_SYMBOL_ATTRIBUTES
+  TC_COPY_SYMBOL_ATTRIBUTES (dest, src);
+#endif
 }
 
 int
@@ -2497,6 +2609,17 @@ symbol_constant_p (symbolS *s)
   return s->sy_value.X_op == O_constant;
 }
 
+/* Return whether a symbol was cloned and thus removed from the global
+   symbol list.  */
+
+int
+symbol_shadow_p (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_next == s;
+}
+
 /* Return the BFD symbol for a symbol.  */
 
 asymbol *
@@ -2818,3 +2941,219 @@ symbol_print_statistics (FILE *file)
   fprintf (file, "%lu mini local symbols created, %lu converted\n",
 	   local_symbol_count, local_symbol_conversion_count);
 }
+
+#ifdef OBJ_COMPLEX_RELC
+
+/* Convert given symbol to a new complex-relocation symbol name.  This
+   may be a recursive function, since it might be called for non-leaf
+   nodes (plain symbols) in the expression tree.  The caller owns the
+   returning string, so should free it eventually.  Errors are
+   indicated via as_bad and a NULL return value.  The given symbol
+   is marked with sy_used_in_reloc.  */
+
+char *
+symbol_relc_make_sym (symbolS * sym)
+{
+  char * terminal = NULL;
+  const char * sname;
+  char typetag;
+  int sname_len;
+
+  assert (sym != NULL);
+
+  /* Recurse to symbol_relc_make_expr if this symbol
+     is defined as an expression or a plain value.  */
+  if (   S_GET_SEGMENT (sym) == expr_section
+      || S_GET_SEGMENT (sym) == absolute_section)
+    return symbol_relc_make_expr (& sym->sy_value);
+
+  /* This may be a "fake symbol" L0\001, referring to ".".
+     Write out a special null symbol to refer to this position.  */
+  if (! strcmp (S_GET_NAME (sym), FAKE_LABEL_NAME))
+    return xstrdup (".");
+
+  /* We hope this is a plain leaf symbol.  Construct the encoding
+     as {S,s}II...:CCCCCCC....
+     where 'S'/'s' means section symbol / plain symbol
+     III is decimal for the symbol name length
+     CCC is the symbol name itself.  */
+  symbol_mark_used_in_reloc (sym);
+
+  sname = S_GET_NAME (sym);
+  sname_len = strlen (sname);
+  typetag = symbol_section_p (sym) ? 'S' : 's';
+
+  terminal = xmalloc (1 /* S or s */
+		      + 8 /* sname_len in decimal */
+		      + 1 /* _ spacer */
+		      + sname_len /* name itself */
+		      + 1 /* \0 */ );
+
+  sprintf (terminal, "%c%d:%s", typetag, sname_len, sname);
+  return terminal;
+}
+
+/* Convert given value to a new complex-relocation symbol name.  This
+   is a non-recursive function, since it is be called for leaf nodes
+   (plain values) in the expression tree.  The caller owns the
+   returning string, so should free() it eventually.  No errors.  */
+
+char *
+symbol_relc_make_value (offsetT val)
+{
+  char * terminal = xmalloc (28);  /* Enough for long long.  */
+
+  terminal[0] = '#';
+  sprintf_vma (& terminal[1], val);
+  return terminal;
+}
+
+/* Convert given expression to a new complex-relocation symbol name.
+   This is a recursive function, since it traverses the entire given
+   expression tree.  The caller owns the returning string, so should
+   free() it eventually.  Errors are indicated via as_bad() and a NULL
+   return value.  */
+
+char *
+symbol_relc_make_expr (expressionS * exp)
+{
+  char * opstr = NULL; /* Operator prefix string.  */
+  int    arity = 0;    /* Arity of this operator.  */
+  char * operands[3];  /* Up to three operands.  */
+  char * concat_string = NULL;
+
+  operands[0] = operands[1] = operands[2] = NULL;
+
+  assert (exp != NULL);
+
+  /* Match known operators -> fill in opstr, arity, operands[] and fall
+     through to construct subexpression fragments; may instead return 
+     string directly for leaf nodes.  */
+
+  /* See expr.h for the meaning of all these enums.  Many operators 
+     have an unnatural arity (X_add_number implicitly added).  The
+     conversion logic expands them to explicit "+" subexpressions.   */
+
+  switch (exp->X_op)
+    {
+    default:
+      as_bad ("Unknown expression operator (enum %d)", exp->X_op);
+      break;
+
+      /* Leaf nodes.  */
+    case O_constant:
+      return symbol_relc_make_value (exp->X_add_number);
+
+    case O_symbol:
+      if (exp->X_add_number) 
+	{ 
+	  arity = 2; 
+	  opstr = "+"; 
+	  operands[0] = symbol_relc_make_sym (exp->X_add_symbol);
+	  operands[1] = symbol_relc_make_value (exp->X_add_number);
+	  break;
+	}
+      else
+	return symbol_relc_make_sym (exp->X_add_symbol);
+
+      /* Helper macros for nesting nodes.  */
+
+#define HANDLE_XADD_OPT1(str_) 						\
+      if (exp->X_add_number)						\
+        {								\
+          arity = 2;							\
+          opstr = "+:" str_;						\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_value (exp->X_add_number);	\
+          break;							\
+        }								\
+      else								\
+        {								\
+          arity = 1;							\
+          opstr = str_;							\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+        }								\
+      break
+      
+#define HANDLE_XADD_OPT2(str_) 						\
+      if (exp->X_add_number)						\
+        {								\
+          arity = 3;							\
+          opstr = "+:" str_;						\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_sym (exp->X_op_symbol);	\
+          operands[2] = symbol_relc_make_value (exp->X_add_number);	\
+        }								\
+      else								\
+        {								\
+          arity = 2;							\
+          opstr = str_;							\
+          operands[0] = symbol_relc_make_sym (exp->X_add_symbol);	\
+          operands[1] = symbol_relc_make_sym (exp->X_op_symbol);	\
+        } 								\
+      break
+
+      /* Nesting nodes.  */
+
+    case O_uminus:       	HANDLE_XADD_OPT1 ("0-");
+    case O_bit_not:      	HANDLE_XADD_OPT1 ("~");
+    case O_logical_not:  	HANDLE_XADD_OPT1 ("!");
+    case O_multiply:     	HANDLE_XADD_OPT2 ("*");
+    case O_divide:       	HANDLE_XADD_OPT2 ("/");
+    case O_modulus:      	HANDLE_XADD_OPT2 ("%");
+    case O_left_shift:   	HANDLE_XADD_OPT2 ("<<");
+    case O_right_shift:  	HANDLE_XADD_OPT2 (">>");
+    case O_bit_inclusive_or:	HANDLE_XADD_OPT2 ("|");
+    case O_bit_exclusive_or:	HANDLE_XADD_OPT2 ("^");
+    case O_bit_and:      	HANDLE_XADD_OPT2 ("&");
+    case O_add:          	HANDLE_XADD_OPT2 ("+");
+    case O_subtract:     	HANDLE_XADD_OPT2 ("-");
+    case O_eq:           	HANDLE_XADD_OPT2 ("==");
+    case O_ne:           	HANDLE_XADD_OPT2 ("!=");
+    case O_lt:           	HANDLE_XADD_OPT2 ("<");
+    case O_le:           	HANDLE_XADD_OPT2 ("<=");
+    case O_ge:           	HANDLE_XADD_OPT2 (">=");
+    case O_gt:           	HANDLE_XADD_OPT2 (">");
+    case O_logical_and:  	HANDLE_XADD_OPT2 ("&&");
+    case O_logical_or:   	HANDLE_XADD_OPT2 ("||");
+    }
+
+  /* Validate & reject early.  */
+  if (arity >= 1 && ((operands[0] == NULL) || (strlen (operands[0]) == 0)))
+    opstr = NULL;
+  if (arity >= 2 && ((operands[1] == NULL) || (strlen (operands[1]) == 0)))
+    opstr = NULL;
+  if (arity >= 3 && ((operands[2] == NULL) || (strlen (operands[2]) == 0)))
+    opstr = NULL;
+
+  if (opstr == NULL)
+    concat_string = NULL;
+  else
+    {
+      /* Allocate new string; include inter-operand padding gaps etc.  */
+      concat_string = xmalloc (strlen (opstr) 
+			       + 1
+			       + (arity >= 1 ? (strlen (operands[0]) + 1 ) : 0)
+			       + (arity >= 2 ? (strlen (operands[1]) + 1 ) : 0)
+			       + (arity >= 3 ? (strlen (operands[2]) + 0 ) : 0)
+			       + 1);
+      assert (concat_string != NULL);
+      
+      /* Format the thing.  */
+      sprintf (concat_string, 
+	       (arity == 0 ? "%s" :
+		arity == 1 ? "%s:%s" :
+		arity == 2 ? "%s:%s:%s" :
+		/* arity == 3 */ "%s:%s:%s:%s"),
+	       opstr, operands[0], operands[1], operands[2]);
+    }
+
+  /* Free operand strings (not opstr).  */
+  if (arity >= 1) xfree (operands[0]);
+  if (arity >= 2) xfree (operands[1]);
+  if (arity >= 3) xfree (operands[2]);
+
+  return concat_string;
+}
+
+#endif
diff --git a/gas/symbols.h b/gas/symbols.h
index 7a4b8f7a6da3..483f8ee089bf 100644
--- a/gas/symbols.h
+++ b/gas/symbols.h
@@ -35,6 +35,9 @@ extern int symbol_table_frozen;
    default.  */
 extern int symbols_case_sensitive;
 
+char * symbol_relc_make_expr  (expressionS *);
+char * symbol_relc_make_sym   (symbolS *);
+char * symbol_relc_make_value (offsetT);
 char *decode_local_label_name (char *s);
 symbolS *symbol_find (const char *name);
 symbolS *symbol_find_noref (const char *name, int noref);
@@ -192,6 +195,7 @@ extern int symbol_section_p (symbolS *);
 extern int symbol_equated_p (symbolS *);
 extern int symbol_equated_reloc_p (symbolS *);
 extern int symbol_constant_p (symbolS *);
+extern int symbol_shadow_p (symbolS *);
 extern asymbol *symbol_get_bfdsym (symbolS *);
 extern void symbol_set_bfdsym (symbolS *, asymbol *);
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6637ab929508..f6e6691dc53e 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,348 +1,633 @@
-2006-06-14  Thiemo Seufer  <ths@mips.com>
+2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/m68k/mcf-coproc.d: New.
+	* gas/m68k/mcf-coproc.s: New.
+	* gas/m68k/all.exp: Add it.
+
+2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
+
+	* gas/cr16: New directory
+	* gas/cr16.exp: New file
+	* add_test.d and  add_test.s: New files
+	* and_test.d and and_test.s: New files
+	* ash_test.d and ash_test.s: New files
+	* bal_test.d and bal_test.s: New files
+	* bcc_test.d and bcc_test.s: New files
+	* beq0_test.d and beq0_test.s: New files
+	* cbitb_test.d and cbitb_test.s: New files
+	* cbitw_test.d and cbitw_test.s: New files
+	* cinv_test.d and cinv_test.s: New files
+	* cmp_test.d and cmp_test.s: New files
+	* excp_test.d and excp_test.s: New files
+	* jal_test.d and jal_test.s: New files
+	* jcc_test.d and jcc_test.s: New files
+	* loadb_test.d and loadb_test.s: New files
+	* loadd_test.d and loadd_test.s: New files
+	* loadm_test.d and loadm_test.s: New files
+	* loadw_test.d and loadw_test.s: New files
+	* lpsp_test.d and lpsp_test.s: New files
+	* lsh_test.d and lsh_test.s: New files
+	* mov_test.d and mov_test.s: New files
+	* mul_test.d and mul_test.s: New files
+	* or_test.d and or_test.s: New files
+	* popret_test.d and popret_test.s: New files
+	* pop_test.d and pop_test.s: New files
+	* push_test.d and push_test.s: New files
+	* sbitb_test.d and sbitb_test.s: New files
+	* sbitw_test.d and sbitw_test.s: New files
+	* scc_test.d and scc_test.s: New files
+	* storb_test.d and storb_test.s: New files
+	* stord_test.d and stord_test.s: New files
+	* storm_test.d and storm_test.s: New files
+	* storw_test.d and storw_test.s: New files
+	* sub_test.d and sub_test.s: New files
+	* tbitb_test.d and tbitb_test.s: New files
+	* tbit_test.d and tbit_test.s: New files
+	* tbitw_test.d and tbitw_test.s: New files
+	* xor_test.d and xor_test.s: New files
+
+2007-06-26  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/vfp1xD.d: Add new fmrx/fmxr tests.
+	* gas/arm/vfp1xD.s: Ditto.
+	* gas/arm/vfp1xD_t2.d: Ditto.
+	* gas/arm/vfp1xD_t2.s: Ditto.
+
+2007-06-24  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/backslash-at.d: Fix for non-ELF arm targets.
+
+2007-06-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4667
+	* gas/i386/i386.exp: Run simd, simd-intel, x86-64-simd
+	and x86-64-simd-intel.
+
+	* gas/i386/opcode-intel.d: Updated.
+
+	* gas/i386/simd-intel.d: New.
+	* gas/i386/simd.d: Likewise.
+	* gas/i386/simd.s: Likewise.
+	* gas/i386/x86-64-simd-intel.d: Likewise.
+	* gas/i386/x86-64-simd.d: Likewise.
+	* gas/i386/x86-64-simd.s: Likewise.
+
+2007-06-18  Kazu Hirata  <kazu@codesourcery.com>
+
+	* gas/m68k/all.exp: Run mcf-wdebug.
+	* gas/testsuite/gas/m68k/mcf-wdebug.d,
+	gas/testsuite/gas/m68k/mcf-wdebug.s: New.
+
+2007-06-14  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Add tests for shift instructions.
+	* gas/arm/thumb32.d: Ditto.
+
+2007-06-06  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb.d: Update expected output.
+	* gas/arm/thumb2_relax.d: Ditto.
+
+2007-06-05  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Add writeback addressing mode tests.
+	* gas/arm/thumb32.s: Update expected output.
+
+2007-06-05  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/4587
+	* gas/sparc/sparc.exp: Run pr4587 list test.
+	* gas/sparc/pr4587.s: New test case.
+	* gas/sparc/pr4587.l: Expected assembler output.
+
+2007-06-05  Nick Clifton  <nickc@redhat.com>
+
+	* lib/gas-defs.exp (run_list_test): New proc.
+	* gas/alpha/alpha.exp: Delete proc run_list_test.
+	* gas/bfin/bfin.exp : Likewise.
+	* gas/cfi/cfi.exp : Likewise.
+	* gas/crx/allinsn.exp : Likewise.
+	* gas/d10v/d10v.exp : Likewise.
+	* gas/d30v/d30v.exp : Likewise.
+	* gas/frv/allinsn.exp : Likewise.
+	* gas/i386/i386.exp : Likewise.
+	* gas/i860.i860.exp : Likewise.
+	* gas/ia64/ia64.exp : Likewise.
+	* gas/lns/lns.exp : Likewise.
+	* gas/macros/macros.exp : Likewise.
+	* gas/maxq10/maxq10.exp : Likewise.
+	* gas/maxq20/maxq20.exp : Likewise.
+	* gas/mips/mips.exp : Likewise.
+	* gas/mmix/mmix-list.exp : Likewise.
+	* gas/mn10300/basic.exp : Likewise.
+	* gas/msp430/msp430.exp : Likewise.
+	* gas/pdp11/pdp11.exp : Likewise.
+	* gas/ppc/ppc.exp : Likewise.
+	* gas/s390/s390.exp : Likewise.
+	* gas/elf/elf.exp (proc run_list_test): Rename to run_elf_list_test.
+
+2007-05-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR gas/4558
+	* gas/sparc/sparc.exp: Add v9branch{1,2,3,4,5} tests.
+	* gas/sparc/v9branch1.d: New test.
+	* gas/sparc/v9branch1.s: New.
+	* gas/sparc/v9branch2.d: New test.
+	* gas/sparc/v9branch2.s: New.
+	* gas/sparc/v9branch3.d: New test.
+	* gas/sparc/v9branch3.s: New.
+	* gas/sparc/v9branch4.d: New test.
+	* gas/sparc/v9branch4.s: New.
+	* gas/sparc/v9branch5.d: New test.
+	* gas/sparc/v9branch5.s: New.
+
+2007-03-25  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Add tests for subs pc, lr.
+	* gas/arm/thumb32.d: Change error-output: to stderr:.
+	Update expected output.
+
+2007-05-22  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/backslash-at.d: Update expected output.
+
+2007-05-17  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/mips/mips16e-jrc.d, gas/mips/mips16e-save.d,
-	gas/mips/mips32-dsp.d, gas/mips/mips32-mt.d: Explicitly specify
-	o32 ABI.
+	2003-06-05  Michal Ludvig  <mludvig@suse.cz>
+	* gas/cfi/cfi-x86_64.s: Test new directives
+	and different writings of registers and numbers.
+	* gas/cfi/cfi-x86_64.d: Updated pattern to
+	match the above change.
+
+2007-05-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* gas/arm/backslash-at.d: New.
+	* gas/arm/backslash-at.s: New.
+
+2007-05-15  Vincent Riviere  <vincent.riviere@freesbee.fr>
+	    Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3041
+	* gas/m68k/p3041.s: New test case.
+	* gas/m68k/p3041.d: New expected disassembly.
+	* gas/m68k/all.exp: Run new test for m68k-*-netbsd toolchains.
+	Only run arch-cpu-1 test for ELF based toolchains.
+
+	Tidy ups for m68k-netbsd gas toolchain:
+	* gas/m68k/cpu32.d: Allow for extra text after expected
+	disassembly.
+	* gas/m68k/mcf-trap.d: Allow for alternative trap mnemonics.
+	* gas/m68k/br-isab.d: Fix name of test.
+	* gas/m68k/br-isac.d: Fix name of test.
+	
+2007-05-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4502
+	* gas/i386/amd.d: Replace "pfmulhrw" with "pmulhrw".
+
+2007-05-04  Kazu Hirata  <kazu@codesourcery.com>
+
+	* gas/m68k/all.exp: Skip fmoveml on fido.
+
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/4460
+	* gas/i386/gotpc.s: Add a new test.
+	* gas/i386/reloc64.s: Likewise.
+
+	* gas/i386/gotpc.d: Updated.
+	* gas/i386/reloc64.d: Likewise.
+
+2007-05-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/crc32-intel.d: Updated.
+	* gas/i386/crc32.d: Likewise.
+	* gas/i386/sse4_2.d: Likewise.
+	* gas/i386/x86-64-crc32-intel.d: Likewise.
+	* gas/i386/x86-64-crc32.d: Likewise.
+	* gas/i386/x86-64-sse4_2.d: Likewise.
+
+	* gas/i386/crc32.s: Remove crc32 instructions with ambiguous
+	operand size and suffix in crc32 instructions in Intel mode.
+	* gas/i386/x86-64-crc32.s: Likewise.
+
+	* gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous
+	operand size.
+	* gas/i386/x86-64-sse4_2.s: Likewise.
+
+	* gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32.
+
+	* gas/i386/inval-crc32.l: New.
+	* gas/i386/inval-crc32.s: Likewise.
+	* gas/i386/x86-64-inval-crc32.l: Likewise.
+	* gas/i386/x86-64-inval-crc32.s: Likewise.
+
+2007-05-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/crc32-intel.d: New file.
+	* gas/i386/crc32.d:Likewise.
+	* gas/i386/crc32.s:Likewise.
+	* gas/i386/x86-64-crc32-intel.d:Likewise.
+	* gas/i386/x86-64-crc32.d:Likewise.
+	* gas/i386/x86-64-crc32.s:Likewise.
+
+	* gas/i386/i386.exp: Run crc32, crc32-intel, x86-64-crc32
+	and x86-64-crc32-intel.
+
+2007-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4430
+	* gas/i386/amd.d: Updated.
+	* gas/i386/immed32.d: Likewise.
+	* gas/i386/intel.d: Likewise.
+	* gas/i386/intel16.d: Likewise.
+	* gas/i386/intelok.d: Likewise.
+	* gas/i386/jump16.d: Likewise.
+	* gas/i386/naked.d: Likewise.
+	* gas/i386/opcode-suffix.d: Likewise.
+	* gas/i386/opcode.d: Likewise.
+	* gas/i386/prescott.d: Likewise.
+	* gas/i386/ssemmx2.d: Likewise.
+	* gas/i386/tlsd.d: Likewise.
+	* gas/i386/tlspic.d: Likewise.
+	* gas/i386/x86-64-addr32.d: Likewise.
+	* gas/i386/x86-64-prescott.d: Likewise.
+	* gas/i386/x86-64-rip.d: Likewise.
+	* gas/i386/x86_64.d: Likewise.
 
-2006-05-26  Richard Sandiford  <richard@codesourcery.com>
+2007-04-26  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
-	* gas/m68k/mcf-fpu.d: Adjust accordingly.
+	PR binutils/4429
+	* gas/i386/i386.exp: Run "x86-64-addr32-intel" and
+	"x86-64-rip-intel".
 
-2006-05-22  Nick Clifton  <nickc@redhat.com>
+	* gas/i386/intelok.d: Updated.
 
-	* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in
-	warning messages.
-	* gas/mips/mips32-mt.l: Likewise.
+	* gas/i386/x86-64-addr32-intel.d: New file.
+	* gas/i386/x86-64-rip-intel.d: Likewise.
 
-2006-05-19  Thiemo Seufer  <ths@mips.com>
+2007-04-24  Andreas Krebbel  <krebbel1@de.ibm.com>
 
-	* gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add little
-	endian testcases.
-	* gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian.
-	* gas/mips/mips.exp: Run new testcases.
+	* gas/s390/zarch-z9-ec.d: Add pfpo, ectg and csst.
+	* gas/s390/zarch-z9-ec.s: Likewise.
 
-2006-05-11  Thiemo Seufer  <ths@mips.com>
+2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* gas/mips/jal-range.l: Don't check the range of j or jal
-	addresses.
+	* gas/m68k/br-isaa.s: New.
+	* gas/m68k/br-isaa.d: New.
+	* gas/m68k/br-isab.s: New.
+	* gas/m68k/br-isab.d: New.
+	* gas/m68k/br-isac.s: New.
+	* gas/m68k/br-isac.d: New.
+	* gas/m68k/all.exp: Adjust.
 
-2006-05-04  Thiemo Seufer  <ths@mips.com>
+2007-04-21  Richard Earnshaw  <rearnsha@arm.com>
 
-	* gas/mips/mips32-mt.d: Fix mftr argument order.
+	* gas/arm/arch4t.d: Convert to unified syntax.
+	* gas/arm/archv6.d: Likewise.
+	* gas/arm/archv6t2.d: Likewise.
+	* gas/arm/arch3.d: Likewise.
+	* gas/arm/arch7dm.d: Likewise.
+	* gas/arm/arch7t.d: Likewise.
+	* gas/arm/archv1.d: Likewise.
+	* gas/arm/copro.d: Likewise.
+	* gas/arm/inst.d: Likewise.
+	* gas/arm/macro1.d: Likewise.
+	* gas/arm/tcompat.d: Likewise.
+	* gas/arm/wince_inst.d: Likewise.
+	* gas/arm/xscale.d: Likewise.
 
-2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+	* gas/arm/thumb.d: White space cleanup.
+	* gas/arm/thumb2_relax.d: Likewise.
+	* gas/arm/thumb32.d: Likewise.
+	
+2007-04-20  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh.
-	* gas/arm/iwmmxt.d: Update expected results.
-	* gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh.
-	* gas/arm/iwmmxt-bad2.l: Update expected error messages.
+	* gas/m68k/ctrl-1.d, gas/m68k/ctrl-1.s: New.
+	* gas/m68k/ctrl-2.d, gas/m68k/ctrl-2.s: New.
+	* gas/m68k/all.exp: Add them.
 
-2006-04-16  Nick Clifton  <nickc@redhat.com>
+2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 
-	* gas/arm/arch7.d: Skip test for non-ELF targets.
-	* gas/arm/blx-local.d: Likewise.
-	* gas/arm/svc.d: Likewise.
-	* gas/arm/thumb2_bcond.d: Likewise.
-	* gas/arm/thumb2_it_bad.d: Likewise.
+	* gas/ppc/range64.s: New.
+	* gas/ppc/range64.l: New.
+	* gas/ppc/range.s: New.
+	* gas/ppc/range.l: New.
+	* gas/ppc/ppc.exp (run_list_test): New.  Use to run new tests.
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+2007-04-20  Richard Earnshaw  <rearnsha@arm.com>
 
-	* gas/arm/blx-local.d: New test.
-	* gas/arm/blx-local.d: New test.
+	* gas/arm/mapshort.s: Add a small .data section.
+	* gas/arm/mapshort-eabi.d: Check the data section doesn't confuse
+	disassembly.
+	* gas/arm/mapshort-elf.d: Likewise.
 
-2006-04-07  Paul Brook  <paul@codesourcery.com>
+2007-04-19  Paul Brook  <paul@codesourcery.com>
 
-	* gas/arm/thumb2_pool.d: New test.
-	* gas/arm/thumb2_pool.s: New test.
+	* gas/arm/thumb1_unified.d: New test.
+	* gas/arm/thumb1_unified.s: New test.
 
-2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+2007-04-19  Nathan Froyd <froydnj@codesourcery.com>
 
-	* gas/sparc/vxworks-pic.s, gas/sparc/vxworks-pic.d: New test.
-	* gas/sparc/sparc.exp: Run it.  Remove sparc*-*-vxworks* XFAILs.
+	* gas/ppc/booke.s: Add tlbsx, tlbsxe.
+	* gas/ppc/booke.d: Update.
 
-2006-03-23  H.J. Lu  <hongjiu.lu@intel.com>
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
 
-	* gas/i386/rep.s: Pad with .p2align.
-	* gas/i386/rep.d: Adjust.
+	* gas/i386/i386.exp: Add sse4.2 and x86-64-sse4.2.
 
-2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+	* gas/i386/sse4_2.d: New file.
+	* gas/i386/sse4_2.s: Likewise.
+	* gas/i386/x86-64-sse4_2.d: Likewise.
+	* gas/i386/x86-64-sse4_2.s: Likewise.
 
-	* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
-	* gas/mips/vxworks1-xgot.d: New tests.
-	* gas/mips/mips.exp: Run them.  Do not run other tests on VxWorks.
-	
-2006-03-21  Paul Brook  <paul@codesourcery.com>
+2007-04-18  H.J. Lu <hongjiu.lu@intel.com>
 
-	* gas/arm/thumb32.d: Correct expected output.
+	* gas/i386/i386.exp: Add sse4.1 and x86-64-sse4.1.
 
-2006-03-20  Paul Brook  <paul@codesourcery.com>
+	* gas/i386/sse4_1.d: New file.
+	* gas/i386/sse4_1.s: Likewise.
+	* gas/i386/x86-64-sse4_1.d: Likewise.
+	* gas/i386/x86-64-sse4_1.s: Likewise.
 
-	* gas/arm/thumb2_bcond.d: New test.
-	* gas/arm/thumb2_bcond.s: New test.
-	* gas/arm/thumb2_it_bad.d: New test.
-	* gas/arm/thumb2_it_bad.l: New test.
-	* gas/arm/thumb2_it_bad.s: New test.
+2007-04-18  Paul Brook  <paul@codesourcery.com>
 
-2006-03-17  Paul Brook  <paul@codesourcery.com>
+	* gas/arm/thumb2_add.s: Add rsb #0 test.
+	* gas/arm/thumb2_add.d: Update expected output.
 
-	* gas/arm/thumb32.d: Add ldm and stm tests.
-	* gas/arm/thumb32.s: Ditto.
+2007-04-04  Paul Brook  <paul@codesourcery.com>
 
-2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
+	* gas/arm/neon-cov.s: Add new vext test.
+	* gas/arm/neon-cov.d: Ditto.
 
-	* gas/bfin/shift2.s: Add new tests.
-	* gas/bfin/shift.d: Match changed disassembler behaviour.
-	* gas/bfin/parallel2.d: Likewise.
-	* gas/bfin/shift2.d: Likewise; also match new tests.
+2007-04-01  Christian Groessler  <chris@groessler.org>
 
-2006-03-16  Paul Brook  <paul@codesourcery.com>
+	* gas/z8k/calr.d: Fix for 64bit bfd.
+	* gas/z8k/djnz.d: Likewise.
+	* gas/z8k/inout.d: Likewise.
+	* gas/z8k/jmp-cc.d: Likewise.
+	* gas/z8k/jr-back.d: Likewise.
+	* gas/z8k/jr-forw.d: Likewise.
+	* gas/z8k/reglabel.d: Likewise.
+	* gas/z8k/ctrl-names.d: Fix name.  Fix for 64bit bfd.
+	* gas/z8k/ret-cc.d: Likewise.
 
-	* gas/arm/svc.d: New test.
-	* gas/arm/svc.s: New test.
-	* gas/arm/inst.d: Accept svc mnemonic.
-	* gas/arm/thumb.d: Ditto.
-	* gas/arm/wince_inst.d: Ditto.
+2007-03-31  Alan Modra  <amodra@bigpond.net.au>
 
-2006-03-09  Paul Brook  <paul@codesourcery.com>
+	* gas/i386/nops-3.s: Don't use .align.
 
-	* gas/arm/nomapping.d: New test.
-	* gas/arm/nomapping.s: New test.
+2007-03-30  Paul Brook  <paul@codesourcery.com>
 
-2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
+	* gas/arm/thumb2_ldmstm.d: New test.
+	* gas/arm/thumb2_ldmstm.s: New test.
 
-	PR binutils/2428
-	* gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and
-	x86-64-rep-suffix.
+2007-03-27  Alan Modra  <amodra@bigpond.net.au>
 
-	* gas/i386/naked.d: Replace repz with rep.
-	* gas/i386/x86_64.d: Likewise.
+	* gas/ppc/reloc.s: New.
+	* gas/ppc/reloc.d: New.
 
-	* gas/i386/rep-suffix.d: New file. 
-	* gas/i386/rep-suffix.s: Likewise.
-	* gas/i386/rep.d: Likewise.
-	* gas/i386/rep.s: Likewise.
-	* gas/i386/x86-64-rep-suffix.d: Likewise.
-	* gas/i386/x86-64-rep-suffix.s: Likewise.
-	* gas/i386/x86-64-rep.d: Likewise.
-	* gas/i386/x86-64-rep.s: Likewise.
+2007-03-26  Julian Brown  <julian@codesourcery.com>
 
-2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+	* gas/arm/neon-const.s: Use FP syntax for 0/-0.
+	* gas/arm/vfp-neon-syntax-inc.s: Likewise, for 1.
+	* gas/arm/neon-cov.s: Use float syntax for FP immediate.
 
-	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
-	* gas/arm/pic.d: Skip for *-*-vxworks*...
-	* gas/arm/pic_vxworks.d: ...use this version instead.
-	* gas/arm/unwind_vxworks.d: Fix expected output.
+2007-03-24  Paul Brook  <paul@codesourcery.com>
+	Mark Shinwell  <shinwell@codesourcery.com>
 
-2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+	* gas/arm/archv6.s: Add new SRS tests.
+	* gas/arm/archv6.d: Update expected output.
+	* gas/arm/thumb32.s: Add new SRS tests.
+	* gas/arm/thumb32.d: Update expected output.
+	* gas/arm/srs-t2.d: New.
+	* gas/arm/srs-t2.l: New.
+	* gas/arm/srs-t2.s: New.
+	* gas/arm/srs-arm.d: New.
+	* gas/arm/srs-arm.l: New.
+	* gas/arm/srs-arm.s: New.
 
-	* gas/m68k/arch-cpu-1.s: Tweak.
-	* gas/m68k/arch-cpu-1.d: Tweak.
+2007-03-23  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+	* gas/i386/rex.s: Add tests for rex.WRXB.
+	* gas/i386/rex.d: Updated.
 
-	* gas/all/altmacro.s: Adjust.
-	* gas/all/altmac2.s: Adjust.
+	* gas/i386/rex.d: Replace rex64XYZ with rex.WRXB.
+	* gas/i386/x86-64-io-intel.d : Likewise.
+	* gas/i386/x86-64-io-suffix.d: Likewise.
+	* gas/i386/x86-64-io.d: Likewise.
+	* gas/i386/x86-64-opcode.d: Likewise.
 
-2006-02-28  Jan Beulich  <jbeulich@novell.com>
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/macros/paren[sd]: New.
-	* gas/macros/macros.exp: Run new test.
+	PR binutils/4218
+	* gas/i386/nops.s: Add testcases for nop r/m.
+	* gas/i386/x86-64-nops.s: Likewise.
 
-2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+	* gas/i386/x86-64-opcode.s: Add testcases for xchg with %ax,
+	%eax and %rax.
 
-	* gas/i386/i386.exp: Add merom and x86-64-merom.
+	* gas/i386/nops.d: Updated.
+	* gas/i386/x86-64-nops.d: Likewise.
+	* gas/i386/x86-64-opcode.d: Likewise.
 
-	* gas/i386/merom.d: New file.
-	* gas/i386/merom.s: Likewise.
-	* gas/i386/x86-64-merom.d: Likewise.
-	* gas/i386/x86-64-merom.s: Likewise.
+2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 
-2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+	* gas/i386/i386.exp: Run nops-3.
 
-	* gas/sparc/rdhpr.s: New test.
-	* gas/sparc/rdhpr.d: New test.
-	* gas/sparc/wrhpr.s: New test.
-	* gas/sparc/wrhpr.d: New test.
-	* gas/sparc/window.s: New test.
-	* gas/sparc/window.d: New test.
-	* gas/sparc/rdpr.s: Add case for reading %gl register.
-	* gas/sparc/rdpr.d: Likewise.
-	* gas/sparc/wrpr.s: Add case for writing %gl register.
-	* gas/sparc/wrpr.d: Likewise.
-	* gas/sparc/sparc.exp: Update for new tests.
-	
-2006-02-24  Paul Brook  <paul@codesourcery.com>
-
-	* gas/arm/thumb32.d: Fix expected msr and mrs output.
-	* gas/arm/arch7.d: New test.
-	* gas/arm/arch7.s: New test.
-	* gas/arm/arch7m-bad.l: New test.
-	* gas/arm/arch7m-bad.d: New test.
-	* gas/arm/arch7m-bad.s: New test.
-
-2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* gas/ia64/opc-i.s: Add tests for tf.
-	* gas/ia64/pseudo.s: Likewise.
-	* gas/ia64/opc-i.d: Updated.
-	* gas/ia64/pseudo.d: Likewise.
-
-2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
-	* gas/ia64/dv-raw-err.l: Updated.
-
-	* gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1.
-	* gas/ia64/opc-b.d: Updated.
-
-2005-02-22  Paul Brook  <paul@codesourcery.com>
-
-	* gas/arm/thumb32.d: Fix expected pld opcode.
-
-2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
-            Anil Paranjape   <anilp1@kpitcummins.com>
-            Shilin Shakti    <shilins@kpitcummins.com>
-
-	* gas/xc16x: New directory.
-	* gas/xc16x/xc16x.exp: New file
-	* gas/xc16x/add.s: New file
-	* gas/xc16x/add_test.s: New file
-	* gas/xc16x/addb.s: New file
-	* gas/xc16x/addc.s: New file
-	* gas/xc16x/addcb.s: New file   
-	* gas/xc16x/and.s: New file
-	* gas/xc16x/andb.s: New file
-	* gas/xc16x/bfldl.s: New file
-	* gas/xc16x/bit.s: New file
-	* gas/xc16x/calla.s: New file
-	* gas/xc16x/calli.s: New file
-	* gas/xc16x/cmp.s: New file  
-	* gas/xc16x/cmp_test.s: New file
-	* gas/xc16x/cmpb.s: New file
-	* gas/xc16x/cmpi.s: New file
-	* gas/xc16x/cpl.s: New file
-	* gas/xc16x/div.s: New file
-	* gas/xc16x/jmpa.s: New file
-	* gas/xc16x/jmpi.s: New file
-	* gas/xc16x/jmpr.s: New file
-	* gas/xc16x/mov.s: New file
-	* gas/xc16x/mov_test.s: New file 
-	* gas/xc16x/movb.s: New file
-	* gas/xc16x/movbs.s: New file
-	* gas/xc16x/movbz.s: New file  
-	* gas/xc16x/mul.s: New file
-	* gas/xc16x/neg.s: New file
-	* gas/xc16x/nop.s: New file
-	* gas/xc16x/or.s: New file
-	* gas/xc16x/orb.s: New file
-	* gas/xc16x/prior.s: New file
-	* gas/xc16x/pushpop.s: New file
-	* gas/xc16x/ret.s: New file
-	* gas/xc16x/scxt.s: New file
-	* gas/xc16x/shlrol.s: New file
-	* gas/xc16x/sub.s: New file
-	* gas/xc16x/sub_test.s: New file 
-	* gas/xc16x/subb.s: New file
-	* gas/xc16x/subcb.s: New file
-	* gas/xc16x/syscontrol1.s: New file
-	* gas/xc16x/syscontrol2.s: New file
-	* gas/xc16x/trap.s: New file
-	* gas/xc16x/xor.s: New file
-	* gas/xc16x/xorb.s: New file
-
-2006-02-12  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* gas/i386/x86-64-crx-suffix.d: Undo the last change.
-
-2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix".
-
-	* gas/i386/x86-64-crx-suffix.d: Minor update.
-
-	* gas/i386/x86-64-drx-suffix.d: New file.
-	* gas/i386/x86-64-drx.d: Likewise.
-	* gas/i386/x86-64-drx.s: Likewise.
-
-2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".
-
-	* gas/i386/x86-64-crx-suffix.d: New file.
-	* gas/i386/x86-64-crx.d: Likewise.
-	* gas/i386/x86-64-crx.s: Likewise.
-
-2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
-
-	* testsuite/gas/m68k/all.exp: Add arch-cpu-1 test.
-	* testsuite/gas/m68k/arch-cpu-1.[sd]: New.
-
-2005-02-02  Paul Brook  <paul@codesourcery.com>
-
-	* gas/arm/thumb2_invert.d: New test.
-	* gas/arm/thumb2_invert.s: New test.
-
-2006-01-31  Paul Brook  <paul@codesourcery.com>
-
-	* gas/testsuite/gas/arm/iwmmxt-bad.s: Add check for bad register name.
-	* gas/testsuite/gas/arm/iwmmxt-bad.l: Ditto.
-
-2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
-
-	* gas/z80/z80.exp: Add offset.
-	* gas/z80/offset.d: New file.
-	* gas/z80/offset.s: New file.
-
-2006-01-16  Paul Brook  <paul@codesourcery.com>
-
-	* gas/m68k/all.exp: Add mcf-fpu.
-	* gas/m68k/mcf-fpu.d: New file.
-	* gas/m68k/mcf-fpu.s: New file.
-
-2006-01-11  Nick Clifton  <nickc@redhat.com>
-
-	* gas/tic54x/address.d: Work with 64bit hosts.
-	* gas/tic54x/addrfar.d: Likewise.
-	* gas/tic54x/align.d: Likewise.
-	* gas/tic54x/all-opcodes.d: Likewise.
-	* gas/tic54x/asg.d: Likewise.
-	* gas/tic54x/cons.d: Likewise.
-	* gas/tic54x/consfar.d: Likewise.
-	* gas/tic54x/extaddr.d: Likewise.
-	* gas/tic54x/field.d: Likewise.
-	* gas/tic54x/labels.d: Likewise.
-	* gas/tic54x/loop.d: Likewise.
-	* gas/tic54x/lp.d: Likewise.
-	* gas/tic54x/macro.d: Likewise.
-	* gas/tic54x/math.d: Likewise.
-	* gas/tic54x/opcodes.d: Likewise.
-	* gas/tic54x/sections.d: Likewise.
-	* gas/tic54x/set.d: Likewise.
-	* gas/tic54x/struct.d: Likewise.
-	* gas/tic54x/subsym.d: Likewise.
-
-2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
-
-	PR gas/2117
-	* gas/ia64/ia64.exp: Add ltoff22x-2, ltoff22x-3, ltoff22x-4 and
-	ltoff22x-5.
-
-	* gas/ia64/ltoff22x-2.d: New file.
-	* gas/ia64/ltoff22x-2.s: Likewise.
-	* gas/ia64/ltoff22x-3.d: Likewise.
-	* gas/ia64/ltoff22x-3.s: Likewise.
-	* gas/ia64/ltoff22x-4.d: Likewise.
-	* gas/ia64/ltoff22x-4.s: Likewise.
-	* gas/ia64/ltoff22x-5.d: Likewise.
-	* gas/ia64/ltoff22x-5.s: Likewise.
+	* gas/i386/nops-3.d: New file.
+	* gas/i386/nops-3.s: Likewise.
+
+2007-03-20  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* gas/arm/mul-overlap.s: Don't use %type.
+	* gas/arm/mul-overlap.l: Update line numbers.
+	* gas/arm/mul-overlap-v6.s: Don't use %type.
+
+2007-03-18  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* gas/arm/mul-overlap.s: New.
+	* gas/arm/mul-overlap.d: New.
+	* gas/arm/mul-overlap.l: New.
+	* gas/arm/mul-overlap-v6.s: New.
+	* gas/arm/mul-overlap-v6.d: New.
+
+2007-03-14  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/thumbver.d, gas/arm/thumbver.s: New test.
+
+2007-03-14  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_add.d: Add tests using sp.
+	* gas/arm/thumb2_add.s: Ditto.
+
+2007-03-14  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 4029
+	* gas/all/relax.s: New.
+	* gas/all/relax.d: New.
+	* gas/all/gas.exp: Run it.
+
+2007-03-11  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* gas/mmix/comment-1.d, gas/mmix/bspec-1.d, gas/mmix/bspec-2.d:
+	Adjust for change in readelf output.
+
+2007-03-06  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+	* gas/s390/zarch-z9-ec.d: New file.
+	* gas/s390/zarch-z9-ec.s: New file.
+	* gas/s390/s390.exp: Run the z9-ec testcases.
+
+2007-03-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3918
+	* lib/gas-defs.exp (gas_started): New variable. Initialized to
+	0.
+	(gas_start): Set gas_started to 1.
+	(gas_finish): Skip if gas_started is 0.  Reset gas_started to 0.
+
+2007-03-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/relax_branch_align.d: New test.
+	* gas/arm/relax_branch_align.s: New test.
+
+2007-02-28  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3797
+	* gas/lns/lns.exp: Do not run the lns-common test for the d10v
+	port.
+	* gas/d10v/address-002.l: Update expected assembler output.
+	* gas/d10v/address-003.l, gas/d10v/address-004.l,
+	gas/d10v/address-005.l, gas/d10v/address-006.l,
+	gas/d10v/address-007.l, gas/d10v/address-008.l,
+	gas/d10v/address-009.l, gas/d10v/address-010.l,
+	gas/d10v/address-011.l, gas/d10v/address-012.l,
+	gas/d10v/address-013.l, gas/d10v/address-014.l,
+	gas/d10v/address-015.l, gas/d10v/address-016.l,
+	gas/d10v/address-017.l, gas/d10v/address-018.l,
+	gas/d10v/address-019.l, gas/d10v/address-020.l,
+	gas/d10v/address-021.l, gas/d10v/address-022.l,
+	gas/d10v/address-023.l, gas/d10v/address-024.l,
+	gas/d10v/address-025.l, gas/d10v/address-026.l,
+	gas/d10v/address-027.l, gas/d10v/address-030.l,
+	gas/d10v/address-031.l, gas/d10v/address-032.l,
+	gas/d10v/address-033.l, gas/d10v/address-034.l,
+	gas/d10v/address-035.l, gas/d10v/address-036.l,
+	gas/d10v/address-037.l, gas/d10v/address-038.l,
+	gas/d10v/address-039.l, gas/d10v/address-040.l,
+	gas/d10v/address-041.l: Likewise.
+
+2007-02-28  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3975
+	* gas/arm/mapshort.d: Split into two new files...
+	* gas/arm/mapshort-eabi.d: The one and...
+	* gas/arm/mapshort-elf.d: This one.
+	* gas/arm/arch7.d: Remove 32-bit host expectation.
+	* gas/arm/arm7t.d: Replace ".word 0x00000000" with ".*" as some
+	arm targets will disassemble this value as an instruction.
+	* gas/arm/neon-ldst-rm.d: Likewise.
+	* gas/arm/thumb2_pool.d: Only run this test for ELF based arm
+	ports.
+	* gas/arm/thumbrel.d: Only run this test for EABI based arm
+	ports.
+	* gas/arm/wince_inst.d: Fix expected branch targets.
+
+2007-02-22  DJ Delorie  <dj@redhat.com>
+
+	* gas/s390/esa-g5.s: Adjust for corrected PKA syntax.
+	* gas/s390/esa-g5.d: Adjust for corrected PKA syntax.
+
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+            Chao-Ying Fu  <fu@mips.com>
+
+	* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
+	DSP R2.
+	* gas/mips/mips.exp: Run new test.
+
+2007-02-19  Andreas Krebbel  <krebbel1@de.ibm.com>
+
+	* gas/s390/esa-g5.d (cfxbr, cfebr, cfdbr): Exchanged floating
+	point and fixed point operands.
+	* gas/s390/esa-g5.s: Likewise.
+	* gas/s390/zarch-z900.d (cfdr, cfer, cfxr, cgdbr, cgebr, cgxbr,
+	cgdr, cger, cgxr): Likewise.
+	* gas/s390/zarch-z900.s: Likewise.
+
+2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/4027
+	* gas/i386/opcode.s: Add more tests for "test".
+	* i386/opcode-intel.d: Updated.
+	* gas/i386/opcode-suffix.d: Likewise.
+	* gas/i386/opcode.d: Likewise.
+
+2007-02-06  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3810 gas/3800
+	* gas/elf/elf.exp: Expect the redef test to fail on targets which
+	do not convert fixups against ordinary symbols into relocs against
+	section symbols.
+	* gas/all/gas.exp: Likewise.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+
+	* gas/mep/relocs-junk1.s: Add a .data section.
+	* gas/mep/relocs.d: Updated to match above.
+
+2007-02-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3961
+	* gas/i386/secrel.d: Support 64bit host.
+
+2007-02-02  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/3812
+	* gas/v850/v850e1.d: Correct expected disassembly of cmov insn to
+	account for sign extension.
+
+2007-01-11  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_add.d: Add test for missing operand.
+	* gas/arm/thumb2_add.s: Ditto.
+
+2007-01-11  Nick Clifton  <nickc@redhat.com>
+
+	* gas/mcore/allinsn.s: Remove use of '#' before numbers - it is a
+	line comment character.
+	* gas/mcore/allinsn.d: Adjust expected disassembly to match real
+	output.
+
+	* gas/lns/lns.exp: Run the alternative version of the lns-common-1
+	test for the MCore target.
+
+2007-01-08  Kai Tietz	<kai.tietz@onevision.com>
+
+	* gas/all/gas.exp: Renamed target x86_64-*-mingw64 to x86_64-*-mingw*.
+	* gas/i386/i386.exp: Ditto.
+
+2007-01-04  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/archv6.s: Add more cpsie tests.
+	* gas/arm/archv6.d: Ditto.
+
+2007-01-04  Andreas Schwab  <schwab@suse.de>
+
+	* gas/m68k/cpu32.[sd]: New test.
+	* gas/m68k/all.exp: Run it.
+
+2007-01-04  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/neon-omit.d: Fix expected encodings for vshl, vqshl.
 
-2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+2007-01-04  Paul Brook  <paul@codesourcery.com>
 
-	PR gas/2101
-	* gas/mmix/hex2.s, gas/mmix/hex2.d: New test.
+	* gas/arm/neon-cov.d: Adjust expected output.
+	* gas/arm/neon-omit.s: Add tests for vcgt and vcle.  Reorder vacle
+	and vacle.
+	* gas/arm/neon-omit.d: Adjust expected output.
 
-For older changes see ChangeLog-2005
+For older changes see ChangeLog-2006
 
 Local Variables:
 mode: change-log
diff --git a/gas/testsuite/ChangeLog-2006 b/gas/testsuite/ChangeLog-2006
new file mode 100644
index 000000000000..3561fd9ddd61
--- /dev/null
+++ b/gas/testsuite/ChangeLog-2006
@@ -0,0 +1,1094 @@
+2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/intel.s: Add tests for "shrd %cl,%edx,%eax" and
+	"shld %cl,%edx,%eax".
+	* gas/i386/opcode.s: Likewise.
+
+	* gas/i386/intel.d: Updated.
+	* gas/i386/opcode-intel.d: Likewise.
+	* gas/i386/opcode-suffix.d: Likewise.
+	* gas/i386/opcode.d: Likewise.
+
+2006-12-27  Kazu Hirata  <kazu@codesourcery.com>
+
+	* gas/m68k/all.exp: Add support for fido.
+	* gas/m68k/fido.d, gas/m68k/fido.s: New.
+
+2006-12-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/cfi/cfi-common-6.s: Do not use |.
+
+2006-12-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-inval.s: cmpxchg16b needs oword ptr, instead
+	of xmmword ptr.
+	* gas/i386/x86_64.s: Likewise.
+	* gas/i386/x86-64-inval.l: Updated.
+
+2006-12-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-inval.s: Add cmpxchg16b.
+	* gas/i386/x86_64.s: Likewise.
+	* gas/i386/x86-64-inval.l: Updated.
+	* gas/i386/x86_64.d: Likewise.
+
+2006-12-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/3712
+	* gas/i386/inval.s: Add invalid insertq.
+	* gas/i386/x86-64-inval.s: Likewise.
+
+	* gas/i386/inval.l: Updated.
+	* gas/i386/x86-64-inval.l: Likewise.
+
+2006-12-08  Christian Groessler  <chris@groessler.org>
+
+	* gas/z8k/reglabel.d: New test.
+	* gas/z8k/reglabel.s: New test.
+	* gas/z8k/z8k.exp: Run new test.
+
+2006-12-06  H.J. Lu <hjl@gnu.org>
+
+	* gas/i386/amdfam10.d: Updated for operand/address-size override
+	prefix position change.
+	* gas/i386/naked.d: Likewise.
+	* gas/i386/rep-suffix.d: Likewise.
+	* gas/i386/rep.d: Likewise.
+	* gas/i386/white.l: Likewise.
+	* gas/i386/x86-64-amdfam10.d: Likewise.
+	* gas/i386/x86-64-rep-suffix.d: Likewise.
+	* gas/i386/x86-64-rep.d: Likewise.
+	* gas/i386/x86_64.d: Likewise.
+
+2006-12-04  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/opcode-intel.d: Fix wrong expectation. Make white space
+	expectations more consistent.
+
+2006-12-01  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/opcode.d: Adjust name.
+	* gas/i386/opcode-intel.d: New.
+	* gas/i386/opcode-suffix.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2006-12-01  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumbrel.s: New test.
+	* gas/arm/thumbrel.d: New test.
+
+2006-11-30  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intel.d: Adjust.
+	* gas/i386/naked.d: Adjust.
+	* gas/i386/opcode.d: Adjust.
+
+2006-11-30  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/x86-64-io.[sd]: New.
+	* gas/i386/x86-64-io-intel.d: New.
+	* gas/i386/x86-64-io-suffix.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2006-11-30  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intel.s: Use Intel syntax in Intel syntax test.
+	* gas/i386/x86-64-cbw.[sd]: New.
+	* gas/i386/x86-64-cbw-intel.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2006-11-29  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/vfpv3-const-conv.s: Improve test coverage.
+	* gas/arm/vfpv3-const-conv.d: Adjust expected output.
+	* gas/arm/vfp-neon-syntax_t2.d: Ditto.
+	* gas/arm/vfp-neon-syntax.d: Ditto.
+
+2006-11-27  Bob Wilson  <bob.wilson@acm.org>
+
+	* gas/elf/section2.e-xtensa: New file.
+	* gas/elf/elf.exp: Use it.
+
+2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/arm7t.d, gas/arm/neon-ldst-rm.d, gas/arm/thumb2_pool.d,
+	gas/arm/tls.d: Update for $d support.
+	* gas/arm/mapshort.d, gas/arm/mapshort.s: New test.
+	* gas/elf/section2.e-armeabi: Update.
+	* gas/elf/section2.e-armelf: New file.
+	* gas/elf/elf.exp: Use it.
+
+2006-11-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/m68k/all.exp: Add mcf-trap.
+	* gas/m68k/mcf-trap.[sd]: New.
+
+2006-11-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/elf/equ-reloc.[sd]: New.
+	* gas/elf/elf.exp: Run new test.
+
+2006-11-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/merom.d: Use "#pass" instead of "#..." to skip the
+	rest of output.
+	* gas/i386/x86-64-merom.d: Likewise.
+
+2006-11-10  Thiemo Seufer  <ths@mips.com>
+
+	* gas/cfi/cfi.exp: Don't run cfi-common-6 for mips*-*.
+
+2006-11-10  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* gas/arm/undefined.d: Run test on Windows CE.
+	* gas/arm/undefined_coff.d: Don't run test on Windows CE.
+
+	* gas/arm/local_label_coff.s: New test.
+	* gas/arm/local_label_coff.d: New test.
+	* gas/arm/local_label_elf.s: New test.
+	* gas/arm/local_label_elf.d: New test.
+	* gas/arm/local_label_wince.s: New test.
+	* gas/arm/local_label_wince.d: New test.
+
+2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/sse2.s: Test movdqa with memory destination.
+	* gas/i386/sse2.d: Updated.
+
+2006-11-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/sse2.s: Test movdqu with memory destination.
+	* gas/i386/sse2.d: Updated.
+
+2006-11-06  David Daney  <ddaney@avtrex.com>
+
+	* gas/mips/elf-rel26.s: New test.
+	* gas/mips/elf-rel26.d: Ditto.
+	* gas/mips/mips.exp: Run it.
+
+2006-11-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* gas/cfi/cfi-common-6.d: New test.
+	* gas/cfi/cfi-common-6.s: New.
+	* gas/cfi/cfi.exp: Add cfi-common-6 test.
+
+	* gas/cfi/cfi-common-5.d: New test.
+	* gas/cfi/cfi-common-5.s: New.
+	* gas/cfi/cfi.exp: Add cfi-common-5 test.
+
+2006-11-01  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips16-intermix.d, gas/mips/mips16-intermix.s: New
+	testcase.
+	* gas/mips/mips.exp: Run new testcase.
+
+2006-11-01  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* gas/score/rD_rA.d: Correct not! and not.c instruction disassembly.
+	* gas/score/b.d: Correct b! and b instruction disassembly.
+
+2006-10-29  Randolph Chung  <tausq@debian.org>
+
+	* gas/cfi/cfi.exp [hppa*-linux*]: Run hppa CFI test.
+	* gas/cfi/cfi-hppa-1.s: New file.
+	* gas/cfi/cfi-hppa-1.h: New file.
+
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+	* gas/ppc/cell.s: New file.
+	* gas/ppc/cell.d: New file.
+	* gas/ppc/ppc.exp: Test cell.s.
+
+2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+	* gas/i386/amdfam10.d : Modify to support for the change in POPCNT
+	opcode in amdfam10 architecture.
+	* gas/i386/x86-64-amdfam10.d : Ditto.
+
+2006-10-21  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/sh64/syntax-1.d: Update.
+
+2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* gas/sh/pcrel-coff.d: Update patterns (remove 0x on addresses).
+	* gas/sh/pcrel-hms.d: Likewise.
+	* gas/sh/pcrel.d: Likewise.
+	* gas/sh/pcrel2.d: Likewise.
+	* gas/sh/pic.d: Likewise.
+	* gas/sh/tlsd.d: Likewise.
+	* gas/sh/tlsdnopic.d: Likewise.
+	* gas/sh/tlsdpic.d: Likewise.
+
+2006-10-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Indent "x86-64-nops-1".
+
+2006-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/neon-cov.s: Test pseudo-instruction forms of
+	vmov, vmvn and logic immediate instructions.
+	* gas/arm/neon-cov.d: ditto.
+
+2006-09-28  Bridge Wu  <mingqiao.wu@gmail.com>
+
+	* gas/arm/iwmmxt-wldstbh.s: New file.
+	* gas/arm/iwmmxt-wldstbh.d: New file.
+
+2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+            Ian Lance Taylor  <ian@wasabisystems.com>
+            Ben Elliston  <bje@wasabisystems.com>
+
+	* gas/arm/iwmmxt2.s: New file.
+	* gas/arm/iwmmxt2.d: New file.
+
+2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/3235
+	* gas/i386/addr16.d: New file.
+	* gas/i386/addr16.s: Likewise.
+	* gas/i386/addr32.d: Likewise.
+	* gas/i386/addr32.s: Likewise.
+
+	* gas/i386/i386.exp: Add "addr16" and "addr32".
+
+	* gas/i386/x86-64-addr32.s: Add tests for "add32 mov".
+	* gas/i386/x86-64-addr32.d: Updated.
+
+2006-09-20  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* gas/all/gas.exp: Add support for x86_64-*-mingw64.
+	* gas/i386/immed64.d: Add #pass for avoid proplems with alignment paddings.
+	* gas/i386/rex.d: Changed for x86_64-mingw32 target matching and padding.
+	* gas/i386/i386.d: Likewise.
+	* gas/i386/x86-64-addr32.d: Likewise.
+	* gas/i386/x86-64-branch.d: Likewise.
+	* gas/i386/x86-64-crx-suffix.d: Likewise.
+	* gas/i386/x86-64-crx.d: Likewise.
+	* gas/i386/x86-64-drx-suffix.d: Likewise.
+	* gas/i386/x86-64-crx-suffix.d: Likewise.
+	* gas/i386/x86-64-opcode.d: Likewise.
+	* gas/i386/x86-64-pcrel.d: Likewise.
+
+2006-09-19  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* gas/bfin/load.s, gas/bfin/load.d: Add constant folding tests.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* gas/score: New directory.
+	* gas/elf/section2.e-score: New file.
+	* gas/elf/elf.exp: Add special case for Score target.
+
+2006-09-16  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/unwind.s: Test two argument form of .movsp.
+	* gas/arm/unwind.d: Update expected output.
+	* gas/arm/unwind_vxworks.d: Ditto.
+
+2006-09-08  Kazu Hirata  <kazu@codesourcery.com>
+
+	* lib/gas-dg.exp (gas-dg-test): Treat $dir as a literal.
+
+2006-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arm-it.s: New test.
+	* gas/arm/arm-it.d: New test.
+
+2006-09-07  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/neon-omit.s: Test three-argument variants.
+	* gas/arm/neon-omit.d: Update expected output.
+
+2006-09-04  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes.
+	* gas/arm/neon-cov.d: Adjust expected output.
+
+2006-08-21  Joseph Myers  <joseph@codesourcery.com>
+
+	* gas/arm/unwind.s: Test not merging iWMMXt register save with
+	previous long opcode.
+	* gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Update.
+
+2006-08-16  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/noarm.s: Add test for disabled ARM insns.
+	* gas/arm/noarm.d: Drive test for above.
+	* gas/arm/noarm.l: Expected error output.
+
+2006-08-15  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* gas/mips/mips.exp: Handle mips*-sde-elf*.
+
+2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+	* sse2.d: Fixed the correct result for cvtpi2pd, cvtpd2pi 
+	and cvttpd2pi.
+
+2006-08-12  Thiemo Seufer  <ths@networkno.de>
+
+	* gas/mips/mips16-save.d: Fix testcase.
+
+2006-08-08  Bob Wilson  <bob.wilson@acm.org>
+
+	* gas/lns/lns-common-1-alt.d: New file.
+	* gas/lns/lns.exp: Use lns-common-1-alt.d for xtensa targets.
+
+2006-08-04 Pedro Alves <pedro_alves@portugalmail.pt>
+
+	* gas/arm/wince.s: New test.
+	* gas/arm/wince.d: New test.
+
+	* gas/arm/thumb2_add.s: Don't use elf specific ".type"
+	pseudo-op.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* gas/arm/iwmmxt-bad.s: Test invalid register names for wldrw and
+	wstrw.
+	* gas/arm/iwmmxt-bad.l: Update.
+
+2006-08-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
+	* gas/arm/iwmmxt.d: Update.
+
+2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/nops-2-i386.d: Updated.
+	* gas/i386/nops-2-merom.d: Likewise.
+	* gas/i386/nops-2.d: Likewise.
+
+2006-07-29  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/m68k/mcf-fpu.s: Add tests for all addressing modes.
+	* gas/m68k/mcf-fpu.d: Update accordingly.
+
+2006-07-20 Dwarakanath Rajagopal	<dwarak.rajagopal@amd.com>
+	   Michael Meissner		<michael.meissner@amd.com>
+
+	* gas/i386/amdfam10.s: Add .p2align 4,0 to make sure segment is
+	aligned on all systems.
+	* gas/i386/x86-64-amdfam10.s: Likewise.
+	* gas/i386/amdfam10.d: Adjust output for alignment.
+	* gas/i386/x86-64-amdfam10.d: Likewise.
+
+2006-07-19  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/archv6t2.d: Adjust expected output for rbit.
+
+2006-07-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/opcode.s: Add sldt, smsw and str.
+	* gas/i386/x86-64-opcode.s: Likewise.
+
+	* gas/i386/opcode.d: Updated.
+	* gas/i386/x86-64-opcode.d: Likewise.
+
+2006-07-18  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_add.d: New test.
+	* gas/arm/thumb2_add.s: New test.
+
+2006-07-18  Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/mips4.s, gas/mips/mips4.d: Enable the "pref" test.  Change
+	arguments for "madd.s" so that the instruction is correct for mips1
+	and still matches "bc3*".
+
+2006-07-13 Dwarakanath Rajagopal	<dwarak.rajagopal@amd.com>
+	   Michael Meissner		<michael.meissner@amd.com>
+
+	* gas/i386/amdfam10.s: New file for amdfam10 instructions.
+	* gam/i386/amdfam10.d: Ditto.
+	* gas/i386/x86-64-amdfam10.s: Ditto.
+	* gam/i386/x86-64-amdfam10.d: Ditto.
+
+2006-07-12  Nick Clifton  <nickc@redhat.com>
+
+	* gas/sh/basic.exp: Run "too_large" dump test.
+	* gas/sh/too_large.s: New test file.  Check that .byte directives
+	do not generate a bogus overflow message.
+	* gas/sh/too_large.s: New test control file.
+
+2006-07-05  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/vfp-neon-syntax.d: Tweak expected fmsrr syntax.
+	* gas/arm/vfp-neon-syntax_t2.d: Likewise.
+	* gas/arm/vfp2.d: Likewise.
+	* gas/arm/vfp2_t2.d: Likewise.
+
+2006-07-04  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/e32-rel2.d, gas/mips/e32-rel4.d: Use -mabi=32 for as.
+	* gas/mips/mips.exp: Move mips16e testcase to ELF only tests.
+	Run elf{el}-rel2 and elf-rel4 for all arches with gpr64. Run
+	e32-rel2 and e32-rel4 also for 64 bit configurations.
+
+2006-06-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Run nops-1, nops-1-i386, nops-1-i686,
+	nops-1-merom, nops-2, nops-2-i386, nops-2-merom, x86-64-nops-1,
+	x86-64-nops-1-k8, x86-64-nops-1-nocona and x86-64-nops-1-merom.
+
+	* gas/i386/nops-1.s: New file.
+	* gas/i386/nops-2.s: Likewise.
+	* gas/i386/nops-1-i386.d: Likewise.
+	* gas/i386/nops-1-i686.d: Likewise.
+	* gas/i386/nops-1-merom.d: Likewise.
+	* gas/i386/nops-1.d: Likewise.
+	* gas/i386/nops-2-i386.d: Likewise.
+	* gas/i386/nops-2-merom.d: Likewise.
+	* gas/i386/nops-2.d: Likewise.
+	* gas/i386/x86-64-nops-1.s: Likewise.
+	* gas/i386/x86-64-nops-1-k8.d: Likewise.
+	* gas/i386/x86-64-nops-1-merom.d: Likewise.
+	* gas/i386/x86-64-nops-1-nocona.d: Likewise.
+	* gas/i386/x86-64-nops-1.d: Likewise.
+
+	* gas/i386/sse2.d: Updated to expect xchg %ax,%ax as 2 byte
+	nop.
+
+2006-06-20  Thiemo Seufer  <ths@networkno.de>
+
+	* gas/mips/mips.exp: Explicitly specify o32 ABI.
+	* gas/mips/mips64-dsp.d: Dump o32 register names.
+	* gas/mips/smartmips.d: Explicitly specify o32 ABI.
+
+2006-06-18  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/group-reloc-alu-encoding-bad.d: Skip for non-ELF
+	targets.
+	* gas/arm/group-reloc-alu-parsing-bad.d: Likewise.
+	* gas/arm/group-reloc-ldc-encoding-bad.d: Likewise.
+	* gas/arm/group-reloc-ldc-parsing-bad.d: Likewise.
+	* gas/arm/group-reloc-ldc.d: Likewise.
+	* gas/arm/group-reloc-ldr-encoding-bad.d: Likewise.
+	* gas/arm/group-reloc-ldr-parsing-bad.d: Likewise.
+	* gas/arm/group-reloc-ldr.d: Likewise.
+	* gas/arm/group-reloc-ldrs-encoding-bad.d: Likewise.
+	* gas/arm/group-reloc-ldrs-parsing-bad.d: Likewise.
+	* gas/arm/group-reloc-ldrs.d: Likewise.
+	
+2006-06-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* gas/arm/group-reloc-alu.d: New test.
+	* gas/arm/group-reloc-alu-encoding-bad.d: New test.
+	* gas/arm/group-reloc-alu-encoding-bad.l: New test.
+	* gas/arm/group-reloc-alu-encoding-bad.s: New test.
+	* gas/arm/group-reloc-alu-parsing-bad.d: New test.
+	* gas/arm/group-reloc-alu-parsing-bad.l: New test.
+	* gas/arm/group-reloc-alu-parsing-bad.s: New test.
+	* gas/arm/group-reloc-alu.s: New test.
+	* gas/arm/group-reloc-ldc.d: New test.
+	* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
+	* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
+	* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
+	* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
+	* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
+	* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
+	* gas/arm/group-reloc-ldc.s: New test.
+	* gas/arm/group-reloc-ldr.d: New test.
+	* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
+	* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
+	* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
+	* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
+	* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
+	* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
+	* gas/arm/group-reloc-ldr.s: New test.
+	* gas/arm/group-reloc-ldrs.d: New test.
+	* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
+	* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
+	* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
+	* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
+	* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
+	* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
+	* gas/arm/group-reloc-ldrs.s: New test.
+
+2006-06-14  Thiemo Seufer  <ths@mips.com>
+            Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/elf-rel6.d, gas/mips/elf-rel6.s: Extend testcase.
+	* gas/mips/elf-rel6.d-n32.d, gas/mips/elf-rel6-n64.d: New files.
+	* gas/mips/mips.exp: Run new testcases.
+
+2006-06-14  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips16e-jrc.d, gas/mips/mips16e-save.d,
+	gas/mips/mips32-dsp.d, gas/mips/mips32-mt.d: Explicitly specify
+	o32 ABI.
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Run nops and x86-64-nops.
+
+	* gas/i386/nops.d: New file.
+	* gas/i386/nops.s: Likewise.
+	* gas/i386/x86-64-nops.d: Likewise.
+	* gas/i386/x86-64-nops.s: Likewise.
+
+2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/opcode.s: Add "xchg %ax,%ax".
+	* gas/i386/opcode.d: Updated.
+
+	* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
+	xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
+	* gas/i386/x86-64-opcode.d: Updated.
+
+2006-06-09  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips32-sf32.s, gas/mips/mips32-sf32.d: New test for odd
+	single precision FPRs on MIPS32.
+	* gas/mips/mips.exp: Run them.
+
+2006-06-08  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips32.s: Added cop2 branches with explicit condition
+	code register numbers.
+	* gas/mips/mips32.d: Likewise.
+
+2006-06-07  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/itblock.s: New file. Helper macro for making all-true IT
+	blocks.
+	* gas/arm/neon-cond-bad-inc.s: New test. Make sure unconditional
+	Neon instructions are rejected...
+	* gas/arm/neon-cond-bad.s: In ARM mode, and...
+	* gas/arm/neon-cond-bad_t2.s: Accepted in Thumb mode (with IT).
+	* gas/arm/neon-cond-bad.l: Expected error output in ARM mode.
+	* gas/arm/neon-cond-bad.d: Control ARM mode test.
+	* gas/arm/neon-cond-bad_t2.d: Expected output in Thumb mode.
+	* gas/arm/vfp-neon-syntax-inc.s: Test VFP Neon-style syntax.
+	* gas/arm/vfp-neon-syntax.s: ...in ARM mode.
+	* gas/arm/vfp-neon-syntax_t2.s: ...and Thumb mode.
+	* gas/arm/vfp-neon-syntax.d: Expected output in ARM mode.
+	* gas/arm/vfp-neon-syntax_t2.d: Expected output in Thumb mode.
+
+2006-06-06  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_bcond.d: Update expected output.
+	* gas/arm/thumb32.d: Ditto.
+	* gas/arm/vfp1_t2.d: Ditto.
+	* gas/arm/vfp1xD_t2.d: Ditto.
+
+2006-06-06  Thiemo Seufer  <ths@mips.com>
+            Chao-ying Fu  <fu@mips.com>
+
+	* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
+	* gas/mips/mips.exp: Run DSP64 tests.
+
+2006-06-05  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips32-dsp.d, gas/mips/mips32-dsp.s, gas/mips/mips32-mt.d,
+	gas/mips/mips32-mt.s: Remove instructions with invalid arguments.
+	* gas/mips/mips32-dsp.l, gas/mips/mips32-mt.l: Delete file.
+
+2006-05-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
+	* gas/m68k/mcf-fpu.d: Adjust accordingly.
+
+2006-05-25  Jie Zhang  <jie.zhang@analog.com>
+	
+	* gas/bfin/vector2.s, gas/bfin/vector2.d: Test to ensure (m) is not
+	thrown away.
+
+2006-05-23  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips-gp32-fp64-pic.d, mips/mips-gp32-fp64.d,
+	gas/mips/mips-gp64-fp32-pic.d, gas/mips/mips-gp64-fp32.l,
+	gas/mips/mips-gp64-fp64.d: Adjust test cases to the changes assembler
+	output.
+	* gas/mips/mips-gp32-fp64.l, gas/mips/mips-gp64-fp32-pic.l: New files,
+	catch assembler warnings.
+
+2006-05-22  Nick Clifton  <nickc@redhat.com>
+
+	* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in
+	warning messages.
+	* gas/mips/mips32-mt.l: Likewise.
+
+2006-05-19  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add little
+	endian testcases.
+	* gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian.
+	* gas/mips/mips.exp: Run new testcases.
+
+2006-05-14  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips.exp: Run new tests.
+	* gas/mips/mips16e.s, gas/mips/mips16e.d, gas/mips/mips16e-64.s,
+	gas/mips/mips16e-64.d, gas/mips/mips16e-64.l: New tests.
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/local_function.d: New test.
+	* gas/arm/local_function.s: New test.
+
+2006-05-11  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/jal-range.l: Don't check the range of j or jal
+	addresses.
+
+2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-gidt.d: Adjusted.
+
+2006-05-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Run x86-64-gidt.
+
+	* gas/i386/x86-64-gidt.d: New file.
+	* gas/i386/x86-64-gidt.s: Likewise.
+
+2006-05-09  David Ung  <davidu@mips.com>
+
+	* gas/mips/jal-range.l: Only warn about an out-of-range j or jal
+	address.
+
+2006-05-08  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips32.s, gas/mips/mips32.d: Extend testcase to check
+	larger offset arguments for cache instructions.
+
+2006-05-08  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+            David Ung  <davidu@mips.com>
+
+	* gas/mips/smartmips.s, gas/mips/smartmips.d: New smartmips test.
+	* gas/mips/mips.exp: Run smartmips test.
+
+2006-05-05  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/vfp-neon-overlap.s: New test. Overlapping VFP/Neon
+	instructions.
+	* gas/arm/vfp-neon-overlap.d: Expected output of above.
+	* gas/arm/vfp1xD.d: Test for fldmx/fstmx.
+	* gas/arm/vfp1xD_t2.d: Likewise.
+	* gas/arm/vfpv3-32drs.d: Likewise.
+
+2006-05-05  Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/noreorder.s, gas/mips/noreorder.d: New test for
+	reorder/noreorder corner case.
+	* gas/mips/mips.exp: Run new test.
+	
+2006-05-04  Kazu Hirata  <kazu@codesourcery.com>
+
+	* gas/arm/armv1.d (error-output): New.
+	* gas/arm/armv1.l: New.
+	* gas/arm/thumb32.d (error-output): New.
+	* gas/arm/thumb32.l: New.
+
+2006-05-04  Thiemo Seufer  <ths@mips.com>
+            Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
+	* gas/mips/set-arch.d: Adjust according to opcode table changes.
+
+2006-05-03  Thiemo Seufer  <ths@mips.com>
+
+	* gas/mips/mips32-mt.d: Fix mftr argument order.
+
+2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh.
+	* gas/arm/iwmmxt.d: Update expected results.
+	* gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh.
+	* gas/arm/iwmmxt-bad2.l: Update expected error messages.
+
+2006-04-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/fp.d: New file.
+	* gas/i386/fp.s: Likewise.
+
+	* gas/i386/i386.exp: Run "fp".
+
+2006-04-28  Thiemo Seufer  <ths@mips.com>
+            David Ung  <davidu@mips.com>
+	    Nigel Stephens  <nigel@mips.com>
+
+	* gas/mips/cp0sel-names-mips32r2.d,
+	gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/neon-const.s: New testcase. Neon floating-point constants.
+	* gas/arm/neon-const.d: Expected output of above.
+	* gas/arm/neon-cov.d: Expect floating-point disassembly for VMOV.F32.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/neon-psyn.s: Basic test of programmers syntax.
+	* gas/arm/neon-psyn.d: Expected output of above.
+
+2006-04-26  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction.
+	* gas/arm/copro.d: Update accordingly.
+	* gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode.
+	* gas/arm/neon-cond.d: Expected results of above.
+	* gas/arm/neon-cov.s: New test. Coverage of Neon instructions.
+	* gas/arm/neon-cov.d: Expected results of above.
+	* gas/arm/neon-ldst-es.s: New test. Element and structure loads and
+	stores.
+	* gas/arm/neon-ldst-es.d: Expected results of above.
+	* gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads
+	and stores.
+	* gas/arm/neon-ldst-rm.d: Expected results of above.
+	* gas/arm/neon-omit.s: New test. Omission of optional operands.
+	* gas/arm/neon-omit.d: Expected results of above.
+	* gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions.
+	* gas/arm/vfp1_t2.d: Likewise.
+	* gas/arm/vfp1xD.d: Likewise.
+	* gas/arm/vfp1xD_t2.d: Likewise.
+	* gas/arm/vfp2.d: Likewise.
+	* gas/arm/vfp2_t2.d: Likewise.
+	* gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP
+	instructions.
+	* gas/arm/vfp3-32drs.d: Expected results of above.
+	* gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and
+	conversion instructions.
+	* gas/arm/vfp3-const-conv.d: Expected results of above.
+
+2005-04-20  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arch7.d: Remove skip.
+	* gas/arm/svc.d: Ditto.
+	* gas/arm/thumb2_bcond.d: Ditto.
+	* gas/arm/thumb2_it_bad.d: Ditto.
+
+2006-04-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2533
+	* gas/i386/inval.s: Add test for illegal immediate register
+	operand.
+	* gas/i386/inval.l: Updated.
+
+2006-04-16  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/arch7.d: Skip test for non-ELF targets.
+	* gas/arm/blx-local.d: Likewise.
+	* gas/arm/svc.d: Likewise.
+	* gas/arm/thumb2_bcond.d: Likewise.
+	* gas/arm/thumb2_it_bad.d: Likewise.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/blx-local.d: New test.
+	* gas/arm/blx-local.d: New test.
+
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_pool.d: New test.
+	* gas/arm/thumb2_pool.s: New test.
+
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/sparc/vxworks-pic.s, gas/sparc/vxworks-pic.d: New test.
+	* gas/sparc/sparc.exp: Run it.  Remove sparc*-*-vxworks* XFAILs.
+
+2006-03-23  Michael Matz  <matz@suse.de>
+
+	* gas/i386/reloc64.s: Accept 64-bit forms.
+	* gas/i386/reloc64.d: Adjust.
+	* gas/i386/reloc64.l: Adjust.
+
+2006-03-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/rep.s: Pad with .p2align.
+	* gas/i386/rep.d: Adjust.
+
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
+	* gas/mips/vxworks1-xgot.d: New tests.
+	* gas/mips/mips.exp: Run them.  Do not run other tests on VxWorks.
+	
+2006-03-21  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Correct expected output.
+
+2006-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_bcond.d: New test.
+	* gas/arm/thumb2_bcond.s: New test.
+	* gas/arm/thumb2_it_bad.d: New test.
+	* gas/arm/thumb2_it_bad.l: New test.
+	* gas/arm/thumb2_it_bad.s: New test.
+
+2006-03-17  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Add ldm and stm tests.
+	* gas/arm/thumb32.s: Ditto.
+
+2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* gas/bfin/shift2.s: Add new tests.
+	* gas/bfin/shift.d: Match changed disassembler behaviour.
+	* gas/bfin/parallel2.d: Likewise.
+	* gas/bfin/shift2.d: Likewise; also match new tests.
+
+2006-03-16  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/svc.d: New test.
+	* gas/arm/svc.s: New test.
+	* gas/arm/inst.d: Accept svc mnemonic.
+	* gas/arm/thumb.d: Ditto.
+	* gas/arm/wince_inst.d: Ditto.
+
+2006-03-09  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/nomapping.d: New test.
+	* gas/arm/nomapping.s: New test.
+
+2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/2428
+	* gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and
+	x86-64-rep-suffix.
+
+	* gas/i386/naked.d: Replace repz with rep.
+	* gas/i386/x86_64.d: Likewise.
+
+	* gas/i386/rep-suffix.d: New file. 
+	* gas/i386/rep-suffix.s: Likewise.
+	* gas/i386/rep.d: Likewise.
+	* gas/i386/rep.s: Likewise.
+	* gas/i386/x86-64-rep-suffix.d: Likewise.
+	* gas/i386/x86-64-rep-suffix.s: Likewise.
+	* gas/i386/x86-64-rep.d: Likewise.
+	* gas/i386/x86-64-rep.s: Likewise.
+
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
+	* gas/arm/pic.d: Skip for *-*-vxworks*...
+	* gas/arm/pic_vxworks.d: ...use this version instead.
+	* gas/arm/unwind_vxworks.d: Fix expected output.
+
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/m68k/arch-cpu-1.s: Tweak.
+	* gas/m68k/arch-cpu-1.d: Tweak.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/altmacro.s: Adjust.
+	* gas/all/altmac2.s: Adjust.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/paren[sd]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add merom and x86-64-merom.
+
+	* gas/i386/merom.d: New file.
+	* gas/i386/merom.s: Likewise.
+	* gas/i386/x86-64-merom.d: Likewise.
+	* gas/i386/x86-64-merom.s: Likewise.
+
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+	* gas/sparc/rdhpr.s: New test.
+	* gas/sparc/rdhpr.d: New test.
+	* gas/sparc/wrhpr.s: New test.
+	* gas/sparc/wrhpr.d: New test.
+	* gas/sparc/window.s: New test.
+	* gas/sparc/window.d: New test.
+	* gas/sparc/rdpr.s: Add case for reading %gl register.
+	* gas/sparc/rdpr.d: Likewise.
+	* gas/sparc/wrpr.s: Add case for writing %gl register.
+	* gas/sparc/wrpr.d: Likewise.
+	* gas/sparc/sparc.exp: Update for new tests.
+	
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Fix expected msr and mrs output.
+	* gas/arm/arch7.d: New test.
+	* gas/arm/arch7.s: New test.
+	* gas/arm/arch7m-bad.l: New test.
+	* gas/arm/arch7m-bad.d: New test.
+	* gas/arm/arch7m-bad.s: New test.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/opc-i.s: Add tests for tf.
+	* gas/ia64/pseudo.s: Likewise.
+	* gas/ia64/opc-i.d: Updated.
+	* gas/ia64/pseudo.d: Likewise.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
+	* gas/ia64/dv-raw-err.l: Updated.
+
+	* gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1.
+	* gas/ia64/opc-b.d: Updated.
+
+2005-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Fix expected pld opcode.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* gas/xc16x: New directory.
+	* gas/xc16x/xc16x.exp: New file
+	* gas/xc16x/add.s: New file
+	* gas/xc16x/add_test.s: New file
+	* gas/xc16x/addb.s: New file
+	* gas/xc16x/addc.s: New file
+	* gas/xc16x/addcb.s: New file   
+	* gas/xc16x/and.s: New file
+	* gas/xc16x/andb.s: New file
+	* gas/xc16x/bfldl.s: New file
+	* gas/xc16x/bit.s: New file
+	* gas/xc16x/calla.s: New file
+	* gas/xc16x/calli.s: New file
+	* gas/xc16x/cmp.s: New file  
+	* gas/xc16x/cmp_test.s: New file
+	* gas/xc16x/cmpb.s: New file
+	* gas/xc16x/cmpi.s: New file
+	* gas/xc16x/cpl.s: New file
+	* gas/xc16x/div.s: New file
+	* gas/xc16x/jmpa.s: New file
+	* gas/xc16x/jmpi.s: New file
+	* gas/xc16x/jmpr.s: New file
+	* gas/xc16x/mov.s: New file
+	* gas/xc16x/mov_test.s: New file 
+	* gas/xc16x/movb.s: New file
+	* gas/xc16x/movbs.s: New file
+	* gas/xc16x/movbz.s: New file  
+	* gas/xc16x/mul.s: New file
+	* gas/xc16x/neg.s: New file
+	* gas/xc16x/nop.s: New file
+	* gas/xc16x/or.s: New file
+	* gas/xc16x/orb.s: New file
+	* gas/xc16x/prior.s: New file
+	* gas/xc16x/pushpop.s: New file
+	* gas/xc16x/ret.s: New file
+	* gas/xc16x/scxt.s: New file
+	* gas/xc16x/shlrol.s: New file
+	* gas/xc16x/sub.s: New file
+	* gas/xc16x/sub_test.s: New file 
+	* gas/xc16x/subb.s: New file
+	* gas/xc16x/subcb.s: New file
+	* gas/xc16x/syscontrol1.s: New file
+	* gas/xc16x/syscontrol2.s: New file
+	* gas/xc16x/trap.s: New file
+	* gas/xc16x/xor.s: New file
+	* gas/xc16x/xorb.s: New file
+
+2006-02-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-crx-suffix.d: Undo the last change.
+
+2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix".
+
+	* gas/i386/x86-64-crx-suffix.d: Minor update.
+
+	* gas/i386/x86-64-drx-suffix.d: New file.
+	* gas/i386/x86-64-drx.d: Likewise.
+	* gas/i386/x86-64-drx.s: Likewise.
+
+2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".
+
+	* gas/i386/x86-64-crx-suffix.d: New file.
+	* gas/i386/x86-64-crx.d: Likewise.
+	* gas/i386/x86-64-crx.s: Likewise.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/m68k/all.exp: Add arch-cpu-1 test.
+	* gas/m68k/arch-cpu-1.[sd]: New.
+
+2005-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_invert.d: New test.
+	* gas/arm/thumb2_invert.s: New test.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/iwmmxt-bad.s: Add check for bad register name.
+	* gas/arm/iwmmxt-bad.l: Ditto.
+
+2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
+
+	* gas/z80/z80.exp: Add offset.
+	* gas/z80/offset.d: New file.
+	* gas/z80/offset.s: New file.
+
+2006-01-16  Paul Brook  <paul@codesourcery.com>
+
+	* gas/m68k/all.exp: Add mcf-fpu.
+	* gas/m68k/mcf-fpu.d: New file.
+	* gas/m68k/mcf-fpu.s: New file.
+
+2006-01-11  Nick Clifton  <nickc@redhat.com>
+
+	* gas/tic54x/address.d: Work with 64bit hosts.
+	* gas/tic54x/addrfar.d: Likewise.
+	* gas/tic54x/align.d: Likewise.
+	* gas/tic54x/all-opcodes.d: Likewise.
+	* gas/tic54x/asg.d: Likewise.
+	* gas/tic54x/cons.d: Likewise.
+	* gas/tic54x/consfar.d: Likewise.
+	* gas/tic54x/extaddr.d: Likewise.
+	* gas/tic54x/field.d: Likewise.
+	* gas/tic54x/labels.d: Likewise.
+	* gas/tic54x/loop.d: Likewise.
+	* gas/tic54x/lp.d: Likewise.
+	* gas/tic54x/macro.d: Likewise.
+	* gas/tic54x/math.d: Likewise.
+	* gas/tic54x/opcodes.d: Likewise.
+	* gas/tic54x/sections.d: Likewise.
+	* gas/tic54x/set.d: Likewise.
+	* gas/tic54x/struct.d: Likewise.
+	* gas/tic54x/subsym.d: Likewise.
+
+2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2117
+	* gas/ia64/ia64.exp: Add ltoff22x-2, ltoff22x-3, ltoff22x-4 and
+	ltoff22x-5.
+
+	* gas/ia64/ltoff22x-2.d: New file.
+	* gas/ia64/ltoff22x-2.s: Likewise.
+	* gas/ia64/ltoff22x-3.d: Likewise.
+	* gas/ia64/ltoff22x-3.s: Likewise.
+	* gas/ia64/ltoff22x-4.d: Likewise.
+	* gas/ia64/ltoff22x-4.s: Likewise.
+	* gas/ia64/ltoff22x-5.d: Likewise.
+	* gas/ia64/ltoff22x-5.s: Likewise.
+
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR gas/2101
+	* gas/mmix/hex2.s, gas/mmix/hex2.d: New test.
+
+For older changes see ChangeLog-2005
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index 928dd88348e2..cb8c6777a432 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -16,7 +16,10 @@ gas_test "p2425.s" ""   "" "pcrel values in assignment"
 # The ".space" directive is taken care of in the C54x-specific tests, so fail
 #  here 
 #
-if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] } then {
+# The test also doesn't work on mep targets, since they use RELC, and it
+# will avoid simplifying the expression since it conservatively assumes
+# ugly expressions can be saved until link-time.
+if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] || [istarget mep*-*-*]} then {
     setup_xfail *-*-*
     fail "simplifiable double subtraction"
 } else {
@@ -80,13 +83,18 @@ case $target_triplet in {
     default {
 	setup_xfail "*c30*-*-*" "*c4x*-*-*" "pdp11-*-*"
 	run_dump_test redef
+	# The next two tests can fail if the target does not convert fixups
+	# against ordinary symbols into relocations against section symbols.
+	# This is usually revealed by the error message:
+	#  symbol `sym' required but not present
 	setup_xfail "*c30*-*-*" "*c4x*-*-*" "*arm*-*-*aout*" "*arm*-*-*coff" \
 	    "*arm*-*-pe" "crx*-*-*" "h8300*-*-*" "m68hc*-*-*" "maxq-*-*" \
-	    "pdp11-*-*" "vax*-*-*" "z8k-*-*"
+	    "mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*" "cr16-*-*"
 	run_dump_test redef2
 	setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \
 	    "bfin-*-*" "*c4x*-*-*" "crx*-*-*" "h8300*-*-*" "hppa*-*-hpux*" \
-	    "m68hc*-*-*" "maxq-*-*" "or32-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*"
+	    "m68hc*-*-*" "maxq-*-*" "mn10300-*-*" "or32-*-*" "pdp11-*-*" \
+	    "vax*-*-*" "z8k-*-*" "cr16-*-*"
 	run_dump_test redef3
 	setup_xfail "*c4x*-*-*"
 	gas_test_error "redef4.s" "" ".set for symbol already used as label"
@@ -207,6 +215,7 @@ if {   ([istarget *-*-coff*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-
      || [istarget i*86-*-isc*] \
      || [istarget i*86-*-go32*] \
      || [istarget i*86-*-cygwin*] \
+     || [istarget x86_64-*-mingw*] \
      || [istarget i*86-*-*nt] \
      || [istarget i*86-*-interix*] \
      || ([istarget i960-*-vxworks5.*] && ![istarget i960-*-vxworks5.0*]) } {
@@ -256,6 +265,11 @@ if {  ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \
 run_dump_test assign
 run_dump_test sleb128
 
+# .byte is 32 bits on tic4x, and .p2align isn't supported on tic54x
+if { ![istarget "tic4x*-*-*"] && ![istarget "tic54x*-*-*"] } {
+    run_dump_test relax
+}
+
 # .quad is 16 bytes on i960.
 if { ![istarget "i960-*-*"] } {
     run_dump_test quad
diff --git a/gas/testsuite/gas/all/relax.d b/gas/testsuite/gas/all/relax.d
new file mode 100644
index 000000000000..1e581c2695b0
--- /dev/null
+++ b/gas/testsuite/gas/all/relax.d
@@ -0,0 +1,13 @@
+#objdump : -s -j .data -j "\$DATA\$"
+#name : relax .uleb128
+
+.*: .*
+
+Contents of section .*
+ 0000 01020381 01000000 00000000 00000000.*
+#...
+ 0080 00000004 ffff0500 06078380 01000000.*
+#...
+ 4080 00000000 00000000 00000008 ffffffff.*
+ 4090 09090909 09090909 09090909 09090909.*
+#pass
diff --git a/gas/testsuite/gas/all/relax.s b/gas/testsuite/gas/all/relax.s
new file mode 100644
index 000000000000..104a8956bd6a
--- /dev/null
+++ b/gas/testsuite/gas/all/relax.s
@@ -0,0 +1,20 @@
+ .data
+ .byte 1, 2, 3
+ .uleb128 L2 - L1
+L1:
+ .space 128 - 2
+ .byte 4
+ .p2align 1, 0xff
+L2:
+ .byte 5
+
+ .p2align 2
+ .byte 6, 7
+ .uleb128 L4 - L3
+L3:
+ .space 128*128 - 2
+ .byte 8
+ .p2align 2, 0xff
+L4:
+ .byte 9
+ .p2align 4, 9
diff --git a/gas/testsuite/gas/alpha/alpha.exp b/gas/testsuite/gas/alpha/alpha.exp
index da785ae04043..04d99329dd7a 100644
--- a/gas/testsuite/gas/alpha/alpha.exp
+++ b/gas/testsuite/gas/alpha/alpha.exp
@@ -2,19 +2,6 @@
 # Some generic alpha tests
 #
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "alpha $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 if { [istarget alpha*-*-*] } then {
 
     set elf [expr [istarget *-*-elf*] \
diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d
index 0fdaa8fdecbe..f7e343f03bc1 100644
--- a/gas/testsuite/gas/arm/arch4t.d
+++ b/gas/testsuite/gas/arm/arch4t.d
@@ -11,14 +11,14 @@ Disassembly of section .text:
 0+0c <[^>]+> e1d540f0 ?	ldrsh	r4, \[r5\]
 0+10 <[^>]+> e19140d3 ?	ldrsb	r4, \[r1, r3\]
 0+14 <[^>]+> e1b410f4 ?	ldrsh	r1, \[r4, r4\]!
-0+18 <[^>]+> 011510d3 ?	ldreqsb	r1, \[r5, -r3\]
-0+1c <[^>]+> 109620b7 ?	ldrneh	r2, \[r6\], r7
-0+20 <[^>]+> 309720f8 ?	ldrccsh	r2, \[r7\], r8
+0+18 <[^>]+> 011510d3 ?	ldrsbeq	r1, \[r5, -r3\]
+0+1c <[^>]+> 109620b7 ?	ldrhne	r2, \[r6\], r7
+0+20 <[^>]+> 309720f8 ?	ldrshcc	r2, \[r7\], r8
 0+24 <[^>]+> e1d32fdf ?	ldrsb	r2, \[r3, #255\]
 0+28 <[^>]+> e1541ffa ?	ldrsh	r1, \[r4, #-250\]
 0+2c <[^>]+> e1d51fd0 ?	ldrsb	r1, \[r5, #240\]
 0+30 <[^>]+> e1cf23b0 ?	strh	r2, \[pc, #48\]	; 0+68 <[^>]+>
-0+34 <[^>]+> 11c330b0 ?	strneh	r3, \[r3\]
+0+34 <[^>]+> 11c330b0 ?	strhne	r3, \[r3\]
 0+38 <[^>]+> e328f002 ?	msr	CPSR_f, #2	; 0x2
 0+3c <[^>]+> e121f003 ?	msr	CPSR_c, r3
 0+40 <[^>]+> e122f004 ?	msr	CPSR_x, r4
diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d
index 992948b83314..9cf73edf1891 100644
--- a/gas/testsuite/gas/arm/arch7.d
+++ b/gas/testsuite/gas/arm/arch7.d
@@ -1,6 +1,5 @@
 #name: ARM V7 instructions
 #as: -march=armv7r
-#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 #objdump: -dr --prefix-addresses --show-raw-insn
 
 .*: +file format .*arm.*
@@ -29,8 +28,8 @@ Disassembly of section .text:
 0+050 <[^>]*> f995 f000 	pli	\[r5\]
 0+054 <[^>]*> f995 ffff 	pli	\[r5, #4095\]
 0+058 <[^>]*> f915 fcff 	pli	\[r5, #-255\]
-0+05c <[^>]*> f99f ffff 	pli	\[pc, #4095\]	; 0000105f <[^>]*>
-0+060 <[^>]*> f91f ffff 	pli	\[pc, #-4095\]	; fffff065 <[^>]*>
+0+05c <[^>]*> f99f ffff 	pli	\[pc, #4095\]	; 0+0105f <[^>]*>
+0+060 <[^>]*> f91f ffff 	pli	\[pc, #-4095\]	; f+ff065 <[^>]*>
 0+064 <[^>]*> f3af 80f0 	dbg	#0
 0+068 <[^>]*> f3af 80ff 	dbg	#15
 0+06c <[^>]*> f3bf 8f5f 	dmb	sy
diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d
index 1dbaad3a714f..6015a4707ec9 100644
--- a/gas/testsuite/gas/arm/archv6.d
+++ b/gas/testsuite/gas/arm/archv6.d
@@ -13,13 +13,13 @@ Disassembly of section .text:
 0+014 <[^>]*> fc4570c3 ?	mcrr2	0, 12, r7, r5, cr3
 0+018 <[^>]*> fc5570c3 ?	mrrc2	0, 12, r7, r5, cr3
 0+01c <[^>]*> e6852018 ?	pkhbt	r2, r5, r8
-0+020 <[^>]*> e6852198 ?	pkhbt	r2, r5, r8, LSL #3
-0+024 <[^>]*> e6852198 ?	pkhbt	r2, r5, r8, LSL #3
-0+028 <[^>]*> 06852198 ?	pkhbteq	r2, r5, r8, LSL #3
+0+020 <[^>]*> e6852198 ?	pkhbt	r2, r5, r8, lsl #3
+0+024 <[^>]*> e6852198 ?	pkhbt	r2, r5, r8, lsl #3
+0+028 <[^>]*> 06852198 ?	pkhbteq	r2, r5, r8, lsl #3
 0+02c <[^>]*> e6882015 ?	pkhbt	r2, r8, r5
-0+030 <[^>]*> e68521d8 ?	pkhtb	r2, r5, r8, ASR #3
-0+034 <[^>]*> e68521d8 ?	pkhtb	r2, r5, r8, ASR #3
-0+038 <[^>]*> 068521d8 ?	pkhtbeq	r2, r5, r8, ASR #3
+0+030 <[^>]*> e68521d8 ?	pkhtb	r2, r5, r8, asr #3
+0+034 <[^>]*> e68521d8 ?	pkhtb	r2, r5, r8, asr #3
+0+038 <[^>]*> 068521d8 ?	pkhtbeq	r2, r5, r8, asr #3
 0+03c <[^>]*> e6242f17 ?	qadd16	r2, r4, r7
 0+040 <[^>]*> 16242f17 ?	qadd16ne	r2, r4, r7
 0+044 <[^>]*> e6242f97 ?	qadd8	r2, r4, r7
@@ -49,19 +49,19 @@ Disassembly of section .text:
 0+0a4 <[^>]*> e6142f17 ?	sadd16	r2, r4, r7
 0+0a8 <[^>]*> 16142f17 ?	sadd16ne	r2, r4, r7
 0+0ac <[^>]*> e6b42075 ?	sxtah	r2, r4, r5
-0+0b0 <[^>]*> e6b42475 ?	sxtah	r2, r4, r5, ROR #8
+0+0b0 <[^>]*> e6b42475 ?	sxtah	r2, r4, r5, ror #8
 0+0b4 <[^>]*> 16b42075 ?	sxtahne	r2, r4, r5
-0+0b8 <[^>]*> 16b42475 ?	sxtahne	r2, r4, r5, ROR #8
+0+0b8 <[^>]*> 16b42475 ?	sxtahne	r2, r4, r5, ror #8
 0+0bc <[^>]*> e6142f97 ?	sadd8	r2, r4, r7
 0+0c0 <[^>]*> 16142f97 ?	sadd8ne	r2, r4, r7
 0+0c4 <[^>]*> e6842075 ?	sxtab16	r2, r4, r5
-0+0c8 <[^>]*> e6842475 ?	sxtab16	r2, r4, r5, ROR #8
+0+0c8 <[^>]*> e6842475 ?	sxtab16	r2, r4, r5, ror #8
 0+0cc <[^>]*> 16842075 ?	sxtab16ne	r2, r4, r5
-0+0d0 <[^>]*> 16842475 ?	sxtab16ne	r2, r4, r5, ROR #8
+0+0d0 <[^>]*> 16842475 ?	sxtab16ne	r2, r4, r5, ror #8
 0+0d4 <[^>]*> e6a42075 ?	sxtab	r2, r4, r5
-0+0d8 <[^>]*> e6a42475 ?	sxtab	r2, r4, r5, ROR #8
+0+0d8 <[^>]*> e6a42475 ?	sxtab	r2, r4, r5, ror #8
 0+0dc <[^>]*> 16a42075 ?	sxtabne	r2, r4, r5
-0+0e0 <[^>]*> 16a42475 ?	sxtabne	r2, r4, r5, ROR #8
+0+0e0 <[^>]*> 16a42475 ?	sxtabne	r2, r4, r5, ror #8
 0+0e4 <[^>]*> e6142f37 ?	saddaddx	r2, r4, r7
 0+0e8 <[^>]*> 16142f37 ?	saddaddxne	r2, r4, r7
 0+0ec <[^>]*> e6821fb3 ?	sel	r1, r2, r3
@@ -116,11 +116,11 @@ Disassembly of section .text:
 0+1b0 <[^>]*> d701f352 ?	smusdle	r1, r2, r3
 0+1b4 <[^>]*> e701f372 ?	smusdx	r1, r2, r3
 0+1b8 <[^>]*> d701f372 ?	smusdxle	r1, r2, r3
-0+1bc <[^>]*> f8cd0510 ?	srsia	#16
-0+1c0 <[^>]*> f9ed0510 ?	srsib	#16!
+0+1bc <[^>]*> f8cd0510 ?	srsia	sp, #16
+0+1c0 <[^>]*> f9ed0510 ?	srsib	sp!, #16
 0+1c4 <[^>]*> e6a01012 ?	ssat	r1, #1, r2
-0+1c8 <[^>]*> e6a01152 ?	ssat	r1, #1, r2, ASR #2
-0+1cc <[^>]*> e6a01112 ?	ssat	r1, #1, r2, LSL #2
+0+1c8 <[^>]*> e6a01152 ?	ssat	r1, #1, r2, asr #2
+0+1cc <[^>]*> e6a01112 ?	ssat	r1, #1, r2, lsl #2
 0+1d0 <[^>]*> e6a01f31 ?	ssat16	r1, #1, r1
 0+1d4 <[^>]*> d6a01f31 ?	ssat16le	r1, #1, r1
 0+1d8 <[^>]*> e6142f77 ?	ssub16	r2, r4, r7
@@ -131,34 +131,34 @@ Disassembly of section .text:
 0+1ec <[^>]*> 16142f57 ?	ssubaddxne	r2, r4, r7
 0+1f0 <[^>]*> e1831f92 ?	strex	r1, r2, \[r3\]
 0+1f4 <[^>]*> 11831f92 ?	strexne	r1, r2, \[r3\]
-0+1f8 <[^>]*> e6bf2075 ?	sxth r2,r5
-0+1fc <[^>]*> e6bf2475 ?	sxth r2,r5, ROR #8
-0+200 <[^>]*> 16bf2075 ?	sxthne r2,r5
-0+204 <[^>]*> 16bf2475 ?	sxthne r2,r5, ROR #8
-0+208 <[^>]*> e68f2075 ?	sxtb16 r2,r5
-0+20c <[^>]*> e68f2475 ?	sxtb16 r2,r5, ROR #8
-0+210 <[^>]*> 168f2075 ?	sxtb16ne r2,r5
-0+214 <[^>]*> 168f2475 ?	sxtb16ne r2,r5, ROR #8
-0+218 <[^>]*> e6af2075 ?	sxtb r2,r5
-0+21c <[^>]*> e6af2475 ?	sxtb r2,r5, ROR #8
-0+220 <[^>]*> 16af2075 ?	sxtbne r2,r5
-0+224 <[^>]*> 16af2475 ?	sxtbne r2,r5, ROR #8
+0+1f8 <[^>]*> e6bf2075 ?	sxth	r2, r5
+0+1fc <[^>]*> e6bf2475 ?	sxth	r2, r5, ror #8
+0+200 <[^>]*> 16bf2075 ?	sxthne	r2, r5
+0+204 <[^>]*> 16bf2475 ?	sxthne	r2, r5, ror #8
+0+208 <[^>]*> e68f2075 ?	sxtb16	r2, r5
+0+20c <[^>]*> e68f2475 ?	sxtb16	r2, r5, ror #8
+0+210 <[^>]*> 168f2075 ?	sxtb16ne	r2, r5
+0+214 <[^>]*> 168f2475 ?	sxtb16ne	r2, r5, ror #8
+0+218 <[^>]*> e6af2075 ?	sxtb	r2, r5
+0+21c <[^>]*> e6af2475 ?	sxtb	r2, r5, ror #8
+0+220 <[^>]*> 16af2075 ?	sxtbne	r2, r5
+0+224 <[^>]*> 16af2475 ?	sxtbne	r2, r5, ror #8
 0+228 <[^>]*> e6542f17 ?	uadd16	r2, r4, r7
 0+22c <[^>]*> 16542f17 ?	uadd16ne	r2, r4, r7
 0+230 <[^>]*> e6f32075 ?	uxtah	r2, r3, r5
-0+234 <[^>]*> e6f32475 ?	uxtah	r2, r3, r5, ROR #8
+0+234 <[^>]*> e6f32475 ?	uxtah	r2, r3, r5, ror #8
 0+238 <[^>]*> 16f32075 ?	uxtahne	r2, r3, r5
-0+23c <[^>]*> 16f32475 ?	uxtahne	r2, r3, r5, ROR #8
+0+23c <[^>]*> 16f32475 ?	uxtahne	r2, r3, r5, ror #8
 0+240 <[^>]*> e6542f97 ?	uadd8	r2, r4, r7
 0+244 <[^>]*> 16542f97 ?	uadd8ne	r2, r4, r7
 0+248 <[^>]*> e6c32075 ?	uxtab16	r2, r3, r5
-0+24c <[^>]*> e6c32475 ?	uxtab16	r2, r3, r5, ROR #8
+0+24c <[^>]*> e6c32475 ?	uxtab16	r2, r3, r5, ror #8
 0+250 <[^>]*> 16c32075 ?	uxtab16ne	r2, r3, r5
-0+254 <[^>]*> 16c32475 ?	uxtab16ne	r2, r3, r5, ROR #8
+0+254 <[^>]*> 16c32475 ?	uxtab16ne	r2, r3, r5, ror #8
 0+258 <[^>]*> e6e32075 ?	uxtab	r2, r3, r5
-0+25c <[^>]*> e6e32475 ?	uxtab	r2, r3, r5, ROR #8
+0+25c <[^>]*> e6e32475 ?	uxtab	r2, r3, r5, ror #8
 0+260 <[^>]*> 16e32075 ?	uxtabne	r2, r3, r5
-0+264 <[^>]*> 16e32475 ?	uxtabne	r2, r3, r5, ROR #8
+0+264 <[^>]*> 16e32475 ?	uxtabne	r2, r3, r5, ror #8
 0+268 <[^>]*> e6542f37 ?	uaddsubx	r2, r4, r7
 0+26c <[^>]*> 16542f37 ?	uaddsubxne	r2, r4, r7
 0+270 <[^>]*> e6742f17 ?	uhadd16	r2, r4, r7
@@ -192,28 +192,32 @@ Disassembly of section .text:
 0+2e0 <[^>]*> e7814312 ?	usada8	r1, r2, r3, r4
 0+2e4 <[^>]*> 17814312 ?	usada8ne	r1, r2, r3, r4
 0+2e8 <[^>]*> e6ef1012 ?	usat	r1, #15, r2
-0+2ec <[^>]*> e6ef1252 ?	usat	r1, #15, r2, ASR #4
-0+2f0 <[^>]*> e6ef1212 ?	usat	r1, #15, r2, LSL #4
+0+2ec <[^>]*> e6ef1252 ?	usat	r1, #15, r2, asr #4
+0+2f0 <[^>]*> e6ef1212 ?	usat	r1, #15, r2, lsl #4
 0+2f4 <[^>]*> e6ef1f32 ?	usat16	r1, #15, r2
 0+2f8 <[^>]*> d6ef1f32 ?	usat16le	r1, #15, r2
 0+2fc <[^>]*> d6ef1012 ?	usatle	r1, #15, r2
-0+300 <[^>]*> d6ef1252 ?	usatle	r1, #15, r2, ASR #4
-0+304 <[^>]*> d6ef1212 ?	usatle	r1, #15, r2, LSL #4
+0+300 <[^>]*> d6ef1252 ?	usatle	r1, #15, r2, asr #4
+0+304 <[^>]*> d6ef1212 ?	usatle	r1, #15, r2, lsl #4
 0+308 <[^>]*> e6542f77 ?	usub16	r2, r4, r7
 0+30c <[^>]*> 16542f77 ?	usub16ne	r2, r4, r7
 0+310 <[^>]*> e6542ff7 ?	usub8	r2, r4, r7
 0+314 <[^>]*> 16542ff7 ?	usub8ne	r2, r4, r7
 0+318 <[^>]*> e6542f57 ?	usubaddx	r2, r4, r7
 0+31c <[^>]*> 16542f57 ?	usubaddxne	r2, r4, r7
-0+320 <[^>]*> e6ff2075 ?	uxth r2,r5
-0+324 <[^>]*> e6ff2475 ?	uxth r2,r5, ROR #8
-0+328 <[^>]*> 16ff2075 ?	uxthne r2,r5
-0+32c <[^>]*> 16ff2475 ?	uxthne r2,r5, ROR #8
-0+330 <[^>]*> e6cf2075 ?	uxtb16 r2,r5
-0+334 <[^>]*> e6cf2475 ?	uxtb16 r2,r5, ROR #8
-0+338 <[^>]*> 16cf2075 ?	uxtb16ne r2,r5
-0+33c <[^>]*> 16cf2475 ?	uxtb16ne r2,r5, ROR #8
-0+340 <[^>]*> e6ef2075 ?	uxtb r2,r5
-0+344 <[^>]*> e6ef2475 ?	uxtb r2,r5, ROR #8
-0+348 <[^>]*> 16ef2075 ?	uxtbne r2,r5
-0+34c <[^>]*> 16ef2475 ?	uxtbne r2,r5, ROR #8
+0+320 <[^>]*> e6ff2075 ?	uxth	r2, r5
+0+324 <[^>]*> e6ff2475 ?	uxth	r2, r5, ror #8
+0+328 <[^>]*> 16ff2075 ?	uxthne	r2, r5
+0+32c <[^>]*> 16ff2475 ?	uxthne	r2, r5, ror #8
+0+330 <[^>]*> e6cf2075 ?	uxtb16	r2, r5
+0+334 <[^>]*> e6cf2475 ?	uxtb16	r2, r5, ror #8
+0+338 <[^>]*> 16cf2075 ?	uxtb16ne	r2, r5
+0+33c <[^>]*> 16cf2475 ?	uxtb16ne	r2, r5, ror #8
+0+340 <[^>]*> e6ef2075 ?	uxtb	r2, r5
+0+344 <[^>]*> e6ef2475 ?	uxtb	r2, r5, ror #8
+0+348 <[^>]*> 16ef2075 ?	uxtbne	r2, r5
+0+34c <[^>]*> 16ef2475 ?	uxtbne	r2, r5, ror #8
+0+350 <[^>]*> f10a00ca ?	cpsie	if,#10
+0+354 <[^>]*> f10a00d5 ?	cpsie	if,#21
+0+358 <[^>]*> f8cd0510 ?	srsia	sp, #16
+0+35c <[^>]*> f9ed0510 ?	srsib	sp!, #16
diff --git a/gas/testsuite/gas/arm/archv6.s b/gas/testsuite/gas/arm/archv6.s
index 50378b7c3798..85f05c185d02 100644
--- a/gas/testsuite/gas/arm/archv6.s
+++ b/gas/testsuite/gas/arm/archv6.s
@@ -214,3 +214,7 @@ label:
 	uxtb r2, r5, ROR #8
 	uxtbne r2, r5
 	uxtbne r2, r5, ROR #8
+	cpsie if, #10
+	cpsie if, #21
+	srsia sp, #16
+	srsib sp!, #16
diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d
index 8e8b0387a336..e6e57c843b90 100644
--- a/gas/testsuite/gas/arm/archv6t2.d
+++ b/gas/testsuite/gas/arm/archv6t2.d
@@ -24,10 +24,10 @@ Disassembly of section .text:
 0+40 <[^>]+> e7a00059 	sbfx	r0, r9, #0, #1
 0+44 <[^>]+> e7a008d0 	sbfx	r0, r0, #17, #1
 0+48 <[^>]+> e7b10050 	sbfx	r0, r0, #0, #18
-0+4c <[^>]+> e3ff0f30 	rbit	r0, r0
-0+50 <[^>]+> 13ff0f30 	rbitne	r0, r0
-0+54 <[^>]+> e3ff9f30 	rbit	r9, r0
-0+58 <[^>]+> e3ff0f39 	rbit	r0, r9
+0+4c <[^>]+> e6ff0f30 	rbit	r0, r0
+0+50 <[^>]+> 16ff0f30 	rbitne	r0, r0
+0+54 <[^>]+> e6ff9f30 	rbit	r9, r0
+0+58 <[^>]+> e6ff0f39 	rbit	r0, r9
 0+5c <[^>]+> e0600090 	mls	r0, r0, r0, r0
 0+60 <[^>]+> 10600090 	mlsne	r0, r0, r0, r0
 0+64 <[^>]+> e0690090 	mls	r9, r0, r0, r0
@@ -44,7 +44,7 @@ Disassembly of section .text:
 0+90 <[^>]+> e0f900f0 	ldrsht	r0, \[r9\]
 0+94 <[^>]+> e0f900d0 	ldrsbt	r0, \[r9\]
 0+98 <[^>]+> e0e900b0 	strht	r0, \[r9\]
-0+9c <[^>]+> 10f900b0 	ldrneht	r0, \[r9\]
+0+9c <[^>]+> 10f900b0 	ldrhtne	r0, \[r9\]
 0+a0 <[^>]+> e0b090b9 	ldrht	r9, \[r0\], r9
 0+a4 <[^>]+> e03090b9 	ldrht	r9, \[r0\], -r9
 0+a8 <[^>]+> e0f099b9 	ldrht	r9, \[r0\], #153
diff --git a/gas/testsuite/gas/arm/arm-it.d b/gas/testsuite/gas/arm/arm-it.d
new file mode 100644
index 000000000000..674f815f1dec
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm-it.d
@@ -0,0 +1,9 @@
+#name: ARM IT instruction
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> 03a00000 ?	moveq	r0, #0	; 0x0
+0+004 <[^>]*> e1a0f00e ?	mov	pc, lr
diff --git a/gas/testsuite/gas/arm/arm-it.s b/gas/testsuite/gas/arm/arm-it.s
new file mode 100644
index 000000000000..f3c56e8c4b70
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm-it.s
@@ -0,0 +1,8 @@
+	# Check that IT is accepted in ARM mode on older architectures
+	.text
+	.syntax unified
+	.arch armv4
+label1:
+	it	eq
+	moveq	r0, #0
+	mov	pc, lr
diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d
index 06323b1c0cdf..41b6b7eb8fdc 100644
--- a/gas/testsuite/gas/arm/arm3.d
+++ b/gas/testsuite/gas/arm/arm3.d
@@ -7,5 +7,5 @@
 Disassembly of section .text:
 0+0 <[^>]*> e1080091 ?	swp	r0, r1, \[r8\]
 0+4 <[^>]*> e1423093 ?	swpb	r3, r3, \[r2\]
-0+8 <[^>]*> a1454091 ?	swpgeb	r4, r1, \[r5\]
+0+8 <[^>]*> a1454091 ?	swpbge	r4, r1, \[r5\]
 0+c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d
index ef47ca6c6689..43f64204e97a 100644
--- a/gas/testsuite/gas/arm/arm7dm.d
+++ b/gas/testsuite/gas/arm/arm7dm.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
 0+0c <[^>]+> e0a10394 ?	umlal	r0, r1, r4, r3
 0+10 <[^>]+> 10c10493 ?	smullne	r0, r1, r3, r4
 0+14 <[^>]+> e0d01b99 ?	smulls	r1, r0, r9, fp
-0+18 <[^>]+> 00b92994 ?	umlaleqs	r2, r9, r4, r9
+0+18 <[^>]+> 00b92994 ?	umlalseq	r2, r9, r4, r9
 0+1c <[^>]+> a0eaee98 ?	smlalge	lr, sl, r8, lr
 0+20 <[^>]+> e322f000 ?	msr	CPSR_x, #0	; 0x0
 0+24 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d
index 17e4e9d4fb5e..37abd7a7781f 100644
--- a/gas/testsuite/gas/arm/arm7t.d
+++ b/gas/testsuite/gas/arm/arm7t.d
@@ -49,20 +49,20 @@ Disassembly of section .text:
 0+9c <[^>]*> e1df03fc ?	ldrsh	r0, \[pc, #60\]	; 0+e0 <[^>]*>
 0+a0 <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+dc <[^>]*>
 0+a4 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
-0+a8 <[^>]*> 119100b2 ?	ldrneh	r0, \[r1, r2\]
-0+ac <[^>]*> 819100b2 ?	ldrhih	r0, \[r1, r2\]
-0+b0 <[^>]*> b19100b2 ?	ldrlth	r0, \[r1, r2\]
+0+a8 <[^>]*> 119100b2 ?	ldrhne	r0, \[r1, r2\]
+0+ac <[^>]*> 819100b2 ?	ldrhhi	r0, \[r1, r2\]
+0+b0 <[^>]*> b19100b2 ?	ldrhlt	r0, \[r1, r2\]
 0+b4 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
-0+b8 <[^>]*> 119100f2 ?	ldrnesh	r0, \[r1, r2\]
-0+bc <[^>]*> 819100f2 ?	ldrhish	r0, \[r1, r2\]
-0+c0 <[^>]*> b19100f2 ?	ldrltsh	r0, \[r1, r2\]
+0+b8 <[^>]*> 119100f2 ?	ldrshne	r0, \[r1, r2\]
+0+bc <[^>]*> 819100f2 ?	ldrshhi	r0, \[r1, r2\]
+0+c0 <[^>]*> b19100f2 ?	ldrshlt	r0, \[r1, r2\]
 0+c4 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
-0+c8 <[^>]*> 119100d2 ?	ldrnesb	r0, \[r1, r2\]
-0+cc <[^>]*> 819100d2 ?	ldrhisb	r0, \[r1, r2\]
-0+d0 <[^>]*> b19100d2 ?	ldrltsb	r0, \[r1, r2\]
+0+c8 <[^>]*> 119100d2 ?	ldrsbne	r0, \[r1, r2\]
+0+cc <[^>]*> 819100d2 ?	ldrsbhi	r0, \[r1, r2\]
+0+d0 <[^>]*> b19100d2 ?	ldrsblt	r0, \[r1, r2\]
 0+d4 <[^>]*> e1df00f4 ?	ldrsh	r0, \[pc, #4\]	; 0+e0 <[^>]*>
 0+d8 <[^>]*> e1df00f4 ?	ldrsh	r0, \[pc, #4\]	; 0+e4 <[^>]*>
-0+dc <[^>]*> 00000000 ?	andeq	r0, r0, r0
+0+dc <[^>]*> 00000000 ?	.*
 [		]*dc:.*fred
 0+e0 <[^>]*> 0000c0de ?	.*
 0+e4 <[^>]*> 0000dead ?	.*
diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d
index 4e4c91376179..99e8471e2222 100644
--- a/gas/testsuite/gas/arm/armv1.d
+++ b/gas/testsuite/gas/arm/armv1.d
@@ -1,6 +1,7 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: ARM v1 instructions
 #as: -mcpu=arm7t
+#error-output: armv1.l
 
 # Test the ARM v1 instructions
 
@@ -52,19 +53,19 @@ Disassembly of section .text:
 0+a8 <[^>]*> e5c00000 ?	strb	r0, \[r0\]
 0+ac <[^>]*> e4a10000 ?	strt	r0, \[r1\]
 0+b0 <[^>]*> e4e10000 ?	strbt	r0, \[r1\]
-0+b4 <[^>]*> e8800001 ?	stmia	r0, {r0}
+0+b4 <[^>]*> e8800001 ?	stm	r0, {r0}
 0+b8 <[^>]*> e9800001 ?	stmib	r0, {r0}
 0+bc <[^>]*> e8000001 ?	stmda	r0, {r0}
 0+c0 <[^>]*> e9000001 ?	stmdb	r0, {r0}
 0+c4 <[^>]*> e9000001 ?	stmdb	r0, {r0}
 0+c8 <[^>]*> e9800001 ?	stmib	r0, {r0}
-0+cc <[^>]*> e8800001 ?	stmia	r0, {r0}
+0+cc <[^>]*> e8800001 ?	stm	r0, {r0}
 0+d0 <[^>]*> e8000001 ?	stmda	r0, {r0}
-0+d4 <[^>]*> e8900001 ?	ldmia	r0, {r0}
+0+d4 <[^>]*> e8900001 ?	ldm	r0, {r0}
 0+d8 <[^>]*> e9900001 ?	ldmib	r0, {r0}
 0+dc <[^>]*> e8100001 ?	ldmda	r0, {r0}
 0+e0 <[^>]*> e9100001 ?	ldmdb	r0, {r0}
-0+e4 <[^>]*> e8900001 ?	ldmia	r0, {r0}
+0+e4 <[^>]*> e8900001 ?	ldm	r0, {r0}
 0+e8 <[^>]*> e8100001 ?	ldmda	r0, {r0}
 0+ec <[^>]*> e9100001 ?	ldmdb	r0, {r0}
 0+f0 <[^>]*> e9900001 ?	ldmib	r0, {r0}
diff --git a/gas/testsuite/gas/arm/armv1.l b/gas/testsuite/gas/arm/armv1.l
new file mode 100644
index 000000000000..369f9d4a5105
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv1.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:26: Warning: s suffix on comparison instruction is deprecated
+[^:]*:29: Warning: s suffix on comparison instruction is deprecated
+[^:]*:32: Warning: s suffix on comparison instruction is deprecated
+[^:]*:35: Warning: s suffix on comparison instruction is deprecated
diff --git a/gas/testsuite/gas/arm/backslash-at.d b/gas/testsuite/gas/arm/backslash-at.d
new file mode 100644
index 000000000000..a8992bdb4fac
--- /dev/null
+++ b/gas/testsuite/gas/arm/backslash-at.d
@@ -0,0 +1,17 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Backslash-at for ARM
+
+.*:     file format .*arm.*
+
+Disassembly of section .text:
+0+000 <.*>.*615c.*
+0+002 <foo> e3a00000 	mov	r0, #0	; 0x0
+0+006 <foo\+0x4> e3a00000 	mov	r0, #0	; 0x0
+0+00a <foo\+0x8> e3a00000 	mov	r0, #0	; 0x0
+0+00e <foo\+0xc> e3a00001 	mov	r0, #1	; 0x1
+0+012 <foo\+0x10> e3a00001 	mov	r0, #1	; 0x1
+0+016 <foo\+0x14> e3a00001 	mov	r0, #1	; 0x1
+0+01a <foo\+0x18> e3a00002 	mov	r0, #2	; 0x2
+0+01e <foo\+0x1c> e3a00002 	mov	r0, #2	; 0x2
+0+022 <foo\+0x20> e3a00002 	mov	r0, #2	; 0x2
+#...
diff --git a/gas/testsuite/gas/arm/backslash-at.s b/gas/testsuite/gas/arm/backslash-at.s
new file mode 100644
index 000000000000..4975aea688f8
--- /dev/null
+++ b/gas/testsuite/gas/arm/backslash-at.s
@@ -0,0 +1,16 @@
+@ Check that \@ is not destroyed when assembling for the ARM.
+
+.macro bar
+	mov	r0, #\@
+	mov	r0, #\@@comment
+	mov	r0, #\@ @comment
+.endm
+
+.byte	'\\
+.byte	'\a
+
+foo:
+	bar
+	bar
+	bar
+
diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
index 5f5dd110e99a..37d0f2d6fdb5 100644
--- a/gas/testsuite/gas/arm/copro.d
+++ b/gas/testsuite/gas/arm/copro.d
@@ -12,7 +12,7 @@ Disassembly of section .text:
 0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
 0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
 0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
-0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
+0+014 <[^>]*> 5cf31710 	ldclpl	7, cr1, \[r3\], #64
 0+018 <[^>]*> ed1f8001 	ldc	0, cr8, \[pc, #-4\]
 0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
 0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
@@ -31,7 +31,7 @@ Disassembly of section .text:
 0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
 0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
 0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
-0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
+0+060 <[^>]*> ecd88cff 	ldcl	12, cr8, \[r8\], \{255\}
 0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
 0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
 0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s
index 334b000f4409..e6976329c756 100644
--- a/gas/testsuite/gas/arm/copro.s
+++ b/gas/testsuite/gas/arm/copro.s
@@ -33,7 +33,8 @@ bar:
         stcl    p8,  c2, [r5], {5}
         ldc2l   9,   c1, [r6], {6}
         stc2l   p10, c0, [r7], {7}
-        ldcl    11,  c8, [r8], {255}
+        @ using '11' below results in an (invalid) Neon vldmia instruction.
+        ldcl    12,  c8, [r8], {255}
         stcl    p12, c9, [r9], {254}
         mrrc    13,   0, r7, r0, cr4
         mcrr    p14,  0, r7, r0, cr5
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d
new file mode 100644
index 000000000000..e10a6a7589ba
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, encoding failures (alu)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-alu-encoding-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l
new file mode 100644
index 000000000000..fe8827cec78b
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l
@@ -0,0 +1,81 @@
+[^:]*: Assembler messages:
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:23: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:24: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:25: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:26: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:28: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:29: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:30: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
+[^:]*:31: Error: the offset 0x00011001 is not representable
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s
new file mode 100644
index 000000000000..bdde4ad45068
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s
@@ -0,0 +1,35 @@
+@ Tests that should fail for ALU group relocations.
+
+	.text
+
+	.macro alutest insn sym offset
+
+	\insn	r0, r0, #:pc_g0:(\sym + \offset)
+	\insn	r0, r0, #:pc_g1:(\sym + \offset)
+	\insn	r0, r0, #:pc_g2:(\sym + \offset)
+
+	\insn	r0, r0, #:pc_g0_nc:(\sym + \offset)
+	\insn	r0, r0, #:pc_g1_nc:(\sym + \offset)
+
+	\insn	r0, r0, #:sb_g0:(\sym + \offset)
+	\insn	r0, r0, #:sb_g1:(\sym + \offset)
+	\insn	r0, r0, #:sb_g2:(\sym + \offset)
+
+	\insn	r0, r0, #:sb_g0_nc:(\sym + \offset)
+	\insn	r0, r0, #:sb_g1_nc:(\sym + \offset)
+
+	.endm
+
+	alutest add f 0x11001
+	alutest add localsym 0x11001
+	alutest adds f 0x11001
+	alutest adds localsym 0x11001
+
+	alutest add f "-0x11001"
+	alutest add localsym "-0x11001"
+	alutest adds f "-0x11001"
+	alutest adds localsym "-0x11001"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d
new file mode 100644
index 000000000000..808bc05f0805
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, parsing failures (alu)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-alu-parsing-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l
new file mode 100644
index 000000000000..1c27ad02ffc9
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)'
+[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)'
+[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)'
+[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)'
diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s
new file mode 100644
index 000000000000..70a62acefa60
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s
@@ -0,0 +1,12 @@
+@ Tests that should fail for ALU group relocations.
+
+	.text
+
+@ Group relocs aren't allowed on SUB(S) instructions...
+	sub	r0, r0, #:pc_g0:(foo)
+	subs	r0, r0, #:pc_g0:(foo)
+
+@ Some nonexistent relocations:
+	add	r0, r0, #:pc_g2_nc:(foo)
+	add	r0, r0, #:sb_g2_nc:(foo)
+
diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d
new file mode 100644
index 000000000000..40e502588375
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu.d
@@ -0,0 +1,168 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Group relocation tests (alu)
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			0: R_ARM_ALU_PC_G0	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			4: R_ARM_ALU_PC_G1	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			8: R_ARM_ALU_PC_G2	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			c: R_ARM_ALU_PC_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			10: R_ARM_ALU_PC_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			14: R_ARM_ALU_SB_G0	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			18: R_ARM_ALU_SB_G1	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			1c: R_ARM_ALU_SB_G2	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			20: R_ARM_ALU_SB_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			24: R_ARM_ALU_SB_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			28: R_ARM_ALU_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			2c: R_ARM_ALU_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			30: R_ARM_ALU_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			34: R_ARM_ALU_PC_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			38: R_ARM_ALU_PC_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			3c: R_ARM_ALU_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			40: R_ARM_ALU_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			44: R_ARM_ALU_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			48: R_ARM_ALU_SB_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2800c01 	add	r0, r0, #256	; 0x100
+			4c: R_ARM_ALU_SB_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			50: R_ARM_ALU_PC_G0	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			54: R_ARM_ALU_PC_G1	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			58: R_ARM_ALU_PC_G2	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			5c: R_ARM_ALU_PC_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			60: R_ARM_ALU_PC_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			64: R_ARM_ALU_SB_G0	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			68: R_ARM_ALU_SB_G1	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			6c: R_ARM_ALU_SB_G2	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			70: R_ARM_ALU_SB_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			74: R_ARM_ALU_SB_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			78: R_ARM_ALU_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			7c: R_ARM_ALU_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			80: R_ARM_ALU_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			84: R_ARM_ALU_PC_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			88: R_ARM_ALU_PC_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			8c: R_ARM_ALU_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			90: R_ARM_ALU_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			94: R_ARM_ALU_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			98: R_ARM_ALU_SB_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2900c01 	adds	r0, r0, #256	; 0x100
+			9c: R_ARM_ALU_SB_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			a0: R_ARM_ALU_PC_G0	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			a4: R_ARM_ALU_PC_G1	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			a8: R_ARM_ALU_PC_G2	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			ac: R_ARM_ALU_PC_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			b0: R_ARM_ALU_PC_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			b4: R_ARM_ALU_SB_G0	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			b8: R_ARM_ALU_SB_G1	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			bc: R_ARM_ALU_SB_G2	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			c0: R_ARM_ALU_SB_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			c4: R_ARM_ALU_SB_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			c8: R_ARM_ALU_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			cc: R_ARM_ALU_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			d0: R_ARM_ALU_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			d4: R_ARM_ALU_PC_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			d8: R_ARM_ALU_PC_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			dc: R_ARM_ALU_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			e0: R_ARM_ALU_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			e4: R_ARM_ALU_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			e8: R_ARM_ALU_SB_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2400c01 	sub	r0, r0, #256	; 0x100
+			ec: R_ARM_ALU_SB_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			f0: R_ARM_ALU_PC_G0	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			f4: R_ARM_ALU_PC_G1	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			f8: R_ARM_ALU_PC_G2	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			fc: R_ARM_ALU_PC_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			100: R_ARM_ALU_PC_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			104: R_ARM_ALU_SB_G0	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			108: R_ARM_ALU_SB_G1	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			10c: R_ARM_ALU_SB_G2	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			110: R_ARM_ALU_SB_G0_NC	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			114: R_ARM_ALU_SB_G1_NC	f
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			118: R_ARM_ALU_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			11c: R_ARM_ALU_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			120: R_ARM_ALU_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			124: R_ARM_ALU_PC_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			128: R_ARM_ALU_PC_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			12c: R_ARM_ALU_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			130: R_ARM_ALU_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			134: R_ARM_ALU_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			138: R_ARM_ALU_SB_G0_NC	localsym
+0[0-9a-f]+ <[^>]+> e2500c01 	subs	r0, r0, #256	; 0x100
+			13c: R_ARM_ALU_SB_G1_NC	localsym
+0[0-9a-f]+ <[^>]+> e3a00000 	mov	r0, #0	; 0x0
diff --git a/gas/testsuite/gas/arm/group-reloc-alu.s b/gas/testsuite/gas/arm/group-reloc-alu.s
new file mode 100644
index 000000000000..696f1dac0cc4
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-alu.s
@@ -0,0 +1,39 @@
+@ Tests for ALU group relocations.
+
+	.text
+
+	.macro alutest insn sym offset
+
+	\insn	r0, r0, #:pc_g0:(\sym \offset)
+	\insn	r0, r0, #:pc_g1:(\sym \offset)
+
+@ Try this one without the hash; it should still work.
+	\insn	r0, r0, :pc_g2:(\sym \offset)
+
+	\insn	r0, r0, #:pc_g0_nc:(\sym \offset)
+	\insn	r0, r0, #:pc_g1_nc:(\sym \offset)
+
+	\insn	r0, r0, #:sb_g0:(\sym \offset)
+	\insn	r0, r0, #:sb_g1:(\sym \offset)
+	\insn	r0, r0, #:sb_g2:(\sym \offset)
+
+	\insn	r0, r0, #:sb_g0_nc:(\sym \offset)
+	\insn	r0, r0, #:sb_g1_nc:(\sym \offset)
+
+	.endm
+
+	alutest add f "+ 0x100"
+	alutest add localsym "+ 0x100"
+	alutest adds f "+ 0x100"
+	alutest adds localsym "+ 0x100"
+
+@ The following should cause the insns to be switched to SUB(S).
+
+	alutest add f "- 0x100"
+	alutest add localsym "- 0x100"
+	alutest adds f "- 0x100"
+	alutest adds localsym "- 0x100"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d
new file mode 100644
index 000000000000..52ee2e55b653
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, encoding failures (ldc)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldc-encoding-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
new file mode 100644
index 000000000000..22e53a5901d6
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l
@@ -0,0 +1,721 @@
+[^:]*: Assembler messages:
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
+[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
new file mode 100644
index 000000000000..5ab27c25fb7a
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
@@ -0,0 +1,169 @@
+@ LDC group relocation tests that are supposed to fail during encoding.
+
+	.text
+
+@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
+
+	.macro ldctest load store cst
+
+	\load	0, c0, [r0, #:pc_g0:(f + \cst)]
+	\load	0, c0, [r0, #:pc_g1:(f + \cst)]
+	\load	0, c0, [r0, #:pc_g2:(f + \cst)]
+
+	\load	0, c0, [r0, #:sb_g0:(f + \cst)]
+	\load	0, c0, [r0, #:sb_g1:(f + \cst)]
+	\load	0, c0, [r0, #:sb_g2:(f + \cst)]
+
+	\store	0, c0, [r0, #:pc_g0:(f + \cst)]
+	\store	0, c0, [r0, #:pc_g1:(f + \cst)]
+	\store	0, c0, [r0, #:pc_g2:(f + \cst)]
+
+	\store	0, c0, [r0, #:sb_g0:(f + \cst)]
+	\store	0, c0, [r0, #:sb_g1:(f + \cst)]
+	\store	0, c0, [r0, #:sb_g2:(f + \cst)]
+
+	\load	0, c0, [r0, #:pc_g0:(f - \cst)]
+	\load	0, c0, [r0, #:pc_g1:(f - \cst)]
+	\load	0, c0, [r0, #:pc_g2:(f - \cst)]
+
+	\load	0, c0, [r0, #:sb_g0:(f - \cst)]
+	\load	0, c0, [r0, #:sb_g1:(f - \cst)]
+	\load	0, c0, [r0, #:sb_g2:(f - \cst)]
+
+	\store	0, c0, [r0, #:pc_g0:(f - \cst)]
+	\store	0, c0, [r0, #:pc_g1:(f - \cst)]
+	\store	0, c0, [r0, #:pc_g2:(f - \cst)]
+
+	\store	0, c0, [r0, #:sb_g0:(f - \cst)]
+	\store	0, c0, [r0, #:sb_g1:(f - \cst)]
+	\store	0, c0, [r0, #:sb_g2:(f - \cst)]
+
+	.endm
+
+	ldctest ldc stc 0x1
+	ldctest ldcl stcl 0x1
+	ldctest ldc2 stc2 0x1
+	ldctest ldc2l stc2l 0x1
+
+	ldctest ldc stc 0x808
+	ldctest ldcl stcl 0x808
+	ldctest ldc2 stc2 0x808
+	ldctest ldc2l stc2l 0x808
+
+@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
+
+	.fpu	fpa
+
+	.macro	fpa_test load store cst
+
+	\load	f0, [r0, #:pc_g0:(f + \cst)]
+	\load	f0, [r0, #:pc_g1:(f + \cst)]
+	\load	f0, [r0, #:pc_g2:(f + \cst)]
+
+	\load	f0, [r0, #:sb_g0:(f + \cst)]
+	\load	f0, [r0, #:sb_g1:(f + \cst)]
+	\load	f0, [r0, #:sb_g2:(f + \cst)]
+
+	\store	f0, [r0, #:pc_g0:(f + \cst)]
+	\store	f0, [r0, #:pc_g1:(f + \cst)]
+	\store	f0, [r0, #:pc_g2:(f + \cst)]
+
+	\store	f0, [r0, #:sb_g0:(f + \cst)]
+	\store	f0, [r0, #:sb_g1:(f + \cst)]
+	\store	f0, [r0, #:sb_g2:(f + \cst)]
+
+	\load	f0, [r0, #:pc_g0:(f - \cst)]
+	\load	f0, [r0, #:pc_g1:(f - \cst)]
+	\load	f0, [r0, #:pc_g2:(f - \cst)]
+
+	\load	f0, [r0, #:sb_g0:(f - \cst)]
+	\load	f0, [r0, #:sb_g1:(f - \cst)]
+	\load	f0, [r0, #:sb_g2:(f - \cst)]
+
+	\store	f0, [r0, #:pc_g0:(f - \cst)]
+	\store	f0, [r0, #:pc_g1:(f - \cst)]
+	\store	f0, [r0, #:pc_g2:(f - \cst)]
+
+	\store	f0, [r0, #:sb_g0:(f - \cst)]
+	\store	f0, [r0, #:sb_g1:(f - \cst)]
+	\store	f0, [r0, #:sb_g2:(f - \cst)]
+
+	.endm
+
+	fpa_test ldfs stfs 0x1
+	fpa_test ldfd stfd 0x1
+	fpa_test ldfe stfe 0x1
+	fpa_test ldfp stfp 0x1
+
+	fpa_test ldfs stfs 0x808
+	fpa_test ldfd stfd 0x808
+	fpa_test ldfe stfe 0x808
+	fpa_test ldfp stfp 0x808
+
+@ FLDS/FSTS
+
+	.fpu	vfp
+
+	.macro vfp_test load store reg cst
+
+	\load	\reg, [r0, #:pc_g0:(f + \cst)]
+	\load	\reg, [r0, #:pc_g1:(f + \cst)]
+	\load	\reg, [r0, #:pc_g2:(f + \cst)]
+
+	\load	\reg, [r0, #:sb_g0:(f + \cst)]
+	\load	\reg, [r0, #:sb_g1:(f + \cst)]
+	\load	\reg, [r0, #:sb_g2:(f + \cst)]
+
+	\store	\reg, [r0, #:pc_g0:(f + \cst)]
+	\store	\reg, [r0, #:pc_g1:(f + \cst)]
+	\store	\reg, [r0, #:pc_g2:(f + \cst)]
+
+	\store	\reg, [r0, #:sb_g0:(f + \cst)]
+	\store	\reg, [r0, #:sb_g1:(f + \cst)]
+	\store	\reg, [r0, #:sb_g2:(f + \cst)]
+
+	\load	\reg, [r0, #:pc_g0:(f - \cst)]
+	\load	\reg, [r0, #:pc_g1:(f - \cst)]
+	\load	\reg, [r0, #:pc_g2:(f - \cst)]
+
+	\load	\reg, [r0, #:sb_g0:(f - \cst)]
+	\load	\reg, [r0, #:sb_g1:(f - \cst)]
+	\load	\reg, [r0, #:sb_g2:(f - \cst)]
+
+	\store	\reg, [r0, #:pc_g0:(f - \cst)]
+	\store	\reg, [r0, #:pc_g1:(f - \cst)]
+	\store	\reg, [r0, #:pc_g2:(f - \cst)]
+
+	\store	\reg, [r0, #:sb_g0:(f - \cst)]
+	\store	\reg, [r0, #:sb_g1:(f - \cst)]
+	\store	\reg, [r0, #:sb_g2:(f - \cst)]
+
+	.endm
+
+	vfp_test flds fsts s0 0x1
+	vfp_test flds fsts s0 0x808
+
+@ FLDD/FSTD
+
+	vfp_test fldd fstd d0 0x1
+	vfp_test fldd fstd d0 0x808
+
+@ VLDR/VSTR
+
+	vfp_test vldr vstr d0 0x1
+	vfp_test vldr vstr d0 0x808
+
+@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
+
+	.cpu	ep9312
+
+	vfp_test cfldrs cfstrs mvf0 0x1
+	vfp_test cfldrd cfstrd mvd0 0x1
+	vfp_test cfldr32 cfstr32 mvfx0 0x1
+	vfp_test cfldr64 cfstr64 mvdx0 0x1
+
+	vfp_test cfldrs cfstrs mvf0 0x808
+	vfp_test cfldrd cfstrd mvd0 0x808
+	vfp_test cfldr32 cfstr32 mvfx0 0x808
+	vfp_test cfldr64 cfstr64 mvdx0 0x808
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d
new file mode 100644
index 000000000000..09e32997e855
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, parsing failures (ldc)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldc-parsing-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
new file mode 100644
index 000000000000..238d94db1d94
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l
@@ -0,0 +1,147 @@
+[^:]*: Assembler messages:
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]'
+[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]'
+[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:54: Error: too many positional arguments
+[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]'
+[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]'
+[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]'
+[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]'
+[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]'
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
new file mode 100644
index 000000000000..a815f5de75b5
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s
@@ -0,0 +1,67 @@
+@ Tests for LDC group relocations that are meant to fail during parsing.
+
+	.macro ldctest insn reg
+
+	\insn	0, \reg, [r0, #:pc_g0_nc:(sym)]
+	\insn	0, \reg, [r0, #:pc_g1_nc:(sym)]
+	\insn	0, \reg, [r0, #:sb_g0_nc:(sym)]
+	\insn	0, \reg, [r0, #:sb_g1_nc:(sym)]
+
+	\insn	0, \reg, [r0, #:foo:(sym)]
+
+	.endm
+
+	.macro ldctest2 insn reg
+
+	\insn	\reg, [r0, #:pc_g0_nc:(sym)]
+	\insn	\reg, [r0, #:pc_g1_nc:(sym)]
+	\insn	\reg, [r0, #:sb_g0_nc:(sym)]
+	\insn	\reg, [r0, #:sb_g1_nc:(sym)]
+
+	\insn	\reg, [r0, #:foo:(sym)]
+
+	.endm
+
+	ldctest ldc c0
+	ldctest ldcl c0
+	ldctest ldc2 c0
+	ldctest ldc2l c0
+
+	ldctest stc c0
+	ldctest stcl c0
+	ldctest stc2 c0
+	ldctest stc2l c0
+
+	.fpu 	fpa
+
+	ldctest2 ldfs f0
+	ldctest2 stfs f0
+	ldctest2 ldfd f0
+	ldctest2 stfd f0
+	ldctest2 ldfe f0
+	ldctest2 stfe f0
+	ldctest2 ldfp f0
+	ldctest2 stfp f0
+
+	.fpu	vfp
+
+	ldctest2 flds s0
+	ldctest2 fsts s0
+
+	ldctest2 fldd d0
+	ldctest2 fstd d0
+
+	ldctest2 vldr d0		FIXME
+	ldctest2 vstr d0
+
+	.cpu	ep9312
+
+	ldctest2 cfldrs mvf0
+	ldctest2 cfstrs mvf0
+	ldctest2 cfldrd mvd0
+	ldctest2 cfstrd mvd0
+	ldctest2 cfldr32 mvfx0
+	ldctest2 cfstr32 mvfx0
+	ldctest2 cfldr64 mvdx0
+	ldctest2 cfstr64 mvdx0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/arm/group-reloc-ldc.d
new file mode 100644
index 000000000000..731a025f0441
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.d
@@ -0,0 +1,727 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Group relocation tests (ldc)
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			10: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900085 	ldc	0, cr0, \[r0, #532\]
+			14: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			18: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			1c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			20: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			24: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			28: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800085 	stc	0, cr0, \[r0, #532\]
+			2c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			30: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			34: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			38: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			3c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			40: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100085 	ldc	0, cr0, \[r0, #-532\]
+			44: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			48: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			4c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			50: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			54: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			58: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000085 	stc	0, cr0, \[r0, #-532\]
+			5c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			60: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			64: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			68: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			6c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			70: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edd00085 	ldcl	0, cr0, \[r0, #532\]
+			74: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			78: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			7c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			80: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			84: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			88: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edc00085 	stcl	0, cr0, \[r0, #532\]
+			8c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			90: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			94: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			98: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			9c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			a0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed500085 	ldcl	0, cr0, \[r0, #-532\]
+			a4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			a8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			ac: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			b0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			b4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			b8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed400085 	stcl	0, cr0, \[r0, #-532\]
+			bc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			c0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			c4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			c8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			cc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			d0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd900085 	ldc2	0, cr0, \[r0, #532\]
+			d4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			d8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			dc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			e0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			e4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			e8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd800085 	stc2	0, cr0, \[r0, #532\]
+			ec: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			f0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			f4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			f8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			fc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			100: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd100085 	ldc2	0, cr0, \[r0, #-532\]
+			104: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			108: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			10c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			110: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			114: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			118: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd000085 	stc2	0, cr0, \[r0, #-532\]
+			11c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			120: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			124: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			128: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			12c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			130: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fdd00085 	ldc2l	0, cr0, \[r0, #532\]
+			134: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			138: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			13c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			140: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			144: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			148: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fdc00085 	stc2l	0, cr0, \[r0, #532\]
+			14c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			150: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			154: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			158: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			15c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			160: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd500085 	ldc2l	0, cr0, \[r0, #-532\]
+			164: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			168: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			16c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			170: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			174: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			178: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> fd400085 	stc2l	0, cr0, \[r0, #-532\]
+			17c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			180: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			184: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			188: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			18c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			190: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900185 	ldfs	f0, \[r0, #532\]
+			194: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			198: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			19c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			1a0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			1a4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			1a8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800185 	stfs	f0, \[r0, #532\]
+			1ac: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1b0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1b4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1b8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1bc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1c0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100185 	ldfs	f0, \[r0, #-532\]
+			1c4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1c8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1cc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1d0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1d4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1d8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000185 	stfs	f0, \[r0, #-532\]
+			1dc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1e0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1e4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1e8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1ec: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1f0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed908185 	ldfd	f0, \[r0, #532\]
+			1f4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			1f8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			1fc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			200: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			204: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			208: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed808185 	stfd	f0, \[r0, #532\]
+			20c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			210: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			214: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			218: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			21c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			220: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed108185 	ldfd	f0, \[r0, #-532\]
+			224: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			228: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			22c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			230: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			234: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			238: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed008185 	stfd	f0, \[r0, #-532\]
+			23c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			240: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			244: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			248: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			24c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			250: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edd00185 	ldfe	f0, \[r0, #532\]
+			254: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			258: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			25c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			260: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			264: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			268: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edc00185 	stfe	f0, \[r0, #532\]
+			26c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			270: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			274: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			278: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			27c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			280: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed500185 	ldfe	f0, \[r0, #-532\]
+			284: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			288: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			28c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			290: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			294: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			298: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed400185 	stfe	f0, \[r0, #-532\]
+			29c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2a0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2a4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2a8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2ac: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2b0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edd08185 	ldfp	f0, \[r0, #532\]
+			2b4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2b8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2bc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2c0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2c4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2c8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edc08185 	stfp	f0, \[r0, #532\]
+			2cc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2d0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2d4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2d8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2dc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2e0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed508185 	ldfp	f0, \[r0, #-532\]
+			2e4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2e8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2ec: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2f0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2f4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2f8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed408185 	stfp	f0, \[r0, #-532\]
+			2fc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			300: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			304: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			308: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			30c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			310: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900a85 	flds	s0, \[r0, #532\]
+			314: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			318: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			31c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			320: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			324: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			328: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800a85 	fsts	s0, \[r0, #532\]
+			32c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			330: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			334: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			338: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			33c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			340: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100a85 	flds	s0, \[r0, #-532\]
+			344: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			348: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			34c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			350: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			354: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			358: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000a85 	fsts	s0, \[r0, #-532\]
+			35c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			360: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			364: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			368: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			36c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			370: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			374: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			378: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			37c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			380: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			384: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			388: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			38c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			390: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			394: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			398: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			39c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3a0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3a4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3a8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3ac: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3b0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3b4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3b8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			3bc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3c0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3c4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3c8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3cc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3d0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900b85 	vldr	d0, \[r0, #532\]
+			3d4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3d8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3dc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3e0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3e4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3e8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800b85 	vstr	d0, \[r0, #532\]
+			3ec: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3f0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3f4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3f8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			3fc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			400: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100b85 	vldr	d0, \[r0, #-532\]
+			404: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			408: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			40c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			410: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			414: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			418: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000b85 	vstr	d0, \[r0, #-532\]
+			41c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			420: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			424: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			428: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			42c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			430: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900485 	cfldrs	mvf0, \[r0, #532\]
+			434: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			438: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			43c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			440: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			444: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			448: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800485 	cfstrs	mvf0, \[r0, #532\]
+			44c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			450: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			454: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			458: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			45c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			460: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100485 	cfldrs	mvf0, \[r0, #-532\]
+			464: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			468: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			46c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			470: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			474: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			478: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000485 	cfstrs	mvf0, \[r0, #-532\]
+			47c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			480: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			484: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			488: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			48c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			490: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edd00485 	cfldrd	mvd0, \[r0, #532\]
+			494: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			498: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			49c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			4a0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			4a4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			4a8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edc00485 	cfstrd	mvd0, \[r0, #532\]
+			4ac: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4b0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4b4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4b8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4bc: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4c0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed500485 	cfldrd	mvd0, \[r0, #-532\]
+			4c4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4c8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4cc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4d0: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4d4: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4d8: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed400485 	cfstrd	mvd0, \[r0, #-532\]
+			4dc: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4e0: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4e4: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4e8: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4ec: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4f0: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed900585 	cfldr32	mvfx0, \[r0, #532\]
+			4f4: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			4f8: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			4fc: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			500: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			504: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			508: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed800585 	cfstr32	mvfx0, \[r0, #532\]
+			50c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			510: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			514: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			518: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			51c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			520: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed100585 	cfldr32	mvfx0, \[r0, #-532\]
+			524: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			528: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			52c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			530: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			534: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			538: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed000585 	cfstr32	mvfx0, \[r0, #-532\]
+			53c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			540: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			544: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			548: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			54c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			550: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edd00585 	cfldr64	mvdx0, \[r0, #532\]
+			554: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			558: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			55c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			560: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			564: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			568: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> edc00585 	cfstr64	mvdx0, \[r0, #532\]
+			56c: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			570: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			574: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			578: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			57c: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			580: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed500585 	cfldr64	mvdx0, \[r0, #-532\]
+			584: R_ARM_LDC_SB_G2	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			588: R_ARM_LDC_PC_G0	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			58c: R_ARM_LDC_PC_G1	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			590: R_ARM_LDC_PC_G2	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			594: R_ARM_LDC_SB_G0	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			598: R_ARM_LDC_SB_G1	f
+0[0-9a-f]+ <[^>]+> ed400585 	cfstr64	mvdx0, \[r0, #-532\]
+			59c: R_ARM_LDC_SB_G2	f
diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/arm/group-reloc-ldc.s
new file mode 100644
index 000000000000..df27aaf55e07
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldc.s
@@ -0,0 +1,151 @@
+@ LDC group relocation tests.
+
+	.text
+
+@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
+
+	.macro ldctest load store
+
+	\load	0, c0, [r0, #:pc_g0:(f + 0x214)]
+	\load	0, c0, [r0, #:pc_g1:(f + 0x214)]
+	\load	0, c0, [r0, #:pc_g2:(f + 0x214)]
+
+	\load	0, c0, [r0, #:sb_g0:(f + 0x214)]
+	\load	0, c0, [r0, #:sb_g1:(f + 0x214)]
+	\load	0, c0, [r0, #:sb_g2:(f + 0x214)]
+
+	\store	0, c0, [r0, #:pc_g0:(f + 0x214)]
+	\store	0, c0, [r0, #:pc_g1:(f + 0x214)]
+	\store	0, c0, [r0, #:pc_g2:(f + 0x214)]
+
+	\store	0, c0, [r0, #:sb_g0:(f + 0x214)]
+	\store	0, c0, [r0, #:sb_g1:(f + 0x214)]
+	\store	0, c0, [r0, #:sb_g2:(f + 0x214)]
+
+	\load	0, c0, [r0, #:pc_g0:(f - 0x214)]
+	\load	0, c0, [r0, #:pc_g1:(f - 0x214)]
+	\load	0, c0, [r0, #:pc_g2:(f - 0x214)]
+
+	\load	0, c0, [r0, #:sb_g0:(f - 0x214)]
+	\load	0, c0, [r0, #:sb_g1:(f - 0x214)]
+	\load	0, c0, [r0, #:sb_g2:(f - 0x214)]
+
+	\store	0, c0, [r0, #:pc_g0:(f - 0x214)]
+	\store	0, c0, [r0, #:pc_g1:(f - 0x214)]
+	\store	0, c0, [r0, #:pc_g2:(f - 0x214)]
+
+	\store	0, c0, [r0, #:sb_g0:(f - 0x214)]
+	\store	0, c0, [r0, #:sb_g1:(f - 0x214)]
+	\store	0, c0, [r0, #:sb_g2:(f - 0x214)]
+
+	.endm
+
+	ldctest ldc stc
+	ldctest ldcl stcl
+	ldctest ldc2 stc2
+	ldctest ldc2l stc2l
+
+@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
+
+	.fpu	fpa
+
+	.macro	fpa_test load store
+
+	\load	f0, [r0, #:pc_g0:(f + 0x214)]
+	\load	f0, [r0, #:pc_g1:(f + 0x214)]
+	\load	f0, [r0, #:pc_g2:(f + 0x214)]
+
+	\load	f0, [r0, #:sb_g0:(f + 0x214)]
+	\load	f0, [r0, #:sb_g1:(f + 0x214)]
+	\load	f0, [r0, #:sb_g2:(f + 0x214)]
+
+	\store	f0, [r0, #:pc_g0:(f + 0x214)]
+	\store	f0, [r0, #:pc_g1:(f + 0x214)]
+	\store	f0, [r0, #:pc_g2:(f + 0x214)]
+
+	\store	f0, [r0, #:sb_g0:(f + 0x214)]
+	\store	f0, [r0, #:sb_g1:(f + 0x214)]
+	\store	f0, [r0, #:sb_g2:(f + 0x214)]
+
+	\load	f0, [r0, #:pc_g0:(f - 0x214)]
+	\load	f0, [r0, #:pc_g1:(f - 0x214)]
+	\load	f0, [r0, #:pc_g2:(f - 0x214)]
+
+	\load	f0, [r0, #:sb_g0:(f - 0x214)]
+	\load	f0, [r0, #:sb_g1:(f - 0x214)]
+	\load	f0, [r0, #:sb_g2:(f - 0x214)]
+
+	\store	f0, [r0, #:pc_g0:(f - 0x214)]
+	\store	f0, [r0, #:pc_g1:(f - 0x214)]
+	\store	f0, [r0, #:pc_g2:(f - 0x214)]
+
+	\store	f0, [r0, #:sb_g0:(f - 0x214)]
+	\store	f0, [r0, #:sb_g1:(f - 0x214)]
+	\store	f0, [r0, #:sb_g2:(f - 0x214)]
+
+	.endm
+
+	fpa_test ldfs stfs
+	fpa_test ldfd stfd
+	fpa_test ldfe stfe
+	fpa_test ldfp stfp
+
+@ FLDS/FSTS
+
+	.fpu	vfp
+
+	.macro vfp_test load store reg
+
+	\load	\reg, [r0, #:pc_g0:(f + 0x214)]
+	\load	\reg, [r0, #:pc_g1:(f + 0x214)]
+	\load	\reg, [r0, #:pc_g2:(f + 0x214)]
+
+	\load	\reg, [r0, #:sb_g0:(f + 0x214)]
+	\load	\reg, [r0, #:sb_g1:(f + 0x214)]
+	\load	\reg, [r0, #:sb_g2:(f + 0x214)]
+
+	\store	\reg, [r0, #:pc_g0:(f + 0x214)]
+	\store	\reg, [r0, #:pc_g1:(f + 0x214)]
+	\store	\reg, [r0, #:pc_g2:(f + 0x214)]
+
+	\store	\reg, [r0, #:sb_g0:(f + 0x214)]
+	\store	\reg, [r0, #:sb_g1:(f + 0x214)]
+	\store	\reg, [r0, #:sb_g2:(f + 0x214)]
+
+	\load	\reg, [r0, #:pc_g0:(f - 0x214)]
+	\load	\reg, [r0, #:pc_g1:(f - 0x214)]
+	\load	\reg, [r0, #:pc_g2:(f - 0x214)]
+
+	\load	\reg, [r0, #:sb_g0:(f - 0x214)]
+	\load	\reg, [r0, #:sb_g1:(f - 0x214)]
+	\load	\reg, [r0, #:sb_g2:(f - 0x214)]
+
+	\store	\reg, [r0, #:pc_g0:(f - 0x214)]
+	\store	\reg, [r0, #:pc_g1:(f - 0x214)]
+	\store	\reg, [r0, #:pc_g2:(f - 0x214)]
+
+	\store	\reg, [r0, #:sb_g0:(f - 0x214)]
+	\store	\reg, [r0, #:sb_g1:(f - 0x214)]
+	\store	\reg, [r0, #:sb_g2:(f - 0x214)]
+
+	.endm
+
+	vfp_test flds fsts s0
+
+@ FLDD/FSTD
+
+	vfp_test fldd fstd d0
+
+@ VLDR/VSTR
+
+	vfp_test vldr vstr d0
+
+@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
+
+	.cpu	ep9312
+
+	vfp_test cfldrs cfstrs mvf0
+	vfp_test cfldrd cfstrd mvd0
+	vfp_test cfldr32 cfstr32 mvfx0
+	vfp_test cfldr64 cfstr64 mvdx0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d
new file mode 100644
index 000000000000..49ba77478e44
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, encoding failures (ldr)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldr-encoding-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l
new file mode 100644
index 000000000000..276a341dc34d
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l
@@ -0,0 +1,97 @@
+[^:]*: Assembler messages:
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s
new file mode 100644
index 000000000000..3c528f19975b
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s
@@ -0,0 +1,39 @@
+@ Tests that are supposed to fail during encoding
+@ for LDR group relocations.
+
+	.text
+
+	.macro ldrtest load store sym offset
+
+	\load	r0, [r0, #:pc_g0:(\sym \offset)]
+	\load	r0, [r0, #:pc_g1:(\sym \offset)]
+	\load	r0, [r0, #:pc_g2:(\sym \offset)]
+	\load	r0, [r0, #:sb_g0:(\sym \offset)]
+	\load	r0, [r0, #:sb_g1:(\sym \offset)]
+	\load	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	\store	r0, [r0, #:pc_g0:(\sym \offset)]
+	\store	r0, [r0, #:pc_g1:(\sym \offset)]
+	\store	r0, [r0, #:pc_g2:(\sym \offset)]
+	\store	r0, [r0, #:sb_g0:(\sym \offset)]
+	\store	r0, [r0, #:sb_g1:(\sym \offset)]
+	\store	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
+@ So these should all fail.
+
+	ldrtest ldr str f "+ 4096"
+	ldrtest ldrb strb f "+ 4096"
+	ldrtest ldr str f "- 4096"
+	ldrtest ldrb strb f "- 4096"
+
+	ldrtest ldr str localsym "+ 4096"
+	ldrtest ldrb strb localsym "+ 4096"
+	ldrtest ldr str localsym "- 4096"
+	ldrtest ldrb strb localsym "- 4096"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d
new file mode 100644
index 000000000000..fa0941e80a9e
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, parsing failures (ldr)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldr-parsing-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l
new file mode 100644
index 000000000000..316a6a6c8d8d
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l
@@ -0,0 +1,21 @@
+[^:]*: Assembler messages:
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]'
+[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]'
+[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]'
+[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]'
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s
new file mode 100644
index 000000000000..c7d0ba759651
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s
@@ -0,0 +1,33 @@
+@ Tests that are supposed to fail during parsing of LDR group relocations.
+
+	.text
+
+@ No NC variants exist for the LDR relocations.
+
+	ldr	r0, [r0, #:pc_g0_nc:(f)]
+	ldr	r0, [r0, #:pc_g1_nc:(f)]
+	ldr	r0, [r0, #:sb_g0_nc:(f)]
+	ldr	r0, [r0, #:sb_g1_nc:(f)]
+
+	str	r0, [r0, #:pc_g0_nc:(f)]
+	str	r0, [r0, #:pc_g1_nc:(f)]
+	str	r0, [r0, #:sb_g0_nc:(f)]
+	str	r0, [r0, #:sb_g1_nc:(f)]
+
+	ldrb	r0, [r0, #:pc_g0_nc:(f)]
+	ldrb	r0, [r0, #:pc_g1_nc:(f)]
+	ldrb	r0, [r0, #:sb_g0_nc:(f)]
+	ldrb	r0, [r0, #:sb_g1_nc:(f)]
+
+	strb	r0, [r0, #:pc_g0_nc:(f)]
+	strb	r0, [r0, #:pc_g1_nc:(f)]
+	strb	r0, [r0, #:sb_g0_nc:(f)]
+	strb	r0, [r0, #:sb_g1_nc:(f)]
+
+@ Instructions with a gibberish relocation code.
+
+	ldr	r0, [r0, #:foo:(f)]
+	str	r0, [r0, #:foo:(f)]
+	ldrb	r0, [r0, #:foo:(f)]
+	strb	r0, [r0, #:foo:(f)]
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.d b/gas/testsuite/gas/arm/group-reloc-ldr.d
new file mode 100644
index 000000000000..cfc1b235cb6c
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr.d
@@ -0,0 +1,200 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Group relocation tests (ldr)
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			0: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			4: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			8: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			c: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			10: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			14: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			18: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			1c: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			20: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			24: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			28: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			2c: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			30: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			34: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			38: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			3c: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			40: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			44: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			48: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			4c: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			50: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			54: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			58: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			5c: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			60: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			64: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			68: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			6c: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			70: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			74: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			78: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			7c: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			80: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			84: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			88: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			8c: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			90: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			94: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			98: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			9c: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			a0: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			a4: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			a8: R_ARM_LDR_PC_G0	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			ac: R_ARM_LDR_PC_G1	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			b0: R_ARM_LDR_PC_G2	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			b4: R_ARM_LDR_SB_G0	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			b8: R_ARM_LDR_SB_G1	f
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			bc: R_ARM_LDR_SB_G2	f
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			c0: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			c4: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			c8: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			cc: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			d0: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5900fff 	ldr	r0, \[r0, #4095\]
+			d4: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			d8: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			dc: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			e0: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			e4: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			e8: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5800fff 	str	r0, \[r0, #4095\]
+			ec: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			f0: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			f4: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			f8: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			fc: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			100: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5d00fff 	ldrb	r0, \[r0, #4095\]
+			104: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			108: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			10c: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			110: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			114: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			118: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5c00fff 	strb	r0, \[r0, #4095\]
+			11c: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			120: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			124: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			128: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			12c: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			130: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5100fff 	ldr	r0, \[r0, #-4095\]
+			134: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			138: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			13c: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			140: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			144: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			148: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5000fff 	str	r0, \[r0, #-4095\]
+			14c: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			150: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			154: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			158: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			15c: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			160: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5500fff 	ldrb	r0, \[r0, #-4095\]
+			164: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			168: R_ARM_LDR_PC_G0	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			16c: R_ARM_LDR_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			170: R_ARM_LDR_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			174: R_ARM_LDR_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			178: R_ARM_LDR_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e5400fff 	strb	r0, \[r0, #-4095\]
+			17c: R_ARM_LDR_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e3a00000 	mov	r0, #0	; 0x0
diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.s b/gas/testsuite/gas/arm/group-reloc-ldr.s
new file mode 100644
index 000000000000..389042d70aff
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldr.s
@@ -0,0 +1,41 @@
+@ Tests for LDR group relocations.
+
+	.text
+
+	.macro ldrtest load store sym offset
+
+	\load	r0, [r0, #:pc_g0:(\sym \offset)]
+	\load	r0, [r0, #:pc_g1:(\sym \offset)]
+	\load	r0, [r0, #:pc_g2:(\sym \offset)]
+	\load	r0, [r0, #:sb_g0:(\sym \offset)]
+	\load	r0, [r0, #:sb_g1:(\sym \offset)]
+	\load	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	\store	r0, [r0, #:pc_g0:(\sym \offset)]
+	\store	r0, [r0, #:pc_g1:(\sym \offset)]
+	\store	r0, [r0, #:pc_g2:(\sym \offset)]
+	\store	r0, [r0, #:sb_g0:(\sym \offset)]
+	\store	r0, [r0, #:sb_g1:(\sym \offset)]
+	\store	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
+@ So these should all (just) work.
+
+	ldrtest ldr str f "+ 4095"
+	ldrtest ldrb strb f "+ 4095"
+	ldrtest ldr str f "- 4095"
+	ldrtest ldrb strb f "- 4095"
+
+@ The same as the above, but for a local symbol.  These should not be
+@ resolved by the assembler but instead left to the linker.
+
+	ldrtest ldr str localsym "+ 4095"
+	ldrtest ldrb strb localsym "+ 4095"
+	ldrtest ldr str localsym "- 4095"
+	ldrtest ldrb strb localsym "- 4095"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d
new file mode 100644
index 000000000000..ff8babf8d5a3
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, encoding failures (ldrs)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldrs-encoding-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l
new file mode 100644
index 000000000000..2621002d2ee4
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l
@@ -0,0 +1,121 @@
+[^:]*: Assembler messages:
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
+[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s
new file mode 100644
index 000000000000..ac7a90f0e9e2
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s
@@ -0,0 +1,54 @@
+@ Tests that are meant to fail during encoding of LDRS group relocations.
+
+	.text
+
+	.macro ldrtest2 load sym offset
+
+	\load	r0, [r0, #:pc_g1:(\sym \offset)]
+	\load	r0, [r0, #:pc_g2:(\sym \offset)]
+	\load	r0, [r0, #:sb_g0:(\sym \offset)]
+	\load	r0, [r0, #:sb_g1:(\sym \offset)]
+	\load	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+	.macro ldrtest load store sym offset
+
+	ldrtest2 \load \sym \offset
+
+	\store	r0, [r0, #:pc_g1:(\sym \offset)]
+	\store	r0, [r0, #:pc_g2:(\sym \offset)]
+	\store	r0, [r0, #:sb_g0:(\sym \offset)]
+	\store	r0, [r0, #:sb_g1:(\sym \offset)]
+	\store	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the 
+@ magnitude of the addend.  So these should all (just) fail.
+
+	ldrtest ldrd strd f "+ 256"
+	ldrtest ldrh strh f "+ 256"
+	ldrtest2 ldrsh f "+ 256"
+	ldrtest2 ldrsb f "+ 256"
+
+	ldrtest ldrd strd f "- 256"
+	ldrtest ldrh strh f "- 256"
+	ldrtest2 ldrsh f "- 256"
+	ldrtest2 ldrsb f "- 256"
+
+@ The same as the above, but for a local symbol.
+
+	ldrtest ldrd strd localsym "+ 256"
+	ldrtest ldrh strh localsym "+ 256"
+	ldrtest2 ldrsh localsym "+ 256"
+	ldrtest2 ldrsb localsym "+ 256"
+
+	ldrtest ldrd strd localsym "- 256"
+	ldrtest ldrh strh localsym "- 256"
+	ldrtest2 ldrsh localsym "- 256"
+	ldrtest2 ldrsb localsym "- 256"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d
new file mode 100644
index 000000000000..cb46d8465d1e
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d
@@ -0,0 +1,3 @@
+#name: Group relocation tests, parsing failures (ldrs)
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: group-reloc-ldrs-parsing-bad.l
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l
new file mode 100644
index 000000000000..b3d60351f198
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l
@@ -0,0 +1,31 @@
+[^:]*: Assembler messages:
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]'
+[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]'
+[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]'
+[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]'
+[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]'
+[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]'
+[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]'
+[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]'
+[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]'
+[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]'
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s
new file mode 100644
index 000000000000..16c1bea5ecfc
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s
@@ -0,0 +1,44 @@
+@ Tests that are supposed to fail during parsing of LDRS group relocations.
+
+	.text
+
+@ No NC variants exist for the LDRS relocations.
+
+	ldrd	r0, [r0, #:pc_g0_nc:(f)]
+	ldrd	r0, [r0, #:pc_g1_nc:(f)]
+	ldrd	r0, [r0, #:sb_g0_nc:(f)]
+	ldrd	r0, [r0, #:sb_g1_nc:(f)]
+
+	strd	r0, [r0, #:pc_g0_nc:(f)]
+	strd	r0, [r0, #:pc_g1_nc:(f)]
+	strd	r0, [r0, #:sb_g0_nc:(f)]
+	strd	r0, [r0, #:sb_g1_nc:(f)]
+
+	ldrh	r0, [r0, #:pc_g0_nc:(f)]
+	ldrh	r0, [r0, #:pc_g1_nc:(f)]
+	ldrh	r0, [r0, #:sb_g0_nc:(f)]
+	ldrh	r0, [r0, #:sb_g1_nc:(f)]
+
+	strh	r0, [r0, #:pc_g0_nc:(f)]
+	strh	r0, [r0, #:pc_g1_nc:(f)]
+	strh	r0, [r0, #:sb_g0_nc:(f)]
+	strh	r0, [r0, #:sb_g1_nc:(f)]
+
+	ldrsh	r0, [r0, #:pc_g0_nc:(f)]
+	ldrsh	r0, [r0, #:pc_g1_nc:(f)]
+	ldrsh	r0, [r0, #:sb_g0_nc:(f)]
+	ldrsh	r0, [r0, #:sb_g1_nc:(f)]
+
+	ldrsb	r0, [r0, #:pc_g0_nc:(f)]
+	ldrsb	r0, [r0, #:pc_g1_nc:(f)]
+	ldrsb	r0, [r0, #:sb_g0_nc:(f)]
+	ldrsb	r0, [r0, #:sb_g1_nc:(f)]
+
+@ Instructions with a gibberish relocation code.
+	ldrd	r0, [r0, #:foo:(f)]
+	strd	r0, [r0, #:foo:(f)]
+	ldrh	r0, [r0, #:foo:(f)]
+	strh	r0, [r0, #:foo:(f)]
+	ldrsh	r0, [r0, #:foo:(f)]
+	ldrsb	r0, [r0, #:foo:(f)]
+
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d
new file mode 100644
index 000000000000..9896f4bdb6f6
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d
@@ -0,0 +1,248 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#name: Group relocation tests (ldrs)
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			0: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			4: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			8: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			c: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			10: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			14: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			18: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			1c: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			20: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			24: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			28: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			2c: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			30: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			34: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			38: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			3c: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			40: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			44: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			48: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			4c: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			50: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			54: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			58: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			5c: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			60: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			64: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			68: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			6c: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			70: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			74: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			78: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			7c: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			80: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			84: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			88: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			8c: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			90: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			94: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			98: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			9c: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			a0: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			a4: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			a8: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			ac: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			b0: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			b4: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			b8: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			bc: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			c0: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			c4: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			c8: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			cc: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			d0: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			d4: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			d8: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			dc: R_ARM_LDRS_PC_G1	f
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			e0: R_ARM_LDRS_PC_G2	f
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			e4: R_ARM_LDRS_SB_G0	f
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			e8: R_ARM_LDRS_SB_G1	f
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			ec: R_ARM_LDRS_SB_G2	f
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			f0: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			f4: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			f8: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			fc: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fdf 	ldrd	r0, \[r0, #255\]
+			100: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			104: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			108: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			10c: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			110: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fff 	strd	r0, \[r0, #255\]
+			114: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			118: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			11c: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			120: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			124: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fbf 	ldrh	r0, \[r0, #255\]
+			128: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			12c: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			130: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			134: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			138: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1c00fbf 	strh	r0, \[r0, #255\]
+			13c: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			140: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			144: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			148: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			14c: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fff 	ldrsh	r0, \[r0, #255\]
+			150: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			154: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			158: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			15c: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			160: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1d00fdf 	ldrsb	r0, \[r0, #255\]
+			164: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			168: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			16c: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			170: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			174: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fdf 	ldrd	r0, \[r0, #-255\]
+			178: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			17c: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			180: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			184: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			188: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fff 	strd	r0, \[r0, #-255\]
+			18c: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			190: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			194: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			198: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			19c: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fbf 	ldrh	r0, \[r0, #-255\]
+			1a0: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			1a4: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			1a8: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			1ac: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			1b0: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1400fbf 	strh	r0, \[r0, #-255\]
+			1b4: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			1b8: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			1bc: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			1c0: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			1c4: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fff 	ldrsh	r0, \[r0, #-255\]
+			1c8: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			1cc: R_ARM_LDRS_PC_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			1d0: R_ARM_LDRS_PC_G2	localsym
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			1d4: R_ARM_LDRS_SB_G0	localsym
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			1d8: R_ARM_LDRS_SB_G1	localsym
+0[0-9a-f]+ <[^>]+> e1500fdf 	ldrsb	r0, \[r0, #-255\]
+			1dc: R_ARM_LDRS_SB_G2	localsym
+0[0-9a-f]+ <[^>]+> e3a00000 	mov	r0, #0	; 0x0
diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.s b/gas/testsuite/gas/arm/group-reloc-ldrs.s
new file mode 100644
index 000000000000..fa74e7eabe0a
--- /dev/null
+++ b/gas/testsuite/gas/arm/group-reloc-ldrs.s
@@ -0,0 +1,54 @@
+@ Tests for LDRS group relocations.
+
+	.text
+
+	.macro ldrtest2 load sym offset
+
+	\load	r0, [r0, #:pc_g1:(\sym \offset)]
+	\load	r0, [r0, #:pc_g2:(\sym \offset)]
+	\load	r0, [r0, #:sb_g0:(\sym \offset)]
+	\load	r0, [r0, #:sb_g1:(\sym \offset)]
+	\load	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+	.macro ldrtest load store sym offset
+
+	ldrtest2 \load \sym \offset
+
+	\store	r0, [r0, #:pc_g1:(\sym \offset)]
+	\store	r0, [r0, #:pc_g2:(\sym \offset)]
+	\store	r0, [r0, #:sb_g0:(\sym \offset)]
+	\store	r0, [r0, #:sb_g1:(\sym \offset)]
+	\store	r0, [r0, #:sb_g2:(\sym \offset)]
+
+	.endm
+
+@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the 
+@ magnitude of the addend.  So these should all (just) work.
+
+	ldrtest ldrd strd f "+ 255"
+	ldrtest ldrh strh f "+ 255"
+	ldrtest2 ldrsh f "+ 255"
+	ldrtest2 ldrsb f "+ 255"
+
+	ldrtest ldrd strd f "- 255"
+	ldrtest ldrh strh f "- 255"
+	ldrtest2 ldrsh f "- 255"
+	ldrtest2 ldrsb f "- 255"
+
+@ The same as the above, but for a local symbol.
+
+	ldrtest ldrd strd localsym "+ 255"
+	ldrtest ldrh strh localsym "+ 255"
+	ldrtest2 ldrsh localsym "+ 255"
+	ldrtest2 ldrsb localsym "+ 255"
+
+	ldrtest ldrd strd localsym "- 255"
+	ldrtest ldrh strh localsym "- 255"
+	ldrtest2 ldrsh localsym "- 255"
+	ldrtest2 ldrsb localsym "- 255"
+
+localsym:
+	mov	r0, #0
+
diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d
index fbf27b4ab8db..4d56e8eca3d2 100644
--- a/gas/testsuite/gas/arm/inst.d
+++ b/gas/testsuite/gas/arm/inst.d
@@ -11,11 +11,11 @@
 Disassembly of section .text:
 0+000 <[^>]*> e3a00000 ?	mov	r0, #0	; 0x0
 0+004 <[^>]*> e1a01002 ?	mov	r1, r2
-0+008 <[^>]*> e1a03184 ?	mov	r3, r4, lsl #3
-0+00c <[^>]*> e1a05736 ?	mov	r5, r6, lsr r7
-0+010 <[^>]*> e1a08a59 ?	mov	r8, r9, asr sl
-0+014 <[^>]*> e1a0bd1c ?	mov	fp, ip, lsl sp
-0+018 <[^>]*> e1a0e06f ?	mov	lr, pc, rrx
+0+008 <[^>]*> e1a03184 ?	lsl	r3, r4, #3
+0+00c <[^>]*> e1a05736 ?	lsr	r5, r6, r7
+0+010 <[^>]*> e1a08a59 ?	asr	r8, r9, sl
+0+014 <[^>]*> e1a0bd1c ?	lsl	fp, ip, sp
+0+018 <[^>]*> e1a0e06f ?	rrx	lr, pc
 0+01c <[^>]*> e1a01002 ?	mov	r1, r2
 0+020 <[^>]*> 01a02003 ?	moveq	r2, r3
 0+024 <[^>]*> 11a04005 ?	movne	r4, r5
@@ -28,13 +28,13 @@ Disassembly of section .text:
 0+040 <[^>]*> 41a03006 ?	movmi	r3, r6
 0+044 <[^>]*> 51a07009 ?	movpl	r7, r9
 0+048 <[^>]*> 61a01008 ?	movvs	r1, r8
-0+04c <[^>]*> 71a09fa1 ?	movvc	r9, r1, lsr #31
+0+04c <[^>]*> 71a09fa1 ?	lsrvc	r9, r1, #31
 0+050 <[^>]*> 81a0800f ?	movhi	r8, pc
 0+054 <[^>]*> 91a0f00e ?	movls	pc, lr
 0+058 <[^>]*> 21a09008 ?	movcs	r9, r8
 0+05c <[^>]*> 31a01003 ?	movcc	r1, r3
 0+060 <[^>]*> e1b00008 ?	movs	r0, r8
-0+064 <[^>]*> 31b00007 ?	movccs	r0, r7
+0+064 <[^>]*> 31b00007 ?	movscc	r0, r7
 0+068 <[^>]*> e281000a ?	add	r0, r1, #10	; 0xa
 0+06c <[^>]*> e0832004 ?	add	r2, r3, r4
 0+070 <[^>]*> e0865287 ?	add	r5, r6, r7, lsl #5
@@ -114,11 +114,11 @@ Disassembly of section .text:
 0+198 <[^>]*> e0000291 ?	mul	r0, r1, r2
 0+19c <[^>]*> e0110392 ?	muls	r1, r2, r3
 0+1a0 <[^>]*> 10000091 ?	mulne	r0, r1, r0
-0+1a4 <[^>]*> 90190798 ?	mullss	r9, r8, r7
+0+1a4 <[^>]*> 90190798 ?	mulsls	r9, r8, r7
 0+1a8 <[^>]*> e021ba99 ?	mla	r1, r9, sl, fp
 0+1ac <[^>]*> e033c994 ?	mlas	r3, r4, r9, ip
 0+1b0 <[^>]*> b029d798 ?	mlalt	r9, r8, r7, sp
-0+1b4 <[^>]*> a034e391 ?	mlages	r4, r1, r3, lr
+0+1b4 <[^>]*> a034e391 ?	mlasge	r4, r1, r3, lr
 0+1b8 <[^>]*> e5910000 ?	ldr	r0, \[r1\]
 0+1bc <[^>]*> e7911002 ?	ldr	r1, \[r1, r2\]
 0+1c0 <[^>]*> e7b32004 ?	ldr	r2, \[r3, r4\]!
@@ -130,7 +130,7 @@ Disassembly of section .text:
 0+1d8 <[^>]*> e6942425 ?	ldr	r2, \[r4\], r5, lsr #8
 0+1dc <[^>]*> e51f0008 ?	ldr	r0, \[pc, #-8\]	; 0+1dc <[^>]*>
 0+1e0 <[^>]*> e5d43000 ?	ldrb	r3, \[r4\]
-0+1e4 <[^>]*> 14f85000 ?	ldrnebt	r5, \[r8\]
+0+1e4 <[^>]*> 14f85000 ?	ldrbtne	r5, \[r8\]
 0+1e8 <[^>]*> e5810000 ?	str	r0, \[r1\]
 0+1ec <[^>]*> e7811002 ?	str	r1, \[r1, r2\]
 0+1f0 <[^>]*> e7a43003 ?	str	r3, \[r4, r3\]!
@@ -143,21 +143,21 @@ Disassembly of section .text:
 0+20c <[^>]*> e50f1004 ?	str	r1, \[pc, #-4\]	; 0+210 <[^>]*>
 0+210 <[^>]*> e5c71000 ?	strb	r1, \[r7\]
 0+214 <[^>]*> e4e02000 ?	strbt	r2, \[r0\]
-0+218 <[^>]*> e8900002 ?	ldmia	r0, {r1}
-0+21c <[^>]*> 09920038 ?	ldmeqib	r2, {r3, r4, r5}
+0+218 <[^>]*> e8900002 ?	ldm	r0, {r1}
+0+21c <[^>]*> 09920038 ?	ldmibeq	r2, {r3, r4, r5}
 0+220 <[^>]*> e853ffff ?	ldmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
 0+224 <[^>]*> e93b05ff ?	ldmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
 0+228 <[^>]*> e99100f7 ?	ldmib	r1, {r0, r1, r2, r4, r5, r6, r7}
-0+22c <[^>]*> e89201f8 ?	ldmia	r2, {r3, r4, r5, r6, r7, r8}
+0+22c <[^>]*> e89201f8 ?	ldm	r2, {r3, r4, r5, r6, r7, r8}
 0+230 <[^>]*> e9130003 ?	ldmdb	r3, {r0, r1}
 0+234 <[^>]*> e8540300 ?	ldmda	r4, {r8, r9}\^
-0+238 <[^>]*> e8800002 ?	stmia	r0, {r1}
-0+23c <[^>]*> 09820038 ?	stmeqib	r2, {r3, r4, r5}
+0+238 <[^>]*> e8800002 ?	stm	r0, {r1}
+0+23c <[^>]*> 09820038 ?	stmibeq	r2, {r3, r4, r5}
 0+240 <[^>]*> e843ffff ?	stmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
 0+244 <[^>]*> e92b05ff ?	stmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
 0+248 <[^>]*> e8010007 ?	stmda	r1, {r0, r1, r2}
 0+24c <[^>]*> e9020018 ?	stmdb	r2, {r3, r4}
-0+250 <[^>]*> e8830003 ?	stmia	r3, {r0, r1}
+0+250 <[^>]*> e8830003 ?	stm	r3, {r0, r1}
 0+254 <[^>]*> e9c40300 ?	stmib	r4, {r8, r9}\^
 0+258 <[^>]*> ef123456 ?	(swi|svc)	0x00123456
 0+25c <[^>]*> 2f000033 ?	(swi|svc)cs	0x00000033
@@ -169,35 +169,35 @@ Disassembly of section .text:
 [		]*268:.*_wibble.*
 0+26c <[^>]*> da...... ?	ble	0[0123456789abcdef]+ <[^>]*>
 [		]*26c:.*testerfunc.*
-0+270 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
+0+270 <[^>]*> e1a01102 ?	lsl	r1, r2, #2
 0+274 <[^>]*> e1a01002 ?	mov	r1, r2
-0+278 <[^>]*> e1a01f82 ?	mov	r1, r2, lsl #31
-0+27c <[^>]*> e1a01312 ?	mov	r1, r2, lsl r3
-0+280 <[^>]*> e1a01122 ?	mov	r1, r2, lsr #2
-0+284 <[^>]*> e1a01fa2 ?	mov	r1, r2, lsr #31
-0+288 <[^>]*> e1a01022 ?	mov	r1, r2, lsr #32
-0+28c <[^>]*> e1a01332 ?	mov	r1, r2, lsr r3
-0+290 <[^>]*> e1a01142 ?	mov	r1, r2, asr #2
-0+294 <[^>]*> e1a01fc2 ?	mov	r1, r2, asr #31
-0+298 <[^>]*> e1a01042 ?	mov	r1, r2, asr #32
-0+29c <[^>]*> e1a01352 ?	mov	r1, r2, asr r3
-0+2a0 <[^>]*> e1a01162 ?	mov	r1, r2, ror #2
-0+2a4 <[^>]*> e1a01fe2 ?	mov	r1, r2, ror #31
-0+2a8 <[^>]*> e1a01372 ?	mov	r1, r2, ror r3
-0+2ac <[^>]*> e1a01062 ?	mov	r1, r2, rrx
-0+2b0 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
+0+278 <[^>]*> e1a01f82 ?	lsl	r1, r2, #31
+0+27c <[^>]*> e1a01312 ?	lsl	r1, r2, r3
+0+280 <[^>]*> e1a01122 ?	lsr	r1, r2, #2
+0+284 <[^>]*> e1a01fa2 ?	lsr	r1, r2, #31
+0+288 <[^>]*> e1a01022 ?	lsr	r1, r2, #32
+0+28c <[^>]*> e1a01332 ?	lsr	r1, r2, r3
+0+290 <[^>]*> e1a01142 ?	asr	r1, r2, #2
+0+294 <[^>]*> e1a01fc2 ?	asr	r1, r2, #31
+0+298 <[^>]*> e1a01042 ?	asr	r1, r2, #32
+0+29c <[^>]*> e1a01352 ?	asr	r1, r2, r3
+0+2a0 <[^>]*> e1a01162 ?	ror	r1, r2, #2
+0+2a4 <[^>]*> e1a01fe2 ?	ror	r1, r2, #31
+0+2a8 <[^>]*> e1a01372 ?	ror	r1, r2, r3
+0+2ac <[^>]*> e1a01062 ?	rrx	r1, r2
+0+2b0 <[^>]*> e1a01102 ?	lsl	r1, r2, #2
 0+2b4 <[^>]*> e1a01002 ?	mov	r1, r2
-0+2b8 <[^>]*> e1a01f82 ?	mov	r1, r2, lsl #31
-0+2bc <[^>]*> e1a01312 ?	mov	r1, r2, lsl r3
-0+2c0 <[^>]*> e1a01122 ?	mov	r1, r2, lsr #2
-0+2c4 <[^>]*> e1a01fa2 ?	mov	r1, r2, lsr #31
-0+2c8 <[^>]*> e1a01022 ?	mov	r1, r2, lsr #32
-0+2cc <[^>]*> e1a01332 ?	mov	r1, r2, lsr r3
-0+2d0 <[^>]*> e1a01142 ?	mov	r1, r2, asr #2
-0+2d4 <[^>]*> e1a01fc2 ?	mov	r1, r2, asr #31
-0+2d8 <[^>]*> e1a01042 ?	mov	r1, r2, asr #32
-0+2dc <[^>]*> e1a01352 ?	mov	r1, r2, asr r3
-0+2e0 <[^>]*> e1a01162 ?	mov	r1, r2, ror #2
-0+2e4 <[^>]*> e1a01fe2 ?	mov	r1, r2, ror #31
-0+2e8 <[^>]*> e1a01372 ?	mov	r1, r2, ror r3
-0+2ec <[^>]*> e1a01062 ?	mov	r1, r2, rrx
+0+2b8 <[^>]*> e1a01f82 ?	lsl	r1, r2, #31
+0+2bc <[^>]*> e1a01312 ?	lsl	r1, r2, r3
+0+2c0 <[^>]*> e1a01122 ?	lsr	r1, r2, #2
+0+2c4 <[^>]*> e1a01fa2 ?	lsr	r1, r2, #31
+0+2c8 <[^>]*> e1a01022 ?	lsr	r1, r2, #32
+0+2cc <[^>]*> e1a01332 ?	lsr	r1, r2, r3
+0+2d0 <[^>]*> e1a01142 ?	asr	r1, r2, #2
+0+2d4 <[^>]*> e1a01fc2 ?	asr	r1, r2, #31
+0+2d8 <[^>]*> e1a01042 ?	asr	r1, r2, #32
+0+2dc <[^>]*> e1a01352 ?	asr	r1, r2, r3
+0+2e0 <[^>]*> e1a01162 ?	ror	r1, r2, #2
+0+2e4 <[^>]*> e1a01fe2 ?	ror	r1, r2, #31
+0+2e8 <[^>]*> e1a01372 ?	ror	r1, r2, r3
+0+2ec <[^>]*> e1a01062 ?	rrx	r1, r2
diff --git a/gas/testsuite/gas/arm/itblock.s b/gas/testsuite/gas/arm/itblock.s
new file mode 100644
index 000000000000..0fb3c198d744
--- /dev/null
+++ b/gas/testsuite/gas/arm/itblock.s
@@ -0,0 +1,21 @@
+# All-true IT block macro.
+
+	.macro itblock num cond=""
+	.if x\cond != x
+	.if \num == 4
+	itttt \cond
+	.else
+	.if \num == 3
+	ittt \cond
+	.else
+	.if \num == 2
+	itt \cond
+	.else
+	.if \num == 1
+	.it \cond
+	.endif
+	.endif
+	.endif
+	.endif
+	.endif
+	.endm
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.l b/gas/testsuite/gas/arm/iwmmxt-bad.l
index 65889380cf1b..d030a6da46ae 100644
--- a/gas/testsuite/gas/arm/iwmmxt-bad.l
+++ b/gas/testsuite/gas/arm/iwmmxt-bad.l
@@ -8,3 +8,5 @@
 [^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]'
 [^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]'
 [^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1'
+[^:]*:10: Error: iWMMXt data or control register expected -- `wldrw wibble,\[r1\]'
+[^:]*:11: Error: iWMMXt data or control register expected -- `wstrw wibble,\[r1\]'
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.s b/gas/testsuite/gas/arm/iwmmxt-bad.s
index 47d8d71f8656..98fc239374b7 100644
--- a/gas/testsuite/gas/arm/iwmmxt-bad.s
+++ b/gas/testsuite/gas/arm/iwmmxt-bad.s
@@ -7,3 +7,5 @@
 	wstrh	wcgr0,[r1]
 	wstrd	wcgr0,[r1]
 	tmcr	wibble,r1
+	wldrw	wibble,[r1]
+	wstrw	wibble,[r1]
diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d
new file mode 100644
index 000000000000..c17a1d858a10
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt
+#name: Intel(r) Wireless MMX(tm) technology instructions version 1
+#as: -mcpu=xscale+iwmmxt -EL
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <iwmmxt> ecb11000[ 	]+wldrb[ 	]+wr1, \[r1\]
+0+004 <[^>]*> ecf11000[ 	]+wldrh[ 	]+wr1, \[r1\]
+0+008 <[^>]*> eca11000[ 	]+wstrb[ 	]+wr1, \[r1\]
+0+00c <[^>]*> ece11000[ 	]+wstrh[ 	]+wr1, \[r1\]
diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s
new file mode 100644
index 000000000000..fd58c105de50
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s
@@ -0,0 +1,8 @@
+        .text
+        .global iwmmxt
+iwmmxt:
+
+       wldrb   wr1, [r1], #0
+       wldrh   wr1, [r1], #0
+       wstrb   wr1, [r1], #0
+       wstrh   wr1, [r1], #0
diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d
index 494199d2bc45..85f4ac2e84e4 100644
--- a/gas/testsuite/gas/arm/iwmmxt.d
+++ b/gas/testsuite/gas/arm/iwmmxt.d
@@ -166,6 +166,6 @@ Disassembly of section .text:
 0+278 <[^>]*> 0e9540ea[ 	]+wunpckilweq[ 	]+wr4, wr5, wr10
 0+27c <[^>]*> 1e143005[ 	]+wxorne[ 	]+wr3, wr4, wr5
 0+280 <[^>]*> ae377007[ 	]+wandnge[ 	]+wr7, wr7, wr7
-0+284 <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
-0+288 <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
+0+284 <[^>]*> ee080110[ 	]+tmcr[ 	]+wcgr0, r0
+0+288 <[^>]*> ee1a1110[ 	]+tmrc[ 	]+r1, wcgr2
 0+28c <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s
index 0ebbad5cd3c7..42bbb7ab4ceb 100644
--- a/gas/testsuite/gas/arm/iwmmxt.s
+++ b/gas/testsuite/gas/arm/iwmmxt.s
@@ -203,7 +203,8 @@ iwmmxt:
 
 	wzeroge		wr7
 
+	tmcr		wcgr0, r0
+	tmrc		r1, wcgr2
+
 	@ a.out-required section size padding
 	nop
-	nop
-	nop
diff --git a/gas/testsuite/gas/arm/iwmmxt2.d b/gas/testsuite/gas/arm/iwmmxt2.d
new file mode 100644
index 000000000000..7c1bbeb921e3
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt2.d
@@ -0,0 +1,119 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt
+#name: Intel(r) Wireless MMX(tm) technology instructions version 2
+#as: -mcpu=xscale+iwmmxt+iwmmxt2 -EL
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <iwmmxt2> ee654186[ 	]+waddhc[ 	]+wr4, wr5, wr6
+0+004 <[^>]*> eea87189[ 	]+waddwc[ 	]+wr7, wr8, wr9
+0+008 <[^>]*> ce954106[ 	]+wmadduxgt[ 	]+wr4, wr5, wr6
+0+00c <[^>]*> 0ec87109[ 	]+wmadduneq[ 	]+wr7, wr8, wr9
+0+010 <[^>]*> 1eb54106[ 	]+wmaddsxne[ 	]+wr4, wr5, wr6
+0+014 <[^>]*> aee87109[ 	]+wmaddsnge[ 	]+wr7, wr8, wr9
+0+018 <[^>]*> eed21103[ 	]+wmulumr[ 	]+wr1, wr2, wr3
+0+01c <[^>]*> eef21103[ 	]+wmulsmr[ 	]+wr1, wr2, wr3
+0+020 <[^>]*> ce13f190[ 	]+torvscbgt[ 	]+pc
+0+024 <[^>]*> 1e53f190[ 	]+torvschne[ 	]+pc
+0+028 <[^>]*> 0e93f190[ 	]+torvscweq[ 	]+pc
+0+02c <[^>]*> ee2211c0[ 	]+wabsb[ 	]+wr1, wr2
+0+030 <[^>]*> ee6431c0[ 	]+wabsh[ 	]+wr3, wr4
+0+034 <[^>]*> eea651c0[ 	]+wabsw[ 	]+wr5, wr6
+0+038 <[^>]*> ce2211c0[ 	]+wabsbgt[ 	]+wr1, wr2
+0+03c <[^>]*> ee1211c3[ 	]+wabsdiffb[ 	]+wr1, wr2, wr3
+0+040 <[^>]*> ee5541c6[ 	]+wabsdiffh[ 	]+wr4, wr5, wr6
+0+044 <[^>]*> ee9871c9[ 	]+wabsdiffw[ 	]+wr7, wr8, wr9
+0+048 <[^>]*> ce1211c3[ 	]+wabsdiffbgt[ 	]+wr1, wr2, wr3
+0+04c <[^>]*> ee6211a3[ 	]+waddbhusm[ 	]+wr1, wr2, wr3
+0+050 <[^>]*> ee2541a6[ 	]+waddbhusl[ 	]+wr4, wr5, wr6
+0+054 <[^>]*> ce6211a3[ 	]+waddbhusmgt[ 	]+wr1, wr2, wr3
+0+058 <[^>]*> ce2541a6[ 	]+waddbhuslgt[ 	]+wr4, wr5, wr6
+0+05c <[^>]*> ee421003[ 	]+wavg4[ 	]+wr1, wr2, wr3
+0+060 <[^>]*> ce454006[ 	]+wavg4gt[ 	]+wr4, wr5, wr6
+0+064 <[^>]*> ee521003[ 	]+wavg4r[ 	]+wr1, wr2, wr3
+0+068 <[^>]*> ce554006[ 	]+wavg4rgt[ 	]+wr4, wr5, wr6
+0+06c <[^>]*> fc711102[ 	]+wldrd[ 	]+wr1, \[r1\], -r2
+0+070 <[^>]*> fc712132[ 	]+wldrd[ 	]+wr2, \[r1\], -r2, lsl #3
+0+074 <[^>]*> fcf13102[ 	]+wldrd[ 	]+wr3, \[r1\], \+r2
+0+078 <[^>]*> fcf14142[ 	]+wldrd[ 	]+wr4, \[r1\], \+r2, lsl #4
+0+07c <[^>]*> fd515102[ 	]+wldrd[ 	]+wr5, \[r1, -r2\]
+0+080 <[^>]*> fd516132[ 	]+wldrd[ 	]+wr6, \[r1, -r2, lsl #3\]
+0+084 <[^>]*> fdd17102[ 	]+wldrd[ 	]wr7, \[r1, \+r2\]
+0+088 <[^>]*> fdd18142[ 	]+wldrd[ 	]wr8, \[r1, \+r2, lsl #4\]
+0+08c <[^>]*> fd719102[ 	]+wldrd[ 	]wr9, \[r1, -r2\]!
+0+090 <[^>]*> fd71a132[ 	]+wldrd[ 	]wr10, \[r1, -r2, lsl #3\]!
+0+094 <[^>]*> fdf1b102[ 	]+wldrd[ 	]wr11, \[r1, \+r2\]!
+0+098 <[^>]*> fdf1c142[ 	]+wldrd[ 	]wr12, \[r1, \+r2, lsl #4\]!
+0+09c <[^>]*> ee821083[ 	]+wmerge[ 	]wr1, wr2, wr3, #4
+0+0a0 <[^>]*> ce821083[ 	]+wmergegt[ 	]wr1, wr2, wr3, #4
+0+0a4 <[^>]*> 0e3210a3[ 	]+wmiatteq[ 	]wr1, wr2, wr3
+0+0a8 <[^>]*> ce2210a3[ 	]+wmiatbgt[ 	]wr1, wr2, wr3
+0+0ac <[^>]*> 1e1210a3[ 	]+wmiabtne[ 	]wr1, wr2, wr3
+0+0b0 <[^>]*> ce0210a3[ 	]+wmiabbgt[ 	]wr1, wr2, wr3
+0+0b4 <[^>]*> 0e7210a3[ 	]+wmiattneq[ 	]wr1, wr2, wr3
+0+0b8 <[^>]*> 1e6210a3[ 	]+wmiatbnne[ 	]wr1, wr2, wr3
+0+0bc <[^>]*> ce5210a3[ 	]+wmiabtngt[ 	]wr1, wr2, wr3
+0+0c0 <[^>]*> 0e4210a3[ 	]+wmiabbneq[ 	]wr1, wr2, wr3
+0+0c4 <[^>]*> 0eb21123[ 	]+wmiawtteq[ 	]wr1, wr2, wr3
+0+0c8 <[^>]*> cea21123[ 	]+wmiawtbgt[ 	]wr1, wr2, wr3
+0+0cc <[^>]*> 1e921123[ 	]+wmiawbtne[ 	]wr1, wr2, wr3
+0+0d0 <[^>]*> ce821123[ 	]+wmiawbbgt[ 	]wr1, wr2, wr3
+0+0d4 <[^>]*> 1ef21123[ 	]+wmiawttnne[ 	]wr1, wr2, wr3
+0+0d8 <[^>]*> cee21123[ 	]+wmiawtbngt[ 	]wr1, wr2, wr3
+0+0dc <[^>]*> 0ed21123[ 	]+wmiawbtneq[ 	]wr1, wr2, wr3
+0+0e0 <[^>]*> 1ec21123[ 	]+wmiawbbnne[ 	]wr1, wr2, wr3
+0+0e4 <[^>]*> 0ed210c3[ 	]+wmulwumeq[ 	]wr1, wr2, wr3
+0+0e8 <[^>]*> cec210c3[ 	]+wmulwumrgt[ 	]wr1, wr2, wr3
+0+0ec <[^>]*> 1ef210c3[ 	]+wmulwsmne[ 	]wr1, wr2, wr3
+0+0f0 <[^>]*> 0ee210c3[ 	]+wmulwsmreq[ 	]wr1, wr2, wr3
+0+0f4 <[^>]*> ceb210c3[ 	]+wmulwlgt[ 	]wr1, wr2, wr3
+0+0f8 <[^>]*> aeb210c3[ 	]+wmulwlge[ 	]wr1, wr2, wr3
+0+0fc <[^>]*> 1eb210a3[ 	]+wqmiattne[ 	]wr1, wr2, wr3
+0+100 <[^>]*> 0ef210a3[ 	]+wqmiattneq[ 	]wr1, wr2, wr3
+0+104 <[^>]*> cea210a3[ 	]+wqmiatbgt[ 	]wr1, wr2, wr3
+0+108 <[^>]*> aee210a3[ 	]+wqmiatbnge[ 	]wr1, wr2, wr3
+0+10c <[^>]*> 1e9210a3[ 	]+wqmiabtne[ 	]wr1, wr2, wr3
+0+110 <[^>]*> 0ed210a3[ 	]+wqmiabtneq[ 	]wr1, wr2, wr3
+0+114 <[^>]*> ce8210a3[ 	]+wqmiabbgt[ 	]wr1, wr2, wr3
+0+118 <[^>]*> 1ec210a3[ 	]+wqmiabbnne[ 	]wr1, wr2, wr3
+0+11c <[^>]*> ce121083[ 	]+wqmulmgt[ 	]wr1, wr2, wr3
+0+120 <[^>]*> 0e321083[ 	]+wqmulmreq[ 	]wr1, wr2, wr3
+0+124 <[^>]*> cec210e3[ 	]+wqmulwmgt[ 	]wr1, wr2, wr3
+0+128 <[^>]*> 0ee210e3[ 	]+wqmulwmreq[ 	]wr1, wr2, wr3
+0+12c <[^>]*> fc611102[ 	]+wstrd[ 	]+wr1, \[r1\], -r2
+0+130 <[^>]*> fc612132[ 	]+wstrd[ 	]+wr2, \[r1\], -r2, lsl #3
+0+134 <[^>]*> fce13102[ 	]+wstrd[ 	]+wr3, \[r1\], \+r2
+0+138 <[^>]*> fce14142[ 	]+wstrd[ 	]+wr4, \[r1\], \+r2, lsl #4
+0+13c <[^>]*> fd415102[ 	]+wstrd[ 	]+wr5, \[r1, -r2\]
+0+140 <[^>]*> fd416132[ 	]+wstrd[ 	]+wr6, \[r1, -r2, lsl #3\]
+0+144 <[^>]*> fdc17102[ 	]+wstrd[ 	]wr7, \[r1, \+r2\]
+0+148 <[^>]*> fdc18142[ 	]+wstrd[ 	]wr8, \[r1, \+r2, lsl #4\]
+0+14c <[^>]*> fd619102[ 	]+wstrd[ 	]wr9, \[r1, -r2\]!
+0+150 <[^>]*> fd61a132[ 	]+wstrd[ 	]wr10, \[r1, -r2, lsl #3\]!
+0+154 <[^>]*> fde1b102[ 	]+wstrd[ 	]wr11, \[r1, \+r2\]!
+0+158 <[^>]*> fde1c142[ 	]+wstrd[ 	]wr12, \[r1, \+r2, lsl #4\]!
+0+15c <[^>]*> ced211c3[ 	]+wsubaddhxgt[ 	]wr1, wr2, wr3
+0+160 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+164 <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+168 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+16c <[^>]*> fe721145[ 	]+wrorh[ 	]wr1, wr2, #21
+0+170 <[^>]*> feb2104d[ 	]+wrorw[ 	]wr1, wr2, #13
+0+174 <[^>]*> fef2104e[ 	]+wrord[ 	]wr1, wr2, #14
+0+178 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+17c <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+180 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+184 <[^>]*> fe59204b[ 	]+wsllh[ 	]wr2, wr9, #11
+0+188 <[^>]*> fe95304d[ 	]+wsllw[ 	]wr3, wr5, #13
+0+18c <[^>]*> fed8304f[ 	]+wslld[ 	]wr3, wr8, #15
+0+190 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+194 <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+198 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+19c <[^>]*> fe49204c[ 	]+wsrah[ 	]wr2, wr9, #12
+0+1a0 <[^>]*> fe85304e[ 	]+wsraw[ 	]wr3, wr5, #14
+0+1a4 <[^>]*> fec83140[ 	]+wsrad[ 	]wr3, wr8, #16
+0+1a8 <[^>]*> fe721140[ 	]+wrorh[ 	]wr1, wr2, #16
+0+1ac <[^>]*> feb21040[ 	]+wrorw[ 	]wr1, wr2, #32
+0+1b0 <[^>]*> ee021002[ 	]+wor[ 	]wr1, wr2, wr2
+0+1b4 <[^>]*> fe69204c[ 	]+wsrlh[ 	]wr2, wr9, #12
+0+1b8 <[^>]*> fea5304e[ 	]+wsrlw[ 	]wr3, wr5, #14
+0+1bc <[^>]*> fee83140[ 	]+wsrld[ 	]wr3, wr8, #16
diff --git a/gas/testsuite/gas/arm/iwmmxt2.s b/gas/testsuite/gas/arm/iwmmxt2.s
new file mode 100644
index 000000000000..314f64f11e0b
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt2.s
@@ -0,0 +1,137 @@
+	.text
+	.global iwmmxt2
+iwmmxt2:
+
+	waddhc		wr4, wr5, wr6
+	waddwc		wr7, wr8, wr9
+
+	wmadduxgt	wr4, wr5, wr6
+	wmadduneq	wr7, wr8, wr9
+	wmaddsxne	wr4, wr5, wr6
+	wmaddsnge	wr7, wr8, wr9
+
+	wmulumr		wr1, wr2, wr3
+	wmulsmr		wr1, wr2, wr3
+
+	torvscbgt	r15
+	torvschne	r15
+	torvscweq	r15
+
+	wabsb		wr1, wr2
+	wabsh		wr3, wr4
+	wabsw		wr5, wr6
+	wabsbgt		wr1, wr2
+
+	wabsdiffb	wr1, wr2, wr3
+	wabsdiffh	wr4, wr5, wr6
+	wabsdiffw	wr7, wr8, wr9
+	wabsdiffbgt	wr1, wr2, wr3
+
+	waddbhusm	wr1, wr2, wr3
+	waddbhusl	wr4, wr5, wr6
+	waddbhusmgt	wr1, wr2, wr3
+	waddbhuslgt	wr4, wr5, wr6
+
+	wavg4		wr1, wr2, wr3
+	wavg4gt		wr4, wr5, wr6
+	wavg4r		wr1, wr2, wr3
+	wavg4rgt	wr4, wr5, wr6
+
+	wldrd		wr1, [r1], -r2
+	wldrd		wr2, [r1], -r2,lsl #3
+	wldrd		wr3, [r1], +r2
+	wldrd		wr4, [r1], +r2,lsl #4
+	wldrd		wr5, [r1, -r2]
+	wldrd		wr6, [r1, -r2,lsl #3]
+	wldrd		wr7, [r1, +r2]
+	wldrd		wr8, [r1, +r2,lsl #4]
+	wldrd		wr9, [r1, -r2]!
+	wldrd		wr10, [r1, -r2,lsl #3]!
+	wldrd		wr11, [r1, +r2]!
+	wldrd		wr12, [r1, +r2,lsl #4]!
+
+	wmerge		wr1, wr2, wr3, #4
+	wmergegt	wr1, wr2, wr3, #4
+
+	wmiatteq	wr1, wr2, wr3
+	wmiatbgt	wr1, wr2, wr3
+	wmiabtne	wr1, wr2, wr3
+	wmiabbgt	wr1, wr2, wr3
+	wmiattneq	wr1, wr2, wr3
+	wmiatbnne	wr1, wr2, wr3
+	wmiabtngt	wr1, wr2, wr3
+	wmiabbneq	wr1, wr2, wr3
+
+	wmiawtteq	wr1, wr2, wr3
+	wmiawtbgt	wr1, wr2, wr3
+	wmiawbtne	wr1, wr2, wr3
+	wmiawbbgt	wr1, wr2, wr3
+	wmiawttnne	wr1, wr2, wr3
+	wmiawtbngt	wr1, wr2, wr3
+	wmiawbtneq	wr1, wr2, wr3
+	wmiawbbnne	wr1, wr2, wr3
+
+	wmulwumeq	wr1, wr2, wr3
+	wmulwumrgt	wr1, wr2, wr3
+	wmulwsmne	wr1, wr2, wr3
+	wmulwsmreq	wr1, wr2, wr3
+	wmulwlgt	wr1, wr2, wr3
+	wmulwlge	wr1, wr2, wr3
+
+	wqmiattne	wr1, wr2, wr3
+	wqmiattneq	wr1, wr2, wr3
+	wqmiatbgt	wr1, wr2, wr3
+	wqmiatbnge	wr1, wr2, wr3
+	wqmiabtne	wr1, wr2, wr3
+	wqmiabtneq	wr1, wr2, wr3
+	wqmiabbgt	wr1, wr2, wr3
+	wqmiabbnne	wr1, wr2, wr3
+
+	wqmulmgt	wr1, wr2, wr3
+	wqmulmreq	wr1, wr2, wr3
+
+	wqmulwmgt	wr1, wr2, wr3
+	wqmulwmreq	wr1, wr2, wr3
+
+	wstrd		wr1, [r1], -r2
+	wstrd		wr2, [r1], -r2,lsl #3
+	wstrd		wr3, [r1], +r2
+	wstrd		wr4, [r1], +r2,lsl #4
+	wstrd		wr5, [r1, -r2]
+	wstrd		wr6, [r1, -r2,lsl #3]
+	wstrd		wr7, [r1, +r2]
+	wstrd		wr8, [r1, +r2,lsl #4]
+	wstrd		wr9, [r1, -r2]!
+	wstrd		wr10, [r1, -r2,lsl #3]!
+	wstrd		wr11, [r1, +r2]!
+	wstrd		wr12, [r1, +r2,lsl #4]!
+
+	wsubaddhxgt	wr1, wr2, wr3
+
+	wrorh		wr1, wr2, #0
+	wrorw		wr1, wr2, #0
+	wrord		wr1, wr2, #0
+	wrorh		wr1, wr2, #21
+	wrorw		wr1, wr2, #13
+	wrord		wr1, wr2, #14
+
+	wsllh		wr1, wr2, #0
+	wsllw		wr1, wr2, #0
+	wslld		wr1, wr2, #0
+	wsllh		wr2, wr9, #11
+	wsllw		wr3, wr5, #13
+	wslld		wr3, wr8, #15
+
+	wsrah		wr1, wr2, #0
+	wsraw		wr1, wr2, #0
+	wsrad		wr1, wr2, #0
+	wsrah		wr2, wr9, #12
+	wsraw		wr3, wr5, #14
+	wsrad		wr3, wr8, #16
+
+	wsrlh		wr1, wr2, #0
+	wsrlw		wr1, wr2, #0
+	wsrld		wr1, wr2, #0
+	wsrlh		wr2, wr9, #12
+	wsrlw		wr3, wr5, #14
+	wsrld		wr3, wr8, #16
diff --git a/gas/testsuite/gas/arm/local_function.d b/gas/testsuite/gas/arm/local_function.d
new file mode 100644
index 000000000000..46da8eceb6c7
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_function.d
@@ -0,0 +1,10 @@
+#objdump: -r
+#name: Relocations agains local function symbols
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*:     file format.*
+
+RELOCATION RECORDS FOR \[.text\]:
+OFFSET   TYPE              VALUE 
+00000000 R_ARM_(CALL|PC24)        bar
diff --git a/gas/testsuite/gas/arm/local_function.s b/gas/testsuite/gas/arm/local_function.s
new file mode 100644
index 000000000000..1d98a37425cc
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_function.s
@@ -0,0 +1,10 @@
+	.text
+	.type foo, %function
+foo:
+	bl bar
+
+	.section .text.bar
+	nop
+	.type bar, %function
+bar:
+	nop
diff --git a/gas/testsuite/gas/arm/local_label_coff.d b/gas/testsuite/gas/arm/local_label_coff.d
new file mode 100644
index 000000000000..5e45ac8c479c
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_coff.d
@@ -0,0 +1,11 @@
+#nm: -n
+#name: ARM local label relocs to section symbol relocs (COFF)
+# This test is only valid on COFF based targets, except Windows CE.
+# There are ELF and Windows CE versions of this test.
+#not-skip: *-unknown-pe *-epoc-pe *-*-*coff
+
+# Check if relocations against local symbols are converted to 
+# relocations against section symbols.
+0+0 b .bss
+0+0 d .data
+0+0 t .text
diff --git a/gas/testsuite/gas/arm/local_label_coff.s b/gas/testsuite/gas/arm/local_label_coff.s
new file mode 100644
index 000000000000..985f568ac3f0
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_coff.s
@@ -0,0 +1,3 @@
+	.text
+Lused_label:
+	.word	Lused_label
diff --git a/gas/testsuite/gas/arm/local_label_elf.d b/gas/testsuite/gas/arm/local_label_elf.d
new file mode 100644
index 000000000000..d4a8c8ea73f7
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_elf.d
@@ -0,0 +1,9 @@
+#nm: -n
+#name: ARM local label relocs to section symbol relocs (ELF)
+# This test is only valid on ELF targets.
+# There are COFF and Windows CE versions of this test.
+#skip: *-*-*coff *-*-pe *-wince-* *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Check if relocations against local symbols are converted to 
+# relocations against section symbols.
+
diff --git a/gas/testsuite/gas/arm/local_label_elf.s b/gas/testsuite/gas/arm/local_label_elf.s
new file mode 100644
index 000000000000..e9f5467d4122
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_elf.s
@@ -0,0 +1,3 @@
+	.text
+.Lused_label:
+	.word	.Lused_label
diff --git a/gas/testsuite/gas/arm/local_label_wince.d b/gas/testsuite/gas/arm/local_label_wince.d
new file mode 100644
index 000000000000..97fc58aea824
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_wince.d
@@ -0,0 +1,11 @@
+#nm: -n
+#name: ARM local label relocs to section symbol relocs (WinCE)
+# This test is only valid on Windows CE.
+# There are ELF and COFF versions of this test.
+#not-skip: *-*-wince *-wince-*
+
+# Check if relocations against local symbols are converted to 
+# relocations against section symbols.
+0+0 b .bss
+0+0 d .data
+0+0 t .text
diff --git a/gas/testsuite/gas/arm/local_label_wince.s b/gas/testsuite/gas/arm/local_label_wince.s
new file mode 100644
index 000000000000..e9f5467d4122
--- /dev/null
+++ b/gas/testsuite/gas/arm/local_label_wince.s
@@ -0,0 +1,3 @@
+	.text
+.Lused_label:
+	.word	.Lused_label
diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d
index 2384594fc545..c29bb626156e 100644
--- a/gas/testsuite/gas/arm/macro1.d
+++ b/gas/testsuite/gas/arm/macro1.d
@@ -6,7 +6,7 @@
 
 Disassembly of section .text:
 
-0+0 <[^>]*> e8bd8030 ?	ldmia	sp!, {r4, r5, pc}
+0+0 <[^>]*> e8bd8030 ?	pop	{r4, r5, pc}
 0+4 <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
 0+8 <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
 0+c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/mapshort-eabi.d b/gas/testsuite/gas/arm/mapshort-eabi.d
new file mode 100644
index 000000000000..9cbfc3eacd4a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mapshort-eabi.d
@@ -0,0 +1,45 @@
+#objdump: --syms --special-syms -d
+#name: ARM Mapping Symbols for .short (EABI version)
+# This test is only valid on EABI based ports.
+#target: *-*-*eabi *-*-symbianelf
+#source: mapshort.s
+
+# Test the generation and use of ARM ELF Mapping Symbols
+
+.*: +file format .*arm.*
+
+SYMBOL TABLE:
+0+00 l    d  .text	00000000 .text
+0+00 l    d  .data	00000000 .data
+0+00 l    d  .bss	00000000 .bss
+0+00 l     F .text	00000000 foo
+0+00 l       .text	00000000 \$a
+0+04 l       .text	00000000 \$t
+0+08 l       .text	00000000 \$d
+0+12 l       .text	00000000 \$t
+0+16 l       .text	00000000 \$d
+0+18 l       .text	00000000 \$a
+0+1c l       .text	00000000 \$d
+0+1f l       .text	00000000 bar
+0+00 l       .data	00000000 wibble
+0+00 l       .data	00000000 \$d
+0+00 l    d  .ARM.attributes	00000000 .ARM.attributes
+
+
+Disassembly of section .text:
+
+0+00 <foo>:
+   0:	e1a00000 	nop			\(mov r0,r0\)
+   4:	46c0      	nop			\(mov r8, r8\)
+   6:	46c0      	nop			\(mov r8, r8\)
+   8:	00000002 	.word	0x00000002
+   c:	00010001 	.word	0x00010001
+  10:	0003      	.short	0x0003
+  12:	46c0      	nop			\(mov r8, r8\)
+  14:	46c0      	nop			\(mov r8, r8\)
+  16:	0001      	.short	0x0001
+  18:	ebfffff8 	bl	0 <foo>
+  1c:	0008      	.short	0x0008
+  1e:	09          	.byte	0x09
+0+1f <bar>:
+  1f:	0a          	.byte	0x0a
diff --git a/gas/testsuite/gas/arm/mapshort-elf.d b/gas/testsuite/gas/arm/mapshort-elf.d
new file mode 100644
index 000000000000..09602f08091e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mapshort-elf.d
@@ -0,0 +1,44 @@
+#objdump: --syms --special-syms -d
+#name: ARM Mapping Symbols for .short (ELF version)
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi *-*-syymbianelf
+#source: mapshort.s
+
+# Test the generation and use of ARM ELF Mapping Symbols
+
+.*: +file format .*arm.*
+
+SYMBOL TABLE:
+0+00 l    d  .text	00000000 .text
+0+00 l    d  .data	00000000 .data
+0+00 l    d  .bss	00000000 .bss
+0+00 l     F .text	00000000 foo
+0+00 l       .text	00000000 \$a
+0+04 l       .text	00000000 \$t
+0+08 l       .text	00000000 \$d
+0+12 l       .text	00000000 \$t
+0+16 l       .text	00000000 \$d
+0+18 l       .text	00000000 \$a
+0+1c l       .text	00000000 \$d
+0+1f l       .text	00000000 bar
+0+00 l       .data	00000000 wibble
+0+00 l       .data	00000000 \$d
+# The ELF based port does not generate a .ARM.attributes symbol
+
+Disassembly of section .text:
+
+0+00 <foo>:
+   0:	e1a00000 	nop			\(mov r0,r0\)
+   4:	46c0      	nop			\(mov r8, r8\)
+   6:	46c0      	nop			\(mov r8, r8\)
+   8:	00000002 	.word	0x00000002
+   c:	00010001 	.word	0x00010001
+  10:	0003      	.short	0x0003
+  12:	46c0      	nop			\(mov r8, r8\)
+  14:	46c0      	nop			\(mov r8, r8\)
+  16:	0001      	.short	0x0001
+  18:	ebfffff8 	bl	0 <foo>
+  1c:	0008      	.short	0x0008
+  1e:	09          	.byte	0x09
+0+1f <bar>:
+  1f:	0a          	.byte	0x0a
diff --git a/gas/testsuite/gas/arm/mapshort.s b/gas/testsuite/gas/arm/mapshort.s
new file mode 100644
index 000000000000..741cb8251053
--- /dev/null
+++ b/gas/testsuite/gas/arm/mapshort.s
@@ -0,0 +1,24 @@
+	.text
+	.type foo, %function
+foo:
+	.code 32
+	nop
+	.code 16
+	nop
+	nop
+	.long 2
+	.short 1
+	.short 1
+	.short 3
+	nop
+	nop
+	.short 1
+	.code 32
+	bl foo
+	.short 8
+	.byte 9
+bar:
+	.byte 10
+	.data
+wibble:
+	.word 0
diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.d b/gas/testsuite/gas/arm/mul-overlap-v6.d
new file mode 100644
index 000000000000..ff42190a5d0d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mul-overlap-v6.d
@@ -0,0 +1,10 @@
+# name: Overlapping multiplication operands for ARMv6
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> e0000090 	mul	r0, r0, r0
+0[0-9a-f]+ <[^>]+> e0202190 	mla	r0, r0, r1, r2
+0[0-9a-f]+ <[^>]+> e0602190 	mls	r0, r0, r1, r2
+0[0-9a-f]+ <[^>]+> e12fff1e 	bx	lr
diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.s b/gas/testsuite/gas/arm/mul-overlap-v6.s
new file mode 100644
index 000000000000..f35c124ae39f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mul-overlap-v6.s
@@ -0,0 +1,9 @@
+	.arch	armv6t2
+	.text
+	.align	2
+	.global	foo
+foo:
+	mul	r0, r0, r0
+	mla	r0, r0, r1, r2
+	mls	r0, r0, r1, r2
+	bx	lr
diff --git a/gas/testsuite/gas/arm/mul-overlap.d b/gas/testsuite/gas/arm/mul-overlap.d
new file mode 100644
index 000000000000..53406e3f413b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mul-overlap.d
@@ -0,0 +1,2 @@
+# name: Overlapping multiplication operands without architecture specification
+# error-output: mul-overlap.l
diff --git a/gas/testsuite/gas/arm/mul-overlap.l b/gas/testsuite/gas/arm/mul-overlap.l
new file mode 100644
index 000000000000..a895c0102a3f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mul-overlap.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:5: Rd and Rm should be different in mul
+[^:]*:6: Rd and Rm should be different in mla
diff --git a/gas/testsuite/gas/arm/mul-overlap.s b/gas/testsuite/gas/arm/mul-overlap.s
new file mode 100644
index 000000000000..6932eaeb13fe
--- /dev/null
+++ b/gas/testsuite/gas/arm/mul-overlap.s
@@ -0,0 +1,8 @@
+	.text
+	.align	2
+	.global	foo
+foo:
+	mul	r0, r0, r0
+	mla	r0, r0, r1, r2
+	mls	r0, r0, r1, r2
+	bx	lr
diff --git a/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/gas/testsuite/gas/arm/neon-cond-bad-inc.s
new file mode 100644
index 000000000000..a92d19675e1c
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad-inc.s
@@ -0,0 +1,57 @@
+# Check for illegal conditional Neon instructions in ARM mode. The instructions
+# which overlap with VFP are the tricky cases, so test those.
+
+	.include "itblock.s"
+
+	.syntax unified
+	.text
+func:
+	itblock 4 eq
+	vmoveq q0,q1
+        vmoveq d0,d1
+	vmoveq.i32 q0,#0
+        vmoveq.i32 d0,#0
+        @ Following four *can* be conditional.
+	itblock 4 eq
+        vmoveq.32 d0[1], r2
+	vmoveq d0,r1,r2
+        vmoveq.32 r2,d1[0]
+        vmoveq r0,r1,d2
+
+	.macro dyadic_eq op eq="eq" f32=".f32"
+	itblock 2 eq
+        \op\eq\f32 d0,d1,d2
+        \op\eq\f32 q0,q1,q2
+        .endm
+       
+        dyadic_eq vmul
+        dyadic_eq vmla
+        dyadic_eq vmls
+        dyadic_eq vadd
+        dyadic_eq vsub
+        
+	.macro monadic_eq op eq="eq" f32=".f32"
+	itblock 2 eq
+        \op\eq\f32 d0,d1
+        \op\eq\f32 q0,q1
+        .endm
+
+	monadic_eq vabs
+        monadic_eq vneg
+        
+        .macro cvt to from dot="."
+	itblock 2 eq
+        vcvteq\dot\to\dot\from d0,d1
+        vcvteq\dot\to\dot\from q0,q1
+        .endm
+        
+	cvt s32 f32
+        cvt u32 f32
+        cvt f32 s32
+        cvt f32 u32
+
+	itblock 4 eq
+	vdupeq.32 d0,r1
+	vdupeq.32 q0,r1
+	vdupeq.32 d0,d1[0]
+	vdupeq.32 q0,d1[1]
diff --git a/gas/testsuite/gas/arm/neon-cond-bad.d b/gas/testsuite/gas/arm/neon-cond-bad.d
new file mode 100644
index 000000000000..105ba4d7f26e
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad.d
@@ -0,0 +1,3 @@
+# name: Illegal conditions in Neon instructions, ARM mode
+# as: -mfpu=neon -I$srcdir/$subdir
+# error-output: neon-cond-bad.l
diff --git a/gas/testsuite/gas/arm/neon-cond-bad.l b/gas/testsuite/gas/arm/neon-cond-bad.l
new file mode 100644
index 000000000000..a79f79d64f83
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad.l
@@ -0,0 +1,29 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1'
+[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1'
+[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0'
+[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0'
+[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
+[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2'
+[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
+[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2'
+[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
+[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2'
+[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
+[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'
+[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
+[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2'
+[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
+[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'
+[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
+[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'
+[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
+[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'
+[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'
+[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'
+[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]'
+[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]'
diff --git a/gas/testsuite/gas/arm/neon-cond-bad.s b/gas/testsuite/gas/arm/neon-cond-bad.s
new file mode 100644
index 000000000000..16afd8635e91
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad.s
@@ -0,0 +1,2 @@
+	.arm
+	.include "neon-cond-bad-inc.s"
diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/gas/testsuite/gas/arm/neon-cond-bad_t2.d
new file mode 100644
index 000000000000..517caa758ee4
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.d
@@ -0,0 +1,55 @@
+# name: Conditions in Neon instructions, Thumb mode (illegal in ARM).
+# as: -mfpu=neon -I$srcdir/$subdir
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ef22 0152 	vorreq	q0, q1, q1
+0[0-9a-f]+ <[^>]+> ef21 0111 	vorreq	d0, d1, d1
+0[0-9a-f]+ <[^>]+> ef80 0050 	vmoveq\.i32	q0, #0	; 0x00000000
+0[0-9a-f]+ <[^>]+> ef80 0010 	vmoveq\.i32	d0, #0	; 0x00000000
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ee20 2b10 	vmoveq\.32	d0\[1\], r2
+0[0-9a-f]+ <[^>]+> ec42 1b10 	vmoveq	d0, r1, r2
+0[0-9a-f]+ <[^>]+> ee11 2b10 	vmoveq\.32	r2, d1\[0\]
+0[0-9a-f]+ <[^>]+> ec51 0b12 	vmoveq	r0, r1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ff01 0d12 	vmuleq\.f32	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ff02 0d54 	vmuleq\.f32	q0, q1, q2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ef01 0d12 	vmlaeq\.f32	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ef02 0d54 	vmlaeq\.f32	q0, q1, q2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ef21 0d12 	vmlseq\.f32	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ef22 0d54 	vmlseq\.f32	q0, q1, q2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ef01 0d02 	vaddeq\.f32	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ef02 0d44 	vaddeq\.f32	q0, q1, q2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ef21 0d02 	vsubeq\.f32	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ef22 0d44 	vsubeq\.f32	q0, q1, q2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffb9 0701 	vabseq\.f32	d0, d1
+0[0-9a-f]+ <[^>]+> ffb9 0742 	vabseq\.f32	q0, q1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffb9 0781 	vnegeq\.f32	d0, d1
+0[0-9a-f]+ <[^>]+> ffb9 07c2 	vnegeq\.f32	q0, q1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffbb 0701 	vcvteq\.s32\.f32	d0, d1
+0[0-9a-f]+ <[^>]+> ffbb 0742 	vcvteq\.s32\.f32	q0, q1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffbb 0781 	vcvteq\.u32\.f32	d0, d1
+0[0-9a-f]+ <[^>]+> ffbb 07c2 	vcvteq\.u32\.f32	q0, q1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffbb 0601 	vcvteq\.f32\.s32	d0, d1
+0[0-9a-f]+ <[^>]+> ffbb 0642 	vcvteq\.f32\.s32	q0, q1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ffbb 0681 	vcvteq\.f32\.u32	d0, d1
+0[0-9a-f]+ <[^>]+> ffbb 06c2 	vcvteq\.f32\.u32	q0, q1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ee80 1b10 	vdupeq\.32	d0, r1
+0[0-9a-f]+ <[^>]+> eea0 1b10 	vdupeq\.32	q0, r1
+0[0-9a-f]+ <[^>]+> ffb4 0c01 	vdupeq\.32	d0, d1\[0\]
+0[0-9a-f]+ <[^>]+> ffbc 0c41 	vdupeq\.32	q0, d1\[1\]
diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.s b/gas/testsuite/gas/arm/neon-cond-bad_t2.s
new file mode 100644
index 000000000000..2655d11a049d
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.s
@@ -0,0 +1,2 @@
+	.thumb
+	.include "neon-cond-bad-inc.s"
diff --git a/gas/testsuite/gas/arm/neon-cond.d b/gas/testsuite/gas/arm/neon-cond.d
new file mode 100644
index 000000000000..0b7d8ede73b6
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond.d
@@ -0,0 +1,14 @@
+# name: Conditional Neon instructions
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> 0d943b00 	vldreq	d3, \[r4\]
+0[0-9a-f]+ <[^>]+> be035b70 	vmovlt\.16	d3\[1\], r5
+0[0-9a-f]+ <[^>]+> ac474b13 	vmovge	d3, r4, r7
+0[0-9a-f]+ <[^>]+> 3c543b3e 	vmovcc	r3, r4, d30
+0[0-9a-f]+ <[^>]+> 1e223b10 	vmovne\.32	d2\[1\], r3
+0[0-9a-f]+ <[^>]+> 2c521b13 	vmovcs	r1, r2, d3
+0[0-9a-f]+ <[^>]+> 3c421b14 	vmovcc	d4, r1, r2
diff --git a/gas/testsuite/gas/arm/neon-cond.s b/gas/testsuite/gas/arm/neon-cond.s
new file mode 100644
index 000000000000..8f62575aa5e5
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cond.s
@@ -0,0 +1,13 @@
+@ test conditional compilation 
+
+	.arm
+	.text
+	.syntax unified
+
+	vldreq.32 d3,[r4]
+	vmovlt.16 d3[1], r5
+	vmovge d3, r4, r7
+	vmovcc r3, r4, d30
+	vmovne.32 d2[1],r3
+	vmovcs r1,r2,d3
+	vmovcc d4,r1,r2
diff --git a/gas/testsuite/gas/arm/neon-const.d b/gas/testsuite/gas/arm/neon-const.d
new file mode 100644
index 000000000000..a1bc97cf381f
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-const.d
@@ -0,0 +1,265 @@
+# name: Neon floating-point constants
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f2800050 	vmov\.i32	q0, #0	; 0x00000000
+0[0-9a-f]+ <[^>]+> f2800f50 	vmov\.f32	q0, #2	; 0x40000000
+0[0-9a-f]+ <[^>]+> f2810f50 	vmov\.f32	q0, #4	; 0x40800000
+0[0-9a-f]+ <[^>]+> f2820f50 	vmov\.f32	q0, #8	; 0x41000000
+0[0-9a-f]+ <[^>]+> f2830f50 	vmov\.f32	q0, #16	; 0x41800000
+0[0-9a-f]+ <[^>]+> f2840f50 	vmov\.f32	q0, #0\.125	; 0x3e000000
+0[0-9a-f]+ <[^>]+> f2850f50 	vmov\.f32	q0, #0\.25	; 0x3e800000
+0[0-9a-f]+ <[^>]+> f2860f50 	vmov\.f32	q0, #0\.5	; 0x3f000000
+0[0-9a-f]+ <[^>]+> f2870f50 	vmov\.f32	q0, #1	; 0x3f800000
+0[0-9a-f]+ <[^>]+> f2800f51 	vmov\.f32	q0, #2\.125	; 0x40080000
+0[0-9a-f]+ <[^>]+> f2810f51 	vmov\.f32	q0, #4\.25	; 0x40880000
+0[0-9a-f]+ <[^>]+> f2820f51 	vmov\.f32	q0, #8\.5	; 0x41080000
+0[0-9a-f]+ <[^>]+> f2830f51 	vmov\.f32	q0, #17	; 0x41880000
+0[0-9a-f]+ <[^>]+> f2840f51 	vmov\.f32	q0, #0\.1328125	; 0x3e080000
+0[0-9a-f]+ <[^>]+> f2850f51 	vmov\.f32	q0, #0\.265625	; 0x3e880000
+0[0-9a-f]+ <[^>]+> f2860f51 	vmov\.f32	q0, #0\.53125	; 0x3f080000
+0[0-9a-f]+ <[^>]+> f2870f51 	vmov\.f32	q0, #1\.0625	; 0x3f880000
+0[0-9a-f]+ <[^>]+> f2800f52 	vmov\.f32	q0, #2\.25	; 0x40100000
+0[0-9a-f]+ <[^>]+> f2810f52 	vmov\.f32	q0, #4\.5	; 0x40900000
+0[0-9a-f]+ <[^>]+> f2820f52 	vmov\.f32	q0, #9	; 0x41100000
+0[0-9a-f]+ <[^>]+> f2830f52 	vmov\.f32	q0, #18	; 0x41900000
+0[0-9a-f]+ <[^>]+> f2840f52 	vmov\.f32	q0, #0\.140625	; 0x3e100000
+0[0-9a-f]+ <[^>]+> f2850f52 	vmov\.f32	q0, #0\.28125	; 0x3e900000
+0[0-9a-f]+ <[^>]+> f2860f52 	vmov\.f32	q0, #0\.5625	; 0x3f100000
+0[0-9a-f]+ <[^>]+> f2870f52 	vmov\.f32	q0, #1\.125	; 0x3f900000
+0[0-9a-f]+ <[^>]+> f2800f53 	vmov\.f32	q0, #2\.375	; 0x40180000
+0[0-9a-f]+ <[^>]+> f2810f53 	vmov\.f32	q0, #4\.75	; 0x40980000
+0[0-9a-f]+ <[^>]+> f2820f53 	vmov\.f32	q0, #9\.5	; 0x41180000
+0[0-9a-f]+ <[^>]+> f2830f53 	vmov\.f32	q0, #19	; 0x41980000
+0[0-9a-f]+ <[^>]+> f2840f53 	vmov\.f32	q0, #0\.1484375	; 0x3e180000
+0[0-9a-f]+ <[^>]+> f2850f53 	vmov\.f32	q0, #0\.296875	; 0x3e980000
+0[0-9a-f]+ <[^>]+> f2860f53 	vmov\.f32	q0, #0\.59375	; 0x3f180000
+0[0-9a-f]+ <[^>]+> f2870f53 	vmov\.f32	q0, #1\.1875	; 0x3f980000
+0[0-9a-f]+ <[^>]+> f2800f54 	vmov\.f32	q0, #2\.5	; 0x40200000
+0[0-9a-f]+ <[^>]+> f2810f54 	vmov\.f32	q0, #5	; 0x40a00000
+0[0-9a-f]+ <[^>]+> f2820f54 	vmov\.f32	q0, #10	; 0x41200000
+0[0-9a-f]+ <[^>]+> f2830f54 	vmov\.f32	q0, #20	; 0x41a00000
+0[0-9a-f]+ <[^>]+> f2840f54 	vmov\.f32	q0, #0\.15625	; 0x3e200000
+0[0-9a-f]+ <[^>]+> f2850f54 	vmov\.f32	q0, #0\.3125	; 0x3ea00000
+0[0-9a-f]+ <[^>]+> f2860f54 	vmov\.f32	q0, #0\.625	; 0x3f200000
+0[0-9a-f]+ <[^>]+> f2870f54 	vmov\.f32	q0, #1\.25	; 0x3fa00000
+0[0-9a-f]+ <[^>]+> f2800f55 	vmov\.f32	q0, #2\.625	; 0x40280000
+0[0-9a-f]+ <[^>]+> f2810f55 	vmov\.f32	q0, #5\.25	; 0x40a80000
+0[0-9a-f]+ <[^>]+> f2820f55 	vmov\.f32	q0, #10\.5	; 0x41280000
+0[0-9a-f]+ <[^>]+> f2830f55 	vmov\.f32	q0, #21	; 0x41a80000
+0[0-9a-f]+ <[^>]+> f2840f55 	vmov\.f32	q0, #0\.1640625	; 0x3e280000
+0[0-9a-f]+ <[^>]+> f2850f55 	vmov\.f32	q0, #0\.328125	; 0x3ea80000
+0[0-9a-f]+ <[^>]+> f2860f55 	vmov\.f32	q0, #0\.65625	; 0x3f280000
+0[0-9a-f]+ <[^>]+> f2870f55 	vmov\.f32	q0, #1\.3125	; 0x3fa80000
+0[0-9a-f]+ <[^>]+> f2800f56 	vmov\.f32	q0, #2\.75	; 0x40300000
+0[0-9a-f]+ <[^>]+> f2810f56 	vmov\.f32	q0, #5\.5	; 0x40b00000
+0[0-9a-f]+ <[^>]+> f2820f56 	vmov\.f32	q0, #11	; 0x41300000
+0[0-9a-f]+ <[^>]+> f2830f56 	vmov\.f32	q0, #22	; 0x41b00000
+0[0-9a-f]+ <[^>]+> f2840f56 	vmov\.f32	q0, #0\.171875	; 0x3e300000
+0[0-9a-f]+ <[^>]+> f2850f56 	vmov\.f32	q0, #0\.34375	; 0x3eb00000
+0[0-9a-f]+ <[^>]+> f2860f56 	vmov\.f32	q0, #0\.6875	; 0x3f300000
+0[0-9a-f]+ <[^>]+> f2870f56 	vmov\.f32	q0, #1\.375	; 0x3fb00000
+0[0-9a-f]+ <[^>]+> f2800f57 	vmov\.f32	q0, #2\.875	; 0x40380000
+0[0-9a-f]+ <[^>]+> f2810f57 	vmov\.f32	q0, #5\.75	; 0x40b80000
+0[0-9a-f]+ <[^>]+> f2820f57 	vmov\.f32	q0, #11\.5	; 0x41380000
+0[0-9a-f]+ <[^>]+> f2830f57 	vmov\.f32	q0, #23	; 0x41b80000
+0[0-9a-f]+ <[^>]+> f2840f57 	vmov\.f32	q0, #0\.1796875	; 0x3e380000
+0[0-9a-f]+ <[^>]+> f2850f57 	vmov\.f32	q0, #0\.359375	; 0x3eb80000
+0[0-9a-f]+ <[^>]+> f2860f57 	vmov\.f32	q0, #0\.71875	; 0x3f380000
+0[0-9a-f]+ <[^>]+> f2870f57 	vmov\.f32	q0, #1\.4375	; 0x3fb80000
+0[0-9a-f]+ <[^>]+> f2800f58 	vmov\.f32	q0, #3	; 0x40400000
+0[0-9a-f]+ <[^>]+> f2810f58 	vmov\.f32	q0, #6	; 0x40c00000
+0[0-9a-f]+ <[^>]+> f2820f58 	vmov\.f32	q0, #12	; 0x41400000
+0[0-9a-f]+ <[^>]+> f2830f58 	vmov\.f32	q0, #24	; 0x41c00000
+0[0-9a-f]+ <[^>]+> f2840f58 	vmov\.f32	q0, #0\.1875	; 0x3e400000
+0[0-9a-f]+ <[^>]+> f2850f58 	vmov\.f32	q0, #0\.375	; 0x3ec00000
+0[0-9a-f]+ <[^>]+> f2860f58 	vmov\.f32	q0, #0\.75	; 0x3f400000
+0[0-9a-f]+ <[^>]+> f2870f58 	vmov\.f32	q0, #1\.5	; 0x3fc00000
+0[0-9a-f]+ <[^>]+> f2800f59 	vmov\.f32	q0, #3\.125	; 0x40480000
+0[0-9a-f]+ <[^>]+> f2810f59 	vmov\.f32	q0, #6\.25	; 0x40c80000
+0[0-9a-f]+ <[^>]+> f2820f59 	vmov\.f32	q0, #12\.5	; 0x41480000
+0[0-9a-f]+ <[^>]+> f2830f59 	vmov\.f32	q0, #25	; 0x41c80000
+0[0-9a-f]+ <[^>]+> f2840f59 	vmov\.f32	q0, #0\.1953125	; 0x3e480000
+0[0-9a-f]+ <[^>]+> f2850f59 	vmov\.f32	q0, #0\.390625	; 0x3ec80000
+0[0-9a-f]+ <[^>]+> f2860f59 	vmov\.f32	q0, #0\.78125	; 0x3f480000
+0[0-9a-f]+ <[^>]+> f2870f59 	vmov\.f32	q0, #1\.5625	; 0x3fc80000
+0[0-9a-f]+ <[^>]+> f2800f5a 	vmov\.f32	q0, #3\.25	; 0x40500000
+0[0-9a-f]+ <[^>]+> f2810f5a 	vmov\.f32	q0, #6\.5	; 0x40d00000
+0[0-9a-f]+ <[^>]+> f2820f5a 	vmov\.f32	q0, #13	; 0x41500000
+0[0-9a-f]+ <[^>]+> f2830f5a 	vmov\.f32	q0, #26	; 0x41d00000
+0[0-9a-f]+ <[^>]+> f2840f5a 	vmov\.f32	q0, #0\.203125	; 0x3e500000
+0[0-9a-f]+ <[^>]+> f2850f5a 	vmov\.f32	q0, #0\.40625	; 0x3ed00000
+0[0-9a-f]+ <[^>]+> f2860f5a 	vmov\.f32	q0, #0\.8125	; 0x3f500000
+0[0-9a-f]+ <[^>]+> f2870f5a 	vmov\.f32	q0, #1\.625	; 0x3fd00000
+0[0-9a-f]+ <[^>]+> f2800f5b 	vmov\.f32	q0, #3\.375	; 0x40580000
+0[0-9a-f]+ <[^>]+> f2810f5b 	vmov\.f32	q0, #6\.75	; 0x40d80000
+0[0-9a-f]+ <[^>]+> f2820f5b 	vmov\.f32	q0, #13\.5	; 0x41580000
+0[0-9a-f]+ <[^>]+> f2830f5b 	vmov\.f32	q0, #27	; 0x41d80000
+0[0-9a-f]+ <[^>]+> f2840f5b 	vmov\.f32	q0, #0\.2109375	; 0x3e580000
+0[0-9a-f]+ <[^>]+> f2850f5b 	vmov\.f32	q0, #0\.421875	; 0x3ed80000
+0[0-9a-f]+ <[^>]+> f2860f5b 	vmov\.f32	q0, #0\.84375	; 0x3f580000
+0[0-9a-f]+ <[^>]+> f2870f5b 	vmov\.f32	q0, #1\.6875	; 0x3fd80000
+0[0-9a-f]+ <[^>]+> f2800f5c 	vmov\.f32	q0, #3\.5	; 0x40600000
+0[0-9a-f]+ <[^>]+> f2810f5c 	vmov\.f32	q0, #7	; 0x40e00000
+0[0-9a-f]+ <[^>]+> f2820f5c 	vmov\.f32	q0, #14	; 0x41600000
+0[0-9a-f]+ <[^>]+> f2830f5c 	vmov\.f32	q0, #28	; 0x41e00000
+0[0-9a-f]+ <[^>]+> f2840f5c 	vmov\.f32	q0, #0\.21875	; 0x3e600000
+0[0-9a-f]+ <[^>]+> f2850f5c 	vmov\.f32	q0, #0\.4375	; 0x3ee00000
+0[0-9a-f]+ <[^>]+> f2860f5c 	vmov\.f32	q0, #0\.875	; 0x3f600000
+0[0-9a-f]+ <[^>]+> f2870f5c 	vmov\.f32	q0, #1\.75	; 0x3fe00000
+0[0-9a-f]+ <[^>]+> f2800f5d 	vmov\.f32	q0, #3\.625	; 0x40680000
+0[0-9a-f]+ <[^>]+> f2810f5d 	vmov\.f32	q0, #7\.25	; 0x40e80000
+0[0-9a-f]+ <[^>]+> f2820f5d 	vmov\.f32	q0, #14\.5	; 0x41680000
+0[0-9a-f]+ <[^>]+> f2830f5d 	vmov\.f32	q0, #29	; 0x41e80000
+0[0-9a-f]+ <[^>]+> f2840f5d 	vmov\.f32	q0, #0\.2265625	; 0x3e680000
+0[0-9a-f]+ <[^>]+> f2850f5d 	vmov\.f32	q0, #0\.453125	; 0x3ee80000
+0[0-9a-f]+ <[^>]+> f2860f5d 	vmov\.f32	q0, #0\.90625	; 0x3f680000
+0[0-9a-f]+ <[^>]+> f2870f5d 	vmov\.f32	q0, #1\.8125	; 0x3fe80000
+0[0-9a-f]+ <[^>]+> f2800f5e 	vmov\.f32	q0, #3\.75	; 0x40700000
+0[0-9a-f]+ <[^>]+> f2810f5e 	vmov\.f32	q0, #7\.5	; 0x40f00000
+0[0-9a-f]+ <[^>]+> f2820f5e 	vmov\.f32	q0, #15	; 0x41700000
+0[0-9a-f]+ <[^>]+> f2830f5e 	vmov\.f32	q0, #30	; 0x41f00000
+0[0-9a-f]+ <[^>]+> f2840f5e 	vmov\.f32	q0, #0\.234375	; 0x3e700000
+0[0-9a-f]+ <[^>]+> f2850f5e 	vmov\.f32	q0, #0\.46875	; 0x3ef00000
+0[0-9a-f]+ <[^>]+> f2860f5e 	vmov\.f32	q0, #0\.9375	; 0x3f700000
+0[0-9a-f]+ <[^>]+> f2870f5e 	vmov\.f32	q0, #1\.875	; 0x3ff00000
+0[0-9a-f]+ <[^>]+> f2800f5f 	vmov\.f32	q0, #3\.875	; 0x40780000
+0[0-9a-f]+ <[^>]+> f2810f5f 	vmov\.f32	q0, #7\.75	; 0x40f80000
+0[0-9a-f]+ <[^>]+> f2820f5f 	vmov\.f32	q0, #15\.5	; 0x41780000
+0[0-9a-f]+ <[^>]+> f2830f5f 	vmov\.f32	q0, #31	; 0x41f80000
+0[0-9a-f]+ <[^>]+> f2840f5f 	vmov\.f32	q0, #0\.2421875	; 0x3e780000
+0[0-9a-f]+ <[^>]+> f2850f5f 	vmov\.f32	q0, #0\.484375	; 0x3ef80000
+0[0-9a-f]+ <[^>]+> f2860f5f 	vmov\.f32	q0, #0\.96875	; 0x3f780000
+0[0-9a-f]+ <[^>]+> f2870f5f 	vmov\.f32	q0, #1\.9375	; 0x3ff80000
+0[0-9a-f]+ <[^>]+> f3800650 	vmov\.i32	q0, #-2147483648	; 0x80000000
+0[0-9a-f]+ <[^>]+> f3800f50 	vmov\.f32	q0, #-2	; 0xc0000000
+0[0-9a-f]+ <[^>]+> f3810f50 	vmov\.f32	q0, #-4	; 0xc0800000
+0[0-9a-f]+ <[^>]+> f3820f50 	vmov\.f32	q0, #-8	; 0xc1000000
+0[0-9a-f]+ <[^>]+> f3830f50 	vmov\.f32	q0, #-16	; 0xc1800000
+0[0-9a-f]+ <[^>]+> f3840f50 	vmov\.f32	q0, #-0\.125	; 0xbe000000
+0[0-9a-f]+ <[^>]+> f3850f50 	vmov\.f32	q0, #-0\.25	; 0xbe800000
+0[0-9a-f]+ <[^>]+> f3860f50 	vmov\.f32	q0, #-0\.5	; 0xbf000000
+0[0-9a-f]+ <[^>]+> f3870f50 	vmov\.f32	q0, #-1	; 0xbf800000
+0[0-9a-f]+ <[^>]+> f3800f51 	vmov\.f32	q0, #-2\.125	; 0xc0080000
+0[0-9a-f]+ <[^>]+> f3810f51 	vmov\.f32	q0, #-4\.25	; 0xc0880000
+0[0-9a-f]+ <[^>]+> f3820f51 	vmov\.f32	q0, #-8\.5	; 0xc1080000
+0[0-9a-f]+ <[^>]+> f3830f51 	vmov\.f32	q0, #-17	; 0xc1880000
+0[0-9a-f]+ <[^>]+> f3840f51 	vmov\.f32	q0, #-0\.1328125	; 0xbe080000
+0[0-9a-f]+ <[^>]+> f3850f51 	vmov\.f32	q0, #-0\.265625	; 0xbe880000
+0[0-9a-f]+ <[^>]+> f3860f51 	vmov\.f32	q0, #-0\.53125	; 0xbf080000
+0[0-9a-f]+ <[^>]+> f3870f51 	vmov\.f32	q0, #-1\.0625	; 0xbf880000
+0[0-9a-f]+ <[^>]+> f3800f52 	vmov\.f32	q0, #-2\.25	; 0xc0100000
+0[0-9a-f]+ <[^>]+> f3810f52 	vmov\.f32	q0, #-4\.5	; 0xc0900000
+0[0-9a-f]+ <[^>]+> f3820f52 	vmov\.f32	q0, #-9	; 0xc1100000
+0[0-9a-f]+ <[^>]+> f3830f52 	vmov\.f32	q0, #-18	; 0xc1900000
+0[0-9a-f]+ <[^>]+> f3840f52 	vmov\.f32	q0, #-0\.140625	; 0xbe100000
+0[0-9a-f]+ <[^>]+> f3850f52 	vmov\.f32	q0, #-0\.28125	; 0xbe900000
+0[0-9a-f]+ <[^>]+> f3860f52 	vmov\.f32	q0, #-0\.5625	; 0xbf100000
+0[0-9a-f]+ <[^>]+> f3870f52 	vmov\.f32	q0, #-1\.125	; 0xbf900000
+0[0-9a-f]+ <[^>]+> f3800f53 	vmov\.f32	q0, #-2\.375	; 0xc0180000
+0[0-9a-f]+ <[^>]+> f3810f53 	vmov\.f32	q0, #-4\.75	; 0xc0980000
+0[0-9a-f]+ <[^>]+> f3820f53 	vmov\.f32	q0, #-9\.5	; 0xc1180000
+0[0-9a-f]+ <[^>]+> f3830f53 	vmov\.f32	q0, #-19	; 0xc1980000
+0[0-9a-f]+ <[^>]+> f3840f53 	vmov\.f32	q0, #-0\.1484375	; 0xbe180000
+0[0-9a-f]+ <[^>]+> f3850f53 	vmov\.f32	q0, #-0\.296875	; 0xbe980000
+0[0-9a-f]+ <[^>]+> f3860f53 	vmov\.f32	q0, #-0\.59375	; 0xbf180000
+0[0-9a-f]+ <[^>]+> f3870f53 	vmov\.f32	q0, #-1\.1875	; 0xbf980000
+0[0-9a-f]+ <[^>]+> f3800f54 	vmov\.f32	q0, #-2\.5	; 0xc0200000
+0[0-9a-f]+ <[^>]+> f3810f54 	vmov\.f32	q0, #-5	; 0xc0a00000
+0[0-9a-f]+ <[^>]+> f3820f54 	vmov\.f32	q0, #-10	; 0xc1200000
+0[0-9a-f]+ <[^>]+> f3830f54 	vmov\.f32	q0, #-20	; 0xc1a00000
+0[0-9a-f]+ <[^>]+> f3840f54 	vmov\.f32	q0, #-0\.15625	; 0xbe200000
+0[0-9a-f]+ <[^>]+> f3850f54 	vmov\.f32	q0, #-0\.3125	; 0xbea00000
+0[0-9a-f]+ <[^>]+> f3860f54 	vmov\.f32	q0, #-0\.625	; 0xbf200000
+0[0-9a-f]+ <[^>]+> f3870f54 	vmov\.f32	q0, #-1\.25	; 0xbfa00000
+0[0-9a-f]+ <[^>]+> f3800f55 	vmov\.f32	q0, #-2\.625	; 0xc0280000
+0[0-9a-f]+ <[^>]+> f3810f55 	vmov\.f32	q0, #-5\.25	; 0xc0a80000
+0[0-9a-f]+ <[^>]+> f3820f55 	vmov\.f32	q0, #-10\.5	; 0xc1280000
+0[0-9a-f]+ <[^>]+> f3830f55 	vmov\.f32	q0, #-21	; 0xc1a80000
+0[0-9a-f]+ <[^>]+> f3840f55 	vmov\.f32	q0, #-0\.1640625	; 0xbe280000
+0[0-9a-f]+ <[^>]+> f3850f55 	vmov\.f32	q0, #-0\.328125	; 0xbea80000
+0[0-9a-f]+ <[^>]+> f3860f55 	vmov\.f32	q0, #-0\.65625	; 0xbf280000
+0[0-9a-f]+ <[^>]+> f3870f55 	vmov\.f32	q0, #-1\.3125	; 0xbfa80000
+0[0-9a-f]+ <[^>]+> f3800f56 	vmov\.f32	q0, #-2\.75	; 0xc0300000
+0[0-9a-f]+ <[^>]+> f3810f56 	vmov\.f32	q0, #-5\.5	; 0xc0b00000
+0[0-9a-f]+ <[^>]+> f3820f56 	vmov\.f32	q0, #-11	; 0xc1300000
+0[0-9a-f]+ <[^>]+> f3830f56 	vmov\.f32	q0, #-22	; 0xc1b00000
+0[0-9a-f]+ <[^>]+> f3840f56 	vmov\.f32	q0, #-0\.171875	; 0xbe300000
+0[0-9a-f]+ <[^>]+> f3850f56 	vmov\.f32	q0, #-0\.34375	; 0xbeb00000
+0[0-9a-f]+ <[^>]+> f3860f56 	vmov\.f32	q0, #-0\.6875	; 0xbf300000
+0[0-9a-f]+ <[^>]+> f3870f56 	vmov\.f32	q0, #-1\.375	; 0xbfb00000
+0[0-9a-f]+ <[^>]+> f3800f57 	vmov\.f32	q0, #-2\.875	; 0xc0380000
+0[0-9a-f]+ <[^>]+> f3810f57 	vmov\.f32	q0, #-5\.75	; 0xc0b80000
+0[0-9a-f]+ <[^>]+> f3820f57 	vmov\.f32	q0, #-11\.5	; 0xc1380000
+0[0-9a-f]+ <[^>]+> f3830f57 	vmov\.f32	q0, #-23	; 0xc1b80000
+0[0-9a-f]+ <[^>]+> f3840f57 	vmov\.f32	q0, #-0\.1796875	; 0xbe380000
+0[0-9a-f]+ <[^>]+> f3850f57 	vmov\.f32	q0, #-0\.359375	; 0xbeb80000
+0[0-9a-f]+ <[^>]+> f3860f57 	vmov\.f32	q0, #-0\.71875	; 0xbf380000
+0[0-9a-f]+ <[^>]+> f3870f57 	vmov\.f32	q0, #-1\.4375	; 0xbfb80000
+0[0-9a-f]+ <[^>]+> f3800f58 	vmov\.f32	q0, #-3	; 0xc0400000
+0[0-9a-f]+ <[^>]+> f3810f58 	vmov\.f32	q0, #-6	; 0xc0c00000
+0[0-9a-f]+ <[^>]+> f3820f58 	vmov\.f32	q0, #-12	; 0xc1400000
+0[0-9a-f]+ <[^>]+> f3830f58 	vmov\.f32	q0, #-24	; 0xc1c00000
+0[0-9a-f]+ <[^>]+> f3840f58 	vmov\.f32	q0, #-0\.1875	; 0xbe400000
+0[0-9a-f]+ <[^>]+> f3850f58 	vmov\.f32	q0, #-0\.375	; 0xbec00000
+0[0-9a-f]+ <[^>]+> f3860f58 	vmov\.f32	q0, #-0\.75	; 0xbf400000
+0[0-9a-f]+ <[^>]+> f3870f58 	vmov\.f32	q0, #-1\.5	; 0xbfc00000
+0[0-9a-f]+ <[^>]+> f3800f59 	vmov\.f32	q0, #-3\.125	; 0xc0480000
+0[0-9a-f]+ <[^>]+> f3810f59 	vmov\.f32	q0, #-6\.25	; 0xc0c80000
+0[0-9a-f]+ <[^>]+> f3820f59 	vmov\.f32	q0, #-12\.5	; 0xc1480000
+0[0-9a-f]+ <[^>]+> f3830f59 	vmov\.f32	q0, #-25	; 0xc1c80000
+0[0-9a-f]+ <[^>]+> f3840f59 	vmov\.f32	q0, #-0\.1953125	; 0xbe480000
+0[0-9a-f]+ <[^>]+> f3850f59 	vmov\.f32	q0, #-0\.390625	; 0xbec80000
+0[0-9a-f]+ <[^>]+> f3860f59 	vmov\.f32	q0, #-0\.78125	; 0xbf480000
+0[0-9a-f]+ <[^>]+> f3870f59 	vmov\.f32	q0, #-1\.5625	; 0xbfc80000
+0[0-9a-f]+ <[^>]+> f3800f5a 	vmov\.f32	q0, #-3\.25	; 0xc0500000
+0[0-9a-f]+ <[^>]+> f3810f5a 	vmov\.f32	q0, #-6\.5	; 0xc0d00000
+0[0-9a-f]+ <[^>]+> f3820f5a 	vmov\.f32	q0, #-13	; 0xc1500000
+0[0-9a-f]+ <[^>]+> f3830f5a 	vmov\.f32	q0, #-26	; 0xc1d00000
+0[0-9a-f]+ <[^>]+> f3840f5a 	vmov\.f32	q0, #-0\.203125	; 0xbe500000
+0[0-9a-f]+ <[^>]+> f3850f5a 	vmov\.f32	q0, #-0\.40625	; 0xbed00000
+0[0-9a-f]+ <[^>]+> f3860f5a 	vmov\.f32	q0, #-0\.8125	; 0xbf500000
+0[0-9a-f]+ <[^>]+> f3870f5a 	vmov\.f32	q0, #-1\.625	; 0xbfd00000
+0[0-9a-f]+ <[^>]+> f3800f5b 	vmov\.f32	q0, #-3\.375	; 0xc0580000
+0[0-9a-f]+ <[^>]+> f3810f5b 	vmov\.f32	q0, #-6\.75	; 0xc0d80000
+0[0-9a-f]+ <[^>]+> f3820f5b 	vmov\.f32	q0, #-13\.5	; 0xc1580000
+0[0-9a-f]+ <[^>]+> f3830f5b 	vmov\.f32	q0, #-27	; 0xc1d80000
+0[0-9a-f]+ <[^>]+> f3840f5b 	vmov\.f32	q0, #-0\.2109375	; 0xbe580000
+0[0-9a-f]+ <[^>]+> f3850f5b 	vmov\.f32	q0, #-0\.421875	; 0xbed80000
+0[0-9a-f]+ <[^>]+> f3860f5b 	vmov\.f32	q0, #-0\.84375	; 0xbf580000
+0[0-9a-f]+ <[^>]+> f3870f5b 	vmov\.f32	q0, #-1\.6875	; 0xbfd80000
+0[0-9a-f]+ <[^>]+> f3800f5c 	vmov\.f32	q0, #-3\.5	; 0xc0600000
+0[0-9a-f]+ <[^>]+> f3810f5c 	vmov\.f32	q0, #-7	; 0xc0e00000
+0[0-9a-f]+ <[^>]+> f3820f5c 	vmov\.f32	q0, #-14	; 0xc1600000
+0[0-9a-f]+ <[^>]+> f3830f5c 	vmov\.f32	q0, #-28	; 0xc1e00000
+0[0-9a-f]+ <[^>]+> f3840f5c 	vmov\.f32	q0, #-0\.21875	; 0xbe600000
+0[0-9a-f]+ <[^>]+> f3850f5c 	vmov\.f32	q0, #-0\.4375	; 0xbee00000
+0[0-9a-f]+ <[^>]+> f3860f5c 	vmov\.f32	q0, #-0\.875	; 0xbf600000
+0[0-9a-f]+ <[^>]+> f3870f5c 	vmov\.f32	q0, #-1\.75	; 0xbfe00000
+0[0-9a-f]+ <[^>]+> f3800f5d 	vmov\.f32	q0, #-3\.625	; 0xc0680000
+0[0-9a-f]+ <[^>]+> f3810f5d 	vmov\.f32	q0, #-7\.25	; 0xc0e80000
+0[0-9a-f]+ <[^>]+> f3820f5d 	vmov\.f32	q0, #-14\.5	; 0xc1680000
+0[0-9a-f]+ <[^>]+> f3830f5d 	vmov\.f32	q0, #-29	; 0xc1e80000
+0[0-9a-f]+ <[^>]+> f3840f5d 	vmov\.f32	q0, #-0\.2265625	; 0xbe680000
+0[0-9a-f]+ <[^>]+> f3850f5d 	vmov\.f32	q0, #-0\.453125	; 0xbee80000
+0[0-9a-f]+ <[^>]+> f3860f5d 	vmov\.f32	q0, #-0\.90625	; 0xbf680000
+0[0-9a-f]+ <[^>]+> f3870f5d 	vmov\.f32	q0, #-1\.8125	; 0xbfe80000
+0[0-9a-f]+ <[^>]+> f3800f5e 	vmov\.f32	q0, #-3\.75	; 0xc0700000
+0[0-9a-f]+ <[^>]+> f3810f5e 	vmov\.f32	q0, #-7\.5	; 0xc0f00000
+0[0-9a-f]+ <[^>]+> f3820f5e 	vmov\.f32	q0, #-15	; 0xc1700000
+0[0-9a-f]+ <[^>]+> f3830f5e 	vmov\.f32	q0, #-30	; 0xc1f00000
+0[0-9a-f]+ <[^>]+> f3840f5e 	vmov\.f32	q0, #-0\.234375	; 0xbe700000
+0[0-9a-f]+ <[^>]+> f3850f5e 	vmov\.f32	q0, #-0\.46875	; 0xbef00000
+0[0-9a-f]+ <[^>]+> f3860f5e 	vmov\.f32	q0, #-0\.9375	; 0xbf700000
+0[0-9a-f]+ <[^>]+> f3870f5e 	vmov\.f32	q0, #-1\.875	; 0xbff00000
+0[0-9a-f]+ <[^>]+> f3800f5f 	vmov\.f32	q0, #-3\.875	; 0xc0780000
+0[0-9a-f]+ <[^>]+> f3810f5f 	vmov\.f32	q0, #-7\.75	; 0xc0f80000
+0[0-9a-f]+ <[^>]+> f3820f5f 	vmov\.f32	q0, #-15\.5	; 0xc1780000
+0[0-9a-f]+ <[^>]+> f3830f5f 	vmov\.f32	q0, #-31	; 0xc1f80000
+0[0-9a-f]+ <[^>]+> f3840f5f 	vmov\.f32	q0, #-0\.2421875	; 0xbe780000
+0[0-9a-f]+ <[^>]+> f3850f5f 	vmov\.f32	q0, #-0\.484375	; 0xbef80000
+0[0-9a-f]+ <[^>]+> f3860f5f 	vmov\.f32	q0, #-0\.96875	; 0xbf780000
+0[0-9a-f]+ <[^>]+> f3870f5f 	vmov\.f32	q0, #-1\.9375	; 0xbff80000
diff --git a/gas/testsuite/gas/arm/neon-const.s b/gas/testsuite/gas/arm/neon-const.s
new file mode 100644
index 000000000000..a6fb55075a93
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-const.s
@@ -0,0 +1,297 @@
+@ test floating-point constant parsing.
+
+	.arm
+	.text
+	.syntax unified
+
+        vmov.f32 q0, 0.0
+
+	vmov.f32 q0, 2.0
+        vmov.f32 q0, 4.0
+        vmov.f32 q0, 8.0
+        vmov.f32 q0, 16.0
+        vmov.f32 q0, 0.125
+        vmov.f32 q0, 0.25
+        vmov.f32 q0, 0.5
+        vmov.f32 q0, 1.0
+
+        vmov.f32 q0, 2.125
+        vmov.f32 q0, 4.25
+        vmov.f32 q0, 8.5
+        vmov.f32 q0, 17.0
+        vmov.f32 q0, 0.1328125
+        vmov.f32 q0, 0.265625
+        vmov.f32 q0, 0.53125
+        vmov.f32 q0, 1.0625
+        
+        vmov.f32 q0, 2.25
+        vmov.f32 q0, 4.5
+        vmov.f32 q0, 9.0
+        vmov.f32 q0, 18.0
+        vmov.f32 q0, 0.140625
+        vmov.f32 q0, 0.28125
+        vmov.f32 q0, 0.5625
+        vmov.f32 q0, 1.125
+        
+        vmov.f32 q0, 2.375
+        vmov.f32 q0, 4.75
+        vmov.f32 q0, 9.5
+        vmov.f32 q0, 19.0
+        vmov.f32 q0, 0.1484375
+        vmov.f32 q0, 0.296875
+        vmov.f32 q0, 0.59375
+        vmov.f32 q0, 1.1875
+        
+        vmov.f32 q0, 2.5
+        vmov.f32 q0, 5.0
+        vmov.f32 q0, 10.0
+        vmov.f32 q0, 20.0
+        vmov.f32 q0, 0.15625
+        vmov.f32 q0, 0.3125
+        vmov.f32 q0, 0.625
+        vmov.f32 q0, 1.25
+        
+        vmov.f32 q0, 2.625
+        vmov.f32 q0, 5.25
+        vmov.f32 q0, 10.5
+        vmov.f32 q0, 21.0
+        vmov.f32 q0, 0.1640625
+        vmov.f32 q0, 0.328125
+        vmov.f32 q0, 0.65625
+        vmov.f32 q0, 1.3125
+        
+        vmov.f32 q0, 2.75
+        vmov.f32 q0, 5.5
+        vmov.f32 q0, 11.0
+        vmov.f32 q0, 22.0
+        vmov.f32 q0, 0.171875
+        vmov.f32 q0, 0.34375
+        vmov.f32 q0, 0.6875
+        vmov.f32 q0, 1.375
+        
+        vmov.f32 q0, 2.875
+        vmov.f32 q0, 5.75
+        vmov.f32 q0, 11.5
+        vmov.f32 q0, 23.0
+        vmov.f32 q0, 0.1796875
+        vmov.f32 q0, 0.359375
+        vmov.f32 q0, 0.71875
+        vmov.f32 q0, 1.4375
+        
+        vmov.f32 q0, 3.0
+        vmov.f32 q0, 6.0
+        vmov.f32 q0, 12.0
+        vmov.f32 q0, 24.0
+        vmov.f32 q0, 0.1875
+        vmov.f32 q0, 0.375
+        vmov.f32 q0, 0.75
+        vmov.f32 q0, 1.5
+        
+        vmov.f32 q0, 3.125
+        vmov.f32 q0, 6.25
+        vmov.f32 q0, 12.5
+        vmov.f32 q0, 25.0
+        vmov.f32 q0, 0.1953125
+        vmov.f32 q0, 0.390625
+        vmov.f32 q0, 0.78125
+        vmov.f32 q0, 1.5625
+        
+        vmov.f32 q0, 3.25
+        vmov.f32 q0, 6.5
+        vmov.f32 q0, 13.0
+        vmov.f32 q0, 26.0
+        vmov.f32 q0, 0.203125
+        vmov.f32 q0, 0.40625
+        vmov.f32 q0, 0.8125
+        vmov.f32 q0, 1.625
+        
+        vmov.f32 q0, 3.375
+        vmov.f32 q0, 6.75
+        vmov.f32 q0, 13.5
+        vmov.f32 q0, 27.0
+        vmov.f32 q0, 0.2109375
+        vmov.f32 q0, 0.421875
+        vmov.f32 q0, 0.84375
+        vmov.f32 q0, 1.6875
+
+        vmov.f32 q0, 3.5
+        vmov.f32 q0, 7.0
+        vmov.f32 q0, 14.0
+        vmov.f32 q0, 28.0
+        vmov.f32 q0, 0.21875
+        vmov.f32 q0, 0.4375
+        vmov.f32 q0, 0.875
+        vmov.f32 q0, 1.75
+        
+        vmov.f32 q0, 3.625
+        vmov.f32 q0, 7.25
+        vmov.f32 q0, 14.5
+        vmov.f32 q0, 29.0
+        vmov.f32 q0, 0.2265625
+        vmov.f32 q0, 0.453125
+        vmov.f32 q0, 0.90625
+        vmov.f32 q0, 1.8125
+        
+        vmov.f32 q0, 3.75
+        vmov.f32 q0, 7.5
+        vmov.f32 q0, 15.0
+        vmov.f32 q0, 30.0
+        vmov.f32 q0, 0.234375
+        vmov.f32 q0, 0.46875
+        vmov.f32 q0, 0.9375
+        vmov.f32 q0, 1.875
+        
+        vmov.f32 q0, 3.875
+        vmov.f32 q0, 7.75
+        vmov.f32 q0, 15.5
+        vmov.f32 q0, 31.0
+        vmov.f32 q0, 0.2421875
+        vmov.f32 q0, 0.484375
+        vmov.f32 q0, 0.96875
+        vmov.f32 q0, 1.9375
+
+        vmov.f32 q0, -0.0
+
+	vmov.f32 q0, -2.0
+        vmov.f32 q0, -4.0
+        vmov.f32 q0, -8.0
+        vmov.f32 q0, -16.0
+        vmov.f32 q0, -0.125
+        vmov.f32 q0, -0.25
+        vmov.f32 q0, -0.5
+        vmov.f32 q0, -1.0
+
+        vmov.f32 q0, -2.125
+        vmov.f32 q0, -4.25
+        vmov.f32 q0, -8.5
+        vmov.f32 q0, -17.0
+        vmov.f32 q0, -0.1328125
+        vmov.f32 q0, -0.265625
+        vmov.f32 q0, -0.53125
+        vmov.f32 q0, -1.0625
+        
+        vmov.f32 q0, -2.25
+        vmov.f32 q0, -4.5
+        vmov.f32 q0, -9.0
+        vmov.f32 q0, -18.0
+        vmov.f32 q0, -0.140625
+        vmov.f32 q0, -0.28125
+        vmov.f32 q0, -0.5625
+        vmov.f32 q0, -1.125
+        
+        vmov.f32 q0, -2.375
+        vmov.f32 q0, -4.75
+        vmov.f32 q0, -9.5
+        vmov.f32 q0, -19.0
+        vmov.f32 q0, -0.1484375
+        vmov.f32 q0, -0.296875
+        vmov.f32 q0, -0.59375
+        vmov.f32 q0, -1.1875
+        
+        vmov.f32 q0, -2.5
+        vmov.f32 q0, -5.0
+        vmov.f32 q0, -10.0
+        vmov.f32 q0, -20.0
+        vmov.f32 q0, -0.15625
+        vmov.f32 q0, -0.3125
+        vmov.f32 q0, -0.625
+        vmov.f32 q0, -1.25
+        
+        vmov.f32 q0, -2.625
+        vmov.f32 q0, -5.25
+        vmov.f32 q0, -10.5
+        vmov.f32 q0, -21.0
+        vmov.f32 q0, -0.1640625
+        vmov.f32 q0, -0.328125
+        vmov.f32 q0, -0.65625
+        vmov.f32 q0, -1.3125
+        
+        vmov.f32 q0, -2.75
+        vmov.f32 q0, -5.5
+        vmov.f32 q0, -11.0
+        vmov.f32 q0, -22.0
+        vmov.f32 q0, -0.171875
+        vmov.f32 q0, -0.34375
+        vmov.f32 q0, -0.6875
+        vmov.f32 q0, -1.375
+        
+        vmov.f32 q0, -2.875
+        vmov.f32 q0, -5.75
+        vmov.f32 q0, -11.5
+        vmov.f32 q0, -23.0
+        vmov.f32 q0, -0.1796875
+        vmov.f32 q0, -0.359375
+        vmov.f32 q0, -0.71875
+        vmov.f32 q0, -1.4375
+        
+        vmov.f32 q0, -3.0
+        vmov.f32 q0, -6.0
+        vmov.f32 q0, -12.0
+        vmov.f32 q0, -24.0
+        vmov.f32 q0, -0.1875
+        vmov.f32 q0, -0.375
+        vmov.f32 q0, -0.75
+        vmov.f32 q0, -1.5
+        
+        vmov.f32 q0, -3.125
+        vmov.f32 q0, -6.25
+        vmov.f32 q0, -12.5
+        vmov.f32 q0, -25.0
+        vmov.f32 q0, -0.1953125
+        vmov.f32 q0, -0.390625
+        vmov.f32 q0, -0.78125
+        vmov.f32 q0, -1.5625
+        
+        vmov.f32 q0, -3.25
+        vmov.f32 q0, -6.5
+        vmov.f32 q0, -13.0
+        vmov.f32 q0, -26.0
+        vmov.f32 q0, -0.203125
+        vmov.f32 q0, -0.40625
+        vmov.f32 q0, -0.8125
+        vmov.f32 q0, -1.625
+        
+        vmov.f32 q0, -3.375
+        vmov.f32 q0, -6.75
+        vmov.f32 q0, -13.5
+        vmov.f32 q0, -27.0
+        vmov.f32 q0, -0.2109375
+        vmov.f32 q0, -0.421875
+        vmov.f32 q0, -0.84375
+        vmov.f32 q0, -1.6875
+
+        vmov.f32 q0, -3.5
+        vmov.f32 q0, -7.0
+        vmov.f32 q0, -14.0
+        vmov.f32 q0, -28.0
+        vmov.f32 q0, -0.21875
+        vmov.f32 q0, -0.4375
+        vmov.f32 q0, -0.875
+        vmov.f32 q0, -1.75
+        
+        vmov.f32 q0, -3.625
+        vmov.f32 q0, -7.25
+        vmov.f32 q0, -14.5
+        vmov.f32 q0, -29.0
+        vmov.f32 q0, -0.2265625
+        vmov.f32 q0, -0.453125
+        vmov.f32 q0, -0.90625
+        vmov.f32 q0, -1.8125
+        
+        vmov.f32 q0, -3.75
+        vmov.f32 q0, -7.5
+        vmov.f32 q0, -15.0
+        vmov.f32 q0, -30.0
+        vmov.f32 q0, -0.234375
+        vmov.f32 q0, -0.46875
+        vmov.f32 q0, -0.9375
+        vmov.f32 q0, -1.875
+        
+        vmov.f32 q0, -3.875
+        vmov.f32 q0, -7.75
+        vmov.f32 q0, -15.5
+        vmov.f32 q0, -31.0
+        vmov.f32 q0, -0.2421875
+        vmov.f32 q0, -0.484375
+        vmov.f32 q0, -0.96875
+        vmov.f32 q0, -1.9375
diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d
new file mode 100644
index 000000000000..e3f02f811f14
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cov.d
@@ -0,0 +1,1522 @@
+# name: Neon instruction coverage
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> f2000750 	vaba\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000750 	vaba\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000710 	vaba\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100750 	vaba\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100750 	vaba\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100710 	vaba\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200750 	vaba\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200750 	vaba\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200710 	vaba\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000750 	vaba\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000750 	vaba\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000710 	vaba\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100750 	vaba\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100750 	vaba\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100710 	vaba\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200750 	vaba\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200750 	vaba\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200710 	vaba\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000040 	vhadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000040 	vhadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000000 	vhadd\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100040 	vhadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100040 	vhadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100000 	vhadd\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200040 	vhadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200040 	vhadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200000 	vhadd\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000040 	vhadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000040 	vhadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000000 	vhadd\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100040 	vhadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100040 	vhadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100000 	vhadd\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200040 	vhadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200040 	vhadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200000 	vhadd\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000140 	vrhadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000140 	vrhadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000100 	vrhadd\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100140 	vrhadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100140 	vrhadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100100 	vrhadd\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200140 	vrhadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200140 	vrhadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200100 	vrhadd\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000140 	vrhadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000140 	vrhadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000100 	vrhadd\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100140 	vrhadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100140 	vrhadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100100 	vrhadd\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200140 	vrhadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200140 	vrhadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200100 	vrhadd\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000240 	vhsub\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000240 	vhsub\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000200 	vhsub\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100240 	vhsub\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100240 	vhsub\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100200 	vhsub\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200240 	vhsub\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200240 	vhsub\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200200 	vhsub\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000240 	vhsub\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000240 	vhsub\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000200 	vhsub\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100240 	vhsub\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100240 	vhsub\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100200 	vhsub\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200240 	vhsub\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200240 	vhsub\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200200 	vhsub\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000050 	vqadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000050 	vqadd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000010 	vqadd\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100050 	vqadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100050 	vqadd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100010 	vqadd\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200050 	vqadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200050 	vqadd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200010 	vqadd\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300050 	vqadd\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300050 	vqadd\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300010 	vqadd\.s64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000050 	vqadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000050 	vqadd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000010 	vqadd\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100050 	vqadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100050 	vqadd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100010 	vqadd\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200050 	vqadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200050 	vqadd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200010 	vqadd\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300050 	vqadd\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300050 	vqadd\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300010 	vqadd\.u64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000250 	vqsub\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000250 	vqsub\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000210 	vqsub\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100250 	vqsub\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100250 	vqsub\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100210 	vqsub\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200250 	vqsub\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200250 	vqsub\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200210 	vqsub\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300250 	vqsub\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300250 	vqsub\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300210 	vqsub\.s64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000250 	vqsub\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000250 	vqsub\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000210 	vqsub\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100250 	vqsub\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100250 	vqsub\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100210 	vqsub\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200250 	vqsub\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200250 	vqsub\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200210 	vqsub\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300250 	vqsub\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300250 	vqsub\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300210 	vqsub\.u64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000540 	vrshl\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000540 	vrshl\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000500 	vrshl\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100540 	vrshl\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100540 	vrshl\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100500 	vrshl\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200540 	vrshl\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200540 	vrshl\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200500 	vrshl\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300540 	vrshl\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300540 	vrshl\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300500 	vrshl\.s64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000540 	vrshl\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000540 	vrshl\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000500 	vrshl\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100540 	vrshl\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100540 	vrshl\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100500 	vrshl\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200540 	vrshl\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200540 	vrshl\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200500 	vrshl\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300540 	vrshl\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300540 	vrshl\.u64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300500 	vrshl\.u64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000550 	vqrshl\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000550 	vqrshl\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000510 	vqrshl\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100550 	vqrshl\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100550 	vqrshl\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100510 	vqrshl\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200550 	vqrshl\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200550 	vqrshl\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200510 	vqrshl\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300550 	vqrshl\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300550 	vqrshl\.s64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300510 	vqrshl\.s64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000550 	vqrshl\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000550 	vqrshl\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000510 	vqrshl\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100550 	vqrshl\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100550 	vqrshl\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100510 	vqrshl\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200550 	vqrshl\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200550 	vqrshl\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200510 	vqrshl\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300550 	vqrshl\.u64	q0, q0, q0
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+0[0-9a-f]+ <[^>]+> f3800790 	vqshl\.u64	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f2000150 	vand	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000150 	vand	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000110 	vand	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100150 	vbic	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100150 	vbic	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100110 	vbic	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200150 	vorr	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200150 	vorr	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200110 	vorr	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300150 	vorn	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300150 	vorn	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300110 	vorn	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000150 	veor	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000150 	veor	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000110 	veor	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3820175 	vbic\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 	vbic\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 	vbic\.i32	d0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 	vbic\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 	vbic\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 	vbic\.i32	d0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 	vbic\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 	vbic\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 	vbic\.i32	d0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 	vbic\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 	vbic\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 	vbic\.i32	d0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 	vbic\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 	vbic\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f 	vbic\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f 	vbic\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f 	vbic\.i32	d0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f 	vbic\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f 	vbic\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f 	vbic\.i32	d0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f 	vbic\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f 	vbic\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f 	vbic\.i32	d0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 	vbic\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 	vbic\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387097f 	vbic\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f 	vbic\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f 	vbic\.i16	d0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f 	vbic\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f 	vbic\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f 	vbic\.i16	d0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 	vbic\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 	vbic\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 	vbic\.i16	d0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 	vorr\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 	vorr\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 	vorr\.i32	d0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 	vorr\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 	vorr\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 	vorr\.i32	d0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 	vorr\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 	vorr\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 	vorr\.i32	d0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 	vorr\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 	vorr\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 	vorr\.i32	d0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 	vorr\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 	vorr\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f 	vorr\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f 	vorr\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f 	vorr\.i32	d0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f 	vorr\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f 	vorr\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f 	vorr\.i32	d0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f 	vorr\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f 	vorr\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f 	vorr\.i32	d0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 	vorr\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 	vorr\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387095f 	vorr\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f 	vorr\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f 	vorr\.i16	d0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f 	vorr\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f 	vorr\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f 	vorr\.i16	d0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 	vorr\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 	vorr\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 	vorr\.i16	d0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f3820175 	vbic\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820175 	vbic\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820135 	vbic\.i32	d0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820375 	vbic\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820375 	vbic\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820335 	vbic\.i32	d0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820575 	vbic\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820575 	vbic\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820535 	vbic\.i32	d0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820775 	vbic\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820775 	vbic\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820735 	vbic\.i32	d0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 	vbic\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 	vbic\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387017f 	vbic\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387013f 	vbic\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387037f 	vbic\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387037f 	vbic\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387033f 	vbic\.i32	d0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387057f 	vbic\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387057f 	vbic\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387053f 	vbic\.i32	d0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387077f 	vbic\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387077f 	vbic\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387073f 	vbic\.i32	d0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820975 	vbic\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820935 	vbic\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b75 	vbic\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b35 	vbic\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387097f 	vbic\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387097f 	vbic\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387093f 	vbic\.i16	d0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b7f 	vbic\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b7f 	vbic\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b3f 	vbic\.i16	d0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f2800970 	vbic\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800970 	vbic\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800930 	vbic\.i16	d0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f3820155 	vorr\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820155 	vorr\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820115 	vorr\.i32	d0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820355 	vorr\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820355 	vorr\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820315 	vorr\.i32	d0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820555 	vorr\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820555 	vorr\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820515 	vorr\.i32	d0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820755 	vorr\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820755 	vorr\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820715 	vorr\.i32	d0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 	vorr\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 	vorr\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387015f 	vorr\.i32	q0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387011f 	vorr\.i32	d0, #255	; 0x000000ff
+0[0-9a-f]+ <[^>]+> f387035f 	vorr\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387035f 	vorr\.i32	q0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387031f 	vorr\.i32	d0, #65280	; 0x0000ff00
+0[0-9a-f]+ <[^>]+> f387055f 	vorr\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387055f 	vorr\.i32	q0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387051f 	vorr\.i32	d0, #16711680	; 0x00ff0000
+0[0-9a-f]+ <[^>]+> f387075f 	vorr\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387075f 	vorr\.i32	q0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f387071f 	vorr\.i32	d0, #-16777216	; 0xff000000
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820955 	vorr\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820915 	vorr\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b55 	vorr\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820b15 	vorr\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f387095f 	vorr\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387095f 	vorr\.i16	q0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f387091f 	vorr\.i16	d0, #255	; 0x00ff
+0[0-9a-f]+ <[^>]+> f3870b5f 	vorr\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b5f 	vorr\.i16	q0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f3870b1f 	vorr\.i16	d0, #65280	; 0xff00
+0[0-9a-f]+ <[^>]+> f2800950 	vorr\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800950 	vorr\.i16	q0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f2800910 	vorr\.i16	d0, #0	; 0x0000
+0[0-9a-f]+ <[^>]+> f3100150 	vbsl	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100150 	vbsl	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100110 	vbsl	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200150 	vbit	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200150 	vbit	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200110 	vbit	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300150 	vbif	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300150 	vbif	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300110 	vbif	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000740 	vabd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000740 	vabd\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000700 	vabd\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100740 	vabd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100740 	vabd\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100700 	vabd\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200740 	vabd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200740 	vabd\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200700 	vabd\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000740 	vabd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000740 	vabd\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000700 	vabd\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100740 	vabd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100740 	vabd\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100700 	vabd\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200740 	vabd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200740 	vabd\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200700 	vabd\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200d40 	vabd\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200d40 	vabd\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200d00 	vabd\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000640 	vmax\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000640 	vmax\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000600 	vmax\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100640 	vmax\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100640 	vmax\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100600 	vmax\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200640 	vmax\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200640 	vmax\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200600 	vmax\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000640 	vmax\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000640 	vmax\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000600 	vmax\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100640 	vmax\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100640 	vmax\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100600 	vmax\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200640 	vmax\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200640 	vmax\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200600 	vmax\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000f40 	vmax\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000f40 	vmax\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000f00 	vmax\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000650 	vmin\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000650 	vmin\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000610 	vmin\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100650 	vmin\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100650 	vmin\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100610 	vmin\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200650 	vmin\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200650 	vmin\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200610 	vmin\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000650 	vmin\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000650 	vmin\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000610 	vmin\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100650 	vmin\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100650 	vmin\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100610 	vmin\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200650 	vmin\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200650 	vmin\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200610 	vmin\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200f40 	vmin\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200f40 	vmin\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200f00 	vmin\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000350 	vcge\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000350 	vcge\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000310 	vcge\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100350 	vcge\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100350 	vcge\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100310 	vcge\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200350 	vcge\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200350 	vcge\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200310 	vcge\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000350 	vcge\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000350 	vcge\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000310 	vcge\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100350 	vcge\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100350 	vcge\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100310 	vcge\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200350 	vcge\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200350 	vcge\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200310 	vcge\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000e40 	vcge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e40 	vcge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e00 	vcge\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000340 	vcgt\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000340 	vcgt\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000300 	vcgt\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100340 	vcgt\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100340 	vcgt\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100300 	vcgt\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200340 	vcgt\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200340 	vcgt\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200300 	vcgt\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000340 	vcgt\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000340 	vcgt\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000300 	vcgt\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100340 	vcgt\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100340 	vcgt\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100300 	vcgt\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200340 	vcgt\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200340 	vcgt\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200300 	vcgt\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e40 	vcgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e40 	vcgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e00 	vcgt\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000350 	vcge\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000350 	vcge\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000310 	vcge\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100350 	vcge\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100350 	vcge\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100310 	vcge\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200350 	vcge\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200350 	vcge\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200310 	vcge\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000350 	vcge\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000350 	vcge\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000310 	vcge\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100350 	vcge\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100350 	vcge\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100310 	vcge\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200350 	vcge\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200350 	vcge\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200310 	vcge\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000e40 	vcge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e40 	vcge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e00 	vcge\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000340 	vcgt\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000340 	vcgt\.s8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000300 	vcgt\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100340 	vcgt\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100340 	vcgt\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100300 	vcgt\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200340 	vcgt\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200340 	vcgt\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200300 	vcgt\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000340 	vcgt\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000340 	vcgt\.u8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000300 	vcgt\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100340 	vcgt\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100340 	vcgt\.u16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100300 	vcgt\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200340 	vcgt\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200340 	vcgt\.u32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200300 	vcgt\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e40 	vcgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e40 	vcgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e00 	vcgt\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000850 	vceq\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000850 	vceq\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000810 	vceq\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100850 	vceq\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100850 	vceq\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100810 	vceq\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200810 	vceq\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200810 	vceq\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200850 	vceq\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200810 	vceq\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000e40 	vceq\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000e40 	vceq\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000e00 	vceq\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3b100c0 	vcge\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b100c0 	vcge\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10080 	vcge\.s8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b500c0 	vcge\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b500c0 	vcge\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50080 	vcge\.s16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b900c0 	vcge\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b900c0 	vcge\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90080 	vcge\.s32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b904c0 	vcge\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b904c0 	vcge\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90480 	vcge\.f32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b10040 	vcgt\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10040 	vcgt\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10000 	vcgt\.s8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b50040 	vcgt\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50040 	vcgt\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50000 	vcgt\.s16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90040 	vcgt\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90040 	vcgt\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90000 	vcgt\.s32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90440 	vcgt\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90440 	vcgt\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90400 	vcgt\.f32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b101c0 	vcle\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b101c0 	vcle\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10180 	vcle\.s8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b501c0 	vcle\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b501c0 	vcle\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50180 	vcle\.s16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b901c0 	vcle\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b901c0 	vcle\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90180 	vcle\.s32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b905c0 	vcle\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b905c0 	vcle\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90580 	vcle\.f32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b10240 	vclt\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10240 	vclt\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10200 	vclt\.s8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b50240 	vclt\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50240 	vclt\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50200 	vclt\.s16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90240 	vclt\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90240 	vclt\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90200 	vclt\.s32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90640 	vclt\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90640 	vclt\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90600 	vclt\.f32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b10140 	vceq\.i8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10140 	vceq\.i8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b10100 	vceq\.i8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b50140 	vceq\.i16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50140 	vceq\.i16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b50100 	vceq\.i16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90100 	vceq\.i32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90100 	vceq\.i32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90140 	vceq\.i32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90100 	vceq\.i32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3b90540 	vceq\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90540 	vceq\.f32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3b90500 	vceq\.f32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f2000a00 	vpmax\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100a00 	vpmax\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200a00 	vpmax\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000a00 	vpmax\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100a00 	vpmax\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200a00 	vpmax\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000f00 	vpmax\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000a10 	vpmin\.s8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100a10 	vpmin\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200a10 	vpmin\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000a10 	vpmin\.u8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100a10 	vpmin\.u16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200a10 	vpmin\.u32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200f00 	vpmin\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000940 	vmla\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000940 	vmla\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000900 	vmla\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100940 	vmla\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100940 	vmla\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100900 	vmla\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200900 	vmla\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200900 	vmla\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200940 	vmla\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200900 	vmla\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000d50 	vmla\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000d50 	vmla\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000d10 	vmla\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900040 	vmla\.i16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900040 	vmla\.i16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900040 	vmla\.i16	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00040 	vmla\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00040 	vmla\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00040 	vmla\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00040 	vmla\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00140 	vmla\.f32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00140 	vmla\.f32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00140 	vmla\.f32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3000940 	vmls\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000940 	vmls\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000900 	vmls\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100940 	vmls\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100940 	vmls\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100900 	vmls\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200900 	vmls\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200900 	vmls\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200940 	vmls\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200900 	vmls\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200d50 	vmls\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200d50 	vmls\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200d10 	vmls\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900440 	vmls\.i16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900440 	vmls\.i16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900440 	vmls\.i16	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00440 	vmls\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00440 	vmls\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00440 	vmls\.i32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00440 	vmls\.i32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00540 	vmls\.f32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00540 	vmls\.f32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00540 	vmls\.f32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2000b10 	vpadd\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100b10 	vpadd\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200b10 	vpadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200b10 	vpadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200b10 	vpadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000d00 	vpadd\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000840 	vadd\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000840 	vadd\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000800 	vadd\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100840 	vadd\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100840 	vadd\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100800 	vadd\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200800 	vadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200800 	vadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200840 	vadd\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200800 	vadd\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2300840 	vadd\.i64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300840 	vadd\.i64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2300800 	vadd\.i64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000d40 	vadd\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000d40 	vadd\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000d00 	vadd\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000840 	vsub\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000840 	vsub\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000800 	vsub\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3100840 	vsub\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100840 	vsub\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100800 	vsub\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200800 	vsub\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200800 	vsub\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200840 	vsub\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200800 	vsub\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3300840 	vsub\.i64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300840 	vsub\.i64	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3300800 	vsub\.i64	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200d40 	vsub\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200d40 	vsub\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200d00 	vsub\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000850 	vtst\.8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000850 	vtst\.8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000810 	vtst\.8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100850 	vtst\.16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100850 	vtst\.16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100810 	vtst\.16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200850 	vtst\.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200850 	vtst\.32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200810 	vtst\.32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000950 	vmul\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000950 	vmul\.i8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000910 	vmul\.i8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100950 	vmul\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100950 	vmul\.i16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100910 	vmul\.i16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200910 	vmul\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200910 	vmul\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200950 	vmul\.i32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200910 	vmul\.i32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000d50 	vmul\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000d50 	vmul\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000d10 	vmul\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000950 	vmul\.p8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000950 	vmul\.p8	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000910 	vmul\.p8	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2100b40 	vqdmulh\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100b40 	vqdmulh\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2100b00 	vqdmulh\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200b40 	vqdmulh\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200b40 	vqdmulh\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200b00 	vqdmulh\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900c40 	vqdmulh\.s16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900c40 	vqdmulh\.s16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900c40 	vqdmulh\.s16	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00c40 	vqdmulh\.s32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00c40 	vqdmulh\.s32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00c40 	vqdmulh\.s32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3100b40 	vqrdmulh\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100b40 	vqrdmulh\.s16	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3100b00 	vqrdmulh\.s16	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200b40 	vqrdmulh\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200b40 	vqrdmulh\.s32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200b00 	vqrdmulh\.s32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900d40 	vqrdmulh\.s16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900d40 	vqrdmulh\.s16	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900d40 	vqrdmulh\.s16	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00d40 	vqrdmulh\.s32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00d40 	vqrdmulh\.s32	q0, q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00d40 	vqrdmulh\.s32	d0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3000e50 	vacge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e50 	vacge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e10 	vacge\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e50 	vacgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e50 	vacgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e10 	vacgt\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3000e50 	vacge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e50 	vacge\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3000e10 	vacge\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3200e50 	vacgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e50 	vacgt\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3200e10 	vacgt\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2000f50 	vrecps\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000f50 	vrecps\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2000f10 	vrecps\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f2200f50 	vrsqrts\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200f50 	vrsqrts\.f32	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200f10 	vrsqrts\.f32	d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3b10340 	vabs\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b10340 	vabs\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b10300 	vabs\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b50340 	vabs\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b50340 	vabs\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b50300 	vabs\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b90340 	vabs\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90340 	vabs\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90300 	vabs\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b90740 	vabs\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90740 	vabs\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90700 	vabs\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b103c0 	vneg\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b103c0 	vneg\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b10380 	vneg\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b503c0 	vneg\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b503c0 	vneg\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b50380 	vneg\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b903c0 	vneg\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b903c0 	vneg\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90380 	vneg\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b907c0 	vneg\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b907c0 	vneg\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b90780 	vneg\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f2890050 	vshr\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890050 	vshr\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890010 	vshr\.s8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f2910050 	vshr\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910050 	vshr\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910010 	vshr\.s16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f2a10050 	vshr\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10050 	vshr\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10010 	vshr\.s32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f28100d0 	vshr\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f28100d0 	vshr\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f2810090 	vshr\.s64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3890050 	vshr\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890050 	vshr\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890010 	vshr\.u8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f3910050 	vshr\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910050 	vshr\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910010 	vshr\.u16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f3a10050 	vshr\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10050 	vshr\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10010 	vshr\.u32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f38100d0 	vshr\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f38100d0 	vshr\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f3810090 	vshr\.u64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f2890250 	vrshr\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890250 	vrshr\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890210 	vrshr\.s8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f2910250 	vrshr\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910250 	vrshr\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910210 	vrshr\.s16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f2a10250 	vrshr\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10250 	vrshr\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10210 	vrshr\.s32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f28102d0 	vrshr\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f28102d0 	vrshr\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f2810290 	vrshr\.s64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3890250 	vrshr\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890250 	vrshr\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890210 	vrshr\.u8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f3910250 	vrshr\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910250 	vrshr\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910210 	vrshr\.u16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f3a10250 	vrshr\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10250 	vrshr\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10210 	vrshr\.u32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f38102d0 	vrshr\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f38102d0 	vrshr\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f3810290 	vrshr\.u64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f2890150 	vsra\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890150 	vsra\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890110 	vsra\.s8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f2910150 	vsra\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910150 	vsra\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910110 	vsra\.s16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f2a10150 	vsra\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10150 	vsra\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10110 	vsra\.s32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f28101d0 	vsra\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f28101d0 	vsra\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f2810190 	vsra\.s64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3890150 	vsra\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890150 	vsra\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890110 	vsra\.u8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f3910150 	vsra\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910150 	vsra\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910110 	vsra\.u16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f3a10150 	vsra\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10150 	vsra\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10110 	vsra\.u32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f38101d0 	vsra\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f38101d0 	vsra\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f3810190 	vsra\.u64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f2890350 	vrsra\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890350 	vrsra\.s8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f2890310 	vrsra\.s8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f2910350 	vrsra\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910350 	vrsra\.s16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910310 	vrsra\.s16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f2a10350 	vrsra\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10350 	vrsra\.s32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f2a10310 	vrsra\.s32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f28103d0 	vrsra\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f28103d0 	vrsra\.s64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f2810390 	vrsra\.s64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3890350 	vrsra\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890350 	vrsra\.u8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890310 	vrsra\.u8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f3910350 	vrsra\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910350 	vrsra\.u16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910310 	vrsra\.u16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f3a10350 	vrsra\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10350 	vrsra\.u32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10310 	vrsra\.u32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f38103d0 	vrsra\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f38103d0 	vrsra\.u64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f3810390 	vrsra\.u64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3880550 	vsli\.8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3880550 	vsli\.8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3880510 	vsli\.8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3900550 	vsli\.16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3900550 	vsli\.16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3900510 	vsli\.16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3a00550 	vsli\.32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3a00550 	vsli\.32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3a00510 	vsli\.32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f38005d0 	vsli\.64	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f38005d0 	vsli\.64	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3800590 	vsli\.64	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3890450 	vsri\.8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890450 	vsri\.8	q0, q0, #7
+0[0-9a-f]+ <[^>]+> f3890410 	vsri\.8	d0, d0, #7
+0[0-9a-f]+ <[^>]+> f3910450 	vsri\.16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910450 	vsri\.16	q0, q0, #15
+0[0-9a-f]+ <[^>]+> f3910410 	vsri\.16	d0, d0, #15
+0[0-9a-f]+ <[^>]+> f3a10450 	vsri\.32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10450 	vsri\.32	q0, q0, #31
+0[0-9a-f]+ <[^>]+> f3a10410 	vsri\.32	d0, d0, #31
+0[0-9a-f]+ <[^>]+> f38104d0 	vsri\.64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f38104d0 	vsri\.64	q0, q0, #63
+0[0-9a-f]+ <[^>]+> f3810490 	vsri\.64	d0, d0, #63
+0[0-9a-f]+ <[^>]+> f3880650 	vqshlu\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3880650 	vqshlu\.s8	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3880610 	vqshlu\.s8	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3900650 	vqshlu\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3900650 	vqshlu\.s16	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3900610 	vqshlu\.s16	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f3a00650 	vqshlu\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3a00650 	vqshlu\.s32	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3a00610 	vqshlu\.s32	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f38006d0 	vqshlu\.s64	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f38006d0 	vqshlu\.s64	q0, q0, #0
+0[0-9a-f]+ <[^>]+> f3800690 	vqshlu\.s64	d0, d0, #0
+0[0-9a-f]+ <[^>]+> f2890910 	vqshrn\.s16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f2910910 	vqshrn\.s32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2a10910 	vqshrn\.s64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f3890910 	vqshrn\.u16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f3910910 	vqshrn\.u32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f3a10910 	vqshrn\.u64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f2890950 	vqrshrn\.s16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f2910950 	vqrshrn\.s32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2a10950 	vqrshrn\.s64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f3890950 	vqrshrn\.u16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f3910950 	vqrshrn\.u32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f3a10950 	vqrshrn\.u64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f3890810 	vqshrun\.s16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f3910810 	vqshrun\.s32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f3a10810 	vqshrun\.s64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f3890850 	vqrshrun\.s16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f3910850 	vqrshrun\.s32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f3a10850 	vqrshrun\.s64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f2890810 	vshrn\.i16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f2910810 	vshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910810 	vshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910810 	vshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2a10810 	vshrn\.i64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f2890850 	vrshrn\.i16	d0, q0, #7
+0[0-9a-f]+ <[^>]+> f2910850 	vrshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910850 	vrshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2910850 	vrshrn\.i32	d0, q0, #15
+0[0-9a-f]+ <[^>]+> f2a10850 	vrshrn\.i64	d0, q0, #31
+0[0-9a-f]+ <[^>]+> f2890a10 	vshll\.s8	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f2910a10 	vshll\.s16	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f2a10a10 	vshll\.s32	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f3890a10 	vshll\.u8	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f3910a10 	vshll\.u16	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f3a10a10 	vshll\.u32	d0, q0, #1
+0[0-9a-f]+ <[^>]+> f3b20300 	vshll\.i8	q0, d0, #8
+0[0-9a-f]+ <[^>]+> f3b60300 	vshll\.i16	q0, d0, #16
+0[0-9a-f]+ <[^>]+> f3ba0300 	vshll\.i32	q0, d0, #32
+0[0-9a-f]+ <[^>]+> f3ba0300 	vshll\.i32	q0, d0, #32
+0[0-9a-f]+ <[^>]+> f3ba0300 	vshll\.i32	q0, d0, #32
+0[0-9a-f]+ <[^>]+> f3bb0740 	vcvt\.s32\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb07c0 	vcvt\.u32\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0640 	vcvt\.f32\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb06c0 	vcvt\.f32\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0740 	vcvt\.s32\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb07c0 	vcvt\.u32\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0640 	vcvt\.f32\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb06c0 	vcvt\.f32\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0700 	vcvt\.s32\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb0780 	vcvt\.u32\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb0600 	vcvt\.f32\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb0680 	vcvt\.f32\.u32	d0, d0
+0[0-9a-f]+ <[^>]+> f2bf0f50 	vcvt\.s32\.f32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f3bf0f50 	vcvt\.u32\.f32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f2bf0e50 	vcvt\.f32\.s32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f3bf0e50 	vcvt\.f32\.u32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f2bf0f50 	vcvt\.s32\.f32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f3bf0f50 	vcvt\.u32\.f32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f2bf0e50 	vcvt\.f32\.s32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f3bf0e50 	vcvt\.f32\.u32	q0, q0, #1
+0[0-9a-f]+ <[^>]+> f2bf0f10 	vcvt\.s32\.f32	d0, d0, #1
+0[0-9a-f]+ <[^>]+> f3bf0f10 	vcvt\.u32\.f32	d0, d0, #1
+0[0-9a-f]+ <[^>]+> f2bf0e10 	vcvt\.f32\.s32	d0, d0, #1
+0[0-9a-f]+ <[^>]+> f3bf0e10 	vcvt\.f32\.u32	d0, d0, #1
+0[0-9a-f]+ <[^>]+> f2200150 	vorr	q0, q0, q0
+0[0-9a-f]+ <[^>]+> f2200110 	vorr	d0, d0, d0
+0[0-9a-f]+ <[^>]+> ee400b10 	vmov\.8	d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ee000b30 	vmov\.16	d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ee000b10 	vmov\.32	d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ec400b10 	vmov	d0, r0, r0
+0[0-9a-f]+ <[^>]+> ee500b10 	vmov\.s8	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee100b30 	vmov\.s16	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> eed00b10 	vmov\.u8	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee900b30 	vmov\.u16	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee100b10 	vmov\.32	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ec510b10 	vmov	r0, r1, d0
+0[0-9a-f]+ <[^>]+> f2870057 	vmov\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 	vmov\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 	vmov\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 	vmov\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870057 	vmov\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870017 	vmov\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 	vmvn\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 	vmvn\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 	vmvn\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 	vmvn\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870077 	vmvn\.i32	q0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870037 	vmvn\.i32	d0, #119	; 0x00000077
+0[0-9a-f]+ <[^>]+> f2870257 	vmov\.i32	q0, #30464	; 0x00007700
+0[0-9a-f]+ <[^>]+> f2870217 	vmov\.i32	d0, #30464	; 0x00007700
+0[0-9a-f]+ <[^>]+> f2870277 	vmvn\.i32	q0, #30464	; 0x00007700
+0[0-9a-f]+ <[^>]+> f2870237 	vmvn\.i32	d0, #30464	; 0x00007700
+0[0-9a-f]+ <[^>]+> f2870457 	vmov\.i32	q0, #7798784	; 0x00770000
+0[0-9a-f]+ <[^>]+> f2870417 	vmov\.i32	d0, #7798784	; 0x00770000
+0[0-9a-f]+ <[^>]+> f2870477 	vmvn\.i32	q0, #7798784	; 0x00770000
+0[0-9a-f]+ <[^>]+> f2870437 	vmvn\.i32	d0, #7798784	; 0x00770000
+0[0-9a-f]+ <[^>]+> f2870657 	vmov\.i32	q0, #1996488704	; 0x77000000
+0[0-9a-f]+ <[^>]+> f2870617 	vmov\.i32	d0, #1996488704	; 0x77000000
+0[0-9a-f]+ <[^>]+> f2870677 	vmvn\.i32	q0, #1996488704	; 0x77000000
+0[0-9a-f]+ <[^>]+> f2870637 	vmvn\.i32	d0, #1996488704	; 0x77000000
+0[0-9a-f]+ <[^>]+> f2870857 	vmov\.i16	q0, #119	; 0x0077
+0[0-9a-f]+ <[^>]+> f2870817 	vmov\.i16	d0, #119	; 0x0077
+0[0-9a-f]+ <[^>]+> f2870877 	vmvn\.i16	q0, #119	; 0x0077
+0[0-9a-f]+ <[^>]+> f2870837 	vmvn\.i16	d0, #119	; 0x0077
+0[0-9a-f]+ <[^>]+> f2870a57 	vmov\.i16	q0, #30464	; 0x7700
+0[0-9a-f]+ <[^>]+> f2870a17 	vmov\.i16	d0, #30464	; 0x7700
+0[0-9a-f]+ <[^>]+> f2870a77 	vmvn\.i16	q0, #30464	; 0x7700
+0[0-9a-f]+ <[^>]+> f2870a37 	vmvn\.i16	d0, #30464	; 0x7700
+0[0-9a-f]+ <[^>]+> f2870c57 	vmov\.i32	q0, #30719	; 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c17 	vmov\.i32	d0, #30719	; 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c77 	vmvn\.i32	q0, #30719	; 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870c37 	vmvn\.i32	d0, #30719	; 0x000077ff
+0[0-9a-f]+ <[^>]+> f2870d57 	vmov\.i32	q0, #7864319	; 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d17 	vmov\.i32	d0, #7864319	; 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d77 	vmvn\.i32	q0, #7864319	; 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870d37 	vmvn\.i32	d0, #7864319	; 0x0077ffff
+0[0-9a-f]+ <[^>]+> f2870e57 	vmov\.i8	q0, #119	; 0x77
+0[0-9a-f]+ <[^>]+> f2870e17 	vmov\.i8	d0, #119	; 0x77
+0[0-9a-f]+ <[^>]+> f3810e71 	vmov\.i64	q0, #0xff0000ff000000ff
+0[0-9a-f]+ <[^>]+> f3810e31 	vmov\.i64	d0, #0xff0000ff000000ff
+0[0-9a-f]+ <[^>]+> f2810f51 	vmov\.f32	q0, #4\.25	; 0x40880000
+0[0-9a-f]+ <[^>]+> f2810f11 	vmov\.f32	d0, #4\.25	; 0x40880000
+0[0-9a-f]+ <[^>]+> f3820e55 	vmov\.i8	q0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 	vmov\.i8	d0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a 	vmov\.i8	q0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a 	vmov\.i8	d0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f3820e55 	vmov\.i8	q0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 	vmov\.i8	d0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a 	vmov\.i8	q0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a 	vmov\.i8	d0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 	vmov\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 	vmov\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 	vmov\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 	vmov\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820e55 	vmov\.i8	q0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f3820e15 	vmov\.i8	d0, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f2850e5a 	vmov\.i8	q0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f2850e1a 	vmov\.i8	d0, #90	; 0x5a
+0[0-9a-f]+ <[^>]+> f3820855 	vmov\.i16	q0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820815 	vmov\.i16	d0, #165	; 0x00a5
+0[0-9a-f]+ <[^>]+> f3820a55 	vmov\.i16	q0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820a15 	vmov\.i16	d0, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f3820055 	vmov\.i32	q0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820015 	vmov\.i32	d0, #165	; 0x000000a5
+0[0-9a-f]+ <[^>]+> f3820255 	vmov\.i32	q0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820215 	vmov\.i32	d0, #42240	; 0x0000a500
+0[0-9a-f]+ <[^>]+> f3820455 	vmov\.i32	q0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820415 	vmov\.i32	d0, #10813440	; 0x00a50000
+0[0-9a-f]+ <[^>]+> f3820655 	vmov\.i32	q0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820615 	vmov\.i32	d0, #-1526726656	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f3820c55 	vmov\.i32	q0, #42495	; 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820c15 	vmov\.i32	d0, #42495	; 0x0000a5ff
+0[0-9a-f]+ <[^>]+> f3820d55 	vmov\.i32	q0, #10878975	; 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f3820d15 	vmov\.i32	d0, #10878975	; 0x00a5ffff
+0[0-9a-f]+ <[^>]+> f285067a 	vmvn\.i32	q0, #1509949440	; 0x5a000000
+0[0-9a-f]+ <[^>]+> f285063a 	vmvn\.i32	d0, #1509949440	; 0x5a000000
+0[0-9a-f]+ <[^>]+> f3b005c0 	vmvn	q0, q0
+0[0-9a-f]+ <[^>]+> f3b005c0 	vmvn	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00580 	vmvn	d0, d0
+0[0-9a-f]+ <[^>]+> f2800500 	vabal\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900500 	vabal\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00500 	vabal\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800500 	vabal\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900500 	vabal\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00500 	vabal\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2800700 	vabdl\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900700 	vabdl\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00700 	vabdl\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800700 	vabdl\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900700 	vabdl\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00700 	vabdl\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2800000 	vaddl\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900000 	vaddl\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00000 	vaddl\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800000 	vaddl\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900000 	vaddl\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00000 	vaddl\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2800200 	vsubl\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900200 	vsubl\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00200 	vsubl\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800200 	vsubl\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900200 	vsubl\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00200 	vsubl\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2800800 	vmlal\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900800 	vmlal\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00800 	vmlal\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800800 	vmlal\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900800 	vmlal\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00800 	vmlal\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900240 	vmlal\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00240 	vmlal\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900240 	vmlal\.u16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00240 	vmlal\.u32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2800a00 	vmlsl\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900a00 	vmlsl\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00a00 	vmlsl\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800a00 	vmlsl\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900a00 	vmlsl\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00a00 	vmlsl\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900640 	vmlsl\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00640 	vmlsl\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900640 	vmlsl\.u16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00640 	vmlsl\.u32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2800100 	vaddw\.s8	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2900100 	vaddw\.s16	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2a00100 	vaddw\.s32	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3800100 	vaddw\.u8	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3900100 	vaddw\.u16	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3a00100 	vaddw\.u32	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2800300 	vsubw\.s8	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2900300 	vsubw\.s16	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2a00300 	vsubw\.s32	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3800300 	vsubw\.u8	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3900300 	vsubw\.u16	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f3a00300 	vsubw\.u32	q0, q0, d0
+0[0-9a-f]+ <[^>]+> f2800400 	vaddhn\.i16	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900400 	vaddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900400 	vaddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900400 	vaddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2a00400 	vaddhn\.i64	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3800400 	vraddhn\.i16	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900400 	vraddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900400 	vraddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900400 	vraddhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3a00400 	vraddhn\.i64	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2800600 	vsubhn\.i16	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900600 	vsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900600 	vsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900600 	vsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2a00600 	vsubhn\.i64	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3800600 	vrsubhn\.i16	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900600 	vrsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900600 	vrsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3900600 	vrsubhn\.i32	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f3a00600 	vrsubhn\.i64	d0, q0, q0
+0[0-9a-f]+ <[^>]+> f2900900 	vqdmlal\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00900 	vqdmlal\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900340 	vqdmlal\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00340 	vqdmlal\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900b00 	vqdmlsl\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00b00 	vqdmlsl\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900740 	vqdmlsl\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00740 	vqdmlsl\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2900d00 	vqdmull\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00d00 	vqdmull\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900b40 	vqdmull\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00b40 	vqdmull\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2800c00 	vmull\.s8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900c00 	vmull\.s16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2a00c00 	vmull\.s32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3800c00 	vmull\.u8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3900c00 	vmull\.u16	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f3a00c00 	vmull\.u32	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2800e00 	vmull\.p8	q0, d0, d0
+0[0-9a-f]+ <[^>]+> f2900a40 	vmull\.s16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2a00a40 	vmull\.s32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3900a40 	vmull\.u16	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3a00a40 	vmull\.u32	q0, d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2b00040 	vext\.8	q0, q0, q0, #0
+0[0-9a-f]+ <[^>]+> f2b00040 	vext\.8	q0, q0, q0, #0
+0[0-9a-f]+ <[^>]+> f2b00000 	vext\.8	d0, d0, d0, #0
+0[0-9a-f]+ <[^>]+> f2b00840 	vext\.8	q0, q0, q0, #8
+0[0-9a-f]+ <[^>]+> f3b00040 	vrev64\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00040 	vrev64\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00000 	vrev64\.8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b40040 	vrev64\.16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40040 	vrev64\.16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40000 	vrev64\.16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b80040 	vrev64\.32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80040 	vrev64\.32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80000 	vrev64\.32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b000c0 	vrev32\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b000c0 	vrev32\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00080 	vrev32\.8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b400c0 	vrev32\.16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b400c0 	vrev32\.16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40080 	vrev32\.16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b00140 	vrev16\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00140 	vrev16\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00100 	vrev16\.8	d0, d0
+0[0-9a-f]+ <[^>]+> eee00b10 	vdup\.8	q0, r0
+0[0-9a-f]+ <[^>]+> eee00b10 	vdup\.8	q0, r0
+0[0-9a-f]+ <[^>]+> eec00b10 	vdup\.8	d0, r0
+0[0-9a-f]+ <[^>]+> f3b10c40 	vdup\.8	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b10c40 	vdup\.8	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b10c00 	vdup\.8	d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> eea00b30 	vdup\.16	q0, r0
+0[0-9a-f]+ <[^>]+> eea00b30 	vdup\.16	q0, r0
+0[0-9a-f]+ <[^>]+> ee800b30 	vdup\.16	d0, r0
+0[0-9a-f]+ <[^>]+> f3b20c40 	vdup\.16	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b20c40 	vdup\.16	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b20c00 	vdup\.16	d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> eea00b10 	vdup\.32	q0, r0
+0[0-9a-f]+ <[^>]+> eea00b10 	vdup\.32	q0, r0
+0[0-9a-f]+ <[^>]+> ee800b10 	vdup\.32	d0, r0
+0[0-9a-f]+ <[^>]+> f3b40c40 	vdup\.32	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b40c40 	vdup\.32	q0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f3b40c00 	vdup\.32	d0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f2880a10 	vmovl\.s8	q0, d0
+0[0-9a-f]+ <[^>]+> f2900a10 	vmovl\.s16	q0, d0
+0[0-9a-f]+ <[^>]+> f2a00a10 	vmovl\.s32	q0, d0
+0[0-9a-f]+ <[^>]+> f3880a10 	vmovl\.u8	q0, d0
+0[0-9a-f]+ <[^>]+> f3900a10 	vmovl\.u16	q0, d0
+0[0-9a-f]+ <[^>]+> f3a00a10 	vmovl\.u32	q0, d0
+0[0-9a-f]+ <[^>]+> f3b20200 	vmovn\.i16	d0, q0
+0[0-9a-f]+ <[^>]+> f3b60200 	vmovn\.i32	d0, q0
+0[0-9a-f]+ <[^>]+> f3ba0200 	vmovn\.i64	d0, q0
+0[0-9a-f]+ <[^>]+> f3b60200 	vmovn\.i32	d0, q0
+0[0-9a-f]+ <[^>]+> f3b60200 	vmovn\.i32	d0, q0
+0[0-9a-f]+ <[^>]+> f3b20280 	vqmovn\.s16	d0, q0
+0[0-9a-f]+ <[^>]+> f3b60280 	vqmovn\.s32	d0, q0
+0[0-9a-f]+ <[^>]+> f3ba0280 	vqmovn\.s64	d0, q0
+0[0-9a-f]+ <[^>]+> f3b202c0 	vqmovn\.u16	d0, q0
+0[0-9a-f]+ <[^>]+> f3b602c0 	vqmovn\.u32	d0, q0
+0[0-9a-f]+ <[^>]+> f3ba02c0 	vqmovn\.u64	d0, q0
+0[0-9a-f]+ <[^>]+> f3b20240 	vqmovun\.s16	d0, q0
+0[0-9a-f]+ <[^>]+> f3b60240 	vqmovun\.s32	d0, q0
+0[0-9a-f]+ <[^>]+> f3ba0240 	vqmovun\.s64	d0, q0
+0[0-9a-f]+ <[^>]+> f3b201c2 	vzip\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b201c2 	vzip\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20181 	vzip\.8	d0, d1
+0[0-9a-f]+ <[^>]+> f3b601c2 	vzip\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b601c2 	vzip\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b60181 	vzip\.16	d0, d1
+0[0-9a-f]+ <[^>]+> f3ba01c2 	vzip\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba01c2 	vzip\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba0081 	vtrn\.32	d0, d1
+0[0-9a-f]+ <[^>]+> f3b20142 	vuzp\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20142 	vuzp\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20101 	vuzp\.8	d0, d1
+0[0-9a-f]+ <[^>]+> f3b60142 	vuzp\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b60142 	vuzp\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b60101 	vuzp\.16	d0, d1
+0[0-9a-f]+ <[^>]+> f3ba0142 	vuzp\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba0142 	vuzp\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba0081 	vtrn\.32	d0, d1
+0[0-9a-f]+ <[^>]+> f3b00740 	vqabs\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00740 	vqabs\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00700 	vqabs\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b40740 	vqabs\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40740 	vqabs\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40700 	vqabs\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b80740 	vqabs\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80740 	vqabs\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80700 	vqabs\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b007c0 	vqneg\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b007c0 	vqneg\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00780 	vqneg\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b407c0 	vqneg\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b407c0 	vqneg\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40780 	vqneg\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b807c0 	vqneg\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b807c0 	vqneg\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80780 	vqneg\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b00640 	vpadal\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00640 	vpadal\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00600 	vpadal\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b40640 	vpadal\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40640 	vpadal\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40600 	vpadal\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b80640 	vpadal\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80640 	vpadal\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80600 	vpadal\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b006c0 	vpadal\.u8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b006c0 	vpadal\.u8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00680 	vpadal\.u8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b406c0 	vpadal\.u16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b406c0 	vpadal\.u16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40680 	vpadal\.u16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b806c0 	vpadal\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b806c0 	vpadal\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80680 	vpadal\.u32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b00240 	vpaddl\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00240 	vpaddl\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00200 	vpaddl\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b40240 	vpaddl\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40240 	vpaddl\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40200 	vpaddl\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b80240 	vpaddl\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80240 	vpaddl\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80200 	vpaddl\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b002c0 	vpaddl\.u8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b002c0 	vpaddl\.u8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00280 	vpaddl\.u8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b402c0 	vpaddl\.u16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b402c0 	vpaddl\.u16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40280 	vpaddl\.u16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b802c0 	vpaddl\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b802c0 	vpaddl\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80280 	vpaddl\.u32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb0440 	vrecpe\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0440 	vrecpe\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0400 	vrecpe\.u32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb0540 	vrecpe\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0540 	vrecpe\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0500 	vrecpe\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb04c0 	vrsqrte\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb04c0 	vrsqrte\.u32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0480 	vrsqrte\.u32	d0, d0
+0[0-9a-f]+ <[^>]+> f3bb05c0 	vrsqrte\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb05c0 	vrsqrte\.f32	q0, q0
+0[0-9a-f]+ <[^>]+> f3bb0580 	vrsqrte\.f32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b00440 	vcls\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00440 	vcls\.s8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00400 	vcls\.s8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b40440 	vcls\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40440 	vcls\.s16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40400 	vcls\.s16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b80440 	vcls\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80440 	vcls\.s32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80400 	vcls\.s32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b004c0 	vclz\.i8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b004c0 	vclz\.i8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00480 	vclz\.i8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b404c0 	vclz\.i16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b404c0 	vclz\.i16	q0, q0
+0[0-9a-f]+ <[^>]+> f3b40480 	vclz\.i16	d0, d0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80480 	vclz\.i32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80480 	vclz\.i32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b804c0 	vclz\.i32	q0, q0
+0[0-9a-f]+ <[^>]+> f3b80480 	vclz\.i32	d0, d0
+0[0-9a-f]+ <[^>]+> f3b00540 	vcnt\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00540 	vcnt\.8	q0, q0
+0[0-9a-f]+ <[^>]+> f3b00500 	vcnt\.8	d0, d0
+0[0-9a-f]+ <[^>]+> f3b20042 	vswp	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20042 	vswp	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20001 	vswp	d0, d1
+0[0-9a-f]+ <[^>]+> f3b200c2 	vtrn\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b200c2 	vtrn\.8	q0, q1
+0[0-9a-f]+ <[^>]+> f3b20081 	vtrn\.8	d0, d1
+0[0-9a-f]+ <[^>]+> f3b600c2 	vtrn\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b600c2 	vtrn\.16	q0, q1
+0[0-9a-f]+ <[^>]+> f3b60081 	vtrn\.16	d0, d1
+0[0-9a-f]+ <[^>]+> f3ba00c2 	vtrn\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba00c2 	vtrn\.32	q0, q1
+0[0-9a-f]+ <[^>]+> f3ba0081 	vtrn\.32	d0, d1
+0[0-9a-f]+ <[^>]+> f3b00800 	vtbl\.8	d0, {d0}, d0
+0[0-9a-f]+ <[^>]+> f3b00840 	vtbx\.8	d0, {d0}, d0
diff --git a/gas/testsuite/gas/arm/neon-cov.s b/gas/testsuite/gas/arm/neon-cov.s
new file mode 100644
index 000000000000..04194a83eb07
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-cov.s
@@ -0,0 +1,666 @@
+@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
+@ possible, but without causing instructions to be badly-formed.
+
+	.arm
+	.syntax unified
+	.text
+
+	.macro regs3_1 op opq vtype
+	\op\vtype q0,q0,q0
+	\opq\vtype q0,q0,q0
+	\op\vtype d0,d0,d0
+	.endm
+
+	.macro dregs3_1 op vtype
+	\op\vtype d0,d0,d0
+	.endm
+
+	.macro regn3_1 op operand2 vtype
+	\op\vtype d0,q0,\operand2
+	.endm
+
+	.macro regl3_1 op operand2 vtype
+	\op\vtype q0,d0,\operand2
+	.endm
+
+	.macro regw3_1 op operand2 vtype
+	\op\vtype q0,q0,\operand2
+	.endm
+
+	.macro regs2_1 op opq vtype
+	\op\vtype q0,q0
+	\opq\vtype q0,q0
+	\op\vtype d0,d0
+	.endm
+
+	.macro regs3_su_32 op opq
+	regs3_1 \op \opq .s8
+	regs3_1 \op \opq .s16
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u8
+	regs3_1 \op \opq .u16
+	regs3_1 \op \opq .u32
+	.endm
+
+	regs3_su_32 vaba vabaq
+	regs3_su_32 vhadd vhaddq
+	regs3_su_32 vrhadd vrhaddq
+	regs3_su_32 vhsub vhsubq
+
+	.macro regs3_su_64 op opq
+	regs3_1 \op \opq .s8
+	regs3_1 \op \opq .s16
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .s64
+	regs3_1 \op \opq .u8
+	regs3_1 \op \opq .u16
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .u64
+	.endm
+
+	regs3_su_64 vqadd vqaddq
+	regs3_su_64 vqsub vqsubq
+	regs3_su_64 vrshl vrshlq
+	regs3_su_64 vqrshl vqrshlq
+
+	regs3_su_64 vshl vshlq
+	regs3_su_64 vqshl vqshlq
+
+	.macro regs2i_1 op opq imm vtype
+	\op\vtype q0,q0,\imm
+	\opq\vtype q0,q0,\imm
+	\op\vtype d0,d0,\imm
+	.endm
+
+	.macro regs2i_su_64 op opq imm
+	regs2i_1 \op \opq \imm .s8
+	regs2i_1 \op \opq \imm .s16
+	regs2i_1 \op \opq \imm .s32
+	regs2i_1 \op \opq \imm .s64
+	regs2i_1 \op \opq \imm .u8
+	regs2i_1 \op \opq \imm .u16
+	regs2i_1 \op \opq \imm .u32
+	regs2i_1 \op \opq \imm .u64
+	.endm
+
+	.macro regs2i_i_64 op opq imm
+	regs2i_1 \op \opq \imm .i8
+	regs2i_1 \op \opq \imm .i16
+	regs2i_1 \op \opq \imm .i32
+	regs2i_1 \op \opq \imm .s32
+	regs2i_1 \op \opq \imm .u32
+	regs2i_1 \op \opq \imm .i64
+	.endm
+
+	regs2i_i_64 vshl vshlq 0
+	regs2i_su_64 vqshl vqshlq 0
+
+	.macro regs3_ntyp op opq
+	regs3_1 \op \opq .8
+	.endm
+
+	regs3_ntyp vand vandq
+	regs3_ntyp vbic vbicq
+	regs3_ntyp vorr vorrq
+	regs3_ntyp vorn vornq
+	regs3_ntyp veor veorq
+
+	.macro logic_imm_1 op opq imm vtype
+	\op\vtype q0,\imm
+	\opq\vtype q0,\imm
+	\op\vtype d0,\imm
+	.endm
+
+	.macro logic_imm op opq
+	logic_imm_1 \op \opq 0x000000a5000000a5 .i64
+	logic_imm_1 \op \opq 0x0000a5000000a500 .i64
+	logic_imm_1 \op \opq 0x00a5000000a50000 .i64
+	logic_imm_1 \op \opq 0xa5000000a5000000 .i64
+	logic_imm_1 \op \opq 0x00a500a500a500a5 .i64
+	logic_imm_1 \op \opq 0xa500a500a500a500 .i64
+	logic_imm_1 \op \opq 0x000000ff .i32
+	logic_imm_1 \op \opq 0x000000ff .s32
+	logic_imm_1 \op \opq 0x000000ff .u32
+	logic_imm_1 \op \opq 0x0000ff00 .i32
+	logic_imm_1 \op \opq 0x00ff0000 .i32
+	logic_imm_1 \op \opq 0xff000000 .i32
+	logic_imm_1 \op \opq 0x00a500a5 .i32
+	logic_imm_1 \op \opq 0xa500a500 .i32
+	logic_imm_1 \op \opq 0x00ff .i16
+	logic_imm_1 \op \opq 0xff00 .i16
+	logic_imm_1 \op \opq 0x00 .i8
+	.endm
+
+	logic_imm vbic vbicq
+	logic_imm vorr vorrq
+
+	.macro logic_inv_imm op opq
+	logic_imm_1 \op \opq 0xffffff5affffff5a .i64
+	logic_imm_1 \op \opq 0xffff5affffff5aff .i64
+	logic_imm_1 \op \opq 0xff5affffff5affff .i64
+	logic_imm_1 \op \opq 0x5affffff5affffff .i64
+	logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64
+	logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64
+	logic_imm_1 \op \opq 0xffffff00 .i32
+	logic_imm_1 \op \opq 0xffffff00 .s32
+	logic_imm_1 \op \opq 0xffffff00 .u32
+	logic_imm_1 \op \opq 0xffff00ff .i32
+	logic_imm_1 \op \opq 0xff00ffff .i32
+	logic_imm_1 \op \opq 0x00ffffff .i32
+	logic_imm_1 \op \opq 0xff5aff5a .i32
+	logic_imm_1 \op \opq 0x5aff5aff .i32
+	logic_imm_1 \op \opq 0xff00 .i16
+	logic_imm_1 \op \opq 0x00ff .i16
+	logic_imm_1 \op \opq 0xff .i8
+	.endm
+
+	logic_inv_imm vand vandq
+	logic_inv_imm vorn vornq
+
+	regs3_ntyp vbsl vbslq
+	regs3_ntyp vbit vbitq
+	regs3_ntyp vbif vbifq
+
+	.macro regs3_suf_32 op opq
+	regs3_1 \op \opq .s8
+	regs3_1 \op \opq .s16
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u8
+	regs3_1 \op \opq .u16
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .f32
+	.endm
+
+	.macro regs3_if_32 op opq
+	regs3_1 \op \opq .i8
+	regs3_1 \op \opq .i16
+	regs3_1 \op \opq .i32
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .f32
+	.endm
+
+	regs3_suf_32 vabd vabdq
+	regs3_suf_32 vmax vmaxq
+	regs3_suf_32 vmin vminq
+
+	regs3_suf_32 vcge vcgeq
+	regs3_suf_32 vcgt vcgtq
+	regs3_suf_32 vcle vcleq
+	regs3_suf_32 vclt vcltq
+
+	regs3_if_32 vceq vceqq
+
+	.macro regs2i_sf_0 op opq
+	regs2i_1 \op \opq 0 .s8
+	regs2i_1 \op \opq 0 .s16
+	regs2i_1 \op \opq 0 .s32
+	regs2i_1 \op \opq 0 .f32
+	.endm
+
+	regs2i_sf_0 vcge vcgeq
+	regs2i_sf_0 vcgt vcgtq
+	regs2i_sf_0 vcle vcleq
+	regs2i_sf_0 vclt vcltq
+
+	.macro regs2i_if_0 op opq
+	regs2i_1 \op \opq 0 .i8
+	regs2i_1 \op \opq 0 .i16
+	regs2i_1 \op \opq 0 .i32
+	regs2i_1 \op \opq 0 .s32
+	regs2i_1 \op \opq 0 .u32
+	regs2i_1 \op \opq 0 .f32
+	.endm
+
+	regs2i_if_0 vceq vceqq
+
+	.macro dregs3_suf_32 op
+	dregs3_1 \op .s8
+	dregs3_1 \op .s16
+	dregs3_1 \op .s32
+	dregs3_1 \op .u8
+	dregs3_1 \op .u16
+	dregs3_1 \op .u32
+	dregs3_1 \op .f32
+	.endm
+
+	dregs3_suf_32 vpmax
+	dregs3_suf_32 vpmin
+
+	.macro sregs3_1 op opq vtype
+	\op\vtype q0,q0,q0
+	\opq\vtype q0,q0,q0
+	\op\vtype d0,d0,d0
+	.endm
+
+	.macro sclr21_1 op opq vtype
+	\op\vtype q0,q0,d0[0]
+	\opq\vtype q0,q0,d0[0]
+	\op\vtype d0,d0,d0[0]
+	.endm
+
+	.macro mul_incl_scalar op opq
+	regs3_1 \op \opq .i8
+	regs3_1 \op \opq .i16
+	regs3_1 \op \opq .i32
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .f32
+	sclr21_1 \op \opq .i16
+	sclr21_1 \op \opq .i32
+	sclr21_1 \op \opq .s32
+	sclr21_1 \op \opq .u32
+	sclr21_1 \op \opq .f32
+	.endm
+
+	mul_incl_scalar vmla vmlaq
+	mul_incl_scalar vmls vmlsq
+
+	.macro dregs3_if_32 op
+	dregs3_1 \op .i8
+	dregs3_1 \op .i16
+	dregs3_1 \op .i32
+	dregs3_1 \op .s32
+	dregs3_1 \op .u32
+	dregs3_1 \op .f32
+	.endm
+
+	dregs3_if_32 vpadd
+
+	.macro regs3_if_64 op opq
+	regs3_1 \op \opq .i8
+	regs3_1 \op \opq .i16
+	regs3_1 \op \opq .i32
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .i64
+	regs3_1 \op \opq .f32
+	.endm
+
+	regs3_if_64 vadd vaddq
+	regs3_if_64 vsub vsubq
+
+	.macro regs3_sz_32 op opq
+	regs3_1 \op \opq .8
+	regs3_1 \op \opq .16
+	regs3_1 \op \opq .32
+	.endm
+
+	regs3_sz_32 vtst vtstq
+
+	.macro regs3_ifp_32 op opq
+        regs3_1 \op \opq .i8
+	regs3_1 \op \opq .i16
+	regs3_1 \op \opq .i32
+	regs3_1 \op \opq .s32
+	regs3_1 \op \opq .u32
+	regs3_1 \op \opq .f32
+	regs3_1 \op \opq .p8
+	.endm
+
+	regs3_ifp_32 vmul vmulq
+
+	.macro dqmulhs op opq
+	regs3_1 \op \opq .s16
+	regs3_1 \op \opq .s32
+	sclr21_1 \op \opq .s16
+	sclr21_1 \op \opq .s32
+	.endm
+
+	dqmulhs vqdmulh vqdmulhq
+	dqmulhs vqrdmulh vqrdmulhq
+
+	regs3_1 vacge vacgeq .f32
+	regs3_1 vacgt vacgtq .f32
+	regs3_1 vacle vacleq .f32
+	regs3_1 vaclt vacltq .f32
+	regs3_1 vrecps vrecpsq .f32
+	regs3_1 vrsqrts vrsqrtsq .f32
+
+	.macro regs2_sf_32 op opq
+	regs2_1 \op \opq .s8
+	regs2_1 \op \opq .s16
+	regs2_1 \op \opq .s32
+	regs2_1 \op \opq .f32
+	.endm
+
+	regs2_sf_32 vabs vabsq
+	regs2_sf_32 vneg vnegq
+
+	.macro rshift_imm op opq
+	regs2i_1 \op \opq 7 .s8
+	regs2i_1 \op \opq 15 .s16
+	regs2i_1 \op \opq 31 .s32
+	regs2i_1 \op \opq 63 .s64
+	regs2i_1 \op \opq 7 .u8
+	regs2i_1 \op \opq 15 .u16
+	regs2i_1 \op \opq 31 .u32
+	regs2i_1 \op \opq 63 .u64
+	.endm
+
+	rshift_imm vshr vshrq
+	rshift_imm vrshr vrshrq
+	rshift_imm vsra vsraq
+	rshift_imm vrsra vrsraq
+
+	regs2i_1 vsli vsliq 0 .8
+	regs2i_1 vsli vsliq 0 .16
+	regs2i_1 vsli vsliq 0 .32
+	regs2i_1 vsli vsliq 0 .64
+
+	regs2i_1 vsri vsriq 7 .8
+	regs2i_1 vsri vsriq 15 .16
+	regs2i_1 vsri vsriq 31 .32
+	regs2i_1 vsri vsriq 63 .64
+
+	regs2i_1 vqshlu vqshluq 0 .s8
+	regs2i_1 vqshlu vqshluq 0 .s16
+	regs2i_1 vqshlu vqshluq 0 .s32
+	regs2i_1 vqshlu vqshluq 0 .s64
+
+	.macro qrshift_imm op
+	regn3_1 \op 7 .s16
+	regn3_1 \op 15 .s32
+	regn3_1 \op 31 .s64
+	regn3_1 \op 7 .u16
+	regn3_1 \op 15 .u32
+	regn3_1 \op 31 .u64
+	.endm
+
+	.macro qrshiftu_imm op
+	regn3_1 \op 7 .s16
+	regn3_1 \op 15 .s32
+	regn3_1 \op 31 .s64
+	.endm
+
+	.macro qrshifti_imm op
+	regn3_1 \op 7 .i16
+	regn3_1 \op 15 .i32
+	regn3_1 \op 15 .s32
+	regn3_1 \op 15 .u32
+	regn3_1 \op 31 .i64
+	.endm
+
+	qrshift_imm vqshrn
+	qrshift_imm vqrshrn
+	qrshiftu_imm vqshrun
+	qrshiftu_imm vqrshrun
+
+	qrshifti_imm vshrn
+	qrshifti_imm vrshrn
+
+	regl3_1 vshll 1 .s8
+	regl3_1 vshll 1 .s16
+	regl3_1 vshll 1 .s32
+	regl3_1 vshll 1 .u8
+	regl3_1 vshll 1 .u16
+	regl3_1 vshll 1 .u32
+
+	regl3_1 vshll 8 .i8
+	regl3_1 vshll 16 .i16
+	regl3_1 vshll 32 .i32
+	regl3_1 vshll 32 .s32
+	regl3_1 vshll 32 .u32
+
+	.macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
+	\op\t1 \opr,\opr\arg
+	\op\t2 \opr,\opr\arg
+	\op\t3 \opr,\opr\arg
+	\op\t4 \opr,\opr\arg
+	.endm
+
+	convert vcvt q0
+	convert vcvtq q0
+	convert vcvt d0
+	convert vcvt q0 ",1"
+	convert vcvtq q0 ",1"
+	convert vcvt d0 ",1"
+
+	vmov q0,q0
+	vmov d0,d0
+	vmov.8 d0[0],r0
+	vmov.16 d0[0],r0
+	vmov.32 d0[0],r0
+	vmov d0,r0,r0
+	vmov.s8 r0,d0[0]
+	vmov.s16 r0,d0[0]
+	vmov.u8 r0,d0[0]
+	vmov.u16 r0,d0[0]
+	vmov.32 r0,d0[0]
+	vmov r0,r1,d0
+
+	.macro mov_imm op imm vtype
+	\op\vtype q0,\imm
+	\op\vtype d0,\imm
+	.endm
+
+	mov_imm vmov 0x00000077 .i32
+	mov_imm vmov 0x00000077 .s32
+	mov_imm vmov 0x00000077 .u32
+	mov_imm vmvn 0x00000077 .i32
+	mov_imm vmvn 0x00000077 .s32
+	mov_imm vmvn 0x00000077 .u32
+	mov_imm vmov 0x00007700 .i32
+	mov_imm vmvn 0x00007700 .i32
+	mov_imm vmov 0x00770000 .i32
+	mov_imm vmvn 0x00770000 .i32
+	mov_imm vmov 0x77000000 .i32
+	mov_imm vmvn 0x77000000 .i32
+	mov_imm vmov 0x0077 .i16
+	mov_imm vmvn 0x0077 .i16
+	mov_imm vmov 0x7700 .i16
+	mov_imm vmvn 0x7700 .i16
+	mov_imm vmov 0x000077ff .i32
+	mov_imm vmvn 0x000077ff .i32
+	mov_imm vmov 0x0077ffff .i32
+	mov_imm vmvn 0x0077ffff .i32
+	mov_imm vmov 0x77 .i8
+	mov_imm vmov 0xff0000ff000000ff .i64
+	mov_imm vmov 4.25 .f32
+
+	mov_imm vmov 0xa5a5 .i16
+	mov_imm vmvn 0xa5a5 .i16
+	mov_imm vmov 0xa5a5a5a5 .i32
+	mov_imm vmvn 0xa5a5a5a5 .i32
+	mov_imm vmov 0x00a500a5 .i32
+	mov_imm vmov 0xa500a500 .i32
+	mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64
+	mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64
+	mov_imm vmov 0x00a500a500a500a5 .i64
+	mov_imm vmov 0xa500a500a500a500 .i64
+	mov_imm vmov 0x000000a5000000a5 .i64
+	mov_imm vmov 0x0000a5000000a500 .i64
+	mov_imm vmov 0x00a5000000a50000 .i64
+	mov_imm vmov 0xa5000000a5000000 .i64
+	mov_imm vmov 0x0000a5ff0000a5ff .i64
+	mov_imm vmov 0x00a5ffff00a5ffff .i64
+	mov_imm vmov 0xa5ffffffa5ffffff .i64
+
+	vmvn q0,q0
+	vmvnq q0,q0
+	vmvn d0,d0
+
+	.macro long_ops op
+	regl3_1 \op d0 .s8
+	regl3_1 \op d0 .s16
+	regl3_1 \op d0 .s32
+	regl3_1 \op d0 .u8
+	regl3_1 \op d0 .u16
+	regl3_1 \op d0 .u32
+	.endm
+
+	long_ops vabal
+	long_ops vabdl
+	long_ops vaddl
+	long_ops vsubl
+
+	.macro long_mac op
+	regl3_1 \op d0 .s8
+	regl3_1 \op d0 .s16
+	regl3_1 \op d0 .s32
+	regl3_1 \op d0 .u8
+	regl3_1 \op d0 .u16
+	regl3_1 \op d0 .u32
+	regl3_1 \op "d0[0]" .s16
+	regl3_1 \op "d0[0]" .s32
+	regl3_1 \op "d0[0]" .u16
+	regl3_1 \op "d0[0]" .u32
+	.endm
+
+	long_mac vmlal
+	long_mac vmlsl
+
+	.macro wide_ops op
+	regw3_1 \op d0 .s8
+	regw3_1 \op d0 .s16
+	regw3_1 \op d0 .s32
+	regw3_1 \op d0 .u8
+	regw3_1 \op d0 .u16
+	regw3_1 \op d0 .u32
+	.endm
+
+	wide_ops vaddw
+	wide_ops vsubw
+
+	.macro narr_ops op
+	regn3_1 \op q0 .i16
+	regn3_1 \op q0 .i32
+	regn3_1 \op q0 .s32
+	regn3_1 \op q0 .u32
+	regn3_1 \op q0 .i64
+	.endm
+
+	narr_ops vaddhn
+	narr_ops vraddhn
+	narr_ops vsubhn
+	narr_ops vrsubhn
+
+	.macro long_dmac op
+	regl3_1 \op d0 .s16
+	regl3_1 \op d0 .s32
+	regl3_1 \op "d0[0]" .s16
+	regl3_1 \op "d0[0]" .s32
+	.endm
+
+	long_dmac vqdmlal
+	long_dmac vqdmlsl
+	long_dmac vqdmull
+
+	regl3_1 vmull d0 .s8
+	regl3_1 vmull d0 .s16
+	regl3_1 vmull d0 .s32
+	regl3_1 vmull d0 .u8
+	regl3_1 vmull d0 .u16
+	regl3_1 vmull d0 .u32
+	regl3_1 vmull d0 .p8
+	regl3_1 vmull "d0[0]" .s16
+	regl3_1 vmull "d0[0]" .s32
+	regl3_1 vmull "d0[0]" .u16
+	regl3_1 vmull "d0[0]" .u32
+
+	vext.8 q0,q0,q0,0
+	vextq.8 q0,q0,q0,0
+	vext.8 d0,d0,d0,0
+	vext.8 q0,q0,q0,8
+
+	.macro revs op opq vtype
+	\op\vtype q0,q0
+	\opq\vtype q0,q0
+	\op\vtype d0,d0
+	.endm
+
+	revs vrev64 vrev64q .8
+	revs vrev64 vrev64q .16
+	revs vrev64 vrev64q .32
+	revs vrev32 vrev32q .8
+	revs vrev32 vrev32q .16
+	revs vrev16 vrev16q .8
+
+	.macro dups op opq vtype
+	\op\vtype q0,r0
+	\opq\vtype q0,r0
+	\op\vtype d0,r0
+	\op\vtype q0,d0[0]
+	\opq\vtype q0,d0[0]
+	\op\vtype d0,d0[0]
+	.endm
+
+	dups vdup vdupq .8
+	dups vdup vdupq .16
+	dups vdup vdupq .32
+
+	.macro binop_3typ op op1 op2 t1 t2 t3
+	\op\t1 \op1,\op2
+	\op\t2 \op1,\op2
+	\op\t3 \op1,\op2
+	.endm
+
+	binop_3typ vmovl q0 d0 .s8 .s16 .s32
+	binop_3typ vmovl q0 d0 .u8 .u16 .u32
+	binop_3typ vmovn d0 q0 .i16 .i32 .i64
+	vmovn.s32 d0, q0
+	vmovn.u32 d0, q0
+	binop_3typ vqmovn d0 q0 .s16 .s32 .s64
+	binop_3typ vqmovn d0 q0 .u16 .u32 .u64
+	binop_3typ vqmovun d0 q0 .s16 .s32 .s64
+
+	.macro binops op opq vtype="" rhs="0"
+	\op\vtype q0,q\rhs
+	\opq\vtype q0,q\rhs
+	\op\vtype d0,d\rhs
+	.endm
+
+	.macro regs2_sz_32 op opq
+	binops \op \opq .8 1
+	binops \op \opq .16 1
+	binops \op \opq .32 1
+	.endm
+
+	regs2_sz_32 vzip vzipq
+	regs2_sz_32 vuzp vuzpq
+
+	.macro regs2_s_32 op opq
+	binops \op \opq .s8
+	binops \op \opq .s16
+	binops \op \opq .s32
+	.endm
+
+	regs2_s_32 vqabs vqabsq
+	regs2_s_32 vqneg vqnegq
+
+	.macro regs2_su_32 op opq
+	regs2_s_32 \op \opq
+	binops \op \opq .u8
+	binops \op \opq .u16
+	binops \op \opq .u32
+	.endm
+
+	regs2_su_32 vpadal vpadalq
+	regs2_su_32 vpaddl vpaddlq
+
+	binops vrecpe vrecpeq .u32
+	binops vrecpe vrecpeq .f32
+	binops vrsqrte vrsqrteq .u32
+	binops vrsqrte vrsqrteq .f32
+
+	regs2_s_32 vcls vclsq
+
+	.macro regs2_i_32 op opq
+	binops \op \opq .i8
+	binops \op \opq .i16
+	binops \op \opq .i32
+	binops \op \opq .s32
+	binops \op \opq .u32
+	.endm
+
+	regs2_i_32 vclz vclzq
+
+	binops vcnt vcntq .8
+
+	binops vswp vswpq "" 1
+
+	regs2_sz_32 vtrn vtrnq
+
+	vtbl.8 d0,{d0},d0
+	vtbx.8 d0,{d0},d0
+	
diff --git a/gas/testsuite/gas/arm/neon-ldst-es.d b/gas/testsuite/gas/arm/neon-ldst-es.d
new file mode 100644
index 000000000000..c520ac93116b
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-ldst-es.d
@@ -0,0 +1,57 @@
+# name: Neon element and structure loads and stores
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> f406282f 	vst2\.8	{d2-d3}, \[r6, :128\]
+0[0-9a-f]+ <[^>]+> f427140d 	vld3\.8	{d1-d3}, \[r7\]!
+0[0-9a-f]+ <[^>]+> f4091553 	vst3\.16	{d1,d3,d5}, \[r9, :64\], r3
+0[0-9a-f]+ <[^>]+> f42a208f 	vld4\.32	{d2-d5}, \[sl\]
+0[0-9a-f]+ <[^>]+> f40a114f 	vst4\.16	{d1,d3,d5,d7}, \[sl\]
+0[0-9a-f]+ <[^>]+> f4aa1c6f 	vld1\.16	{d1\[\]-d2\[\]}, \[sl\]
+0[0-9a-f]+ <[^>]+> f4aa1c5f 	vld1\.16	{d1\[\]}, \[sl, :16\]
+0[0-9a-f]+ <[^>]+> f4aa1dbf 	vld2\.32	{d1\[\],d3\[\]}, \[sl, :64\]
+0[0-9a-f]+ <[^>]+> f4aa3e0c 	vld3\.8	{d3\[\]-d5\[\]}, \[sl\], ip
+0[0-9a-f]+ <[^>]+> f4a9af6d 	vld4\.16	{d10\[\],d12\[\],d14\[\],d16\[\]}, \[r9\]!
+0[0-9a-f]+ <[^>]+> f4a9af5f 	vld4\.16	{d10\[\]-d13\[\]}, \[r9, :64\]
+0[0-9a-f]+ <[^>]+> f4a9af9f 	vld4\.32	{d10\[\]-d13\[\]}, \[r9, :64\]
+0[0-9a-f]+ <[^>]+> f4a9afdf 	vld4\.32	{d10\[\]-d13\[\]}, \[r9, :128\]
+0[0-9a-f]+ <[^>]+> f4a530ed 	vld1\.8	{d3\[7\]}, \[r5\]!
+0[0-9a-f]+ <[^>]+> f48554df 	vst1\.16	{d5\[3\]}, \[r5, :16\]
+0[0-9a-f]+ <[^>]+> f4a535dd 	vld2\.16	{d3\[3\],d4\[3\]}, \[r5, :32\]!
+0[0-9a-f]+ <[^>]+> f4858a83 	vst3\.32	{d8\[1\],d9\[1\],d10\[1\]}, \[r5\], r3
+0[0-9a-f]+ <[^>]+> f4a7804f 	vld1\.8	{d8\[2\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7848f 	vld1\.16	{d8\[2\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7849f 	vld1\.16	{d8\[2\]}, \[r7, :16\]
+0[0-9a-f]+ <[^>]+> f4a7888f 	vld1\.32	{d8\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a788bf 	vld1\.32	{d8\[1\]}, \[r7, :32\]
+0[0-9a-f]+ <[^>]+> f4a7812f 	vld2\.8	{d8\[1\],d9\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7813f 	vld2\.8	{d8\[1\],d9\[1\]}, \[r7, :16\]
+0[0-9a-f]+ <[^>]+> f4a7854f 	vld2\.16	{d8\[1\],d9\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7855f 	vld2\.16	{d8\[1\],d9\[1\]}, \[r7, :32\]
+0[0-9a-f]+ <[^>]+> f4a7856f 	vld2\.16	{d8\[1\],d10\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7857f 	vld2\.16	{d8\[1\],d10\[1\]}, \[r7, :32\]
+0[0-9a-f]+ <[^>]+> f4a7898f 	vld2\.32	{d8\[1\],d9\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7899f 	vld2\.32	{d8\[1\],d9\[1\]}, \[r7, :64\]
+0[0-9a-f]+ <[^>]+> f4a789cf 	vld2\.32	{d8\[1\],d10\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a789df 	vld2\.32	{d8\[1\],d10\[1\]}, \[r7, :64\]
+0[0-9a-f]+ <[^>]+> f4a7822f 	vld3\.8	{d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7864f 	vld3\.16	{d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7866f 	vld3\.16	{d8\[1\],d10\[1\],d12\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a78a8f 	vld3\.32	{d8\[1\],d9\[1\],d10\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a78acf 	vld3\.32	{d8\[1\],d10\[1\],d12\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7834f 	vld4\.8	{d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7835f 	vld4\.8	{d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7, :32\]
+0[0-9a-f]+ <[^>]+> f4a7876f 	vld4\.16	{d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a7875f 	vld4\.16	{d8\[1\],d9\[1\],d10\[1\],d11\[1\]}, \[r7, :64\]
+0[0-9a-f]+ <[^>]+> f4a78bcf 	vld4\.32	{d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\]
+0[0-9a-f]+ <[^>]+> f4a78bdf 	vld4\.32	{d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :64\]
+0[0-9a-f]+ <[^>]+> f4a78bef 	vld4\.32	{d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :128\]
+0[0-9a-f]+ <[^>]+> f3b43805 	vtbl\.8	d3, {d4}, d5
+0[0-9a-f]+ <[^>]+> f3b23b05 	vtbl\.8	d3, {d2-d5}, d5
+0[0-9a-f]+ <[^>]+> f3be3985 	vtbl\.8	d3, {d30-d31}, d5
+0[0-9a-f]+ <[^>]+> f427288f 	vld2\.32	{d2-d3}, \[r7\]
+0[0-9a-f]+ <[^>]+> f427208f 	vld4\.32	{d2-d5}, \[r7\]
+0[0-9a-f]+ <[^>]+> f467c08f 	vld4\.32	{d28-d31}, \[r7\]
diff --git a/gas/testsuite/gas/arm/neon-ldst-es.s b/gas/testsuite/gas/arm/neon-ldst-es.s
new file mode 100644
index 000000000000..5a29a4379390
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-ldst-es.s
@@ -0,0 +1,59 @@
+@ test element and structure loads and stores.
+
+	.text
+	.arm
+	.syntax unified
+
+	vst2.8 {d2,d3},[r6,:128]
+	vld3.8 {d1,d2,d3},[r7]!
+	vst3.16 {d1,d3,d5},[r9,:64],r3
+	vld4.32 {d2,d3,d4,d5},[r10]
+	vst4.16 {d1,d3,d5,d7},[r10]
+	vld1.16 {d1[],d2[]},[r10]
+	vld1.16 {d1[]},[r10,:16]
+	vld2.32 {d1[],d3[]},[r10,:64]
+	vld3.s8 {d3[],d4[],d5[]},[r10],r12
+	vld4.16 {d10[],d12[],d14[],d16[]},[r9]!
+	vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64]
+	vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64]
+	vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128]
+	vld1.8 {d3[7]},[r5]!
+	vst1.16 {d5[3]},[r5,:16]
+	vld2.16 {d3[3],d4[3]},[r5,:32]!
+	vst3.32 {d8[1],d9[1],d10[1]},[r5],r3
+        
+        vld1.8 {d8[2]},[r7]
+        vld1.16 {d8[2]},[r7]
+        vld1.16 {d8[2]},[r7,:16]
+        vld1.32 {d8[1]},[r7]
+        vld1.32 {d8[1]},[r7,:32]
+        vld2.8 {d8[1],d9[1]},[r7]
+        vld2.8 {d8[1],d9[1]},[r7,:16]
+        vld2.16 {d8[1],d9[1]},[r7]
+        vld2.16 {d8[1],d9[1]},[r7,:32]
+        vld2.16 {d8[1],d10[1]},[r7]
+        vld2.16 {d8[1],d10[1]},[r7,:32]
+        vld2.32 {d8[1],d9[1]},[r7]
+        vld2.32 {d8[1],d9[1]},[r7,:64]
+        vld2.32 {d8[1],d10[1]},[r7]
+        vld2.32 {d8[1],d10[1]},[r7,:64]
+        vld3.8 {d8[1],d9[1],d10[1]},[r7]
+        vld3.16 {d8[1],d9[1],d10[1]},[r7]
+        vld3.16 {d8[1],d10[1],d12[1]},[r7]
+        vld3.32 {d8[1],d9[1],d10[1]},[r7]
+        vld3.32 {d8[1],d10[1],d12[1]},[r7]
+	vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7]
+	vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7,:32]
+        vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7]
+        vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7,:64]
+        vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7]
+        vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:64]
+        vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:128]
+
+	vtbl.8 d3,{d4},d5
+	vtbl.8 d3,{q1-q2},d5
+	vtbl.8 d3,{q15},d5
+
+	vld2.32 {q1},[r7]
+	vld4.32 {q1-q2},[r7]
+	vld4.32 {q14-q15},[r7]
diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.d b/gas/testsuite/gas/arm/neon-ldst-rm.d
new file mode 100644
index 000000000000..86285d6dc35c
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-ldst-rm.d
@@ -0,0 +1,63 @@
+# name: Neon single and multiple register loads and stores
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> ec922b02 	vldmia	r2, {d2}
+0[0-9a-f]+ <[^>]+> ec922b04 	vldmia	r2, {d2-d3}
+0[0-9a-f]+ <[^>]+> ec924b08 	vldmia	r2, {d4-d7}
+0[0-9a-f]+ <[^>]+> ecd28b10 	vldmia	r2, {d24-d31}
+0[0-9a-f]+ <[^>]+> ec923b20 	vldmia	r2, {d3-d18}
+0[0-9a-f]+ <[^>]+> ec922b02 	vldmia	r2, {d2}
+0[0-9a-f]+ <[^>]+> ec922b04 	vldmia	r2, {d2-d3}
+0[0-9a-f]+ <[^>]+> ec924b08 	vldmia	r2, {d4-d7}
+0[0-9a-f]+ <[^>]+> ecd28b10 	vldmia	r2, {d24-d31}
+0[0-9a-f]+ <[^>]+> ec923b20 	vldmia	r2, {d3-d18}
+0[0-9a-f]+ <[^>]+> ecb22b02 	vldmia	r2!, {d2}
+0[0-9a-f]+ <[^>]+> ecb22b04 	vldmia	r2!, {d2-d3}
+0[0-9a-f]+ <[^>]+> ecb24b08 	vldmia	r2!, {d4-d7}
+0[0-9a-f]+ <[^>]+> ecf28b10 	vldmia	r2!, {d24-d31}
+0[0-9a-f]+ <[^>]+> ecb23b20 	vldmia	r2!, {d3-d18}
+0[0-9a-f]+ <[^>]+> ed322b02 	vldmdb	r2!, {d2}
+0[0-9a-f]+ <[^>]+> ed322b04 	vldmdb	r2!, {d2-d3}
+0[0-9a-f]+ <[^>]+> ed324b08 	vldmdb	r2!, {d4-d7}
+0[0-9a-f]+ <[^>]+> ed728b10 	vldmdb	r2!, {d24-d31}
+0[0-9a-f]+ <[^>]+> ed323b20 	vldmdb	r2!, {d3-d18}
+0[0-9a-f]+ <[^>]+> ec822b02 	vstmia	r2, {d2}
+0[0-9a-f]+ <[^>]+> ec822b04 	vstmia	r2, {d2-d3}
+0[0-9a-f]+ <[^>]+> ec824b08 	vstmia	r2, {d4-d7}
+0[0-9a-f]+ <[^>]+> ecc28b10 	vstmia	r2, {d24-d31}
+0[0-9a-f]+ <[^>]+> ec823b20 	vstmia	r2, {d3-d18}
+0[0-9a-f]+ <[^>]+> ec822b02 	vstmia	r2, {d2}
+0[0-9a-f]+ <[^>]+> ec822b04 	vstmia	r2, {d2-d3}
+0[0-9a-f]+ <[^>]+> ec824b08 	vstmia	r2, {d4-d7}
+0[0-9a-f]+ <[^>]+> ecc28b10 	vstmia	r2, {d24-d31}
+0[0-9a-f]+ <[^>]+> ec823b20 	vstmia	r2, {d3-d18}
+0[0-9a-f]+ <[^>]+> eca22b02 	vstmia	r2!, {d2}
+0[0-9a-f]+ <[^>]+> eca22b04 	vstmia	r2!, {d2-d3}
+0[0-9a-f]+ <[^>]+> eca24b08 	vstmia	r2!, {d4-d7}
+0[0-9a-f]+ <[^>]+> ece28b10 	vstmia	r2!, {d24-d31}
+0[0-9a-f]+ <[^>]+> eca23b20 	vstmia	r2!, {d3-d18}
+0[0-9a-f]+ <[^>]+> ed222b02 	vstmdb	r2!, {d2}
+0[0-9a-f]+ <[^>]+> ed222b04 	vstmdb	r2!, {d2-d3}
+0[0-9a-f]+ <[^>]+> ed224b08 	vstmdb	r2!, {d4-d7}
+0[0-9a-f]+ <[^>]+> ed628b10 	vstmdb	r2!, {d24-d31}
+0[0-9a-f]+ <[^>]+> ed223b20 	vstmdb	r2!, {d3-d18}
+0[0-9a-f]+ <backward> 000001f4 	.*
+0[0-9a-f]+ <[^>]+> eddf6b0b 	vldr	d22, \[pc, #44\]	; 0[0-9a-f]+ <forward>
+0[0-9a-f]+ <[^>]+> ed935b00 	vldr	d5, \[r3\]
+0[0-9a-f]+ <[^>]+> ed135b01 	vldr	d5, \[r3, #-4\]
+0[0-9a-f]+ <[^>]+> ed935b01 	vldr	d5, \[r3, #4\]
+0[0-9a-f]+ <[^>]+> ed835b00 	vstr	d5, \[r3\]
+0[0-9a-f]+ <[^>]+> ed035b01 	vstr	d5, \[r3, #-4\]
+0[0-9a-f]+ <[^>]+> ed835b01 	vstr	d5, \[r3, #4\]
+0[0-9a-f]+ <[^>]+> ed935b00 	vldr	d5, \[r3\]
+0[0-9a-f]+ <[^>]+> ed135b40 	vldr	d5, \[r3, #-256\]
+0[0-9a-f]+ <[^>]+> ed935b40 	vldr	d5, \[r3, #256\]
+0[0-9a-f]+ <[^>]+> ed835b00 	vstr	d5, \[r3\]
+0[0-9a-f]+ <[^>]+> ed035b40 	vstr	d5, \[r3, #-256\]
+0[0-9a-f]+ <[^>]+> ed835b40 	vstr	d5, \[r3, #256\]
+0[0-9a-f]+ <forward> 000002bc 	.*
+0[0-9a-f]+ <[^>]+> ed1f7b11 	vldr	d7, \[pc, #-68\]	; 0[0-9a-f]+ <backward>
diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.s b/gas/testsuite/gas/arm/neon-ldst-rm.s
new file mode 100644
index 000000000000..f9421ac5563c
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-ldst-rm.s
@@ -0,0 +1,44 @@
+@ test register and multi-register loads and stores.
+
+	.text
+	.arm
+	.syntax unified
+
+	.macro multi op dir="" wb=""
+	\op\dir r2\wb,{d2}
+	\op\dir r2\wb,{d2-d3}
+	\op\dir r2\wb,{q2-q3}
+	\op\dir r2\wb,{q12-q14,q15}
+	\op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18}
+	.endm
+
+	multi vldm
+	multi vldm ia
+	multi vldm ia "!"
+	multi vldm db "!"
+
+	multi vstm
+	multi vstm ia
+	multi vstm ia "!"
+	multi vstm db "!"
+
+backward:
+	.word 500
+
+	.macro single op offset=""
+	\op d5,[r3]
+	\op d5,[r3,#-\offset]
+	\op d5,[r3,#\offset]
+	.endm
+
+	vldr d22, forward
+
+	single vldr 4
+	single vstr 4
+	single vldr 256
+	single vstr 256
+
+forward:
+	.word 700
+
+	vldr d7, backward
diff --git a/gas/testsuite/gas/arm/neon-omit.d b/gas/testsuite/gas/arm/neon-omit.d
new file mode 100644
index 000000000000..fa7fa2cc75fe
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-omit.d
@@ -0,0 +1,95 @@
+# name: Neon optional register operands
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3022746 	vabd\.u8	q1, q1, q3
+0[0-9a-f]+ <[^>]+> f26cc0c6 	vhadd\.s32	q14, q14, q3
+0[0-9a-f]+ <[^>]+> f2222144 	vrhadd\.s32	q1, q1, q2
+0[0-9a-f]+ <[^>]+> f22aa24e 	vhsub\.s32	q5, q5, q7
+0[0-9a-f]+ <[^>]+> f3186446 	vshl\.u16	q3, q3, q4
+0[0-9a-f]+ <[^>]+> f32ca45a 	vqshl\.u32	q5, q5, q6
+0[0-9a-f]+ <[^>]+> f20ee170 	vand	q7, q7, q8
+0[0-9a-f]+ <[^>]+> f30ee170 	veor	q7, q7, q8
+0[0-9a-f]+ <[^>]+> f3b5a14a 	vceq\.i16	q5, q5, #0
+0[0-9a-f]+ <[^>]+> f31aa85a 	vceq\.i16	q5, q5, q5
+0[0-9a-f]+ <[^>]+> f3b5a24a 	vclt\.s16	q5, q5, #0
+0[0-9a-f]+ <[^>]+> f3b5a34c 	vabs\.s16	q5, q6
+0[0-9a-f]+ <[^>]+> f3b57388 	vneg\.s16	d7, d8
+0[0-9a-f]+ <[^>]+> f3b97708 	vabs\.f32	d7, d8
+0[0-9a-f]+ <[^>]+> f3f927e4 	vneg\.f32	q9, q10
+0[0-9a-f]+ <[^>]+> f2211a03 	vpmax\.s32	d1, d1, d3
+0[0-9a-f]+ <[^>]+> f2255a17 	vpmin\.s32	d5, d5, d7
+0[0-9a-f]+ <[^>]+> f3011f03 	vpmax\.f32	d1, d1, d3
+0[0-9a-f]+ <[^>]+> f3255f07 	vpmin\.f32	d5, d5, d7
+0[0-9a-f]+ <[^>]+> f2122b46 	vqdmulh\.s16	q1, q1, q3
+0[0-9a-f]+ <[^>]+> f3255b07 	vqrdmulh\.s32	d5, d5, d7
+0[0-9a-f]+ <[^>]+> f3922c6d 	vqdmulh\.s16	q1, q1, d5\[3\]
+0[0-9a-f]+ <[^>]+> f2122056 	vqadd\.s16	q1, q1, q3
+0[0-9a-f]+ <[^>]+> f2255017 	vqadd\.s32	d5, d5, d7
+0[0-9a-f]+ <[^>]+> f2222944 	vmla\.i32	q1, q1, q2
+0[0-9a-f]+ <[^>]+> f2133b14 	vpadd\.i16	d3, d3, d4
+0[0-9a-f]+ <[^>]+> f3266948 	vmls\.i32	q3, q3, q4
+0[0-9a-f]+ <[^>]+> f3022e54 	vacge\.f32	q1, q1, q2
+0[0-9a-f]+ <[^>]+> f3266e58 	vacgt\.f32	q3, q3, q4
+0[0-9a-f]+ <[^>]+> f30cae5a 	vacge\.f32	q5, q6, q5
+0[0-9a-f]+ <[^>]+> f320eede 	vacgt\.f32	q7, q8, q7
+0[0-9a-f]+ <[^>]+> f32ee370 	vcge\.u32	q7, q7, q8
+0[0-9a-f]+ <[^>]+> f32ee360 	vcgt\.u32	q7, q7, q8
+0[0-9a-f]+ <[^>]+> f320e3de 	vcge\.u32	q7, q8, q7
+0[0-9a-f]+ <[^>]+> f320e3ce 	vcgt\.u32	q7, q8, q7
+0[0-9a-f]+ <[^>]+> f3a22102 	vaddw\.u32	q1, q1, d2
+0[0-9a-f]+ <[^>]+> f2a66304 	vsubw\.s32	q3, q3, d4
+0[0-9a-f]+ <[^>]+> f2244856 	vtst\.32	q2, q2, q3
+0[0-9a-f]+ <[^>]+> f2011f12 	vrecps\.f32	d1, d1, d2
+0[0-9a-f]+ <[^>]+> f29c2052 	vshr\.s16	q1, q1, #4
+0[0-9a-f]+ <[^>]+> f28b4254 	vrshr\.s8	q2, q2, #5
+0[0-9a-f]+ <[^>]+> f39a6156 	vsra\.u16	q3, q3, #6
+0[0-9a-f]+ <[^>]+> f39a8358 	vrsra\.u16	q4, q4, #6
+0[0-9a-f]+ <[^>]+> f3954554 	vsli\.16	q2, q2, #5
+0[0-9a-f]+ <[^>]+> f3bff69f 	vqshlu\.s64	d15, d15, #63
+0[0-9a-f]+ <[^>]+> f2b55306 	vext\.8	d5, d5, d6, #3
+0[0-9a-f]+ <[^>]+> f3042746 	vabd\.u8	q1, q2, q3
+0[0-9a-f]+ <[^>]+> f262c0c6 	vhadd\.s32	q14, q9, q3
+0[0-9a-f]+ <[^>]+> f22a2144 	vrhadd\.s32	q1, q5, q2
+0[0-9a-f]+ <[^>]+> f220a2ce 	vhsub\.s32	q5, q8, q7
+0[0-9a-f]+ <[^>]+> f31a6448 	vshl\.u16	q3, q4, q5
+0[0-9a-f]+ <[^>]+> f322a45c 	vqshl\.u32	q5, q6, q1
+0[0-9a-f]+ <[^>]+> f200e1dc 	vand	q7, q8, q6
+0[0-9a-f]+ <[^>]+> f300e1dc 	veor	q7, q8, q6
+0[0-9a-f]+ <[^>]+> f3b5a146 	vceq\.i16	q5, q3, #0
+0[0-9a-f]+ <[^>]+> f316a85a 	vceq\.i16	q5, q3, q5
+0[0-9a-f]+ <[^>]+> f3b5a246 	vclt\.s16	q5, q3, #0
+0[0-9a-f]+ <[^>]+> f2231a20 	vpmax\.s32	d1, d3, d16
+0[0-9a-f]+ <[^>]+> f2275a34 	vpmin\.s32	d5, d7, d20
+0[0-9a-f]+ <[^>]+> f3031f07 	vpmax\.f32	d1, d3, d7
+0[0-9a-f]+ <[^>]+> f32c5f07 	vpmin\.f32	d5, d12, d7
+0[0-9a-f]+ <[^>]+> f2162b60 	vqdmulh\.s16	q1, q3, q8
+0[0-9a-f]+ <[^>]+> f3275b09 	vqrdmulh\.s32	d5, d7, d9
+0[0-9a-f]+ <[^>]+> f39c2c6d 	vqdmulh\.s16	q1, q6, d5\[3\]
+0[0-9a-f]+ <[^>]+> f21620d6 	vqadd\.s16	q1, q11, q3
+0[0-9a-f]+ <[^>]+> f227503f 	vqadd\.s32	d5, d7, d31
+0[0-9a-f]+ <[^>]+> f2242962 	vmla\.i32	q1, q2, q9
+0[0-9a-f]+ <[^>]+> f21a3b94 	vpadd\.i16	d3, d26, d4
+0[0-9a-f]+ <[^>]+> f328694a 	vmls\.i32	q3, q4, q5
+0[0-9a-f]+ <[^>]+> f3082e54 	vacge\.f32	q1, q4, q2
+0[0-9a-f]+ <[^>]+> f3226e58 	vacgt\.f32	q3, q1, q4
+0[0-9a-f]+ <[^>]+> f30cae72 	vacge\.f32	q5, q6, q9
+0[0-9a-f]+ <[^>]+> f320eed2 	vacgt\.f32	q7, q8, q1
+0[0-9a-f]+ <[^>]+> f320e3d6 	vcge\.u32	q7, q8, q3
+0[0-9a-f]+ <[^>]+> f320e3c6 	vcgt\.u32	q7, q8, q3
+0[0-9a-f]+ <[^>]+> f326e370 	vcge\.u32	q7, q3, q8
+0[0-9a-f]+ <[^>]+> f326e360 	vcgt\.u32	q7, q3, q8
+0[0-9a-f]+ <[^>]+> f3aa2102 	vaddw\.u32	q1, q5, d2
+0[0-9a-f]+ <[^>]+> f2a26304 	vsubw\.s32	q3, q1, d4
+0[0-9a-f]+ <[^>]+> f22648d6 	vtst\.32	q2, q11, q3
+0[0-9a-f]+ <[^>]+> f20e1f92 	vrecps\.f32	d1, d30, d2
+0[0-9a-f]+ <[^>]+> f29c207a 	vshr\.s16	q1, q13, #4
+0[0-9a-f]+ <[^>]+> f28b4272 	vrshr\.s8	q2, q9, #5
+0[0-9a-f]+ <[^>]+> f39a6152 	vsra\.u16	q3, q1, #6
+0[0-9a-f]+ <[^>]+> f3dae358 	vrsra\.u16	q15, q4, #6
+0[0-9a-f]+ <[^>]+> f3954556 	vsli\.16	q2, q3, #5
+0[0-9a-f]+ <[^>]+> f3bff6b7 	vqshlu\.s64	d15, d23, #63
+0[0-9a-f]+ <[^>]+> f2b25386 	vext\.8	d5, d18, d6, #3
diff --git a/gas/testsuite/gas/arm/neon-omit.s b/gas/testsuite/gas/arm/neon-omit.s
new file mode 100644
index 000000000000..42a7e8903b16
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-omit.s
@@ -0,0 +1,97 @@
+@ test omitted optional arguments
+
+	.text
+	.arm
+	.syntax unified
+
+	vabd.u8 q1,q3
+	vhadd.s32 q14, q3
+	vrhadd.s32 q1,q2
+	vhsub.s32 q5,q7
+	vshl.u16 q3,q4
+	vqshl.u32 q5,q6
+	vand.64 q7,q8
+	veor.64 q7,q8
+	vceq.i16 q5,#0
+	vceq.i16 q5,q5
+	vclt.s16 q5,#0
+	vabs.s16 q5,q6
+	vneg.s16 d7,d8
+	vabs.f d7,d8
+	vneg.f q9,q10
+	vpmax.s32 d1,d3
+	vpmin.s32 d5,d7
+	vpmax.f32 d1,d3
+	vpmin.f32 d5,d7
+	vqdmulh.s16 q1,q3
+	vqrdmulh.s32 d5,d7
+	vqdmulh.s16 q1,d5[3]
+	vqadd.s16 q1,q3
+	vqadd.s32 d5,d7
+	vmla.i32 q1,q2
+	vpadd.i16 d3,d4
+	vmls.s32 q3,q4
+	vacge.f q1,q2
+	vacgt.f q3,q4
+	vacle.f q5,q6
+	vaclt.f q7,q8
+	vcge.u32 q7,q8
+	vcgt.u32 q7,q8
+	vcle.u32 q7,q8
+	vclt.u32 q7,q8
+	vaddw.u32 q1,d2
+	vsubw.s32 q3,d4
+	vtst.i32 q2,q3
+	vrecps.f d1,d2
+	vshr.s16 q1,#4
+        vrshr.s8 q2,#5
+	vsra.u16 q3,#6
+        vrsra.u16 q4,#6
+	vsli.16 q2,#5
+	vqshlu.s64 d15,#63
+	vext.8 d5,d6,#3
+
+@ Also test three-argument forms without omitted arguments
+
+	vabd.u8 q1,q2,q3
+	vhadd.s32 q14,q9,q3
+	vrhadd.s32 q1,q5,q2
+	vhsub.s32 q5,q8,q7
+	vshl.u16 q3,q4,q5
+	vqshl.u32 q5,q6,q1
+	vand.64 q7,q8,q6
+	veor.64 q7,q8,q6
+	vceq.i16 q5,q3,#0
+	vceq.i16 q5,q3,q5
+	vclt.s16 q5,q3,#0
+	vpmax.s32 d1,d3,d16
+	vpmin.s32 d5,d7,d20
+	vpmax.f32 d1,d3,d7
+	vpmin.f32 d5,d12,d7
+	vqdmulh.s16 q1,q3,q8
+	vqrdmulh.s32 d5,d7,d9
+	vqdmulh.s16 q1,q6,d5[3]
+	vqadd.s16 q1,q11,q3
+	vqadd.s32 d5,d7,d31
+	vmla.i32 q1,q2,q9
+	vpadd.i16 d3,d26,d4
+	vmls.s32 q3,q4,q5
+	vacge.f q1,q4,q2
+	vacgt.f q3,q1,q4
+	vacle.f q5,q9,q6
+	vaclt.f q7,q1,q8
+	vcge.u32 q7,q8,q3
+	vcgt.u32 q7,q8,q3
+	vcle.u32 q7,q8,q3
+	vclt.u32 q7,q8,q3
+	vaddw.u32 q1,q5,d2
+	vsubw.s32 q3,q1,d4
+	vtst.i32 q2,q11,q3
+	vrecps.f d1,d30,d2
+	vshr.s16 q1,q13,#4
+        vrshr.s8 q2,q9,#5
+	vsra.u16 q3,q1,#6
+        vrsra.u16 q15,q4,#6
+	vsli.16 q2,q3,#5
+	vqshlu.s64 d15,d23,#63
+	vext.8 d5,d18,d6,#3
diff --git a/gas/testsuite/gas/arm/neon-psyn.d b/gas/testsuite/gas/arm/neon-psyn.d
new file mode 100644
index 000000000000..c318672f72b4
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-psyn.d
@@ -0,0 +1,37 @@
+# name: Neon programmers syntax
+# as: -mfpu=neon
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f2144954 	vmul\.i16	q2, q2, q2
+0[0-9a-f]+ <[^>]+> f2a33862 	vmul\.i32	d3, d3, d2\[1\]
+0[0-9a-f]+ <[^>]+> f2233912 	vmul\.i32	d3, d3, d2
+0[0-9a-f]+ <[^>]+> f2222803 	vadd\.i32	d2, d2, d3
+0[0-9a-f]+ <[^>]+> f3924a4a 	vmull\.u16	q2, d2, d2\[1\]
+0[0-9a-f]+ <[^>]+> f2910061 	vmla\.i16	d0, d1, d1\[2\]
+0[0-9a-f]+ <[^>]+> f2910061 	vmla\.i16	d0, d1, d1\[2\]
+0[0-9a-f]+ <[^>]+> f2255805 	vadd\.i32	d5, d5, d5
+0[0-9a-f]+ <[^>]+> f2275117 	vorr	d5, d7, d7
+0[0-9a-f]+ <[^>]+> ee021b70 	vmov\.16	d2\[1\], r1
+0[0-9a-f]+ <[^>]+> ee251b10 	vmov\.32	d5\[1\], r1
+0[0-9a-f]+ <[^>]+> ec432b15 	vmov	d5, r2, r3
+0[0-9a-f]+ <[^>]+> ee554b30 	vmov\.s8	r4, d5\[1\]
+0[0-9a-f]+ <[^>]+> ec565b15 	vmov	r5, r6, d5
+0[0-9a-f]+ <[^>]+> f396a507 	vabal\.u16	q5, d6, d7
+0[0-9a-f]+ <[^>]+> f3bb2744 	vcvt\.s32\.f32	q1, q2
+0[0-9a-f]+ <[^>]+> f3bb4e15 	vcvt\.f32\.u32	d4, d5, #5
+0[0-9a-f]+ <[^>]+> f3bc7c05 	vdup\.32	d7, d5\[1\]
+0[0-9a-f]+ <[^>]+> f3ba1904 	vtbl\.8	d1, {d10-d11}, d4
+0[0-9a-f]+ <[^>]+> f4aa698f 	vld2\.32	{d6\[1\],d7\[1\]}, \[sl\]
+0[0-9a-f]+ <[^>]+> f4aa476f 	vld4\.16	{d4\[1\],d6\[1\],d8\[1\],d10\[1\]}, \[sl\]
+0[0-9a-f]+ <[^>]+> f4aa6e4f 	vld3\.16	{d6\[\]-d8\[\]}, \[sl\]
+0[0-9a-f]+ <[^>]+> ee100b30 	vmov\.s16	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> f42a604f 	vld4\.16	{d6-d9}, \[sl\]
+0[0-9a-f]+ <[^>]+> f4aa266f 	vld3\.16	{d2\[1\],d4\[1\],d6\[1\]}, \[sl\]
+0[0-9a-f]+ <[^>]+> f3b47908 	vtbl\.8	d7, {d4-d5}, d8
+0[0-9a-f]+ <[^>]+> f3142156 	vbsl	q1, q2, q3
+0[0-9a-f]+ <[^>]+> f3032e04 	vcge\.f32	d2, d3, d4
+0[0-9a-f]+ <[^>]+> f3b52083 	vcge\.s16	d2, d3, #0
+0[0-9a-f]+ <[^>]+> ee823b30 	vdup\.16	d2, r3
diff --git a/gas/testsuite/gas/arm/neon-psyn.s b/gas/testsuite/gas/arm/neon-psyn.s
new file mode 100644
index 000000000000..5d412a8552f0
--- /dev/null
+++ b/gas/testsuite/gas/arm/neon-psyn.s
@@ -0,0 +1,78 @@
+	.arm
+	.syntax unified
+
+fish	.qn	q2
+cow	.dn	d2[1]
+chips	.dn	d2
+banana	.dn	d3
+
+	vmul fish.s16, fish.s16, fish.s16
+
+	vmul banana, banana, cow.s32
+	vmul d3.s32, d3.s32, d2.s32
+	vadd d2.s32, d3.s32
+	vmull fish.u32, chips.u16, chips.u16[1]
+
+X	.dn D0.S16
+Y	.dn D1.S16
+Z 	.dn Y[2]
+
+	VMLA X, Y, Z
+	VMLA X, Y, Y[2]
+
+foo	.dn d5
+bar	.dn d7
+foos	.dn foo[1]
+
+	vadd foo, foo, foo.u32
+
+	vmov foo, bar
+	vmov d2.s16[1], r1
+	vmov d5.s32[1], r1
+	vmov foo, r2, r3
+	vmov r4, foos.s8
+	vmov r5, r6, foo
+
+baa	.qn	q5
+moo	.dn	d6
+sheep	.dn	d7
+chicken	.dn	d8
+
+	vabal baa, moo.u16, sheep.u16
+
+	vcvt q1.s32, q2.f32
+	vcvt d4.f, d5.u32, #5
+
+	vdup bar, foos.32
+	vtbl d1, {baa}, d4.8
+
+el1	.dn	d4.16[1]
+el2	.dn	d6.16[1]
+el3	.dn	d8.16[1]
+el4	.dn	d10.16[1]
+
+	vld2 {moo.32[1], sheep.32[1]}, [r10]
+	vld4 {el1, el2, el3, el4}, [r10]
+	vld3 {moo.16[], sheep.16[], chicken.16[]}, [r10]
+
+	vmov r0,d0.s16[0]
+
+el5	.qn	q3.16
+el6	.qn	q4.16
+
+	vld4 {el5,el6}, [r10]
+
+	vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10]
+
+chicken8	.dn	chicken.8
+
+	vtbl d7.8, {d4, d5}, chicken8
+
+	vbsl q1.8, q2.16, q3.8
+
+	vcge d2.32, d3.f, d4.f
+	vcge d2.16, d3.s16, #0
+
+dupme	.dn	d2.s16
+
+	vdup dupme, r3
diff --git a/gas/testsuite/gas/arm/noarm.d b/gas/testsuite/gas/arm/noarm.d
new file mode 100644
index 000000000000..ae34f8342f95
--- /dev/null
+++ b/gas/testsuite/gas/arm/noarm.d
@@ -0,0 +1,3 @@
+# name: Disallow ARM instructions on V7M
+# as: 
+# error-output: noarm.l
diff --git a/gas/testsuite/gas/arm/noarm.l b/gas/testsuite/gas/arm/noarm.l
new file mode 100644
index 000000000000..edc59a2d5374
--- /dev/null
+++ b/gas/testsuite/gas/arm/noarm.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:12: Error: selected processor does not support ARM opcodes
+[^:]*:13: Error: attempt to use an ARM instruction on a Thumb-only processor -- `nop'
diff --git a/gas/testsuite/gas/arm/noarm.s b/gas/testsuite/gas/arm/noarm.s
new file mode 100644
index 000000000000..3dadd4468f14
--- /dev/null
+++ b/gas/testsuite/gas/arm/noarm.s
@@ -0,0 +1,13 @@
+        .arch armv7a
+        .syntax unified
+	.text
+func:
+	nop
+	movw r0, #0
+
+	.arch armv7
+	.thumb
+	nop
+	movw r0, #0
+	.arm
+	nop
diff --git a/gas/testsuite/gas/arm/relax_branch_align.d b/gas/testsuite/gas/arm/relax_branch_align.d
new file mode 100644
index 000000000000..e23b0951584d
--- /dev/null
+++ b/gas/testsuite/gas/arm/relax_branch_align.d
@@ -0,0 +1,13 @@
+#name: Branch relaxation with alignment.
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> bf00      	nop
+0+002 <[^>]+> f000 8080 	beq.w	0+106 <[^>]*>
+0+006 <[^>]+> bf00      	nop
+#...
+0+100 <[^>]+> bf00      	nop
+0+102 <[^>]+> f47f af80 	bne.w	0+006 <[^>]*>
+0+106 <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/relax_branch_align.s b/gas/testsuite/gas/arm/relax_branch_align.s
new file mode 100644
index 000000000000..718ce4982139
--- /dev/null
+++ b/gas/testsuite/gas/arm/relax_branch_align.s
@@ -0,0 +1,17 @@
+	.syntax unified
+	.thumb
+fn:
+	nop
+.L191:
+	beq	.L192
+.L46:
+	nop
+	.align	2
+.L54:
+	.rept 62
+	.word	0
+	.endr
+	nop
+	bne	.L46
+.L192:
+	nop
diff --git a/gas/testsuite/gas/arm/srs-arm.d b/gas/testsuite/gas/arm/srs-arm.d
new file mode 100644
index 000000000000..844c692dd9fc
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-arm.d
@@ -0,0 +1,2 @@
+# name: SRS instruction in ARM mode
+# error-output: srs-arm.l
diff --git a/gas/testsuite/gas/arm/srs-arm.l b/gas/testsuite/gas/arm/srs-arm.l
new file mode 100644
index 000000000000..ad992f8f7177
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-arm.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13'
+[^:]*:13: Error: SRS base register must be r13 -- `srsda r4,#13'
+[^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13'
+[^:]*:15: Error: SRS base register must be r13 -- `srsib r4,#13'
diff --git a/gas/testsuite/gas/arm/srs-arm.s b/gas/testsuite/gas/arm/srs-arm.s
new file mode 100644
index 000000000000..7d00fc8f0d6c
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-arm.s
@@ -0,0 +1,16 @@
+       .arch   armv6
+
+foo:
+       srsdb   r13, #13
+       srsdb   r13!, #13
+       srsia   r13, #13
+       srsia   r13!, #13
+       srsda   r13, #13
+       srsda   r13!, #13
+       srsib   r13, #13
+       srsib   r13!, #13
+       srsdb   r4, #13
+       srsda   r4, #13
+       srsia   r4, #13
+       srsib   r4, #13
+
diff --git a/gas/testsuite/gas/arm/srs-t2.d b/gas/testsuite/gas/arm/srs-t2.d
new file mode 100644
index 000000000000..dfa57dbd8af3
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-t2.d
@@ -0,0 +1,2 @@
+# name: SRS instruction in Thumb-2 mode
+# error-output: srs-t2.l
diff --git a/gas/testsuite/gas/arm/srs-t2.l b/gas/testsuite/gas/arm/srs-t2.l
new file mode 100644
index 000000000000..f0703759193c
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-t2.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]*:8: Error: SRS base register must be r13 -- `srsdb r4,#13'
+[^:]*:9: Error: SRS base register must be r13 -- `srsia r4,#13'
diff --git a/gas/testsuite/gas/arm/srs-t2.s b/gas/testsuite/gas/arm/srs-t2.s
new file mode 100644
index 000000000000..7132626a59a7
--- /dev/null
+++ b/gas/testsuite/gas/arm/srs-t2.s
@@ -0,0 +1,10 @@
+       .arch   armv6t2
+
+foo:
+       srsdb   r13, #13
+       srsdb   r13!, #13
+       srsia   r13, #13
+       srsia   r13!, #13
+       srsdb   r4, #13
+       srsia   r4, #13
+
diff --git a/gas/testsuite/gas/arm/svc.d b/gas/testsuite/gas/arm/svc.d
index fdeb9302083b..697756c7965d 100644
--- a/gas/testsuite/gas/arm/svc.d
+++ b/gas/testsuite/gas/arm/svc.d
@@ -1,6 +1,5 @@
 # name: SWI/SVC instructions
 # objdump: -dr --prefix-addresses --show-raw-insn
-# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d
index 47e9d89d9f94..be7afae7a40c 100644
--- a/gas/testsuite/gas/arm/tcompat.d
+++ b/gas/testsuite/gas/arm/tcompat.d
@@ -12,30 +12,30 @@ Disassembly of section .text:
 0+04 <[^>]*> e1a09000 ?	mov	r9, r0
 0+08 <[^>]*> e1a00009 ?	mov	r0, r9
 0+0c <[^>]*> e1a0c00e ?	mov	ip, lr
-0+10 <[^>]*> 91b09019 ?	movlss	r9, r9, lsl r0
-0+14 <[^>]*> 91a00910 ?	movls	r0, r0, lsl r9
-0+18 <[^>]*> e1b00880 ?	movs	r0, r0, lsl #17
-0+1c <[^>]*> e1a00889 ?	mov	r0, r9, lsl #17
-0+20 <[^>]*> 91b09039 ?	movlss	r9, r9, lsr r0
-0+24 <[^>]*> 91a00930 ?	movls	r0, r0, lsr r9
-0+28 <[^>]*> e1b008a0 ?	movs	r0, r0, lsr #17
-0+2c <[^>]*> e1a008a9 ?	mov	r0, r9, lsr #17
-0+30 <[^>]*> 91b09059 ?	movlss	r9, r9, asr r0
-0+34 <[^>]*> 91a00950 ?	movls	r0, r0, asr r9
-0+38 <[^>]*> e1b008c0 ?	movs	r0, r0, asr #17
-0+3c <[^>]*> e1a008c9 ?	mov	r0, r9, asr #17
-0+40 <[^>]*> 91b09079 ?	movlss	r9, r9, ror r0
-0+44 <[^>]*> 91a00970 ?	movls	r0, r0, ror r9
-0+48 <[^>]*> e1b008e0 ?	movs	r0, r0, ror #17
-0+4c <[^>]*> e1a008e9 ?	mov	r0, r9, ror #17
+0+10 <[^>]*> 91b09019 ?	lslsls	r9, r9, r0
+0+14 <[^>]*> 91a00910 ?	lslls	r0, r0, r9
+0+18 <[^>]*> e1b00880 ?	lsls	r0, r0, #17
+0+1c <[^>]*> e1a00889 ?	lsl	r0, r9, #17
+0+20 <[^>]*> 91b09039 ?	lsrsls	r9, r9, r0
+0+24 <[^>]*> 91a00930 ?	lsrls	r0, r0, r9
+0+28 <[^>]*> e1b008a0 ?	lsrs	r0, r0, #17
+0+2c <[^>]*> e1a008a9 ?	lsr	r0, r9, #17
+0+30 <[^>]*> 91b09059 ?	asrsls	r9, r9, r0
+0+34 <[^>]*> 91a00950 ?	asrls	r0, r0, r9
+0+38 <[^>]*> e1b008c0 ?	asrs	r0, r0, #17
+0+3c <[^>]*> e1a008c9 ?	asr	r0, r9, #17
+0+40 <[^>]*> 91b09079 ?	rorsls	r9, r9, r0
+0+44 <[^>]*> 91a00970 ?	rorls	r0, r0, r9
+0+48 <[^>]*> e1b008e0 ?	rors	r0, r0, #17
+0+4c <[^>]*> e1a008e9 ?	ror	r0, r9, #17
 0+50 <[^>]*> e2690000 ?	rsb	r0, r9, #0	; 0x0
 0+54 <[^>]*> e2709000 ?	rsbs	r9, r0, #0	; 0x0
 0+58 <[^>]*> 92600000 ?	rsbls	r0, r0, #0	; 0x0
-0+5c <[^>]*> 92799000 ?	rsblss	r9, r9, #0	; 0x0
-0+60 <[^>]*> e92d000e ?	stmdb	sp!, {r1, r2, r3}
-0+64 <[^>]*> 992d8154 ?	stmlsdb	sp!, {r2, r4, r6, r8, pc}
-0+68 <[^>]*> e8bd000e ?	ldmia	sp!, {r1, r2, r3}
-0+6c <[^>]*> 98bd8154 ?	ldmlsia	sp!, {r2, r4, r6, r8, pc}
+0+5c <[^>]*> 92799000 ?	rsbsls	r9, r9, #0	; 0x0
+0+60 <[^>]*> e92d000e ?	push	{r1, r2, r3}
+0+64 <[^>]*> 992d8154 ?	pushls	{r2, r4, r6, r8, pc}
+0+68 <[^>]*> e8bd000e ?	pop	{r1, r2, r3}
+0+6c <[^>]*> 98bd8154 ?	popls	{r2, r4, r6, r8, pc}
 0+70 <[^>]*> e0000001 ?	and	r0, r0, r1
 0+74 <[^>]*> e0200001 ?	eor	r0, r0, r1
 0+78 <[^>]*> e0400001 ?	sub	r0, r0, r1
diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
index d3f815a2986a..7f9b253a443f 100644
--- a/gas/testsuite/gas/arm/thumb.d
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -50,7 +50,7 @@ Disassembly of section \.text:
 0+050 <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+052 <[^>]+> 4738      	bx	r7
 0+054 <[^>]+> 4740      	bx	r8
-0+056 <[^>]+> 0000      	lsls	r0, r0, #0
+0+056 <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+058 <[^>]+> 4778      	bx	pc
 0+05a <[^>]+> 4b20      	ldr	r3, \[pc, #128\]	\(0+0dc <[^>]+>\)
 0+05c <[^>]+> 4c02      	ldr	r4, \[pc, #8\]	\(0+068 <[^>]+>\)
@@ -58,7 +58,7 @@ Disassembly of section \.text:
 0+060 <[^>]+> 5511      	strb	r1, \[r2, r4\]
 0+062 <[^>]+> 59f5      	ldr	r5, \[r6, r7\]
 0+064 <[^>]+> 5d62      	ldrb	r2, \[r4, r5\]
-	\.\.\.
+0+066 <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+068 <[^>]+> 52d1      	strh	r1, \[r2, r3\]
 0+06a <[^>]+> 5a23      	ldrh	r3, \[r4, r0\]
 0+06c <[^>]+> 57f1      	ldrsb	r1, \[r6, r7\]
@@ -75,7 +75,7 @@ Disassembly of section \.text:
 0+082 <[^>]+> 93ff      	str	r3, \[sp, #1020\]
 0+084 <[^>]+> 990b      	ldr	r1, \[sp, #44\]
 0+086 <[^>]+> 9a00      	ldr	r2, \[sp, #0\]
-0+088 <[^>]+> a7ff      	add	r7, pc, #1020	\(adr r7,0+488 <[^>]+>\)
+0+088 <[^>]+> a7ff      	add	r7, pc, #1020	\(adr r7, 0+488 <[^>]+>\)
 0+08a <[^>]+> ac80      	add	r4, sp, #512
 0+08c <[^>]+> b043      	add	sp, #268
 0+08e <[^>]+> b09a      	sub	sp, #104
@@ -111,11 +111,11 @@ Disassembly of section \.text:
 0+0ca <[^>]+> b07f      	add	sp, #508
 0+0cc <[^>]+> b0ff      	sub	sp, #508
 0+0ce <[^>]+> a8ff      	add	r0, sp, #1020
-0+0d0 <[^>]+> a0ff      	add	r0, pc, #1020	\(adr r0,0+4d0 <[^>]+>\)
+0+0d0 <[^>]+> a0ff      	add	r0, pc, #1020	\(adr r0, 0+4d0 <[^>]+>\)
 0+0d2 <[^>]+> b01a      	add	sp, #104
 0+0d4 <[^>]+> b09a      	sub	sp, #104
 0+0d6 <[^>]+> a81a      	add	r0, sp, #104
-0+0d8 <[^>]+> a01a      	add	r0, pc, #104	\(adr r0,0+144 <[^>]+>\)
+0+0d8 <[^>]+> a01a      	add	r0, pc, #104	\(adr r0, 0+144 <[^>]+>\)
 0+0da <[^>]+> 3168      	adds	r1, #104
 0+0dc <[^>]+> 2668      	movs	r6, #104
 0+0de <[^>]+> 2f68      	cmp	r7, #104
@@ -127,14 +127,14 @@ Disassembly of section \.text:
 0+0f0 <[^>]+> eb00000f 	bl	0+134 <[^>]+>
 0+0f4 <[^>]+> e12fff10 	bx	r0
 0+0f8 <[^>]+> ef123456 	(swi|svc)	0x00123456
-0+0fc <[^>]+> a004      	add	r0, pc, #16	\(adr r0,0+110 <[^>]+>\)
+0+0fc <[^>]+> a004      	add	r0, pc, #16	\(adr r0, 0+110 <[^>]+>\)
 0+0fe <[^>]+> e77f      	b.n	0+000 <[^>]+>
 0+100 <[^>]+> e018      	b.n	0+134 <[^>]+>
 0+102 <[^>]+> f7ff ff7d 	bl	0+000 <[^>]+>
 0+106 <[^>]+> f000 f815 	bl	0+134 <[^>]+>
 0+10a <[^>]+> 4700      	bx	r0
 0+10c <[^>]+> dfff      	(swi|svc)	255
-	\.\.\.
+0+10e <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+110 <[^>]+> d010      	beq.n	0+134 <[^>]+>
 0+112 <[^>]+> d10f      	bne.n	0+134 <[^>]+>
 0+114 <[^>]+> d20e      	bcs.n	0+134 <[^>]+>
diff --git a/gas/testsuite/gas/arm/thumb1_unified.d b/gas/testsuite/gas/arm/thumb1_unified.d
new file mode 100644
index 000000000000..c2fdf306325a
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb1_unified.d
@@ -0,0 +1,20 @@
+# name: Thumb-1 unified
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> 200c      	movs	r0, #12
+0[0-9a-f]+ <[^>]+> 1cd1      	adds	r1, r2, #3
+0[0-9a-f]+ <[^>]+> 1ed1      	subs	r1, r2, #3
+0[0-9a-f]+ <[^>]+> 3364      	adds	r3, #100
+0[0-9a-f]+ <[^>]+> 3c83      	subs	r4, #131
+0[0-9a-f]+ <[^>]+> 2d27      	cmp	r5, #39
+0[0-9a-f]+ <[^>]+> a103      	add	r1, pc, #12	\(adr [^)]*\)
+0[0-9a-f]+ <[^>]+> 4a03      	ldr	r2, \[pc, #12\]	\([^)]*\)
+0[0-9a-f]+ <[^>]+> 6863      	ldr	r3, \[r4, #4\]
+0[0-9a-f]+ <[^>]+> 9d01      	ldr	r5, \[sp, #4\]
+0[0-9a-f]+ <[^>]+> b001      	add	sp, #4
+0[0-9a-f]+ <[^>]+> b081      	sub	sp, #4
+0[0-9a-f]+ <[^>]+> af01      	add	r7, sp, #4
+0[0-9a-f]+ <[^>]+> 4251      	negs	r1, r2
diff --git a/gas/testsuite/gas/arm/thumb1_unified.s b/gas/testsuite/gas/arm/thumb1_unified.s
new file mode 100644
index 000000000000..c8da6ec5aa8e
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb1_unified.s
@@ -0,0 +1,25 @@
+.text
+.arch armv4t
+.syntax unified
+.thumb
+foo:
+movs r0, #12
+adds r1, r2, #3
+subs r1, r2, #3
+adds r3, r3, #0x64
+subs r4, r4, #0x83
+cmp r5, #0x27
+
+adr r1, bar
+ldr r2, bar
+ldr r3, [r4, #4]
+ldr r5, [sp, #4]
+add sp, sp, #4
+sub sp, sp, #4
+add r7, sp, #4
+
+rsbs r1, r2, #0
+
+.align 2
+bar:
+
diff --git a/gas/testsuite/gas/arm/thumb2_add.d b/gas/testsuite/gas/arm/thumb2_add.d
new file mode 100644
index 000000000000..5100bb691a7a
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_add.d
@@ -0,0 +1,30 @@
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> f60f 0000 	addw	r0, pc, #2048	; 0x800
+0+004 <[^>]+> f20f 0900 	addw	r9, pc, #0	; 0x0
+0+008 <[^>]+> f20f 4900 	addw	r9, pc, #1024	; 0x400
+0+00c <[^>]+> f509 6880 	add.w	r8, r9, #1024	; 0x400
+0+010 <[^>]+> f209 1801 	addw	r8, r9, #257	; 0x101
+0+014 <[^>]+> f201 1301 	addw	r3, r1, #257	; 0x101
+0+018 <[^>]+> f6af 0000 	subw	r0, pc, #2048	; 0x800
+0+01c <[^>]+> f2af 0900 	subw	r9, pc, #0	; 0x0
+0+020 <[^>]+> f2af 4900 	subw	r9, pc, #1024	; 0x400
+0+024 <[^>]+> f5a9 6880 	sub.w	r8, r9, #1024	; 0x400
+0+028 <[^>]+> f2a9 1801 	subw	r8, r9, #257	; 0x101
+0+02c <[^>]+> f2a1 1301 	subw	r3, r1, #257	; 0x101
+0+030 <[^>]+> f103 0301 	add.w	r3, r3, #1	; 0x1
+0+034 <[^>]+> f1a3 0301 	sub.w	r3, r3, #1	; 0x1
+0+038 <[^>]+> b0c0      	sub	sp, #256
+0+03a <[^>]+> f5ad 7d00 	sub.w	sp, sp, #512	; 0x200
+0+03e <[^>]+> f2ad 1d01 	subw	sp, sp, #257	; 0x101
+0+042 <[^>]+> b040      	add	sp, #256
+0+044 <[^>]+> f50d 7d00 	add.w	sp, sp, #512	; 0x200
+0+048 <[^>]+> f20d 1d01 	addw	sp, sp, #257	; 0x101
+0+04c <[^>]+> a840      	add	r0, sp, #256
+0+04e <[^>]+> f50d 6580 	add.w	r5, sp, #1024	; 0x400
+0+052 <[^>]+> f20d 1901 	addw	r9, sp, #257	; 0x101
+0+056 <[^>]+> 4271      	negs	r1, r6
diff --git a/gas/testsuite/gas/arm/thumb2_add.s b/gas/testsuite/gas/arm/thumb2_add.s
new file mode 100644
index 000000000000..a3b178a05291
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_add.s
@@ -0,0 +1,31 @@
+	.syntax unified
+	.text
+	.align	2
+	.global	thumb2_add
+	.thumb
+	.thumb_func
+thumb2_add:
+	add r0, pc, #0x800
+	add r9, pc, #0
+	add r9, pc, #0x400
+	add r8, r9, #0x400
+	add r8, r9, #0x101
+	add r3, r1, #0x101
+	sub r0, pc, #0x800
+	sub r9, pc, #0
+	sub r9, pc, #0x400
+	sub r8, r9, #0x400
+	sub r8, r9, #0x101
+	sub r3, r1, #0x101
+	add r3, #1
+	sub r3, #1
+	sub sp, sp, #0x100
+	sub sp, sp, #0x200
+	sub sp, sp, #0x101
+	add sp, sp, #0x100
+	add sp, sp, #0x200
+	add sp, sp, #0x101
+	add r0, sp, #0x100
+	add r5, sp, #0x400
+	add r9, sp, #0x101
+	rsbs r1, r6, #0
diff --git a/gas/testsuite/gas/arm/thumb2_bcond.d b/gas/testsuite/gas/arm/thumb2_bcond.d
index 8ab75320e1a3..02903a954191 100644
--- a/gas/testsuite/gas/arm/thumb2_bcond.d
+++ b/gas/testsuite/gas/arm/thumb2_bcond.d
@@ -1,26 +1,25 @@
 # as:
 # objdump: -dr --prefix-addresses --show-raw-insn
-# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 
 .*: +file format .*arm.*
 
 Disassembly of section .text:
 0+000 <[^>]+> bf18      	it	ne
-0+002 <[^>]+> e7fd      	b(|ne).n	0+0 <[^>]+>
+0+002 <[^>]+> e7fd      	bne.n	0+0 <[^>]+>
 0+004 <[^>]+> bf38      	it	cc
-0+006 <[^>]+> f7ff bffb 	b(|cc).w	0+0 <[^>]+>
+0+006 <[^>]+> f7ff bffb 	bcc.w	0+0 <[^>]+>
 0+00a <[^>]+> bf28      	it	cs
-0+00c <[^>]+> f7ff fff8 	bl(|cs)	0+0 <[^>]+>
+0+00c <[^>]+> f7ff fff8 	blcs	0+0 <[^>]+>
 0+010 <[^>]+> bfb8      	it	lt
-0+012 <[^>]+> 47a8      	blx(|lr)	r5
+0+012 <[^>]+> 47a8      	blxlt	r5
 0+014 <[^>]+> bf08      	it	eq
-0+016 <[^>]+> 4740      	bx(|eq)	r8
+0+016 <[^>]+> 4740      	bxeq	r8
 0+018 <[^>]+> bfc8      	it	gt
-0+01a <[^>]+> e8d4 f001 	tbb(|gt)	\[r4, r1\]
+0+01a <[^>]+> e8d4 f001 	tbbgt	\[r4, r1\]
 0+01e <[^>]+> bfb8      	it	lt
-0+020 <[^>]+> df00      	svc(|lt)	0
+0+020 <[^>]+> df00      	svclt	0
 0+022 <[^>]+> bfdc      	itt	le
 0+024 <[^>]+> be00      	bkpt	0x0000
-0+026 <[^>]+> bf00      	nop
+0+026 <[^>]+> bf00      	nople
 0+028 <[^>]+> bf00      	nop
 0+02a <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.d b/gas/testsuite/gas/arm/thumb2_it_bad.d
index f905c9f5e73b..1cca8b9650cb 100644
--- a/gas/testsuite/gas/arm/thumb2_it_bad.d
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.d
@@ -1,4 +1,3 @@
 #name: Invalid IT instructions
 #as:
-#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 #error-output: thumb2_it_bad.l
diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.d b/gas/testsuite/gas/arm/thumb2_ldmstm.d
new file mode 100644
index 000000000000..2f50486489c2
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_ldmstm.d
@@ -0,0 +1,27 @@
+# name: Thumb-2 LDM/STM single reg
+# as: -march=armv6t2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> bc01      	pop	{r0}
+0[0-9a-f]+ <[^>]+> f85d 8b04 	ldr.w	r8, \[sp\], #4
+0[0-9a-f]+ <[^>]+> f8d1 9000 	ldr.w	r9, \[r1\]
+0[0-9a-f]+ <[^>]+> f852 cb04 	ldr.w	ip, \[r2\], #4
+0[0-9a-f]+ <[^>]+> f85d 2d04 	ldr.w	r2, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f85d 8d04 	ldr.w	r8, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f856 4c04 	ldr.w	r4, \[r6, #-4\]
+0[0-9a-f]+ <[^>]+> f856 8c04 	ldr.w	r8, \[r6, #-4\]
+0[0-9a-f]+ <[^>]+> f852 4d04 	ldr.w	r4, \[r2, #-4\]!
+0[0-9a-f]+ <[^>]+> f852 cd04 	ldr.w	ip, \[r2, #-4\]!
+0[0-9a-f]+ <[^>]+> b408      	push	{r3}
+0[0-9a-f]+ <[^>]+> f84d 9b04 	str.w	r9, \[sp\], #4
+0[0-9a-f]+ <[^>]+> f8c3 c000 	str.w	ip, \[r3\]
+0[0-9a-f]+ <[^>]+> f844 cb04 	str.w	ip, \[r4\], #4
+0[0-9a-f]+ <[^>]+> f84d 3d04 	str.w	r3, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f84d 9d04 	str.w	r9, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f847 5c04 	str.w	r5, \[r7, #-4\]
+0[0-9a-f]+ <[^>]+> f846 cc04 	str.w	ip, \[r6, #-4\]
+0[0-9a-f]+ <[^>]+> f846 bd04 	str.w	fp, \[r6, #-4\]!
+0[0-9a-f]+ <[^>]+> f845 8d04 	str.w	r8, \[r5, #-4\]!
diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.s b/gas/testsuite/gas/arm/thumb2_ldmstm.s
new file mode 100644
index 000000000000..fd4410af3c4a
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_ldmstm.s
@@ -0,0 +1,24 @@
+.syntax unified
+.thumb
+ldmstm:
+	ldmia sp!, {r0}
+	ldmia sp!, {r8}
+	ldmia r1, {r9}
+	ldmia r2!, {ip}
+	ldmdb sp!, {r2}
+	ldmdb sp!, {r8}
+	ldmdb r6, {r4}
+	ldmdb r6, {r8}
+	ldmdb r2!, {r4}
+	ldmdb r2!, {ip}
+	stmia sp!, {r3}
+	stmia sp!, {r9}
+	stmia r3, {ip}
+	stmia r4!, {ip}
+	stmdb sp!, {r3}
+	stmdb sp!, {r9}
+	stmdb r7, {r5}
+	stmdb r6, {ip}
+	stmdb r6!, {fp}
+	stmdb r5!, {r8}
+
diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d
index 7bf0c605d5fd..752da7fb6aa7 100644
--- a/gas/testsuite/gas/arm/thumb2_pool.d
+++ b/gas/testsuite/gas/arm/thumb2_pool.d
@@ -1,5 +1,7 @@
 # as: -march=armv6t2
 # objdump: -dr --prefix-addresses --show-raw-insn
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 
 .*: +file format .*arm.*
 
@@ -11,5 +13,4 @@ Disassembly of section .text:
 0+00c <[^>]+> bf00      	nop
 0+00e <[^>]+> f8df 5004 	ldr\.w	r5, \[pc, #4\]	; 00+14 <[^>]+>
 0+012 <[^>]+> 4900      	ldr	r1, \[pc, #0\]	\(00+14 <[^>]+>\)
-0+014 <[^>]+> (5678|1234) .*
-0+016 <[^>]+> (1234|5678) .*
+0+014 <[^>]+> 12345678 ?	.word	0x12345678
diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d
index 48cd1f21f806..327ef42b5347 100644
--- a/gas/testsuite/gas/arm/thumb2_relax.d
+++ b/gas/testsuite/gas/arm/thumb2_relax.d
@@ -20,7 +20,7 @@ Disassembly of section .text:
 0+02e <[^>]+> f89f 800c 	ldrb.w	r8, \[pc, #12\]	; 0+03c <[^>]+>
 0+032 <[^>]+> f89f 100a 	ldrb.w	r1, \[pc, #10\]	; 0+03e <[^>]+>
 0+036 <[^>]+> f81f 1038 	ldrb.w	r1, \[pc, #-56\]	; 0+000 <[^>]+>
-0+03a <[^>]+> 0000      	lsls	r0, r0, #0
+0+03a <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+03c <[^>]+> bf00      	nop
 0+03e <[^>]+> f995 1000 	ldrsb.w	r1, \[r5\]
 0+042 <[^>]+> f995 1023 	ldrsb.w	r1, \[r5, #35\]
@@ -89,7 +89,7 @@ Disassembly of section .text:
 0+126 <[^>]+> f8df 800c 	ldr.w	r8, \[pc, #12\]	; 0+134 <[^>]+>
 0+12a <[^>]+> f8df 100a 	ldr.w	r1, \[pc, #10\]	; 0+136 <[^>]+>
 0+12e <[^>]+> f85f 1036 	ldr.w	r1, \[pc, #-54\]	; 0+0fa <[^>]+>
-0+132 <[^>]+> 0000      	lsls	r0, r0, #0
+0+132 <[^>]+> 46c0      	nop			\(mov r8, r8\)
 0+134 <[^>]+> bf00      	nop
 0+136 <[^>]+> 7029      	strb	r1, \[r5, #0\]
 0+138 <[^>]+> f885 1023 	strb.w	r1, \[r5, #35\]
@@ -142,7 +142,7 @@ Disassembly of section .text:
 0+1e0 <[^>]+> f8cf 1006 	str.w	r1, \[pc, #6\]	; 0+1ea <[^>]+>
 0+1e4 <[^>]+> f84f 103a 	str.w	r1, \[pc, #-58\]	; 0+1ae <[^>]+>
 0+1e8 <[^>]+> bf00      	nop
-0+1ea <[^>]+> a104      	add	r1, pc, #16	\(adr r1,0+1fc <[^>]+>\)
+0+1ea <[^>]+> a104      	add	r1, pc, #16	\(adr r1, 0+1fc <[^>]+>\)
 0+1ec <[^>]+> f20f 010c 	addw	r1, pc, #12	; 0xc
 0+1f0 <[^>]+> f20f 0808 	addw	r8, pc, #8	; 0x8
 0+1f4 <[^>]+> f20f 0106 	addw	r1, pc, #6	; 0x6
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 2977779aefdd..0d96818858e2 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -3,6 +3,7 @@
 # objdump: -dr --prefix-addresses --show-raw-insn
 # The arm-aout and arm-pe ports do not support Thumb branch relocations.
 # not-target: *-*-*aout* *-*-pe
+# stderr: thumb32.l
 
 .*: +file format .*arm.*
 
@@ -62,9 +63,9 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eb00 0800 	add\.w	r8, r0, r0
 0[0-9a-f]+ <[^>]+> 4401      	add	r1, r0
 0[0-9a-f]+ <[^>]+> 4408      	add	r0, r1
-0[0-9a-f]+ <[^>]+> a000      	add	r0, pc, #0	\(adr r0,[0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a500      	add	r5, pc, #0	\(adr r5,[0-9a-f]+ <[^>]+>\)
-0[0-9a-f]+ <[^>]+> a081      	add	r0, pc, #516	\(adr r0,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a000      	add	r0, pc, #0	\(adr r0, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a500      	add	r5, pc, #0	\(adr r5, [0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a081      	add	r0, pc, #516	\(adr r0, [0-9a-f]+ <[^>]+>\)
 0[0-9a-f]+ <[^>]+> a800      	add	r0, sp, #0
 0[0-9a-f]+ <[^>]+> ad00      	add	r5, sp, #0
 0[0-9a-f]+ <[^>]+> a881      	add	r0, sp, #516
@@ -349,163 +350,163 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> bf90      	nop	\{9\}
 0[0-9a-f]+ <[^>]+> f3af 8081 	nop\.w	\{129\}
 0[0-9a-f]+ <[^>]+> bf08      	it	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf18      	it	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf28      	it	cs
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopcs
 0[0-9a-f]+ <[^>]+> bf28      	it	cs
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopcs
 0[0-9a-f]+ <[^>]+> bf38      	it	cc
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopcc
 0[0-9a-f]+ <[^>]+> bf38      	it	cc
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopcc
 0[0-9a-f]+ <[^>]+> bf38      	it	cc
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopcc
 0[0-9a-f]+ <[^>]+> bf48      	it	mi
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopmi
 0[0-9a-f]+ <[^>]+> bf58      	it	pl
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	noppl
 0[0-9a-f]+ <[^>]+> bf68      	it	vs
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopvs
 0[0-9a-f]+ <[^>]+> bf78      	it	vc
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopvc
 0[0-9a-f]+ <[^>]+> bf88      	it	hi
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nophi
 0[0-9a-f]+ <[^>]+> bfa8      	it	ge
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopge
 0[0-9a-f]+ <[^>]+> bfb8      	it	lt
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	noplt
 0[0-9a-f]+ <[^>]+> bfc8      	it	gt
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopgt
 0[0-9a-f]+ <[^>]+> bfd8      	it	le
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nople
 0[0-9a-f]+ <[^>]+> bfe8      	it	al
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopal
 0[0-9a-f]+ <[^>]+> bf04      	itt	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf0c      	ite	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf02      	ittt	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf0a      	itet	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf06      	itte	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf0e      	itee	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf09      	itett	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf05      	ittet	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf03      	ittte	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf07      	ittee	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf0b      	itete	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf0d      	iteet	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf0f      	iteee	eq
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf1c      	itt	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf14      	ite	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf1e      	ittt	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf16      	itet	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf1a      	itte	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf12      	itee	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf1f      	itttt	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf17      	itett	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf1b      	ittet	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf1d      	ittte	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf19      	ittee	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf15      	itete	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> bf13      	iteet	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopne
 0[0-9a-f]+ <[^>]+> bf11      	iteee	ne
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
-0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nopne
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
+0[0-9a-f]+ <[^>]+> bf00      	nopeq
 0[0-9a-f]+ <[^>]+> f895 f000 	pld	\[r5\]
 0[0-9a-f]+ <[^>]+> f895 f330 	pld	\[r5, #816\]
 0[0-9a-f]+ <[^>]+> f815 fc30 	pld	\[r5, #-48\]
@@ -949,8 +950,83 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> e890 0300 	ldmia.w	r0, \{r8, r9\}
 0[0-9a-f]+ <[^>]+> e880 0300 	stmia.w	r0, \{r8, r9\}
 0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
-0[0-9a-f]+ <[^>]+> c806      	ldmia	r0!, \{r1, r2\}
-0[0-9a-f]+ <[^>]+> c006      	stmia	r0!, \{r1, r2\}
-0[0-9a-f]+ <[^>]+> e890 0300 	ldmia.w	r0, \{r8, r9\}
-0[0-9a-f]+ <[^>]+> e880 0300 	stmia.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> c806      	ldmiaeq	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> c006      	stmiaeq	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> e890 0300 	ldmiaeq.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> e880 0300 	stmiaeq.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> e98d c010 	srsia	sp, #16
+0[0-9a-f]+ <[^>]+> e80d c010 	srsdb	sp, #16
+0[0-9a-f]+ <[^>]+> e9ad c015 	srsia	sp!, #21
+0[0-9a-f]+ <[^>]+> e9ad c00a 	srsia	sp!, #10
+0[0-9a-f]+ <[^>]+> f3de 8f00 	subs	pc, lr, #0
+0[0-9a-f]+ <[^>]+> f3de 8f00 	subs	pc, lr, #0
+0[0-9a-f]+ <[^>]+> f3de 8f04 	subs	pc, lr, #4
+0[0-9a-f]+ <[^>]+> f3de 8fff 	subs	pc, lr, #255
+0[0-9a-f]+ <[^>]+> e9f9 240c 	ldrd	r2, r4, \[r9, #48\]!
+0[0-9a-f]+ <[^>]+> e979 240c 	ldrd	r2, r4, \[r9, #-48\]!
+0[0-9a-f]+ <[^>]+> e9e9 240c 	strd	r2, r4, \[r9, #48\]!
+0[0-9a-f]+ <[^>]+> e969 240c 	strd	r2, r4, \[r9, #-48\]!
+0[0-9a-f]+ <[^>]+> e8f9 240c 	ldrd	r2, r4, \[r9\], #48
+0[0-9a-f]+ <[^>]+> e879 240c 	ldrd	r2, r4, \[r9\], #-48
+0[0-9a-f]+ <[^>]+> e8e9 240c 	strd	r2, r4, \[r9\], #48
+0[0-9a-f]+ <[^>]+> e869 240c 	strd	r2, r4, \[r9\], #-48
+0[0-9a-f]+ <[^>]+> f8d5 1301 	ldr.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f855 1f30 	ldr.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f855 1d30 	ldr.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f855 1b30 	ldr.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f855 1930 	ldr.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f855 1009 	ldr.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f895 1301 	ldrb.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f815 1f30 	ldrb.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f815 1d30 	ldrb.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f815 1b30 	ldrb.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f815 1930 	ldrb.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f815 1009 	ldrb.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f995 1301 	ldrsb.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f915 1f30 	ldrsb.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f915 1d30 	ldrsb.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f915 1b30 	ldrsb.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f915 1930 	ldrsb.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f915 1009 	ldrsb.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f8b5 1301 	ldrh.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f835 1f30 	ldrh.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f835 1d30 	ldrh.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f835 1b30 	ldrh.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f835 1930 	ldrh.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f835 1009 	ldrh.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> f9b5 1301 	ldrsh.w	r1, \[r5, #769]
+0[0-9a-f]+ <[^>]+> f935 1f30 	ldrsh.w	r1, \[r5, #48]!
+0[0-9a-f]+ <[^>]+> f935 1d30 	ldrsh.w	r1, \[r5, #-48]!
+0[0-9a-f]+ <[^>]+> f935 1b30 	ldrsh.w	r1, \[r5\], #48
+0[0-9a-f]+ <[^>]+> f935 1930 	ldrsh.w	r1, \[r5\], #-48
+0[0-9a-f]+ <[^>]+> f935 1009 	ldrsh.w	r1, \[r5, r9\]
+0[0-9a-f]+ <[^>]+> 00a1      	lsls	r1, r4, #2
+0[0-9a-f]+ <[^>]+> ea5f 0389 	movs.w	r3, r9, lsl #2
+0[0-9a-f]+ <[^>]+> fa12 f103 	lsls.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 4099      	lsls	r1, r3
+0[0-9a-f]+ <[^>]+> fa11 f109 	lsls.w	r1, r1, r9
+0[0-9a-f]+ <[^>]+> fa02 f103 	lsl.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa01 f103 	lsl.w	r1, r1, r3
+0[0-9a-f]+ <[^>]+> 08a1      	lsrs	r1, r4, #2
+0[0-9a-f]+ <[^>]+> ea5f 0399 	movs.w	r3, r9, lsr #2
+0[0-9a-f]+ <[^>]+> fa32 f103 	lsrs.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 40d9      	lsrs	r1, r3
+0[0-9a-f]+ <[^>]+> fa31 f109 	lsrs.w	r1, r1, r9
+0[0-9a-f]+ <[^>]+> fa22 f103 	lsr.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa21 f103 	lsr.w	r1, r1, r3
+0[0-9a-f]+ <[^>]+> 10a1      	asrs	r1, r4, #2
+0[0-9a-f]+ <[^>]+> ea5f 03a9 	movs.w	r3, r9, asr #2
+0[0-9a-f]+ <[^>]+> fa52 f103 	asrs.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 4119      	asrs	r1, r3
+0[0-9a-f]+ <[^>]+> fa51 f109 	asrs.w	r1, r1, r9
+0[0-9a-f]+ <[^>]+> fa42 f103 	asr.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa41 f103 	asr.w	r1, r1, r3
+0[0-9a-f]+ <[^>]+> ea5f 01b4 	movs.w	r1, r4, ror #2
+0[0-9a-f]+ <[^>]+> ea5f 03b9 	movs.w	r3, r9, ror #2
+0[0-9a-f]+ <[^>]+> fa72 f103 	rors.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 41d9      	rors	r1, r3
+0[0-9a-f]+ <[^>]+> fa71 f109 	rors.w	r1, r1, r9
+0[0-9a-f]+ <[^>]+> fa62 f103 	ror.w	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa61 f103 	ror.w	r1, r1, r3
 0[0-9a-f]+ <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb32.l b/gas/testsuite/gas/arm/thumb32.l
new file mode 100644
index 000000000000..c687beac79e8
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb32.l
@@ -0,0 +1,17 @@
+[^;]*: Assembler messages:
+[^;]*:446: Warning: s suffix on comparison instruction is deprecated
+[^;]*:446: Warning: s suffix on comparison instruction is deprecated
+[^;]*:446: Warning: s suffix on comparison instruction is deprecated
+[^;]*:446: Warning: s suffix on comparison instruction is deprecated
+[^;]*:447: Warning: s suffix on comparison instruction is deprecated
+[^;]*:447: Warning: s suffix on comparison instruction is deprecated
+[^;]*:447: Warning: s suffix on comparison instruction is deprecated
+[^;]*:447: Warning: s suffix on comparison instruction is deprecated
+[^;]*:448: Warning: s suffix on comparison instruction is deprecated
+[^;]*:448: Warning: s suffix on comparison instruction is deprecated
+[^;]*:448: Warning: s suffix on comparison instruction is deprecated
+[^;]*:448: Warning: s suffix on comparison instruction is deprecated
+[^;]*:449: Warning: s suffix on comparison instruction is deprecated
+[^;]*:449: Warning: s suffix on comparison instruction is deprecated
+[^;]*:449: Warning: s suffix on comparison instruction is deprecated
+[^;]*:449: Warning: s suffix on comparison instruction is deprecated
diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
index b75a0850f384..697dfd240f34 100644
--- a/gas/testsuite/gas/arm/thumb32.s
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -769,3 +769,51 @@ xta:
 	ldmeq	r0, {r8, r9}
 	stmeq	r0, {r8, r9}
 	nop
+
+srs:
+	srsia sp, #16
+	srsdb sp, #16
+	srsia sp!, #21
+	srsia sp!, #10
+
+	movs pc, lr
+	subs pc, lr, #0
+	subs pc, lr, #4
+	subs pc, lr, #255
+
+	ldrd r2, r4, [r9, #48]!
+	ldrd r2, r4, [r9, #-48]!
+	strd r2, r4, [r9, #48]!
+	strd r2, r4, [r9, #-48]!
+	ldrd r2, r4, [r9], #48
+	ldrd r2, r4, [r9], #-48
+	strd r2, r4, [r9], #48
+	strd r2, r4, [r9], #-48
+
+	.macro ldaddr op
+	ldr\op	r1, [r5, #0x301]
+	ldr\op	r1, [r5, #0x30]!
+	ldr\op	r1, [r5, #-0x30]!
+	ldr\op	r1, [r5], #0x30
+	ldr\op	r1, [r5], #-0x30
+	ldr\op	r1, [r5, r9]
+	.endm
+	ldaddr
+	ldaddr b
+	ldaddr sb
+	ldaddr h
+	ldaddr sh
+	.macro movshift op s="s"
+	movs r1, r4, \op #2
+	movs r3, r9, \op #2
+	movs r1, r2, \op r3
+	movs r1, r1, \op r3
+	movs r1, r1, \op r9
+	mov r1, r2, \op r3
+	mov r1, r1, \op r3
+	.endm
+	movshift lsl
+	movshift lsr
+	movshift asr
+	movshift ror
+	nop
diff --git a/gas/testsuite/gas/arm/thumbrel.d b/gas/testsuite/gas/arm/thumbrel.d
new file mode 100644
index 000000000000..fff41af9cc98
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbrel.d
@@ -0,0 +1,14 @@
+#objdump: -sr
+# This test is only valid on EABI based ports.
+#target: *-*-*eabi *-*-symbianelf
+
+.*:     file format.*
+
+RELOCATION RECORDS FOR \[.text\]:
+OFFSET   TYPE              VALUE 
+00000004 R_ARM_REL32       b
+
+Contents of section .text:
+ 0000 00000000 (00000004|04000000) 00000000 00000000  .*
+# Ignore .ARM.attributes section
+#...
diff --git a/gas/testsuite/gas/arm/thumbrel.s b/gas/testsuite/gas/arm/thumbrel.s
new file mode 100644
index 000000000000..769da16156c7
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbrel.s
@@ -0,0 +1,11 @@
+@ Check that PC-relative relocs against local function symbols are
+@ generated correctly.
+.text
+.thumb
+a:
+.word 0
+.word b - a
+.word 0
+.word 0
+.type b, %function
+b:
diff --git a/gas/testsuite/gas/arm/thumbver.d b/gas/testsuite/gas/arm/thumbver.d
new file mode 100644
index 000000000000..ddc46df56d42
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbver.d
@@ -0,0 +1,15 @@
+# as: -meabi=4
+# readelf: -s
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+Symbol table '\.symtab' contains .* entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00000000     0 SECTION LOCAL  DEFAULT    1 
+#...
+     .*: 00000001     0 FUNC    LOCAL  DEFAULT    1 a_alias
+     .*: 00000001     0 FUNC    LOCAL  DEFAULT    1 a_body
+     .*: 00000000     0 NOTYPE  LOCAL  DEFAULT    1 \$t
+     .*: 00000001     0 FUNC    LOCAL  DEFAULT    1 a_export@VERSION
+#...
diff --git a/gas/testsuite/gas/arm/thumbver.s b/gas/testsuite/gas/arm/thumbver.s
new file mode 100644
index 000000000000..ad81395ee40c
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbver.s
@@ -0,0 +1,9 @@
+@ Check that symbols created by .symver are marked as Thumb.
+
+	.thumb_set a_alias, a_body
+	.symver a_alias, a_export@VERSION
+	.type a_body, %function
+	.code 16
+	.thumb_func
+a_body:
+	nop
diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d
index 5b41109292cb..5189dfff01f4 100644
--- a/gas/testsuite/gas/arm/tls.d
+++ b/gas/testsuite/gas/arm/tls.d
@@ -15,11 +15,11 @@ Disassembly of section .text:
    0:	e1a00000 	nop			\(mov r0,r0\)
    4:	e1a00000 	nop			\(mov r0,r0\)
    8:	e1a0f00e 	mov	pc, lr
-   c:	00000000 	andeq	r0, r0, r0
+   c:	00000000 	.word	0x00000000
 			c: R_ARM_TLS_GD32	a
-  10:	00000004 	andeq	r0, r0, r4
+  10:	00000004 	.word	0x00000004
 			10: R_ARM_TLS_LDM32	b
-  14:	00000008 	andeq	r0, r0, r8
+  14:	00000008 	.word	0x00000008
 			14: R_ARM_TLS_IE32	c
-  18:	00000000 	andeq	r0, r0, r0
+  18:	00000000 	.word	0x00000000
 			18: R_ARM_TLS_LE32	d
diff --git a/gas/testsuite/gas/arm/undefined.d b/gas/testsuite/gas/arm/undefined.d
index 6a6149561cc3..e3e9bb08929c 100644
--- a/gas/testsuite/gas/arm/undefined.d
+++ b/gas/testsuite/gas/arm/undefined.d
@@ -1,4 +1,5 @@
 #name: Undefined local label error
-# COFF and aout based ports use a different naming convention for local labels.
-#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# COFF and aout based ports, except Windows CE, 
+# use a different naming convention for local labels.
+#skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix*
 #error-output: undefined.l
diff --git a/gas/testsuite/gas/arm/undefined_coff.d b/gas/testsuite/gas/arm/undefined_coff.d
index ab0bbcdc6672..d2800275b078 100644
--- a/gas/testsuite/gas/arm/undefined_coff.d
+++ b/gas/testsuite/gas/arm/undefined_coff.d
@@ -1,4 +1,5 @@
 #name: Undefined local label error
-# COFF and aout based ports use a different naming convention for local labels.
-#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# COFF and aout based ports, except Windows CE, 
+# use a different naming convention for local labels.
+#not-skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix*
 #error-output: undefined_coff.l
diff --git a/gas/testsuite/gas/arm/unwind.d b/gas/testsuite/gas/arm/unwind.d
index cd4a7c7995c2..060f7ba56afe 100644
--- a/gas/testsuite/gas/arm/unwind.d
+++ b/gas/testsuite/gas/arm/unwind.d
@@ -25,18 +25,22 @@ OFFSET   TYPE              VALUE
 0000001c R_ARM_PREL31      .ARM.extab.*
 00000020 R_ARM_PREL31      .text.*
 00000028 R_ARM_PREL31      .text.*
+00000030 R_ARM_PREL31      .text.*
+00000034 R_ARM_PREL31      .ARM.extab.*
 
 
 Contents of section .text:
  0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003)  .*
- 0010 (04200520|20052004)                             .*
+ 0010 (04200520 0600a0e3|20052004 e3a00006)                    .*
 Contents of section .ARM.extab:
  0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000  .*
- 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600)  .*
- 0020 (b0b0c1c1|c1c1b0b0) 00000000                    .*
+ 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600)  .*
+ 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42)  .*
+ 0030 (b0008086|868000b0) 00000000                    .*
 Contents of section .ARM.exidx:
  0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000  .*
  0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c)  .*
  0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0)  .*
+ 0030 (14000000 2c000000|00000014 0000002c)                    .*
 # Ignore .ARM.attributes section
 #...
diff --git a/gas/testsuite/gas/arm/unwind.s b/gas/testsuite/gas/arm/unwind.s
index 7d0f126954f1..bbd73a157d94 100644
--- a/gas/testsuite/gas/arm/unwind.s
+++ b/gas/testsuite/gas/arm/unwind.s
@@ -27,6 +27,8 @@ foo2:	@ Custom personality routine
 	.fnend
 foo3:	@ Saving iwmmxt registers
 	.fnstart
+	.save {wr12}
+	.save {wr13}
 	.save {wr11}
 	.save {wr10}
 	.save {wr10, wr11}
@@ -49,3 +51,17 @@ foo5:	@ Save r0-r3 only.
 	.save {r0, r1, r2, r3}
 	mov r0, #5
 	.fnend
+	.code 32
+foo6:	@ Nested function with frame pointer
+	.fnstart
+	.pad #4
+	@push {ip}
+	.movsp ip, #4
+	@mov ip, sp
+	.pad #4
+	.save {fp, ip, lr}
+	@stmfd sp!, {fp, ip, lr, pc}
+	.setfp fp, ip, #-8
+	@sub fp, ip, #8
+	mov r0, #6
+	.fnend
diff --git a/gas/testsuite/gas/arm/unwind_vxworks.d b/gas/testsuite/gas/arm/unwind_vxworks.d
index ccd16a65cc9a..11817cf48c16 100644
--- a/gas/testsuite/gas/arm/unwind_vxworks.d
+++ b/gas/testsuite/gas/arm/unwind_vxworks.d
@@ -24,6 +24,8 @@ OFFSET   TYPE              VALUE
 0000001c R_ARM_PREL31      .ARM.extab.*\+0x0000001c
 00000020 R_ARM_PREL31      .text.*\+0x00000010
 00000028 R_ARM_PREL31      .text.*\+0x00000012
+00000030 R_ARM_PREL31      .text.*\+0x00000014
+00000034 R_ARM_PREL31      .ARM.extab.*\+0x0000002c
 
 
 Contents of section .text:
@@ -31,11 +33,13 @@ Contents of section .text:
  0010 (04200520|20052004)                             .*
 Contents of section .ARM.extab:
  0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000  .*
- 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600)  .*
- 0020 (b0b0c1c1|c1c1b0b0) 00000000                    .*
+ 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600)  .*
+ 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42)  .*
+ 0030 (b0008086|868000b0) 00000000                    .*
 Contents of section .ARM.exidx:
  0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000  .*
  0010 00000000 00000000 00000000 00000000  .*
  0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0)  .*
+ 0030 00000000 00000000                    .*
 # Ignore .ARM.attributes section
 #...
diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.d b/gas/testsuite/gas/arm/vfp-neon-overlap.d
new file mode 100644
index 000000000000..b7815640089d
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-overlap.d
@@ -0,0 +1,35 @@
+# name: VFP/Neon overlapping instructions
+# as: -mfpu=vfp
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> ec410b10 	vmov	d0, r0, r1
+0[0-9a-f]+ <[^>]+> ec410b10 	vmov	d0, r0, r1
+0[0-9a-f]+ <[^>]+> ec510b10 	vmov	r0, r1, d0
+0[0-9a-f]+ <[^>]+> ec510b10 	vmov	r0, r1, d0
+0[0-9a-f]+ <[^>]+> ec900b09 	fldmiax	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b09 	fldmdbx	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b09 	fstmiax	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b09 	fstmdbx	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed900b00 	vldr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed900b00 	vldr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed800b00 	vstr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ed800b00 	vstr	d0, \[r0\]
+0[0-9a-f]+ <[^>]+> ec900b08 	vldmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec900b08 	vldmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b08 	vldmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed300b08 	vldmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b08 	vstmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ec800b08 	vstmia	r0, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b08 	vstmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ed200b08 	vstmdb	r0!, {d0-d3}
+0[0-9a-f]+ <[^>]+> ee300b10 	vmov\.32	r0, d0\[1\]
+0[0-9a-f]+ <[^>]+> ee300b10 	vmov\.32	r0, d0\[1\]
+0[0-9a-f]+ <[^>]+> ee100b10 	vmov\.32	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee100b10 	vmov\.32	r0, d0\[0\]
+0[0-9a-f]+ <[^>]+> ee200b10 	vmov\.32	d0\[1\], r0
+0[0-9a-f]+ <[^>]+> ee200b10 	vmov\.32	d0\[1\], r0
+0[0-9a-f]+ <[^>]+> ee000b10 	vmov\.32	d0\[0\], r0
+0[0-9a-f]+ <[^>]+> ee000b10 	vmov\.32	d0\[0\], r0
diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.s b/gas/testsuite/gas/arm/vfp-neon-overlap.s
new file mode 100644
index 000000000000..19c286afca43
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-overlap.s
@@ -0,0 +1,41 @@
+@ VFP/Neon overlapping instructions
+
+	.arm
+	.text
+	.syntax unified
+
+	fmdrr d0,r0,r1
+        vmov d0,r0,r1
+        fmrrd r0,r1,d0
+        vmov r0,r1,d0
+
+	@ the 'x' versions should disassemble as VFP instructions, because
+        @ they can't be represented in Neon syntax.
+
+	fldmiax r0,{d0-d3}
+        fldmdbx r0!,{d0-d3}
+        fstmiax r0,{d0-d3}
+        fstmdbx r0!,{d0-d3}
+
+	fldd d0,[r0]
+        vldr d0,[r0]
+        fstd d0,[r0]
+        vstr d0,[r0]
+
+	fldmiad r0,{d0-d3}
+        vldmia r0,{d0-d3}
+        fldmdbd r0!,{d0-d3}
+        vldmdb r0!,{d0-d3}
+        fstmiad r0,{d0-d3}
+        vstmia r0,{d0-d3}
+        fstmdbd r0!,{d0-d3}
+        vstmdb r0!,{d0-d3}
+
+	fmrdh r0,d0
+        vmov.32 r0,d0[1]
+        fmrdl r0,d0
+        vmov.32 r0,d0[0]
+	fmdhr d0,r0
+        vmov.32 d0[1],r0
+        fmdlr d0,r0
+        vmov.32 d0[0],r0
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
new file mode 100644
index 000000000000..fad0bded369c
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s
@@ -0,0 +1,162 @@
+@ VFP with Neon-style syntax
+	.syntax unified
+
+	.include "itblock.s"
+
+func:
+	.macro testvmov cond="" f32=".f32" f64=".f64"
+	itblock 4 \cond
+        vmov\cond\f32 s0,s1
+        vmov\cond\f64 d0,d1
+        vmov\cond\f32 s0,#0.25
+        vmov\cond\f64 d0,#1.0
+	itblock 4 \cond
+        vmov\cond r0,s1
+        vmov\cond s0,r1
+        vmov\cond r0,r1,s2,s3
+        vmov\cond s0,s1,r2,r4
+	.endm
+
+	@ Test VFP vmov variants. These can all be conditional.
+	testvmov
+	testvmov eq
+
+	.macro monadic op cond="" f32=".f32" f64=".f64"
+	itblock 2 \cond
+	\op\cond\f32 s0,s1
+	\op\cond\f64 d0,d1
+	.endm
+
+	.macro monadic_c op
+	monadic \op
+	monadic \op eq
+	.endm
+
+	.macro dyadic op cond="" f32=".f32" f64=".f64"
+	itblock 2 \cond
+	\op\cond\f32 s0,s1,s2
+	\op\cond\f64 d0,d1,d2
+	.endm
+
+	.macro dyadic_c op
+	dyadic \op
+	dyadic \op eq
+	.endm
+
+	.macro dyadicz op cond="" f32=".f32" f64=".f64"
+	itblock 2 \cond
+	\op\cond\f32 s0,#0
+	\op\cond\f64 d0,#0
+	.endm
+
+	.macro dyadicz_c op
+	dyadicz \op
+	dyadicz \op eq
+	.endm
+
+	monadic_c vsqrt
+	monadic_c vabs
+	monadic_c vneg
+	monadic_c vcmp
+	monadic_c vcmpe
+
+	dyadic_c vnmul
+	dyadic_c vnmla
+	dyadic_c vnmls
+
+	dyadic_c vmul
+	dyadic_c vmla
+	dyadic_c vmls
+
+	dyadic_c vadd
+	dyadic_c vsub
+
+	dyadic_c vdiv
+
+	dyadicz_c vcmp
+	dyadicz_c vcmpe
+
+	.macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
+	itblock 4 \cond
+	vcvtz\cond\s32\f32 s0,s1
+	vcvtz\cond\u32\f32 s0,s1
+	vcvtz\cond\s32\f64 s0,d1
+	vcvtz\cond\u32\f64 s0,d1
+	.endm
+
+	cvtz
+	cvtz eq
+
+	.macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
+	itblock 4 \cond
+	vcvt\cond\s32\f32 s0,s1
+	vcvt\cond\u32\f32 s0,s1
+	vcvt\cond\f32\s32 s0,s1
+	vcvt\cond\f32\u32 s0,s1
+	itblock 4 \cond
+	vcvt\cond\f32\f64 s0,d1
+	vcvt\cond\f64\f32 d0,s1
+	vcvt\cond\s32\f64 s0,d1
+	vcvt\cond\u32\f64 s0,d1
+	itblock 2 \cond
+	vcvt\cond\f64\s32 d0,s1
+	vcvt\cond\f64\u32 d0,s1
+	.endm
+
+	cvt
+	cvt eq
+
+	.macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
+	itblock 4 \cond
+	vcvt\cond\s32\f32 s0,s0,#1
+	vcvt\cond\u32\f32 s0,s0,#1
+	vcvt\cond\f32\s32 s0,s0,#1
+	vcvt\cond\f32\u32 s0,s0,#1
+	itblock 4 \cond
+	vcvt\cond\s32\f64 d0,d0,#1
+	vcvt\cond\u32\f64 d0,d0,#1
+	vcvt\cond\f64\s32 d0,d0,#1
+	vcvt\cond\f64\u32 d0,d0,#1
+	itblock 4 \cond
+	vcvt\cond\f32\s16 s0,s0,#1
+	vcvt\cond\f32\u16 s0,s0,#1
+	vcvt\cond\f64\s16 d0,d0,#1
+	vcvt\cond\f64\u16 d0,d0,#1
+	itblock 4 \cond
+	vcvt\cond\s16\f32 s0,s0,#1
+	vcvt\cond\u16\f32 s0,s0,#1
+	vcvt\cond\s16\f64 d0,d0,#1
+	vcvt\cond\u16\f64 d0,d0,#1
+	.endm
+
+	cvti
+	cvti eq
+
+	.macro multi op cond="" n="" ia="ia" db="db"
+	itblock 4 \cond
+	\op\n\cond r0,{s3-s6}
+	\op\ia\cond r0,{s3-s6}
+	\op\ia\cond r0!,{s3-s6}
+	\op\db\cond r0!,{s3-s6}
+	itblock 4 \cond
+	\op\n\cond r0,{d3-d6}
+	\op\ia\cond r0,{d3-d6}
+	\op\ia\cond r0!,{d3-d6}
+	\op\db\cond r0!,{d3-d6}
+	.endm
+
+	multi vldm
+	multi vldm eq
+	multi vstm
+	multi vstm eq
+
+	.macro single op cond=""
+	itblock 2 \cond
+	\op\cond s0,[r0,#4]
+	\op\cond d0,[r0,#4]
+	.endm
+
+	single vldr
+	single vldr eq
+	single vstr
+	single vstr eq
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.d b/gas/testsuite/gas/arm/vfp-neon-syntax.d
new file mode 100644
index 000000000000..8d9743527bca
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax.d
@@ -0,0 +1,187 @@
+# name: VFP Neon-style syntax, ARM mode
+# as: -mfpu=vfp3 -I$srcdir/$subdir
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> eeb00a60 	fcpys	s0, s1
+0[0-9a-f]+ <[^>]+> eeb00b41 	fcpyd	d0, d1
+0[0-9a-f]+ <[^>]+> eeb50a00 	fconsts	s0, #80
+0[0-9a-f]+ <[^>]+> eeb70b00 	fconstd	d0, #112
+0[0-9a-f]+ <[^>]+> ee100a90 	fmrs	r0, s1
+0[0-9a-f]+ <[^>]+> ee001a10 	fmsr	s0, r1
+0[0-9a-f]+ <[^>]+> ec510a11 	fmrrs	r0, r1, {s2, s3}
+0[0-9a-f]+ <[^>]+> ec442a10 	fmsrr	{s0, s1}, r2, r4
+0[0-9a-f]+ <[^>]+> 0eb00a60 	fcpyseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb00b41 	fcpydeq	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb50a00 	fconstseq	s0, #80
+0[0-9a-f]+ <[^>]+> 0eb70b00 	fconstdeq	d0, #112
+0[0-9a-f]+ <[^>]+> 0e100a90 	fmrseq	r0, s1
+0[0-9a-f]+ <[^>]+> 0e001a10 	fmsreq	s0, r1
+0[0-9a-f]+ <[^>]+> 0c510a11 	fmrrseq	r0, r1, {s2, s3}
+0[0-9a-f]+ <[^>]+> 0c442a10 	fmsrreq	{s0, s1}, r2, r4
+0[0-9a-f]+ <[^>]+> eeb10ae0 	fsqrts	s0, s1
+0[0-9a-f]+ <[^>]+> eeb10bc1 	fsqrtd	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb10ae0 	fsqrtseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb10bc1 	fsqrtdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb00ae0 	fabss	s0, s1
+0[0-9a-f]+ <[^>]+> eeb00bc1 	fabsd	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb00ae0 	fabsseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb00bc1 	fabsdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb10a60 	fnegs	s0, s1
+0[0-9a-f]+ <[^>]+> eeb10b41 	fnegd	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb10a60 	fnegseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb10b41 	fnegdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb40a60 	fcmps	s0, s1
+0[0-9a-f]+ <[^>]+> eeb40b41 	fcmpd	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb40a60 	fcmpseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb40b41 	fcmpdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb40ae0 	fcmpes	s0, s1
+0[0-9a-f]+ <[^>]+> eeb40bc1 	fcmped	d0, d1
+0[0-9a-f]+ <[^>]+> 0eb40ae0 	fcmpeseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb40bc1 	fcmpedeq	d0, d1
+0[0-9a-f]+ <[^>]+> ee200ac1 	fnmuls	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee210b42 	fnmuld	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e200ac1 	fnmulseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e210b42 	fnmuldeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee000ac1 	fnmacs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee010b42 	fnmacd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e000ac1 	fnmacseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e010b42 	fnmacdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee100ac1 	fnmscs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee110b42 	fnmscd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e100ac1 	fnmscseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e110b42 	fnmscdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee200a81 	fmuls	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee210b02 	fmuld	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e200a81 	fmulseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e210b02 	fmuldeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee000a81 	fmacs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee010b02 	fmacd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e000a81 	fmacseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e010b02 	fmacdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee100a81 	fmscs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee110b02 	fmscd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e100a81 	fmscseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e110b02 	fmscdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee300a81 	fadds	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee310b02 	faddd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e300a81 	faddseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e310b02 	fadddeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee300ac1 	fsubs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee310b42 	fsubd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e300ac1 	fsubseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e310b42 	fsubdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee800a81 	fdivs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee810b02 	fdivd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> 0e800a81 	fdivseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> 0e810b02 	fdivdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> eeb50a40 	fcmpzs	s0
+0[0-9a-f]+ <[^>]+> eeb50b40 	fcmpzd	d0
+0[0-9a-f]+ <[^>]+> 0eb50a40 	fcmpzseq	s0
+0[0-9a-f]+ <[^>]+> 0eb50b40 	fcmpzdeq	d0
+0[0-9a-f]+ <[^>]+> eeb50ac0 	fcmpezs	s0
+0[0-9a-f]+ <[^>]+> eeb50bc0 	fcmpezd	d0
+0[0-9a-f]+ <[^>]+> 0eb50ac0 	fcmpezseq	s0
+0[0-9a-f]+ <[^>]+> 0eb50bc0 	fcmpezdeq	d0
+0[0-9a-f]+ <[^>]+> eebd0ae0 	ftosizs	s0, s1
+0[0-9a-f]+ <[^>]+> eebc0ae0 	ftouizs	s0, s1
+0[0-9a-f]+ <[^>]+> eebd0bc1 	ftosizd	s0, d1
+0[0-9a-f]+ <[^>]+> eebc0bc1 	ftouizd	s0, d1
+0[0-9a-f]+ <[^>]+> 0ebd0ae0 	ftosizseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0ebc0ae0 	ftouizseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0ebd0bc1 	ftosizdeq	s0, d1
+0[0-9a-f]+ <[^>]+> 0ebc0bc1 	ftouizdeq	s0, d1
+0[0-9a-f]+ <[^>]+> eebd0a60 	ftosis	s0, s1
+0[0-9a-f]+ <[^>]+> eebc0a60 	ftouis	s0, s1
+0[0-9a-f]+ <[^>]+> eeb80ae0 	fsitos	s0, s1
+0[0-9a-f]+ <[^>]+> eeb80a60 	fuitos	s0, s1
+0[0-9a-f]+ <[^>]+> eeb70bc1 	fcvtsd	s0, d1
+0[0-9a-f]+ <[^>]+> eeb70ae0 	fcvtds	d0, s1
+0[0-9a-f]+ <[^>]+> eebd0b41 	ftosid	s0, d1
+0[0-9a-f]+ <[^>]+> eebc0b41 	ftouid	s0, d1
+0[0-9a-f]+ <[^>]+> eeb80be0 	fsitod	d0, s1
+0[0-9a-f]+ <[^>]+> eeb80b60 	fuitod	d0, s1
+0[0-9a-f]+ <[^>]+> 0ebd0a60 	ftosiseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0ebc0a60 	ftouiseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb80ae0 	fsitoseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb80a60 	fuitoseq	s0, s1
+0[0-9a-f]+ <[^>]+> 0eb70bc1 	fcvtsdeq	s0, d1
+0[0-9a-f]+ <[^>]+> 0eb70ae0 	fcvtdseq	d0, s1
+0[0-9a-f]+ <[^>]+> 0ebd0b41 	ftosideq	s0, d1
+0[0-9a-f]+ <[^>]+> 0ebc0b41 	ftouideq	s0, d1
+0[0-9a-f]+ <[^>]+> 0eb80be0 	fsitodeq	d0, s1
+0[0-9a-f]+ <[^>]+> 0eb80b60 	fuitodeq	d0, s1
+0[0-9a-f]+ <[^>]+> eebe0aef 	ftosls	s0, #1
+0[0-9a-f]+ <[^>]+> eebf0aef 	ftouls	s0, #1
+0[0-9a-f]+ <[^>]+> eeba0aef 	fsltos	s0, #1
+0[0-9a-f]+ <[^>]+> eebb0aef 	fultos	s0, #1
+0[0-9a-f]+ <[^>]+> eebe0bef 	ftosld	d0, #1
+0[0-9a-f]+ <[^>]+> eebf0bef 	ftould	d0, #1
+0[0-9a-f]+ <[^>]+> eeba0bef 	fsltod	d0, #1
+0[0-9a-f]+ <[^>]+> eebb0bef 	fultod	d0, #1
+0[0-9a-f]+ <[^>]+> eeba0a67 	fshtos	s0, #1
+0[0-9a-f]+ <[^>]+> eebb0a67 	fuhtos	s0, #1
+0[0-9a-f]+ <[^>]+> eeba0b67 	fshtod	d0, #1
+0[0-9a-f]+ <[^>]+> eebb0b67 	fuhtod	d0, #1
+0[0-9a-f]+ <[^>]+> eebe0a67 	ftoshs	s0, #1
+0[0-9a-f]+ <[^>]+> eebf0a67 	ftouhs	s0, #1
+0[0-9a-f]+ <[^>]+> eebe0b67 	ftoshd	d0, #1
+0[0-9a-f]+ <[^>]+> eebf0b67 	ftouhd	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebe0aef 	ftoslseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebf0aef 	ftoulseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0eba0aef 	fsltoseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebb0aef 	fultoseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebe0bef 	ftosldeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebf0bef 	ftouldeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0eba0bef 	fsltodeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebb0bef 	fultodeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0eba0a67 	fshtoseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebb0a67 	fuhtoseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0eba0b67 	fshtodeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebb0b67 	fuhtodeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebe0a67 	ftoshseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebf0a67 	ftouhseq	s0, #1
+0[0-9a-f]+ <[^>]+> 0ebe0b67 	ftoshdeq	d0, #1
+0[0-9a-f]+ <[^>]+> 0ebf0b67 	ftouhdeq	d0, #1
+0[0-9a-f]+ <[^>]+> ecd01a04 	fldmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecd01a04 	fldmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecf01a04 	fldmias	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed701a04 	fldmdbs	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ec903b08 	vldmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec903b08 	vldmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ecb03b08 	vldmia	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed303b08 	vldmdb	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0cd01a04 	fldmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0cd01a04 	fldmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0cf01a04 	fldmiaseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0d701a04 	fldmdbseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0c903b08 	vldmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0c903b08 	vldmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0cb03b08 	vldmiaeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0d303b08 	vldmdbeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ecc01a04 	fstmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecc01a04 	fstmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ece01a04 	fstmias	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed601a04 	fstmdbs	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ec803b08 	vstmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec803b08 	vstmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> eca03b08 	vstmia	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed203b08 	vstmdb	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0cc01a04 	fstmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0cc01a04 	fstmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0ce01a04 	fstmiaseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0d601a04 	fstmdbseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> 0c803b08 	vstmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0c803b08 	vstmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0ca03b08 	vstmiaeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> 0d203b08 	vstmdbeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed900a01 	flds	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed900b01 	vldr	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> 0d900a01 	fldseq	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> 0d900b01 	vldreq	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed800a01 	fsts	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed800b01 	vstr	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> 0d800a01 	fstseq	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> 0d800b01 	vstreq	d0, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.s b/gas/testsuite/gas/arm/vfp-neon-syntax.s
new file mode 100644
index 000000000000..7c0bc633ed10
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax.s
@@ -0,0 +1,2 @@
+	.arm
+	.include "vfp-neon-syntax-inc.s"
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
new file mode 100644
index 000000000000..5c0223528583
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
@@ -0,0 +1,219 @@
+# name: VFP Neon-style syntax, Thumb mode
+# as: -mfpu=vfp3 -I$srcdir/$subdir
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> eeb0 0a60 	fcpys	s0, s1
+0[0-9a-f]+ <[^>]+> eeb0 0b41 	fcpyd	d0, d1
+0[0-9a-f]+ <[^>]+> eeb5 0a00 	fconsts	s0, #80
+0[0-9a-f]+ <[^>]+> eeb7 0b00 	fconstd	d0, #112
+0[0-9a-f]+ <[^>]+> ee10 0a90 	fmrs	r0, s1
+0[0-9a-f]+ <[^>]+> ee00 1a10 	fmsr	s0, r1
+0[0-9a-f]+ <[^>]+> ec51 0a11 	fmrrs	r0, r1, {s2, s3}
+0[0-9a-f]+ <[^>]+> ec44 2a10 	fmsrr	{s0, s1}, r2, r4
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eeb0 0a60 	fcpyseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb0 0b41 	fcpydeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb5 0a00 	fconstseq	s0, #80
+0[0-9a-f]+ <[^>]+> eeb7 0b00 	fconstdeq	d0, #112
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ee10 0a90 	fmrseq	r0, s1
+0[0-9a-f]+ <[^>]+> ee00 1a10 	fmsreq	s0, r1
+0[0-9a-f]+ <[^>]+> ec51 0a11 	fmrrseq	r0, r1, {s2, s3}
+0[0-9a-f]+ <[^>]+> ec44 2a10 	fmsrreq	{s0, s1}, r2, r4
+0[0-9a-f]+ <[^>]+> eeb1 0ae0 	fsqrts	s0, s1
+0[0-9a-f]+ <[^>]+> eeb1 0bc1 	fsqrtd	d0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb1 0ae0 	fsqrtseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb1 0bc1 	fsqrtdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb0 0ae0 	fabss	s0, s1
+0[0-9a-f]+ <[^>]+> eeb0 0bc1 	fabsd	d0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb0 0ae0 	fabsseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb0 0bc1 	fabsdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb1 0a60 	fnegs	s0, s1
+0[0-9a-f]+ <[^>]+> eeb1 0b41 	fnegd	d0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb1 0a60 	fnegseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb1 0b41 	fnegdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb4 0a60 	fcmps	s0, s1
+0[0-9a-f]+ <[^>]+> eeb4 0b41 	fcmpd	d0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb4 0a60 	fcmpseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb4 0b41 	fcmpdeq	d0, d1
+0[0-9a-f]+ <[^>]+> eeb4 0ae0 	fcmpes	s0, s1
+0[0-9a-f]+ <[^>]+> eeb4 0bc1 	fcmped	d0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb4 0ae0 	fcmpeseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb4 0bc1 	fcmpedeq	d0, d1
+0[0-9a-f]+ <[^>]+> ee20 0ac1 	fnmuls	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee21 0b42 	fnmuld	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee20 0ac1 	fnmulseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee21 0b42 	fnmuldeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee00 0ac1 	fnmacs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee01 0b42 	fnmacd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee00 0ac1 	fnmacseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee01 0b42 	fnmacdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee10 0ac1 	fnmscs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee11 0b42 	fnmscd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee10 0ac1 	fnmscseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee11 0b42 	fnmscdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee20 0a81 	fmuls	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee21 0b02 	fmuld	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee20 0a81 	fmulseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee21 0b02 	fmuldeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee00 0a81 	fmacs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee01 0b02 	fmacd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee00 0a81 	fmacseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee01 0b02 	fmacdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee10 0a81 	fmscs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee11 0b02 	fmscd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee10 0a81 	fmscseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee11 0b02 	fmscdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee30 0a81 	fadds	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee31 0b02 	faddd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee30 0a81 	faddseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee31 0b02 	fadddeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee30 0ac1 	fsubs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee31 0b42 	fsubd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee30 0ac1 	fsubseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee31 0b42 	fsubdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> ee80 0a81 	fdivs	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee81 0b02 	fdivd	d0, d1, d2
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ee80 0a81 	fdivseq	s0, s1, s2
+0[0-9a-f]+ <[^>]+> ee81 0b02 	fdivdeq	d0, d1, d2
+0[0-9a-f]+ <[^>]+> eeb5 0a40 	fcmpzs	s0
+0[0-9a-f]+ <[^>]+> eeb5 0b40 	fcmpzd	d0
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb5 0a40 	fcmpzseq	s0
+0[0-9a-f]+ <[^>]+> eeb5 0b40 	fcmpzdeq	d0
+0[0-9a-f]+ <[^>]+> eeb5 0ac0 	fcmpezs	s0
+0[0-9a-f]+ <[^>]+> eeb5 0bc0 	fcmpezd	d0
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb5 0ac0 	fcmpezseq	s0
+0[0-9a-f]+ <[^>]+> eeb5 0bc0 	fcmpezdeq	d0
+0[0-9a-f]+ <[^>]+> eebd 0ae0 	ftosizs	s0, s1
+0[0-9a-f]+ <[^>]+> eebc 0ae0 	ftouizs	s0, s1
+0[0-9a-f]+ <[^>]+> eebd 0bc1 	ftosizd	s0, d1
+0[0-9a-f]+ <[^>]+> eebc 0bc1 	ftouizd	s0, d1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eebd 0ae0 	ftosizseq	s0, s1
+0[0-9a-f]+ <[^>]+> eebc 0ae0 	ftouizseq	s0, s1
+0[0-9a-f]+ <[^>]+> eebd 0bc1 	ftosizdeq	s0, d1
+0[0-9a-f]+ <[^>]+> eebc 0bc1 	ftouizdeq	s0, d1
+0[0-9a-f]+ <[^>]+> eebd 0a60 	ftosis	s0, s1
+0[0-9a-f]+ <[^>]+> eebc 0a60 	ftouis	s0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0ae0 	fsitos	s0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0a60 	fuitos	s0, s1
+0[0-9a-f]+ <[^>]+> eeb7 0bc1 	fcvtsd	s0, d1
+0[0-9a-f]+ <[^>]+> eeb7 0ae0 	fcvtds	d0, s1
+0[0-9a-f]+ <[^>]+> eebd 0b41 	ftosid	s0, d1
+0[0-9a-f]+ <[^>]+> eebc 0b41 	ftouid	s0, d1
+0[0-9a-f]+ <[^>]+> eeb8 0be0 	fsitod	d0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0b60 	fuitod	d0, s1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eebd 0a60 	ftosiseq	s0, s1
+0[0-9a-f]+ <[^>]+> eebc 0a60 	ftouiseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0ae0 	fsitoseq	s0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0a60 	fuitoseq	s0, s1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eeb7 0bc1 	fcvtsdeq	s0, d1
+0[0-9a-f]+ <[^>]+> eeb7 0ae0 	fcvtdseq	d0, s1
+0[0-9a-f]+ <[^>]+> eebd 0b41 	ftosideq	s0, d1
+0[0-9a-f]+ <[^>]+> eebc 0b41 	ftouideq	s0, d1
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> eeb8 0be0 	fsitodeq	d0, s1
+0[0-9a-f]+ <[^>]+> eeb8 0b60 	fuitodeq	d0, s1
+0[0-9a-f]+ <[^>]+> eebe 0aef 	ftosls	s0, #1
+0[0-9a-f]+ <[^>]+> eebf 0aef 	ftouls	s0, #1
+0[0-9a-f]+ <[^>]+> eeba 0aef 	fsltos	s0, #1
+0[0-9a-f]+ <[^>]+> eebb 0aef 	fultos	s0, #1
+0[0-9a-f]+ <[^>]+> eebe 0bef 	ftosld	d0, #1
+0[0-9a-f]+ <[^>]+> eebf 0bef 	ftould	d0, #1
+0[0-9a-f]+ <[^>]+> eeba 0bef 	fsltod	d0, #1
+0[0-9a-f]+ <[^>]+> eebb 0bef 	fultod	d0, #1
+0[0-9a-f]+ <[^>]+> eeba 0a67 	fshtos	s0, #1
+0[0-9a-f]+ <[^>]+> eebb 0a67 	fuhtos	s0, #1
+0[0-9a-f]+ <[^>]+> eeba 0b67 	fshtod	d0, #1
+0[0-9a-f]+ <[^>]+> eebb 0b67 	fuhtod	d0, #1
+0[0-9a-f]+ <[^>]+> eebe 0a67 	ftoshs	s0, #1
+0[0-9a-f]+ <[^>]+> eebf 0a67 	ftouhs	s0, #1
+0[0-9a-f]+ <[^>]+> eebe 0b67 	ftoshd	d0, #1
+0[0-9a-f]+ <[^>]+> eebf 0b67 	ftouhd	d0, #1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eebe 0aef 	ftoslseq	s0, #1
+0[0-9a-f]+ <[^>]+> eebf 0aef 	ftoulseq	s0, #1
+0[0-9a-f]+ <[^>]+> eeba 0aef 	fsltoseq	s0, #1
+0[0-9a-f]+ <[^>]+> eebb 0aef 	fultoseq	s0, #1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eebe 0bef 	ftosldeq	d0, #1
+0[0-9a-f]+ <[^>]+> eebf 0bef 	ftouldeq	d0, #1
+0[0-9a-f]+ <[^>]+> eeba 0bef 	fsltodeq	d0, #1
+0[0-9a-f]+ <[^>]+> eebb 0bef 	fultodeq	d0, #1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eeba 0a67 	fshtoseq	s0, #1
+0[0-9a-f]+ <[^>]+> eebb 0a67 	fuhtoseq	s0, #1
+0[0-9a-f]+ <[^>]+> eeba 0b67 	fshtodeq	d0, #1
+0[0-9a-f]+ <[^>]+> eebb 0b67 	fuhtodeq	d0, #1
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> eebe 0a67 	ftoshseq	s0, #1
+0[0-9a-f]+ <[^>]+> eebf 0a67 	ftouhseq	s0, #1
+0[0-9a-f]+ <[^>]+> eebe 0b67 	ftoshdeq	d0, #1
+0[0-9a-f]+ <[^>]+> eebf 0b67 	ftouhdeq	d0, #1
+0[0-9a-f]+ <[^>]+> ecd0 1a04 	fldmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecd0 1a04 	fldmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecf0 1a04 	fldmias	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed70 1a04 	fldmdbs	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ec90 3b08 	vldmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec90 3b08 	vldmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ecb0 3b08 	vldmia	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed30 3b08 	vldmdb	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ecd0 1a04 	fldmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecd0 1a04 	fldmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecf0 1a04 	fldmiaseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed70 1a04 	fldmdbseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ec90 3b08 	vldmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec90 3b08 	vldmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ecb0 3b08 	vldmiaeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed30 3b08 	vldmdbeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ecc0 1a04 	fstmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecc0 1a04 	fstmias	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ece0 1a04 	fstmias	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed60 1a04 	fstmdbs	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ec80 3b08 	vstmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec80 3b08 	vstmia	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> eca0 3b08 	vstmia	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed20 3b08 	vstmdb	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ecc0 1a04 	fstmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ecc0 1a04 	fstmiaseq	r0, {s3-s6}
+0[0-9a-f]+ <[^>]+> ece0 1a04 	fstmiaseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> ed60 1a04 	fstmdbseq	r0!, {s3-s6}
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> ec80 3b08 	vstmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> ec80 3b08 	vstmiaeq	r0, {d3-d6}
+0[0-9a-f]+ <[^>]+> eca0 3b08 	vstmiaeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed20 3b08 	vstmdbeq	r0!, {d3-d6}
+0[0-9a-f]+ <[^>]+> ed90 0a01 	flds	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed90 0b01 	vldr	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ed90 0a01 	fldseq	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed90 0b01 	vldreq	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed80 0a01 	fsts	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed80 0b01 	vstr	d0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> ed80 0a01 	fstseq	s0, \[r0, #4\]
+0[0-9a-f]+ <[^>]+> ed80 0b01 	vstreq	d0, \[r0, #4\]
diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s
new file mode 100644
index 000000000000..00f78d01cef7
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s
@@ -0,0 +1,2 @@
+	.thumb
+	.include "vfp-neon-syntax-inc.s"
diff --git a/gas/testsuite/gas/arm/vfp1.d b/gas/testsuite/gas/arm/vfp1.d
index 672b23de31d5..3894909539bb 100644
--- a/gas/testsuite/gas/arm/vfp1.d
+++ b/gas/testsuite/gas/arm/vfp1.d
@@ -24,20 +24,20 @@ Disassembly of section .text:
 0+038 <[^>]*> ee100b40 	fnmscd	d0, d0, d0
 0+03c <[^>]*> ee200b40 	fnmuld	d0, d0, d0
 0+040 <[^>]*> ee300b40 	fsubd	d0, d0, d0
-0+044 <[^>]*> ed900b00 	fldd	d0, \[r0\]
-0+048 <[^>]*> ed800b00 	fstd	d0, \[r0\]
-0+04c <[^>]*> ec900b02 	fldmiad	r0, {d0}
-0+050 <[^>]*> ec900b02 	fldmiad	r0, {d0}
-0+054 <[^>]*> ecb00b02 	fldmiad	r0!, {d0}
-0+058 <[^>]*> ecb00b02 	fldmiad	r0!, {d0}
-0+05c <[^>]*> ed300b02 	fldmdbd	r0!, {d0}
-0+060 <[^>]*> ed300b02 	fldmdbd	r0!, {d0}
-0+064 <[^>]*> ec800b02 	fstmiad	r0, {d0}
-0+068 <[^>]*> ec800b02 	fstmiad	r0, {d0}
-0+06c <[^>]*> eca00b02 	fstmiad	r0!, {d0}
-0+070 <[^>]*> eca00b02 	fstmiad	r0!, {d0}
-0+074 <[^>]*> ed200b02 	fstmdbd	r0!, {d0}
-0+078 <[^>]*> ed200b02 	fstmdbd	r0!, {d0}
+0+044 <[^>]*> ed900b00 	vldr	d0, \[r0\]
+0+048 <[^>]*> ed800b00 	vstr	d0, \[r0\]
+0+04c <[^>]*> ec900b02 	vldmia	r0, {d0}
+0+050 <[^>]*> ec900b02 	vldmia	r0, {d0}
+0+054 <[^>]*> ecb00b02 	vldmia	r0!, {d0}
+0+058 <[^>]*> ecb00b02 	vldmia	r0!, {d0}
+0+05c <[^>]*> ed300b02 	vldmdb	r0!, {d0}
+0+060 <[^>]*> ed300b02 	vldmdb	r0!, {d0}
+0+064 <[^>]*> ec800b02 	vstmia	r0, {d0}
+0+068 <[^>]*> ec800b02 	vstmia	r0, {d0}
+0+06c <[^>]*> eca00b02 	vstmia	r0!, {d0}
+0+070 <[^>]*> eca00b02 	vstmia	r0!, {d0}
+0+074 <[^>]*> ed200b02 	vstmdb	r0!, {d0}
+0+078 <[^>]*> ed200b02 	vstmdb	r0!, {d0}
 0+07c <[^>]*> eeb80bc0 	fsitod	d0, s0
 0+080 <[^>]*> eeb80b40 	fuitod	d0, s0
 0+084 <[^>]*> eebd0b40 	ftosid	s0, d0
@@ -46,10 +46,10 @@ Disassembly of section .text:
 0+090 <[^>]*> eebc0bc0 	ftouizd	s0, d0
 0+094 <[^>]*> eeb70ac0 	fcvtds	d0, s0
 0+098 <[^>]*> eeb70bc0 	fcvtsd	s0, d0
-0+09c <[^>]*> ee300b10 	fmrdh	r0, d0
-0+0a0 <[^>]*> ee100b10 	fmrdl	r0, d0
-0+0a4 <[^>]*> ee200b10 	fmdhr	d0, r0
-0+0a8 <[^>]*> ee000b10 	fmdlr	d0, r0
+0+09c <[^>]*> ee300b10 	vmov\.32	r0, d0\[1\]
+0+0a0 <[^>]*> ee100b10 	vmov\.32	r0, d0\[0\]
+0+0a4 <[^>]*> ee200b10 	vmov\.32	d0\[1\], r0
+0+0a8 <[^>]*> ee000b10 	vmov\.32	d0\[0\], r0
 0+0ac <[^>]*> eeb51b40 	fcmpzd	d1
 0+0b0 <[^>]*> eeb52b40 	fcmpzd	d2
 0+0b4 <[^>]*> eeb5fb40 	fcmpzd	d15
@@ -89,46 +89,46 @@ Disassembly of section .text:
 0+13c <[^>]*> eeb70bc1 	fcvtsd	s0, d1
 0+140 <[^>]*> eeb70bc2 	fcvtsd	s0, d2
 0+144 <[^>]*> eeb70bcf 	fcvtsd	s0, d15
-0+148 <[^>]*> ee301b10 	fmrdh	r1, d0
-0+14c <[^>]*> ee30eb10 	fmrdh	lr, d0
-0+150 <[^>]*> ee310b10 	fmrdh	r0, d1
-0+154 <[^>]*> ee320b10 	fmrdh	r0, d2
-0+158 <[^>]*> ee3f0b10 	fmrdh	r0, d15
-0+15c <[^>]*> ee101b10 	fmrdl	r1, d0
-0+160 <[^>]*> ee10eb10 	fmrdl	lr, d0
-0+164 <[^>]*> ee110b10 	fmrdl	r0, d1
-0+168 <[^>]*> ee120b10 	fmrdl	r0, d2
-0+16c <[^>]*> ee1f0b10 	fmrdl	r0, d15
-0+170 <[^>]*> ee201b10 	fmdhr	d0, r1
-0+174 <[^>]*> ee20eb10 	fmdhr	d0, lr
-0+178 <[^>]*> ee210b10 	fmdhr	d1, r0
-0+17c <[^>]*> ee220b10 	fmdhr	d2, r0
-0+180 <[^>]*> ee2f0b10 	fmdhr	d15, r0
-0+184 <[^>]*> ee001b10 	fmdlr	d0, r1
-0+188 <[^>]*> ee00eb10 	fmdlr	d0, lr
-0+18c <[^>]*> ee010b10 	fmdlr	d1, r0
-0+190 <[^>]*> ee020b10 	fmdlr	d2, r0
-0+194 <[^>]*> ee0f0b10 	fmdlr	d15, r0
-0+198 <[^>]*> ed910b00 	fldd	d0, \[r1\]
-0+19c <[^>]*> ed9e0b00 	fldd	d0, \[lr\]
-0+1a0 <[^>]*> ed900b00 	fldd	d0, \[r0\]
-0+1a4 <[^>]*> ed900bff 	fldd	d0, \[r0, #1020\]
-0+1a8 <[^>]*> ed100bff 	fldd	d0, \[r0, #-1020\]
-0+1ac <[^>]*> ed901b00 	fldd	d1, \[r0\]
-0+1b0 <[^>]*> ed902b00 	fldd	d2, \[r0\]
-0+1b4 <[^>]*> ed90fb00 	fldd	d15, \[r0\]
-0+1b8 <[^>]*> ed8ccbc9 	fstd	d12, \[ip, #804\]
-0+1bc <[^>]*> ec901b02 	fldmiad	r0, {d1}
-0+1c0 <[^>]*> ec902b02 	fldmiad	r0, {d2}
-0+1c4 <[^>]*> ec90fb02 	fldmiad	r0, {d15}
-0+1c8 <[^>]*> ec900b04 	fldmiad	r0, {d0-d1}
-0+1cc <[^>]*> ec900b06 	fldmiad	r0, {d0-d2}
-0+1d0 <[^>]*> ec900b20 	fldmiad	r0, {d0-d15}
-0+1d4 <[^>]*> ec901b1e 	fldmiad	r0, {d1-d15}
-0+1d8 <[^>]*> ec902b1c 	fldmiad	r0, {d2-d15}
-0+1dc <[^>]*> ec90eb04 	fldmiad	r0, {d14-d15}
-0+1e0 <[^>]*> ec910b02 	fldmiad	r1, {d0}
-0+1e4 <[^>]*> ec9e0b02 	fldmiad	lr, {d0}
+0+148 <[^>]*> ee301b10 	vmov\.32	r1, d0\[1\]
+0+14c <[^>]*> ee30eb10 	vmov\.32	lr, d0\[1\]
+0+150 <[^>]*> ee310b10 	vmov\.32	r0, d1\[1\]
+0+154 <[^>]*> ee320b10 	vmov\.32	r0, d2\[1\]
+0+158 <[^>]*> ee3f0b10 	vmov\.32	r0, d15\[1\]
+0+15c <[^>]*> ee101b10 	vmov\.32	r1, d0\[0\]
+0+160 <[^>]*> ee10eb10 	vmov\.32	lr, d0\[0\]
+0+164 <[^>]*> ee110b10 	vmov\.32	r0, d1\[0\]
+0+168 <[^>]*> ee120b10 	vmov\.32	r0, d2\[0\]
+0+16c <[^>]*> ee1f0b10 	vmov\.32	r0, d15\[0\]
+0+170 <[^>]*> ee201b10 	vmov\.32	d0\[1\], r1
+0+174 <[^>]*> ee20eb10 	vmov\.32	d0\[1\], lr
+0+178 <[^>]*> ee210b10 	vmov\.32	d1\[1\], r0
+0+17c <[^>]*> ee220b10 	vmov\.32	d2\[1\], r0
+0+180 <[^>]*> ee2f0b10 	vmov\.32	d15\[1\], r0
+0+184 <[^>]*> ee001b10 	vmov\.32	d0\[0\], r1
+0+188 <[^>]*> ee00eb10 	vmov\.32	d0\[0\], lr
+0+18c <[^>]*> ee010b10 	vmov\.32	d1\[0\], r0
+0+190 <[^>]*> ee020b10 	vmov\.32	d2\[0\], r0
+0+194 <[^>]*> ee0f0b10 	vmov\.32	d15\[0\], r0
+0+198 <[^>]*> ed910b00 	vldr	d0, \[r1\]
+0+19c <[^>]*> ed9e0b00 	vldr	d0, \[lr\]
+0+1a0 <[^>]*> ed900b00 	vldr	d0, \[r0\]
+0+1a4 <[^>]*> ed900bff 	vldr	d0, \[r0, #1020\]
+0+1a8 <[^>]*> ed100bff 	vldr	d0, \[r0, #-1020\]
+0+1ac <[^>]*> ed901b00 	vldr	d1, \[r0\]
+0+1b0 <[^>]*> ed902b00 	vldr	d2, \[r0\]
+0+1b4 <[^>]*> ed90fb00 	vldr	d15, \[r0\]
+0+1b8 <[^>]*> ed8ccbc9 	vstr	d12, \[ip, #804\]
+0+1bc <[^>]*> ec901b02 	vldmia	r0, {d1}
+0+1c0 <[^>]*> ec902b02 	vldmia	r0, {d2}
+0+1c4 <[^>]*> ec90fb02 	vldmia	r0, {d15}
+0+1c8 <[^>]*> ec900b04 	vldmia	r0, {d0-d1}
+0+1cc <[^>]*> ec900b06 	vldmia	r0, {d0-d2}
+0+1d0 <[^>]*> ec900b20 	vldmia	r0, {d0-d15}
+0+1d4 <[^>]*> ec901b1e 	vldmia	r0, {d1-d15}
+0+1d8 <[^>]*> ec902b1c 	vldmia	r0, {d2-d15}
+0+1dc <[^>]*> ec90eb04 	vldmia	r0, {d14-d15}
+0+1e0 <[^>]*> ec910b02 	vldmia	r1, {d0}
+0+1e4 <[^>]*> ec9e0b02 	vldmia	lr, {d0}
 0+1e8 <[^>]*> eeb50b40 	fcmpzd	d0
 0+1ec <[^>]*> eeb51b40 	fcmpzd	d1
 0+1f0 <[^>]*> eeb52b40 	fcmpzd	d2
@@ -162,20 +162,20 @@ Disassembly of section .text:
 0+260 <[^>]*> 0e167b4b 	fnmscdeq	d7, d6, d11
 0+264 <[^>]*> 0e245b4c 	fnmuldeq	d5, d4, d12
 0+268 <[^>]*> 0e3d3b4e 	fsubdeq	d3, d13, d14
-0+26c <[^>]*> 0d952b00 	flddeq	d2, \[r5\]
-0+270 <[^>]*> 0d8c1b00 	fstdeq	d1, \[ip\]
-0+274 <[^>]*> 0c911b02 	fldmiadeq	r1, {d1}
-0+278 <[^>]*> 0c922b02 	fldmiadeq	r2, {d2}
-0+27c <[^>]*> 0cb33b02 	fldmiadeq	r3!, {d3}
-0+280 <[^>]*> 0cb44b02 	fldmiadeq	r4!, {d4}
-0+284 <[^>]*> 0d355b02 	fldmdbdeq	r5!, {d5}
-0+288 <[^>]*> 0d366b02 	fldmdbdeq	r6!, {d6}
-0+28c <[^>]*> 0c87fb02 	fstmiadeq	r7, {d15}
-0+290 <[^>]*> 0c88eb02 	fstmiadeq	r8, {d14}
-0+294 <[^>]*> 0ca9db02 	fstmiadeq	r9!, {d13}
-0+298 <[^>]*> 0caacb02 	fstmiadeq	sl!, {d12}
-0+29c <[^>]*> 0d2bbb02 	fstmdbdeq	fp!, {d11}
-0+2a0 <[^>]*> 0d2cab02 	fstmdbdeq	ip!, {d10}
+0+26c <[^>]*> 0d952b00 	vldreq	d2, \[r5\]
+0+270 <[^>]*> 0d8c1b00 	vstreq	d1, \[ip\]
+0+274 <[^>]*> 0c911b02 	vldmiaeq	r1, {d1}
+0+278 <[^>]*> 0c922b02 	vldmiaeq	r2, {d2}
+0+27c <[^>]*> 0cb33b02 	vldmiaeq	r3!, {d3}
+0+280 <[^>]*> 0cb44b02 	vldmiaeq	r4!, {d4}
+0+284 <[^>]*> 0d355b02 	vldmdbeq	r5!, {d5}
+0+288 <[^>]*> 0d366b02 	vldmdbeq	r6!, {d6}
+0+28c <[^>]*> 0c87fb02 	vstmiaeq	r7, {d15}
+0+290 <[^>]*> 0c88eb02 	vstmiaeq	r8, {d14}
+0+294 <[^>]*> 0ca9db02 	vstmiaeq	r9!, {d13}
+0+298 <[^>]*> 0caacb02 	vstmiaeq	sl!, {d12}
+0+29c <[^>]*> 0d2bbb02 	vstmdbeq	fp!, {d11}
+0+2a0 <[^>]*> 0d2cab02 	vstmdbeq	ip!, {d10}
 0+2a4 <[^>]*> 0eb8fbe0 	fsitodeq	d15, s1
 0+2a8 <[^>]*> 0eb81b6f 	fuitodeq	d1, s31
 0+2ac <[^>]*> 0efd0b4f 	ftosideq	s1, d15
@@ -184,10 +184,10 @@ Disassembly of section .text:
 0+2b8 <[^>]*> 0efc5bc3 	ftouizdeq	s11, d3
 0+2bc <[^>]*> 0eb71ac5 	fcvtdseq	d1, s10
 0+2c0 <[^>]*> 0ef75bc1 	fcvtsdeq	s11, d1
-0+2c4 <[^>]*> 0e318b10 	fmrdheq	r8, d1
-0+2c8 <[^>]*> 0e1f7b10 	fmrdleq	r7, d15
-0+2cc <[^>]*> 0e21fb10 	fmdhreq	d1, pc
-0+2d0 <[^>]*> 0e0f1b10 	fmdlreq	d15, r1
+0+2c4 <[^>]*> 0e318b10 	vmoveq\.32	r8, d1\[1\]
+0+2c8 <[^>]*> 0e1f7b10 	vmoveq\.32	r7, d15\[0\]
+0+2cc <[^>]*> 0e21fb10 	vmoveq\.32	d1\[1\], pc
+0+2d0 <[^>]*> 0e0f1b10 	vmoveq\.32	d15\[0\], r1
 0+2d4 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
 0+2d8 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
 0+2dc <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d
index 22c4fd6f01dc..3bf1f9a9d74b 100644
--- a/gas/testsuite/gas/arm/vfp1_t2.d
+++ b/gas/testsuite/gas/arm/vfp1_t2.d
@@ -24,20 +24,20 @@ Disassembly of section .text:
 0+038 <[^>]*> ee10 0b40 	fnmscd	d0, d0, d0
 0+03c <[^>]*> ee20 0b40 	fnmuld	d0, d0, d0
 0+040 <[^>]*> ee30 0b40 	fsubd	d0, d0, d0
-0+044 <[^>]*> ed90 0b00 	fldd	d0, \[r0\]
-0+048 <[^>]*> ed80 0b00 	fstd	d0, \[r0\]
-0+04c <[^>]*> ec90 0b02 	fldmiad	r0, {d0}
-0+050 <[^>]*> ec90 0b02 	fldmiad	r0, {d0}
-0+054 <[^>]*> ecb0 0b02 	fldmiad	r0!, {d0}
-0+058 <[^>]*> ecb0 0b02 	fldmiad	r0!, {d0}
-0+05c <[^>]*> ed30 0b02 	fldmdbd	r0!, {d0}
-0+060 <[^>]*> ed30 0b02 	fldmdbd	r0!, {d0}
-0+064 <[^>]*> ec80 0b02 	fstmiad	r0, {d0}
-0+068 <[^>]*> ec80 0b02 	fstmiad	r0, {d0}
-0+06c <[^>]*> eca0 0b02 	fstmiad	r0!, {d0}
-0+070 <[^>]*> eca0 0b02 	fstmiad	r0!, {d0}
-0+074 <[^>]*> ed20 0b02 	fstmdbd	r0!, {d0}
-0+078 <[^>]*> ed20 0b02 	fstmdbd	r0!, {d0}
+0+044 <[^>]*> ed90 0b00 	vldr	d0, \[r0\]
+0+048 <[^>]*> ed80 0b00 	vstr	d0, \[r0\]
+0+04c <[^>]*> ec90 0b02 	vldmia	r0, {d0}
+0+050 <[^>]*> ec90 0b02 	vldmia	r0, {d0}
+0+054 <[^>]*> ecb0 0b02 	vldmia	r0!, {d0}
+0+058 <[^>]*> ecb0 0b02 	vldmia	r0!, {d0}
+0+05c <[^>]*> ed30 0b02 	vldmdb	r0!, {d0}
+0+060 <[^>]*> ed30 0b02 	vldmdb	r0!, {d0}
+0+064 <[^>]*> ec80 0b02 	vstmia	r0, {d0}
+0+068 <[^>]*> ec80 0b02 	vstmia	r0, {d0}
+0+06c <[^>]*> eca0 0b02 	vstmia	r0!, {d0}
+0+070 <[^>]*> eca0 0b02 	vstmia	r0!, {d0}
+0+074 <[^>]*> ed20 0b02 	vstmdb	r0!, {d0}
+0+078 <[^>]*> ed20 0b02 	vstmdb	r0!, {d0}
 0+07c <[^>]*> eeb8 0bc0 	fsitod	d0, s0
 0+080 <[^>]*> eeb8 0b40 	fuitod	d0, s0
 0+084 <[^>]*> eebd 0b40 	ftosid	s0, d0
@@ -46,10 +46,10 @@ Disassembly of section .text:
 0+090 <[^>]*> eebc 0bc0 	ftouizd	s0, d0
 0+094 <[^>]*> eeb7 0ac0 	fcvtds	d0, s0
 0+098 <[^>]*> eeb7 0bc0 	fcvtsd	s0, d0
-0+09c <[^>]*> ee30 0b10 	fmrdh	r0, d0
-0+0a0 <[^>]*> ee10 0b10 	fmrdl	r0, d0
-0+0a4 <[^>]*> ee20 0b10 	fmdhr	d0, r0
-0+0a8 <[^>]*> ee00 0b10 	fmdlr	d0, r0
+0+09c <[^>]*> ee30 0b10 	vmov\.32	r0, d0\[1\]
+0+0a0 <[^>]*> ee10 0b10 	vmov\.32	r0, d0\[0\]
+0+0a4 <[^>]*> ee20 0b10 	vmov\.32	d0\[1\], r0
+0+0a8 <[^>]*> ee00 0b10 	vmov\.32	d0\[0\], r0
 0+0ac <[^>]*> eeb5 1b40 	fcmpzd	d1
 0+0b0 <[^>]*> eeb5 2b40 	fcmpzd	d2
 0+0b4 <[^>]*> eeb5 fb40 	fcmpzd	d15
@@ -89,46 +89,46 @@ Disassembly of section .text:
 0+13c <[^>]*> eeb7 0bc1 	fcvtsd	s0, d1
 0+140 <[^>]*> eeb7 0bc2 	fcvtsd	s0, d2
 0+144 <[^>]*> eeb7 0bcf 	fcvtsd	s0, d15
-0+148 <[^>]*> ee30 1b10 	fmrdh	r1, d0
-0+14c <[^>]*> ee30 eb10 	fmrdh	lr, d0
-0+150 <[^>]*> ee31 0b10 	fmrdh	r0, d1
-0+154 <[^>]*> ee32 0b10 	fmrdh	r0, d2
-0+158 <[^>]*> ee3f 0b10 	fmrdh	r0, d15
-0+15c <[^>]*> ee10 1b10 	fmrdl	r1, d0
-0+160 <[^>]*> ee10 eb10 	fmrdl	lr, d0
-0+164 <[^>]*> ee11 0b10 	fmrdl	r0, d1
-0+168 <[^>]*> ee12 0b10 	fmrdl	r0, d2
-0+16c <[^>]*> ee1f 0b10 	fmrdl	r0, d15
-0+170 <[^>]*> ee20 1b10 	fmdhr	d0, r1
-0+174 <[^>]*> ee20 eb10 	fmdhr	d0, lr
-0+178 <[^>]*> ee21 0b10 	fmdhr	d1, r0
-0+17c <[^>]*> ee22 0b10 	fmdhr	d2, r0
-0+180 <[^>]*> ee2f 0b10 	fmdhr	d15, r0
-0+184 <[^>]*> ee00 1b10 	fmdlr	d0, r1
-0+188 <[^>]*> ee00 eb10 	fmdlr	d0, lr
-0+18c <[^>]*> ee01 0b10 	fmdlr	d1, r0
-0+190 <[^>]*> ee02 0b10 	fmdlr	d2, r0
-0+194 <[^>]*> ee0f 0b10 	fmdlr	d15, r0
-0+198 <[^>]*> ed91 0b00 	fldd	d0, \[r1\]
-0+19c <[^>]*> ed9e 0b00 	fldd	d0, \[lr\]
-0+1a0 <[^>]*> ed90 0b00 	fldd	d0, \[r0\]
-0+1a4 <[^>]*> ed90 0bff 	fldd	d0, \[r0, #1020\]
-0+1a8 <[^>]*> ed10 0bff 	fldd	d0, \[r0, #-1020\]
-0+1ac <[^>]*> ed90 1b00 	fldd	d1, \[r0\]
-0+1b0 <[^>]*> ed90 2b00 	fldd	d2, \[r0\]
-0+1b4 <[^>]*> ed90 fb00 	fldd	d15, \[r0\]
-0+1b8 <[^>]*> ed8c cbc9 	fstd	d12, \[ip, #804\]
-0+1bc <[^>]*> ec90 1b02 	fldmiad	r0, {d1}
-0+1c0 <[^>]*> ec90 2b02 	fldmiad	r0, {d2}
-0+1c4 <[^>]*> ec90 fb02 	fldmiad	r0, {d15}
-0+1c8 <[^>]*> ec90 0b04 	fldmiad	r0, {d0-d1}
-0+1cc <[^>]*> ec90 0b06 	fldmiad	r0, {d0-d2}
-0+1d0 <[^>]*> ec90 0b20 	fldmiad	r0, {d0-d15}
-0+1d4 <[^>]*> ec90 1b1e 	fldmiad	r0, {d1-d15}
-0+1d8 <[^>]*> ec90 2b1c 	fldmiad	r0, {d2-d15}
-0+1dc <[^>]*> ec90 eb04 	fldmiad	r0, {d14-d15}
-0+1e0 <[^>]*> ec91 0b02 	fldmiad	r1, {d0}
-0+1e4 <[^>]*> ec9e 0b02 	fldmiad	lr, {d0}
+0+148 <[^>]*> ee30 1b10 	vmov\.32	r1, d0\[1\]
+0+14c <[^>]*> ee30 eb10 	vmov\.32	lr, d0\[1\]
+0+150 <[^>]*> ee31 0b10 	vmov\.32	r0, d1\[1\]
+0+154 <[^>]*> ee32 0b10 	vmov\.32	r0, d2\[1\]
+0+158 <[^>]*> ee3f 0b10 	vmov\.32	r0, d15\[1\]
+0+15c <[^>]*> ee10 1b10 	vmov\.32	r1, d0\[0\]
+0+160 <[^>]*> ee10 eb10 	vmov\.32	lr, d0\[0\]
+0+164 <[^>]*> ee11 0b10 	vmov\.32	r0, d1\[0\]
+0+168 <[^>]*> ee12 0b10 	vmov\.32	r0, d2\[0\]
+0+16c <[^>]*> ee1f 0b10 	vmov\.32	r0, d15\[0\]
+0+170 <[^>]*> ee20 1b10 	vmov\.32	d0\[1\], r1
+0+174 <[^>]*> ee20 eb10 	vmov\.32	d0\[1\], lr
+0+178 <[^>]*> ee21 0b10 	vmov\.32	d1\[1\], r0
+0+17c <[^>]*> ee22 0b10 	vmov\.32	d2\[1\], r0
+0+180 <[^>]*> ee2f 0b10 	vmov\.32	d15\[1\], r0
+0+184 <[^>]*> ee00 1b10 	vmov\.32	d0\[0\], r1
+0+188 <[^>]*> ee00 eb10 	vmov\.32	d0\[0\], lr
+0+18c <[^>]*> ee01 0b10 	vmov\.32	d1\[0\], r0
+0+190 <[^>]*> ee02 0b10 	vmov\.32	d2\[0\], r0
+0+194 <[^>]*> ee0f 0b10 	vmov\.32	d15\[0\], r0
+0+198 <[^>]*> ed91 0b00 	vldr	d0, \[r1\]
+0+19c <[^>]*> ed9e 0b00 	vldr	d0, \[lr\]
+0+1a0 <[^>]*> ed90 0b00 	vldr	d0, \[r0\]
+0+1a4 <[^>]*> ed90 0bff 	vldr	d0, \[r0, #1020\]
+0+1a8 <[^>]*> ed10 0bff 	vldr	d0, \[r0, #-1020\]
+0+1ac <[^>]*> ed90 1b00 	vldr	d1, \[r0\]
+0+1b0 <[^>]*> ed90 2b00 	vldr	d2, \[r0\]
+0+1b4 <[^>]*> ed90 fb00 	vldr	d15, \[r0\]
+0+1b8 <[^>]*> ed8c cbc9 	vstr	d12, \[ip, #804\]
+0+1bc <[^>]*> ec90 1b02 	vldmia	r0, {d1}
+0+1c0 <[^>]*> ec90 2b02 	vldmia	r0, {d2}
+0+1c4 <[^>]*> ec90 fb02 	vldmia	r0, {d15}
+0+1c8 <[^>]*> ec90 0b04 	vldmia	r0, {d0-d1}
+0+1cc <[^>]*> ec90 0b06 	vldmia	r0, {d0-d2}
+0+1d0 <[^>]*> ec90 0b20 	vldmia	r0, {d0-d15}
+0+1d4 <[^>]*> ec90 1b1e 	vldmia	r0, {d1-d15}
+0+1d8 <[^>]*> ec90 2b1c 	vldmia	r0, {d2-d15}
+0+1dc <[^>]*> ec90 eb04 	vldmia	r0, {d14-d15}
+0+1e0 <[^>]*> ec91 0b02 	vldmia	r1, {d0}
+0+1e4 <[^>]*> ec9e 0b02 	vldmia	lr, {d0}
 0+1e8 <[^>]*> eeb5 0b40 	fcmpzd	d0
 0+1ec <[^>]*> eeb5 1b40 	fcmpzd	d1
 0+1f0 <[^>]*> eeb5 2b40 	fcmpzd	d2
@@ -145,61 +145,60 @@ Disassembly of section .text:
 0+21c <[^>]*> eeb5 db40 	fcmpzd	d13
 0+220 <[^>]*> eeb5 eb40 	fcmpzd	d14
 0+224 <[^>]*> eeb5 fb40 	fcmpzd	d15
-# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
 0+228 <[^>]*> bf01      	itttt	eq
-0+22a <[^>]*> eeb4 1bcf 	fcmped(eq|)	d1, d15
-0+22e <[^>]*> eeb5 2bc0 	fcmpezd(eq|)	d2
-0+232 <[^>]*> eeb4 3b4e 	fcmpd(eq|)	d3, d14
-0+236 <[^>]*> eeb5 4b40 	fcmpzd(eq|)	d4
+0+22a <[^>]*> eeb4 1bcf 	fcmpedeq	d1, d15
+0+22e <[^>]*> eeb5 2bc0 	fcmpezdeq	d2
+0+232 <[^>]*> eeb4 3b4e 	fcmpdeq	d3, d14
+0+236 <[^>]*> eeb5 4b40 	fcmpzdeq	d4
 0+23a <[^>]*> bf01      	itttt	eq
-0+23c <[^>]*> eeb0 5bcd 	fabsd(eq|)	d5, d13
-0+240 <[^>]*> eeb0 6b4c 	fcpyd(eq|)	d6, d12
-0+244 <[^>]*> eeb1 7b4b 	fnegd(eq|)	d7, d11
-0+248 <[^>]*> eeb1 8bca 	fsqrtd(eq|)	d8, d10
+0+23c <[^>]*> eeb0 5bcd 	fabsdeq	d5, d13
+0+240 <[^>]*> eeb0 6b4c 	fcpydeq	d6, d12
+0+244 <[^>]*> eeb1 7b4b 	fnegdeq	d7, d11
+0+248 <[^>]*> eeb1 8bca 	fsqrtdeq	d8, d10
 0+24c <[^>]*> bf01      	itttt	eq
-0+24e <[^>]*> ee31 9b0f 	faddd(eq|)	d9, d1, d15
-0+252 <[^>]*> ee83 2b0e 	fdivd(eq|)	d2, d3, d14
-0+256 <[^>]*> ee0d 4b0c 	fmacd(eq|)	d4, d13, d12
-0+25a <[^>]*> ee16 5b0b 	fmscd(eq|)	d5, d6, d11
+0+24e <[^>]*> ee31 9b0f 	fadddeq	d9, d1, d15
+0+252 <[^>]*> ee83 2b0e 	fdivdeq	d2, d3, d14
+0+256 <[^>]*> ee0d 4b0c 	fmacdeq	d4, d13, d12
+0+25a <[^>]*> ee16 5b0b 	fmscdeq	d5, d6, d11
 0+25e <[^>]*> bf01      	itttt	eq
-0+260 <[^>]*> ee2a 7b09 	fmuld(eq|)	d7, d10, d9
-0+264 <[^>]*> ee09 8b4a 	fnmacd(eq|)	d8, d9, d10
-0+268 <[^>]*> ee16 7b4b 	fnmscd(eq|)	d7, d6, d11
-0+26c <[^>]*> ee24 5b4c 	fnmuld(eq|)	d5, d4, d12
+0+260 <[^>]*> ee2a 7b09 	fmuldeq	d7, d10, d9
+0+264 <[^>]*> ee09 8b4a 	fnmacdeq	d8, d9, d10
+0+268 <[^>]*> ee16 7b4b 	fnmscdeq	d7, d6, d11
+0+26c <[^>]*> ee24 5b4c 	fnmuldeq	d5, d4, d12
 0+270 <[^>]*> bf02      	ittt	eq
-0+272 <[^>]*> ee3d 3b4e 	fsubd(eq|)	d3, d13, d14
-0+276 <[^>]*> ed95 2b00 	fldd(eq|)	d2, \[r5\]
-0+27a <[^>]*> ed8c 1b00 	fstd(eq|)	d1, \[ip\]
+0+272 <[^>]*> ee3d 3b4e 	fsubdeq	d3, d13, d14
+0+276 <[^>]*> ed95 2b00 	vldreq	d2, \[r5\]
+0+27a <[^>]*> ed8c 1b00 	vstreq	d1, \[ip\]
 0+27e <[^>]*> bf01      	itttt	eq
-0+280 <[^>]*> ec91 1b02 	fldmiad(eq|)	r1, {d1}
-0+284 <[^>]*> ec92 2b02 	fldmiad(eq|)	r2, {d2}
-0+288 <[^>]*> ecb3 3b02 	fldmiad(eq|)	r3!, {d3}
-0+28c <[^>]*> ecb4 4b02 	fldmiad(eq|)	r4!, {d4}
+0+280 <[^>]*> ec91 1b02 	vldmiaeq	r1, {d1}
+0+284 <[^>]*> ec92 2b02 	vldmiaeq	r2, {d2}
+0+288 <[^>]*> ecb3 3b02 	vldmiaeq	r3!, {d3}
+0+28c <[^>]*> ecb4 4b02 	vldmiaeq	r4!, {d4}
 0+290 <[^>]*> bf01      	itttt	eq
-0+292 <[^>]*> ed35 5b02 	fldmdbd(eq|)	r5!, {d5}
-0+296 <[^>]*> ed36 6b02 	fldmdbd(eq|)	r6!, {d6}
-0+29a <[^>]*> ec87 fb02 	fstmiad(eq|)	r7, {d15}
-0+29e <[^>]*> ec88 eb02 	fstmiad(eq|)	r8, {d14}
+0+292 <[^>]*> ed35 5b02 	vldmdbeq	r5!, {d5}
+0+296 <[^>]*> ed36 6b02 	vldmdbeq	r6!, {d6}
+0+29a <[^>]*> ec87 fb02 	vstmiaeq	r7, {d15}
+0+29e <[^>]*> ec88 eb02 	vstmiaeq	r8, {d14}
 0+2a2 <[^>]*> bf01      	itttt	eq
-0+2a4 <[^>]*> eca9 db02 	fstmiad(eq|)	r9!, {d13}
-0+2a8 <[^>]*> ecaa cb02 	fstmiad(eq|)	sl!, {d12}
-0+2ac <[^>]*> ed2b bb02 	fstmdbd(eq|)	fp!, {d11}
-0+2b0 <[^>]*> ed2c ab02 	fstmdbd(eq|)	ip!, {d10}
+0+2a4 <[^>]*> eca9 db02 	vstmiaeq	r9!, {d13}
+0+2a8 <[^>]*> ecaa cb02 	vstmiaeq	sl!, {d12}
+0+2ac <[^>]*> ed2b bb02 	vstmdbeq	fp!, {d11}
+0+2b0 <[^>]*> ed2c ab02 	vstmdbeq	ip!, {d10}
 0+2b4 <[^>]*> bf01      	itttt	eq
-0+2b6 <[^>]*> eeb8 fbe0 	fsitod(eq|)	d15, s1
-0+2ba <[^>]*> eeb8 1b6f 	fuitod(eq|)	d1, s31
-0+2be <[^>]*> eefd 0b4f 	ftosid(eq|)	s1, d15
-0+2c2 <[^>]*> eefd fbc2 	ftosizd(eq|)	s31, d2
+0+2b6 <[^>]*> eeb8 fbe0 	fsitodeq	d15, s1
+0+2ba <[^>]*> eeb8 1b6f 	fuitodeq	d1, s31
+0+2be <[^>]*> eefd 0b4f 	ftosideq	s1, d15
+0+2c2 <[^>]*> eefd fbc2 	ftosizdeq	s31, d2
 0+2c6 <[^>]*> bf01      	itttt	eq
-0+2c8 <[^>]*> eefc 7b42 	ftouid(eq|)	s15, d2
-0+2cc <[^>]*> eefc 5bc3 	ftouizd(eq|)	s11, d3
-0+2d0 <[^>]*> eeb7 1ac5 	fcvtds(eq|)	d1, s10
-0+2d4 <[^>]*> eef7 5bc1 	fcvtsd(eq|)	s11, d1
+0+2c8 <[^>]*> eefc 7b42 	ftouideq	s15, d2
+0+2cc <[^>]*> eefc 5bc3 	ftouizdeq	s11, d3
+0+2d0 <[^>]*> eeb7 1ac5 	fcvtdseq	d1, s10
+0+2d4 <[^>]*> eef7 5bc1 	fcvtsdeq	s11, d1
 0+2d8 <[^>]*> bf01      	itttt	eq
-0+2da <[^>]*> ee31 8b10 	fmrdh(eq|)	r8, d1
-0+2de <[^>]*> ee1f 7b10 	fmrdl(eq|)	r7, d15
-0+2e2 <[^>]*> ee21 fb10 	fmdhr(eq|)	d1, pc
-0+2e6 <[^>]*> ee0f 1b10 	fmdlr(eq|)	d15, r1
+0+2da <[^>]*> ee31 8b10 	vmoveq\.32	r8, d1\[1\]
+0+2de <[^>]*> ee1f 7b10 	vmoveq\.32	r7, d15\[0\]
+0+2e2 <[^>]*> ee21 fb10 	vmoveq\.32	d1\[1\], pc
+0+2e6 <[^>]*> ee0f 1b10 	vmoveq\.32	d15\[0\], r1
 0+2ea <[^>]*> bf00      	nop
 0+2ec <[^>]*> bf00      	nop
 0+2ee <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index 096b46c86e4c..22932e5284c0 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -239,3 +239,15 @@ Disassembly of section .text:
 0+394 <[^>]*> 0ef09a10 	fmrxeq	r9, fpsid
 0+398 <[^>]*> 0e019a90 	fmsreq	s3, r9
 0+39c <[^>]*> 0ee08a10 	fmxreq	fpsid, r8
+0+3a0 <[^>]*> eef90a10 	fmrx	r0, fpinst	@ Impl def
+0+3a4 <[^>]*> eefa0a10 	fmrx	r0, fpinst2	@ Impl def
+0+3a8 <[^>]*> eef70a10 	fmrx	r0, mvfr0
+0+3ac <[^>]*> eef60a10 	fmrx	r0, mvfr1
+0+3b0 <[^>]*> eefc0a10 	fmrx	r0, <impl def 0xc>
+0+3b4 <[^>]*> eee90a10 	fmxr	fpinst, r0	@ Impl def
+0+3b8 <[^>]*> eeea0a10 	fmxr	fpinst2, r0	@ Impl def
+0+3bc <[^>]*> eee70a10 	fmxr	mvfr0, r0
+0+3c0 <[^>]*> eee60a10 	fmxr	mvfr1, r0
+0+3c4 <[^>]*> eeec0a10 	fmxr	<impl def 0xc>, r0
+0+3c8 <[^>]*> e1a00000 	nop			\(mov r0,r0\)
+0+3cc <[^>]*> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s
index 82f080f499b0..ecc022638158 100644
--- a/gas/testsuite/gas/arm/vfp1xD.s
+++ b/gas/testsuite/gas/arm/vfp1xD.s
@@ -337,3 +337,17 @@ F:
 	fmsreq	s3, r9
 	fmxreq	fpsid, r8
 
+	@ Implementation specific system registers
+	fmrx	r0, fpinst
+	fmrx	r0, fpinst2
+	fmrx	r0, mvfr0
+	fmrx	r0, mvfr1
+	fmrx	r0, c12
+	fmxr	fpinst, r0
+	fmxr	fpinst2, r0
+	fmxr	mvfr0, r0
+	fmxr	mvfr1, r0
+	fmxr	c12, r0
+
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
index 327383d01c5b..d2943114d6c0 100644
--- a/gas/testsuite/gas/arm/vfp1xD_t2.d
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
@@ -185,74 +185,87 @@ Disassembly of section .text:
 0+2bc <[^>]*> eef5 ea40 	fcmpzs	s29
 0+2c0 <[^>]*> eeb5 fa40 	fcmpzs	s30
 0+2c4 <[^>]*> eef5 fa40 	fcmpzs	s31
-# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
 0+2c8 <[^>]*> bf01      	itttt	eq
-0+2ca <[^>]*> eef1 fa10 	fmstat(eq|)
-0+2ce <[^>]*> eef4 1ae3 	fcmpes(eq|)	s3, s7
-0+2d2 <[^>]*> eef5 2ac0 	fcmpezs(eq|)	s5
-0+2d6 <[^>]*> eef4 0a41 	fcmps(eq|)	s1, s2
+0+2ca <[^>]*> eef1 fa10 	fmstateq
+0+2ce <[^>]*> eef4 1ae3 	fcmpeseq	s3, s7
+0+2d2 <[^>]*> eef5 2ac0 	fcmpezseq	s5
+0+2d6 <[^>]*> eef4 0a41 	fcmpseq	s1, s2
 0+2da <[^>]*> bf01      	itttt	eq
-0+2dc <[^>]*> eef5 0a40 	fcmpzs(eq|)	s1
-0+2e0 <[^>]*> eef0 0ae1 	fabss(eq|)	s1, s3
-0+2e4 <[^>]*> eef0 fa69 	fcpys(eq|)	s31, s19
-0+2e8 <[^>]*> eeb1 aa44 	fnegs(eq|)	s20, s8
+0+2dc <[^>]*> eef5 0a40 	fcmpzseq	s1
+0+2e0 <[^>]*> eef0 0ae1 	fabsseq	s1, s3
+0+2e4 <[^>]*> eef0 fa69 	fcpyseq	s31, s19
+0+2e8 <[^>]*> eeb1 aa44 	fnegseq	s20, s8
 0+2ec <[^>]*> bf01      	itttt	eq
-0+2ee <[^>]*> eef1 2ae3 	fsqrts(eq|)	s5, s7
-0+2f2 <[^>]*> ee32 3a82 	fadds(eq|)	s6, s5, s4
-0+2f6 <[^>]*> eec1 1a20 	fdivs(eq|)	s3, s2, s1
-0+2fa <[^>]*> ee4f fa2e 	fmacs(eq|)	s31, s30, s29
+0+2ee <[^>]*> eef1 2ae3 	fsqrtseq	s5, s7
+0+2f2 <[^>]*> ee32 3a82 	faddseq	s6, s5, s4
+0+2f6 <[^>]*> eec1 1a20 	fdivseq	s3, s2, s1
+0+2fa <[^>]*> ee4f fa2e 	fmacseq	s31, s30, s29
 0+2fe <[^>]*> bf01      	itttt	eq
-0+300 <[^>]*> ee1d ea8d 	fmscs(eq|)	s28, s27, s26
-0+304 <[^>]*> ee6c ca2b 	fmuls(eq|)	s25, s24, s23
-0+308 <[^>]*> ee0a baca 	fnmacs(eq|)	s22, s21, s20
-0+30c <[^>]*> ee59 9a68 	fnmscs(eq|)	s19, s18, s17
+0+300 <[^>]*> ee1d ea8d 	fmscseq	s28, s27, s26
+0+304 <[^>]*> ee6c ca2b 	fmulseq	s25, s24, s23
+0+308 <[^>]*> ee0a baca 	fnmacseq	s22, s21, s20
+0+30c <[^>]*> ee59 9a68 	fnmscseq	s19, s18, s17
 0+310 <[^>]*> bf01      	itttt	eq
-0+312 <[^>]*> ee27 8ac7 	fnmuls(eq|)	s16, s15, s14
-0+316 <[^>]*> ee76 6a65 	fsubs(eq|)	s13, s12, s11
-0+31a <[^>]*> ed98 5a00 	flds(eq|)	s10, \[r8\]
-0+31e <[^>]*> edc7 4a00 	fsts(eq|)	s9, \[r7\]
+0+312 <[^>]*> ee27 8ac7 	fnmulseq	s16, s15, s14
+0+316 <[^>]*> ee76 6a65 	fsubseq	s13, s12, s11
+0+31a <[^>]*> ed98 5a00 	fldseq	s10, \[r8\]
+0+31e <[^>]*> edc7 4a00 	fstseq	s9, \[r7\]
 0+322 <[^>]*> bf01      	itttt	eq
-0+324 <[^>]*> ec91 4a01 	fldmias(eq|)	r1, {s8}
-0+328 <[^>]*> ecd2 3a01 	fldmias(eq|)	r2, {s7}
-0+32c <[^>]*> ecb3 3a01 	fldmias(eq|)	r3!, {s6}
-0+330 <[^>]*> ecf4 2a01 	fldmias(eq|)	r4!, {s5}
+0+324 <[^>]*> ec91 4a01 	fldmiaseq	r1, {s8}
+0+328 <[^>]*> ecd2 3a01 	fldmiaseq	r2, {s7}
+0+32c <[^>]*> ecb3 3a01 	fldmiaseq	r3!, {s6}
+0+330 <[^>]*> ecf4 2a01 	fldmiaseq	r4!, {s5}
 0+334 <[^>]*> bf01      	itttt	eq
-0+336 <[^>]*> ed35 2a01 	fldmdbs(eq|)	r5!, {s4}
-0+33a <[^>]*> ed76 1a01 	fldmdbs(eq|)	r6!, {s3}
-0+33e <[^>]*> ec97 1b03 	fldmiax(eq|)	r7, {d1}
-0+342 <[^>]*> ec98 2b03 	fldmiax(eq|)	r8, {d2}
+0+336 <[^>]*> ed35 2a01 	fldmdbseq	r5!, {s4}
+0+33a <[^>]*> ed76 1a01 	fldmdbseq	r6!, {s3}
+0+33e <[^>]*> ec97 1b03 	fldmiaxeq	r7, {d1}
+0+342 <[^>]*> ec98 2b03 	fldmiaxeq	r8, {d2}
 0+346 <[^>]*> bf01      	itttt	eq
-0+348 <[^>]*> ecb9 3b03 	fldmiax(eq|)	r9!, {d3}
-0+34c <[^>]*> ecba 4b03 	fldmiax(eq|)	sl!, {d4}
-0+350 <[^>]*> ed3b 5b03 	fldmdbx(eq|)	fp!, {d5}
-0+354 <[^>]*> ed3c 6b03 	fldmdbx(eq|)	ip!, {d6}
+0+348 <[^>]*> ecb9 3b03 	fldmiaxeq	r9!, {d3}
+0+34c <[^>]*> ecba 4b03 	fldmiaxeq	sl!, {d4}
+0+350 <[^>]*> ed3b 5b03 	fldmdbxeq	fp!, {d5}
+0+354 <[^>]*> ed3c 6b03 	fldmdbxeq	ip!, {d6}
 0+358 <[^>]*> bf01      	itttt	eq
-0+35a <[^>]*> ec8d 1a01 	fstmias(eq|)	sp, {s2}
-0+35e <[^>]*> ecce 0a01 	fstmias(eq|)	lr, {s1}
-0+362 <[^>]*> ece1 fa01 	fstmias(eq|)	r1!, {s31}
-0+366 <[^>]*> eca2 fa01 	fstmias(eq|)	r2!, {s30}
+0+35a <[^>]*> ec8d 1a01 	fstmiaseq	sp, {s2}
+0+35e <[^>]*> ecce 0a01 	fstmiaseq	lr, {s1}
+0+362 <[^>]*> ece1 fa01 	fstmiaseq	r1!, {s31}
+0+366 <[^>]*> eca2 fa01 	fstmiaseq	r2!, {s30}
 0+36a <[^>]*> bf01      	itttt	eq
-0+36c <[^>]*> ed63 ea01 	fstmdbs(eq|)	r3!, {s29}
-0+370 <[^>]*> ed24 ea01 	fstmdbs(eq|)	r4!, {s28}
-0+374 <[^>]*> ec85 7b03 	fstmiax(eq|)	r5, {d7}
-0+378 <[^>]*> ec86 8b03 	fstmiax(eq|)	r6, {d8}
+0+36c <[^>]*> ed63 ea01 	fstmdbseq	r3!, {s29}
+0+370 <[^>]*> ed24 ea01 	fstmdbseq	r4!, {s28}
+0+374 <[^>]*> ec85 7b03 	fstmiaxeq	r5, {d7}
+0+378 <[^>]*> ec86 8b03 	fstmiaxeq	r6, {d8}
 0+37c <[^>]*> bf01      	itttt	eq
-0+37e <[^>]*> eca7 9b03 	fstmiax(eq|)	r7!, {d9}
-0+382 <[^>]*> eca8 ab03 	fstmiax(eq|)	r8!, {d10}
-0+386 <[^>]*> ed29 bb03 	fstmdbx(eq|)	r9!, {d11}
-0+38a <[^>]*> ed2a cb03 	fstmdbx(eq|)	sl!, {d12}
+0+37e <[^>]*> eca7 9b03 	fstmiaxeq	r7!, {d9}
+0+382 <[^>]*> eca8 ab03 	fstmiaxeq	r8!, {d10}
+0+386 <[^>]*> ed29 bb03 	fstmdbxeq	r9!, {d11}
+0+38a <[^>]*> ed2a cb03 	fstmdbxeq	sl!, {d12}
 0+38e <[^>]*> bf01      	itttt	eq
-0+390 <[^>]*> eef8 dac3 	fsitos(eq|)	s27, s6
-0+394 <[^>]*> eefd ca62 	ftosis(eq|)	s25, s5
-0+398 <[^>]*> eefd bac2 	ftosizs(eq|)	s23, s4
-0+39c <[^>]*> eefc aa61 	ftouis(eq|)	s21, s3
+0+390 <[^>]*> eef8 dac3 	fsitoseq	s27, s6
+0+394 <[^>]*> eefd ca62 	ftosiseq	s25, s5
+0+398 <[^>]*> eefd bac2 	ftosizseq	s23, s4
+0+39c <[^>]*> eefc aa61 	ftouiseq	s21, s3
 0+3a0 <[^>]*> bf01      	itttt	eq
-0+3a2 <[^>]*> eefc 9ac1 	ftouizs(eq|)	s19, s2
-0+3a6 <[^>]*> eef8 8a60 	fuitos(eq|)	s17, s1
-0+3aa <[^>]*> ee11 ba90 	fmrs(eq|)	fp, s3
-0+3ae <[^>]*> eef0 9a10 	fmrx(eq|)	r9, fpsid
+0+3a2 <[^>]*> eefc 9ac1 	ftouizseq	s19, s2
+0+3a6 <[^>]*> eef8 8a60 	fuitoseq	s17, s1
+0+3aa <[^>]*> ee11 ba90 	fmrseq	fp, s3
+0+3ae <[^>]*> eef0 9a10 	fmrxeq	r9, fpsid
 0+3b2 <[^>]*> bf04      	itt	eq
-0+3b4 <[^>]*> ee01 9a90 	fmsr(eq|)	s3, r9
-0+3b8 <[^>]*> eee0 8a10 	fmxr(eq|)	fpsid, r8
-0+3bc <[^>]*> bf00      	nop
-0+3be <[^>]*> bf00      	nop
+0+3b4 <[^>]*> ee01 9a90 	fmsreq	s3, r9
+0+3b8 <[^>]*> eee0 8a10 	fmxreq	fpsid, r8
+0+3bc <[^>]*> eef9 0a10 	fmrx	r0, fpinst	@ Impl def
+0+3c0 <[^>]*> eefa 0a10 	fmrx	r0, fpinst2	@ Impl def
+0+3c4 <[^>]*> eef7 0a10 	fmrx	r0, mvfr0
+0+3c8 <[^>]*> eef6 0a10 	fmrx	r0, mvfr1
+0+3cc <[^>]*> eefc 0a10 	fmrx	r0, <impl def 0xc>
+0+3d0 <[^>]*> eee9 0a10 	fmxr	fpinst, r0	@ Impl def
+0+3d4 <[^>]*> eeea 0a10 	fmxr	fpinst2, r0	@ Impl def
+0+3d8 <[^>]*> eee7 0a10 	fmxr	mvfr0, r0
+0+3dc <[^>]*> eee6 0a10 	fmxr	mvfr1, r0
+0+3e0 <[^>]*> eeec 0a10 	fmxr	<impl def 0xc>, r0
+0+3e4 <[^>]*> bf00      	nop
+0+3e6 <[^>]*> bf00      	nop
+0+3e8 <[^>]*> bf00      	nop
+0+3ea <[^>]*> bf00      	nop
+0+3ec <[^>]*> bf00      	nop
+0+3ee <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s
index f3087a37ee96..8e962c07e3e9 100644
--- a/gas/testsuite/gas/arm/vfp1xD_t2.s
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.s
@@ -354,6 +354,21 @@ F:
 	fmsreq	s3, r9
 	fmxreq	fpsid, r8
 
-	@ 2 nops to pad to 16-byte boundary
+	@ Implementation specific system registers
+	fmrx	r0, fpinst
+	fmrx	r0, fpinst2
+	fmrx	r0, mvfr0
+	fmrx	r0, mvfr1
+	fmrx	r0, c12
+	fmxr	fpinst, r0
+	fmxr	fpinst2, r0
+	fmxr	mvfr0, r0
+	fmxr	mvfr1, r0
+	fmxr	c12, r0
+
+	nop
+	nop
+	nop
+	nop
 	nop
 	nop
diff --git a/gas/testsuite/gas/arm/vfp2.d b/gas/testsuite/gas/arm/vfp2.d
index f9b6096081eb..438019fc12ed 100644
--- a/gas/testsuite/gas/arm/vfp2.d
+++ b/gas/testsuite/gas/arm/vfp2.d
@@ -7,11 +7,11 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]*> ec4a5b10 	fmdrr	d0, r5, sl
-0+004 <[^>]*> ec5a5b10 	fmrrd	r5, sl, d0
-0+008 <[^>]*> ec4a5a37 	fmsrr	r5, sl, {s15, s16}
+0+000 <[^>]*> ec4a5b10 	vmov	d0, r5, sl
+0+004 <[^>]*> ec5a5b10 	vmov	r5, sl, d0
+0+008 <[^>]*> ec4a5a37 	fmsrr	{s15, s16}, r5, sl
 0+00c <[^>]*> ec5a5a37 	fmrrs	r5, sl, {s15, s16}
-0+010 <[^>]*> ec45ab1f 	fmdrr	d15, sl, r5
-0+014 <[^>]*> ec55ab1f 	fmrrd	sl, r5, d15
-0+018 <[^>]*> ec45aa38 	fmsrr	sl, r5, {s17, s18}
+0+010 <[^>]*> ec45ab1f 	vmov	d15, sl, r5
+0+014 <[^>]*> ec55ab1f 	vmov	sl, r5, d15
+0+018 <[^>]*> ec45aa38 	fmsrr	{s17, s18}, sl, r5
 0+01c <[^>]*> ec55aa38 	fmrrs	sl, r5, {s17, s18}
diff --git a/gas/testsuite/gas/arm/vfp2_t2.d b/gas/testsuite/gas/arm/vfp2_t2.d
index bb988e5472e2..f07b6a58bcba 100644
--- a/gas/testsuite/gas/arm/vfp2_t2.d
+++ b/gas/testsuite/gas/arm/vfp2_t2.d
@@ -7,11 +7,11 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]*> ec4a 5b10 	fmdrr	d0, r5, sl
-0+004 <[^>]*> ec5a 5b10 	fmrrd	r5, sl, d0
-0+008 <[^>]*> ec4a 5a37 	fmsrr	r5, sl, {s15, s16}
+0+000 <[^>]*> ec4a 5b10 	vmov	d0, r5, sl
+0+004 <[^>]*> ec5a 5b10 	vmov	r5, sl, d0
+0+008 <[^>]*> ec4a 5a37 	fmsrr	{s15, s16}, r5, sl
 0+00c <[^>]*> ec5a 5a37 	fmrrs	r5, sl, {s15, s16}
-0+010 <[^>]*> ec45 ab1f 	fmdrr	d15, sl, r5
-0+014 <[^>]*> ec55 ab1f 	fmrrd	sl, r5, d15
-0+018 <[^>]*> ec45 aa38 	fmsrr	sl, r5, {s17, s18}
+0+010 <[^>]*> ec45 ab1f 	vmov	d15, sl, r5
+0+014 <[^>]*> ec55 ab1f 	vmov	sl, r5, d15
+0+018 <[^>]*> ec45 aa38 	fmsrr	{s17, s18}, sl, r5
 0+01c <[^>]*> ec55 aa38 	fmrrs	sl, r5, {s17, s18}
diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.d b/gas/testsuite/gas/arm/vfpv3-32drs.d
new file mode 100644
index 000000000000..f42c373f4c3d
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-32drs.d
@@ -0,0 +1,73 @@
+# name: VFPv3 extra D registers
+# as: -mfpu=vfp3
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> eeb03b66 	fcpyd	d3, d22
+0[0-9a-f]+ <[^>]+> eef06b43 	fcpyd	d22, d3
+0[0-9a-f]+ <[^>]+> eef76acb 	fcvtds	d22, s22
+0[0-9a-f]+ <[^>]+> eeb7bbe6 	fcvtsd	s22, d22
+0[0-9a-f]+ <[^>]+> ee254b90 	vmov\.32	d21\[1\], r4
+0[0-9a-f]+ <[^>]+> ee0b5b90 	vmov\.32	d27\[0\], r5
+0[0-9a-f]+ <[^>]+> ee376b90 	vmov\.32	r6, d23\[1\]
+0[0-9a-f]+ <[^>]+> ee197b90 	vmov\.32	r7, d25\[0\]
+0[0-9a-f]+ <[^>]+> eef86bcb 	fsitod	d22, s22
+0[0-9a-f]+ <[^>]+> eef85b6a 	fuitod	d21, s21
+0[0-9a-f]+ <[^>]+> eebdab64 	ftosid	s20, d20
+0[0-9a-f]+ <[^>]+> eebdabe4 	ftosizd	s20, d20
+0[0-9a-f]+ <[^>]+> eefc9b63 	ftouid	s19, d19
+0[0-9a-f]+ <[^>]+> eefc9be3 	ftouizd	s19, d19
+0[0-9a-f]+ <[^>]+> edda3b01 	vldr	d19, \[sl, #4\]
+0[0-9a-f]+ <[^>]+> edca5b01 	vstr	d21, \[sl, #4\]
+0[0-9a-f]+ <[^>]+> ecba5b04 	vldmia	sl!, {d5-d6}
+0[0-9a-f]+ <[^>]+> ecfa2b06 	vldmia	sl!, {d18-d20}
+0[0-9a-f]+ <[^>]+> ecba5b05 	fldmiax	sl!, {d5-d6}
+0[0-9a-f]+ <[^>]+> ecfa2b07 	fldmiax	sl!, {d18-d20}
+0[0-9a-f]+ <[^>]+> ed7a2b05 	fldmdbx	sl!, {d18-d19}
+0[0-9a-f]+ <[^>]+> ecc94b0a 	vstmia	r9, {d20-d24}
+0[0-9a-f]+ <[^>]+> eeb03bc5 	fabsd	d3, d5
+0[0-9a-f]+ <[^>]+> eeb0cbe2 	fabsd	d12, d18
+0[0-9a-f]+ <[^>]+> eef02be3 	fabsd	d18, d19
+0[0-9a-f]+ <[^>]+> eeb13b45 	fnegd	d3, d5
+0[0-9a-f]+ <[^>]+> eeb1cb62 	fnegd	d12, d18
+0[0-9a-f]+ <[^>]+> eef12b63 	fnegd	d18, d19
+0[0-9a-f]+ <[^>]+> eeb13bc5 	fsqrtd	d3, d5
+0[0-9a-f]+ <[^>]+> eeb1cbe2 	fsqrtd	d12, d18
+0[0-9a-f]+ <[^>]+> eef12be3 	fsqrtd	d18, d19
+0[0-9a-f]+ <[^>]+> ee353b06 	faddd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee32cb84 	faddd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee732ba4 	faddd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee353b46 	fsubd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee32cbc4 	fsubd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee732be4 	fsubd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee253b06 	fmuld	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee22cb84 	fmuld	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee632ba4 	fmuld	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee853b06 	fdivd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee82cb84 	fdivd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> eec32ba4 	fdivd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee053b06 	fmacd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee02cb84 	fmacd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee432ba4 	fmacd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee153b06 	fmscd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee12cb84 	fmscd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee532ba4 	fmscd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee253b46 	fnmuld	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee22cbc4 	fnmuld	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee632be4 	fnmuld	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee053b46 	fnmacd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee02cbc4 	fnmacd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee432be4 	fnmacd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> ee153b46 	fnmscd	d3, d5, d6
+0[0-9a-f]+ <[^>]+> ee12cbc4 	fnmscd	d12, d18, d4
+0[0-9a-f]+ <[^>]+> ee532be4 	fnmscd	d18, d19, d20
+0[0-9a-f]+ <[^>]+> eeb43b62 	fcmpd	d3, d18
+0[0-9a-f]+ <[^>]+> eef42b43 	fcmpd	d18, d3
+0[0-9a-f]+ <[^>]+> eef53b40 	fcmpzd	d19
+0[0-9a-f]+ <[^>]+> eeb43be2 	fcmped	d3, d18
+0[0-9a-f]+ <[^>]+> eef42bc3 	fcmped	d18, d3
+0[0-9a-f]+ <[^>]+> eef53bc0 	fcmpezd	d19
+0[0-9a-f]+ <[^>]+> ec443b3f 	vmov	d31, r3, r4
+0[0-9a-f]+ <[^>]+> ec565b3e 	vmov	r5, r6, d30
diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.s b/gas/testsuite/gas/arm/vfpv3-32drs.s
new file mode 100644
index 000000000000..ef72c24eb5ad
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-32drs.s
@@ -0,0 +1,68 @@
+.arm
+.syntax unified
+	fcpyd d3,d22
+	fcpyd d22,d3
+	fcvtds d22,s22
+	fcvtsd s22,d22
+	fmdhr d21,r4
+	fmdlr d27,r5
+	fmrdh r6,d23
+	fmrdl r7,d25
+	fsitod d22,s22
+	fuitod d21,s21
+	ftosid s20,d20
+	ftosizd s20,d20
+	ftouid s19,d19
+	ftouizd s19,d19
+	fldd d19,[r10,#4]
+	fstd d21,[r10,#4]
+	fldmiad r10!,{d5,d6}
+	fldmiad r10!,{d18,d19,d20}
+	fldmiax r10!,{d5,d6}
+	fldmiax r10!,{d18,d19,d20}
+	fldmdbx r10!,{d18,d19}
+	fstmiad r9,{d20,d21,d22,d23,d24}
+	fabsd d3,d5
+	fabsd d12,d18
+	fabsd d18,d19
+	fnegd d3,d5
+	fnegd d12,d18
+	fnegd d18,d19
+	fsqrtd d3,d5
+	fsqrtd d12,d18
+	fsqrtd d18,d19
+	faddd d3,d5,d6
+	faddd d12,d18,d4
+	faddd d18,d19,d20
+	fsubd d3,d5,d6
+	fsubd d12,d18,d4
+	fsubd d18,d19,d20
+	fmuld d3,d5,d6
+	fmuld d12,d18,d4
+	fmuld d18,d19,d20
+	fdivd d3,d5,d6
+	fdivd d12,d18,d4
+	fdivd d18,d19,d20
+	fmacd d3,d5,d6
+	fmacd d12,d18,d4
+	fmacd d18,d19,d20
+	fmscd d3,d5,d6
+	fmscd d12,d18,d4
+	fmscd d18,d19,d20
+	fnmuld d3,d5,d6
+	fnmuld d12,d18,d4
+	fnmuld d18,d19,d20
+	fnmacd d3,d5,d6
+	fnmacd d12,d18,d4
+	fnmacd d18,d19,d20
+	fnmscd d3,d5,d6
+	fnmscd d12,d18,d4
+	fnmscd d18,d19,d20
+	fcmpd d3,d18
+	fcmpd d18,d3
+	fcmpzd d19
+	fcmped d3,d18
+	fcmped d18,d3
+	fcmpezd d19
+	fmdrr d31,r3,r4
+	fmrrd r5,r6,d30
diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.d b/gas/testsuite/gas/arm/vfpv3-const-conv.d
new file mode 100644
index 000000000000..9515feff7133
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-const-conv.d
@@ -0,0 +1,29 @@
+# name: VFPv3 additional constant and conversion ops
+# as: -mfpu=vfp3
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0[0-9a-f]+ <[^>]+> eef08a04 	fconsts	s17, #4
+0[0-9a-f]+ <[^>]+> eeba9a05 	fconsts	s18, #165
+0[0-9a-f]+ <[^>]+> eef49a00 	fconsts	s19, #64
+0[0-9a-f]+ <[^>]+> eef01b04 	fconstd	d17, #4
+0[0-9a-f]+ <[^>]+> eefa2b05 	fconstd	d18, #165
+0[0-9a-f]+ <[^>]+> eef43b00 	fconstd	d19, #64
+0[0-9a-f]+ <[^>]+> eefa8a63 	fshtos	s17, #9
+0[0-9a-f]+ <[^>]+> eefa1b63 	fshtod	d17, #9
+0[0-9a-f]+ <[^>]+> eefa8aeb 	fsltos	s17, #9
+0[0-9a-f]+ <[^>]+> eefa1beb 	fsltod	d17, #9
+0[0-9a-f]+ <[^>]+> eefb8a63 	fuhtos	s17, #9
+0[0-9a-f]+ <[^>]+> eefb1b63 	fuhtod	d17, #9
+0[0-9a-f]+ <[^>]+> eefb8aeb 	fultos	s17, #9
+0[0-9a-f]+ <[^>]+> eefb1beb 	fultod	d17, #9
+0[0-9a-f]+ <[^>]+> eefe9a64 	ftoshs	s19, #7
+0[0-9a-f]+ <[^>]+> eefe3b64 	ftoshd	d19, #7
+0[0-9a-f]+ <[^>]+> eefe9aec 	ftosls	s19, #7
+0[0-9a-f]+ <[^>]+> eefe3bec 	ftosld	d19, #7
+0[0-9a-f]+ <[^>]+> eeff9a64 	ftouhs	s19, #7
+0[0-9a-f]+ <[^>]+> eeff3b64 	ftouhd	d19, #7
+0[0-9a-f]+ <[^>]+> eeff9aec 	ftouls	s19, #7
+0[0-9a-f]+ <[^>]+> eeff3bec 	ftould	d19, #7
diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.s b/gas/testsuite/gas/arm/vfpv3-const-conv.s
new file mode 100644
index 000000000000..d726d14b568e
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfpv3-const-conv.s
@@ -0,0 +1,25 @@
+.arm
+.syntax unified
+	fconsts s17, #4
+	fconsts s18, #0xa5
+	fconsts s19, #0x40
+	fconstd d17, #4
+	fconstd d18, #0xa5
+	fconstd d19, #0x40
+	fshtos s17, 9
+	fshtod d17, 9
+	fsltos s17, 9
+	fsltod d17, 9
+	fuhtos s17, 9
+	fuhtod d17, 9
+	fultos s17, 9
+	fultod d17, 9
+
+	ftoshs s19, 7
+	ftoshd d19, 7
+	ftosls s19, 7
+	ftosld d19, 7
+	ftouhs s19, 7
+	ftouhd d19, 7
+	ftouls s19, 7
+	ftould d19, 7
diff --git a/gas/testsuite/gas/arm/wince.d b/gas/testsuite/gas/arm/wince.d
new file mode 100644
index 000000000000..1770cacd4f14
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince.d
@@ -0,0 +1,30 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: ARM WinCE basic tests
+#as: -mcpu=arm7m -EL
+#source: wince.s
+#not-skip: *-wince-*
+
+# Some WinCE specific tests.
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <global_data> 00000007 	andeq	r0, r0, r7
+			0: ARM_32	global_data
+0+004 <global_sym> e1a00000 	nop			\(mov r0,r0\)
+0+008 <global_sym\+0x4> e1a00000 	nop			\(mov r0,r0\)
+0+000c <global_sym\+0x8> e1a00000 	nop			\(mov r0,r0\)
+0+010 <global_sym\+0xc> eafffffb 	b	f+ff8 <global_sym\+0xf+ff4>
+			10: ARM_26D	global_sym\+0xf+ffc
+0+018 <global_sym\+0x14> ebfffffa 	bl	f+ff4 <global_sym\+0xf+ff0>
+			14: ARM_26D	global_sym\+0xf+ffc
+0+01c <global_sym\+0x18> 0afffff9 	beq	f+ff0 <global_sym\+0xf+fec>
+			18: ARM_26D	global_sym\+0xf+ffc
+0+020 <global_sym\+0x1c> eafffff8 	b	0+008 <global_sym\+0x4>
+0+024 <global_sym\+0x20> ebfffff7 	bl	0+008 <global_sym\+0x4>
+0+028 <global_sym\+0x24> 0afffff6 	beq	0+008 <global_sym\+0x4>
+0+02c <global_sym\+0x28> eafffff5 	b	0+008 <global_sym\+0x4>
+0+030 <global_sym\+0x2c> ebfffff4 	bl	0+008 <global_sym\+0x4>
+0+034 <global_sym\+0x30> e51f0034 	ldr	r0, \[pc, #-52\]	; 0+008 <global_sym\+0x4>
+0+038 <global_sym\+0x34> e51f0038 	ldr	r0, \[pc, #-56\]	; 0+008 <global_sym\+0x4>
+0+03c <global_sym\+0x38> e51f003c 	ldr	r0, \[pc, #-60\]	; 0+008 <global_sym\+0x4>
diff --git a/gas/testsuite/gas/arm/wince.s b/gas/testsuite/gas/arm/wince.s
new file mode 100644
index 000000000000..e8b76a045901
--- /dev/null
+++ b/gas/testsuite/gas/arm/wince.s
@@ -0,0 +1,25 @@
+	.global	global_data
+	.text
+	.global	global_sym
+	.def global_sym; .scl	2; .type 32; .endef
+
+global_data:
+	.word	global_data+7
+
+global_sym:
+def_sym:
+undef_sym:
+	nop
+	nop
+	nop
+	b	global_sym
+	bl	global_sym
+	beq	global_sym
+	b	def_sym
+	bl	def_sym
+	beq	def_sym
+	b	undef_sym
+	bl	undef_sym
+	ldr	r0, global_sym
+	ldr	r0, def_sym
+	ldr	r0, undef_sym
diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d
index a9852e0394b8..e3f060d90db0 100644
--- a/gas/testsuite/gas/arm/wince_inst.d
+++ b/gas/testsuite/gas/arm/wince_inst.d
@@ -36,7 +36,7 @@ Disassembly of section .text:
 0+058 <[^>]*> 21a09008 ?	movcs	r9, r8
 0+05c <[^>]*> 31a01003 ?	movcc	r1, r3
 0+060 <[^>]*> e1b00008 ?	movs	r0, r8
-0+064 <[^>]*> 31b00007 ?	movccs	r0, r7
+0+064 <[^>]*> 31b00007 ?	movscc	r0, r7
 0+068 <[^>]*> e281000a ?	add	r0, r1, #10	; 0xa
 0+06c <[^>]*> e0832004 ?	add	r2, r3, r4
 0+070 <[^>]*> e0865287 ?	add	r5, r6, r7, lsl #5
@@ -116,11 +116,11 @@ Disassembly of section .text:
 0+198 <[^>]*> e0000291 ?	mul	r0, r1, r2
 0+19c <[^>]*> e0110392 ?	muls	r1, r2, r3
 0+1a0 <[^>]*> 10000091 ?	mulne	r0, r1, r0
-0+1a4 <[^>]*> 90190798 ?	mullss	r9, r8, r7
+0+1a4 <[^>]*> 90190798 ?	mulsls	r9, r8, r7
 0+1a8 <[^>]*> e021ba99 ?	mla	r1, r9, sl, fp
 0+1ac <[^>]*> e033c994 ?	mlas	r3, r4, r9, ip
 0+1b0 <[^>]*> b029d798 ?	mlalt	r9, r8, r7, sp
-0+1b4 <[^>]*> a034e391 ?	mlages	r4, r1, r3, lr
+0+1b4 <[^>]*> a034e391 ?	mlasge	r4, r1, r3, lr
 0+1b8 <[^>]*> e5910000 ?	ldr	r0, \[r1\]
 0+1bc <[^>]*> e7911002 ?	ldr	r1, \[r1, r2\]
 0+1c0 <[^>]*> e7b32004 ?	ldr	r2, \[r3, r4\]!
@@ -132,7 +132,7 @@ Disassembly of section .text:
 0+1d8 <[^>]*> e6942425 ?	ldr	r2, \[r4\], r5, lsr #8
 0+1dc <[^>]*> e51f0008 ?	ldr	r0, \[pc, #-8\]	; 0+1dc <[^>]*>
 0+1e0 <[^>]*> e5d43000 ?	ldrb	r3, \[r4\]
-0+1e4 <[^>]*> 14f85000 ?	ldrnebt	r5, \[r8\]
+0+1e4 <[^>]*> 14f85000 ?	ldrbtne	r5, \[r8\]
 0+1e8 <[^>]*> e5810000 ?	str	r0, \[r1\]
 0+1ec <[^>]*> e7811002 ?	str	r1, \[r1, r2\]
 0+1f0 <[^>]*> e7a43003 ?	str	r3, \[r4, r3\]!
@@ -145,31 +145,31 @@ Disassembly of section .text:
 0+20c <[^>]*> e50f1004 ?	str	r1, \[pc, #-4\]	; 0+210 <[^>]*>
 0+210 <[^>]*> e5c71000 ?	strb	r1, \[r7\]
 0+214 <[^>]*> e4e02000 ?	strbt	r2, \[r0\]
-0+218 <[^>]*> e8900002 ?	ldmia	r0, {r1}
-0+21c <[^>]*> 09920038 ?	ldmeqib	r2, {r3, r4, r5}
+0+218 <[^>]*> e8900002 ?	ldm	r0, {r1}
+0+21c <[^>]*> 09920038 ?	ldmibeq	r2, {r3, r4, r5}
 0+220 <[^>]*> e853ffff ?	ldmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
 0+224 <[^>]*> e93b05ff ?	ldmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
 0+228 <[^>]*> e99100f7 ?	ldmib	r1, {r0, r1, r2, r4, r5, r6, r7}
-0+22c <[^>]*> e89201f8 ?	ldmia	r2, {r3, r4, r5, r6, r7, r8}
+0+22c <[^>]*> e89201f8 ?	ldm	r2, {r3, r4, r5, r6, r7, r8}
 0+230 <[^>]*> e9130003 ?	ldmdb	r3, {r0, r1}
 0+234 <[^>]*> e8540300 ?	ldmda	r4, {r8, r9}\^
-0+238 <[^>]*> e8800002 ?	stmia	r0, {r1}
-0+23c <[^>]*> 09820038 ?	stmeqib	r2, {r3, r4, r5}
+0+238 <[^>]*> e8800002 ?	stm	r0, {r1}
+0+23c <[^>]*> 09820038 ?	stmibeq	r2, {r3, r4, r5}
 0+240 <[^>]*> e843ffff ?	stmda	r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^
 0+244 <[^>]*> e92b05ff ?	stmdb	fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl}
 0+248 <[^>]*> e8010007 ?	stmda	r1, {r0, r1, r2}
 0+24c <[^>]*> e9020018 ?	stmdb	r2, {r3, r4}
-0+250 <[^>]*> e8830003 ?	stmia	r3, {r0, r1}
+0+250 <[^>]*> e8830003 ?	stm	r3, {r0, r1}
 0+254 <[^>]*> e9c40300 ?	stmib	r4, {r8, r9}\^
 0+258 <[^>]*> ef123456 ?	(swi|svc)	0x00123456
 0+25c <[^>]*> 2f000033 ?	(swi|svc)cs	0x00000033
-0+260 <[^>]*> eb000000 ?	bl	0+268 <[^>]*>
+0+260 <[^>]*> eb000000 ?	bl	0.* <[^>]*>
 [		]*260:.*_wombat.*
-0+264 <[^>]*> 5b000000 ?	blpl	0+26c <[^>]*>
+0+264 <[^>]*> 5b000000 ?	blpl	0.* <[^>]*>
 [		]*264:.*ARM.*hohum
-0+268 <[^>]*> ea000000 ?	b	0+270 <[^>]*>
+0+268 <[^>]*> ea000000 ?	b	0.* <[^>]*>
 [		]*268:.*_wibble.*
-0+26c <[^>]*> da000000 ?	ble	0+274 <[^>]*>
+0+26c <[^>]*> da000000 ?	ble	0.* <[^>]*>
 [		]*26c:.*testerfunc.*
 0+270 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
 0+274 <[^>]*> e1a01002 ?	mov	r1, r2
diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d
index fc38ba14e57e..32ecf1f3354a 100644
--- a/gas/testsuite/gas/arm/xscale.d
+++ b/gas/testsuite/gas/arm/xscale.d
@@ -24,12 +24,12 @@ Disassembly of section .text:
 0+38 <[^>]*> f7d2f003 	pld	\[r2, r3\]
 0+3c <[^>]*> f754f285 	pld	\[r4, -r5, lsl #5\]
 0+40 <[^>]*> e1c100d0 	ldrd	r0, \[r1\]
-0+44 <[^>]*> 01c327d8 	ldreqd	r2, \[r3, #120\]
-0+48 <[^>]*> b10540d6 	ldrltd	r4, \[r5, -r6\]
+0+44 <[^>]*> 01c327d8 	ldrdeq	r2, \[r3, #120\]
+0+48 <[^>]*> b10540d6 	ldrdlt	r4, \[r5, -r6\]
 0+4c <[^>]*> e16a88f9 	strd	r8, \[sl, #-137\]!
 0+50 <[^>]*> e1ac00fd 	strd	r0, \[ip, sp\]!
-0+54 <[^>]*> 30ce21f0 	strccd	r2, \[lr\], #16
-0+58 <[^>]*> 708640f8 	strvcd	r4, \[r6\], r8
+0+54 <[^>]*> 30ce21f0 	strdcc	r2, \[lr\], #16
+0+58 <[^>]*> 708640f8 	strdvc	r4, \[r6\], r8
 0+5c <[^>]*> e5910000 	ldr	r0, \[r1\]
 0+60 <[^>]*> e5832000 	str	r2, \[r3\]
 0+64 <[^>]*> e321f011 	msr	CPSR_c, #17	; 0x11
diff --git a/gas/testsuite/gas/bfin/bfin.exp b/gas/testsuite/gas/bfin/bfin.exp
index 51690a16fe05..9f7849b27b9a 100644
--- a/gas/testsuite/gas/bfin/bfin.exp
+++ b/gas/testsuite/gas/bfin/bfin.exp
@@ -1,17 +1,5 @@
 # Blackfin assembler testsuite
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "bfin $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
 if [istarget bfin*-*-*] {
 	run_dump_test "arithmetic"
 	run_dump_test "bit"
diff --git a/gas/testsuite/gas/bfin/load.d b/gas/testsuite/gas/bfin/load.d
index 58d97c2a82f4..07af13973295 100644
--- a/gas/testsuite/gas/bfin/load.d
+++ b/gas/testsuite/gas/bfin/load.d
@@ -31,84 +31,86 @@ Disassembly of section .text:
   54:	36 e1 ff 7f 	M2=0x7fff \(X\);
   58:	81 60       	R1=0x10\(x\);
   5a:	3c e1 00 00 	L0=0x0 \(X\);
-  5e:	27 e1 eb 00 	R7=0xeb \(X\);
+  5e:	27 e1 f3 00 	R7=0xf3 \(X\);
+  62:	00 e1 03 00 	R0.L=0x3;
+  66:	01 e1 0f 00 	R1.L=0xf;
 
-00000062 <load_pointer_register>:
-  62:	7e 91       	SP=\[FP\];
-  64:	47 90       	FP=\[P0\+\+\];
-  66:	f1 90       	P1=\[SP--\];
-  68:	96 af       	SP=\[P2\+0x38\];
-  6a:	3b ac       	P3=\[FP\+0x0];
-  6c:	3c e5 ff 7f 	P4=\[FP\+0x1fffc\];
-  70:	3e e5 01 80 	SP=\[FP\+-131068\];
-  74:	26 ac       	SP=\[P4\+0x0\];
-  76:	0d b8       	P5=\[FP-128\];
+0000006a <load_pointer_register>:
+  6a:	7e 91       	SP=\[FP\];
+  6c:	47 90       	FP=\[P0\+\+\];
+  6e:	f1 90       	P1=\[SP--\];
+  70:	96 af       	SP=\[P2\+0x38\];
+  72:	3b ac       	P3=\[FP\+0x0\];
+  74:	3c e5 ff 7f 	P4=\[FP\+0x1fffc\];
+  78:	3e e5 01 80 	SP=\[FP\+-131068\];
+  7c:	26 ac       	SP=\[P4\+0x0\];
+  7e:	0d b8       	P5=\[FP-128\];
 
-00000078 <load_data_register>:
-  78:	07 91       	R7=\[P0\];
-  7a:	2e 90       	R6=\[P5\+\+\];
-  7c:	a5 90       	R5=\[P4--\];
-  7e:	bc a2       	R4=\[FP\+0x28\];
-  80:	33 e4 ff 7f 	R3=\[SP\+0x1fffc\];
-  84:	32 a0       	R2=\[SP\+0x0\];
-  86:	39 e4 01 80 	R1=\[FP\+-131068\];
-  8a:	06 80       	R0=\[SP\+\+P0\];
-  8c:	05 b8       	R5=\[FP-128\];
-  8e:	02 9d       	R2=\[I0\];
-  90:	09 9c       	R1=\[I1\+\+\];
-  92:	93 9c       	R3=\[I2--\];
-  94:	9c 9d       	R4=\[I3\+\+M0\];
+00000080 <load_data_register>:
+  80:	07 91       	R7=\[P0\];
+  82:	2e 90       	R6=\[P5\+\+\];
+  84:	a5 90       	R5=\[P4--\];
+  86:	bc a2       	R4=\[FP\+0x28\];
+  88:	33 e4 ff 7f 	R3=\[SP\+0x1fffc\];
+  8c:	32 a0       	R2=\[SP\+0x0\];
+  8e:	39 e4 01 80 	R1=\[FP\+-131068\];
+  92:	06 80       	R0=\[SP\+\+P0\];
+  94:	05 b8       	R5=\[FP-128\];
+  96:	02 9d       	R2=\[I0\];
+  98:	09 9c       	R1=\[I1\+\+\];
+  9a:	93 9c       	R3=\[I2--\];
+  9c:	9c 9d       	R4=\[I3\+\+M0\];
 
-00000096 <load_half_word_zero_extend>:
-  96:	37 95       	R7=W\[SP\] \(Z\);
-  98:	3e 94       	R6=W\[FP\+\+\] \(Z\);
-  9a:	85 94       	R5=W\[P0--\] \(Z\);
-  9c:	cc a7       	R4=W\[P1\+0x1e\] \(Z\);
-  9e:	73 e4 fe 7f 	R3=W\[SP\+0xfffc\] \(Z\);
-  a2:	7a e4 02 80 	R2=W\[FP\+-65532\] \(Z\);
-  a6:	28 86       	R0=W\[P0\+\+P5\] \(Z\);
+0000009e <load_half_word_zero_extend>:
+  9e:	37 95       	R7=W\[SP\] \(Z\);
+  a0:	3e 94       	R6=W\[FP\+\+\] \(Z\);
+  a2:	85 94       	R5=W\[P0--\] \(Z\);
+  a4:	cc a7       	R4=W\[P1\+0x1e\] \(Z\);
+  a6:	73 e4 fe 7f 	R3=W\[SP\+0xfffc\] \(Z\);
+  aa:	7a e4 02 80 	R2=W\[FP\+-65532\] \(Z\);
+  ae:	28 86       	R0=W\[P0\+\+P5\] \(Z\);
 
-000000a8 <load_half_word_sign_extend>:
-  a8:	77 95       	R7=W\[SP\]\(X\);
-  aa:	7e 94       	R6=W\[FP\+\+\]\(X\);
-  ac:	c5 94       	R5=W\[P0--\]\(X\);
-  ae:	0d ab       	R5=W\[P1\+0x18\]\(X\);
-  b0:	73 e5 fe 7f 	R3=W\[SP\+0xfffc\]\(X\);
-  b4:	7f e5 02 80 	R7=W\[FP\+-65532\]\(X\);
-  b8:	51 8e       	R1=W\[P1\+\+P2\]\(X\);
+000000b0 <load_half_word_sign_extend>:
+  b0:	77 95       	R7=W\[SP\]\(X\);
+  b2:	7e 94       	R6=W\[FP\+\+\]\(X\);
+  b4:	c5 94       	R5=W\[P0--\]\(X\);
+  b6:	0d ab       	R5=W\[P1\+0x18\]\(X\);
+  b8:	73 e5 fe 7f 	R3=W\[SP\+0xfffc\]\(X\);
+  bc:	7f e5 02 80 	R7=W\[FP\+-65532\]\(X\);
+  c0:	51 8e       	R1=W\[P1\+\+P2\]\(X\);
 
-000000ba <load_high_data_register_half>:
-  ba:	40 9d       	R0.H=W\[I0\];
-  bc:	49 9c       	R1.H=W\[I1\+\+\];
-  be:	d2 9c       	R2.H=W\[I2--\];
-  c0:	f6 84       	R3.H=W\[SP\];
-  c2:	07 85       	R4.H=W\[FP\+\+P0\];
+000000c2 <load_high_data_register_half>:
+  c2:	40 9d       	R0.H=W\[I0\];
+  c4:	49 9c       	R1.H=W\[I1\+\+\];
+  c6:	d2 9c       	R2.H=W\[I2--\];
+  c8:	f6 84       	R3.H=W\[SP\];
+  ca:	07 85       	R4.H=W\[FP\+\+P0\];
 
-000000c4 <load_low_data_register_half>:
-  c4:	3f 9d       	R7.L=W\[I3\];
-  c6:	36 9c       	R6.L=W\[I2\+\+\];
-  c8:	ad 9c       	R5.L=W\[I1--\];
-  ca:	00 83       	R4.L=W\[P0\];
-  cc:	da 82       	R3.L=W\[P2\+\+P3\];
+000000cc <load_low_data_register_half>:
+  cc:	3f 9d       	R7.L=W\[I3\];
+  ce:	36 9c       	R6.L=W\[I2\+\+\];
+  d0:	ad 9c       	R5.L=W\[I1--\];
+  d2:	00 83       	R4.L=W\[P0\];
+  d4:	da 82       	R3.L=W\[P2\+\+P3\];
 
-000000ce <load_byte_zero_extend>:
-  ce:	05 99       	R5=B\[P0\] \(Z\);
-  d0:	0c 98       	R4=B\[P1\+\+\] \(Z\);
-  d2:	90 98       	R0=B\[P2--\] \(Z\);
-  d4:	b3 e4 ff 7f 	R3=B\[SP\+0x7fff\] \(Z\);
-  d8:	b7 e4 01 80 	R7=B\[SP\+-32767\] \(Z\);
+000000d6 <load_byte_zero_extend>:
+  d6:	05 99       	R5=B\[P0\] \(Z\);
+  d8:	0c 98       	R4=B\[P1\+\+\] \(Z\);
+  da:	90 98       	R0=B\[P2--\] \(Z\);
+  dc:	b3 e4 ff 7f 	R3=B\[SP\+0x7fff\] \(Z\);
+  e0:	b7 e4 01 80 	R7=B\[SP\+-32767\] \(Z\);
 
-000000dc <load_byte_sign_extend>:
-  dc:	45 99       	R5=B\[P0\]\(X\);
-  de:	4a 98       	R2=B\[P1\+\+\]\(X\);
-  e0:	fb 98       	R3=B\[FP--\]\(X\);
-  e2:	b7 e5 00 00 	R7=B\[SP\+0x0\]\(X\);
-  e6:	be e5 01 80 	R6=B\[FP\+-32767\]\(X\);
+000000e4 <load_byte_sign_extend>:
+  e4:	45 99       	R5=B\[P0\]\(X\);
+  e6:	4a 98       	R2=B\[P1\+\+\]\(X\);
+  e8:	fb 98       	R3=B\[FP--\]\(X\);
+  ea:	b7 e5 00 00 	R7=B\[SP\+0x0\]\(X\);
+  ee:	be e5 01 80 	R6=B\[FP\+-32767\]\(X\);
 
-000000ea <load_data1>:
+000000f2 <load_data1>:
 	...
 
-000000eb <load_data2>:
-  eb:	10 00       	IF ! CC JUMP eb <load_data2>;
-  ed:	00 00       	NOP;
+000000f3 <load_data2>:
+  f3:	10 00       	IF ! CC JUMP f3 <load_data2>;
+  f5:	00 00       	NOP;
 	...
diff --git a/gas/testsuite/gas/bfin/load.s b/gas/testsuite/gas/bfin/load.s
index 07f4732a7e99..96ae1faad194 100644
--- a/gas/testsuite/gas/bfin/load.s
+++ b/gas/testsuite/gas/bfin/load.s
@@ -36,6 +36,10 @@ load_immediate:
 	L0 = foo1;
 	r7 = load_data2;
 
+	/* Test constant folding.  */
+	r0.l = (a + 5) - 2; 
+	r1.l = (a + 5) + 10;
+
 	.text
 	.global load_pointer_register
 load_pointer_register:
diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d
index 57f3a91e2fa3..1a6b88492e88 100644
--- a/gas/testsuite/gas/bfin/vector2.d
+++ b/gas/testsuite/gas/bfin/vector2.d
@@ -469,3 +469,6 @@ Disassembly of section .text:
  734:	00 9e 32 9c 
  738:	8b c8 9a 2f 	R6 = \(a0 \+= R3.H \* R2.H\) \(FU\) \|\| I2-=M0 \|\| NOP;
  73c:	72 9e 00 00 
+ 740:	14 c2 1a a0 	R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L;
+ 744:	1c c2 b8 60 	R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L;
+ 748:	1c c0 b8 60 	R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\);
\ No newline at end of file
diff --git a/gas/testsuite/gas/bfin/vector2.s b/gas/testsuite/gas/bfin/vector2.s
index 30cca43c1ebe..d9ea20131e73 100755
--- a/gas/testsuite/gas/bfin/vector2.s
+++ b/gas/testsuite/gas/bfin/vector2.s
@@ -666,3 +666,8 @@ Ireg. */
 r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;

 /* which the assembler expands into:

 r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */

+

+/* Test for ensure (m) is not thown away.  */

+r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;

+R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);

+R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);

diff --git a/gas/testsuite/gas/cfi/cfi-common-5.d b/gas/testsuite/gas/cfi/cfi-common-5.d
new file mode 100644
index 000000000000..fed50c55b4bb
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-5.d
@@ -0,0 +1,24 @@
+#readelf: -wf
+#name: CFI common 5
+The section .eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     [01]b
+#...
+00000014 00000014 00000018 FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_remember_state
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_restore_state
+#...
+0000002c 0000001[48] 00000030 FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0 ofs 16
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa_offset: 0
+#pass
diff --git a/gas/testsuite/gas/cfi/cfi-common-5.s b/gas/testsuite/gas/cfi/cfi-common-5.s
new file mode 100644
index 000000000000..f59d97782348
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-5.s
@@ -0,0 +1,24 @@
+	.text
+	.cfi_startproc simple
+
+	.subsection 3
+	.cfi_startproc simple
+	.long 0
+	.cfi_def_cfa 0, 16
+	.previous
+
+	.long 0
+	.cfi_remember_state
+
+	.subsection 3
+	.long 0
+	.cfi_adjust_cfa_offset -16
+	.previous
+
+	.long 0
+	.cfi_restore_state
+	.cfi_endproc
+
+	.subsection 3
+	.cfi_endproc
+	.previous
diff --git a/gas/testsuite/gas/cfi/cfi-common-6.d b/gas/testsuite/gas/cfi/cfi-common-6.d
new file mode 100644
index 000000000000..dcc7b79b9697
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-6.d
@@ -0,0 +1,73 @@
+#readelf: -wf
+#name: CFI common 6
+The section .eh_frame contains:
+
+00000000 00000018 00000000 CIE
+  Version:               1
+  Augmentation:          "zPLR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     03 .. .. .. .. 0c 1b
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000001c 00000018 00000020 FDE cie=00000000 pc=00000000..00000004
+  Augmentation data:     (00 00 00 00 de ad be ef|ef be ad de 00 00 00 00)
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000038 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zLR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     0c 1b
+
+  DW_CFA_nop
+
+0000004c 00000018 00000018 FDE cie=00000038 pc=00000004..00000008
+  Augmentation data:     (00 00 00 00 de ad be ef|ef be ad de 00 00 00 00)
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000068 00000018 0000006c FDE cie=00000000 pc=00000008..0000000c
+  Augmentation data:     (00 00 00 00 be ef de ad|ad de ef be 00 00 00 00)
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000084 00000018 00000000 CIE
+  Version:               1
+  Augmentation:          "zPLR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     1b .. .. .. .. 1b 1b
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000a0 00000014 00000020 FDE cie=00000084 pc=0000000c..00000010
+  Augmentation data:     .. .. .. ..
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000b8 00000014 00000038 FDE cie=00000084 pc=00000010..00000014
+  Augmentation data:     .. .. .. ..
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/gas/testsuite/gas/cfi/cfi-common-6.s b/gas/testsuite/gas/cfi/cfi-common-6.s
new file mode 100644
index 000000000000..2471bff68ebc
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-6.s
@@ -0,0 +1,40 @@
+	.text
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.cfi_lsda 12, 0xdeadbeef
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.cfi_lsda 12, 0xdeadbeef
+	.cfi_personality 0xff
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.cfi_lsda 12, 0xbeefdead
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality (0x1b), my_personality_v1
+	.cfi_lsda 27, 1f
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality (0x1b), my_personality_v1
+	.cfi_lsda 27, 2f
+	.long 0
+	.cfi_endproc
+
+my_personality_v0:
+	.long 0
+my_personality_v1:
+	.long 0
+1:
+	.long 0
+2:
+	.long 0
diff --git a/gas/testsuite/gas/cfi/cfi-hppa-1.d b/gas/testsuite/gas/cfi/cfi-hppa-1.d
new file mode 100644
index 000000000000..7b06d55f327b
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-hppa-1.d
@@ -0,0 +1,38 @@
+#readelf: -wf
+#name: CFI on hppa
+The section .eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 4
+  Data alignment factor: -[48]
+  Return address column: 2
+  Augmentation data:     1b
+
+  DW_CFA_def_cfa: r30 ofs 0
+
+00000014 00000018 00000018 FDE cie=00000000 pc=00000000..00000018
+  DW_CFA_advance_loc: 8 to 00000008
+  DW_CFA_def_cfa_reg: r3
+  DW_CFA_advance_loc: 4 to 0000000c
+  DW_CFA_def_cfa_offset: 4660
+  DW_CFA_advance_loc: 8 to 00000014
+  DW_CFA_def_cfa_reg: r30
+  DW_CFA_nop
+
+00000030 00000018 00000034 FDE cie=00000000 pc=00000018..00000040
+  DW_CFA_advance_loc: 12 to 00000024
+  DW_CFA_def_cfa_reg: r3
+  DW_CFA_offset: r2 at cfa-24
+  DW_CFA_advance_loc: 24 to 0000003c
+  DW_CFA_def_cfa_reg: r30
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000004c 00000010 00000050 FDE cie=00000000 pc=00000040..00000048
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/gas/testsuite/gas/cfi/cfi-hppa-1.s b/gas/testsuite/gas/cfi/cfi-hppa-1.s
new file mode 100644
index 000000000000..923350ccb949
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-hppa-1.s
@@ -0,0 +1,66 @@
+#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o
+
+	.text
+	.align 4
+	.level 1.1
+
+.globl func_locvars
+	.type	func_locvars, @function
+func_locvars:
+	.PROC
+	.CALLINFO FRAME=0x1234,NO_CALLS,SAVE_SP,ENTRY_GR=3
+	.ENTRY
+	.cfi_startproc
+	copy %r3,%r1
+	copy %r30,%r3
+	.cfi_def_cfa_register r3
+	stwm %r1,0x1234(%r30)
+	.cfi_adjust_cfa_offset 0x1234
+	ldo 64(%r3),%r30
+	ldwm -64(%r30),%r3
+	.cfi_def_cfa_register sp
+	bv,n %r0(%r2)
+	.cfi_endproc
+	.EXIT
+	.PROCEND
+
+.globl func_prologue
+	.type	func_prologue, @function
+func_prologue:
+	.PROC
+	.CALLINFO FRAME=64,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3
+	.ENTRY
+	.cfi_startproc
+#; This is not ABI-compliant but helps the test to run on both
+#; 32-bit and 64-bit targets
+	stw %r2,-24(%r30)
+	copy %r3,%r1
+	copy %r30,%r3
+	.cfi_def_cfa_register r3
+	.cfi_offset r2, -24
+	stwm %r1,64(%r30)
+	bl func_locvars,%r2
+	nop
+	ldw -20(%r3),%r2
+	ldo 64(%r3),%r30
+	ldwm -64(%r30),%r3
+	.cfi_def_cfa_register sp
+	bv,n %r0(%r2)
+	.cfi_endproc
+	.EXIT
+	.PROCEND
+
+	.align 4
+.globl main
+	.type	main, @function
+main:
+	.PROC
+	.CALLINFO CALLS
+	.ENTRY
+	#; tail call - simple function that doesn't touch the stack
+	.cfi_startproc
+	b func_prologue
+	nop
+	.cfi_endproc
+	.EXIT
+	.PROCEND
diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d
index f34643545028..2f37a9cb6446 100644
--- a/gas/testsuite/gas/cfi/cfi-x86_64.d
+++ b/gas/testsuite/gas/cfi/cfi-x86_64.d
@@ -35,7 +35,7 @@ The section .eh_frame contains:
 
 00000050 00000014 00000054 FDE cie=00000000 pc=00000022..00000035
   DW_CFA_advance_loc: 3 to 00000025
-  DW_CFA_def_cfa_reg: r12
+  DW_CFA_def_cfa_reg: r8
   DW_CFA_advance_loc: 15 to 00000034
   DW_CFA_def_cfa_reg: r7
   DW_CFA_nop
@@ -50,3 +50,40 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
+00000090 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: -8
+  Return address column: 16
+  Augmentation data:     1b
+
+  DW_CFA_def_cfa: r7 ofs 8
+
+000000a4 00000030 00000018 FDE cie=00000090 pc=0000004d..00000058
+  DW_CFA_advance_loc: 1 to 0000004e
+  DW_CFA_def_cfa_offset: 16
+  DW_CFA_advance_loc: 1 to 0000004f
+  DW_CFA_def_cfa_reg: r8
+  DW_CFA_advance_loc: 1 to 00000050
+  DW_CFA_def_cfa_offset: 4676
+  DW_CFA_advance_loc: 1 to 00000051
+  DW_CFA_offset_extended_sf: r4 at cfa\+16
+  DW_CFA_advance_loc: 1 to 00000052
+  DW_CFA_register: r8 in r9
+  DW_CFA_advance_loc: 1 to 00000053
+  DW_CFA_remember_state
+  DW_CFA_advance_loc: 1 to 00000054
+  DW_CFA_restore: r6
+  DW_CFA_advance_loc: 1 to 00000055
+  DW_CFA_undefined: r16
+  DW_CFA_advance_loc: 1 to 00000056
+  DW_CFA_same_value: r3
+  DW_CFA_advance_loc: 1 to 00000057
+  DW_CFA_restore_state
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.s b/gas/testsuite/gas/cfi/cfi-x86_64.s
index 10035ad7f8fd..c2e2464b3630 100644
--- a/gas/testsuite/gas/cfi/cfi-x86_64.s
+++ b/gas/testsuite/gas/cfi/cfi-x86_64.s
@@ -35,9 +35,9 @@ func_prologue:
 	#; each instruction.
 	pushq	%rbp
 	.cfi_def_cfa_offset	16
-	.cfi_offset		rbp,-16
+	.cfi_offset		%rbp, -16
 	movq	%rsp, %rbp
-	.cfi_def_cfa_register	rbp
+	.cfi_def_cfa_register	%rbp
 
 	#; function body
 	call	func_locvars
@@ -46,7 +46,7 @@ func_prologue:
 	#; epilogue with valid CFI
 	#; (we're better than gcc :-)
 	leaveq
-	.cfi_def_cfa		rsp,8
+	.cfi_def_cfa		%rsp, 8
 	ret
 	.cfi_endproc
 
@@ -59,21 +59,21 @@ func_prologue:
 func_otherreg:
 	.cfi_startproc
 
-	#; save frame pointer to r12
-	movq	%rsp,%r12
-	.cfi_def_cfa_register	r12
+	#; save frame pointer to r8
+	movq	%rsp,%r8
+	.cfi_def_cfa_register	r8
 
 	#; alocate space for local vars
 	#;  (no .cfi_{def,adjust}_cfa_offset here,
-	#;   because CFA is computed from r12!)
+	#;   because CFA is computed from r8!)
 	sub	$100,%rsp
 
 	#; function body
 	call	func_prologue
 	addl	$2, %eax
 	
-	#; restore frame pointer from r12
-	movq	%r12,%rsp
+	#; restore frame pointer from r8
+	movq	%r8,%rsp
 	.cfi_def_cfa_register	rsp
 	ret
 	.cfi_endproc
@@ -105,3 +105,34 @@ _start:
 	syscall
 	hlt
 	.cfi_endproc
+
+#; func_alldirectives
+#; - test for all .cfi directives. 
+#;   This function is never called and the CFI info doesn't make sense.
+
+	.type	func_alldirectives,@function
+func_alldirectives:
+	.cfi_startproc simple
+	.cfi_def_cfa	rsp,8
+	nop
+	.cfi_def_cfa_offset	16
+	nop
+	.cfi_def_cfa_register	r8
+	nop
+	.cfi_adjust_cfa_offset	0x1234
+	nop
+	.cfi_offset	%rsi, 0x10
+	nop
+	.cfi_register	%r8, %r9
+	nop
+	.cfi_remember_state
+	nop
+	.cfi_restore %rbp
+	nop
+	.cfi_undefined %rip
+	nop
+	.cfi_same_value rbx
+	nop
+	.cfi_restore_state
+	ret
+	.cfi_endproc
diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp
index eeb551098291..b396f9e85235 100644
--- a/gas/testsuite/gas/cfi/cfi.exp
+++ b/gas/testsuite/gas/cfi/cfi.exp
@@ -1,17 +1,3 @@
-# ??? This probably shouldn't be replicated here...
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "cfi $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-        fail $testname
-        verbose "output is [file_contents "dump.out"]" 2
-        return
-    }
-    pass $testname
-}
-
 if ![is_elf_format] then {
     return
 }
@@ -61,6 +47,8 @@ if [istarget "x86_64-*"] then {
 
 } elseif { [istarget "mips*-*"] } then {
     run_dump_test "cfi-mips-1"
+} elseif { [istarget "hppa*-linux*"] } then {
+    run_dump_test "cfi-hppa-1"
 } else {
     return
 }
@@ -70,3 +58,9 @@ run_dump_test "cfi-common-1"
 run_dump_test "cfi-common-2"
 run_dump_test "cfi-common-3"
 run_dump_test "cfi-common-4"
+run_dump_test "cfi-common-5"
+
+# MIPS doesn't support PC relative cfi directives
+if { ![istarget "mips*-*"] } then {
+    run_dump_test "cfi-common-6"
+}
diff --git a/gas/testsuite/gas/cr16/add_test.d b/gas/testsuite/gas/cr16/add_test.d
new file mode 100644
index 000000000000..c2a0fe0e3c8e
--- /dev/null
+++ b/gas/testsuite/gas/cr16/add_test.d
@@ -0,0 +1,71 @@
+#as:
+#objdump:  -dr
+#name:  add_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 30       	addb	\$0xf:s,r1
+   2:	b2 30 ff 00 	addb	\$0xff:m,r2
+   6:	b1 30 ff 0f 	addb	\$0xfff:m,r1
+   a:	b1 30 14 00 	addb	\$0x14:m,r1
+   e:	a2 30       	addb	\$0xa:s,r2
+  10:	b2 30 0b 00 	addb	\$0xb:m,r2
+  14:	12 31       	addb	r1,r2
+  16:	23 31       	addb	r2,r3
+  18:	34 31       	addb	r3,r4
+  1a:	56 31       	addb	r5,r6
+  1c:	67 31       	addb	r6,r7
+  1e:	78 31       	addb	r7,r8
+  20:	f1 34       	addcb	\$0xf:s,r1
+  22:	b2 34 ff 00 	addcb	\$0xff:m,r2
+  26:	b1 34 ff 0f 	addcb	\$0xfff:m,r1
+  2a:	b1 34 14 00 	addcb	\$0x14:m,r1
+  2e:	a2 34       	addcb	\$0xa:s,r2
+  30:	b2 34 0b 00 	addcb	\$0xb:m,r2
+  34:	12 35       	addcb	r1,r2
+  36:	23 35       	addcb	r2,r3
+  38:	34 35       	addcb	r3,r4
+  3a:	56 35       	addcb	r5,r6
+  3c:	67 35       	addcb	r6,r7
+  3e:	78 35       	addcb	r7,r8
+  40:	f1 36       	addcw	\$0xf:s,r1
+  42:	b2 36 ff 00 	addcw	\$0xff:m,r2
+  46:	b1 36 ff 0f 	addcw	\$0xfff:m,r1
+  4a:	b1 36 14 00 	addcw	\$0x14:m,r1
+  4e:	a2 36       	addcw	\$0xa:s,r2
+  50:	b2 36 0b 00 	addcw	\$0xb:m,r2
+  54:	12 37       	addcw	r1,r2
+  56:	23 37       	addcw	r2,r3
+  58:	34 37       	addcw	r3,r4
+  5a:	56 37       	addcw	r5,r6
+  5c:	67 37       	addcw	r6,r7
+  5e:	78 37       	addcw	r7,r8
+  60:	f1 32       	addw	\$0xf:s,r1
+  62:	b2 32 ff 00 	addw	\$0xff:m,r2
+  66:	b1 32 ff 0f 	addw	\$0xfff:m,r1
+  6a:	b1 32 14 00 	addw	\$0x14:m,r1
+  6e:	a2 32       	addw	\$0xa:s,r2
+  70:	12 33       	addw	r1,r2
+  72:	23 33       	addw	r2,r3
+  74:	34 33       	addw	r3,r4
+  76:	56 33       	addw	r5,r6
+  78:	67 33       	addw	r6,r7
+  7a:	78 33       	addw	r7,r8
+  7c:	f1 60       	addd	\$0xf:s,\(r2,r1\)
+  7e:	b1 60 0b 00 	addd	\$0xb:m,\(r2,r1\)
+  82:	b1 60 ff 00 	addd	\$0xff:m,\(r2,r1\)
+  86:	b1 60 ff 0f 	addd	\$0xfff:m,\(r2,r1\)
+  8a:	10 04 ff ff 	addd	\$0xffff:m,\(r2,r1\)
+  8e:	1f 04 ff ff 	addd	\$0xfffff:m,\(r2,r1\)
+  92:	21 00 ff 0f 	addd	\$0xfffffff:l,\(r2,r1\)
+  96:	ff ff 
+  98:	91 60       	addd	\$-1:s,\(r2,r1\)
+  9a:	31 61       	addd	\(r4,r3\),\(r2,r1\)
+  9c:	31 61       	addd	\(r4,r3\),\(r2,r1\)
+  9e:	af 60       	addd	\$0xa:s,\(sp\)
+  a0:	ef 60       	addd	\$0xe:s,\(sp\)
+  a2:	bf 60 0b 00 	addd	\$0xb:m,\(sp\)
+  a6:	8f 60       	addd	\$0x8:s,\(sp\)
diff --git a/gas/testsuite/gas/cr16/add_test.s b/gas/testsuite/gas/cr16/add_test.s
new file mode 100644
index 000000000000..de5270db19c3
--- /dev/null
+++ b/gas/testsuite/gas/cr16/add_test.s
@@ -0,0 +1,98 @@
+        .text
+        .global main
+main:
+        ###########
+	# ADDB imm4/imm16, reg
+        ###########
+	addb    $0xf,r1
+	addb    $0xff,r2
+	addb    $0xfff,r1
+	#addb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addb    $20,r1
+	addb    $10,r2
+	addb    $11,r2
+        ###########
+	# ADDB reg, reg
+        ###########
+	addb    r1,r2
+	addb    r2,r3
+	addb    r3,r4
+	addb    r5,r6
+	addb    r6,r7
+	addb    r7,r8
+        ###########
+	# ADDCB imm4/imm16, reg
+        ###########
+	addcb    $0xf,r1
+	addcb    $0xff,r2
+	addcb    $0xfff,r1
+	#addcb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addcb    $20,r1
+	addcb    $10,r2
+	addcb    $11,r2
+        ###########
+	# ADDCB reg, reg
+        ###########
+	addcb    r1,r2
+	addcb    r2,r3
+	addcb    r3,r4
+	addcb    r5,r6
+	addcb    r6,r7
+	addcb    r7,r8
+        ###########
+	# ADDCW imm4/imm16, reg
+        ###########
+	addcw    $0xf,r1
+	addcw    $0xff,r2
+	addcw    $0xfff,r1
+	#addcw    $0xffff,r2 # check with CRASM 4.1
+	addcw    $20,r1
+	addcw    $10,r2
+	addcw    $11,r2
+        ###########
+	# ADDCW reg, reg
+        ###########
+	addcw    r1,r2
+	addcw    r2,r3
+	addcw    r3,r4
+	addcw    r5,r6
+	addcw    r6,r7
+	addcw    r7,r8
+        ###########
+	# ADDW imm4/imm16, reg
+        ###########
+	addw    $0xf,r1
+	addw    $0xff,r2
+	addw    $0xfff,r1
+	#addw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	addw    $20,r1
+	addw    $10,r2
+        ###########
+	# ADDW reg, reg
+        ###########
+	addw    r1,r2
+	addw    r2,r3
+	addw    r3,r4
+	addw    r5,r6
+	addw    r6,r7
+	addw    r7,r8
+        ###########
+	# ADDD imm4/imm16/imm20/imm32, regp
+        ###########
+	addd    $0xf,(r2,r1)
+	addd    $0xB,(r2,r1)
+	addd    $0xff,(r2,r1)
+	addd    $0xfff,(r2,r1)
+	addd    $0xffff,(r2,r1)
+	addd    $0xfffff,(r2,r1)
+	addd    $0xfffffff,(r2,r1)
+	addd    $0xffffffff,(r2,r1)
+        ###########
+	# ADDD regp, regp
+        ###########
+	addd    (r4,r3),(r2,r1)
+	addd    (r4,r3),(r2,r1)
+	addd    $10,(sp)
+	addd    $14,(sp)
+	addd    $11,(sp)
+	addd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/and_test.d b/gas/testsuite/gas/cr16/and_test.d
new file mode 100644
index 000000000000..f8e1f27f57bf
--- /dev/null
+++ b/gas/testsuite/gas/cr16/and_test.d
@@ -0,0 +1,55 @@
+#as:
+#objdump:  -dr
+#name:  and_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 20       	andb	\$0xf:s,r1
+   2:	b2 20 ff 00 	andb	\$0xff:m,r2
+   6:	b1 20 ff 0f 	andb	\$0xfff:m,r1
+   a:	b2 20 ff ff 	andb	\$0xffff:m,r2
+   e:	b1 20 14 00 	andb	\$0x14:m,r1
+  12:	a2 20       	andb	\$0xa:s,r2
+  14:	12 21       	andb	r1,r2
+  16:	23 21       	andb	r2,r3
+  18:	34 21       	andb	r3,r4
+  1a:	56 21       	andb	r5,r6
+  1c:	67 21       	andb	r6,r7
+  1e:	78 21       	andb	r7,r8
+  20:	f1 22       	andw	\$0xf:s,r1
+  22:	b2 22 ff 00 	andw	\$0xff:m,r2
+  26:	b1 22 ff 0f 	andw	\$0xfff:m,r1
+  2a:	b2 22 ff ff 	andw	\$0xffff:m,r2
+  2e:	b1 22 14 00 	andw	\$0x14:m,r1
+  32:	a2 22       	andw	\$0xa:s,r2
+  34:	12 23       	andw	r1,r2
+  36:	23 23       	andw	r2,r3
+  38:	34 23       	andw	r3,r4
+  3a:	56 23       	andw	r5,r6
+  3c:	67 23       	andw	r6,r7
+  3e:	78 23       	andw	r7,r8
+  40:	41 00 00 00 	andd	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	41 00 00 00 	andd	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	41 00 00 00 	andd	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	41 00 00 00 	andd	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	41 00 0f 00 	andd	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	41 00 ff 0f 	andd	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	41 00 ff ff 	andd	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 b0 	andd	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 b0 	andd	\(r4,r3\),\(r2,r1\)
+  72:	4f 00 00 00 	andd	\$0xa:l,\(sp\)
+  76:	0a 00 
+  78:	4f 00 00 00 	andd	\$0xe:l,\(sp\)
+  7c:	0e 00 
+  7e:	4f 00 00 00 	andd	\$0x8:l,\(sp\)
+  82:	08 00 
diff --git a/gas/testsuite/gas/cr16/and_test.s b/gas/testsuite/gas/cr16/and_test.s
new file mode 100644
index 000000000000..b21fdb7fec63
--- /dev/null
+++ b/gas/testsuite/gas/cr16/and_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# ANDB imm4/imm16, reg
+        ###########
+	andb    $0xf,r1
+	andb    $0xff,r2
+	andb    $0xfff,r1
+	andb    $0xffff,r2
+	andb    $20,r1
+	andb    $10,r2
+        ###########
+	# ANDB reg, reg
+        ###########
+	andb    r1,r2
+	andb    r2,r3
+	andb    r3,r4
+	andb    r5,r6
+	andb    r6,r7
+	andb    r7,r8
+        ###########
+	# ANDW imm4/imm16, reg
+        ###########
+	andw    $0xf,r1
+	andw    $0xff,r2
+	andw    $0xfff,r1
+	andw    $0xffff,r2
+	andw    $20,r1
+	andw    $10,r2
+        ###########
+	# ANDW reg, reg
+        ###########
+	andw    r1,r2
+	andw    r2,r3
+	andw    r3,r4
+	andw    r5,r6
+	andw    r6,r7
+	andw    r7,r8
+        ###########
+	# ANDD imm4/imm16/imm32, regp
+        ###########
+	andd    $0xf,(r2,r1)
+	andd    $0xff,(r2,r1)
+	andd    $0xfff,(r2,r1)
+	andd    $0xffff,(r2,r1)
+	andd    $0xfffff,(r2,r1)
+	andd    $0xfffffff,(r2,r1)
+	andd    $0xffffffff,(r2,r1)
+        ###########
+	# ANDD regp, regp
+        ###########
+	andd    (r4,r3),(r2,r1)
+	andd    (r4,r3),(r2,r1)
+	andd    $10,(sp)
+	andd    $14,(sp)
+	andd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/ash_test.d b/gas/testsuite/gas/cr16/ash_test.d
new file mode 100644
index 000000000000..2818012f7b13
--- /dev/null
+++ b/gas/testsuite/gas/cr16/ash_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  ash_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 40       	ashub	\$7:s,r1
+   2:	91 40       	ashub	\$-7:s,r1
+   4:	41 40       	ashub	\$4:s,r1
+   6:	c1 40       	ashub	\$-4:s,r1
+   8:	81 40       	ashub	\$-8:s,r1
+   a:	31 40       	ashub	\$3:s,r1
+   c:	d1 40       	ashub	\$-3:s,r1
+   e:	21 41       	ashub	r2,r1
+  10:	34 41       	ashub	r3,r4
+  12:	56 41       	ashub	r5,r6
+  14:	8a 41       	ashub	r8,r10
+  16:	71 42       	ashuw	\$7:s,r1
+  18:	91 43       	ashuw	\$-7:s,r1
+  1a:	41 42       	ashuw	\$4:s,r1
+  1c:	c1 43       	ashuw	\$-4:s,r1
+  1e:	81 42       	ashuw	\$8:s,r1
+  20:	81 43       	ashuw	\$-8:s,r1
+  22:	31 42       	ashuw	\$3:s,r1
+  24:	d1 43       	ashuw	\$-3:s,r1
+  26:	21 45       	ashuw	r2,r1
+  28:	34 45       	ashuw	r3,r4
+  2a:	56 45       	ashuw	r5,r6
+  2c:	8a 45       	ashuw	r8,r10
+  2e:	72 4c       	ashud	\$7:s,\(r3,r2\)
+  30:	92 4f       	ashud	\$-7:s,\(r3,r2\)
+  32:	82 4c       	ashud	\$8:s,\(r3,r2\)
+  34:	82 4f       	ashud	\$-8:s,\(r3,r2\)
+  36:	42 4c       	ashud	\$4:s,\(r3,r2\)
+  38:	c2 4f       	ashud	\$-4:s,\(r3,r2\)
+  3a:	c2 4c       	ashud	\$12:s,\(r3,r2\)
+  3c:	42 4f       	ashud	\$-12:s,\(r3,r2\)
+  3e:	31 4c       	ashud	\$3:s,\(r2,r1\)
+  40:	d1 4f       	ashud	\$-3:s,\(r2,r1\)
+  42:	41 48       	ashud	r4,\(r2,r1\)
+  44:	51 48       	ashud	r5,\(r2,r1\)
+  46:	61 48       	ashud	r6,\(r2,r1\)
+  48:	81 48       	ashud	r8,\(r2,r1\)
+  4a:	11 48       	ashud	r1,\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/ash_test.s b/gas/testsuite/gas/cr16/ash_test.s
new file mode 100644
index 000000000000..dc3e794929ca
--- /dev/null
+++ b/gas/testsuite/gas/cr16/ash_test.s
@@ -0,0 +1,59 @@
+        .text
+        .global main
+main:
+	#####################################
+	# ASHUB cnt(left +)/cnt (right -), reg
+	#####################################
+        ashub   $7,r1
+        ashub   $-7,r1
+        ashub   $4,r1
+        ashub   $-4,r1
+        ashub	$-8,r1
+        ashub   $3,r1
+        ashub   $-3,r1
+	#####################################
+	# ASHUB reg, reg
+	#####################################
+        ashub   r2,r1
+        ashub   r3,r4
+        ashub   r5,r6
+        ashub   r8,r10
+	#####################################
+	# ASHUW cnt(left +)/cnt (right -), reg
+	#####################################
+        ashuw   $7,r1
+        ashuw   $-7,r1
+        ashuw   $4,r1
+        ashuw   $-4,r1
+        ashuw	$8,r1
+        ashuw	$-8,r1
+        ashuw   $3,r1
+        ashuw   $-3,r1
+	#####################################
+	# ASHUW reg, reg
+	#####################################
+        ashuw   r2,r1
+        ashuw   r3,r4
+        ashuw   r5,r6
+        ashuw   r8,r10
+	#####################################
+	# ASHUD cnt(left +)/cnt (right -), regp
+	#####################################
+        ashud   $7, (r3,r2)
+        ashud   $-7, (r3,r2)
+        ashud   $8, (r3,r2)
+        ashud   $-8, (r3,r2)
+        ashud   $4, (r3,r2)
+        ashud   $-4, (r3,r2)
+        ashud   $12,(r3,r2)
+        ashud   $-12,(r3,r2)
+        ashud	$3,(r2,r1)
+        ashud	$-3,(r2,r1)
+	#####################################
+	# ASHUD reg, regp
+	#####################################
+        ashud   r4,(r2,r1)
+        ashud   r5,(r2,r1)
+        ashud   r6,(r2,r1)
+        ashud   r8,(r2,r1)
+        ashud   r1,(r2,r1)
diff --git a/gas/testsuite/gas/cr16/bal_test.d b/gas/testsuite/gas/cr16/bal_test.d
new file mode 100644
index 000000000000..eb1558de9829
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bal_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  bal_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	0f c0 22 f1 	bal	\(ra\),\*\+0xff122 <main\+0xff122>:m
+   4:	ff c0 26 f1 	bal	\(ra\),\*\+0xfff12a <main\+0xfff12a>:m
+   8:	00 c0 22 00 	bal	\(ra\),\*\+0x2a <main\+0x2a>:m
+   c:	00 c0 22 01 	bal	\(ra\),\*\+0x12e <main\+0x12e>:m
+  10:	00 c0 22 f1 	bal	\(ra\),\*\+0xf132 <main\+0xf132>:m
+  14:	00 c0 2a 81 	bal	\(ra\),\*\+0x813e <main\+0x813e>:m
+  18:	10 00 00 20 	bal	\(r1,r0\),\*\+0x13a <main\+0x13a>:l
+  1c:	22 01 
+  1e:	10 00 ac 2f 	bal	\(r11,r10\),\*\+0xcff140 <main\+0xcff140>:l
+  22:	22 f1 
+  24:	10 00 6a 2f 	bal	\(r7,r6\),\*\+0xaff146 <main\+0xaff146>:l
+  28:	22 f1 
+  2a:	10 00 38 2f 	bal	\(r4,r3\),\*\+0x8ff14c <main\+0x8ff14c>:l
+  2e:	22 f1 
+  30:	10 00 7f 2f 	bal	\(r8,r7\),\*\+0xfff152 <main\+0xfff152>:l
+  34:	22 f1 
diff --git a/gas/testsuite/gas/cr16/bal_test.s b/gas/testsuite/gas/cr16/bal_test.s
new file mode 100644
index 000000000000..b89f1f6baa65
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bal_test.s
@@ -0,0 +1,14 @@
+        .text

+        .global main

+main:

+bal     (ra),*+0xff122

+bal     (ra),*+0xfff126

+bal     (ra),*+0x22

+bal     (ra),*+0x122

+bal     (ra),*+0xf122

+bal     (ra),*+0x812a

+bal	(r1,r0),*+0x122

+bal	(r11,r10),*+0xcff122

+bal	(r7,r6),*+0xaff122

+bal	(r4,r3),*+0x8ff122

+bal	(r8,r7),*+0xfff122

diff --git a/gas/testsuite/gas/cr16/bcc_test.d b/gas/testsuite/gas/cr16/bcc_test.d
new file mode 100644
index 000000000000..4613edf92d4d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bcc_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  bcc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	01 11       	beq	\*\+0x22 <main\+0x22>:s
+   2:	19 11       	bne	\*\+0x34 <main\+0x34>:s
+   4:	32 12       	bcc	\*\+0x48 <main\+0x48>:s
+   6:	3a 12       	bcc	\*\+0x5a <main\+0x5a>:s
+   8:	43 13       	bhi	\*\+0x6e <main\+0x6e>:s
+   a:	cb 13       	blt	\*\+0x80 <main\+0x80>:s
+   c:	64 14       	bgt	\*\+0x94 <main\+0x94>:s
+   e:	8d 14       	bfs	\*\+0xa8 <main\+0xa8>:s
+  10:	95 15       	bfc	\*\+0xba <main\+0xba>:s
+  12:	a0 18 bc 01 	blo	\*\+0x1ce <main\+0x1ce>:m
+  16:	40 18 cc 01 	bhi	\*\+0x1e2 <main\+0x1e2>:m
+  1a:	c0 18 d6 01 	blt	\*\+0x1f0 <main\+0x1f0>:m
+  1e:	d0 18 e6 01 	bge	\*\+0x204 <main\+0x204>:m
+  22:	eb 17       	br	\*\+0x118 <main\+0x118>:s
+  24:	00 18 12 01 	beq	\*\+0x136 <main\+0x136>:m
+  28:	00 18 12 1f 	beq	\*\+0x1f3a <main\+0x1f3a>:m
+  2c:	00 18 22 0f 	beq	\*\+0xf4e <main\+0xf4e>:m
+  30:	10 18 34 0f 	bne	\*\+0xf64 <main\+0xf64>:m
+  34:	30 18 44 0f 	bcc	\*\+0xf78 <main\+0xf78>:m
+  38:	30 18 56 0f 	bcc	\*\+0xf8e <main\+0xf8e>:m
+  3c:	40 18 66 0f 	bhi	\*\+0xfa2 <main\+0xfa2>:m
+  40:	c0 18 78 0f 	blt	\*\+0xfb8 <main\+0xfb8>:m
+  44:	60 18 88 0f 	bgt	\*\+0xfcc <main\+0xfcc>:m
+  48:	80 18 9a 0f 	bfs	\*\+0xfe2 <main\+0xfe2>:m
+  4c:	90 18 aa 0f 	bfc	\*\+0xff6 <main\+0xff6>:m
+  50:	a0 18 bc 1f 	blo	\*\+0x200c <main\+0x200c>:m
+  54:	40 18 cc 1f 	bhi	\*\+0x2020 <main\+0x2020>:m
+  58:	c0 18 da 1f 	blt	\*\+0x2032 <main\+0x2032>:m
+  5c:	d0 18 ea 1f 	bge	\*\+0x2046 <main\+0x2046>:m
+  60:	e0 18 fa ff 	br	\*\+0x1005a <main\+0x1005a>:m
+  64:	10 00 0f 0f 	beq	\*\+0xff1f76 <main\+0xff1f76>:l
+  68:	12 1f 
+  6a:	10 00 0a 0a 	beq	\*\+0xaa0f8c <main\+0xaa0f8c>:l
+  6e:	22 0f 
+  70:	10 00 1b 0b 	bne	\*\+0xbb0fa4 <main\+0xbb0fa4>:l
+  74:	34 0f 
+  76:	10 00 3c 0c 	bcc	\*\+0xcc0fba <main\+0xcc0fba>:l
+  7a:	44 0f 
+  7c:	10 00 3d 0d 	bcc	\*\+0xdd0fd2 <main\+0xdd0fd2>:l
+  80:	56 0f 
+  82:	10 00 49 09 	bhi	\*\+0x990fe8 <main\+0x990fe8>:l
+  86:	66 0f 
+  88:	10 00 c8 08 	blt	\*\+0x881000 <main\+0x881000>:l
+  8c:	78 0f 
+  8e:	10 00 67 07 	bgt	\*\+0x771016 <main\+0x771016>:l
+  92:	88 0f 
+  94:	10 00 86 06 	bfs	\*\+0x66102e <main\+0x66102e>:l
+  98:	9a 0f 
+  9a:	10 00 95 05 	bfc	\*\+0x551044 <main\+0x551044>:l
+  9e:	aa 0f 
+  a0:	10 00 a4 04 	blo	\*\+0x44205c <main\+0x44205c>:l
+  a4:	bc 1f 
+  a6:	10 00 43 03 	bhi	\*\+0x332072 <main\+0x332072>:l
+  aa:	cc 1f 
+  ac:	10 00 c2 02 	blt	\*\+0x22208a <main\+0x22208a>:l
+  b0:	de 1f 
+  b2:	10 00 d1 01 	bge	\*\+0x1120a0 <main\+0x1120a0>:l
+  b6:	ee 1f 
+  b8:	10 00 e0 0f 	br	\*\+0x1000b6 <main\+0x1000b6>:l
+  bc:	fe ff 
diff --git a/gas/testsuite/gas/cr16/bcc_test.s b/gas/testsuite/gas/cr16/bcc_test.s
new file mode 100644
index 000000000000..50f3fbe01d58
--- /dev/null
+++ b/gas/testsuite/gas/cr16/bcc_test.s
@@ -0,0 +1,59 @@
+        .text

+        .global main

+main:

+	###################

+	# bcc disp9/disp17/disp25

+	###################

+	# bcc disp9

+	###################

+	beq	*+0x022

+	bne	*+0x032

+	bcc	*+0x044

+	bcc	*+0x054

+	bhi	*+0x066

+	blt	*+0x076

+	bgt	*+0x088

+	bfs	*+0x09a

+	bfc	*+0x0aa

+	blo	*+0x1bc

+	bhi	*+0x1cc

+	blt	*+0x1d6

+	bge	*+0x1e6

+	br	*+0x0f6

+	###################

+	# bcc disp17

+	###################

+	beq	*+0x112

+	beq	*+0x1f12

+	beq	*+0x0f22

+	bne	*+0x0f34

+	bcc	*+0x0f44

+	bcc	*+0x0f56

+	bhi	*+0x0f66

+	blt	*+0x0f78

+	bgt	*+0x0f88

+	bfs	*+0x0f9a

+	bfc	*+0x0faa

+	blo	*+0x1fbc

+	bhi	*+0x1fcc

+	blt	*+0x1fda

+	bge	*+0x1fea

+	br	*+0xfffa

+	###################

+	# bcc disp25

+	###################

+	beq	*+0xff1f12

+	beq	*+0xaa0f22

+	bne	*+0xbb0f34

+	bcc	*+0xcc0f44

+	bcc	*+0xdd0f56

+	bhi	*+0x990f66

+	blt	*+0x880f78

+	bgt	*+0x770f88

+	bfs	*+0x660f9a

+	bfc	*+0x550faa

+	blo	*+0x441fbc

+	bhi	*+0x331fcc

+	blt	*+0x221fde

+	bge	*+0x111fee

+	br	*+0x0ffffe

diff --git a/gas/testsuite/gas/cr16/beq0_test.d b/gas/testsuite/gas/cr16/beq0_test.d
new file mode 100644
index 000000000000..82f923c01412
--- /dev/null
+++ b/gas/testsuite/gas/cr16/beq0_test.d
@@ -0,0 +1,15 @@
+#as:
+#objdump:  -dr
+#name:  beq0_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 0c       	beq0b	r1,\*\+0x10 <main\+0x10>:s
+   2:	b1 0c       	beq0b	r1,\*\+0x18 <main\+0x18>:s
+   4:	e1 0c       	beq0b	r1,\*\+0x1e <main\+0x1e>:s
+   6:	71 0e       	beq0w	r1,\*\+0x10 <main\+0x10>:s
+   8:	b1 0e       	beq0w	r1,\*\+0x18 <main\+0x18>:s
+   a:	e1 0e       	beq0w	r1,\*\+0x1e <main\+0x1e>:s
diff --git a/gas/testsuite/gas/cr16/beq0_test.s b/gas/testsuite/gas/cr16/beq0_test.s
new file mode 100644
index 000000000000..70e9f6ab6ed5
--- /dev/null
+++ b/gas/testsuite/gas/cr16/beq0_test.s
@@ -0,0 +1,15 @@
+        .text
+        .global main
+main:
+	###################
+	# beq0b reg, dispu5
+	###################
+	beq0b	r1,*+16
+	beq0b	r1,*+24
+	beq0b	r1,*+30
+	###################
+	# beq0w reg, dispu5
+	###################
+	beq0w	r1,*+16
+	beq0w	r1,*+24
+	beq0w	r1,*+30
diff --git a/gas/testsuite/gas/cr16/cbitb_test.d b/gas/testsuite/gas/cr16/cbitb_test.d
new file mode 100644
index 000000000000..bbb382e503c0
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  cbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 6b cd 0b 	cbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 6b cd ab 	cbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f 7a 	cbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 68 14 00 	cbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 68 fc ab 	cbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 68 34 12 	cbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 68 34 12 	cbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 68 34 00 	cbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 6a 3a 4a 	cbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 6a 3a 4a 	cbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 6a 5a 4b 	cbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 6a 1a 41 	cbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 6a 14 01 	cbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 6a 	cbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e 60 	cbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 60 	cbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f 60 	cbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 40 	cbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 6b 34 00 	cbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 6b ab 00 	cbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 40 	cbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 40 	cbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 40 	cbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 40 	cbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 6b ff 0f 	cbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 6b ff 0f 	cbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 6b ff ff 	cbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 6b 43 23 	cbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 41 	cbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 44 	cbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d 5f 	cbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 4f 	cbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 4f 	cbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 44 	cbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 6a       	cbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 6b 01 00 	cbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 6b 34 12 	cbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 6b 34 12 	cbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 51 	cbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 6b 23 01 	cbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 51 	cbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/cbitb_test.s b/gas/testsuite/gas/cr16/cbitb_test.s
new file mode 100644
index 000000000000..1e65ef304f2a
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	cbitb $4,0xbcd
+	cbitb $5,0xaabcd
+	cbitb $3,0xfaabcd
+
+	cbitb $5,[r12]0x14
+	cbitb $4,[r13]0xabfc
+	cbitb $3,[r12]0x1234
+	cbitb $3,[r13]0x1234
+	cbitb $3,[r12]0x34
+
+	cbitb $3,[r12]0xa7a(r1,r0)
+	cbitb $3,[r12]0xa7a(r3,r2)
+	cbitb $3,[r12]0xa7a(r4,r3)
+	cbitb $3,[r12]0xa7a(r5,r4)
+	cbitb $3,[r12]0xa7a(r6,r5)
+	cbitb $3,[r12]0xa7a(r7,r6)
+	cbitb $3,[r12]0xa7a(r9,r8)
+	cbitb $3,[r12]0xa7a(r11,r10)
+	cbitb $3,[r13]0xa7a(r1,r0)
+	cbitb $3,[r13]0xa7a(r3,r2)
+	cbitb $3,[r13]0xa7a(r4,r3)
+	cbitb $3,[r13]0xa7a(r5,r4)
+	cbitb $3,[r13]0xa7a(r6,r5)
+	cbitb $3,[r13]0xa7a(r7,r6)
+	cbitb $3,[r13]0xa7a(r9,r8)
+	cbitb $3,[r13]0xa7a(r11,r10)
+	cbitb $5,[r13]0xb7a(r4,r3)
+	cbitb $1,[r12]0x17a(r6,r5)
+	cbitb $1,[r13]0x134(r6,r5)
+	cbitb $3,[r12]0xabcde(r4,r3)
+	cbitb $5,[r13]0xabcd(r4,r3)
+	cbitb $3,[r12]0xabcd(r6,r5)
+	cbitb $3,[r13]0xbcde(r6,r5)
+
+	cbitb $5,0x0(r2)
+	cbitb $3,0x34(r12)
+	cbitb $3,0xab(r13)
+	cbitb $5,0xad(r1)
+	cbitb $5,0xcd(r2)
+	cbitb $5,0xfff(r0)
+	cbitb $3,0xbcd(r4)
+	cbitb $3,0xfff(r12)
+	cbitb $3,0xfff(r13)
+	cbitb $3,0xffff(r13)
+	cbitb $3,0x2343(r12)
+	cbitb $3,0x12345(r2)
+	cbitb $3,0x4abcd(r8)
+	cbitb $3,0xfabcd(r13)
+	cbitb $3,0xfabcd(r8)
+	cbitb $3,0xfabcd(r9)
+	cbitb $3,0x4abcd(r9)
+
+	cbitb $3,0x0(r2,r1)
+	cbitb $5,0x1(r2,r1)
+	cbitb $4,0x1234(r2,r1)
+	cbitb $3,0x1234(r2,r1)
+	cbitb $3,0x12345(r2,r1)
+	cbitb $3,0x123(r2,r1)
+	cbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/cbitw_test.d b/gas/testsuite/gas/cr16/cbitw_test.d
new file mode 100644
index 000000000000..55e1543cd954
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  cbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 6f cd 0b 	cbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 6f cd ab 	cbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f 7a 	cbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 6f cd 0b 	cbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 6f cd ab 	cbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef 7a 	cbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 6c 14 00 	cbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 6d fc ab 	cbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 6c 34 12 	cbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 6d 34 12 	cbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 6c 34 00 	cbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 6c 14 00 	cbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 6d fc ab 	cbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 6c 34 12 	cbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 6d 34 12 	cbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 6c 34 00 	cbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 6a 3a 4a 	cbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 6a 3a 4a 	cbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 6a 5a 4b 	cbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 6a 1a 41 	cbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 6a 14 01 	cbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 6a 	cbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e 60 	cbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 60 	cbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f 60 	cbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 6a da 4a 	cbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 6a da 4a 	cbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 6a fa 4b 	cbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 6a ba 41 	cbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 6a b4 01 	cbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 6a 	cbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe 60 	cbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 60 	cbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df 60 	cbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 40 	cbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 69 34 00 	cbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 69 ab 00 	cbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 40 	cbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 40 	cbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 40 	cbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 40 	cbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 69 ff 0f 	cbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 69 ff 0f 	cbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 69 ff ff 	cbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 69 43 23 	cbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 41 	cbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 44 	cbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d 5f 	cbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 4f 	cbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 4f 	cbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 44 	cbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 40 	cbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 69 34 00 	cbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 69 ab 00 	cbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 40 	cbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 40 	cbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 40 	cbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 40 	cbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 69 ff 0f 	cbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 69 ff 0f 	cbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 69 ff ff 	cbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 69 43 23 	cbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 41 	cbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 44 	cbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd 5f 	cbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 4f 	cbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 4f 	cbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 44 	cbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 6e       	cbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 69 01 00 	cbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 69 34 12 	cbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 69 34 12 	cbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 51 	cbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 69 23 01 	cbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 51 	cbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 6e       	cbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 69 01 00 	cbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 69 34 12 	cbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 69 34 12 	cbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 51 	cbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 69 23 01 	cbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 51 	cbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/cbitw_test.s b/gas/testsuite/gas/cr16/cbitw_test.s
new file mode 100644
index 000000000000..61bda0874904
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	cbitw $4,0xbcd
+	cbitw $5,0xaabcd
+	cbitw $3,0xfaabcd
+	cbitw $10,0xbcd
+	cbitw $15,0xaabcd
+	cbitw $14,0xfaabcd
+
+	cbitw $5,[r12]0x14
+	cbitw $4,[r13]0xabfc
+	cbitw $3,[r12]0x1234
+	cbitw $3,[r13]0x1234
+	cbitw $3,[r12]0x34
+	cbitw $15,[r12]0x14
+	cbitw $14,[r13]0xabfc
+	cbitw $13,[r12]0x1234
+	cbitw $13,[r13]0x1234
+	cbitw $11,[r12]0x34
+
+	cbitw $3,[r12]0xa7a(r1,r0)
+	cbitw $3,[r12]0xa7a(r3,r2)
+	cbitw $3,[r12]0xa7a(r4,r3)
+	cbitw $3,[r12]0xa7a(r5,r4)
+	cbitw $3,[r12]0xa7a(r6,r5)
+	cbitw $3,[r12]0xa7a(r7,r6)
+	cbitw $3,[r12]0xa7a(r9,r8)
+	cbitw $3,[r12]0xa7a(r11,r10)
+	cbitw $3,[r13]0xa7a(r1,r0)
+	cbitw $3,[r13]0xa7a(r3,r2)
+	cbitw $3,[r13]0xa7a(r4,r3)
+	cbitw $3,[r13]0xa7a(r5,r4)
+	cbitw $3,[r13]0xa7a(r6,r5)
+	cbitw $3,[r13]0xa7a(r7,r6)
+	cbitw $3,[r13]0xa7a(r9,r8)
+	cbitw $3,[r13]0xa7a(r11,r10)
+	cbitw $5,[r13]0xb7a(r4,r3)
+	cbitw $1,[r12]0x17a(r6,r5)
+	cbitw $1,[r13]0x134(r6,r5)
+	cbitw $3,[r12]0xabcde(r4,r3)
+	cbitw $5,[r13]0xabcd(r4,r3)
+	cbitw $3,[r12]0xabcd(r6,r5)
+	cbitw $3,[r13]0xbcde(r6,r5)
+	cbitw $13,[r12]0xa7a(r1,r0)
+	cbitw $13,[r12]0xa7a(r3,r2)
+	cbitw $13,[r12]0xa7a(r4,r3)
+	cbitw $13,[r12]0xa7a(r5,r4)
+	cbitw $13,[r12]0xa7a(r6,r5)
+	cbitw $13,[r12]0xa7a(r7,r6)
+	cbitw $13,[r12]0xa7a(r9,r8)
+	cbitw $13,[r12]0xa7a(r11,r10)
+	cbitw $13,[r13]0xa7a(r1,r0)
+	cbitw $13,[r13]0xa7a(r3,r2)
+	cbitw $13,[r13]0xa7a(r4,r3)
+	cbitw $13,[r13]0xa7a(r5,r4)
+	cbitw $13,[r13]0xa7a(r6,r5)
+	cbitw $13,[r13]0xa7a(r7,r6)
+	cbitw $13,[r13]0xa7a(r9,r8)
+	cbitw $13,[r13]0xa7a(r11,r10)
+	cbitw $15,[r13]0xb7a(r4,r3)
+	cbitw $11,[r12]0x17a(r6,r5)
+	cbitw $11,[r13]0x134(r6,r5)
+	cbitw $13,[r12]0xabcde(r4,r3)
+	cbitw $15,[r13]0xabcd(r4,r3)
+	cbitw $13,[r12]0xabcd(r6,r5)
+	cbitw $13,[r13]0xbcde(r6,r5)
+
+	cbitw $5,0x0(r2)
+	cbitw $3,0x34(r12)
+	cbitw $3,0xab(r13)
+	cbitw $5,0xad(r1)
+	cbitw $5,0xcd(r2)
+	cbitw $5,0xfff(r0)
+	cbitw $3,0xbcd(r4)
+	cbitw $3,0xfff(r12)
+	cbitw $3,0xfff(r13)
+	cbitw $3,0xffff(r13)
+	cbitw $3,0x2343(r12)
+	cbitw $3,0x12345(r2)
+	cbitw $3,0x4abcd(r8)
+	cbitw $3,0xfabcd(r13)
+	cbitw $3,0xfabcd(r8)
+	cbitw $3,0xfabcd(r9)
+	cbitw $3,0x4abcd(r9)
+	cbitw $15,0x0(r2)
+	cbitw $13,0x34(r12)
+	cbitw $13,0xab(r13)
+	cbitw $15,0xad(r1)
+	cbitw $15,0xcd(r2)
+	cbitw $15,0xfff(r0)
+	cbitw $13,0xbcd(r4)
+	cbitw $13,0xfff(r12)
+	cbitw $13,0xfff(r13)
+	cbitw $13,0xffff(r13)
+	cbitw $13,0x2343(r12)
+	cbitw $13,0x12345(r2)
+	cbitw $13,0x4abcd(r8)
+	cbitw $13,0xfabcd(r13)
+	cbitw $13,0xfabcd(r8)
+	cbitw $13,0xfabcd(r9)
+	cbitw $13,0x4abcd(r9)
+
+	cbitw $3,0x0(r2,r1)
+	cbitw $5,0x1(r2,r1)
+	cbitw $4,0x1234(r2,r1)
+	cbitw $3,0x1234(r2,r1)
+	cbitw $3,0x12345(r2,r1)
+	cbitw $3,0x123(r2,r1)
+	cbitw $3,0x12345(r2,r1)
+	cbitw $13,0x0(r2,r1)
+	cbitw $15,0x1(r2,r1)
+	cbitw $14,0x1234(r2,r1)
+	cbitw $13,0x1234(r2,r1)
+	cbitw $13,0x12345(r2,r1)
+	cbitw $13,0x123(r2,r1)
+	cbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/cinv_test.d b/gas/testsuite/gas/cr16/cinv_test.d
new file mode 100644
index 000000000000..f1e2f253b5a3
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cinv_test.d
@@ -0,0 +1,15 @@
+#as:
+#objdump:  -dr
+#name:  cinv_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	0a 00       	cinv    \[i\]
+   2:	0b 00       	cinv    \[i,u\]
+   4:	0c 00       	cinv    \[d\]
+   6:	0d 00       	cinv    \[d,u\]
+   8:	0e 00       	cinv    \[d,i\]
+   a:	0f 00       	cinv    \[d,i,u\]
diff --git a/gas/testsuite/gas/cr16/cinv_test.s b/gas/testsuite/gas/cr16/cinv_test.s
new file mode 100644
index 000000000000..eda4b97bad23
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cinv_test.s
@@ -0,0 +1,12 @@
+        .text

+        .global main

+main:

+	##############################

+	# cin [i/i,u/d/d,u/d,i/d,i,u]

+	##############################

+	cinv   [i]

+	cinv   [i,u]

+	cinv   [d]

+	cinv   [d,u]

+	cinv   [d,i]

+	cinv   [d,i,u]

diff --git a/gas/testsuite/gas/cr16/cmp_test.d b/gas/testsuite/gas/cr16/cmp_test.d
new file mode 100644
index 000000000000..6c3e101740be
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cmp_test.d
@@ -0,0 +1,51 @@
+#as:
+#objdump:  -dr
+#name:  cmp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 50       	cmpb	\$0xf:s,r1
+   2:	b2 50 ff 00 	cmpb	\$0xff:m,r2
+   6:	b1 50 ff 0f 	cmpb	\$0xfff:m,r1
+   a:	b1 50 14 00 	cmpb	\$0x14:m,r1
+   e:	a2 50       	cmpb	\$0xa:s,r2
+  10:	b2 50 0b 00 	cmpb	\$0xb:m,r2
+  14:	12 51       	cmpb	r1,r2
+  16:	23 51       	cmpb	r2,r3
+  18:	34 51       	cmpb	r3,r4
+  1a:	56 51       	cmpb	r5,r6
+  1c:	67 51       	cmpb	r6,r7
+  1e:	78 51       	cmpb	r7,r8
+  20:	f1 52       	cmpw	\$0xf:s,r1
+  22:	b1 52 0b 00 	cmpw	\$0xb:m,r1
+  26:	b2 52 ff 00 	cmpw	\$0xff:m,r2
+  2a:	b1 52 ff 0f 	cmpw	\$0xfff:m,r1
+  2e:	b1 52 14 00 	cmpw	\$0x14:m,r1
+  32:	a2 52       	cmpw	\$0xa:s,r2
+  34:	b2 52 0b 00 	cmpw	\$0xb:m,r2
+  38:	12 53       	cmpw	r1,r2
+  3a:	23 53       	cmpw	r2,r3
+  3c:	34 53       	cmpw	r3,r4
+  3e:	56 53       	cmpw	r5,r6
+  40:	67 53       	cmpw	r6,r7
+  42:	78 53       	cmpw	r7,r8
+  44:	f1 56       	cmpd	\$0xf:s,\(r2,r1\)
+  46:	b1 56 0b 00 	cmpd	\$0xb:m,\(r2,r1\)
+  4a:	b1 56 ff 00 	cmpd	\$0xff:m,\(r2,r1\)
+  4e:	b1 56 ff 0f 	cmpd	\$0xfff:m,\(r2,r1\)
+  52:	91 00 00 00 	cmpd	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	91 00 0f 00 	cmpd	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	91 00 ff 0f 	cmpd	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	91 56       	cmpd	\$-1:s,\(r2,r1\)
+  66:	31 57       	cmpd	\(r4,r3\),\(r2,r1\)
+  68:	31 57       	cmpd	\(r4,r3\),\(r2,r1\)
+  6a:	af 56       	cmpd	\$0xa:s,\(sp\)
+  6c:	ef 56       	cmpd	\$0xe:s,\(sp\)
+  6e:	bf 56 0b 00 	cmpd	\$0xb:m,\(sp\)
+  72:	8f 56       	cmpd	\$0x8:s,\(sp\)
diff --git a/gas/testsuite/gas/cr16/cmp_test.s b/gas/testsuite/gas/cr16/cmp_test.s
new file mode 100644
index 000000000000..2d0af3bce71d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cmp_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+        ###########
+	# CMPB imm4/imm16, reg
+        ###########
+	cmpb    $0xf,r1
+	cmpb    $0xff,r2
+	cmpb    $0xfff,r1
+	#cmpb    $0xffff,r2 // CHCEFK WITH CRASM 4.1
+	cmpb    $20,r1
+	cmpb    $10,r2
+	cmpb    $11,r2
+        ###########
+	# CMPB reg, reg
+        ###########
+	cmpb    r1,r2
+	cmpb    r2,r3
+	cmpb    r3,r4
+	cmpb    r5,r6
+	cmpb    r6,r7
+	cmpb    r7,r8
+        ###########
+	# CMPW imm4/imm16, reg
+        ###########
+	cmpw    $0xf,r1
+	cmpw    $0xB,r1
+	cmpw    $0xff,r2
+	cmpw    $0xfff,r1
+	#cmpw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	cmpw    $20,r1
+	cmpw    $10,r2
+	cmpw    $11,r2
+        ###########
+	# CMPW reg, reg
+        ###########
+	cmpw    r1,r2
+	cmpw    r2,r3
+	cmpw    r3,r4
+	cmpw    r5,r6
+	cmpw    r6,r7
+	cmpw    r7,r8
+        ###########
+	# CMPD imm4/imm16/imm32, regp
+        ###########
+	cmpd    $0xf,(r2,r1)
+	cmpd    $0xB,(r2,r1)
+	cmpd    $0xff,(r2,r1)
+	cmpd    $0xfff,(r2,r1)
+	cmpd    $0xffff,(r2,r1)
+	cmpd    $0xfffff,(r2,r1)
+	cmpd    $0xfffffff,(r2,r1)
+	cmpd    $0xffffffff,(r2,r1)
+        ###########
+	# CMPD regp, regp
+        ###########
+	cmpd    (r4,r3),(r2,r1)
+	cmpd    (r4,r3),(r2,r1)
+	cmpd    $10,(sp)
+	cmpd    $14,(sp)
+	cmpd    $11,(sp)
+	cmpd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/cr16.exp b/gas/testsuite/gas/cr16/cr16.exp
new file mode 100644
index 000000000000..6697c33d6aee
--- /dev/null
+++ b/gas/testsuite/gas/cr16/cr16.exp
@@ -0,0 +1,27 @@
+#
+# Driver for CR16 assembler testsuite
+#
+
+proc run_list_test { name opts } {
+  global srcdir subdir
+  set testname "cr16 $name"
+  set file $srcdir/$subdir/$name
+  gas_run ${name}.s $opts ">&dump.out"
+  if {[regexp_diff "dump.out" "${file}.l"] } {
+    fail $testname
+    verbose "output is [file_contents "dump.out"]" 2
+    return
+  }
+  pass $testname
+}
+
+if ![istarget cr16-*-*] {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach test $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $test]
+    run_dump_test [file rootname $test]
+}
diff --git a/gas/testsuite/gas/cr16/excp_test.d b/gas/testsuite/gas/cr16/excp_test.d
new file mode 100644
index 000000000000..7c4053b8aa58
--- /dev/null
+++ b/gas/testsuite/gas/cr16/excp_test.d
@@ -0,0 +1,18 @@
+#as:
+#objdump:  -dr
+#name:  excp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c5 00       	excp	svc
+   2:	c6 00       	excp	dvz
+   4:	c7 00       	excp	flg
+   6:	c8 00       	excp	bpt
+   8:	c9 00       	excp	trc
+   a:	ca 00       	excp	und
+   c:	cc 00       	excp	iad
+   e:	ce 00       	excp	dbg
+  10:	cf 00       	excp	ise
diff --git a/gas/testsuite/gas/cr16/excp_test.s b/gas/testsuite/gas/cr16/excp_test.s
new file mode 100644
index 000000000000..4984a749ed20
--- /dev/null
+++ b/gas/testsuite/gas/cr16/excp_test.s
@@ -0,0 +1,15 @@
+        .text
+        .global main
+main:
+	##########################################
+	# excp svc/dvz/flg/bpt/trc/und/iad/dbg/ise
+	##########################################
+	excp	svc
+	excp	dvz
+	excp	flg
+	excp	bpt
+	excp	trc
+	excp	und
+	excp	iad
+	excp	dbg
+	excp	ise
diff --git a/gas/testsuite/gas/cr16/jal_test.d b/gas/testsuite/gas/cr16/jal_test.d
new file mode 100644
index 000000000000..51a4e7637c6c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jal_test.d
@@ -0,0 +1,14 @@
+#as:
+#objdump:  -dr
+#name:  jal_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	d1 00       	jal	\(r2,r1\)
+   2:	14 00 15 80 	jal	\(r6,r5\),\(r2,r1\)
+   6:	14 00 32 80 	jal	\(r3,r2\),\(r4,r3\)
+   a:	14 00 30 80 	jal	\(r1,r0\),\(r4,r3\)
+   e:	14 00 72 80 	jal	\(r3,r2\),\(r8,r7\)
diff --git a/gas/testsuite/gas/cr16/jal_test.s b/gas/testsuite/gas/cr16/jal_test.s
new file mode 100644
index 000000000000..2a4715b98f4e
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jal_test.s
@@ -0,0 +1,11 @@
+        .text
+        .global main
+main:
+	################
+	# JAL regp regp
+	################
+	jal (r2,r1)
+	jal (r6,r5),(r2,r1)
+	jal (r3,r2),(r4,r3)
+	jal (r1,r0), (r4,r3)
+	jal (r3,r2), (r8,r7)
diff --git a/gas/testsuite/gas/cr16/jcc_test.d b/gas/testsuite/gas/cr16/jcc_test.d
new file mode 100644
index 000000000000..e192c9db0ac3
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jcc_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  jcc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 0a       	jeq	\(r1,r0\)
+   2:	11 0a       	jne	\(r2,r1\)
+   4:	32 0a       	jcc	\(r3,r2\)
+   6:	33 0a       	jcc	\(r4,r3\)
+   8:	44 0a       	jhi	\(r5,r4\)
+   a:	c5 0a       	jlt	\(r6,r5\)
+   c:	66 0a       	jgt	\(r7,r6\)
+   e:	87 0a       	jfs	\(r8,r7\)
+  10:	98 0a       	jfc	\(r9,r8\)
+  12:	a9 0a       	jlo	\(r10,r9\)
+  14:	4a 0a       	jhi	\(r11,r10\)
+  16:	c0 0a       	jlt	\(r1,r0\)
+  18:	d2 0a       	jge	\(r3,r2\)
+  1a:	e5 0a       	jump	\(r6,r5\)
+  1c:	f5 0a       	jusr	\(r6,r5\)
diff --git a/gas/testsuite/gas/cr16/jcc_test.s b/gas/testsuite/gas/cr16/jcc_test.s
new file mode 100644
index 000000000000..c384e1a9daa2
--- /dev/null
+++ b/gas/testsuite/gas/cr16/jcc_test.s
@@ -0,0 +1,21 @@
+        .text
+        .global main
+main:
+	##########
+	# JCond regp
+	##########
+	jeq	(r1,r0)
+	jne	(r2,r1)
+	jcc	(r3,r2)
+	jcc	(r4,r3)
+	jhi	(r5,r4)
+	jlt	(r6,r5)
+	jgt	(r7,r6)
+	jfs	(r8,r7)
+	jfc	(r9,r8)
+	jlo	(r10,r9)
+	jhi	(r11,r10)
+	jlt	(r1,r0)
+	jge	(r3,r2)
+	jump	(r6,r5)
+	jusr	(r6,r5)
diff --git a/gas/testsuite/gas/cr16/loadb_test.d b/gas/testsuite/gas/cr16/loadb_test.d
new file mode 100644
index 000000000000..0e22d5743b0f
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadb_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadd_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 88 00 00 	loadb	0x0 <main>:m,r0
+   4:	10 88 ff 00 	loadb	0xff <main\+0xff>:m,r1
+   8:	30 88 ff 0f 	loadb	0xfff <main\+0xfff>:m,r3
+   c:	40 88 34 12 	loadb	0x1234 <main\+0x1234>:m,r4
+  10:	50 88 34 12 	loadb	0x1234 <main\+0x1234>:m,r5
+  14:	12 00 07 7a 	loadb	0x7a1234 <main\+0x7a1234>:l,r0
+  18:	34 12 
+  1a:	12 00 1b 7a 	loadb	0xba1234 <main\+0xba1234>:l,r1
+  1e:	34 12 
+  20:	2f 88 ff ff 	loadb	0xfffff <main\+0xfffff>:m,r2
+  24:	00 8a 00 00 	loadb	\[r12\]0x0:m,r0
+  28:	00 8b 00 00 	loadb	\[r12\]0x0:m,r0
+  2c:	10 8a ff 00 	loadb	\[r12\]0xff:m,r1
+  30:	10 8b ff 00 	loadb	\[r12\]0xff:m,r1
+  34:	30 8a ff 0f 	loadb	\[r12\]0xfff:m,r3
+  38:	30 8b ff 0f 	loadb	\[r12\]0xfff:m,r3
+  3c:	40 8a 34 12 	loadb	\[r13\]0x1234:m,r4
+  40:	40 8b 34 12 	loadb	\[r13\]0x1234:m,r4
+  44:	50 8a 34 12 	loadb	\[r13\]0x1234:m,r5
+  48:	50 8b 34 12 	loadb	\[r13\]0x1234:m,r5
+  4c:	20 8a 67 45 	loadb	\[r12\]0x4567:m,r2
+  50:	2a 8b 34 12 	loadb	\[r12\]0xa1234:m,r2
+  54:	10 b4       	loadb	0x4:s\(r1,r0\),r1
+  56:	32 b4       	loadb	0x4:s\(r3,r2\),r3
+  58:	40 bf 34 12 	loadb	0x1234:m\(r1,r0\),r4
+  5c:	52 bf 34 12 	loadb	0x1234:m\(r3,r2\),r5
+  60:	12 00 60 5a 	loadb	0xa1234:l\(r1,r0\),r6
+  64:	34 12 
+  66:	18 00 10 5f 	loadb	0xffffc:l\(r1,r0\),r1
+  6a:	fc ff 
+  6c:	18 00 32 5f 	loadb	0xffffc:l\(r3,r2\),r3
+  70:	fc ff 
+  72:	18 00 40 5f 	loadb	0xfedcc:l\(r1,r0\),r4
+  76:	cc ed 
+  78:	18 00 52 5f 	loadb	0xfedcc:l\(r3,r2\),r5
+  7c:	cc ed 
+  7e:	18 00 60 55 	loadb	0x5edcc:l\(r1,r0\),r6
+  82:	cc ed 
+  84:	00 b0       	loadb	0x0:s\(r1,r0\),r0
+  86:	10 b0       	loadb	0x0:s\(r1,r0\),r1
+  88:	00 bf 0f 00 	loadb	0xf:m\(r1,r0\),r0
+  8c:	10 bf 0f 00 	loadb	0xf:m\(r1,r0\),r1
+  90:	20 bf 34 12 	loadb	0x1234:m\(r1,r0\),r2
+  94:	32 bf cd ab 	loadb	0xabcd:m\(r3,r2\),r3
+  98:	43 bf ff af 	loadb	0xafff:m\(r4,r3\),r4
+  9c:	12 00 55 5a 	loadb	0xa1234:l\(r6,r5\),r5
+  a0:	34 12 
+  a2:	18 00 00 5f 	loadb	0xffff1:l\(r1,r0\),r0
+  a6:	f1 ff 
+  a8:	18 00 10 5f 	loadb	0xffff1:l\(r1,r0\),r1
+  ac:	f1 ff 
+  ae:	18 00 20 5f 	loadb	0xfedcc:l\(r1,r0\),r2
+  b2:	cc ed 
+  b4:	18 00 32 5f 	loadb	0xf5433:l\(r3,r2\),r3
+  b8:	33 54 
+  ba:	18 00 43 5f 	loadb	0xf5001:l\(r4,r3\),r4
+  be:	01 50 
+  c0:	18 00 55 55 	loadb	0x5edcc:l\(r6,r5\),r5
+  c4:	cc ed 
+  c6:	00 be       	loadb	\[r12\]0x0:s\(r1,r0\),r0
+  c8:	18 be       	loadb	\[r13\]0x0:s\(r1,r0\),r1
+  ca:	70 86 04 12 	loadb	\[r12\]0x234:m\(r1,r0\),r7
+  ce:	12 00 38 61 	loadb	\[r13\]0x1abcd:l\(r1,r0\),r3
+  d2:	cd ab 
+  d4:	12 00 40 6a 	loadb	\[r12\]0xa1234:l\(r1,r0\),r4
+  d8:	34 12 
+  da:	12 00 58 6b 	loadb	\[r13\]0xb1234:l\(r1,r0\),r5
+  de:	34 12 
+  e0:	12 00 68 6f 	loadb	\[r13\]0xfffff:l\(r1,r0\),r6
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadb_test.s b/gas/testsuite/gas/cr16/loadb_test.s
new file mode 100644
index 000000000000..258e3b380048
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadb_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadb abs20/24 reg

+	######################

+	loadb 0x0,r0

+	loadb 0xff,r1

+	loadb 0xfff,r3

+	loadb 0x1234,r4

+	loadb 0x1234,r5

+	loadb 0x7A1234,r0

+	loadb 0xBA1234,r1

+	loadb 0xffffff,r2

+	######################

+	#  loadb abs20 rel reg

+	######################

+	loadb [r12]0x0,r0

+	loadb [r13]0x0,r0

+	loadb [r12]0xff,r1

+	loadb [r13]0xff,r1

+	loadb [r12]0xfff,r3

+	loadb [r13]0xfff,r3

+	loadb [r12]0x1234,r4

+	loadb [r13]0x1234,r4

+	loadb [r12]0x1234,r5

+	loadb [r13]0x1234,r5

+	loadb [r12]0x4567,r2

+	loadb [r13]0xA1234,r2

+	###################################

+	#  loadb rbase(disp20/-disp20)  reg

+	###################################

+	loadb 0x4(r1,r0),r1

+	loadb 0x4(r3,r2),r3

+	loadb 0x1234(r1,r0),r4

+	loadb 0x1234(r3,r2),r5

+	loadb 0xA1234(r1,r0),r6

+	loadb -0x4(r1,r0),r1

+	loadb -0x4(r3,r2),r3

+	loadb -0x1234(r1,r0),r4

+	loadb -0x1234(r3,r2),r5

+	loadb -0xA1234(r1,r0),r6

+	#################################################

+	#  loadb rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadb 0x0(r1,r0),r0

+	loadb 0x0(r1,r0),r1

+	loadb 0xf(r1,r0),r0

+	loadb 0xf(r1,r0),r1

+	loadb 0x1234(r1,r0),r2

+	loadb 0xabcd(r3,r2),r3

+	loadb 0xAfff(r4,r3),r4

+	loadb 0xA1234(r6,r5),r5

+	loadb -0xf(r1,r0),r0

+	loadb -0xf(r1,r0),r1

+	loadb -0x1234(r1,r0),r2

+	loadb -0xabcd(r3,r2),r3

+	loadb -0xAfff(r4,r3),r4

+	loadb -0xA1234(r6,r5),r5

+	####################################

+	#  loadb rbase(disp0/disp14) rel reg

+	####################################

+	loadb [r12]0x0(r1,r0),r0

+	loadb [r13]0x0(r1,r0),r1

+	loadb [r12]0x1234(r1,r0),r2

+	loadb [r13]0x1abcd(r1,r0),r3

+	#################################

+	#  loadb rpbase(disp20) rel reg

+	#################################

+	loadb [r12]0xA1234(r1,r0),r4

+	loadb [r13]0xB1234(r1,r0),r5

+	loadb [r13]0xfffff(r1,r0),r6

diff --git a/gas/testsuite/gas/cr16/loadd_test.d b/gas/testsuite/gas/cr16/loadd_test.d
new file mode 100644
index 000000000000..77ea45fc8b6d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadd_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadd_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 87 00 00 	loadd	0x0 <main>:m,\(r1,r0\)
+   4:	00 87 ff 00 	loadd	0xff <main\+0xff>:m,\(r1,r0\)
+   8:	20 87 ff 0f 	loadd	0xfff <main\+0xfff>:m,\(r3,r2\)
+   c:	30 87 34 12 	loadd	0x1234 <main\+0x1234>:m,\(r4,r3\)
+  10:	40 87 34 12 	loadd	0x1234 <main\+0x1234>:m,\(r5,r4\)
+  14:	12 00 07 ba 	loadd	0x7a1234 <main\+0x7a1234>:l,\(r1,r0\)
+  18:	34 12 
+  1a:	12 00 0b ba 	loadd	0xba1234 <main\+0xba1234>:l,\(r1,r0\)
+  1e:	34 12 
+  20:	1f 87 ff ff 	loadd	0xfffff <main\+0xfffff>:m,\(r2,r1\)
+  24:	00 8c 00 00 	loadd	\[r12\]0x0:m,\(r1,r0\)
+  28:	00 8d 00 00 	loadd	\[r12\]0x0:m,\(r1,r0\)
+  2c:	00 8c ff 00 	loadd	\[r12\]0xff:m,\(r1,r0\)
+  30:	00 8d ff 00 	loadd	\[r12\]0xff:m,\(r1,r0\)
+  34:	20 8c ff 0f 	loadd	\[r12\]0xfff:m,\(r3,r2\)
+  38:	20 8d ff 0f 	loadd	\[r12\]0xfff:m,\(r3,r2\)
+  3c:	30 8c 34 12 	loadd	\[r12\]0x1234:m,\(r4,r3\)
+  40:	30 8d 34 12 	loadd	\[r12\]0x1234:m,\(r4,r3\)
+  44:	40 8c 34 12 	loadd	\[r13\]0x1234:m,\(r5,r4\)
+  48:	40 8d 34 12 	loadd	\[r13\]0x1234:m,\(r5,r4\)
+  4c:	10 8c 67 45 	loadd	\[r12\]0x4567:m,\(r2,r1\)
+  50:	1a 8d 34 12 	loadd	\[r12\]0xa1234:m,\(r2,r1\)
+  54:	10 a2       	loadd	0x4:s\(r1,r0\),\(r2,r1\)
+  56:	22 a2       	loadd	0x4:s\(r3,r2\),\(r3,r2\)
+  58:	30 af 34 12 	loadd	0x1234:m\(r1,r0\),\(r4,r3\)
+  5c:	42 af 34 12 	loadd	0x1234:m\(r3,r2\),\(r5,r4\)
+  60:	12 00 50 9a 	loadd	0xa1234:l\(r1,r0\),\(r6,r5\)
+  64:	34 12 
+  66:	18 00 10 9f 	loadd	0xffffc:l\(r1,r0\),\(r2,r1\)
+  6a:	fc ff 
+  6c:	18 00 22 9f 	loadd	0xffffc:l\(r3,r2\),\(r3,r2\)
+  70:	fc ff 
+  72:	18 00 30 9f 	loadd	0xfedcc:l\(r1,r0\),\(r4,r3\)
+  76:	cc ed 
+  78:	18 00 42 9f 	loadd	0xfedcc:l\(r3,r2\),\(r5,r4\)
+  7c:	cc ed 
+  7e:	18 00 50 95 	loadd	0x5edcc:l\(r1,r0\),\(r6,r5\)
+  82:	cc ed 
+  84:	00 a0       	loadd	0x0:s\(r1,r0\),\(r1,r0\)
+  86:	00 a0       	loadd	0x0:s\(r1,r0\),\(r1,r0\)
+  88:	00 af 0f 00 	loadd	0xf:m\(r1,r0\),\(r1,r0\)
+  8c:	00 af 0f 00 	loadd	0xf:m\(r1,r0\),\(r1,r0\)
+  90:	10 af 34 12 	loadd	0x1234:m\(r1,r0\),\(r2,r1\)
+  94:	22 af cd ab 	loadd	0xabcd:m\(r3,r2\),\(r3,r2\)
+  98:	33 af ff af 	loadd	0xafff:m\(r4,r3\),\(r4,r3\)
+  9c:	12 00 65 9a 	loadd	0xa1234:l\(r6,r5\),\(r7,r6\)
+  a0:	34 12 
+  a2:	18 00 00 9f 	loadd	0xffff1:l\(r1,r0\),\(r1,r0\)
+  a6:	f1 ff 
+  a8:	18 00 00 9f 	loadd	0xffff1:l\(r1,r0\),\(r1,r0\)
+  ac:	f1 ff 
+  ae:	18 00 10 9f 	loadd	0xfedcc:l\(r1,r0\),\(r2,r1\)
+  b2:	cc ed 
+  b4:	18 00 22 9f 	loadd	0xf5433:l\(r3,r2\),\(r3,r2\)
+  b8:	33 54 
+  ba:	18 00 43 9f 	loadd	0xf5001:l\(r4,r3\),\(r5,r4\)
+  be:	01 50 
+  c0:	18 00 45 95 	loadd	0x5edcc:l\(r6,r5\),\(r5,r4\)
+  c4:	cc ed 
+  c6:	00 ae       	loadd	\[r12\]0x0:s\(r1,r0\),\(r1,r0\)
+  c8:	08 ae       	loadd	\[r13\]0x0:s\(r1,r0\),\(r1,r0\)
+  ca:	b0 86 04 12 	loadd	\[r12\]0x234:m\(r1,r0\),\(r12,r11\)
+  ce:	12 00 28 a1 	loadd	\[r13\]0x1abcd:l\(r1,r0\),\(r3,r2\)
+  d2:	cd ab 
+  d4:	12 00 20 aa 	loadd	\[r12\]0xa1234:l\(r1,r0\),\(r3,r2\)
+  d8:	34 12 
+  da:	12 00 38 ab 	loadd	\[r13\]0xb1234:l\(r1,r0\),\(r4,r3\)
+  de:	34 12 
+  e0:	12 00 48 af 	loadd	\[r13\]0xfffff:l\(r1,r0\),\(r5,r4\)
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadd_test.s b/gas/testsuite/gas/cr16/loadd_test.s
new file mode 100644
index 000000000000..677752d7522d
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadd_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadd abs20/24 regp

+	######################

+	loadd 0x0,(r1,r0)

+	loadd 0xff,(r1,r0)

+	loadd 0xfff,(r3,r2)

+	loadd 0x1234,(r4,r3)

+	loadd 0x1234,(r5,r4)

+	loadd 0x7A1234,(r1,r0)

+	loadd 0xBA1234,(r1,r0)

+	loadd 0xffffff,(r2,r1)

+	######################

+	#  loadd abs20 rel regp

+	######################

+	loadd [r12]0x0,(r1,r0)

+	loadd [r13]0x0,(r1,r0)

+	loadd [r12]0xff,(r1,r0)

+	loadd [r13]0xff,(r1,r0)

+	loadd [r12]0xfff,(r3,r2)

+	loadd [r13]0xfff,(r3,r2)

+	loadd [r12]0x1234,(r4,r3)

+	loadd [r13]0x1234,(r4,r3)

+	loadd [r12]0x1234,(r5,r4)

+	loadd [r13]0x1234,(r5,r4)

+	loadd [r12]0x4567,(r2,r1)

+	loadd [r13]0xA1234,(r2,r1)

+	###################################

+	#  loadd rbase(disp20/-disp20)  regp

+	###################################

+	loadd 0x4(r1,r0),(r2,r1)

+	loadd 0x4(r3,r2),(r3,r2)

+	loadd 0x1234(r1,r0),(r4,r3)

+	loadd 0x1234(r3,r2),(r5,r4)

+	loadd 0xA1234(r1,r0),(r6,r5)

+	loadd -0x4(r1,r0),(r2,r1)

+	loadd -0x4(r3,r2),(r3,r2)

+	loadd -0x1234(r1,r0),(r4,r3)

+	loadd -0x1234(r3,r2),(r5,r4)

+	loadd -0xA1234(r1,r0),(r6,r5)

+	#################################################

+	#  loadd rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadd 0x0(r1,r0),(r1,r0)

+	loadd 0x0(r1,r0),(r1,r0)

+	loadd 0xf(r1,r0),(r1,r0)

+	loadd 0xf(r1,r0),(r1,r0)

+	loadd 0x1234(r1,r0),(r2,r1)

+	loadd 0xabcd(r3,r2),(r3,r2)

+	loadd 0xAfff(r4,r3),(r4,r3)

+	loadd 0xA1234(r6,r5),(r7,r6)

+	loadd -0xf(r1,r0),(r1,r0)

+	loadd -0xf(r1,r0),(r1,r0)

+	loadd -0x1234(r1,r0),(r2,r1)

+	loadd -0xabcd(r3,r2),(r3,r2)

+	loadd -0xAfff(r4,r3),(r5,r4)

+	loadd -0xA1234(r6,r5),(r5,r4)

+	####################################

+	#  loadd rbase(disp0/disp14) rel reg

+	####################################

+	loadd [r12]0x0(r1,r0),(r1,r0)

+	loadd [r13]0x0(r1,r0),(r1,r0)

+	loadd [r12]0x1234(r1,r0),(r2,r1)

+	loadd [r13]0x1abcd(r1,r0),(r3,r2)

+	#################################

+	#  loadd rpbase(disp20) rel reg

+	#################################

+	loadd [r12]0xA1234(r1,r0),(r3,r2)

+	loadd [r13]0xB1234(r1,r0),(r4,r3)

+	loadd [r13]0xfffff(r1,r0),(r5,r4)

diff --git a/gas/testsuite/gas/cr16/loadm_test.d b/gas/testsuite/gas/cr16/loadm_test.d
new file mode 100644
index 000000000000..7d7ff3e99994
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadm_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  loadm_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	a0 00       	loadm	\$0x1,r0
+   2:	a1 00       	loadm	\$0x2,r0
+   4:	a2 00       	loadm	\$0x3,r0
+   6:	a3 00       	loadm	\$0x4,r0
+   8:	a4 00       	loadm	\$0x5,r0
+   a:	a5 00       	loadm	\$0x6,r0
+   c:	a6 00       	loadm	\$0x7,r0
+   e:	a7 00       	loadm	\$0x8,r0
+  10:	a8 00       	loadmp	\$0x1,r0
+  12:	a9 00       	loadmp	\$0x2,r0
+  14:	aa 00       	loadmp	\$0x3,r0
+  16:	ab 00       	loadmp	\$0x4,r0
+  18:	ac 00       	loadmp	\$0x5,r0
+  1a:	ad 00       	loadmp	\$0x6,r0
+  1c:	ae 00       	loadmp	\$0x7,r0
+  1e:	af 00       	loadmp	\$0x8,r0
diff --git a/gas/testsuite/gas/cr16/loadm_test.s b/gas/testsuite/gas/cr16/loadm_test.s
new file mode 100644
index 000000000000..3549e2049c2c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadm_test.s
@@ -0,0 +1,25 @@
+        .text
+        .global main
+main:
+	##############
+	# loadm cnt
+	##############
+ 	loadm $1
+ 	loadm $2
+ 	loadm $3
+ 	loadm $4
+ 	loadm $5
+ 	loadm $6
+ 	loadm $7
+ 	loadm $8
+	##############
+	# loadmp cnt
+	##############
+ 	loadmp $1
+ 	loadmp $2
+ 	loadmp $3
+ 	loadmp $4
+ 	loadmp $5
+ 	loadmp $6
+ 	loadmp $7
+ 	loadmp $8
diff --git a/gas/testsuite/gas/cr16/loadw_test.d b/gas/testsuite/gas/cr16/loadw_test.d
new file mode 100644
index 000000000000..cc4f311ae991
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadw_test.d
@@ -0,0 +1,79 @@
+#as:
+#objdump:  -dr
+#name:  loadw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 89 00 00 	loadw	0x0 <main>:m,r0
+   4:	10 89 ff 00 	loadw	0xff <main\+0xff>:m,r1
+   8:	30 89 ff 0f 	loadw	0xfff <main\+0xfff>:m,r3
+   c:	40 89 34 12 	loadw	0x1234 <main\+0x1234>:m,r4
+  10:	50 89 34 12 	loadw	0x1234 <main\+0x1234>:m,r5
+  14:	12 00 07 fa 	loadw	0x7a1234 <main\+0x7a1234>:l,r0
+  18:	34 12 
+  1a:	12 00 1b fa 	loadw	0xba1234 <main\+0xba1234>:l,r1
+  1e:	34 12 
+  20:	2f 89 ff ff 	loadw	0xfffff <main\+0xfffff>:m,r2
+  24:	00 8e 00 00 	loadw	\[r12\]0x0:m,r0
+  28:	00 8f 00 00 	loadw	\[r12\]0x0:m,r0
+  2c:	10 8e ff 00 	loadw	\[r12\]0xff:m,r1
+  30:	10 8f ff 00 	loadw	\[r12\]0xff:m,r1
+  34:	30 8e ff 0f 	loadw	\[r12\]0xfff:m,r3
+  38:	30 8f ff 0f 	loadw	\[r12\]0xfff:m,r3
+  3c:	40 8e 34 12 	loadw	\[r13\]0x1234:m,r4
+  40:	40 8f 34 12 	loadw	\[r13\]0x1234:m,r4
+  44:	50 8e 34 12 	loadw	\[r13\]0x1234:m,r5
+  48:	50 8f 34 12 	loadw	\[r13\]0x1234:m,r5
+  4c:	20 8e 67 45 	loadw	\[r12\]0x4567:m,r2
+  50:	2a 8f 34 12 	loadw	\[r12\]0xa1234:m,r2
+  54:	10 92       	loadw	0x4:s\(r1,r0\),r1
+  56:	32 92       	loadw	0x4:s\(r3,r2\),r3
+  58:	40 9f 34 12 	loadw	0x1234:m\(r1,r0\),r4
+  5c:	52 9f 34 12 	loadw	0x1234:m\(r3,r2\),r5
+  60:	12 00 60 da 	loadw	0xa1234:l\(r1,r0\),r6
+  64:	34 12 
+  66:	18 00 10 df 	loadw	0xffffc:l\(r1,r0\),r1
+  6a:	fc ff 
+  6c:	18 00 32 df 	loadw	0xffffc:l\(r3,r2\),r3
+  70:	fc ff 
+  72:	18 00 40 df 	loadw	0xfedcc:l\(r1,r0\),r4
+  76:	cc ed 
+  78:	18 00 52 df 	loadw	0xfedcc:l\(r3,r2\),r5
+  7c:	cc ed 
+  7e:	18 00 60 d5 	loadw	0x5edcc:l\(r1,r0\),r6
+  82:	cc ed 
+  84:	00 90       	loadw	0x0:s\(r1,r0\),r0
+  86:	10 90       	loadw	0x0:s\(r1,r0\),r1
+  88:	00 9f 0f 00 	loadw	0xf:m\(r1,r0\),r0
+  8c:	10 9f 0f 00 	loadw	0xf:m\(r1,r0\),r1
+  90:	20 9f 34 12 	loadw	0x1234:m\(r1,r0\),r2
+  94:	32 9f cd ab 	loadw	0xabcd:m\(r3,r2\),r3
+  98:	43 9f ff af 	loadw	0xafff:m\(r4,r3\),r4
+  9c:	12 00 55 da 	loadw	0xa1234:l\(r6,r5\),r5
+  a0:	34 12 
+  a2:	18 00 00 df 	loadw	0xffff1:l\(r1,r0\),r0
+  a6:	f1 ff 
+  a8:	18 00 10 df 	loadw	0xffff1:l\(r1,r0\),r1
+  ac:	f1 ff 
+  ae:	18 00 20 df 	loadw	0xfedcc:l\(r1,r0\),r2
+  b2:	cc ed 
+  b4:	18 00 32 df 	loadw	0xf5433:l\(r3,r2\),r3
+  b8:	33 54 
+  ba:	18 00 43 df 	loadw	0xf5001:l\(r4,r3\),r4
+  be:	01 50 
+  c0:	18 00 55 d5 	loadw	0x5edcc:l\(r6,r5\),r5
+  c4:	cc ed 
+  c6:	00 9e       	loadw	\[r12\]0x0:s\(r1,r0\),r0
+  c8:	18 9e       	loadw	\[r13\]0x0:s\(r1,r0\),r1
+  ca:	f0 86 04 12 	loadw	\[r12\]0x234:m\(r1,r0\),r15
+  ce:	12 00 38 e1 	loadw	\[r13\]0x1abcd:l\(r1,r0\),r3
+  d2:	cd ab 
+  d4:	12 00 40 ea 	loadw	\[r12\]0xa1234:l\(r1,r0\),r4
+  d8:	34 12 
+  da:	12 00 58 eb 	loadw	\[r13\]0xb1234:l\(r1,r0\),r5
+  de:	34 12 
+  e0:	12 00 68 ef 	loadw	\[r13\]0xfffff:l\(r1,r0\),r6
+  e4:	ff ff 
diff --git a/gas/testsuite/gas/cr16/loadw_test.s b/gas/testsuite/gas/cr16/loadw_test.s
new file mode 100644
index 000000000000..bd9a2bb0ae90
--- /dev/null
+++ b/gas/testsuite/gas/cr16/loadw_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  loadw abs20/24 reg

+	######################

+	loadw 0x0,r0

+	loadw 0xff,r1

+	loadw 0xfff,r3

+	loadw 0x1234,r4

+	loadw 0x1234,r5

+	loadw 0x7A1234,r0

+	loadw 0xBA1234,r1

+	loadw 0xffffff,r2

+	######################

+	#  loadw abs20 rel reg

+	######################

+	loadw [r12]0x0,r0

+	loadw [r13]0x0,r0

+	loadw [r12]0xff,r1

+	loadw [r13]0xff,r1

+	loadw [r12]0xfff,r3

+	loadw [r13]0xfff,r3

+	loadw [r12]0x1234,r4

+	loadw [r13]0x1234,r4

+	loadw [r12]0x1234,r5

+	loadw [r13]0x1234,r5

+	loadw [r12]0x4567,r2

+	loadw [r13]0xA1234,r2

+	###################################

+	#  loadw rbase(disp20/-disp20)  reg

+	###################################

+	loadw 0x4(r1,r0),r1

+	loadw 0x4(r3,r2),r3

+	loadw 0x1234(r1,r0),r4

+	loadw 0x1234(r3,r2),r5

+	loadw 0xA1234(r1,r0),r6

+	loadw -0x4(r1,r0),r1

+	loadw -0x4(r3,r2),r3

+	loadw -0x1234(r1,r0),r4

+	loadw -0x1234(r3,r2),r5

+	loadw -0xA1234(r1,r0),r6

+	#################################################

+	#  loadw rpbase(disp4/disp16/disp20/-disp20)  reg

+	#################################################

+	loadw 0x0(r1,r0),r0

+	loadw 0x0(r1,r0),r1

+	loadw 0xf(r1,r0),r0

+	loadw 0xf(r1,r0),r1

+	loadw 0x1234(r1,r0),r2

+	loadw 0xabcd(r3,r2),r3

+	loadw 0xAfff(r4,r3),r4

+	loadw 0xA1234(r6,r5),r5

+	loadw -0xf(r1,r0),r0

+	loadw -0xf(r1,r0),r1

+	loadw -0x1234(r1,r0),r2

+	loadw -0xabcd(r3,r2),r3

+	loadw -0xAfff(r4,r3),r4

+	loadw -0xA1234(r6,r5),r5

+	####################################

+	#  loadw rbase(disp0/disp14) rel reg

+	####################################

+	loadw [r12]0x0(r1,r0),r0

+	loadw [r13]0x0(r1,r0),r1

+	loadw [r12]0x1234(r1,r0),r2

+	loadw [r13]0x1abcd(r1,r0),r3

+	#################################

+	#  loadw rpbase(disp20) rel reg

+	#################################

+	loadw [r12]0xA1234(r1,r0),r4

+	loadw [r13]0xB1234(r1,r0),r5

+	loadw [r13]0xfffff(r1,r0),r6

diff --git a/gas/testsuite/gas/cr16/lpsp_test.d b/gas/testsuite/gas/cr16/lpsp_test.d
new file mode 100644
index 000000000000..66ca8e25e39b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lpsp_test.d
@@ -0,0 +1,57 @@
+#as:
+#objdump:  -dr
+#name:  lpsp_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	14 00 91 00 	lpr	r1,psr
+   4:	14 00 82 00 	lpr	r2,cfg
+   8:	14 00 a2 00 	lpr	r2,intbasel
+   c:	14 00 b3 00 	lpr	r3,intbaseh
+  10:	14 00 c4 00 	lpr	r4,ispl
+  14:	14 00 d5 00 	lpr	r5,isph
+  18:	14 00 e6 00 	lpr	r6,uspl
+  1c:	14 00 f7 00 	lpr	r7,usph
+  20:	14 00 18 00 	lpr	r8,dsr
+  24:	14 00 29 00 	lpr	r9,dcrl
+  28:	14 00 3a 00 	lpr	r10,dcrh
+  2c:	14 00 4b 00 	lpr	r11,car0l
+  30:	14 00 50 00 	lpr	r0,car0h
+  34:	14 00 61 00 	lpr	r1,car1l
+  38:	14 00 73 00 	lpr	r3,car1h
+  3c:	14 00 90 10 	lprd	\(r1,r0\),psr
+  40:	14 00 81 10 	lprd	\(r2,r1\),cfg
+  44:	14 00 a2 10 	lprd	\(r3,r2\),intbase
+  48:	14 00 c3 10 	lprd	\(r4,r3\),isp
+  4c:	14 00 e4 10 	lprd	\(r5,r4\),usp
+  50:	14 00 15 10 	lprd	\(r6,r5\),dsr
+  54:	14 00 26 10 	lprd	\(r7,r6\),dcr
+  58:	14 00 47 10 	lprd	\(r8,r7\),car0
+  5c:	14 00 68 10 	lprd	\(r9,r8\),car1
+  60:	14 00 90 20 	spr	psr,r0
+  64:	14 00 81 20 	spr	cfg,r1
+  68:	14 00 a2 20 	spr	intbasel,r2
+  6c:	14 00 b3 20 	spr	intbaseh,r3
+  70:	14 00 c4 20 	spr	ispl,r4
+  74:	14 00 d5 20 	spr	isph,r5
+  78:	14 00 e6 20 	spr	uspl,r6
+  7c:	14 00 f7 20 	spr	usph,r7
+  80:	14 00 18 20 	spr	dsr,r8
+  84:	14 00 29 20 	spr	dcrl,r9
+  88:	14 00 3a 20 	spr	dcrh,r10
+  8c:	14 00 4b 20 	spr	car0l,r11
+  90:	14 00 50 20 	spr	car0h,r0
+  94:	14 00 61 20 	spr	car1l,r1
+  98:	14 00 72 20 	spr	car1h,r2
+  9c:	14 00 90 30 	sprd	psr,\(r1,r0\)
+  a0:	14 00 81 30 	sprd	cfg,\(r2,r1\)
+  a4:	14 00 a2 30 	sprd	intbase,\(r3,r2\)
+  a8:	14 00 c3 30 	sprd	isp,\(r4,r3\)
+  ac:	14 00 e4 30 	sprd	usp,\(r5,r4\)
+  b0:	14 00 15 30 	sprd	dsr,\(r6,r5\)
+  b4:	14 00 26 30 	sprd	dcr,\(r7,r6\)
+  b8:	14 00 47 30 	sprd	car0,\(r8,r7\)
+  bc:	14 00 68 30 	sprd	car1,\(r9,r8\)
diff --git a/gas/testsuite/gas/cr16/lpsp_test.s b/gas/testsuite/gas/cr16/lpsp_test.s
new file mode 100644
index 000000000000..8e9d45961bca
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lpsp_test.s
@@ -0,0 +1,63 @@
+        .text

+        .global main

+main:

+	################

+	# lpr reg, preg

+	################

+	lpr	r1,psr

+	lpr	r2,cfg

+	lpr	r2,intbasel

+	lpr	r3,intbaseh

+	lpr	r4,ispl

+	lpr	r5,isph

+	lpr	r6,uspl

+	lpr	r7,usph

+	lpr	r8,dsr

+	lpr	r9,dcrl

+	lpr	r10,dcrh

+	lpr	r11,car0l

+	lpr	r0,car0h

+	lpr	r1,car1l

+	lpr	r3,car1h

+	#################

+	# lprd regp, preg

+	#################

+	lprd	(r1,r0),psr

+	lprd	(r2,r1),cfg

+	lprd	(r3,r2),intbase

+	lprd	(r4,r3),isp

+	lprd	(r5,r4),usp

+	lprd	(r6,r5),dsr

+	lprd	(r7,r6),dcr

+	lprd	(r8,r7),car0

+	lprd	(r9,r8),car1

+	#################

+	# spr preg, reg

+	#################

+	spr	psr,r0

+	spr	cfg,r1

+	spr	intbasel,r2

+	spr	intbaseh,r3

+	spr	ispl,r4

+	spr	isph,r5

+	spr	uspl,r6

+	spr	usph,r7

+	spr	dsr,r8

+	spr	dcrl,r9

+	spr	dcrh,r10

+	spr	car0l,r11

+	spr	car0h,r0

+	spr	car1l,r1

+	spr	car1h,r2

+	#################

+	# sprd preg, regp

+	#################

+	sprd	psr,(r1,r0)

+	sprd	cfg,(r2,r1)

+	sprd	intbase,(r3,r2)

+	sprd	isp,(r4,r3)

+	sprd	usp,(r5,r4)

+	sprd	dsr,(r6,r5)

+	sprd	dcr,(r7,r6)

+	sprd	car0,(r8,r7)

+	sprd	car1,(r9,r8)

diff --git a/gas/testsuite/gas/cr16/lsh_test.d b/gas/testsuite/gas/cr16/lsh_test.d
new file mode 100644
index 000000000000..aba1cda98560
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lsh_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  lsh_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	71 40       	ashub	\$7:s,r1
+   2:	91 09       	lshb	\$-7:s,r1
+   4:	41 40       	ashub	\$4:s,r1
+   6:	c1 09       	lshb	\$-4:s,r1
+   8:	81 09       	lshb	\$-8:s,r1
+   a:	31 40       	ashub	\$3:s,r1
+   c:	d1 09       	lshb	\$-3:s,r1
+   e:	21 44       	lshb	r2,r1
+  10:	34 44       	lshb	r3,r4
+  12:	56 44       	lshb	r5,r6
+  14:	8a 44       	lshb	r8,r10
+  16:	71 42       	ashuw	\$7:s,r1
+  18:	91 49       	lshw	\$-7:s,r1
+  1a:	41 42       	ashuw	\$4:s,r1
+  1c:	c1 49       	lshw	\$-4:s,r1
+  1e:	81 42       	ashuw	\$8:s,r1
+  20:	81 49       	lshw	\$-8:s,r1
+  22:	31 42       	ashuw	\$3:s,r1
+  24:	d1 49       	lshw	\$-3:s,r1
+  26:	21 46       	lshw	r2,r1
+  28:	34 46       	lshw	r3,r4
+  2a:	56 46       	lshw	r5,r6
+  2c:	8a 46       	lshw	r8,r10
+  2e:	72 4c       	ashud	\$7:s,\(r3,r2\)
+  30:	92 4b       	lshd	\$-7:s,\(r3,r2\)
+  32:	82 4c       	ashud	\$8:s,\(r3,r2\)
+  34:	82 4b       	lshd	\$-8:s,\(r3,r2\)
+  36:	42 4c       	ashud	\$4:s,\(r3,r2\)
+  38:	c2 4b       	lshd	\$-4:s,\(r3,r2\)
+  3a:	c2 4c       	ashud	\$12:s,\(r3,r2\)
+  3c:	42 4b       	lshd	\$-12:s,\(r3,r2\)
+  3e:	31 4c       	ashud	\$3:s,\(r2,r1\)
+  40:	d1 4b       	lshd	\$-3:s,\(r2,r1\)
+  42:	41 47       	lshd	r4,\(r2,r1\)
+  44:	51 47       	lshd	r5,\(r2,r1\)
+  46:	61 47       	lshd	r6,\(r2,r1\)
+  48:	81 47       	lshd	r8,\(r2,r1\)
+  4a:	11 47       	lshd	r1,\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/lsh_test.s b/gas/testsuite/gas/cr16/lsh_test.s
new file mode 100644
index 000000000000..3236cbdda758
--- /dev/null
+++ b/gas/testsuite/gas/cr16/lsh_test.s
@@ -0,0 +1,59 @@
+        .text
+        .global main
+main:
+	###########################
+	# LSHB cnt(right -), reg
+	###########################
+        lshb   $7,r1
+        lshb   $-7,r1
+        lshb   $4,r1
+        lshb   $-4,r1
+        lshb	$-8,r1
+        lshb   $3,r1
+        lshb   $-3,r1
+	###########################
+	# LSHB reg, reg
+	###########################
+        lshb   r2,r1
+        lshb   r3,r4
+        lshb   r5,r6
+        lshb   r8,r10
+	###########################
+	# LSHW cnt (right -), reg
+	###########################
+        lshw   $7,r1
+        lshw   $-7,r1
+        lshw   $4,r1
+        lshw   $-4,r1
+        lshw	$8,r1
+        lshw	$-8,r1
+        lshw   $3,r1
+        lshw   $-3,r1
+	##########################
+	# LSHW reg, reg
+	##########################
+        lshw   r2,r1
+        lshw   r3,r4
+        lshw   r5,r6
+        lshw   r8,r10
+	###########################
+	# LSHD cnt (right -), regp
+	############################
+        lshd   $7, (r3,r2)
+        lshd   $-7, (r3,r2)
+        lshd   $8, (r3,r2)
+        lshd   $-8, (r3,r2)
+        lshd   $4, (r3,r2)
+        lshd   $-4, (r3,r2)
+        lshd   $12,(r3,r2)
+        lshd   $-12,(r3,r2)
+        lshd	$3,(r2,r1)
+        lshd	$-3,(r2,r1)
+	#################
+	# LSHD reg, regp
+	#################
+        lshd   r4,(r2,r1)
+        lshd   r5,(r2,r1)
+        lshd   r6,(r2,r1)
+        lshd   r8,(r2,r1)
+        lshd   r1,(r2,r1)
diff --git a/gas/testsuite/gas/cr16/mov_test.d b/gas/testsuite/gas/cr16/mov_test.d
new file mode 100644
index 000000000000..ce253e7fa7fc
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mov_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  mov_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 58       	movb	\$0xf:s,r1
+   2:	b2 58 ff 00 	movb	\$0xff:m,r2
+   6:	b1 58 ff 0f 	movb	\$0xfff:m,r1
+   a:	b1 58 14 00 	movb	\$0x14:m,r1
+   e:	a2 58       	movb	\$0xa:s,r2
+  10:	b2 58 0b 00 	movb	\$0xb:m,r2
+  14:	12 59       	movb	r1,r2
+  16:	23 59       	movb	r2,r3
+  18:	34 59       	movb	r3,r4
+  1a:	56 59       	movb	r5,r6
+  1c:	67 59       	movb	r6,r7
+  1e:	78 59       	movb	r7,r8
+  20:	f1 5a       	movw	\$0xf:s,r1
+  22:	b1 5a 0b 00 	movw	\$0xb:m,r1
+  26:	b2 5a ff 00 	movw	\$0xff:m,r2
+  2a:	b1 5a ff 0f 	movw	\$0xfff:m,r1
+  2e:	b1 5a 14 00 	movw	\$0x14:m,r1
+  32:	a2 5a       	movw	\$0xa:s,r2
+  34:	b2 5a 0b 00 	movw	\$0xb:m,r2
+  38:	12 5b       	movw	r1,r2
+  3a:	23 5b       	movw	r2,r3
+  3c:	34 5b       	movw	r3,r4
+  3e:	56 5b       	movw	r5,r6
+  40:	67 5b       	movw	r6,r7
+  42:	78 5b       	movw	r7,r8
+  44:	f1 54       	movd	\$0xf:s,\(r2,r1\)
+  46:	b1 54 0b 00 	movd	\$0xb:m,\(r2,r1\)
+  4a:	b1 54 ff 00 	movd	\$0xff:m,\(r2,r1\)
+  4e:	b1 54 ff 0f 	movd	\$0xfff:m,\(r2,r1\)
+  52:	10 05 ff ff 	movd	\$0xffff:m,\(r2,r1\)
+  56:	1f 05 ff ff 	movd	\$0xfffff:m,\(r2,r1\)
+  5a:	71 00 ff 0f 	movd	\$0xfffffff:l,\(r2,r1\)
+  5e:	ff ff 
+  60:	91 54       	movd	\$-1:s,\(r2,r1\)
+  62:	31 55       	movd	\(r4,r3\),\(r2,r1\)
+  64:	31 55       	movd	\(r4,r3\),\(r2,r1\)
+  66:	af 54       	movd	\$0xa:s,\(sp\)
+  68:	ef 54       	movd	\$0xe:s,\(sp\)
+  6a:	bf 54 0b 00 	movd	\$0xb:m,\(sp\)
+  6e:	8f 54       	movd	\$0x8:s,\(sp\)
+  70:	12 5c       	movxb	r1,r2
+  72:	34 5c       	movxb	r3,r4
+  74:	56 5c       	movxb	r5,r6
+  76:	78 5c       	movxb	r7,r8
+  78:	9a 5c       	movxb	r9,r10
+  7a:	12 5e       	movxw	r1,\(r3,r2\)
+  7c:	33 5e       	movxw	r3,\(r4,r3\)
+  7e:	55 5e       	movxw	r5,\(r6,r5\)
+  80:	77 5e       	movxw	r7,\(r8,r7\)
+  82:	98 5e       	movxw	r9,\(r9,r8\)
+  84:	12 5d       	movzb	r1,r2
+  86:	34 5d       	movzb	r3,r4
+  88:	56 5d       	movzb	r5,r6
+  8a:	78 5d       	movzb	r7,r8
+  8c:	9a 5d       	movzb	r9,r10
+  8e:	12 5f       	movzw	r1,\(r3,r2\)
+  90:	33 5f       	movzw	r3,\(r4,r3\)
+  92:	55 5f       	movzw	r5,\(r6,r5\)
+  94:	77 5f       	movzw	r7,\(r8,r7\)
+  96:	98 5f       	movzw	r9,\(r9,r8\)
diff --git a/gas/testsuite/gas/cr16/mov_test.s b/gas/testsuite/gas/cr16/mov_test.s
new file mode 100644
index 000000000000..20fdf4d5443b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mov_test.s
@@ -0,0 +1,94 @@
+        .text
+        .global main
+main:
+        ###########
+	# MOVB imm4/imm16, reg
+        ###########
+	movb    $0xf,r1
+	movb    $0xff,r2
+	movb    $0xfff,r1
+	#movb    $0xffff,r2 // CHECK WITH CRASM 4.1
+	movb    $20,r1
+	movb    $10,r2
+	movb    $11,r2
+        ###########
+	# MOVB reg, reg
+        ###########
+	movb    r1,r2
+	movb    r2,r3
+	movb    r3,r4
+	movb    r5,r6
+	movb    r6,r7
+	movb    r7,r8
+        ###########
+	# MOVW imm4/imm16, reg
+        ###########
+	movw    $0xf,r1
+	movw    $0xB,r1
+	movw    $0xff,r2
+	movw    $0xfff,r1
+	#movw    $0xffff,r2 // CHECK WITH CRASM 4.1
+	movw    $20,r1
+	movw    $10,r2
+	movw    $11,r2
+        ###########
+	# MOVW reg, reg
+        ###########
+	movw    r1,r2
+	movw    r2,r3
+	movw    r3,r4
+	movw    r5,r6
+	movw    r6,r7
+	movw    r7,r8
+        ###########
+	# MOVD imm4/imm16/imm20/imm32, regp
+        ###########
+	movd    $0xf,(r2,r1)
+	movd    $0xB,(r2,r1)
+	movd    $0xff,(r2,r1)
+	movd    $0xfff,(r2,r1)
+	movd    $0xffff,(r2,r1)
+	movd    $0xfffff,(r2,r1)
+	movd    $0xfffffff,(r2,r1)
+	movd    $0xffffffff,(r2,r1)
+        ###########
+	# MOVD regp, regp
+        ###########
+	movd    (r4,r3),(r2,r1)
+	movd    (r4,r3),(r2,r1)
+	movd    $10,(sp)
+	movd    $14,(sp)
+	movd    $11,(sp)
+	movd    $8,(sp)
+        ###########
+	# MOVXB reg, reg
+        ###########
+	movxb	r1,r2
+	movxb	r3,r4
+	movxb	r5,r6
+	movxb	r7,r8
+	movxb	r9,r10
+        ###########
+	# MOVXW reg, regp
+        ###########
+	movxw	r1,(r3,r2)
+	movxw	r3,(r4,r3)
+	movxw	r5,(r6,r5)
+	movxw	r7,(r8,r7)
+	movxw	r9,(r9,r8)
+        ###########
+	# MOVZB reg, reg
+        ###########
+	movzb	r1,r2
+	movzb	r3,r4
+	movzb	r5,r6
+	movzb	r7,r8
+	movzb	r9,r10
+        ###########
+	# MOVZW reg, regp
+        ###########
+	movzw	r1,(r3,r2)
+	movzw	r3,(r4,r3)
+	movzw	r5,(r6,r5)
+	movzw	r7,(r8,r7)
+	movzw	r9,(r9,r8)
diff --git a/gas/testsuite/gas/cr16/mul_test.d b/gas/testsuite/gas/cr16/mul_test.d
new file mode 100644
index 000000000000..6e5755d33e12
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mul_test.d
@@ -0,0 +1,47 @@
+#as:
+#objdump:  -dr
+#name:  mul_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 64       	mulb	\$0xf:s,r1
+   2:	b2 64 ff 00 	mulb	\$0xff:m,r2
+   6:	b1 64 ff 0f 	mulb	\$0xfff:m,r1
+   a:	b1 64 14 00 	mulb	\$0x14:m,r1
+   e:	a2 64       	mulb	\$0xa:s,r2
+  10:	12 65       	mulb	r1,r2
+  12:	23 65       	mulb	r2,r3
+  14:	34 65       	mulb	r3,r4
+  16:	56 65       	mulb	r5,r6
+  18:	67 65       	mulb	r6,r7
+  1a:	78 65       	mulb	r7,r8
+  1c:	f1 66       	mulw	\$0xf:s,r1
+  1e:	b2 66 ff 00 	mulw	\$0xff:m,r2
+  22:	b1 66 ff 0f 	mulw	\$0xfff:m,r1
+  26:	b1 66 14 00 	mulw	\$0x14:m,r1
+  2a:	a2 66       	mulw	\$0xa:s,r2
+  2c:	12 67       	mulw	r1,r2
+  2e:	23 67       	mulw	r2,r3
+  30:	34 67       	mulw	r3,r4
+  32:	56 67       	mulw	r5,r6
+  34:	67 67       	mulw	r6,r7
+  36:	78 67       	mulw	r7,r8
+  38:	12 0b       	mulsb	r1,r2
+  3a:	34 0b       	mulsb	r3,r4
+  3c:	56 0b       	mulsb	r5,r6
+  3e:	78 0b       	mulsb	r7,r8
+  40:	9a 0b       	mulsb	r9,r10
+  42:	12 62       	mulsw	r1,\(r3,r2\)
+  44:	33 62       	mulsw	r3,\(r4,r3\)
+  46:	55 62       	mulsw	r5,\(r6,r5\)
+  48:	77 62       	mulsw	r7,\(r8,r7\)
+  4a:	98 62       	mulsw	r9,\(r9,r8\)
+  4c:	14 00 12 d2 	macqw	r1,r2,\(r3,r2\)
+  50:	14 00 45 d4 	macqw	r4,r5,\(r5,r4\)
+  54:	14 00 12 e2 	macuw	r1,r2,\(r3,r2\)
+  58:	14 00 45 e7 	macuw	r4,r5,\(r8,r7\)
+  5c:	14 00 12 f2 	macsw	r1,r2,\(r3,r2\)
+  60:	14 00 45 f6 	macsw	r4,r5,\(r7,r6\)
diff --git a/gas/testsuite/gas/cr16/mul_test.s b/gas/testsuite/gas/cr16/mul_test.s
new file mode 100644
index 000000000000..c2b960c7f0fc
--- /dev/null
+++ b/gas/testsuite/gas/cr16/mul_test.s
@@ -0,0 +1,64 @@
+        .text
+        .global main
+main:
+        ###########
+	# MULB imm4/imm16, reg
+        ###########
+	mulb    $0xf,r1
+	mulb    $0xff,r2
+	mulb    $0xfff,r1
+	#mulb    $0xffff,r2 // CHCEK WITH CRASM 4.1
+	mulb    $20,r1
+	mulb    $10,r2
+        ###########
+	# MULB reg, reg
+        ###########
+	mulb    r1,r2
+	mulb    r2,r3
+	mulb    r3,r4
+	mulb    r5,r6
+	mulb    r6,r7
+	mulb    r7,r8
+        ###########
+	# MULW imm4/imm16, reg
+        ###########
+	mulw    $0xf,r1
+	mulw    $0xff,r2
+	mulw    $0xfff,r1
+	#mulw    $0xffff,r2 // CHCEK WITH CRASM 4.1
+	mulw    $20,r1
+	mulw    $10,r2
+        ###########
+	# MULW reg, reg
+        ###########
+	mulw    r1,r2
+	mulw    r2,r3
+	mulw    r3,r4
+	mulw    r5,r6
+	mulw    r6,r7
+	mulw    r7,r8
+        ###########
+	# MULSB reg, reg
+        ###########
+	mulsb	r1,r2
+	mulsb	r3,r4
+	mulsb	r5,r6
+	mulsb	r7,r8
+	mulsb	r9,r10
+        ###########
+	# MULSW reg, regp
+        ###########
+	mulsw	r1,(r3,r2)
+	mulsw	r3,(r4,r3)
+	mulsw	r5,(r6,r5)
+	mulsw	r7,(r8,r7)
+	mulsw	r9,(r9,r8)
+        #############################
+	# MUC[q/u/s/]w reg, reg, regp
+        #############################
+	macqw   r1,r2,(r3,r2)
+	macqw   r4,r5,(r5,r4)
+	macuw   r1,r2,(r3,r2)
+	macuw   r4,r5,(r8,r7)
+	macsw   r1,r2,(r3,r2)
+	macsw   r4,r5,(r7,r6)
diff --git a/gas/testsuite/gas/cr16/or_test.d b/gas/testsuite/gas/cr16/or_test.d
new file mode 100644
index 000000000000..73d95d0ca5d9
--- /dev/null
+++ b/gas/testsuite/gas/cr16/or_test.d
@@ -0,0 +1,49 @@
+#as:
+#objdump:  -dr
+#name:  or_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 24       	orb	\$0xf:s,r1
+   2:	b2 24 ff 00 	orb	\$0xff:m,r2
+   6:	b1 24 ff 0f 	orb	\$0xfff:m,r1
+   a:	b2 24 ff ff 	orb	\$0xffff:m,r2
+   e:	b1 24 14 00 	orb	\$0x14:m,r1
+  12:	a2 24       	orb	\$0xa:s,r2
+  14:	12 25       	orb	r1,r2
+  16:	23 25       	orb	r2,r3
+  18:	34 25       	orb	r3,r4
+  1a:	56 25       	orb	r5,r6
+  1c:	67 25       	orb	r6,r7
+  1e:	78 25       	orb	r7,r8
+  20:	f1 26       	orw	\$0xf:s,r1
+  22:	b2 26 ff 00 	orw	\$0xff:m,r2
+  26:	b1 26 ff 0f 	orw	\$0xfff:m,r1
+  2a:	b2 26 ff ff 	orw	\$0xffff:m,r2
+  2e:	b1 26 14 00 	orw	\$0x14:m,r1
+  32:	a2 26       	orw	\$0xa:s,r2
+  34:	12 27       	orw	r1,r2
+  36:	23 27       	orw	r2,r3
+  38:	34 27       	orw	r3,r4
+  3a:	56 27       	orw	r5,r6
+  3c:	67 27       	orw	r6,r7
+  3e:	78 27       	orw	r7,r8
+  40:	51 00 00 00 	ord	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	51 00 00 00 	ord	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	51 00 00 00 	ord	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	51 00 00 00 	ord	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	51 00 0f 00 	ord	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	51 00 ff 0f 	ord	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	51 00 ff ff 	ord	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 90 	ord	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 90 	ord	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/or_test.s b/gas/testsuite/gas/cr16/or_test.s
new file mode 100644
index 000000000000..df140c164865
--- /dev/null
+++ b/gas/testsuite/gas/cr16/or_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# ORB imm4/imm16, reg
+        ###########
+	orb    $0xf,r1
+	orb    $0xff,r2
+	orb    $0xfff,r1
+	orb    $0xffff,r2
+	orb    $20,r1
+	orb    $10,r2
+        ###########
+	# ORB reg, reg
+        ###########
+	orb    r1,r2
+	orb    r2,r3
+	orb    r3,r4
+	orb    r5,r6
+	orb    r6,r7
+	orb    r7,r8
+        ###########
+	# ORW imm4/imm16, reg
+        ###########
+	orw    $0xf,r1
+	orw    $0xff,r2
+	orw    $0xfff,r1
+	orw    $0xffff,r2
+	orw    $20,r1
+	orw    $10,r2
+        ###########
+	# ORW reg, reg
+        ###########
+	orw    r1,r2
+	orw    r2,r3
+	orw    r3,r4
+	orw    r5,r6
+	orw    r6,r7
+	orw    r7,r8
+        ###########
+	# ORD imm32, regp
+        ###########
+	ord    $0xf,(r2,r1)
+	ord    $0xff,(r2,r1)
+	ord    $0xfff,(r2,r1)
+	ord    $0xffff,(r2,r1)
+	ord    $0xfffff,(r2,r1)
+	ord    $0xfffffff,(r2,r1)
+	ord    $0xffffffff,(r2,r1)
+        ###########
+	# ORD regp, regp
+        ###########
+	ord    (r4,r3),(r2,r1)
+	ord    (r4,r3),(r2,r1)
+	#ord    $10,(sp)
+	#ord    $14,(sp)
+	#ord    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/pop_test.d b/gas/testsuite/gas/cr16/pop_test.d
new file mode 100644
index 000000000000..1ed8c431b935
--- /dev/null
+++ b/gas/testsuite/gas/cr16/pop_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  pop_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 02       	pop	\$0x1,r7,RA
+   2:	96 02       	pop	\$0x2,r6,RA
+   4:	a5 02       	pop	\$0x3,r5,RA
+   6:	b4 02       	pop	\$0x4,r4,RA
+   8:	c3 02       	pop	\$0x5,r3,RA
+   a:	d2 02       	pop	\$0x6,r2,RA
+   c:	e1 02       	pop	\$0x7,r1,RA
+   e:	07 02       	pop	\$0x1,r7
+  10:	16 02       	pop	\$0x2,r6
+  12:	25 02       	pop	\$0x3,r5
+  14:	34 02       	pop	\$0x4,r4
+  16:	43 02       	pop	\$0x5,r3
+  18:	52 02       	pop	\$0x6,r2
+  1a:	61 02       	pop	\$0x7,r1
+  1c:	1e 02       	pop	RA
diff --git a/gas/testsuite/gas/cr16/pop_test.s b/gas/testsuite/gas/cr16/pop_test.s
new file mode 100644
index 000000000000..e88acff66112
--- /dev/null
+++ b/gas/testsuite/gas/cr16/pop_test.s
@@ -0,0 +1,27 @@
+        .text
+        .global main
+main:
+	####################
+	# pop uimm3 regr RA
+	####################
+	pop $1,r7,RA
+	pop $2,r6,RA
+	pop $3,r5,RA
+	pop $4,r4,RA
+	pop $5,r3,RA
+	pop $6,r2,RA
+	pop $7,r1,RA
+	#################
+	# pop uimm3 regr
+	#################
+	pop $1,r7
+	pop $2,r6
+	pop $3,r5
+	pop $4,r4
+	pop $5,r3
+	pop $6,r2
+	pop $7,r1
+	##########
+	# pop RA
+	##########
+	pop RA
diff --git a/gas/testsuite/gas/cr16/popret_test.d b/gas/testsuite/gas/cr16/popret_test.d
new file mode 100644
index 000000000000..cbc8f85a874b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/popret_test.d
@@ -0,0 +1,24 @@
+#as:
+#objdump:  -dr
+#name:  popret_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 03       	popret	\$0x1,r7,RA
+   2:	96 03       	popret	\$0x2,r6,RA
+   4:	a5 03       	popret	\$0x3,r5,RA
+   6:	b4 03       	popret	\$0x4,r4,RA
+   8:	c3 03       	popret	\$0x5,r3,RA
+   a:	d2 03       	popret	\$0x6,r2,RA
+   c:	e1 03       	popret	\$0x7,r1,RA
+   e:	07 03       	popret	\$0x1,r7
+  10:	16 03       	popret	\$0x2,r6
+  12:	25 03       	popret	\$0x3,r5
+  14:	34 03       	popret	\$0x4,r4
+  16:	43 03       	popret	\$0x5,r3
+  18:	52 03       	popret	\$0x6,r2
+  1a:	61 03       	popret	\$0x7,r1
+  1c:	1e 03       	popret	RA
diff --git a/gas/testsuite/gas/cr16/popret_test.s b/gas/testsuite/gas/cr16/popret_test.s
new file mode 100644
index 000000000000..f88bf2844d23
--- /dev/null
+++ b/gas/testsuite/gas/cr16/popret_test.s
@@ -0,0 +1,27 @@
+        .text
+        .global main
+main:
+	####################
+	# popret uimm3 regr RA
+	####################
+	popret $1,r7,RA
+	popret $2,r6,RA
+	popret $3,r5,RA
+	popret $4,r4,RA
+	popret $5,r3,RA
+	popret $6,r2,RA
+	popret $7,r1,RA
+	#################
+	# popret uimm3 regr
+	#################
+	popret $1,r7
+	popret $2,r6
+	popret $3,r5
+	popret $4,r4
+	popret $5,r3
+	popret $6,r2
+	popret $7,r1
+	##########
+	# popret RA
+	##########
+	popret RA
diff --git a/gas/testsuite/gas/cr16/push_test.d b/gas/testsuite/gas/cr16/push_test.d
new file mode 100644
index 000000000000..0a8afab80a5b
--- /dev/null
+++ b/gas/testsuite/gas/cr16/push_test.d
@@ -0,0 +1,26 @@
+#as:
+#objdump:  -dr
+#name:  push_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	87 01       	push	\$0x1,r7,RA
+   2:	96 01       	push	\$0x2,r6,RA
+   4:	a5 01       	push	\$0x3,r5,RA
+   6:	b4 01       	push	\$0x4,r4,RA
+   8:	c3 01       	push	\$0x5,r3,RA
+   a:	d2 01       	push	\$0x6,r2,RA
+   c:	e1 01       	push	\$0x7,r1,RA
+   e:	07 01       	push	\$0x1,r7
+  10:	16 01       	push	\$0x2,r6
+  12:	25 01       	push	\$0x3,r5
+  14:	34 01       	push	\$0x4,r4
+  16:	43 01       	push	\$0x5,r3
+  18:	52 01       	push	\$0x6,r2
+  1a:	61 01       	push	\$0x7,r1
+  1c:	5c 01       	push	\$0x6,r12
+  1e:	1e 01       	push	RA
+  20:	1e 01       	push	RA
diff --git a/gas/testsuite/gas/cr16/push_test.s b/gas/testsuite/gas/cr16/push_test.s
new file mode 100644
index 000000000000..804419cc548c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/push_test.s
@@ -0,0 +1,40 @@
+        .text
+        .global main
+main:
+	####################
+	# push uimm3 regr RA
+	####################
+	push $1,r7,RA
+	push $2,r6,RA
+	push $3,r5,RA
+	push $4,r4,RA
+	push $5,r3,RA
+	push $6,r2,RA
+	push $7,r1,RA
+#push $6,r12,RA
+	#push $7,r13,RA
+	#push $7,r12,RA
+	#push $8,r12,RA
+	#################
+	# push uimm3 regr
+	#################
+	push $1,r7
+	push $2,r6
+	push $3,r5
+	push $4,r4
+	push $5,r3
+	push $6,r2
+	push $7,r1
+	push $6,r12
+	#push $7,r13
+	#push $7,r12
+	#push $8,r12
+	#push $6,r13
+	##########
+	# push RA
+	##########
+	#push r1
+	#push r4
+	#push r9
+	push ra
+	push RA
diff --git a/gas/testsuite/gas/cr16/sbitb_test.d b/gas/testsuite/gas/cr16/sbitb_test.d
new file mode 100644
index 000000000000..e04dddeef342
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  sbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 73 cd 0b 	sbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 73 cd ab 	sbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f ba 	sbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 70 14 00 	sbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 70 fc ab 	sbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 70 34 12 	sbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 70 34 12 	sbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 70 34 00 	sbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 72 3a 4a 	sbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 72 3a 4a 	sbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 72 5a 4b 	sbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 72 1a 41 	sbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 72 14 01 	sbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 aa 	sbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e a0 	sbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 a0 	sbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f a0 	sbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 80 	sbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 73 34 00 	sbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 73 ab 00 	sbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 80 	sbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 80 	sbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 80 	sbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 80 	sbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 73 ff 0f 	sbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 73 ff 0f 	sbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 73 ff ff 	sbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 73 43 23 	sbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 81 	sbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 84 	sbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d 9f 	sbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 8f 	sbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 8f 	sbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 84 	sbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 72       	sbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 73 01 00 	sbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 73 34 12 	sbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 73 34 12 	sbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 91 	sbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 73 23 01 	sbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 91 	sbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/sbitb_test.s b/gas/testsuite/gas/cr16/sbitb_test.s
new file mode 100644
index 000000000000..937e6c622111
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	sbitb $4,0xbcd
+	sbitb $5,0xaabcd
+	sbitb $3,0xfaabcd
+
+	sbitb $5,[r12]0x14
+	sbitb $4,[r13]0xabfc
+	sbitb $3,[r12]0x1234
+	sbitb $3,[r13]0x1234
+	sbitb $3,[r12]0x34
+
+	sbitb $3,[r12]0xa7a(r1,r0)
+	sbitb $3,[r12]0xa7a(r3,r2)
+	sbitb $3,[r12]0xa7a(r4,r3)
+	sbitb $3,[r12]0xa7a(r5,r4)
+	sbitb $3,[r12]0xa7a(r6,r5)
+	sbitb $3,[r12]0xa7a(r7,r6)
+	sbitb $3,[r12]0xa7a(r9,r8)
+	sbitb $3,[r12]0xa7a(r11,r10)
+	sbitb $3,[r13]0xa7a(r1,r0)
+	sbitb $3,[r13]0xa7a(r3,r2)
+	sbitb $3,[r13]0xa7a(r4,r3)
+	sbitb $3,[r13]0xa7a(r5,r4)
+	sbitb $3,[r13]0xa7a(r6,r5)
+	sbitb $3,[r13]0xa7a(r7,r6)
+	sbitb $3,[r13]0xa7a(r9,r8)
+	sbitb $3,[r13]0xa7a(r11,r10)
+	sbitb $5,[r13]0xb7a(r4,r3)
+	sbitb $1,[r12]0x17a(r6,r5)
+	sbitb $1,[r13]0x134(r6,r5)
+	sbitb $3,[r12]0xabcde(r4,r3)
+	sbitb $5,[r13]0xabcd(r4,r3)
+	sbitb $3,[r12]0xabcd(r6,r5)
+	sbitb $3,[r13]0xbcde(r6,r5)
+
+	sbitb $5,0x0(r2)
+	sbitb $3,0x34(r12)
+	sbitb $3,0xab(r13)
+	sbitb $5,0xad(r1)
+	sbitb $5,0xcd(r2)
+	sbitb $5,0xfff(r0)
+	sbitb $3,0xbcd(r4)
+	sbitb $3,0xfff(r12)
+	sbitb $3,0xfff(r13)
+	sbitb $3,0xffff(r13)
+	sbitb $3,0x2343(r12)
+	sbitb $3,0x12345(r2)
+	sbitb $3,0x4abcd(r8)
+	sbitb $3,0xfabcd(r13)
+	sbitb $3,0xfabcd(r8)
+	sbitb $3,0xfabcd(r9)
+	sbitb $3,0x4abcd(r9)
+
+	sbitb $3,0x0(r2,r1)
+	sbitb $5,0x1(r2,r1)
+	sbitb $4,0x1234(r2,r1)
+	sbitb $3,0x1234(r2,r1)
+	sbitb $3,0x12345(r2,r1)
+	sbitb $3,0x123(r2,r1)
+	sbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/sbitw_test.d b/gas/testsuite/gas/cr16/sbitw_test.d
new file mode 100644
index 000000000000..afc75f4d5d94
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  sbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 77 cd 0b 	sbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 77 cd ab 	sbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f ba 	sbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 77 cd 0b 	sbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 77 cd ab 	sbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef ba 	sbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 74 14 00 	sbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 75 fc ab 	sbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 74 34 12 	sbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 75 34 12 	sbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 74 34 00 	sbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 74 14 00 	sbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 75 fc ab 	sbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 74 34 12 	sbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 75 34 12 	sbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 74 34 00 	sbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 72 3a 4a 	sbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 72 3a 4a 	sbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 72 5a 4b 	sbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 72 1a 41 	sbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 72 14 01 	sbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 aa 	sbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e a0 	sbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 a0 	sbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f a0 	sbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 72 da 4a 	sbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 72 da 4a 	sbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 72 fa 4b 	sbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 72 ba 41 	sbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 72 b4 01 	sbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 aa 	sbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe a0 	sbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 a0 	sbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df a0 	sbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 80 	sbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 71 34 00 	sbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 71 ab 00 	sbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 80 	sbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 80 	sbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 80 	sbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 80 	sbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 71 ff 0f 	sbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 71 ff 0f 	sbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 71 ff ff 	sbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 71 43 23 	sbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 81 	sbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 84 	sbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d 9f 	sbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 8f 	sbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 8f 	sbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 84 	sbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 80 	sbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 71 34 00 	sbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 71 ab 00 	sbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 80 	sbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 80 	sbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 80 	sbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 80 	sbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 71 ff 0f 	sbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 71 ff 0f 	sbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 71 ff ff 	sbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 71 43 23 	sbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 81 	sbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 84 	sbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd 9f 	sbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 8f 	sbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 8f 	sbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 84 	sbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 76       	sbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 71 01 00 	sbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 71 34 12 	sbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 71 34 12 	sbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 91 	sbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 71 23 01 	sbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 91 	sbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 76       	sbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 71 01 00 	sbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 71 34 12 	sbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 71 34 12 	sbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 91 	sbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 71 23 01 	sbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 91 	sbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/sbitw_test.s b/gas/testsuite/gas/cr16/sbitw_test.s
new file mode 100644
index 000000000000..334d033a44fa
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	sbitw $4,0xbcd
+	sbitw $5,0xaabcd
+	sbitw $3,0xfaabcd
+	sbitw $10,0xbcd
+	sbitw $15,0xaabcd
+	sbitw $14,0xfaabcd
+
+	sbitw $5,[r12]0x14
+	sbitw $4,[r13]0xabfc
+	sbitw $3,[r12]0x1234
+	sbitw $3,[r13]0x1234
+	sbitw $3,[r12]0x34
+	sbitw $15,[r12]0x14
+	sbitw $14,[r13]0xabfc
+	sbitw $13,[r12]0x1234
+	sbitw $13,[r13]0x1234
+	sbitw $11,[r12]0x34
+
+	sbitw $3,[r12]0xa7a(r1,r0)
+	sbitw $3,[r12]0xa7a(r3,r2)
+	sbitw $3,[r12]0xa7a(r4,r3)
+	sbitw $3,[r12]0xa7a(r5,r4)
+	sbitw $3,[r12]0xa7a(r6,r5)
+	sbitw $3,[r12]0xa7a(r7,r6)
+	sbitw $3,[r12]0xa7a(r9,r8)
+	sbitw $3,[r12]0xa7a(r11,r10)
+	sbitw $3,[r13]0xa7a(r1,r0)
+	sbitw $3,[r13]0xa7a(r3,r2)
+	sbitw $3,[r13]0xa7a(r4,r3)
+	sbitw $3,[r13]0xa7a(r5,r4)
+	sbitw $3,[r13]0xa7a(r6,r5)
+	sbitw $3,[r13]0xa7a(r7,r6)
+	sbitw $3,[r13]0xa7a(r9,r8)
+	sbitw $3,[r13]0xa7a(r11,r10)
+	sbitw $5,[r13]0xb7a(r4,r3)
+	sbitw $1,[r12]0x17a(r6,r5)
+	sbitw $1,[r13]0x134(r6,r5)
+	sbitw $3,[r12]0xabcde(r4,r3)
+	sbitw $5,[r13]0xabcd(r4,r3)
+	sbitw $3,[r12]0xabcd(r6,r5)
+	sbitw $3,[r13]0xbcde(r6,r5)
+	sbitw $13,[r12]0xa7a(r1,r0)
+	sbitw $13,[r12]0xa7a(r3,r2)
+	sbitw $13,[r12]0xa7a(r4,r3)
+	sbitw $13,[r12]0xa7a(r5,r4)
+	sbitw $13,[r12]0xa7a(r6,r5)
+	sbitw $13,[r12]0xa7a(r7,r6)
+	sbitw $13,[r12]0xa7a(r9,r8)
+	sbitw $13,[r12]0xa7a(r11,r10)
+	sbitw $13,[r13]0xa7a(r1,r0)
+	sbitw $13,[r13]0xa7a(r3,r2)
+	sbitw $13,[r13]0xa7a(r4,r3)
+	sbitw $13,[r13]0xa7a(r5,r4)
+	sbitw $13,[r13]0xa7a(r6,r5)
+	sbitw $13,[r13]0xa7a(r7,r6)
+	sbitw $13,[r13]0xa7a(r9,r8)
+	sbitw $13,[r13]0xa7a(r11,r10)
+	sbitw $15,[r13]0xb7a(r4,r3)
+	sbitw $11,[r12]0x17a(r6,r5)
+	sbitw $11,[r13]0x134(r6,r5)
+	sbitw $13,[r12]0xabcde(r4,r3)
+	sbitw $15,[r13]0xabcd(r4,r3)
+	sbitw $13,[r12]0xabcd(r6,r5)
+	sbitw $13,[r13]0xbcde(r6,r5)
+
+	sbitw $5,0x0(r2)
+	sbitw $3,0x34(r12)
+	sbitw $3,0xab(r13)
+	sbitw $5,0xad(r1)
+	sbitw $5,0xcd(r2)
+	sbitw $5,0xfff(r0)
+	sbitw $3,0xbcd(r4)
+	sbitw $3,0xfff(r12)
+	sbitw $3,0xfff(r13)
+	sbitw $3,0xffff(r13)
+	sbitw $3,0x2343(r12)
+	sbitw $3,0x12345(r2)
+	sbitw $3,0x4abcd(r8)
+	sbitw $3,0xfabcd(r13)
+	sbitw $3,0xfabcd(r8)
+	sbitw $3,0xfabcd(r9)
+	sbitw $3,0x4abcd(r9)
+	sbitw $15,0x0(r2)
+	sbitw $13,0x34(r12)
+	sbitw $13,0xab(r13)
+	sbitw $15,0xad(r1)
+	sbitw $15,0xcd(r2)
+	sbitw $15,0xfff(r0)
+	sbitw $13,0xbcd(r4)
+	sbitw $13,0xfff(r12)
+	sbitw $13,0xfff(r13)
+	sbitw $13,0xffff(r13)
+	sbitw $13,0x2343(r12)
+	sbitw $13,0x12345(r2)
+	sbitw $13,0x4abcd(r8)
+	sbitw $13,0xfabcd(r13)
+	sbitw $13,0xfabcd(r8)
+	sbitw $13,0xfabcd(r9)
+	sbitw $13,0x4abcd(r9)
+
+	sbitw $3,0x0(r2,r1)
+	sbitw $5,0x1(r2,r1)
+	sbitw $4,0x1234(r2,r1)
+	sbitw $3,0x1234(r2,r1)
+	sbitw $3,0x12345(r2,r1)
+	sbitw $3,0x123(r2,r1)
+	sbitw $3,0x12345(r2,r1)
+	sbitw $13,0x0(r2,r1)
+	sbitw $15,0x1(r2,r1)
+	sbitw $14,0x1234(r2,r1)
+	sbitw $13,0x1234(r2,r1)
+	sbitw $13,0x12345(r2,r1)
+	sbitw $13,0x123(r2,r1)
+	sbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/scc_test.d b/gas/testsuite/gas/cr16/scc_test.d
new file mode 100644
index 000000000000..308e75518c8c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/scc_test.d
@@ -0,0 +1,22 @@
+#as:
+#objdump:  -dr
+#name:  scc_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	02 08       	seq	r2
+   2:	13 08       	sne	r3
+   4:	23 08       	scs	r3
+   6:	34 08       	scc	r4
+   8:	45 08       	shi	r5
+   a:	56 08       	sls	r6
+   c:	67 08       	sgt	r7
+   e:	88 08       	sfs	r8
+  10:	99 08       	sfc	r9
+  12:	aa 08       	slo	r10
+  14:	b1 08       	shs	r1
+  16:	cb 08       	slt	r11
+  18:	d0 08       	sge	r0
diff --git a/gas/testsuite/gas/cr16/scc_test.s b/gas/testsuite/gas/cr16/scc_test.s
new file mode 100644
index 000000000000..9b9d01c3059f
--- /dev/null
+++ b/gas/testsuite/gas/cr16/scc_test.s
@@ -0,0 +1,19 @@
+        .text
+        .global main
+main:
+	##########
+	# SCond reg
+	##########
+	seq	r2
+	sne	r3
+	scs	r3
+	scc	r4
+	shi	r5
+	sls	r6
+	sgt	r7
+	sfs	r8
+	sfc	r9
+	slo	r10
+	shs	r1
+	slt	r11
+	sge	r0
diff --git a/gas/testsuite/gas/cr16/storb_test.d b/gas/testsuite/gas/cr16/storb_test.d
new file mode 100644
index 000000000000..dc2a9c260f09
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storb_test.d
@@ -0,0 +1,153 @@
+#as:
+#objdump:  -dr
+#name:  storb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c8 00 00 	storb	r0,0x0 <main>:m
+   4:	10 c8 ff 00 	storb	r1,0xff <main\+0xff>:m
+   8:	30 c8 ff 0f 	storb	r3,0xfff <main\+0xfff>:m
+   c:	40 c8 34 12 	storb	r4,0x1234 <main\+0x1234>:m
+  10:	50 c8 34 12 	storb	r5,0x1234 <main\+0x1234>:m
+  14:	13 00 07 7a 	storb	r0,0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 1b 7a 	storb	r1,0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 2f 7f 	storb	r2,0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 ca 00 00 	storb	r0,\[r12\]0x0:m
+  2a:	00 cb 00 00 	storb	r0,\[r12\]0x0:m
+  2e:	10 ca ff 00 	storb	r1,\[r12\]0xff:m
+  32:	10 cb ff 00 	storb	r1,\[r12\]0xff:m
+  36:	30 ca ff 0f 	storb	r3,\[r12\]0xfff:m
+  3a:	30 cb ff 0f 	storb	r3,\[r12\]0xfff:m
+  3e:	40 ca 34 12 	storb	r4,\[r13\]0x1234:m
+  42:	40 cb 34 12 	storb	r4,\[r13\]0x1234:m
+  46:	50 ca 34 12 	storb	r5,\[r13\]0x1234:m
+  4a:	50 cb 34 12 	storb	r5,\[r13\]0x1234:m
+  4e:	20 ca 67 45 	storb	r2,\[r12\]0x4567:m
+  52:	2a cb 34 12 	storb	r2,\[r12\]0xa1234:m
+  56:	10 f4       	storb	r1,0x4:s\(r1,r0\)
+  58:	32 f4       	storb	r3,0x4:s\(r3,r2\)
+  5a:	40 ff 34 12 	storb	r4,0x1234:m\(r1,r0\)
+  5e:	52 ff 34 12 	storb	r5,0x1234:m\(r3,r2\)
+  62:	13 00 60 5a 	storb	r6,0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 5f 	storb	r1,0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 32 5f 	storb	r3,0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 40 5f 	storb	r4,0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 52 5f 	storb	r5,0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 60 55 	storb	r6,0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 f0       	storb	r0,0x0:s\(r1,r0\)
+  88:	00 f0       	storb	r0,0x0:s\(r1,r0\)
+  8a:	00 ff 0f 00 	storb	r0,0xf:m\(r1,r0\)
+  8e:	10 ff 0f 00 	storb	r1,0xf:m\(r1,r0\)
+  92:	20 ff 34 12 	storb	r2,0x1234:m\(r1,r0\)
+  96:	32 ff cd ab 	storb	r3,0xabcd:m\(r3,r2\)
+  9a:	43 ff ff af 	storb	r4,0xafff:m\(r4,r3\)
+  9e:	13 00 55 5a 	storb	r5,0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 5f 	storb	r0,0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 10 5f 	storb	r1,0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 20 5f 	storb	r2,0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 32 5f 	storb	r3,0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 5f 	storb	r4,0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 55 55 	storb	r5,0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 fe       	storb	r0,\[r12\]0x0:s\(r1,r0\)
+  ca:	18 fe       	storb	r1,\[r13\]0x0:s\(r1,r0\)
+  cc:	70 c6 04 12 	storb	r7,\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 38 61 	storb	r3,\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 40 6a 	storb	r4,\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 58 6b 	storb	r5,\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 68 6f 	storb	r6,\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
+  e8:	40 81 cd 0b 	storb	\$0x4:s,0xbcd <main\+0xbcd>:m
+  ec:	5a 81 cd ab 	storb	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+  f0:	12 00 3f 3a 	storb	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+  f4:	cd ab 
+  f6:	50 84 14 00 	storb	\$0x5:s,\[r13\]0x14:m
+  fa:	40 85 fc ab 	storb	\$0x4:s,\[r13\]0xabfc:m
+  fe:	30 84 34 12 	storb	\$0x3:s,\[r12\]0x1234:m
+ 102:	30 85 34 12 	storb	\$0x3:s,\[r12\]0x1234:m
+ 106:	30 84 34 00 	storb	\$0x3:s,\[r12\]0x34:m
+ 10a:	30 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+ 10e:	31 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+ 112:	36 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+ 116:	32 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+ 11a:	37 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+ 11e:	33 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+ 122:	34 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+ 126:	35 86 3a 4a 	storb	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+ 12a:	38 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+ 12e:	39 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+ 132:	3e 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+ 136:	3a 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+ 13a:	3f 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+ 13e:	3b 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+ 142:	3c 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+ 146:	3d 86 3a 4a 	storb	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+ 14a:	3e 86 5a 4b 	storb	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+ 14e:	37 86 1a 41 	storb	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+ 152:	3f 86 14 01 	storb	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+ 156:	12 00 36 2a 	storb	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+ 15a:	de bc 
+ 15c:	12 00 5e 20 	storb	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+ 160:	cd ab 
+ 162:	12 00 37 20 	storb	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+ 166:	cd ab 
+ 168:	12 00 3f 20 	storb	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+ 16c:	de bc 
+ 16e:	12 00 52 00 	storb	\$0x5:s,0x0:l\(r2\)
+ 172:	00 00 
+ 174:	3c 83 34 00 	storb	\$0x3:s,0x34:m\(r12\)
+ 178:	3d 83 ab 00 	storb	\$0x3:s,0xab:m\(r13\)
+ 17c:	12 00 51 00 	storb	\$0x5:s,0xad:l\(r1\)
+ 180:	ad 00 
+ 182:	12 00 52 00 	storb	\$0x5:s,0xcd:l\(r2\)
+ 186:	cd 00 
+ 188:	12 00 50 00 	storb	\$0x5:s,0xfff:l\(r0\)
+ 18c:	ff 0f 
+ 18e:	12 00 34 00 	storb	\$0x3:s,0xbcd:l\(r4\)
+ 192:	cd 0b 
+ 194:	3c 83 ff 0f 	storb	\$0x3:s,0xfff:m\(r12\)
+ 198:	3d 83 ff 0f 	storb	\$0x3:s,0xfff:m\(r13\)
+ 19c:	3d 83 ff ff 	storb	\$0x3:s,0xffff:m\(r13\)
+ 1a0:	3c 83 43 23 	storb	\$0x3:s,0x2343:m\(r12\)
+ 1a4:	12 00 32 01 	storb	\$0x3:s,0x2345:l\(r2\)
+ 1a8:	45 23 
+ 1aa:	12 00 38 04 	storb	\$0x3:s,0xabcd:l\(r8\)
+ 1ae:	cd ab 
+ 1b0:	12 00 3d 1f 	storb	\$0x3:s,0xfabcd:l\(r13\)
+ 1b4:	cd ab 
+ 1b6:	12 00 38 0f 	storb	\$0x3:s,0xabcd:l\(r8\)
+ 1ba:	cd ab 
+ 1bc:	12 00 39 0f 	storb	\$0x3:s,0xabcd:l\(r9\)
+ 1c0:	cd ab 
+ 1c2:	12 00 39 04 	storb	\$0x3:s,0xabcd:l\(r9\)
+ 1c6:	cd ab 
+ 1c8:	31 82       	storb	\$0x3:s,0x0:s\(r2,r1\)
+ 1ca:	51 83 01 00 	storb	\$0x5:s,0x1:m\(r2,r1\)
+ 1ce:	41 83 34 12 	storb	\$0x4:s,0x1234:m\(r2,r1\)
+ 1d2:	31 83 34 12 	storb	\$0x3:s,0x1234:m\(r2,r1\)
+ 1d6:	12 00 31 11 	storb	\$0x3:s,0x12345:l\(r2,r1\)
+ 1da:	45 23 
+ 1dc:	31 83 23 01 	storb	\$0x3:s,0x123:m\(r2,r1\)
+ 1e0:	12 00 31 11 	storb	\$0x3:s,0x12345:l\(r2,r1\)
+ 1e4:	45 23 
diff --git a/gas/testsuite/gas/cr16/storb_test.s b/gas/testsuite/gas/cr16/storb_test.s
new file mode 100644
index 000000000000..2cd2706ec07c
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storb_test.s
@@ -0,0 +1,143 @@
+        .text

+        .global main

+main:

+	######################

+	#  storb reg abs20/24 

+	######################

+	storb r0,0x0

+	storb r1,0xff

+	storb r3,0xfff

+	storb r4,0x1234

+	storb r5,0x1234

+	storb r0,0x7A1234

+	storb r1,0xBA1234

+	storb r2,0xffffff

+	######################

+	#  storb abs20 rel reg

+	######################

+	storb r0,[r12]0x0

+	storb r0,[r13]0x0

+	storb r1,[r12]0xff

+	storb r1,[r13]0xff

+	storb r3,[r12]0xfff

+	storb r3,[r13]0xfff

+	storb r4,[r12]0x1234

+	storb r4,[r13]0x1234

+	storb r5,[r12]0x1234

+	storb r5,[r13]0x1234

+	storb r2,[r12]0x4567

+	storb r2,[r13]0xA1234

+	###################################

+	#  storb reg rbase(disp20/-disp20) 

+	###################################

+	storb r1,0x4(r1,r0)

+	storb r3,0x4(r3,r2)

+	storb r4,0x1234(r1,r0)

+	storb r5,0x1234(r3,r2)

+	storb r6,0xA1234(r1,r0)

+	storb r1,-0x4(r1,r0)

+	storb r3,-0x4(r3,r2)

+	storb r4,-0x1234(r1,r0)

+	storb r5,-0x1234(r3,r2)

+	storb r6,-0xA1234(r1,r0)

+	#################################################

+	#  storb reg rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	storb r0,0x0(r1,r0)

+	storb r0,0x0(r1,r0)

+	storb r0,0xf(r1,r0)

+	storb r1,0xf(r1,r0)

+	storb r2,0x1234(r1,r0)

+	storb r3,0xabcd(r3,r2)

+	storb r4,0xAfff(r4,r3)

+	storb r5,0xA1234(r6,r5)

+	storb r0,-0xf(r1,r0)

+	storb r1,-0xf(r1,r0)

+	storb r2,-0x1234(r1,r0)

+	storb r3,-0xabcd(r3,r2)

+	storb r4,-0xAfff(r4,r3)

+	storb r5,-0xA1234(r6,r5)

+	####################################

+	#  storb rbase(disp0/disp14) rel reg

+	####################################

+	storb r0,[r12]0x0(r1,r0)

+	storb r1,[r13]0x0(r1,r0)

+	storb r2,[r12]0x1234(r1,r0)

+	storb r3,[r13]0x1abcd(r1,r0)

+	#################################

+	#  storb reg rpbase(disp20) rel

+	#################################

+	storb r4,[r12]0xA1234(r1,r0)

+	storb r5,[r13]0xB1234(r1,r0)

+	storb r6,[r13]0xfffff(r1,r0)

+	#######################

+	# storb reg, uimm16/20

+	######################

+	storb $4,0xbcd

+	storb $5,0xaabcd

+	storb $3,0xfaabcd

+

+	#######################

+	# storb reg, uimm16/20

+	######################

+	storb $5,[r12]0x14

+	storb $4,[r13]0xabfc

+	storb $3,[r12]0x1234

+	storb $3,[r13]0x1234

+	storb $3,[r12]0x34

+	#######################

+	# storb imm, index-rbase

+	######################

+	storb $3,[r12]0xa7a(r1,r0)

+	storb $3,[r12]0xa7a(r3,r2)

+	storb $3,[r12]0xa7a(r4,r3)

+	storb $3,[r12]0xa7a(r5,r4)

+	storb $3,[r12]0xa7a(r6,r5)

+	storb $3,[r12]0xa7a(r7,r6)

+	storb $3,[r12]0xa7a(r9,r8)

+	storb $3,[r12]0xa7a(r11,r10)

+	storb $3,[r13]0xa7a(r1,r0)

+	storb $3,[r13]0xa7a(r3,r2)

+	storb $3,[r13]0xa7a(r4,r3)

+	storb $3,[r13]0xa7a(r5,r4)

+	storb $3,[r13]0xa7a(r6,r5)

+	storb $3,[r13]0xa7a(r7,r6)

+	storb $3,[r13]0xa7a(r9,r8)

+	storb $3,[r13]0xa7a(r11,r10)

+	storb $5,[r13]0xb7a(r4,r3)

+	storb $1,[r12]0x17a(r6,r5)

+	storb $1,[r13]0x134(r6,r5)

+	storb $3,[r12]0xabcde(r4,r3)

+	storb $5,[r13]0xabcd(r4,r3)

+	storb $3,[r12]0xabcd(r6,r5)

+	storb $3,[r13]0xbcde(r6,r5)

+	#######################

+	# storb imm4, rbase(disp)

+	######################

+	storb $5,0x0(r2)

+	storb $3,0x34(r12)

+	storb $3,0xab(r13)

+	storb $5,0xad(r1)

+	storb $5,0xcd(r2)

+	storb $5,0xfff(r0)

+	storb $3,0xbcd(r4)

+	storb $3,0xfff(r12)

+	storb $3,0xfff(r13)

+	storb $3,0xffff(r13)

+	storb $3,0x2343(r12)

+	storb $3,0x12345(r2)

+	storb $3,0x4abcd(r8)

+	storb $3,0xfabcd(r13)

+	storb $3,0xfabcd(r8)

+	storb $3,0xfabcd(r9)

+	storb $3,0x4abcd(r9)

+	##########################

+	# storb imm, disp20(rpbase)

+	#########################

+	storb $3,0x0(r2,r1)

+	storb $5,0x1(r2,r1)

+	storb $4,0x1234(r2,r1)

+	storb $3,0x1234(r2,r1)

+	storb $3,0x12345(r2,r1)

+	storb $3,0x123(r2,r1)

+	storb $3,0x12345(r2,r1)

diff --git a/gas/testsuite/gas/cr16/stord_test.d b/gas/testsuite/gas/cr16/stord_test.d
new file mode 100644
index 000000000000..9e31b7a886e9
--- /dev/null
+++ b/gas/testsuite/gas/cr16/stord_test.d
@@ -0,0 +1,80 @@
+#as:
+#objdump:  -dr
+#name:  stord_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c7 00 00 	stord	\(r1,r0\),0x0 <main>:m
+   4:	00 c7 ff 00 	stord	\(r1,r0\),0xff <main\+0xff>:m
+   8:	20 c7 ff 0f 	stord	\(r3,r2\),0xfff <main\+0xfff>:m
+   c:	30 c7 34 12 	stord	\(r4,r3\),0x1234 <main\+0x1234>:m
+  10:	40 c7 34 12 	stord	\(r5,r4\),0x1234 <main\+0x1234>:m
+  14:	13 00 07 ba 	stord	\(r1,r0\),0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 0b ba 	stord	\(r1,r0\),0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 1f bf 	stord	\(r2,r1\),0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 cc 00 00 	stord	\(r1,r0\),\[r12\]0x0:m
+  2a:	00 cd 00 00 	stord	\(r1,r0\),\[r12\]0x0:m
+  2e:	00 cc ff 00 	stord	\(r1,r0\),\[r12\]0xff:m
+  32:	00 cd ff 00 	stord	\(r1,r0\),\[r12\]0xff:m
+  36:	20 cc ff 0f 	stord	\(r3,r2\),\[r12\]0xfff:m
+  3a:	20 cd ff 0f 	stord	\(r3,r2\),\[r12\]0xfff:m
+  3e:	30 cc 34 12 	stord	\(r4,r3\),\[r12\]0x1234:m
+  42:	30 cd 34 12 	stord	\(r4,r3\),\[r12\]0x1234:m
+  46:	40 cc 34 12 	stord	\(r5,r4\),\[r13\]0x1234:m
+  4a:	40 cd 34 12 	stord	\(r5,r4\),\[r13\]0x1234:m
+  4e:	10 cc 67 45 	stord	\(r2,r1\),\[r12\]0x4567:m
+  52:	1a cd 34 12 	stord	\(r2,r1\),\[r12\]0xa1234:m
+  56:	10 e2       	stord	\(r2,r1\),0x4:s\(r1,r0\)
+  58:	22 e2       	stord	\(r3,r2\),0x4:s\(r3,r2\)
+  5a:	30 ef 34 12 	stord	\(r4,r3\),0x1234:m\(r1,r0\)
+  5e:	42 ef 34 12 	stord	\(r5,r4\),0x1234:m\(r3,r2\)
+  62:	13 00 50 9a 	stord	\(r6,r5\),0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 9f 	stord	\(r2,r1\),0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 22 9f 	stord	\(r3,r2\),0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 30 9f 	stord	\(r4,r3\),0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 42 9f 	stord	\(r5,r4\),0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 50 95 	stord	\(r6,r5\),0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 e0       	stord	\(r1,r0\),0x0:s\(r1,r0\)
+  88:	00 e0       	stord	\(r1,r0\),0x0:s\(r1,r0\)
+  8a:	00 ef 0f 00 	stord	\(r1,r0\),0xf:m\(r1,r0\)
+  8e:	00 ef 0f 00 	stord	\(r1,r0\),0xf:m\(r1,r0\)
+  92:	10 ef 34 12 	stord	\(r2,r1\),0x1234:m\(r1,r0\)
+  96:	22 ef cd ab 	stord	\(r3,r2\),0xabcd:m\(r3,r2\)
+  9a:	33 ef ff af 	stord	\(r4,r3\),0xafff:m\(r4,r3\)
+  9e:	13 00 65 9a 	stord	\(r7,r6\),0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 9f 	stord	\(r1,r0\),0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 00 9f 	stord	\(r1,r0\),0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 10 9f 	stord	\(r2,r1\),0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 22 9f 	stord	\(r3,r2\),0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 9f 	stord	\(r5,r4\),0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 45 95 	stord	\(r5,r4\),0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 ee       	stord	\(r1,r0\),\[r12\]0x0:s\(r1,r0\)
+  ca:	08 ee       	stord	\(r1,r0\),\[r13\]0x0:s\(r1,r0\)
+  cc:	b0 c6 04 12 	stord	\(r12,r11\),\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 28 a1 	stord	\(r3,r2\),\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 20 aa 	stord	\(r3,r2\),\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 38 ab 	stord	\(r4,r3\),\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 48 af 	stord	\(r5,r4\),\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
diff --git a/gas/testsuite/gas/cr16/stord_test.s b/gas/testsuite/gas/cr16/stord_test.s
new file mode 100644
index 000000000000..dcac741fc052
--- /dev/null
+++ b/gas/testsuite/gas/cr16/stord_test.s
@@ -0,0 +1,72 @@
+        .text

+        .global main

+main:

+	######################

+	#  stord abs20/24 regp

+	######################

+	stord (r1,r0),0x0

+	stord (r1,r0),0xff

+	stord (r3,r2),0xfff

+	stord (r4,r3),0x1234

+	stord (r5,r4),0x1234

+	stord (r1,r0),0x7A1234

+	stord (r1,r0),0xBA1234

+	stord (r2,r1),0xffffff

+	######################

+	#  stord abs20 rel regp

+	######################

+	stord (r1,r0),[r12]0x0

+	stord (r1,r0),[r13]0x0

+	stord (r1,r0),[r12]0xff

+	stord (r1,r0),[r13]0xff

+	stord (r3,r2),[r12]0xfff

+	stord (r3,r2),[r13]0xfff

+	stord (r4,r3),[r12]0x1234

+	stord (r4,r3),[r13]0x1234

+	stord (r5,r4),[r12]0x1234

+	stord (r5,r4),[r13]0x1234

+	stord (r2,r1),[r12]0x4567

+	stord (r2,r1),[r13]0xA1234

+	###################################

+	#  stord regp rbase(disp20/-disp20)  

+	###################################

+	stord (r2,r1),0x4(r1,r0)

+	stord (r3,r2),0x4(r3,r2)

+	stord (r4,r3),0x1234(r1,r0)

+	stord (r5,r4),0x1234(r3,r2)

+	stord (r6,r5),0xA1234(r1,r0)

+	stord (r2,r1),-0x4(r1,r0)

+	stord (r3,r2),-0x4(r3,r2)

+	stord (r4,r3),-0x1234(r1,r0)

+	stord (r5,r4),-0x1234(r3,r2)

+	stord (r6,r5),-0xA1234(r1,r0)

+	#################################################

+	#  stord regp rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	stord (r1,r0),0x0(r1,r0)

+	stord (r1,r0),0x0(r1,r0)

+	stord (r1,r0),0xf(r1,r0)

+	stord (r1,r0),0xf(r1,r0)

+	stord (r2,r1),0x1234(r1,r0)

+	stord (r3,r2),0xabcd(r3,r2)

+	stord (r4,r3),0xAfff(r4,r3)

+	stord (r7,r6),0xA1234(r6,r5)

+	stord (r1,r0),-0xf(r1,r0)

+	stord (r1,r0),-0xf(r1,r0)

+	stord (r2,r1),-0x1234(r1,r0)

+	stord (r3,r2),-0xabcd(r3,r2)

+	stord (r5,r4),-0xAfff(r4,r3)

+	stord (r5,r4),-0xA1234(r6,r5)

+	####################################

+	#  stord rbase(disp0/disp14) rel reg

+	####################################

+	stord (r1,r0),[r12]0x0(r1,r0)

+	stord (r1,r0),[r13]0x0(r1,r0)

+	stord (r2,r1),[r12]0x1234(r1,r0)

+	stord (r3,r2),[r13]0x1abcd(r1,r0)

+	#################################

+	#  stord rpbase(disp20) rel reg

+	#################################

+	stord (r3,r2),[r12]0xA1234(r1,r0)

+	stord (r4,r3),[r13]0xB1234(r1,r0)

+	stord (r5,r4),[r13]0xfffff(r1,r0)

diff --git a/gas/testsuite/gas/cr16/storm_test.d b/gas/testsuite/gas/cr16/storm_test.d
new file mode 100644
index 000000000000..8e103ba9d665
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storm_test.d
@@ -0,0 +1,25 @@
+#as:
+#objdump:  -dr
+#name:  storm_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	b0 00       	storm	\$0x1,r0
+   2:	b1 00       	storm	\$0x2,r0
+   4:	b2 00       	storm	\$0x3,r0
+   6:	b3 00       	storm	\$0x4,r0
+   8:	b4 00       	storm	\$0x5,r0
+   a:	b5 00       	storm	\$0x6,r0
+   c:	b6 00       	storm	\$0x7,r0
+   e:	b7 00       	storm	\$0x8,r0
+  10:	b8 00       	stormp	\$0x1,r0
+  12:	b9 00       	stormp	\$0x2,r0
+  14:	ba 00       	stormp	\$0x3,r0
+  16:	bb 00       	stormp	\$0x4,r0
+  18:	bc 00       	stormp	\$0x5,r0
+  1a:	bd 00       	stormp	\$0x6,r0
+  1c:	be 00       	stormp	\$0x7,r0
+  1e:	bf 00       	stormp	\$0x8,r0
diff --git a/gas/testsuite/gas/cr16/storm_test.s b/gas/testsuite/gas/cr16/storm_test.s
new file mode 100644
index 000000000000..ad5de6117e73
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storm_test.s
@@ -0,0 +1,25 @@
+        .text
+        .global main
+main:
+	##############
+	# storm cnt
+	##############
+ 	storm $1
+ 	storm $2
+ 	storm $3
+ 	storm $4
+ 	storm $5
+ 	storm $6
+ 	storm $7
+ 	storm $8
+	##############
+	# stormp cnt
+	##############
+ 	stormp $1
+ 	stormp $2
+ 	stormp $3
+ 	stormp $4
+ 	stormp $5
+ 	stormp $6
+ 	stormp $7
+ 	stormp $8
diff --git a/gas/testsuite/gas/cr16/storw_test.d b/gas/testsuite/gas/cr16/storw_test.d
new file mode 100644
index 000000000000..02b1b6543aee
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storw_test.d
@@ -0,0 +1,153 @@
+#as:
+#objdump:  -dr
+#name:  storw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 c9 00 00 	storw	r0,0x0 <main>:m
+   4:	10 c9 ff 00 	storw	r1,0xff <main\+0xff>:m
+   8:	30 c9 ff 0f 	storw	r3,0xfff <main\+0xfff>:m
+   c:	40 c9 34 12 	storw	r4,0x1234 <main\+0x1234>:m
+  10:	50 c9 34 12 	storw	r5,0x1234 <main\+0x1234>:m
+  14:	13 00 07 fa 	storw	r0,0x7a1234 <main\+0x7a1234>:l
+  18:	34 12 
+  1a:	13 00 1b fa 	storw	r1,0xba1234 <main\+0xba1234>:l
+  1e:	34 12 
+  20:	13 00 2f ff 	storw	r2,0xffffff <main\+0xffffff>:l
+  24:	ff ff 
+  26:	00 ce 00 00 	storw	r0,\[r12\]0x0:m
+  2a:	00 cf 00 00 	storw	r0,\[r12\]0x0:m
+  2e:	10 ce ff 00 	storw	r1,\[r12\]0xff:m
+  32:	10 cf ff 00 	storw	r1,\[r12\]0xff:m
+  36:	30 ce ff 0f 	storw	r3,\[r12\]0xfff:m
+  3a:	30 cf ff 0f 	storw	r3,\[r12\]0xfff:m
+  3e:	40 ce 34 12 	storw	r4,\[r13\]0x1234:m
+  42:	40 cf 34 12 	storw	r4,\[r13\]0x1234:m
+  46:	50 ce 34 12 	storw	r5,\[r13\]0x1234:m
+  4a:	50 cf 34 12 	storw	r5,\[r13\]0x1234:m
+  4e:	20 ce 67 45 	storw	r2,\[r12\]0x4567:m
+  52:	2a cf 34 12 	storw	r2,\[r12\]0xa1234:m
+  56:	10 d2       	storw	r1,0x4:s\(r1,r0\)
+  58:	32 d2       	storw	r3,0x4:s\(r3,r2\)
+  5a:	40 df 34 12 	storw	r4,0x1234:m\(r1,r0\)
+  5e:	52 df 34 12 	storw	r5,0x1234:m\(r3,r2\)
+  62:	13 00 60 da 	storw	r6,0xa1234:l\(r1,r0\)
+  66:	34 12 
+  68:	19 00 10 df 	storw	r1,0xffffc:l\(r1,r0\)
+  6c:	fc ff 
+  6e:	19 00 32 df 	storw	r3,0xffffc:l\(r3,r2\)
+  72:	fc ff 
+  74:	19 00 40 df 	storw	r4,0xfedcc:l\(r1,r0\)
+  78:	cc ed 
+  7a:	19 00 52 df 	storw	r5,0xfedcc:l\(r3,r2\)
+  7e:	cc ed 
+  80:	19 00 60 d5 	storw	r6,0x5edcc:l\(r1,r0\)
+  84:	cc ed 
+  86:	00 d0       	storw	r0,0x0:s\(r1,r0\)
+  88:	00 d0       	storw	r0,0x0:s\(r1,r0\)
+  8a:	00 df 0f 00 	storw	r0,0xf:m\(r1,r0\)
+  8e:	10 df 0f 00 	storw	r1,0xf:m\(r1,r0\)
+  92:	20 df 34 12 	storw	r2,0x1234:m\(r1,r0\)
+  96:	32 df cd ab 	storw	r3,0xabcd:m\(r3,r2\)
+  9a:	43 df ff af 	storw	r4,0xafff:m\(r4,r3\)
+  9e:	13 00 55 da 	storw	r5,0xa1234:l\(r6,r5\)
+  a2:	34 12 
+  a4:	19 00 00 df 	storw	r0,0xffff1:l\(r1,r0\)
+  a8:	f1 ff 
+  aa:	19 00 10 df 	storw	r1,0xffff1:l\(r1,r0\)
+  ae:	f1 ff 
+  b0:	19 00 20 df 	storw	r2,0xfedcc:l\(r1,r0\)
+  b4:	cc ed 
+  b6:	19 00 32 df 	storw	r3,0xf5433:l\(r3,r2\)
+  ba:	33 54 
+  bc:	19 00 43 df 	storw	r4,0xf5001:l\(r4,r3\)
+  c0:	01 50 
+  c2:	19 00 55 d5 	storw	r5,0x5edcc:l\(r6,r5\)
+  c6:	cc ed 
+  c8:	00 de       	storw	r0,\[r12\]0x0:s\(r1,r0\)
+  ca:	18 de       	storw	r1,\[r13\]0x0:s\(r1,r0\)
+  cc:	f0 c6 04 12 	storw	r15,\[r12\]0x234:m\(r1,r0\)
+  d0:	13 00 38 e1 	storw	r3,\[r13\]0x1abcd:l\(r1,r0\)
+  d4:	cd ab 
+  d6:	13 00 40 ea 	storw	r4,\[r12\]0xa1234:l\(r1,r0\)
+  da:	34 12 
+  dc:	13 00 58 eb 	storw	r5,\[r13\]0xb1234:l\(r1,r0\)
+  e0:	34 12 
+  e2:	13 00 68 ef 	storw	r6,\[r13\]0xfffff:l\(r1,r0\)
+  e6:	ff ff 
+  e8:	40 c1 cd 0b 	storw	\$0x4:s,0xbcd <main\+0xbcd>:m
+  ec:	5a c1 cd ab 	storw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+  f0:	13 00 3f 3a 	storw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+  f4:	cd ab 
+  f6:	50 c4 14 00 	storw	\$0x5:s,\[r13\]0x14:m
+  fa:	40 c5 fc ab 	storw	\$0x4:s,\[r13\]0xabfc:m
+  fe:	30 c4 34 12 	storw	\$0x3:s,\[r12\]0x1234:m
+ 102:	30 c5 34 12 	storw	\$0x3:s,\[r12\]0x1234:m
+ 106:	30 c4 34 00 	storw	\$0x3:s,\[r12\]0x34:m
+ 10a:	30 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+ 10e:	31 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+ 112:	36 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+ 116:	32 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+ 11a:	37 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+ 11e:	33 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+ 122:	34 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+ 126:	35 c6 3a 4a 	storw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+ 12a:	38 c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+ 12e:	39 c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+ 132:	3e c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+ 136:	3a c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+ 13a:	3f c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+ 13e:	3b c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+ 142:	3c c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+ 146:	3d c6 3a 4a 	storw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+ 14a:	3e c6 5a 4b 	storw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+ 14e:	37 c6 1a 41 	storw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+ 152:	3f c6 14 01 	storw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+ 156:	13 00 36 2a 	storw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+ 15a:	de bc 
+ 15c:	13 00 5e 20 	storw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+ 160:	cd ab 
+ 162:	13 00 37 20 	storw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+ 166:	cd ab 
+ 168:	13 00 3f 20 	storw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+ 16c:	de bc 
+ 16e:	13 00 52 00 	storw	\$0x5:s,0x0:l\(r2\)
+ 172:	00 00 
+ 174:	3c c3 34 00 	storw	\$0x3:s,0x34:m\(r12\)
+ 178:	3d c3 ab 00 	storw	\$0x3:s,0xab:m\(r13\)
+ 17c:	13 00 51 00 	storw	\$0x5:s,0xad:l\(r1\)
+ 180:	ad 00 
+ 182:	13 00 52 00 	storw	\$0x5:s,0xcd:l\(r2\)
+ 186:	cd 00 
+ 188:	13 00 50 00 	storw	\$0x5:s,0xfff:l\(r0\)
+ 18c:	ff 0f 
+ 18e:	13 00 34 00 	storw	\$0x3:s,0xbcd:l\(r4\)
+ 192:	cd 0b 
+ 194:	3c c3 ff 0f 	storw	\$0x3:s,0xfff:m\(r12\)
+ 198:	3d c3 ff 0f 	storw	\$0x3:s,0xfff:m\(r13\)
+ 19c:	3d c3 ff ff 	storw	\$0x3:s,0xffff:m\(r13\)
+ 1a0:	3c c3 43 23 	storw	\$0x3:s,0x2343:m\(r12\)
+ 1a4:	13 00 32 01 	storw	\$0x3:s,0x2345:l\(r2\)
+ 1a8:	45 23 
+ 1aa:	13 00 38 04 	storw	\$0x3:s,0xabcd:l\(r8\)
+ 1ae:	cd ab 
+ 1b0:	13 00 3d 1f 	storw	\$0x3:s,0xfabcd:l\(r13\)
+ 1b4:	cd ab 
+ 1b6:	13 00 38 0f 	storw	\$0x3:s,0xabcd:l\(r8\)
+ 1ba:	cd ab 
+ 1bc:	13 00 39 0f 	storw	\$0x3:s,0xabcd:l\(r9\)
+ 1c0:	cd ab 
+ 1c2:	13 00 39 04 	storw	\$0x3:s,0xabcd:l\(r9\)
+ 1c6:	cd ab 
+ 1c8:	31 c2       	storw	\$0x3:s,0x0:s\(r2,r1\)
+ 1ca:	51 c3 01 00 	storw	\$0x5:s,0x1:m\(r2,r1\)
+ 1ce:	41 c3 34 12 	storw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1d2:	31 c3 34 12 	storw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1d6:	13 00 31 11 	storw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1da:	45 23 
+ 1dc:	31 c3 23 01 	storw	\$0x3:s,0x123:m\(r2,r1\)
+ 1e0:	13 00 31 11 	storw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1e4:	45 23 
diff --git a/gas/testsuite/gas/cr16/storw_test.s b/gas/testsuite/gas/cr16/storw_test.s
new file mode 100644
index 000000000000..6adee5cee1ff
--- /dev/null
+++ b/gas/testsuite/gas/cr16/storw_test.s
@@ -0,0 +1,144 @@
+        .text

+        .global main

+main:

+	######################

+	#  storw reg abs20/24 

+	######################

+	storw r0,0x0

+	storw r1,0xff

+	storw r3,0xfff

+	storw r4,0x1234

+	storw r5,0x1234

+	storw r0,0x7A1234

+	storw r1,0xBA1234

+	storw r2,0xffffff

+	######################

+	#  storw abs20 rel reg

+	######################

+	storw r0,[r12]0x0

+	storw r0,[r13]0x0

+	storw r1,[r12]0xff

+	storw r1,[r13]0xff

+	storw r3,[r12]0xfff

+	storw r3,[r13]0xfff

+	storw r4,[r12]0x1234

+	storw r4,[r13]0x1234

+	storw r5,[r12]0x1234

+	storw r5,[r13]0x1234

+	storw r2,[r12]0x4567

+	storw r2,[r13]0xA1234

+	###################################

+	#  storw reg rbase(disp20/-disp20) 

+	###################################

+	storw r1,0x4(r1,r0)

+	storw r3,0x4(r3,r2)

+	storw r4,0x1234(r1,r0)

+	storw r5,0x1234(r3,r2)

+	storw r6,0xA1234(r1,r0)

+	storw r1,-0x4(r1,r0)

+	storw r3,-0x4(r3,r2)

+	storw r4,-0x1234(r1,r0)

+	storw r5,-0x1234(r3,r2)

+	storw r6,-0xA1234(r1,r0)

+	#################################################

+	#  storw reg rpbase(disp4/disp16/disp20/-disp20) 

+	#################################################

+	storw r0,0x0(r1,r0)

+	storw r0,0x0(r1,r0)

+	storw r0,0xf(r1,r0)

+	storw r1,0xf(r1,r0)

+	storw r2,0x1234(r1,r0)

+	storw r3,0xabcd(r3,r2)

+	storw r4,0xAfff(r4,r3)

+	storw r5,0xA1234(r6,r5)

+	storw r0,-0xf(r1,r0)

+	storw r1,-0xf(r1,r0)

+	storw r2,-0x1234(r1,r0)

+	storw r3,-0xabcd(r3,r2)

+	storw r4,-0xAfff(r4,r3)

+	storw r5,-0xA1234(r6,r5)

+	####################################

+	#  storw rbase(disp0/disp14) rel reg

+	####################################

+	storw r0,[r12]0x0(r1,r0)

+	storw r1,[r13]0x0(r1,r0)

+	storw r2,[r12]0x1234(r1,r0)

+	storw r3,[r13]0x1abcd(r1,r0)

+	#################################

+	#  storw reg rpbase(disp20) rel

+	#################################

+	storw r4,[r12]0xA1234(r1,r0)

+	storw r5,[r13]0xB1234(r1,r0)

+	storw r6,[r13]0xfffff(r1,r0)

+	#######################

+	# storw reg, uimm16/20

+	######################

+	storw $4,0xbcd

+	storw $5,0xaabcd

+	storw $3,0xfaabcd

+

+	#######################

+	# storw reg, uimm16/20

+	######################

+	storw $5,[r12]0x14

+	storw $4,[r13]0xabfc

+	storw $3,[r12]0x1234

+	storw $3,[r13]0x1234

+	storw $3,[r12]0x34

+	#######################

+	# storw imm, index-rbase

+	######################

+	storw $3,[r12]0xa7a(r1,r0)

+	storw $3,[r12]0xa7a(r3,r2)

+	storw $3,[r12]0xa7a(r4,r3)

+	storw $3,[r12]0xa7a(r5,r4)

+	storw $3,[r12]0xa7a(r6,r5)

+	storw $3,[r12]0xa7a(r7,r6)

+	storw $3,[r12]0xa7a(r9,r8)

+	storw $3,[r12]0xa7a(r11,r10)

+	storw $3,[r13]0xa7a(r1,r0)

+	storw $3,[r13]0xa7a(r3,r2)

+	storw $3,[r13]0xa7a(r4,r3)

+	storw $3,[r13]0xa7a(r5,r4)

+	storw $3,[r13]0xa7a(r6,r5)

+	storw $3,[r13]0xa7a(r7,r6)

+	storw $3,[r13]0xa7a(r9,r8)

+	storw $3,[r13]0xa7a(r11,r10)

+	storw $5,[r13]0xb7a(r4,r3)

+	storw $1,[r12]0x17a(r6,r5)

+	storw $1,[r13]0x134(r6,r5)

+	storw $3,[r12]0xabcde(r4,r3)

+	storw $5,[r13]0xabcd(r4,r3)

+	storw $3,[r12]0xabcd(r6,r5)

+	storw $3,[r13]0xbcde(r6,r5)

+	#######################

+	# storw imm4, rbase(disp)

+	######################

+	storw $5,0x0(r2)

+	storw $3,0x34(r12)

+	storw $3,0xab(r13)

+	storw $5,0xad(r1)

+	storw $5,0xcd(r2)

+	storw $5,0xfff(r0)

+	storw $3,0xbcd(r4)

+	storw $3,0xfff(r12)

+	storw $3,0xfff(r13)

+	storw $3,0xffff(r13)

+	storw $3,0x2343(r12)

+	storw $3,0x12345(r2)

+	storw $3,0x4abcd(r8)

+	storw $3,0xfabcd(r13)

+	storw $3,0xfabcd(r8)

+	storw $3,0xfabcd(r9)

+	storw $3,0x4abcd(r9)

+	##########################

+	# storw imm, disp20(rpbase)

+	#########################

+	storw $3,0x0(r2,r1)

+	storw $5,0x1(r2,r1)

+	storw $4,0x1234(r2,r1)

+	storw $3,0x1234(r2,r1)

+	storw $3,0x12345(r2,r1)

+	storw $3,0x123(r2,r1)

+	storw $3,0x12345(r2,r1)

+

diff --git a/gas/testsuite/gas/cr16/sub_test.d b/gas/testsuite/gas/cr16/sub_test.d
new file mode 100644
index 000000000000..1744836588d1
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sub_test.d
@@ -0,0 +1,69 @@
+#as:
+#objdump:  -dr
+#name:  sub_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 38       	subb	\$0xf:s,r1
+   2:	b2 38 ff 00 	subb	\$0xff:m,r2
+   6:	b1 38 ff 0f 	subb	\$0xfff:m,r1
+   a:	b1 38 14 00 	subb	\$0x14:m,r1
+   e:	a2 38       	subb	\$0xa:s,r2
+  10:	12 39       	subb	r1,r2
+  12:	23 39       	subb	r2,r3
+  14:	34 39       	subb	r3,r4
+  16:	56 39       	subb	r5,r6
+  18:	67 39       	subb	r6,r7
+  1a:	78 39       	subb	r7,r8
+  1c:	f1 3c       	subcb	\$0xf:s,r1
+  1e:	b2 3c ff 00 	subcb	\$0xff:m,r2
+  22:	b1 3c ff 0f 	subcb	\$0xfff:m,r1
+  26:	b1 3c 14 00 	subcb	\$0x14:m,r1
+  2a:	a2 3c       	subcb	\$0xa:s,r2
+  2c:	12 3d       	subcb	r1,r2
+  2e:	23 3d       	subcb	r2,r3
+  30:	34 3d       	subcb	r3,r4
+  32:	56 3d       	subcb	r5,r6
+  34:	67 3d       	subcb	r6,r7
+  36:	78 3d       	subcb	r7,r8
+  38:	f1 3e       	subcw	\$0xf:s,r1
+  3a:	b2 3e ff 00 	subcw	\$0xff:m,r2
+  3e:	b1 3e ff 0f 	subcw	\$0xfff:m,r1
+  42:	b1 3e 14 00 	subcw	\$0x14:m,r1
+  46:	a2 3e       	subcw	\$0xa:s,r2
+  48:	12 3f       	subcw	r1,r2
+  4a:	23 3f       	subcw	r2,r3
+  4c:	34 3f       	subcw	r3,r4
+  4e:	56 3f       	subcw	r5,r6
+  50:	67 3f       	subcw	r6,r7
+  52:	78 3f       	subcw	r7,r8
+  54:	f1 3a       	subw	\$0xf:s,r1
+  56:	b2 3a ff 00 	subw	\$0xff:m,r2
+  5a:	b1 3a ff 0f 	subw	\$0xfff:m,r1
+  5e:	b1 3a 14 00 	subw	\$0x14:m,r1
+  62:	a2 3a       	subw	\$0xa:s,r2
+  64:	12 3b       	subw	r1,r2
+  66:	23 3b       	subw	r2,r3
+  68:	34 3b       	subw	r3,r4
+  6a:	56 3b       	subw	r5,r6
+  6c:	67 3b       	subw	r6,r7
+  6e:	78 3b       	subw	r7,r8
+  70:	31 00 00 00 	subd	\$0xf:l,\(r2,r1\)
+  74:	0f 00 
+  76:	31 00 00 00 	subd	\$0xff:l,\(r2,r1\)
+  7a:	ff 00 
+  7c:	31 00 00 00 	subd	\$0xfff:l,\(r2,r1\)
+  80:	ff 0f 
+  82:	31 00 00 00 	subd	\$0xffff:l,\(r2,r1\)
+  86:	ff ff 
+  88:	31 00 0f 00 	subd	\$0xfffff:l,\(r2,r1\)
+  8c:	ff ff 
+  8e:	31 00 ff 0f 	subd	\$0xfffffff:l,\(r2,r1\)
+  92:	ff ff 
+  94:	31 00 ff ff 	subd	\$0xffffffff:l,\(r2,r1\)
+  98:	ff ff 
+  9a:	14 00 31 c0 	subd	\(r4,r3\),\(r2,r1\)
+  9e:	14 00 31 c0 	subd	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/sub_test.s b/gas/testsuite/gas/cr16/sub_test.s
new file mode 100644
index 000000000000..ad0ac07a6ef8
--- /dev/null
+++ b/gas/testsuite/gas/cr16/sub_test.s
@@ -0,0 +1,93 @@
+        .text
+        .global main
+main:
+        ###########
+	# SUBB imm4/imm16, reg
+        ###########
+	subb    $0xf,r1
+	subb    $0xff,r2
+	subb    $0xfff,r1
+	#subb    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subb    $20,r1
+	subb    $10,r2
+        ###########
+	# SUBB reg, reg
+        ###########
+	subb    r1,r2
+	subb    r2,r3
+	subb    r3,r4
+	subb    r5,r6
+	subb    r6,r7
+	subb    r7,r8
+        ###########
+	# SUBCB imm4/imm16, reg
+        ###########
+	subcb    $0xf,r1
+	subcb    $0xff,r2
+	subcb    $0xfff,r1
+	#subcb    $0xffff,r2   // CHECK WITH CRASM 4.1
+	subcb    $20,r1
+	subcb    $10,r2
+        ###########
+	# SUBCB reg, reg
+        ###########
+	subcb    r1,r2
+	subcb    r2,r3
+	subcb    r3,r4
+	subcb    r5,r6
+	subcb    r6,r7
+	subcb    r7,r8
+        ###########
+	# SUBCW imm4/imm16, reg
+        ###########
+	subcw    $0xf,r1
+	subcw    $0xff,r2
+	subcw    $0xfff,r1
+	#subcw    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subcw    $20,r1
+	subcw    $10,r2
+        ###########
+	# SUBCW reg, reg
+        ###########
+	subcw    r1,r2
+	subcw    r2,r3
+	subcw    r3,r4
+	subcw    r5,r6
+	subcw    r6,r7
+	subcw    r7,r8
+        ###########
+	# SUBW imm4/imm16, reg
+        ###########
+	subw    $0xf,r1
+	subw    $0xff,r2
+	subw    $0xfff,r1
+	#subw    $0xffff,r2  // CHECK WITH CRASM 4.1
+	subw    $20,r1
+	subw    $10,r2
+        ###########
+	# SUBW reg, reg
+        ###########
+	subw    r1,r2
+	subw    r2,r3
+	subw    r3,r4
+	subw    r5,r6
+	subw    r6,r7
+	subw    r7,r8
+        ###########
+	# SUBD imm4/imm16/imm32, regp
+        ###########
+	subd    $0xf,(r2,r1)
+	subd    $0xff,(r2,r1)
+	subd    $0xfff,(r2,r1)
+	subd    $0xffff,(r2,r1)
+	subd    $0xfffff,(r2,r1)
+	subd    $0xfffffff,(r2,r1)
+	subd    $0xffffffff,(r2,r1)
+        ###########
+	# SUBD regp, regp
+        ###########
+	subd    (r4,r3),(r2,r1)
+	subd    (r4,r3),(r2,r1)
+	#subd    $10,(sp)
+	#subd    $14,(sp)
+	#subd    $8,(sp)
diff --git a/gas/testsuite/gas/cr16/tbit_test.d b/gas/testsuite/gas/cr16/tbit_test.d
new file mode 100644
index 000000000000..cf5b4993b942
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbit_test.d
@@ -0,0 +1,37 @@
+#as:
+#objdump:  -dr
+#name:  tbit_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	00 06       	tbit	\$0x0:s,r0
+   2:	11 06       	tbit	\$0x1:s,r1
+   4:	22 06       	tbit	\$0x2:s,r2
+   6:	33 06       	tbit	\$0x3:s,r3
+   8:	44 06       	tbit	\$0x4:s,r4
+   a:	55 06       	tbit	\$0x5:s,r5
+   c:	66 06       	tbit	\$0x6:s,r6
+   e:	77 06       	tbit	\$0x7:s,r7
+  10:	88 06       	tbit	\$0x8:s,r8
+  12:	99 06       	tbit	\$0x9:s,r9
+  14:	aa 06       	tbit	\$0xa:s,r10
+  16:	bb 06       	tbit	\$0xb:s,r11
+  18:	cc 06       	tbit	\$0xc:s,r12
+  1a:	dd 06       	tbit	\$0xd:s,r13
+  1c:	00 07       	tbit	r0,r0
+  1e:	11 07       	tbit	r1,r1
+  20:	22 07       	tbit	r2,r2
+  22:	33 07       	tbit	r3,r3
+  24:	44 07       	tbit	r4,r4
+  26:	55 07       	tbit	r5,r5
+  28:	66 07       	tbit	r6,r6
+  2a:	77 07       	tbit	r7,r7
+  2c:	88 07       	tbit	r8,r8
+  2e:	99 07       	tbit	r9,r9
+  30:	aa 07       	tbit	r10,r10
+  32:	bb 07       	tbit	r11,r11
+  34:	cc 07       	tbit	r12,r12
+  36:	dd 07       	tbit	r13,r13
diff --git a/gas/testsuite/gas/cr16/tbit_test.s b/gas/testsuite/gas/cr16/tbit_test.s
new file mode 100644
index 000000000000..aec79232e4e4
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbit_test.s
@@ -0,0 +1,41 @@
+        .text
+        .global main
+main:
+	##################
+	# tbit uimm4, reg
+	#################
+	tbit	$0,r0
+	tbit	$1,r1
+	tbit	$2,r2
+	tbit	$3,r3
+	tbit	$4,r4
+	tbit	$5,r5
+	tbit	$6,r6
+	tbit	$7,r7
+	tbit	$8,r8
+	tbit	$9,r9
+	tbit	$10,r10
+	tbit	$11,r11
+	tbit	$12,r12
+	tbit	$13,r13
+#	tbit	$14,r14 // Add error check for these INST
+#	tbit	$15,r15 // Add error check for these INST
+	##################
+	# tbit reg, reg
+	#################
+	tbit	r0,r0
+	tbit	r1,r1
+	tbit	r2,r2
+	tbit	r3,r3
+	tbit	r4,r4
+	tbit	r5,r5
+	tbit	r6,r6
+	tbit	r7,r7
+	tbit	r8,r8
+	tbit	r9,r9
+	tbit	r10,r10
+	tbit	r11,r11
+	tbit	r12,r12
+	tbit	r13,r13
+#	tbit	r14,r14 // Add error check for these INST
+#	tbit	r15,r15 // Add error check for these INST
diff --git a/gas/testsuite/gas/cr16/tbitb_test.d b/gas/testsuite/gas/cr16/tbitb_test.d
new file mode 100644
index 000000000000..9965fac585cc
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitb_test.d
@@ -0,0 +1,82 @@
+#as:
+#objdump:  -dr
+#name:  tbitb_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	c0 7b cd 0b 	tbitb	\$0x4,0xbcd <main\+0xbcd>:m
+   4:	da 7b cd ab 	tbitb	\$0x5,0xaabcd <main\+0xaabcd>:m
+   8:	10 00 3f fa 	tbitb	\$0x3,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	50 78 14 00 	tbitb	\$0x5,\[r12\]0x14:m
+  12:	c0 78 fc ab 	tbitb	\$0x4,\[r13\]0xabfc:m
+  16:	30 78 34 12 	tbitb	\$0x3,\[r12\]0x1234:m
+  1a:	b0 78 34 12 	tbitb	\$0x3,\[r13\]0x1234:m
+  1e:	30 78 34 00 	tbitb	\$0x3,\[r12\]0x34:m
+  22:	b0 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r1,r0\)
+  26:	b1 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r3,r2\)
+  2a:	b6 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r4,r3\)
+  2e:	b2 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r5,r4\)
+  32:	b7 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r6,r5\)
+  36:	b3 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r7,r6\)
+  3a:	b4 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r9,r8\)
+  3e:	b5 7a 3a 4a 	tbitb	\$0x3,\[r12\]0xa7a:m\(r11,r10\)
+  42:	b8 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r1,r0\)
+  46:	b9 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r3,r2\)
+  4a:	be 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r4,r3\)
+  4e:	ba 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r5,r4\)
+  52:	bf 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r6,r5\)
+  56:	bb 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r7,r6\)
+  5a:	bc 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r9,r8\)
+  5e:	bd 7a 3a 4a 	tbitb	\$0x3,\[r13\]0xa7a:m\(r11,r10\)
+  62:	be 7a 5a 4b 	tbitb	\$0x5,\[r13\]0xb7a:m\(r4,r3\)
+  66:	b7 7a 1a 41 	tbitb	\$0x1,\[r12\]0x17a:m\(r6,r5\)
+  6a:	bf 7a 14 01 	tbitb	\$0x1,\[r13\]0x134:m\(r6,r5\)
+  6e:	10 00 36 ea 	tbitb	\$0x3,\[r12\]0xabcde:l\(r4,r3\)
+  72:	de bc 
+  74:	10 00 5e e0 	tbitb	\$0x5,\[r13\]0xabcd:l\(r4,r3\)
+  78:	cd ab 
+  7a:	10 00 37 e0 	tbitb	\$0x3,\[r12\]0xabcd:l\(r6,r5\)
+  7e:	cd ab 
+  80:	10 00 3f e0 	tbitb	\$0x3,\[r13\]0xbcde:l\(r6,r5\)
+  84:	de bc 
+  86:	10 00 52 c0 	tbitb	\$0x5,0x0:l\(r2\)
+  8a:	00 00 
+  8c:	3c 7b 34 00 	tbitb	\$0x3,0x34:m\(r12\)
+  90:	3d 7b ab 00 	tbitb	\$0x3,0xab:m\(r13\)
+  94:	10 00 51 c0 	tbitb	\$0x5,0xad:l\(r1\)
+  98:	ad 00 
+  9a:	10 00 52 c0 	tbitb	\$0x5,0xcd:l\(r2\)
+  9e:	cd 00 
+  a0:	10 00 50 c0 	tbitb	\$0x5,0xfff:l\(r0\)
+  a4:	ff 0f 
+  a6:	10 00 34 c0 	tbitb	\$0x3,0xbcd:l\(r4\)
+  aa:	cd 0b 
+  ac:	3c 7b ff 0f 	tbitb	\$0x3,0xfff:m\(r12\)
+  b0:	3d 7b ff 0f 	tbitb	\$0x3,0xfff:m\(r13\)
+  b4:	3d 7b ff ff 	tbitb	\$0x3,0xffff:m\(r13\)
+  b8:	3c 7b 43 23 	tbitb	\$0x3,0x2343:m\(r12\)
+  bc:	10 00 32 c1 	tbitb	\$0x3,0x2345:l\(r2\)
+  c0:	45 23 
+  c2:	10 00 38 c4 	tbitb	\$0x3,0xabcd:l\(r8\)
+  c6:	cd ab 
+  c8:	10 00 3d df 	tbitb	\$0x3,0xfabcd:l\(r13\)
+  cc:	cd ab 
+  ce:	10 00 38 cf 	tbitb	\$0x3,0xabcd:l\(r8\)
+  d2:	cd ab 
+  d4:	10 00 39 cf 	tbitb	\$0x3,0xabcd:l\(r9\)
+  d8:	cd ab 
+  da:	10 00 39 c4 	tbitb	\$0x3,0xabcd:l\(r9\)
+  de:	cd ab 
+  e0:	31 7a       	tbitb	\$0x3,0x0:s\(r2,r1\)
+  e2:	51 7b 01 00 	tbitb	\$0x5,0x1:m\(r2,r1\)
+  e6:	41 7b 34 12 	tbitb	\$0x4,0x1234:m\(r2,r1\)
+  ea:	31 7b 34 12 	tbitb	\$0x3,0x1234:m\(r2,r1\)
+  ee:	10 00 31 d1 	tbitb	\$0x3,0x12345:l\(r2,r1\)
+  f2:	45 23 
+  f4:	31 7b 23 01 	tbitb	\$0x3,0x123:m\(r2,r1\)
+  f8:	10 00 31 d1 	tbitb	\$0x3,0x12345:l\(r2,r1\)
+  fc:	45 23 
diff --git a/gas/testsuite/gas/cr16/tbitb_test.s b/gas/testsuite/gas/cr16/tbitb_test.s
new file mode 100644
index 000000000000..7fe427ee02af
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitb_test.s
@@ -0,0 +1,62 @@
+        .text
+        .global main
+main:
+	tbitb $4,0xbcd
+	tbitb $5,0xaabcd
+	tbitb $3,0xfaabcd
+
+	tbitb $5,[r12]0x14
+	tbitb $4,[r13]0xabfc
+	tbitb $3,[r12]0x1234
+	tbitb $3,[r13]0x1234
+	tbitb $3,[r12]0x34
+
+	tbitb $3,[r12]0xa7a(r1,r0)
+	tbitb $3,[r12]0xa7a(r3,r2)
+	tbitb $3,[r12]0xa7a(r4,r3)
+	tbitb $3,[r12]0xa7a(r5,r4)
+	tbitb $3,[r12]0xa7a(r6,r5)
+	tbitb $3,[r12]0xa7a(r7,r6)
+	tbitb $3,[r12]0xa7a(r9,r8)
+	tbitb $3,[r12]0xa7a(r11,r10)
+	tbitb $3,[r13]0xa7a(r1,r0)
+	tbitb $3,[r13]0xa7a(r3,r2)
+	tbitb $3,[r13]0xa7a(r4,r3)
+	tbitb $3,[r13]0xa7a(r5,r4)
+	tbitb $3,[r13]0xa7a(r6,r5)
+	tbitb $3,[r13]0xa7a(r7,r6)
+	tbitb $3,[r13]0xa7a(r9,r8)
+	tbitb $3,[r13]0xa7a(r11,r10)
+	tbitb $5,[r13]0xb7a(r4,r3)
+	tbitb $1,[r12]0x17a(r6,r5)
+	tbitb $1,[r13]0x134(r6,r5)
+	tbitb $3,[r12]0xabcde(r4,r3)
+	tbitb $5,[r13]0xabcd(r4,r3)
+	tbitb $3,[r12]0xabcd(r6,r5)
+	tbitb $3,[r13]0xbcde(r6,r5)
+
+	tbitb $5,0x0(r2)
+	tbitb $3,0x34(r12)
+	tbitb $3,0xab(r13)
+	tbitb $5,0xad(r1)
+	tbitb $5,0xcd(r2)
+	tbitb $5,0xfff(r0)
+	tbitb $3,0xbcd(r4)
+	tbitb $3,0xfff(r12)
+	tbitb $3,0xfff(r13)
+	tbitb $3,0xffff(r13)
+	tbitb $3,0x2343(r12)
+	tbitb $3,0x12345(r2)
+	tbitb $3,0x4abcd(r8)
+	tbitb $3,0xfabcd(r13)
+	tbitb $3,0xfabcd(r8)
+	tbitb $3,0xfabcd(r9)
+	tbitb $3,0x4abcd(r9)
+
+	tbitb $3,0x0(r2,r1)
+	tbitb $5,0x1(r2,r1)
+	tbitb $4,0x1234(r2,r1)
+	tbitb $3,0x1234(r2,r1)
+	tbitb $3,0x12345(r2,r1)
+	tbitb $3,0x123(r2,r1)
+	tbitb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/tbitw_test.d b/gas/testsuite/gas/cr16/tbitw_test.d
new file mode 100644
index 000000000000..81022b1a8cec
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitw_test.d
@@ -0,0 +1,155 @@
+#as:
+#objdump:  -dr
+#name:  tbitw_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	40 7f cd 0b 	tbitw	\$0x4:s,0xbcd <main\+0xbcd>:m
+   4:	5a 7f cd ab 	tbitw	\$0x5:s,0xaabcd <main\+0xaabcd>:m
+   8:	11 00 3f fa 	tbitw	\$0x3:s,0xfaabcd <main\+0xfaabcd>:l
+   c:	cd ab 
+   e:	a0 7f cd 0b 	tbitw	\$0xa:s,0xbcd <main\+0xbcd>:m
+  12:	fa 7f cd ab 	tbitw	\$0xf:s,0xaabcd <main\+0xaabcd>:m
+  16:	11 00 ef fa 	tbitw	\$0xe:s,0xfaabcd <main\+0xfaabcd>:l
+  1a:	cd ab 
+  1c:	50 7c 14 00 	tbitw	\$0x5:s,\[r13\]0x14:m
+  20:	40 7d fc ab 	tbitw	\$0x4:s,\[r13\]0xabfc:m
+  24:	30 7c 34 12 	tbitw	\$0x3:s,\[r12\]0x1234:m
+  28:	30 7d 34 12 	tbitw	\$0x3:s,\[r12\]0x1234:m
+  2c:	30 7c 34 00 	tbitw	\$0x3:s,\[r12\]0x34:m
+  30:	f0 7c 14 00 	tbitw	\$0xf:s,\[r13\]0x14:m
+  34:	e0 7d fc ab 	tbitw	\$0xe:s,\[r13\]0xabfc:m
+  38:	d0 7c 34 12 	tbitw	\$0xd:s,\[r13\]0x1234:m
+  3c:	d0 7d 34 12 	tbitw	\$0xd:s,\[r13\]0x1234:m
+  40:	b0 7c 34 00 	tbitw	\$0xb:s,\[r12\]0x34:m
+  44:	f0 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r1,r0\)
+  48:	f1 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r3,r2\)
+  4c:	f6 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r4,r3\)
+  50:	f2 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r5,r4\)
+  54:	f7 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r6,r5\)
+  58:	f3 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r7,r6\)
+  5c:	f4 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r9,r8\)
+  60:	f5 7a 3a 4a 	tbitw	\$0x3:s,\[r12\]0xa7a:m\(r11,r10\)
+  64:	f8 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r1,r0\)
+  68:	f9 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r3,r2\)
+  6c:	fe 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r4,r3\)
+  70:	fa 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r5,r4\)
+  74:	ff 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r6,r5\)
+  78:	fb 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r7,r6\)
+  7c:	fc 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r9,r8\)
+  80:	fd 7a 3a 4a 	tbitw	\$0x3:s,\[r13\]0xa7a:m\(r11,r10\)
+  84:	fe 7a 5a 4b 	tbitw	\$0x5:s,\[r13\]0xb7a:m\(r4,r3\)
+  88:	f7 7a 1a 41 	tbitw	\$0x1:s,\[r12\]0x17a:m\(r6,r5\)
+  8c:	ff 7a 14 01 	tbitw	\$0x1:s,\[r13\]0x134:m\(r6,r5\)
+  90:	11 00 36 ea 	tbitw	\$0x3:s,\[r12\]0xabcde:l\(r4,r3\)
+  94:	de bc 
+  96:	11 00 5e e0 	tbitw	\$0x5:s,\[r13\]0xabcd:l\(r4,r3\)
+  9a:	cd ab 
+  9c:	11 00 37 e0 	tbitw	\$0x3:s,\[r12\]0xabcd:l\(r6,r5\)
+  a0:	cd ab 
+  a2:	11 00 3f e0 	tbitw	\$0x3:s,\[r13\]0xbcde:l\(r6,r5\)
+  a6:	de bc 
+  a8:	f0 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r1,r0\)
+  ac:	f1 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r3,r2\)
+  b0:	f6 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r4,r3\)
+  b4:	f2 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r5,r4\)
+  b8:	f7 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r6,r5\)
+  bc:	f3 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r7,r6\)
+  c0:	f4 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r9,r8\)
+  c4:	f5 7a da 4a 	tbitw	\$0xd:s,\[r12\]0xafa:m\(r11,r10\)
+  c8:	f8 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r1,r0\)
+  cc:	f9 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r3,r2\)
+  d0:	fe 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r4,r3\)
+  d4:	fa 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r5,r4\)
+  d8:	ff 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r6,r5\)
+  dc:	fb 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r7,r6\)
+  e0:	fc 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r9,r8\)
+  e4:	fd 7a da 4a 	tbitw	\$0xd:s,\[r13\]0xafa:m\(r11,r10\)
+  e8:	fe 7a fa 4b 	tbitw	\$0xf:s,\[r13\]0xbfa:m\(r4,r3\)
+  ec:	f7 7a ba 41 	tbitw	\$0xb:s,\[r12\]0x1fa:m\(r6,r5\)
+  f0:	ff 7a b4 01 	tbitw	\$0xb:s,\[r13\]0x1b4:m\(r6,r5\)
+  f4:	11 00 d6 ea 	tbitw	\$0xd:s,\[r12\]0xabcde:l\(r4,r3\)
+  f8:	de bc 
+  fa:	11 00 fe e0 	tbitw	\$0xf:s,\[r13\]0xabcd:l\(r4,r3\)
+  fe:	cd ab 
+ 100:	11 00 d7 e0 	tbitw	\$0xd:s,\[r12\]0xabcd:l\(r6,r5\)
+ 104:	cd ab 
+ 106:	11 00 df e0 	tbitw	\$0xd:s,\[r13\]0xbcde:l\(r6,r5\)
+ 10a:	de bc 
+ 10c:	11 00 52 c0 	tbitw	\$0x5:s,0x0:l\(r2\)
+ 110:	00 00 
+ 112:	3c 79 34 00 	tbitw	\$0x3:s,0x34:m\(r12\)
+ 116:	3d 79 ab 00 	tbitw	\$0x3:s,0xab:m\(r13\)
+ 11a:	11 00 51 c0 	tbitw	\$0x5:s,0xad:l\(r1\)
+ 11e:	ad 00 
+ 120:	11 00 52 c0 	tbitw	\$0x5:s,0xcd:l\(r2\)
+ 124:	cd 00 
+ 126:	11 00 50 c0 	tbitw	\$0x5:s,0xfff:l\(r0\)
+ 12a:	ff 0f 
+ 12c:	11 00 34 c0 	tbitw	\$0x3:s,0xbcd:l\(r4\)
+ 130:	cd 0b 
+ 132:	3c 79 ff 0f 	tbitw	\$0x3:s,0xfff:m\(r12\)
+ 136:	3d 79 ff 0f 	tbitw	\$0x3:s,0xfff:m\(r13\)
+ 13a:	3d 79 ff ff 	tbitw	\$0x3:s,0xffff:m\(r13\)
+ 13e:	3c 79 43 23 	tbitw	\$0x3:s,0x2343:m\(r12\)
+ 142:	11 00 32 c1 	tbitw	\$0x3:s,0x2345:l\(r2\)
+ 146:	45 23 
+ 148:	11 00 38 c4 	tbitw	\$0x3:s,0xabcd:l\(r8\)
+ 14c:	cd ab 
+ 14e:	11 00 3d df 	tbitw	\$0x3:s,0xfabcd:l\(r13\)
+ 152:	cd ab 
+ 154:	11 00 38 cf 	tbitw	\$0x3:s,0xabcd:l\(r8\)
+ 158:	cd ab 
+ 15a:	11 00 39 cf 	tbitw	\$0x3:s,0xabcd:l\(r9\)
+ 15e:	cd ab 
+ 160:	11 00 39 c4 	tbitw	\$0x3:s,0xabcd:l\(r9\)
+ 164:	cd ab 
+ 166:	11 00 f2 c0 	tbitw	\$0xf:s,0x0:l\(r2\)
+ 16a:	00 00 
+ 16c:	dc 79 34 00 	tbitw	\$0xd:s,0x34:m\(r12\)
+ 170:	dd 79 ab 00 	tbitw	\$0xd:s,0xab:m\(r13\)
+ 174:	11 00 f1 c0 	tbitw	\$0xf:s,0xad:l\(r1\)
+ 178:	ad 00 
+ 17a:	11 00 f2 c0 	tbitw	\$0xf:s,0xcd:l\(r2\)
+ 17e:	cd 00 
+ 180:	11 00 f0 c0 	tbitw	\$0xf:s,0xfff:l\(r0\)
+ 184:	ff 0f 
+ 186:	11 00 d4 c0 	tbitw	\$0xd:s,0xbcd:l\(r4\)
+ 18a:	cd 0b 
+ 18c:	dc 79 ff 0f 	tbitw	\$0xd:s,0xfff:m\(r12\)
+ 190:	dd 79 ff 0f 	tbitw	\$0xd:s,0xfff:m\(r13\)
+ 194:	dd 79 ff ff 	tbitw	\$0xd:s,0xffff:m\(r13\)
+ 198:	dc 79 43 23 	tbitw	\$0xd:s,0x2343:m\(r12\)
+ 19c:	11 00 d2 c1 	tbitw	\$0xd:s,0x2345:l\(r2\)
+ 1a0:	45 23 
+ 1a2:	11 00 d8 c4 	tbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1a6:	cd ab 
+ 1a8:	11 00 dd df 	tbitw	\$0xd:s,0xfabcd:l\(r13\)
+ 1ac:	cd ab 
+ 1ae:	11 00 d8 cf 	tbitw	\$0xd:s,0xabcd:l\(r8\)
+ 1b2:	cd ab 
+ 1b4:	11 00 d9 cf 	tbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1b8:	cd ab 
+ 1ba:	11 00 d9 c4 	tbitw	\$0xd:s,0xabcd:l\(r9\)
+ 1be:	cd ab 
+ 1c0:	31 7e       	tbitw	\$0x3:s,0x0:s\(r2,r1\)
+ 1c2:	51 79 01 00 	tbitw	\$0x5:s,0x1:m\(r2,r1\)
+ 1c6:	41 79 34 12 	tbitw	\$0x4:s,0x1234:m\(r2,r1\)
+ 1ca:	31 79 34 12 	tbitw	\$0x3:s,0x1234:m\(r2,r1\)
+ 1ce:	11 00 31 d1 	tbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1d2:	45 23 
+ 1d4:	31 79 23 01 	tbitw	\$0x3:s,0x123:m\(r2,r1\)
+ 1d8:	11 00 31 d1 	tbitw	\$0x3:s,0x12345:l\(r2,r1\)
+ 1dc:	45 23 
+ 1de:	d1 7e       	tbitw	\$0xd:s,0x0:s\(r2,r1\)
+ 1e0:	f1 79 01 00 	tbitw	\$0xf:s,0x1:m\(r2,r1\)
+ 1e4:	e1 79 34 12 	tbitw	\$0xe:s,0x1234:m\(r2,r1\)
+ 1e8:	d1 79 34 12 	tbitw	\$0xd:s,0x1234:m\(r2,r1\)
+ 1ec:	11 00 d1 d1 	tbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1f0:	45 23 
+ 1f2:	d1 79 23 01 	tbitw	\$0xd:s,0x123:m\(r2,r1\)
+ 1f6:	11 00 d1 d1 	tbitw	\$0xd:s,0x12345:l\(r2,r1\)
+ 1fa:	45 23 
diff --git a/gas/testsuite/gas/cr16/tbitw_test.s b/gas/testsuite/gas/cr16/tbitw_test.s
new file mode 100644
index 000000000000..939804cd0094
--- /dev/null
+++ b/gas/testsuite/gas/cr16/tbitw_test.s
@@ -0,0 +1,117 @@
+        .text
+        .global main
+main:
+	tbitw $4,0xbcd
+	tbitw $5,0xaabcd
+	tbitw $3,0xfaabcd
+	tbitw $10,0xbcd
+	tbitw $15,0xaabcd
+	tbitw $14,0xfaabcd
+
+	tbitw $5,[r12]0x14
+	tbitw $4,[r13]0xabfc
+	tbitw $3,[r12]0x1234
+	tbitw $3,[r13]0x1234
+	tbitw $3,[r12]0x34
+	tbitw $15,[r12]0x14
+	tbitw $14,[r13]0xabfc
+	tbitw $13,[r12]0x1234
+	tbitw $13,[r13]0x1234
+	tbitw $11,[r12]0x34
+
+	tbitw $3,[r12]0xa7a(r1,r0)
+	tbitw $3,[r12]0xa7a(r3,r2)
+	tbitw $3,[r12]0xa7a(r4,r3)
+	tbitw $3,[r12]0xa7a(r5,r4)
+	tbitw $3,[r12]0xa7a(r6,r5)
+	tbitw $3,[r12]0xa7a(r7,r6)
+	tbitw $3,[r12]0xa7a(r9,r8)
+	tbitw $3,[r12]0xa7a(r11,r10)
+	tbitw $3,[r13]0xa7a(r1,r0)
+	tbitw $3,[r13]0xa7a(r3,r2)
+	tbitw $3,[r13]0xa7a(r4,r3)
+	tbitw $3,[r13]0xa7a(r5,r4)
+	tbitw $3,[r13]0xa7a(r6,r5)
+	tbitw $3,[r13]0xa7a(r7,r6)
+	tbitw $3,[r13]0xa7a(r9,r8)
+	tbitw $3,[r13]0xa7a(r11,r10)
+	tbitw $5,[r13]0xb7a(r4,r3)
+	tbitw $1,[r12]0x17a(r6,r5)
+	tbitw $1,[r13]0x134(r6,r5)
+	tbitw $3,[r12]0xabcde(r4,r3)
+	tbitw $5,[r13]0xabcd(r4,r3)
+	tbitw $3,[r12]0xabcd(r6,r5)
+	tbitw $3,[r13]0xbcde(r6,r5)
+	tbitw $13,[r12]0xa7a(r1,r0)
+	tbitw $13,[r12]0xa7a(r3,r2)
+	tbitw $13,[r12]0xa7a(r4,r3)
+	tbitw $13,[r12]0xa7a(r5,r4)
+	tbitw $13,[r12]0xa7a(r6,r5)
+	tbitw $13,[r12]0xa7a(r7,r6)
+	tbitw $13,[r12]0xa7a(r9,r8)
+	tbitw $13,[r12]0xa7a(r11,r10)
+	tbitw $13,[r13]0xa7a(r1,r0)
+	tbitw $13,[r13]0xa7a(r3,r2)
+	tbitw $13,[r13]0xa7a(r4,r3)
+	tbitw $13,[r13]0xa7a(r5,r4)
+	tbitw $13,[r13]0xa7a(r6,r5)
+	tbitw $13,[r13]0xa7a(r7,r6)
+	tbitw $13,[r13]0xa7a(r9,r8)
+	tbitw $13,[r13]0xa7a(r11,r10)
+	tbitw $15,[r13]0xb7a(r4,r3)
+	tbitw $11,[r12]0x17a(r6,r5)
+	tbitw $11,[r13]0x134(r6,r5)
+	tbitw $13,[r12]0xabcde(r4,r3)
+	tbitw $15,[r13]0xabcd(r4,r3)
+	tbitw $13,[r12]0xabcd(r6,r5)
+	tbitw $13,[r13]0xbcde(r6,r5)
+
+	tbitw $5,0x0(r2)
+	tbitw $3,0x34(r12)
+	tbitw $3,0xab(r13)
+	tbitw $5,0xad(r1)
+	tbitw $5,0xcd(r2)
+	tbitw $5,0xfff(r0)
+	tbitw $3,0xbcd(r4)
+	tbitw $3,0xfff(r12)
+	tbitw $3,0xfff(r13)
+	tbitw $3,0xffff(r13)
+	tbitw $3,0x2343(r12)
+	tbitw $3,0x12345(r2)
+	tbitw $3,0x4abcd(r8)
+	tbitw $3,0xfabcd(r13)
+	tbitw $3,0xfabcd(r8)
+	tbitw $3,0xfabcd(r9)
+	tbitw $3,0x4abcd(r9)
+	tbitw $15,0x0(r2)
+	tbitw $13,0x34(r12)
+	tbitw $13,0xab(r13)
+	tbitw $15,0xad(r1)
+	tbitw $15,0xcd(r2)
+	tbitw $15,0xfff(r0)
+	tbitw $13,0xbcd(r4)
+	tbitw $13,0xfff(r12)
+	tbitw $13,0xfff(r13)
+	tbitw $13,0xffff(r13)
+	tbitw $13,0x2343(r12)
+	tbitw $13,0x12345(r2)
+	tbitw $13,0x4abcd(r8)
+	tbitw $13,0xfabcd(r13)
+	tbitw $13,0xfabcd(r8)
+	tbitw $13,0xfabcd(r9)
+	tbitw $13,0x4abcd(r9)
+
+	tbitw $3,0x0(r2,r1)
+	tbitw $5,0x1(r2,r1)
+	tbitw $4,0x1234(r2,r1)
+	tbitw $3,0x1234(r2,r1)
+	tbitw $3,0x12345(r2,r1)
+	tbitw $3,0x123(r2,r1)
+	tbitw $3,0x12345(r2,r1)
+	tbitw $13,0x0(r2,r1)
+	tbitw $15,0x1(r2,r1)
+	tbitw $14,0x1234(r2,r1)
+	tbitw $13,0x1234(r2,r1)
+	tbitw $13,0x12345(r2,r1)
+	tbitw $13,0x123(r2,r1)
+	tbitw $13,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/xor_test.d b/gas/testsuite/gas/cr16/xor_test.d
new file mode 100644
index 000000000000..57f7e23676e0
--- /dev/null
+++ b/gas/testsuite/gas/cr16/xor_test.d
@@ -0,0 +1,49 @@
+#as:
+#objdump:  -dr
+#name:  xor_test
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	f1 28       	xorb	\$0xf:s,r1
+   2:	b2 28 ff 00 	xorb	\$0xff:m,r2
+   6:	b1 28 ff 0f 	xorb	\$0xfff:m,r1
+   a:	b2 28 ff ff 	xorb	\$0xffff:m,r2
+   e:	b1 28 14 00 	xorb	\$0x14:m,r1
+  12:	a2 28       	xorb	\$0xa:s,r2
+  14:	12 29       	xorb	r1,r2
+  16:	23 29       	xorb	r2,r3
+  18:	34 29       	xorb	r3,r4
+  1a:	56 29       	xorb	r5,r6
+  1c:	67 29       	xorb	r6,r7
+  1e:	78 29       	xorb	r7,r8
+  20:	f1 2a       	xorw	\$0xf:s,r1
+  22:	b2 2a ff 00 	xorw	\$0xff:m,r2
+  26:	b1 2a ff 0f 	xorw	\$0xfff:m,r1
+  2a:	b2 2a ff ff 	xorw	\$0xffff:m,r2
+  2e:	b1 2a 14 00 	xorw	\$0x14:m,r1
+  32:	a2 2a       	xorw	\$0xa:s,r2
+  34:	12 2b       	xorw	r1,r2
+  36:	23 2b       	xorw	r2,r3
+  38:	34 2b       	xorw	r3,r4
+  3a:	56 2b       	xorw	r5,r6
+  3c:	67 2b       	xorw	r6,r7
+  3e:	78 2b       	xorw	r7,r8
+  40:	61 00 00 00 	xord	\$0xf:l,\(r2,r1\)
+  44:	0f 00 
+  46:	61 00 00 00 	xord	\$0xff:l,\(r2,r1\)
+  4a:	ff 00 
+  4c:	61 00 00 00 	xord	\$0xfff:l,\(r2,r1\)
+  50:	ff 0f 
+  52:	61 00 00 00 	xord	\$0xffff:l,\(r2,r1\)
+  56:	ff ff 
+  58:	61 00 0f 00 	xord	\$0xfffff:l,\(r2,r1\)
+  5c:	ff ff 
+  5e:	61 00 ff 0f 	xord	\$0xfffffff:l,\(r2,r1\)
+  62:	ff ff 
+  64:	61 00 ff ff 	xord	\$0xffffffff:l,\(r2,r1\)
+  68:	ff ff 
+  6a:	14 00 31 a0 	xord	\(r4,r3\),\(r2,r1\)
+  6e:	14 00 31 a0 	xord	\(r4,r3\),\(r2,r1\)
diff --git a/gas/testsuite/gas/cr16/xor_test.s b/gas/testsuite/gas/cr16/xor_test.s
new file mode 100644
index 000000000000..b99d103c3b34
--- /dev/null
+++ b/gas/testsuite/gas/cr16/xor_test.s
@@ -0,0 +1,57 @@
+        .text
+        .global main
+main:
+        ###########
+	# XORB imm4/imm16, reg
+        ###########
+	xorb    $0xf,r1
+	xorb    $0xff,r2
+	xorb    $0xfff,r1
+	xorb    $0xffff,r2
+	xorb    $20,r1
+	xorb    $10,r2
+        ###########
+	# XORB reg, reg
+        ###########
+	xorb    r1,r2
+	xorb    r2,r3
+	xorb    r3,r4
+	xorb    r5,r6
+	xorb    r6,r7
+	xorb    r7,r8
+        ###########
+	# XORW imm4/imm16, reg
+        ###########
+	xorw    $0xf,r1
+	xorw    $0xff,r2
+	xorw    $0xfff,r1
+	xorw    $0xffff,r2
+	xorw    $20,r1
+	xorw    $10,r2
+        ###########
+	# XORW reg, reg
+        ###########
+	xorw    r1,r2
+	xorw    r2,r3
+	xorw    r3,r4
+	xorw    r5,r6
+	xorw    r6,r7
+	xorw    r7,r8
+        ###########
+	# XORD imm32, regp
+        ###########
+	xord    $0xf,(r2,r1)
+	xord    $0xff,(r2,r1)
+	xord    $0xfff,(r2,r1)
+	xord    $0xffff,(r2,r1)
+	xord    $0xfffff,(r2,r1)
+	xord    $0xfffffff,(r2,r1)
+	xord    $0xffffffff,(r2,r1)
+        ###########
+	# XORD regp, regp
+        ###########
+	xord    (r4,r3),(r2,r1)
+	xord    (r4,r3),(r2,r1)
+	#xord    $10,(sp)
+	#xord    $14,(sp)
+	#xord    $8,(sp)
diff --git a/gas/testsuite/gas/crx/allinsn.exp b/gas/testsuite/gas/crx/allinsn.exp
index f3f8ae80a58e..2a52f701b5c1 100644
--- a/gas/testsuite/gas/crx/allinsn.exp
+++ b/gas/testsuite/gas/crx/allinsn.exp
@@ -2,19 +2,6 @@
 # Driver for CRX assembler testsuite
 #
 
-proc run_list_test { name opts } {
-  global srcdir subdir
-  set testname "CRX $name"
-  set file $srcdir/$subdir/$name
-  gas_run ${name}.s $opts ">&dump.out"
-  if {[regexp_diff "dump.out" "${file}.l"] } {
-    fail $testname
-    verbose "output is [file_contents "dump.out"]" 2
-    return
-  }
-  pass $testname
-}
-
 if ![istarget crx-*-*] {
     return
 }
diff --git a/gas/testsuite/gas/d10v/address-002.l b/gas/testsuite/gas/d10v/address-002.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-002.l
+++ b/gas/testsuite/gas/d10v/address-002.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-003.l b/gas/testsuite/gas/d10v/address-003.l
index 2f8c4f596b8e..36068de50a8f 100644
--- a/gas/testsuite/gas/d10v/address-003.l
+++ b/gas/testsuite/gas/d10v/address-003.l
@@ -1,3 +1,4 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
+
diff --git a/gas/testsuite/gas/d10v/address-004.l b/gas/testsuite/gas/d10v/address-004.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-004.l
+++ b/gas/testsuite/gas/d10v/address-004.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-005.l b/gas/testsuite/gas/d10v/address-005.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-005.l
+++ b/gas/testsuite/gas/d10v/address-005.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-006.l b/gas/testsuite/gas/d10v/address-006.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-006.l
+++ b/gas/testsuite/gas/d10v/address-006.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-007.l b/gas/testsuite/gas/d10v/address-007.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-007.l
+++ b/gas/testsuite/gas/d10v/address-007.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-008.l b/gas/testsuite/gas/d10v/address-008.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-008.l
+++ b/gas/testsuite/gas/d10v/address-008.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-009.l b/gas/testsuite/gas/d10v/address-009.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-009.l
+++ b/gas/testsuite/gas/d10v/address-009.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-010.l b/gas/testsuite/gas/d10v/address-010.l
index 2f8c4f596b8e..2847fa9b9ee5 100644
--- a/gas/testsuite/gas/d10v/address-010.l
+++ b/gas/testsuite/gas/d10v/address-010.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld r0
diff --git a/gas/testsuite/gas/d10v/address-011.l b/gas/testsuite/gas/d10v/address-011.l
index 2f8c4f596b8e..688385e4d196 100644
--- a/gas/testsuite/gas/d10v/address-011.l
+++ b/gas/testsuite/gas/d10v/address-011.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld2w r0
diff --git a/gas/testsuite/gas/d10v/address-012.l b/gas/testsuite/gas/d10v/address-012.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-012.l
+++ b/gas/testsuite/gas/d10v/address-012.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-013.l b/gas/testsuite/gas/d10v/address-013.l
index 2f8c4f596b8e..edf420d15df6 100644
--- a/gas/testsuite/gas/d10v/address-013.l
+++ b/gas/testsuite/gas/d10v/address-013.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st r0
diff --git a/gas/testsuite/gas/d10v/address-014.l b/gas/testsuite/gas/d10v/address-014.l
index 2f8c4f596b8e..49f87bbc3ec2 100644
--- a/gas/testsuite/gas/d10v/address-014.l
+++ b/gas/testsuite/gas/d10v/address-014.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st2w r0
diff --git a/gas/testsuite/gas/d10v/address-015.l b/gas/testsuite/gas/d10v/address-015.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-015.l
+++ b/gas/testsuite/gas/d10v/address-015.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-016.l b/gas/testsuite/gas/d10v/address-016.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-016.l
+++ b/gas/testsuite/gas/d10v/address-016.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-017.l b/gas/testsuite/gas/d10v/address-017.l
index 2f8c4f596b8e..2847fa9b9ee5 100644
--- a/gas/testsuite/gas/d10v/address-017.l
+++ b/gas/testsuite/gas/d10v/address-017.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld r0
diff --git a/gas/testsuite/gas/d10v/address-018.l b/gas/testsuite/gas/d10v/address-018.l
index 2f8c4f596b8e..688385e4d196 100644
--- a/gas/testsuite/gas/d10v/address-018.l
+++ b/gas/testsuite/gas/d10v/address-018.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld2w r0
diff --git a/gas/testsuite/gas/d10v/address-019.l b/gas/testsuite/gas/d10v/address-019.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-019.l
+++ b/gas/testsuite/gas/d10v/address-019.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-020.l b/gas/testsuite/gas/d10v/address-020.l
index 2f8c4f596b8e..edf420d15df6 100644
--- a/gas/testsuite/gas/d10v/address-020.l
+++ b/gas/testsuite/gas/d10v/address-020.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st r0
diff --git a/gas/testsuite/gas/d10v/address-021.l b/gas/testsuite/gas/d10v/address-021.l
index 2f8c4f596b8e..49f87bbc3ec2 100644
--- a/gas/testsuite/gas/d10v/address-021.l
+++ b/gas/testsuite/gas/d10v/address-021.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st2w r0
diff --git a/gas/testsuite/gas/d10v/address-022.l b/gas/testsuite/gas/d10v/address-022.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-022.l
+++ b/gas/testsuite/gas/d10v/address-022.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-023.l b/gas/testsuite/gas/d10v/address-023.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-023.l
+++ b/gas/testsuite/gas/d10v/address-023.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-024.l b/gas/testsuite/gas/d10v/address-024.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-024.l
+++ b/gas/testsuite/gas/d10v/address-024.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-025.l b/gas/testsuite/gas/d10v/address-025.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-025.l
+++ b/gas/testsuite/gas/d10v/address-025.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-026.l b/gas/testsuite/gas/d10v/address-026.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-026.l
+++ b/gas/testsuite/gas/d10v/address-026.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-027.l b/gas/testsuite/gas/d10v/address-027.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-027.l
+++ b/gas/testsuite/gas/d10v/address-027.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-030.l b/gas/testsuite/gas/d10v/address-030.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-030.l
+++ b/gas/testsuite/gas/d10v/address-030.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-031.l b/gas/testsuite/gas/d10v/address-031.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-031.l
+++ b/gas/testsuite/gas/d10v/address-031.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-032.l b/gas/testsuite/gas/d10v/address-032.l
index 2f8c4f596b8e..2847fa9b9ee5 100644
--- a/gas/testsuite/gas/d10v/address-032.l
+++ b/gas/testsuite/gas/d10v/address-032.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld r0
diff --git a/gas/testsuite/gas/d10v/address-033.l b/gas/testsuite/gas/d10v/address-033.l
index 2f8c4f596b8e..688385e4d196 100644
--- a/gas/testsuite/gas/d10v/address-033.l
+++ b/gas/testsuite/gas/d10v/address-033.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld2w r0
diff --git a/gas/testsuite/gas/d10v/address-034.l b/gas/testsuite/gas/d10v/address-034.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-034.l
+++ b/gas/testsuite/gas/d10v/address-034.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/address-035.l b/gas/testsuite/gas/d10v/address-035.l
index 2f8c4f596b8e..edf420d15df6 100644
--- a/gas/testsuite/gas/d10v/address-035.l
+++ b/gas/testsuite/gas/d10v/address-035.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st r0
diff --git a/gas/testsuite/gas/d10v/address-036.l b/gas/testsuite/gas/d10v/address-036.l
index 2f8c4f596b8e..49f87bbc3ec2 100644
--- a/gas/testsuite/gas/d10v/address-036.l
+++ b/gas/testsuite/gas/d10v/address-036.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: st2w r0
diff --git a/gas/testsuite/gas/d10v/address-037.l b/gas/testsuite/gas/d10v/address-037.l
index 2f8c4f596b8e..1ad93db858b5 100644
--- a/gas/testsuite/gas/d10v/address-037.l
+++ b/gas/testsuite/gas/d10v/address-037.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldb r0
diff --git a/gas/testsuite/gas/d10v/address-038.l b/gas/testsuite/gas/d10v/address-038.l
index 2f8c4f596b8e..72cff1d71ff1 100644
--- a/gas/testsuite/gas/d10v/address-038.l
+++ b/gas/testsuite/gas/d10v/address-038.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ldub r0
diff --git a/gas/testsuite/gas/d10v/address-039.l b/gas/testsuite/gas/d10v/address-039.l
index 2f8c4f596b8e..2847fa9b9ee5 100644
--- a/gas/testsuite/gas/d10v/address-039.l
+++ b/gas/testsuite/gas/d10v/address-039.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld r0
diff --git a/gas/testsuite/gas/d10v/address-040.l b/gas/testsuite/gas/d10v/address-040.l
index 2f8c4f596b8e..688385e4d196 100644
--- a/gas/testsuite/gas/d10v/address-040.l
+++ b/gas/testsuite/gas/d10v/address-040.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: ld2w r0
diff --git a/gas/testsuite/gas/d10v/address-041.l b/gas/testsuite/gas/d10v/address-041.l
index 2f8c4f596b8e..a41162138632 100644
--- a/gas/testsuite/gas/d10v/address-041.l
+++ b/gas/testsuite/gas/d10v/address-041.l
@@ -1,3 +1,3 @@
 .*: Assembler messages:
 .*:6: Error: bad opcode or operands
-.*:6: Fatal error: can't find opcode 
+.*:6: Error: could not assemble: stb r0
diff --git a/gas/testsuite/gas/d10v/d10v.exp b/gas/testsuite/gas/d10v/d10v.exp
index 6169ecf1aa63..0b152b016a15 100644
--- a/gas/testsuite/gas/d10v/d10v.exp
+++ b/gas/testsuite/gas/d10v/d10v.exp
@@ -1,19 +1,6 @@
 #
 # Driver for D10V assembler testsuite
 #
-proc run_list_test { name opts } {
-  global srcdir subdir
-  set testname "D10V $name"
-  set file $srcdir/$subdir/$name
-  gas_run ${name}.s $opts ">&dump.out"
-  if {[regexp_diff "dump.out" "${file}.l"] } {
-    fail $testname
-    verbose "output is [file_contents "dump.out"]" 2
-    return
-  }
-  pass $testname
-}
-
 if {[istarget d10v-*-*]} {
     run_dump_test "inst"
     run_dump_test "address-001"
diff --git a/gas/testsuite/gas/d30v/d30.exp b/gas/testsuite/gas/d30v/d30.exp
index 275b0e06df1d..d06f6066c636 100644
--- a/gas/testsuite/gas/d30v/d30.exp
+++ b/gas/testsuite/gas/d30v/d30.exp
@@ -2,19 +2,6 @@
 # D30V assembler tests
 #
 
-proc run_list_test { name opts } {
-  global srcdir subdir
-  set testname "D30V $name"
-  set file $srcdir/$subdir/$name
-  gas_run ${name}.s $opts ">&dump.out"
-  if {[regexp_diff "dump.out" "${file}.l"] } {
-    fail $testname
-    verbose "output is [file_contents "dump.out"]" 2
-    return
-  }
-  pass $testname
-}
-
 if {[istarget d30v-*-*]} {
   run_dump_test "inst"
   run_dump_test "align"
diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp
index 43265d0d2fae..227b77ef472e 100644
--- a/gas/testsuite/gas/elf/elf.exp
+++ b/gas/testsuite/gas/elf/elf.exp
@@ -2,7 +2,7 @@
 # elf tests
 #
 
-proc run_list_test { name suffix opts readelf_opts readelf_pipe } {
+proc run_elf_list_test { name suffix opts readelf_opts readelf_pipe } {
     global READELF
     global srcdir subdir
     set testname "elf $name list"
@@ -50,11 +50,21 @@ if { ([istarget "*-*-*elf*"]
     if {[istarget m32r*-*-*]} then {
 	set target_machine -m32r
     }
+    if {[istarget "score-*-*"]} then {
+	set target_machine -score
+    }
+    if {[istarget "xtensa-*-*"]} then {
+	set target_machine -xtensa
+    }
     if { ([istarget "*arm*-*-*"]
-	  || [istarget "xscale*-*-*"])
-	&& ([istarget "*-*-*eabi"]
-	    || [istarget "*-*-symbianelf"])} then {
-	set target_machine -armeabi
+	  || [istarget "xscale*-*-*"]) } {
+	
+	if { ([istarget "*-*-*eabi"]
+	      || [istarget "*-*-symbianelf"])} then {
+	    set target_machine -armeabi
+	} else {
+	    set target_machine -armelf
+	}
     }
     run_dump_test "ehopt0"
     run_dump_test "group0a" 
@@ -68,16 +78,22 @@ if { ([istarget "*-*-*elf*"]
 	{ mips*-*-* } { }
 	{ *c54x*-*-* } { }
 	default {
+	    # The next test can fail if the target does not convert fixups
+	    # against ordinary symbols into relocations against section symbols.
+	    # This is usually revealed by the error message:
+	    #  symbol `sym' required but not present
+	    setup_xfail "h8300-*-*" "mn10300-*-*"
 	    run_dump_test redef
+	    run_dump_test equ-reloc
 	}
     }
     run_dump_test "section0" 
     run_dump_test "section1" 
-    run_list_test "section2" "$target_machine" "-al" "-s" ""
+    run_elf_list_test "section2" "$target_machine" "-al" "-s" ""
     run_dump_test "section3" 
     run_dump_test "section4"
-    run_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\""
+    run_elf_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\""
     run_dump_test "struct" 
     run_dump_test "symver" 
-    run_list_test "type" "" "" "-s" "| grep \"1 \\\[FONT\\\]\""
+    run_elf_list_test "type" "" "" "-s" "| grep \"1 \\\[FONT\\\]\""
 }
diff --git a/gas/testsuite/gas/elf/equ-reloc.d b/gas/testsuite/gas/elf/equ-reloc.d
new file mode 100644
index 000000000000..e4e7d47f47a9
--- /dev/null
+++ b/gas/testsuite/gas/elf/equ-reloc.d
@@ -0,0 +1,13 @@
+#objdump: -rsj .data
+#name: elf equate relocs
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[.*\]:
+OFFSET *TYPE *VALUE 
+0*0 [^ ]+ +(\.bss(\+0x0*4)?|y1)
+0*4 [^ ]+ +(\.bss(\+0x0*8)?|y2)
+#...
+Contents of section .data:
+ 0000 0[04]00000[04] 0[08]00000[08].*
+#pass
diff --git a/gas/testsuite/gas/elf/equ-reloc.s b/gas/testsuite/gas/elf/equ-reloc.s
new file mode 100644
index 000000000000..efdd0e1b8ab5
--- /dev/null
+++ b/gas/testsuite/gas/elf/equ-reloc.s
@@ -0,0 +1,16 @@
+	.data
+	.long x1, x2
+
+	.global x1, x2, z2
+
+	.set x1, y1
+	.set x2, y2
+	.set x2, z2
+
+	.section .bss, "aw", %nobits
+x1:
+	.zero	4
+y1:
+	.zero	4
+y2:
+	.zero	4
diff --git a/gas/testsuite/gas/elf/section2.e-armeabi b/gas/testsuite/gas/elf/section2.e-armeabi
index 84463b1f8b2b..44ecffc37768 100644
--- a/gas/testsuite/gas/elf/section2.e-armeabi
+++ b/gas/testsuite/gas/elf/section2.e-armeabi
@@ -1,9 +1,10 @@
 
-Symbol table '.symtab' contains 6 entries:
+Symbol table '.symtab' contains 7 entries:
    Num:    Value[ 	]* Size Type    Bind   Vis      Ndx Name
      0: 0+0     0 NOTYPE  LOCAL  DEFAULT  UND 
      1: 0+0     0 SECTION LOCAL  DEFAULT    1 
      2: 0+0     0 SECTION LOCAL  DEFAULT    2 
      3: 0+0     0 SECTION LOCAL  DEFAULT    3 
      4: 0+0     0 SECTION LOCAL  DEFAULT    4 
-     5: 0+0     0 SECTION LOCAL  DEFAULT    5 
+     5: 0+0     0 NOTYPE  LOCAL  DEFAULT    4 \$d
+     6: 0+0     0 SECTION LOCAL  DEFAULT    5 
diff --git a/gas/testsuite/gas/elf/section2.e-armelf b/gas/testsuite/gas/elf/section2.e-armelf
new file mode 100644
index 000000000000..8d2e4ff6a758
--- /dev/null
+++ b/gas/testsuite/gas/elf/section2.e-armelf
@@ -0,0 +1,9 @@
+
+Symbol table '.symtab' contains 6 entries:
+   Num:    Value[ 	]* Size Type    Bind   Vis      Ndx Name
+     0: 0+0     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+0     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+0     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+0     0 SECTION LOCAL  DEFAULT    3 
+     4: 0+0     0 SECTION LOCAL  DEFAULT    4 
+     5: 0+0     0 NOTYPE  LOCAL  DEFAULT    4 \$d
diff --git a/gas/testsuite/gas/elf/section2.e-score b/gas/testsuite/gas/elf/section2.e-score
new file mode 100644
index 000000000000..6f30cbaa16e4
--- /dev/null
+++ b/gas/testsuite/gas/elf/section2.e-score
@@ -0,0 +1,9 @@
+
+Symbol table '.symtab' contains 6 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00000000     0 SECTION LOCAL  DEFAULT    1 
+     2: 00000000     0 SECTION LOCAL  DEFAULT    2 
+     3: 00000000     0 SECTION LOCAL  DEFAULT    3 
+     4: 00000000     0 SECTION LOCAL  DEFAULT    5 
+     5: 00000000     0 SECTION LOCAL  DEFAULT    4 
diff --git a/gas/testsuite/gas/elf/section2.e-xtensa b/gas/testsuite/gas/elf/section2.e-xtensa
new file mode 100644
index 000000000000..84463b1f8b2b
--- /dev/null
+++ b/gas/testsuite/gas/elf/section2.e-xtensa
@@ -0,0 +1,9 @@
+
+Symbol table '.symtab' contains 6 entries:
+   Num:    Value[ 	]* Size Type    Bind   Vis      Ndx Name
+     0: 0+0     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+0     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+0     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+0     0 SECTION LOCAL  DEFAULT    3 
+     4: 0+0     0 SECTION LOCAL  DEFAULT    4 
+     5: 0+0     0 SECTION LOCAL  DEFAULT    5 
diff --git a/gas/testsuite/gas/frv/allinsn.exp b/gas/testsuite/gas/frv/allinsn.exp
index ed29d20893b3..b6950aeb614c 100644
--- a/gas/testsuite/gas/frv/allinsn.exp
+++ b/gas/testsuite/gas/frv/allinsn.exp
@@ -1,31 +1,19 @@
 # FRV assembler testsuite.
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "$name error test ($opts)"
-    gas_run $name.s $opts >&dump.out
-    if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} {
-	fail $testname
-	verbose "output is [file_contents dump.out]" 2
-	return
-    }
-    pass $testname
-}
-
 if [istarget frv*-*-*] {
     run_dump_test "allinsn"
 
     run_dump_test "fdpic"
     run_dump_test "reloc1"
     run_dump_test "fr405-insn"
-    run_list_test "fr405-insn" "-mcpu=fr400"
-    run_list_test "fr405-insn" "-mcpu=fr500"
+    run_list_test "fr405-insn" "-mcpu=fr400" "fr405-insn -mcpu=fr400"
+    run_list_test "fr405-insn" "-mcpu=fr500" "fr405-insn -mcpu=fr500"
 
     run_dump_test "fr450-spr"
     run_dump_test "fr450-insn"
-    run_list_test "fr450-insn" "-mcpu=fr405"
-    run_list_test "fr450-insn" "-mcpu=fr400"
-    run_list_test "fr450-insn" "-mcpu=fr500"
+    run_list_test "fr450-insn" "-mcpu=fr405" "fr450-insn -mcpu=fr405"
+    run_list_test "fr450-insn" "-mcpu=fr400" "fr450-insn -mcpu=fr400"
+    run_list_test "fr450-insn" "-mcpu=fr500" "fr450-insn -mcpu=fr500"
     run_list_test "fr450-media-issue" "-mcpu=fr450"
 
     run_dump_test "fr550-pack1"
diff --git a/gas/testsuite/gas/i386/addr16.d b/gas/testsuite/gas/i386/addr16.d
new file mode 100644
index 000000000000..910d72570fcf
--- /dev/null
+++ b/gas/testsuite/gas/i386/addr16.d
@@ -0,0 +1,15 @@
+#objdump: -drw
+#name: i386 16-bit addressing in 32-bit mode.
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+67 a0 98 08 [	 ]+addr16[	 ]+mov[ 	]+0x898,%al
+[	 ]*4:[	 ]+67 66 a1 98 08 [	 ]+addr16[	 ]+mov[ 	]+0x898,%ax
+[	 ]*9:[	 ]+67 a1 98 08 [	 ]+addr16[	 ]+mov[ 	]+0x898,%eax
+[	 ]*d:[	 ]+67 a2 98 08 [	 ]+addr16[	 ]+mov[ 	]+%al,0x898
+[	 ]*11:[	 ]+67 66 a3 98 08 [	 ]+addr16[	 ]+mov[ 	]+%ax,0x898
+[	 ]*16:[	 ]+67 a3 98 08[	 ]+addr16[	 ]+mov[ 	]+%eax,0x898
+#pass
diff --git a/gas/testsuite/gas/i386/addr16.s b/gas/testsuite/gas/i386/addr16.s
new file mode 100644
index 000000000000..b1510e798510
--- /dev/null
+++ b/gas/testsuite/gas/i386/addr16.s
@@ -0,0 +1,7 @@
+	.text
+	addr16 mov	0x0898,%al
+	addr16 mov	0x0898,%ax
+	addr16 mov	0x0898,%eax
+	addr16 mov	%al,0x0898
+	addr16 mov	%ax,0x0898
+	addr16 mov	%eax,0x0898
diff --git a/gas/testsuite/gas/i386/addr32.d b/gas/testsuite/gas/i386/addr32.d
new file mode 100644
index 000000000000..5866a30c7927
--- /dev/null
+++ b/gas/testsuite/gas/i386/addr32.d
@@ -0,0 +1,15 @@
+#objdump: -drw -mi8086
+#name: i386 32-bit addressing in 16-bit mode.
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+67 a0 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%al
+[	 ]*6:[	 ]+67 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%ax
+[	 ]*c:[	 ]+67 66 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%eax
+[	 ]*13:[	 ]+67 a2 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%al,0x600898
+[	 ]*19:[	 ]+67 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%ax,0x600898
+[	 ]*1f:[	 ]+67 66 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%eax,0x600898
+#pass
diff --git a/gas/testsuite/gas/i386/addr32.s b/gas/testsuite/gas/i386/addr32.s
new file mode 100644
index 000000000000..3dab339dc256
--- /dev/null
+++ b/gas/testsuite/gas/i386/addr32.s
@@ -0,0 +1,8 @@
+	.text
+	.code16
+	addr32 mov	0x600898,%al
+	addr32 mov	0x600898,%ax
+	addr32 mov	0x600898,%eax
+	addr32 mov	%al,0x600898
+	addr32 mov	%ax,0x600898
+	addr32 mov	%eax,0x600898
diff --git a/gas/testsuite/gas/i386/amd.d b/gas/testsuite/gas/i386/amd.d
index 1ff16792f19f..8009260e50a1 100644
--- a/gas/testsuite/gas/i386/amd.d
+++ b/gas/testsuite/gas/i386/amd.d
@@ -17,7 +17,7 @@ Disassembly of section .text:
   27:	0f 0f ae 90 90 00 00 90 [ 	]*pfcmpge 0x9090\(%esi\),%mm5
   2f:	0f 0f 74 75 00 a0 [ 	]*pfcmpgt 0x0\(%ebp,%esi,2\),%mm6
   35:	0f 0f 7c 75 02 a4 [ 	]*pfmax  0x2\(%ebp,%esi,2\),%mm7
-  3b:	0f 0f 84 75 90 90 90 90 94 [ 	]*pfmin  0x90909090\(%ebp,%esi,2\),%mm0
+  3b:	0f 0f 84 75 90 90 90 90 94 [ 	]*pfmin  -0x6f6f6f70\(%ebp,%esi,2\),%mm0
   44:	0f 0f 0d 04 00 00 00 b4 [ 	]*pfmul  0x4,%mm1
   4c:	2e 0f 0f 54 c3 07 96 [ 	]*pfrcp  %cs:0x7\(%ebx,%eax,8\),%mm2
   53:	0f 0f d8 a6 [ 	]*pfrcpit1 %mm0,%mm3
@@ -27,7 +27,7 @@ Disassembly of section .text:
   63:	0f 0f fc 9a [ 	]*pfsub  %mm4,%mm7
   67:	0f 0f c5 aa [ 	]*pfsubr %mm5,%mm0
   6b:	0f 0f ce 0d [ 	]*pi2fd  %mm6,%mm1
-  6f:	0f 0f d7 b7 [ 	]*pfmulhrw %mm7,%mm2
+  6f:	0f 0f d7 b7 [ 	]*pmulhrw %mm7,%mm2
   73:	2e 0f [ 	]*\(bad\)  
   75:	0f 54 c3 [ 	]*andps  %xmm3,%xmm0
   78:	07 [ 	]*pop    %es
diff --git a/gas/testsuite/gas/i386/amdfam10.d b/gas/testsuite/gas/i386/amdfam10.d
new file mode 100644
index 000000000000..ba63e49bfd1b
--- /dev/null
+++ b/gas/testsuite/gas/i386/amdfam10.d
@@ -0,0 +1,23 @@
+#objdump: -dw
+#name: i386 amdfam10
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	f3 0f bd 19[ 	]+lzcnt  \(%ecx\),%ebx
+   4:	66 f3 0f bd 19[ 	 ]+lzcnt  \(%ecx\),%bx
+   9:	f3 0f bd d9[ 	 ]+lzcnt  %ecx,%ebx
+   d:	66 f3 0f bd d9[ 	 ]+lzcnt  %cx,%bx
+  12:	f3 0f b8 19[ 	]+popcnt \(%ecx\),%ebx
+  16:	66 f3 0f b8 19[ 	]+popcnt \(%ecx\),%bx
+  1b:	f3 0f b8 d9[ 	]+popcnt %ecx,%ebx
+  1f:	66 f3 0f b8 d9[ 	]+popcnt %cx,%bx
+  24:	66 0f 79 ca[ 	]+extrq  %xmm2,%xmm1
+  28:	66 0f 78 c1 02 04[ 	]*extrq  \$0x4,\$0x2,%xmm1
+  2e:	f2 0f 79 ca[ 	]+insertq %xmm2,%xmm1
+  32:	f2 0f 78 ca 02 04[ 	]*insertq \$0x4,\$0x2,%xmm2,%xmm1
+  38:	f2 0f 2b 09[ 	]+movntsd %xmm1,\(%ecx\)
+  3c:	f3 0f 2b 09[ 	]+movntss %xmm1,\(%ecx\)
+
diff --git a/gas/testsuite/gas/i386/amdfam10.s b/gas/testsuite/gas/i386/amdfam10.s
new file mode 100644
index 000000000000..bef51fee2f38
--- /dev/null
+++ b/gas/testsuite/gas/i386/amdfam10.s
@@ -0,0 +1,21 @@
+#AMDFAM10 New Instructions
+
+	.text
+foo:
+	lzcnt	(%ecx),%ebx
+	lzcnt	(%ecx),%bx
+	lzcnt	%ecx,%ebx
+	lzcnt	%cx,%bx
+	popcnt	(%ecx),%ebx
+	popcnt	(%ecx),%bx
+	popcnt	%ecx,%ebx
+	popcnt	%cx,%bx
+	extrq	%xmm2,%xmm1
+	extrq	$4,$2,%xmm1
+	insertq	%xmm2,%xmm1
+	insertq	$4,$2,%xmm2,%xmm1
+	movntsd	%xmm1,(%ecx)
+	movntss %xmm1,(%ecx)
+
+	# Force a good alignment.
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/crc32-intel.d b/gas/testsuite/gas/i386/crc32-intel.d
new file mode 100644
index 000000000000..705f6b809838
--- /dev/null
+++ b/gas/testsuite/gas/i386/crc32-intel.d
@@ -0,0 +1,25 @@
+#objdump: -dwMintel
+#name: i386 crc32 (Intel disassembly)
+#source: crc32.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32  eax,BYTE PTR \[esi\]
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32  eax,WORD PTR \[esi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32  eax,DWORD PTR \[esi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32  eax,BYTE PTR \[esi\]
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32  eax,WORD PTR \[esi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32  eax,DWORD PTR \[esi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+#pass
diff --git a/gas/testsuite/gas/i386/crc32.d b/gas/testsuite/gas/i386/crc32.d
new file mode 100644
index 000000000000..a398a75f9a69
--- /dev/null
+++ b/gas/testsuite/gas/i386/crc32.d
@@ -0,0 +1,24 @@
+#objdump: -dw
+#name: i386 crc32
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32b \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32w \(%esi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32l \(%esi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32b \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32w \(%esi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32l \(%esi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+#pass
diff --git a/gas/testsuite/gas/i386/crc32.s b/gas/testsuite/gas/i386/crc32.s
new file mode 100644
index 000000000000..edcfe1c4c0c8
--- /dev/null
+++ b/gas/testsuite/gas/i386/crc32.s
@@ -0,0 +1,24 @@
+# Check crc32 in SSE4.2
+
+	.text
+foo:
+
+crc32b (%esi), %eax
+crc32w (%esi), %eax
+crc32l (%esi), %eax
+crc32  %al, %eax
+crc32b  %al, %eax
+crc32  %ax, %eax
+crc32w  %ax, %eax
+crc32  %eax, %eax
+crc32l  %eax, %eax
+
+.intel_syntax noprefix
+crc32  eax,byte ptr [esi]
+crc32  eax, word ptr [esi]
+crc32  eax,dword ptr [esi]
+crc32  eax,al
+crc32  eax, ax
+crc32  eax,eax
+
+.p2align 4,0
diff --git a/gas/testsuite/gas/i386/fp.d b/gas/testsuite/gas/i386/fp.d
new file mode 100644
index 000000000000..21838e262bc2
--- /dev/null
+++ b/gas/testsuite/gas/i386/fp.d
@@ -0,0 +1,8 @@
+#objdump: -s -j .data
+#name: i386 fp
+
+.*:     file format .*
+
+Contents of section .data:
+ 0000 00881bcd 4b789ad4 004071a3 79094f93  ....Kx...@q.y.O.
+ 0010 0a40789a 5440789a 54400000 00000000  .@x.T@x.T@......
diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s
new file mode 100644
index 000000000000..4187d4e55c31
--- /dev/null
+++ b/gas/testsuite/gas/i386/fp.s
@@ -0,0 +1,13 @@
+	.data
+# .tfloat is 80-bit floating point format.
+	.tfloat 3.32192809488736218171e0
+#	.byte 0x0, 0x88, 0x1b, 0xcd, 0x4b, 0x78, 0x9a, 0xd4, 0x0, 0x40
+# .double is 64-bit floating point format.
+	.double 3.32192809488736218171e0
+#	.byte 0x71, 0xa3, 0x79, 0x09, 0x4f, 0x93, 0x0a, 0x40
+# The next two are 32-bit floating point format.
+	.float 3.32192809488736218171e0
+#	.byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0
+	.single 3.32192809488736218171e0
+#	.byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0
+	.byte 0, 0, 0, 0, 0, 0
diff --git a/gas/testsuite/gas/i386/gotpc.d b/gas/testsuite/gas/i386/gotpc.d
index 499e831c1b45..ef79cbd78322 100644
--- a/gas/testsuite/gas/i386/gotpc.d
+++ b/gas/testsuite/gas/i386/gotpc.d
@@ -49,4 +49,6 @@ Disassembly of section .text:
   e0:	e0 00 [ 	]*loopne e2 <test\+0xe2>	e0: (R_386_)?GOTPC	_GLOBAL_OFFSET_TABLE_
   e2:	00 00 [ 	]*add    %al,\(%eax\)
   e4:	00 00 [ 	]*add    %al,\(%eax\)	e4: (R_386_)?GOTOFF	_GLOBAL_OFFSET_TABLE_
-	...
+  e6:	00 00 [ 	]*add    %al,\(%eax\)
+  e8:	8b 83 00 00 00 00 [ 	]*mov    0x0\(%ebx\),%eax	ea: (R_386_)?GOTOFF	_GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/gas/testsuite/gas/i386/gotpc.s b/gas/testsuite/gas/i386/gotpc.s
index 5787b8e8f88c..fc771f6cff55 100644
--- a/gas/testsuite/gas/i386/gotpc.s
+++ b/gas/testsuite/gas/i386/gotpc.s
@@ -38,3 +38,4 @@ test:
 	movl _GLOBAL_OFFSET_TABLE_@GOTOFF(%ebx), %ebx
 	.long _GLOBAL_OFFSET_TABLE_+[.-test]
 	.long _GLOBAL_OFFSET_TABLE_@GOTOFF
+	movl _GLOBAL_OFFSET_TABLE_@GOTOFF (%ebx), %eax
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index a12bc91fb210..8f0437c47381 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1,19 +1,6 @@
 #
 # i386 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "i386 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 proc gas_64_check { } {
     global NM
     global NMFLAGS
@@ -46,6 +33,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_list_test "modrm" "-al --listing-lhs-width=2"
     run_dump_test "naked"
     run_dump_test "opcode"
+    run_dump_test "opcode-intel"
+    run_dump_test "opcode-suffix"
     run_dump_test "intel"
     run_dump_test "intel16"
     run_list_test "intelbad" ""
@@ -68,9 +57,29 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "crx"
     run_list_test "cr-err" ""
     run_dump_test "svme"
+    run_dump_test "amdfam10"
     run_dump_test "merom"
     run_dump_test "rep"
     run_dump_test "rep-suffix"
+    run_dump_test "fp"
+    run_dump_test "nops"
+    run_dump_test "nops-1"
+    run_dump_test "nops-1-i386"
+    run_dump_test "nops-1-i686"
+    run_dump_test "nops-1-merom"
+    run_dump_test "nops-2"
+    run_dump_test "nops-2-i386"
+    run_dump_test "nops-2-merom"
+    run_dump_test "nops-3"
+    run_dump_test "addr16"
+    run_dump_test "addr32"
+    run_dump_test "sse4_1"
+    run_dump_test "sse4_2"
+    run_dump_test "crc32"
+    run_dump_test "crc32-intel"
+    run_list_test "inval-crc32" "-al"
+    run_dump_test "simd"
+    run_dump_test "simd-intel"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -121,9 +130,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
 
     run_dump_test "x86_64"
     run_dump_test "x86-64-addr32"
+    run_dump_test "x86-64-addr32-intel"
     run_dump_test "x86-64-opcode"
     run_dump_test "x86-64-pcrel"
     run_dump_test "x86-64-rip"
+    run_dump_test "x86-64-rip-intel"
     run_dump_test "x86-64-stack"
     run_dump_test "x86-64-stack-intel"
     run_dump_test "x86-64-stack-suffix"
@@ -132,6 +143,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_list_test "x86-64-inval-seg" "-al"
     run_dump_test "x86-64-branch"
     run_dump_test "svme64"
+    run_dump_test "x86-64-amdfam10"
     run_dump_test "x86-64-vmx"
     run_dump_test "immed64"
     run_dump_test "x86-64-prescott"
@@ -142,6 +154,26 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-merom"
     run_dump_test "x86-64-rep"
     run_dump_test "x86-64-rep-suffix"
+    run_dump_test "x86-64-cbw"
+    run_dump_test "x86-64-cbw-intel"
+    run_dump_test "x86-64-io"
+    run_dump_test "x86-64-io-intel"
+    run_dump_test "x86-64-io-suffix"
+    run_dump_test "x86-64-gidt"
+    run_dump_test "x86-64-nops"
+    if ![istarget "x86_64-*-mingw*"] then {
+	run_dump_test "x86-64-nops-1"
+    }
+    run_dump_test "x86-64-nops-1-k8"
+    run_dump_test "x86-64-nops-1-nocona"
+    run_dump_test "x86-64-nops-1-merom"
+    run_dump_test "x86-64-sse4_1"
+    run_dump_test "x86-64-sse4_2"
+    run_dump_test "x86-64-crc32"
+    run_dump_test "x86-64-crc32-intel"
+    run_list_test "x86-64-inval-crc32" "-al"
+    run_dump_test "x86-64-simd"
+    run_dump_test "x86-64-simd-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/immed32.d b/gas/testsuite/gas/i386/immed32.d
index 3d308a833b4a..d22538fb4fb5 100644
--- a/gas/testsuite/gas/i386/immed32.d
+++ b/gas/testsuite/gas/i386/immed32.d
@@ -9,9 +9,9 @@ Disassembly of section \.text:
 [ 	]*[0-9a-fA-F]+:[ 	]+ff 50 04[ 	]+calll? +\*0x4\(%eax\)
 [ 	]*[0-9a-fA-F]+:[ 	]+ff 90 08 00 00 00[ 	]+calll? +\*0x8\(%eax\)
 [ 	]*[0-9a-fA-F]+:[ 	]+ff 90 00 00 00 00[ 	]+calll? +\*0x0\(%eax\)
-[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 57 04[ 	]+(addr16 )?calll? +\*4\(%bx\)
-[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 08 00[ 	]+(addr16 )?calll? +\*8\(%bx\)
-[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 00 00[ 	]+(addr16 )?calll? +\*0\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 57 04[ 	]+(addr16 )?calll? +\*0x4\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 08 00[ 	]+(addr16 )?calll? +\*0x8\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 00 00[ 	]+(addr16 )?calll? +\*0x0\(%bx\)
 [ 	]*[0-9a-fA-F]+:[ 	]+b0 04[ 	]+movb? +\$0x4,%al
 [ 	]*[0-9a-fA-F]+:[ 	]+b0 08[ 	]+movb? +\$0x8,%al
 [ 	]*[0-9a-fA-F]+:[ 	]+b0 00[ 	]+movb? +\$0x0,%al
diff --git a/gas/testsuite/gas/i386/immed64.d b/gas/testsuite/gas/i386/immed64.d
index c2ab3248b7d6..667680675a58 100644
--- a/gas/testsuite/gas/i386/immed64.d
+++ b/gas/testsuite/gas/i386/immed64.d
@@ -57,3 +57,4 @@ Disassembly of section \.text:
 [ 	]*[0-9a-fA-F]+:[ 	]+e5 04[ 	]+inl? +\$0x4,%eax
 [ 	]*[0-9a-fA-F]+:[ 	]+e5 08[ 	]+inl? +\$0x8,%eax
 [ 	]*[0-9a-fA-F]+:[ 	]+e5 00[ 	]+inl? +\$0x0,%eax
+#pass
diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 02b1a0a197f5..f8a96dfd7327 100644
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -8,62 +8,62 @@
 Disassembly of section .text:
 
 0+000 <foo>:
-   0:	00 90 90 90 90 90 [ 	]*add    %dl,0x90909090\(%eax\)
-   6:	01 90 90 90 90 90 [ 	]*add    %edx,0x90909090\(%eax\)
-   c:	02 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%dl
-  12:	03 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%edx
+   0:	00 90 90 90 90 90 [ 	]*add    %dl,-0x6f6f6f70\(%eax\)
+   6:	01 90 90 90 90 90 [ 	]*add    %edx,-0x6f6f6f70\(%eax\)
+   c:	02 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%dl
+  12:	03 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%edx
   18:	04 90 [ 	]*add    \$0x90,%al
   1a:	05 90 90 90 90 [ 	]*add    \$0x90909090,%eax
   1f:	06 [ 	]*push   %es
   20:	07 [ 	]*pop    %es
-  21:	08 90 90 90 90 90 [ 	]*or     %dl,0x90909090\(%eax\)
-  27:	09 90 90 90 90 90 [ 	]*or     %edx,0x90909090\(%eax\)
-  2d:	0a 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%dl
-  33:	0b 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%edx
+  21:	08 90 90 90 90 90 [ 	]*or     %dl,-0x6f6f6f70\(%eax\)
+  27:	09 90 90 90 90 90 [ 	]*or     %edx,-0x6f6f6f70\(%eax\)
+  2d:	0a 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%dl
+  33:	0b 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%edx
   39:	0c 90 [ 	]*or     \$0x90,%al
   3b:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
   40:	0e [ 	]*push   %cs
-  41:	10 90 90 90 90 90 [ 	]*adc    %dl,0x90909090\(%eax\)
-  47:	11 90 90 90 90 90 [ 	]*adc    %edx,0x90909090\(%eax\)
-  4d:	12 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%dl
-  53:	13 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%edx
+  41:	10 90 90 90 90 90 [ 	]*adc    %dl,-0x6f6f6f70\(%eax\)
+  47:	11 90 90 90 90 90 [ 	]*adc    %edx,-0x6f6f6f70\(%eax\)
+  4d:	12 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%dl
+  53:	13 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%edx
   59:	14 90 [ 	]*adc    \$0x90,%al
   5b:	15 90 90 90 90 [ 	]*adc    \$0x90909090,%eax
   60:	16 [ 	]*push   %ss
   61:	17 [ 	]*pop    %ss
-  62:	18 90 90 90 90 90 [ 	]*sbb    %dl,0x90909090\(%eax\)
-  68:	19 90 90 90 90 90 [ 	]*sbb    %edx,0x90909090\(%eax\)
-  6e:	1a 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%dl
-  74:	1b 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%edx
+  62:	18 90 90 90 90 90 [ 	]*sbb    %dl,-0x6f6f6f70\(%eax\)
+  68:	19 90 90 90 90 90 [ 	]*sbb    %edx,-0x6f6f6f70\(%eax\)
+  6e:	1a 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%dl
+  74:	1b 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%edx
   7a:	1c 90 [ 	]*sbb    \$0x90,%al
   7c:	1d 90 90 90 90 [ 	]*sbb    \$0x90909090,%eax
   81:	1e [ 	]*push   %ds
   82:	1f [ 	]*pop    %ds
-  83:	20 90 90 90 90 90 [ 	]*and    %dl,0x90909090\(%eax\)
-  89:	21 90 90 90 90 90 [ 	]*and    %edx,0x90909090\(%eax\)
-  8f:	22 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%dl
-  95:	23 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%edx
+  83:	20 90 90 90 90 90 [ 	]*and    %dl,-0x6f6f6f70\(%eax\)
+  89:	21 90 90 90 90 90 [ 	]*and    %edx,-0x6f6f6f70\(%eax\)
+  8f:	22 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%dl
+  95:	23 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%edx
   9b:	24 90 [ 	]*and    \$0x90,%al
   9d:	25 90 90 90 90 [ 	]*and    \$0x90909090,%eax
   a2:	27 [ 	]*daa    
-  a3:	28 90 90 90 90 90 [ 	]*sub    %dl,0x90909090\(%eax\)
-  a9:	29 90 90 90 90 90 [ 	]*sub    %edx,0x90909090\(%eax\)
-  af:	2a 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%dl
-  b5:	2b 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%edx
+  a3:	28 90 90 90 90 90 [ 	]*sub    %dl,-0x6f6f6f70\(%eax\)
+  a9:	29 90 90 90 90 90 [ 	]*sub    %edx,-0x6f6f6f70\(%eax\)
+  af:	2a 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%dl
+  b5:	2b 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%edx
   bb:	2c 90 [ 	]*sub    \$0x90,%al
   bd:	2d 90 90 90 90 [ 	]*sub    \$0x90909090,%eax
   c2:	2f [ 	]*das    
-  c3:	30 90 90 90 90 90 [ 	]*xor    %dl,0x90909090\(%eax\)
-  c9:	31 90 90 90 90 90 [ 	]*xor    %edx,0x90909090\(%eax\)
-  cf:	32 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%dl
-  d5:	33 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%edx
+  c3:	30 90 90 90 90 90 [ 	]*xor    %dl,-0x6f6f6f70\(%eax\)
+  c9:	31 90 90 90 90 90 [ 	]*xor    %edx,-0x6f6f6f70\(%eax\)
+  cf:	32 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%dl
+  d5:	33 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%edx
   db:	34 90 [ 	]*xor    \$0x90,%al
   dd:	35 90 90 90 90 [ 	]*xor    \$0x90909090,%eax
   e2:	37 [ 	]*aaa    
-  e3:	38 90 90 90 90 90 [ 	]*cmp    %dl,0x90909090\(%eax\)
-  e9:	39 90 90 90 90 90 [ 	]*cmp    %edx,0x90909090\(%eax\)
-  ef:	3a 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%dl
-  f5:	3b 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%edx
+  e3:	38 90 90 90 90 90 [ 	]*cmp    %dl,-0x6f6f6f70\(%eax\)
+  e9:	39 90 90 90 90 90 [ 	]*cmp    %edx,-0x6f6f6f70\(%eax\)
+  ef:	3a 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%dl
+  f5:	3b 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%edx
   fb:	3c 90 [ 	]*cmp    \$0x90,%al
   fd:	3d 90 90 90 90 [ 	]*cmp    \$0x90909090,%eax
  102:	3f [ 	]*aas    
@@ -101,12 +101,12 @@ Disassembly of section .text:
  122:	5f [ 	]*pop    %edi
  123:	60 [ 	]*pusha  
  124:	61 [ 	]*popa   
- 125:	62 90 90 90 90 90 [ 	]*bound  %edx,0x90909090\(%eax\)
- 12b:	63 90 90 90 90 90 [ 	]*arpl   %dx,0x90909090\(%eax\)
+ 125:	62 90 90 90 90 90 [ 	]*bound  %edx,-0x6f6f6f70\(%eax\)
+ 12b:	63 90 90 90 90 90 [ 	]*arpl   %dx,-0x6f6f6f70\(%eax\)
  131:	68 90 90 90 90 [ 	]*push   \$0x90909090
- 136:	69 90 90 90 90 90 90 90 90 90 [ 	]*imul   \$0x90909090,0x90909090\(%eax\),%edx
+ 136:	69 90 90 90 90 90 90 90 90 90 [ 	]*imul   \$0x90909090,-0x6f6f6f70\(%eax\),%edx
  140:	6a 90 [ 	]*push   \$0xffffff90
- 142:	6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,0x90909090\(%eax\),%edx
+ 142:	6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,-0x6f6f6f70\(%eax\),%edx
  149:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
  14a:	6d [ 	]*insl   \(%dx\),%es:\(%edi\)
  14b:	6e [ 	]*outsb  %ds:\(%esi\),\(%dx\)
@@ -127,21 +127,21 @@ Disassembly of section .text:
  167:	7d 90 [ 	]*jge    (0x)?f9.*
  169:	7e 90 [ 	]*jle    (0x)?fb.*
  16b:	7f 90 [ 	]*jg     (0x)?fd.*
- 16d:	80 90 90 90 90 90 90 [ 	]*adcb   \$0x90,0x90909090\(%eax\)
- 174:	81 90 90 90 90 90 90 90 90 90 [ 	]*adcl   \$0x90909090,0x90909090\(%eax\)
- 17e:	83 90 90 90 90 90 90 [ 	]*adcl   \$0xffffff90,0x90909090\(%eax\)
- 185:	84 90 90 90 90 90 [ 	]*test   %dl,0x90909090\(%eax\)
- 18b:	85 90 90 90 90 90 [ 	]*test   %edx,0x90909090\(%eax\)
- 191:	86 90 90 90 90 90 [ 	]*xchg   %dl,0x90909090\(%eax\)
- 197:	87 90 90 90 90 90 [ 	]*xchg   %edx,0x90909090\(%eax\)
- 19d:	88 90 90 90 90 90 [ 	]*mov    %dl,0x90909090\(%eax\)
- 1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,0x90909090\(%eax\)
- 1a9:	8a 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dl
- 1af:	8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%edx
- 1b5:	8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 1bb:	8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%edx
- 1c1:	8e 90 90 90 90 90 [ 	]*movw   0x90909090\(%eax\),%ss
- 1c7:	8f 80 90 90 90 90 [ 	]*popl   0x90909090\(%eax\)
+ 16d:	80 90 90 90 90 90 90 [ 	]*adcb   \$0x90,-0x6f6f6f70\(%eax\)
+ 174:	81 90 90 90 90 90 90 90 90 90 [ 	]*adcl   \$0x90909090,-0x6f6f6f70\(%eax\)
+ 17e:	83 90 90 90 90 90 90 [ 	]*adcl   \$0xffffff90,-0x6f6f6f70\(%eax\)
+ 185:	84 90 90 90 90 90 [ 	]*test   %dl,-0x6f6f6f70\(%eax\)
+ 18b:	85 90 90 90 90 90 [ 	]*test   %edx,-0x6f6f6f70\(%eax\)
+ 191:	86 90 90 90 90 90 [ 	]*xchg   %dl,-0x6f6f6f70\(%eax\)
+ 197:	87 90 90 90 90 90 [ 	]*xchg   %edx,-0x6f6f6f70\(%eax\)
+ 19d:	88 90 90 90 90 90 [ 	]*mov    %dl,-0x6f6f6f70\(%eax\)
+ 1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,-0x6f6f6f70\(%eax\)
+ 1a9:	8a 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%dl
+ 1af:	8b 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%edx
+ 1b5:	8c 90 90 90 90 90 [ 	]*mov    %ss,-0x6f6f6f70\(%eax\)
+ 1bb:	8d 90 90 90 90 90 [ 	]*lea    -0x6f6f6f70\(%eax\),%edx
+ 1c1:	8e 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%ss
+ 1c7:	8f 80 90 90 90 90 [ 	]*popl   -0x6f6f6f70\(%eax\)
  1cd:	90 [ 	]*nop    
  1ce:	91 [ 	]*xchg   %eax,%ecx
  1cf:	92 [ 	]*xchg   %eax,%edx
@@ -190,14 +190,14 @@ Disassembly of section .text:
  231:	bd 90 90 90 90 [ 	]*mov    \$0x90909090,%ebp
  236:	be 90 90 90 90 [ 	]*mov    \$0x90909090,%esi
  23b:	bf 90 90 90 90 [ 	]*mov    \$0x90909090,%edi
- 240:	c0 90 90 90 90 90 90 [ 	]*rclb   \$0x90,0x90909090\(%eax\)
- 247:	c1 90 90 90 90 90 90 [ 	]*rcll   \$0x90,0x90909090\(%eax\)
+ 240:	c0 90 90 90 90 90 90 [ 	]*rclb   \$0x90,-0x6f6f6f70\(%eax\)
+ 247:	c1 90 90 90 90 90 90 [ 	]*rcll   \$0x90,-0x6f6f6f70\(%eax\)
  24e:	c2 90 90 [ 	]*ret    \$0x9090
  251:	c3 [ 	]*ret    
- 252:	c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%edx
- 258:	c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%edx
- 25e:	c6 80 90 90 90 90 90 [ 	]*movb   \$0x90,0x90909090\(%eax\)
- 265:	c7 80 90 90 90 90 90 90 90 90 [ 	]*movl   \$0x90909090,0x90909090\(%eax\)
+ 252:	c4 90 90 90 90 90 [ 	]*les    -0x6f6f6f70\(%eax\),%edx
+ 258:	c5 90 90 90 90 90 [ 	]*lds    -0x6f6f6f70\(%eax\),%edx
+ 25e:	c6 80 90 90 90 90 90 [ 	]*movb   \$0x90,-0x6f6f6f70\(%eax\)
+ 265:	c7 80 90 90 90 90 90 90 90 90 [ 	]*movl   \$0x90909090,-0x6f6f6f70\(%eax\)
  26f:	c8 90 90 90 [ 	]*enter  \$0x9090,\$0x90
  273:	c9 [ 	]*leave  
  274:	ca 90 90 [ 	]*lret   \$0x9090
@@ -206,21 +206,21 @@ Disassembly of section .text:
  279:	cd 90 [ 	]*int    \$0x90
  27b:	ce [ 	]*into   
  27c:	cf [ 	]*iret   
- 27d:	d0 90 90 90 90 90 [ 	]*rclb   0x90909090\(%eax\)
- 283:	d1 90 90 90 90 90 [ 	]*rcll   0x90909090\(%eax\)
- 289:	d2 90 90 90 90 90 [ 	]*rclb   %cl,0x90909090\(%eax\)
- 28f:	d3 90 90 90 90 90 [ 	]*rcll   %cl,0x90909090\(%eax\)
+ 27d:	d0 90 90 90 90 90 [ 	]*rclb   -0x6f6f6f70\(%eax\)
+ 283:	d1 90 90 90 90 90 [ 	]*rcll   -0x6f6f6f70\(%eax\)
+ 289:	d2 90 90 90 90 90 [ 	]*rclb   %cl,-0x6f6f6f70\(%eax\)
+ 28f:	d3 90 90 90 90 90 [ 	]*rcll   %cl,-0x6f6f6f70\(%eax\)
  295:	d4 90 [ 	]*aam    \$0xffffff90
  297:	d5 90 [ 	]*aad    \$0xffffff90
  299:	d7 [ 	]*xlat   %ds:\(%ebx\)
- 29a:	d8 90 90 90 90 90 [ 	]*fcoms  0x90909090\(%eax\)
- 2a0:	d9 90 90 90 90 90 [ 	]*fsts   0x90909090\(%eax\)
- 2a6:	da 90 90 90 90 90 [ 	]*ficoml 0x90909090\(%eax\)
- 2ac:	db 90 90 90 90 90 [ 	]*fistl  0x90909090\(%eax\)
- 2b2:	dc 90 90 90 90 90 [ 	]*fcoml  0x90909090\(%eax\)
- 2b8:	dd 90 90 90 90 90 [ 	]*fstl   0x90909090\(%eax\)
- 2be:	de 90 90 90 90 90 [ 	]*ficom  0x90909090\(%eax\)
- 2c4:	df 90 90 90 90 90 [ 	]*fist   0x90909090\(%eax\)
+ 29a:	d8 90 90 90 90 90 [ 	]*fcoms  -0x6f6f6f70\(%eax\)
+ 2a0:	d9 90 90 90 90 90 [ 	]*fsts   -0x6f6f6f70\(%eax\)
+ 2a6:	da 90 90 90 90 90 [ 	]*ficoml -0x6f6f6f70\(%eax\)
+ 2ac:	db 90 90 90 90 90 [ 	]*fistl  -0x6f6f6f70\(%eax\)
+ 2b2:	dc 90 90 90 90 90 [ 	]*fcoml  -0x6f6f6f70\(%eax\)
+ 2b8:	dd 90 90 90 90 90 [ 	]*fstl   -0x6f6f6f70\(%eax\)
+ 2be:	de 90 90 90 90 90 [ 	]*ficom  -0x6f6f6f70\(%eax\)
+ 2c4:	df 90 90 90 90 90 [ 	]*fist   -0x6f6f6f70\(%eax\)
  2ca:	e0 90 [ 	]*loopne (0x)?25c.*
  2cc:	e1 90 [ 	]*loope  (0x)?25e.*
  2ce:	e2 90 [ 	]*loop   (0x)?260.*
@@ -239,19 +239,19 @@ Disassembly of section .text:
  2f0:	ef [ 	]*out    %eax,\(%dx\)
  2f1:	f4 [ 	]*hlt    
  2f2:	f5 [ 	]*cmc    
- 2f3:	f6 90 90 90 90 90 [ 	]*notb   0x90909090\(%eax\)
- 2f9:	f7 90 90 90 90 90 [ 	]*notl   0x90909090\(%eax\)
+ 2f3:	f6 90 90 90 90 90 [ 	]*notb   -0x6f6f6f70\(%eax\)
+ 2f9:	f7 90 90 90 90 90 [ 	]*notl   -0x6f6f6f70\(%eax\)
  2ff:	f8 [ 	]*clc    
  300:	f9 [ 	]*stc    
  301:	fa [ 	]*cli    
  302:	fb [ 	]*sti    
  303:	fc [ 	]*cld    
  304:	fd [ 	]*std    
- 305:	ff 90 90 90 90 90 [ 	]*call   \*0x90909090\(%eax\)
- 30b:	0f 00 90 90 90 90 90 [ 	]*lldt   0x90909090\(%eax\)
- 312:	0f 01 90 90 90 90 90 [ 	]*lgdtl  0x90909090\(%eax\)
- 319:	0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%edx
- 320:	0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%edx
+ 305:	ff 90 90 90 90 90 [ 	]*call   \*-0x6f6f6f70\(%eax\)
+ 30b:	0f 00 90 90 90 90 90 [ 	]*lldt   -0x6f6f6f70\(%eax\)
+ 312:	0f 01 90 90 90 90 90 [ 	]*lgdtl  -0x6f6f6f70\(%eax\)
+ 319:	0f 02 90 90 90 90 90 [ 	]*lar    -0x6f6f6f70\(%eax\),%edx
+ 320:	0f 03 90 90 90 90 90 [ 	]*lsl    -0x6f6f6f70\(%eax\),%edx
  327:	0f 06 [ 	]*clts   
  329:	0f 08 [ 	]*invd   
  32b:	0f 09 [ 	]*wbinvd 
@@ -266,45 +266,45 @@ Disassembly of section .text:
  343:	0f 31 [ 	]*rdtsc  
  345:	0f 32 [ 	]*rdmsr  
  347:	0f 33 [ 	]*rdpmc  
- 349:	0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%edx
- 350:	0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%edx
- 357:	0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%edx
- 35e:	0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%edx
- 365:	0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%edx
- 36c:	0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%edx
- 373:	0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%edx
- 37a:	0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%edx
- 381:	0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%edx
- 388:	0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%edx
- 38f:	0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%edx
- 396:	0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%edx
- 39d:	0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%edx
- 3a4:	0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%edx
- 3ab:	0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%edx
- 3b2:	0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%edx
- 3b9:	0f 60 90 90 90 90 90 [ 	]*punpcklbw 0x90909090\(%eax\),%mm2
- 3c0:	0f 61 90 90 90 90 90 [ 	]*punpcklwd 0x90909090\(%eax\),%mm2
- 3c7:	0f 62 90 90 90 90 90 [ 	]*punpckldq 0x90909090\(%eax\),%mm2
- 3ce:	0f 63 90 90 90 90 90 [ 	]*packsswb 0x90909090\(%eax\),%mm2
- 3d5:	0f 64 90 90 90 90 90 [ 	]*pcmpgtb 0x90909090\(%eax\),%mm2
- 3dc:	0f 65 90 90 90 90 90 [ 	]*pcmpgtw 0x90909090\(%eax\),%mm2
- 3e3:	0f 66 90 90 90 90 90 [ 	]*pcmpgtd 0x90909090\(%eax\),%mm2
- 3ea:	0f 67 90 90 90 90 90 [ 	]*packuswb 0x90909090\(%eax\),%mm2
- 3f1:	0f 68 90 90 90 90 90 [ 	]*punpckhbw 0x90909090\(%eax\),%mm2
- 3f8:	0f 69 90 90 90 90 90 [ 	]*punpckhwd 0x90909090\(%eax\),%mm2
- 3ff:	0f 6a 90 90 90 90 90 [ 	]*punpckhdq 0x90909090\(%eax\),%mm2
- 406:	0f 6b 90 90 90 90 90 [ 	]*packssdw 0x90909090\(%eax\),%mm2
- 40d:	0f 6e 90 90 90 90 90 [ 	]*movd   0x90909090\(%eax\),%mm2
- 414:	0f 6f 90 90 90 90 90 [ 	]*movq   0x90909090\(%eax\),%mm2
+ 349:	0f 40 90 90 90 90 90 [ 	]*cmovo  -0x6f6f6f70\(%eax\),%edx
+ 350:	0f 41 90 90 90 90 90 [ 	]*cmovno -0x6f6f6f70\(%eax\),%edx
+ 357:	0f 42 90 90 90 90 90 [ 	]*cmovb  -0x6f6f6f70\(%eax\),%edx
+ 35e:	0f 43 90 90 90 90 90 [ 	]*cmovae -0x6f6f6f70\(%eax\),%edx
+ 365:	0f 44 90 90 90 90 90 [ 	]*cmove  -0x6f6f6f70\(%eax\),%edx
+ 36c:	0f 45 90 90 90 90 90 [ 	]*cmovne -0x6f6f6f70\(%eax\),%edx
+ 373:	0f 46 90 90 90 90 90 [ 	]*cmovbe -0x6f6f6f70\(%eax\),%edx
+ 37a:	0f 47 90 90 90 90 90 [ 	]*cmova  -0x6f6f6f70\(%eax\),%edx
+ 381:	0f 48 90 90 90 90 90 [ 	]*cmovs  -0x6f6f6f70\(%eax\),%edx
+ 388:	0f 49 90 90 90 90 90 [ 	]*cmovns -0x6f6f6f70\(%eax\),%edx
+ 38f:	0f 4a 90 90 90 90 90 [ 	]*cmovp  -0x6f6f6f70\(%eax\),%edx
+ 396:	0f 4b 90 90 90 90 90 [ 	]*cmovnp -0x6f6f6f70\(%eax\),%edx
+ 39d:	0f 4c 90 90 90 90 90 [ 	]*cmovl  -0x6f6f6f70\(%eax\),%edx
+ 3a4:	0f 4d 90 90 90 90 90 [ 	]*cmovge -0x6f6f6f70\(%eax\),%edx
+ 3ab:	0f 4e 90 90 90 90 90 [ 	]*cmovle -0x6f6f6f70\(%eax\),%edx
+ 3b2:	0f 4f 90 90 90 90 90 [ 	]*cmovg  -0x6f6f6f70\(%eax\),%edx
+ 3b9:	0f 60 90 90 90 90 90 [ 	]*punpcklbw -0x6f6f6f70\(%eax\),%mm2
+ 3c0:	0f 61 90 90 90 90 90 [ 	]*punpcklwd -0x6f6f6f70\(%eax\),%mm2
+ 3c7:	0f 62 90 90 90 90 90 [ 	]*punpckldq -0x6f6f6f70\(%eax\),%mm2
+ 3ce:	0f 63 90 90 90 90 90 [ 	]*packsswb -0x6f6f6f70\(%eax\),%mm2
+ 3d5:	0f 64 90 90 90 90 90 [ 	]*pcmpgtb -0x6f6f6f70\(%eax\),%mm2
+ 3dc:	0f 65 90 90 90 90 90 [ 	]*pcmpgtw -0x6f6f6f70\(%eax\),%mm2
+ 3e3:	0f 66 90 90 90 90 90 [ 	]*pcmpgtd -0x6f6f6f70\(%eax\),%mm2
+ 3ea:	0f 67 90 90 90 90 90 [ 	]*packuswb -0x6f6f6f70\(%eax\),%mm2
+ 3f1:	0f 68 90 90 90 90 90 [ 	]*punpckhbw -0x6f6f6f70\(%eax\),%mm2
+ 3f8:	0f 69 90 90 90 90 90 [ 	]*punpckhwd -0x6f6f6f70\(%eax\),%mm2
+ 3ff:	0f 6a 90 90 90 90 90 [ 	]*punpckhdq -0x6f6f6f70\(%eax\),%mm2
+ 406:	0f 6b 90 90 90 90 90 [ 	]*packssdw -0x6f6f6f70\(%eax\),%mm2
+ 40d:	0f 6e 90 90 90 90 90 [ 	]*movd   -0x6f6f6f70\(%eax\),%mm2
+ 414:	0f 6f 90 90 90 90 90 [ 	]*movq   -0x6f6f6f70\(%eax\),%mm2
  41b:	0f 71 d0 90 [ 	]*psrlw  \$0x90,%mm0
  41f:	0f 72 d0 90 [ 	]*psrld  \$0x90,%mm0
  423:	0f 73 d0 90 [ 	]*psrlq  \$0x90,%mm0
- 427:	0f 74 90 90 90 90 90 [ 	]*pcmpeqb 0x90909090\(%eax\),%mm2
- 42e:	0f 75 90 90 90 90 90 [ 	]*pcmpeqw 0x90909090\(%eax\),%mm2
- 435:	0f 76 90 90 90 90 90 [ 	]*pcmpeqd 0x90909090\(%eax\),%mm2
+ 427:	0f 74 90 90 90 90 90 [ 	]*pcmpeqb -0x6f6f6f70\(%eax\),%mm2
+ 42e:	0f 75 90 90 90 90 90 [ 	]*pcmpeqw -0x6f6f6f70\(%eax\),%mm2
+ 435:	0f 76 90 90 90 90 90 [ 	]*pcmpeqd -0x6f6f6f70\(%eax\),%mm2
  43c:	0f 77 [ 	]*emms   
- 43e:	0f 7e 90 90 90 90 90 [ 	]*movd   %mm2,0x90909090\(%eax\)
- 445:	0f 7f 90 90 90 90 90 [ 	]*movq   %mm2,0x90909090\(%eax\)
+ 43e:	0f 7e 90 90 90 90 90 [ 	]*movd   %mm2,-0x6f6f6f70\(%eax\)
+ 445:	0f 7f 90 90 90 90 90 [ 	]*movq   %mm2,-0x6f6f6f70\(%eax\)
  44c:	0f 80 90 90 90 90 [ 	]*jo     (0x)?909094e2.*
  452:	0f 81 90 90 90 90 [ 	]*jno    (0x)?909094e8.*
  458:	0f 82 90 90 90 90 [ 	]*jb     (0x)?909094ee.*
@@ -321,51 +321,51 @@ Disassembly of section .text:
  49a:	0f 8d 90 90 90 90 [ 	]*jge    (0x)?90909530.*
  4a0:	0f 8e 90 90 90 90 [ 	]*jle    (0x)?90909536.*
  4a6:	0f 8f 90 90 90 90 [ 	]*jg     (0x)?9090953c.*
- 4ac:	0f 90 80 90 90 90 90 [ 	]*seto   0x90909090\(%eax\)
- 4b3:	0f 91 80 90 90 90 90 [ 	]*setno  0x90909090\(%eax\)
- 4ba:	0f 92 80 90 90 90 90 [ 	]*setb   0x90909090\(%eax\)
- 4c1:	0f 93 80 90 90 90 90 [ 	]*setae  0x90909090\(%eax\)
- 4c8:	0f 94 80 90 90 90 90 [ 	]*sete   0x90909090\(%eax\)
- 4cf:	0f 95 80 90 90 90 90 [ 	]*setne  0x90909090\(%eax\)
- 4d6:	0f 96 80 90 90 90 90 [ 	]*setbe  0x90909090\(%eax\)
- 4dd:	0f 97 80 90 90 90 90 [ 	]*seta   0x90909090\(%eax\)
- 4e4:	0f 98 80 90 90 90 90 [ 	]*sets   0x90909090\(%eax\)
- 4eb:	0f 99 80 90 90 90 90 [ 	]*setns  0x90909090\(%eax\)
- 4f2:	0f 9a 80 90 90 90 90 [ 	]*setp   0x90909090\(%eax\)
- 4f9:	0f 9b 80 90 90 90 90 [ 	]*setnp  0x90909090\(%eax\)
- 500:	0f 9c 80 90 90 90 90 [ 	]*setl   0x90909090\(%eax\)
- 507:	0f 9d 80 90 90 90 90 [ 	]*setge  0x90909090\(%eax\)
- 50e:	0f 9e 80 90 90 90 90 [ 	]*setle  0x90909090\(%eax\)
- 515:	0f 9f 80 90 90 90 90 [ 	]*setg   0x90909090\(%eax\)
+ 4ac:	0f 90 80 90 90 90 90 [ 	]*seto   -0x6f6f6f70\(%eax\)
+ 4b3:	0f 91 80 90 90 90 90 [ 	]*setno  -0x6f6f6f70\(%eax\)
+ 4ba:	0f 92 80 90 90 90 90 [ 	]*setb   -0x6f6f6f70\(%eax\)
+ 4c1:	0f 93 80 90 90 90 90 [ 	]*setae  -0x6f6f6f70\(%eax\)
+ 4c8:	0f 94 80 90 90 90 90 [ 	]*sete   -0x6f6f6f70\(%eax\)
+ 4cf:	0f 95 80 90 90 90 90 [ 	]*setne  -0x6f6f6f70\(%eax\)
+ 4d6:	0f 96 80 90 90 90 90 [ 	]*setbe  -0x6f6f6f70\(%eax\)
+ 4dd:	0f 97 80 90 90 90 90 [ 	]*seta   -0x6f6f6f70\(%eax\)
+ 4e4:	0f 98 80 90 90 90 90 [ 	]*sets   -0x6f6f6f70\(%eax\)
+ 4eb:	0f 99 80 90 90 90 90 [ 	]*setns  -0x6f6f6f70\(%eax\)
+ 4f2:	0f 9a 80 90 90 90 90 [ 	]*setp   -0x6f6f6f70\(%eax\)
+ 4f9:	0f 9b 80 90 90 90 90 [ 	]*setnp  -0x6f6f6f70\(%eax\)
+ 500:	0f 9c 80 90 90 90 90 [ 	]*setl   -0x6f6f6f70\(%eax\)
+ 507:	0f 9d 80 90 90 90 90 [ 	]*setge  -0x6f6f6f70\(%eax\)
+ 50e:	0f 9e 80 90 90 90 90 [ 	]*setle  -0x6f6f6f70\(%eax\)
+ 515:	0f 9f 80 90 90 90 90 [ 	]*setg   -0x6f6f6f70\(%eax\)
  51c:	0f a0 [ 	]*push   %fs
  51e:	0f a1 [ 	]*pop    %fs
  520:	0f a2 [ 	]*cpuid  
- 522:	0f a3 90 90 90 90 90 [ 	]*bt     %edx,0x90909090\(%eax\)
- 529:	0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%edx,0x90909090\(%eax\)
- 531:	0f a5 90 90 90 90 90 [ 	]*shld   %cl,%edx,0x90909090\(%eax\)
+ 522:	0f a3 90 90 90 90 90 [ 	]*bt     %edx,-0x6f6f6f70\(%eax\)
+ 529:	0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%edx,-0x6f6f6f70\(%eax\)
+ 531:	0f a5 90 90 90 90 90 [ 	]*shld   %cl,%edx,-0x6f6f6f70\(%eax\)
  538:	0f a8 [ 	]*push   %gs
  53a:	0f a9 [ 	]*pop    %gs
  53c:	0f aa [ 	]*rsm    
- 53e:	0f ab 90 90 90 90 90 [ 	]*bts    %edx,0x90909090\(%eax\)
- 545:	0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%edx,0x90909090\(%eax\)
- 54d:	0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%edx,0x90909090\(%eax\)
- 554:	0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%edx
- 55b:	0f b0 90 90 90 90 90 [ 	]*cmpxchg %dl,0x90909090\(%eax\)
- 562:	0f b1 90 90 90 90 90 [ 	]*cmpxchg %edx,0x90909090\(%eax\)
- 569:	0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%edx
- 570:	0f b3 90 90 90 90 90 [ 	]*btr    %edx,0x90909090\(%eax\)
- 577:	0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%edx
- 57e:	0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%edx
- 585:	0f b6 90 90 90 90 90 [ 	]*movzbl 0x90909090\(%eax\),%edx
- 58c:	0f b7 90 90 90 90 90 [ 	]*movzwl 0x90909090\(%eax\),%edx
+ 53e:	0f ab 90 90 90 90 90 [ 	]*bts    %edx,-0x6f6f6f70\(%eax\)
+ 545:	0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%edx,-0x6f6f6f70\(%eax\)
+ 54d:	0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%edx,-0x6f6f6f70\(%eax\)
+ 554:	0f af 90 90 90 90 90 [ 	]*imul   -0x6f6f6f70\(%eax\),%edx
+ 55b:	0f b0 90 90 90 90 90 [ 	]*cmpxchg %dl,-0x6f6f6f70\(%eax\)
+ 562:	0f b1 90 90 90 90 90 [ 	]*cmpxchg %edx,-0x6f6f6f70\(%eax\)
+ 569:	0f b2 90 90 90 90 90 [ 	]*lss    -0x6f6f6f70\(%eax\),%edx
+ 570:	0f b3 90 90 90 90 90 [ 	]*btr    %edx,-0x6f6f6f70\(%eax\)
+ 577:	0f b4 90 90 90 90 90 [ 	]*lfs    -0x6f6f6f70\(%eax\),%edx
+ 57e:	0f b5 90 90 90 90 90 [ 	]*lgs    -0x6f6f6f70\(%eax\),%edx
+ 585:	0f b6 90 90 90 90 90 [ 	]*movzbl -0x6f6f6f70\(%eax\),%edx
+ 58c:	0f b7 90 90 90 90 90 [ 	]*movzwl -0x6f6f6f70\(%eax\),%edx
  593:	0f b9 [ 	]*ud2b   
- 595:	0f bb 90 90 90 90 90 [ 	]*btc    %edx,0x90909090\(%eax\)
- 59c:	0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%edx
- 5a3:	0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%edx
- 5aa:	0f be 90 90 90 90 90 [ 	]*movsbl 0x90909090\(%eax\),%edx
- 5b1:	0f bf 90 90 90 90 90 [ 	]*movswl 0x90909090\(%eax\),%edx
- 5b8:	0f c0 90 90 90 90 90 [ 	]*xadd   %dl,0x90909090\(%eax\)
- 5bf:	0f c1 90 90 90 90 90 [ 	]*xadd   %edx,0x90909090\(%eax\)
+ 595:	0f bb 90 90 90 90 90 [ 	]*btc    %edx,-0x6f6f6f70\(%eax\)
+ 59c:	0f bc 90 90 90 90 90 [ 	]*bsf    -0x6f6f6f70\(%eax\),%edx
+ 5a3:	0f bd 90 90 90 90 90 [ 	]*bsr    -0x6f6f6f70\(%eax\),%edx
+ 5aa:	0f be 90 90 90 90 90 [ 	]*movsbl -0x6f6f6f70\(%eax\),%edx
+ 5b1:	0f bf 90 90 90 90 90 [ 	]*movswl -0x6f6f6f70\(%eax\),%edx
+ 5b8:	0f c0 90 90 90 90 90 [ 	]*xadd   %dl,-0x6f6f6f70\(%eax\)
+ 5bf:	0f c1 90 90 90 90 90 [ 	]*xadd   %edx,-0x6f6f6f70\(%eax\)
  5c6:	0f c8 [ 	]*bswap  %eax
  5c8:	0f c9 [ 	]*bswap  %ecx
  5ca:	0f ca [ 	]*bswap  %edx
@@ -374,65 +374,65 @@ Disassembly of section .text:
  5d0:	0f cd [ 	]*bswap  %ebp
  5d2:	0f ce [ 	]*bswap  %esi
  5d4:	0f cf [ 	]*bswap  %edi
- 5d6:	0f d1 90 90 90 90 90 [ 	]*psrlw  0x90909090\(%eax\),%mm2
- 5dd:	0f d2 90 90 90 90 90 [ 	]*psrld  0x90909090\(%eax\),%mm2
- 5e4:	0f d3 90 90 90 90 90 [ 	]*psrlq  0x90909090\(%eax\),%mm2
- 5eb:	0f d5 90 90 90 90 90 [ 	]*pmullw 0x90909090\(%eax\),%mm2
- 5f2:	0f d8 90 90 90 90 90 [ 	]*psubusb 0x90909090\(%eax\),%mm2
- 5f9:	0f d9 90 90 90 90 90 [ 	]*psubusw 0x90909090\(%eax\),%mm2
- 600:	0f db 90 90 90 90 90 [ 	]*pand   0x90909090\(%eax\),%mm2
- 607:	0f dc 90 90 90 90 90 [ 	]*paddusb 0x90909090\(%eax\),%mm2
- 60e:	0f dd 90 90 90 90 90 [ 	]*paddusw 0x90909090\(%eax\),%mm2
- 615:	0f df 90 90 90 90 90 [ 	]*pandn  0x90909090\(%eax\),%mm2
- 61c:	0f e1 90 90 90 90 90 [ 	]*psraw  0x90909090\(%eax\),%mm2
- 623:	0f e2 90 90 90 90 90 [ 	]*psrad  0x90909090\(%eax\),%mm2
- 62a:	0f e5 90 90 90 90 90 [ 	]*pmulhw 0x90909090\(%eax\),%mm2
- 631:	0f e8 90 90 90 90 90 [ 	]*psubsb 0x90909090\(%eax\),%mm2
- 638:	0f e9 90 90 90 90 90 [ 	]*psubsw 0x90909090\(%eax\),%mm2
- 63f:	0f eb 90 90 90 90 90 [ 	]*por    0x90909090\(%eax\),%mm2
- 646:	0f ec 90 90 90 90 90 [ 	]*paddsb 0x90909090\(%eax\),%mm2
- 64d:	0f ed 90 90 90 90 90 [ 	]*paddsw 0x90909090\(%eax\),%mm2
- 654:	0f ef 90 90 90 90 90 [ 	]*pxor   0x90909090\(%eax\),%mm2
- 65b:	0f f1 90 90 90 90 90 [ 	]*psllw  0x90909090\(%eax\),%mm2
- 662:	0f f2 90 90 90 90 90 [ 	]*pslld  0x90909090\(%eax\),%mm2
- 669:	0f f3 90 90 90 90 90 [ 	]*psllq  0x90909090\(%eax\),%mm2
- 670:	0f f5 90 90 90 90 90 [ 	]*pmaddwd 0x90909090\(%eax\),%mm2
- 677:	0f f8 90 90 90 90 90 [ 	]*psubb  0x90909090\(%eax\),%mm2
- 67e:	0f f9 90 90 90 90 90 [ 	]*psubw  0x90909090\(%eax\),%mm2
- 685:	0f fa 90 90 90 90 90 [ 	]*psubd  0x90909090\(%eax\),%mm2
- 68c:	0f fc 90 90 90 90 90 [ 	]*paddb  0x90909090\(%eax\),%mm2
- 693:	0f fd 90 90 90 90 90 [ 	]*paddw  0x90909090\(%eax\),%mm2
- 69a:	0f fe 90 90 90 90 90 [ 	]*paddd  0x90909090\(%eax\),%mm2
- 6a1:	66 01 90 90 90 90 90 [ 	]*add    %dx,0x90909090\(%eax\)
- 6a8:	66 03 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%dx
+ 5d6:	0f d1 90 90 90 90 90 [ 	]*psrlw  -0x6f6f6f70\(%eax\),%mm2
+ 5dd:	0f d2 90 90 90 90 90 [ 	]*psrld  -0x6f6f6f70\(%eax\),%mm2
+ 5e4:	0f d3 90 90 90 90 90 [ 	]*psrlq  -0x6f6f6f70\(%eax\),%mm2
+ 5eb:	0f d5 90 90 90 90 90 [ 	]*pmullw -0x6f6f6f70\(%eax\),%mm2
+ 5f2:	0f d8 90 90 90 90 90 [ 	]*psubusb -0x6f6f6f70\(%eax\),%mm2
+ 5f9:	0f d9 90 90 90 90 90 [ 	]*psubusw -0x6f6f6f70\(%eax\),%mm2
+ 600:	0f db 90 90 90 90 90 [ 	]*pand   -0x6f6f6f70\(%eax\),%mm2
+ 607:	0f dc 90 90 90 90 90 [ 	]*paddusb -0x6f6f6f70\(%eax\),%mm2
+ 60e:	0f dd 90 90 90 90 90 [ 	]*paddusw -0x6f6f6f70\(%eax\),%mm2
+ 615:	0f df 90 90 90 90 90 [ 	]*pandn  -0x6f6f6f70\(%eax\),%mm2
+ 61c:	0f e1 90 90 90 90 90 [ 	]*psraw  -0x6f6f6f70\(%eax\),%mm2
+ 623:	0f e2 90 90 90 90 90 [ 	]*psrad  -0x6f6f6f70\(%eax\),%mm2
+ 62a:	0f e5 90 90 90 90 90 [ 	]*pmulhw -0x6f6f6f70\(%eax\),%mm2
+ 631:	0f e8 90 90 90 90 90 [ 	]*psubsb -0x6f6f6f70\(%eax\),%mm2
+ 638:	0f e9 90 90 90 90 90 [ 	]*psubsw -0x6f6f6f70\(%eax\),%mm2
+ 63f:	0f eb 90 90 90 90 90 [ 	]*por    -0x6f6f6f70\(%eax\),%mm2
+ 646:	0f ec 90 90 90 90 90 [ 	]*paddsb -0x6f6f6f70\(%eax\),%mm2
+ 64d:	0f ed 90 90 90 90 90 [ 	]*paddsw -0x6f6f6f70\(%eax\),%mm2
+ 654:	0f ef 90 90 90 90 90 [ 	]*pxor   -0x6f6f6f70\(%eax\),%mm2
+ 65b:	0f f1 90 90 90 90 90 [ 	]*psllw  -0x6f6f6f70\(%eax\),%mm2
+ 662:	0f f2 90 90 90 90 90 [ 	]*pslld  -0x6f6f6f70\(%eax\),%mm2
+ 669:	0f f3 90 90 90 90 90 [ 	]*psllq  -0x6f6f6f70\(%eax\),%mm2
+ 670:	0f f5 90 90 90 90 90 [ 	]*pmaddwd -0x6f6f6f70\(%eax\),%mm2
+ 677:	0f f8 90 90 90 90 90 [ 	]*psubb  -0x6f6f6f70\(%eax\),%mm2
+ 67e:	0f f9 90 90 90 90 90 [ 	]*psubw  -0x6f6f6f70\(%eax\),%mm2
+ 685:	0f fa 90 90 90 90 90 [ 	]*psubd  -0x6f6f6f70\(%eax\),%mm2
+ 68c:	0f fc 90 90 90 90 90 [ 	]*paddb  -0x6f6f6f70\(%eax\),%mm2
+ 693:	0f fd 90 90 90 90 90 [ 	]*paddw  -0x6f6f6f70\(%eax\),%mm2
+ 69a:	0f fe 90 90 90 90 90 [ 	]*paddd  -0x6f6f6f70\(%eax\),%mm2
+ 6a1:	66 01 90 90 90 90 90 [ 	]*add    %dx,-0x6f6f6f70\(%eax\)
+ 6a8:	66 03 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%dx
  6af:	66 05 90 90 [ 	]*add    \$0x9090,%ax
  6b3:	66 06 [ 	]*pushw  %es
  6b5:	66 07 [ 	]*popw   %es
- 6b7:	66 09 90 90 90 90 90 [ 	]*or     %dx,0x90909090\(%eax\)
- 6be:	66 0b 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%dx
+ 6b7:	66 09 90 90 90 90 90 [ 	]*or     %dx,-0x6f6f6f70\(%eax\)
+ 6be:	66 0b 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%dx
  6c5:	66 0d 90 90 [ 	]*or     \$0x9090,%ax
  6c9:	66 0e [ 	]*pushw  %cs
- 6cb:	66 11 90 90 90 90 90 [ 	]*adc    %dx,0x90909090\(%eax\)
- 6d2:	66 13 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%dx
+ 6cb:	66 11 90 90 90 90 90 [ 	]*adc    %dx,-0x6f6f6f70\(%eax\)
+ 6d2:	66 13 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%dx
  6d9:	66 15 90 90 [ 	]*adc    \$0x9090,%ax
  6dd:	66 16 [ 	]*pushw  %ss
  6df:	66 17 [ 	]*popw   %ss
- 6e1:	66 19 90 90 90 90 90 [ 	]*sbb    %dx,0x90909090\(%eax\)
- 6e8:	66 1b 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%dx
+ 6e1:	66 19 90 90 90 90 90 [ 	]*sbb    %dx,-0x6f6f6f70\(%eax\)
+ 6e8:	66 1b 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%dx
  6ef:	66 1d 90 90 [ 	]*sbb    \$0x9090,%ax
  6f3:	66 1e [ 	]*pushw  %ds
  6f5:	66 1f [ 	]*popw   %ds
- 6f7:	66 21 90 90 90 90 90 [ 	]*and    %dx,0x90909090\(%eax\)
- 6fe:	66 23 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%dx
+ 6f7:	66 21 90 90 90 90 90 [ 	]*and    %dx,-0x6f6f6f70\(%eax\)
+ 6fe:	66 23 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%dx
  705:	66 25 90 90 [ 	]*and    \$0x9090,%ax
- 709:	66 29 90 90 90 90 90 [ 	]*sub    %dx,0x90909090\(%eax\)
- 710:	66 2b 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%dx
+ 709:	66 29 90 90 90 90 90 [ 	]*sub    %dx,-0x6f6f6f70\(%eax\)
+ 710:	66 2b 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%dx
  717:	66 2d 90 90 [ 	]*sub    \$0x9090,%ax
- 71b:	66 31 90 90 90 90 90 [ 	]*xor    %dx,0x90909090\(%eax\)
- 722:	66 33 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%dx
+ 71b:	66 31 90 90 90 90 90 [ 	]*xor    %dx,-0x6f6f6f70\(%eax\)
+ 722:	66 33 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%dx
  729:	66 35 90 90 [ 	]*xor    \$0x9090,%ax
- 72d:	66 39 90 90 90 90 90 [ 	]*cmp    %dx,0x90909090\(%eax\)
- 734:	66 3b 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%dx
+ 72d:	66 39 90 90 90 90 90 [ 	]*cmp    %dx,-0x6f6f6f70\(%eax\)
+ 734:	66 3b 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%dx
  73b:	66 3d 90 90 [ 	]*cmp    \$0x9090,%ax
  73f:	66 40 [ 	]*inc    %ax
  741:	66 41 [ 	]*inc    %cx
@@ -468,22 +468,22 @@ Disassembly of section .text:
  77d:	66 5f [ 	]*pop    %di
  77f:	66 60 [ 	]*pushaw 
  781:	66 61 [ 	]*popaw  
- 783:	66 62 90 90 90 90 90 [ 	]*bound  %dx,0x90909090\(%eax\)
+ 783:	66 62 90 90 90 90 90 [ 	]*bound  %dx,-0x6f6f6f70\(%eax\)
  78a:	66 68 90 90 [ 	]*pushw  \$0x9090
- 78e:	66 69 90 90 90 90 90 90 90 [ 	]*imul   \$0x9090,0x90909090\(%eax\),%dx
+ 78e:	66 69 90 90 90 90 90 90 90 [ 	]*imul   \$0x9090,-0x6f6f6f70\(%eax\),%dx
  797:	66 6a 90 [ 	]*pushw  \$0xffffff90
- 79a:	66 6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,0x90909090\(%eax\),%dx
+ 79a:	66 6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,-0x6f6f6f70\(%eax\),%dx
  7a2:	66 6d [ 	]*insw   \(%dx\),%es:\(%edi\)
  7a4:	66 6f [ 	]*outsw  %ds:\(%esi\),\(%dx\)
- 7a6:	66 81 90 90 90 90 90 90 90 [ 	]*adcw   \$0x9090,0x90909090\(%eax\)
- 7af:	66 83 90 90 90 90 90 90 [ 	]*adcw   \$0xffffff90,0x90909090\(%eax\)
- 7b7:	66 85 90 90 90 90 90 [ 	]*test   %dx,0x90909090\(%eax\)
- 7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
- 7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
- 7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,0x90909090\(%eax\)
- 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7a6:	66 81 90 90 90 90 90 90 90 [ 	]*adcw   \$0x9090,-0x6f6f6f70\(%eax\)
+ 7af:	66 83 90 90 90 90 90 90 [ 	]*adcw   \$0xffffff90,-0x6f6f6f70\(%eax\)
+ 7b7:	66 85 90 90 90 90 90 [ 	]*test   %dx,-0x6f6f6f70\(%eax\)
+ 7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,-0x6f6f6f70\(%eax\)
+ 7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,-0x6f6f6f70\(%eax\)
+ 7cc:	66 8b 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%dx
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,-0x6f6f6f70\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    -0x6f6f6f70\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   -0x6f6f6f70\(%eax\)
  7e7:	66 91 [ 	]*xchg   %ax,%cx
  7e9:	66 92 [ 	]*xchg   %ax,%dx
  7eb:	66 93 [ 	]*xchg   %ax,%bx
@@ -512,67 +512,67 @@ Disassembly of section .text:
  831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
  835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
  839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,-0x6f6f6f70\(%eax\)
  845:	66 c2 90 90 [ 	]*retw   \$0x9090
  849:	66 c3 [ 	]*retw   
- 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    -0x6f6f6f70\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    -0x6f6f6f70\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,-0x6f6f6f70\(%eax\)
  862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
  867:	66 c9 [ 	]*leavew 
  869:	66 ca 90 90 [ 	]*lretw  \$0x9090
  86d:	66 cb [ 	]*lretw  
  86f:	66 cf [ 	]*iretw  
- 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   -0x6f6f6f70\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,-0x6f6f6f70\(%eax\)
  87f:	66 e5 90 [ 	]*in     \$0x90,%ax
  882:	66 e7 90 [ 	]*out    %ax,\$0x90
  885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
  889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
  88f:	66 ed [ 	]*in     \(%dx\),%ax
  891:	66 ef [ 	]*out    %ax,\(%dx\)
- 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   -0x6f6f6f70\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*-0x6f6f6f70\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    -0x6f6f6f70\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    -0x6f6f6f70\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  -0x6f6f6f70\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno -0x6f6f6f70\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  -0x6f6f6f70\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae -0x6f6f6f70\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  -0x6f6f6f70\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne -0x6f6f6f70\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe -0x6f6f6f70\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  -0x6f6f6f70\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  -0x6f6f6f70\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns -0x6f6f6f70\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  -0x6f6f6f70\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp -0x6f6f6f70\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  -0x6f6f6f70\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge -0x6f6f6f70\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle -0x6f6f6f70\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  -0x6f6f6f70\(%eax\),%dx
  931:	66 0f a0 [ 	]*pushw  %fs
  934:	66 0f a1 [ 	]*popw   %fs
- 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,-0x6f6f6f70\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,-0x6f6f6f70\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,-0x6f6f6f70\(%eax\)
  950:	66 0f a8 [ 	]*pushw  %gs
  953:	66 0f a9 [ 	]*popw   %gs
- 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,-0x6f6f6f70\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,-0x6f6f6f70\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,-0x6f6f6f70\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   -0x6f6f6f70\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,-0x6f6f6f70\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    -0x6f6f6f70\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,-0x6f6f6f70\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    -0x6f6f6f70\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    -0x6f6f6f70\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw -0x6f6f6f70\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,-0x6f6f6f70\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    -0x6f6f6f70\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    -0x6f6f6f70\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw -0x6f6f6f70\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,-0x6f6f6f70\(%eax\)
 
 0+9cf <gs_foo>:
  9cf:	c3 [ 	]*ret    
@@ -591,7 +591,7 @@ Disassembly of section .text:
  9ec:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
  9ef:	eb 0c [ 	]*jmp    9fd <rot5>
  9f1:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
- 9f2:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 9f2:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,-0x6f6f6f70\(%eax\)
  9fa:	83 e0 f8 [ 	]*and    \$0xfffffff8,%eax
 
 0+9fd <rot5>:
@@ -601,7 +601,7 @@ Disassembly of section .text:
  a04:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
  a09:	0e [ 	]*push   %cs
  a0a:	8b 04 5d 00 00 00 00 [ 	]*mov    0x0\(,%ebx,2\),%eax
- a11:	10 14 85 90 90 90 90 [ 	]*adc    %dl,0x90909090\(,%eax,4\)
+ a11:	10 14 85 90 90 90 90 [ 	]*adc    %dl,-0x6f6f6f70\(,%eax,4\)
  a18:	2f [ 	]*das    
  a19:	ea 90 90 90 90 90 90 [ 	]*ljmp   \$0x9090,\$0x90909090
  a20:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
@@ -628,5 +628,6 @@ Disassembly of section .text:
  a87:	b0 11 [ 	]*mov    \$0x11,%al
  a89:	b3 47 [ 	]*mov    \$0x47,%bl
  a8b:	b3 47 [ 	]*mov    \$0x47,%bl
- a8d:	00 00 .*
+ a8d:	0f ad d0 [ 	]*shrd   %cl,%edx,%eax
+ a90:	0f a5 d0 [ 	]*shld   %cl,%edx,%eax
 [ 	]*...
diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 464f4b6d411b..ef65aa9c30f0 100644
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -484,8 +484,8 @@ foo:
  xchg   bp, ax
  xchg   si, ax
  xchg   di, ax
- cbtw
- cwtd
+ cbw
+ cwd
  callw  0x9090,0x9090
  pushfw
  popfw
@@ -624,5 +624,8 @@ rot5:
 	mov	%al, 0x11
 	mov	%bl, ((( 0x4711  ) >> 8) & 0xff) 
 	mov	%bl, 0x47
-	
+
+ shrd   eax, edx, cl
+ shld   eax, edx, cl
+
  .p2align 4,0
diff --git a/gas/testsuite/gas/i386/intel16.d b/gas/testsuite/gas/i386/intel16.d
index 495fe14f211b..e6d0ee28f83a 100644
--- a/gas/testsuite/gas/i386/intel16.d
+++ b/gas/testsuite/gas/i386/intel16.d
@@ -7,12 +7,12 @@
 Disassembly of section .text:
 
 0+000 <.text>:
-   0:	66 0f bf 06 00 00 [ 	]*movswl 0,%eax
-   6:	66 0f be 06 00 00 [ 	]*movsbl 0,%eax
-   c:	0f be 06 00 00 [ 	]*movsbw 0,%ax
-  11:	66 0f b7 06 00 00 [ 	]*movzwl 0,%eax
-  17:	66 0f b6 06 00 00 [ 	]*movzbl 0,%eax
-  1d:	0f b6 06 00 00 [ 	]*movzbw 0,%ax
+   0:	66 0f bf 06 00 00 [ 	]*movswl 0x0,%eax
+   6:	66 0f be 06 00 00 [ 	]*movsbl 0x0,%eax
+   c:	0f be 06 00 00 [ 	]*movsbw 0x0,%ax
+  11:	66 0f b7 06 00 00 [ 	]*movzwl 0x0,%eax
+  17:	66 0f b6 06 00 00 [ 	]*movzbl 0x0,%eax
+  1d:	0f b6 06 00 00 [ 	]*movzbw 0x0,%ax
   22:	8d 00 [ 	]*lea    \(%bx,%si\),%ax
   24:	8d 02 [ 	]*lea    \(%bp,%si\),%ax
   26:	8d 01 [ 	]*lea    \(%bx,%di\),%ax
diff --git a/gas/testsuite/gas/i386/intelok.d b/gas/testsuite/gas/i386/intelok.d
index 8e7fdbf75447..878b712cf117 100644
--- a/gas/testsuite/gas/i386/intelok.d
+++ b/gas/testsuite/gas/i386/intelok.d
@@ -94,35 +94,35 @@ Disassembly of section .text:
 [ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
 [ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
 [ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
-[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+4\]
-[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+4\]
-[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+6\]
-[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+6\]
-[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+12\]
-[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+12\]
-[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+18\]
-[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+18\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?4\]
+[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?4\]
+[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?6\]
+[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?6\]
+[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0xc\]
+[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0xc\]
+[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0x12\]
+[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0x12\]
 [ 	]*[0-9a-f]+:	8b 04 85 02 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
 [ 	]*[0-9a-f]+:	8b 04 85 02 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
-[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\]
-[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\]
-[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\]
-[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\]
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 fb[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\-5\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 0f[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+15\]
-[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+16\]
-[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+16\]
-[ 	]*[0-9a-f]+:	8b 44 08 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+16\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
-[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\+(0x)?0]
+[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\+(0x)?0]
+[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\+(0x)?0]
+[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\+(0x)?0]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 fb[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\-(0x)?5\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 0f[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+0xf\]
+[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0x10\]
+[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+0x10\]
+[ 	]*[0-9a-f]+:	8b 44 08 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+0x10\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\]
 [ 	]*[0-9a-f]+:	8b 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
 [ 	]*[0-9a-f]+:	8b 04 08[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\]
 [ 	]*[0-9a-f]+:	8b 04 08[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\]
@@ -153,12 +153,12 @@ Disassembly of section .text:
 [ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
 [ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
 [ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
-[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1]
-[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?0\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1]
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?0\]
 [ 	]*[0-9a-f]+:	8b 80 01 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
-[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
-[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?0\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
 [ 	]*[0-9a-f]+:	a1 01 00 00 00[ 	]+mov[ 	]+eax,ds:0x1
 [ 	]*[0-9a-f]+:	a1 ff ff ff ff[ 	]+mov[ 	]+eax,ds:0xffffffff
 [ 	]*[0-9a-f]+:	26 a1 02 00 00 00[ 	]+mov[ 	]+eax,es:0x2
diff --git a/gas/testsuite/gas/i386/inval-crc32.l b/gas/testsuite/gas/i386/inval-crc32.l
new file mode 100644
index 000000000000..14f908d1b9fc
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-crc32.l
@@ -0,0 +1,43 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\# Check illegal crc32 in SSE4\.2
+[ 	]*2[ 	]+
+[ 	]*3[ 	]+\.text
+[ 	]*4[ 	]+foo:
+[ 	]*5[ 	]+
+[ 	]*6[ 	]+crc32b \(%esi\), %al
+[ 	]*7[ 	]+crc32w \(%esi\), %ax
+[ 	]*8[ 	]+crc32 \(%esi\), %al
+[ 	]*9[ 	]+crc32 \(%esi\), %ax
+[ 	]*10[ 	]+crc32 \(%esi\), %eax
+[ 	]*11[ 	]+crc32  %al, %al
+[ 	]*12[ 	]+crc32b  %al, %al
+[ 	]*13[ 	]+crc32  %ax, %ax
+[ 	]*14[ 	]+crc32w  %ax, %ax
+[ 	]*15[ 	]+
+[ 	]*16[ 	]+\.intel_syntax noprefix
+[ 	]*17[ 	]+crc32  al,byte ptr \[esi\]
+[ 	]*18[ 	]+crc32  ax, word ptr \[esi\]
+[ 	]*19[ 	]+crc32  al, \[esi\]
+[ 	]*20[ 	]+crc32  ax, \[esi\]
+[ 	]*21[ 	]+crc32  eax, \[esi\]
+[ 	]*22[ 	]+crc32  al,al
+[ 	]*23[ 	]+crc32  ax, ax
diff --git a/gas/testsuite/gas/i386/inval-crc32.s b/gas/testsuite/gas/i386/inval-crc32.s
new file mode 100644
index 000000000000..5232fb0ae98e
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-crc32.s
@@ -0,0 +1,23 @@
+# Check illegal crc32 in SSE4.2
+
+	.text
+foo:
+
+crc32b (%esi), %al
+crc32w (%esi), %ax
+crc32 (%esi), %al
+crc32 (%esi), %ax
+crc32 (%esi), %eax
+crc32  %al, %al
+crc32b  %al, %al
+crc32  %ax, %ax
+crc32w  %ax, %ax
+
+.intel_syntax noprefix
+crc32  al,byte ptr [esi]
+crc32  ax, word ptr [esi]
+crc32  al, [esi]
+crc32  ax, [esi]
+crc32  eax, [esi]
+crc32  al,al
+crc32  ax, ax
diff --git a/gas/testsuite/gas/i386/inval.l b/gas/testsuite/gas/i386/inval.l
index e78949918531..8abcbde95a73 100644
--- a/gas/testsuite/gas/i386/inval.l
+++ b/gas/testsuite/gas/i386/inval.l
@@ -45,6 +45,8 @@
 .*:46: Error: .*
 .*:47: Error: .*
 .*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
 GAS LISTING .*
 
 
@@ -96,3 +98,5 @@ GAS LISTING .*
   46 [ 	]*	fstb	%st\(0\)
   47 [ 	]*	fcompll	28\(%ebp\)
   48 [ 	]*	fldlw	\(%eax\)
+  49 [ 	]*	movl	\$%ebx,%eax
+  50 [ 	]*	insertq	\$4,\$2,%xmm2,%ebx
diff --git a/gas/testsuite/gas/i386/inval.s b/gas/testsuite/gas/i386/inval.s
index e37a18eac60d..5b440ed0b55f 100644
--- a/gas/testsuite/gas/i386/inval.s
+++ b/gas/testsuite/gas/i386/inval.s
@@ -46,3 +46,5 @@ foo:	jaw	foo
 	fstb	%st(0)
 	fcompll	28(%ebp)
 	fldlw	(%eax)
+	movl	$%ebx,%eax
+	insertq	$4,$2,%xmm2,%ebx
diff --git a/gas/testsuite/gas/i386/jump16.d b/gas/testsuite/gas/i386/jump16.d
index 3d5d6bbb42f2..87951effa576 100644
--- a/gas/testsuite/gas/i386/jump16.d
+++ b/gas/testsuite/gas/i386/jump16.d
@@ -8,33 +8,33 @@ Disassembly of section .text:
 0+000 <.text>:
    0:	eb fe [ 	]*jmp    (0x0|0 <.text>)
    2:	e9 (fe|fb) ff [ 	]*jmp    (0x3|0x0|0 <.text>)	3: (R_386_PC)?(DISP)?16	xxx
-   5:	ff 26 00 00 [ 	]*jmp    \*0	7: (R_386_)?(dir)?16	xxx
+   5:	ff 26 00 00 [ 	]*jmp    \*0x0	7: (R_386_)?(dir)?16	xxx
    9:	66 ff e7 [ 	]*jmpl   \*%edi
    c:	67 ff 27 [ 	]*addr32 jmp \*\(%edi\)
    f:	67 ff af 00 00 00 00 [ 	]*addr32 ljmp \*0x0\(%edi\)	12: (R_386_)?(dir)?32	xxx
-  16:	ff 2e 00 00 [ 	]*ljmp   \*0	18: (R_386_)?(dir)?16	xxx
+  16:	ff 2e 00 00 [ 	]*ljmp   \*0x0	18: (R_386_)?(dir)?16	xxx
   1a:	ea 00 00 34 12 [ 	]*ljmp   \$0x1234,\$0x0	1b: (R_386_)?(dir)?16	xxx
   1f:	66 e8 db ff ff ff [ 	]*calll  (0x0|0 <.text>)
   25:	66 e8 (fc|d5) ff ff ff [ 	]*calll  (0x27|0x0|0 <.text>)	27: (R_386_PC)?(DISP)?32	xxx
-  2b:	66 ff 16 00 00 [ 	]*calll  \*0	2e: (R_386_)?(dir)?16	xxx
+  2b:	66 ff 16 00 00 [ 	]*calll  \*0x0	2e: (R_386_)?(dir)?16	xxx
   30:	66 ff d7 [ 	]*calll  \*%edi
   33:	67 66 ff 17 [ 	]*addr32 calll \*\(%edi\)
   37:	67 66 ff 9f 00 00 00 00 [ 	]*addr32 lcalll \*0x0\(%edi\)	3b: (R_386_)?(dir)?32	xxx
-  3f:	66 ff 1e 00 00 [ 	]*lcalll \*0	42: (R_386_)?(dir)?16	xxx
+  3f:	66 ff 1e 00 00 [ 	]*lcalll \*0x0	42: (R_386_)?(dir)?16	xxx
   44:	66 9a 00 00 00 00 34 12 [ 	]*lcalll \$0x1234,\$0x0	46: (R_386_)?(dir)?32	xxx
   4c:	eb b2 [ 	]*jmp    (0x0|0 <.text>)
-  4e:	ff 26 00 00 [ 	]*jmp    \*0	50: (R_386_)?(dir)?16	xxx
+  4e:	ff 26 00 00 [ 	]*jmp    \*0x0	50: (R_386_)?(dir)?16	xxx
   52:	ff e7 [ 	]*jmp    \*%di
   54:	ff 25 [ 	]*jmp    \*\(%di\)
-  56:	ff ad 00 00 [ 	]*ljmp   \*0\(%di\)	58: (R_386_)?(dir)?16	xxx
-  5a:	ff 2e 00 00 [ 	]*ljmp   \*0	5c: (R_386_)?(dir)?16	xxx
+  56:	ff ad 00 00 [ 	]*ljmp   \*0x0\(%di\)	58: (R_386_)?(dir)?16	xxx
+  5a:	ff 2e 00 00 [ 	]*ljmp   \*0x0	5c: (R_386_)?(dir)?16	xxx
   5e:	ea 00 00 34 12 [ 	]*ljmp   \$0x1234,\$0x0	5f: (R_386_)?(dir)?16	xxx
   63:	e8 9a ff [ 	]*call   (0x0|0 <.text>)
   66:	e8 (fe|97) ff [ 	]*call   (0x67|0x0|0 <.text>)	67: (R_386_PC)?(DISP)?16	xxx
-  69:	ff 16 00 00 [ 	]*call   \*0	6b: (R_386_)?(dir)?16	xxx
+  69:	ff 16 00 00 [ 	]*call   \*0x0	6b: (R_386_)?(dir)?16	xxx
   6d:	ff d7 [ 	]*call   \*%di
   6f:	ff 15 [ 	]*call   \*\(%di\)
-  71:	ff 9d 00 00 [ 	]*lcall  \*0\(%di\)	73: (R_386_)?(dir)?16	xxx
-  75:	ff 1e 00 00 [ 	]*lcall  \*0	77: (R_386_)?(dir)?16	xxx
+  71:	ff 9d 00 00 [ 	]*lcall  \*0x0\(%di\)	73: (R_386_)?(dir)?16	xxx
+  75:	ff 1e 00 00 [ 	]*lcall  \*0x0	77: (R_386_)?(dir)?16	xxx
   79:	9a 00 00 34 12 [ 	]*lcall  \$0x1234,\$0x0	7a: (R_386_)?(dir)?16	xxx
 	...
diff --git a/gas/testsuite/gas/i386/merom.d b/gas/testsuite/gas/i386/merom.d
index a09721c85eca..9baa234e45fe 100644
--- a/gas/testsuite/gas/i386/merom.d
+++ b/gas/testsuite/gas/i386/merom.d
@@ -70,4 +70,4 @@ Disassembly of section .text:
  116:	0f 38 1e c1[ 	]+pabsd  %mm1,%mm0
  11a:	66 0f 38 1e 01[ 	]+pabsd  \(%ecx\),%xmm0
  11f:	66 0f 38 1e c1[ 	]+pabsd  %xmm1,%xmm0
-	...
+#pass
diff --git a/gas/testsuite/gas/i386/naked.d b/gas/testsuite/gas/i386/naked.d
index 66214d58addf..27c1c052e501 100644
--- a/gas/testsuite/gas/i386/naked.d
+++ b/gas/testsuite/gas/i386/naked.d
@@ -6,16 +6,16 @@
 Disassembly of section .text:
 
 0+000 <foo>:
-   0:	66 26 ff 23 [ 	]*jmpw   \*%es:\(%ebx\)
+   0:	26 66 ff 23 [ 	]*jmpw   \*%es:\(%ebx\)
    4:	8a 25 50 00 00 00 [ 	]*mov    0x50,%ah
    a:	b2 20 [ 	]*mov    \$0x20,%dl
    c:	bb 00 00 00 00 [ 	]*mov    \$0x0,%ebx	d: (R_386_)?(dir)?32	.text
   11:	d9 c9 [ 	]*fxch   %st\(1\)
-  13:	36 8c a4 81 d2 04 00 00 [ 	]*movw   %fs,%ss:0x4d2\(%ecx,%eax,4\)
-  1b:	8c 2c ed 00 00 00 00 [ 	]*movw   %gs,0x0\(,%ebp,8\)
+  13:	36 8c a4 81 d2 04 00 00 [ 	]*mov    %fs,%ss:0x4d2\(%ecx,%eax,4\)
+  1b:	8c 2c ed 00 00 00 00 [ 	]*mov    %gs,0x0\(,%ebp,8\)
   22:	26 88 25 00 00 00 00 [ 	]*mov    %ah,%es:0x0
-  29:	2e 8b 74 14 80 [ 	]*mov    %cs:0xffffff80\(%esp,%edx,1\),%esi
-  2e:	f3 65 a5 [ 	]*rep movsl %gs:\(%esi\),%es:\(%edi\)
+  29:	2e 8b 74 14 80 [ 	]*mov    %cs:-0x80\(%esp,%edx,1\),%esi
+  2e:	65 f3 a5 [ 	]*rep movsl %gs:\(%esi\),%es:\(%edi\)
   31:	ec [ 	]*in     \(%dx\),%al
   32:	66 ef [ 	]*out    %ax,\(%dx\)
   34:	67 d2 14 [ 	]*addr16 rclb %cl,\(%si\)
diff --git a/gas/testsuite/gas/i386/nops-1-i386.d b/gas/testsuite/gas/i386/nops-1-i386.d
new file mode 100644
index 000000000000..6d1582aa3752
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-1-i386.d
@@ -0,0 +1,177 @@
+#as: -mtune=i686 -march=i386
+#source: nops-1.s
+#objdump: -drw
+#name: i386 -mtune=i686 -march=i386 nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+eb 0d[	 ]+jmp[ 	]+10[ 	]+<nop14>
+[	 ]*3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*f:[	 ]+90[	 ]+nop[ 	]*
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*19:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*29:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*3a:[	 ]+8d bf 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*49:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*59:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+89 f6[	 ]+mov[ 	]+%esi,%esi
+[	 ]*69:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*79:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ac:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[ 	]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-1-i686.d b/gas/testsuite/gas/i386/nops-1-i686.d
new file mode 100644
index 000000000000..b3ee23bb24b8
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-1-i686.d
@@ -0,0 +1,161 @@
+#as: -mtune=i686
+#source: nops-1.s
+#objdump: -drw
+#name: i386 -mtune=i686 nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+[	 ]*8:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+[	 ]*19:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*29:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*3a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*4a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%eax\)
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-1-merom.d b/gas/testsuite/gas/i386/nops-1-merom.d
new file mode 100644
index 000000000000..90668e56f07b
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-1-merom.d
@@ -0,0 +1,156 @@
+#as: -mtune=merom
+#source: nops-1.s
+#objdump: -drw
+#name: i386 -mtune=merom nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%eax\)
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%eax\)
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-1.d b/gas/testsuite/gas/i386/nops-1.d
new file mode 100644
index 000000000000..4e81e9554585
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-1.d
@@ -0,0 +1,176 @@
+#source: nops-1.s
+#objdump: -drw
+#name: i386 nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+eb 0d[	 ]+jmp[ 	]+10[ 	]+<nop14>
+[	 ]*3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*f:[	 ]+90[	 ]+nop[ 	]*
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*19:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*29:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*3a:[	 ]+8d bf 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*49:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*59:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+89 f6[	 ]+mov[ 	]+%esi,%esi
+[	 ]*69:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*79:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ac:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[ 	]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-1.s b/gas/testsuite/gas/i386/nops-1.s
new file mode 100644
index 000000000000..a4fd7694de76
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-1.s
@@ -0,0 +1,147 @@
+	.text
+nop15:
+	nop
+	.p2align 4
+
+nop14:
+	nop
+	nop
+	.p2align 4
+
+nop13:
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop12:
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop11:
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop10:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop9:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop8:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop7:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop6:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop5:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop4:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop3:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop2:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/nops-2-i386.d b/gas/testsuite/gas/i386/nops-2-i386.d
new file mode 100644
index 000000000000..c7dffabe70be
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-2-i386.d
@@ -0,0 +1,182 @@
+#as: -march=i386
+#source: nops-2.s
+#objdump: -drw
+#name: i386 -march=i386 nops 2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop>:
+[	 ]*0:[	 ]+0f 44 c0[	 ]+cmove[ 	]+%eax,%eax
+[	 ]*3:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*9:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+10 <nop15>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+eb 0d[	 ]+jmp[ 	]+20[ 	]+<nop14>
+[	 ]*13:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*14:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*15:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*16:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*17:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*18:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*19:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1f:[	 ]+90[	 ]+nop[ 	]*
+
+0+20 <nop14>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*29:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+30 <nop13>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*39:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+40 <nop12>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*4a:[	 ]+8d bf 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+50 <nop11>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*59:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+60 <nop10>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*69:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+70 <nop9>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+89 f6[	 ]+mov[ 	]+%esi,%esi
+[	 ]*79:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+80 <nop8>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+90 <nop7>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+a0 <nop6>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+b0 <nop5>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+c0 <nop4>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+d0 <nop3>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+e0 <nop2>:
+[	 ]*e0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ea:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*eb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ec:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ed:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ee:[	 ]+66 90[ 	]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-2-merom.d b/gas/testsuite/gas/i386/nops-2-merom.d
new file mode 100644
index 000000000000..c6ea559761e0
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-2-merom.d
@@ -0,0 +1,182 @@
+#as: -march=i386 -mtune=merom
+#source: nops-2.s
+#objdump: -drw
+#name: i386 -march=i386 -mtune=merom nops 2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop>:
+[	 ]*0:[	 ]+0f 44 c0[	 ]+cmove[ 	]+%eax,%eax
+[	 ]*3:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*9:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+10 <nop15>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+eb 0d[	 ]+jmp[ 	]+20[ 	]+<nop14>
+[	 ]*13:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*14:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*15:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*16:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*17:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*18:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*19:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1f:[	 ]+90[	 ]+nop[ 	]*
+
+0+20 <nop14>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*29:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+30 <nop13>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*39:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+40 <nop12>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*4a:[	 ]+8d bf 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+50 <nop11>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*59:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+60 <nop10>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*69:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+70 <nop9>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+89 f6[	 ]+mov[ 	]+%esi,%esi
+[	 ]*79:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+80 <nop8>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+90 <nop7>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+a0 <nop6>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+b0 <nop5>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+c0 <nop4>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+d0 <nop3>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+e0 <nop2>:
+[	 ]*e0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ea:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*eb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ec:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ed:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ee:[	 ]+66 90[ 	]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-2.d b/gas/testsuite/gas/i386/nops-2.d
new file mode 100644
index 000000000000..6382f7e3772a
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-2.d
@@ -0,0 +1,181 @@
+#source: nops-2.s
+#objdump: -drw
+#name: i386 nops 2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop>:
+[	 ]*0:[	 ]+0f 44 c0[	 ]+cmove[ 	]+%eax,%eax
+[	 ]*3:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*9:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+10 <nop15>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+eb 0d[	 ]+jmp[ 	]+20[ 	]+<nop14>
+[	 ]*13:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*14:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*15:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*16:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*17:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*18:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*19:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1f:[	 ]+90[	 ]+nop[ 	]*
+
+0+20 <nop14>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*29:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+30 <nop13>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*39:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+40 <nop12>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*4a:[	 ]+8d bf 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+50 <nop11>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*59:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+60 <nop10>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+[	 ]*69:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+70 <nop9>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+89 f6[	 ]+mov[ 	]+%esi,%esi
+[	 ]*79:[	 ]+8d bc 27 00 00 00 00[	 ]+lea[ 	]+0x0\(%edi\),%edi
+
+0+80 <nop8>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+90 <nop7>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+a0 <nop6>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+8d b6 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+b0 <nop5>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+c0 <nop4>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+8d 74 26 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+d0 <nop3>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+8d 76 00[	 ]+lea[ 	]+0x0\(%esi\),%esi
+
+0+e0 <nop2>:
+[	 ]*e0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ea:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*eb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ec:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ed:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ee:[	 ]+66 90[ 	]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops-2.s b/gas/testsuite/gas/i386/nops-2.s
new file mode 100644
index 000000000000..afbb87e09488
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-2.s
@@ -0,0 +1,151 @@
+	.text
+nop:
+	cmove	%eax,%eax
+	.p2align 4
+
+nop15:
+	nop
+	.p2align 4
+
+nop14:
+	nop
+	nop
+	.p2align 4
+
+nop13:
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop12:
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop11:
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop10:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop9:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop8:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop7:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop6:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop5:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop4:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop3:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop2:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/nops-3.d b/gas/testsuite/gas/i386/nops-3.d
new file mode 100644
index 000000000000..10cc95c3fc98
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-3.d
@@ -0,0 +1,43 @@
+#source: nops-3.s
+#objdump: -drw
+#name: i386 nops 3
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*f:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*13:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*14:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*15:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*16:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*17:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*18:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*19:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1a:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1b:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1c:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1d:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1e:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1f:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*20:[	 ]+89 c3[	 ]+mov[ 	]+%eax,%ebx[ 	]*
+#pass
diff --git a/gas/testsuite/gas/i386/nops-3.s b/gas/testsuite/gas/i386/nops-3.s
new file mode 100644
index 000000000000..c42b354788b9
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops-3.s
@@ -0,0 +1,6 @@
+	.text
+nop:
+	nop
+	.p2align 5
+	mov %eax,%ebx
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/nops.d b/gas/testsuite/gas/i386/nops.d
new file mode 100644
index 000000000000..dc01585a69d9
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops.d
@@ -0,0 +1,24 @@
+#objdump: -drw
+#name: i386 nops
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%eax\)
+[	 ]*3:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%eax\)
+[	 ]*7:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*c:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*12:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax\)
+[	 ]*19:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*21:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%eax,%eax,1\)
+[	 ]*2a:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%eax,%eax,1\)
+[	 ]*34:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%eax\)
+[	 ]*37:[	 ]+0f 1f c0[	 ]+nop[ 	]+%eax
+[	 ]*3a:[	 ]+66 0f 1f c0[	 ]+nop[ 	]+%ax
+[	 ]*3e:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%eax\)
+[	 ]*41:[	 ]+66 0f 1f 00[	 ]+nopw[ 	]+\(%eax\)
+[	 ]*45:[	 ]+0f 1f c0[	 ]+nop[ 	]+%eax
+[	 ]*48:[	 ]+66 0f 1f c0[	 ]+nop[ 	]+%ax
+#pass
diff --git a/gas/testsuite/gas/i386/nops.s b/gas/testsuite/gas/i386/nops.s
new file mode 100644
index 000000000000..9dddb42b9ea1
--- /dev/null
+++ b/gas/testsuite/gas/i386/nops.s
@@ -0,0 +1,20 @@
+	.text
+
+	.byte 0x0f, 0x1f, 0x0	
+	.byte 0x0f, 0x1f, 0x40, 0x0	
+	.byte 0x0f, 0x1f, 0x44, 0x0,  0x0	
+	.byte 0x66, 0x0f, 0x1f, 0x44, 0x0,  0x0	
+	.byte 0x0f, 0x1f, 0x80, 0x0,  0x0,  0x0, 0x0	
+	.byte 0x0f, 0x1f, 0x84, 0x0,  0x0,  0x0, 0x0, 0x0
+	.byte 0x66, 0x0f, 0x1f, 0x84, 0x0,  0x0, 0x0, 0x0, 0x0
+	.byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
+
+	nop (%eax) 
+	nop %eax
+	nop %ax
+	nopl (%eax) 
+	nopw (%eax) 
+	nopl %eax
+	nopw %ax
+
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
new file mode 100644
index 000000000000..2b728e113277
--- /dev/null
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -0,0 +1,615 @@
+#source: opcode.s
+#as: -J
+#objdump: -dwMintel
+#name: i386 opcodes (Intel disassembly)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+ *[0-9a-f]+:	00 90 90 90 90 90[ 	]+add[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	01 90 90 90 90 90[ 	]+add[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	02 90 90 90 90 90[ 	]+add[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	03 90 90 90 90 90[ 	]+add[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	04 90[ 	]+add[ 	]+al,0x90
+ *[0-9a-f]+:	05 90 90 90 90[ 	]+add[ 	]+eax,0x90909090
+ *[0-9a-f]+:	06[ 	]+push[ 	]+es
+ *[0-9a-f]+:	07[ 	]+pop[ 	]+es
+ *[0-9a-f]+:	08 90 90 90 90 90[ 	]+or[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	09 90 90 90 90 90[ 	]+or[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0a 90 90 90 90 90[ 	]+or[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0b 90 90 90 90 90[ 	]+or[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0c 90[ 	]+or[ 	]+al,0x90
+ *[0-9a-f]+:	0d 90 90 90 90[ 	]+or[ 	]+eax,0x90909090
+ *[0-9a-f]+:	0e[ 	]+push[ 	]+cs
+ *[0-9a-f]+:	10 90 90 90 90 90[ 	]+adc[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	11 90 90 90 90 90[ 	]+adc[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	12 90 90 90 90 90[ 	]+adc[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	13 90 90 90 90 90[ 	]+adc[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	14 90[ 	]+adc[ 	]+al,0x90
+ *[0-9a-f]+:	15 90 90 90 90[ 	]+adc[ 	]+eax,0x90909090
+ *[0-9a-f]+:	16[ 	]+push[ 	]+ss
+ *[0-9a-f]+:	17[ 	]+pop[ 	]+ss
+ *[0-9a-f]+:	18 90 90 90 90 90[ 	]+sbb[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	19 90 90 90 90 90[ 	]+sbb[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	1a 90 90 90 90 90[ 	]+sbb[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	1b 90 90 90 90 90[ 	]+sbb[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	1c 90[ 	]+sbb[ 	]+al,0x90
+ *[0-9a-f]+:	1d 90 90 90 90[ 	]+sbb[ 	]+eax,0x90909090
+ *[0-9a-f]+:	1e[ 	]+push[ 	]+ds
+ *[0-9a-f]+:	1f[ 	]+pop[ 	]+ds
+ *[0-9a-f]+:	20 90 90 90 90 90[ 	]+and[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	21 90 90 90 90 90[ 	]+and[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	22 90 90 90 90 90[ 	]+and[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	23 90 90 90 90 90[ 	]+and[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	24 90[ 	]+and[ 	]+al,0x90
+ *[0-9a-f]+:	25 90 90 90 90[ 	]+and[ 	]+eax,0x90909090
+ *[0-9a-f]+:	27[ 	]+daa[ 	]*
+ *[0-9a-f]+:	28 90 90 90 90 90[ 	]+sub[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	29 90 90 90 90 90[ 	]+sub[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	2a 90 90 90 90 90[ 	]+sub[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	2b 90 90 90 90 90[ 	]+sub[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	2c 90[ 	]+sub[ 	]+al,0x90
+ *[0-9a-f]+:	2d 90 90 90 90[ 	]+sub[ 	]+eax,0x90909090
+ *[0-9a-f]+:	2f[ 	]+das[ 	]*
+ *[0-9a-f]+:	30 90 90 90 90 90[ 	]+xor[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	31 90 90 90 90 90[ 	]+xor[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	32 90 90 90 90 90[ 	]+xor[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	33 90 90 90 90 90[ 	]+xor[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	34 90[ 	]+xor[ 	]+al,0x90
+ *[0-9a-f]+:	35 90 90 90 90[ 	]+xor[ 	]+eax,0x90909090
+ *[0-9a-f]+:	37[ 	]+aaa[ 	]*
+ *[0-9a-f]+:	38 90 90 90 90 90[ 	]+cmp[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	39 90 90 90 90 90[ 	]+cmp[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	3a 90 90 90 90 90[ 	]+cmp[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	3b 90 90 90 90 90[ 	]+cmp[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	3c 90[ 	]+cmp[ 	]+al,0x90
+ *[0-9a-f]+:	3d 90 90 90 90[ 	]+cmp[ 	]+eax,0x90909090
+ *[0-9a-f]+:	3f[ 	]+aas[ 	]*
+ *[0-9a-f]+:	40[ 	]+inc[ 	]+eax
+ *[0-9a-f]+:	41[ 	]+inc[ 	]+ecx
+ *[0-9a-f]+:	42[ 	]+inc[ 	]+edx
+ *[0-9a-f]+:	43[ 	]+inc[ 	]+ebx
+ *[0-9a-f]+:	44[ 	]+inc[ 	]+esp
+ *[0-9a-f]+:	45[ 	]+inc[ 	]+ebp
+ *[0-9a-f]+:	46[ 	]+inc[ 	]+esi
+ *[0-9a-f]+:	47[ 	]+inc[ 	]+edi
+ *[0-9a-f]+:	48[ 	]+dec[ 	]+eax
+ *[0-9a-f]+:	49[ 	]+dec[ 	]+ecx
+ *[0-9a-f]+:	4a[ 	]+dec[ 	]+edx
+ *[0-9a-f]+:	4b[ 	]+dec[ 	]+ebx
+ *[0-9a-f]+:	4c[ 	]+dec[ 	]+esp
+ *[0-9a-f]+:	4d[ 	]+dec[ 	]+ebp
+ *[0-9a-f]+:	4e[ 	]+dec[ 	]+esi
+ *[0-9a-f]+:	4f[ 	]+dec[ 	]+edi
+ *[0-9a-f]+:	50[ 	]+push[ 	]+eax
+ *[0-9a-f]+:	51[ 	]+push[ 	]+ecx
+ *[0-9a-f]+:	52[ 	]+push[ 	]+edx
+ *[0-9a-f]+:	53[ 	]+push[ 	]+ebx
+ *[0-9a-f]+:	54[ 	]+push[ 	]+esp
+ *[0-9a-f]+:	55[ 	]+push[ 	]+ebp
+ *[0-9a-f]+:	56[ 	]+push[ 	]+esi
+ *[0-9a-f]+:	57[ 	]+push[ 	]+edi
+ *[0-9a-f]+:	58[ 	]+pop[ 	]+eax
+ *[0-9a-f]+:	59[ 	]+pop[ 	]+ecx
+ *[0-9a-f]+:	5a[ 	]+pop[ 	]+edx
+ *[0-9a-f]+:	5b[ 	]+pop[ 	]+ebx
+ *[0-9a-f]+:	5c[ 	]+pop[ 	]+esp
+ *[0-9a-f]+:	5d[ 	]+pop[ 	]+ebp
+ *[0-9a-f]+:	5e[ 	]+pop[ 	]+esi
+ *[0-9a-f]+:	5f[ 	]+pop[ 	]+edi
+ *[0-9a-f]+:	60[ 	]+pusha[ 	]*
+ *[0-9a-f]+:	61[ 	]+popa[ 	]*
+ *[0-9a-f]+:	62 90 90 90 90 90[ 	]+bound[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	63 90 90 90 90 90[ 	]+arpl[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	68 90 90 90 90[ 	]+push[ 	]+0x90909090
+ *[0-9a-f]+:	69 90 90 90 90 90 90 90 90 90[ 	]+imul[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0x90909090
+ *[0-9a-f]+:	6a 90[ 	]+push[ 	]+0xffffff90
+ *[0-9a-f]+:	6b 90 90 90 90 90 90[ 	]+imul[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0xffffff90
+ *[0-9a-f]+:	6c[ 	]+ins[ 	]+BYTE PTR es:\[edi\],dx
+ *[0-9a-f]+:	6d[ 	]+ins[ 	]+DWORD PTR es:\[edi\],dx
+ *[0-9a-f]+:	6e[ 	]+outs[ 	]+dx,BYTE PTR ds:\[esi\]
+ *[0-9a-f]+:	6f[ 	]+outs[ 	]+dx,DWORD PTR ds:\[esi\]
+ *[0-9a-f]+:	70 90[ 	]+jo[ 	]+(0x)?df.*
+ *[0-9a-f]+:	71 90[ 	]+jno[ 	]+(0x)?e1.*
+ *[0-9a-f]+:	72 90[ 	]+jb[ 	]+(0x)?e3.*
+ *[0-9a-f]+:	73 90[ 	]+jae[ 	]+(0x)?e5.*
+ *[0-9a-f]+:	74 90[ 	]+je[ 	]+(0x)?e7.*
+ *[0-9a-f]+:	75 90[ 	]+jne[ 	]+(0x)?e9.*
+ *[0-9a-f]+:	76 90[ 	]+jbe[ 	]+(0x)?eb.*
+ *[0-9a-f]+:	77 90[ 	]+ja[ 	]+(0x)?ed.*
+ *[0-9a-f]+:	78 90[ 	]+js[ 	]+(0x)?ef.*
+ *[0-9a-f]+:	79 90[ 	]+jns[ 	]+(0x)?f1.*
+ *[0-9a-f]+:	7a 90[ 	]+jp[ 	]+(0x)?f3.*
+ *[0-9a-f]+:	7b 90[ 	]+jnp[ 	]+(0x)?f5.*
+ *[0-9a-f]+:	7c 90[ 	]+jl[ 	]+(0x)?f7.*
+ *[0-9a-f]+:	7d 90[ 	]+jge[ 	]+(0x)?f9.*
+ *[0-9a-f]+:	7e 90[ 	]+jle[ 	]+(0x)?fb.*
+ *[0-9a-f]+:	7f 90[ 	]+jg[ 	]+(0x)?fd.*
+ *[0-9a-f]+:	80 90 90 90 90 90 90[ 	]+adc[ 	]+BYTE PTR \[eax-0x6f6f6f70\],0x90
+ *[0-9a-f]+:	81 90 90 90 90 90 90 90 90 90[ 	]+adc[ 	]+DWORD PTR \[eax-0x6f6f6f70\],0x90909090
+ *[0-9a-f]+:	83 90 90 90 90 90 90[ 	]+adc[ 	]+DWORD PTR \[eax-0x6f6f6f70\],0xffffff90
+ *[0-9a-f]+:	84 90 90 90 90 90[ 	]+test[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	85 90 90 90 90 90[ 	]+test[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	86 90 90 90 90 90[ 	]+xchg[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	87 90 90 90 90 90[ 	]+xchg[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	88 90 90 90 90 90[ 	]+mov[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	89 90 90 90 90 90[ 	]+mov[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	8a 90 90 90 90 90[ 	]+mov[ 	]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	8b 90 90 90 90 90[ 	]+mov[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	8c 90 90 90 90 90[ 	]+mov[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],ss
+ *[0-9a-f]+:	8d 90 90 90 90 90[ 	]+lea[ 	]+edx,\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	8e 90 90 90 90 90[ 	]+mov[ 	]+ss,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	8f 80 90 90 90 90[ 	]+pop[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	90[ 	]+nop[ 	]*
+ *[0-9a-f]+:	91[ 	]+xchg[ 	]+ecx,eax
+ *[0-9a-f]+:	92[ 	]+xchg[ 	]+edx,eax
+ *[0-9a-f]+:	93[ 	]+xchg[ 	]+ebx,eax
+ *[0-9a-f]+:	94[ 	]+xchg[ 	]+esp,eax
+ *[0-9a-f]+:	95[ 	]+xchg[ 	]+ebp,eax
+ *[0-9a-f]+:	96[ 	]+xchg[ 	]+esi,eax
+ *[0-9a-f]+:	97[ 	]+xchg[ 	]+edi,eax
+ *[0-9a-f]+:	98[ 	]+cwde[ 	]*
+ *[0-9a-f]+:	99[ 	]+cdq[ 	]*
+ *[0-9a-f]+:	9a 90 90 90 90 90 90[ 	]+call[ 	]+0x9090:0x90909090
+ *[0-9a-f]+:	9b[ 	]+fwait
+ *[0-9a-f]+:	9c[ 	]+pushf[ 	]*
+ *[0-9a-f]+:	9d[ 	]+popf[ 	]*
+ *[0-9a-f]+:	9e[ 	]+sahf[ 	]*
+ *[0-9a-f]+:	9f[ 	]+lahf[ 	]*
+ *[0-9a-f]+:	a0 90 90 90 90[ 	]+mov[ 	]+al,ds:0x90909090
+ *[0-9a-f]+:	a1 90 90 90 90[ 	]+mov[ 	]+eax,ds:0x90909090
+ *[0-9a-f]+:	a2 90 90 90 90[ 	]+mov[ 	]+ds:0x90909090,al
+ *[0-9a-f]+:	a3 90 90 90 90[ 	]+mov[ 	]+ds:0x90909090,eax
+ *[0-9a-f]+:	a4[ 	]+movs[ 	]+BYTE PTR es:\[edi\],(BYTE PTR )?ds:\[esi\]
+ *[0-9a-f]+:	a5[ 	]+movs[ 	]+DWORD PTR es:\[edi\],(DWORD PTR )?ds:\[esi\]
+ *[0-9a-f]+:	a6[ 	]+cmps[ 	]+BYTE PTR ds:\[esi\],(BYTE PTR )?es:\[edi\]
+ *[0-9a-f]+:	a7[ 	]+cmps[ 	]+DWORD PTR ds:\[esi\],(DWORD PTR )?es:\[edi\]
+ *[0-9a-f]+:	a8 90[ 	]+test[ 	]+al,0x90
+ *[0-9a-f]+:	a9 90 90 90 90[ 	]+test[ 	]+eax,0x90909090
+ *[0-9a-f]+:	aa[ 	]+stos[ 	]+BYTE PTR es:\[edi\](,al)?
+ *[0-9a-f]+:	ab[ 	]+stos[ 	]+DWORD PTR es:\[edi\](,eax)?
+ *[0-9a-f]+:	ac[ 	]+lods[ 	]+(al,)?BYTE PTR ds:\[esi\]
+ *[0-9a-f]+:	ad[ 	]+lods[ 	]+(eax,)?DWORD PTR ds:\[esi\]
+ *[0-9a-f]+:	ae[ 	]+scas[ 	]+(al,)?BYTE PTR es:\[edi\]
+ *[0-9a-f]+:	af[ 	]+scas[ 	]+(eax,)?DWORD PTR es:\[edi\]
+ *[0-9a-f]+:	b0 90[ 	]+mov[ 	]+al,0x90
+ *[0-9a-f]+:	b1 90[ 	]+mov[ 	]+cl,0x90
+ *[0-9a-f]+:	b2 90[ 	]+mov[ 	]+dl,0x90
+ *[0-9a-f]+:	b3 90[ 	]+mov[ 	]+bl,0x90
+ *[0-9a-f]+:	b4 90[ 	]+mov[ 	]+ah,0x90
+ *[0-9a-f]+:	b5 90[ 	]+mov[ 	]+ch,0x90
+ *[0-9a-f]+:	b6 90[ 	]+mov[ 	]+dh,0x90
+ *[0-9a-f]+:	b7 90[ 	]+mov[ 	]+bh,0x90
+ *[0-9a-f]+:	b8 90 90 90 90[ 	]+mov[ 	]+eax,0x90909090
+ *[0-9a-f]+:	b9 90 90 90 90[ 	]+mov[ 	]+ecx,0x90909090
+ *[0-9a-f]+:	ba 90 90 90 90[ 	]+mov[ 	]+edx,0x90909090
+ *[0-9a-f]+:	bb 90 90 90 90[ 	]+mov[ 	]+ebx,0x90909090
+ *[0-9a-f]+:	bc 90 90 90 90[ 	]+mov[ 	]+esp,0x90909090
+ *[0-9a-f]+:	bd 90 90 90 90[ 	]+mov[ 	]+ebp,0x90909090
+ *[0-9a-f]+:	be 90 90 90 90[ 	]+mov[ 	]+esi,0x90909090
+ *[0-9a-f]+:	bf 90 90 90 90[ 	]+mov[ 	]+edi,0x90909090
+ *[0-9a-f]+:	c0 90 90 90 90 90 90[ 	]+rcl[ 	]+BYTE PTR \[eax-0x6f6f6f70\],0x90
+ *[0-9a-f]+:	c1 90 90 90 90 90 90[ 	]+rcl[ 	]+DWORD PTR \[eax-0x6f6f6f70\],0x90
+ *[0-9a-f]+:	c2 90 90[ 	]+ret[ 	]+0x9090
+ *[0-9a-f]+:	c3[ 	]+ret[ 	]*
+ *[0-9a-f]+:	c4 90 90 90 90 90[ 	]+les[ 	]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	c5 90 90 90 90 90[ 	]+lds[ 	]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	c6 80 90 90 90 90 90[ 	]+mov[ 	]+BYTE PTR \[eax-0x6f6f6f70\],0x90
+ *[0-9a-f]+:	c7 80 90 90 90 90 90 90 90 90[ 	]+mov[ 	]+DWORD PTR \[eax-0x6f6f6f70\],0x90909090
+ *[0-9a-f]+:	c8 90 90 90[ 	]+enter[ 	]+0x9090,0x90
+ *[0-9a-f]+:	c9[ 	]+leave[ 	]*
+ *[0-9a-f]+:	ca 90 90[ 	]+lret[ 	]+0x9090
+ *[0-9a-f]+:	cb[ 	]+lret[ 	]*
+ *[0-9a-f]+:	cc[ 	]+int3[ 	]*
+ *[0-9a-f]+:	cd 90[ 	]+int[ 	]+0x90
+ *[0-9a-f]+:	ce[ 	]+into[ 	]*
+ *[0-9a-f]+:	cf[ 	]+iret[ 	]*
+ *[0-9a-f]+:	d0 90 90 90 90 90[ 	]+rcl[ 	]+BYTE PTR \[eax-0x6f6f6f70\],1
+ *[0-9a-f]+:	d1 90 90 90 90 90[ 	]+rcl[ 	]+DWORD PTR \[eax-0x6f6f6f70\],1
+ *[0-9a-f]+:	d2 90 90 90 90 90[ 	]+rcl[ 	]+BYTE PTR \[eax-0x6f6f6f70\],cl
+ *[0-9a-f]+:	d3 90 90 90 90 90[ 	]+rcl[ 	]+DWORD PTR \[eax-0x6f6f6f70\],cl
+ *[0-9a-f]+:	d4 90[ 	]+aam[ 	]+0xffffff90
+ *[0-9a-f]+:	d5 90[ 	]+aad[ 	]+0xffffff90
+ *[0-9a-f]+:	d7[ 	]+xlat[ 	]+(BYTE PTR )?(ds:)?\[ebx\]
+ *[0-9a-f]+:	d8 90 90 90 90 90[ 	]+fcom[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	d9 90 90 90 90 90[ 	]+fst[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	da 90 90 90 90 90[ 	]+ficom[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	db 90 90 90 90 90[ 	]+fist[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	dc 90 90 90 90 90[ 	]+fcom[ 	]+QWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	dd 90 90 90 90 90[ 	]+fst[ 	]+QWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	de 90 90 90 90 90[ 	]+ficom[ 	]+WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	df 90 90 90 90 90[ 	]+fist[ 	]+WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	e0 90[ 	]+loopne[ 	]+(0x)?25c.*
+ *[0-9a-f]+:	e1 90[ 	]+loope[ 	]+(0x)?25e.*
+ *[0-9a-f]+:	e2 90[ 	]+loop[ 	]+(0x)?260.*
+ *[0-9a-f]+:	e3 90[ 	]+jecxz[ 	]+(0x)?262.*
+ *[0-9a-f]+:	e4 90[ 	]+in[ 	]+al,0x90
+ *[0-9a-f]+:	e5 90[ 	]+in[ 	]+eax,0x90
+ *[0-9a-f]+:	e6 90[ 	]+out[ 	]+0x90,al
+ *[0-9a-f]+:	e7 90[ 	]+out[ 	]+0x90,eax
+ *[0-9a-f]+:	e8 90 90 90 90[ 	]+call[ 	]+(0x)?9090936f.*
+ *[0-9a-f]+:	e9 90 90 90 90[ 	]+jmp[ 	]+(0x)?90909374.*
+ *[0-9a-f]+:	ea 90 90 90 90 90 90[ 	]+jmp[ 	]+0x9090:0x90909090
+ *[0-9a-f]+:	eb 90[ 	]+jmp[ 	]+(0x)?27d.*
+ *[0-9a-f]+:	ec[ 	]+in[ 	]+al,dx
+ *[0-9a-f]+:	ed[ 	]+in[ 	]+eax,dx
+ *[0-9a-f]+:	ee[ 	]+out[ 	]+dx,al
+ *[0-9a-f]+:	ef[ 	]+out[ 	]+dx,eax
+ *[0-9a-f]+:	f4[ 	]+hlt[ 	]*
+ *[0-9a-f]+:	f5[ 	]+cmc[ 	]*
+ *[0-9a-f]+:	f6 90 90 90 90 90[ 	]+not[ 	]+BYTE PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	f7 90 90 90 90 90[ 	]+not[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	f8[ 	]+clc[ 	]*
+ *[0-9a-f]+:	f9[ 	]+stc[ 	]*
+ *[0-9a-f]+:	fa[ 	]+cli[ 	]*
+ *[0-9a-f]+:	fb[ 	]+sti[ 	]*
+ *[0-9a-f]+:	fc[ 	]+cld[ 	]*
+ *[0-9a-f]+:	fd[ 	]+std[ 	]*
+ *[0-9a-f]+:	ff 90 90 90 90 90[ 	]+call[ 	]+DWORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 00 90 90 90 90 90[ 	]+lldt[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 01 90 90 90 90 90[ 	]+lgdtd[ 	]+\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 02 90 90 90 90 90[ 	]+lar[ 	]+edx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 03 90 90 90 90 90[ 	]+lsl[ 	]+edx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 06[ 	]+clts[ 	]*
+ *[0-9a-f]+:	0f 08[ 	]+invd[ 	]*
+ *[0-9a-f]+:	0f 09[ 	]+wbinvd[ 	]*
+ *[0-9a-f]+:	0f 0b[ 	]+ud2a[ 	]*
+ *[0-9a-f]+:	0f 20 d0[ 	]+mov[ 	]+eax,cr2
+ *[0-9a-f]+:	0f 21 d0[ 	]+mov[ 	]+eax,db2
+ *[0-9a-f]+:	0f 22 d0[ 	]+mov[ 	]+cr2,eax
+ *[0-9a-f]+:	0f 23 d0[ 	]+mov[ 	]+db2,eax
+ *[0-9a-f]+:	0f 24 d0[ 	]+mov[ 	]+eax,tr2
+ *[0-9a-f]+:	0f 26 d0[ 	]+mov[ 	]+tr2,eax
+ *[0-9a-f]+:	0f 30[ 	]+wrmsr[ 	]*
+ *[0-9a-f]+:	0f 31[ 	]+rdtsc[ 	]*
+ *[0-9a-f]+:	0f 32[ 	]+rdmsr[ 	]*
+ *[0-9a-f]+:	0f 33[ 	]+rdpmc[ 	]*
+ *[0-9a-f]+:	0f 40 90 90 90 90 90[ 	]+cmovo[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 41 90 90 90 90 90[ 	]+cmovno[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 42 90 90 90 90 90[ 	]+cmovb[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 43 90 90 90 90 90[ 	]+cmovae[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 44 90 90 90 90 90[ 	]+cmove[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 45 90 90 90 90 90[ 	]+cmovne[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 46 90 90 90 90 90[ 	]+cmovbe[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 47 90 90 90 90 90[ 	]+cmova[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 48 90 90 90 90 90[ 	]+cmovs[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 49 90 90 90 90 90[ 	]+cmovns[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4a 90 90 90 90 90[ 	]+cmovp[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4b 90 90 90 90 90[ 	]+cmovnp[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4c 90 90 90 90 90[ 	]+cmovl[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4d 90 90 90 90 90[ 	]+cmovge[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4e 90 90 90 90 90[ 	]+cmovle[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 4f 90 90 90 90 90[ 	]+cmovg[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 60 90 90 90 90 90[ 	]+punpcklbw[ 	]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 61 90 90 90 90 90[ 	]+punpcklwd[ 	]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 62 90 90 90 90 90[ 	]+punpckldq[ 	]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 63 90 90 90 90 90[ 	]+packsswb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 64 90 90 90 90 90[ 	]+pcmpgtb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 65 90 90 90 90 90[ 	]+pcmpgtw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 66 90 90 90 90 90[ 	]+pcmpgtd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 67 90 90 90 90 90[ 	]+packuswb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 68 90 90 90 90 90[ 	]+punpckhbw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 69 90 90 90 90 90[ 	]+punpckhwd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 6a 90 90 90 90 90[ 	]+punpckhdq[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 6b 90 90 90 90 90[ 	]+packssdw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 6e 90 90 90 90 90[ 	]+movd[ 	]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 6f 90 90 90 90 90[ 	]+movq[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 71 d0 90[ 	]+psrlw[ 	]+mm0,0x90
+ *[0-9a-f]+:	0f 72 d0 90[ 	]+psrld[ 	]+mm0,0x90
+ *[0-9a-f]+:	0f 73 d0 90[ 	]+psrlq[ 	]+mm0,0x90
+ *[0-9a-f]+:	0f 74 90 90 90 90 90[ 	]+pcmpeqb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 75 90 90 90 90 90[ 	]+pcmpeqw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 76 90 90 90 90 90[ 	]+pcmpeqd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 77[ 	]+emms[ 	]*
+ *[0-9a-f]+:	0f 7e 90 90 90 90 90[ 	]+movd[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],mm2
+ *[0-9a-f]+:	0f 7f 90 90 90 90 90[ 	]+movq[ 	]+(QWORD PTR )?\[eax-0x6f6f6f70\],mm2
+ *[0-9a-f]+:	0f 80 90 90 90 90[ 	]+jo[ 	]+909094e2 <foo\+0x909094e2>
+ *[0-9a-f]+:	0f 81 90 90 90 90[ 	]+jno[ 	]+909094e8 <foo\+0x909094e8>
+ *[0-9a-f]+:	0f 82 90 90 90 90[ 	]+jb[ 	]+909094ee <foo\+0x909094ee>
+ *[0-9a-f]+:	0f 83 90 90 90 90[ 	]+jae[ 	]+909094f4 <foo\+0x909094f4>
+ *[0-9a-f]+:	0f 84 90 90 90 90[ 	]+je[ 	]+909094fa <foo\+0x909094fa>
+ *[0-9a-f]+:	0f 85 90 90 90 90[ 	]+jne[ 	]+90909500 <foo\+0x90909500>
+ *[0-9a-f]+:	0f 86 90 90 90 90[ 	]+jbe[ 	]+90909506 <foo\+0x90909506>
+ *[0-9a-f]+:	0f 87 90 90 90 90[ 	]+ja[ 	]+9090950c <foo\+0x9090950c>
+ *[0-9a-f]+:	0f 88 90 90 90 90[ 	]+js[ 	]+90909512 <foo\+0x90909512>
+ *[0-9a-f]+:	0f 89 90 90 90 90[ 	]+jns[ 	]+90909518 <foo\+0x90909518>
+ *[0-9a-f]+:	0f 8a 90 90 90 90[ 	]+jp[ 	]+9090951e <foo\+0x9090951e>
+ *[0-9a-f]+:	0f 8b 90 90 90 90[ 	]+jnp[ 	]+90909524 <foo\+0x90909524>
+ *[0-9a-f]+:	0f 8c 90 90 90 90[ 	]+jl[ 	]+9090952a <foo\+0x9090952a>
+ *[0-9a-f]+:	0f 8d 90 90 90 90[ 	]+jge[ 	]+90909530 <foo\+0x90909530>
+ *[0-9a-f]+:	0f 8e 90 90 90 90[ 	]+jle[ 	]+90909536 <foo\+0x90909536>
+ *[0-9a-f]+:	0f 8f 90 90 90 90[ 	]+jg[ 	]+9090953c <foo\+0x9090953c>
+ *[0-9a-f]+:	0f 90 80 90 90 90 90[ 	]+seto[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 91 80 90 90 90 90[ 	]+setno[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 92 80 90 90 90 90[ 	]+setb[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 93 80 90 90 90 90[ 	]+setae[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 94 80 90 90 90 90[ 	]+sete[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 95 80 90 90 90 90[ 	]+setne[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 96 80 90 90 90 90[ 	]+setbe[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 97 80 90 90 90 90[ 	]+seta[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 98 80 90 90 90 90[ 	]+sets[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 99 80 90 90 90 90[ 	]+setns[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9a 80 90 90 90 90[ 	]+setp[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9b 80 90 90 90 90[ 	]+setnp[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9c 80 90 90 90 90[ 	]+setl[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9d 80 90 90 90 90[ 	]+setge[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9e 80 90 90 90 90[ 	]+setle[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f 9f 80 90 90 90 90[ 	]+setg[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f a0[ 	]+push[ 	]+fs
+ *[0-9a-f]+:	0f a1[ 	]+pop[ 	]+fs
+ *[0-9a-f]+:	0f a2[ 	]+cpuid[ 	]*
+ *[0-9a-f]+:	0f a3 90 90 90 90 90[ 	]+bt[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f a4 90 90 90 90 90 90[ 	]+shld[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,0x90
+ *[0-9a-f]+:	0f a5 90 90 90 90 90[ 	]+shld[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,cl
+ *[0-9a-f]+:	0f a8[ 	]+push[ 	]+gs
+ *[0-9a-f]+:	0f a9[ 	]+pop[ 	]+gs
+ *[0-9a-f]+:	0f aa[ 	]+rsm[ 	]*
+ *[0-9a-f]+:	0f ab 90 90 90 90 90[ 	]+bts[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f ac 90 90 90 90 90 90[ 	]+shrd[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,0x90
+ *[0-9a-f]+:	0f ad 90 90 90 90 90[ 	]+shrd[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,cl
+ *[0-9a-f]+:	0f af 90 90 90 90 90[ 	]+imul[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b0 90 90 90 90 90[ 	]+cmpxchg (BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	0f b1 90 90 90 90 90[ 	]+cmpxchg (DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f b2 90 90 90 90 90[ 	]+lss[ 	]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b3 90 90 90 90 90[ 	]+btr[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f b4 90 90 90 90 90[ 	]+lfs[ 	]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b5 90 90 90 90 90[ 	]+lgs[ 	]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b6 90 90 90 90 90[ 	]+movzx[ 	]+edx,BYTE PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b7 90 90 90 90 90[ 	]+movzx[ 	]+edx,WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f b9[ 	]+ud2b[ 	]*
+ *[0-9a-f]+:	0f bb 90 90 90 90 90[ 	]+btc[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f bc 90 90 90 90 90[ 	]+bsf[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f bd 90 90 90 90 90[ 	]+bsr[ 	]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f be 90 90 90 90 90[ 	]+movsx[ 	]+edx,BYTE PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f bf 90 90 90 90 90[ 	]+movsx[ 	]+edx,WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f c0 90 90 90 90 90[ 	]+xadd[ 	]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl
+ *[0-9a-f]+:	0f c1 90 90 90 90 90[ 	]+xadd[ 	]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
+ *[0-9a-f]+:	0f c8[ 	]+bswap[ 	]+eax
+ *[0-9a-f]+:	0f c9[ 	]+bswap[ 	]+ecx
+ *[0-9a-f]+:	0f ca[ 	]+bswap[ 	]+edx
+ *[0-9a-f]+:	0f cb[ 	]+bswap[ 	]+ebx
+ *[0-9a-f]+:	0f cc[ 	]+bswap[ 	]+esp
+ *[0-9a-f]+:	0f cd[ 	]+bswap[ 	]+ebp
+ *[0-9a-f]+:	0f ce[ 	]+bswap[ 	]+esi
+ *[0-9a-f]+:	0f cf[ 	]+bswap[ 	]+edi
+ *[0-9a-f]+:	0f d1 90 90 90 90 90[ 	]+psrlw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f d2 90 90 90 90 90[ 	]+psrld[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f d3 90 90 90 90 90[ 	]+psrlq[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f d5 90 90 90 90 90[ 	]+pmullw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f d8 90 90 90 90 90[ 	]+psubusb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f d9 90 90 90 90 90[ 	]+psubusw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f db 90 90 90 90 90[ 	]+pand[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f dc 90 90 90 90 90[ 	]+paddusb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f dd 90 90 90 90 90[ 	]+paddusw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f df 90 90 90 90 90[ 	]+pandn[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f e1 90 90 90 90 90[ 	]+psraw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f e2 90 90 90 90 90[ 	]+psrad[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f e5 90 90 90 90 90[ 	]+pmulhw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f e8 90 90 90 90 90[ 	]+psubsb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f e9 90 90 90 90 90[ 	]+psubsw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f eb 90 90 90 90 90[ 	]+por[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f ec 90 90 90 90 90[ 	]+paddsb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f ed 90 90 90 90 90[ 	]+paddsw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f ef 90 90 90 90 90[ 	]+pxor[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f1 90 90 90 90 90[ 	]+psllw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f2 90 90 90 90 90[ 	]+pslld[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f3 90 90 90 90 90[ 	]+psllq[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f5 90 90 90 90 90[ 	]+pmaddwd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f8 90 90 90 90 90[ 	]+psubb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f f9 90 90 90 90 90[ 	]+psubw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f fa 90 90 90 90 90[ 	]+psubd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f fc 90 90 90 90 90[ 	]+paddb[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f fd 90 90 90 90 90[ 	]+paddw[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	0f fe 90 90 90 90 90[ 	]+paddd[ 	]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 01 90 90 90 90 90[ 	]+add[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 03 90 90 90 90 90[ 	]+add[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 05 90 90[ 	]+add[ 	]+ax,0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	06[ 	]+push[ 	]+es
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	07[ 	]+pop[ 	]+es
+ *[0-9a-f]+:	66 09 90 90 90 90 90[ 	]+or[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0b 90 90 90 90 90[ 	]+or[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0d 90 90[ 	]+or[ 	]+ax,0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	0e[ 	]+push[ 	]+cs
+ *[0-9a-f]+:	66 11 90 90 90 90 90[ 	]+adc[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 13 90 90 90 90 90[ 	]+adc[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 15 90 90[ 	]+adc[ 	]+ax,0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	16[ 	]+push[ 	]+ss
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	17[ 	]+pop[ 	]+ss
+ *[0-9a-f]+:	66 19 90 90 90 90 90[ 	]+sbb[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 1b 90 90 90 90 90[ 	]+sbb[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 1d 90 90[ 	]+sbb[ 	]+ax,0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	1e[ 	]+push[ 	]+ds
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	1f[ 	]+pop[ 	]+ds
+ *[0-9a-f]+:	66 21 90 90 90 90 90[ 	]+and[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 23 90 90 90 90 90[ 	]+and[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 25 90 90[ 	]+and[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 29 90 90 90 90 90[ 	]+sub[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 2b 90 90 90 90 90[ 	]+sub[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 2d 90 90[ 	]+sub[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 31 90 90 90 90 90[ 	]+xor[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 33 90 90 90 90 90[ 	]+xor[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 35 90 90[ 	]+xor[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 39 90 90 90 90 90[ 	]+cmp[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 3b 90 90 90 90 90[ 	]+cmp[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 3d 90 90[ 	]+cmp[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 40[ 	]+inc[ 	]+ax
+ *[0-9a-f]+:	66 41[ 	]+inc[ 	]+cx
+ *[0-9a-f]+:	66 42[ 	]+inc[ 	]+dx
+ *[0-9a-f]+:	66 43[ 	]+inc[ 	]+bx
+ *[0-9a-f]+:	66 44[ 	]+inc[ 	]+sp
+ *[0-9a-f]+:	66 45[ 	]+inc[ 	]+bp
+ *[0-9a-f]+:	66 46[ 	]+inc[ 	]+si
+ *[0-9a-f]+:	66 47[ 	]+inc[ 	]+di
+ *[0-9a-f]+:	66 48[ 	]+dec[ 	]+ax
+ *[0-9a-f]+:	66 49[ 	]+dec[ 	]+cx
+ *[0-9a-f]+:	66 4a[ 	]+dec[ 	]+dx
+ *[0-9a-f]+:	66 4b[ 	]+dec[ 	]+bx
+ *[0-9a-f]+:	66 4c[ 	]+dec[ 	]+sp
+ *[0-9a-f]+:	66 4d[ 	]+dec[ 	]+bp
+ *[0-9a-f]+:	66 4e[ 	]+dec[ 	]+si
+ *[0-9a-f]+:	66 4f[ 	]+dec[ 	]+di
+ *[0-9a-f]+:	66 50[ 	]+push[ 	]+ax
+ *[0-9a-f]+:	66 51[ 	]+push[ 	]+cx
+ *[0-9a-f]+:	66 52[ 	]+push[ 	]+dx
+ *[0-9a-f]+:	66 53[ 	]+push[ 	]+bx
+ *[0-9a-f]+:	66 54[ 	]+push[ 	]+sp
+ *[0-9a-f]+:	66 55[ 	]+push[ 	]+bp
+ *[0-9a-f]+:	66 56[ 	]+push[ 	]+si
+ *[0-9a-f]+:	66 57[ 	]+push[ 	]+di
+ *[0-9a-f]+:	66 58[ 	]+pop[ 	]+ax
+ *[0-9a-f]+:	66 59[ 	]+pop[ 	]+cx
+ *[0-9a-f]+:	66 5a[ 	]+pop[ 	]+dx
+ *[0-9a-f]+:	66 5b[ 	]+pop[ 	]+bx
+ *[0-9a-f]+:	66 5c[ 	]+pop[ 	]+sp
+ *[0-9a-f]+:	66 5d[ 	]+pop[ 	]+bp
+ *[0-9a-f]+:	66 5e[ 	]+pop[ 	]+si
+ *[0-9a-f]+:	66 5f[ 	]+pop[ 	]+di
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	60[ 	]+pusha[ 	]*
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	61[ 	]+popa[ 	]*
+ *[0-9a-f]+:	66 62 90 90 90 90 90[ 	]+bound[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 68 90 90[ 	]+push[ 	]+0x9090
+ *[0-9a-f]+:	66 69 90 90 90 90 90 90 90[ 	]+imul[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\],0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	6a 90[ 	]+push[ 	]+0xffffff90
+ *[0-9a-f]+:	66 6b 90 90 90 90 90 90[ 	]+imul[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\],0xffffff90
+ *[0-9a-f]+:	66 6d[ 	]+ins[ 	]+WORD PTR es:\[edi\],dx
+ *[0-9a-f]+:	66 6f[ 	]+outs[ 	]+dx,WORD PTR ds:\[esi\]
+ *[0-9a-f]+:	66 81 90 90 90 90 90 90 90[ 	]+adc[ 	]+WORD PTR \[eax-0x6f6f6f70\],0x9090
+ *[0-9a-f]+:	66 83 90 90 90 90 90 90[ 	]+adc[ 	]+WORD PTR \[eax-0x6f6f6f70\],0xffffff90
+ *[0-9a-f]+:	66 85 90 90 90 90 90[ 	]+test[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 87 90 90 90 90 90[ 	]+xchg[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 89 90 90 90 90 90[ 	]+mov[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 8b 90 90 90 90 90[ 	]+mov[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	8c 90 90 90 90 90[ 	]+mov[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],ss
+ *[0-9a-f]+:	66 8d 90 90 90 90 90[ 	]+lea[ 	]+dx,\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 8f 80 90 90 90 90[ 	]+pop[ 	]+WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 91[ 	]+xchg[ 	]+cx,ax
+ *[0-9a-f]+:	66 92[ 	]+xchg[ 	]+dx,ax
+ *[0-9a-f]+:	66 93[ 	]+xchg[ 	]+bx,ax
+ *[0-9a-f]+:	66 94[ 	]+xchg[ 	]+sp,ax
+ *[0-9a-f]+:	66 95[ 	]+xchg[ 	]+bp,ax
+ *[0-9a-f]+:	66 96[ 	]+xchg[ 	]+si,ax
+ *[0-9a-f]+:	66 97[ 	]+xchg[ 	]+di,ax
+ *[0-9a-f]+:	66 98[ 	]+cbw[ 	]*
+ *[0-9a-f]+:	66 99[ 	]+cwd[ 	]*
+ *[0-9a-f]+:	66 9a 90 90 90 90[ 	]+call[ 	]+0x9090:0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	9c[ 	]+pushf[ 	]*
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	9d[ 	]+popf[ 	]*
+ *[0-9a-f]+:	66 a1 90 90 90 90[ 	]+mov[ 	]+ax,ds:0x90909090
+ *[0-9a-f]+:	66 a3 90 90 90 90[ 	]+mov[ 	]+ds:0x90909090,ax
+ *[0-9a-f]+:	66 a5[ 	]+movs[ 	]+WORD PTR es:\[edi\],(WORD PTR )?ds:\[esi\]
+ *[0-9a-f]+:	66 a7[ 	]+cmps[ 	]+WORD PTR ds:\[esi\],(WORD PTR )?es:\[edi\]
+ *[0-9a-f]+:	66 a9 90 90[ 	]+test[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 ab[ 	]+stos[ 	]+WORD PTR es:\[edi\](,ax)?
+ *[0-9a-f]+:	66 ad[ 	]+lods[ 	]+(ax,)?WORD PTR ds:\[esi\]
+ *[0-9a-f]+:	66 af[ 	]+scas[ 	]+(ax,)?WORD PTR es:\[edi\]
+ *[0-9a-f]+:	66 b8 90 90[ 	]+mov[ 	]+ax,0x9090
+ *[0-9a-f]+:	66 b9 90 90[ 	]+mov[ 	]+cx,0x9090
+ *[0-9a-f]+:	66 ba 90 90[ 	]+mov[ 	]+dx,0x9090
+ *[0-9a-f]+:	66 bb 90 90[ 	]+mov[ 	]+bx,0x9090
+ *[0-9a-f]+:	66 bc 90 90[ 	]+mov[ 	]+sp,0x9090
+ *[0-9a-f]+:	66 bd 90 90[ 	]+mov[ 	]+bp,0x9090
+ *[0-9a-f]+:	66 be 90 90[ 	]+mov[ 	]+si,0x9090
+ *[0-9a-f]+:	66 bf 90 90[ 	]+mov[ 	]+di,0x9090
+ *[0-9a-f]+:	66 c1 90 90 90 90 90 90[ 	]+rcl[ 	]+WORD PTR \[eax-0x6f6f6f70\],0x90
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	c2 90 90[ 	]+ret[ 	]+0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	c3[ 	]+ret[ 	]*
+ *[0-9a-f]+:	66 c4 90 90 90 90 90[ 	]+les[ 	]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 c5 90 90 90 90 90[ 	]+lds[ 	]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 c7 80 90 90 90 90 90 90[ 	]+mov[ 	]+WORD PTR \[eax-0x6f6f6f70\],0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	c8 90 90 90[ 	]+enter[ 	]+0x9090,0x90
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	c9[ 	]+leave[ 	]*
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	ca 90 90[ 	]+lret[ 	]+0x9090
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	cb[ 	]+lret[ 	]*
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	cf[ 	]+iret[ 	]*
+ *[0-9a-f]+:	66 d1 90 90 90 90 90[ 	]+rcl[ 	]+WORD PTR \[eax-0x6f6f6f70\],1
+ *[0-9a-f]+:	66 d3 90 90 90 90 90[ 	]+rcl[ 	]+WORD PTR \[eax-0x6f6f6f70\],cl
+ *[0-9a-f]+:	66 e5 90[ 	]+in[ 	]+ax,0x90
+ *[0-9a-f]+:	66 e7 90[ 	]+out[ 	]+0x90,ax
+ *[0-9a-f]+:	66 e8 8f 90[ 	]+call[ 	]+(0x)?9918.*
+ *[0-9a-f]+:	66 ea 90 90 90 90[ 	]+jmp[ 	]+0x9090:0x9090
+ *[0-9a-f]+:	66 ed[ 	]+in[ 	]+ax,dx
+ *[0-9a-f]+:	66 ef[ 	]+out[ 	]+dx,ax
+ *[0-9a-f]+:	66 f7 90 90 90 90 90[ 	]+not[ 	]+WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 ff 90 90 90 90 90[ 	]+call[ 	]+WORD PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 02 90 90 90 90 90[ 	]+lar[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 03 90 90 90 90 90[ 	]+lsl[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 40 90 90 90 90 90[ 	]+cmovo[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 41 90 90 90 90 90[ 	]+cmovno[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 42 90 90 90 90 90[ 	]+cmovb[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 43 90 90 90 90 90[ 	]+cmovae[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 44 90 90 90 90 90[ 	]+cmove[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 45 90 90 90 90 90[ 	]+cmovne[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 46 90 90 90 90 90[ 	]+cmovbe[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 47 90 90 90 90 90[ 	]+cmova[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 48 90 90 90 90 90[ 	]+cmovs[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 49 90 90 90 90 90[ 	]+cmovns[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4a 90 90 90 90 90[ 	]+cmovp[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4b 90 90 90 90 90[ 	]+cmovnp[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4c 90 90 90 90 90[ 	]+cmovl[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4d 90 90 90 90 90[ 	]+cmovge[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4e 90 90 90 90 90[ 	]+cmovle[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f 4f 90 90 90 90 90[ 	]+cmovg[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	0f a0[ 	]+push[ 	]+fs
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	0f a1[ 	]+pop[ 	]+fs
+ *[0-9a-f]+:	66 0f a3 90 90 90 90 90[ 	]+bt[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0f a4 90 90 90 90 90 90[ 	]+shld[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,0x90
+ *[0-9a-f]+:	66 0f a5 90 90 90 90 90[ 	]+shld[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,cl
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	0f a8[ 	]+push[ 	]+gs
+ *[0-9a-f]+:	66[ 	]+data16
+ *[0-9a-f]+:	0f a9[ 	]+pop[ 	]+gs
+ *[0-9a-f]+:	66 0f ab 90 90 90 90 90[ 	]+bts[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0f ac 90 90 90 90 90 90[ 	]+shrd[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,0x90
+ *[0-9a-f]+:	66 0f ad 90 90 90 90 90[ 	]+shrd[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,cl
+ *[0-9a-f]+:	66 0f af 90 90 90 90 90[ 	]+imul[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f b1 90 90 90 90 90[ 	]+cmpxchg (WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0f b2 90 90 90 90 90[ 	]+lss[ 	]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f b3 90 90 90 90 90[ 	]+btr[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0f b4 90 90 90 90 90[ 	]+lfs[ 	]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f b5 90 90 90 90 90[ 	]+lgs[ 	]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f b6 90 90 90 90 90[ 	]+movzx[ 	]+dx,BYTE PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f bb 90 90 90 90 90[ 	]+btc[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 0f bc 90 90 90 90 90[ 	]+bsf[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f bd 90 90 90 90 90[ 	]+bsr[ 	]+dx,(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f be 90 90 90 90 90[ 	]+movsx[ 	]+dx,BYTE PTR \[eax-0x6f6f6f70\]
+ *[0-9a-f]+:	66 0f c1 90 90 90 90 90[ 	]+xadd[ 	]+(WORD PTR )?\[eax-0x6f6f6f70\],dx
+ *[0-9a-f]+:	66 90[ 	]+xchg[ 	]+ax,ax
+ *[0-9a-f]+:	0f 00 c0[ 	]+sldt[ 	]+eax
+ *[0-9a-f]+:	66 0f 00 c0[ 	]+sldt[ 	]+ax
+ *[0-9a-f]+:	0f 00 00[ 	]+sldt[ 	]+(WORD PTR )?\[eax\]
+ *[0-9a-f]+:	0f 01 e0[ 	]+smsw[ 	]+eax
+ *[0-9a-f]+:	66 0f 01 e0[ 	]+smsw[ 	]+ax
+ *[0-9a-f]+:	0f 01 20[ 	]+smsw[ 	]+(WORD PTR )?\[eax\]
+ *[0-9a-f]+:	0f 00 c8[ 	]+str[ 	]+eax
+ *[0-9a-f]+:	66 0f 00 c8[ 	]+str[ 	]+ax
+ *[0-9a-f]+:	0f 00 08[ 	]+str[ 	]+(WORD PTR )?\[eax\]
+ *[0-9a-f]+:	0f ad d0 [ 	]*shrd[ 	]+eax,edx,cl
+ *[0-9a-f]+:	0f a5 d0 [ 	]*shld[ 	]+eax,edx,cl
+ *[0-9a-f]+:	85 c3 [ 	]*test[ 	]+ebx,eax
+ *[0-9a-f]+:	85 d8 [ 	]*test[ 	]+eax,ebx
+ *[0-9a-f]+:	85 18 [ 	]*test[ 	]+(DWORD PTR )?\[eax\],ebx
+#pass
+	\.\.\.
diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
new file mode 100644
index 000000000000..9db7e671135d
--- /dev/null
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -0,0 +1,591 @@
+#source: opcode.s
+#as: -J
+#objdump: -dwMsuffix
+#name: i386 opcodes (w/ suffix)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+ *[0-9a-f]+:	00 90 90 90 90 90[ 	]+addb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	01 90 90 90 90 90[ 	]+addl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	02 90 90 90 90 90[ 	]+addb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	03 90 90 90 90 90[ 	]+addl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	04 90[ 	]+addb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	05 90 90 90 90[ 	]+addl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	06[ 	]+pushl[ 	]+%es
+ *[0-9a-f]+:	07[ 	]+popl[ 	]+%es
+ *[0-9a-f]+:	08 90 90 90 90 90[ 	]+orb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	09 90 90 90 90 90[ 	]+orl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0a 90 90 90 90 90[ 	]+orb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	0b 90 90 90 90 90[ 	]+orl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0c 90[ 	]+orb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	0d 90 90 90 90[ 	]+orl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	0e[ 	]+pushl[ 	]+%cs
+ *[0-9a-f]+:	10 90 90 90 90 90[ 	]+adcb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	11 90 90 90 90 90[ 	]+adcl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	12 90 90 90 90 90[ 	]+adcb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	13 90 90 90 90 90[ 	]+adcl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	14 90[ 	]+adcb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	15 90 90 90 90[ 	]+adcl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	16[ 	]+pushl[ 	]+%ss
+ *[0-9a-f]+:	17[ 	]+popl[ 	]+%ss
+ *[0-9a-f]+:	18 90 90 90 90 90[ 	]+sbbb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	19 90 90 90 90 90[ 	]+sbbl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	1a 90 90 90 90 90[ 	]+sbbb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	1b 90 90 90 90 90[ 	]+sbbl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	1c 90[ 	]+sbbb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	1d 90 90 90 90[ 	]+sbbl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	1e[ 	]+pushl[ 	]+%ds
+ *[0-9a-f]+:	1f[ 	]+popl[ 	]+%ds
+ *[0-9a-f]+:	20 90 90 90 90 90[ 	]+andb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	21 90 90 90 90 90[ 	]+andl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	22 90 90 90 90 90[ 	]+andb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	23 90 90 90 90 90[ 	]+andl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	24 90[ 	]+andb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	25 90 90 90 90[ 	]+andl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	27[ 	]+daa[ 	]+
+ *[0-9a-f]+:	28 90 90 90 90 90[ 	]+subb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	29 90 90 90 90 90[ 	]+subl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	2a 90 90 90 90 90[ 	]+subb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	2b 90 90 90 90 90[ 	]+subl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	2c 90[ 	]+subb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	2d 90 90 90 90[ 	]+subl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	2f[ 	]+das[ 	]+
+ *[0-9a-f]+:	30 90 90 90 90 90[ 	]+xorb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	31 90 90 90 90 90[ 	]+xorl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	32 90 90 90 90 90[ 	]+xorb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	33 90 90 90 90 90[ 	]+xorl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	34 90[ 	]+xorb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	35 90 90 90 90[ 	]+xorl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	37[ 	]+aaa[ 	]+
+ *[0-9a-f]+:	38 90 90 90 90 90[ 	]+cmpb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	39 90 90 90 90 90[ 	]+cmpl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	3a 90 90 90 90 90[ 	]+cmpb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	3b 90 90 90 90 90[ 	]+cmpl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	3c 90[ 	]+cmpb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	3d 90 90 90 90[ 	]+cmpl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	3f[ 	]+aas[ 	]+
+ *[0-9a-f]+:	40[ 	]+incl[ 	]+%eax
+ *[0-9a-f]+:	41[ 	]+incl[ 	]+%ecx
+ *[0-9a-f]+:	42[ 	]+incl[ 	]+%edx
+ *[0-9a-f]+:	43[ 	]+incl[ 	]+%ebx
+ *[0-9a-f]+:	44[ 	]+incl[ 	]+%esp
+ *[0-9a-f]+:	45[ 	]+incl[ 	]+%ebp
+ *[0-9a-f]+:	46[ 	]+incl[ 	]+%esi
+ *[0-9a-f]+:	47[ 	]+incl[ 	]+%edi
+ *[0-9a-f]+:	48[ 	]+decl[ 	]+%eax
+ *[0-9a-f]+:	49[ 	]+decl[ 	]+%ecx
+ *[0-9a-f]+:	4a[ 	]+decl[ 	]+%edx
+ *[0-9a-f]+:	4b[ 	]+decl[ 	]+%ebx
+ *[0-9a-f]+:	4c[ 	]+decl[ 	]+%esp
+ *[0-9a-f]+:	4d[ 	]+decl[ 	]+%ebp
+ *[0-9a-f]+:	4e[ 	]+decl[ 	]+%esi
+ *[0-9a-f]+:	4f[ 	]+decl[ 	]+%edi
+ *[0-9a-f]+:	50[ 	]+pushl[ 	]+%eax
+ *[0-9a-f]+:	51[ 	]+pushl[ 	]+%ecx
+ *[0-9a-f]+:	52[ 	]+pushl[ 	]+%edx
+ *[0-9a-f]+:	53[ 	]+pushl[ 	]+%ebx
+ *[0-9a-f]+:	54[ 	]+pushl[ 	]+%esp
+ *[0-9a-f]+:	55[ 	]+pushl[ 	]+%ebp
+ *[0-9a-f]+:	56[ 	]+pushl[ 	]+%esi
+ *[0-9a-f]+:	57[ 	]+pushl[ 	]+%edi
+ *[0-9a-f]+:	58[ 	]+popl[ 	]+%eax
+ *[0-9a-f]+:	59[ 	]+popl[ 	]+%ecx
+ *[0-9a-f]+:	5a[ 	]+popl[ 	]+%edx
+ *[0-9a-f]+:	5b[ 	]+popl[ 	]+%ebx
+ *[0-9a-f]+:	5c[ 	]+popl[ 	]+%esp
+ *[0-9a-f]+:	5d[ 	]+popl[ 	]+%ebp
+ *[0-9a-f]+:	5e[ 	]+popl[ 	]+%esi
+ *[0-9a-f]+:	5f[ 	]+popl[ 	]+%edi
+ *[0-9a-f]+:	60[ 	]+pushal 
+ *[0-9a-f]+:	61[ 	]+popal[ 	]+
+ *[0-9a-f]+:	62 90 90 90 90 90[ 	]+boundl %edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	63 90 90 90 90 90[ 	]+arpl[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	68 90 90 90 90[ 	]+pushl[ 	]+\$0x90909090
+ *[0-9a-f]+:	69 90 90 90 90 90 90 90 90 90[ 	]+imull[ 	]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	6a 90[ 	]+pushl[ 	]+\$0xffffff90
+ *[0-9a-f]+:	6b 90 90 90 90 90 90[ 	]+imull[ 	]+\$0xffffff90,-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	6c[ 	]+insb[ 	]+\(%dx\),%es:\(%edi\)
+ *[0-9a-f]+:	6d[ 	]+insl[ 	]+\(%dx\),%es:\(%edi\)
+ *[0-9a-f]+:	6e[ 	]+outsb[ 	]+%ds:\(%esi\),\(%dx\)
+ *[0-9a-f]+:	6f[ 	]+outsl[ 	]+%ds:\(%esi\),\(%dx\)
+ *[0-9a-f]+:	70 90[ 	]+jo[ 	]+(0x)?df.*
+ *[0-9a-f]+:	71 90[ 	]+jno[ 	]+(0x)?e1.*
+ *[0-9a-f]+:	72 90[ 	]+jb[ 	]+(0x)?e3.*
+ *[0-9a-f]+:	73 90[ 	]+jae[ 	]+(0x)?e5.*
+ *[0-9a-f]+:	74 90[ 	]+je[ 	]+(0x)?e7.*
+ *[0-9a-f]+:	75 90[ 	]+jne[ 	]+(0x)?e9.*
+ *[0-9a-f]+:	76 90[ 	]+jbe[ 	]+(0x)?eb.*
+ *[0-9a-f]+:	77 90[ 	]+ja[ 	]+(0x)?ed.*
+ *[0-9a-f]+:	78 90[ 	]+js[ 	]+(0x)?ef.*
+ *[0-9a-f]+:	79 90[ 	]+jns[ 	]+(0x)?f1.*
+ *[0-9a-f]+:	7a 90[ 	]+jp[ 	]+(0x)?f3.*
+ *[0-9a-f]+:	7b 90[ 	]+jnp[ 	]+(0x)?f5.*
+ *[0-9a-f]+:	7c 90[ 	]+jl[ 	]+(0x)?f7.*
+ *[0-9a-f]+:	7d 90[ 	]+jge[ 	]+(0x)?f9.*
+ *[0-9a-f]+:	7e 90[ 	]+jle[ 	]+(0x)?fb.*
+ *[0-9a-f]+:	7f 90[ 	]+jg[ 	]+(0x)?fd.*
+ *[0-9a-f]+:	80 90 90 90 90 90 90[ 	]+adcb[ 	]+\$0x90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	81 90 90 90 90 90 90 90 90 90[ 	]+adcl[ 	]+\$0x90909090,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	83 90 90 90 90 90 90[ 	]+adcl[ 	]+\$0xffffff90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	84 90 90 90 90 90[ 	]+testb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	85 90 90 90 90 90[ 	]+testl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	86 90 90 90 90 90[ 	]+xchgb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	87 90 90 90 90 90[ 	]+xchgl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	88 90 90 90 90 90[ 	]+movb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	89 90 90 90 90 90[ 	]+movl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	8a 90 90 90 90 90[ 	]+movb[ 	]+-0x6f6f6f70\(%eax\),%dl
+ *[0-9a-f]+:	8b 90 90 90 90 90[ 	]+movl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	8c 90 90 90 90 90[ 	]+movw[ 	]+%ss,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	8d 90 90 90 90 90[ 	]+leal[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	8e 90 90 90 90 90[ 	]+movw[ 	]+-0x6f6f6f70\(%eax\),%ss
+ *[0-9a-f]+:	8f 80 90 90 90 90[ 	]+popl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	90[ 	]+nop[ 	]+
+ *[0-9a-f]+:	91[ 	]+xchgl[ 	]+%eax,%ecx
+ *[0-9a-f]+:	92[ 	]+xchgl[ 	]+%eax,%edx
+ *[0-9a-f]+:	93[ 	]+xchgl[ 	]+%eax,%ebx
+ *[0-9a-f]+:	94[ 	]+xchgl[ 	]+%eax,%esp
+ *[0-9a-f]+:	95[ 	]+xchgl[ 	]+%eax,%ebp
+ *[0-9a-f]+:	96[ 	]+xchgl[ 	]+%eax,%esi
+ *[0-9a-f]+:	97[ 	]+xchgl[ 	]+%eax,%edi
+ *[0-9a-f]+:	98[ 	]+cwtl[ 	]+
+ *[0-9a-f]+:	99[ 	]+cltd[ 	]+
+ *[0-9a-f]+:	9a 90 90 90 90 90 90[ 	]+lcalll \$0x9090,\$0x90909090
+ *[0-9a-f]+:	9b[ 	]+fwait
+ *[0-9a-f]+:	9c[ 	]+pushfl 
+ *[0-9a-f]+:	9d[ 	]+popfl[ 	]+
+ *[0-9a-f]+:	9e[ 	]+sahf[ 	]+
+ *[0-9a-f]+:	9f[ 	]+lahf[ 	]+
+ *[0-9a-f]+:	a0 90 90 90 90[ 	]+movb[ 	]+0x90909090,%al
+ *[0-9a-f]+:	a1 90 90 90 90[ 	]+movl[ 	]+0x90909090,%eax
+ *[0-9a-f]+:	a2 90 90 90 90[ 	]+movb[ 	]+%al,0x90909090
+ *[0-9a-f]+:	a3 90 90 90 90[ 	]+movl[ 	]+%eax,0x90909090
+ *[0-9a-f]+:	a4[ 	]+movsb[ 	]+%ds:\(%esi\),%es:\(%edi\)
+ *[0-9a-f]+:	a5[ 	]+movsl[ 	]+%ds:\(%esi\),%es:\(%edi\)
+ *[0-9a-f]+:	a6[ 	]+cmpsb[ 	]+%es:\(%edi\),%ds:\(%esi\)
+ *[0-9a-f]+:	a7[ 	]+cmpsl[ 	]+%es:\(%edi\),%ds:\(%esi\)
+ *[0-9a-f]+:	a8 90[ 	]+testb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	a9 90 90 90 90[ 	]+testl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	aa[ 	]+stosb[ 	]+%al,%es:\(%edi\)
+ *[0-9a-f]+:	ab[ 	]+stosl[ 	]+%eax,%es:\(%edi\)
+ *[0-9a-f]+:	ac[ 	]+lodsb[ 	]+%ds:\(%esi\),%al
+ *[0-9a-f]+:	ad[ 	]+lodsl[ 	]+%ds:\(%esi\),%eax
+ *[0-9a-f]+:	ae[ 	]+scasb[ 	]+%es:\(%edi\),%al
+ *[0-9a-f]+:	af[ 	]+scasl[ 	]+%es:\(%edi\),%eax
+ *[0-9a-f]+:	b0 90[ 	]+movb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	b1 90[ 	]+movb[ 	]+\$0x90,%cl
+ *[0-9a-f]+:	b2 90[ 	]+movb[ 	]+\$0x90,%dl
+ *[0-9a-f]+:	b3 90[ 	]+movb[ 	]+\$0x90,%bl
+ *[0-9a-f]+:	b4 90[ 	]+movb[ 	]+\$0x90,%ah
+ *[0-9a-f]+:	b5 90[ 	]+movb[ 	]+\$0x90,%ch
+ *[0-9a-f]+:	b6 90[ 	]+movb[ 	]+\$0x90,%dh
+ *[0-9a-f]+:	b7 90[ 	]+movb[ 	]+\$0x90,%bh
+ *[0-9a-f]+:	b8 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%eax
+ *[0-9a-f]+:	b9 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%ecx
+ *[0-9a-f]+:	ba 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%edx
+ *[0-9a-f]+:	bb 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%ebx
+ *[0-9a-f]+:	bc 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%esp
+ *[0-9a-f]+:	bd 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%ebp
+ *[0-9a-f]+:	be 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%esi
+ *[0-9a-f]+:	bf 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,%edi
+ *[0-9a-f]+:	c0 90 90 90 90 90 90[ 	]+rclb[ 	]+\$0x90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	c1 90 90 90 90 90 90[ 	]+rcll[ 	]+\$0x90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	c2 90 90[ 	]+retl[ 	]+\$0x9090
+ *[0-9a-f]+:	c3[ 	]+retl[ 	]+
+ *[0-9a-f]+:	c4 90 90 90 90 90[ 	]+lesl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	c5 90 90 90 90 90[ 	]+ldsl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	c6 80 90 90 90 90 90[ 	]+movb[ 	]+\$0x90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	c7 80 90 90 90 90 90 90 90 90[ 	]+movl[ 	]+\$0x90909090,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	c8 90 90 90[ 	]+enterl \$0x9090,\$0x90
+ *[0-9a-f]+:	c9[ 	]+leavel 
+ *[0-9a-f]+:	ca 90 90[ 	]+lretl[ 	]+\$0x9090
+ *[0-9a-f]+:	cb[ 	]+lretl[ 	]+
+ *[0-9a-f]+:	cc[ 	]+int3[ 	]+
+ *[0-9a-f]+:	cd 90[ 	]+int[ 	]+\$0x90
+ *[0-9a-f]+:	ce[ 	]+into[ 	]+
+ *[0-9a-f]+:	cf[ 	]+iretl[ 	]+
+ *[0-9a-f]+:	d0 90 90 90 90 90[ 	]+rclb[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	d1 90 90 90 90 90[ 	]+rcll[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	d2 90 90 90 90 90[ 	]+rclb[ 	]+%cl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	d3 90 90 90 90 90[ 	]+rcll[ 	]+%cl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	d4 90[ 	]+aam[ 	]+\$0xffffff90
+ *[0-9a-f]+:	d5 90[ 	]+aad[ 	]+\$0xffffff90
+ *[0-9a-f]+:	d7[ 	]+xlat[ 	]+%ds:\(%ebx\)
+ *[0-9a-f]+:	d8 90 90 90 90 90[ 	]+fcoms[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	d9 90 90 90 90 90[ 	]+fsts[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	da 90 90 90 90 90[ 	]+ficoml -0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	db 90 90 90 90 90[ 	]+fistl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	dc 90 90 90 90 90[ 	]+fcoml[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	dd 90 90 90 90 90[ 	]+fstl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	de 90 90 90 90 90[ 	]+ficom[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	df 90 90 90 90 90[ 	]+fist[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	e0 90[ 	]+loopnel (0x)?25c.*
+ *[0-9a-f]+:	e1 90[ 	]+loopel (0x)?25e.*
+ *[0-9a-f]+:	e2 90[ 	]+loopl[ 	]+(0x)?260.*
+ *[0-9a-f]+:	e3 90[ 	]+jecxz[ 	]+(0x)?262.*
+ *[0-9a-f]+:	e4 90[ 	]+inb[ 	]+\$0x90,%al
+ *[0-9a-f]+:	e5 90[ 	]+inl[ 	]+\$0x90,%eax
+ *[0-9a-f]+:	e6 90[ 	]+outb[ 	]+%al,\$0x90
+ *[0-9a-f]+:	e7 90[ 	]+outl[ 	]+%eax,\$0x90
+ *[0-9a-f]+:	e8 90 90 90 90[ 	]+calll[ 	]+(0x)?9090936f.*
+ *[0-9a-f]+:	e9 90 90 90 90[ 	]+jmpl[ 	]+(0x)?90909374.*
+ *[0-9a-f]+:	ea 90 90 90 90 90 90[ 	]+ljmpl[ 	]+\$0x9090,\$0x90909090
+ *[0-9a-f]+:	eb 90[ 	]+jmp[ 	]+(0x)?27d.*
+ *[0-9a-f]+:	ec[ 	]+inb[ 	]+\(%dx\),%al
+ *[0-9a-f]+:	ed[ 	]+inl[ 	]+\(%dx\),%eax
+ *[0-9a-f]+:	ee[ 	]+outb[ 	]+%al,\(%dx\)
+ *[0-9a-f]+:	ef[ 	]+outl[ 	]+%eax,\(%dx\)
+ *[0-9a-f]+:	f4[ 	]+hlt[ 	]+
+ *[0-9a-f]+:	f5[ 	]+cmc[ 	]+
+ *[0-9a-f]+:	f6 90 90 90 90 90[ 	]+notb[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	f7 90 90 90 90 90[ 	]+notl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	f8[ 	]+clc[ 	]+
+ *[0-9a-f]+:	f9[ 	]+stc[ 	]+
+ *[0-9a-f]+:	fa[ 	]+cli[ 	]+
+ *[0-9a-f]+:	fb[ 	]+sti[ 	]+
+ *[0-9a-f]+:	fc[ 	]+cld[ 	]+
+ *[0-9a-f]+:	fd[ 	]+std[ 	]+
+ *[0-9a-f]+:	ff 90 90 90 90 90[ 	]+calll[ 	]+\*-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 00 90 90 90 90 90[ 	]+lldt[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 01 90 90 90 90 90[ 	]+lgdtl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 02 90 90 90 90 90[ 	]+larl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 03 90 90 90 90 90[ 	]+lsll[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 06[ 	]+clts[ 	]+
+ *[0-9a-f]+:	0f 08[ 	]+invd[ 	]+
+ *[0-9a-f]+:	0f 09[ 	]+wbinvd 
+ *[0-9a-f]+:	0f 0b[ 	]+ud2a[ 	]+
+ *[0-9a-f]+:	0f 20 d0[ 	]+movl[ 	]+%cr2,%eax
+ *[0-9a-f]+:	0f 21 d0[ 	]+movl[ 	]+%db2,%eax
+ *[0-9a-f]+:	0f 22 d0[ 	]+movl[ 	]+%eax,%cr2
+ *[0-9a-f]+:	0f 23 d0[ 	]+movl[ 	]+%eax,%db2
+ *[0-9a-f]+:	0f 24 d0[ 	]+movl[ 	]+%tr2,%eax
+ *[0-9a-f]+:	0f 26 d0[ 	]+movl[ 	]+%eax,%tr2
+ *[0-9a-f]+:	0f 30[ 	]+wrmsr[ 	]+
+ *[0-9a-f]+:	0f 31[ 	]+rdtsc[ 	]+
+ *[0-9a-f]+:	0f 32[ 	]+rdmsr[ 	]+
+ *[0-9a-f]+:	0f 33[ 	]+rdpmc[ 	]+
+ *[0-9a-f]+:	0f 40 90 90 90 90 90[ 	]+cmovo[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 41 90 90 90 90 90[ 	]+cmovno -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 42 90 90 90 90 90[ 	]+cmovb[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 43 90 90 90 90 90[ 	]+cmovae -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 44 90 90 90 90 90[ 	]+cmove[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 45 90 90 90 90 90[ 	]+cmovne -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 46 90 90 90 90 90[ 	]+cmovbe -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 47 90 90 90 90 90[ 	]+cmova[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 48 90 90 90 90 90[ 	]+cmovs[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 49 90 90 90 90 90[ 	]+cmovns -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4a 90 90 90 90 90[ 	]+cmovp[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4b 90 90 90 90 90[ 	]+cmovnp -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4c 90 90 90 90 90[ 	]+cmovl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4d 90 90 90 90 90[ 	]+cmovge -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4e 90 90 90 90 90[ 	]+cmovle -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 4f 90 90 90 90 90[ 	]+cmovg[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f 60 90 90 90 90 90[ 	]+punpcklbw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 61 90 90 90 90 90[ 	]+punpcklwd -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 62 90 90 90 90 90[ 	]+punpckldq -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 63 90 90 90 90 90[ 	]+packsswb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 64 90 90 90 90 90[ 	]+pcmpgtb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 65 90 90 90 90 90[ 	]+pcmpgtw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 66 90 90 90 90 90[ 	]+pcmpgtd -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 67 90 90 90 90 90[ 	]+packuswb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 68 90 90 90 90 90[ 	]+punpckhbw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 69 90 90 90 90 90[ 	]+punpckhwd -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 6a 90 90 90 90 90[ 	]+punpckhdq -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 6b 90 90 90 90 90[ 	]+packssdw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 6e 90 90 90 90 90[ 	]+movd[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 6f 90 90 90 90 90[ 	]+movq[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 71 d0 90[ 	]+psrlw[ 	]+\$0x90,%mm0
+ *[0-9a-f]+:	0f 72 d0 90[ 	]+psrld[ 	]+\$0x90,%mm0
+ *[0-9a-f]+:	0f 73 d0 90[ 	]+psrlq[ 	]+\$0x90,%mm0
+ *[0-9a-f]+:	0f 74 90 90 90 90 90[ 	]+pcmpeqb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 75 90 90 90 90 90[ 	]+pcmpeqw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 76 90 90 90 90 90[ 	]+pcmpeqd -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f 77[ 	]+emms[ 	]+
+ *[0-9a-f]+:	0f 7e 90 90 90 90 90[ 	]+movd[ 	]+%mm2,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 7f 90 90 90 90 90[ 	]+movq[ 	]+%mm2,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 80 90 90 90 90[ 	]+jo[ 	]+909094e2 <foo\+0x909094e2>
+ *[0-9a-f]+:	0f 81 90 90 90 90[ 	]+jno[ 	]+909094e8 <foo\+0x909094e8>
+ *[0-9a-f]+:	0f 82 90 90 90 90[ 	]+jb[ 	]+909094ee <foo\+0x909094ee>
+ *[0-9a-f]+:	0f 83 90 90 90 90[ 	]+jae[ 	]+909094f4 <foo\+0x909094f4>
+ *[0-9a-f]+:	0f 84 90 90 90 90[ 	]+je[ 	]+909094fa <foo\+0x909094fa>
+ *[0-9a-f]+:	0f 85 90 90 90 90[ 	]+jne[ 	]+90909500 <foo\+0x90909500>
+ *[0-9a-f]+:	0f 86 90 90 90 90[ 	]+jbe[ 	]+90909506 <foo\+0x90909506>
+ *[0-9a-f]+:	0f 87 90 90 90 90[ 	]+ja[ 	]+9090950c <foo\+0x9090950c>
+ *[0-9a-f]+:	0f 88 90 90 90 90[ 	]+js[ 	]+90909512 <foo\+0x90909512>
+ *[0-9a-f]+:	0f 89 90 90 90 90[ 	]+jns[ 	]+90909518 <foo\+0x90909518>
+ *[0-9a-f]+:	0f 8a 90 90 90 90[ 	]+jp[ 	]+9090951e <foo\+0x9090951e>
+ *[0-9a-f]+:	0f 8b 90 90 90 90[ 	]+jnp[ 	]+90909524 <foo\+0x90909524>
+ *[0-9a-f]+:	0f 8c 90 90 90 90[ 	]+jl[ 	]+9090952a <foo\+0x9090952a>
+ *[0-9a-f]+:	0f 8d 90 90 90 90[ 	]+jge[ 	]+90909530 <foo\+0x90909530>
+ *[0-9a-f]+:	0f 8e 90 90 90 90[ 	]+jle[ 	]+90909536 <foo\+0x90909536>
+ *[0-9a-f]+:	0f 8f 90 90 90 90[ 	]+jg[ 	]+9090953c <foo\+0x9090953c>
+ *[0-9a-f]+:	0f 90 80 90 90 90 90[ 	]+seto[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 91 80 90 90 90 90[ 	]+setno[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 92 80 90 90 90 90[ 	]+setb[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 93 80 90 90 90 90[ 	]+setae[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 94 80 90 90 90 90[ 	]+sete[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 95 80 90 90 90 90[ 	]+setne[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 96 80 90 90 90 90[ 	]+setbe[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 97 80 90 90 90 90[ 	]+seta[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 98 80 90 90 90 90[ 	]+sets[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 99 80 90 90 90 90[ 	]+setns[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9a 80 90 90 90 90[ 	]+setp[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9b 80 90 90 90 90[ 	]+setnp[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9c 80 90 90 90 90[ 	]+setl[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9d 80 90 90 90 90[ 	]+setge[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9e 80 90 90 90 90[ 	]+setle[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f 9f 80 90 90 90 90[ 	]+setg[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f a0[ 	]+pushl[ 	]+%fs
+ *[0-9a-f]+:	0f a1[ 	]+popl[ 	]+%fs
+ *[0-9a-f]+:	0f a2[ 	]+cpuid[ 	]+
+ *[0-9a-f]+:	0f a3 90 90 90 90 90[ 	]+btl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f a4 90 90 90 90 90 90[ 	]+shldl[ 	]+\$0x90,%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f a5 90 90 90 90 90[ 	]+shldl[ 	]+%cl,%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f a8[ 	]+pushl[ 	]+%gs
+ *[0-9a-f]+:	0f a9[ 	]+popl[ 	]+%gs
+ *[0-9a-f]+:	0f aa[ 	]+rsm[ 	]+
+ *[0-9a-f]+:	0f ab 90 90 90 90 90[ 	]+btsl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f ac 90 90 90 90 90 90[ 	]+shrdl[ 	]+\$0x90,%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f ad 90 90 90 90 90[ 	]+shrdl[ 	]+%cl,%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f af 90 90 90 90 90[ 	]+imull[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b0 90 90 90 90 90[ 	]+cmpxchgb %dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f b1 90 90 90 90 90[ 	]+cmpxchgl %edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f b2 90 90 90 90 90[ 	]+lssl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b3 90 90 90 90 90[ 	]+btrl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f b4 90 90 90 90 90[ 	]+lfsl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b5 90 90 90 90 90[ 	]+lgsl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b6 90 90 90 90 90[ 	]+movzbl -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b7 90 90 90 90 90[ 	]+movzwl -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f b9[ 	]+ud2b[ 	]+
+ *[0-9a-f]+:	0f bb 90 90 90 90 90[ 	]+btcl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f bc 90 90 90 90 90[ 	]+bsfl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f bd 90 90 90 90 90[ 	]+bsrl[ 	]+-0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f be 90 90 90 90 90[ 	]+movsbl -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f bf 90 90 90 90 90[ 	]+movswl -0x6f6f6f70\(%eax\),%edx
+ *[0-9a-f]+:	0f c0 90 90 90 90 90[ 	]+xaddb[ 	]+%dl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f c1 90 90 90 90 90[ 	]+xaddl[ 	]+%edx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	0f c8[ 	]+bswap[ 	]+%eax
+ *[0-9a-f]+:	0f c9[ 	]+bswap[ 	]+%ecx
+ *[0-9a-f]+:	0f ca[ 	]+bswap[ 	]+%edx
+ *[0-9a-f]+:	0f cb[ 	]+bswap[ 	]+%ebx
+ *[0-9a-f]+:	0f cc[ 	]+bswap[ 	]+%esp
+ *[0-9a-f]+:	0f cd[ 	]+bswap[ 	]+%ebp
+ *[0-9a-f]+:	0f ce[ 	]+bswap[ 	]+%esi
+ *[0-9a-f]+:	0f cf[ 	]+bswap[ 	]+%edi
+ *[0-9a-f]+:	0f d1 90 90 90 90 90[ 	]+psrlw[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f d2 90 90 90 90 90[ 	]+psrld[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f d3 90 90 90 90 90[ 	]+psrlq[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f d5 90 90 90 90 90[ 	]+pmullw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f d8 90 90 90 90 90[ 	]+psubusb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f d9 90 90 90 90 90[ 	]+psubusw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f db 90 90 90 90 90[ 	]+pand[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f dc 90 90 90 90 90[ 	]+paddusb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f dd 90 90 90 90 90[ 	]+paddusw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f df 90 90 90 90 90[ 	]+pandn[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f e1 90 90 90 90 90[ 	]+psraw[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f e2 90 90 90 90 90[ 	]+psrad[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f e5 90 90 90 90 90[ 	]+pmulhw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f e8 90 90 90 90 90[ 	]+psubsb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f e9 90 90 90 90 90[ 	]+psubsw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f eb 90 90 90 90 90[ 	]+por[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f ec 90 90 90 90 90[ 	]+paddsb -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f ed 90 90 90 90 90[ 	]+paddsw -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f ef 90 90 90 90 90[ 	]+pxor[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f1 90 90 90 90 90[ 	]+psllw[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f2 90 90 90 90 90[ 	]+pslld[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f3 90 90 90 90 90[ 	]+psllq[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f5 90 90 90 90 90[ 	]+pmaddwd -0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f8 90 90 90 90 90[ 	]+psubb[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f f9 90 90 90 90 90[ 	]+psubw[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f fa 90 90 90 90 90[ 	]+psubd[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f fc 90 90 90 90 90[ 	]+paddb[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f fd 90 90 90 90 90[ 	]+paddw[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	0f fe 90 90 90 90 90[ 	]+paddd[ 	]+-0x6f6f6f70\(%eax\),%mm2
+ *[0-9a-f]+:	66 01 90 90 90 90 90[ 	]+addw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 03 90 90 90 90 90[ 	]+addw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 05 90 90[ 	]+addw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 06[ 	]+pushw[ 	]+%es
+ *[0-9a-f]+:	66 07[ 	]+popw[ 	]+%es
+ *[0-9a-f]+:	66 09 90 90 90 90 90[ 	]+orw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0b 90 90 90 90 90[ 	]+orw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0d 90 90[ 	]+orw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 0e[ 	]+pushw[ 	]+%cs
+ *[0-9a-f]+:	66 11 90 90 90 90 90[ 	]+adcw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 13 90 90 90 90 90[ 	]+adcw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 15 90 90[ 	]+adcw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 16[ 	]+pushw[ 	]+%ss
+ *[0-9a-f]+:	66 17[ 	]+popw[ 	]+%ss
+ *[0-9a-f]+:	66 19 90 90 90 90 90[ 	]+sbbw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 1b 90 90 90 90 90[ 	]+sbbw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 1d 90 90[ 	]+sbbw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 1e[ 	]+pushw[ 	]+%ds
+ *[0-9a-f]+:	66 1f[ 	]+popw[ 	]+%ds
+ *[0-9a-f]+:	66 21 90 90 90 90 90[ 	]+andw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 23 90 90 90 90 90[ 	]+andw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 25 90 90[ 	]+andw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 29 90 90 90 90 90[ 	]+subw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 2b 90 90 90 90 90[ 	]+subw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 2d 90 90[ 	]+subw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 31 90 90 90 90 90[ 	]+xorw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 33 90 90 90 90 90[ 	]+xorw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 35 90 90[ 	]+xorw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 39 90 90 90 90 90[ 	]+cmpw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 3b 90 90 90 90 90[ 	]+cmpw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 3d 90 90[ 	]+cmpw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 40[ 	]+incw[ 	]+%ax
+ *[0-9a-f]+:	66 41[ 	]+incw[ 	]+%cx
+ *[0-9a-f]+:	66 42[ 	]+incw[ 	]+%dx
+ *[0-9a-f]+:	66 43[ 	]+incw[ 	]+%bx
+ *[0-9a-f]+:	66 44[ 	]+incw[ 	]+%sp
+ *[0-9a-f]+:	66 45[ 	]+incw[ 	]+%bp
+ *[0-9a-f]+:	66 46[ 	]+incw[ 	]+%si
+ *[0-9a-f]+:	66 47[ 	]+incw[ 	]+%di
+ *[0-9a-f]+:	66 48[ 	]+decw[ 	]+%ax
+ *[0-9a-f]+:	66 49[ 	]+decw[ 	]+%cx
+ *[0-9a-f]+:	66 4a[ 	]+decw[ 	]+%dx
+ *[0-9a-f]+:	66 4b[ 	]+decw[ 	]+%bx
+ *[0-9a-f]+:	66 4c[ 	]+decw[ 	]+%sp
+ *[0-9a-f]+:	66 4d[ 	]+decw[ 	]+%bp
+ *[0-9a-f]+:	66 4e[ 	]+decw[ 	]+%si
+ *[0-9a-f]+:	66 4f[ 	]+decw[ 	]+%di
+ *[0-9a-f]+:	66 50[ 	]+pushw[ 	]+%ax
+ *[0-9a-f]+:	66 51[ 	]+pushw[ 	]+%cx
+ *[0-9a-f]+:	66 52[ 	]+pushw[ 	]+%dx
+ *[0-9a-f]+:	66 53[ 	]+pushw[ 	]+%bx
+ *[0-9a-f]+:	66 54[ 	]+pushw[ 	]+%sp
+ *[0-9a-f]+:	66 55[ 	]+pushw[ 	]+%bp
+ *[0-9a-f]+:	66 56[ 	]+pushw[ 	]+%si
+ *[0-9a-f]+:	66 57[ 	]+pushw[ 	]+%di
+ *[0-9a-f]+:	66 58[ 	]+popw[ 	]+%ax
+ *[0-9a-f]+:	66 59[ 	]+popw[ 	]+%cx
+ *[0-9a-f]+:	66 5a[ 	]+popw[ 	]+%dx
+ *[0-9a-f]+:	66 5b[ 	]+popw[ 	]+%bx
+ *[0-9a-f]+:	66 5c[ 	]+popw[ 	]+%sp
+ *[0-9a-f]+:	66 5d[ 	]+popw[ 	]+%bp
+ *[0-9a-f]+:	66 5e[ 	]+popw[ 	]+%si
+ *[0-9a-f]+:	66 5f[ 	]+popw[ 	]+%di
+ *[0-9a-f]+:	66 60[ 	]+pushaw 
+ *[0-9a-f]+:	66 61[ 	]+popaw[ 	]+
+ *[0-9a-f]+:	66 62 90 90 90 90 90[ 	]+boundw %dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 68 90 90[ 	]+pushw[ 	]+\$0x9090
+ *[0-9a-f]+:	66 69 90 90 90 90 90 90 90[ 	]+imulw[ 	]+\$0x9090,-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 6a 90[ 	]+pushw[ 	]+\$0xffffff90
+ *[0-9a-f]+:	66 6b 90 90 90 90 90 90[ 	]+imulw[ 	]+\$0xffffff90,-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 6d[ 	]+insw[ 	]+\(%dx\),%es:\(%edi\)
+ *[0-9a-f]+:	66 6f[ 	]+outsw[ 	]+%ds:\(%esi\),\(%dx\)
+ *[0-9a-f]+:	66 81 90 90 90 90 90 90 90[ 	]+adcw[ 	]+\$0x9090,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 83 90 90 90 90 90 90[ 	]+adcw[ 	]+\$0xffffff90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 85 90 90 90 90 90[ 	]+testw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 87 90 90 90 90 90[ 	]+xchgw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 89 90 90 90 90 90[ 	]+movw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 8b 90 90 90 90 90[ 	]+movw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	8c 90 90 90 90 90[ 	]+movw[ 	]+%ss,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 8d 90 90 90 90 90[ 	]+leaw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 8f 80 90 90 90 90[ 	]+popw[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 91[ 	]+xchgw[ 	]+%ax,%cx
+ *[0-9a-f]+:	66 92[ 	]+xchgw[ 	]+%ax,%dx
+ *[0-9a-f]+:	66 93[ 	]+xchgw[ 	]+%ax,%bx
+ *[0-9a-f]+:	66 94[ 	]+xchgw[ 	]+%ax,%sp
+ *[0-9a-f]+:	66 95[ 	]+xchgw[ 	]+%ax,%bp
+ *[0-9a-f]+:	66 96[ 	]+xchgw[ 	]+%ax,%si
+ *[0-9a-f]+:	66 97[ 	]+xchgw[ 	]+%ax,%di
+ *[0-9a-f]+:	66 98[ 	]+cbtw[ 	]+
+ *[0-9a-f]+:	66 99[ 	]+cwtd[ 	]+
+ *[0-9a-f]+:	66 9a 90 90 90 90[ 	]+lcallw \$0x9090,\$0x9090
+ *[0-9a-f]+:	66 9c[ 	]+pushfw 
+ *[0-9a-f]+:	66 9d[ 	]+popfw[ 	]+
+ *[0-9a-f]+:	66 a1 90 90 90 90[ 	]+movw[ 	]+0x90909090,%ax
+ *[0-9a-f]+:	66 a3 90 90 90 90[ 	]+movw[ 	]+%ax,0x90909090
+ *[0-9a-f]+:	66 a5[ 	]+movsw[ 	]+%ds:\(%esi\),%es:\(%edi\)
+ *[0-9a-f]+:	66 a7[ 	]+cmpsw[ 	]+%es:\(%edi\),%ds:\(%esi\)
+ *[0-9a-f]+:	66 a9 90 90[ 	]+testw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 ab[ 	]+stosw[ 	]+%ax,%es:\(%edi\)
+ *[0-9a-f]+:	66 ad[ 	]+lodsw[ 	]+%ds:\(%esi\),%ax
+ *[0-9a-f]+:	66 af[ 	]+scasw[ 	]+%es:\(%edi\),%ax
+ *[0-9a-f]+:	66 b8 90 90[ 	]+movw[ 	]+\$0x9090,%ax
+ *[0-9a-f]+:	66 b9 90 90[ 	]+movw[ 	]+\$0x9090,%cx
+ *[0-9a-f]+:	66 ba 90 90[ 	]+movw[ 	]+\$0x9090,%dx
+ *[0-9a-f]+:	66 bb 90 90[ 	]+movw[ 	]+\$0x9090,%bx
+ *[0-9a-f]+:	66 bc 90 90[ 	]+movw[ 	]+\$0x9090,%sp
+ *[0-9a-f]+:	66 bd 90 90[ 	]+movw[ 	]+\$0x9090,%bp
+ *[0-9a-f]+:	66 be 90 90[ 	]+movw[ 	]+\$0x9090,%si
+ *[0-9a-f]+:	66 bf 90 90[ 	]+movw[ 	]+\$0x9090,%di
+ *[0-9a-f]+:	66 c1 90 90 90 90 90 90[ 	]+rclw[ 	]+\$0x90,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 c2 90 90[ 	]+retw[ 	]+\$0x9090
+ *[0-9a-f]+:	66 c3[ 	]+retw[ 	]+
+ *[0-9a-f]+:	66 c4 90 90 90 90 90[ 	]+lesw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 c5 90 90 90 90 90[ 	]+ldsw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 c7 80 90 90 90 90 90 90[ 	]+movw[ 	]+\$0x9090,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 c8 90 90 90[ 	]+enterw \$0x9090,\$0x90
+ *[0-9a-f]+:	66 c9[ 	]+leavew 
+ *[0-9a-f]+:	66 ca 90 90[ 	]+lretw[ 	]+\$0x9090
+ *[0-9a-f]+:	66 cb[ 	]+lretw[ 	]+
+ *[0-9a-f]+:	66 cf[ 	]+iretw[ 	]+
+ *[0-9a-f]+:	66 d1 90 90 90 90 90[ 	]+rclw[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 d3 90 90 90 90 90[ 	]+rclw[ 	]+%cl,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 e5 90[ 	]+inw[ 	]+\$0x90,%ax
+ *[0-9a-f]+:	66 e7 90[ 	]+outw[ 	]+%ax,\$0x90
+ *[0-9a-f]+:	66 e8 8f 90[ 	]+callw[ 	]+(0x)?9918.*
+ *[0-9a-f]+:	66 ea 90 90 90 90[ 	]+ljmpw[ 	]+\$0x9090,\$0x9090
+ *[0-9a-f]+:	66 ed[ 	]+inw[ 	]+\(%dx\),%ax
+ *[0-9a-f]+:	66 ef[ 	]+outw[ 	]+%ax,\(%dx\)
+ *[0-9a-f]+:	66 f7 90 90 90 90 90[ 	]+notw[ 	]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 ff 90 90 90 90 90[ 	]+callw[ 	]+\*-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f 02 90 90 90 90 90[ 	]+larw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 03 90 90 90 90 90[ 	]+lslw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 40 90 90 90 90 90[ 	]+cmovo[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 41 90 90 90 90 90[ 	]+cmovno -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 42 90 90 90 90 90[ 	]+cmovb[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 43 90 90 90 90 90[ 	]+cmovae -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 44 90 90 90 90 90[ 	]+cmove[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 45 90 90 90 90 90[ 	]+cmovne -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 46 90 90 90 90 90[ 	]+cmovbe -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 47 90 90 90 90 90[ 	]+cmova[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 48 90 90 90 90 90[ 	]+cmovs[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 49 90 90 90 90 90[ 	]+cmovns -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4a 90 90 90 90 90[ 	]+cmovp[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4b 90 90 90 90 90[ 	]+cmovnp -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4c 90 90 90 90 90[ 	]+cmovl[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4d 90 90 90 90 90[ 	]+cmovge -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4e 90 90 90 90 90[ 	]+cmovle -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f 4f 90 90 90 90 90[ 	]+cmovg[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f a0[ 	]+pushw[ 	]+%fs
+ *[0-9a-f]+:	66 0f a1[ 	]+popw[ 	]+%fs
+ *[0-9a-f]+:	66 0f a3 90 90 90 90 90[ 	]+btw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f a4 90 90 90 90 90 90[ 	]+shldw[ 	]+\$0x90,%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f a5 90 90 90 90 90[ 	]+shldw[ 	]+%cl,%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f a8[ 	]+pushw[ 	]+%gs
+ *[0-9a-f]+:	66 0f a9[ 	]+popw[ 	]+%gs
+ *[0-9a-f]+:	66 0f ab 90 90 90 90 90[ 	]+btsw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f ac 90 90 90 90 90 90[ 	]+shrdw[ 	]+\$0x90,%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f ad 90 90 90 90 90[ 	]+shrdw[ 	]+%cl,%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f af 90 90 90 90 90[ 	]+imulw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f b1 90 90 90 90 90[ 	]+cmpxchgw %dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f b2 90 90 90 90 90[ 	]+lssw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f b3 90 90 90 90 90[ 	]+btrw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f b4 90 90 90 90 90[ 	]+lfsw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f b5 90 90 90 90 90[ 	]+lgsw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f b6 90 90 90 90 90[ 	]+movzbw -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f bb 90 90 90 90 90[ 	]+btcw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 0f bc 90 90 90 90 90[ 	]+bsfw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f bd 90 90 90 90 90[ 	]+bsrw[ 	]+-0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f be 90 90 90 90 90[ 	]+movsbw -0x6f6f6f70\(%eax\),%dx
+ *[0-9a-f]+:	66 0f c1 90 90 90 90 90[ 	]+xaddw[ 	]+%dx,-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+:	66 90[ 	]+xchgw[ 	]+%ax,%ax
+ *[0-9a-f]+:	0f 00 c0[ 	]+sldtl[ 	]+%eax
+ *[0-9a-f]+:	66 0f 00 c0[ 	]+sldtw[ 	]+%ax
+ *[0-9a-f]+:	0f 00 00[ 	]+sldtw[ 	]+\(%eax\)
+ *[0-9a-f]+:	0f 01 e0[ 	]+smswl[ 	]+%eax
+ *[0-9a-f]+:	66 0f 01 e0[ 	]+smsww[ 	]+%ax
+ *[0-9a-f]+:	0f 01 20[ 	]+smsww[ 	]+\(%eax\)
+ *[0-9a-f]+:	0f 00 c8[ 	]+strl[ 	]+%eax
+ *[0-9a-f]+:	66 0f 00 c8[ 	]+strw[ 	]+%ax
+ *[0-9a-f]+:	0f 00 08[ 	]+strw[ 	]+\(%eax\)
+ *[0-9a-f]+:	0f ad d0 [ 	]*shrdl[ 	]+%cl,%edx,%eax
+ *[0-9a-f]+:	0f a5 d0 [ 	]*shldl[ 	]+%cl,%edx,%eax
+ *[0-9a-f]+:	85 c3 [ 	]*testl[ 	]+%eax,%ebx
+ *[0-9a-f]+:	85 d8 [ 	]*testl[ 	]+%ebx,%eax
+ *[0-9a-f]+:	85 18 [ 	]*testl[ 	]+%ebx,\(%eax\)
+#pass
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index 808ddc5371a4..5683895d0dc3 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -1,68 +1,68 @@
 #as: -J
 #objdump: -dw
-#name: i386 intel
+#name: i386 opcodes
 
 .*: +file format .*
 
 Disassembly of section .text:
 
 0+000 <foo>:
-   0:	00 90 90 90 90 90 [ 	]*add    %dl,0x90909090\(%eax\)
-   6:	01 90 90 90 90 90 [ 	]*add    %edx,0x90909090\(%eax\)
-   c:	02 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%dl
-  12:	03 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%edx
+   0:	00 90 90 90 90 90 [ 	]*add    %dl,-0x6f6f6f70\(%eax\)
+   6:	01 90 90 90 90 90 [ 	]*add    %edx,-0x6f6f6f70\(%eax\)
+   c:	02 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%dl
+  12:	03 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%edx
   18:	04 90 [ 	]*add    \$0x90,%al
   1a:	05 90 90 90 90 [ 	]*add    \$0x90909090,%eax
   1f:	06 [ 	]*push   %es
   20:	07 [ 	]*pop    %es
-  21:	08 90 90 90 90 90 [ 	]*or     %dl,0x90909090\(%eax\)
-  27:	09 90 90 90 90 90 [ 	]*or     %edx,0x90909090\(%eax\)
-  2d:	0a 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%dl
-  33:	0b 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%edx
+  21:	08 90 90 90 90 90 [ 	]*or     %dl,-0x6f6f6f70\(%eax\)
+  27:	09 90 90 90 90 90 [ 	]*or     %edx,-0x6f6f6f70\(%eax\)
+  2d:	0a 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%dl
+  33:	0b 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%edx
   39:	0c 90 [ 	]*or     \$0x90,%al
   3b:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
   40:	0e [ 	]*push   %cs
-  41:	10 90 90 90 90 90 [ 	]*adc    %dl,0x90909090\(%eax\)
-  47:	11 90 90 90 90 90 [ 	]*adc    %edx,0x90909090\(%eax\)
-  4d:	12 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%dl
-  53:	13 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%edx
+  41:	10 90 90 90 90 90 [ 	]*adc    %dl,-0x6f6f6f70\(%eax\)
+  47:	11 90 90 90 90 90 [ 	]*adc    %edx,-0x6f6f6f70\(%eax\)
+  4d:	12 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%dl
+  53:	13 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%edx
   59:	14 90 [ 	]*adc    \$0x90,%al
   5b:	15 90 90 90 90 [ 	]*adc    \$0x90909090,%eax
   60:	16 [ 	]*push   %ss
   61:	17 [ 	]*pop    %ss
-  62:	18 90 90 90 90 90 [ 	]*sbb    %dl,0x90909090\(%eax\)
-  68:	19 90 90 90 90 90 [ 	]*sbb    %edx,0x90909090\(%eax\)
-  6e:	1a 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%dl
-  74:	1b 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%edx
+  62:	18 90 90 90 90 90 [ 	]*sbb    %dl,-0x6f6f6f70\(%eax\)
+  68:	19 90 90 90 90 90 [ 	]*sbb    %edx,-0x6f6f6f70\(%eax\)
+  6e:	1a 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%dl
+  74:	1b 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%edx
   7a:	1c 90 [ 	]*sbb    \$0x90,%al
   7c:	1d 90 90 90 90 [ 	]*sbb    \$0x90909090,%eax
   81:	1e [ 	]*push   %ds
   82:	1f [ 	]*pop    %ds
-  83:	20 90 90 90 90 90 [ 	]*and    %dl,0x90909090\(%eax\)
-  89:	21 90 90 90 90 90 [ 	]*and    %edx,0x90909090\(%eax\)
-  8f:	22 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%dl
-  95:	23 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%edx
+  83:	20 90 90 90 90 90 [ 	]*and    %dl,-0x6f6f6f70\(%eax\)
+  89:	21 90 90 90 90 90 [ 	]*and    %edx,-0x6f6f6f70\(%eax\)
+  8f:	22 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%dl
+  95:	23 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%edx
   9b:	24 90 [ 	]*and    \$0x90,%al
   9d:	25 90 90 90 90 [ 	]*and    \$0x90909090,%eax
   a2:	27 [ 	]*daa    
-  a3:	28 90 90 90 90 90 [ 	]*sub    %dl,0x90909090\(%eax\)
-  a9:	29 90 90 90 90 90 [ 	]*sub    %edx,0x90909090\(%eax\)
-  af:	2a 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%dl
-  b5:	2b 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%edx
+  a3:	28 90 90 90 90 90 [ 	]*sub    %dl,-0x6f6f6f70\(%eax\)
+  a9:	29 90 90 90 90 90 [ 	]*sub    %edx,-0x6f6f6f70\(%eax\)
+  af:	2a 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%dl
+  b5:	2b 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%edx
   bb:	2c 90 [ 	]*sub    \$0x90,%al
   bd:	2d 90 90 90 90 [ 	]*sub    \$0x90909090,%eax
   c2:	2f [ 	]*das    
-  c3:	30 90 90 90 90 90 [ 	]*xor    %dl,0x90909090\(%eax\)
-  c9:	31 90 90 90 90 90 [ 	]*xor    %edx,0x90909090\(%eax\)
-  cf:	32 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%dl
-  d5:	33 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%edx
+  c3:	30 90 90 90 90 90 [ 	]*xor    %dl,-0x6f6f6f70\(%eax\)
+  c9:	31 90 90 90 90 90 [ 	]*xor    %edx,-0x6f6f6f70\(%eax\)
+  cf:	32 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%dl
+  d5:	33 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%edx
   db:	34 90 [ 	]*xor    \$0x90,%al
   dd:	35 90 90 90 90 [ 	]*xor    \$0x90909090,%eax
   e2:	37 [ 	]*aaa    
-  e3:	38 90 90 90 90 90 [ 	]*cmp    %dl,0x90909090\(%eax\)
-  e9:	39 90 90 90 90 90 [ 	]*cmp    %edx,0x90909090\(%eax\)
-  ef:	3a 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%dl
-  f5:	3b 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%edx
+  e3:	38 90 90 90 90 90 [ 	]*cmp    %dl,-0x6f6f6f70\(%eax\)
+  e9:	39 90 90 90 90 90 [ 	]*cmp    %edx,-0x6f6f6f70\(%eax\)
+  ef:	3a 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%dl
+  f5:	3b 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%edx
   fb:	3c 90 [ 	]*cmp    \$0x90,%al
   fd:	3d 90 90 90 90 [ 	]*cmp    \$0x90909090,%eax
  102:	3f [ 	]*aas    
@@ -100,12 +100,12 @@ Disassembly of section .text:
  122:	5f [ 	]*pop    %edi
  123:	60 [ 	]*pusha  
  124:	61 [ 	]*popa   
- 125:	62 90 90 90 90 90 [ 	]*bound  %edx,0x90909090\(%eax\)
- 12b:	63 90 90 90 90 90 [ 	]*arpl   %dx,0x90909090\(%eax\)
+ 125:	62 90 90 90 90 90 [ 	]*bound  %edx,-0x6f6f6f70\(%eax\)
+ 12b:	63 90 90 90 90 90 [ 	]*arpl   %dx,-0x6f6f6f70\(%eax\)
  131:	68 90 90 90 90 [ 	]*push   \$0x90909090
- 136:	69 90 90 90 90 90 90 90 90 90 [ 	]*imul   \$0x90909090,0x90909090\(%eax\),%edx
+ 136:	69 90 90 90 90 90 90 90 90 90 [ 	]*imul   \$0x90909090,-0x6f6f6f70\(%eax\),%edx
  140:	6a 90 [ 	]*push   \$0xffffff90
- 142:	6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,0x90909090\(%eax\),%edx
+ 142:	6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,-0x6f6f6f70\(%eax\),%edx
  149:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
  14a:	6d [ 	]*insl   \(%dx\),%es:\(%edi\)
  14b:	6e [ 	]*outsb  %ds:\(%esi\),\(%dx\)
@@ -126,21 +126,21 @@ Disassembly of section .text:
  167:	7d 90 [ 	]*jge    (0x)?f9.*
  169:	7e 90 [ 	]*jle    (0x)?fb.*
  16b:	7f 90 [ 	]*jg     (0x)?fd.*
- 16d:	80 90 90 90 90 90 90 [ 	]*adcb   \$0x90,0x90909090\(%eax\)
- 174:	81 90 90 90 90 90 90 90 90 90 [ 	]*adcl   \$0x90909090,0x90909090\(%eax\)
- 17e:	83 90 90 90 90 90 90 [ 	]*adcl   \$0xffffff90,0x90909090\(%eax\)
- 185:	84 90 90 90 90 90 [ 	]*test   %dl,0x90909090\(%eax\)
- 18b:	85 90 90 90 90 90 [ 	]*test   %edx,0x90909090\(%eax\)
- 191:	86 90 90 90 90 90 [ 	]*xchg   %dl,0x90909090\(%eax\)
- 197:	87 90 90 90 90 90 [ 	]*xchg   %edx,0x90909090\(%eax\)
- 19d:	88 90 90 90 90 90 [ 	]*mov    %dl,0x90909090\(%eax\)
- 1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,0x90909090\(%eax\)
- 1a9:	8a 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dl
- 1af:	8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%edx
- 1b5:	8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 1bb:	8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%edx
- 1c1:	8e 90 90 90 90 90 [ 	]*movw   0x90909090\(%eax\),%ss
- 1c7:	8f 80 90 90 90 90 [ 	]*popl   0x90909090\(%eax\)
+ 16d:	80 90 90 90 90 90 90 [ 	]*adcb   \$0x90,-0x6f6f6f70\(%eax\)
+ 174:	81 90 90 90 90 90 90 90 90 90 [ 	]*adcl   \$0x90909090,-0x6f6f6f70\(%eax\)
+ 17e:	83 90 90 90 90 90 90 [ 	]*adcl   \$0xffffff90,-0x6f6f6f70\(%eax\)
+ 185:	84 90 90 90 90 90 [ 	]*test   %dl,-0x6f6f6f70\(%eax\)
+ 18b:	85 90 90 90 90 90 [ 	]*test   %edx,-0x6f6f6f70\(%eax\)
+ 191:	86 90 90 90 90 90 [ 	]*xchg   %dl,-0x6f6f6f70\(%eax\)
+ 197:	87 90 90 90 90 90 [ 	]*xchg   %edx,-0x6f6f6f70\(%eax\)
+ 19d:	88 90 90 90 90 90 [ 	]*mov    %dl,-0x6f6f6f70\(%eax\)
+ 1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,-0x6f6f6f70\(%eax\)
+ 1a9:	8a 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%dl
+ 1af:	8b 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%edx
+ 1b5:	8c 90 90 90 90 90 [ 	]*mov    %ss,-0x6f6f6f70\(%eax\)
+ 1bb:	8d 90 90 90 90 90 [ 	]*lea    -0x6f6f6f70\(%eax\),%edx
+ 1c1:	8e 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%ss
+ 1c7:	8f 80 90 90 90 90 [ 	]*popl   -0x6f6f6f70\(%eax\)
  1cd:	90 [ 	]*nop    
  1ce:	91 [ 	]*xchg   %eax,%ecx
  1cf:	92 [ 	]*xchg   %eax,%edx
@@ -189,14 +189,14 @@ Disassembly of section .text:
  231:	bd 90 90 90 90 [ 	]*mov    \$0x90909090,%ebp
  236:	be 90 90 90 90 [ 	]*mov    \$0x90909090,%esi
  23b:	bf 90 90 90 90 [ 	]*mov    \$0x90909090,%edi
- 240:	c0 90 90 90 90 90 90 [ 	]*rclb   \$0x90,0x90909090\(%eax\)
- 247:	c1 90 90 90 90 90 90 [ 	]*rcll   \$0x90,0x90909090\(%eax\)
+ 240:	c0 90 90 90 90 90 90 [ 	]*rclb   \$0x90,-0x6f6f6f70\(%eax\)
+ 247:	c1 90 90 90 90 90 90 [ 	]*rcll   \$0x90,-0x6f6f6f70\(%eax\)
  24e:	c2 90 90 [ 	]*ret    \$0x9090
  251:	c3 [ 	]*ret    
- 252:	c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%edx
- 258:	c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%edx
- 25e:	c6 80 90 90 90 90 90 [ 	]*movb   \$0x90,0x90909090\(%eax\)
- 265:	c7 80 90 90 90 90 90 90 90 90 [ 	]*movl   \$0x90909090,0x90909090\(%eax\)
+ 252:	c4 90 90 90 90 90 [ 	]*les    -0x6f6f6f70\(%eax\),%edx
+ 258:	c5 90 90 90 90 90 [ 	]*lds    -0x6f6f6f70\(%eax\),%edx
+ 25e:	c6 80 90 90 90 90 90 [ 	]*movb   \$0x90,-0x6f6f6f70\(%eax\)
+ 265:	c7 80 90 90 90 90 90 90 90 90 [ 	]*movl   \$0x90909090,-0x6f6f6f70\(%eax\)
  26f:	c8 90 90 90 [ 	]*enter  \$0x9090,\$0x90
  273:	c9 [ 	]*leave  
  274:	ca 90 90 [ 	]*lret   \$0x9090
@@ -205,21 +205,21 @@ Disassembly of section .text:
  279:	cd 90 [ 	]*int    \$0x90
  27b:	ce [ 	]*into   
  27c:	cf [ 	]*iret   
- 27d:	d0 90 90 90 90 90 [ 	]*rclb   0x90909090\(%eax\)
- 283:	d1 90 90 90 90 90 [ 	]*rcll   0x90909090\(%eax\)
- 289:	d2 90 90 90 90 90 [ 	]*rclb   %cl,0x90909090\(%eax\)
- 28f:	d3 90 90 90 90 90 [ 	]*rcll   %cl,0x90909090\(%eax\)
+ 27d:	d0 90 90 90 90 90 [ 	]*rclb   -0x6f6f6f70\(%eax\)
+ 283:	d1 90 90 90 90 90 [ 	]*rcll   -0x6f6f6f70\(%eax\)
+ 289:	d2 90 90 90 90 90 [ 	]*rclb   %cl,-0x6f6f6f70\(%eax\)
+ 28f:	d3 90 90 90 90 90 [ 	]*rcll   %cl,-0x6f6f6f70\(%eax\)
  295:	d4 90 [ 	]*aam    \$0xffffff90
  297:	d5 90 [ 	]*aad    \$0xffffff90
  299:	d7 [ 	]*xlat   %ds:\(%ebx\)
- 29a:	d8 90 90 90 90 90 [ 	]*fcoms  0x90909090\(%eax\)
- 2a0:	d9 90 90 90 90 90 [ 	]*fsts   0x90909090\(%eax\)
- 2a6:	da 90 90 90 90 90 [ 	]*ficoml 0x90909090\(%eax\)
- 2ac:	db 90 90 90 90 90 [ 	]*fistl  0x90909090\(%eax\)
- 2b2:	dc 90 90 90 90 90 [ 	]*fcoml  0x90909090\(%eax\)
- 2b8:	dd 90 90 90 90 90 [ 	]*fstl   0x90909090\(%eax\)
- 2be:	de 90 90 90 90 90 [ 	]*ficom  0x90909090\(%eax\)
- 2c4:	df 90 90 90 90 90 [ 	]*fist   0x90909090\(%eax\)
+ 29a:	d8 90 90 90 90 90 [ 	]*fcoms  -0x6f6f6f70\(%eax\)
+ 2a0:	d9 90 90 90 90 90 [ 	]*fsts   -0x6f6f6f70\(%eax\)
+ 2a6:	da 90 90 90 90 90 [ 	]*ficoml -0x6f6f6f70\(%eax\)
+ 2ac:	db 90 90 90 90 90 [ 	]*fistl  -0x6f6f6f70\(%eax\)
+ 2b2:	dc 90 90 90 90 90 [ 	]*fcoml  -0x6f6f6f70\(%eax\)
+ 2b8:	dd 90 90 90 90 90 [ 	]*fstl   -0x6f6f6f70\(%eax\)
+ 2be:	de 90 90 90 90 90 [ 	]*ficom  -0x6f6f6f70\(%eax\)
+ 2c4:	df 90 90 90 90 90 [ 	]*fist   -0x6f6f6f70\(%eax\)
  2ca:	e0 90 [ 	]*loopne (0x)?25c.*
  2cc:	e1 90 [ 	]*loope  (0x)?25e.*
  2ce:	e2 90 [ 	]*loop   (0x)?260.*
@@ -238,19 +238,19 @@ Disassembly of section .text:
  2f0:	ef [ 	]*out    %eax,\(%dx\)
  2f1:	f4 [ 	]*hlt    
  2f2:	f5 [ 	]*cmc    
- 2f3:	f6 90 90 90 90 90 [ 	]*notb   0x90909090\(%eax\)
- 2f9:	f7 90 90 90 90 90 [ 	]*notl   0x90909090\(%eax\)
+ 2f3:	f6 90 90 90 90 90 [ 	]*notb   -0x6f6f6f70\(%eax\)
+ 2f9:	f7 90 90 90 90 90 [ 	]*notl   -0x6f6f6f70\(%eax\)
  2ff:	f8 [ 	]*clc    
  300:	f9 [ 	]*stc    
  301:	fa [ 	]*cli    
  302:	fb [ 	]*sti    
  303:	fc [ 	]*cld    
  304:	fd [ 	]*std    
- 305:	ff 90 90 90 90 90 [ 	]*call   \*0x90909090\(%eax\)
- 30b:	0f 00 90 90 90 90 90 [ 	]*lldt   0x90909090\(%eax\)
- 312:	0f 01 90 90 90 90 90 [ 	]*lgdtl  0x90909090\(%eax\)
- 319:	0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%edx
- 320:	0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%edx
+ 305:	ff 90 90 90 90 90 [ 	]*call   \*-0x6f6f6f70\(%eax\)
+ 30b:	0f 00 90 90 90 90 90 [ 	]*lldt   -0x6f6f6f70\(%eax\)
+ 312:	0f 01 90 90 90 90 90 [ 	]*lgdtl  -0x6f6f6f70\(%eax\)
+ 319:	0f 02 90 90 90 90 90 [ 	]*lar    -0x6f6f6f70\(%eax\),%edx
+ 320:	0f 03 90 90 90 90 90 [ 	]*lsl    -0x6f6f6f70\(%eax\),%edx
  327:	0f 06 [ 	]*clts   
  329:	0f 08 [ 	]*invd   
  32b:	0f 09 [ 	]*wbinvd 
@@ -265,45 +265,45 @@ Disassembly of section .text:
  343:	0f 31 [ 	]*rdtsc  
  345:	0f 32 [ 	]*rdmsr  
  347:	0f 33 [ 	]*rdpmc  
- 349:	0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%edx
- 350:	0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%edx
- 357:	0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%edx
- 35e:	0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%edx
- 365:	0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%edx
- 36c:	0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%edx
- 373:	0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%edx
- 37a:	0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%edx
- 381:	0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%edx
- 388:	0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%edx
- 38f:	0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%edx
- 396:	0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%edx
- 39d:	0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%edx
- 3a4:	0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%edx
- 3ab:	0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%edx
- 3b2:	0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%edx
- 3b9:	0f 60 90 90 90 90 90 [ 	]*punpcklbw 0x90909090\(%eax\),%mm2
- 3c0:	0f 61 90 90 90 90 90 [ 	]*punpcklwd 0x90909090\(%eax\),%mm2
- 3c7:	0f 62 90 90 90 90 90 [ 	]*punpckldq 0x90909090\(%eax\),%mm2
- 3ce:	0f 63 90 90 90 90 90 [ 	]*packsswb 0x90909090\(%eax\),%mm2
- 3d5:	0f 64 90 90 90 90 90 [ 	]*pcmpgtb 0x90909090\(%eax\),%mm2
- 3dc:	0f 65 90 90 90 90 90 [ 	]*pcmpgtw 0x90909090\(%eax\),%mm2
- 3e3:	0f 66 90 90 90 90 90 [ 	]*pcmpgtd 0x90909090\(%eax\),%mm2
- 3ea:	0f 67 90 90 90 90 90 [ 	]*packuswb 0x90909090\(%eax\),%mm2
- 3f1:	0f 68 90 90 90 90 90 [ 	]*punpckhbw 0x90909090\(%eax\),%mm2
- 3f8:	0f 69 90 90 90 90 90 [ 	]*punpckhwd 0x90909090\(%eax\),%mm2
- 3ff:	0f 6a 90 90 90 90 90 [ 	]*punpckhdq 0x90909090\(%eax\),%mm2
- 406:	0f 6b 90 90 90 90 90 [ 	]*packssdw 0x90909090\(%eax\),%mm2
- 40d:	0f 6e 90 90 90 90 90 [ 	]*movd   0x90909090\(%eax\),%mm2
- 414:	0f 6f 90 90 90 90 90 [ 	]*movq   0x90909090\(%eax\),%mm2
+ 349:	0f 40 90 90 90 90 90 [ 	]*cmovo  -0x6f6f6f70\(%eax\),%edx
+ 350:	0f 41 90 90 90 90 90 [ 	]*cmovno -0x6f6f6f70\(%eax\),%edx
+ 357:	0f 42 90 90 90 90 90 [ 	]*cmovb  -0x6f6f6f70\(%eax\),%edx
+ 35e:	0f 43 90 90 90 90 90 [ 	]*cmovae -0x6f6f6f70\(%eax\),%edx
+ 365:	0f 44 90 90 90 90 90 [ 	]*cmove  -0x6f6f6f70\(%eax\),%edx
+ 36c:	0f 45 90 90 90 90 90 [ 	]*cmovne -0x6f6f6f70\(%eax\),%edx
+ 373:	0f 46 90 90 90 90 90 [ 	]*cmovbe -0x6f6f6f70\(%eax\),%edx
+ 37a:	0f 47 90 90 90 90 90 [ 	]*cmova  -0x6f6f6f70\(%eax\),%edx
+ 381:	0f 48 90 90 90 90 90 [ 	]*cmovs  -0x6f6f6f70\(%eax\),%edx
+ 388:	0f 49 90 90 90 90 90 [ 	]*cmovns -0x6f6f6f70\(%eax\),%edx
+ 38f:	0f 4a 90 90 90 90 90 [ 	]*cmovp  -0x6f6f6f70\(%eax\),%edx
+ 396:	0f 4b 90 90 90 90 90 [ 	]*cmovnp -0x6f6f6f70\(%eax\),%edx
+ 39d:	0f 4c 90 90 90 90 90 [ 	]*cmovl  -0x6f6f6f70\(%eax\),%edx
+ 3a4:	0f 4d 90 90 90 90 90 [ 	]*cmovge -0x6f6f6f70\(%eax\),%edx
+ 3ab:	0f 4e 90 90 90 90 90 [ 	]*cmovle -0x6f6f6f70\(%eax\),%edx
+ 3b2:	0f 4f 90 90 90 90 90 [ 	]*cmovg  -0x6f6f6f70\(%eax\),%edx
+ 3b9:	0f 60 90 90 90 90 90 [ 	]*punpcklbw -0x6f6f6f70\(%eax\),%mm2
+ 3c0:	0f 61 90 90 90 90 90 [ 	]*punpcklwd -0x6f6f6f70\(%eax\),%mm2
+ 3c7:	0f 62 90 90 90 90 90 [ 	]*punpckldq -0x6f6f6f70\(%eax\),%mm2
+ 3ce:	0f 63 90 90 90 90 90 [ 	]*packsswb -0x6f6f6f70\(%eax\),%mm2
+ 3d5:	0f 64 90 90 90 90 90 [ 	]*pcmpgtb -0x6f6f6f70\(%eax\),%mm2
+ 3dc:	0f 65 90 90 90 90 90 [ 	]*pcmpgtw -0x6f6f6f70\(%eax\),%mm2
+ 3e3:	0f 66 90 90 90 90 90 [ 	]*pcmpgtd -0x6f6f6f70\(%eax\),%mm2
+ 3ea:	0f 67 90 90 90 90 90 [ 	]*packuswb -0x6f6f6f70\(%eax\),%mm2
+ 3f1:	0f 68 90 90 90 90 90 [ 	]*punpckhbw -0x6f6f6f70\(%eax\),%mm2
+ 3f8:	0f 69 90 90 90 90 90 [ 	]*punpckhwd -0x6f6f6f70\(%eax\),%mm2
+ 3ff:	0f 6a 90 90 90 90 90 [ 	]*punpckhdq -0x6f6f6f70\(%eax\),%mm2
+ 406:	0f 6b 90 90 90 90 90 [ 	]*packssdw -0x6f6f6f70\(%eax\),%mm2
+ 40d:	0f 6e 90 90 90 90 90 [ 	]*movd   -0x6f6f6f70\(%eax\),%mm2
+ 414:	0f 6f 90 90 90 90 90 [ 	]*movq   -0x6f6f6f70\(%eax\),%mm2
  41b:	0f 71 d0 90 [ 	]*psrlw  \$0x90,%mm0
  41f:	0f 72 d0 90 [ 	]*psrld  \$0x90,%mm0
  423:	0f 73 d0 90 [ 	]*psrlq  \$0x90,%mm0
- 427:	0f 74 90 90 90 90 90 [ 	]*pcmpeqb 0x90909090\(%eax\),%mm2
- 42e:	0f 75 90 90 90 90 90 [ 	]*pcmpeqw 0x90909090\(%eax\),%mm2
- 435:	0f 76 90 90 90 90 90 [ 	]*pcmpeqd 0x90909090\(%eax\),%mm2
+ 427:	0f 74 90 90 90 90 90 [ 	]*pcmpeqb -0x6f6f6f70\(%eax\),%mm2
+ 42e:	0f 75 90 90 90 90 90 [ 	]*pcmpeqw -0x6f6f6f70\(%eax\),%mm2
+ 435:	0f 76 90 90 90 90 90 [ 	]*pcmpeqd -0x6f6f6f70\(%eax\),%mm2
  43c:	0f 77 [ 	]*emms   
- 43e:	0f 7e 90 90 90 90 90 [ 	]*movd   %mm2,0x90909090\(%eax\)
- 445:	0f 7f 90 90 90 90 90 [ 	]*movq   %mm2,0x90909090\(%eax\)
+ 43e:	0f 7e 90 90 90 90 90 [ 	]*movd   %mm2,-0x6f6f6f70\(%eax\)
+ 445:	0f 7f 90 90 90 90 90 [ 	]*movq   %mm2,-0x6f6f6f70\(%eax\)
  44c:	0f 80 90 90 90 90 [ 	]*jo     (0x)?909094e2.*
  452:	0f 81 90 90 90 90 [ 	]*jno    (0x)?909094e8.*
  458:	0f 82 90 90 90 90 [ 	]*jb     (0x)?909094ee.*
@@ -320,51 +320,51 @@ Disassembly of section .text:
  49a:	0f 8d 90 90 90 90 [ 	]*jge    (0x)?90909530.*
  4a0:	0f 8e 90 90 90 90 [ 	]*jle    (0x)?90909536.*
  4a6:	0f 8f 90 90 90 90 [ 	]*jg     (0x)?9090953c.*
- 4ac:	0f 90 80 90 90 90 90 [ 	]*seto   0x90909090\(%eax\)
- 4b3:	0f 91 80 90 90 90 90 [ 	]*setno  0x90909090\(%eax\)
- 4ba:	0f 92 80 90 90 90 90 [ 	]*setb   0x90909090\(%eax\)
- 4c1:	0f 93 80 90 90 90 90 [ 	]*setae  0x90909090\(%eax\)
- 4c8:	0f 94 80 90 90 90 90 [ 	]*sete   0x90909090\(%eax\)
- 4cf:	0f 95 80 90 90 90 90 [ 	]*setne  0x90909090\(%eax\)
- 4d6:	0f 96 80 90 90 90 90 [ 	]*setbe  0x90909090\(%eax\)
- 4dd:	0f 97 80 90 90 90 90 [ 	]*seta   0x90909090\(%eax\)
- 4e4:	0f 98 80 90 90 90 90 [ 	]*sets   0x90909090\(%eax\)
- 4eb:	0f 99 80 90 90 90 90 [ 	]*setns  0x90909090\(%eax\)
- 4f2:	0f 9a 80 90 90 90 90 [ 	]*setp   0x90909090\(%eax\)
- 4f9:	0f 9b 80 90 90 90 90 [ 	]*setnp  0x90909090\(%eax\)
- 500:	0f 9c 80 90 90 90 90 [ 	]*setl   0x90909090\(%eax\)
- 507:	0f 9d 80 90 90 90 90 [ 	]*setge  0x90909090\(%eax\)
- 50e:	0f 9e 80 90 90 90 90 [ 	]*setle  0x90909090\(%eax\)
- 515:	0f 9f 80 90 90 90 90 [ 	]*setg   0x90909090\(%eax\)
+ 4ac:	0f 90 80 90 90 90 90 [ 	]*seto   -0x6f6f6f70\(%eax\)
+ 4b3:	0f 91 80 90 90 90 90 [ 	]*setno  -0x6f6f6f70\(%eax\)
+ 4ba:	0f 92 80 90 90 90 90 [ 	]*setb   -0x6f6f6f70\(%eax\)
+ 4c1:	0f 93 80 90 90 90 90 [ 	]*setae  -0x6f6f6f70\(%eax\)
+ 4c8:	0f 94 80 90 90 90 90 [ 	]*sete   -0x6f6f6f70\(%eax\)
+ 4cf:	0f 95 80 90 90 90 90 [ 	]*setne  -0x6f6f6f70\(%eax\)
+ 4d6:	0f 96 80 90 90 90 90 [ 	]*setbe  -0x6f6f6f70\(%eax\)
+ 4dd:	0f 97 80 90 90 90 90 [ 	]*seta   -0x6f6f6f70\(%eax\)
+ 4e4:	0f 98 80 90 90 90 90 [ 	]*sets   -0x6f6f6f70\(%eax\)
+ 4eb:	0f 99 80 90 90 90 90 [ 	]*setns  -0x6f6f6f70\(%eax\)
+ 4f2:	0f 9a 80 90 90 90 90 [ 	]*setp   -0x6f6f6f70\(%eax\)
+ 4f9:	0f 9b 80 90 90 90 90 [ 	]*setnp  -0x6f6f6f70\(%eax\)
+ 500:	0f 9c 80 90 90 90 90 [ 	]*setl   -0x6f6f6f70\(%eax\)
+ 507:	0f 9d 80 90 90 90 90 [ 	]*setge  -0x6f6f6f70\(%eax\)
+ 50e:	0f 9e 80 90 90 90 90 [ 	]*setle  -0x6f6f6f70\(%eax\)
+ 515:	0f 9f 80 90 90 90 90 [ 	]*setg   -0x6f6f6f70\(%eax\)
  51c:	0f a0 [ 	]*push   %fs
  51e:	0f a1 [ 	]*pop    %fs
  520:	0f a2 [ 	]*cpuid  
- 522:	0f a3 90 90 90 90 90 [ 	]*bt     %edx,0x90909090\(%eax\)
- 529:	0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%edx,0x90909090\(%eax\)
- 531:	0f a5 90 90 90 90 90 [ 	]*shld   %cl,%edx,0x90909090\(%eax\)
+ 522:	0f a3 90 90 90 90 90 [ 	]*bt     %edx,-0x6f6f6f70\(%eax\)
+ 529:	0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%edx,-0x6f6f6f70\(%eax\)
+ 531:	0f a5 90 90 90 90 90 [ 	]*shld   %cl,%edx,-0x6f6f6f70\(%eax\)
  538:	0f a8 [ 	]*push   %gs
  53a:	0f a9 [ 	]*pop    %gs
  53c:	0f aa [ 	]*rsm    
- 53e:	0f ab 90 90 90 90 90 [ 	]*bts    %edx,0x90909090\(%eax\)
- 545:	0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%edx,0x90909090\(%eax\)
- 54d:	0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%edx,0x90909090\(%eax\)
- 554:	0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%edx
- 55b:	0f b0 90 90 90 90 90 [ 	]*cmpxchg %dl,0x90909090\(%eax\)
- 562:	0f b1 90 90 90 90 90 [ 	]*cmpxchg %edx,0x90909090\(%eax\)
- 569:	0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%edx
- 570:	0f b3 90 90 90 90 90 [ 	]*btr    %edx,0x90909090\(%eax\)
- 577:	0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%edx
- 57e:	0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%edx
- 585:	0f b6 90 90 90 90 90 [ 	]*movzbl 0x90909090\(%eax\),%edx
- 58c:	0f b7 90 90 90 90 90 [ 	]*movzwl 0x90909090\(%eax\),%edx
+ 53e:	0f ab 90 90 90 90 90 [ 	]*bts    %edx,-0x6f6f6f70\(%eax\)
+ 545:	0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%edx,-0x6f6f6f70\(%eax\)
+ 54d:	0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%edx,-0x6f6f6f70\(%eax\)
+ 554:	0f af 90 90 90 90 90 [ 	]*imul   -0x6f6f6f70\(%eax\),%edx
+ 55b:	0f b0 90 90 90 90 90 [ 	]*cmpxchg %dl,-0x6f6f6f70\(%eax\)
+ 562:	0f b1 90 90 90 90 90 [ 	]*cmpxchg %edx,-0x6f6f6f70\(%eax\)
+ 569:	0f b2 90 90 90 90 90 [ 	]*lss    -0x6f6f6f70\(%eax\),%edx
+ 570:	0f b3 90 90 90 90 90 [ 	]*btr    %edx,-0x6f6f6f70\(%eax\)
+ 577:	0f b4 90 90 90 90 90 [ 	]*lfs    -0x6f6f6f70\(%eax\),%edx
+ 57e:	0f b5 90 90 90 90 90 [ 	]*lgs    -0x6f6f6f70\(%eax\),%edx
+ 585:	0f b6 90 90 90 90 90 [ 	]*movzbl -0x6f6f6f70\(%eax\),%edx
+ 58c:	0f b7 90 90 90 90 90 [ 	]*movzwl -0x6f6f6f70\(%eax\),%edx
  593:	0f b9 [ 	]*ud2b   
- 595:	0f bb 90 90 90 90 90 [ 	]*btc    %edx,0x90909090\(%eax\)
- 59c:	0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%edx
- 5a3:	0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%edx
- 5aa:	0f be 90 90 90 90 90 [ 	]*movsbl 0x90909090\(%eax\),%edx
- 5b1:	0f bf 90 90 90 90 90 [ 	]*movswl 0x90909090\(%eax\),%edx
- 5b8:	0f c0 90 90 90 90 90 [ 	]*xadd   %dl,0x90909090\(%eax\)
- 5bf:	0f c1 90 90 90 90 90 [ 	]*xadd   %edx,0x90909090\(%eax\)
+ 595:	0f bb 90 90 90 90 90 [ 	]*btc    %edx,-0x6f6f6f70\(%eax\)
+ 59c:	0f bc 90 90 90 90 90 [ 	]*bsf    -0x6f6f6f70\(%eax\),%edx
+ 5a3:	0f bd 90 90 90 90 90 [ 	]*bsr    -0x6f6f6f70\(%eax\),%edx
+ 5aa:	0f be 90 90 90 90 90 [ 	]*movsbl -0x6f6f6f70\(%eax\),%edx
+ 5b1:	0f bf 90 90 90 90 90 [ 	]*movswl -0x6f6f6f70\(%eax\),%edx
+ 5b8:	0f c0 90 90 90 90 90 [ 	]*xadd   %dl,-0x6f6f6f70\(%eax\)
+ 5bf:	0f c1 90 90 90 90 90 [ 	]*xadd   %edx,-0x6f6f6f70\(%eax\)
  5c6:	0f c8 [ 	]*bswap  %eax
  5c8:	0f c9 [ 	]*bswap  %ecx
  5ca:	0f ca [ 	]*bswap  %edx
@@ -373,65 +373,65 @@ Disassembly of section .text:
  5d0:	0f cd [ 	]*bswap  %ebp
  5d2:	0f ce [ 	]*bswap  %esi
  5d4:	0f cf [ 	]*bswap  %edi
- 5d6:	0f d1 90 90 90 90 90 [ 	]*psrlw  0x90909090\(%eax\),%mm2
- 5dd:	0f d2 90 90 90 90 90 [ 	]*psrld  0x90909090\(%eax\),%mm2
- 5e4:	0f d3 90 90 90 90 90 [ 	]*psrlq  0x90909090\(%eax\),%mm2
- 5eb:	0f d5 90 90 90 90 90 [ 	]*pmullw 0x90909090\(%eax\),%mm2
- 5f2:	0f d8 90 90 90 90 90 [ 	]*psubusb 0x90909090\(%eax\),%mm2
- 5f9:	0f d9 90 90 90 90 90 [ 	]*psubusw 0x90909090\(%eax\),%mm2
- 600:	0f db 90 90 90 90 90 [ 	]*pand   0x90909090\(%eax\),%mm2
- 607:	0f dc 90 90 90 90 90 [ 	]*paddusb 0x90909090\(%eax\),%mm2
- 60e:	0f dd 90 90 90 90 90 [ 	]*paddusw 0x90909090\(%eax\),%mm2
- 615:	0f df 90 90 90 90 90 [ 	]*pandn  0x90909090\(%eax\),%mm2
- 61c:	0f e1 90 90 90 90 90 [ 	]*psraw  0x90909090\(%eax\),%mm2
- 623:	0f e2 90 90 90 90 90 [ 	]*psrad  0x90909090\(%eax\),%mm2
- 62a:	0f e5 90 90 90 90 90 [ 	]*pmulhw 0x90909090\(%eax\),%mm2
- 631:	0f e8 90 90 90 90 90 [ 	]*psubsb 0x90909090\(%eax\),%mm2
- 638:	0f e9 90 90 90 90 90 [ 	]*psubsw 0x90909090\(%eax\),%mm2
- 63f:	0f eb 90 90 90 90 90 [ 	]*por    0x90909090\(%eax\),%mm2
- 646:	0f ec 90 90 90 90 90 [ 	]*paddsb 0x90909090\(%eax\),%mm2
- 64d:	0f ed 90 90 90 90 90 [ 	]*paddsw 0x90909090\(%eax\),%mm2
- 654:	0f ef 90 90 90 90 90 [ 	]*pxor   0x90909090\(%eax\),%mm2
- 65b:	0f f1 90 90 90 90 90 [ 	]*psllw  0x90909090\(%eax\),%mm2
- 662:	0f f2 90 90 90 90 90 [ 	]*pslld  0x90909090\(%eax\),%mm2
- 669:	0f f3 90 90 90 90 90 [ 	]*psllq  0x90909090\(%eax\),%mm2
- 670:	0f f5 90 90 90 90 90 [ 	]*pmaddwd 0x90909090\(%eax\),%mm2
- 677:	0f f8 90 90 90 90 90 [ 	]*psubb  0x90909090\(%eax\),%mm2
- 67e:	0f f9 90 90 90 90 90 [ 	]*psubw  0x90909090\(%eax\),%mm2
- 685:	0f fa 90 90 90 90 90 [ 	]*psubd  0x90909090\(%eax\),%mm2
- 68c:	0f fc 90 90 90 90 90 [ 	]*paddb  0x90909090\(%eax\),%mm2
- 693:	0f fd 90 90 90 90 90 [ 	]*paddw  0x90909090\(%eax\),%mm2
- 69a:	0f fe 90 90 90 90 90 [ 	]*paddd  0x90909090\(%eax\),%mm2
- 6a1:	66 01 90 90 90 90 90 [ 	]*add    %dx,0x90909090\(%eax\)
- 6a8:	66 03 90 90 90 90 90 [ 	]*add    0x90909090\(%eax\),%dx
+ 5d6:	0f d1 90 90 90 90 90 [ 	]*psrlw  -0x6f6f6f70\(%eax\),%mm2
+ 5dd:	0f d2 90 90 90 90 90 [ 	]*psrld  -0x6f6f6f70\(%eax\),%mm2
+ 5e4:	0f d3 90 90 90 90 90 [ 	]*psrlq  -0x6f6f6f70\(%eax\),%mm2
+ 5eb:	0f d5 90 90 90 90 90 [ 	]*pmullw -0x6f6f6f70\(%eax\),%mm2
+ 5f2:	0f d8 90 90 90 90 90 [ 	]*psubusb -0x6f6f6f70\(%eax\),%mm2
+ 5f9:	0f d9 90 90 90 90 90 [ 	]*psubusw -0x6f6f6f70\(%eax\),%mm2
+ 600:	0f db 90 90 90 90 90 [ 	]*pand   -0x6f6f6f70\(%eax\),%mm2
+ 607:	0f dc 90 90 90 90 90 [ 	]*paddusb -0x6f6f6f70\(%eax\),%mm2
+ 60e:	0f dd 90 90 90 90 90 [ 	]*paddusw -0x6f6f6f70\(%eax\),%mm2
+ 615:	0f df 90 90 90 90 90 [ 	]*pandn  -0x6f6f6f70\(%eax\),%mm2
+ 61c:	0f e1 90 90 90 90 90 [ 	]*psraw  -0x6f6f6f70\(%eax\),%mm2
+ 623:	0f e2 90 90 90 90 90 [ 	]*psrad  -0x6f6f6f70\(%eax\),%mm2
+ 62a:	0f e5 90 90 90 90 90 [ 	]*pmulhw -0x6f6f6f70\(%eax\),%mm2
+ 631:	0f e8 90 90 90 90 90 [ 	]*psubsb -0x6f6f6f70\(%eax\),%mm2
+ 638:	0f e9 90 90 90 90 90 [ 	]*psubsw -0x6f6f6f70\(%eax\),%mm2
+ 63f:	0f eb 90 90 90 90 90 [ 	]*por    -0x6f6f6f70\(%eax\),%mm2
+ 646:	0f ec 90 90 90 90 90 [ 	]*paddsb -0x6f6f6f70\(%eax\),%mm2
+ 64d:	0f ed 90 90 90 90 90 [ 	]*paddsw -0x6f6f6f70\(%eax\),%mm2
+ 654:	0f ef 90 90 90 90 90 [ 	]*pxor   -0x6f6f6f70\(%eax\),%mm2
+ 65b:	0f f1 90 90 90 90 90 [ 	]*psllw  -0x6f6f6f70\(%eax\),%mm2
+ 662:	0f f2 90 90 90 90 90 [ 	]*pslld  -0x6f6f6f70\(%eax\),%mm2
+ 669:	0f f3 90 90 90 90 90 [ 	]*psllq  -0x6f6f6f70\(%eax\),%mm2
+ 670:	0f f5 90 90 90 90 90 [ 	]*pmaddwd -0x6f6f6f70\(%eax\),%mm2
+ 677:	0f f8 90 90 90 90 90 [ 	]*psubb  -0x6f6f6f70\(%eax\),%mm2
+ 67e:	0f f9 90 90 90 90 90 [ 	]*psubw  -0x6f6f6f70\(%eax\),%mm2
+ 685:	0f fa 90 90 90 90 90 [ 	]*psubd  -0x6f6f6f70\(%eax\),%mm2
+ 68c:	0f fc 90 90 90 90 90 [ 	]*paddb  -0x6f6f6f70\(%eax\),%mm2
+ 693:	0f fd 90 90 90 90 90 [ 	]*paddw  -0x6f6f6f70\(%eax\),%mm2
+ 69a:	0f fe 90 90 90 90 90 [ 	]*paddd  -0x6f6f6f70\(%eax\),%mm2
+ 6a1:	66 01 90 90 90 90 90 [ 	]*add    %dx,-0x6f6f6f70\(%eax\)
+ 6a8:	66 03 90 90 90 90 90 [ 	]*add    -0x6f6f6f70\(%eax\),%dx
  6af:	66 05 90 90 [ 	]*add    \$0x9090,%ax
  6b3:	66 06 [ 	]*pushw  %es
  6b5:	66 07 [ 	]*popw   %es
- 6b7:	66 09 90 90 90 90 90 [ 	]*or     %dx,0x90909090\(%eax\)
- 6be:	66 0b 90 90 90 90 90 [ 	]*or     0x90909090\(%eax\),%dx
+ 6b7:	66 09 90 90 90 90 90 [ 	]*or     %dx,-0x6f6f6f70\(%eax\)
+ 6be:	66 0b 90 90 90 90 90 [ 	]*or     -0x6f6f6f70\(%eax\),%dx
  6c5:	66 0d 90 90 [ 	]*or     \$0x9090,%ax
  6c9:	66 0e [ 	]*pushw  %cs
- 6cb:	66 11 90 90 90 90 90 [ 	]*adc    %dx,0x90909090\(%eax\)
- 6d2:	66 13 90 90 90 90 90 [ 	]*adc    0x90909090\(%eax\),%dx
+ 6cb:	66 11 90 90 90 90 90 [ 	]*adc    %dx,-0x6f6f6f70\(%eax\)
+ 6d2:	66 13 90 90 90 90 90 [ 	]*adc    -0x6f6f6f70\(%eax\),%dx
  6d9:	66 15 90 90 [ 	]*adc    \$0x9090,%ax
  6dd:	66 16 [ 	]*pushw  %ss
  6df:	66 17 [ 	]*popw   %ss
- 6e1:	66 19 90 90 90 90 90 [ 	]*sbb    %dx,0x90909090\(%eax\)
- 6e8:	66 1b 90 90 90 90 90 [ 	]*sbb    0x90909090\(%eax\),%dx
+ 6e1:	66 19 90 90 90 90 90 [ 	]*sbb    %dx,-0x6f6f6f70\(%eax\)
+ 6e8:	66 1b 90 90 90 90 90 [ 	]*sbb    -0x6f6f6f70\(%eax\),%dx
  6ef:	66 1d 90 90 [ 	]*sbb    \$0x9090,%ax
  6f3:	66 1e [ 	]*pushw  %ds
  6f5:	66 1f [ 	]*popw   %ds
- 6f7:	66 21 90 90 90 90 90 [ 	]*and    %dx,0x90909090\(%eax\)
- 6fe:	66 23 90 90 90 90 90 [ 	]*and    0x90909090\(%eax\),%dx
+ 6f7:	66 21 90 90 90 90 90 [ 	]*and    %dx,-0x6f6f6f70\(%eax\)
+ 6fe:	66 23 90 90 90 90 90 [ 	]*and    -0x6f6f6f70\(%eax\),%dx
  705:	66 25 90 90 [ 	]*and    \$0x9090,%ax
- 709:	66 29 90 90 90 90 90 [ 	]*sub    %dx,0x90909090\(%eax\)
- 710:	66 2b 90 90 90 90 90 [ 	]*sub    0x90909090\(%eax\),%dx
+ 709:	66 29 90 90 90 90 90 [ 	]*sub    %dx,-0x6f6f6f70\(%eax\)
+ 710:	66 2b 90 90 90 90 90 [ 	]*sub    -0x6f6f6f70\(%eax\),%dx
  717:	66 2d 90 90 [ 	]*sub    \$0x9090,%ax
- 71b:	66 31 90 90 90 90 90 [ 	]*xor    %dx,0x90909090\(%eax\)
- 722:	66 33 90 90 90 90 90 [ 	]*xor    0x90909090\(%eax\),%dx
+ 71b:	66 31 90 90 90 90 90 [ 	]*xor    %dx,-0x6f6f6f70\(%eax\)
+ 722:	66 33 90 90 90 90 90 [ 	]*xor    -0x6f6f6f70\(%eax\),%dx
  729:	66 35 90 90 [ 	]*xor    \$0x9090,%ax
- 72d:	66 39 90 90 90 90 90 [ 	]*cmp    %dx,0x90909090\(%eax\)
- 734:	66 3b 90 90 90 90 90 [ 	]*cmp    0x90909090\(%eax\),%dx
+ 72d:	66 39 90 90 90 90 90 [ 	]*cmp    %dx,-0x6f6f6f70\(%eax\)
+ 734:	66 3b 90 90 90 90 90 [ 	]*cmp    -0x6f6f6f70\(%eax\),%dx
  73b:	66 3d 90 90 [ 	]*cmp    \$0x9090,%ax
  73f:	66 40 [ 	]*inc    %ax
  741:	66 41 [ 	]*inc    %cx
@@ -467,22 +467,22 @@ Disassembly of section .text:
  77d:	66 5f [ 	]*pop    %di
  77f:	66 60 [ 	]*pushaw 
  781:	66 61 [ 	]*popaw  
- 783:	66 62 90 90 90 90 90 [ 	]*bound  %dx,0x90909090\(%eax\)
+ 783:	66 62 90 90 90 90 90 [ 	]*bound  %dx,-0x6f6f6f70\(%eax\)
  78a:	66 68 90 90 [ 	]*pushw  \$0x9090
- 78e:	66 69 90 90 90 90 90 90 90 [ 	]*imul   \$0x9090,0x90909090\(%eax\),%dx
+ 78e:	66 69 90 90 90 90 90 90 90 [ 	]*imul   \$0x9090,-0x6f6f6f70\(%eax\),%dx
  797:	66 6a 90 [ 	]*pushw  \$0xffffff90
- 79a:	66 6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,0x90909090\(%eax\),%dx
+ 79a:	66 6b 90 90 90 90 90 90 [ 	]*imul   \$0xffffff90,-0x6f6f6f70\(%eax\),%dx
  7a2:	66 6d [ 	]*insw   \(%dx\),%es:\(%edi\)
  7a4:	66 6f [ 	]*outsw  %ds:\(%esi\),\(%dx\)
- 7a6:	66 81 90 90 90 90 90 90 90 [ 	]*adcw   \$0x9090,0x90909090\(%eax\)
- 7af:	66 83 90 90 90 90 90 90 [ 	]*adcw   \$0xffffff90,0x90909090\(%eax\)
- 7b7:	66 85 90 90 90 90 90 [ 	]*test   %dx,0x90909090\(%eax\)
- 7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
- 7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
- 7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,0x90909090\(%eax\)
- 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7a6:	66 81 90 90 90 90 90 90 90 [ 	]*adcw   \$0x9090,-0x6f6f6f70\(%eax\)
+ 7af:	66 83 90 90 90 90 90 90 [ 	]*adcw   \$0xffffff90,-0x6f6f6f70\(%eax\)
+ 7b7:	66 85 90 90 90 90 90 [ 	]*test   %dx,-0x6f6f6f70\(%eax\)
+ 7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,-0x6f6f6f70\(%eax\)
+ 7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,-0x6f6f6f70\(%eax\)
+ 7cc:	66 8b 90 90 90 90 90 [ 	]*mov    -0x6f6f6f70\(%eax\),%dx
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,-0x6f6f6f70\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    -0x6f6f6f70\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   -0x6f6f6f70\(%eax\)
  7e7:	66 91 [ 	]*xchg   %ax,%cx
  7e9:	66 92 [ 	]*xchg   %ax,%dx
  7eb:	66 93 [ 	]*xchg   %ax,%bx
@@ -511,65 +511,80 @@ Disassembly of section .text:
  831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
  835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
  839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,-0x6f6f6f70\(%eax\)
  845:	66 c2 90 90 [ 	]*retw   \$0x9090
  849:	66 c3 [ 	]*retw   
- 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    -0x6f6f6f70\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    -0x6f6f6f70\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,-0x6f6f6f70\(%eax\)
  862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
  867:	66 c9 [ 	]*leavew 
  869:	66 ca 90 90 [ 	]*lretw  \$0x9090
  86d:	66 cb [ 	]*lretw  
  86f:	66 cf [ 	]*iretw  
- 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   -0x6f6f6f70\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,-0x6f6f6f70\(%eax\)
  87f:	66 e5 90 [ 	]*in     \$0x90,%ax
  882:	66 e7 90 [ 	]*out    %ax,\$0x90
  885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
  889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
  88f:	66 ed [ 	]*in     \(%dx\),%ax
  891:	66 ef [ 	]*out    %ax,\(%dx\)
- 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   -0x6f6f6f70\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*-0x6f6f6f70\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    -0x6f6f6f70\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    -0x6f6f6f70\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  -0x6f6f6f70\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno -0x6f6f6f70\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  -0x6f6f6f70\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae -0x6f6f6f70\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  -0x6f6f6f70\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne -0x6f6f6f70\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe -0x6f6f6f70\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  -0x6f6f6f70\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  -0x6f6f6f70\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns -0x6f6f6f70\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  -0x6f6f6f70\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp -0x6f6f6f70\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  -0x6f6f6f70\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge -0x6f6f6f70\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle -0x6f6f6f70\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  -0x6f6f6f70\(%eax\),%dx
  931:	66 0f a0 [ 	]*pushw  %fs
  934:	66 0f a1 [ 	]*popw   %fs
- 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,-0x6f6f6f70\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,-0x6f6f6f70\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,-0x6f6f6f70\(%eax\)
  950:	66 0f a8 [ 	]*pushw  %gs
  953:	66 0f a9 [ 	]*popw   %gs
- 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
-	\.\.\.
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,-0x6f6f6f70\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,-0x6f6f6f70\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,-0x6f6f6f70\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   -0x6f6f6f70\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,-0x6f6f6f70\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    -0x6f6f6f70\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,-0x6f6f6f70\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    -0x6f6f6f70\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    -0x6f6f6f70\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw -0x6f6f6f70\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,-0x6f6f6f70\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    -0x6f6f6f70\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    -0x6f6f6f70\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw -0x6f6f6f70\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,-0x6f6f6f70\(%eax\)
+ 9cf:	66 90 [ 	]*xchg   %ax,%ax
+ 9d1:	0f 00 c0 [ 	]*sldt   %eax
+ 9d4:	66 0f 00 c0 [ 	]*sldt   %ax
+ 9d8:	0f 00 00 [ 	]*sldt   \(%eax\)
+ 9db:	0f 01 e0 [ 	]*smsw   %eax
+ 9de:	66 0f 01 e0 [ 	]*smsw   %ax
+ 9e2:	0f 01 20 [ 	]*smsw   \(%eax\)
+ 9e5:	0f 00 c8 [ 	]*str    %eax
+ 9e8:	66 0f 00 c8 [ 	]*str    %ax
+ 9ec:	0f 00 08 [ 	]*str    \(%eax\)
+ 9ef:	0f ad d0 [ 	]*shrd   %cl,%edx,%eax
+ 9f2:	0f a5 d0 [ 	]*shld   %cl,%edx,%eax
+ 9f5:	85 c3 [ 	]*test   %eax,%ebx
+ 9f7:	85 d8 [ 	]*test   %ebx,%eax
+ 9f9:	85 18 [ 	]*test   %ebx,\(%eax\)
+#pass
diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 8d7cd050f165..b54b9fcf89bd 100644
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -566,5 +566,24 @@ foo:
  movsbw 0x90909090(%eax),%dx
  xadd   %dx,0x90909090(%eax)
 
+ xchg   %ax,%ax
+
+ sldt	%eax
+ sldt	%ax
+ sldt	(%eax)
+ smsw	%eax
+ smsw	%ax
+ smsw	(%eax)
+ str	%eax
+ str	%ax
+ str	(%eax)
+
+ shrd   %cl,%edx,%eax
+ shld   %cl,%edx,%eax
+
+ test   %eax,%ebx
+ test   %ebx,%eax
+ test   (%eax),%ebx
+
 # Force a good alignment.
  .p2align 4,0
diff --git a/gas/testsuite/gas/i386/prefix.d b/gas/testsuite/gas/i386/prefix.d
index 229a2a766a30..9021f09e250b 100644
--- a/gas/testsuite/gas/i386/prefix.d
+++ b/gas/testsuite/gas/i386/prefix.d
@@ -6,10 +6,10 @@
 Disassembly of section .text:
 
 0+000 <foo>:
-   0:	9b 67 26 d9 3c [ 	]*addr16 fstcw %es:\(%si\)
+   0:	9b 26 67 d9 3c [ 	]*addr16 fstcw %es:\(%si\)
    5:	9b df e0 [ 	]*fstsw  %ax
    8:	9b df e0 [ 	]*fstsw  %ax
    b:	9b df e0 [ 	]*fstsw  %ax
    e:	9b 67 df e0 [ 	]*addr16 fstsw %ax
-  12:	f3 67 66 36 a7 [ 	]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
+  12:	36 67 66 f3 a7 [ 	]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
 #pass
diff --git a/gas/testsuite/gas/i386/prescott.d b/gas/testsuite/gas/i386/prescott.d
index 1e66065433ac..9b701c007d4b 100644
--- a/gas/testsuite/gas/i386/prescott.d
+++ b/gas/testsuite/gas/i386/prescott.d
@@ -10,9 +10,9 @@ Disassembly of section .text:
    4:	66 0f d0 ca [ 	]*addsubpd %xmm2,%xmm1
    8:	f2 0f d0 13 [ 	]*addsubps \(%ebx\),%xmm2
    c:	f2 0f d0 dc [ 	]*addsubps %xmm4,%xmm3
-  10:	df 88 90 90 90 90 [ 	]*fisttp 0x90909090\(%eax\)
-  16:	db 88 90 90 90 90 [ 	]*fisttpl 0x90909090\(%eax\)
-  1c:	dd 88 90 90 90 90 [ 	]*fisttpll 0x90909090\(%eax\)
+  10:	df 88 90 90 90 90 [ 	]*fisttp -0x6f6f6f70\(%eax\)
+  16:	db 88 90 90 90 90 [ 	]*fisttpl -0x6f6f6f70\(%eax\)
+  1c:	dd 88 90 90 90 90 [ 	]*fisttpll -0x6f6f6f70\(%eax\)
   22:	66 0f 7c 65 00 [ 	]*haddpd 0x0\(%ebp\),%xmm4
   27:	66 0f 7c ee [ 	]*haddpd %xmm6,%xmm5
   2b:	f2 0f 7c 37 [ 	]*haddps \(%edi\),%xmm6
diff --git a/gas/testsuite/gas/i386/reloc64.d b/gas/testsuite/gas/i386/reloc64.d
index 11dfdb4fedd2..333deaa3a614 100644
--- a/gas/testsuite/gas/i386/reloc64.d
+++ b/gas/testsuite/gas/i386/reloc64.d
@@ -47,6 +47,7 @@ Disassembly of section \.text:
 .*[ 	]+R_X86_64_TPOFF64[ 	]+xtrn
 .*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
 .*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
 Disassembly of section \.data:
 #...
 .*[ 	]+R_X86_64_64[ 	]+xtrn
diff --git a/gas/testsuite/gas/i386/reloc64.s b/gas/testsuite/gas/i386/reloc64.s
index 47ebfa8dc0ad..7fd741af8395 100644
--- a/gas/testsuite/gas/i386/reloc64.s
+++ b/gas/testsuite/gas/i386/reloc64.s
@@ -195,3 +195,6 @@ bad	.byte	xtrn@gottpoff
 bad	.byte	xtrn@tlsld
 bad	.byte	xtrn@dtpoff
 bad	.byte	xtrn@tpoff
+
+	.text
+	mov	xtrn@tpoff (%rbx), %eax
diff --git a/gas/testsuite/gas/i386/rep-suffix.d b/gas/testsuite/gas/i386/rep-suffix.d
index 9eaaf3dd5d98..ac4e606be0a5 100644
--- a/gas/testsuite/gas/i386/rep-suffix.d
+++ b/gas/testsuite/gas/i386/rep-suffix.d
@@ -8,8 +8,8 @@ Disassembly of section .text:
 0+000 <_start>:
    0:	f3 ac[ 	]+rep lodsb %ds:\(%esi\),%al
    2:	f3 aa[ 	]+rep stosb %al,%es:\(%edi\)
-   4:	f3 66 ad[ 	]+rep lodsw %ds:\(%esi\),%ax
-   7:	f3 66 ab[ 	]+rep stosw %ax,%es:\(%edi\)
+   4:	66 f3 ad[ 	]+rep lodsw %ds:\(%esi\),%ax
+   7:	66 f3 ab[ 	]+rep stosw %ax,%es:\(%edi\)
    a:	f3 ad[ 	]+rep lodsl %ds:\(%esi\),%eax
    c:	f3 ab[ 	]+rep stosl %eax,%es:\(%edi\)
 #pass
diff --git a/gas/testsuite/gas/i386/rep.d b/gas/testsuite/gas/i386/rep.d
index f43cc5feb6cf..279924863940 100644
--- a/gas/testsuite/gas/i386/rep.d
+++ b/gas/testsuite/gas/i386/rep.d
@@ -13,13 +13,13 @@ Disassembly of section .text:
    8:	f3 aa[ 	]+rep stos %al,%es:\(%edi\)
    a:	f3 a6[ 	]+repz cmpsb %es:\(%edi\),%ds:\(%esi\)
    c:	f3 ae[ 	]+repz scas %es:\(%edi\),%al
-   e:	f3 66 6d[ 	]+rep insw \(%dx\),%es:\(%edi\)
-  11:	f3 66 6f[ 	]+rep outsw %ds:\(%esi\),\(%dx\)
-  14:	f3 66 a5[ 	]+rep movsw %ds:\(%esi\),%es:\(%edi\)
-  17:	f3 66 ad[ 	]+rep lods %ds:\(%esi\),%ax
-  1a:	f3 66 ab[ 	]+rep stos %ax,%es:\(%edi\)
-  1d:	f3 66 a7[ 	]+repz cmpsw %es:\(%edi\),%ds:\(%esi\)
-  20:	f3 66 af[ 	]+repz scas %es:\(%edi\),%ax
+   e:	66 f3 6d[ 	]+rep insw \(%dx\),%es:\(%edi\)
+  11:	66 f3 6f[ 	]+rep outsw %ds:\(%esi\),\(%dx\)
+  14:	66 f3 a5[ 	]+rep movsw %ds:\(%esi\),%es:\(%edi\)
+  17:	66 f3 ad[ 	]+rep lods %ds:\(%esi\),%ax
+  1a:	66 f3 ab[ 	]+rep stos %ax,%es:\(%edi\)
+  1d:	66 f3 a7[ 	]+repz cmpsw %es:\(%edi\),%ds:\(%esi\)
+  20:	66 f3 af[ 	]+repz scas %es:\(%edi\),%ax
   23:	f3 6d[ 	]+rep insl \(%dx\),%es:\(%edi\)
   25:	f3 6f[ 	]+rep outsl %ds:\(%esi\),\(%dx\)
   27:	f3 a5[ 	]+rep movsl %ds:\(%esi\),%es:\(%edi\)
@@ -27,25 +27,25 @@ Disassembly of section .text:
   2b:	f3 ab[ 	]+rep stos %eax,%es:\(%edi\)
   2d:	f3 a7[ 	]+repz cmpsl %es:\(%edi\),%ds:\(%esi\)
   2f:	f3 af[ 	]+repz scas %es:\(%edi\),%eax
-  31:	f3 67 6c[ 	]+rep addr16 insb \(%dx\),%es:\(%di\)
-  34:	f3 67 6e[ 	]+rep addr16 outsb %ds:\(%si\),\(%dx\)
-  37:	f3 67 a4[ 	]+rep addr16 movsb %ds:\(%si\),%es:\(%di\)
-  3a:	f3 67 ac[ 	]+rep addr16 lods %ds:\(%si\),%al
-  3d:	f3 67 aa[ 	]+rep addr16 stos %al,%es:\(%di\)
-  40:	f3 67 a6[ 	]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\)
-  43:	f3 67 ae[ 	]+repz addr16 scas %es:\(%di\),%al
-  46:	f3 67 66 6d[ 	]+rep addr16 insw \(%dx\),%es:\(%di\)
-  4a:	f3 67 66 6f[ 	]+rep addr16 outsw %ds:\(%si\),\(%dx\)
-  4e:	f3 67 66 a5[ 	]+rep addr16 movsw %ds:\(%si\),%es:\(%di\)
-  52:	f3 67 66 ad[ 	]+rep addr16 lods %ds:\(%si\),%ax
-  56:	f3 67 66 ab[ 	]+rep addr16 stos %ax,%es:\(%di\)
-  5a:	f3 67 66 a7[ 	]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\)
-  5e:	f3 67 66 af[ 	]+repz addr16 scas %es:\(%di\),%ax
-  62:	f3 67 6d[ 	]+rep addr16 insl \(%dx\),%es:\(%di\)
-  65:	f3 67 6f[ 	]+rep addr16 outsl %ds:\(%si\),\(%dx\)
-  68:	f3 67 a5[ 	]+rep addr16 movsl %ds:\(%si\),%es:\(%di\)
-  6b:	f3 67 ad[ 	]+rep addr16 lods %ds:\(%si\),%eax
-  6e:	f3 67 ab[ 	]+rep addr16 stos %eax,%es:\(%di\)
-  71:	f3 67 a7[ 	]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\)
-  74:	f3 67 af[ 	]+repz addr16 scas %es:\(%di\),%eax
+  31:	67 f3 6c[ 	]+rep addr16 insb \(%dx\),%es:\(%di\)
+  34:	67 f3 6e[ 	]+rep addr16 outsb %ds:\(%si\),\(%dx\)
+  37:	67 f3 a4[ 	]+rep addr16 movsb %ds:\(%si\),%es:\(%di\)
+  3a:	67 f3 ac[ 	]+rep addr16 lods %ds:\(%si\),%al
+  3d:	67 f3 aa[ 	]+rep addr16 stos %al,%es:\(%di\)
+  40:	67 f3 a6[ 	]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\)
+  43:	67 f3 ae[ 	]+repz addr16 scas %es:\(%di\),%al
+  46:	67 66 f3 6d[ 	]+rep addr16 insw \(%dx\),%es:\(%di\)
+  4a:	67 66 f3 6f[ 	]+rep addr16 outsw %ds:\(%si\),\(%dx\)
+  4e:	67 66 f3 a5[ 	]+rep addr16 movsw %ds:\(%si\),%es:\(%di\)
+  52:	67 66 f3 ad[ 	]+rep addr16 lods %ds:\(%si\),%ax
+  56:	67 66 f3 ab[ 	]+rep addr16 stos %ax,%es:\(%di\)
+  5a:	67 66 f3 a7[ 	]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\)
+  5e:	67 66 f3 af[ 	]+repz addr16 scas %es:\(%di\),%ax
+  62:	67 f3 6d[ 	]+rep addr16 insl \(%dx\),%es:\(%di\)
+  65:	67 f3 6f[ 	]+rep addr16 outsl %ds:\(%si\),\(%dx\)
+  68:	67 f3 a5[ 	]+rep addr16 movsl %ds:\(%si\),%es:\(%di\)
+  6b:	67 f3 ad[ 	]+rep addr16 lods %ds:\(%si\),%eax
+  6e:	67 f3 ab[ 	]+rep addr16 stos %eax,%es:\(%di\)
+  71:	67 f3 a7[ 	]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\)
+  74:	67 f3 af[ 	]+repz addr16 scas %es:\(%di\),%eax
 	...
diff --git a/gas/testsuite/gas/i386/rex.d b/gas/testsuite/gas/i386/rex.d
index dab6b12580d1..9023b49ace4b 100644
--- a/gas/testsuite/gas/i386/rex.d
+++ b/gas/testsuite/gas/i386/rex.d
@@ -1,17 +1,33 @@
 #objdump: -dw
 #name: x86-64 manual rex prefix use
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
 0+ <_start>:
 [	 ]*[0-9a-f]+:[	 ]+40 0f ae 00[	 ]+rex fxsavel?[	 ]+\(%rax\)
-[	 ]*[0-9a-f]+:[	 ]+48 0f ae 00[	 ]+(rex64 )?fxsaveq?[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+48 0f ae 00[	 ]+(rex.W )?fxsaveq?[	 ]+\(%rax\)
 [	 ]*[0-9a-f]+:[	 ]+41 0f ae 00[	 ]+fxsavel?[	 ]+\(%r8\)
-[	 ]*[0-9a-f]+:[	 ]+49 0f ae 00[	 ]+(rex64Z? )?fxsaveq?[	 ]+\(%r8\)
+[	 ]*[0-9a-f]+:[	 ]+49 0f ae 00[	 ]+(rex.WB? )?fxsaveq?[	 ]+\(%r8\)
 [	 ]*[0-9a-f]+:[	 ]+42 0f ae 04 05 00 00 00 00[	 ]+fxsavel?[	 ]+(0x0)?\(,%r8(,1)?\)
-[	 ]*[0-9a-f]+:[	 ]+4a 0f ae 04 05 00 00 00 00[	 ]+(rex64Y? )?fxsaveq?[	 ]+(0x0)?\(,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+4a 0f ae 04 05 00 00 00 00[	 ]+(rex.WX? )?fxsaveq?[	 ]+(0x0)?\(,%r8(,1)?\)
 [	 ]*[0-9a-f]+:[	 ]+43 0f ae 04 00[	 ]+fxsavel?[	 ]+\(%r8,%r8(,1)?\)
-[	 ]*[0-9a-f]+:[	 ]+4b 0f ae 04 00[	 ]+(rex64(YZ)? )?fxsaveq?[	 ]+\(%r8,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+4b 0f ae 04 00[	 ]+(rex.W(XB)? )?fxsaveq?[	 ]+\(%r8,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+40[	 ]+rex
+[	 ]*[0-9a-f]+:[	 ]+41[	 ]+rex.B
+[	 ]*[0-9a-f]+:[	 ]+42[	 ]+rex.X
+[	 ]*[0-9a-f]+:[	 ]+43[	 ]+rex.XB
+[	 ]*[0-9a-f]+:[	 ]+44[	 ]+rex.R
+[	 ]*[0-9a-f]+:[	 ]+45[	 ]+rex.RB
+[	 ]*[0-9a-f]+:[	 ]+46[	 ]+rex.RX
+[	 ]*[0-9a-f]+:[	 ]+47[	 ]+rex.RXB
+[	 ]*[0-9a-f]+:[	 ]+48[	 ]+rex.W
+[	 ]*[0-9a-f]+:[	 ]+49[	 ]+rex.WB
+[	 ]*[0-9a-f]+:[	 ]+4a[	 ]+rex.WX
+[	 ]*[0-9a-f]+:[	 ]+4b[	 ]+rex.WXB
+[	 ]*[0-9a-f]+:[	 ]+4c[	 ]+rex.WR
+[	 ]*[0-9a-f]+:[	 ]+4d[	 ]+rex.WRB
+[	 ]*[0-9a-f]+:[	 ]+4e[	 ]+rex.WRX
+[	 ]*[0-9a-f]+:[	 ]+4f[	 ]+rex.WRXB
 #pass
diff --git a/gas/testsuite/gas/i386/rex.s b/gas/testsuite/gas/i386/rex.s
index a142312a2c6b..6f1e38a47038 100644
--- a/gas/testsuite/gas/i386/rex.s
+++ b/gas/testsuite/gas/i386/rex.s
@@ -9,3 +9,21 @@ _start:
 	rex64/fxsave (,%r8)
 	rex/fxsave (%r8,%r8)
 	rex64/fxsave (%r8,%r8)
+
+# Test prefixes family.
+	rex
+	rex.B
+	rex.X
+	rex.XB
+	rex.R
+	rex.RB
+	rex.RX
+	rex.RXB
+	rex.W
+	rex.WB
+	rex.WX
+	rex.WXB
+	rex.WR
+	rex.WRB
+	rex.WRX
+	rex.WRXB
diff --git a/gas/testsuite/gas/i386/secrel.d b/gas/testsuite/gas/i386/secrel.d
index 6a3b915fd77d..58967cb51414 100644
--- a/gas/testsuite/gas/i386/secrel.d
+++ b/gas/testsuite/gas/i386/secrel.d
@@ -4,23 +4,23 @@
 .*: +file format pe-i386

 

 RELOCATION RECORDS FOR \[\.data\]:

-OFFSET   TYPE              VALUE 

-00000024 secrel32          \.text

-00000029 secrel32          \.text

-0000002e secrel32          \.text

-00000033 secrel32          \.text

-00000044 secrel32          \.data

-00000049 secrel32          \.data

-0000004e secrel32          \.data

-00000053 secrel32          \.data

-00000064 secrel32          \.rdata

-00000069 secrel32          \.rdata

-0000006e secrel32          \.rdata

-00000073 secrel32          \.rdata

-00000084 secrel32          ext24

-00000089 secrel32          ext2d

-0000008e secrel32          ext36

-00000093 secrel32          ext3f

+OFFSET[ 	]+TYPE[ 	]+VALUE 

+0+24 secrel32          \.text

+0+29 secrel32          \.text

+0+2e secrel32          \.text

+0+33 secrel32          \.text

+0+44 secrel32          \.data

+0+49 secrel32          \.data

+0+4e secrel32          \.data

+0+53 secrel32          \.data

+0+64 secrel32          \.rdata

+0+69 secrel32          \.rdata

+0+6e secrel32          \.rdata

+0+73 secrel32          \.rdata

+0+84 secrel32          ext24

+0+89 secrel32          ext2d

+0+8e secrel32          ext36

+0+93 secrel32          ext3f

 

 

 Contents of section \.text:

diff --git a/gas/testsuite/gas/i386/simd-intel.d b/gas/testsuite/gas/i386/simd-intel.d
new file mode 100644
index 000000000000..7f4cc102b5c4
--- /dev/null
+++ b/gas/testsuite/gas/i386/simd-intel.d
@@ -0,0 +1,37 @@
+#source: simd.s
+#as: -J
+#objdump: -dw -Mintel
+#name: i386 SIMD (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 0f d0 0d 78 56 34 12 	addsubps xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	66 0f 2f 0d 78 56 34 12 	comisd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 2f 0d 78 56 34 12 	comiss xmm1,DWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f e6 0d 78 56 34 12 	cvtdq2pd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f2 0f e6 0d 78 56 34 12 	cvtpd2dq xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 5a 0d 78 56 34 12 	cvtps2pd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 5b 0d 78 56 34 12 	cvttps2dq xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 7f 0d 78 56 34 12 	movdqu XMMWORD PTR ds:0x12345678,xmm1
+[ 	]*[a-f0-9]+:	f3 0f 6f 0d 78 56 34 12 	movdqu xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	66 0f 17 0d 78 56 34 12 	movhpd QWORD PTR ds:0x12345678,xmm1
+[ 	]*[a-f0-9]+:	66 0f 16 0d 78 56 34 12 	movhpd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 17 0d 78 56 34 12 	movhps QWORD PTR ds:0x12345678,xmm1
+[ 	]*[a-f0-9]+:	0f 16 0d 78 56 34 12 	movhps xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	66 0f 13 0d 78 56 34 12 	movlpd QWORD PTR ds:0x12345678,xmm1
+[ 	]*[a-f0-9]+:	66 0f 12 0d 78 56 34 12 	movlpd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 13 0d 78 56 34 12 	movlps QWORD PTR ds:0x12345678,xmm1
+[ 	]*[a-f0-9]+:	0f 12 0d 78 56 34 12 	movlps xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 16 0d 78 56 34 12 	movshdup xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 12 0d 78 56 34 12 	movsldup xmm1,XMMWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 70 0d 78 56 34 12 90 	pshufhw xmm1,XMMWORD PTR ds:0x12345678,0x90
+[ 	]*[a-f0-9]+:	f2 0f 70 0d 78 56 34 12 90 	pshuflw xmm1,XMMWORD PTR ds:0x12345678,0x90
+[ 	]*[a-f0-9]+:	0f 60 0d 78 56 34 12 	punpcklbw mm1,DWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 62 0d 78 56 34 12 	punpckldq mm1,DWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 61 0d 78 56 34 12 	punpcklwd mm1,DWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	66 0f 2e 0d 78 56 34 12 	ucomisd xmm1,QWORD PTR ds:0x12345678
+[ 	]*[a-f0-9]+:	0f 2e 0d 78 56 34 12 	ucomiss xmm1,DWORD PTR ds:0x12345678
diff --git a/gas/testsuite/gas/i386/simd.d b/gas/testsuite/gas/i386/simd.d
new file mode 100644
index 000000000000..38a296af15d2
--- /dev/null
+++ b/gas/testsuite/gas/i386/simd.d
@@ -0,0 +1,36 @@
+#as: -J
+#objdump: -dw
+#name: i386 SIMD
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 0f d0 0d 78 56 34 12 	addsubps 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	66 0f 2f 0d 78 56 34 12 	comisd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 2f 0d 78 56 34 12 	comiss 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f e6 0d 78 56 34 12 	cvtdq2pd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f e6 0d 78 56 34 12 	cvtpd2dq 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 5a 0d 78 56 34 12 	cvtps2pd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 5b 0d 78 56 34 12 	cvttps2dq 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 7f 0d 78 56 34 12 	movdqu %xmm1,0x12345678
+[ 	]*[a-f0-9]+:	f3 0f 6f 0d 78 56 34 12 	movdqu 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	66 0f 17 0d 78 56 34 12 	movhpd %xmm1,0x12345678
+[ 	]*[a-f0-9]+:	66 0f 16 0d 78 56 34 12 	movhpd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 17 0d 78 56 34 12 	movhps %xmm1,0x12345678
+[ 	]*[a-f0-9]+:	0f 16 0d 78 56 34 12 	movhps 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	66 0f 13 0d 78 56 34 12 	movlpd %xmm1,0x12345678
+[ 	]*[a-f0-9]+:	66 0f 12 0d 78 56 34 12 	movlpd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 13 0d 78 56 34 12 	movlps %xmm1,0x12345678
+[ 	]*[a-f0-9]+:	0f 12 0d 78 56 34 12 	movlps 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 16 0d 78 56 34 12 	movshdup 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 12 0d 78 56 34 12 	movsldup 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 70 0d 78 56 34 12 90 	pshufhw \$0x90,0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	f2 0f 70 0d 78 56 34 12 90 	pshuflw \$0x90,0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 60 0d 78 56 34 12 	punpcklbw 0x12345678,%mm1
+[ 	]*[a-f0-9]+:	0f 62 0d 78 56 34 12 	punpckldq 0x12345678,%mm1
+[ 	]*[a-f0-9]+:	0f 61 0d 78 56 34 12 	punpcklwd 0x12345678,%mm1
+[ 	]*[a-f0-9]+:	66 0f 2e 0d 78 56 34 12 	ucomisd 0x12345678,%xmm1
+[ 	]*[a-f0-9]+:	0f 2e 0d 78 56 34 12 	ucomiss 0x12345678,%xmm1
diff --git a/gas/testsuite/gas/i386/simd.s b/gas/testsuite/gas/i386/simd.s
new file mode 100644
index 000000000000..cd0cf93cb266
--- /dev/null
+++ b/gas/testsuite/gas/i386/simd.s
@@ -0,0 +1,29 @@
+	.text
+_start:
+	addsubps 0x12345678,%xmm1
+	comisd 0x12345678,%xmm1
+	comiss 0x12345678,%xmm1
+	cvtdq2pd 0x12345678,%xmm1
+	cvtpd2dq 0x12345678,%xmm1
+	cvtps2pd 0x12345678,%xmm1
+	cvttps2dq 0x12345678,%xmm1
+	haddps 0x12345678,%xmm1
+	movdqu %xmm1,0x12345678
+	movdqu 0x12345678,%xmm1
+	movhpd %xmm1,0x12345678
+	movhpd 0x12345678,%xmm1
+	movhps %xmm1,0x12345678
+	movhps 0x12345678,%xmm1
+	movlpd %xmm1,0x12345678
+	movlpd 0x12345678,%xmm1
+	movlps %xmm1,0x12345678
+	movlps 0x12345678,%xmm1
+	movshdup 0x12345678,%xmm1
+	movsldup 0x12345678,%xmm1
+	pshufhw $0x90,0x12345678,%xmm1
+	pshuflw $0x90,0x12345678,%xmm1
+	punpcklbw 0x12345678,%mm1
+	punpckldq 0x12345678,%mm1
+	punpcklwd 0x12345678,%mm1
+	ucomisd 0x12345678,%xmm1
+	ucomiss 0x12345678,%xmm1
diff --git a/gas/testsuite/gas/i386/sse2.d b/gas/testsuite/gas/i386/sse2.d
index eb6a161cbf98..8b067f568d7e 100644
--- a/gas/testsuite/gas/i386/sse2.d
+++ b/gas/testsuite/gas/i386/sse2.d
@@ -61,16 +61,16 @@ Disassembly of section .text:
 [ 	]+f5:	f2 0f c2 f8 07[ 	]+cmpordsd %xmm0,%xmm7
 [ 	]+fa:	66 0f 2f c1[ 	]+comisd %xmm1,%xmm0
 [ 	]+fe:	66 0f 2f 0a[ 	]+comisd \(%edx\),%xmm1
- 102:	66 0f 2a d3[ 	]+cvtpi2pd %xmm3,%xmm2
+ 102:	66 0f 2a d3[ 	]+cvtpi2pd %mm3,%xmm2
  106:	66 0f 2a 1c 24[ 	]+cvtpi2pd \(%esp\),%xmm3
  10b:	f2 0f 2a e5[ 	]+cvtsi2sd %ebp,%xmm4
  10f:	f2 0f 2a 2e[ 	]+cvtsi2sd \(%esi\),%xmm5
- 113:	66 0f 2d f7[ 	]+cvtpd2pi %xmm7,%xmm6
- 117:	66 0f 2d 38[ 	]+cvtpd2pi \(%eax\),%xmm7
+ 113:	66 0f 2d f7[ 	]+cvtpd2pi %xmm7,%mm6
+ 117:	66 0f 2d 38[ 	]+cvtpd2pi \(%eax\),%mm7
  11b:	f2 0f 2d 01[ 	]+cvtsd2si \(%ecx\),%eax
  11f:	f2 0f 2d ca[ 	]+cvtsd2si %xmm2,%ecx
- 123:	66 0f 2c 13[ 	]+cvttpd2pi \(%ebx\),%xmm2
- 127:	66 0f 2c dc[ 	]+cvttpd2pi %xmm4,%xmm3
+ 123:	66 0f 2c 13[ 	]+cvttpd2pi \(%ebx\),%mm2
+ 127:	66 0f 2c dc[ 	]+cvttpd2pi %xmm4,%mm3
  12b:	f2 0f 2c 65 00[ 	]+cvttsd2si 0x0\(%ebp\),%esp
  130:	f2 0f 2c ee[ 	]+cvttsd2si %xmm6,%ebp
  134:	66 0f 5e c1[ 	]+divpd[ 	]+%xmm1,%xmm0
@@ -140,9 +140,9 @@ Disassembly of section .text:
  239:	f3 0f 5b c8[ 	]+cvttps2dq %xmm0,%xmm1
  23d:	66 0f f7 c8[ 	]+maskmovdqu %xmm0,%xmm1
  241:	66 0f 6f c8[ 	]+movdqa %xmm0,%xmm1
- 245:	66 0f 6f c8[ 	]+movdqa %xmm0,%xmm1
+ 245:	66 0f 7f 06[ 	]+movdqa %xmm0,\(%esi\)
  249:	f3 0f 6f c8[ 	]+movdqu %xmm0,%xmm1
- 24d:	f3 0f 6f c8[ 	]+movdqu %xmm0,%xmm1
+ 24d:	f3 0f 7f 06[ 	]+movdqu %xmm0,\(%esi\)
  251:	f2 0f d6 c8[ 	]+movdq2q %xmm0,%mm1
  255:	f3 0f d6 c8[ 	]+movq2dq %mm0,%xmm1
  259:	66 0f f4 c8[ 	]+pmuludq %xmm0,%xmm1
@@ -153,4 +153,4 @@ Disassembly of section .text:
  270:	66 0f 73 f8 01[ 	]+pslldq \$0x1,%xmm0
  275:	66 0f 73 d8 01[ 	]+psrldq \$0x1,%xmm0
  27a:	66 0f 6d c8[ 	]+punpckhqdq %xmm0,%xmm1
- 27e:	89 f6[ 	]+mov[ 	]+%esi,%esi
+ 27e:	66 90[ 	]+xchg[ 	]+%ax,%ax
diff --git a/gas/testsuite/gas/i386/sse2.s b/gas/testsuite/gas/i386/sse2.s
index ba5ae8d7b474..edb79fcba353 100644
--- a/gas/testsuite/gas/i386/sse2.s
+++ b/gas/testsuite/gas/i386/sse2.s
@@ -132,9 +132,9 @@ foo:
 	cvttps2dq	%xmm0, %xmm1
 	maskmovdqu	%xmm0, %xmm1
 	movdqa		%xmm0, %xmm1
-	movdqa		%xmm0, %xmm1
-	movdqu		%xmm0, %xmm1
+	movdqa		%xmm0, (%esi)
 	movdqu		%xmm0, %xmm1
+	movdqu		%xmm0, (%esi)
 	movdq2q		%xmm0, %mm1
 	movq2dq		%mm0, %xmm1
 	pmuludq		%xmm0, %xmm1
diff --git a/gas/testsuite/gas/i386/sse4_1.d b/gas/testsuite/gas/i386/sse4_1.d
new file mode 100644
index 000000000000..6797228a5299
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse4_1.d
@@ -0,0 +1,102 @@
+#objdump: -dw
+#name: i386 SSE4.1
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]*[0-9a-f]+:	66 0f 3a 0d 01 00    	blendpd \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0d c1 00    	blendpd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0c 01 00    	blendps \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0c c1 00    	blendps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 15 01       	blendvpd %xmm0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 15 c1       	blendvpd %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 14 01       	blendvps %xmm0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 14 c1       	blendvps %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 41 01 00    	dppd   \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 41 c1 00    	dppd   \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 40 01 00    	dpps   \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 40 c1 00    	dpps   \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 17 c1 00    	extractps \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 17 01 00    	extractps \$0x0,%xmm0,\(%ecx\)
+[ 	]*[0-9a-f]+:	66 0f 3a 21 c1 00    	insertps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 21 01 00    	insertps \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2a 01       	movntdqa \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 42 01 00    	mpsadbw \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 42 c1 00    	mpsadbw \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2b 01       	packusdw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2b c1       	packusdw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 10 01       	pblendvb %xmm0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 10 c1       	pblendvb %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0e 01 00    	pblendw \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0e c1 00    	pblendw \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 29 c1       	pcmpeqq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 29 01       	pcmpeqq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 14 c1 00    	pextrb \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 14 01 00    	pextrb \$0x0,%xmm0,\(%ecx\)
+[ 	]*[0-9a-f]+:	66 0f 3a 16 c1 00    	pextrd \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 16 01 00    	pextrd \$0x0,%xmm0,\(%ecx\)
+[ 	]*[0-9a-f]+:	66 0f c5 c8 00       	pextrw \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 15 01 00    	pextrw \$0x0,%xmm0,\(%ecx\)
+[ 	]*[0-9a-f]+:	66 0f 38 41 c1       	phminposuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 41 01       	phminposuw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 20 01 00    	pinsrb \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 20 c1 00    	pinsrb \$0x0,%ecx,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 22 01 00    	pinsrd \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 22 c1 00    	pinsrd \$0x0,%ecx,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3c c1       	pmaxsb %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3c 01       	pmaxsb \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3d c1       	pmaxsd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3d 01       	pmaxsd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3f c1       	pmaxud %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3f 01       	pmaxud \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3e c1       	pmaxuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3e 01       	pmaxuw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 38 c1       	pminsb %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 38 01       	pminsb \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 39 c1       	pminsd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 39 01       	pminsd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3b c1       	pminud %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3b 01       	pminud \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3a c1       	pminuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3a 01       	pminuw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 20 c1       	pmovsxbw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 20 01       	pmovsxbw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 21 c1       	pmovsxbd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 21 01       	pmovsxbd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 22 c1       	pmovsxbq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 22 01       	pmovsxbq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 23 c1       	pmovsxwd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 23 01       	pmovsxwd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 24 c1       	pmovsxwq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 24 01       	pmovsxwq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 25 c1       	pmovsxdq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 25 01       	pmovsxdq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 30 c1       	pmovzxbw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 30 01       	pmovzxbw \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 31 c1       	pmovzxbd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 31 01       	pmovzxbd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 32 c1       	pmovzxbq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 32 01       	pmovzxbq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 33 c1       	pmovzxwd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 33 01       	pmovzxwd \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 34 c1       	pmovzxwq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 34 01       	pmovzxwq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 35 c1       	pmovzxdq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 35 01       	pmovzxdq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 28 c1       	pmuldq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 28 01       	pmuldq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 40 c1       	pmulld %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 40 01       	pmulld \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 17 c1       	ptest  %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 17 01       	ptest  \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 09 01 00    	roundpd \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 09 c1 00    	roundpd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 08 01 00    	roundps \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 08 c1 00    	roundps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0b 01 00    	roundsd \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0b c1 00    	roundsd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0a 01 00    	roundss \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0a c1 00    	roundss \$0x0,%xmm1,%xmm0
+#pass
diff --git a/gas/testsuite/gas/i386/sse4_1.s b/gas/testsuite/gas/i386/sse4_1.s
new file mode 100644
index 000000000000..258dde8a4b9e
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse4_1.s
@@ -0,0 +1,99 @@
+# Streaming SIMD extensions 4.1 Instructions
+
+	.text
+foo:
+	blendpd		$0,(%ecx),%xmm0
+	blendpd		$0,%xmm1,%xmm0
+	blendps		$0,(%ecx),%xmm0
+	blendps		$0,%xmm1,%xmm0
+	blendvpd	%xmm0,(%ecx),%xmm0
+	blendvpd	%xmm0,%xmm1,%xmm0
+	blendvps	%xmm0,(%ecx),%xmm0
+	blendvps	%xmm0,%xmm1,%xmm0
+	dppd		$0,(%ecx),%xmm0
+	dppd		$0,%xmm1,%xmm0
+	dpps		$0,(%ecx),%xmm0
+	dpps		$0,%xmm1,%xmm0
+	extractps	$0,%xmm0,%ecx
+	extractps	$0,%xmm0,(%ecx)
+	insertps	$0,%xmm1,%xmm0
+	insertps	$0,(%ecx),%xmm0
+	movntdqa	(%ecx),%xmm0
+	mpsadbw		$0,(%ecx),%xmm0
+	mpsadbw		$0,%xmm1,%xmm0
+	packusdw	(%ecx),%xmm0
+	packusdw	%xmm1,%xmm0
+	pblendvb	%xmm0,(%ecx),%xmm0
+	pblendvb	%xmm0,%xmm1,%xmm0
+	pblendw		$0,(%ecx),%xmm0
+	pblendw		$0,%xmm1,%xmm0
+	pcmpeqq		%xmm1,%xmm0
+	pcmpeqq		(%ecx),%xmm0
+	pextrb          $0,%xmm0,%ecx
+	pextrb          $0,%xmm0,(%ecx)
+	pextrd          $0,%xmm0,%ecx
+	pextrd          $0,%xmm0,(%ecx)
+	pextrw          $0,%xmm0,%ecx
+	pextrw          $0,%xmm0,(%ecx)
+	phminposuw	%xmm1,%xmm0
+	phminposuw	(%ecx),%xmm0
+	pinsrb		$0,(%ecx),%xmm0
+	pinsrb		$0,%ecx,%xmm0
+	pinsrd		$0,(%ecx),%xmm0
+	pinsrd		$0,%ecx,%xmm0
+	pmaxsb		%xmm1,%xmm0
+	pmaxsb		(%ecx),%xmm0
+	pmaxsd		%xmm1,%xmm0
+	pmaxsd		(%ecx),%xmm0
+	pmaxud		%xmm1,%xmm0
+	pmaxud		(%ecx),%xmm0
+	pmaxuw		%xmm1,%xmm0
+	pmaxuw		(%ecx),%xmm0
+	pminsb		%xmm1,%xmm0
+	pminsb		(%ecx),%xmm0
+	pminsd		%xmm1,%xmm0
+	pminsd		(%ecx),%xmm0
+	pminud		%xmm1,%xmm0
+	pminud		(%ecx),%xmm0
+	pminuw		%xmm1,%xmm0
+	pminuw		(%ecx),%xmm0
+	pmovsxbw	%xmm1,%xmm0
+	pmovsxbw	(%ecx),%xmm0
+	pmovsxbd	%xmm1,%xmm0
+	pmovsxbd	(%ecx),%xmm0
+	pmovsxbq	%xmm1,%xmm0
+	pmovsxbq	(%ecx),%xmm0
+	pmovsxwd	%xmm1,%xmm0
+	pmovsxwd	(%ecx),%xmm0
+	pmovsxwq	%xmm1,%xmm0
+	pmovsxwq	(%ecx),%xmm0
+	pmovsxdq	%xmm1,%xmm0
+	pmovsxdq	(%ecx),%xmm0
+	pmovzxbw	%xmm1,%xmm0
+	pmovzxbw	(%ecx),%xmm0
+	pmovzxbd	%xmm1,%xmm0
+	pmovzxbd	(%ecx),%xmm0
+	pmovzxbq	%xmm1,%xmm0
+	pmovzxbq	(%ecx),%xmm0
+	pmovzxwd	%xmm1,%xmm0
+	pmovzxwd	(%ecx),%xmm0
+	pmovzxwq	%xmm1,%xmm0
+	pmovzxwq	(%ecx),%xmm0
+	pmovzxdq	%xmm1,%xmm0
+	pmovzxdq	(%ecx),%xmm0
+	pmuldq		%xmm1,%xmm0
+	pmuldq		(%ecx),%xmm0
+	pmulld		%xmm1,%xmm0
+	pmulld		(%ecx),%xmm0
+	ptest		%xmm1,%xmm0
+	ptest		(%ecx),%xmm0
+	roundpd		$0,(%ecx),%xmm0
+	roundpd		$0,%xmm1,%xmm0
+	roundps		$0,(%ecx),%xmm0
+	roundps		$0,%xmm1,%xmm0
+	roundsd		$0,(%ecx),%xmm0
+	roundsd		$0,%xmm1,%xmm0
+	roundss		$0,(%ecx),%xmm0
+	roundss		$0,%xmm1,%xmm0
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/sse4_2.d b/gas/testsuite/gas/i386/sse4_2.d
new file mode 100644
index 000000000000..b889769ac4c7
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse4_2.d
@@ -0,0 +1,36 @@
+#objdump: -dw
+#name: i386 SSE4.2
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 d9       	crc32b %cl,%ebx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 d9    	crc32w %cx,%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 19       	crc32b \(%ecx\),%ebx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 19    	crc32w \(%ecx\),%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 19       	crc32l \(%ecx\),%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 d9       	crc32b %cl,%ebx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 d9    	crc32w %cx,%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+[ 	]*[0-9a-f]+:	66 0f 38 37 01       	pcmpgtq \(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 37 c1       	pcmpgtq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 61 01 00    	pcmpestri \$0x0,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 61 c1 00    	pcmpestri \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 60 01 01    	pcmpestrm \$0x1,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 60 c1 01    	pcmpestrm \$0x1,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 63 01 02    	pcmpistri \$0x2,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 63 c1 02    	pcmpistri \$0x2,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 62 01 03    	pcmpistrm \$0x3,\(%ecx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 62 c1 03    	pcmpistrm \$0x3,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 f3 0f b8 19       	popcnt \(%ecx\),%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 19          	popcnt \(%ecx\),%ebx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 19       	popcnt \(%ecx\),%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 19          	popcnt \(%ecx\),%ebx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 d9       	popcnt %cx,%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 d9       	popcnt %cx,%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+#pass
diff --git a/gas/testsuite/gas/i386/sse4_2.s b/gas/testsuite/gas/i386/sse4_2.s
new file mode 100644
index 000000000000..a6c2e4610ee1
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse4_2.s
@@ -0,0 +1,33 @@
+# Streaming SIMD extensions 4.2 Instructions
+
+	.text
+foo:
+	crc32		%cl,%ebx
+	crc32		%cx,%ebx
+	crc32		%ecx,%ebx
+	crc32b		(%ecx),%ebx
+	crc32w		(%ecx),%ebx
+	crc32l		(%ecx),%ebx
+	crc32b		%cl,%ebx
+	crc32w		%cx,%ebx
+	crc32l		%ecx,%ebx
+	pcmpgtq		(%ecx),%xmm0
+	pcmpgtq		%xmm1,%xmm0
+	pcmpestri	$0x0,(%ecx),%xmm0
+	pcmpestri	$0x0,%xmm1,%xmm0
+	pcmpestrm	$0x1,(%ecx),%xmm0
+	pcmpestrm	$0x1,%xmm1,%xmm0
+	pcmpistri	$0x2,(%ecx),%xmm0
+	pcmpistri	$0x2,%xmm1,%xmm0
+	pcmpistrm	$0x3,(%ecx),%xmm0
+	pcmpistrm	$0x3,%xmm1,%xmm0
+	popcnt		(%ecx),%bx
+	popcnt		(%ecx),%ebx
+	popcntw		(%ecx),%bx
+	popcntl		(%ecx),%ebx
+	popcnt		%cx,%bx
+	popcnt		%ecx,%ebx
+	popcntw		%cx,%bx
+	popcntl		%ecx,%ebx
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/ssemmx2.d b/gas/testsuite/gas/i386/ssemmx2.d
index 04ccbafe457b..f25bc5f80b65 100644
--- a/gas/testsuite/gas/i386/ssemmx2.d
+++ b/gas/testsuite/gas/i386/ssemmx2.d
@@ -34,55 +34,55 @@ Disassembly of section .text:
 [ 	]+6b:	f2 0f 70 da 01[ 	]+pshuflw \$0x1,%xmm2,%xmm3
 [ 	]+70:	f2 0f 70 75 00 04[ 	]+pshuflw \$0x4,0x0\(%ebp\),%xmm6
 [ 	]+76:	66 0f e7 10[ 	]+movntdq %xmm2,\(%eax\)
-[ 	]+7a:	66 0f 60 90 90 90 90 90 	punpcklbw 0x90909090\(%eax\),%xmm2
-[ 	]+82:	66 0f 61 90 90 90 90 90 	punpcklwd 0x90909090\(%eax\),%xmm2
-[ 	]+8a:	66 0f 62 90 90 90 90 90 	punpckldq 0x90909090\(%eax\),%xmm2
-[ 	]+92:	66 0f 63 90 90 90 90 90 	packsswb 0x90909090\(%eax\),%xmm2
-[ 	]+9a:	66 0f 64 90 90 90 90 90 	pcmpgtb 0x90909090\(%eax\),%xmm2
-[ 	]+a2:	66 0f 65 90 90 90 90 90 	pcmpgtw 0x90909090\(%eax\),%xmm2
-[ 	]+aa:	66 0f 66 90 90 90 90 90 	pcmpgtd 0x90909090\(%eax\),%xmm2
-[ 	]+b2:	66 0f 67 90 90 90 90 90 	packuswb 0x90909090\(%eax\),%xmm2
-[ 	]+ba:	66 0f 68 90 90 90 90 90 	punpckhbw 0x90909090\(%eax\),%xmm2
-[ 	]+c2:	66 0f 69 90 90 90 90 90 	punpckhwd 0x90909090\(%eax\),%xmm2
-[ 	]+ca:	66 0f 6a 90 90 90 90 90 	punpckhdq 0x90909090\(%eax\),%xmm2
-[ 	]+d2:	66 0f 6b 90 90 90 90 90 	packssdw 0x90909090\(%eax\),%xmm2
-[ 	]+da:	66 0f 6e 90 90 90 90 90 	movd[ 	]+0x90909090\(%eax\),%xmm2
-[ 	]+e2:	f3 0f 7e 90 90 90 90 90 	movq[ 	]+0x90909090\(%eax\),%xmm2
+[ 	]+7a:	66 0f 60 90 90 90 90 90 	punpcklbw -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+82:	66 0f 61 90 90 90 90 90 	punpcklwd -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+8a:	66 0f 62 90 90 90 90 90 	punpckldq -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+92:	66 0f 63 90 90 90 90 90 	packsswb -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+9a:	66 0f 64 90 90 90 90 90 	pcmpgtb -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+a2:	66 0f 65 90 90 90 90 90 	pcmpgtw -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+aa:	66 0f 66 90 90 90 90 90 	pcmpgtd -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+b2:	66 0f 67 90 90 90 90 90 	packuswb -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+ba:	66 0f 68 90 90 90 90 90 	punpckhbw -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+c2:	66 0f 69 90 90 90 90 90 	punpckhwd -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+ca:	66 0f 6a 90 90 90 90 90 	punpckhdq -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+d2:	66 0f 6b 90 90 90 90 90 	packssdw -0x6f6f6f70\(%eax\),%xmm2
+[ 	]+da:	66 0f 6e 90 90 90 90 90 	movd[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+[ 	]+e2:	f3 0f 7e 90 90 90 90 90 	movq[ 	]+-0x6f6f6f70\(%eax\),%xmm2
 [ 	]+ea:	66 0f 71 d0 90[ 	]+psrlw[ 	]+\$0x90,%xmm0
 [ 	]+ef:	66 0f 72 d0 90[ 	]+psrld[ 	]+\$0x90,%xmm0
 [ 	]+f4:	66 0f 73 d0 90[ 	]+psrlq[ 	]+\$0x90,%xmm0
-[ 	]+f9:	66 0f 74 90 90 90 90 90 	pcmpeqb 0x90909090\(%eax\),%xmm2
- 101:	66 0f 75 90 90 90 90 90 	pcmpeqw 0x90909090\(%eax\),%xmm2
- 109:	66 0f 76 90 90 90 90 90 	pcmpeqd 0x90909090\(%eax\),%xmm2
- 111:	66 0f 7e 90 90 90 90 90 	movd[ 	]+%xmm2,0x90909090\(%eax\)
- 119:	66 0f d6 90 90 90 90 90 	movq[ 	]+%xmm2,0x90909090\(%eax\)
- 121:	66 0f d1 90 90 90 90 90 	psrlw[ 	]+0x90909090\(%eax\),%xmm2
- 129:	66 0f d2 90 90 90 90 90 	psrld[ 	]+0x90909090\(%eax\),%xmm2
- 131:	66 0f d3 90 90 90 90 90 	psrlq[ 	]+0x90909090\(%eax\),%xmm2
- 139:	66 0f d5 90 90 90 90 90 	pmullw 0x90909090\(%eax\),%xmm2
- 141:	66 0f d8 90 90 90 90 90 	psubusb 0x90909090\(%eax\),%xmm2
- 149:	66 0f d9 90 90 90 90 90 	psubusw 0x90909090\(%eax\),%xmm2
- 151:	66 0f db 90 90 90 90 90 	pand[ 	]+0x90909090\(%eax\),%xmm2
- 159:	66 0f dc 90 90 90 90 90 	paddusb 0x90909090\(%eax\),%xmm2
- 161:	66 0f dd 90 90 90 90 90 	paddusw 0x90909090\(%eax\),%xmm2
- 169:	66 0f df 90 90 90 90 90 	pandn[ 	]+0x90909090\(%eax\),%xmm2
- 171:	66 0f e1 90 90 90 90 90 	psraw[ 	]+0x90909090\(%eax\),%xmm2
- 179:	66 0f e2 90 90 90 90 90 	psrad[ 	]+0x90909090\(%eax\),%xmm2
- 181:	66 0f e5 90 90 90 90 90 	pmulhw 0x90909090\(%eax\),%xmm2
- 189:	66 0f e8 90 90 90 90 90 	psubsb 0x90909090\(%eax\),%xmm2
- 191:	66 0f e9 90 90 90 90 90 	psubsw 0x90909090\(%eax\),%xmm2
- 199:	66 0f eb 90 90 90 90 90 	por[ 	]+0x90909090\(%eax\),%xmm2
- 1a1:	66 0f ec 90 90 90 90 90 	paddsb 0x90909090\(%eax\),%xmm2
- 1a9:	66 0f ed 90 90 90 90 90 	paddsw 0x90909090\(%eax\),%xmm2
- 1b1:	66 0f ef 90 90 90 90 90 	pxor[ 	]+0x90909090\(%eax\),%xmm2
- 1b9:	66 0f f1 90 90 90 90 90 	psllw[ 	]+0x90909090\(%eax\),%xmm2
- 1c1:	66 0f f2 90 90 90 90 90 	pslld[ 	]+0x90909090\(%eax\),%xmm2
- 1c9:	66 0f f3 90 90 90 90 90 	psllq[ 	]+0x90909090\(%eax\),%xmm2
- 1d1:	66 0f f5 90 90 90 90 90 	pmaddwd 0x90909090\(%eax\),%xmm2
- 1d9:	66 0f f8 90 90 90 90 90 	psubb[ 	]+0x90909090\(%eax\),%xmm2
- 1e1:	66 0f f9 90 90 90 90 90 	psubw[ 	]+0x90909090\(%eax\),%xmm2
- 1e9:	66 0f fa 90 90 90 90 90 	psubd[ 	]+0x90909090\(%eax\),%xmm2
- 1f1:	66 0f fc 90 90 90 90 90 	paddb[ 	]+0x90909090\(%eax\),%xmm2
- 1f9:	66 0f fd 90 90 90 90 90 	paddw[ 	]+0x90909090\(%eax\),%xmm2
- 201:	66 0f fe 90 90 90 90 90 	paddd[ 	]+0x90909090\(%eax\),%xmm2
+[ 	]+f9:	66 0f 74 90 90 90 90 90 	pcmpeqb -0x6f6f6f70\(%eax\),%xmm2
+ 101:	66 0f 75 90 90 90 90 90 	pcmpeqw -0x6f6f6f70\(%eax\),%xmm2
+ 109:	66 0f 76 90 90 90 90 90 	pcmpeqd -0x6f6f6f70\(%eax\),%xmm2
+ 111:	66 0f 7e 90 90 90 90 90 	movd[ 	]+%xmm2,-0x6f6f6f70\(%eax\)
+ 119:	66 0f d6 90 90 90 90 90 	movq[ 	]+%xmm2,-0x6f6f6f70\(%eax\)
+ 121:	66 0f d1 90 90 90 90 90 	psrlw[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 129:	66 0f d2 90 90 90 90 90 	psrld[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 131:	66 0f d3 90 90 90 90 90 	psrlq[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 139:	66 0f d5 90 90 90 90 90 	pmullw -0x6f6f6f70\(%eax\),%xmm2
+ 141:	66 0f d8 90 90 90 90 90 	psubusb -0x6f6f6f70\(%eax\),%xmm2
+ 149:	66 0f d9 90 90 90 90 90 	psubusw -0x6f6f6f70\(%eax\),%xmm2
+ 151:	66 0f db 90 90 90 90 90 	pand[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 159:	66 0f dc 90 90 90 90 90 	paddusb -0x6f6f6f70\(%eax\),%xmm2
+ 161:	66 0f dd 90 90 90 90 90 	paddusw -0x6f6f6f70\(%eax\),%xmm2
+ 169:	66 0f df 90 90 90 90 90 	pandn[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 171:	66 0f e1 90 90 90 90 90 	psraw[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 179:	66 0f e2 90 90 90 90 90 	psrad[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 181:	66 0f e5 90 90 90 90 90 	pmulhw -0x6f6f6f70\(%eax\),%xmm2
+ 189:	66 0f e8 90 90 90 90 90 	psubsb -0x6f6f6f70\(%eax\),%xmm2
+ 191:	66 0f e9 90 90 90 90 90 	psubsw -0x6f6f6f70\(%eax\),%xmm2
+ 199:	66 0f eb 90 90 90 90 90 	por[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1a1:	66 0f ec 90 90 90 90 90 	paddsb -0x6f6f6f70\(%eax\),%xmm2
+ 1a9:	66 0f ed 90 90 90 90 90 	paddsw -0x6f6f6f70\(%eax\),%xmm2
+ 1b1:	66 0f ef 90 90 90 90 90 	pxor[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1b9:	66 0f f1 90 90 90 90 90 	psllw[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1c1:	66 0f f2 90 90 90 90 90 	pslld[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1c9:	66 0f f3 90 90 90 90 90 	psllq[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1d1:	66 0f f5 90 90 90 90 90 	pmaddwd -0x6f6f6f70\(%eax\),%xmm2
+ 1d9:	66 0f f8 90 90 90 90 90 	psubb[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1e1:	66 0f f9 90 90 90 90 90 	psubw[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1e9:	66 0f fa 90 90 90 90 90 	psubd[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1f1:	66 0f fc 90 90 90 90 90 	paddb[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 1f9:	66 0f fd 90 90 90 90 90 	paddw[ 	]+-0x6f6f6f70\(%eax\),%xmm2
+ 201:	66 0f fe 90 90 90 90 90 	paddd[ 	]+-0x6f6f6f70\(%eax\),%xmm2
  209:	8d b4 26 00 00 00 00 	lea[ 	]+0x0\(%esi\),%esi
diff --git a/gas/testsuite/gas/i386/tlsd.d b/gas/testsuite/gas/i386/tlsd.d
index bbf6fd49cfa9..620a0d944081 100644
--- a/gas/testsuite/gas/i386/tlsd.d
+++ b/gas/testsuite/gas/i386/tlsd.d
@@ -28,6 +28,6 @@ Disassembly of section .text:
   31:	83 c6 00 [ 	]*add    \$0x0,%esi
   34:	8d 88 00 00 00 00 [ 	]*lea    0x0\(%eax\),%ecx
 [ 	]+36: R_386_TLS_LDO_32	baz
-  3a:	8b 5d fc [ 	]*mov    0xfffffffc\(%ebp\),%ebx
+  3a:	8b 5d fc [ 	]*mov    -0x4\(%ebp\),%ebx
   3d:	c9 [ 	]*leave[ 	]*
   3e:	c3 [ 	]*ret[ 	]*
diff --git a/gas/testsuite/gas/i386/tlspic.d b/gas/testsuite/gas/i386/tlspic.d
index bd5dbb7bace9..ccb292c3e685 100644
--- a/gas/testsuite/gas/i386/tlspic.d
+++ b/gas/testsuite/gas/i386/tlspic.d
@@ -25,6 +25,6 @@ Disassembly of section .text:
   2c:	65 8b 0d 00 00 00 00 [ 	]*mov    %gs:0x0,%ecx
   33:	03 8b 00 00 00 00 [ 	]*add    0x0\(%ebx\),%ecx
 [ 	]+35: R_386_TLS_GOTIE	foo
-  39:	8b 5d fc [ 	]*mov    0xfffffffc\(%ebp\),%ebx
+  39:	8b 5d fc [ 	]*mov    -0x4\(%ebp\),%ebx
   3c:	c9 [ 	]*leave[ 	]*
   3d:	c3 [ 	]*ret[ 	]*
diff --git a/gas/testsuite/gas/i386/white.l b/gas/testsuite/gas/i386/white.l
index c2d9157a2248..876c9d525f42 100644
--- a/gas/testsuite/gas/i386/white.l
+++ b/gas/testsuite/gas/i386/white.l
@@ -8,7 +8,7 @@ GAS LISTING .*
    5 0003 C705D711 00007B00 0000     	        mOvl \$ 123 , 4567 
    6 000d 678A787B                   	 ADDr16	mov 123 \( % bx , % si , 1 \) , % bh 
    7 0011 FFE0                       		jmp \* % eax 
-   8 0013 6626FF23                   	foo:	jmpw % es : \* \( % ebx \)	
+   8 0013 2666FF23                   	foo:	jmpw % es : \* \( % ebx \)	
    9                                	 
   10 0017 A0500000 00                		mov \( 0x8 \* 0Xa \) , % al 
   11 001c B020                       		mov \$ \( 8 \* 4 \) , % al 
diff --git a/gas/testsuite/gas/i386/x86-64-addr32-intel.d b/gas/testsuite/gas/i386/x86-64-addr32-intel.d
new file mode 100644
index 000000000000..90858dcc08fe
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-addr32-intel.d
@@ -0,0 +1,23 @@
+#as: -J
+#objdump: -drwMintel
+#name: x86-64 32-bit addressing (Intel mode)
+#source: x86-64-addr32.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+67 48 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+rax,\[[re]ax\+(0x)?0\].*
+[	 ]*8:[	 ]+67 49 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+rax,\[r8d?\+(0x)?0\].*
+[	 ]*10:[	 ]+67 48 8d 05 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+rax,\[[re]ip\+(0x)?0\].*
+[	 ]*18:[	 ]+67 48 8d 04 25 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+rax,ds:0x0.*
+[	 ]*21:[	 ]+67 a0 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+al,ds:0x600898
+[	 ]*27:[	 ]+67 66 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+ax,ds:0x600898
+[	 ]*2e:[	 ]+67 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+eax,ds:0x600898
+[	 ]*34:[	 ]+67 48 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+rax,ds:0x600898
+[	 ]*3b:[	 ]+67 a2 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+ds:0x600898,al
+[	 ]*41:[	 ]+67 66 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+ds:0x600898,ax
+[	 ]*48:[	 ]+67 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+ds:0x600898,eax
+[	 ]*4e:[	 ]+67 48 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+ds:0x600898,rax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-addr32.d b/gas/testsuite/gas/i386/x86-64-addr32.d
index c892fb1ba1d5..c08f382553ba 100644
--- a/gas/testsuite/gas/i386/x86-64-addr32.d
+++ b/gas/testsuite/gas/i386/x86-64-addr32.d
@@ -2,12 +2,21 @@
 #objdump: -drw
 #name: x86-64 32-bit addressing
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
 0+000 <.text>:
 [	 ]*0:[	 ]+67 48 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0\(%[re]ax\),%rax.*
 [	 ]*8:[	 ]+67 49 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0\(%r8d?\),%rax.*
-[	 ]*10:[	 ]+67 48 8d 05 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0\(%[re]ip\),%rax.*
+[	 ]*10:[	 ]+67 48 8d 05 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0\(%[re]ip\),%rax.*
 [	 ]*18:[	 ]+67 48 8d 04 25 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0,%rax.*
+[	 ]*21:[	 ]+67 a0 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%al
+[	 ]*27:[	 ]+67 66 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%ax
+[	 ]*2e:[	 ]+67 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%eax
+[	 ]*34:[	 ]+67 48 a1 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+0x600898,%rax
+[	 ]*3b:[	 ]+67 a2 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%al,0x600898
+[	 ]*41:[	 ]+67 66 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%ax,0x600898
+[	 ]*48:[	 ]+67 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%eax,0x600898
+[	 ]*4e:[	 ]+67 48 a3 98 08 60 00[	 ]+addr32[	 ]+mov[ 	]+%rax,0x600898
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-addr32.s b/gas/testsuite/gas/i386/x86-64-addr32.s
index d18cbb91bcfc..c32525ffa1fe 100644
--- a/gas/testsuite/gas/i386/x86-64-addr32.s
+++ b/gas/testsuite/gas/i386/x86-64-addr32.s
@@ -3,3 +3,11 @@
 	lea		symbol(%r8d), %rax
 	addr32 lea	symbol(%rip), %rax
 	addr32 lea	symbol, %rax
+	addr32 mov	0x600898,%al
+	addr32 mov	0x600898,%ax
+	addr32 mov	0x600898,%eax
+	addr32 mov	0x600898,%rax
+	addr32 mov	%al,0x600898
+	addr32 mov	%ax,0x600898
+	addr32 mov	%eax,0x600898
+	addr32 mov	%rax,0x600898
diff --git a/gas/testsuite/gas/i386/x86-64-amdfam10.d b/gas/testsuite/gas/i386/x86-64-amdfam10.d
new file mode 100644
index 000000000000..ed142b1d95eb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amdfam10.d
@@ -0,0 +1,27 @@
+#objdump: -dw
+#name: x86-64 amdfam10
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	f3 48 0f bd 19[ 	]+lzcnt  \(%rcx\),%rbx
+   5:	f3 0f bd 19[ 	]+lzcnt  \(%rcx\),%ebx
+   9:	66 f3 0f bd 19[ 	]+lzcnt  \(%rcx\),%bx
+   e:	f3 48 0f bd d9[ 	]+lzcnt  %rcx,%rbx
+  13:	f3 0f bd d9[ 	]+lzcnt  %ecx,%ebx
+  17:	66 f3 0f bd d9[ 	]+lzcnt  %cx,%bx
+  1c:	f3 48 0f b8 19[ 	]+popcnt \(%rcx\),%rbx
+  21:	f3 0f b8 19[ 	]+popcnt \(%rcx\),%ebx
+  25:	66 f3 0f b8 19[ 	]+popcnt \(%rcx\),%bx
+  2a:	f3 48 0f b8 d9[ 	]+popcnt %rcx,%rbx
+  2f:	f3 0f b8 d9[ 	]+popcnt %ecx,%ebx
+  33:	66 f3 0f b8 d9[ 	]+popcnt %cx,%bx
+  38:	66 0f 79 ca[ 	]+extrq  %xmm2,%xmm1
+  3c:	66 0f 78 c1 02 04[ 	]+extrq  \$0x4,\$0x2,%xmm1
+  42:	f2 0f 79 ca[ 	]+insertq %xmm2,%xmm1
+  46:	f2 0f 78 ca 02 04[ 	]+insertq \$0x4,\$0x2,%xmm2,%xmm1
+  4c:	f2 0f 2b 09[ 	]+movntsd %xmm1,\(%rcx\)
+  50:	f3 0f 2b 09[ 	]+movntss %xmm1,\(%rcx\)
+	...
diff --git a/gas/testsuite/gas/i386/x86-64-amdfam10.s b/gas/testsuite/gas/i386/x86-64-amdfam10.s
new file mode 100644
index 000000000000..df0416443b09
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-amdfam10.s
@@ -0,0 +1,25 @@
+#AMDFAM10 New Instructions
+
+	.text
+foo:
+	lzcnt	(%rcx),%rbx
+	lzcnt	(%rcx),%ebx
+	lzcnt	(%rcx),%bx
+	lzcnt	%rcx,%rbx
+	lzcnt	%ecx,%ebx
+	lzcnt	%cx,%bx
+	popcnt	(%rcx),%rbx
+	popcnt	(%rcx),%ebx
+	popcnt	(%rcx),%bx
+	popcnt	%rcx,%rbx
+	popcnt	%ecx,%ebx
+	popcnt	%cx,%bx
+	extrq	%xmm2,%xmm1
+	extrq	$4,$2,%xmm1
+	insertq	%xmm2,%xmm1
+	insertq	$4,$2,%xmm2,%xmm1
+	movntsd	%xmm1,(%rcx)
+	movntss %xmm1,(%rcx)
+
+	# Force a good alignment.
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
index 7ddd6fe17778..17c46a752b1c 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -2,7 +2,7 @@
 #objdump: -drw
 #name: x86-64 indirect branch
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
@@ -11,3 +11,4 @@ Disassembly of section .text:
 [	 ]*2:[	 ]+ff d0[	 ]+callq[	 ]+\*%rax
 [	 ]*4:[	 ]+ff e0[	 ]+jmpq[	 ]+\*%rax
 [	 ]*6:[	 ]+ff e0[	 ]+jmpq[	 ]+\*%rax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-cbw-intel.d b/gas/testsuite/gas/i386/x86-64-cbw-intel.d
new file mode 100644
index 000000000000..616ffad9f259
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cbw-intel.d
@@ -0,0 +1,26 @@
+#source: x86-64-cbw.s
+#objdump: -dwMintel
+#name: x86-64 CBW/CWD & Co (Intel disassembly)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_cbw>:
+   0:	66 98                	cbw    
+   2:	98                   	cwde   
+   3:	48 98                	cdqe   
+   5:	66 40 98             	rex cbw    
+   8:	40 98                	rex cwde   
+   a:	66                   	data16
+   b:	48 98                	cdqe   
+
+0+00d <_cwd>:
+   d:	66 99                	cwd    
+   f:	99                   	cdq    
+  10:	48 99                	cqo    
+  12:	66 40 99             	rex cwd    
+  15:	40 99                	rex cdq    
+  17:	66                   	data16
+  18:	48 99                	cqo    
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-cbw.d b/gas/testsuite/gas/i386/x86-64-cbw.d
new file mode 100644
index 000000000000..5474ce2859ba
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cbw.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: x86-64 CBW/CWD & Co
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_cbw>:
+   0:	66 98                	cbtw   
+   2:	98                   	cwtl   
+   3:	48 98                	cltq   
+   5:	66 40 98             	rex cbtw   
+   8:	40 98                	rex cwtl   
+   a:	66                   	data16
+   b:	48 98                	cltq   
+
+0+00d <_cwd>:
+   d:	66 99                	cwtd   
+   f:	99                   	cltd   
+  10:	48 99                	cqto   
+  12:	66 40 99             	rex cwtd   
+  15:	40 99                	rex cltd   
+  17:	66                   	data16
+  18:	48 99                	cqto   
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-cbw.s b/gas/testsuite/gas/i386/x86-64-cbw.s
new file mode 100644
index 000000000000..085c2797348e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cbw.s
@@ -0,0 +1,18 @@
+ .intel_syntax noprefix
+ .text
+_cbw:
+	cbw
+	cwde
+	cdqe
+	rex cbw
+	rex cwde
+	rex64 cbw
+_cwd:
+	cwd
+	cdq
+	cqo
+	rex cwd
+	rex cdq
+	rex64 cwd
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-crc32-intel.d b/gas/testsuite/gas/i386/x86-64-crc32-intel.d
new file mode 100644
index 000000000000..24bd66dd001e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crc32-intel.d
@@ -0,0 +1,35 @@
+#objdump: -drwMintel
+#name: x86-64 crc32 (Intel mode)
+#source: x86-64-crc32.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32  eax,BYTE PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 06    	crc32  rax,BYTE PTR \[rsi\]
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32  eax,WORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32  eax,DWORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 06    	crc32  rax,QWORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32  rax,al
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32  rax,al
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32  rax,rax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32  rax,rax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 06    	crc32  rax,BYTE PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32  eax,BYTE PTR \[rsi\]
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32  eax,WORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32  eax,DWORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 06    	crc32  rax,QWORD PTR \[rsi\]
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32  eax,al
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32  rax,al
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32  eax,ax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32  eax,eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32  rax,rax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-crc32.d b/gas/testsuite/gas/i386/x86-64-crc32.d
new file mode 100644
index 000000000000..1a33fac02d85
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crc32.d
@@ -0,0 +1,34 @@
+#objdump: -dw
+#name: x86-64 crc32
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32b \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 06    	crc32b \(%rsi\),%rax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32w \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32l \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 06    	crc32q \(%rsi\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32b %al,%rax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32b %al,%rax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32q %rax,%rax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32q %rax,%rax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 06    	crc32b \(%rsi\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 06       	crc32b \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 06    	crc32w \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 06       	crc32l \(%rsi\),%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 06    	crc32q \(%rsi\),%rax
+[ 	]*[a-f0-9]+:	f2 0f 38 f0 c0       	crc32b %al,%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f0 c0    	crc32b %al,%rax
+[ 	]*[a-f0-9]+:	66 f2 0f 38 f1 c0    	crc32w %ax,%eax
+[ 	]*[a-f0-9]+:	f2 0f 38 f1 c0       	crc32l %eax,%eax
+[ 	]*[a-f0-9]+:	f2 48 0f 38 f1 c0    	crc32q %rax,%rax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-crc32.s b/gas/testsuite/gas/i386/x86-64-crc32.s
new file mode 100644
index 000000000000..7ebe894e3413
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crc32.s
@@ -0,0 +1,34 @@
+# Check 64bit crc32 in SSE4.2
+
+	.text
+foo:
+
+crc32b (%rsi), %eax
+crc32b (%rsi), %rax
+crc32w (%rsi), %eax
+crc32l (%rsi), %eax
+crc32q (%rsi), %rax
+crc32  %al, %eax
+crc32b  %al, %eax
+crc32  %al, %rax
+crc32b  %al, %rax
+crc32  %ax, %eax
+crc32w  %ax, %eax
+crc32  %eax, %eax
+crc32l  %eax, %eax
+crc32  %rax, %rax
+crc32q  %rax, %rax
+
+.intel_syntax noprefix
+crc32  rax,byte ptr [rsi]
+crc32  eax,byte ptr [rsi]
+crc32  eax, word ptr [rsi]
+crc32  eax,dword ptr [rsi]
+crc32  rax,qword ptr [rsi]
+crc32  eax,al
+crc32  rax,al
+crc32  eax, ax
+crc32  eax,eax
+crc32  rax,rax
+
+.p2align 4,0
diff --git a/gas/testsuite/gas/i386/x86-64-crx-suffix.d b/gas/testsuite/gas/i386/x86-64-crx-suffix.d
index 1dc3584219ed..6dfd47cdef65 100644
--- a/gas/testsuite/gas/i386/x86-64-crx-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-crx-suffix.d
@@ -2,7 +2,7 @@
 #name: x86-64 control register related opcodes (with suffixes)
 #source: x86-64-crx.s
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-crx.d b/gas/testsuite/gas/i386/x86-64-crx.d
index 8c1333f53693..62abe70301a5 100644
--- a/gas/testsuite/gas/i386/x86-64-crx.d
+++ b/gas/testsuite/gas/i386/x86-64-crx.d
@@ -2,7 +2,7 @@
 #name: x86-64 control register related opcodes
 #source: x86-64-crx.s
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-drx-suffix.d b/gas/testsuite/gas/i386/x86-64-drx-suffix.d
index 1f76b8b163b8..254e24defc4d 100644
--- a/gas/testsuite/gas/i386/x86-64-drx-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-drx-suffix.d
@@ -2,7 +2,7 @@
 #name: x86-64 debug register related opcodes (with suffixes)
 #source: x86-64-drx.s
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-drx.d b/gas/testsuite/gas/i386/x86-64-drx.d
index 879ce50a5ef8..18b328f9b30c 100644
--- a/gas/testsuite/gas/i386/x86-64-drx.d
+++ b/gas/testsuite/gas/i386/x86-64-drx.d
@@ -1,7 +1,7 @@
 #objdump: -dw
 #name: x86-64 debug register related opcodes
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-gidt.d b/gas/testsuite/gas/i386/x86-64-gidt.d
new file mode 100644
index 000000000000..d8b0a0671a26
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-gidt.d
@@ -0,0 +1,17 @@
+#objdump: -dw
+#name: 64bit load/store global/interrupt description table register.
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 01 08 [ 	]*sidt   \(%rax\)
+   3:	0f 01 18 [ 	]*lidt   \(%rax\)
+   6:	0f 01 00 [ 	]*sgdt   \(%rax\)
+   9:	0f 01 10 [ 	]*lgdt   \(%rax\)
+   c:	0f 01 08 [ 	]*sidt   \(%rax\)
+   f:	0f 01 18 [ 	]*lidt   \(%rax\)
+  12:	0f 01 00 [ 	]*sgdt   \(%rax\)
+  15:	0f 01 10 [ 	]*lgdt   \(%rax\)
+	...
diff --git a/gas/testsuite/gas/i386/x86-64-gidt.s b/gas/testsuite/gas/i386/x86-64-gidt.s
new file mode 100644
index 000000000000..dd2028910b92
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-gidt.s
@@ -0,0 +1,14 @@
+# Instructions to load/store global/interrupt description table
+# register.
+
+	.text
+foo:
+	sidt (%rax)
+	lidt (%rax)
+	sgdt (%rax)
+	lgdt (%rax)
+	sidtq (%rax)
+	lidtq (%rax)
+	sgdtq (%rax)
+	lgdtq (%rax)
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.l b/gas/testsuite/gas/i386/x86-64-inval-crc32.l
new file mode 100644
index 000000000000..b4a8eaabcf67
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:6: Error: .*
+.*:7: Error: .*
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:14: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\# Check illegal 64bit crc32 in SSE4\.2
+[ 	]*2[ 	]+
+[ 	]*3[ 	]+\.text
+[ 	]*4[ 	]+foo:
+[ 	]*5[ 	]+
+[ 	]*6[ 	]+crc32b \(%rsi\), %al
+[ 	]*7[ 	]+crc32w \(%rsi\), %ax
+[ 	]*8[ 	]+crc32 \(%rsi\), %al
+[ 	]*9[ 	]+crc32 \(%rsi\), %ax
+[ 	]*10[ 	]+crc32 \(%rsi\), %eax
+[ 	]*11[ 	]+crc32 \(%rsi\), %rax
+[ 	]*12[ 	]+crc32  %al, %al
+[ 	]*13[ 	]+crc32b  %al, %al
+[ 	]*14[ 	]+crc32  %ax, %ax
+[ 	]*15[ 	]+crc32w  %ax, %ax
+[ 	]*16[ 	]+crc32  %rax, %eax
+[ 	]*17[ 	]+crc32  %eax, %rax
+[ 	]*18[ 	]+crc32l  %rax, %eax
+[ 	]*19[ 	]+crc32l  %eax, %rax
+[ 	]*20[ 	]+crc32q  %eax, %rax
+[ 	]*21[ 	]+crc32q  %rax, %eax
+[ 	]*22[ 	]+
+[ 	]*23[ 	]+\.intel_syntax noprefix
+[ 	]*24[ 	]+crc32  al,byte ptr \[rsi\]
+[ 	]*25[ 	]+crc32  ax, word ptr \[rsi\]
+[ 	]*26[ 	]+crc32  rax,word ptr \[rsi\]
+[ 	]*27[ 	]+crc32  rax,dword ptr \[rsi\]
+[ 	]*28[ 	]+crc32  al,\[rsi\]
+[ 	]*29[ 	]+crc32  ax,\[rsi\]
+[ 	]*30[ 	]+crc32  eax,\[rsi\]
+[ 	]*31[ 	]+crc32  rax,\[rsi\]
+[ 	]*32[ 	]+crc32  al,al
+[ 	]*33[ 	]+crc32  ax, ax
+[ 	]*34[ 	]+crc32  rax,eax
diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.s b/gas/testsuite/gas/i386/x86-64-inval-crc32.s
new file mode 100644
index 000000000000..77408118ba77
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.s
@@ -0,0 +1,34 @@
+# Check illegal 64bit crc32 in SSE4.2
+
+	.text
+foo:
+
+crc32b (%rsi), %al
+crc32w (%rsi), %ax
+crc32 (%rsi), %al
+crc32 (%rsi), %ax
+crc32 (%rsi), %eax
+crc32 (%rsi), %rax
+crc32  %al, %al
+crc32b  %al, %al
+crc32  %ax, %ax
+crc32w  %ax, %ax
+crc32  %rax, %eax
+crc32  %eax, %rax
+crc32l  %rax, %eax
+crc32l  %eax, %rax
+crc32q  %eax, %rax
+crc32q  %rax, %eax
+
+.intel_syntax noprefix
+crc32  al,byte ptr [rsi]
+crc32  ax, word ptr [rsi]
+crc32  rax,word ptr [rsi]
+crc32  rax,dword ptr [rsi]
+crc32  al,[rsi]
+crc32  ax,[rsi]
+crc32  eax,[rsi]
+crc32  rax,[rsi]
+crc32  al,al
+crc32  ax, ax
+crc32  rax,eax
diff --git a/gas/testsuite/gas/i386/x86-64-inval.l b/gas/testsuite/gas/i386/x86-64-inval.l
index aa080cba46a6..87503e5bbde0 100644
--- a/gas/testsuite/gas/i386/x86-64-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-inval.l
@@ -48,6 +48,8 @@
 .*:49: Error: .*
 .*:50: Error: .*
 .*:51: Error: .*
+.*:52: Error: .*
+.*:54: Error: .*
 GAS LISTING .*
 
 
@@ -102,3 +104,6 @@ GAS LISTING .*
   49 [ 	]*pushfl		# can't have 32-bit stack operands
   50 [ 	]*popfl		# can't have 32-bit stack operands
   51 [ 	]*retl		# can't have 32-bit stack operands
+  52 [ 	]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register.
+  53 [ 	]*.intel_syntax noprefix
+  54 [ 	]*cmpxchg16b dword ptr \[rax\] # Must be oword
diff --git a/gas/testsuite/gas/i386/x86-64-inval.s b/gas/testsuite/gas/i386/x86-64-inval.s
index b069a282e5c5..f7a4379ad407 100644
--- a/gas/testsuite/gas/i386/x86-64-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-inval.s
@@ -49,3 +49,6 @@ foo:	jcxz foo	# No prefix exists to select CX as a counter
         pushfl		# can't have 32-bit stack operands
 	popfl		# can't have 32-bit stack operands
 	retl		# can't have 32-bit stack operands
+	insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register.
+	.intel_syntax noprefix
+	cmpxchg16b dword ptr [rax] # Must be oword
diff --git a/gas/testsuite/gas/i386/x86-64-io-intel.d b/gas/testsuite/gas/i386/x86-64-io-intel.d
new file mode 100644
index 000000000000..c6df6e68c3f0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-io-intel.d
@@ -0,0 +1,28 @@
+#source: x86-64-io.s
+#objdump: -dwMintel
+#name: x86-64 rex.W in/out (Intel disassembly)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_in>:
+   0:	48 ed                	rex.W in     eax,dx
+   2:	66                   	data16
+   3:	48 ed                	rex.W in     eax,dx
+
+0+005 <_out>:
+   5:	48 ef                	rex.W out    dx,eax
+   7:	66                   	data16
+   8:	48 ef                	rex.W out    dx,eax
+
+0+00a <_ins>:
+   a:	48 6d                	rex.W ins    DWORD PTR es:\[rdi\],dx
+   c:	66                   	data16
+   d:	48 6d                	rex.W ins    DWORD PTR es:\[rdi\],dx
+
+0+00f <_outs>:
+   f:	48 6f                	rex.W outs   dx,DWORD PTR ds:\[rsi\]
+  11:	66                   	data16
+  12:	48 6f                	rex.W outs   dx,DWORD PTR ds:\[rsi\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-io-suffix.d b/gas/testsuite/gas/i386/x86-64-io-suffix.d
new file mode 100644
index 000000000000..a0ee9d0289c7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-io-suffix.d
@@ -0,0 +1,28 @@
+#source: x86-64-io.s
+#objdump: -dwMsuffix
+#name: x86-64 rex.W in/out w/ suffix
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_in>:
+   0:	48 ed                	rex.W inl    \(%dx\),%eax
+   2:	66                   	data16
+   3:	48 ed                	rex.W inl    \(%dx\),%eax
+
+0+005 <_out>:
+   5:	48 ef                	rex.W outl   %eax,\(%dx\)
+   7:	66                   	data16
+   8:	48 ef                	rex.W outl   %eax,\(%dx\)
+
+0+00a <_ins>:
+   a:	48 6d                	rex.W insl   \(%dx\),%es:\(%rdi\)
+   c:	66                   	data16
+   d:	48 6d                	rex.W insl   \(%dx\),%es:\(%rdi\)
+
+0+00f <_outs>:
+   f:	48 6f                	rex.W outsl  %ds:\(%rsi\),\(%dx\)
+  11:	66                   	data16
+  12:	48 6f                	rex.W outsl  %ds:\(%rsi\),\(%dx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-io.d b/gas/testsuite/gas/i386/x86-64-io.d
new file mode 100644
index 000000000000..3e3b7e7bad24
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-io.d
@@ -0,0 +1,27 @@
+#objdump: -dw
+#name: x86-64 rex.W in/out
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_in>:
+   0:	48 ed                	rex.W in     \(%dx\),%eax
+   2:	66                   	data16
+   3:	48 ed                	rex.W in     \(%dx\),%eax
+
+0+005 <_out>:
+   5:	48 ef                	rex.W out    %eax,\(%dx\)
+   7:	66                   	data16
+   8:	48 ef                	rex.W out    %eax,\(%dx\)
+
+0+00a <_ins>:
+   a:	48 6d                	rex.W insl   \(%dx\),%es:\(%rdi\)
+   c:	66                   	data16
+   d:	48 6d                	rex.W insl   \(%dx\),%es:\(%rdi\)
+
+0+00f <_outs>:
+   f:	48 6f                	rex.W outsl  %ds:\(%rsi\),\(%dx\)
+  11:	66                   	data16
+  12:	48 6f                	rex.W outsl  %ds:\(%rsi\),\(%dx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-io.s b/gas/testsuite/gas/i386/x86-64-io.s
new file mode 100644
index 000000000000..58200c825b80
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-io.s
@@ -0,0 +1,16 @@
+ .intel_syntax noprefix
+ .text
+_in:
+	rex64 in eax,dx
+	rex64 in ax,dx
+_out:
+	rex64 out dx,eax
+	rex64 out dx,ax
+_ins:
+	rex64 insd
+	rex64 insw
+_outs:
+	rex64 outsd
+	rex64 outsw
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-merom.d b/gas/testsuite/gas/i386/x86-64-merom.d
index f15a6e466abc..4593e526ef25 100644
--- a/gas/testsuite/gas/i386/x86-64-merom.d
+++ b/gas/testsuite/gas/i386/x86-64-merom.d
@@ -70,4 +70,4 @@ Disassembly of section .text:
  116:	0f 38 1e c1[ 	]+pabsd  %mm1,%mm0
  11a:	66 0f 38 1e 01[ 	]+pabsd  \(%rcx\),%xmm0
  11f:	66 0f 38 1e c1[ 	]+pabsd  %xmm1,%xmm0
-	...
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-k8.d b/gas/testsuite/gas/i386/x86-64-nops-1-k8.d
new file mode 100644
index 000000000000..6785fbb065f9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops-1-k8.d
@@ -0,0 +1,177 @@
+#as: -mtune=k8
+#source: x86-64-nops-1.s
+#objdump: -drw
+#name: x86-64 -mtune=k8 nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*5:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*9:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*16:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*1a:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*1d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*27:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*2a:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*2d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*38:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*3c:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*49:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*4d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*5a:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*5d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*6a:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*6d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*7c:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*8d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*9d:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+[	 ]*ae:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+66 66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+66 66 90[	 ]+xchg[ 	]+%ax,%ax
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-merom.d b/gas/testsuite/gas/i386/x86-64-nops-1-merom.d
new file mode 100644
index 000000000000..2aa49aeeec62
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops-1-merom.d
@@ -0,0 +1,156 @@
+#as: -mtune=merom
+#source: x86-64-nops-1.s
+#objdump: -drw
+#name: x86-64 -mtune=merom nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+66 66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d
new file mode 100644
index 000000000000..c1886b605a71
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d
@@ -0,0 +1,161 @@
+#as: -mtune=nocona
+#source: x86-64-nops-1.s
+#objdump: -drw
+#name: x86-64 -mtune=nocona nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*8:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*19:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*29:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*3a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*4a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops-1.d b/gas/testsuite/gas/i386/x86-64-nops-1.d
new file mode 100644
index 000000000000..a6d8188754ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops-1.d
@@ -0,0 +1,160 @@
+#source: x86-64-nops-1.s
+#objdump: -drw
+#name: x86-64 nops 1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <nop15>:
+[	 ]*0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*1:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*8:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+10 <nop14>:
+[	 ]*10:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*11:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*12:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*19:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+20 <nop13>:
+[	 ]*20:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*21:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*22:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*23:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*29:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+30 <nop12>:
+[	 ]*30:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*31:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*32:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*33:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*34:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*3a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+40 <nop11>:
+[	 ]*40:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*41:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*42:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*43:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*44:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*45:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*4a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+50 <nop10>:
+[	 ]*50:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*51:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*52:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*53:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*54:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*55:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*56:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+
+0+60 <nop9>:
+[	 ]*60:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*61:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*62:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*63:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*64:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*65:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*66:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*67:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+70 <nop8>:
+[	 ]*70:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*71:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*72:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*73:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*74:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*75:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*76:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*77:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*78:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+80 <nop7>:
+[	 ]*80:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*81:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*82:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*83:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*84:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*85:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*86:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*87:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*88:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*89:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+90 <nop6>:
+[	 ]*90:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*91:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*92:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*93:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*94:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*95:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*96:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*97:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*98:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*99:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*9a:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+
+0+a0 <nop5>:
+[	 ]*a0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*a9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*aa:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ab:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+
+0+b0 <nop4>:
+[	 ]*b0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*b9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ba:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*bc:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%rax\)
+
+0+c0 <nop3>:
+[	 ]*c0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*c9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*ca:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cb:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*cd:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+
+0+d0 <nop2>:
+[	 ]*d0:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d1:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d2:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d3:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d4:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d5:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d6:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d7:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d8:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*d9:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*da:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*db:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dc:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*dd:[	 ]+90[	 ]+nop[ 	]*
+[	 ]*de:[	 ]+66 90[	 ]+xchg[ 	]+%ax,%ax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops-1.s b/gas/testsuite/gas/i386/x86-64-nops-1.s
new file mode 100644
index 000000000000..a4fd7694de76
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops-1.s
@@ -0,0 +1,147 @@
+	.text
+nop15:
+	nop
+	.p2align 4
+
+nop14:
+	nop
+	nop
+	.p2align 4
+
+nop13:
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop12:
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop11:
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop10:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop9:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop8:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop7:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop6:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop5:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop4:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop3:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
+
+nop2:
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/x86-64-nops.d b/gas/testsuite/gas/i386/x86-64-nops.d
new file mode 100644
index 000000000000..916361925359
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops.d
@@ -0,0 +1,37 @@
+#objdump: -drw
+#name: x86-64 nops
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+[	 ]*3:[	 ]+0f 1f 40 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*7:[	 ]+0f 1f 44 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*c:[	 ]+66 0f 1f 44 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*12:[	 ]+0f 1f 80 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax\)
+[	 ]*19:[	 ]+0f 1f 84 00 00 00 00 00[	 ]+nopl[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*21:[	 ]+66 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+0x0\(%rax,%rax,1\)
+[	 ]*2a:[	 ]+66 2e 0f 1f 84 00 00 00 00 00[	 ]+nopw[ 	]+%cs:0x0\(%rax,%rax,1\)
+[	 ]*34:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+[	 ]*37:[	 ]+48 0f 1f c0[	 ]+nop[ 	]+%rax
+[	 ]*3b:[	 ]+0f 1f c0[	 ]+nop[ 	]+%eax
+[	 ]*3e:[	 ]+66 0f 1f c0[	 ]+nop[ 	]+%ax
+[	 ]*42:[	 ]+48 0f 1f 00[	 ]+nopq[ 	]+\(%rax\)
+[	 ]*46:[	 ]+0f 1f 00[	 ]+nopl[ 	]+\(%rax\)
+[	 ]*49:[	 ]+66 0f 1f 00[	 ]+nopw[ 	]+\(%rax\)
+[	 ]*4d:[	 ]+48 0f 1f c0[	 ]+nop[ 	]+%rax
+[	 ]*51:[	 ]+0f 1f c0[	 ]+nop[ 	]+%eax
+[	 ]*54:[	 ]+66 0f 1f c0[	 ]+nop[ 	]+%ax
+[	 ]*58:[	 ]+41 0f 1f 02[	 ]+nopl[ 	]+\(%r10\)
+[	 ]*5c:[	 ]+49 0f 1f c2[	 ]+nop[ 	]+%r10
+[	 ]*60:[	 ]+41 0f 1f c2[	 ]+nop[ 	]+%r10d
+[	 ]*64:[	 ]+66 41 0f 1f c2[	 ]+nop[ 	]+%r10w
+[	 ]*69:[	 ]+49 0f 1f 02[	 ]+nopq[ 	]+\(%r10\)
+[	 ]*6d:[	 ]+41 0f 1f 02[	 ]+nopl[ 	]+\(%r10\)
+[	 ]*71:[	 ]+66 41 0f 1f 02[	 ]+nopw[ 	]+\(%r10\)
+[	 ]*76:[	 ]+49 0f 1f c2[	 ]+nop[ 	]+%r10
+[	 ]*7a:[	 ]+41 0f 1f c2[	 ]+nop[ 	]+%r10d
+[	 ]*7e:[	 ]+66 41 0f 1f c2[	 ]+nop[ 	]+%r10w
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-nops.s b/gas/testsuite/gas/i386/x86-64-nops.s
new file mode 100644
index 000000000000..2268e7f57699
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-nops.s
@@ -0,0 +1,33 @@
+	.text
+
+	.byte 0x0f, 0x1f, 0x0	
+	.byte 0x0f, 0x1f, 0x40, 0x0	
+	.byte 0x0f, 0x1f, 0x44, 0x0,  0x0	
+	.byte 0x66, 0x0f, 0x1f, 0x44, 0x0,  0x0	
+	.byte 0x0f, 0x1f, 0x80, 0x0,  0x0,  0x0, 0x0	
+	.byte 0x0f, 0x1f, 0x84, 0x0,  0x0,  0x0, 0x0, 0x0
+	.byte 0x66, 0x0f, 0x1f, 0x84, 0x0,  0x0, 0x0, 0x0, 0x0
+	.byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
+
+	nop (%rax) 
+	nop %rax
+	nop %eax
+	nop %ax
+	nopq (%rax) 
+	nopl (%rax) 
+	nopw (%rax) 
+	nopq %rax
+	nopl %eax
+	nopw %ax
+	nop (%r10) 
+	nop %r10
+	nop %r10d
+	nop %r10w
+	nopq (%r10) 
+	nopl (%r10) 
+	nopw (%r10) 
+	nopq %r10
+	nopl %r10d
+	nopw %r10w
+
+	.p2align 4
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index 13d58be1bdb8..912075e3bee9 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -2,7 +2,7 @@
 #objdump: -drw
 #name: x86-64 opcode
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
@@ -263,9 +263,33 @@ Disassembly of section .text:
 [	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
 [	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
 [	 ]*[0-9a-f]+:[	 ]+0f 00 c0[	 ]+sldt[	 ]+%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 0f 00 c0[	 ]+sldt[	 ]+%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 00 c0[	 ]+sldt[	 ]+%ax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 00 00[	 ]+sldt[	 ]+\(%rax\)[	 ]*(#.*)*
 [	 ]*[0-9a-f]+:[	 ]+e6 00[	 ]+out[	 ]+%al,\$0[x0]*[	 ]*(#.*)*
 [	 ]*[0-9a-f]+:[	 ]+66 e7 00[	 ]+out[	 ]+%ax,\$0[x0]*[	 ]*(#.*)*
 [	 ]*[0-9a-f]+:[	 ]+e7 00[	 ]+out[	 ]+%eax,\$0[x0]*[	 ]*(#.*)*
-[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
-[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
-[	 *]...
+[	 ]*[0-9a-f]+:[	 ]+66 90[	 ]+xchg[	 ]+%ax,%ax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+87 c0[	 ]+xchg[	 ]+%eax,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+90[	 ]+nop[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 90[	 ]+rex.W nop[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 90[	 ]+xchg[	 ]+%rax,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 90[	 ]+xchg[	 ]+%eax,%r8d[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 90[	 ]+xchg[	 ]+%eax,%r8d[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 91[	 ]+xchg[	 ]+%eax,%r9d[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 91[	 ]+xchg[	 ]+%eax,%r9d[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+93[	 ]+xchg[	 ]+%eax,%ebx[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+93[	 ]+xchg[	 ]+%eax,%ebx[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 90[	 ]+xchg[	 ]+%ax,%r8w[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 90[	 ]+xchg[	 ]+%ax,%r8w[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 91[	 ]+xchg[	 ]+%ax,%r9w[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 91[	 ]+xchg[	 ]+%ax,%r9w[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 0f 01 e0[	 ]+smsw[	 ]+%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 e0[	 ]+smsw[	 ]+%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 01 e0[	 ]+smsw[	 ]+%ax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 20[	 ]+smsw[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 0f 00 c8[	 ]+str[	 ]+%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 00 c8[	 ]+str[	 ]+%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 00 c8[	 ]+str[	 ]+%ax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 00 08[	 ]+str[	 ]+\(%rax\)[	 ]*(#.*)*
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index 8b132b390468..dd373427dde1 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -373,6 +373,9 @@
 	# SLDT
 #        SLDT (%eax)	              #  --  67	 -- --	 0F 00 00	                 ; A32 override: (Addr64) = ZEXT(Addr32 )
         SLDT %eax	              #  --  --	 -- --	 0F 00 C0
+        SLDT %rax	              #  --  --	 -- 48	 0F 00 C0
+        SLDT %ax	              #  66  --	 -- --	 0F 00 C0
+        SLDT (%rax)	              #  --  --	 -- --	 0F 00 00
 
 	# SWAPGS
 
@@ -387,4 +390,32 @@
 
 	# IN
 
+
+
+	xchg %ax,%ax		      # 66  --	 -- --	 90
+	xchg %eax,%eax		      # --  --	 -- --	 87 C0
+	xchg %rax,%rax		      # --  --	 -- --	 90
+	rex64 xchg %rax,%rax	      # --  --	 -- 48	 90
+	xchg %rax,%r8		      # --  --	 -- 49	 90
+	xchg %eax,%r8d		      # --  --	 -- 41	 90
+	xchg %r8d,%eax		      # --  --	 -- 41	 90
+	xchg %eax,%r9d		      # --  --	 -- 41	 91
+	xchg %r9d,%eax		      # --  --	 -- 41	 91
+	xchg %ebx,%eax		      # --  --	 -- 93
+	xchg %eax,%ebx		      # --  --	 -- 93
+	xchg %ax,%r8w		      # --  --	 -- 66 41 90
+	xchg %r8w,%ax		      # --  --	 -- 66 41 90
+	xchg %ax,%r9w		      # --  --	 -- 66 41 91
+	xchg %r9w,%ax		      # --  --	 -- 66 41 91
+
+        smsw %rax	              #  --  --	 -- 48	 0F 01 e0
+        smsw %eax	              #  --  --	 -- --	 0F 01 e0
+        smsw %ax	              #  66  --	 -- --	 0F 01 e0
+        smsw (%rax)	              #  --  --	 -- --	 0F 01 20
+
+        str %rax	              #  --  --	 -- 48	 0F 00 c8
+        str %eax	              #  --  --	 -- --	 0F 00 c8
+        str %ax		              #  66  --	 -- --	 0F 00 c8
+        str (%rax)	              #  --  --	 -- --	 0F 00 08
+
  .p2align 4,0
diff --git a/gas/testsuite/gas/i386/x86-64-pcrel.d b/gas/testsuite/gas/i386/x86-64-pcrel.d
index 3be86c7c3405..818ea2e6f734 100644
--- a/gas/testsuite/gas/i386/x86-64-pcrel.d
+++ b/gas/testsuite/gas/i386/x86-64-pcrel.d
@@ -1,7 +1,7 @@
 #objdump: -drw
 #name: x86-64 pcrel
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-prescott.d b/gas/testsuite/gas/i386/x86-64-prescott.d
index 43a2d2802027..26b9e6ec95f6 100644
--- a/gas/testsuite/gas/i386/x86-64-prescott.d
+++ b/gas/testsuite/gas/i386/x86-64-prescott.d
@@ -10,9 +10,9 @@ Disassembly of section .text:
    4:	66 0f d0 ca [ 	]*addsubpd %xmm2,%xmm1
    8:	f2 0f d0 13 [ 	]*addsubps \(%rbx\),%xmm2
    c:	f2 0f d0 dc [ 	]*addsubps %xmm4,%xmm3
-  10:	df 88 90 90 90 90 [ 	]*fisttp 0xffffffff90909090\(%rax\)
-  16:	db 88 90 90 90 90 [ 	]*fisttpl 0xffffffff90909090\(%rax\)
-  1c:	dd 88 90 90 90 90 [ 	]*fisttpll 0xffffffff90909090\(%rax\)
+  10:	df 88 90 90 90 90 [ 	]*fisttp -0x6f6f6f70\(%rax\)
+  16:	db 88 90 90 90 90 [ 	]*fisttpl -0x6f6f6f70\(%rax\)
+  1c:	dd 88 90 90 90 90 [ 	]*fisttpll -0x6f6f6f70\(%rax\)
   22:	66 0f 7c 65 00 [ 	]*haddpd 0x0\(%rbp\),%xmm4
   27:	66 0f 7c ee [ 	]*haddpd %xmm6,%xmm5
   2b:	f2 0f 7c 37 [ 	]*haddps \(%rdi\),%xmm6
diff --git a/gas/testsuite/gas/i386/x86-64-rep-suffix.d b/gas/testsuite/gas/i386/x86-64-rep-suffix.d
index a85b4a941779..68a90d9d6be4 100644
--- a/gas/testsuite/gas/i386/x86-64-rep-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-rep-suffix.d
@@ -8,8 +8,8 @@ Disassembly of section .text:
 0+000 <_start>:
    0:	f3 ac[ 	]+rep lodsb %ds:\(%rsi\),%al
    2:	f3 aa[ 	]+rep stosb %al,%es:\(%rdi\)
-   4:	f3 66 ad[ 	]+rep lodsw %ds:\(%rsi\),%ax
-   7:	f3 66 ab[ 	]+rep stosw %ax,%es:\(%rdi\)
+   4:	66 f3 ad[ 	]+rep lodsw %ds:\(%rsi\),%ax
+   7:	66 f3 ab[ 	]+rep stosw %ax,%es:\(%rdi\)
    a:	f3 ad[ 	]+rep lodsl %ds:\(%rsi\),%eax
    c:	f3 ab[ 	]+rep stosl %eax,%es:\(%rdi\)
    e:	f3 48 ad[ 	]+rep lodsq %ds:\(%rsi\),%rax
diff --git a/gas/testsuite/gas/i386/x86-64-rep.d b/gas/testsuite/gas/i386/x86-64-rep.d
index 631b7113d8e7..66fc03636c58 100644
--- a/gas/testsuite/gas/i386/x86-64-rep.d
+++ b/gas/testsuite/gas/i386/x86-64-rep.d
@@ -13,13 +13,13 @@ Disassembly of section .text:
    8:	f3 aa[ 	]+rep stos %al,%es:\(%rdi\)
    a:	f3 a6[ 	]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\)
    c:	f3 ae[ 	]+repz scas %es:\(%rdi\),%al
-   e:	f3 66 6d[ 	]+rep insw \(%dx\),%es:\(%rdi\)
-  11:	f3 66 6f[ 	]+rep outsw %ds:\(%rsi\),\(%dx\)
-  14:	f3 66 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
-  17:	f3 66 ad[ 	]+rep lods %ds:\(%rsi\),%ax
-  1a:	f3 66 ab[ 	]+rep stos %ax,%es:\(%rdi\)
-  1d:	f3 66 a7[ 	]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\)
-  20:	f3 66 af[ 	]+repz scas %es:\(%rdi\),%ax
+   e:	66 f3 6d[ 	]+rep insw \(%dx\),%es:\(%rdi\)
+  11:	66 f3 6f[ 	]+rep outsw %ds:\(%rsi\),\(%dx\)
+  14:	66 f3 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+  17:	66 f3 ad[ 	]+rep lods %ds:\(%rsi\),%ax
+  1a:	66 f3 ab[ 	]+rep stos %ax,%es:\(%rdi\)
+  1d:	66 f3 a7[ 	]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\)
+  20:	66 f3 af[ 	]+repz scas %es:\(%rdi\),%ax
   23:	f3 6d[ 	]+rep insl \(%dx\),%es:\(%rdi\)
   25:	f3 6f[ 	]+rep outsl %ds:\(%rsi\),\(%dx\)
   27:	f3 a5[ 	]+rep movsl %ds:\(%rsi\),%es:\(%rdi\)
@@ -32,30 +32,30 @@ Disassembly of section .text:
   37:	f3 48 ab[ 	]+rep stos %rax,%es:\(%rdi\)
   3a:	f3 48 a7[ 	]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\)
   3d:	f3 48 af[ 	]+repz scas %es:\(%rdi\),%rax
-  40:	f3 67 6c[ 	]+rep addr32 insb \(%dx\),%es:\(%edi\)
-  43:	f3 67 6e[ 	]+rep addr32 outsb %ds:\(%esi\),\(%dx\)
-  46:	f3 67 a4[ 	]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\)
-  49:	f3 67 ac[ 	]+rep addr32 lods %ds:\(%esi\),%al
-  4c:	f3 67 aa[ 	]+rep addr32 stos %al,%es:\(%edi\)
-  4f:	f3 67 a6[ 	]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\)
-  52:	f3 67 ae[ 	]+repz addr32 scas %es:\(%edi\),%al
-  55:	f3 67 66 6d[ 	]+rep addr32 insw \(%dx\),%es:\(%edi\)
-  59:	f3 67 66 6f[ 	]+rep addr32 outsw %ds:\(%esi\),\(%dx\)
-  5d:	f3 67 66 a5[ 	]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\)
-  61:	f3 67 66 ad[ 	]+rep addr32 lods %ds:\(%esi\),%ax
-  65:	f3 67 66 ab[ 	]+rep addr32 stos %ax,%es:\(%edi\)
-  69:	f3 67 66 a7[ 	]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\)
-  6d:	f3 67 66 af[ 	]+repz addr32 scas %es:\(%edi\),%ax
-  71:	f3 67 6d[ 	]+rep addr32 insl \(%dx\),%es:\(%edi\)
-  74:	f3 67 6f[ 	]+rep addr32 outsl %ds:\(%esi\),\(%dx\)
-  77:	f3 67 a5[ 	]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\)
-  7a:	f3 67 ad[ 	]+rep addr32 lods %ds:\(%esi\),%eax
-  7d:	f3 67 ab[ 	]+rep addr32 stos %eax,%es:\(%edi\)
-  80:	f3 67 a7[ 	]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\)
-  83:	f3 67 af[ 	]+repz addr32 scas %es:\(%edi\),%eax
-  86:	f3 67 48 a5[ 	]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\)
-  8a:	f3 67 48 ad[ 	]+rep addr32 lods %ds:\(%esi\),%rax
-  8e:	f3 67 48 ab[ 	]+rep addr32 stos %rax,%es:\(%edi\)
-  92:	f3 67 48 a7[ 	]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\)
-  96:	f3 67 48 af[ 	]+repz addr32 scas %es:\(%edi\),%rax
+  40:	67 f3 6c[ 	]+rep addr32 insb \(%dx\),%es:\(%edi\)
+  43:	67 f3 6e[ 	]+rep addr32 outsb %ds:\(%esi\),\(%dx\)
+  46:	67 f3 a4[ 	]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\)
+  49:	67 f3 ac[ 	]+rep addr32 lods %ds:\(%esi\),%al
+  4c:	67 f3 aa[ 	]+rep addr32 stos %al,%es:\(%edi\)
+  4f:	67 f3 a6[ 	]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\)
+  52:	67 f3 ae[ 	]+repz addr32 scas %es:\(%edi\),%al
+  55:	67 66 f3 6d[ 	]+rep addr32 insw \(%dx\),%es:\(%edi\)
+  59:	67 66 f3 6f[ 	]+rep addr32 outsw %ds:\(%esi\),\(%dx\)
+  5d:	67 66 f3 a5[ 	]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\)
+  61:	67 66 f3 ad[ 	]+rep addr32 lods %ds:\(%esi\),%ax
+  65:	67 66 f3 ab[ 	]+rep addr32 stos %ax,%es:\(%edi\)
+  69:	67 66 f3 a7[ 	]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\)
+  6d:	67 66 f3 af[ 	]+repz addr32 scas %es:\(%edi\),%ax
+  71:	67 f3 6d[ 	]+rep addr32 insl \(%dx\),%es:\(%edi\)
+  74:	67 f3 6f[ 	]+rep addr32 outsl %ds:\(%esi\),\(%dx\)
+  77:	67 f3 a5[ 	]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\)
+  7a:	67 f3 ad[ 	]+rep addr32 lods %ds:\(%esi\),%eax
+  7d:	67 f3 ab[ 	]+rep addr32 stos %eax,%es:\(%edi\)
+  80:	67 f3 a7[ 	]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\)
+  83:	67 f3 af[ 	]+repz addr32 scas %es:\(%edi\),%eax
+  86:	67 f3 48 a5[ 	]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\)
+  8a:	67 f3 48 ad[ 	]+rep addr32 lods %ds:\(%esi\),%rax
+  8e:	67 f3 48 ab[ 	]+rep addr32 stos %rax,%es:\(%edi\)
+  92:	67 f3 48 a7[ 	]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\)
+  96:	67 f3 48 af[ 	]+repz addr32 scas %es:\(%edi\),%rax
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-rip-intel.d b/gas/testsuite/gas/i386/x86-64-rip-intel.d
new file mode 100644
index 000000000000..162f654c556d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rip-intel.d
@@ -0,0 +1,15 @@
+#as: -J
+#objdump: -drwMintel
+#name: x86-64 rip addressing (Intel mode)
+#source: x86-64-rip.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+eax,\[rip\+0x0\][ 	]*(#.*)?
+[	 ]*6:[	 ]+8d 05 11 11 11 11[	 ]+lea[	 ]+eax,\[rip\+0x11111111\][ 	]*(#.*)?
+[	 ]*c:[	 ]+8d 05 01 00 00 00[	 ]+lea[	 ]+eax,\[rip\+0x1\][ 	]*(#.*)?
+[	 ]*12:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+eax,\[rip\+0x0\][ 	]*(#.*)?
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rip.d b/gas/testsuite/gas/i386/x86-64-rip.d
index 1b1d6c8a31c5..66fe771b9608 100644
--- a/gas/testsuite/gas/i386/x86-64-rip.d
+++ b/gas/testsuite/gas/i386/x86-64-rip.d
@@ -2,12 +2,13 @@
 #objdump: -drw
 #name: x86-64 rip addressing
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
 0+000 <.text>:
-[	 ]*0:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0\(%rip\),%eax[ 	]*(#.*)?
-[	 ]*6:[	 ]+8d 05 11 11 11 11[	 ]+lea[	 ]+286331153\(%rip\),%eax[ 	]*(#.*)?
-[	 ]*c:[	 ]+8d 05 01 00 00 00[	 ]+lea[	 ]+1\(%rip\),%eax[ 	]*(#.*)?
-[	 ]*12:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*0:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0x0\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*6:[	 ]+8d 05 11 11 11 11[	 ]+lea[	 ]+0x11111111\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*c:[	 ]+8d 05 01 00 00 00[	 ]+lea[	 ]+0x1\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*12:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0x0\(%rip\),%eax[ 	]*(#.*)?
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-simd-intel.d b/gas/testsuite/gas/i386/x86-64-simd-intel.d
new file mode 100644
index 000000000000..799a9b314cf0
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d
@@ -0,0 +1,37 @@
+#source: x86-64-simd.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 SIMD (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 0f d0 0d 78 56 34 12 	addsubps xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 2f 0d 78 56 34 12 	comisd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 2f 0d 78 56 34 12 	comiss xmm1,DWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f e6 0d 78 56 34 12 	cvtdq2pd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f e6 0d 78 56 34 12 	cvtpd2dq xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 5a 0d 78 56 34 12 	cvtps2pd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 5b 0d 78 56 34 12 	cvttps2dq xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 7f 0d 78 56 34 12 	movdqu XMMWORD PTR \[rip\+0x12345678\],xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 6f 0d 78 56 34 12 	movdqu xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 17 0d 78 56 34 12 	movhpd QWORD PTR \[rip\+0x12345678\],xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 16 0d 78 56 34 12 	movhpd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 17 0d 78 56 34 12 	movhps QWORD PTR \[rip\+0x12345678\],xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 16 0d 78 56 34 12 	movhps xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 13 0d 78 56 34 12 	movlpd QWORD PTR \[rip\+0x12345678\],xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 12 0d 78 56 34 12 	movlpd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 13 0d 78 56 34 12 	movlps QWORD PTR \[rip\+0x12345678\],xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 12 0d 78 56 34 12 	movlps xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 16 0d 78 56 34 12 	movshdup xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 12 0d 78 56 34 12 	movsldup xmm1,XMMWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 70 0d 78 56 34 12 90 	pshufhw xmm1,XMMWORD PTR \[rip\+0x12345678\],0x90[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f 70 0d 78 56 34 12 90 	pshuflw xmm1,XMMWORD PTR \[rip\+0x12345678\],0x90[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 60 0d 78 56 34 12 	punpcklbw mm1,DWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 62 0d 78 56 34 12 	punpckldq mm1,DWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 61 0d 78 56 34 12 	punpcklwd mm1,DWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 2e 0d 78 56 34 12 	ucomisd xmm1,QWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 2e 0d 78 56 34 12 	ucomiss xmm1,DWORD PTR \[rip\+0x12345678\][ 	]*(#.*)?
diff --git a/gas/testsuite/gas/i386/x86-64-simd.d b/gas/testsuite/gas/i386/x86-64-simd.d
new file mode 100644
index 000000000000..f00b2c15ed80
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-simd.d
@@ -0,0 +1,36 @@
+#as: -J
+#objdump: -dw
+#name: x86-64 SIMD
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 0f d0 0d 78 56 34 12 	addsubps 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 2f 0d 78 56 34 12 	comisd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 2f 0d 78 56 34 12 	comiss 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f e6 0d 78 56 34 12 	cvtdq2pd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f e6 0d 78 56 34 12 	cvtpd2dq 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 5a 0d 78 56 34 12 	cvtps2pd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 5b 0d 78 56 34 12 	cvttps2dq 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f 7c 0d 78 56 34 12 	haddps 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 7f 0d 78 56 34 12 	movdqu %xmm1,0x12345678\(%rip\)[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 6f 0d 78 56 34 12 	movdqu 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 17 0d 78 56 34 12 	movhpd %xmm1,0x12345678\(%rip\)[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 16 0d 78 56 34 12 	movhpd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 17 0d 78 56 34 12 	movhps %xmm1,0x12345678\(%rip\)[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 16 0d 78 56 34 12 	movhps 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 13 0d 78 56 34 12 	movlpd %xmm1,0x12345678\(%rip\)[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 12 0d 78 56 34 12 	movlpd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 13 0d 78 56 34 12 	movlps %xmm1,0x12345678\(%rip\)[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 12 0d 78 56 34 12 	movlps 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 16 0d 78 56 34 12 	movshdup 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 12 0d 78 56 34 12 	movsldup 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f3 0f 70 0d 78 56 34 12 90 	pshufhw \$0x90,0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	f2 0f 70 0d 78 56 34 12 90 	pshuflw \$0x90,0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 60 0d 78 56 34 12 	punpcklbw 0x12345678\(%rip\),%mm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 62 0d 78 56 34 12 	punpckldq 0x12345678\(%rip\),%mm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 61 0d 78 56 34 12 	punpcklwd 0x12345678\(%rip\),%mm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	66 0f 2e 0d 78 56 34 12 	ucomisd 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
+[ 	]*[a-f0-9]+:	0f 2e 0d 78 56 34 12 	ucomiss 0x12345678\(%rip\),%xmm1[ 	]*(#.*)?
diff --git a/gas/testsuite/gas/i386/x86-64-simd.s b/gas/testsuite/gas/i386/x86-64-simd.s
new file mode 100644
index 000000000000..579c1ecbeda5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-simd.s
@@ -0,0 +1,29 @@
+	.text
+_start:
+	addsubps 0x12345678(%rip),%xmm1
+	comisd 0x12345678(%rip),%xmm1
+	comiss 0x12345678(%rip),%xmm1
+	cvtdq2pd 0x12345678(%rip),%xmm1
+	cvtpd2dq 0x12345678(%rip),%xmm1
+	cvtps2pd 0x12345678(%rip),%xmm1
+	cvttps2dq 0x12345678(%rip),%xmm1
+	haddps 0x12345678(%rip),%xmm1
+	movdqu %xmm1,0x12345678(%rip)
+	movdqu 0x12345678(%rip),%xmm1
+	movhpd %xmm1,0x12345678(%rip)
+	movhpd 0x12345678(%rip),%xmm1
+	movhps %xmm1,0x12345678(%rip)
+	movhps 0x12345678(%rip),%xmm1
+	movlpd %xmm1,0x12345678(%rip)
+	movlpd 0x12345678(%rip),%xmm1
+	movlps %xmm1,0x12345678(%rip)
+	movlps 0x12345678(%rip),%xmm1
+	movshdup 0x12345678(%rip),%xmm1
+	movsldup 0x12345678(%rip),%xmm1
+	pshufhw $0x90,0x12345678(%rip),%xmm1
+	pshuflw $0x90,0x12345678(%rip),%xmm1
+	punpcklbw 0x12345678(%rip),%mm1
+	punpckldq 0x12345678(%rip),%mm1
+	punpcklwd 0x12345678(%rip),%mm1
+	ucomisd 0x12345678(%rip),%xmm1
+	ucomiss 0x12345678(%rip),%xmm1
diff --git a/gas/testsuite/gas/i386/x86-64-sse4_1.d b/gas/testsuite/gas/i386/x86-64-sse4_1.d
new file mode 100644
index 000000000000..6ed99e28378a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-sse4_1.d
@@ -0,0 +1,110 @@
+#objdump: -dw
+#name: x86-64 SSE4.1
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]*[0-9a-f]+:	66 0f 3a 0d 01 00    	blendpd \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0d c1 00    	blendpd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0c 01 00    	blendps \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0c c1 00    	blendps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 15 01       	blendvpd %xmm0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 15 c1       	blendvpd %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 14 01       	blendvps %xmm0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 14 c1       	blendvps %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 41 01 00    	dppd   \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 41 c1 00    	dppd   \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 40 01 00    	dpps   \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 40 c1 00    	dpps   \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 48 0f 3a 17 c1 00 	extractps \$0x0,%xmm0,%rcx
+[ 	]*[0-9a-f]+:	66 0f 3a 17 c1 00    	extractps \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 17 01 00    	extractps \$0x0,%xmm0,\(%rcx\)
+[ 	]*[0-9a-f]+:	66 0f 3a 21 c1 00    	insertps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 21 01 00    	insertps \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2a 01       	movntdqa \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 42 01 00    	mpsadbw \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 42 c1 00    	mpsadbw \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2b 01       	packusdw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 2b c1       	packusdw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 10 01       	pblendvb %xmm0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 10 c1       	pblendvb %xmm0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0e 01 00    	pblendw \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0e c1 00    	pblendw \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 29 c1       	pcmpeqq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 29 01       	pcmpeqq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 48 0f 3a 14 c1 00 	pextrb \$0x0,%xmm0,%rcx
+[ 	]*[0-9a-f]+:	66 0f 3a 14 c1 00    	pextrb \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 14 01 00    	pextrb \$0x0,%xmm0,\(%rcx\)
+[ 	]*[0-9a-f]+:	66 0f 3a 16 c1 00    	pextrd \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 16 01 00    	pextrd \$0x0,%xmm0,\(%rcx\)
+[ 	]*[0-9a-f]+:	66 48 0f 3a 16 c1 00 	pextrq \$0x0,%xmm0,%rcx
+[ 	]*[0-9a-f]+:	66 48 0f 3a 16 01 00 	pextrq \$0x0,%xmm0,\(%rcx\)
+[ 	]*[0-9a-f]+:	66 48 0f c5 c8 00    	pextrw \$0x0,%xmm0,%rcx
+[ 	]*[0-9a-f]+:	66 0f c5 c8 00       	pextrw \$0x0,%xmm0,%ecx
+[ 	]*[0-9a-f]+:	66 0f 3a 15 01 00    	pextrw \$0x0,%xmm0,\(%rcx\)
+[ 	]*[0-9a-f]+:	66 0f 38 41 c1       	phminposuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 41 01       	phminposuw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 20 01 00    	pinsrb \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 20 c1 00    	pinsrb \$0x0,%ecx,%xmm0
+[ 	]*[0-9a-f]+:	66 48 0f 3a 20 c1 00 	pinsrb \$0x0,%rcx,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 22 01 00    	pinsrd \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 22 c1 00    	pinsrd \$0x0,%ecx,%xmm0
+[ 	]*[0-9a-f]+:	66 48 0f 3a 22 01 00 	pinsrq \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 48 0f 3a 22 c1 00 	pinsrq \$0x0,%rcx,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3c c1       	pmaxsb %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3c 01       	pmaxsb \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3d c1       	pmaxsd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3d 01       	pmaxsd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3f c1       	pmaxud %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3f 01       	pmaxud \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3e c1       	pmaxuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3e 01       	pmaxuw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 38 c1       	pminsb %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 38 01       	pminsb \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 39 c1       	pminsd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 39 01       	pminsd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3b c1       	pminud %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3b 01       	pminud \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3a c1       	pminuw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 3a 01       	pminuw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 20 c1       	pmovsxbw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 20 01       	pmovsxbw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 21 c1       	pmovsxbd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 21 01       	pmovsxbd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 22 c1       	pmovsxbq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 22 01       	pmovsxbq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 23 c1       	pmovsxwd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 23 01       	pmovsxwd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 24 c1       	pmovsxwq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 24 01       	pmovsxwq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 25 c1       	pmovsxdq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 25 01       	pmovsxdq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 30 c1       	pmovzxbw %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 30 01       	pmovzxbw \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 31 c1       	pmovzxbd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 31 01       	pmovzxbd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 32 c1       	pmovzxbq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 32 01       	pmovzxbq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 33 c1       	pmovzxwd %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 33 01       	pmovzxwd \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 34 c1       	pmovzxwq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 34 01       	pmovzxwq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 35 c1       	pmovzxdq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 35 01       	pmovzxdq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 28 c1       	pmuldq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 28 01       	pmuldq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 40 c1       	pmulld %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 40 01       	pmulld \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 17 c1       	ptest  %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 17 01       	ptest  \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 09 01 00    	roundpd \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 09 c1 00    	roundpd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 08 01 00    	roundps \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 08 c1 00    	roundps \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0b 01 00    	roundsd \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0b c1 00    	roundsd \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0a 01 00    	roundss \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 0a c1 00    	roundss \$0x0,%xmm1,%xmm0
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-sse4_1.s b/gas/testsuite/gas/i386/x86-64-sse4_1.s
new file mode 100644
index 000000000000..70c2394833a1
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-sse4_1.s
@@ -0,0 +1,107 @@
+# Streaming SIMD extensions 4.1 Instructions
+
+	.text
+foo:
+	blendpd		$0x0,(%rcx),%xmm0
+	blendpd		$0x0,%xmm1,%xmm0
+	blendps		$0x0,(%rcx),%xmm0
+	blendps		$0x0,%xmm1,%xmm0
+	blendvpd	%xmm0,(%rcx),%xmm0
+	blendvpd	%xmm0,%xmm1,%xmm0
+	blendvps	%xmm0,(%rcx),%xmm0
+	blendvps	%xmm0,%xmm1,%xmm0
+	dppd		$0x0,(%rcx),%xmm0
+	dppd		$0x0,%xmm1,%xmm0
+	dpps		$0x0,(%rcx),%xmm0
+	dpps		$0x0,%xmm1,%xmm0
+	extractps	$0x0,%xmm0,%rcx
+	extractps	$0x0,%xmm0,%ecx
+	extractps	$0x0,%xmm0,(%rcx)
+	insertps	$0x0,%xmm1,%xmm0
+	insertps	$0x0,(%rcx),%xmm0
+	movntdqa	(%rcx),%xmm0
+	mpsadbw		$0x0,(%rcx),%xmm0
+	mpsadbw		$0x0,%xmm1,%xmm0
+	packusdw	(%rcx),%xmm0
+	packusdw	%xmm1,%xmm0
+	pblendvb	%xmm0,(%rcx),%xmm0
+	pblendvb	%xmm0,%xmm1,%xmm0
+	pblendw		$0x0,(%rcx),%xmm0
+	pblendw		$0x0,%xmm1,%xmm0
+	pcmpeqq		%xmm1,%xmm0
+	pcmpeqq		(%rcx),%xmm0
+	pextrb          $0x0,%xmm0,%rcx
+	pextrb          $0x0,%xmm0,%ecx
+	pextrb          $0x0,%xmm0,(%rcx)
+	pextrd          $0x0,%xmm0,%ecx
+	pextrd          $0x0,%xmm0,(%rcx)
+	pextrq          $0x0,%xmm0,%rcx
+	pextrq          $0x0,%xmm0,(%rcx)
+	pextrw          $0x0,%xmm0,%rcx
+	pextrw          $0x0,%xmm0,%ecx
+	pextrw          $0x0,%xmm0,(%rcx)
+	phminposuw	%xmm1,%xmm0
+	phminposuw	(%rcx),%xmm0
+	pinsrb		$0x0,(%rcx),%xmm0
+	pinsrb		$0x0,%ecx,%xmm0
+	pinsrb		$0x0,%rcx,%xmm0
+	pinsrd		$0x0,(%rcx),%xmm0
+	pinsrd		$0x0,%ecx,%xmm0
+	pinsrq		$0x0,(%rcx),%xmm0
+	pinsrq		$0x0,%rcx,%xmm0
+	pmaxsb		%xmm1,%xmm0
+	pmaxsb		(%rcx),%xmm0
+	pmaxsd		%xmm1,%xmm0
+	pmaxsd		(%rcx),%xmm0
+	pmaxud		%xmm1,%xmm0
+	pmaxud		(%rcx),%xmm0
+	pmaxuw		%xmm1,%xmm0
+	pmaxuw		(%rcx),%xmm0
+	pminsb		%xmm1,%xmm0
+	pminsb		(%rcx),%xmm0
+	pminsd		%xmm1,%xmm0
+	pminsd		(%rcx),%xmm0
+	pminud		%xmm1,%xmm0
+	pminud		(%rcx),%xmm0
+	pminuw		%xmm1,%xmm0
+	pminuw		(%rcx),%xmm0
+	pmovsxbw	%xmm1,%xmm0
+	pmovsxbw	(%rcx),%xmm0
+	pmovsxbd	%xmm1,%xmm0
+	pmovsxbd	(%rcx),%xmm0
+	pmovsxbq	%xmm1,%xmm0
+	pmovsxbq	(%rcx),%xmm0
+	pmovsxwd	%xmm1,%xmm0
+	pmovsxwd	(%rcx),%xmm0
+	pmovsxwq	%xmm1,%xmm0
+	pmovsxwq	(%rcx),%xmm0
+	pmovsxdq	%xmm1,%xmm0
+	pmovsxdq	(%rcx),%xmm0
+	pmovzxbw	%xmm1,%xmm0
+	pmovzxbw	(%rcx),%xmm0
+	pmovzxbd	%xmm1,%xmm0
+	pmovzxbd	(%rcx),%xmm0
+	pmovzxbq	%xmm1,%xmm0
+	pmovzxbq	(%rcx),%xmm0
+	pmovzxwd	%xmm1,%xmm0
+	pmovzxwd	(%rcx),%xmm0
+	pmovzxwq	%xmm1,%xmm0
+	pmovzxwq	(%rcx),%xmm0
+	pmovzxdq	%xmm1,%xmm0
+	pmovzxdq	(%rcx),%xmm0
+	pmuldq		%xmm1,%xmm0
+	pmuldq		(%rcx),%xmm0
+	pmulld		%xmm1,%xmm0
+	pmulld		(%rcx),%xmm0
+	ptest		%xmm1,%xmm0
+	ptest		(%rcx),%xmm0
+	roundpd		$0x0,(%rcx),%xmm0
+	roundpd		$0x0,%xmm1,%xmm0
+	roundps		$0x0,(%rcx),%xmm0
+	roundps		$0x0,%xmm1,%xmm0
+	roundsd		$0x0,(%rcx),%xmm0
+	roundsd		$0x0,%xmm1,%xmm0
+	roundss		$0x0,(%rcx),%xmm0
+	roundss		$0x0,%xmm1,%xmm0
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.d b/gas/testsuite/gas/i386/x86-64-sse4_2.d
new file mode 100644
index 000000000000..379dbb54a1a9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-sse4_2.d
@@ -0,0 +1,45 @@
+#objdump: -dw
+#name: x86-64 SSE4.2
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 d9       	crc32b %cl,%ebx
+[ 	]*[0-9a-f]+:	f2 48 0f 38 f0 d9    	crc32b %cl,%rbx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 d9    	crc32w %cx,%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+[ 	]*[0-9a-f]+:	f2 48 0f 38 f1 d9    	crc32q %rcx,%rbx
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 19       	crc32b \(%rcx\),%ebx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 19    	crc32w \(%rcx\),%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 19       	crc32l \(%rcx\),%ebx
+[ 	]*[0-9a-f]+:	f2 48 0f 38 f1 19    	crc32q \(%rcx\),%rbx
+[ 	]*[0-9a-f]+:	f2 0f 38 f0 d9       	crc32b %cl,%ebx
+[ 	]*[0-9a-f]+:	f2 48 0f 38 f0 d9    	crc32b %cl,%rbx
+[ 	]*[0-9a-f]+:	66 f2 0f 38 f1 d9    	crc32w %cx,%ebx
+[ 	]*[0-9a-f]+:	f2 0f 38 f1 d9       	crc32l %ecx,%ebx
+[ 	]*[0-9a-f]+:	f2 48 0f 38 f1 d9    	crc32q %rcx,%rbx
+[ 	]*[0-9a-f]+:	66 0f 38 37 01       	pcmpgtq \(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 38 37 c1       	pcmpgtq %xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 61 01 00    	pcmpestri \$0x0,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 61 c1 00    	pcmpestri \$0x0,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 60 01 01    	pcmpestrm \$0x1,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 60 c1 01    	pcmpestrm \$0x1,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 63 01 02    	pcmpistri \$0x2,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 63 c1 02    	pcmpistri \$0x2,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 62 01 03    	pcmpistrm \$0x3,\(%rcx\),%xmm0
+[ 	]*[0-9a-f]+:	66 0f 3a 62 c1 03    	pcmpistrm \$0x3,%xmm1,%xmm0
+[ 	]*[0-9a-f]+:	66 f3 0f b8 19       	popcnt \(%rcx\),%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 19          	popcnt \(%rcx\),%ebx
+[ 	]*[0-9a-f]+:	f3 48 0f b8 19       	popcnt \(%rcx\),%rbx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 19       	popcnt \(%rcx\),%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 19          	popcnt \(%rcx\),%ebx
+[ 	]*[0-9a-f]+:	f3 48 0f b8 19       	popcnt \(%rcx\),%rbx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 d9       	popcnt %cx,%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[0-9a-f]+:	f3 48 0f b8 d9       	popcnt %rcx,%rbx
+[ 	]*[0-9a-f]+:	66 f3 0f b8 d9       	popcnt %cx,%bx
+[ 	]*[0-9a-f]+:	f3 0f b8 d9          	popcnt %ecx,%ebx
+[ 	]*[0-9a-f]+:	f3 48 0f b8 d9       	popcnt %rcx,%rbx
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.s b/gas/testsuite/gas/i386/x86-64-sse4_2.s
new file mode 100644
index 000000000000..9d59b10aab8e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-sse4_2.s
@@ -0,0 +1,42 @@
+# Streaming SIMD extensions 4.2 Instructions
+
+	.text
+foo:
+	crc32		%cl,%ebx
+	crc32		%cl,%rbx
+	crc32		%cx,%ebx
+	crc32		%ecx,%ebx
+	crc32		%rcx,%rbx
+	crc32b		(%rcx),%ebx
+	crc32w		(%rcx),%ebx
+	crc32l		(%rcx),%ebx
+	crc32q		(%rcx),%rbx
+	crc32b		%cl,%ebx
+	crc32b		%cl,%rbx
+	crc32w		%cx,%ebx
+	crc32l		%ecx,%ebx
+	crc32q		%rcx,%rbx
+	pcmpgtq		(%rcx),%xmm0
+	pcmpgtq		%xmm1,%xmm0
+	pcmpestri	$0x0,(%rcx),%xmm0
+	pcmpestri	$0x0,%xmm1,%xmm0
+	pcmpestrm	$0x1,(%rcx),%xmm0
+	pcmpestrm	$0x1,%xmm1,%xmm0
+	pcmpistri	$0x2,(%rcx),%xmm0
+	pcmpistri	$0x2,%xmm1,%xmm0
+	pcmpistrm	$0x3,(%rcx),%xmm0
+	pcmpistrm	$0x3,%xmm1,%xmm0
+	popcnt		(%rcx),%bx
+	popcnt		(%rcx),%ebx
+	popcnt		(%rcx),%rbx
+	popcntw		(%rcx),%bx
+	popcntl		(%rcx),%ebx
+	popcntq		(%rcx),%rbx
+	popcnt		%cx,%bx
+	popcnt		%ecx,%ebx
+	popcnt		%rcx,%rbx
+	popcntw		%cx,%bx
+	popcntl		%ecx,%ebx
+	popcntq		%rcx,%rbx
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-stack-intel.d b/gas/testsuite/gas/i386/x86-64-stack-intel.d
index 0dfab4d3fbe8..aaeff2ffcb39 100644
--- a/gas/testsuite/gas/i386/x86-64-stack-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-stack-intel.d
@@ -2,7 +2,7 @@
 #name: x86-64 stack-related opcodes (Intel mode)
 #source: x86-64-stack.s
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/x86-64-stack-suffix.d
index c5d789d8a71d..75fd900feae1 100644
--- a/gas/testsuite/gas/i386/x86-64-stack-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-stack-suffix.d
@@ -2,7 +2,7 @@
 #name: x86-64 stack-related opcodes (with suffixes)
 #source: x86-64-stack.s
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86-64-stack.d b/gas/testsuite/gas/i386/x86-64-stack.d
index fa010a981a12..f686a04fee88 100644
--- a/gas/testsuite/gas/i386/x86-64-stack.d
+++ b/gas/testsuite/gas/i386/x86-64-stack.d
@@ -1,7 +1,7 @@
 #objdump: -dw
 #name: x86-64 stack-related opcodes
 
-.*: +file format elf64-x86-64
+.*: +file format .*
 
 Disassembly of section .text:
 
diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index 60452a512735..a5bf0fdacc51 100644
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -6,7 +6,7 @@
 
 Disassembly of section .text:
 
-0+ <bar-0x1a7>:
+0+ <.*>:
 [ 	]+0:	01 ca[ 	]+add[ 	]+%ecx,%edx
 [ 	]+2:	44 01 ca[ 	]+add[ 	]+%r9d,%edx
 [ 	]+5:	41 01 ca[ 	]+add[ 	]+%ecx,%r10d
@@ -38,7 +38,7 @@ Disassembly of section .text:
 [ 	]+5a:	44 0f 20 c0[ 	]+mov[ 	]+%cr8,%rax
 [ 	]+5e:	44 0f 22 c0[ 	]+mov[ 	]+%rax,%cr8
 [ 	]+62:	f3 48 a5[ 	]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
-[ 	]+65:	f3 66 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]+65:	66 f3 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
 [ 	]+68:	f3 48 a5[ 	]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
 [ 	]+6b:	b0 11[ 	]+mov[ 	]+\$0x11,%al
 [ 	]+6d:	b4 11[ 	]+mov[ 	]+\$0x11,%ah
@@ -52,7 +52,7 @@ Disassembly of section .text:
 [ 	]+96:	41 03 00[ 	]+add[ 	]+\(%r8\),%eax
 [ 	]+99:	45 03 00[ 	]+add[ 	]+\(%r8\),%r8d
 [ 	]+9c:	49 03 00[ 	]+add[ 	]+\(%r8\),%rax
-[ 	]+9f:	03 05 22 22 22 22[ 	]+add[ 	]+572662306\(%rip\),%eax.*
+[ 	]+9f:	03 05 22 22 22 22[ 	]+add[ 	]+0x22222222\(%rip\),%eax.*
 [ 	]+a5:	03 45 00[ 	]+add[ 	]+0x0\(%rbp\),%eax
 [ 	]+a8:	03 04 25 22 22 22 22 	add[ 	]+0x22222222,%eax
 [ 	]+af:	41 03 45 00[ 	]+add[ 	]+0x0\(%r13\),%eax
@@ -84,10 +84,10 @@ Disassembly of section .text:
  10b:	83 04 81 11[ 	]+addl[ 	]+\$0x11,\(%rcx,%rax,4\)
  10f:	41 83 04 81 11[ 	]+addl[ 	]+\$0x11,\(%r9,%rax,4\)
  114:	42 83 04 81 11[ 	]+addl[ 	]+\$0x11,\(%rcx,%r8,4\)
- 119:	83 05 22 22 22 22 33 	addl[ 	]+\$0x33,572662306\(%rip\).*
- 120:	48 83 05 22 22 22 22 33 	addq[ 	]+\$0x33,572662306\(%rip\).*
- 128:	81 05 22 22 22 22 33 33 33 33 	addl[ 	]+\$0x33333333,572662306\(%rip\).*
- 132:	48 81 05 22 22 22 22 33 33 33 33 	addq[ 	]+\$0x33333333,572662306\(%rip\).*
+ 119:	83 05 22 22 22 22 33 	addl[ 	]+\$0x33,0x22222222\(%rip\).*
+ 120:	48 83 05 22 22 22 22 33 	addq[ 	]+\$0x33,0x22222222\(%rip\).*
+ 128:	81 05 22 22 22 22 33 33 33 33 	addl[ 	]+\$0x33333333,0x22222222\(%rip\).*
+ 132:	48 81 05 22 22 22 22 33 33 33 33 	addq[ 	]+\$0x33333333,0x22222222\(%rip\).*
  13d:	83 04 c5 22 22 22 22 33 	addl[ 	]+\$0x33,0x22222222\(,%rax,8\)
  145:	83 80 22 22 22 22 33 	addl[ 	]+\$0x33,0x22222222\(%rax\)
  14c:	83 80 22 22 22 22 33 	addl[ 	]+\$0x33,0x22222222\(%rax\)
@@ -113,7 +113,7 @@ Disassembly of section .text:
  1b9:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
  1c2:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
  1c9:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
- 1cf:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
+ 1cf:	8b 05 00 00 00 00[ 	]+mov[ 	]+0x0\(%rip\),%eax.*
  1d5:	b0 00[ 	]+mov[ 	]+\$0x0,%al
  1d7:	66 b8 00 00[ 	]+mov[ 	]+\$0x0,%ax
  1db:	b8 00 00 00 00[ 	]+mov[ 	]+\$0x0,%eax
@@ -121,7 +121,7 @@ Disassembly of section .text:
  1e7:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
  1f0:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
  1f7:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
- 1fd:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
+ 1fd:	8b 05 00 00 00 00[ 	]+mov[ 	]+0x0\(%rip\),%eax.*
 
 0+203 <foo>:
  203:	a0 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%al
@@ -156,4 +156,6 @@ Disassembly of section .text:
  2fc:	66 89 04 25 11 22 33 ff 	mov[ 	]+%ax,0xffffffffff332211
  304:	89 04 25 11 22 33 ff 	mov[ 	]+%eax,0xffffffffff332211
  30b:	48 89 04 25 11 22 33 ff 	mov[ 	]+%rax,0xffffffffff332211
+ 313:	48 0f c7 08[ 	]+cmpxchg16b \(%rax\)
+ 317:	48 0f c7 08[ 	]+cmpxchg16b \(%rax\)
 #pass
diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s
index 3e5532ab297b..aad9b2737754 100644
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -188,5 +188,10 @@ movw %ax,0xffffffffff332211
 movl %eax,0xffffffffff332211
 movq %rax,0xffffffffff332211
 
+cmpxchg16b (%rax)
+
+.intel_syntax noprefix
+cmpxchg16b oword ptr [rax]
+
 # Get a good alignment.
  .p2align	4,0
diff --git a/gas/testsuite/gas/i860/i860.exp b/gas/testsuite/gas/i860/i860.exp
index 041d859cc92a..39e40af26fd8 100644
--- a/gas/testsuite/gas/i860/i860.exp
+++ b/gas/testsuite/gas/i860/i860.exp
@@ -1,18 +1,5 @@
 # i860 assembler testsuite.
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "i860 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-        fail $testname
-        verbose "output is [file_contents "dump.out"]" 2
-        return
-    }
-    pass $testname
-}
-
 if [istarget i860-*-*] {
     run_dump_test "bitwise"
     run_dump_test "branch"
diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp
index f68c107f528b..3dfd10b8c343 100644
--- a/gas/testsuite/gas/ia64/ia64.exp
+++ b/gas/testsuite/gas/ia64/ia64.exp
@@ -1,19 +1,6 @@
 #
 # ia64 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "ia64 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 if [istarget "ia64-*"] then {
 
     run_dump_test "regs"
diff --git a/gas/testsuite/gas/lns/lns-common-1-alt.d b/gas/testsuite/gas/lns/lns-common-1-alt.d
new file mode 100644
index 000000000000..f76e8528ce35
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns-common-1-alt.d
@@ -0,0 +1,39 @@
+#source: lns-common-1.s
+#readelf: -wl
+#name: lns-common-1
+Dump of debug contents of section \.debug_line:
+#...
+  Initial value of 'is_stmt':  1
+#...
+ Line Number Statements:
+  Extended opcode 2: set Address to .*
+  Copy
+  Set column to 3
+  Advance Line by 1 to 2
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Set prologue_end to true
+  Advance Line by 1 to 3
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Set column to 0
+  Set epilogue_begin to true
+  Advance Line by 1 to 4
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Set ISA to 1
+  Set basic block
+  Advance Line by 1 to 5
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Set is_stmt to 0
+  Advance Line by 1 to 6
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Set is_stmt to 1
+  Advance Line by 1 to 7
+  Advance PC by fixed size amount .* to .*
+  Copy
+  Advance PC by fixed size amount .* to .*
+  Extended opcode 1: End of Sequence
+#...
diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp
index 1bc95990e3ea..2373290e8425 100644
--- a/gas/testsuite/gas/lns/lns.exp
+++ b/gas/testsuite/gas/lns/lns.exp
@@ -1,17 +1,3 @@
-# ??? This probably shouldn't be replicated here...
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "lns $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-        fail $testname
-        verbose "output is [file_contents "dump.out"]" 2
-        return
-    }
-    pass $testname
-}
-
 if ![is_elf_format] then {
     return
 }
@@ -21,7 +7,21 @@ run_list_test "lns-diag-1" ""
 # ??? Won't work on targets that don't have a bare "nop" insn.
 # Perhaps we could arrange for an include file or something that
 # defined a macro...
-if { ![istarget ia64*-*-*] && ![istarget i370-*-*] && ![istarget i960-*-*]
-     && ![istarget or32-*-*] && ![istarget s390*-*-*] } {
-  run_dump_test "lns-common-1"
+# Nor does it work on targets that do not generate line number
+# information (d10v).
+if {
+        ![istarget d10v-*-*]
+     && ![istarget ia64*-*-*]
+     && ![istarget i370-*-*]
+     && ![istarget i960-*-*]
+     && ![istarget mcore-*-*]
+     && ![istarget or32-*-*]
+     && ![istarget s390*-*-*]
+} {
+    # Use alternate file for targets using DW_LNS_fixed_advance_pc opcodes.
+    if { [istarget xtensa-*-*] } {
+      run_dump_test "lns-common-1-alt"
+    } else {
+      run_dump_test "lns-common-1"
+    }
 }
diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp
index 9516b1ab1dfc..ae9f993b7e41 100644
--- a/gas/testsuite/gas/m68k/all.exp
+++ b/gas/testsuite/gas/m68k/all.exp
@@ -13,7 +13,7 @@ if [istarget "m6811-*-*"] then {
 if [istarget "m6812-*-*"] then {
    return
 }
-if [istarget m68*-*-*] then {
+if { [istarget m68*-*-*] || [istarget fido*-*-*] } then {
     gas_test "t2.s" "" "" "cross-section branch"
     if [istarget m68*-motorola-sysv] then {
 	run_dump_test t2
@@ -29,17 +29,48 @@ if [istarget m68*-*-*] then {
     setup_xfail "*-*"
     clear_xfail "*-*-*elf*" "*-*-sysv4*" "*-*-rtems" "*-*-*gnu*" "*-*-psos*"
     run_dump_test pcrel
-    run_dump_test operands
-    run_dump_test cas
-    run_dump_test bitfield
+
+    # Since fido is basically CPU32, it does not support those
+    # instructions beyond CPU32.  Disable those tests that test them.
+    if ![istarget fido-*-*] then {
+	run_dump_test operands
+	run_dump_test cas
+	run_dump_test bitfield
+    } else {
+	# Test fido-specific instructions.
+	run_dump_test fido
+    }
+
     run_dump_test link
-    run_dump_test fmoveml
+
+    # fido does not have a floating point unit.
+    if ![istarget fido-*-*] then {
+	run_dump_test fmoveml
+    }
+
     run_dump_test mcf-mov3q
     run_dump_test mode5
     run_dump_test mcf-mac
     run_dump_test mcf-emac
+    run_dump_test mcf-coproc
     run_dump_test mcf-fpu
-    run_dump_test arch-cpu-1
+    run_dump_test mcf-trap
+    run_dump_test mcf-wdebug
+    if { [istarget *-*-elf] || [istarget *-*-linux*] } then {
+      run_dump_test arch-cpu-1
+    }
+    run_dump_test cpu32
+
+    run_dump_test br-isaa
+    run_dump_test br-isab
+    run_dump_test br-isac
+
+    run_dump_test ctrl-1
+    run_dump_test ctrl-2
+
+    if { [istarget *-*-netbsd] } then {
+      run_dump_test p3041
+    }
 
     set testname "68000 operands"
     gas_run "operands.s" "-m68000" "2>err.out"
diff --git a/gas/testsuite/gas/m68k/br-isaa.d b/gas/testsuite/gas/m68k/br-isaa.d
new file mode 100644
index 000000000000..0b49dc2ea237
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isaa.d
@@ -0,0 +1,15 @@
+#name: br-isaa.d
+#objdump: -d
+#as: -march=isaa -pcrel
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+   0:	4e71           	nop
+   2:	60fc           	bras 0 <foo>
+   4:	6000 0000      	braw 6 <foo\+0x6>
+   8:	61f6           	bsrs 0 <foo>
+   a:	6100 0000      	bsrw c <foo\+0xc>
+   e:	4e71           	nop
diff --git a/gas/testsuite/gas/m68k/br-isaa.s b/gas/testsuite/gas/m68k/br-isaa.s
new file mode 100644
index 000000000000..d405338c9a24
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isaa.s
@@ -0,0 +1,6 @@
+foo:	nop
+	jbra foo
+	jbra bar
+	jbsr foo
+	jbsr bar
+	nop
diff --git a/gas/testsuite/gas/m68k/br-isab.d b/gas/testsuite/gas/m68k/br-isab.d
new file mode 100644
index 000000000000..20e093f734d3
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isab.d
@@ -0,0 +1,16 @@
+#name: br-isab.d
+#objdump: -d
+#as: -march=isab -pcrel
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+   0:	4e71           	nop
+   2:	61ff ffff fffc 	bsrl 0 <foo>
+   8:	60f6           	bras 0 <foo>
+   a:	60ff 0000 0000 	bral c <foo\+0xc>
+  10:	61ee           	bsrs 0 <foo>
+  12:	61ff 0000 0000 	bsrl 14 <foo\+0x14>
+  18:	4e71           	nop
diff --git a/gas/testsuite/gas/m68k/br-isab.s b/gas/testsuite/gas/m68k/br-isab.s
new file mode 100644
index 000000000000..5db3c076ee5f
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isab.s
@@ -0,0 +1,7 @@
+foo:	nop
+	bsr.l foo
+	jbra foo
+	jbra bar
+	jbsr foo
+	jbsr bar
+	nop
diff --git a/gas/testsuite/gas/m68k/br-isac.d b/gas/testsuite/gas/m68k/br-isac.d
new file mode 100644
index 000000000000..126ff464bb8b
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isac.d
@@ -0,0 +1,16 @@
+#name: br-isac.d
+#objdump: -d
+#as: -march=isac -pcrel
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+   0:	4e71           	nop
+   2:	61ff ffff fffc 	bsrl 0 <foo>
+   8:	60f6           	bras 0 <foo>
+   a:	6000 0000      	braw c <foo\+0xc>
+   e:	61f0           	bsrs 0 <foo>
+  10:	61ff 0000 0000 	bsrl 12 <foo\+0x12>
+  16:	4e71           	nop
diff --git a/gas/testsuite/gas/m68k/br-isac.s b/gas/testsuite/gas/m68k/br-isac.s
new file mode 100644
index 000000000000..5db3c076ee5f
--- /dev/null
+++ b/gas/testsuite/gas/m68k/br-isac.s
@@ -0,0 +1,7 @@
+foo:	nop
+	bsr.l foo
+	jbra foo
+	jbra bar
+	jbsr foo
+	jbsr bar
+	nop
diff --git a/gas/testsuite/gas/m68k/cpu32.d b/gas/testsuite/gas/m68k/cpu32.d
new file mode 100644
index 000000000000..e7054a394733
--- /dev/null
+++ b/gas/testsuite/gas/m68k/cpu32.d
@@ -0,0 +1,35 @@
+#name: cpu32
+#objdump: -d
+#as: -mcpu32
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 0-9a-f]+:	4afa           	bgnd
+[ 0-9a-f]+:	f800 2001      	tblub %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2041      	tbluw %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2081      	tblul %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2401      	tblunb %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2441      	tblunw %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2481      	tblunl %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2801      	tblsb %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2841      	tblsw %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2881      	tblsl %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2c01      	tblsnb %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2c41      	tblsnw %d0,%d1,%d2
+[ 0-9a-f]+:	f800 2c81      	tblsnl %d0,%d1,%d2
+[ 0-9a-f]+:	f810 1100      	tblub %a0@,%d1
+[ 0-9a-f]+:	f810 1140      	tbluw %a0@,%d1
+[ 0-9a-f]+:	f810 1180      	tblul %a0@,%d1
+[ 0-9a-f]+:	f810 1500      	tblunb %a0@,%d1
+[ 0-9a-f]+:	f810 1540      	tblunw %a0@,%d1
+[ 0-9a-f]+:	f810 1580      	tblunl %a0@,%d1
+[ 0-9a-f]+:	f810 1900      	tblsb %a0@,%d1
+[ 0-9a-f]+:	f810 1940      	tblsw %a0@,%d1
+[ 0-9a-f]+:	f810 1980      	tblsl %a0@,%d1
+[ 0-9a-f]+:	f810 1d00      	tblsnb %a0@,%d1
+[ 0-9a-f]+:	f810 1d40      	tblsnw %a0@,%d1
+[ 0-9a-f]+:	f810 1d80      	tblsnl %a0@,%d1
+#...
diff --git a/gas/testsuite/gas/m68k/cpu32.s b/gas/testsuite/gas/m68k/cpu32.s
new file mode 100644
index 000000000000..589e7e305672
--- /dev/null
+++ b/gas/testsuite/gas/m68k/cpu32.s
@@ -0,0 +1,26 @@
+	# cpu32 specific insns
+	bgnd
+	tblub	%d0,%d1,%d2
+	tbluw	%d0,%d1,%d2
+	tblul	%d0,%d1,%d2
+	tblunb	%d0,%d1,%d2
+	tblunw	%d0,%d1,%d2
+	tblunl	%d0,%d1,%d2
+	tblsb	%d0,%d1,%d2
+	tblsw	%d0,%d1,%d2
+	tblsl	%d0,%d1,%d2
+	tblsnb	%d0,%d1,%d2
+	tblsnw	%d0,%d1,%d2
+	tblsnl	%d0,%d1,%d2
+	tblub	(%a0),%d1
+	tbluw	(%a0),%d1
+	tblul	(%a0),%d1
+	tblunb	(%a0),%d1
+	tblunw	(%a0),%d1
+	tblunl	(%a0),%d1
+	tblsb	(%a0),%d1
+	tblsw	(%a0),%d1
+	tblsl	(%a0),%d1
+	tblsnb	(%a0),%d1
+	tblsnw	(%a0),%d1
+	tblsnl	(%a0),%d1
diff --git a/gas/testsuite/gas/m68k/ctrl-1.d b/gas/testsuite/gas/m68k/ctrl-1.d
new file mode 100644
index 000000000000..d4347281b4bf
--- /dev/null
+++ b/gas/testsuite/gas/m68k/ctrl-1.d
@@ -0,0 +1,12 @@
+#name: ctrl-1.d
+#objdump: -d
+#as: -mcpu=5307
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	4e7b 0c04      	movec %d0,%rambar0
+   4:	4e7b 0c04      	movec %d0,%rambar0
+
diff --git a/gas/testsuite/gas/m68k/ctrl-1.s b/gas/testsuite/gas/m68k/ctrl-1.s
new file mode 100644
index 000000000000..cac82d93cb42
--- /dev/null
+++ b/gas/testsuite/gas/m68k/ctrl-1.s
@@ -0,0 +1,2 @@
+	movec	%d0,%rambar
+	movec	%d0,%rambar0
diff --git a/gas/testsuite/gas/m68k/ctrl-2.d b/gas/testsuite/gas/m68k/ctrl-2.d
new file mode 100644
index 000000000000..00b8aa3b7f8e
--- /dev/null
+++ b/gas/testsuite/gas/m68k/ctrl-2.d
@@ -0,0 +1,11 @@
+#name: ctrl-2.d
+#objdump: -d
+#as: -mcpu=5208
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	4e7b 0c05      	movec %d0,%rambar1
+   4:	4e7b 0c05      	movec %d0,%rambar1
diff --git a/gas/testsuite/gas/m68k/ctrl-2.s b/gas/testsuite/gas/m68k/ctrl-2.s
new file mode 100644
index 000000000000..3a36db0bb89c
--- /dev/null
+++ b/gas/testsuite/gas/m68k/ctrl-2.s
@@ -0,0 +1,2 @@
+	movec	%d0,%rambar
+	movec	%d0,%rambar1
diff --git a/gas/testsuite/gas/m68k/fido.d b/gas/testsuite/gas/m68k/fido.d
new file mode 100644
index 000000000000..fff5abbef38a
--- /dev/null
+++ b/gas/testsuite/gas/m68k/fido.d
@@ -0,0 +1,41 @@
+#objdump: -d --prefix-addresses
+#name: fido
+
+# Test parsing of the operands of the fido-specific instructions.
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo> sleep
+0+002 <foo\+(0x|)2> trapx #0
+0+004 <foo\+(0x|)4> trapx #1
+0+006 <foo\+(0x|)6> trapx #2
+0+008 <foo\+(0x|)8> trapx #3
+0+00a <foo\+(0x|)a> trapx #4
+0+00c <foo\+(0x|)c> trapx #5
+0+00e <foo\+(0x|)e> trapx #6
+0+010 <foo\+(0x|)10> trapx #7
+0+012 <foo\+(0x|)12> trapx #8
+0+014 <foo\+(0x|)14> trapx #9
+0+016 <foo\+(0x|)16> trapx #10
+0+018 <foo\+(0x|)18> trapx #11
+0+01a <foo\+(0x|)1a> trapx #12
+0+01c <foo\+(0x|)1c> trapx #13
+0+01e <foo\+(0x|)1e> trapx #14
+0+020 <foo\+(0x|)20> trapx #15
+0+022 <foo\+(0x|)22> movec %cac,%d0
+0+026 <foo\+(0x|)26> movec %cac,%a0
+0+02a <foo\+(0x|)2a> movec %mbb,%d1
+0+02e <foo\+(0x|)2e> movec %mbb,%a1
+0+032 <foo\+(0x|)32> movec %d2,%cac
+0+036 <foo\+(0x|)36> movec %a2,%cac
+0+03a <foo\+(0x|)3a> movec %d3,%mbb
+0+03e <foo\+(0x|)3e> movec %a3,%mbb
+0+042 <foo\+(0x|)42> movec %cac,%d4
+0+046 <foo\+(0x|)46> movec %cac,%a4
+0+04a <foo\+(0x|)4a> movec %mbb,%d5
+0+04e <foo\+(0x|)4e> movec %mbb,%a5
+0+052 <foo\+(0x|)52> movec %d6,%cac
+0+056 <foo\+(0x|)56> movec %fp,%cac
+0+05a <foo\+(0x|)5a> movec %d7,%mbb
+0+05e <foo\+(0x|)5e> movec %sp,%mbb
diff --git a/gas/testsuite/gas/m68k/fido.s b/gas/testsuite/gas/m68k/fido.s
new file mode 100644
index 000000000000..8aaac7c54736
--- /dev/null
+++ b/gas/testsuite/gas/m68k/fido.s
@@ -0,0 +1,37 @@
+# Test parsing of the operands of the fido-specific instructions.
+	.text
+	.globl	foo
+foo:	
+	sleep
+	trapx #0
+	trapx #1
+	trapx #2
+	trapx #3
+	trapx #4
+	trapx #5
+	trapx #6
+	trapx #7
+	trapx #8
+	trapx #9
+	trapx #10
+	trapx #11
+	trapx #12
+	trapx #13
+	trapx #14
+	trapx #15
+	movec #0xffe,%d0
+	movec #0xffe,%a0
+	movec #0xfff,%d1
+	movec #0xfff,%a1
+	movec %d2,#0xffe
+	movec %a2,#0xffe
+	movec %d3,#0xfff
+	movec %a3,#0xfff
+	movec %cac,%d4
+	movec %cac,%a4
+	movec %mbb,%d5
+	movec %mbb,%a5
+	movec %d6,%cac
+	movec %a6,%cac
+	movec %d7,%mbb
+	movec %a7,%mbb
diff --git a/gas/testsuite/gas/m68k/mcf-coproc.d b/gas/testsuite/gas/m68k/mcf-coproc.d
new file mode 100644
index 000000000000..86401cbbcbda
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-coproc.d
@@ -0,0 +1,50 @@
+#objdump: -d
+#as: -mcpu=5475
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <start>:
+[ 0-9a-f]+:	fcc0 0050      	cp0bcbusy [0-9a-f]+ <zero>
+[ 0-9a-f]+:	fc80 2123      	cp0ldl %d0,%d2,#1,#291
+[ 0-9a-f]+:	fc88 a201      	cp0ldl %a0,%a2,#2,#1
+[ 0-9a-f]+:	fc50 a401      	cp0ldw %a0@,%a2,#3,#1
+[ 0-9a-f]+:	fc18 aa01      	cp0ldb %a0@\+,%a2,#6,#1
+[ 0-9a-f]+:	fca0 ac01      	cp0ldl %a0@-,%a2,#7,#1
+[ 0-9a-f]+:	fca8 ae01 0010 	cp0ldl %a0@\(16\),%a2,#8,#1
+[ 0-9a-f]+:	fd80 2123      	cp0stl %d2,%d0,#1,#291
+[ 0-9a-f]+:	fd88 a201      	cp0stl %a2,%a0,#2,#1
+[ 0-9a-f]+:	fd50 a401      	cp0stw %a2,%a0@,#3,#1
+[ 0-9a-f]+:	fd18 aa01      	cp0stb %a2,%a0@\+,#6,#1
+[ 0-9a-f]+:	fda0 ac01      	cp0stl %a2,%a0@-,#7,#1
+[ 0-9a-f]+:	fda8 ae01 0010 	cp0stl %a2,%a0@\(16\),#8,#1
+[ 0-9a-f]+:	fc00 0e00      	cp0nop #8
+[ 0-9a-f]+:	fc80 0400      	cp0nop #3
+[ 0-9a-f]+:	fc80 1400      	cp0ldl %d0,%d1,#3,#0
+[ 0-9a-f]+:	fc88 0400      	cp0ldl %a0,%d0,#3,#0
+[ 0-9a-f]+:	fc90 0400      	cp0ldl %a0@,%d0,#3,#0
+[ 0-9a-f]+:	fca8 0400 0010 	cp0ldl %a0@\(16\),%d0,#3,#0
+[ 0-9a-f]+ <zero>:
+[ 0-9a-f]+:	4e71           	nop
+[ 0-9a-f]+:	fec0 0050      	cp1bcbusy [0-9a-f]+ <one>
+[ 0-9a-f]+:	fe80 2123      	cp1ldl %d0,%d2,#1,#291
+[ 0-9a-f]+:	fe88 a201      	cp1ldl %a0,%a2,#2,#1
+[ 0-9a-f]+:	fe50 a401      	cp1ldw %a0@,%a2,#3,#1
+[ 0-9a-f]+:	fe18 aa01      	cp1ldb %a0@\+,%a2,#6,#1
+[ 0-9a-f]+:	fea0 ac01      	cp1ldl %a0@-,%a2,#7,#1
+[ 0-9a-f]+:	fea8 ae01 0010 	cp1ldl %a0@\(16\),%a2,#8,#1
+[ 0-9a-f]+:	ff80 2123      	cp1stl %d2,%d0,#1,#291
+[ 0-9a-f]+:	ff88 a201      	cp1stl %a2,%a0,#2,#1
+[ 0-9a-f]+:	ff50 a401      	cp1stw %a2,%a0@,#3,#1
+[ 0-9a-f]+:	ff18 aa01      	cp1stb %a2,%a0@\+,#6,#1
+[ 0-9a-f]+:	ffa0 ac01      	cp1stl %a2,%a0@-,#7,#1
+[ 0-9a-f]+:	ffa8 ae01 0010 	cp1stl %a2,%a0@\(16\),#8,#1
+[ 0-9a-f]+:	fe00 0e00      	cp1nop #8
+[ 0-9a-f]+:	fe80 0400      	cp1nop #3
+[ 0-9a-f]+:	fe80 1400      	cp1ldl %d0,%d1,#3,#0
+[ 0-9a-f]+:	fe88 0400      	cp1ldl %a0,%d0,#3,#0
+[ 0-9a-f]+:	fe90 0400      	cp1ldl %a0@,%d0,#3,#0
+[ 0-9a-f]+:	fea8 0400 0010 	cp1ldl %a0@\(16\),%d0,#3,#0
+[ 0-9a-f]+ <one>:
+[ 0-9a-f]+:	4e71           	nop
diff --git a/gas/testsuite/gas/m68k/mcf-coproc.s b/gas/testsuite/gas/m68k/mcf-coproc.s
new file mode 100644
index 000000000000..6173d6ac847f
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-coproc.s
@@ -0,0 +1,47 @@
+
+start:
+	cp0bcbusy  zero
+	cp0ld %d0,%d2,#1,#0x123
+	cp0ldl %a0,%a2,#2,#0x1
+	cp0ldw (%a0),%a2,#3,#0x1
+	cp0ldb (%a0)+,%a2,#6,#0x1
+	cp0ldl -(%a0),%a2,#7,#0x1
+	cp0ldl 16(%a0),%a2,#8,#0x1
+	
+	cp0st %d2,%d0,#1,#0x123
+	cp0stl %a2,%a0,#2,#0x1
+	cp0stw %a2,(%a0),#3,#0x1
+	cp0stb %a2,(%a0)+,#6,#0x1
+	cp0stl %a2,-(%a0),#7,#0x1
+	cp0stl %a2,16(%a0),#8,#0x1
+	
+	cp0nop #8
+	cp0ld %d0,%d0,#3,#0
+	cp0ld %d0,%d1,#3,#0
+	cp0ld %a0,%d0,#3,#0
+	cp0ld (%a0),%d0,#3,#0
+	cp0ld 16(%a0),%d0,#3,#0
+zero:	nop
+	
+	cp1bcbusy  one
+	cp1ld %d0,%d2,#1,#0x123
+	cp1ldl %a0,%a2,#2,#0x1
+	cp1ldw (%a0),%a2,#3,#0x1
+	cp1ldb (%a0)+,%a2,#6,#0x1
+	cp1ldl -(%a0),%a2,#7,#0x1
+	cp1ldl 16(%a0),%a2,#8,#0x1
+	
+	cp1st %d2,%d0,#1,#0x123
+	cp1stl %a2,%a0,#2,#0x1
+	cp1stw %a2,(%a0),#3,#0x1
+	cp1stb %a2,(%a0)+,#6,#0x1
+	cp1stl %a2,-(%a0),#7,#0x1
+	cp1stl %a2,16(%a0),#8,#0x1
+	
+	cp1nop #8
+	cp1ld %d0,%d0,#3,#0
+	cp1ld %d0,%d1,#3,#0
+	cp1ld %a0,%d0,#3,#0
+	cp1ld (%a0),%d0,#3,#0
+	cp1ld 16(%a0),%d0,#3,#0
+one:	nop
diff --git a/gas/testsuite/gas/m68k/mcf-fpu.d b/gas/testsuite/gas/m68k/mcf-fpu.d
index 5167b08dff0d..f285fd235166 100644
--- a/gas/testsuite/gas/m68k/mcf-fpu.d
+++ b/gas/testsuite/gas/m68k/mcf-fpu.d
@@ -7,167 +7,815 @@ Disassembly of section .text:
 
 0+ <.text>:
 [ 0-9a-f]+:	f200 0004      	fsqrtd %fp0,%fp0
+[ 0-9a-f]+:	f205 4004      	fsqrtl %d5,%fp0
+[ 0-9a-f]+:	f214 4004      	fsqrtl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4004      	fsqrtl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4004      	fsqrtl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4004 0008 	fsqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4004 1234 	fsqrtl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4404      	fsqrts %d5,%fp0
+[ 0-9a-f]+:	f214 4404      	fsqrts %a4@,%fp0
+[ 0-9a-f]+:	f21b 4404      	fsqrts %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4404      	fsqrts %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4404 0008 	fsqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4404 1234 	fsqrts %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5004      	fsqrtw %d5,%fp0
+[ 0-9a-f]+:	f214 5004      	fsqrtw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5004      	fsqrtw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5004      	fsqrtw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5004 0008 	fsqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5004 1234 	fsqrtw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5404      	fsqrtd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5404      	fsqrtd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5404      	fsqrtd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5404 0008 	fsqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5404 1234 	fsqrtd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5804      	fsqrtb %d5,%fp0
+[ 0-9a-f]+:	f214 5804      	fsqrtb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5804      	fsqrtb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5804      	fsqrtb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5804 0008 	fsqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5804 1234 	fsqrtb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0041      	fssqrtd %fp0,%fp0
+[ 0-9a-f]+:	f205 4041      	fssqrtl %d5,%fp0
+[ 0-9a-f]+:	f214 4041      	fssqrtl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4041      	fssqrtl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4041      	fssqrtl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4041 0008 	fssqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4041 1234 	fssqrtl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4441      	fssqrts %d5,%fp0
+[ 0-9a-f]+:	f214 4441      	fssqrts %a4@,%fp0
+[ 0-9a-f]+:	f21b 4441      	fssqrts %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4441      	fssqrts %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4441 0008 	fssqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4441 1234 	fssqrts %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5041      	fssqrtw %d5,%fp0
+[ 0-9a-f]+:	f214 5041      	fssqrtw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5041      	fssqrtw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5041      	fssqrtw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5041 0008 	fssqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5041 1234 	fssqrtw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5441      	fssqrtd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5441      	fssqrtd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5441      	fssqrtd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5441 0008 	fssqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5441 1234 	fssqrtd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5841      	fssqrtb %d5,%fp0
+[ 0-9a-f]+:	f214 5841      	fssqrtb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5841      	fssqrtb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5841      	fssqrtb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5841 0008 	fssqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5841 1234 	fssqrtb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0045      	fdsqrtd %fp0,%fp0
+[ 0-9a-f]+:	f205 4045      	fdsqrtl %d5,%fp0
+[ 0-9a-f]+:	f214 4045      	fdsqrtl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4045      	fdsqrtl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4045      	fdsqrtl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4045 0008 	fdsqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4045 1234 	fdsqrtl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4445      	fdsqrts %d5,%fp0
+[ 0-9a-f]+:	f214 4445      	fdsqrts %a4@,%fp0
+[ 0-9a-f]+:	f21b 4445      	fdsqrts %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4445      	fdsqrts %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4445 0008 	fdsqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4445 1234 	fdsqrts %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5045      	fdsqrtw %d5,%fp0
+[ 0-9a-f]+:	f214 5045      	fdsqrtw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5045      	fdsqrtw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5045      	fdsqrtw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5045 0008 	fdsqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5045 1234 	fdsqrtw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5445      	fdsqrtd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5445      	fdsqrtd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5445      	fdsqrtd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5445 0008 	fdsqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5445 1234 	fdsqrtd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5845      	fdsqrtb %d5,%fp0
+[ 0-9a-f]+:	f214 5845      	fdsqrtb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5845      	fdsqrtb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5845      	fdsqrtb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5845 0008 	fdsqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5845 1234 	fdsqrtb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0018      	fabsd %fp0,%fp0
+[ 0-9a-f]+:	f205 4018      	fabsl %d5,%fp0
+[ 0-9a-f]+:	f214 4018      	fabsl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4018      	fabsl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4018      	fabsl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4018 0008 	fabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4018 1234 	fabsl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4418      	fabss %d5,%fp0
+[ 0-9a-f]+:	f214 4418      	fabss %a4@,%fp0
+[ 0-9a-f]+:	f21b 4418      	fabss %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4418      	fabss %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4418 0008 	fabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4418 1234 	fabss %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5018      	fabsw %d5,%fp0
+[ 0-9a-f]+:	f214 5018      	fabsw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5018      	fabsw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5018      	fabsw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5018 0008 	fabsw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5018 1234 	fabsw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5418      	fabsd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5418      	fabsd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5418      	fabsd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5418 0008 	fabsd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5418 1234 	fabsd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5818      	fabsb %d5,%fp0
+[ 0-9a-f]+:	f214 5818      	fabsb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5818      	fabsb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5818      	fabsb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5818 0008 	fabsb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5818 1234 	fabsb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0058      	fsabsd %fp0,%fp0
+[ 0-9a-f]+:	f205 4058      	fsabsl %d5,%fp0
+[ 0-9a-f]+:	f214 4058      	fsabsl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4058      	fsabsl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4058      	fsabsl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4058 0008 	fsabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4058 1234 	fsabsl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4458      	fsabss %d5,%fp0
+[ 0-9a-f]+:	f214 4458      	fsabss %a4@,%fp0
+[ 0-9a-f]+:	f21b 4458      	fsabss %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4458      	fsabss %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4458 0008 	fsabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4458 1234 	fsabss %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5058      	fsabsw %d5,%fp0
+[ 0-9a-f]+:	f214 5058      	fsabsw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5058      	fsabsw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5058      	fsabsw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5058 0008 	fsabsw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5058 1234 	fsabsw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5458      	fsabsd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5458      	fsabsd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5458      	fsabsd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5458 0008 	fsabsd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5458 1234 	fsabsd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5858      	fsabsb %d5,%fp0
+[ 0-9a-f]+:	f214 5858      	fsabsb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5858      	fsabsb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5858      	fsabsb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5858 0008 	fsabsb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5858 1234 	fsabsb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 005c      	fdabsd %fp0,%fp0
+[ 0-9a-f]+:	f205 405c      	fdabsl %d5,%fp0
+[ 0-9a-f]+:	f214 405c      	fdabsl %a4@,%fp0
+[ 0-9a-f]+:	f21b 405c      	fdabsl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 405c      	fdabsl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 405c 0008 	fdabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 405c 1234 	fdabsl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 445c      	fdabss %d5,%fp0
+[ 0-9a-f]+:	f214 445c      	fdabss %a4@,%fp0
+[ 0-9a-f]+:	f21b 445c      	fdabss %a3@\+,%fp0
+[ 0-9a-f]+:	f222 445c      	fdabss %a2@-,%fp0
 [ 0-9a-f]+:	f22e 445c 0008 	fdabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 445c 1234 	fdabss %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 505c      	fdabsw %d5,%fp0
+[ 0-9a-f]+:	f214 505c      	fdabsw %a4@,%fp0
+[ 0-9a-f]+:	f21b 505c      	fdabsw %a3@\+,%fp0
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+[ 0-9a-f]+:	f205 5840      	fsmoveb %d5,%fp0
+[ 0-9a-f]+:	f214 5840      	fsmoveb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5840      	fsmoveb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5840      	fsmoveb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5840 0008 	fsmoveb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5840 1234 	fsmoveb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0044      	fdmoved %fp0,%fp0
+[ 0-9a-f]+:	f205 4044      	fdmovel %d5,%fp0
+[ 0-9a-f]+:	f214 4044      	fdmovel %a4@,%fp0
+[ 0-9a-f]+:	f21b 4044      	fdmovel %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4044      	fdmovel %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4044 0008 	fdmovel %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4044 1234 	fdmovel %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4444      	fdmoves %d5,%fp0
+[ 0-9a-f]+:	f214 4444      	fdmoves %a4@,%fp0
+[ 0-9a-f]+:	f21b 4444      	fdmoves %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4444      	fdmoves %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4444 0008 	fdmoves %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4444 1234 	fdmoves %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5044      	fdmovew %d5,%fp0
+[ 0-9a-f]+:	f214 5044      	fdmovew %a4@,%fp0
+[ 0-9a-f]+:	f21b 5044      	fdmovew %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5044      	fdmovew %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5044 0008 	fdmovew %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5044 1234 	fdmovew %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5444      	fdmoved %a4@,%fp0
+[ 0-9a-f]+:	f21b 5444      	fdmoved %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5444      	fdmoved %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5444 0008 	fdmoved %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5444 1234 	fdmoved %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5844      	fdmoveb %d5,%fp0
+[ 0-9a-f]+:	f214 5844      	fdmoveb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5844      	fdmoveb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5844      	fdmoveb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5844 0008 	fdmoveb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5844 1234 	fdmoveb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0001      	fintd %fp0,%fp0
+[ 0-9a-f]+:	f205 4001      	fintl %d5,%fp0
+[ 0-9a-f]+:	f214 4001      	fintl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4001      	fintl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4001      	fintl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4001 0008 	fintl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4001 1234 	fintl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4401      	fints %d5,%fp0
+[ 0-9a-f]+:	f214 4401      	fints %a4@,%fp0
+[ 0-9a-f]+:	f21b 4401      	fints %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4401      	fints %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4401 0008 	fints %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4401 1234 	fints %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5001      	fintw %d5,%fp0
+[ 0-9a-f]+:	f214 5001      	fintw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5001      	fintw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5001      	fintw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5001 0008 	fintw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5001 1234 	fintw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5401      	fintd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5401      	fintd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5401      	fintd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5401 0008 	fintd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5401 1234 	fintd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5801      	fintb %d5,%fp0
+[ 0-9a-f]+:	f214 5801      	fintb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5801      	fintb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5801      	fintb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5801 0008 	fintb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5801 1234 	fintb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0003      	fintrzd %fp0,%fp0
+[ 0-9a-f]+:	f205 4003      	fintrzl %d5,%fp0
+[ 0-9a-f]+:	f214 4003      	fintrzl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4003      	fintrzl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4003      	fintrzl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4003 0008 	fintrzl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4003 1234 	fintrzl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4403      	fintrzs %d5,%fp0
+[ 0-9a-f]+:	f214 4403      	fintrzs %a4@,%fp0
+[ 0-9a-f]+:	f21b 4403      	fintrzs %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4403      	fintrzs %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4403 0008 	fintrzs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4403 1234 	fintrzs %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5003      	fintrzw %d5,%fp0
+[ 0-9a-f]+:	f214 5003      	fintrzw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5003      	fintrzw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5003      	fintrzw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5003 0008 	fintrzw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5003 1234 	fintrzw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5403      	fintrzd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5403      	fintrzd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5403      	fintrzd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5403 0008 	fintrzd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5403 1234 	fintrzd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5803      	fintrzb %d5,%fp0
+[ 0-9a-f]+:	f214 5803      	fintrzb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5803      	fintrzb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5803      	fintrzb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5803 0008 	fintrzb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5803 1234 	fintrzb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f200 0038      	fcmpd %fp0,%fp0
+[ 0-9a-f]+:	f205 4038      	fcmpl %d5,%fp0
+[ 0-9a-f]+:	f214 4038      	fcmpl %a4@,%fp0
+[ 0-9a-f]+:	f21b 4038      	fcmpl %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4038      	fcmpl %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4038 0008 	fcmpl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4038 1234 	fcmpl %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 4438      	fcmps %d5,%fp0
+[ 0-9a-f]+:	f214 4438      	fcmps %a4@,%fp0
+[ 0-9a-f]+:	f21b 4438      	fcmps %a3@\+,%fp0
+[ 0-9a-f]+:	f222 4438      	fcmps %a2@-,%fp0
 [ 0-9a-f]+:	f22e 4438 0008 	fcmps %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 4438 1234 	fcmps %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5038      	fcmpw %d5,%fp0
+[ 0-9a-f]+:	f214 5038      	fcmpw %a4@,%fp0
+[ 0-9a-f]+:	f21b 5038      	fcmpw %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5038      	fcmpw %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5038 0008 	fcmpw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5038 1234 	fcmpw %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f214 5438      	fcmpd %a4@,%fp0
+[ 0-9a-f]+:	f21b 5438      	fcmpd %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5438      	fcmpd %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5438 0008 	fcmpd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5438 1234 	fcmpd %pc@\(.*\),%fp0
+[ 0-9a-f]+:	f205 5838      	fcmpb %d5,%fp0
+[ 0-9a-f]+:	f214 5838      	fcmpb %a4@,%fp0
+[ 0-9a-f]+:	f21b 5838      	fcmpb %a3@\+,%fp0
+[ 0-9a-f]+:	f222 5838      	fcmpb %a2@-,%fp0
 [ 0-9a-f]+:	f22e 5838 0008 	fcmpb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f23a 5838 1234 	fcmpb %pc@\(.*\),%fp0
 [ 0-9a-f]+:	f22e f0f2 0008 	fmovemd %fp0-%fp3/%fp6,%fp@\(8\)
 [ 0-9a-f]+:	f22e d02c 0008 	fmovemd %fp@\(8\),%fp2/%fp4-%fp5
 [ 0-9a-f]+:	f22e f027 0008 	fmovemd %fp2/%fp5-%fp7,%fp@\(8\)
diff --git a/gas/testsuite/gas/m68k/mcf-fpu.s b/gas/testsuite/gas/m68k/mcf-fpu.s
index 99231a74e31f..fd2a15621c52 100644
--- a/gas/testsuite/gas/m68k/mcf-fpu.s
+++ b/gas/testsuite/gas/m68k/mcf-fpu.s
@@ -2,167 +2,815 @@
 	.text
 
 	fsqrtd	%fp0,%fp0
+	fsqrtl	%d5,%fp0
+	fsqrtl	%a4@,%fp0
+	fsqrtl	%a3@+,%fp0
+	fsqrtl	%a2@-,%fp0
 	fsqrtl	%fp@(8),%fp0
+	fsqrtl	%pc@(.+0x1238),%fp0
+	fsqrts	%d5,%fp0
+	fsqrts	%a4@,%fp0
+	fsqrts	%a3@+,%fp0
+	fsqrts	%a2@-,%fp0
 	fsqrts	%fp@(8),%fp0
+	fsqrts	%pc@(.+0x1238),%fp0
+	fsqrtw	%d5,%fp0
+	fsqrtw	%a4@,%fp0
+	fsqrtw	%a3@+,%fp0
+	fsqrtw	%a2@-,%fp0
 	fsqrtw	%fp@(8),%fp0
+	fsqrtw	%pc@(.+0x1238),%fp0
+	fsqrtd	%a4@,%fp0
+	fsqrtd	%a3@+,%fp0
+	fsqrtd	%a2@-,%fp0
 	fsqrtd	%fp@(8),%fp0
+	fsqrtd	%pc@(.+0x1238),%fp0
+	fsqrtb	%d5,%fp0
+	fsqrtb	%a4@,%fp0
+	fsqrtb	%a3@+,%fp0
+	fsqrtb	%a2@-,%fp0
 	fsqrtb	%fp@(8),%fp0
+	fsqrtb	%pc@(.+0x1238),%fp0
 	fssqrtd	%fp0,%fp0
+	fssqrtl	%d5,%fp0
+	fssqrtl	%a4@,%fp0
+	fssqrtl	%a3@+,%fp0
+	fssqrtl	%a2@-,%fp0
 	fssqrtl	%fp@(8),%fp0
+	fssqrtl	%pc@(.+0x1238),%fp0
+	fssqrts	%d5,%fp0
+	fssqrts	%a4@,%fp0
+	fssqrts	%a3@+,%fp0
+	fssqrts	%a2@-,%fp0
 	fssqrts	%fp@(8),%fp0
+	fssqrts	%pc@(.+0x1238),%fp0
+	fssqrtw	%d5,%fp0
+	fssqrtw	%a4@,%fp0
+	fssqrtw	%a3@+,%fp0
+	fssqrtw	%a2@-,%fp0
 	fssqrtw	%fp@(8),%fp0
+	fssqrtw	%pc@(.+0x1238),%fp0
+	fssqrtd	%a4@,%fp0
+	fssqrtd	%a3@+,%fp0
+	fssqrtd	%a2@-,%fp0
 	fssqrtd	%fp@(8),%fp0
+	fssqrtd	%pc@(.+0x1238),%fp0
+	fssqrtb	%d5,%fp0
+	fssqrtb	%a4@,%fp0
+	fssqrtb	%a3@+,%fp0
+	fssqrtb	%a2@-,%fp0
 	fssqrtb	%fp@(8),%fp0
+	fssqrtb	%pc@(.+0x1238),%fp0
 	fdsqrtd	%fp0,%fp0
+	fdsqrtl	%d5,%fp0
+	fdsqrtl	%a4@,%fp0
+	fdsqrtl	%a3@+,%fp0
+	fdsqrtl	%a2@-,%fp0
 	fdsqrtl	%fp@(8),%fp0
+	fdsqrtl	%pc@(.+0x1238),%fp0
+	fdsqrts	%d5,%fp0
+	fdsqrts	%a4@,%fp0
+	fdsqrts	%a3@+,%fp0
+	fdsqrts	%a2@-,%fp0
 	fdsqrts	%fp@(8),%fp0
+	fdsqrts	%pc@(.+0x1238),%fp0
+	fdsqrtw	%d5,%fp0
+	fdsqrtw	%a4@,%fp0
+	fdsqrtw	%a3@+,%fp0
+	fdsqrtw	%a2@-,%fp0
 	fdsqrtw	%fp@(8),%fp0
+	fdsqrtw	%pc@(.+0x1238),%fp0
+	fdsqrtd	%a4@,%fp0
+	fdsqrtd	%a3@+,%fp0
+	fdsqrtd	%a2@-,%fp0
 	fdsqrtd	%fp@(8),%fp0
+	fdsqrtd	%pc@(.+0x1238),%fp0
+	fdsqrtb	%d5,%fp0
+	fdsqrtb	%a4@,%fp0
+	fdsqrtb	%a3@+,%fp0
+	fdsqrtb	%a2@-,%fp0
 	fdsqrtb	%fp@(8),%fp0
+	fdsqrtb	%pc@(.+0x1238),%fp0
 	fabsd	%fp0,%fp0
+	fabsl	%d5,%fp0
+	fabsl	%a4@,%fp0
+	fabsl	%a3@+,%fp0
+	fabsl	%a2@-,%fp0
 	fabsl	%fp@(8),%fp0
+	fabsl	%pc@(.+0x1238),%fp0
+	fabss	%d5,%fp0
+	fabss	%a4@,%fp0
+	fabss	%a3@+,%fp0
+	fabss	%a2@-,%fp0
 	fabss	%fp@(8),%fp0
+	fabss	%pc@(.+0x1238),%fp0
+	fabsw	%d5,%fp0
+	fabsw	%a4@,%fp0
+	fabsw	%a3@+,%fp0
+	fabsw	%a2@-,%fp0
 	fabsw	%fp@(8),%fp0
+	fabsw	%pc@(.+0x1238),%fp0
+	fabsd	%a4@,%fp0
+	fabsd	%a3@+,%fp0
+	fabsd	%a2@-,%fp0
 	fabsd	%fp@(8),%fp0
+	fabsd	%pc@(.+0x1238),%fp0
+	fabsb	%d5,%fp0
+	fabsb	%a4@,%fp0
+	fabsb	%a3@+,%fp0
+	fabsb	%a2@-,%fp0
 	fabsb	%fp@(8),%fp0
+	fabsb	%pc@(.+0x1238),%fp0
 	fsabsd	%fp0,%fp0
+	fsabsl	%d5,%fp0
+	fsabsl	%a4@,%fp0
+	fsabsl	%a3@+,%fp0
+	fsabsl	%a2@-,%fp0
 	fsabsl	%fp@(8),%fp0
+	fsabsl	%pc@(.+0x1238),%fp0
+	fsabss	%d5,%fp0
+	fsabss	%a4@,%fp0
+	fsabss	%a3@+,%fp0
+	fsabss	%a2@-,%fp0
 	fsabss	%fp@(8),%fp0
+	fsabss	%pc@(.+0x1238),%fp0
+	fsabsw	%d5,%fp0
+	fsabsw	%a4@,%fp0
+	fsabsw	%a3@+,%fp0
+	fsabsw	%a2@-,%fp0
 	fsabsw	%fp@(8),%fp0
+	fsabsw	%pc@(.+0x1238),%fp0
+	fsabsd	%a4@,%fp0
+	fsabsd	%a3@+,%fp0
+	fsabsd	%a2@-,%fp0
 	fsabsd	%fp@(8),%fp0
+	fsabsd	%pc@(.+0x1238),%fp0
+	fsabsb	%d5,%fp0
+	fsabsb	%a4@,%fp0
+	fsabsb	%a3@+,%fp0
+	fsabsb	%a2@-,%fp0
 	fsabsb	%fp@(8),%fp0
+	fsabsb	%pc@(.+0x1238),%fp0
 	fdabsd	%fp0,%fp0
+	fdabsl	%d5,%fp0
+	fdabsl	%a4@,%fp0
+	fdabsl	%a3@+,%fp0
+	fdabsl	%a2@-,%fp0
 	fdabsl	%fp@(8),%fp0
+	fdabsl	%pc@(.+0x1238),%fp0
+	fdabss	%d5,%fp0
+	fdabss	%a4@,%fp0
+	fdabss	%a3@+,%fp0
+	fdabss	%a2@-,%fp0
 	fdabss	%fp@(8),%fp0
+	fdabss	%pc@(.+0x1238),%fp0
+	fdabsw	%d5,%fp0
+	fdabsw	%a4@,%fp0
+	fdabsw	%a3@+,%fp0
+	fdabsw	%a2@-,%fp0
 	fdabsw	%fp@(8),%fp0
+	fdabsw	%pc@(.+0x1238),%fp0
+	fdabsd	%a4@,%fp0
+	fdabsd	%a3@+,%fp0
+	fdabsd	%a2@-,%fp0
 	fdabsd	%fp@(8),%fp0
+	fdabsd	%pc@(.+0x1238),%fp0
+	fdabsb	%d5,%fp0
+	fdabsb	%a4@,%fp0
+	fdabsb	%a3@+,%fp0
+	fdabsb	%a2@-,%fp0
 	fdabsb	%fp@(8),%fp0
+	fdabsb	%pc@(.+0x1238),%fp0
 	fnegd	%fp0,%fp0
+	fnegl	%d5,%fp0
+	fnegl	%a4@,%fp0
+	fnegl	%a3@+,%fp0
+	fnegl	%a2@-,%fp0
 	fnegl	%fp@(8),%fp0
+	fnegl	%pc@(.+0x1238),%fp0
+	fnegs	%d5,%fp0
+	fnegs	%a4@,%fp0
+	fnegs	%a3@+,%fp0
+	fnegs	%a2@-,%fp0
 	fnegs	%fp@(8),%fp0
+	fnegs	%pc@(.+0x1238),%fp0
+	fnegw	%d5,%fp0
+	fnegw	%a4@,%fp0
+	fnegw	%a3@+,%fp0
+	fnegw	%a2@-,%fp0
 	fnegw	%fp@(8),%fp0
+	fnegw	%pc@(.+0x1238),%fp0
+	fnegd	%a4@,%fp0
+	fnegd	%a3@+,%fp0
+	fnegd	%a2@-,%fp0
 	fnegd	%fp@(8),%fp0
+	fnegd	%pc@(.+0x1238),%fp0
+	fnegb	%d5,%fp0
+	fnegb	%a4@,%fp0
+	fnegb	%a3@+,%fp0
+	fnegb	%a2@-,%fp0
 	fnegb	%fp@(8),%fp0
+	fnegb	%pc@(.+0x1238),%fp0
 	fsnegd	%fp0,%fp0
+	fsnegl	%d5,%fp0
+	fsnegl	%a4@,%fp0
+	fsnegl	%a3@+,%fp0
+	fsnegl	%a2@-,%fp0
 	fsnegl	%fp@(8),%fp0
+	fsnegl	%pc@(.+0x1238),%fp0
+	fsnegs	%d5,%fp0
+	fsnegs	%a4@,%fp0
+	fsnegs	%a3@+,%fp0
+	fsnegs	%a2@-,%fp0
 	fsnegs	%fp@(8),%fp0
+	fsnegs	%pc@(.+0x1238),%fp0
+	fsnegw	%d5,%fp0
+	fsnegw	%a4@,%fp0
+	fsnegw	%a3@+,%fp0
+	fsnegw	%a2@-,%fp0
 	fsnegw	%fp@(8),%fp0
+	fsnegw	%pc@(.+0x1238),%fp0
+	fsnegd	%a4@,%fp0
+	fsnegd	%a3@+,%fp0
+	fsnegd	%a2@-,%fp0
 	fsnegd	%fp@(8),%fp0
+	fsnegd	%pc@(.+0x1238),%fp0
+	fsnegb	%d5,%fp0
+	fsnegb	%a4@,%fp0
+	fsnegb	%a3@+,%fp0
+	fsnegb	%a2@-,%fp0
 	fsnegb	%fp@(8),%fp0
+	fsnegb	%pc@(.+0x1238),%fp0
 	fdnegd	%fp0,%fp0
+	fdnegl	%d5,%fp0
+	fdnegl	%a4@,%fp0
+	fdnegl	%a3@+,%fp0
+	fdnegl	%a2@-,%fp0
 	fdnegl	%fp@(8),%fp0
+	fdnegl	%pc@(.+0x1238),%fp0
+	fdnegs	%d5,%fp0
+	fdnegs	%a4@,%fp0
+	fdnegs	%a3@+,%fp0
+	fdnegs	%a2@-,%fp0
 	fdnegs	%fp@(8),%fp0
+	fdnegs	%pc@(.+0x1238),%fp0
+	fdnegw	%d5,%fp0
+	fdnegw	%a4@,%fp0
+	fdnegw	%a3@+,%fp0
+	fdnegw	%a2@-,%fp0
 	fdnegw	%fp@(8),%fp0
+	fdnegw	%pc@(.+0x1238),%fp0
+	fdnegd	%a4@,%fp0
+	fdnegd	%a3@+,%fp0
+	fdnegd	%a2@-,%fp0
 	fdnegd	%fp@(8),%fp0
+	fdnegd	%pc@(.+0x1238),%fp0
+	fdnegb	%d5,%fp0
+	fdnegb	%a4@,%fp0
+	fdnegb	%a3@+,%fp0
+	fdnegb	%a2@-,%fp0
 	fdnegb	%fp@(8),%fp0
+	fdnegb	%pc@(.+0x1238),%fp0
 	fdivd	%fp0,%fp0
+	fdivl	%d5,%fp0
+	fdivl	%a4@,%fp0
+	fdivl	%a3@+,%fp0
+	fdivl	%a2@-,%fp0
 	fdivl	%fp@(8),%fp0
+	fdivl	%pc@(.+0x1238),%fp0
+	fdivs	%d5,%fp0
+	fdivs	%a4@,%fp0
+	fdivs	%a3@+,%fp0
+	fdivs	%a2@-,%fp0
 	fdivs	%fp@(8),%fp0
+	fdivs	%pc@(.+0x1238),%fp0
+	fdivw	%d5,%fp0
+	fdivw	%a4@,%fp0
+	fdivw	%a3@+,%fp0
+	fdivw	%a2@-,%fp0
 	fdivw	%fp@(8),%fp0
+	fdivw	%pc@(.+0x1238),%fp0
+	fdivd	%a4@,%fp0
+	fdivd	%a3@+,%fp0
+	fdivd	%a2@-,%fp0
 	fdivd	%fp@(8),%fp0
+	fdivd	%pc@(.+0x1238),%fp0
+	fdivb	%d5,%fp0
+	fdivb	%a4@,%fp0
+	fdivb	%a3@+,%fp0
+	fdivb	%a2@-,%fp0
 	fdivb	%fp@(8),%fp0
+	fdivb	%pc@(.+0x1238),%fp0
 	fsdivd	%fp0,%fp0
+	fsdivl	%d5,%fp0
+	fsdivl	%a4@,%fp0
+	fsdivl	%a3@+,%fp0
+	fsdivl	%a2@-,%fp0
 	fsdivl	%fp@(8),%fp0
+	fsdivl	%pc@(.+0x1238),%fp0
+	fsdivs	%d5,%fp0
+	fsdivs	%a4@,%fp0
+	fsdivs	%a3@+,%fp0
+	fsdivs	%a2@-,%fp0
 	fsdivs	%fp@(8),%fp0
+	fsdivs	%pc@(.+0x1238),%fp0
+	fsdivw	%d5,%fp0
+	fsdivw	%a4@,%fp0
+	fsdivw	%a3@+,%fp0
+	fsdivw	%a2@-,%fp0
 	fsdivw	%fp@(8),%fp0
+	fsdivw	%pc@(.+0x1238),%fp0
+	fsdivd	%a4@,%fp0
+	fsdivd	%a3@+,%fp0
+	fsdivd	%a2@-,%fp0
 	fsdivd	%fp@(8),%fp0
+	fsdivd	%pc@(.+0x1238),%fp0
+	fsdivb	%d5,%fp0
+	fsdivb	%a4@,%fp0
+	fsdivb	%a3@+,%fp0
+	fsdivb	%a2@-,%fp0
 	fsdivb	%fp@(8),%fp0
+	fsdivb	%pc@(.+0x1238),%fp0
 	fddivd	%fp0,%fp0
+	fddivl	%d5,%fp0
+	fddivl	%a4@,%fp0
+	fddivl	%a3@+,%fp0
+	fddivl	%a2@-,%fp0
 	fddivl	%fp@(8),%fp0
+	fddivl	%pc@(.+0x1238),%fp0
+	fddivs	%d5,%fp0
+	fddivs	%a4@,%fp0
+	fddivs	%a3@+,%fp0
+	fddivs	%a2@-,%fp0
 	fddivs	%fp@(8),%fp0
+	fddivs	%pc@(.+0x1238),%fp0
+	fddivw	%d5,%fp0
+	fddivw	%a4@,%fp0
+	fddivw	%a3@+,%fp0
+	fddivw	%a2@-,%fp0
 	fddivw	%fp@(8),%fp0
+	fddivw	%pc@(.+0x1238),%fp0
+	fddivd	%a4@,%fp0
+	fddivd	%a3@+,%fp0
+	fddivd	%a2@-,%fp0
 	fddivd	%fp@(8),%fp0
+	fddivd	%pc@(.+0x1238),%fp0
+	fddivb	%d5,%fp0
+	fddivb	%a4@,%fp0
+	fddivb	%a3@+,%fp0
+	fddivb	%a2@-,%fp0
 	fddivb	%fp@(8),%fp0
+	fddivb	%pc@(.+0x1238),%fp0
 	faddd	%fp0,%fp0
+	faddl	%d5,%fp0
+	faddl	%a4@,%fp0
+	faddl	%a3@+,%fp0
+	faddl	%a2@-,%fp0
 	faddl	%fp@(8),%fp0
+	faddl	%pc@(.+0x1238),%fp0
+	fadds	%d5,%fp0
+	fadds	%a4@,%fp0
+	fadds	%a3@+,%fp0
+	fadds	%a2@-,%fp0
 	fadds	%fp@(8),%fp0
+	fadds	%pc@(.+0x1238),%fp0
+	faddw	%d5,%fp0
+	faddw	%a4@,%fp0
+	faddw	%a3@+,%fp0
+	faddw	%a2@-,%fp0
 	faddw	%fp@(8),%fp0
+	faddw	%pc@(.+0x1238),%fp0
+	faddd	%a4@,%fp0
+	faddd	%a3@+,%fp0
+	faddd	%a2@-,%fp0
 	faddd	%fp@(8),%fp0
+	faddd	%pc@(.+0x1238),%fp0
+	faddb	%d5,%fp0
+	faddb	%a4@,%fp0
+	faddb	%a3@+,%fp0
+	faddb	%a2@-,%fp0
 	faddb	%fp@(8),%fp0
+	faddb	%pc@(.+0x1238),%fp0
 	fsaddd	%fp0,%fp0
+	fsaddl	%d5,%fp0
+	fsaddl	%a4@,%fp0
+	fsaddl	%a3@+,%fp0
+	fsaddl	%a2@-,%fp0
 	fsaddl	%fp@(8),%fp0
+	fsaddl	%pc@(.+0x1238),%fp0
+	fsadds	%d5,%fp0
+	fsadds	%a4@,%fp0
+	fsadds	%a3@+,%fp0
+	fsadds	%a2@-,%fp0
 	fsadds	%fp@(8),%fp0
+	fsadds	%pc@(.+0x1238),%fp0
+	fsaddw	%d5,%fp0
+	fsaddw	%a4@,%fp0
+	fsaddw	%a3@+,%fp0
+	fsaddw	%a2@-,%fp0
 	fsaddw	%fp@(8),%fp0
+	fsaddw	%pc@(.+0x1238),%fp0
+	fsaddd	%a4@,%fp0
+	fsaddd	%a3@+,%fp0
+	fsaddd	%a2@-,%fp0
 	fsaddd	%fp@(8),%fp0
+	fsaddd	%pc@(.+0x1238),%fp0
+	fsaddb	%d5,%fp0
+	fsaddb	%a4@,%fp0
+	fsaddb	%a3@+,%fp0
+	fsaddb	%a2@-,%fp0
 	fsaddb	%fp@(8),%fp0
+	fsaddb	%pc@(.+0x1238),%fp0
 	fdaddd	%fp0,%fp0
+	fdaddl	%d5,%fp0
+	fdaddl	%a4@,%fp0
+	fdaddl	%a3@+,%fp0
+	fdaddl	%a2@-,%fp0
 	fdaddl	%fp@(8),%fp0
+	fdaddl	%pc@(.+0x1238),%fp0
+	fdadds	%d5,%fp0
+	fdadds	%a4@,%fp0
+	fdadds	%a3@+,%fp0
+	fdadds	%a2@-,%fp0
 	fdadds	%fp@(8),%fp0
+	fdadds	%pc@(.+0x1238),%fp0
+	fdaddw	%d5,%fp0
+	fdaddw	%a4@,%fp0
+	fdaddw	%a3@+,%fp0
+	fdaddw	%a2@-,%fp0
 	fdaddw	%fp@(8),%fp0
+	fdaddw	%pc@(.+0x1238),%fp0
+	fdaddd	%a4@,%fp0
+	fdaddd	%a3@+,%fp0
+	fdaddd	%a2@-,%fp0
 	fdaddd	%fp@(8),%fp0
+	fdaddd	%pc@(.+0x1238),%fp0
+	fdaddb	%d5,%fp0
+	fdaddb	%a4@,%fp0
+	fdaddb	%a3@+,%fp0
+	fdaddb	%a2@-,%fp0
 	fdaddb	%fp@(8),%fp0
+	fdaddb	%pc@(.+0x1238),%fp0
 	fmuld	%fp0,%fp0
+	fmull	%d5,%fp0
+	fmull	%a4@,%fp0
+	fmull	%a3@+,%fp0
+	fmull	%a2@-,%fp0
 	fmull	%fp@(8),%fp0
+	fmull	%pc@(.+0x1238),%fp0
+	fmuls	%d5,%fp0
+	fmuls	%a4@,%fp0
+	fmuls	%a3@+,%fp0
+	fmuls	%a2@-,%fp0
 	fmuls	%fp@(8),%fp0
+	fmuls	%pc@(.+0x1238),%fp0
+	fmulw	%d5,%fp0
+	fmulw	%a4@,%fp0
+	fmulw	%a3@+,%fp0
+	fmulw	%a2@-,%fp0
 	fmulw	%fp@(8),%fp0
+	fmulw	%pc@(.+0x1238),%fp0
+	fmuld	%a4@,%fp0
+	fmuld	%a3@+,%fp0
+	fmuld	%a2@-,%fp0
 	fmuld	%fp@(8),%fp0
+	fmuld	%pc@(.+0x1238),%fp0
+	fmulb	%d5,%fp0
+	fmulb	%a4@,%fp0
+	fmulb	%a3@+,%fp0
+	fmulb	%a2@-,%fp0
 	fmulb	%fp@(8),%fp0
+	fmulb	%pc@(.+0x1238),%fp0
 	fsmuld	%fp0,%fp0
+	fsmull	%d5,%fp0
+	fsmull	%a4@,%fp0
+	fsmull	%a3@+,%fp0
+	fsmull	%a2@-,%fp0
 	fsmull	%fp@(8),%fp0
+	fsmull	%pc@(.+0x1238),%fp0
+	fsmuls	%d5,%fp0
+	fsmuls	%a4@,%fp0
+	fsmuls	%a3@+,%fp0
+	fsmuls	%a2@-,%fp0
 	fsmuls	%fp@(8),%fp0
+	fsmuls	%pc@(.+0x1238),%fp0
+	fsmulw	%d5,%fp0
+	fsmulw	%a4@,%fp0
+	fsmulw	%a3@+,%fp0
+	fsmulw	%a2@-,%fp0
 	fsmulw	%fp@(8),%fp0
+	fsmulw	%pc@(.+0x1238),%fp0
+	fsmuld	%a4@,%fp0
+	fsmuld	%a3@+,%fp0
+	fsmuld	%a2@-,%fp0
 	fsmuld	%fp@(8),%fp0
+	fsmuld	%pc@(.+0x1238),%fp0
+	fsmulb	%d5,%fp0
+	fsmulb	%a4@,%fp0
+	fsmulb	%a3@+,%fp0
+	fsmulb	%a2@-,%fp0
 	fsmulb	%fp@(8),%fp0
+	fsmulb	%pc@(.+0x1238),%fp0
 	fdmuld	%fp0,%fp0
+	fdmull	%d5,%fp0
+	fdmull	%a4@,%fp0
+	fdmull	%a3@+,%fp0
+	fdmull	%a2@-,%fp0
 	fdmull	%fp@(8),%fp0
+	fdmull	%pc@(.+0x1238),%fp0
+	fdmuls	%d5,%fp0
+	fdmuls	%a4@,%fp0
+	fdmuls	%a3@+,%fp0
+	fdmuls	%a2@-,%fp0
 	fdmuls	%fp@(8),%fp0
+	fdmuls	%pc@(.+0x1238),%fp0
+	fdmulw	%d5,%fp0
+	fdmulw	%a4@,%fp0
+	fdmulw	%a3@+,%fp0
+	fdmulw	%a2@-,%fp0
 	fdmulw	%fp@(8),%fp0
+	fdmulw	%pc@(.+0x1238),%fp0
+	fdmuld	%a4@,%fp0
+	fdmuld	%a3@+,%fp0
+	fdmuld	%a2@-,%fp0
 	fdmuld	%fp@(8),%fp0
+	fdmuld	%pc@(.+0x1238),%fp0
+	fdmulb	%d5,%fp0
+	fdmulb	%a4@,%fp0
+	fdmulb	%a3@+,%fp0
+	fdmulb	%a2@-,%fp0
 	fdmulb	%fp@(8),%fp0
+	fdmulb	%pc@(.+0x1238),%fp0
 	fsubd	%fp0,%fp0
+	fsubl	%d5,%fp0
+	fsubl	%a4@,%fp0
+	fsubl	%a3@+,%fp0
+	fsubl	%a2@-,%fp0
 	fsubl	%fp@(8),%fp0
+	fsubl	%pc@(.+0x1238),%fp0
+	fsubs	%d5,%fp0
+	fsubs	%a4@,%fp0
+	fsubs	%a3@+,%fp0
+	fsubs	%a2@-,%fp0
 	fsubs	%fp@(8),%fp0
+	fsubs	%pc@(.+0x1238),%fp0
+	fsubw	%d5,%fp0
+	fsubw	%a4@,%fp0
+	fsubw	%a3@+,%fp0
+	fsubw	%a2@-,%fp0
 	fsubw	%fp@(8),%fp0
+	fsubw	%pc@(.+0x1238),%fp0
+	fsubd	%a4@,%fp0
+	fsubd	%a3@+,%fp0
+	fsubd	%a2@-,%fp0
 	fsubd	%fp@(8),%fp0
+	fsubd	%pc@(.+0x1238),%fp0
+	fsubb	%d5,%fp0
+	fsubb	%a4@,%fp0
+	fsubb	%a3@+,%fp0
+	fsubb	%a2@-,%fp0
 	fsubb	%fp@(8),%fp0
+	fsubb	%pc@(.+0x1238),%fp0
 	fssubd	%fp0,%fp0
+	fssubl	%d5,%fp0
+	fssubl	%a4@,%fp0
+	fssubl	%a3@+,%fp0
+	fssubl	%a2@-,%fp0
 	fssubl	%fp@(8),%fp0
+	fssubl	%pc@(.+0x1238),%fp0
+	fssubs	%d5,%fp0
+	fssubs	%a4@,%fp0
+	fssubs	%a3@+,%fp0
+	fssubs	%a2@-,%fp0
 	fssubs	%fp@(8),%fp0
+	fssubs	%pc@(.+0x1238),%fp0
+	fssubw	%d5,%fp0
+	fssubw	%a4@,%fp0
+	fssubw	%a3@+,%fp0
+	fssubw	%a2@-,%fp0
 	fssubw	%fp@(8),%fp0
+	fssubw	%pc@(.+0x1238),%fp0
+	fssubd	%a4@,%fp0
+	fssubd	%a3@+,%fp0
+	fssubd	%a2@-,%fp0
 	fssubd	%fp@(8),%fp0
+	fssubd	%pc@(.+0x1238),%fp0
+	fssubb	%d5,%fp0
+	fssubb	%a4@,%fp0
+	fssubb	%a3@+,%fp0
+	fssubb	%a2@-,%fp0
 	fssubb	%fp@(8),%fp0
+	fssubb	%pc@(.+0x1238),%fp0
 	fdsubd	%fp0,%fp0
+	fdsubl	%d5,%fp0
+	fdsubl	%a4@,%fp0
+	fdsubl	%a3@+,%fp0
+	fdsubl	%a2@-,%fp0
 	fdsubl	%fp@(8),%fp0
+	fdsubl	%pc@(.+0x1238),%fp0
+	fdsubs	%d5,%fp0
+	fdsubs	%a4@,%fp0
+	fdsubs	%a3@+,%fp0
+	fdsubs	%a2@-,%fp0
 	fdsubs	%fp@(8),%fp0
+	fdsubs	%pc@(.+0x1238),%fp0
+	fdsubw	%d5,%fp0
+	fdsubw	%a4@,%fp0
+	fdsubw	%a3@+,%fp0
+	fdsubw	%a2@-,%fp0
 	fdsubw	%fp@(8),%fp0
+	fdsubw	%pc@(.+0x1238),%fp0
+	fdsubd	%a4@,%fp0
+	fdsubd	%a3@+,%fp0
+	fdsubd	%a2@-,%fp0
 	fdsubd	%fp@(8),%fp0
+	fdsubd	%pc@(.+0x1238),%fp0
+	fdsubb	%d5,%fp0
+	fdsubb	%a4@,%fp0
+	fdsubb	%a3@+,%fp0
+	fdsubb	%a2@-,%fp0
 	fdsubb	%fp@(8),%fp0
+	fdsubb	%pc@(.+0x1238),%fp0
 	fmoved	%fp0,%fp0
+	fmovel	%d5,%fp0
+	fmovel	%a4@,%fp0
+	fmovel	%a3@+,%fp0
+	fmovel	%a2@-,%fp0
 	fmovel	%fp@(8),%fp0
+	fmovel	%pc@(.+0x1238),%fp0
+	fmoves	%d5,%fp0
+	fmoves	%a4@,%fp0
+	fmoves	%a3@+,%fp0
+	fmoves	%a2@-,%fp0
 	fmoves	%fp@(8),%fp0
+	fmoves	%pc@(.+0x1238),%fp0
+	fmovew	%d5,%fp0
+	fmovew	%a4@,%fp0
+	fmovew	%a3@+,%fp0
+	fmovew	%a2@-,%fp0
 	fmovew	%fp@(8),%fp0
+	fmovew	%pc@(.+0x1238),%fp0
+	fmoved	%a4@,%fp0
+	fmoved	%a3@+,%fp0
+	fmoved	%a2@-,%fp0
 	fmoved	%fp@(8),%fp0
+	fmoved	%pc@(.+0x1238),%fp0
+	fmoveb	%d5,%fp0
+	fmoveb	%a4@,%fp0
+	fmoveb	%a3@+,%fp0
+	fmoveb	%a2@-,%fp0
 	fmoveb	%fp@(8),%fp0
+	fmoveb	%pc@(.+0x1238),%fp0
 	fsmoved	%fp0,%fp0
+	fsmovel	%d5,%fp0
+	fsmovel	%a4@,%fp0
+	fsmovel	%a3@+,%fp0
+	fsmovel	%a2@-,%fp0
 	fsmovel	%fp@(8),%fp0
+	fsmovel	%pc@(.+0x1238),%fp0
+	fsmoves	%d5,%fp0
+	fsmoves	%a4@,%fp0
+	fsmoves	%a3@+,%fp0
+	fsmoves	%a2@-,%fp0
 	fsmoves	%fp@(8),%fp0
+	fsmoves	%pc@(.+0x1238),%fp0
+	fsmovew	%d5,%fp0
+	fsmovew	%a4@,%fp0
+	fsmovew	%a3@+,%fp0
+	fsmovew	%a2@-,%fp0
 	fsmovew	%fp@(8),%fp0
+	fsmovew	%pc@(.+0x1238),%fp0
+	fsmoved	%a4@,%fp0
+	fsmoved	%a3@+,%fp0
+	fsmoved	%a2@-,%fp0
 	fsmoved	%fp@(8),%fp0
+	fsmoved	%pc@(.+0x1238),%fp0
+	fsmoveb	%d5,%fp0
+	fsmoveb	%a4@,%fp0
+	fsmoveb	%a3@+,%fp0
+	fsmoveb	%a2@-,%fp0
 	fsmoveb	%fp@(8),%fp0
+	fsmoveb	%pc@(.+0x1238),%fp0
 	fdmoved	%fp0,%fp0
+	fdmovel	%d5,%fp0
+	fdmovel	%a4@,%fp0
+	fdmovel	%a3@+,%fp0
+	fdmovel	%a2@-,%fp0
 	fdmovel	%fp@(8),%fp0
+	fdmovel	%pc@(.+0x1238),%fp0
+	fdmoves	%d5,%fp0
+	fdmoves	%a4@,%fp0
+	fdmoves	%a3@+,%fp0
+	fdmoves	%a2@-,%fp0
 	fdmoves	%fp@(8),%fp0
+	fdmoves	%pc@(.+0x1238),%fp0
+	fdmovew	%d5,%fp0
+	fdmovew	%a4@,%fp0
+	fdmovew	%a3@+,%fp0
+	fdmovew	%a2@-,%fp0
 	fdmovew	%fp@(8),%fp0
+	fdmovew	%pc@(.+0x1238),%fp0
+	fdmoved	%a4@,%fp0
+	fdmoved	%a3@+,%fp0
+	fdmoved	%a2@-,%fp0
 	fdmoved	%fp@(8),%fp0
+	fdmoved	%pc@(.+0x1238),%fp0
+	fdmoveb	%d5,%fp0
+	fdmoveb	%a4@,%fp0
+	fdmoveb	%a3@+,%fp0
+	fdmoveb	%a2@-,%fp0
 	fdmoveb	%fp@(8),%fp0
+	fdmoveb	%pc@(.+0x1238),%fp0
 	fintd	%fp0,%fp0
+	fintl	%d5,%fp0
+	fintl	%a4@,%fp0
+	fintl	%a3@+,%fp0
+	fintl	%a2@-,%fp0
 	fintl	%fp@(8),%fp0
+	fintl	%pc@(.+0x1238),%fp0
+	fints	%d5,%fp0
+	fints	%a4@,%fp0
+	fints	%a3@+,%fp0
+	fints	%a2@-,%fp0
 	fints	%fp@(8),%fp0
+	fints	%pc@(.+0x1238),%fp0
+	fintw	%d5,%fp0
+	fintw	%a4@,%fp0
+	fintw	%a3@+,%fp0
+	fintw	%a2@-,%fp0
 	fintw	%fp@(8),%fp0
+	fintw	%pc@(.+0x1238),%fp0
+	fintd	%a4@,%fp0
+	fintd	%a3@+,%fp0
+	fintd	%a2@-,%fp0
 	fintd	%fp@(8),%fp0
+	fintd	%pc@(.+0x1238),%fp0
+	fintb	%d5,%fp0
+	fintb	%a4@,%fp0
+	fintb	%a3@+,%fp0
+	fintb	%a2@-,%fp0
 	fintb	%fp@(8),%fp0
+	fintb	%pc@(.+0x1238),%fp0
 	fintrzd	%fp0,%fp0
+	fintrzl	%d5,%fp0
+	fintrzl	%a4@,%fp0
+	fintrzl	%a3@+,%fp0
+	fintrzl	%a2@-,%fp0
 	fintrzl	%fp@(8),%fp0
+	fintrzl	%pc@(.+0x1238),%fp0
+	fintrzs	%d5,%fp0
+	fintrzs	%a4@,%fp0
+	fintrzs	%a3@+,%fp0
+	fintrzs	%a2@-,%fp0
 	fintrzs	%fp@(8),%fp0
+	fintrzs	%pc@(.+0x1238),%fp0
+	fintrzw	%d5,%fp0
+	fintrzw	%a4@,%fp0
+	fintrzw	%a3@+,%fp0
+	fintrzw	%a2@-,%fp0
 	fintrzw	%fp@(8),%fp0
+	fintrzw	%pc@(.+0x1238),%fp0
+	fintrzd	%a4@,%fp0
+	fintrzd	%a3@+,%fp0
+	fintrzd	%a2@-,%fp0
 	fintrzd	%fp@(8),%fp0
+	fintrzd	%pc@(.+0x1238),%fp0
+	fintrzb	%d5,%fp0
+	fintrzb	%a4@,%fp0
+	fintrzb	%a3@+,%fp0
+	fintrzb	%a2@-,%fp0
 	fintrzb	%fp@(8),%fp0
+	fintrzb	%pc@(.+0x1238),%fp0
 	fcmpd	%fp0,%fp0
+	fcmpl	%d5,%fp0
+	fcmpl	%a4@,%fp0
+	fcmpl	%a3@+,%fp0
+	fcmpl	%a2@-,%fp0
 	fcmpl	%fp@(8),%fp0
+	fcmpl	%pc@(.+0x1238),%fp0
+	fcmps	%d5,%fp0
+	fcmps	%a4@,%fp0
+	fcmps	%a3@+,%fp0
+	fcmps	%a2@-,%fp0
 	fcmps	%fp@(8),%fp0
+	fcmps	%pc@(.+0x1238),%fp0
+	fcmpw	%d5,%fp0
+	fcmpw	%a4@,%fp0
+	fcmpw	%a3@+,%fp0
+	fcmpw	%a2@-,%fp0
 	fcmpw	%fp@(8),%fp0
+	fcmpw	%pc@(.+0x1238),%fp0
+	fcmpd	%a4@,%fp0
+	fcmpd	%a3@+,%fp0
+	fcmpd	%a2@-,%fp0
 	fcmpd	%fp@(8),%fp0
+	fcmpd	%pc@(.+0x1238),%fp0
+	fcmpb	%d5,%fp0
+	fcmpb	%a4@,%fp0
+	fcmpb	%a3@+,%fp0
+	fcmpb	%a2@-,%fp0
 	fcmpb	%fp@(8),%fp0
+	fcmpb	%pc@(.+0x1238),%fp0
 	fmovemd	%fp0-%fp3/%fp6,%fp@(8)
 	fmovemd	%fp@(8),%fp5/%fp4/%fp2
 	fmovemd	#0x27,%fp@(8)
diff --git a/gas/testsuite/gas/m68k/mcf-trap.d b/gas/testsuite/gas/m68k/mcf-trap.d
new file mode 100644
index 000000000000..63d18fd7bfd4
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-trap.d
@@ -0,0 +1,15 @@
+#name: mcf-trap
+#objdump: -d
+#as: -m5208
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 0-9a-f]+:	51fc           	t[rap]*f
+[ 0-9a-f]+:	51fa 1234      	t[rap]*fw #4660
+[ 0-9a-f]+:	51fb 1234 5678 	t[rap]*fl #305419896
+[ 0-9a-f]+:	51fc           	t[rap]*f
+[ 0-9a-f]+:	51fa 1234      	t[rap]*fw #4660
+[ 0-9a-f]+:	51fb 1234 5678 	t[rap]*fl #305419896
diff --git a/gas/testsuite/gas/m68k/mcf-trap.s b/gas/testsuite/gas/m68k/mcf-trap.s
new file mode 100644
index 000000000000..a5d6acc7db86
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-trap.s
@@ -0,0 +1,9 @@
+	#  the m68k compatible names
+	trapf
+	trapf.w #0x1234
+	trapf.l #0x12345678
+
+	# the coldfire specific names
+	tpf
+	tpf.w #0x1234
+	tpf.l #0x12345678
diff --git a/gas/testsuite/gas/m68k/mcf-wdebug.d b/gas/testsuite/gas/m68k/mcf-wdebug.d
new file mode 100644
index 000000000000..257d1e386031
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-wdebug.d
@@ -0,0 +1,11 @@
+#name: mcf-wdebug
+#objdump: -d
+#as: -m5208
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <foo>:
+   0:	fbd0 0003      	wdebugl %a0@
+   4:	fbd0 0003      	wdebugl %a0@
diff --git a/gas/testsuite/gas/m68k/mcf-wdebug.s b/gas/testsuite/gas/m68k/mcf-wdebug.s
new file mode 100644
index 000000000000..36b9f27df9d9
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-wdebug.s
@@ -0,0 +1,6 @@
+# Check that gas recognizes both wdebug and wdebug.l.
+	.text
+	.globl	foo
+foo:
+	wdebug (%a0)
+	wdebug.l (%a0)
diff --git a/gas/testsuite/gas/m68k/p3041.d b/gas/testsuite/gas/m68k/p3041.d
new file mode 100644
index 000000000000..b4a41c4a01ee
--- /dev/null
+++ b/gas/testsuite/gas/m68k/p3041.d
@@ -0,0 +1,15 @@
+#name: PR 3041
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.*>:
+   0:	4ef9 0000 0002 [ 	]+jmp 2 <mylabel-0x6>
+			2: .*	mylabel
+   6:	4e71 [ 	]+nop
+
+0+8 <mylabel>:
+   8:	4e71 [ 	]+nop
+   a:	4e71 [ 	]+nop
diff --git a/gas/testsuite/gas/m68k/p3041.s b/gas/testsuite/gas/m68k/p3041.s
new file mode 100644
index 000000000000..96a8910b104c
--- /dev/null
+++ b/gas/testsuite/gas/m68k/p3041.s
@@ -0,0 +1,6 @@
+	jmp	mylabel+2
+	nop
+	.weak	mylabel
+mylabel:
+	nop
+	nop
diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp
index e175ad9a53ec..62392ec3b48c 100644
--- a/gas/testsuite/gas/macros/macros.exp
+++ b/gas/testsuite/gas/macros/macros.exp
@@ -1,18 +1,5 @@
 # Run some tests of gas macros.
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "macros $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
     run_dump_test test1
 }
@@ -69,6 +56,7 @@ run_dump_test app3
 run_dump_test app4
 
 run_list_test badarg ""
+
 case $target_triplet in {
     { *c54x*-*-* } { }
     { *c4x*-*-* } { }
diff --git a/gas/testsuite/gas/maxq10/maxq10.exp b/gas/testsuite/gas/maxq10/maxq10.exp
index 482bd4ca2c23..8887b53494eb 100644
--- a/gas/testsuite/gas/maxq10/maxq10.exp
+++ b/gas/testsuite/gas/maxq10/maxq10.exp
@@ -1,19 +1,6 @@
 #
 # MAXQ10 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "maxq10 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 proc gas_64_check { } {
     global NM
     global NMFLAGS
diff --git a/gas/testsuite/gas/maxq20/maxq20.exp b/gas/testsuite/gas/maxq20/maxq20.exp
index d2857f617b96..6d952e9e3ed5 100644
--- a/gas/testsuite/gas/maxq20/maxq20.exp
+++ b/gas/testsuite/gas/maxq20/maxq20.exp
@@ -1,19 +1,6 @@
 #
 # MAXQ20 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "maxq20 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 proc gas_64_check { } {
     global NM
     global NMFLAGS
diff --git a/gas/testsuite/gas/mcore/allinsn.d b/gas/testsuite/gas/mcore/allinsn.d
index 1565ea5d5fe3..a53805bae2f5 100644
--- a/gas/testsuite/gas/mcore/allinsn.d
+++ b/gas/testsuite/gas/mcore/allinsn.d
@@ -40,7 +40,7 @@ Disassembly of section \.text:
   14:	300f      	bclri	r15, 0
 
 0+016 <bf>:
-  16:	eff4      	bf	0x0
+  16:	eff4      	bf	0x.*0
 
 0+018 <bgeni>:
   18:	3270      	bgeni	r0, 7
@@ -64,7 +64,7 @@ Disassembly of section \.text:
   24:	2df3      	bmaski	r3, 31
 
 0+026 <br>:
-  26:	f7ff      	br	0x26
+  26:	f7ff      	br	0x.*26
 
 0+028 <brev>:
   28:	00f4      	brev	r4
@@ -73,10 +73,10 @@ Disassembly of section \.text:
   2a:	35e5      	bseti	r5, 30
 
 0+02c <bsr>:
-  2c:	ffe9      	bsr	0x0
+  2c:	ffe9      	bsr	0x.*0.*
 
 0+02e <bt>:
-  2e:	e7e8      	bt	0x0
+  2e:	e7e8      	bt	0x.*0
 
 0+030 <btsti>:
   30:	37b6      	btsti	r6, 27
@@ -148,7 +148,7 @@ Disassembly of section \.text:
   5c:	150f      	ixw	r15, r0
 
 0+05e <jbf>:
-  5e:	efd0      	bf	0x0
+  5e:	efd0      	bf	0x.*0
 
 0+060 <jbr>:
   60:	f00e      	br	0x7e
@@ -202,10 +202,10 @@ Disassembly of section \.text:
   80:	048e      	loopt	r8, 0x64
 
 0+082 <LRW>:
-  82:	7903      	lrw	r9, (0x86|0x0	// from address pool at 0x90)
+  82:	7901      	lrw	r9, 0x3C0C1BBA
 
 0+084 <lrw>:
-  84:	7904      	lrw	r9, 0x4321
+  84:	7903      	lrw	r9, 0x4321
 
 0+086 <foolit>:
   86:	1234      	mov	r4, r3
@@ -218,184 +218,181 @@ Disassembly of section \.text:
   8c:	0000      	bkpt
 			8c: ADDR32	\.text
   8e:	0000      	bkpt
-  90:	(0000      	bkpt|0086      	dect	r6)
-			90: ADDR32	\.text(\+0x86)?
+  90:	4321      	\.short 0x4321
   92:	0000      	bkpt
-  94:	4321      	\.short 0x4321
-  96:	0000      	bkpt
 
-0+098 <lsli>:
-  98:	3dfd      	lsli	r13, 31
+0+094 <lsli>:
+  94:	3dfd      	lsli	r13, 31
 
-0+09a <lsr>:
-  9a:	0bfe      	lsr	r14, r15
+0+096 <lsr>:
+  96:	0bfe      	lsr	r14, r15
 
-0+09c <lsrc>:
-  9c:	3e00      	lsrc	r0
+0+098 <lsrc>:
+  98:	3e00      	lsrc	r0
 
-0+09e <lsri>:
-  9e:	3e11      	lsri	r1, 1
+0+09a <lsri>:
+  9a:	3e11      	lsri	r1, 1
 
-0+0a0 <mclri>:
-  a0:	3064      	bclri	r4, 6
+0+09c <mclri>:
+  9c:	3064      	bclri	r4, 6
 
-0+0a2 <mfcr>:
-  a2:	1002      	mfcr	r2, psr
+0+09e <mfcr>:
+  9e:	1002      	mfcr	r2, psr
 
-0+0a4 <mov>:
-  a4:	1243      	mov	r3, r4
+0+0a0 <mov>:
+  a0:	1243      	mov	r3, r4
 
-0+0a6 <movf>:
-  a6:	0a65      	movf	r5, r6
+0+0a2 <movf>:
+  a2:	0a65      	movf	r5, r6
 
-0+0a8 <movi>:
-  a8:	67f7      	movi	r7, 127
+0+0a4 <movi>:
+  a4:	67f7      	movi	r7, 127
 
-0+0aa <movt>:
-  aa:	0298      	movt	r8, r9
+0+0a6 <movt>:
+  a6:	0298      	movt	r8, r9
 
-0+0ac <mtcr>:
-  ac:	180a      	mtcr	r10, psr
+0+0a8 <mtcr>:
+  a8:	180a      	mtcr	r10, psr
 
-0+0ae <mult>:
-  ae:	03cb      	mult	r11, r12
+0+0aa <mult>:
+  aa:	03cb      	mult	r11, r12
 
-0+0b0 <mvc>:
-  b0:	002d      	mvc	r13
+0+0ac <mvc>:
+  ac:	002d      	mvc	r13
 
-0+0b2 <mvcv>:
-  b2:	003e      	mvcv	r14
+0+0ae <mvcv>:
+  ae:	003e      	mvcv	r14
 
-0+0b4 <neg>:
-  b4:	2802      	rsubi	r2, 0
+0+0b0 <neg>:
+  b0:	2802      	rsubi	r2, 0
 
-0+0b6 <not>:
-  b6:	01ff      	not	r15
+0+0b2 <not>:
+  b2:	01ff      	not	r15
 
-0+0b8 <or>:
-  b8:	1e10      	or	r0, r1
+0+0b4 <or>:
+  b4:	1e10      	or	r0, r1
 
-0+0ba <rfi>:
-  ba:	0003      	rfi
+0+0b6 <rfi>:
+  b6:	0003      	rfi
 
-0+0bc <rolc>:
-  bc:	0666      	addc	r6, r6
+0+0b8 <rolc>:
+  b8:	0666      	addc	r6, r6
 
-0+0be <rori>:
-  be:	39a9      	rotli	r9, 26
+0+0ba <rori>:
+  ba:	39a9      	rotli	r9, 26
 
-0+0c0 <rotlc>:
-  c0:	0666      	addc	r6, r6
+0+0bc <rotlc>:
+  bc:	0666      	addc	r6, r6
 
-0+0c2 <rotli>:
-  c2:	38a2      	rotli	r2, 10
+0+0be <rotli>:
+  be:	38a2      	rotli	r2, 10
 
-0+0c4 <rotri>:
-  c4:	39a9      	rotli	r9, 26
+0+0c0 <rotri>:
+  c0:	39a9      	rotli	r9, 26
 
-0+0c6 <rsub>:
-  c6:	1443      	rsub	r3, r4
+0+0c2 <rsub>:
+  c2:	1443      	rsub	r3, r4
 
-0+0c8 <rsubi>:
-  c8:	2805      	rsubi	r5, 0
+0+0c4 <rsubi>:
+  c4:	2805      	rsubi	r5, 0
 
-0+0ca <rte>:
-  ca:	0002      	rte
+0+0c6 <rte>:
+  c6:	0002      	rte
 
-0+0cc <rts>:
-  cc:	00cf      	jmp	r15
+0+0c8 <rts>:
+  c8:	00cf      	jmp	r15
 
-0+0ce <setc>:
-  ce:	0c00      	cmphs	r0, r0
+0+0ca <setc>:
+  ca:	0c00      	cmphs	r0, r0
 
-0+0d0 <sextb>:
-  d0:	0156      	sextb	r6
+0+0cc <sextb>:
+  cc:	0156      	sextb	r6
 
-0+0d2 <sexth>:
-  d2:	0177      	sexth	r7
+0+0ce <sexth>:
+  ce:	0177      	sexth	r7
 
-0+0d4 <st\.b>:
-  d4:	b809      	stb	r8, \(r9, 0\)
+0+0d0 <st\.b>:
+  d0:	b809      	stb	r8, \(r9, 0\)
 
-0+0d6 <st\.h>:
-  d6:	da1b      	sth	r10, \(r11, 2\)
+0+0d2 <st\.h>:
+  d2:	da1b      	sth	r10, \(r11, 2\)
 
-0+0d8 <st\.w>:
-  d8:	9c1d      	st	r12, \(r13, 4\)
+0+0d4 <st\.w>:
+  d4:	9c1d      	st	r12, \(r13, 4\)
 
-0+0da <stb>:
-  da:	beff      	stb	r14, \(r15, 15\)
+0+0d6 <stb>:
+  d6:	beff      	stb	r14, \(r15, 15\)
 
-0+0dc <sth>:
-  dc:	d0f1      	sth	r0, \(r1, 30\)
+0+0d8 <sth>:
+  d8:	d0f1      	sth	r0, \(r1, 30\)
 
-0+0de <stw>:
-  de:	92f3      	st	r2, \(r3, 60\)
+0+0da <stw>:
+  da:	92f3      	st	r2, \(r3, 60\)
 
-0+0e0 <st>:
-  e0:	9405      	st	r4, \(r5, 0\)
+0+0dc <st>:
+  dc:	9405      	st	r4, \(r5, 0\)
 
-0+0e2 <stm>:
-  e2:	007e      	stm	r14-r15, \(r0\)
+0+0de <stm>:
+  de:	007e      	stm	r14-r15, \(r0\)
 
-0+0e4 <stop>:
-  e4:	0004      	stop
+0+0e0 <stop>:
+  e0:	0004      	stop
 
-0+0e6 <stq>:
-  e6:	0051      	stq	r4-r7, \(r1\)
+0+0e2 <stq>:
+  e2:	0051      	stq	r4-r7, \(r1\)
 
-0+0e8 <subc>:
-  e8:	07d7      	subc	r7, r13
+0+0e4 <subc>:
+  e4:	07d7      	subc	r7, r13
 
-0+0ea <subi>:
-  ea:	25fe      	subi	r14, 32
+0+0e6 <subi>:
+  e6:	25fe      	subi	r14, 32
 
-0+0ec <subu>:
-  ec:	0539      	subu	r9, r3
+0+0e8 <subu>:
+  e8:	0539      	subu	r9, r3
 
-0+0ee <sync>:
-  ee:	0001      	sync
+0+0ea <sync>:
+  ea:	0001      	sync
 
-0+0f0 <tstlt>:
-  f0:	37f5      	btsti	r5, 31
+0+0ec <tstlt>:
+  ec:	37f5      	btsti	r5, 31
 
-0+0f2 <tstne>:
-  f2:	2a07      	cmpnei	r7, 0
+0+0ee <tstne>:
+  ee:	2a07      	cmpnei	r7, 0
 
-0+0f4 <trap>:
-  f4:	000a      	trap	2
+0+0f0 <trap>:
+  f0:	000a      	trap	2
 
-0+0f6 <tst>:
-  f6:	0eee      	tst	r14, r14
+0+0f2 <tst>:
+  f2:	0eee      	tst	r14, r14
 
-0+0f8 <tstnbz>:
-  f8:	0192      	tstnbz	r2
+0+0f4 <tstnbz>:
+  f4:	0192      	tstnbz	r2
 
-0+0fa <wait>:
-  fa:	0005      	wait
+0+0f6 <wait>:
+  f6:	0005      	wait
 
-0+0fc <xor>:
-  fc:	170f      	xor	r15, r0
+0+0f8 <xor>:
+  f8:	170f      	xor	r15, r0
 
-0+0fe <xsr>:
-  fe:	380b      	xsr	r11
+0+0fa <xsr>:
+  fa:	380b      	xsr	r11
 
-0+0100 <xtrb0>:
- 100:	0131      	xtrb0	r1, r1
+0+0fc <xtrb0>:
+  fc:	0131      	xtrb0	r1, r1
 
-0+0102 <xtrb1>:
- 102:	0122      	xtrb1	r1, r2
+0+0fe <xtrb1>:
+  fe:	0122      	xtrb1	r1, r2
 
-0+0104 <xtrb2>:
- 104:	0110      	xtrb2	r1, r0
+0+0100 <xtrb2>:
+ 100:	0110      	xtrb2	r1, r0
 
-0+0106 <xtrb3>:
- 106:	010d      	xtrb3	r1, r13
+0+0102 <xtrb3>:
+ 102:	010d      	xtrb3	r1, r13
 
-0+0108 <zextb>:
- 108:	0148      	zextb	r8
+0+0104 <zextb>:
+ 104:	0148      	zextb	r8
 
-0+010a <zexth>:
- 10a:	0164      	zexth	r4
- 10c:	0f00      	cmpne	r0, r0
- 10e:	0f00      	cmpne	r0, r0
+0+0106 <zexth>:
+ 106:	0164      	zexth	r4
+ 108:	0f00      	cmpne	r0, r0
+ 10a:	0f00      	cmpne	r0, r0
diff --git a/gas/testsuite/gas/mcore/allinsn.s b/gas/testsuite/gas/mcore/allinsn.s
index 84068404e74a..e9196e750754 100644
--- a/gas/testsuite/gas/mcore/allinsn.s
+++ b/gas/testsuite/gas/mcore/allinsn.s
@@ -13,11 +13,11 @@ footext:
 	test addc  "r1,r2"	// A double forward slash starts a line comment
 	test addi  "r3, 1"	# So does a hash
 	test addu  "r4, r5"	// White space between operands should be ignored
-	test and   "r6,r7"   ;	test andi  "r8,#2" // A semicolon seperates statements
+	test and   "r6,r7"   ;	test andi  "r8,2" // A semicolon seperates statements
 	test andn  "r9, r10"
 	test asr   "r11, R12"	// Uppercase R is allowed as a register prefix
 	test asrc  "r13"
-	test asri  "r14,#0x1f"
+	test asri  "r14,0x1f"
 	test bclri "r15,0"
 	test bf    footext
 	test bgeni "sp, 7"	// r0 can also be refered to as 'sp'
@@ -25,7 +25,7 @@ footext:
 	test BGENi "r0, 31"	// mnemonics should not be allowed, but we relax this...
 	test bgenr "r1, r2"
 	test bkpt
-	test bmaski "r3,#8"
+	test bmaski "r3,8"
 	test BMASKI "r3,0x1f"
 	test br     .  // Dot means the current address
 	test brev   r4
@@ -64,9 +64,9 @@ footext:
 	test jsr    r2
 	test jsri   footext
 	test ld.b   "r3,(r4,0)"
-	test ld.h   "r5 , ( r6, #2)"
+	test ld.h   "r5 , ( r6, 2)"
 	test ld.w   "r7, (r8, 0x4)"
-	test ldb    "r9,(r10,#0xf)"
+	test ldb    "r9,(r10,0xf)"
 	test ldh    "r11, (r12, 30)"
 	test ld     "r13, (r14, 20)"
 	test ldw    "r13, (r14, 60)"
@@ -104,7 +104,7 @@ foolit:
 	test rolc   "r6, 1"
 	test rori   "r9, 6"
 	test rotlc  "r6, 1"
-	test rotli  "r2, #10"
+	test rotli  "r2, 10"
 	test rotri  "r9, 6"
 	test rsub   "r3, r4"
 	test rsubi  "r5, 0x0"
diff --git a/gas/testsuite/gas/mep/allinsn.d b/gas/testsuite/gas/mep/allinsn.d
new file mode 100644
index 000000000000..3a1f62c30609
--- /dev/null
+++ b/gas/testsuite/gas/mep/allinsn.d
@@ -0,0 +1,1345 @@
+#as:
+#objdump: -dr
+#name: allinsn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <sb>:
+   0:	07 88       	sb \$7,\(\$8\)
+   2:	05 98       	sb \$5,\(\$9\)
+   4:	07 e8       	sb \$7,\(\$gp\)
+   6:	0e 88       	sb \$gp,\(\$8\)
+   8:	0f e8       	sb \$sp,\(\$gp\)
+
+0000000a <sh>:
+   a:	03 89       	sh \$3,\(\$8\)
+   c:	0c 19       	sh \$12,\(\$1\)
+   e:	0d 29       	sh \$tp,\(\$2\)
+  10:	02 89       	sh \$2,\(\$8\)
+  12:	0c a9       	sh \$12,\(\$10\)
+
+00000014 <sw>:
+  14:	0b 0a       	sw \$11,\(\$0\)
+  16:	03 7a       	sw \$3,\(\$7\)
+  18:	0d ea       	sw \$tp,\(\$gp\)
+  1a:	08 9a       	sw \$8,\(\$9\)
+  1c:	0e 8a       	sw \$gp,\(\$8\)
+
+0000001e <lb>:
+  1e:	0c bc       	lb \$12,\(\$11\)
+  20:	09 2c       	lb \$9,\(\$2\)
+  22:	08 bc       	lb \$8,\(\$11\)
+  24:	0e 2c       	lb \$gp,\(\$2\)
+  26:	02 cc       	lb \$2,\(\$12\)
+
+00000028 <lh>:
+  28:	0f 8d       	lh \$sp,\(\$8\)
+  2a:	03 ad       	lh \$3,\(\$10\)
+  2c:	09 fd       	lh \$9,\(\$sp\)
+  2e:	06 fd       	lh \$6,\(\$sp\)
+  30:	0f bd       	lh \$sp,\(\$11\)
+
+00000032 <lw>:
+  32:	0c ae       	lw \$12,\(\$10\)
+  34:	09 de       	lw \$9,\(\$tp\)
+  36:	0c ee       	lw \$12,\(\$gp\)
+  38:	0c be       	lw \$12,\(\$11\)
+  3a:	0d ae       	lw \$tp,\(\$10\)
+
+0000003c <lbu>:
+  3c:	0e eb       	lbu \$gp,\(\$gp\)
+  3e:	0c 8b       	lbu \$12,\(\$8\)
+  40:	0e 1b       	lbu \$gp,\(\$1\)
+  42:	08 cb       	lbu \$8,\(\$12\)
+  44:	0c 1b       	lbu \$12,\(\$1\)
+
+00000046 <lhu>:
+  46:	0f 4f       	lhu \$sp,\(\$4\)
+  48:	0e 4f       	lhu \$gp,\(\$4\)
+  4a:	05 4f       	lhu \$5,\(\$4\)
+  4c:	0f df       	lhu \$sp,\(\$tp\)
+  4e:	04 ff       	lhu \$4,\(\$sp\)
+
+00000050 <sw_sp>:
+  50:	c9 8a 00 03 	sw \$9,3\(\$8\)
+  54:	ca 5a 00 04 	sw \$10,4\(\$5\)
+  58:	c0 ea 00 03 	sw \$0,3\(\$gp\)
+  5c:	c0 8a 00 02 	sw \$0,2\(\$8\)
+  60:	cf 8a 00 01 	sw \$sp,1\(\$8\)
+
+00000064 <lw_sp>:
+  64:	cd 5e 00 01 	lw \$tp,1\(\$5\)
+  68:	cf 0e 00 01 	lw \$sp,1\(\$0\)
+  6c:	c0 ce 00 04 	lw \$0,4\(\$12\)
+  70:	cb de 00 01 	lw \$11,1\(\$tp\)
+  74:	c9 4e 00 03 	lw \$9,3\(\$4\)
+
+00000078 <sb_tp>:
+  78:	c5 18 00 01 	sb \$5,1\(\$1\)
+  7c:	ca 98 00 01 	sb \$10,1\(\$9\)
+  80:	c5 38 00 03 	sb \$5,3\(\$3\)
+  84:	c5 38 00 01 	sb \$5,1\(\$3\)
+  88:	ca 48 00 04 	sb \$10,4\(\$4\)
+
+0000008c <sh_tp>:
+  8c:	c3 09 00 01 	sh \$3,1\(\$0\)
+  90:	cd 99 00 01 	sh \$tp,1\(\$9\)
+  94:	c9 a9 00 04 	sh \$9,4\(\$10\)
+  98:	cf e9 00 03 	sh \$sp,3\(\$gp\)
+  9c:	ce 99 00 04 	sh \$gp,4\(\$9\)
+
+000000a0 <sw_tp>:
+  a0:	c6 da 00 02 	sw \$6,2\(\$tp\)
+  a4:	c6 fa 00 01 	sw \$6,1\(\$sp\)
+  a8:	c2 3a 00 02 	sw \$2,2\(\$3\)
+  ac:	c6 ca 00 02 	sw \$6,2\(\$12\)
+  b0:	c3 ba 00 01 	sw \$3,1\(\$11\)
+
+000000b4 <lb_tp>:
+  b4:	cd bc 00 04 	lb \$tp,4\(\$11\)
+  b8:	cd 8c 00 04 	lb \$tp,4\(\$8\)
+  bc:	c5 5c 00 04 	lb \$5,4\(\$5\)
+  c0:	cf ec 00 02 	lb \$sp,2\(\$gp\)
+  c4:	c3 3c 00 02 	lb \$3,2\(\$3\)
+
+000000c8 <lh_tp>:
+  c8:	c7 8d 00 02 	lh \$7,2\(\$8\)
+  cc:	c4 8d 00 03 	lh \$4,3\(\$8\)
+  d0:	ce fd 00 01 	lh \$gp,1\(\$sp\)
+  d4:	c9 0d 00 01 	lh \$9,1\(\$0\)
+  d8:	cd 0d 00 02 	lh \$tp,2\(\$0\)
+
+000000dc <lw_tp>:
+  dc:	48 07       	lw \$8,0x4\(\$sp\)
+  de:	cb 9e 00 04 	lw \$11,4\(\$9\)
+  e2:	ce 2e 00 01 	lw \$gp,1\(\$2\)
+  e6:	c9 ee 00 02 	lw \$9,2\(\$gp\)
+  ea:	c8 ce 00 01 	lw \$8,1\(\$12\)
+
+000000ee <lbu_tp>:
+  ee:	cc 9b 00 01 	lbu \$12,1\(\$9\)
+  f2:	cb 9b 00 01 	lbu \$11,1\(\$9\)
+  f6:	ce 8b 00 03 	lbu \$gp,3\(\$8\)
+  fa:	c0 fb 00 02 	lbu \$0,2\(\$sp\)
+  fe:	cd bb 00 01 	lbu \$tp,1\(\$11\)
+
+00000102 <lhu_tp>:
+ 102:	ce af 00 02 	lhu \$gp,2\(\$10\)
+ 106:	cb 8f 00 01 	lhu \$11,1\(\$8\)
+ 10a:	c1 0f 00 01 	lhu \$1,1\(\$0\)
+ 10e:	c7 ff 00 02 	lhu \$7,2\(\$sp\)
+ 112:	8b 83       	lhu \$3,0x2\(\$tp\)
+
+00000114 <sb16>:
+ 114:	c7 b8 ff ff 	sb \$7,-1\(\$11\)
+ 118:	cd e8 00 01 	sb \$tp,1\(\$gp\)
+ 11c:	c3 e8 00 01 	sb \$3,1\(\$gp\)
+ 120:	ce 68 00 02 	sb \$gp,2\(\$6\)
+ 124:	ce 78 00 01 	sb \$gp,1\(\$7\)
+
+00000128 <sh16>:
+ 128:	cc 49 ff ff 	sh \$12,-1\(\$4\)
+ 12c:	cf 19 00 01 	sh \$sp,1\(\$1\)
+ 130:	c2 c9 ff fe 	sh \$2,-2\(\$12\)
+ 134:	c9 b9 00 02 	sh \$9,2\(\$11\)
+ 138:	c9 c9 ff fe 	sh \$9,-2\(\$12\)
+
+0000013c <sw16>:
+ 13c:	cb ea ff ff 	sw \$11,-1\(\$gp\)
+ 140:	44 06       	sw \$4,0x4\(\$sp\)
+ 142:	c2 3a ff fe 	sw \$2,-2\(\$3\)
+ 146:	c6 2a ff ff 	sw \$6,-1\(\$2\)
+ 14a:	c8 da ff fe 	sw \$8,-2\(\$tp\)
+
+0000014e <lb16>:
+ 14e:	ca 2c ff fe 	lb \$10,-2\(\$2\)
+ 152:	c3 bc ff fe 	lb \$3,-2\(\$11\)
+ 156:	cc 5c 00 01 	lb \$12,1\(\$5\)
+ 15a:	c5 5c 00 01 	lb \$5,1\(\$5\)
+ 15e:	cb dc 00 02 	lb \$11,2\(\$tp\)
+
+00000162 <lh16>:
+ 162:	cf bd ff ff 	lh \$sp,-1\(\$11\)
+ 166:	cd bd ff fe 	lh \$tp,-2\(\$11\)
+ 16a:	c2 ad 00 01 	lh \$2,1\(\$10\)
+ 16e:	c8 7d ff ff 	lh \$8,-1\(\$7\)
+ 172:	ce bd ff ff 	lh \$gp,-1\(\$11\)
+
+00000176 <lw16>:
+ 176:	c0 5e ff ff 	lw \$0,-1\(\$5\)
+ 17a:	cc 7e ff fe 	lw \$12,-2\(\$7\)
+ 17e:	c1 3e ff fe 	lw \$1,-2\(\$3\)
+ 182:	c1 7e 00 02 	lw \$1,2\(\$7\)
+ 186:	c4 8e 00 01 	lw \$4,1\(\$8\)
+
+0000018a <lbu16>:
+ 18a:	cc 4b ff ff 	lbu \$12,-1\(\$4\)
+ 18e:	ce bb 00 01 	lbu \$gp,1\(\$11\)
+ 192:	c1 db ff ff 	lbu \$1,-1\(\$tp\)
+ 196:	c9 db ff ff 	lbu \$9,-1\(\$tp\)
+ 19a:	c8 fb 00 01 	lbu \$8,1\(\$sp\)
+
+0000019e <lhu16>:
+ 19e:	cd ff ff ff 	lhu \$tp,-1\(\$sp\)
+ 1a2:	ce 8f 00 02 	lhu \$gp,2\(\$8\)
+ 1a6:	cf cf ff ff 	lhu \$sp,-1\(\$12\)
+ 1aa:	c3 0f ff ff 	lhu \$3,-1\(\$0\)
+ 1ae:	c3 cf ff fe 	lhu \$3,-2\(\$12\)
+
+000001b2 <sw24>:
+ 1b2:	eb 06 00 00 	sw \$11,\(0x4\)
+ 1b6:	ef 06 00 00 	sw \$sp,\(0x4\)
+ 1ba:	e7 0a 00 00 	sw \$7,\(0x8\)
+ 1be:	ea 12 00 00 	sw \$10,\(0x10\)
+ 1c2:	e8 a2 00 00 	sw \$8,\(0xa0\)
+
+000001c6 <lw24>:
+ 1c6:	e4 07 00 00 	lw \$4,\(0x4\)
+ 1ca:	ef 07 00 00 	lw \$sp,\(0x4\)
+ 1ce:	e4 13 00 00 	lw \$4,\(0x10\)
+ 1d2:	e8 03 00 00 	lw \$8,\(0x0\)
+ 1d6:	ed 0b 00 00 	lw \$tp,\(0x8\)
+
+000001da <extb>:
+ 1da:	1d 0d       	extb \$tp
+ 1dc:	1d 0d       	extb \$tp
+ 1de:	16 0d       	extb \$6
+ 1e0:	1e 0d       	extb \$gp
+ 1e2:	1a 0d       	extb \$10
+
+000001e4 <exth>:
+ 1e4:	1f 2d       	exth \$sp
+ 1e6:	12 2d       	exth \$2
+ 1e8:	15 2d       	exth \$5
+ 1ea:	1a 2d       	exth \$10
+ 1ec:	14 2d       	exth \$4
+
+000001ee <extub>:
+ 1ee:	12 8d       	extub \$2
+ 1f0:	1d 8d       	extub \$tp
+ 1f2:	13 8d       	extub \$3
+ 1f4:	19 8d       	extub \$9
+ 1f6:	1e 8d       	extub \$gp
+
+000001f8 <extuh>:
+ 1f8:	18 ad       	extuh \$8
+ 1fa:	18 ad       	extuh \$8
+ 1fc:	14 ad       	extuh \$4
+ 1fe:	10 ad       	extuh \$0
+ 200:	10 ad       	extuh \$0
+
+00000202 <ssarb>:
+ 202:	12 8c       	ssarb 2\(\$8\)
+ 204:	12 dc       	ssarb 2\(\$tp\)
+ 206:	11 dc       	ssarb 1\(\$tp\)
+ 208:	12 5c       	ssarb 2\(\$5\)
+ 20a:	10 9c       	ssarb 0\(\$9\)
+
+0000020c <mov>:
+ 20c:	02 30       	mov \$2,\$3
+ 20e:	03 b0       	mov \$3,\$11
+ 210:	0f a0       	mov \$sp,\$10
+ 212:	0f 00       	mov \$sp,\$0
+ 214:	03 d0       	mov \$3,\$tp
+
+00000216 <movi8>:
+ 216:	5b ff       	mov \$11,-1
+ 218:	56 02       	mov \$6,2
+ 21a:	5f ff       	mov \$sp,-1
+ 21c:	5f 01       	mov \$sp,1
+ 21e:	5e ff       	mov \$gp,-1
+
+00000220 <movi16>:
+ 220:	5f 00       	mov \$sp,0
+ 222:	50 02       	mov \$0,2
+ 224:	58 ff       	mov \$8,-1
+ 226:	5c 01       	mov \$12,1
+ 228:	57 ff       	mov \$7,-1
+
+0000022a <movu24>:
+ 22a:	d2 01 00 00 	movu \$2,0x1
+ 22e:	ca 11 00 04 	movu \$10,0x4
+ 232:	c9 11 00 00 	movu \$9,0x0
+ 236:	d4 03 00 00 	movu \$4,0x3
+ 23a:	ce 11 00 01 	movu \$gp,0x1
+
+0000023e <movu16>:
+ 23e:	cf 11 00 01 	movu \$sp,0x1
+ 242:	d6 03 00 00 	movu \$6,0x3
+ 246:	d0 03 00 00 	movu \$0,0x3
+ 24a:	ce 11 00 03 	movu \$gp,0x3
+ 24e:	ca 11 00 02 	movu \$10,0x2
+
+00000252 <movh>:
+ 252:	c8 21 00 02 	movh \$8,0x2
+ 256:	cd 21 00 01 	movh \$tp,0x1
+ 25a:	ce 21 00 02 	movh \$gp,0x2
+ 25e:	cc 21 00 00 	movh \$12,0x0
+ 262:	cb 21 00 02 	movh \$11,0x2
+
+00000266 <add3>:
+ 266:	9b 36       	add3 \$6,\$11,\$3
+ 268:	9d 5e       	add3 \$gp,\$tp,\$5
+ 26a:	9b 73       	add3 \$3,\$11,\$7
+ 26c:	9e dd       	add3 \$tp,\$gp,\$tp
+ 26e:	9e 80       	add3 \$0,\$gp,\$8
+
+00000270 <add>:
+ 270:	6c 08       	add \$12,2
+ 272:	6c fc       	add \$12,-1
+ 274:	64 04       	add \$4,1
+ 276:	66 04       	add \$6,1
+ 278:	66 08       	add \$6,2
+
+0000027a <add3i>:
+ 27a:	4b 04       	add3 \$11,\$sp,0x4
+ 27c:	c4 f0 00 01 	add3 \$4,\$sp,1
+ 280:	40 00       	add3 \$0,\$sp,0x0
+ 282:	cd f0 00 03 	add3 \$tp,\$sp,3
+ 286:	4b 00       	add3 \$11,\$sp,0x0
+
+00000288 <advck3>:
+ 288:	0e a7       	advck3 \$0,\$gp,\$10
+ 28a:	0d 07       	advck3 \$0,\$tp,\$0
+ 28c:	0e d7       	advck3 \$0,\$gp,\$tp
+ 28e:	07 87       	advck3 \$0,\$7,\$8
+ 290:	01 27       	advck3 \$0,\$1,\$2
+
+00000292 <sub>:
+ 292:	08 e4       	sub \$8,\$gp
+ 294:	01 94       	sub \$1,\$9
+ 296:	0d 74       	sub \$tp,\$7
+ 298:	0f 34       	sub \$sp,\$3
+ 29a:	02 74       	sub \$2,\$7
+
+0000029c <sbvck3>:
+ 29c:	03 e5       	sbvck3 \$0,\$3,\$gp
+ 29e:	03 75       	sbvck3 \$0,\$3,\$7
+ 2a0:	0a a5       	sbvck3 \$0,\$10,\$10
+ 2a2:	04 d5       	sbvck3 \$0,\$4,\$tp
+ 2a4:	0a f5       	sbvck3 \$0,\$10,\$sp
+
+000002a6 <neg>:
+ 2a6:	0e 71       	neg \$gp,\$7
+ 2a8:	01 71       	neg \$1,\$7
+ 2aa:	02 b1       	neg \$2,\$11
+ 2ac:	0d 81       	neg \$tp,\$8
+ 2ae:	0e d1       	neg \$gp,\$tp
+
+000002b0 <slt3>:
+ 2b0:	0e 82       	slt3 \$0,\$gp,\$8
+ 2b2:	04 d2       	slt3 \$0,\$4,\$tp
+ 2b4:	0a e2       	slt3 \$0,\$10,\$gp
+ 2b6:	0e 52       	slt3 \$0,\$gp,\$5
+ 2b8:	03 c2       	slt3 \$0,\$3,\$12
+
+000002ba <sltu3>:
+ 2ba:	02 83       	sltu3 \$0,\$2,\$8
+ 2bc:	0e b3       	sltu3 \$0,\$gp,\$11
+ 2be:	02 d3       	sltu3 \$0,\$2,\$tp
+ 2c0:	09 83       	sltu3 \$0,\$9,\$8
+ 2c2:	06 93       	sltu3 \$0,\$6,\$9
+
+000002c4 <slt3i>:
+ 2c4:	66 11       	slt3 \$0,\$6,0x2
+ 2c6:	6b 09       	slt3 \$0,\$11,0x1
+ 2c8:	6f 01       	slt3 \$0,\$sp,0x0
+ 2ca:	63 01       	slt3 \$0,\$3,0x0
+ 2cc:	6d 01       	slt3 \$0,\$tp,0x0
+
+000002ce <sltu3i>:
+ 2ce:	6e 25       	sltu3 \$0,\$gp,0x4
+ 2d0:	6d 1d       	sltu3 \$0,\$tp,0x3
+ 2d2:	63 0d       	sltu3 \$0,\$3,0x1
+ 2d4:	6c 05       	sltu3 \$0,\$12,0x0
+ 2d6:	61 1d       	sltu3 \$0,\$1,0x3
+
+000002d8 <sl1ad3>:
+ 2d8:	28 e6       	sl1ad3 \$0,\$8,\$gp
+ 2da:	24 26       	sl1ad3 \$0,\$4,\$2
+ 2dc:	2f c6       	sl1ad3 \$0,\$sp,\$12
+ 2de:	29 16       	sl1ad3 \$0,\$9,\$1
+ 2e0:	28 26       	sl1ad3 \$0,\$8,\$2
+
+000002e2 <sl2ad3>:
+ 2e2:	28 d7       	sl2ad3 \$0,\$8,\$tp
+ 2e4:	22 37       	sl2ad3 \$0,\$2,\$3
+ 2e6:	28 97       	sl2ad3 \$0,\$8,\$9
+ 2e8:	27 c7       	sl2ad3 \$0,\$7,\$12
+ 2ea:	24 c7       	sl2ad3 \$0,\$4,\$12
+
+000002ec <add3x>:
+ 2ec:	cd b0 00 01 	add3 \$tp,\$11,1
+ 2f0:	cd 40 ff ff 	add3 \$tp,\$4,-1
+ 2f4:	c2 d0 00 01 	add3 \$2,\$tp,1
+ 2f8:	c3 e0 00 01 	add3 \$3,\$gp,1
+ 2fc:	ca f0 00 02 	add3 \$10,\$sp,2
+
+00000300 <slt3x>:
+ 300:	c8 12 ff ff 	slt3 \$8,\$1,-1
+ 304:	c0 32 ff fe 	slt3 \$0,\$3,-2
+ 308:	c9 f2 ff ff 	slt3 \$9,\$sp,-1
+ 30c:	c3 82 00 02 	slt3 \$3,\$8,2
+ 310:	cd e2 00 00 	slt3 \$tp,\$gp,0
+
+00000314 <sltu3x>:
+ 314:	cf b3 00 02 	sltu3 \$sp,\$11,0x2
+ 318:	c6 03 00 01 	sltu3 \$6,\$0,0x1
+ 31c:	c9 b3 00 03 	sltu3 \$9,\$11,0x3
+ 320:	64 05       	sltu3 \$0,\$4,0x0
+ 322:	cd e3 00 04 	sltu3 \$tp,\$gp,0x4
+
+00000326 <or>:
+ 326:	1f e0       	or \$sp,\$gp
+ 328:	18 30       	or \$8,\$3
+ 32a:	10 f0       	or \$0,\$sp
+ 32c:	1d 00       	or \$tp,\$0
+ 32e:	18 60       	or \$8,\$6
+
+00000330 <and>:
+ 330:	1f f1       	and \$sp,\$sp
+ 332:	16 e1       	and \$6,\$gp
+ 334:	14 21       	and \$4,\$2
+ 336:	15 81       	and \$5,\$8
+ 338:	17 e1       	and \$7,\$gp
+
+0000033a <xor>:
+ 33a:	11 c2       	xor \$1,\$12
+ 33c:	1c d2       	xor \$12,\$tp
+ 33e:	1a 82       	xor \$10,\$8
+ 340:	1f b2       	xor \$sp,\$11
+ 342:	1c 82       	xor \$12,\$8
+
+00000344 <nor>:
+ 344:	19 53       	nor \$9,\$5
+ 346:	18 23       	nor \$8,\$2
+ 348:	1f 93       	nor \$sp,\$9
+ 34a:	15 f3       	nor \$5,\$sp
+ 34c:	1f e3       	nor \$sp,\$gp
+
+0000034e <or3>:
+ 34e:	cd f4 00 02 	or3 \$tp,\$sp,0x2
+ 352:	cf d4 00 03 	or3 \$sp,\$tp,0x3
+ 356:	c0 a4 00 04 	or3 \$0,\$10,0x4
+ 35a:	c9 f4 00 03 	or3 \$9,\$sp,0x3
+ 35e:	c9 f4 00 00 	or3 \$9,\$sp,0x0
+
+00000362 <and3>:
+ 362:	c5 85 00 01 	and3 \$5,\$8,0x1
+ 366:	cb e5 00 03 	and3 \$11,\$gp,0x3
+ 36a:	c6 05 00 00 	and3 \$6,\$0,0x0
+ 36e:	cf f5 00 00 	and3 \$sp,\$sp,0x0
+ 372:	c1 a5 00 03 	and3 \$1,\$10,0x3
+
+00000376 <xor3>:
+ 376:	c0 06 00 02 	xor3 \$0,\$0,0x2
+ 37a:	cf 66 00 00 	xor3 \$sp,\$6,0x0
+ 37e:	cd 56 00 00 	xor3 \$tp,\$5,0x0
+ 382:	cf 76 00 00 	xor3 \$sp,\$7,0x0
+ 386:	cf f6 00 02 	xor3 \$sp,\$sp,0x2
+
+0000038a <sra>:
+ 38a:	24 1d       	sra \$4,\$1
+ 38c:	28 fd       	sra \$8,\$sp
+ 38e:	21 1d       	sra \$1,\$1
+ 390:	20 5d       	sra \$0,\$5
+ 392:	29 1d       	sra \$9,\$1
+
+00000394 <srl>:
+ 394:	22 bc       	srl \$2,\$11
+ 396:	2f 7c       	srl \$sp,\$7
+ 398:	21 7c       	srl \$1,\$7
+ 39a:	23 dc       	srl \$3,\$tp
+ 39c:	2e 1c       	srl \$gp,\$1
+
+0000039e <sll>:
+ 39e:	2b 0e       	sll \$11,\$0
+ 3a0:	2d 8e       	sll \$tp,\$8
+ 3a2:	28 9e       	sll \$8,\$9
+ 3a4:	2d fe       	sll \$tp,\$sp
+ 3a6:	2f fe       	sll \$sp,\$sp
+
+000003a8 <srai>:
+ 3a8:	61 13       	sra \$1,0x2
+ 3aa:	6f 1b       	sra \$sp,0x3
+ 3ac:	6f 1b       	sra \$sp,0x3
+ 3ae:	66 23       	sra \$6,0x4
+ 3b0:	6f 1b       	sra \$sp,0x3
+
+000003b2 <srli>:
+ 3b2:	6a 02       	srl \$10,0x0
+ 3b4:	69 1a       	srl \$9,0x3
+ 3b6:	66 22       	srl \$6,0x4
+ 3b8:	6a 12       	srl \$10,0x2
+ 3ba:	68 1a       	srl \$8,0x3
+
+000003bc <slli>:
+ 3bc:	60 06       	sll \$0,0x0
+ 3be:	64 06       	sll \$4,0x0
+ 3c0:	6d 16       	sll \$tp,0x2
+ 3c2:	6b 16       	sll \$11,0x2
+ 3c4:	66 06       	sll \$6,0x0
+
+000003c6 <sll3>:
+ 3c6:	6d 27       	sll3 \$0,\$tp,0x4
+ 3c8:	6e 07       	sll3 \$0,\$gp,0x0
+ 3ca:	68 17       	sll3 \$0,\$8,0x2
+ 3cc:	63 17       	sll3 \$0,\$3,0x2
+ 3ce:	68 07       	sll3 \$0,\$8,0x0
+
+000003d0 <fsft>:
+ 3d0:	2e af       	fsft \$gp,\$10
+ 3d2:	2e 9f       	fsft \$gp,\$9
+ 3d4:	2f df       	fsft \$sp,\$tp
+ 3d6:	2b 3f       	fsft \$11,\$3
+ 3d8:	25 3f       	fsft \$5,\$3
+
+000003da <bra>:
+ 3da:	b0 02       	bra 3dc <bra\+0x2>
+ 3dc:	bf fe       	bra 3da <bra>
+ 3de:	b0 02       	bra 3e0 <bra\+0x6>
+ 3e0:	b0 00       	bra 3e0 <bra\+0x6>
+ 3e2:	b0 02       	bra 3e4 <beqz>
+
+000003e4 <beqz>:
+ 3e4:	a1 fe       	beqz \$1,3e2 <bra\+0x8>
+ 3e6:	af 02       	beqz \$sp,3e8 <beqz\+0x4>
+ 3e8:	a4 04       	beqz \$4,3ec <beqz\+0x8>
+ 3ea:	a4 00       	beqz \$4,3ea <beqz\+0x6>
+ 3ec:	a9 fe       	beqz \$9,3ea <beqz\+0x6>
+
+000003ee <bnez>:
+ 3ee:	a8 03       	bnez \$8,3f0 <bnez\+0x2>
+ 3f0:	ad 03       	bnez \$tp,3f2 <bnez\+0x4>
+ 3f2:	ae 01       	bnez \$gp,3f2 <bnez\+0x4>
+ 3f4:	a6 03       	bnez \$6,3f6 <bnez\+0x8>
+ 3f6:	a8 fd       	bnez \$8,3f2 <bnez\+0x4>
+
+000003f8 <beqi>:
+ 3f8:	ed 30 00 00 	beqi \$tp,0x3,3f8 <beqi>
+ 3fc:	e0 40 ff ff 	beqi \$0,0x4,3fa <beqi\+0x2>
+ 400:	ef 40 ff ff 	beqi \$sp,0x4,3fe <beqi\+0x6>
+ 404:	ed 20 00 00 	beqi \$tp,0x2,404 <beqi\+0xc>
+ 408:	e4 20 ff fc 	beqi \$4,0x2,400 <beqi\+0x8>
+
+0000040c <bnei>:
+ 40c:	e8 14 00 00 	bnei \$8,0x1,40c <bnei>
+ 410:	e5 14 00 01 	bnei \$5,0x1,412 <bnei\+0x6>
+ 414:	e5 04 00 04 	bnei \$5,0x0,41c <bnei\+0x10>
+ 418:	e9 44 ff ff 	bnei \$9,0x4,416 <bnei\+0xa>
+ 41c:	e0 44 ff fc 	bnei \$0,0x4,414 <bnei\+0x8>
+
+00000420 <blti>:
+ 420:	e7 3c 00 00 	blti \$7,0x3,420 <blti>
+ 424:	e1 1c 00 00 	blti \$1,0x1,424 <blti\+0x4>
+ 428:	e8 2c 00 01 	blti \$8,0x2,42a <blti\+0xa>
+ 42c:	eb 2c 00 01 	blti \$11,0x2,42e <blti\+0xe>
+ 430:	ef 3c ff ff 	blti \$sp,0x3,42e <blti\+0xe>
+
+00000434 <bgei>:
+ 434:	e4 38 ff fc 	bgei \$4,0x3,42c <blti\+0xc>
+ 438:	e7 08 00 01 	bgei \$7,0x0,43a <bgei\+0x6>
+ 43c:	ed 18 00 00 	bgei \$tp,0x1,43c <bgei\+0x8>
+ 440:	e5 28 ff ff 	bgei \$5,0x2,43e <bgei\+0xa>
+ 444:	ec 48 ff fc 	bgei \$12,0x4,43c <bgei\+0x8>
+
+00000448 <beq>:
+ 448:	e7 21 ff ff 	beq \$7,\$2,446 <bgei\+0x12>
+ 44c:	e1 31 ff fc 	beq \$1,\$3,444 <bgei\+0x10>
+ 450:	e2 01 00 01 	beq \$2,\$0,452 <beq\+0xa>
+ 454:	ef 81 00 01 	beq \$sp,\$8,456 <beq\+0xe>
+ 458:	e3 01 00 00 	beq \$3,\$0,458 <beq\+0x10>
+
+0000045c <bne>:
+ 45c:	e6 35 00 00 	bne \$6,\$3,45c <bne>
+ 460:	ef 35 ff fc 	bne \$sp,\$3,458 <beq\+0x10>
+ 464:	e8 05 00 01 	bne \$8,\$0,466 <bne\+0xa>
+ 468:	ee f5 00 04 	bne \$gp,\$sp,470 <bsr12>
+ 46c:	ef 45 00 01 	bne \$sp,\$4,46e <bne\+0x12>
+
+00000470 <bsr12>:
+ 470:	b0 03       	bsr 472 <bsr12\+0x2>
+ 472:	bf f9       	bsr 46a <bne\+0xe>
+ 474:	bf f1       	bsr 464 <bne\+0x8>
+ 476:	bf ff       	bsr 474 <bsr12\+0x4>
+ 478:	bf f9       	bsr 470 <bsr12>
+
+0000047a <bsr24>:
+ 47a:	b0 05       	bsr 47e <bsr24\+0x4>
+ 47c:	bf ff       	bsr 47a <bsr24>
+ 47e:	bf fd       	bsr 47a <bsr24>
+ 480:	b0 01       	bsr 480 <bsr24\+0x6>
+ 482:	b0 03       	bsr 484 <jmp>
+
+00000484 <jmp>:
+ 484:	10 2e       	jmp \$2
+ 486:	10 de       	jmp \$tp
+ 488:	10 5e       	jmp \$5
+ 48a:	10 fe       	jmp \$sp
+ 48c:	10 8e       	jmp \$8
+
+0000048e <jmp24>:
+ 48e:	d8 28 00 00 	jmp 4 <sb\+0x4>
+ 492:	d8 18 00 00 	jmp 2 <sb\+0x2>
+ 496:	d8 08 00 00 	jmp 0 <sb>
+ 49a:	d8 18 00 00 	jmp 2 <sb\+0x2>
+ 49e:	d8 28 00 00 	jmp 4 <sb\+0x4>
+
+000004a2 <jsr>:
+ 4a2:	10 ff       	jsr \$sp
+ 4a4:	10 df       	jsr \$tp
+ 4a6:	10 df       	jsr \$tp
+ 4a8:	10 6f       	jsr \$6
+ 4aa:	10 6f       	jsr \$6
+
+000004ac <ret>:
+ 4ac:	70 02       	ret
+
+000004ae <repeat>:
+ 4ae:	e4 09 00 01 	repeat \$4,4b0 <repeat\+0x2>
+ 4b2:	e8 09 00 02 	repeat \$8,4b6 <repeat\+0x8>
+ 4b6:	e0 09 00 04 	repeat \$0,4be <repeat\+0x10>
+ 4ba:	e6 09 00 01 	repeat \$6,4bc <repeat\+0xe>
+ 4be:	e4 09 00 01 	repeat \$4,4c0 <repeat\+0x12>
+
+000004c2 <erepeat>:
+ 4c2:	e0 19 00 01 	erepeat 4c4 <erepeat\+0x2>
+ 4c6:	e0 19 00 00 	erepeat 4c6 <erepeat\+0x4>
+ 4ca:	e0 19 00 01 	erepeat 4cc <erepeat\+0xa>
+ 4ce:	e0 19 ff ff 	erepeat 4cc <erepeat\+0xa>
+ 4d2:	e0 19 00 00 	erepeat 4d2 <erepeat\+0x10>
+
+000004d6 <stc>:
+ 4d6:	7d e8       	stc \$tp,\$mb1
+ 4d8:	7d c9       	stc \$tp,\$ccfg
+ 4da:	7b 89       	stc \$11,\$dbg
+ 4dc:	7a c9       	stc \$10,\$ccfg
+ 4de:	79 39       	stc \$9,\$epc
+
+000004e0 <ldc>:
+ 4e0:	7d 8a       	ldc \$tp,\$lo
+ 4e2:	78 7b       	ldc \$8,\$npc
+ 4e4:	79 ca       	ldc \$9,\$mb0
+ 4e6:	7f 2a       	ldc \$sp,\$sar
+ 4e8:	79 cb       	ldc \$9,\$ccfg
+
+000004ea <di>:
+ 4ea:	70 00       	di
+
+000004ec <ei>:
+ 4ec:	70 10       	ei
+
+000004ee <reti>:
+ 4ee:	70 12       	reti
+
+000004f0 <halt>:
+ 4f0:	70 22       	halt
+
+000004f2 <swi>:
+ 4f2:	70 26       	swi 0x2
+ 4f4:	70 06       	swi 0x0
+ 4f6:	70 26       	swi 0x2
+ 4f8:	70 36       	swi 0x3
+ 4fa:	70 16       	swi 0x1
+
+000004fc <break>:
+ 4fc:	70 32       	break
+
+000004fe <syncm>:
+ 4fe:	70 11       	syncm
+
+00000500 <stcb>:
+ 500:	f5 04 00 04 	stcb \$5,0x4
+ 504:	f5 04 00 01 	stcb \$5,0x1
+ 508:	fe 04 00 00 	stcb \$gp,0x0
+ 50c:	ff 04 00 04 	stcb \$sp,0x4
+ 510:	fb 04 00 02 	stcb \$11,0x2
+
+00000514 <ldcb>:
+ 514:	f2 14 00 03 	ldcb \$2,0x3
+ 518:	f2 14 00 04 	ldcb \$2,0x4
+ 51c:	f9 14 00 01 	ldcb \$9,0x1
+ 520:	fa 14 00 04 	ldcb \$10,0x4
+ 524:	f1 14 00 04 	ldcb \$1,0x4
+
+00000528 <bsetm>:
+ 528:	20 a0       	bsetm \(\$10\),0x0
+ 52a:	20 f0       	bsetm \(\$sp\),0x0
+ 52c:	22 10       	bsetm \(\$1\),0x2
+ 52e:	24 f0       	bsetm \(\$sp\),0x4
+ 530:	24 80       	bsetm \(\$8\),0x4
+
+00000532 <bclrm>:
+ 532:	20 51       	bclrm \(\$5\),0x0
+ 534:	22 51       	bclrm \(\$5\),0x2
+ 536:	20 81       	bclrm \(\$8\),0x0
+ 538:	22 91       	bclrm \(\$9\),0x2
+ 53a:	23 51       	bclrm \(\$5\),0x3
+
+0000053c <bnotm>:
+ 53c:	24 e2       	bnotm \(\$gp\),0x4
+ 53e:	24 b2       	bnotm \(\$11\),0x4
+ 540:	20 a2       	bnotm \(\$10\),0x0
+ 542:	24 d2       	bnotm \(\$tp\),0x4
+ 544:	20 82       	bnotm \(\$8\),0x0
+
+00000546 <btstm>:
+ 546:	20 e3       	btstm \$0,\(\$gp\),0x0
+ 548:	21 e3       	btstm \$0,\(\$gp\),0x1
+ 54a:	20 b3       	btstm \$0,\(\$11\),0x0
+ 54c:	23 e3       	btstm \$0,\(\$gp\),0x3
+ 54e:	22 83       	btstm \$0,\(\$8\),0x2
+
+00000550 <tas>:
+ 550:	27 d4       	tas \$7,\(\$tp\)
+ 552:	27 c4       	tas \$7,\(\$12\)
+ 554:	23 84       	tas \$3,\(\$8\)
+ 556:	22 54       	tas \$2,\(\$5\)
+ 558:	26 a4       	tas \$6,\(\$10\)
+
+0000055a <cache>:
+ 55a:	71 d4       	cache 0x1,\(\$tp\)
+ 55c:	73 c4       	cache 0x3,\(\$12\)
+ 55e:	73 94       	cache 0x3,\(\$9\)
+ 560:	74 24       	cache 0x4,\(\$2\)
+ 562:	74 74       	cache 0x4,\(\$7\)
+
+00000564 <mul>:
+ 564:	18 e4       	mul \$8,\$gp
+ 566:	12 94       	mul \$2,\$9
+ 568:	1e f4       	mul \$gp,\$sp
+ 56a:	19 74       	mul \$9,\$7
+ 56c:	17 b4       	mul \$7,\$11
+
+0000056e <mulu>:
+ 56e:	12 55       	mulu \$2,\$5
+ 570:	16 e5       	mulu \$6,\$gp
+ 572:	1e f5       	mulu \$gp,\$sp
+ 574:	1b e5       	mulu \$11,\$gp
+ 576:	13 95       	mulu \$3,\$9
+
+00000578 <mulr>:
+ 578:	1c 66       	mulr \$12,\$6
+ 57a:	1d 86       	mulr \$tp,\$8
+ 57c:	17 a6       	mulr \$7,\$10
+ 57e:	1e 16       	mulr \$gp,\$1
+ 580:	10 f6       	mulr \$0,\$sp
+
+00000582 <mulru>:
+ 582:	14 27       	mulru \$4,\$2
+ 584:	1e 17       	mulru \$gp,\$1
+ 586:	1f 47       	mulru \$sp,\$4
+ 588:	1a 67       	mulru \$10,\$6
+ 58a:	10 e7       	mulru \$0,\$gp
+
+0000058c <madd>:
+ 58c:	f4 b1 30 04 	madd \$4,\$11
+ 590:	ff e1 30 04 	madd \$sp,\$gp
+ 594:	fe f1 30 04 	madd \$gp,\$sp
+ 598:	f4 d1 30 04 	madd \$4,\$tp
+ 59c:	f1 e1 30 04 	madd \$1,\$gp
+
+000005a0 <maddu>:
+ 5a0:	f0 11 30 05 	maddu \$0,\$1
+ 5a4:	f7 61 30 05 	maddu \$7,\$6
+ 5a8:	f9 51 30 05 	maddu \$9,\$5
+ 5ac:	fe f1 30 05 	maddu \$gp,\$sp
+ 5b0:	f7 d1 30 05 	maddu \$7,\$tp
+
+000005b4 <maddr>:
+ 5b4:	f6 81 30 06 	maddr \$6,\$8
+ 5b8:	f9 e1 30 06 	maddr \$9,\$gp
+ 5bc:	f8 e1 30 06 	maddr \$8,\$gp
+ 5c0:	f3 21 30 06 	maddr \$3,\$2
+ 5c4:	f1 b1 30 06 	maddr \$1,\$11
+
+000005c8 <maddru>:
+ 5c8:	fa 31 30 07 	maddru \$10,\$3
+ 5cc:	ff c1 30 07 	maddru \$sp,\$12
+ 5d0:	f8 81 30 07 	maddru \$8,\$8
+ 5d4:	fe 31 30 07 	maddru \$gp,\$3
+ 5d8:	f8 f1 30 07 	maddru \$8,\$sp
+
+000005dc <div>:
+ 5dc:	19 38       	div \$9,\$3
+ 5de:	14 e8       	div \$4,\$gp
+ 5e0:	12 c8       	div \$2,\$12
+ 5e2:	18 d8       	div \$8,\$tp
+ 5e4:	1d 68       	div \$tp,\$6
+
+000005e6 <divu>:
+ 5e6:	19 59       	divu \$9,\$5
+ 5e8:	18 d9       	divu \$8,\$tp
+ 5ea:	10 e9       	divu \$0,\$gp
+ 5ec:	19 59       	divu \$9,\$5
+ 5ee:	10 59       	divu \$0,\$5
+
+000005f0 <dret>:
+ 5f0:	70 13       	dret
+
+000005f2 <dbreak>:
+ 5f2:	70 33       	dbreak
+
+000005f4 <ldz>:
+ 5f4:	fe 41 00 00 	ldz \$gp,\$4
+ 5f8:	fa b1 00 00 	ldz \$10,\$11
+ 5fc:	f9 91 00 00 	ldz \$9,\$9
+ 600:	ff d1 00 00 	ldz \$sp,\$tp
+ 604:	fe 31 00 00 	ldz \$gp,\$3
+
+00000608 <abs>:
+ 608:	ff 91 00 03 	abs \$sp,\$9
+ 60c:	f5 41 00 03 	abs \$5,\$4
+ 610:	fd d1 00 03 	abs \$tp,\$tp
+ 614:	f0 31 00 03 	abs \$0,\$3
+ 618:	f3 e1 00 03 	abs \$3,\$gp
+
+0000061c <ave>:
+ 61c:	fb a1 00 02 	ave \$11,\$10
+ 620:	f8 a1 00 02 	ave \$8,\$10
+ 624:	fe 21 00 02 	ave \$gp,\$2
+ 628:	fa c1 00 02 	ave \$10,\$12
+ 62c:	ff 81 00 02 	ave \$sp,\$8
+
+00000630 <min>:
+ 630:	f8 31 00 04 	min \$8,\$3
+ 634:	f7 01 00 04 	min \$7,\$0
+ 638:	f2 21 00 04 	min \$2,\$2
+ 63c:	f5 61 00 04 	min \$5,\$6
+ 640:	fb 51 00 04 	min \$11,\$5
+
+00000644 <max>:
+ 644:	fb f1 00 05 	max \$11,\$sp
+ 648:	fe 01 00 05 	max \$gp,\$0
+ 64c:	fc f1 00 05 	max \$12,\$sp
+ 650:	fe 21 00 05 	max \$gp,\$2
+ 654:	fe f1 00 05 	max \$gp,\$sp
+
+00000658 <minu>:
+ 658:	fb 81 00 06 	minu \$11,\$8
+ 65c:	f7 51 00 06 	minu \$7,\$5
+ 660:	f8 e1 00 06 	minu \$8,\$gp
+ 664:	fb 41 00 06 	minu \$11,\$4
+ 668:	f2 f1 00 06 	minu \$2,\$sp
+
+0000066c <maxu>:
+ 66c:	f3 31 00 07 	maxu \$3,\$3
+ 670:	fd 01 00 07 	maxu \$tp,\$0
+ 674:	f4 81 00 07 	maxu \$4,\$8
+ 678:	fe 21 00 07 	maxu \$gp,\$2
+ 67c:	fc 81 00 07 	maxu \$12,\$8
+
+00000680 <clip>:
+ 680:	fa 01 10 08 	clip \$10,0x1
+ 684:	ff 01 10 20 	clip \$sp,0x4
+ 688:	f4 01 10 18 	clip \$4,0x3
+ 68c:	ff 01 10 18 	clip \$sp,0x3
+ 690:	f1 01 10 00 	clip \$1,0x0
+
+00000694 <clipu>:
+ 694:	fa 01 10 21 	clipu \$10,0x4
+ 698:	fd 01 10 09 	clipu \$tp,0x1
+ 69c:	f5 01 10 21 	clipu \$5,0x4
+ 6a0:	fe 01 10 01 	clipu \$gp,0x0
+ 6a4:	f5 01 10 09 	clipu \$5,0x1
+
+000006a8 <sadd>:
+ 6a8:	f5 01 00 08 	sadd \$5,\$0
+ 6ac:	ff 31 00 08 	sadd \$sp,\$3
+ 6b0:	f0 a1 00 08 	sadd \$0,\$10
+ 6b4:	ff c1 00 08 	sadd \$sp,\$12
+ 6b8:	f4 21 00 08 	sadd \$4,\$2
+
+000006bc <ssub>:
+ 6bc:	f1 a1 00 0a 	ssub \$1,\$10
+ 6c0:	f4 71 00 0a 	ssub \$4,\$7
+ 6c4:	f8 31 00 0a 	ssub \$8,\$3
+ 6c8:	f7 e1 00 0a 	ssub \$7,\$gp
+ 6cc:	fd 41 00 0a 	ssub \$tp,\$4
+
+000006d0 <saddu>:
+ 6d0:	f9 e1 00 09 	saddu \$9,\$gp
+ 6d4:	f0 a1 00 09 	saddu \$0,\$10
+ 6d8:	f7 c1 00 09 	saddu \$7,\$12
+ 6dc:	f5 f1 00 09 	saddu \$5,\$sp
+ 6e0:	fd 31 00 09 	saddu \$tp,\$3
+
+000006e4 <ssubu>:
+ 6e4:	ff e1 00 0b 	ssubu \$sp,\$gp
+ 6e8:	f0 f1 00 0b 	ssubu \$0,\$sp
+ 6ec:	f3 a1 00 0b 	ssubu \$3,\$10
+ 6f0:	ff d1 00 0b 	ssubu \$sp,\$tp
+ 6f4:	f2 91 00 0b 	ssubu \$2,\$9
+
+000006f8 <swcp>:
+ 6f8:	33 d8       	swcp \$c3,\(\$tp\)
+ 6fa:	3f d8       	swcp \$c15,\(\$tp\)
+ 6fc:	3d 08       	swcp \$c13,\(\$0\)
+ 6fe:	3c c8       	swcp \$c12,\(\$12\)
+ 700:	39 e8       	swcp \$c9,\(\$gp\)
+
+00000702 <lwcp>:
+ 702:	37 39       	lwcp \$c7,\(\$3\)
+ 704:	36 39       	lwcp \$c6,\(\$3\)
+ 706:	30 29       	lwcp \$c0,\(\$2\)
+ 708:	38 89       	lwcp \$c8,\(\$8\)
+ 70a:	3b d9       	lwcp \$c11,\(\$tp\)
+
+0000070c <smcp>:
+ 70c:	3e 9a       	smcp \$c14,\(\$9\)
+ 70e:	32 8a       	smcp \$c2,\(\$8\)
+ 710:	3e fa       	smcp \$c14,\(\$sp\)
+ 712:	3a 8a       	smcp \$c10,\(\$8\)
+ 714:	32 8a       	smcp \$c2,\(\$8\)
+
+00000716 <lmcp>:
+ 716:	3b 1b       	lmcp \$c11,\(\$1\)
+ 718:	38 8b       	lmcp \$c8,\(\$8\)
+ 71a:	3b db       	lmcp \$c11,\(\$tp\)
+ 71c:	38 0b       	lmcp \$c8,\(\$0\)
+ 71e:	38 eb       	lmcp \$c8,\(\$gp\)
+
+00000720 <swcpi>:
+ 720:	37 00       	swcpi \$c7,\(\$0\+\)
+ 722:	36 e0       	swcpi \$c6,\(\$gp\+\)
+ 724:	3c 80       	swcpi \$c12,\(\$8\+\)
+ 726:	3e f0       	swcpi \$c14,\(\$sp\+\)
+ 728:	36 00       	swcpi \$c6,\(\$0\+\)
+
+0000072a <lwcpi>:
+ 72a:	38 21       	lwcpi \$c8,\(\$2\+\)
+ 72c:	39 01       	lwcpi \$c9,\(\$0\+\)
+ 72e:	33 e1       	lwcpi \$c3,\(\$gp\+\)
+ 730:	3d 51       	lwcpi \$c13,\(\$5\+\)
+ 732:	3b e1       	lwcpi \$c11,\(\$gp\+\)
+
+00000734 <smcpi>:
+ 734:	38 22       	smcpi \$c8,\(\$2\+\)
+ 736:	3b 92       	smcpi \$c11,\(\$9\+\)
+ 738:	34 32       	smcpi \$c4,\(\$3\+\)
+ 73a:	3e 22       	smcpi \$c14,\(\$2\+\)
+ 73c:	39 32       	smcpi \$c9,\(\$3\+\)
+
+0000073e <lmcpi>:
+ 73e:	36 e3       	lmcpi \$c6,\(\$gp\+\)
+ 740:	39 53       	lmcpi \$c9,\(\$5\+\)
+ 742:	3a 63       	lmcpi \$c10,\(\$6\+\)
+ 744:	31 63       	lmcpi \$c1,\(\$6\+\)
+ 746:	32 83       	lmcpi \$c2,\(\$8\+\)
+
+00000748 <swcp16>:
+ 748:	f0 2c ff ff 	swcp \$c0,-1\(\$2\)
+ 74c:	f5 ac 00 01 	swcp \$c5,1\(\$10\)
+ 750:	f8 cc 00 02 	swcp \$c8,2\(\$12\)
+ 754:	fe 1c ff ff 	swcp \$c14,-1\(\$1\)
+ 758:	fc 3c 00 02 	swcp \$c12,2\(\$3\)
+
+0000075c <lwcp16>:
+ 75c:	f8 5d ff ff 	lwcp \$c8,-1\(\$5\)
+ 760:	fc fd 00 01 	lwcp \$c12,1\(\$sp\)
+ 764:	f1 0d 00 02 	lwcp \$c1,2\(\$0\)
+ 768:	f4 dd 00 01 	lwcp \$c4,1\(\$tp\)
+ 76c:	f6 bd 00 02 	lwcp \$c6,2\(\$11\)
+
+00000770 <smcp16>:
+ 770:	f9 ae ff ff 	smcp \$c9,-1\(\$10\)
+ 774:	fe ee 00 01 	smcp \$c14,1\(\$gp\)
+ 778:	f3 fe 00 02 	smcp \$c3,2\(\$sp\)
+ 77c:	ff 8e ff fe 	smcp \$c15,-2\(\$8\)
+ 780:	fd de 00 01 	smcp \$c13,1\(\$tp\)
+
+00000784 <lmcp16>:
+ 784:	f0 ff 00 01 	lmcp \$c0,1\(\$sp\)
+ 788:	ff 8f 00 01 	lmcp \$c15,1\(\$8\)
+ 78c:	f2 8f ff ff 	lmcp \$c2,-1\(\$8\)
+ 790:	fe 8f 00 01 	lmcp \$c14,1\(\$8\)
+ 794:	f1 af ff ff 	lmcp \$c1,-1\(\$10\)
+
+00000798 <sbcpa>:
+ 798:	fe f5 00 02 	sbcpa \$c14,\(\$sp\+\),2
+ 79c:	f2 45 00 fe 	sbcpa \$c2,\(\$4\+\),-2
+ 7a0:	f8 15 00 00 	sbcpa \$c8,\(\$1\+\),0
+ 7a4:	fb 35 00 00 	sbcpa \$c11,\(\$3\+\),0
+ 7a8:	f9 e5 00 fe 	sbcpa \$c9,\(\$gp\+\),-2
+
+000007ac <lbcpa>:
+ 7ac:	f7 25 40 fe 	lbcpa \$c7,\(\$2\+\),-2
+ 7b0:	fc f5 40 02 	lbcpa \$c12,\(\$sp\+\),2
+ 7b4:	f5 45 40 fe 	lbcpa \$c5,\(\$4\+\),-2
+ 7b8:	f7 45 40 fe 	lbcpa \$c7,\(\$4\+\),-2
+ 7bc:	f8 f5 40 00 	lbcpa \$c8,\(\$sp\+\),0
+
+000007c0 <shcpa>:
+ 7c0:	f0 e5 10 00 	shcpa \$c0,\(\$gp\+\),0
+ 7c4:	fc f5 10 10 	shcpa \$c12,\(\$sp\+\),16
+ 7c8:	f1 45 10 04 	shcpa \$c1,\(\$4\+\),4
+ 7cc:	f5 45 10 e0 	shcpa \$c5,\(\$4\+\),-32
+ 7d0:	f1 f5 10 00 	shcpa \$c1,\(\$sp\+\),0
+
+000007d4 <lhcpa>:
+ 7d4:	f4 45 50 00 	lhcpa \$c4,\(\$4\+\),0
+ 7d8:	f6 55 50 30 	lhcpa \$c6,\(\$5\+\),48
+ 7dc:	f3 65 50 cc 	lhcpa \$c3,\(\$6\+\),-52
+ 7e0:	f8 65 50 e8 	lhcpa \$c8,\(\$6\+\),-24
+ 7e4:	f0 95 50 00 	lhcpa \$c0,\(\$9\+\),0
+
+000007e8 <swcpa>:
+ 7e8:	f1 95 20 10 	swcpa \$c1,\(\$9\+\),16
+ 7ec:	f7 f5 20 20 	swcpa \$c7,\(\$sp\+\),32
+ 7f0:	f3 c5 20 30 	swcpa \$c3,\(\$12\+\),48
+ 7f4:	fa 95 20 08 	swcpa \$c10,\(\$9\+\),8
+ 7f8:	fe 85 20 04 	swcpa \$c14,\(\$8\+\),4
+
+000007fc <lwcpa>:
+ 7fc:	f6 e5 60 f8 	lwcpa \$c6,\(\$gp\+\),-8
+ 800:	f4 75 60 04 	lwcpa \$c4,\(\$7\+\),4
+ 804:	fb e5 60 f0 	lwcpa \$c11,\(\$gp\+\),-16
+ 808:	fa f5 60 e0 	lwcpa \$c10,\(\$sp\+\),-32
+ 80c:	f2 25 60 08 	lwcpa \$c2,\(\$2\+\),8
+
+00000810 <smcpa>:
+ 810:	fd f5 30 f8 	smcpa \$c13,\(\$sp\+\),-8
+ 814:	f6 75 30 f8 	smcpa \$c6,\(\$7\+\),-8
+ 818:	f5 35 30 10 	smcpa \$c5,\(\$3\+\),16
+ 81c:	fd f5 30 10 	smcpa \$c13,\(\$sp\+\),16
+ 820:	f3 c5 30 30 	smcpa \$c3,\(\$12\+\),48
+
+00000824 <lmcpa>:
+ 824:	f9 45 70 00 	lmcpa \$c9,\(\$4\+\),0
+ 828:	f3 f5 70 f0 	lmcpa \$c3,\(\$sp\+\),-16
+ 82c:	ff d5 70 08 	lmcpa \$c15,\(\$tp\+\),8
+ 830:	f8 85 70 f8 	lmcpa \$c8,\(\$8\+\),-8
+ 834:	fa 95 70 00 	lmcpa \$c10,\(\$9\+\),0
+
+00000838 <sbcpm0>:
+ 838:	fa d5 08 08 	sbcpm0 \$c10,\(\$tp\+\),8
+ 83c:	fd 55 08 f8 	sbcpm0 \$c13,\(\$5\+\),-8
+ 840:	f4 55 08 f8 	sbcpm0 \$c4,\(\$5\+\),-8
+ 844:	fa d5 08 10 	sbcpm0 \$c10,\(\$tp\+\),16
+ 848:	f4 55 08 e8 	sbcpm0 \$c4,\(\$5\+\),-24
+
+0000084c <lbcpm0>:
+ 84c:	f0 45 48 00 	lbcpm0 \$c0,\(\$4\+\),0
+ 850:	f9 75 48 f8 	lbcpm0 \$c9,\(\$7\+\),-8
+ 854:	fc 85 48 18 	lbcpm0 \$c12,\(\$8\+\),24
+ 858:	f8 c5 48 10 	lbcpm0 \$c8,\(\$12\+\),16
+ 85c:	f7 85 48 10 	lbcpm0 \$c7,\(\$8\+\),16
+
+00000860 <shcpm0>:
+ 860:	f2 d5 18 02 	shcpm0 \$c2,\(\$tp\+\),2
+ 864:	f7 f5 18 fe 	shcpm0 \$c7,\(\$sp\+\),-2
+ 868:	f8 25 18 02 	shcpm0 \$c8,\(\$2\+\),2
+ 86c:	fd 55 18 00 	shcpm0 \$c13,\(\$5\+\),0
+ 870:	f3 e5 18 08 	shcpm0 \$c3,\(\$gp\+\),8
+
+00000874 <lhcpm0>:
+ 874:	f7 45 58 08 	lhcpm0 \$c7,\(\$4\+\),8
+ 878:	f3 35 58 fe 	lhcpm0 \$c3,\(\$3\+\),-2
+ 87c:	f3 15 58 00 	lhcpm0 \$c3,\(\$1\+\),0
+ 880:	f2 e5 58 00 	lhcpm0 \$c2,\(\$gp\+\),0
+ 884:	fc 65 58 02 	lhcpm0 \$c12,\(\$6\+\),2
+
+00000888 <swcpm0>:
+ 888:	f8 85 28 20 	swcpm0 \$c8,\(\$8\+\),32
+ 88c:	f9 f5 28 00 	swcpm0 \$c9,\(\$sp\+\),0
+ 890:	f9 25 28 f0 	swcpm0 \$c9,\(\$2\+\),-16
+ 894:	f0 e5 28 30 	swcpm0 \$c0,\(\$gp\+\),48
+ 898:	ff 15 28 08 	swcpm0 \$c15,\(\$1\+\),8
+
+0000089c <lwcpm0>:
+ 89c:	fe a5 68 fc 	lwcpm0 \$c14,\(\$10\+\),-4
+ 8a0:	fb f5 68 fc 	lwcpm0 \$c11,\(\$sp\+\),-4
+ 8a4:	f5 75 68 f8 	lwcpm0 \$c5,\(\$7\+\),-8
+ 8a8:	f2 c5 68 20 	lwcpm0 \$c2,\(\$12\+\),32
+ 8ac:	f2 e5 68 10 	lwcpm0 \$c2,\(\$gp\+\),16
+
+000008b0 <smcpm0>:
+ 8b0:	f1 c5 38 08 	smcpm0 \$c1,\(\$12\+\),8
+ 8b4:	f8 45 38 f0 	smcpm0 \$c8,\(\$4\+\),-16
+ 8b8:	fa b5 38 00 	smcpm0 \$c10,\(\$11\+\),0
+ 8bc:	f1 35 38 f0 	smcpm0 \$c1,\(\$3\+\),-16
+ 8c0:	fb f5 38 f8 	smcpm0 \$c11,\(\$sp\+\),-8
+
+000008c4 <lmcpm0>:
+ 8c4:	fe a5 78 00 	lmcpm0 \$c14,\(\$10\+\),0
+ 8c8:	f6 f5 78 f0 	lmcpm0 \$c6,\(\$sp\+\),-16
+ 8cc:	fd 15 78 08 	lmcpm0 \$c13,\(\$1\+\),8
+ 8d0:	fa d5 78 e8 	lmcpm0 \$c10,\(\$tp\+\),-24
+ 8d4:	f7 e5 78 e8 	lmcpm0 \$c7,\(\$gp\+\),-24
+
+000008d8 <sbcpm1>:
+ 8d8:	f9 85 0c 00 	sbcpm1 \$c9,\(\$8\+\),0
+ 8dc:	f7 c5 0c e8 	sbcpm1 \$c7,\(\$12\+\),-24
+ 8e0:	ff 55 0c e8 	sbcpm1 \$c15,\(\$5\+\),-24
+ 8e4:	f5 d5 0c 10 	sbcpm1 \$c5,\(\$tp\+\),16
+ 8e8:	f6 15 0c 80 	sbcpm1 \$c6,\(\$1\+\),-128
+
+000008ec <lbcpm1>:
+ 8ec:	f6 e5 4c 02 	lbcpm1 \$c6,\(\$gp\+\),2
+ 8f0:	f7 d5 4c fe 	lbcpm1 \$c7,\(\$tp\+\),-2
+ 8f4:	f4 d5 4c 01 	lbcpm1 \$c4,\(\$tp\+\),1
+ 8f8:	fc 25 4c fe 	lbcpm1 \$c12,\(\$2\+\),-2
+ 8fc:	fb 75 4c 01 	lbcpm1 \$c11,\(\$7\+\),1
+
+00000900 <shcpm1>:
+ 900:	f4 85 1c 18 	shcpm1 \$c4,\(\$8\+\),24
+ 904:	fb 65 1c f0 	shcpm1 \$c11,\(\$6\+\),-16
+ 908:	f7 85 1c 08 	shcpm1 \$c7,\(\$8\+\),8
+ 90c:	f5 c5 1c 10 	shcpm1 \$c5,\(\$12\+\),16
+ 910:	f0 85 1c e0 	shcpm1 \$c0,\(\$8\+\),-32
+
+00000914 <lhcpm1>:
+ 914:	fb 05 5c 00 	lhcpm1 \$c11,\(\$0\+\),0
+ 918:	f7 d5 5c fe 	lhcpm1 \$c7,\(\$tp\+\),-2
+ 91c:	fa 85 5c 08 	lhcpm1 \$c10,\(\$8\+\),8
+ 920:	f3 d5 5c 00 	lhcpm1 \$c3,\(\$tp\+\),0
+ 924:	f9 65 5c 02 	lhcpm1 \$c9,\(\$6\+\),2
+
+00000928 <swcpm1>:
+ 928:	f9 85 2c 18 	swcpm1 \$c9,\(\$8\+\),24
+ 92c:	f9 e5 2c 00 	swcpm1 \$c9,\(\$gp\+\),0
+ 930:	f9 85 2c 10 	swcpm1 \$c9,\(\$8\+\),16
+ 934:	fe 15 2c 00 	swcpm1 \$c14,\(\$1\+\),0
+ 938:	f2 f5 2c 08 	swcpm1 \$c2,\(\$sp\+\),8
+
+0000093c <lwcpm1>:
+ 93c:	f8 85 6c 00 	lwcpm1 \$c8,\(\$8\+\),0
+ 940:	f3 e5 6c f0 	lwcpm1 \$c3,\(\$gp\+\),-16
+ 944:	f7 65 6c f8 	lwcpm1 \$c7,\(\$6\+\),-8
+ 948:	fe 85 6c e8 	lwcpm1 \$c14,\(\$8\+\),-24
+ 94c:	f3 85 6c 18 	lwcpm1 \$c3,\(\$8\+\),24
+
+00000950 <smcpm1>:
+ 950:	fa 45 3c 00 	smcpm1 \$c10,\(\$4\+\),0
+ 954:	f6 f5 3c f0 	smcpm1 \$c6,\(\$sp\+\),-16
+ 958:	fd 75 3c e8 	smcpm1 \$c13,\(\$7\+\),-24
+ 95c:	f3 e5 3c f8 	smcpm1 \$c3,\(\$gp\+\),-8
+ 960:	f0 25 3c 08 	smcpm1 \$c0,\(\$2\+\),8
+
+00000964 <lmcpm1>:
+ 964:	fc 15 7c 00 	lmcpm1 \$c12,\(\$1\+\),0
+ 968:	f0 65 7c 08 	lmcpm1 \$c0,\(\$6\+\),8
+ 96c:	f6 25 7c f8 	lmcpm1 \$c6,\(\$2\+\),-8
+ 970:	fc e5 7c f0 	lmcpm1 \$c12,\(\$gp\+\),-16
+ 974:	fe f5 7c 30 	lmcpm1 \$c14,\(\$sp\+\),48
+
+00000... <bcpeq>:
+ ...:	d8 44 00 00 	bcpeq 0x4,... <bcpeq>
+ ...:	d8 04 ff ff 	bcpeq 0x0,... <bcpeq\+0x2>
+ ...:	d8 44 ff ff 	bcpeq 0x4,... <bcpeq\+0x6>
+ ...:	d8 14 00 01 	bcpeq 0x1,... <bcpeq\+0xe>
+ ...:	d8 24 00 01 	bcpeq 0x2,... <bcpeq\+0x12>
+
+00000... <bcpne>:
+ ...:	d8 25 00 00 	bcpne 0x2,... <bcpne>
+ ...:	d8 45 00 00 	bcpne 0x4,... <bcpne\+0x4>
+ ...:	d8 15 00 00 	bcpne 0x1,... <bcpne\+0x8>
+ ...:	d8 45 00 00 	bcpne 0x4,... <bcpne\+0xc>
+ ...:	d8 15 00 01 	bcpne 0x1,... <bcpne\+0x12>
+
+00000... <bcpat>:
+ ...:	d8 16 ff ff 	bcpat 0x1,... <bcpne\+0x12>
+ ...:	d8 06 00 01 	bcpat 0x0,... <bcpat\+0x6>
+ ...:	d8 06 ff ff 	bcpat 0x0,... <bcpat\+0x6>
+ ...:	d8 26 00 00 	bcpat 0x2,... <bcpat\+0xc>
+ ...:	d8 16 ff ff 	bcpat 0x1,... <bcpat\+0xe>
+
+00000... <bcpaf>:
+ ...:	d8 47 00 00 	bcpaf 0x4,... <bcpaf>
+ ...:	d8 37 00 00 	bcpaf 0x3,... <bcpaf\+0x4>
+ ...:	d8 47 00 00 	bcpaf 0x4,... <bcpaf\+0x8>
+ ...:	d8 17 00 01 	bcpaf 0x1,... <bcpaf\+0xe>
+ ...:	d8 47 00 01 	bcpaf 0x4,... <bcpaf\+0x12>
+
+00000... <synccp>:
+ ...:	70 21       	synccp
+
+00000... <jsrv>:
+ ...:	18 bf       	jsrv \$11
+ ...:	18 5f       	jsrv \$5
+ ...:	18 af       	jsrv \$10
+ ...:	18 cf       	jsrv \$12
+ ...:	18 af       	jsrv \$10
+
+00000... <bsrv>:
+ ...:	df fb ff ff 	bsrv ... <jsrv\+0x8>
+ ...:	df fb ff ff 	bsrv ... <bsrv\+0x2>
+ ...:	df fb ff ff 	bsrv ... <bsrv\+0x6>
+ ...:	d8 1b 00 00 	bsrv ... <bsrv\+0xe>
+ ...:	d8 0b 00 00 	bsrv ... <bsrv\+0x10>
+
+00000... <case106341>:
+ ...:	7a 78       	stc \$10,\$hi
+ ...:	70 8a       	ldc \$0,\$lo
+
+00000... <case106821>:
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 08       	sb \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 09       	sh \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0a       	sw \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0c       	lb \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0d       	lh \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0e       	lw \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0b       	lbu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	00 0f       	lhu \$0,\(\$0\)
+ ...:	c0 08 00 01 	sb \$0,1\(\$0\)
+ ...:	c0 08 00 01 	sb \$0,1\(\$0\)
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+ ...:	c0 08 00 01 	sb \$0,1\(\$0\)
+ ...:	c0 08 00 01 	sb \$0,1\(\$0\)
+ ...:	c0 09 00 01 	sh \$0,1\(\$0\)
+ ...:	c0 09 00 01 	sh \$0,1\(\$0\)
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+ ...:	c0 09 00 01 	sh \$0,1\(\$0\)
+ ...:	c0 09 00 01 	sh \$0,1\(\$0\)
+ ...:	c0 0a 00 01 	sw \$0,1\(\$0\)
+ ...:	c0 0a 00 01 	sw \$0,1\(\$0\)
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+ ...:	c0 0a 00 01 	sw \$0,1\(\$0\)
+ ...:	c0 0a 00 01 	sw \$0,1\(\$0\)
+ ...:	c0 0c 00 01 	lb \$0,1\(\$0\)
+ ...:	c0 0c 00 01 	lb \$0,1\(\$0\)
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+ ...:	c0 0c 00 01 	lb \$0,1\(\$0\)
+ ...:	c0 0c 00 01 	lb \$0,1\(\$0\)
+ ...:	c0 0d 00 01 	lh \$0,1\(\$0\)
+ ...:	c0 0d 00 01 	lh \$0,1\(\$0\)
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+ ...:	c0 0d 00 01 	lh \$0,1\(\$0\)
+ ...:	c0 0d 00 01 	lh \$0,1\(\$0\)
+ ...:	c0 0e 00 01 	lw \$0,1\(\$0\)
+ ...:	c0 0e 00 01 	lw \$0,1\(\$0\)
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+ ...:	c0 0e 00 01 	lw \$0,1\(\$0\)
+ ...:	c0 0e 00 01 	lw \$0,1\(\$0\)
+ ...:	c0 0b 00 01 	lbu \$0,1\(\$0\)
+ ...:	c0 0b 00 01 	lbu \$0,1\(\$0\)
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+ ...:	c0 0b 00 01 	lbu \$0,1\(\$0\)
+ ...:	c0 0b 00 01 	lbu \$0,1\(\$0\)
+ ...:	c0 0f 00 01 	lhu \$0,1\(\$0\)
+ ...:	c0 0f 00 01 	lhu \$0,1\(\$0\)
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+ ...:	c0 0f 00 01 	lhu \$0,1\(\$0\)
+ ...:	c0 0f 00 01 	lhu \$0,1\(\$0\)
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 08 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 09 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
diff --git a/gas/testsuite/gas/mep/allinsn.exp b/gas/testsuite/gas/mep/allinsn.exp
new file mode 100644
index 000000000000..259ed10b1a14
--- /dev/null
+++ b/gas/testsuite/gas/mep/allinsn.exp
@@ -0,0 +1,9 @@
+# MEP assembler testsuite. -*- Tcl -*-
+
+if [istarget mep*-*-*] {
+    foreach test {allinsn dj1 dj2} {
+	run_dump_test $test
+	run_dump_test $test.le
+    }
+    run_dump_test branch1
+}
diff --git a/gas/testsuite/gas/mep/allinsn.le.d b/gas/testsuite/gas/mep/allinsn.le.d
new file mode 100644
index 000000000000..2d9c50bad6e0
--- /dev/null
+++ b/gas/testsuite/gas/mep/allinsn.le.d
@@ -0,0 +1,1346 @@
+#as: -EL
+#objdump: -dr
+#source: allinsn.s
+#name: allinsn.le
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <sb>:
+   0:	88 07       	sb \$7,\(\$8\)
+   2:	98 05       	sb \$5,\(\$9\)
+   4:	e8 07       	sb \$7,\(\$gp\)
+   6:	88 0e       	sb \$gp,\(\$8\)
+   8:	e8 0f       	sb \$sp,\(\$gp\)
+
+0000000a <sh>:
+   a:	89 03       	sh \$3,\(\$8\)
+   c:	19 0c       	sh \$12,\(\$1\)
+   e:	29 0d       	sh \$tp,\(\$2\)
+  10:	89 02       	sh \$2,\(\$8\)
+  12:	a9 0c       	sh \$12,\(\$10\)
+
+00000014 <sw>:
+  14:	0a 0b       	sw \$11,\(\$0\)
+  16:	7a 03       	sw \$3,\(\$7\)
+  18:	ea 0d       	sw \$tp,\(\$gp\)
+  1a:	9a 08       	sw \$8,\(\$9\)
+  1c:	8a 0e       	sw \$gp,\(\$8\)
+
+0000001e <lb>:
+  1e:	bc 0c       	lb \$12,\(\$11\)
+  20:	2c 09       	lb \$9,\(\$2\)
+  22:	bc 08       	lb \$8,\(\$11\)
+  24:	2c 0e       	lb \$gp,\(\$2\)
+  26:	cc 02       	lb \$2,\(\$12\)
+
+00000028 <lh>:
+  28:	8d 0f       	lh \$sp,\(\$8\)
+  2a:	ad 03       	lh \$3,\(\$10\)
+  2c:	fd 09       	lh \$9,\(\$sp\)
+  2e:	fd 06       	lh \$6,\(\$sp\)
+  30:	bd 0f       	lh \$sp,\(\$11\)
+
+00000032 <lw>:
+  32:	ae 0c       	lw \$12,\(\$10\)
+  34:	de 09       	lw \$9,\(\$tp\)
+  36:	ee 0c       	lw \$12,\(\$gp\)
+  38:	be 0c       	lw \$12,\(\$11\)
+  3a:	ae 0d       	lw \$tp,\(\$10\)
+
+0000003c <lbu>:
+  3c:	eb 0e       	lbu \$gp,\(\$gp\)
+  3e:	8b 0c       	lbu \$12,\(\$8\)
+  40:	1b 0e       	lbu \$gp,\(\$1\)
+  42:	cb 08       	lbu \$8,\(\$12\)
+  44:	1b 0c       	lbu \$12,\(\$1\)
+
+00000046 <lhu>:
+  46:	4f 0f       	lhu \$sp,\(\$4\)
+  48:	4f 0e       	lhu \$gp,\(\$4\)
+  4a:	4f 05       	lhu \$5,\(\$4\)
+  4c:	df 0f       	lhu \$sp,\(\$tp\)
+  4e:	ff 04       	lhu \$4,\(\$sp\)
+
+00000050 <sw_sp>:
+  50:	8a c9 03 00 	sw \$9,3\(\$8\)
+  54:	5a ca 04 00 	sw \$10,4\(\$5\)
+  58:	ea c0 03 00 	sw \$0,3\(\$gp\)
+  5c:	8a c0 02 00 	sw \$0,2\(\$8\)
+  60:	8a cf 01 00 	sw \$sp,1\(\$8\)
+
+00000064 <lw_sp>:
+  64:	5e cd 01 00 	lw \$tp,1\(\$5\)
+  68:	0e cf 01 00 	lw \$sp,1\(\$0\)
+  6c:	ce c0 04 00 	lw \$0,4\(\$12\)
+  70:	de cb 01 00 	lw \$11,1\(\$tp\)
+  74:	4e c9 03 00 	lw \$9,3\(\$4\)
+
+00000078 <sb_tp>:
+  78:	18 c5 01 00 	sb \$5,1\(\$1\)
+  7c:	98 ca 01 00 	sb \$10,1\(\$9\)
+  80:	38 c5 03 00 	sb \$5,3\(\$3\)
+  84:	38 c5 01 00 	sb \$5,1\(\$3\)
+  88:	48 ca 04 00 	sb \$10,4\(\$4\)
+
+0000008c <sh_tp>:
+  8c:	09 c3 01 00 	sh \$3,1\(\$0\)
+  90:	99 cd 01 00 	sh \$tp,1\(\$9\)
+  94:	a9 c9 04 00 	sh \$9,4\(\$10\)
+  98:	e9 cf 03 00 	sh \$sp,3\(\$gp\)
+  9c:	99 ce 04 00 	sh \$gp,4\(\$9\)
+
+000000a0 <sw_tp>:
+  a0:	da c6 02 00 	sw \$6,2\(\$tp\)
+  a4:	fa c6 01 00 	sw \$6,1\(\$sp\)
+  a8:	3a c2 02 00 	sw \$2,2\(\$3\)
+  ac:	ca c6 02 00 	sw \$6,2\(\$12\)
+  b0:	ba c3 01 00 	sw \$3,1\(\$11\)
+
+000000b4 <lb_tp>:
+  b4:	bc cd 04 00 	lb \$tp,4\(\$11\)
+  b8:	8c cd 04 00 	lb \$tp,4\(\$8\)
+  bc:	5c c5 04 00 	lb \$5,4\(\$5\)
+  c0:	ec cf 02 00 	lb \$sp,2\(\$gp\)
+  c4:	3c c3 02 00 	lb \$3,2\(\$3\)
+
+000000c8 <lh_tp>:
+  c8:	8d c7 02 00 	lh \$7,2\(\$8\)
+  cc:	8d c4 03 00 	lh \$4,3\(\$8\)
+  d0:	fd ce 01 00 	lh \$gp,1\(\$sp\)
+  d4:	0d c9 01 00 	lh \$9,1\(\$0\)
+  d8:	0d cd 02 00 	lh \$tp,2\(\$0\)
+
+000000dc <lw_tp>:
+  dc:	07 48       	lw \$8,0x4\(\$sp\)
+  de:	9e cb 04 00 	lw \$11,4\(\$9\)
+  e2:	2e ce 01 00 	lw \$gp,1\(\$2\)
+  e6:	ee c9 02 00 	lw \$9,2\(\$gp\)
+  ea:	ce c8 01 00 	lw \$8,1\(\$12\)
+
+000000ee <lbu_tp>:
+  ee:	9b cc 01 00 	lbu \$12,1\(\$9\)
+  f2:	9b cb 01 00 	lbu \$11,1\(\$9\)
+  f6:	8b ce 03 00 	lbu \$gp,3\(\$8\)
+  fa:	fb c0 02 00 	lbu \$0,2\(\$sp\)
+  fe:	bb cd 01 00 	lbu \$tp,1\(\$11\)
+
+00000102 <lhu_tp>:
+ 102:	af ce 02 00 	lhu \$gp,2\(\$10\)
+ 106:	8f cb 01 00 	lhu \$11,1\(\$8\)
+ 10a:	0f c1 01 00 	lhu \$1,1\(\$0\)
+ 10e:	ff c7 02 00 	lhu \$7,2\(\$sp\)
+ 112:	83 8b       	lhu \$3,0x2\(\$tp\)
+
+00000114 <sb16>:
+ 114:	b8 c7 ff ff 	sb \$7,-1\(\$11\)
+ 118:	e8 cd 01 00 	sb \$tp,1\(\$gp\)
+ 11c:	e8 c3 01 00 	sb \$3,1\(\$gp\)
+ 120:	68 ce 02 00 	sb \$gp,2\(\$6\)
+ 124:	78 ce 01 00 	sb \$gp,1\(\$7\)
+
+00000128 <sh16>:
+ 128:	49 cc ff ff 	sh \$12,-1\(\$4\)
+ 12c:	19 cf 01 00 	sh \$sp,1\(\$1\)
+ 130:	c9 c2 fe ff 	sh \$2,-2\(\$12\)
+ 134:	b9 c9 02 00 	sh \$9,2\(\$11\)
+ 138:	c9 c9 fe ff 	sh \$9,-2\(\$12\)
+
+0000013c <sw16>:
+ 13c:	ea cb ff ff 	sw \$11,-1\(\$gp\)
+ 140:	06 44       	sw \$4,0x4\(\$sp\)
+ 142:	3a c2 fe ff 	sw \$2,-2\(\$3\)
+ 146:	2a c6 ff ff 	sw \$6,-1\(\$2\)
+ 14a:	da c8 fe ff 	sw \$8,-2\(\$tp\)
+
+0000014e <lb16>:
+ 14e:	2c ca fe ff 	lb \$10,-2\(\$2\)
+ 152:	bc c3 fe ff 	lb \$3,-2\(\$11\)
+ 156:	5c cc 01 00 	lb \$12,1\(\$5\)
+ 15a:	5c c5 01 00 	lb \$5,1\(\$5\)
+ 15e:	dc cb 02 00 	lb \$11,2\(\$tp\)
+
+00000162 <lh16>:
+ 162:	bd cf ff ff 	lh \$sp,-1\(\$11\)
+ 166:	bd cd fe ff 	lh \$tp,-2\(\$11\)
+ 16a:	ad c2 01 00 	lh \$2,1\(\$10\)
+ 16e:	7d c8 ff ff 	lh \$8,-1\(\$7\)
+ 172:	bd ce ff ff 	lh \$gp,-1\(\$11\)
+
+00000176 <lw16>:
+ 176:	5e c0 ff ff 	lw \$0,-1\(\$5\)
+ 17a:	7e cc fe ff 	lw \$12,-2\(\$7\)
+ 17e:	3e c1 fe ff 	lw \$1,-2\(\$3\)
+ 182:	7e c1 02 00 	lw \$1,2\(\$7\)
+ 186:	8e c4 01 00 	lw \$4,1\(\$8\)
+
+0000018a <lbu16>:
+ 18a:	4b cc ff ff 	lbu \$12,-1\(\$4\)
+ 18e:	bb ce 01 00 	lbu \$gp,1\(\$11\)
+ 192:	db c1 ff ff 	lbu \$1,-1\(\$tp\)
+ 196:	db c9 ff ff 	lbu \$9,-1\(\$tp\)
+ 19a:	fb c8 01 00 	lbu \$8,1\(\$sp\)
+
+0000019e <lhu16>:
+ 19e:	ff cd ff ff 	lhu \$tp,-1\(\$sp\)
+ 1a2:	8f ce 02 00 	lhu \$gp,2\(\$8\)
+ 1a6:	cf cf ff ff 	lhu \$sp,-1\(\$12\)
+ 1aa:	0f c3 ff ff 	lhu \$3,-1\(\$0\)
+ 1ae:	cf c3 fe ff 	lhu \$3,-2\(\$12\)
+
+000001b2 <sw24>:
+ 1b2:	06 eb 00 00 	sw \$11,\(0x4\)
+ 1b6:	06 ef 00 00 	sw \$sp,\(0x4\)
+ 1ba:	0a e7 00 00 	sw \$7,\(0x8\)
+ 1be:	12 ea 00 00 	sw \$10,\(0x10\)
+ 1c2:	a2 e8 00 00 	sw \$8,\(0xa0\)
+
+000001c6 <lw24>:
+ 1c6:	07 e4 00 00 	lw \$4,\(0x4\)
+ 1ca:	07 ef 00 00 	lw \$sp,\(0x4\)
+ 1ce:	13 e4 00 00 	lw \$4,\(0x10\)
+ 1d2:	03 e8 00 00 	lw \$8,\(0x0\)
+ 1d6:	0b ed 00 00 	lw \$tp,\(0x8\)
+
+000001da <extb>:
+ 1da:	0d 1d       	extb \$tp
+ 1dc:	0d 1d       	extb \$tp
+ 1de:	0d 16       	extb \$6
+ 1e0:	0d 1e       	extb \$gp
+ 1e2:	0d 1a       	extb \$10
+
+000001e4 <exth>:
+ 1e4:	2d 1f       	exth \$sp
+ 1e6:	2d 12       	exth \$2
+ 1e8:	2d 15       	exth \$5
+ 1ea:	2d 1a       	exth \$10
+ 1ec:	2d 14       	exth \$4
+
+000001ee <extub>:
+ 1ee:	8d 12       	extub \$2
+ 1f0:	8d 1d       	extub \$tp
+ 1f2:	8d 13       	extub \$3
+ 1f4:	8d 19       	extub \$9
+ 1f6:	8d 1e       	extub \$gp
+
+000001f8 <extuh>:
+ 1f8:	ad 18       	extuh \$8
+ 1fa:	ad 18       	extuh \$8
+ 1fc:	ad 14       	extuh \$4
+ 1fe:	ad 10       	extuh \$0
+ 200:	ad 10       	extuh \$0
+
+00000202 <ssarb>:
+ 202:	8c 12       	ssarb 2\(\$8\)
+ 204:	dc 12       	ssarb 2\(\$tp\)
+ 206:	dc 11       	ssarb 1\(\$tp\)
+ 208:	5c 12       	ssarb 2\(\$5\)
+ 20a:	9c 10       	ssarb 0\(\$9\)
+
+0000020c <mov>:
+ 20c:	30 02       	mov \$2,\$3
+ 20e:	b0 03       	mov \$3,\$11
+ 210:	a0 0f       	mov \$sp,\$10
+ 212:	00 0f       	mov \$sp,\$0
+ 214:	d0 03       	mov \$3,\$tp
+
+00000216 <movi8>:
+ 216:	ff 5b       	mov \$11,-1
+ 218:	02 56       	mov \$6,2
+ 21a:	ff 5f       	mov \$sp,-1
+ 21c:	01 5f       	mov \$sp,1
+ 21e:	ff 5e       	mov \$gp,-1
+
+00000220 <movi16>:
+ 220:	00 5f       	mov \$sp,0
+ 222:	02 50       	mov \$0,2
+ 224:	ff 58       	mov \$8,-1
+ 226:	01 5c       	mov \$12,1
+ 228:	ff 57       	mov \$7,-1
+
+0000022a <movu24>:
+ 22a:	01 d2 00 00 	movu \$2,0x1
+ 22e:	11 ca 04 00 	movu \$10,0x4
+ 232:	11 c9 00 00 	movu \$9,0x0
+ 236:	03 d4 00 00 	movu \$4,0x3
+ 23a:	11 ce 01 00 	movu \$gp,0x1
+
+0000023e <movu16>:
+ 23e:	11 cf 01 00 	movu \$sp,0x1
+ 242:	03 d6 00 00 	movu \$6,0x3
+ 246:	03 d0 00 00 	movu \$0,0x3
+ 24a:	11 ce 03 00 	movu \$gp,0x3
+ 24e:	11 ca 02 00 	movu \$10,0x2
+
+00000252 <movh>:
+ 252:	21 c8 02 00 	movh \$8,0x2
+ 256:	21 cd 01 00 	movh \$tp,0x1
+ 25a:	21 ce 02 00 	movh \$gp,0x2
+ 25e:	21 cc 00 00 	movh \$12,0x0
+ 262:	21 cb 02 00 	movh \$11,0x2
+
+00000266 <add3>:
+ 266:	36 9b       	add3 \$6,\$11,\$3
+ 268:	5e 9d       	add3 \$gp,\$tp,\$5
+ 26a:	73 9b       	add3 \$3,\$11,\$7
+ 26c:	dd 9e       	add3 \$tp,\$gp,\$tp
+ 26e:	80 9e       	add3 \$0,\$gp,\$8
+
+00000270 <add>:
+ 270:	08 6c       	add \$12,2
+ 272:	fc 6c       	add \$12,-1
+ 274:	04 64       	add \$4,1
+ 276:	04 66       	add \$6,1
+ 278:	08 66       	add \$6,2
+
+0000027a <add3i>:
+ 27a:	04 4b       	add3 \$11,\$sp,0x4
+ 27c:	f0 c4 01 00 	add3 \$4,\$sp,1
+ 280:	00 40       	add3 \$0,\$sp,0x0
+ 282:	f0 cd 03 00 	add3 \$tp,\$sp,3
+ 286:	00 4b       	add3 \$11,\$sp,0x0
+
+00000288 <advck3>:
+ 288:	a7 0e       	advck3 \$0,\$gp,\$10
+ 28a:	07 0d       	advck3 \$0,\$tp,\$0
+ 28c:	d7 0e       	advck3 \$0,\$gp,\$tp
+ 28e:	87 07       	advck3 \$0,\$7,\$8
+ 290:	27 01       	advck3 \$0,\$1,\$2
+
+00000292 <sub>:
+ 292:	e4 08       	sub \$8,\$gp
+ 294:	94 01       	sub \$1,\$9
+ 296:	74 0d       	sub \$tp,\$7
+ 298:	34 0f       	sub \$sp,\$3
+ 29a:	74 02       	sub \$2,\$7
+
+0000029c <sbvck3>:
+ 29c:	e5 03       	sbvck3 \$0,\$3,\$gp
+ 29e:	75 03       	sbvck3 \$0,\$3,\$7
+ 2a0:	a5 0a       	sbvck3 \$0,\$10,\$10
+ 2a2:	d5 04       	sbvck3 \$0,\$4,\$tp
+ 2a4:	f5 0a       	sbvck3 \$0,\$10,\$sp
+
+000002a6 <neg>:
+ 2a6:	71 0e       	neg \$gp,\$7
+ 2a8:	71 01       	neg \$1,\$7
+ 2aa:	b1 02       	neg \$2,\$11
+ 2ac:	81 0d       	neg \$tp,\$8
+ 2ae:	d1 0e       	neg \$gp,\$tp
+
+000002b0 <slt3>:
+ 2b0:	82 0e       	slt3 \$0,\$gp,\$8
+ 2b2:	d2 04       	slt3 \$0,\$4,\$tp
+ 2b4:	e2 0a       	slt3 \$0,\$10,\$gp
+ 2b6:	52 0e       	slt3 \$0,\$gp,\$5
+ 2b8:	c2 03       	slt3 \$0,\$3,\$12
+
+000002ba <sltu3>:
+ 2ba:	83 02       	sltu3 \$0,\$2,\$8
+ 2bc:	b3 0e       	sltu3 \$0,\$gp,\$11
+ 2be:	d3 02       	sltu3 \$0,\$2,\$tp
+ 2c0:	83 09       	sltu3 \$0,\$9,\$8
+ 2c2:	93 06       	sltu3 \$0,\$6,\$9
+
+000002c4 <slt3i>:
+ 2c4:	11 66       	slt3 \$0,\$6,0x2
+ 2c6:	09 6b       	slt3 \$0,\$11,0x1
+ 2c8:	01 6f       	slt3 \$0,\$sp,0x0
+ 2ca:	01 63       	slt3 \$0,\$3,0x0
+ 2cc:	01 6d       	slt3 \$0,\$tp,0x0
+
+000002ce <sltu3i>:
+ 2ce:	25 6e       	sltu3 \$0,\$gp,0x4
+ 2d0:	1d 6d       	sltu3 \$0,\$tp,0x3
+ 2d2:	0d 63       	sltu3 \$0,\$3,0x1
+ 2d4:	05 6c       	sltu3 \$0,\$12,0x0
+ 2d6:	1d 61       	sltu3 \$0,\$1,0x3
+
+000002d8 <sl1ad3>:
+ 2d8:	e6 28       	sl1ad3 \$0,\$8,\$gp
+ 2da:	26 24       	sl1ad3 \$0,\$4,\$2
+ 2dc:	c6 2f       	sl1ad3 \$0,\$sp,\$12
+ 2de:	16 29       	sl1ad3 \$0,\$9,\$1
+ 2e0:	26 28       	sl1ad3 \$0,\$8,\$2
+
+000002e2 <sl2ad3>:
+ 2e2:	d7 28       	sl2ad3 \$0,\$8,\$tp
+ 2e4:	37 22       	sl2ad3 \$0,\$2,\$3
+ 2e6:	97 28       	sl2ad3 \$0,\$8,\$9
+ 2e8:	c7 27       	sl2ad3 \$0,\$7,\$12
+ 2ea:	c7 24       	sl2ad3 \$0,\$4,\$12
+
+000002ec <add3x>:
+ 2ec:	b0 cd 01 00 	add3 \$tp,\$11,1
+ 2f0:	40 cd ff ff 	add3 \$tp,\$4,-1
+ 2f4:	d0 c2 01 00 	add3 \$2,\$tp,1
+ 2f8:	e0 c3 01 00 	add3 \$3,\$gp,1
+ 2fc:	f0 ca 02 00 	add3 \$10,\$sp,2
+
+00000300 <slt3x>:
+ 300:	12 c8 ff ff 	slt3 \$8,\$1,-1
+ 304:	32 c0 fe ff 	slt3 \$0,\$3,-2
+ 308:	f2 c9 ff ff 	slt3 \$9,\$sp,-1
+ 30c:	82 c3 02 00 	slt3 \$3,\$8,2
+ 310:	e2 cd 00 00 	slt3 \$tp,\$gp,0
+
+00000314 <sltu3x>:
+ 314:	b3 cf 02 00 	sltu3 \$sp,\$11,0x2
+ 318:	03 c6 01 00 	sltu3 \$6,\$0,0x1
+ 31c:	b3 c9 03 00 	sltu3 \$9,\$11,0x3
+ 320:	05 64       	sltu3 \$0,\$4,0x0
+ 322:	e3 cd 04 00 	sltu3 \$tp,\$gp,0x4
+
+00000326 <or>:
+ 326:	e0 1f       	or \$sp,\$gp
+ 328:	30 18       	or \$8,\$3
+ 32a:	f0 10       	or \$0,\$sp
+ 32c:	00 1d       	or \$tp,\$0
+ 32e:	60 18       	or \$8,\$6
+
+00000330 <and>:
+ 330:	f1 1f       	and \$sp,\$sp
+ 332:	e1 16       	and \$6,\$gp
+ 334:	21 14       	and \$4,\$2
+ 336:	81 15       	and \$5,\$8
+ 338:	e1 17       	and \$7,\$gp
+
+0000033a <xor>:
+ 33a:	c2 11       	xor \$1,\$12
+ 33c:	d2 1c       	xor \$12,\$tp
+ 33e:	82 1a       	xor \$10,\$8
+ 340:	b2 1f       	xor \$sp,\$11
+ 342:	82 1c       	xor \$12,\$8
+
+00000344 <nor>:
+ 344:	53 19       	nor \$9,\$5
+ 346:	23 18       	nor \$8,\$2
+ 348:	93 1f       	nor \$sp,\$9
+ 34a:	f3 15       	nor \$5,\$sp
+ 34c:	e3 1f       	nor \$sp,\$gp
+
+0000034e <or3>:
+ 34e:	f4 cd 02 00 	or3 \$tp,\$sp,0x2
+ 352:	d4 cf 03 00 	or3 \$sp,\$tp,0x3
+ 356:	a4 c0 04 00 	or3 \$0,\$10,0x4
+ 35a:	f4 c9 03 00 	or3 \$9,\$sp,0x3
+ 35e:	f4 c9 00 00 	or3 \$9,\$sp,0x0
+
+00000362 <and3>:
+ 362:	85 c5 01 00 	and3 \$5,\$8,0x1
+ 366:	e5 cb 03 00 	and3 \$11,\$gp,0x3
+ 36a:	05 c6 00 00 	and3 \$6,\$0,0x0
+ 36e:	f5 cf 00 00 	and3 \$sp,\$sp,0x0
+ 372:	a5 c1 03 00 	and3 \$1,\$10,0x3
+
+00000376 <xor3>:
+ 376:	06 c0 02 00 	xor3 \$0,\$0,0x2
+ 37a:	66 cf 00 00 	xor3 \$sp,\$6,0x0
+ 37e:	56 cd 00 00 	xor3 \$tp,\$5,0x0
+ 382:	76 cf 00 00 	xor3 \$sp,\$7,0x0
+ 386:	f6 cf 02 00 	xor3 \$sp,\$sp,0x2
+
+0000038a <sra>:
+ 38a:	1d 24       	sra \$4,\$1
+ 38c:	fd 28       	sra \$8,\$sp
+ 38e:	1d 21       	sra \$1,\$1
+ 390:	5d 20       	sra \$0,\$5
+ 392:	1d 29       	sra \$9,\$1
+
+00000394 <srl>:
+ 394:	bc 22       	srl \$2,\$11
+ 396:	7c 2f       	srl \$sp,\$7
+ 398:	7c 21       	srl \$1,\$7
+ 39a:	dc 23       	srl \$3,\$tp
+ 39c:	1c 2e       	srl \$gp,\$1
+
+0000039e <sll>:
+ 39e:	0e 2b       	sll \$11,\$0
+ 3a0:	8e 2d       	sll \$tp,\$8
+ 3a2:	9e 28       	sll \$8,\$9
+ 3a4:	fe 2d       	sll \$tp,\$sp
+ 3a6:	fe 2f       	sll \$sp,\$sp
+
+000003a8 <srai>:
+ 3a8:	13 61       	sra \$1,0x2
+ 3aa:	1b 6f       	sra \$sp,0x3
+ 3ac:	1b 6f       	sra \$sp,0x3
+ 3ae:	23 66       	sra \$6,0x4
+ 3b0:	1b 6f       	sra \$sp,0x3
+
+000003b2 <srli>:
+ 3b2:	02 6a       	srl \$10,0x0
+ 3b4:	1a 69       	srl \$9,0x3
+ 3b6:	22 66       	srl \$6,0x4
+ 3b8:	12 6a       	srl \$10,0x2
+ 3ba:	1a 68       	srl \$8,0x3
+
+000003bc <slli>:
+ 3bc:	06 60       	sll \$0,0x0
+ 3be:	06 64       	sll \$4,0x0
+ 3c0:	16 6d       	sll \$tp,0x2
+ 3c2:	16 6b       	sll \$11,0x2
+ 3c4:	06 66       	sll \$6,0x0
+
+000003c6 <sll3>:
+ 3c6:	27 6d       	sll3 \$0,\$tp,0x4
+ 3c8:	07 6e       	sll3 \$0,\$gp,0x0
+ 3ca:	17 68       	sll3 \$0,\$8,0x2
+ 3cc:	17 63       	sll3 \$0,\$3,0x2
+ 3ce:	07 68       	sll3 \$0,\$8,0x0
+
+000003d0 <fsft>:
+ 3d0:	af 2e       	fsft \$gp,\$10
+ 3d2:	9f 2e       	fsft \$gp,\$9
+ 3d4:	df 2f       	fsft \$sp,\$tp
+ 3d6:	3f 2b       	fsft \$11,\$3
+ 3d8:	3f 25       	fsft \$5,\$3
+
+000003da <bra>:
+ 3da:	02 b0       	bra 3dc <bra\+0x2>
+ 3dc:	fe bf       	bra 3da <bra>
+ 3de:	02 b0       	bra 3e0 <bra\+0x6>
+ 3e0:	00 b0       	bra 3e0 <bra\+0x6>
+ 3e2:	02 b0       	bra 3e4 <beqz>
+
+000003e4 <beqz>:
+ 3e4:	fe a1       	beqz \$1,3e2 <bra\+0x8>
+ 3e6:	02 af       	beqz \$sp,3e8 <beqz\+0x4>
+ 3e8:	04 a4       	beqz \$4,3ec <beqz\+0x8>
+ 3ea:	00 a4       	beqz \$4,3ea <beqz\+0x6>
+ 3ec:	fe a9       	beqz \$9,3ea <beqz\+0x6>
+
+000003ee <bnez>:
+ 3ee:	03 a8       	bnez \$8,3f0 <bnez\+0x2>
+ 3f0:	03 ad       	bnez \$tp,3f2 <bnez\+0x4>
+ 3f2:	01 ae       	bnez \$gp,3f2 <bnez\+0x4>
+ 3f4:	03 a6       	bnez \$6,3f6 <bnez\+0x8>
+ 3f6:	fd a8       	bnez \$8,3f2 <bnez\+0x4>
+
+000003f8 <beqi>:
+ 3f8:	30 ed 00 00 	beqi \$tp,0x3,3f8 <beqi>
+ 3fc:	40 e0 ff ff 	beqi \$0,0x4,3fa <beqi\+0x2>
+ 400:	40 ef ff ff 	beqi \$sp,0x4,3fe <beqi\+0x6>
+ 404:	20 ed 00 00 	beqi \$tp,0x2,404 <beqi\+0xc>
+ 408:	20 e4 fc ff 	beqi \$4,0x2,400 <beqi\+0x8>
+
+0000040c <bnei>:
+ 40c:	14 e8 00 00 	bnei \$8,0x1,40c <bnei>
+ 410:	14 e5 01 00 	bnei \$5,0x1,412 <bnei\+0x6>
+ 414:	04 e5 04 00 	bnei \$5,0x0,41c <bnei\+0x10>
+ 418:	44 e9 ff ff 	bnei \$9,0x4,416 <bnei\+0xa>
+ 41c:	44 e0 fc ff 	bnei \$0,0x4,414 <bnei\+0x8>
+
+00000420 <blti>:
+ 420:	3c e7 00 00 	blti \$7,0x3,420 <blti>
+ 424:	1c e1 00 00 	blti \$1,0x1,424 <blti\+0x4>
+ 428:	2c e8 01 00 	blti \$8,0x2,42a <blti\+0xa>
+ 42c:	2c eb 01 00 	blti \$11,0x2,42e <blti\+0xe>
+ 430:	3c ef ff ff 	blti \$sp,0x3,42e <blti\+0xe>
+
+00000434 <bgei>:
+ 434:	38 e4 fc ff 	bgei \$4,0x3,42c <blti\+0xc>
+ 438:	08 e7 01 00 	bgei \$7,0x0,43a <bgei\+0x6>
+ 43c:	18 ed 00 00 	bgei \$tp,0x1,43c <bgei\+0x8>
+ 440:	28 e5 ff ff 	bgei \$5,0x2,43e <bgei\+0xa>
+ 444:	48 ec fc ff 	bgei \$12,0x4,43c <bgei\+0x8>
+
+00000448 <beq>:
+ 448:	21 e7 ff ff 	beq \$7,\$2,446 <bgei\+0x12>
+ 44c:	31 e1 fc ff 	beq \$1,\$3,444 <bgei\+0x10>
+ 450:	01 e2 01 00 	beq \$2,\$0,452 <beq\+0xa>
+ 454:	81 ef 01 00 	beq \$sp,\$8,456 <beq\+0xe>
+ 458:	01 e3 00 00 	beq \$3,\$0,458 <beq\+0x10>
+
+0000045c <bne>:
+ 45c:	35 e6 00 00 	bne \$6,\$3,45c <bne>
+ 460:	35 ef fc ff 	bne \$sp,\$3,458 <beq\+0x10>
+ 464:	05 e8 01 00 	bne \$8,\$0,466 <bne\+0xa>
+ 468:	f5 ee 04 00 	bne \$gp,\$sp,470 <bsr12>
+ 46c:	45 ef 01 00 	bne \$sp,\$4,46e <bne\+0x12>
+
+00000470 <bsr12>:
+ 470:	03 b0       	bsr 472 <bsr12\+0x2>
+ 472:	f9 bf       	bsr 46a <bne\+0xe>
+ 474:	f1 bf       	bsr 464 <bne\+0x8>
+ 476:	ff bf       	bsr 474 <bsr12\+0x4>
+ 478:	f9 bf       	bsr 470 <bsr12>
+
+0000047a <bsr24>:
+ 47a:	05 b0       	bsr 47e <bsr24\+0x4>
+ 47c:	ff bf       	bsr 47a <bsr24>
+ 47e:	fd bf       	bsr 47a <bsr24>
+ 480:	01 b0       	bsr 480 <bsr24\+0x6>
+ 482:	03 b0       	bsr 484 <jmp>
+
+00000484 <jmp>:
+ 484:	2e 10       	jmp \$2
+ 486:	de 10       	jmp \$tp
+ 488:	5e 10       	jmp \$5
+ 48a:	fe 10       	jmp \$sp
+ 48c:	8e 10       	jmp \$8
+
+0000048e <jmp24>:
+ 48e:	28 d8 00 00 	jmp 4 <sb\+0x4>
+ 492:	18 d8 00 00 	jmp 2 <sb\+0x2>
+ 496:	08 d8 00 00 	jmp 0 <sb>
+ 49a:	18 d8 00 00 	jmp 2 <sb\+0x2>
+ 49e:	28 d8 00 00 	jmp 4 <sb\+0x4>
+
+000004a2 <jsr>:
+ 4a2:	ff 10       	jsr \$sp
+ 4a4:	df 10       	jsr \$tp
+ 4a6:	df 10       	jsr \$tp
+ 4a8:	6f 10       	jsr \$6
+ 4aa:	6f 10       	jsr \$6
+
+000004ac <ret>:
+ 4ac:	02 70       	ret
+
+000004ae <repeat>:
+ 4ae:	09 e4 01 00 	repeat \$4,4b0 <repeat\+0x2>
+ 4b2:	09 e8 02 00 	repeat \$8,4b6 <repeat\+0x8>
+ 4b6:	09 e0 04 00 	repeat \$0,4be <repeat\+0x10>
+ 4ba:	09 e6 01 00 	repeat \$6,4bc <repeat\+0xe>
+ 4be:	09 e4 01 00 	repeat \$4,4c0 <repeat\+0x12>
+
+000004c2 <erepeat>:
+ 4c2:	19 e0 01 00 	erepeat 4c4 <erepeat\+0x2>
+ 4c6:	19 e0 00 00 	erepeat 4c6 <erepeat\+0x4>
+ 4ca:	19 e0 01 00 	erepeat 4cc <erepeat\+0xa>
+ 4ce:	19 e0 ff ff 	erepeat 4cc <erepeat\+0xa>
+ 4d2:	19 e0 00 00 	erepeat 4d2 <erepeat\+0x10>
+
+000004d6 <stc>:
+ 4d6:	e8 7d       	stc \$tp,\$mb1
+ 4d8:	c9 7d       	stc \$tp,\$ccfg
+ 4da:	89 7b       	stc \$11,\$dbg
+ 4dc:	c9 7a       	stc \$10,\$ccfg
+ 4de:	39 79       	stc \$9,\$epc
+
+000004e0 <ldc>:
+ 4e0:	8a 7d       	ldc \$tp,\$lo
+ 4e2:	7b 78       	ldc \$8,\$npc
+ 4e4:	ca 79       	ldc \$9,\$mb0
+ 4e6:	2a 7f       	ldc \$sp,\$sar
+ 4e8:	cb 79       	ldc \$9,\$ccfg
+
+000004ea <di>:
+ 4ea:	00 70       	di
+
+000004ec <ei>:
+ 4ec:	10 70       	ei
+
+000004ee <reti>:
+ 4ee:	12 70       	reti
+
+000004f0 <halt>:
+ 4f0:	22 70       	halt
+
+000004f2 <swi>:
+ 4f2:	26 70       	swi 0x2
+ 4f4:	06 70       	swi 0x0
+ 4f6:	26 70       	swi 0x2
+ 4f8:	36 70       	swi 0x3
+ 4fa:	16 70       	swi 0x1
+
+000004fc <break>:
+ 4fc:	32 70       	break
+
+000004fe <syncm>:
+ 4fe:	11 70       	syncm
+
+00000500 <stcb>:
+ 500:	04 f5 04 00 	stcb \$5,0x4
+ 504:	04 f5 01 00 	stcb \$5,0x1
+ 508:	04 fe 00 00 	stcb \$gp,0x0
+ 50c:	04 ff 04 00 	stcb \$sp,0x4
+ 510:	04 fb 02 00 	stcb \$11,0x2
+
+00000514 <ldcb>:
+ 514:	14 f2 03 00 	ldcb \$2,0x3
+ 518:	14 f2 04 00 	ldcb \$2,0x4
+ 51c:	14 f9 01 00 	ldcb \$9,0x1
+ 520:	14 fa 04 00 	ldcb \$10,0x4
+ 524:	14 f1 04 00 	ldcb \$1,0x4
+
+00000528 <bsetm>:
+ 528:	a0 20       	bsetm \(\$10\),0x0
+ 52a:	f0 20       	bsetm \(\$sp\),0x0
+ 52c:	10 22       	bsetm \(\$1\),0x2
+ 52e:	f0 24       	bsetm \(\$sp\),0x4
+ 530:	80 24       	bsetm \(\$8\),0x4
+
+00000532 <bclrm>:
+ 532:	51 20       	bclrm \(\$5\),0x0
+ 534:	51 22       	bclrm \(\$5\),0x2
+ 536:	81 20       	bclrm \(\$8\),0x0
+ 538:	91 22       	bclrm \(\$9\),0x2
+ 53a:	51 23       	bclrm \(\$5\),0x3
+
+0000053c <bnotm>:
+ 53c:	e2 24       	bnotm \(\$gp\),0x4
+ 53e:	b2 24       	bnotm \(\$11\),0x4
+ 540:	a2 20       	bnotm \(\$10\),0x0
+ 542:	d2 24       	bnotm \(\$tp\),0x4
+ 544:	82 20       	bnotm \(\$8\),0x0
+
+00000546 <btstm>:
+ 546:	e3 20       	btstm \$0,\(\$gp\),0x0
+ 548:	e3 21       	btstm \$0,\(\$gp\),0x1
+ 54a:	b3 20       	btstm \$0,\(\$11\),0x0
+ 54c:	e3 23       	btstm \$0,\(\$gp\),0x3
+ 54e:	83 22       	btstm \$0,\(\$8\),0x2
+
+00000550 <tas>:
+ 550:	d4 27       	tas \$7,\(\$tp\)
+ 552:	c4 27       	tas \$7,\(\$12\)
+ 554:	84 23       	tas \$3,\(\$8\)
+ 556:	54 22       	tas \$2,\(\$5\)
+ 558:	a4 26       	tas \$6,\(\$10\)
+
+0000055a <cache>:
+ 55a:	d4 71       	cache 0x1,\(\$tp\)
+ 55c:	c4 73       	cache 0x3,\(\$12\)
+ 55e:	94 73       	cache 0x3,\(\$9\)
+ 560:	24 74       	cache 0x4,\(\$2\)
+ 562:	74 74       	cache 0x4,\(\$7\)
+
+00000564 <mul>:
+ 564:	e4 18       	mul \$8,\$gp
+ 566:	94 12       	mul \$2,\$9
+ 568:	f4 1e       	mul \$gp,\$sp
+ 56a:	74 19       	mul \$9,\$7
+ 56c:	b4 17       	mul \$7,\$11
+
+0000056e <mulu>:
+ 56e:	55 12       	mulu \$2,\$5
+ 570:	e5 16       	mulu \$6,\$gp
+ 572:	f5 1e       	mulu \$gp,\$sp
+ 574:	e5 1b       	mulu \$11,\$gp
+ 576:	95 13       	mulu \$3,\$9
+
+00000578 <mulr>:
+ 578:	66 1c       	mulr \$12,\$6
+ 57a:	86 1d       	mulr \$tp,\$8
+ 57c:	a6 17       	mulr \$7,\$10
+ 57e:	16 1e       	mulr \$gp,\$1
+ 580:	f6 10       	mulr \$0,\$sp
+
+00000582 <mulru>:
+ 582:	27 14       	mulru \$4,\$2
+ 584:	17 1e       	mulru \$gp,\$1
+ 586:	47 1f       	mulru \$sp,\$4
+ 588:	67 1a       	mulru \$10,\$6
+ 58a:	e7 10       	mulru \$0,\$gp
+
+0000058c <madd>:
+ 58c:	b1 f4 04 30 	madd \$4,\$11
+ 590:	e1 ff 04 30 	madd \$sp,\$gp
+ 594:	f1 fe 04 30 	madd \$gp,\$sp
+ 598:	d1 f4 04 30 	madd \$4,\$tp
+ 59c:	e1 f1 04 30 	madd \$1,\$gp
+
+000005a0 <maddu>:
+ 5a0:	11 f0 05 30 	maddu \$0,\$1
+ 5a4:	61 f7 05 30 	maddu \$7,\$6
+ 5a8:	51 f9 05 30 	maddu \$9,\$5
+ 5ac:	f1 fe 05 30 	maddu \$gp,\$sp
+ 5b0:	d1 f7 05 30 	maddu \$7,\$tp
+
+000005b4 <maddr>:
+ 5b4:	81 f6 06 30 	maddr \$6,\$8
+ 5b8:	e1 f9 06 30 	maddr \$9,\$gp
+ 5bc:	e1 f8 06 30 	maddr \$8,\$gp
+ 5c0:	21 f3 06 30 	maddr \$3,\$2
+ 5c4:	b1 f1 06 30 	maddr \$1,\$11
+
+000005c8 <maddru>:
+ 5c8:	31 fa 07 30 	maddru \$10,\$3
+ 5cc:	c1 ff 07 30 	maddru \$sp,\$12
+ 5d0:	81 f8 07 30 	maddru \$8,\$8
+ 5d4:	31 fe 07 30 	maddru \$gp,\$3
+ 5d8:	f1 f8 07 30 	maddru \$8,\$sp
+
+000005dc <div>:
+ 5dc:	38 19       	div \$9,\$3
+ 5de:	e8 14       	div \$4,\$gp
+ 5e0:	c8 12       	div \$2,\$12
+ 5e2:	d8 18       	div \$8,\$tp
+ 5e4:	68 1d       	div \$tp,\$6
+
+000005e6 <divu>:
+ 5e6:	59 19       	divu \$9,\$5
+ 5e8:	d9 18       	divu \$8,\$tp
+ 5ea:	e9 10       	divu \$0,\$gp
+ 5ec:	59 19       	divu \$9,\$5
+ 5ee:	59 10       	divu \$0,\$5
+
+000005f0 <dret>:
+ 5f0:	13 70       	dret
+
+000005f2 <dbreak>:
+ 5f2:	33 70       	dbreak
+
+000005f4 <ldz>:
+ 5f4:	41 fe 00 00 	ldz \$gp,\$4
+ 5f8:	b1 fa 00 00 	ldz \$10,\$11
+ 5fc:	91 f9 00 00 	ldz \$9,\$9
+ 600:	d1 ff 00 00 	ldz \$sp,\$tp
+ 604:	31 fe 00 00 	ldz \$gp,\$3
+
+00000608 <abs>:
+ 608:	91 ff 03 00 	abs \$sp,\$9
+ 60c:	41 f5 03 00 	abs \$5,\$4
+ 610:	d1 fd 03 00 	abs \$tp,\$tp
+ 614:	31 f0 03 00 	abs \$0,\$3
+ 618:	e1 f3 03 00 	abs \$3,\$gp
+
+0000061c <ave>:
+ 61c:	a1 fb 02 00 	ave \$11,\$10
+ 620:	a1 f8 02 00 	ave \$8,\$10
+ 624:	21 fe 02 00 	ave \$gp,\$2
+ 628:	c1 fa 02 00 	ave \$10,\$12
+ 62c:	81 ff 02 00 	ave \$sp,\$8
+
+00000630 <min>:
+ 630:	31 f8 04 00 	min \$8,\$3
+ 634:	01 f7 04 00 	min \$7,\$0
+ 638:	21 f2 04 00 	min \$2,\$2
+ 63c:	61 f5 04 00 	min \$5,\$6
+ 640:	51 fb 04 00 	min \$11,\$5
+
+00000644 <max>:
+ 644:	f1 fb 05 00 	max \$11,\$sp
+ 648:	01 fe 05 00 	max \$gp,\$0
+ 64c:	f1 fc 05 00 	max \$12,\$sp
+ 650:	21 fe 05 00 	max \$gp,\$2
+ 654:	f1 fe 05 00 	max \$gp,\$sp
+
+00000658 <minu>:
+ 658:	81 fb 06 00 	minu \$11,\$8
+ 65c:	51 f7 06 00 	minu \$7,\$5
+ 660:	e1 f8 06 00 	minu \$8,\$gp
+ 664:	41 fb 06 00 	minu \$11,\$4
+ 668:	f1 f2 06 00 	minu \$2,\$sp
+
+0000066c <maxu>:
+ 66c:	31 f3 07 00 	maxu \$3,\$3
+ 670:	01 fd 07 00 	maxu \$tp,\$0
+ 674:	81 f4 07 00 	maxu \$4,\$8
+ 678:	21 fe 07 00 	maxu \$gp,\$2
+ 67c:	81 fc 07 00 	maxu \$12,\$8
+
+00000680 <clip>:
+ 680:	01 fa 08 10 	clip \$10,0x1
+ 684:	01 ff 20 10 	clip \$sp,0x4
+ 688:	01 f4 18 10 	clip \$4,0x3
+ 68c:	01 ff 18 10 	clip \$sp,0x3
+ 690:	01 f1 00 10 	clip \$1,0x0
+
+00000694 <clipu>:
+ 694:	01 fa 21 10 	clipu \$10,0x4
+ 698:	01 fd 09 10 	clipu \$tp,0x1
+ 69c:	01 f5 21 10 	clipu \$5,0x4
+ 6a0:	01 fe 01 10 	clipu \$gp,0x0
+ 6a4:	01 f5 09 10 	clipu \$5,0x1
+
+000006a8 <sadd>:
+ 6a8:	01 f5 08 00 	sadd \$5,\$0
+ 6ac:	31 ff 08 00 	sadd \$sp,\$3
+ 6b0:	a1 f0 08 00 	sadd \$0,\$10
+ 6b4:	c1 ff 08 00 	sadd \$sp,\$12
+ 6b8:	21 f4 08 00 	sadd \$4,\$2
+
+000006bc <ssub>:
+ 6bc:	a1 f1 0a 00 	ssub \$1,\$10
+ 6c0:	71 f4 0a 00 	ssub \$4,\$7
+ 6c4:	31 f8 0a 00 	ssub \$8,\$3
+ 6c8:	e1 f7 0a 00 	ssub \$7,\$gp
+ 6cc:	41 fd 0a 00 	ssub \$tp,\$4
+
+000006d0 <saddu>:
+ 6d0:	e1 f9 09 00 	saddu \$9,\$gp
+ 6d4:	a1 f0 09 00 	saddu \$0,\$10
+ 6d8:	c1 f7 09 00 	saddu \$7,\$12
+ 6dc:	f1 f5 09 00 	saddu \$5,\$sp
+ 6e0:	31 fd 09 00 	saddu \$tp,\$3
+
+000006e4 <ssubu>:
+ 6e4:	e1 ff 0b 00 	ssubu \$sp,\$gp
+ 6e8:	f1 f0 0b 00 	ssubu \$0,\$sp
+ 6ec:	a1 f3 0b 00 	ssubu \$3,\$10
+ 6f0:	d1 ff 0b 00 	ssubu \$sp,\$tp
+ 6f4:	91 f2 0b 00 	ssubu \$2,\$9
+
+000006f8 <swcp>:
+ 6f8:	d8 33       	swcp \$c3,\(\$tp\)
+ 6fa:	d8 3f       	swcp \$c15,\(\$tp\)
+ 6fc:	08 3d       	swcp \$c13,\(\$0\)
+ 6fe:	c8 3c       	swcp \$c12,\(\$12\)
+ 700:	e8 39       	swcp \$c9,\(\$gp\)
+
+00000702 <lwcp>:
+ 702:	39 37       	lwcp \$c7,\(\$3\)
+ 704:	39 36       	lwcp \$c6,\(\$3\)
+ 706:	29 30       	lwcp \$c0,\(\$2\)
+ 708:	89 38       	lwcp \$c8,\(\$8\)
+ 70a:	d9 3b       	lwcp \$c11,\(\$tp\)
+
+0000070c <smcp>:
+ 70c:	9a 3e       	smcp \$c14,\(\$9\)
+ 70e:	8a 32       	smcp \$c2,\(\$8\)
+ 710:	fa 3e       	smcp \$c14,\(\$sp\)
+ 712:	8a 3a       	smcp \$c10,\(\$8\)
+ 714:	8a 32       	smcp \$c2,\(\$8\)
+
+00000716 <lmcp>:
+ 716:	1b 3b       	lmcp \$c11,\(\$1\)
+ 718:	8b 38       	lmcp \$c8,\(\$8\)
+ 71a:	db 3b       	lmcp \$c11,\(\$tp\)
+ 71c:	0b 38       	lmcp \$c8,\(\$0\)
+ 71e:	eb 38       	lmcp \$c8,\(\$gp\)
+
+00000720 <swcpi>:
+ 720:	00 37       	swcpi \$c7,\(\$0\+\)
+ 722:	e0 36       	swcpi \$c6,\(\$gp\+\)
+ 724:	80 3c       	swcpi \$c12,\(\$8\+\)
+ 726:	f0 3e       	swcpi \$c14,\(\$sp\+\)
+ 728:	00 36       	swcpi \$c6,\(\$0\+\)
+
+0000072a <lwcpi>:
+ 72a:	21 38       	lwcpi \$c8,\(\$2\+\)
+ 72c:	01 39       	lwcpi \$c9,\(\$0\+\)
+ 72e:	e1 33       	lwcpi \$c3,\(\$gp\+\)
+ 730:	51 3d       	lwcpi \$c13,\(\$5\+\)
+ 732:	e1 3b       	lwcpi \$c11,\(\$gp\+\)
+
+00000734 <smcpi>:
+ 734:	22 38       	smcpi \$c8,\(\$2\+\)
+ 736:	92 3b       	smcpi \$c11,\(\$9\+\)
+ 738:	32 34       	smcpi \$c4,\(\$3\+\)
+ 73a:	22 3e       	smcpi \$c14,\(\$2\+\)
+ 73c:	32 39       	smcpi \$c9,\(\$3\+\)
+
+0000073e <lmcpi>:
+ 73e:	e3 36       	lmcpi \$c6,\(\$gp\+\)
+ 740:	53 39       	lmcpi \$c9,\(\$5\+\)
+ 742:	63 3a       	lmcpi \$c10,\(\$6\+\)
+ 744:	63 31       	lmcpi \$c1,\(\$6\+\)
+ 746:	83 32       	lmcpi \$c2,\(\$8\+\)
+
+00000748 <swcp16>:
+ 748:	2c f0 ff ff 	swcp \$c0,-1\(\$2\)
+ 74c:	ac f5 01 00 	swcp \$c5,1\(\$10\)
+ 750:	cc f8 02 00 	swcp \$c8,2\(\$12\)
+ 754:	1c fe ff ff 	swcp \$c14,-1\(\$1\)
+ 758:	3c fc 02 00 	swcp \$c12,2\(\$3\)
+
+0000075c <lwcp16>:
+ 75c:	5d f8 ff ff 	lwcp \$c8,-1\(\$5\)
+ 760:	fd fc 01 00 	lwcp \$c12,1\(\$sp\)
+ 764:	0d f1 02 00 	lwcp \$c1,2\(\$0\)
+ 768:	dd f4 01 00 	lwcp \$c4,1\(\$tp\)
+ 76c:	bd f6 02 00 	lwcp \$c6,2\(\$11\)
+
+00000770 <smcp16>:
+ 770:	ae f9 ff ff 	smcp \$c9,-1\(\$10\)
+ 774:	ee fe 01 00 	smcp \$c14,1\(\$gp\)
+ 778:	fe f3 02 00 	smcp \$c3,2\(\$sp\)
+ 77c:	8e ff fe ff 	smcp \$c15,-2\(\$8\)
+ 780:	de fd 01 00 	smcp \$c13,1\(\$tp\)
+
+00000784 <lmcp16>:
+ 784:	ff f0 01 00 	lmcp \$c0,1\(\$sp\)
+ 788:	8f ff 01 00 	lmcp \$c15,1\(\$8\)
+ 78c:	8f f2 ff ff 	lmcp \$c2,-1\(\$8\)
+ 790:	8f fe 01 00 	lmcp \$c14,1\(\$8\)
+ 794:	af f1 ff ff 	lmcp \$c1,-1\(\$10\)
+
+00000798 <sbcpa>:
+ 798:	f5 fe 02 00 	sbcpa \$c14,\(\$sp\+\),2
+ 79c:	45 f2 fe 00 	sbcpa \$c2,\(\$4\+\),-2
+ 7a0:	15 f8 00 00 	sbcpa \$c8,\(\$1\+\),0
+ 7a4:	35 fb 00 00 	sbcpa \$c11,\(\$3\+\),0
+ 7a8:	e5 f9 fe 00 	sbcpa \$c9,\(\$gp\+\),-2
+
+000007ac <lbcpa>:
+ 7ac:	25 f7 fe 40 	lbcpa \$c7,\(\$2\+\),-2
+ 7b0:	f5 fc 02 40 	lbcpa \$c12,\(\$sp\+\),2
+ 7b4:	45 f5 fe 40 	lbcpa \$c5,\(\$4\+\),-2
+ 7b8:	45 f7 fe 40 	lbcpa \$c7,\(\$4\+\),-2
+ 7bc:	f5 f8 00 40 	lbcpa \$c8,\(\$sp\+\),0
+
+000007c0 <shcpa>:
+ 7c0:	e5 f0 00 10 	shcpa \$c0,\(\$gp\+\),0
+ 7c4:	f5 fc 10 10 	shcpa \$c12,\(\$sp\+\),16
+ 7c8:	45 f1 04 10 	shcpa \$c1,\(\$4\+\),4
+ 7cc:	45 f5 e0 10 	shcpa \$c5,\(\$4\+\),-32
+ 7d0:	f5 f1 00 10 	shcpa \$c1,\(\$sp\+\),0
+
+000007d4 <lhcpa>:
+ 7d4:	45 f4 00 50 	lhcpa \$c4,\(\$4\+\),0
+ 7d8:	55 f6 30 50 	lhcpa \$c6,\(\$5\+\),48
+ 7dc:	65 f3 cc 50 	lhcpa \$c3,\(\$6\+\),-52
+ 7e0:	65 f8 e8 50 	lhcpa \$c8,\(\$6\+\),-24
+ 7e4:	95 f0 00 50 	lhcpa \$c0,\(\$9\+\),0
+
+000007e8 <swcpa>:
+ 7e8:	95 f1 10 20 	swcpa \$c1,\(\$9\+\),16
+ 7ec:	f5 f7 20 20 	swcpa \$c7,\(\$sp\+\),32
+ 7f0:	c5 f3 30 20 	swcpa \$c3,\(\$12\+\),48
+ 7f4:	95 fa 08 20 	swcpa \$c10,\(\$9\+\),8
+ 7f8:	85 fe 04 20 	swcpa \$c14,\(\$8\+\),4
+
+000007fc <lwcpa>:
+ 7fc:	e5 f6 f8 60 	lwcpa \$c6,\(\$gp\+\),-8
+ 800:	75 f4 04 60 	lwcpa \$c4,\(\$7\+\),4
+ 804:	e5 fb f0 60 	lwcpa \$c11,\(\$gp\+\),-16
+ 808:	f5 fa e0 60 	lwcpa \$c10,\(\$sp\+\),-32
+ 80c:	25 f2 08 60 	lwcpa \$c2,\(\$2\+\),8
+
+00000810 <smcpa>:
+ 810:	f5 fd f8 30 	smcpa \$c13,\(\$sp\+\),-8
+ 814:	75 f6 f8 30 	smcpa \$c6,\(\$7\+\),-8
+ 818:	35 f5 10 30 	smcpa \$c5,\(\$3\+\),16
+ 81c:	f5 fd 10 30 	smcpa \$c13,\(\$sp\+\),16
+ 820:	c5 f3 30 30 	smcpa \$c3,\(\$12\+\),48
+
+00000824 <lmcpa>:
+ 824:	45 f9 00 70 	lmcpa \$c9,\(\$4\+\),0
+ 828:	f5 f3 f0 70 	lmcpa \$c3,\(\$sp\+\),-16
+ 82c:	d5 ff 08 70 	lmcpa \$c15,\(\$tp\+\),8
+ 830:	85 f8 f8 70 	lmcpa \$c8,\(\$8\+\),-8
+ 834:	95 fa 00 70 	lmcpa \$c10,\(\$9\+\),0
+
+00000838 <sbcpm0>:
+ 838:	d5 fa 08 08 	sbcpm0 \$c10,\(\$tp\+\),8
+ 83c:	55 fd f8 08 	sbcpm0 \$c13,\(\$5\+\),-8
+ 840:	55 f4 f8 08 	sbcpm0 \$c4,\(\$5\+\),-8
+ 844:	d5 fa 10 08 	sbcpm0 \$c10,\(\$tp\+\),16
+ 848:	55 f4 e8 08 	sbcpm0 \$c4,\(\$5\+\),-24
+
+0000084c <lbcpm0>:
+ 84c:	45 f0 00 48 	lbcpm0 \$c0,\(\$4\+\),0
+ 850:	75 f9 f8 48 	lbcpm0 \$c9,\(\$7\+\),-8
+ 854:	85 fc 18 48 	lbcpm0 \$c12,\(\$8\+\),24
+ 858:	c5 f8 10 48 	lbcpm0 \$c8,\(\$12\+\),16
+ 85c:	85 f7 10 48 	lbcpm0 \$c7,\(\$8\+\),16
+
+00000860 <shcpm0>:
+ 860:	d5 f2 02 18 	shcpm0 \$c2,\(\$tp\+\),2
+ 864:	f5 f7 fe 18 	shcpm0 \$c7,\(\$sp\+\),-2
+ 868:	25 f8 02 18 	shcpm0 \$c8,\(\$2\+\),2
+ 86c:	55 fd 00 18 	shcpm0 \$c13,\(\$5\+\),0
+ 870:	e5 f3 08 18 	shcpm0 \$c3,\(\$gp\+\),8
+
+00000874 <lhcpm0>:
+ 874:	45 f7 08 58 	lhcpm0 \$c7,\(\$4\+\),8
+ 878:	35 f3 fe 58 	lhcpm0 \$c3,\(\$3\+\),-2
+ 87c:	15 f3 00 58 	lhcpm0 \$c3,\(\$1\+\),0
+ 880:	e5 f2 00 58 	lhcpm0 \$c2,\(\$gp\+\),0
+ 884:	65 fc 02 58 	lhcpm0 \$c12,\(\$6\+\),2
+
+00000888 <swcpm0>:
+ 888:	85 f8 20 28 	swcpm0 \$c8,\(\$8\+\),32
+ 88c:	f5 f9 00 28 	swcpm0 \$c9,\(\$sp\+\),0
+ 890:	25 f9 f0 28 	swcpm0 \$c9,\(\$2\+\),-16
+ 894:	e5 f0 30 28 	swcpm0 \$c0,\(\$gp\+\),48
+ 898:	15 ff 08 28 	swcpm0 \$c15,\(\$1\+\),8
+
+0000089c <lwcpm0>:
+ 89c:	a5 fe fc 68 	lwcpm0 \$c14,\(\$10\+\),-4
+ 8a0:	f5 fb fc 68 	lwcpm0 \$c11,\(\$sp\+\),-4
+ 8a4:	75 f5 f8 68 	lwcpm0 \$c5,\(\$7\+\),-8
+ 8a8:	c5 f2 20 68 	lwcpm0 \$c2,\(\$12\+\),32
+ 8ac:	e5 f2 10 68 	lwcpm0 \$c2,\(\$gp\+\),16
+
+000008b0 <smcpm0>:
+ 8b0:	c5 f1 08 38 	smcpm0 \$c1,\(\$12\+\),8
+ 8b4:	45 f8 f0 38 	smcpm0 \$c8,\(\$4\+\),-16
+ 8b8:	b5 fa 00 38 	smcpm0 \$c10,\(\$11\+\),0
+ 8bc:	35 f1 f0 38 	smcpm0 \$c1,\(\$3\+\),-16
+ 8c0:	f5 fb f8 38 	smcpm0 \$c11,\(\$sp\+\),-8
+
+000008c4 <lmcpm0>:
+ 8c4:	a5 fe 00 78 	lmcpm0 \$c14,\(\$10\+\),0
+ 8c8:	f5 f6 f0 78 	lmcpm0 \$c6,\(\$sp\+\),-16
+ 8cc:	15 fd 08 78 	lmcpm0 \$c13,\(\$1\+\),8
+ 8d0:	d5 fa e8 78 	lmcpm0 \$c10,\(\$tp\+\),-24
+ 8d4:	e5 f7 e8 78 	lmcpm0 \$c7,\(\$gp\+\),-24
+
+000008d8 <sbcpm1>:
+ 8d8:	85 f9 00 0c 	sbcpm1 \$c9,\(\$8\+\),0
+ 8dc:	c5 f7 e8 0c 	sbcpm1 \$c7,\(\$12\+\),-24
+ 8e0:	55 ff e8 0c 	sbcpm1 \$c15,\(\$5\+\),-24
+ 8e4:	d5 f5 10 0c 	sbcpm1 \$c5,\(\$tp\+\),16
+ 8e8:	15 f6 80 0c 	sbcpm1 \$c6,\(\$1\+\),-128
+
+000008ec <lbcpm1>:
+ 8ec:	e5 f6 02 4c 	lbcpm1 \$c6,\(\$gp\+\),2
+ 8f0:	d5 f7 fe 4c 	lbcpm1 \$c7,\(\$tp\+\),-2
+ 8f4:	d5 f4 01 4c 	lbcpm1 \$c4,\(\$tp\+\),1
+ 8f8:	25 fc fe 4c 	lbcpm1 \$c12,\(\$2\+\),-2
+ 8fc:	75 fb 01 4c 	lbcpm1 \$c11,\(\$7\+\),1
+
+00000900 <shcpm1>:
+ 900:	85 f4 18 1c 	shcpm1 \$c4,\(\$8\+\),24
+ 904:	65 fb f0 1c 	shcpm1 \$c11,\(\$6\+\),-16
+ 908:	85 f7 08 1c 	shcpm1 \$c7,\(\$8\+\),8
+ 90c:	c5 f5 10 1c 	shcpm1 \$c5,\(\$12\+\),16
+ 910:	85 f0 e0 1c 	shcpm1 \$c0,\(\$8\+\),-32
+
+00000914 <lhcpm1>:
+ 914:	05 fb 00 5c 	lhcpm1 \$c11,\(\$0\+\),0
+ 918:	d5 f7 fe 5c 	lhcpm1 \$c7,\(\$tp\+\),-2
+ 91c:	85 fa 08 5c 	lhcpm1 \$c10,\(\$8\+\),8
+ 920:	d5 f3 00 5c 	lhcpm1 \$c3,\(\$tp\+\),0
+ 924:	65 f9 02 5c 	lhcpm1 \$c9,\(\$6\+\),2
+
+00000928 <swcpm1>:
+ 928:	85 f9 18 2c 	swcpm1 \$c9,\(\$8\+\),24
+ 92c:	e5 f9 00 2c 	swcpm1 \$c9,\(\$gp\+\),0
+ 930:	85 f9 10 2c 	swcpm1 \$c9,\(\$8\+\),16
+ 934:	15 fe 00 2c 	swcpm1 \$c14,\(\$1\+\),0
+ 938:	f5 f2 08 2c 	swcpm1 \$c2,\(\$sp\+\),8
+
+0000093c <lwcpm1>:
+ 93c:	85 f8 00 6c 	lwcpm1 \$c8,\(\$8\+\),0
+ 940:	e5 f3 f0 6c 	lwcpm1 \$c3,\(\$gp\+\),-16
+ 944:	65 f7 f8 6c 	lwcpm1 \$c7,\(\$6\+\),-8
+ 948:	85 fe e8 6c 	lwcpm1 \$c14,\(\$8\+\),-24
+ 94c:	85 f3 18 6c 	lwcpm1 \$c3,\(\$8\+\),24
+
+00000950 <smcpm1>:
+ 950:	45 fa 00 3c 	smcpm1 \$c10,\(\$4\+\),0
+ 954:	f5 f6 f0 3c 	smcpm1 \$c6,\(\$sp\+\),-16
+ 958:	75 fd e8 3c 	smcpm1 \$c13,\(\$7\+\),-24
+ 95c:	e5 f3 f8 3c 	smcpm1 \$c3,\(\$gp\+\),-8
+ 960:	25 f0 08 3c 	smcpm1 \$c0,\(\$2\+\),8
+
+00000964 <lmcpm1>:
+ 964:	15 fc 00 7c 	lmcpm1 \$c12,\(\$1\+\),0
+ 968:	65 f0 08 7c 	lmcpm1 \$c0,\(\$6\+\),8
+ 96c:	25 f6 f8 7c 	lmcpm1 \$c6,\(\$2\+\),-8
+ 970:	e5 fc f0 7c 	lmcpm1 \$c12,\(\$gp\+\),-16
+ 974:	f5 fe 30 7c 	lmcpm1 \$c14,\(\$sp\+\),48
+
+00000... <bcpeq>:
+ ...:	44 d8 00 00 	bcpeq 0x4,... <bcpeq>
+ ...:	04 d8 ff ff 	bcpeq 0x0,... <bcpeq\+0x2>
+ ...:	44 d8 ff ff 	bcpeq 0x4,... <bcpeq\+0x6>
+ ...:	14 d8 01 00 	bcpeq 0x1,... <bcpeq\+0xe>
+ ...:	24 d8 01 00 	bcpeq 0x2,... <bcpeq\+0x12>
+
+00000... <bcpne>:
+ ...:	25 d8 00 00 	bcpne 0x2,... <bcpne>
+ ...:	45 d8 00 00 	bcpne 0x4,... <bcpne\+0x4>
+ ...:	15 d8 00 00 	bcpne 0x1,... <bcpne\+0x8>
+ ...:	45 d8 00 00 	bcpne 0x4,... <bcpne\+0xc>
+ ...:	15 d8 01 00 	bcpne 0x1,... <bcpne\+0x12>
+
+00000... <bcpat>:
+ ...:	16 d8 ff ff 	bcpat 0x1,... <bcpne\+0x12>
+ ...:	06 d8 01 00 	bcpat 0x0,... <bcpat\+0x6>
+ ...:	06 d8 ff ff 	bcpat 0x0,... <bcpat\+0x6>
+ ...:	26 d8 00 00 	bcpat 0x2,... <bcpat\+0xc>
+ ...:	16 d8 ff ff 	bcpat 0x1,... <bcpat\+0xe>
+
+00000... <bcpaf>:
+ ...:	47 d8 00 00 	bcpaf 0x4,... <bcpaf>
+ ...:	37 d8 00 00 	bcpaf 0x3,... <bcpaf\+0x4>
+ ...:	47 d8 00 00 	bcpaf 0x4,... <bcpaf\+0x8>
+ ...:	17 d8 01 00 	bcpaf 0x1,... <bcpaf\+0xe>
+ ...:	47 d8 01 00 	bcpaf 0x4,... <bcpaf\+0x12>
+
+00000... <synccp>:
+ ...:	21 70       	synccp
+
+00000... <jsrv>:
+ ...:	bf 18       	jsrv \$11
+ ...:	5f 18       	jsrv \$5
+ ...:	af 18       	jsrv \$10
+ ...:	cf 18       	jsrv \$12
+ ...:	af 18       	jsrv \$10
+
+00000... <bsrv>:
+ ...:	fb df ff ff 	bsrv ... <jsrv\+0x8>
+ ...:	fb df ff ff 	bsrv ... <bsrv\+0x2>
+ ...:	fb df ff ff 	bsrv ... <bsrv\+0x6>
+ ...:	1b d8 00 00 	bsrv ... <bsrv\+0xe>
+ ...:	0b d8 00 00 	bsrv ... <bsrv\+0x10>
+
+00000... <case106341>:
+ ...:	78 7a       	stc \$10,\$hi
+ ...:	8a 70       	ldc \$0,\$lo
+
+00000... <case106821>:
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	08 00       	sb \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	09 00       	sh \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0a 00       	sw \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0c 00       	lb \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0d 00       	lh \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0e 00       	lw \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0b 00       	lbu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	0f 00       	lhu \$0,\(\$0\)
+ ...:	08 c0 01 00 	sb \$0,1\(\$0\)
+ ...:	08 c0 01 00 	sb \$0,1\(\$0\)
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+ ...:	08 c0 01 00 	sb \$0,1\(\$0\)
+ ...:	08 c0 01 00 	sb \$0,1\(\$0\)
+ ...:	09 c0 01 00 	sh \$0,1\(\$0\)
+ ...:	09 c0 01 00 	sh \$0,1\(\$0\)
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+ ...:	09 c0 01 00 	sh \$0,1\(\$0\)
+ ...:	09 c0 01 00 	sh \$0,1\(\$0\)
+ ...:	0a c0 01 00 	sw \$0,1\(\$0\)
+ ...:	0a c0 01 00 	sw \$0,1\(\$0\)
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+ ...:	0a c0 01 00 	sw \$0,1\(\$0\)
+ ...:	0a c0 01 00 	sw \$0,1\(\$0\)
+ ...:	0c c0 01 00 	lb \$0,1\(\$0\)
+ ...:	0c c0 01 00 	lb \$0,1\(\$0\)
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+ ...:	0c c0 01 00 	lb \$0,1\(\$0\)
+ ...:	0c c0 01 00 	lb \$0,1\(\$0\)
+ ...:	0d c0 01 00 	lh \$0,1\(\$0\)
+ ...:	0d c0 01 00 	lh \$0,1\(\$0\)
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+ ...:	0d c0 01 00 	lh \$0,1\(\$0\)
+ ...:	0d c0 01 00 	lh \$0,1\(\$0\)
+ ...:	0e c0 01 00 	lw \$0,1\(\$0\)
+ ...:	0e c0 01 00 	lw \$0,1\(\$0\)
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+ ...:	0e c0 01 00 	lw \$0,1\(\$0\)
+ ...:	0e c0 01 00 	lw \$0,1\(\$0\)
+ ...:	0b c0 01 00 	lbu \$0,1\(\$0\)
+ ...:	0b c0 01 00 	lbu \$0,1\(\$0\)
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+ ...:	0b c0 01 00 	lbu \$0,1\(\$0\)
+ ...:	0b c0 01 00 	lbu \$0,1\(\$0\)
+ ...:	0f c0 01 00 	lhu \$0,1\(\$0\)
+ ...:	0f c0 01 00 	lhu \$0,1\(\$0\)
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+ ...:	0f c0 01 00 	lhu \$0,1\(\$0\)
+ ...:	0f c0 01 00 	lhu \$0,1\(\$0\)
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	08 c0 00 00 	sb \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	09 c0 00 00 	sh \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0a c0 00 00 	sw \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0c c0 00 00 	lb \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0d c0 00 00 	lh \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0e c0 00 00 	lw \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_16	.text\+0x...
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_LOW16	.text\+0x...
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_HI16S	.text\+0x...
+ ...:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			...: R_MEP_HI16U	.text\+0x...
diff --git a/gas/testsuite/gas/mep/allinsn.s b/gas/testsuite/gas/mep/allinsn.s
new file mode 100644
index 000000000000..784337c865d3
--- /dev/null
+++ b/gas/testsuite/gas/mep/allinsn.s
@@ -0,0 +1,1536 @@
+ .data
+foodata: .word 42
+ .text
+footext:
+	.text
+	.global sb
+sb:
+	sb $7,($fp)
+	sb $5,($9)
+	sb $7,($14)
+	sb $14,($fp)
+	sb $15,($14)
+	.text
+	.global sh
+sh:
+	sh $3,($fp)
+	sh $12,($1)
+	sh $13,($2)
+	sh $2,($8)
+	sh $12,($10)
+	.text
+	.global sw
+sw:
+	sw $11,($0)
+	sw $3,($7)
+	sw $13,($14)
+	sw $8,($9)
+	sw $gp,($fp)
+	.text
+	.global lb
+lb:
+	lb $12,($11)
+	lb $9,($2)
+	lb $fp,($11)
+	lb $gp,($2)
+	lb $2,($12)
+	.text
+	.global lh
+lh:
+	lh $15,($8)
+	lh $3,($10)
+	lh $9,($sp)
+	lh $6,($sp)
+	lh $15,($11)
+	.text
+	.global lw
+lw:
+	lw $12,($10)
+	lw $9,($13)
+	lw $12,($gp)
+	lw $12,($11)
+	lw $13,($10)
+	.text
+	.global lbu
+lbu:
+	lbu $14,($14)
+	lbu $12,($fp)
+	lbu $gp,($1)
+	lbu $fp,($12)
+	lbu $12,($1)
+	.text
+	.global lhu
+lhu:
+	lhu $15,($4)
+	lhu $14,($4)
+	lhu $5,($4)
+	lhu $sp,($tp)
+	lhu $4,($15)
+	.text
+	.global sw_sp
+sw_sp:
+	sw $9,3($8)
+	sw $10,4($5)
+	sw $0,3($gp)
+	sw $0,2($8)
+	sw $15,1($8)
+	.text
+	.global lw_sp
+lw_sp:
+	lw $tp,1($5)
+	lw $15,1($0)
+	lw $0,4($12)
+	lw $11,1($tp)
+	lw $9,3($4)
+	.text
+	.global sb_tp
+sb_tp:
+	sb $5,1($1)
+	sb $10,1($9)
+	sb $5,3($3)
+	sb $5,1($3)
+	sb $10,4($4)
+	.text
+	.global sh_tp
+sh_tp:
+	sh $3,1($0)
+	sh $tp,1($9)
+	sh $9,4($10)
+	sh $15,3($14)
+	sh $14,4($9)
+	.text
+	.global sw_tp
+sw_tp:
+	sw $6,2($13)
+	sw $6,1($15)
+	sw $2,2($3)
+	sw $6,2($12)
+	sw $3,1($11)
+	.text
+	.global lb_tp
+lb_tp:
+	lb $tp,4($11)
+	lb $13,4($8)
+	lb $5,4($5)
+	lb $sp,2($gp)
+	lb $3,2($3)
+	.text
+	.global lh_tp
+lh_tp:
+	lh $7,2($fp)
+	lh $4,3($8)
+	lh $14,1($sp)
+	lh $9,1($0)
+	lh $13,2($0)
+	.text
+	.global lw_tp
+lw_tp:
+	lw $8,4($15)
+	lw $11,4($9)
+	lw $gp,1($2)
+	lw $9,2($14)
+	lw $8,1($12)
+	.text
+	.global lbu_tp
+lbu_tp:
+	lbu $12,1($9)
+	lbu $11,1($9)
+	lbu $14,3($8)
+	lbu $0,2($sp)
+	lbu $13,1($11)
+	.text
+	.global lhu_tp
+lhu_tp:
+	lhu $14,2($10)
+	lhu $11,1($8)
+	lhu $1,1($0)
+	lhu $7,2($15)
+	lhu $3,2($tp)
+	.text
+	.global sb16
+sb16:
+	sb $7,-1($11)
+	sb $tp,1($gp)
+	sb $3,1($gp)
+	sb $14,2($6)
+	sb $14,1($7)
+	.text
+	.global sh16
+sh16:
+	sh $12,-1($4)
+	sh $sp,1($1)
+	sh $2,-2($12)
+	sh $9,2($11)
+	sh $9,-2($12)
+	.text
+	.global sw16
+sw16:
+	sw $11,-1($gp)
+	sw $4,4($15)
+	sw $2,-2($3)
+	sw $6,-1($2)
+	sw $fp,-2($tp)
+	.text
+	.global lb16
+lb16:
+	lb $10,-2($2)
+	lb $3,-2($11)
+	lb $12,1($5)
+	lb $5,1($5)
+	lb $11,2($13)
+	.text
+	.global lh16
+lh16:
+	lh $sp,-1($11)
+	lh $tp,-2($11)
+	lh $2,1($10)
+	lh $8,-1($7)
+	lh $14,-1($11)
+	.text
+	.global lw16
+lw16:
+	lw $0,-1($5)
+	lw $12,-2($7)
+	lw $1,-2($3)
+	lw $1,2($7)
+	lw $4,1($fp)
+	.text
+	.global lbu16
+lbu16:
+	lbu $12,-1($4)
+	lbu $14,1($11)
+	lbu $1,-1($13)
+	lbu $9,-1($tp)
+	lbu $8,1($15)
+	.text
+	.global lhu16
+lhu16:
+	lhu $tp,-1($15)
+	lhu $gp,2($fp)
+	lhu $15,-1($12)
+	lhu $3,-1($0)
+	lhu $3,-2($12)
+	.text
+	.global sw24
+sw24:
+	sw $11,(4)
+	sw $sp,(4)
+	sw $7,(8)
+	sw $10,(16)
+	sw $8,(160)
+	.text
+	.global lw24
+lw24:
+	lw $4,(4)
+	lw $sp,(4)
+	lw $4,(16)
+	lw $fp,(0)
+	lw $tp,(8)
+	.text
+	.global extb
+extb:
+	extb $13
+	extb $tp
+	extb $6
+	extb $14
+	extb $10
+	.text
+	.global exth
+exth:
+	exth $15
+	exth $2
+	exth $5
+	exth $10
+	exth $4
+	.text
+	.global extub
+extub:
+	extub $2
+	extub $tp
+	extub $3
+	extub $9
+	extub $gp
+	.text
+	.global extuh
+extuh:
+	extuh $8
+	extuh $8
+	extuh $4
+	extuh $0
+	extuh $0
+	.text
+	.global ssarb
+ssarb:
+	ssarb 2($fp)
+	ssarb 2($13)
+	ssarb 1($13)
+	ssarb 2($5)
+	ssarb 0($9)
+	.text
+	.global mov
+mov:
+	mov $2,$3
+	mov $3,$11
+	mov $15,$10
+	mov $15,$0
+	mov $3,$tp
+	.text
+	.global movi8
+movi8:
+	mov $11,-1
+	mov $6,2
+	mov $sp,-1
+	mov $sp,1
+	mov $gp,-1
+	.text
+	.global movi16
+movi16:
+	mov $15,0
+	mov $0,2
+	mov $8,-1
+	mov $12,1
+	mov $7,-1
+	.text
+	.global movu24
+movu24:
+	movu $2,1
+	movu $10,4
+	movu $9,0
+	movu $4,3
+	movu $14,1
+	.text
+	.global movu16
+movu16:
+	movu $sp,1
+	movu $6,3
+	movu $0,3
+	movu $gp,3
+	movu $10,2
+	.text
+	.global movh
+movh:
+	movh $8,2
+	movh $13,1
+	movh $gp,2
+	movh $12,0
+	movh $11,2
+	.text
+	.global add3
+add3:
+	add3 $6,$11,$3
+	add3 $14,$13,$5
+	add3 $3,$11,$7
+	add3 $13,$14,$13
+	add3 $0,$14,$8
+	.text
+	.global add
+add:
+	add $12,2
+	add $12,-1
+	add $4,1
+	add $6,1
+	add $6,2
+	.text
+	.global add3i
+add3i:
+	add3 $11,$sp,4
+	add3 $4,$sp,1
+	add3 $0,$sp,0
+	add3 $13,$sp,3
+	add3 $11,$sp,0
+	.text
+	.global advck3
+advck3:
+	advck3 $0,$gp,$10
+	advck3 $0,$tp,$0
+	advck3 $0,$gp,$13
+	advck3 $0,$7,$fp
+	advck3 $0,$1,$2
+	.text
+	.global sub
+sub:
+	sub $8,$14
+	sub $1,$9
+	sub $13,$7
+	sub $15,$3
+	sub $2,$7
+	.text
+	.global sbvck3
+sbvck3:
+	sbvck3 $0,$3,$gp
+	sbvck3 $0,$3,$7
+	sbvck3 $0,$10,$10
+	sbvck3 $0,$4,$tp
+	sbvck3 $0,$10,$15
+	.text
+	.global neg
+neg:
+	neg $14,$7
+	neg $1,$7
+	neg $2,$11
+	neg $13,$fp
+	neg $14,$13
+	.text
+	.global slt3
+slt3:
+	slt3 $0,$14,$8
+	slt3 $0,$4,$13
+	slt3 $0,$10,$14
+	slt3 $0,$14,$5
+	slt3 $0,$3,$12
+	.text
+	.global sltu3
+sltu3:
+	sltu3 $0,$2,$8
+	sltu3 $0,$gp,$11
+	sltu3 $0,$2,$tp
+	sltu3 $0,$9,$fp
+	sltu3 $0,$6,$9
+	.text
+	.global slt3i
+slt3i:
+	slt3 $0,$6,2
+	slt3 $0,$11,1
+	slt3 $0,$15,0
+	slt3 $0,$3,0
+	slt3 $0,$tp,0
+	.text
+	.global sltu3i
+sltu3i:
+	sltu3 $0,$14,4
+	sltu3 $0,$tp,3
+	sltu3 $0,$3,1
+	sltu3 $0,$12,0
+	sltu3 $0,$1,3
+	.text
+	.global sl1ad3
+sl1ad3:
+	sl1ad3 $0,$fp,$gp
+	sl1ad3 $0,$4,$2
+	sl1ad3 $0,$sp,$12
+	sl1ad3 $0,$9,$1
+	sl1ad3 $0,$fp,$2
+	.text
+	.global sl2ad3
+sl2ad3:
+	sl2ad3 $0,$8,$13
+	sl2ad3 $0,$2,$3
+	sl2ad3 $0,$8,$9
+	sl2ad3 $0,$7,$12
+	sl2ad3 $0,$4,$12
+	.text
+	.global add3x
+add3x:
+	add3 $tp,$11,1
+	add3 $tp,$4,-1
+	add3 $2,$13,1
+	add3 $3,$gp,1
+	add3 $10,$15,2
+	.text
+	.global slt3x
+slt3x:
+	slt3 $fp,$1,-1
+	slt3 $0,$3,-2
+	slt3 $9,$15,-1
+	slt3 $3,$fp,2
+	slt3 $tp,$14,0
+	.text
+	.global sltu3x
+sltu3x:
+	sltu3 $15,$11,2
+	sltu3 $6,$0,1
+	sltu3 $9,$11,3
+	sltu3 $0,$4,0
+	sltu3 $13,$gp,4
+	.text
+	.global or
+or:
+	or $sp,$gp
+	or $fp,$3
+	or $0,$sp
+	or $tp,$0
+	or $8,$6
+	.text
+	.global and
+and:
+	and $15,$sp
+	and $6,$14
+	and $4,$2
+	and $5,$fp
+	and $7,$14
+	.text
+	.global xor
+xor:
+	xor $1,$12
+	xor $12,$tp
+	xor $10,$8
+	xor $sp,$11
+	xor $12,$8
+	.text
+	.global nor
+nor:
+	nor $9,$5
+	nor $8,$2
+	nor $15,$9
+	nor $5,$sp
+	nor $sp,$14
+	.text
+	.global or3
+or3:
+	or3 $13,$sp,2
+	or3 $sp,$tp,3
+	or3 $0,$10,4
+	or3 $9,$15,3
+	or3 $9,$sp,0
+	.text
+	.global and3
+and3:
+	and3 $5,$8,1
+	and3 $11,$gp,3
+	and3 $6,$0,0
+	and3 $sp,$sp,0
+	and3 $1,$10,3
+	.text
+	.global xor3
+xor3:
+	xor3 $0,$0,2
+	xor3 $15,$6,0
+	xor3 $13,$5,0
+	xor3 $15,$7,0
+	xor3 $15,$sp,2
+	.text
+	.global sra
+sra:
+	sra $4,$1
+	sra $fp,$15
+	sra $1,$1
+	sra $0,$5
+	sra $9,$1
+	.text
+	.global srl
+srl:
+	srl $2,$11
+	srl $15,$7
+	srl $1,$7
+	srl $3,$13
+	srl $14,$1
+	.text
+	.global sll
+sll:
+	sll $11,$0
+	sll $tp,$fp
+	sll $8,$9
+	sll $13,$15
+	sll $sp,$sp
+	.text
+	.global srai
+srai:
+	sra $1,2
+	sra $15,3
+	sra $sp,3
+	sra $6,4
+	sra $sp,3
+	.text
+	.global srli
+srli:
+	srl $10,0
+	srl $9,3
+	srl $6,4
+	srl $10,2
+	srl $8,3
+	.text
+	.global slli
+slli:
+	sll $0,0
+	sll $4,0
+	sll $13,2
+	sll $11,2
+	sll $6,0
+	.text
+	.global sll3
+sll3:
+	sll3 $0,$tp,4
+	sll3 $0,$14,0
+	sll3 $0,$8,2
+	sll3 $0,$3,2
+	sll3 $0,$fp,0
+	.text
+	.global fsft
+fsft:
+	fsft $gp,$10
+	fsft $gp,$9
+	fsft $15,$13
+	fsft $11,$3
+	fsft $5,$3
+	.text
+	.global bra
+bra:
+	bra 2
+	bra -2
+	bra 2
+	bra 0
+	bra 2
+	.text
+	.global beqz
+beqz:
+	beqz $1,-2
+	beqz $sp,2
+	beqz $4,4
+	beqz $4,0
+	beqz $9,-2
+	.text
+	.global bnez
+bnez:
+	bnez $8,2
+	bnez $13,2
+	bnez $gp,0
+	bnez $6,2
+	bnez $8,-4
+	.text
+	.global beqi
+beqi:
+	beqi $tp,3,0
+	beqi $0,4,-2
+	beqi $sp,4,-2
+	beqi $13,2,0
+	beqi $4,2,-8
+	.text
+	.global bnei
+bnei:
+	bnei $8,1,0
+	bnei $5,1,2
+	bnei $5,0,8
+	bnei $9,4,-2
+	bnei $0,4,-8
+	.text
+	.global blti
+blti:
+	blti $7,3,0
+	blti $1,1,0
+	blti $8,2,2
+	blti $11,2,2
+	blti $15,3,-2
+	.text
+	.global bgei
+bgei:
+	bgei $4,3,-8
+	bgei $7,0,2
+	bgei $13,1,0
+	bgei $5,2,-2
+	bgei $12,4,-8
+	.text
+	.global beq
+beq:
+	beq $7,$2,-2
+	beq $1,$3,-8
+	beq $2,$0,2
+	beq $sp,$fp,2
+	beq $3,$0,0
+	.text
+	.global bne
+bne:
+	bne $6,$3,0
+	bne $sp,$3,-8
+	bne $8,$0,2
+	bne $gp,$sp,8
+	bne $sp,$4,2
+	.text
+	.global bsr12
+bsr12:
+	bsr 2
+	bsr -8
+	bsr -16
+	bsr -2
+	bsr -8
+	.text
+	.global bsr24
+bsr24:
+	bsr 4
+	bsr -2
+	bsr -4
+	bsr 0
+	bsr 2
+	.text
+	.global jmp
+jmp:
+	jmp $2
+	jmp $tp
+	jmp $5
+	jmp $sp
+	jmp $fp
+	.text
+	.global jmp24
+jmp24:
+	jmp 4
+	jmp 2
+	jmp 0
+	jmp 2
+	jmp 4
+	.text
+	.global jsr
+jsr:
+	jsr $15
+	jsr $13
+	jsr $13
+	jsr $6
+	jsr $6
+	.text
+	.global ret
+ret:
+	ret
+	.text
+	.global repeat
+repeat:
+	repeat $4,2
+	repeat $fp,4
+	repeat $0,8
+	repeat $6,2
+	repeat $4,2
+	.text
+	.global erepeat
+erepeat:
+	erepeat 2
+	erepeat 0
+	erepeat 2
+	erepeat -2
+	erepeat 0
+	.text
+	.global stc
+stc:
+	stc $13,$mb1
+	stc $tp,$ccfg
+	stc $11,$dbg
+	stc $10,$ccfg
+	stc $9,$epc
+	.text
+	.global ldc
+ldc:
+	ldc $tp,$lo
+	ldc $8,$npc
+	ldc $9,$mb0
+	ldc $15,$sar
+	ldc $9,$ccfg
+	.text
+	.global di
+di:
+	di
+	.text
+	.global ei
+ei:
+	ei
+	.text
+	.global reti
+reti:
+	reti
+	.text
+	.global halt
+halt:
+	halt
+	.text
+	.global swi
+swi:
+	swi 2
+	swi 0
+	swi 2
+	swi 3
+	swi 1
+	.text
+	.global break
+break:
+	break
+	.text
+	.global sycnm
+syncm:
+	syncm
+	.text
+	.global stcb
+stcb:
+	stcb $5,4
+	stcb $5,1
+	stcb $gp,0
+	stcb $15,4
+	stcb $11,2
+	.text
+	.global ldcb
+ldcb:
+	ldcb $2,3
+	ldcb $2,4
+	ldcb $9,1
+	ldcb $10,4
+	ldcb $1,4
+	.text
+	.global bsetm
+bsetm:
+	bsetm ($10),0
+	bsetm ($sp),0
+	bsetm ($1),2
+	bsetm ($sp),4
+	bsetm ($8),4
+	.text
+	.global bclrm
+bclrm:
+	bclrm ($5),0
+	bclrm ($5),2
+	bclrm ($8),0
+	bclrm ($9),2
+	bclrm ($5),3
+	.text
+	.global bnotm
+bnotm:
+	bnotm ($14),4
+	bnotm ($11),4
+	bnotm ($10),0
+	bnotm ($tp),4
+	bnotm ($fp),0
+	.text
+	.global btstm
+btstm:
+	btstm $0,($14),0
+	btstm $0,($14),1
+	btstm $0,($11),0
+	btstm $0,($14),3
+	btstm $0,($fp),2
+	.text
+	.global tas
+tas:
+	tas $7,($tp)
+	tas $7,($12)
+	tas $3,($fp)
+	tas $2,($5)
+	tas $6,($10)
+	.text
+	.global cache
+cache:
+	cache 1,($13)
+	cache 3,($12)
+	cache 3,($9)
+	cache 4,($2)
+	cache 4,($7)
+	.text
+	.global mul
+mul:
+	mul $8,$14
+	mul $2,$9
+	mul $14,$15
+	mul $9,$7
+	mul $7,$11
+	.text
+	.global mulu
+mulu:
+	mulu $2,$5
+	mulu $6,$gp
+	mulu $gp,$sp
+	mulu $11,$14
+	mulu $3,$9
+	.text
+	.global mulr
+mulr:
+	mulr $12,$6
+	mulr $13,$8
+	mulr $7,$10
+	mulr $gp,$1
+	mulr $0,$15
+	.text
+	.global mulru
+mulru:
+	mulru $4,$2
+	mulru $14,$1
+	mulru $15,$4
+	mulru $10,$6
+	mulru $0,$gp
+	.text
+	.global madd
+madd:
+	madd $4,$11
+	madd $15,$14
+	madd $14,$sp
+	madd $4,$tp
+	madd $1,$gp
+	.text
+	.global maddu
+maddu:
+	maddu $0,$1
+	maddu $7,$6
+	maddu $9,$5
+	maddu $gp,$15
+	maddu $7,$13
+	.text
+	.global maddr
+maddr:
+	maddr $6,$fp
+	maddr $9,$14
+	maddr $8,$gp
+	maddr $3,$2
+	maddr $1,$11
+	.text
+	.global maddru
+maddru:
+	maddru $10,$3
+	maddru $15,$12
+	maddru $8,$fp
+	maddru $14,$3
+	maddru $fp,$15
+	.text
+	.global div
+div:
+	div $9,$3
+	div $4,$14
+	div $2,$12
+	div $fp,$tp
+	div $tp,$6
+	.text
+	.global divu
+divu:
+	divu $9,$5
+	divu $8,$13
+	divu $0,$14
+	divu $9,$5
+	divu $0,$5
+	.text
+	.global dret
+dret:
+	dret
+	.text
+	.global dbreak
+dbreak:
+	dbreak
+	.text
+	.global ldz
+ldz:
+	ldz $gp,$4
+	ldz $10,$11
+	ldz $9,$9
+	ldz $15,$tp
+	ldz $gp,$3
+	.text
+	.global abs
+abs:
+	abs $sp,$9
+	abs $5,$4
+	abs $tp,$13
+	abs $0,$3
+	abs $3,$14
+	.text
+	.global ave
+ave:
+	ave $11,$10
+	ave $fp,$10
+	ave $14,$2
+	ave $10,$12
+	ave $15,$8
+	.text
+	.global min
+min:
+	min $8,$3
+	min $7,$0
+	min $2,$2
+	min $5,$6
+	min $11,$5
+	.text
+	.global max
+max:
+	max $11,$sp
+	max $gp,$0
+	max $12,$sp
+	max $gp,$2
+	max $14,$sp
+	.text
+	.global minu
+minu:
+	minu $11,$8
+	minu $7,$5
+	minu $fp,$14
+	minu $11,$4
+	minu $2,$sp
+	.text
+	.global maxu
+maxu:
+	maxu $3,$3
+	maxu $13,$0
+	maxu $4,$fp
+	maxu $gp,$2
+	maxu $12,$fp
+	.text
+	.global clip
+clip:
+	clip $10,1
+	clip $15,4
+	clip $4,3
+	clip $15,3
+	clip $1,0
+	.text
+	.global clipu
+clipu:
+	clipu $10,4
+	clipu $13,1
+	clipu $5,4
+	clipu $14,0
+	clipu $5,1
+	.text
+	.global sadd
+sadd:
+	sadd $5,$0
+	sadd $15,$3
+	sadd $0,$10
+	sadd $sp,$12
+	sadd $4,$2
+	.text
+	.global ssub
+ssub:
+	ssub $1,$10
+	ssub $4,$7
+	ssub $fp,$3
+	ssub $7,$gp
+	ssub $13,$4
+	.text
+	.global saddu
+saddu:
+	saddu $9,$14
+	saddu $0,$10
+	saddu $7,$12
+	saddu $5,$15
+	saddu $13,$3
+	.text
+	.global ssubu
+ssubu:
+	ssubu $15,$gp
+	ssubu $0,$15
+	ssubu $3,$10
+	ssubu $sp,$13
+	ssubu $2,$9
+	.text
+	.global swcp
+swcp:
+	swcp $c3,($13)
+	swcp $c15,($13)
+	swcp $c13,($0)
+	swcp $c12,($12)
+	swcp $c9,($gp)
+	.text
+	.global lwcp
+lwcp:
+	lwcp $c7,($3)
+	lwcp $c6,($3)
+	lwcp $c0,($2)
+	lwcp $c8,($fp)
+	lwcp $c11,($13)
+	.text
+	.global smcp
+smcp:
+	smcp $c14,($9)
+	smcp $c2,($fp)
+	smcp $c14,($15)
+	smcp $c10,($8)
+	smcp $c2,($8)
+	.text
+	.global lmcp
+lmcp:
+	lmcp $c11,($1)
+	lmcp $c8,($8)
+	lmcp $c11,($13)
+	lmcp $c8,($0)
+	lmcp $c8,($14)
+	.text
+	.global swcpi
+swcpi:
+	swcpi $c7,($0+)
+	swcpi $c6,($gp+)
+	swcpi $c12,($8+)
+	swcpi $c14,($15+)
+	swcpi $c6,($0+)
+	.text
+	.global lwcpi
+lwcpi:
+	lwcpi $c8,($2+)
+	lwcpi $c9,($0+)
+	lwcpi $c3,($14+)
+	lwcpi $c13,($5+)
+	lwcpi $c11,($gp+)
+	.text
+	.global smcpi
+smcpi:
+	smcpi $c8,($2+)
+	smcpi $c11,($9+)
+	smcpi $c4,($3+)
+	smcpi $c14,($2+)
+	smcpi $c9,($3+)
+	.text
+	.global lmcpi
+lmcpi:
+	lmcpi $c6,($14+)
+	lmcpi $c9,($5+)
+	lmcpi $c10,($6+)
+	lmcpi $c1,($6+)
+	lmcpi $c2,($8+)
+	.text
+	.global swcp16
+swcp16:
+	swcp $c0,-1($2)
+	swcp $c5,1($10)
+	swcp $c8,2($12)
+	swcp $c14,-1($1)
+	swcp $c12,2($3)
+	.text
+	.global lwcp16
+lwcp16:
+	lwcp $c8,-1($5)
+	lwcp $c12,1($15)
+	lwcp $c1,2($0)
+	lwcp $c4,1($13)
+	lwcp $c6,2($11)
+	.text
+	.global smcp16
+smcp16:
+	smcp $c9,-1($10)
+	smcp $c14,1($gp)
+	smcp $c3,2($sp)
+	smcp $c15,-2($8)
+	smcp $c13,1($13)
+	.text
+	.global lmcp16
+lmcp16:
+	lmcp $c0,1($15)
+	lmcp $c15,1($fp)
+	lmcp $c2,-1($8)
+	lmcp $c14,1($fp)
+	lmcp $c1,-1($10)
+	.text
+	.global sbcpa
+sbcpa:
+	sbcpa $c14,($sp+),2
+	sbcpa $c2,($4+),-2
+	sbcpa $c8,($1+),0
+	sbcpa $c11,($3+),0
+	sbcpa $c9,($14+),-2
+	.text
+	.global lbcpa
+lbcpa:
+	lbcpa $c7,($2+),-2
+	lbcpa $c12,($sp+),2
+	lbcpa $c5,($4+),-2
+	lbcpa $c7,($4+),-2
+	lbcpa $c8,($15+),0
+	.text
+	.global shcpa
+shcpa:
+	shcpa $c0,($14+),0
+	shcpa $c12,($sp+),16
+	shcpa $c1,($4+),4
+	shcpa $c5,($4+),-32
+	shcpa $c1,($15+),0
+	.text
+	.global lhcpa
+lhcpa:
+	lhcpa $c4,($4+),0
+	lhcpa $c6,($5+),48
+	lhcpa $c3,($6+),-52
+	lhcpa $c8,($6+),-24
+	lhcpa $c0,($9+),0
+	.text
+	.global swcpa
+swcpa:
+	swcpa $c1,($9+),16
+	swcpa $c7,($sp+),32
+	swcpa $c3,($12+),48
+	swcpa $c10,($9+),8
+	swcpa $c14,($8+),4
+	.text
+	.global lwcpa
+lwcpa:
+	lwcpa $c6,($gp+),-8
+	lwcpa $c4,($7+),4
+	lwcpa $c11,($gp+),-16
+	lwcpa $c10,($sp+),-32
+	lwcpa $c2,($2+),8
+	.text
+	.global smcpa
+smcpa:
+	smcpa $c13,($15+),-8
+	smcpa $c6,($7+),-8
+	smcpa $c5,($3+),16
+	smcpa $c13,($15+),16
+	smcpa $c3,($12+),48
+	.text
+	.global lmcpa
+lmcpa:
+	lmcpa $c9,($4+),0
+	lmcpa $c3,($sp+),-16
+	lmcpa $c15,($13+),8
+	lmcpa $c8,($8+),-8
+	lmcpa $c10,($9+),0
+	.text
+	.global sbcpm0
+sbcpm0:
+	sbcpm0 $c10,($13+),8
+	sbcpm0 $c13,($5+),-8
+	sbcpm0 $c4,($5+),-8
+	sbcpm0 $c10,($tp+),16
+	sbcpm0 $c4,($5+),-24
+	.text
+	.global lbcpm0
+lbcpm0:
+	lbcpm0 $c0,($4+),0
+	lbcpm0 $c9,($7+),-8
+	lbcpm0 $c12,($fp+),24
+	lbcpm0 $c8,($12+),16
+	lbcpm0 $c7,($fp+),16
+	.text
+	.global shcpm0
+shcpm0:
+	shcpm0 $c2,($13+),2
+	shcpm0 $c7,($15+),-2
+	shcpm0 $c8,($2+),2
+	shcpm0 $c13,($5+),0
+	shcpm0 $c3,($14+),8
+	.text
+	.global lhcpm0
+lhcpm0:
+	lhcpm0 $c7,($4+),8
+	lhcpm0 $c3,($3+),-2
+	lhcpm0 $c3,($1+),0
+	lhcpm0 $c2,($gp+),0
+	lhcpm0 $c12,($6+),2
+	.text
+	.global swcpm0
+swcpm0:
+	swcpm0 $c8,($fp+),32
+	swcpm0 $c9,($sp+),0
+	swcpm0 $c9,($2+),-16
+	swcpm0 $c0,($14+),48
+	swcpm0 $c15,($1+),8
+	.text
+	.global lwcpm0
+lwcpm0:
+	lwcpm0 $c14,($10+),-4
+	lwcpm0 $c11,($sp+),-4
+	lwcpm0 $c5,($7+),-8
+	lwcpm0 $c2,($12+),32
+	lwcpm0 $c2,($gp+),16
+	.text
+	.global smcpm0
+smcpm0:
+	smcpm0 $c1,($12+),8
+	smcpm0 $c8,($4+),-16
+	smcpm0 $c10,($11+),0
+	smcpm0 $c1,($3+),-16
+	smcpm0 $c11,($sp+),-8
+	.text
+	.global lmcpm0
+lmcpm0:
+	lmcpm0 $c14,($10+),0
+	lmcpm0 $c6,($15+),-16
+	lmcpm0 $c13,($1+),8
+	lmcpm0 $c10,($tp+),-24
+	lmcpm0 $c7,($14+),-24
+	.text
+	.global sbcpm1
+sbcpm1:
+	sbcpm1 $c9,($fp+),0
+	sbcpm1 $c7,($12+),-24
+	sbcpm1 $c15,($5+),-24
+	sbcpm1 $c5,($tp+),16
+	sbcpm1 $c6,($1+),-128
+	.text
+	.global lbcpm1
+lbcpm1:
+	lbcpm1 $c6,($gp+),2
+	lbcpm1 $c7,($tp+),-2
+	lbcpm1 $c4,($13+),1
+	lbcpm1 $c12,($2+),-2
+	lbcpm1 $c11,($7+),1
+	.text
+	.global shcpm1
+shcpm1:
+	shcpm1 $c4,($fp+),24
+	shcpm1 $c11,($6+),-16
+	shcpm1 $c7,($8+),8
+	shcpm1 $c5,($12+),16
+	shcpm1 $c0,($8+),-32
+	.text
+	.global lhcpm1
+lhcpm1:
+	lhcpm1 $c11,($0+),0
+	lhcpm1 $c7,($tp+),-2
+	lhcpm1 $c10,($8+),8
+	lhcpm1 $c3,($tp+),0
+	lhcpm1 $c9,($6+),2
+	.text
+	.global swcpm1
+swcpm1:
+	swcpm1 $c9,($8+),24
+	swcpm1 $c9,($14+),0
+	swcpm1 $c9,($fp+),16
+	swcpm1 $c14,($1+),0
+	swcpm1 $c2,($sp+),8
+	.text
+	.global lwcpm1
+lwcpm1:
+	lwcpm1 $c8,($fp+),0
+	lwcpm1 $c3,($14+),-16
+	lwcpm1 $c7,($6+),-8
+	lwcpm1 $c14,($fp+),-24
+	lwcpm1 $c3,($fp+),24
+	.text
+	.global smcpm1
+smcpm1:
+	smcpm1 $c10,($4+),0
+	smcpm1 $c6,($sp+),-16
+	smcpm1 $c13,($7+),-24
+	smcpm1 $c3,($gp+),-8
+	smcpm1 $c0,($2+),8
+	.text
+	.global lmcpm1
+lmcpm1:
+	lmcpm1 $c12,($1+),0
+	lmcpm1 $c0,($6+),8
+	lmcpm1 $c6,($2+),-8
+	lmcpm1 $c12,($gp+),-16
+	lmcpm1 $c14,($15+),48
+/*	
+	.text
+	.global cmov1
+cmov1:
+	cmov $c11,$10
+	cmov $c14,$3
+	cmov $c3,$15
+	cmov $c6,$5
+	cmov $c6,$10
+	.text
+	.global cmov2
+cmov2:
+	cmov $11,$c2
+	cmov $10,$c2
+	cmov $tp,$c10
+	cmov $12,$c9
+	cmov $15,$c3
+	.text
+	.global cmovc1
+cmovc1:
+	cmovc $ccr9,$sp
+	cmovc $ccr12,$fp
+	cmovc $ccr1,$4
+	cmovc $ccr11,$sp
+	cmovc $ccr14,$7
+	.text
+	.global cmovc2
+cmovc2:
+	cmovc $fp,$ccr6
+	cmovc $fp,$ccr6
+	cmovc $7,$ccr8
+	cmovc $sp,$ccr12
+	cmovc $sp,$ccr5
+	.text
+	.global cmovh1
+cmovh1:
+	cmovh $c8,$1
+	cmovh $c12,$sp
+	cmovh $c11,$5
+	cmovh $c4,$4
+	cmovh $c3,$gp
+	.text
+	.global cmovh2
+cmovh2:
+	cmovh $4,$c7
+	cmovh $gp,$c8
+	cmovh $6,$c10
+	cmovh $2,$c8
+	cmovh $10,$c4
+*/	
+	.text
+	.global bcpeq
+bcpeq:
+	bcpeq 4,0
+	bcpeq 0,-2
+	bcpeq 4,-2
+	bcpeq 1,2
+	bcpeq 2,2
+	.text
+	.global bcpne
+bcpne:
+	bcpne 2,0
+	bcpne 4,0
+	bcpne 1,0
+	bcpne 4,0
+	bcpne 1,2
+	.text
+	.global bcpat
+bcpat:
+	bcpat 1,-2
+	bcpat 0,2
+	bcpat 0,-2
+	bcpat 2,0
+	bcpat 1,-2
+	.text
+	.global bcpaf
+bcpaf:
+	bcpaf 4,0
+	bcpaf 3,0
+	bcpaf 4,0
+	bcpaf 1,2
+	bcpaf 4,2
+	.text
+	.global synccp
+synccp:
+	synccp
+	.text
+	.global jsrv
+jsrv:
+	jsrv $11
+	jsrv $5
+	jsrv $10
+	jsrv $12
+	jsrv $10
+	.text
+	.global bsrv
+bsrv:
+	bsrv -2
+	bsrv -2
+	bsrv -2
+	bsrv 2
+	bsrv 0
+	.text
+	.global case106341
+case106341:
+	stc $10,7
+	ldc $0, (4 + 4)
+case106821:
+	/* Actual 16 bit form */
+        sb      $0,($0)
+        sh      $0,($0)
+        sw      $0,($0)
+        lb      $0,($0)
+        lh      $0,($0)
+        lw      $0,($0)
+        lbu     $0,($0)
+        lhu     $0,($0)
+	/* Should use 16 bit form */
+        sb      $0,0($0)
+        sb      $0,%lo(0)($0)
+        sb      $0,%hi(0)($0)
+        sb      $0,%uhi(0)($0)
+        sb      $0,%sdaoff(0)($0)
+        sb      $0,%tpoff(0)($0)
+        sh      $0,0($0)
+        sh      $0,%lo(0)($0)
+        sh      $0,%hi(0)($0)
+        sh      $0,%uhi(0)($0)
+        sh      $0,%sdaoff(0)($0)
+        sh      $0,%tpoff(0)($0)
+        sw      $0,0($0)
+        sw      $0,%lo(0)($0)
+        sw      $0,%hi(0)($0)
+        sw      $0,%uhi(0)($0)
+        sw      $0,%sdaoff(0)($0)
+        sw      $0,%tpoff(0)($0)
+        lb      $0,0($0)
+        lb      $0,%lo(0)($0)
+        lb      $0,%hi(0)($0)
+        lb      $0,%uhi(0)($0)
+        lb      $0,%sdaoff(0)($0)
+        lb      $0,%tpoff(0)($0)
+        lh      $0,0($0)
+        lh      $0,%lo(0)($0)
+        lh      $0,%hi(0)($0)
+        lh      $0,%uhi(0)($0)
+        lh      $0,%sdaoff(0)($0)
+        lh      $0,%tpoff(0)($0)
+        lw      $0,0($0)
+        lw      $0,%lo(0)($0)
+        lw      $0,%hi(0)($0)
+        lw      $0,%uhi(0)($0)
+        lw      $0,%sdaoff(0)($0)
+        lw      $0,%tpoff(0)($0)
+        lbu     $0,0($0)
+        lbu     $0,%lo(0)($0)
+        lbu     $0,%hi(0)($0)
+        lbu     $0,%uhi(0)($0)
+        lbu     $0,%sdaoff(0)($0)
+        lbu     $0,%tpoff(0)($0)
+        lhu     $0,0($0)
+        lhu     $0,%lo(0)($0)
+        lhu     $0,%hi(0)($0)
+        lhu     $0,%uhi(0)($0)
+        lhu     $0,%sdaoff(0)($0)
+        lhu     $0,%tpoff(0)($0)
+	/* Should use 32 bit form */
+        sb      $0,1($0)
+        sb      $0,%lo(1)($0)
+        sb      $0,%hi(1)($0)
+        sb      $0,%uhi(1)($0)
+        sb      $0,%sdaoff(1)($0)
+        sb      $0,%tpoff(1)($0)
+        sh      $0,1($0)
+        sh      $0,%lo(1)($0)
+        sh      $0,%hi(1)($0)
+        sh      $0,%uhi(1)($0)
+        sh      $0,%sdaoff(1)($0)
+        sh      $0,%tpoff(1)($0)
+        sw      $0,1($0)
+        sw      $0,%lo(1)($0)
+        sw      $0,%hi(1)($0)
+        sw      $0,%uhi(1)($0)
+        sw      $0,%sdaoff(1)($0)
+        sw      $0,%tpoff(1)($0)
+        lb      $0,1($0)
+        lb      $0,%lo(1)($0)
+        lb      $0,%hi(1)($0)
+        lb      $0,%uhi(1)($0)
+        lb      $0,%sdaoff(1)($0)
+        lb      $0,%tpoff(1)($0)
+        lh      $0,1($0)
+        lh      $0,%lo(1)($0)
+        lh      $0,%hi(1)($0)
+        lh      $0,%uhi(1)($0)
+        lh      $0,%sdaoff(1)($0)
+        lh      $0,%tpoff(1)($0)
+        lw      $0,1($0)
+        lw      $0,%lo(1)($0)
+        lw      $0,%hi(1)($0)
+        lw      $0,%uhi(1)($0)
+        lw      $0,%sdaoff(1)($0)
+        lw      $0,%tpoff(1)($0)
+        lbu     $0,1($0)
+        lbu     $0,%lo(1)($0)
+        lbu     $0,%hi(1)($0)
+        lbu     $0,%uhi(1)($0)
+        lbu     $0,%sdaoff(1)($0)
+        lbu     $0,%tpoff(1)($0)
+        lhu     $0,1($0)
+        lhu     $0,%lo(1)($0)
+        lhu     $0,%hi(1)($0)
+        lhu     $0,%uhi(1)($0)
+        lhu     $0,%sdaoff(1)($0)
+        lhu     $0,%tpoff(1)($0)
+	/* Should use 32 bit form */
+	sb      $0,case106821($0)
+        sb      $0,%lo(case106821)($0)
+        sb      $0,%hi(case106821)($0)
+        sb      $0,%uhi(case106821)($0)
+	sh      $0,case106821($0)
+        sh      $0,%lo(case106821)($0)
+        sh      $0,%hi(case106821)($0)
+        sh      $0,%uhi(case106821)($0)
+	sw      $0,case106821($0)
+        sw      $0,%lo(case106821)($0)
+        sw      $0,%hi(case106821)($0)
+        sw      $0,%uhi(case106821)($0)
+	lb      $0,case106821($0)
+        lb      $0,%lo(case106821)($0)
+        lb      $0,%hi(case106821)($0)
+        lb      $0,%uhi(case106821)($0)
+	lh      $0,case106821($0)
+        lh      $0,%lo(case106821)($0)
+        lh      $0,%hi(case106821)($0)
+        lh      $0,%uhi(case106821)($0)
+	lw      $0,case106821($0)
+        lw      $0,%lo(case106821)($0)
+        lw      $0,%hi(case106821)($0)
+        lw      $0,%uhi(case106821)($0)
+	lbu     $0,case106821($0)
+        lbu     $0,%lo(case106821)($0)
+        lbu     $0,%hi(case106821)($0)
+        lbu     $0,%uhi(case106821)($0)
+	lhu     $0,case106821($0)
+        lhu     $0,%lo(case106821)($0)
+        lhu     $0,%hi(case106821)($0)
+        lhu     $0,%uhi(case106821)($0)
diff --git a/gas/testsuite/gas/mep/branch1.d b/gas/testsuite/gas/mep/branch1.d
new file mode 100644
index 000000000000..271b9184a548
--- /dev/null
+++ b/gas/testsuite/gas/mep/branch1.d
@@ -0,0 +1,14 @@
+#objdump: -dzr
+
+.*: *file format elf32-mep
+
+Disassembly of section \.text:
+
+.* <.*>:
+  .*:	00 00  *	nop
+  .*:	e4 51 00 04 *	beq \$4,\$5,.* <foo>
+  .*:	00 00  *	nop
+  .*:	00 00  *	nop
+
+.* <foo>:
+  .*:	00 00  *	nop
diff --git a/gas/testsuite/gas/mep/branch1.s b/gas/testsuite/gas/mep/branch1.s
new file mode 100644
index 000000000000..7c69985d7e50
--- /dev/null
+++ b/gas/testsuite/gas/mep/branch1.s
@@ -0,0 +1,7 @@
+	.globl	foo
+	nop
+	beq	$4,$5,foo
+	nop
+	nop
+foo:
+	nop
diff --git a/gas/testsuite/gas/mep/complex-relocs.exp b/gas/testsuite/gas/mep/complex-relocs.exp
new file mode 100644
index 000000000000..ed8a72a413bf
--- /dev/null
+++ b/gas/testsuite/gas/mep/complex-relocs.exp
@@ -0,0 +1,42 @@
+# complex relocations testsuite
+
+proc ld_test { objects ldflags dest test } {
+    set ld_output [target_link $objects $dest $ldflags]
+    if [string match "" $ld_output] then { pass $test } else { fail $test }
+}
+
+proc ld_test_error { objects ldflags dest test } {
+    set ld_output [target_link $objects $dest $ldflags]
+    if [string match "" $ld_output] then { fail $test } else { pass $test }
+}
+
+proc objdump_test { exec flags dest test } {
+    set objdump [find_binutils_prog objdump]
+    verbose -log "$objdump $flags $exec > $dest"
+    catch "exec $objdump $flags $exec > $dest" objdump_output
+    if [string match "" $objdump_output] then { pass $test } else { fail $test }
+}
+
+proc regexp_test { file1 file2 test } {
+    if [regexp_diff $file1 $file2] then { fail $test } else { pass $test }
+}
+
+
+global srcdir subdir
+if [istarget mep*-*-*] {
+
+    # test that complex relocs between files work, generally
+    gas_test relocs-junk1.s {-mconfig=fmax -o relocs-junk1.o} {} {assembling relocs-junk1}
+    gas_test relocs-syms.s {-mconfig=fmax -o relocs-syms.o} {} {assembling relocs-syms}
+    gas_test relocs-junk2.s {-mconfig=fmax -o relocs-junk2.o} {} {assembling relocs-junk2}
+    gas_test relocs-refs.s {-mconfig=fmax -o relocs-refs.o} {} {assembling relocs-refs}
+    ld_test {relocs-junk1.o relocs-syms.o relocs-junk2.o relocs-refs.o} {--defsym __stack=0x1ffff0 --defsym __sbss_end=0x1000 -e 1233} {relocs.x} {linking relocs.x}
+    objdump_test {relocs.x} {-dzs} {relocs.dump} {disassembling relocs.x}
+    regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly for relocs.x}
+
+    foreach test {3} {
+	# perform specific negative boundary tests
+	gas_test "relocs-bad$test.s" [list -mconfig=fmax -o "relocs-bad$test.o"] {} [list assembling "relocs-bad$test"]
+	ld_test_error "relocs-bad$test.o" {-e 1233} "relocs-bad$test.x" [list linking "relocs-bad$test"]
+    }
+}
diff --git a/gas/testsuite/gas/mep/dj1.d b/gas/testsuite/gas/mep/dj1.d
new file mode 100644
index 000000000000..c314d724ce68
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj1.d
@@ -0,0 +1,1393 @@
+#as:
+#objdump: -dr
+#name: dj1
+
+dump.o:     file format elf32-mep
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 00       	nop
+   2:	01 00       	mov \$1,\$0
+   4:	02 00       	mov \$2,\$0
+   6:	03 00       	mov \$3,\$0
+   8:	04 00       	mov \$4,\$0
+   a:	05 00       	mov \$5,\$0
+   c:	06 00       	mov \$6,\$0
+   e:	07 00       	mov \$7,\$0
+  10:	08 00       	mov \$8,\$0
+  12:	09 00       	mov \$9,\$0
+  14:	0a 00       	mov \$10,\$0
+  16:	0b 00       	mov \$11,\$0
+  18:	0c 00       	mov \$12,\$0
+  1a:	0d 00       	mov \$tp,\$0
+  1c:	0e 00       	mov \$gp,\$0
+  1e:	0f 00       	mov \$sp,\$0
+  20:	08 00       	mov \$8,\$0
+  22:	0d 00       	mov \$tp,\$0
+  24:	0e 00       	mov \$gp,\$0
+  26:	0f 00       	mov \$sp,\$0
+  28:	00 08       	sb \$0,\(\$0\)
+  2a:	00 09       	sh \$0,\(\$0\)
+  2c:	00 0a       	sw \$0,\(\$0\)
+  2e:	00 0c       	lb \$0,\(\$0\)
+  30:	00 0d       	lh \$0,\(\$0\)
+  32:	00 0e       	lw \$0,\(\$0\)
+  34:	00 0b       	lbu \$0,\(\$0\)
+  36:	00 0f       	lhu \$0,\(\$0\)
+  38:	0f 08       	sb \$sp,\(\$0\)
+  3a:	0f 09       	sh \$sp,\(\$0\)
+  3c:	0f 0a       	sw \$sp,\(\$0\)
+  3e:	0f 0c       	lb \$sp,\(\$0\)
+  40:	0f 0d       	lh \$sp,\(\$0\)
+  42:	0f 0e       	lw \$sp,\(\$0\)
+  44:	0f 0b       	lbu \$sp,\(\$0\)
+  46:	0f 0f       	lhu \$sp,\(\$0\)
+  48:	00 f8       	sb \$0,\(\$sp\)
+  4a:	00 f9       	sh \$0,\(\$sp\)
+  4c:	00 fa       	sw \$0,\(\$sp\)
+  4e:	00 fc       	lb \$0,\(\$sp\)
+  50:	00 fd       	lh \$0,\(\$sp\)
+  52:	00 fe       	lw \$0,\(\$sp\)
+  54:	00 fb       	lbu \$0,\(\$sp\)
+  56:	00 ff       	lhu \$0,\(\$sp\)
+  58:	0f f8       	sb \$sp,\(\$sp\)
+  5a:	0f f9       	sh \$sp,\(\$sp\)
+  5c:	0f fa       	sw \$sp,\(\$sp\)
+  5e:	0f fc       	lb \$sp,\(\$sp\)
+  60:	0f fd       	lh \$sp,\(\$sp\)
+  62:	0f fe       	lw \$sp,\(\$sp\)
+  64:	0f fb       	lbu \$sp,\(\$sp\)
+  66:	0f ff       	lhu \$sp,\(\$sp\)
+  68:	00 fa       	sw \$0,\(\$sp\)
+  6a:	00 fe       	lw \$0,\(\$sp\)
+  6c:	0f fa       	sw \$sp,\(\$sp\)
+  6e:	0f fe       	lw \$sp,\(\$sp\)
+  70:	40 7e       	sw \$0,0x7c\(\$sp\)
+  72:	40 7f       	lw \$0,0x7c\(\$sp\)
+  74:	4f 7e       	sw \$sp,0x7c\(\$sp\)
+  76:	4f 7f       	lw \$sp,0x7c\(\$sp\)
+  78:	00 fa       	sw \$0,\(\$sp\)
+  7a:	00 fe       	lw \$0,\(\$sp\)
+  7c:	0f fa       	sw \$sp,\(\$sp\)
+  7e:	0f fe       	lw \$sp,\(\$sp\)
+  80:	40 7e       	sw \$0,0x7c\(\$sp\)
+  82:	40 7f       	lw \$0,0x7c\(\$sp\)
+  84:	4f 7e       	sw \$sp,0x7c\(\$sp\)
+  86:	4f 7f       	lw \$sp,0x7c\(\$sp\)
+  88:	00 d8       	sb \$0,\(\$tp\)
+  8a:	00 dc       	lb \$0,\(\$tp\)
+  8c:	00 db       	lbu \$0,\(\$tp\)
+  8e:	07 d8       	sb \$7,\(\$tp\)
+  90:	07 dc       	lb \$7,\(\$tp\)
+  92:	07 db       	lbu \$7,\(\$tp\)
+  94:	80 7f       	sb \$0,0x7f\(\$tp\)
+  96:	88 7f       	lb \$0,0x7f\(\$tp\)
+  98:	48 ff       	lbu \$0,0x7f\(\$tp\)
+  9a:	87 7f       	sb \$7,0x7f\(\$tp\)
+  9c:	8f 7f       	lb \$7,0x7f\(\$tp\)
+  9e:	4f ff       	lbu \$7,0x7f\(\$tp\)
+  a0:	80 00       	sb \$0,0x0\(\$tp\)
+			a0: R_MEP_TPREL7	symbol
+  a2:	88 00       	lb \$0,0x0\(\$tp\)
+			a2: R_MEP_TPREL7	symbol
+  a4:	48 80       	lbu \$0,0x0\(\$tp\)
+			a4: R_MEP_TPREL7	symbol
+  a6:	87 00       	sb \$7,0x0\(\$tp\)
+			a6: R_MEP_TPREL7	symbol
+  a8:	8f 00       	lb \$7,0x0\(\$tp\)
+			a8: R_MEP_TPREL7	symbol
+  aa:	4f 80       	lbu \$7,0x0\(\$tp\)
+			aa: R_MEP_TPREL7	symbol
+  ac:	00 d8       	sb \$0,\(\$tp\)
+  ae:	00 dc       	lb \$0,\(\$tp\)
+  b0:	00 db       	lbu \$0,\(\$tp\)
+  b2:	07 d8       	sb \$7,\(\$tp\)
+  b4:	07 dc       	lb \$7,\(\$tp\)
+  b6:	07 db       	lbu \$7,\(\$tp\)
+  b8:	80 7f       	sb \$0,0x7f\(\$tp\)
+  ba:	88 7f       	lb \$0,0x7f\(\$tp\)
+  bc:	48 ff       	lbu \$0,0x7f\(\$tp\)
+  be:	87 7f       	sb \$7,0x7f\(\$tp\)
+  c0:	8f 7f       	lb \$7,0x7f\(\$tp\)
+  c2:	4f ff       	lbu \$7,0x7f\(\$tp\)
+  c4:	80 00       	sb \$0,0x0\(\$tp\)
+			c4: R_MEP_TPREL7	symbol
+  c6:	88 00       	lb \$0,0x0\(\$tp\)
+			c6: R_MEP_TPREL7	symbol
+  c8:	48 80       	lbu \$0,0x0\(\$tp\)
+			c8: R_MEP_TPREL7	symbol
+  ca:	87 00       	sb \$7,0x0\(\$tp\)
+			ca: R_MEP_TPREL7	symbol
+  cc:	8f 00       	lb \$7,0x0\(\$tp\)
+			cc: R_MEP_TPREL7	symbol
+  ce:	4f 80       	lbu \$7,0x0\(\$tp\)
+			ce: R_MEP_TPREL7	symbol
+  d0:	00 d9       	sh \$0,\(\$tp\)
+  d2:	00 dd       	lh \$0,\(\$tp\)
+  d4:	00 df       	lhu \$0,\(\$tp\)
+  d6:	07 d9       	sh \$7,\(\$tp\)
+  d8:	07 dd       	lh \$7,\(\$tp\)
+  da:	07 df       	lhu \$7,\(\$tp\)
+  dc:	80 fe       	sh \$0,0x7e\(\$tp\)
+  de:	88 fe       	lh \$0,0x7e\(\$tp\)
+  e0:	88 ff       	lhu \$0,0x7e\(\$tp\)
+  e2:	87 fe       	sh \$7,0x7e\(\$tp\)
+  e4:	8f fe       	lh \$7,0x7e\(\$tp\)
+  e6:	8f ff       	lhu \$7,0x7e\(\$tp\)
+  e8:	80 80       	sh \$0,0x0\(\$tp\)
+			e8: R_MEP_TPREL7A2	symbol
+  ea:	88 80       	lh \$0,0x0\(\$tp\)
+			ea: R_MEP_TPREL7A2	symbol
+  ec:	88 81       	lhu \$0,0x0\(\$tp\)
+			ec: R_MEP_TPREL7A2	symbol
+  ee:	87 80       	sh \$7,0x0\(\$tp\)
+			ee: R_MEP_TPREL7A2	symbol
+  f0:	8f 80       	lh \$7,0x0\(\$tp\)
+			f0: R_MEP_TPREL7A2	symbol
+  f2:	8f 81       	lhu \$7,0x0\(\$tp\)
+			f2: R_MEP_TPREL7A2	symbol
+  f4:	00 d9       	sh \$0,\(\$tp\)
+  f6:	00 dd       	lh \$0,\(\$tp\)
+  f8:	00 df       	lhu \$0,\(\$tp\)
+  fa:	07 d9       	sh \$7,\(\$tp\)
+  fc:	07 dd       	lh \$7,\(\$tp\)
+  fe:	07 df       	lhu \$7,\(\$tp\)
+ 100:	80 fe       	sh \$0,0x7e\(\$tp\)
+ 102:	88 fe       	lh \$0,0x7e\(\$tp\)
+ 104:	88 ff       	lhu \$0,0x7e\(\$tp\)
+ 106:	87 fe       	sh \$7,0x7e\(\$tp\)
+ 108:	8f fe       	lh \$7,0x7e\(\$tp\)
+ 10a:	8f ff       	lhu \$7,0x7e\(\$tp\)
+ 10c:	80 80       	sh \$0,0x0\(\$tp\)
+			10c: R_MEP_TPREL7A2	symbol
+ 10e:	88 80       	lh \$0,0x0\(\$tp\)
+			10e: R_MEP_TPREL7A2	symbol
+ 110:	88 81       	lhu \$0,0x0\(\$tp\)
+			110: R_MEP_TPREL7A2	symbol
+ 112:	87 80       	sh \$7,0x0\(\$tp\)
+			112: R_MEP_TPREL7A2	symbol
+ 114:	8f 80       	lh \$7,0x0\(\$tp\)
+			114: R_MEP_TPREL7A2	symbol
+ 116:	8f 81       	lhu \$7,0x0\(\$tp\)
+			116: R_MEP_TPREL7A2	symbol
+ 118:	00 da       	sw \$0,\(\$tp\)
+ 11a:	00 de       	lw \$0,\(\$tp\)
+ 11c:	07 da       	sw \$7,\(\$tp\)
+ 11e:	07 de       	lw \$7,\(\$tp\)
+ 120:	40 fe       	sw \$0,0x7c\(\$tp\)
+ 122:	40 ff       	lw \$0,0x7c\(\$tp\)
+ 124:	47 fe       	sw \$7,0x7c\(\$tp\)
+ 126:	47 ff       	lw \$7,0x7c\(\$tp\)
+ 128:	40 82       	sw \$0,0x0\(\$tp\)
+			128: R_MEP_TPREL7A4	symbol
+ 12a:	40 83       	lw \$0,0x0\(\$tp\)
+			12a: R_MEP_TPREL7A4	symbol
+ 12c:	47 82       	sw \$7,0x0\(\$tp\)
+			12c: R_MEP_TPREL7A4	symbol
+ 12e:	47 83       	lw \$7,0x0\(\$tp\)
+			12e: R_MEP_TPREL7A4	symbol
+ 130:	00 da       	sw \$0,\(\$tp\)
+ 132:	00 de       	lw \$0,\(\$tp\)
+ 134:	07 da       	sw \$7,\(\$tp\)
+ 136:	07 de       	lw \$7,\(\$tp\)
+ 138:	40 fe       	sw \$0,0x7c\(\$tp\)
+ 13a:	40 ff       	lw \$0,0x7c\(\$tp\)
+ 13c:	47 fe       	sw \$7,0x7c\(\$tp\)
+ 13e:	47 ff       	lw \$7,0x7c\(\$tp\)
+ 140:	40 82       	sw \$0,0x0\(\$tp\)
+			140: R_MEP_TPREL7A4	symbol
+ 142:	40 83       	lw \$0,0x0\(\$tp\)
+			142: R_MEP_TPREL7A4	symbol
+ 144:	47 82       	sw \$7,0x0\(\$tp\)
+			144: R_MEP_TPREL7A4	symbol
+ 146:	47 83       	lw \$7,0x0\(\$tp\)
+			146: R_MEP_TPREL7A4	symbol
+ 148:	c0 08 80 00 	sb \$0,-32768\(\$0\)
+ 14c:	c0 09 80 00 	sh \$0,-32768\(\$0\)
+ 150:	c0 0a 80 00 	sw \$0,-32768\(\$0\)
+ 154:	c0 0c 80 00 	lb \$0,-32768\(\$0\)
+ 158:	c0 0d 80 00 	lh \$0,-32768\(\$0\)
+ 15c:	c0 0e 80 00 	lw \$0,-32768\(\$0\)
+ 160:	c0 0b 80 00 	lbu \$0,-32768\(\$0\)
+ 164:	c0 0f 80 00 	lhu \$0,-32768\(\$0\)
+ 168:	cf 08 80 00 	sb \$sp,-32768\(\$0\)
+ 16c:	cf 09 80 00 	sh \$sp,-32768\(\$0\)
+ 170:	cf 0a 80 00 	sw \$sp,-32768\(\$0\)
+ 174:	cf 0c 80 00 	lb \$sp,-32768\(\$0\)
+ 178:	cf 0d 80 00 	lh \$sp,-32768\(\$0\)
+ 17c:	cf 0e 80 00 	lw \$sp,-32768\(\$0\)
+ 180:	cf 0b 80 00 	lbu \$sp,-32768\(\$0\)
+ 184:	cf 0f 80 00 	lhu \$sp,-32768\(\$0\)
+ 188:	c0 08 7f ff 	sb \$0,32767\(\$0\)
+ 18c:	c0 09 7f ff 	sh \$0,32767\(\$0\)
+ 190:	c0 0a 7f ff 	sw \$0,32767\(\$0\)
+ 194:	c0 0c 7f ff 	lb \$0,32767\(\$0\)
+ 198:	c0 0d 7f ff 	lh \$0,32767\(\$0\)
+ 19c:	c0 0e 7f ff 	lw \$0,32767\(\$0\)
+ 1a0:	c0 0b 7f ff 	lbu \$0,32767\(\$0\)
+ 1a4:	c0 0f 7f ff 	lhu \$0,32767\(\$0\)
+ 1a8:	cf 08 7f ff 	sb \$sp,32767\(\$0\)
+ 1ac:	cf 09 7f ff 	sh \$sp,32767\(\$0\)
+ 1b0:	cf 0a 7f ff 	sw \$sp,32767\(\$0\)
+ 1b4:	cf 0c 7f ff 	lb \$sp,32767\(\$0\)
+ 1b8:	cf 0d 7f ff 	lh \$sp,32767\(\$0\)
+ 1bc:	cf 0e 7f ff 	lw \$sp,32767\(\$0\)
+ 1c0:	cf 0b 7f ff 	lbu \$sp,32767\(\$0\)
+ 1c4:	cf 0f 7f ff 	lhu \$sp,32767\(\$0\)
+ 1c8:	c0 08 00 00 	sb \$0,0\(\$0\)
+			1c8: R_MEP_GPREL	symbol
+ 1cc:	c0 09 00 00 	sh \$0,0\(\$0\)
+			1cc: R_MEP_GPREL	symbol
+ 1d0:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			1d0: R_MEP_GPREL	symbol
+ 1d4:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			1d4: R_MEP_GPREL	symbol
+ 1d8:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			1d8: R_MEP_GPREL	symbol
+ 1dc:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			1dc: R_MEP_GPREL	symbol
+ 1e0:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			1e0: R_MEP_GPREL	symbol
+ 1e4:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			1e4: R_MEP_GPREL	symbol
+ 1e8:	cf 08 00 00 	sb \$sp,0\(\$0\)
+			1e8: R_MEP_GPREL	symbol
+ 1ec:	cf 09 00 00 	sh \$sp,0\(\$0\)
+			1ec: R_MEP_GPREL	symbol
+ 1f0:	cf 0a 00 00 	sw \$sp,0\(\$0\)
+			1f0: R_MEP_GPREL	symbol
+ 1f4:	cf 0c 00 00 	lb \$sp,0\(\$0\)
+			1f4: R_MEP_GPREL	symbol
+ 1f8:	cf 0d 00 00 	lh \$sp,0\(\$0\)
+			1f8: R_MEP_GPREL	symbol
+ 1fc:	cf 0e 00 00 	lw \$sp,0\(\$0\)
+			1fc: R_MEP_GPREL	symbol
+ 200:	cf 0b 00 00 	lbu \$sp,0\(\$0\)
+			200: R_MEP_GPREL	symbol
+ 204:	cf 0f 00 00 	lhu \$sp,0\(\$0\)
+			204: R_MEP_GPREL	symbol
+ 208:	c0 08 80 00 	sb \$0,-32768\(\$0\)
+ 20c:	c0 09 80 00 	sh \$0,-32768\(\$0\)
+ 210:	c0 0a 80 00 	sw \$0,-32768\(\$0\)
+ 214:	c0 0c 80 00 	lb \$0,-32768\(\$0\)
+ 218:	c0 0d 80 00 	lh \$0,-32768\(\$0\)
+ 21c:	c0 0e 80 00 	lw \$0,-32768\(\$0\)
+ 220:	c0 0b 80 00 	lbu \$0,-32768\(\$0\)
+ 224:	c0 0f 80 00 	lhu \$0,-32768\(\$0\)
+ 228:	cf 08 80 00 	sb \$sp,-32768\(\$0\)
+ 22c:	cf 09 80 00 	sh \$sp,-32768\(\$0\)
+ 230:	cf 0a 80 00 	sw \$sp,-32768\(\$0\)
+ 234:	cf 0c 80 00 	lb \$sp,-32768\(\$0\)
+ 238:	cf 0d 80 00 	lh \$sp,-32768\(\$0\)
+ 23c:	cf 0e 80 00 	lw \$sp,-32768\(\$0\)
+ 240:	cf 0b 80 00 	lbu \$sp,-32768\(\$0\)
+ 244:	cf 0f 80 00 	lhu \$sp,-32768\(\$0\)
+ 248:	c0 08 7f ff 	sb \$0,32767\(\$0\)
+ 24c:	c0 09 7f ff 	sh \$0,32767\(\$0\)
+ 250:	c0 0a 7f ff 	sw \$0,32767\(\$0\)
+ 254:	c0 0c 7f ff 	lb \$0,32767\(\$0\)
+ 258:	c0 0d 7f ff 	lh \$0,32767\(\$0\)
+ 25c:	c0 0e 7f ff 	lw \$0,32767\(\$0\)
+ 260:	c0 0b 7f ff 	lbu \$0,32767\(\$0\)
+ 264:	c0 0f 7f ff 	lhu \$0,32767\(\$0\)
+ 268:	cf 08 7f ff 	sb \$sp,32767\(\$0\)
+ 26c:	cf 09 7f ff 	sh \$sp,32767\(\$0\)
+ 270:	cf 0a 7f ff 	sw \$sp,32767\(\$0\)
+ 274:	cf 0c 7f ff 	lb \$sp,32767\(\$0\)
+ 278:	cf 0d 7f ff 	lh \$sp,32767\(\$0\)
+ 27c:	cf 0e 7f ff 	lw \$sp,32767\(\$0\)
+ 280:	cf 0b 7f ff 	lbu \$sp,32767\(\$0\)
+ 284:	cf 0f 7f ff 	lhu \$sp,32767\(\$0\)
+ 288:	c0 08 00 00 	sb \$0,0\(\$0\)
+			288: R_MEP_TPREL	symbol
+ 28c:	c0 09 00 00 	sh \$0,0\(\$0\)
+			28c: R_MEP_TPREL	symbol
+ 290:	c0 0a 00 00 	sw \$0,0\(\$0\)
+			290: R_MEP_TPREL	symbol
+ 294:	c0 0c 00 00 	lb \$0,0\(\$0\)
+			294: R_MEP_TPREL	symbol
+ 298:	c0 0d 00 00 	lh \$0,0\(\$0\)
+			298: R_MEP_TPREL	symbol
+ 29c:	c0 0e 00 00 	lw \$0,0\(\$0\)
+			29c: R_MEP_TPREL	symbol
+ 2a0:	c0 0b 00 00 	lbu \$0,0\(\$0\)
+			2a0: R_MEP_TPREL	symbol
+ 2a4:	c0 0f 00 00 	lhu \$0,0\(\$0\)
+			2a4: R_MEP_TPREL	symbol
+ 2a8:	cf 08 00 00 	sb \$sp,0\(\$0\)
+			2a8: R_MEP_TPREL	symbol
+ 2ac:	cf 09 00 00 	sh \$sp,0\(\$0\)
+			2ac: R_MEP_TPREL	symbol
+ 2b0:	cf 0a 00 00 	sw \$sp,0\(\$0\)
+			2b0: R_MEP_TPREL	symbol
+ 2b4:	cf 0c 00 00 	lb \$sp,0\(\$0\)
+			2b4: R_MEP_TPREL	symbol
+ 2b8:	cf 0d 00 00 	lh \$sp,0\(\$0\)
+			2b8: R_MEP_TPREL	symbol
+ 2bc:	cf 0e 00 00 	lw \$sp,0\(\$0\)
+			2bc: R_MEP_TPREL	symbol
+ 2c0:	cf 0b 00 00 	lbu \$sp,0\(\$0\)
+			2c0: R_MEP_TPREL	symbol
+ 2c4:	cf 0f 00 00 	lhu \$sp,0\(\$0\)
+			2c4: R_MEP_TPREL	symbol
+ 2c8:	c0 f8 80 00 	sb \$0,-32768\(\$sp\)
+ 2cc:	c0 f9 80 00 	sh \$0,-32768\(\$sp\)
+ 2d0:	c0 fa 80 00 	sw \$0,-32768\(\$sp\)
+ 2d4:	c0 fc 80 00 	lb \$0,-32768\(\$sp\)
+ 2d8:	c0 fd 80 00 	lh \$0,-32768\(\$sp\)
+ 2dc:	c0 fe 80 00 	lw \$0,-32768\(\$sp\)
+ 2e0:	c0 fb 80 00 	lbu \$0,-32768\(\$sp\)
+ 2e4:	c0 ff 80 00 	lhu \$0,-32768\(\$sp\)
+ 2e8:	cf f8 80 00 	sb \$sp,-32768\(\$sp\)
+ 2ec:	cf f9 80 00 	sh \$sp,-32768\(\$sp\)
+ 2f0:	cf fa 80 00 	sw \$sp,-32768\(\$sp\)
+ 2f4:	cf fc 80 00 	lb \$sp,-32768\(\$sp\)
+ 2f8:	cf fd 80 00 	lh \$sp,-32768\(\$sp\)
+ 2fc:	cf fe 80 00 	lw \$sp,-32768\(\$sp\)
+ 300:	cf fb 80 00 	lbu \$sp,-32768\(\$sp\)
+ 304:	cf ff 80 00 	lhu \$sp,-32768\(\$sp\)
+ 308:	c0 f8 7f ff 	sb \$0,32767\(\$sp\)
+ 30c:	c0 f9 7f ff 	sh \$0,32767\(\$sp\)
+ 310:	c0 fa 7f ff 	sw \$0,32767\(\$sp\)
+ 314:	c0 fc 7f ff 	lb \$0,32767\(\$sp\)
+ 318:	c0 fd 7f ff 	lh \$0,32767\(\$sp\)
+ 31c:	c0 fe 7f ff 	lw \$0,32767\(\$sp\)
+ 320:	c0 fb 7f ff 	lbu \$0,32767\(\$sp\)
+ 324:	c0 ff 7f ff 	lhu \$0,32767\(\$sp\)
+ 328:	cf f8 7f ff 	sb \$sp,32767\(\$sp\)
+ 32c:	cf f9 7f ff 	sh \$sp,32767\(\$sp\)
+ 330:	cf fa 7f ff 	sw \$sp,32767\(\$sp\)
+ 334:	cf fc 7f ff 	lb \$sp,32767\(\$sp\)
+ 338:	cf fd 7f ff 	lh \$sp,32767\(\$sp\)
+ 33c:	cf fe 7f ff 	lw \$sp,32767\(\$sp\)
+ 340:	cf fb 7f ff 	lbu \$sp,32767\(\$sp\)
+ 344:	cf ff 7f ff 	lhu \$sp,32767\(\$sp\)
+ 348:	c0 f8 00 00 	sb \$0,0\(\$sp\)
+			348: R_MEP_GPREL	symbol
+ 34c:	c0 f9 00 00 	sh \$0,0\(\$sp\)
+			34c: R_MEP_GPREL	symbol
+ 350:	c0 fa 00 00 	sw \$0,0\(\$sp\)
+			350: R_MEP_GPREL	symbol
+ 354:	c0 fc 00 00 	lb \$0,0\(\$sp\)
+			354: R_MEP_GPREL	symbol
+ 358:	c0 fd 00 00 	lh \$0,0\(\$sp\)
+			358: R_MEP_GPREL	symbol
+ 35c:	c0 fe 00 00 	lw \$0,0\(\$sp\)
+			35c: R_MEP_GPREL	symbol
+ 360:	c0 fb 00 00 	lbu \$0,0\(\$sp\)
+			360: R_MEP_GPREL	symbol
+ 364:	c0 ff 00 00 	lhu \$0,0\(\$sp\)
+			364: R_MEP_GPREL	symbol
+ 368:	cf f8 00 00 	sb \$sp,0\(\$sp\)
+			368: R_MEP_GPREL	symbol
+ 36c:	cf f9 00 00 	sh \$sp,0\(\$sp\)
+			36c: R_MEP_GPREL	symbol
+ 370:	cf fa 00 00 	sw \$sp,0\(\$sp\)
+			370: R_MEP_GPREL	symbol
+ 374:	cf fc 00 00 	lb \$sp,0\(\$sp\)
+			374: R_MEP_GPREL	symbol
+ 378:	cf fd 00 00 	lh \$sp,0\(\$sp\)
+			378: R_MEP_GPREL	symbol
+ 37c:	cf fe 00 00 	lw \$sp,0\(\$sp\)
+			37c: R_MEP_GPREL	symbol
+ 380:	cf fb 00 00 	lbu \$sp,0\(\$sp\)
+			380: R_MEP_GPREL	symbol
+ 384:	cf ff 00 00 	lhu \$sp,0\(\$sp\)
+			384: R_MEP_GPREL	symbol
+ 388:	c0 f8 80 00 	sb \$0,-32768\(\$sp\)
+ 38c:	c0 f9 80 00 	sh \$0,-32768\(\$sp\)
+ 390:	c0 fa 80 00 	sw \$0,-32768\(\$sp\)
+ 394:	c0 fc 80 00 	lb \$0,-32768\(\$sp\)
+ 398:	c0 fd 80 00 	lh \$0,-32768\(\$sp\)
+ 39c:	c0 fe 80 00 	lw \$0,-32768\(\$sp\)
+ 3a0:	c0 fb 80 00 	lbu \$0,-32768\(\$sp\)
+ 3a4:	c0 ff 80 00 	lhu \$0,-32768\(\$sp\)
+ 3a8:	cf f8 80 00 	sb \$sp,-32768\(\$sp\)
+ 3ac:	cf f9 80 00 	sh \$sp,-32768\(\$sp\)
+ 3b0:	cf fa 80 00 	sw \$sp,-32768\(\$sp\)
+ 3b4:	cf fc 80 00 	lb \$sp,-32768\(\$sp\)
+ 3b8:	cf fd 80 00 	lh \$sp,-32768\(\$sp\)
+ 3bc:	cf fe 80 00 	lw \$sp,-32768\(\$sp\)
+ 3c0:	cf fb 80 00 	lbu \$sp,-32768\(\$sp\)
+ 3c4:	cf ff 80 00 	lhu \$sp,-32768\(\$sp\)
+ 3c8:	c0 f8 7f ff 	sb \$0,32767\(\$sp\)
+ 3cc:	c0 f9 7f ff 	sh \$0,32767\(\$sp\)
+ 3d0:	c0 fa 7f ff 	sw \$0,32767\(\$sp\)
+ 3d4:	c0 fc 7f ff 	lb \$0,32767\(\$sp\)
+ 3d8:	c0 fd 7f ff 	lh \$0,32767\(\$sp\)
+ 3dc:	c0 fe 7f ff 	lw \$0,32767\(\$sp\)
+ 3e0:	c0 fb 7f ff 	lbu \$0,32767\(\$sp\)
+ 3e4:	c0 ff 7f ff 	lhu \$0,32767\(\$sp\)
+ 3e8:	cf f8 7f ff 	sb \$sp,32767\(\$sp\)
+ 3ec:	cf f9 7f ff 	sh \$sp,32767\(\$sp\)
+ 3f0:	cf fa 7f ff 	sw \$sp,32767\(\$sp\)
+ 3f4:	cf fc 7f ff 	lb \$sp,32767\(\$sp\)
+ 3f8:	cf fd 7f ff 	lh \$sp,32767\(\$sp\)
+ 3fc:	cf fe 7f ff 	lw \$sp,32767\(\$sp\)
+ 400:	cf fb 7f ff 	lbu \$sp,32767\(\$sp\)
+ 404:	cf ff 7f ff 	lhu \$sp,32767\(\$sp\)
+ 408:	c0 f8 00 00 	sb \$0,0\(\$sp\)
+			408: R_MEP_TPREL	symbol
+ 40c:	c0 f9 00 00 	sh \$0,0\(\$sp\)
+			40c: R_MEP_TPREL	symbol
+ 410:	40 02       	sw \$0,0x0\(\$sp\)
+			410: R_MEP_TPREL7A4	symbol
+ 412:	c0 fc 00 00 	lb \$0,0\(\$sp\)
+			412: R_MEP_TPREL	symbol
+ 416:	c0 fd 00 00 	lh \$0,0\(\$sp\)
+			416: R_MEP_TPREL	symbol
+ 41a:	40 03       	lw \$0,0x0\(\$sp\)
+			41a: R_MEP_TPREL7A4	symbol
+ 41c:	c0 fb 00 00 	lbu \$0,0\(\$sp\)
+			41c: R_MEP_TPREL	symbol
+ 420:	c0 ff 00 00 	lhu \$0,0\(\$sp\)
+			420: R_MEP_TPREL	symbol
+ 424:	cf f8 00 00 	sb \$sp,0\(\$sp\)
+			424: R_MEP_TPREL	symbol
+ 428:	cf f9 00 00 	sh \$sp,0\(\$sp\)
+			428: R_MEP_TPREL	symbol
+ 42c:	4f 02       	sw \$sp,0x0\(\$sp\)
+			42c: R_MEP_TPREL7A4	symbol
+ 42e:	cf fc 00 00 	lb \$sp,0\(\$sp\)
+			42e: R_MEP_TPREL	symbol
+ 432:	cf fd 00 00 	lh \$sp,0\(\$sp\)
+			432: R_MEP_TPREL	symbol
+ 436:	4f 03       	lw \$sp,0x0\(\$sp\)
+			436: R_MEP_TPREL7A4	symbol
+ 438:	cf fb 00 00 	lbu \$sp,0\(\$sp\)
+			438: R_MEP_TPREL	symbol
+ 43c:	cf ff 00 00 	lhu \$sp,0\(\$sp\)
+			43c: R_MEP_TPREL	symbol
+ 440:	e0 02 00 00 	sw \$0,\(0x0\)
+ 444:	e0 03 00 00 	lw \$0,\(0x0\)
+ 448:	ef 02 00 00 	sw \$sp,\(0x0\)
+ 44c:	ef 03 00 00 	lw \$sp,\(0x0\)
+ 450:	e0 fe ff ff 	sw \$0,\(0xfffffc\)
+ 454:	e0 ff ff ff 	lw \$0,\(0xfffffc\)
+ 458:	ef fe ff ff 	sw \$sp,\(0xfffffc\)
+ 45c:	ef ff ff ff 	lw \$sp,\(0xfffffc\)
+ 460:	e0 02 00 00 	sw \$0,\(0x0\)
+			460: R_MEP_ADDR24A4	symbol
+ 464:	e0 03 00 00 	lw \$0,\(0x0\)
+			464: R_MEP_ADDR24A4	symbol
+ 468:	ef 02 00 00 	sw \$sp,\(0x0\)
+			468: R_MEP_ADDR24A4	symbol
+ 46c:	ef 03 00 00 	lw \$sp,\(0x0\)
+			46c: R_MEP_ADDR24A4	symbol
+ 470:	10 0d       	extb \$0
+ 472:	10 8d       	extub \$0
+ 474:	10 2d       	exth \$0
+ 476:	10 ad       	extuh \$0
+ 478:	1f 0d       	extb \$sp
+ 47a:	1f 8d       	extub \$sp
+ 47c:	1f 2d       	exth \$sp
+ 47e:	1f ad       	extuh \$sp
+ 480:	10 0c       	ssarb 0\(\$0\)
+ 482:	13 0c       	ssarb 3\(\$0\)
+ 484:	10 fc       	ssarb 0\(\$sp\)
+ 486:	13 fc       	ssarb 3\(\$sp\)
+ 488:	00 00       	nop
+ 48a:	0f 00       	mov \$sp,\$0
+ 48c:	00 f0       	mov \$0,\$sp
+ 48e:	0f f0       	mov \$sp,\$sp
+ 490:	c0 01 80 00 	mov \$0,-32768
+ 494:	cf 01 80 00 	mov \$sp,-32768
+ 498:	50 80       	mov \$0,-128
+ 49a:	5f 80       	mov \$sp,-128
+ 49c:	50 00       	mov \$0,0
+ 49e:	5f 00       	mov \$sp,0
+ 4a0:	50 7f       	mov \$0,127
+ 4a2:	5f 7f       	mov \$sp,127
+ 4a4:	c0 01 7f ff 	mov \$0,32767
+ 4a8:	cf 01 7f ff 	mov \$sp,32767
+ 4ac:	c0 01 00 00 	mov \$0,0
+			4ac: R_MEP_LOW16	symbol
+ 4b0:	c0 01 00 00 	mov \$0,0
+			4b0: R_MEP_HI16S	symbol
+ 4b4:	c0 01 00 00 	mov \$0,0
+			4b4: R_MEP_HI16U	symbol
+ 4b8:	c0 01 00 00 	mov \$0,0
+			4b8: R_MEP_GPREL	symbol
+ 4bc:	c0 01 00 00 	mov \$0,0
+			4bc: R_MEP_TPREL	symbol
+ 4c0:	d0 00 00 00 	movu \$0,0x0
+ 4c4:	d7 00 00 00 	movu \$7,0x0
+ 4c8:	d0 ff ff ff 	movu \$0,0xffffff
+ 4cc:	d7 ff ff ff 	movu \$7,0xffffff
+ 4d0:	c0 11 00 00 	movu \$0,0x0
+			4d0: R_MEP_LOW16	symbol
+ 4d4:	c7 11 00 00 	movu \$7,0x0
+			4d4: R_MEP_LOW16	symbol
+ 4d8:	d0 00 00 00 	movu \$0,0x0
+			4d8: R_MEP_UIMM24	symbol
+ 4dc:	d7 00 00 00 	movu \$7,0x0
+			4dc: R_MEP_UIMM24	symbol
+ 4e0:	d0 00 00 00 	movu \$0,0x0
+ 4e4:	c0 21 00 00 	movh \$0,0x0
+ 4e8:	cf 11 00 00 	movu \$sp,0x0
+ 4ec:	cf 21 00 00 	movh \$sp,0x0
+ 4f0:	d0 ff 00 ff 	movu \$0,0xffff
+ 4f4:	c0 21 ff ff 	movh \$0,0xffff
+ 4f8:	cf 11 ff ff 	movu \$sp,0xffff
+ 4fc:	cf 21 ff ff 	movh \$sp,0xffff
+ 500:	c0 11 00 00 	movu \$0,0x0
+			500: R_MEP_LOW16	symbol
+ 504:	c0 21 00 00 	movh \$0,0x0
+			504: R_MEP_LOW16	symbol
+ 508:	cf 11 00 00 	movu \$sp,0x0
+			508: R_MEP_LOW16	symbol
+ 50c:	cf 21 00 00 	movh \$sp,0x0
+			50c: R_MEP_LOW16	symbol
+ 510:	c0 11 00 00 	movu \$0,0x0
+			510: R_MEP_HI16S	symbol
+ 514:	c0 21 00 00 	movh \$0,0x0
+			514: R_MEP_HI16S	symbol
+ 518:	cf 11 00 00 	movu \$sp,0x0
+			518: R_MEP_HI16S	symbol
+ 51c:	cf 21 00 00 	movh \$sp,0x0
+			51c: R_MEP_HI16S	symbol
+ 520:	c0 11 00 00 	movu \$0,0x0
+			520: R_MEP_HI16U	symbol
+ 524:	c0 21 00 00 	movh \$0,0x0
+			524: R_MEP_HI16U	symbol
+ 528:	cf 11 00 00 	movu \$sp,0x0
+			528: R_MEP_HI16U	symbol
+ 52c:	cf 21 00 00 	movh \$sp,0x0
+			52c: R_MEP_HI16U	symbol
+ 530:	c0 11 56 78 	movu \$0,0x5678
+ 534:	c0 21 56 78 	movh \$0,0x5678
+ 538:	cf 11 56 78 	movu \$sp,0x5678
+ 53c:	cf 21 56 78 	movh \$sp,0x5678
+ 540:	c0 11 12 34 	movu \$0,0x1234
+ 544:	c0 21 12 34 	movh \$0,0x1234
+ 548:	cf 11 12 34 	movu \$sp,0x1234
+ 54c:	cf 21 12 34 	movh \$sp,0x1234
+ 550:	c0 11 12 34 	movu \$0,0x1234
+ 554:	c0 21 12 34 	movh \$0,0x1234
+ 558:	cf 11 12 34 	movu \$sp,0x1234
+ 55c:	cf 21 12 34 	movh \$sp,0x1234
+ 560:	90 00       	add3 \$0,\$0,\$0
+ 562:	90 0f       	add3 \$sp,\$0,\$0
+ 564:	9f 00       	add3 \$0,\$sp,\$0
+ 566:	9f 0f       	add3 \$sp,\$sp,\$0
+ 568:	90 f0       	add3 \$0,\$0,\$sp
+ 56a:	90 ff       	add3 \$sp,\$0,\$sp
+ 56c:	9f f0       	add3 \$0,\$sp,\$sp
+ 56e:	9f ff       	add3 \$sp,\$sp,\$sp
+ 570:	60 c0       	add \$0,-16
+ 572:	6f c0       	add \$sp,-16
+ 574:	60 00       	add \$0,0
+ 576:	6f 00       	add \$sp,0
+ 578:	60 3c       	add \$0,15
+ 57a:	6f 3c       	add \$sp,15
+ 57c:	40 00       	add3 \$0,\$sp,0x0
+ 57e:	4f 00       	add3 \$sp,\$sp,0x0
+ 580:	40 7c       	add3 \$0,\$sp,0x7c
+ 582:	4f 7c       	add3 \$sp,\$sp,0x7c
+ 584:	c0 f0 00 01 	add3 \$0,\$sp,1
+ 588:	cf f0 00 01 	add3 \$sp,\$sp,1
+ 58c:	00 07       	advck3 \$0,\$0,\$0
+ 58e:	00 05       	sbvck3 \$0,\$0,\$0
+ 590:	0f 07       	advck3 \$0,\$sp,\$0
+ 592:	0f 05       	sbvck3 \$0,\$sp,\$0
+ 594:	00 f7       	advck3 \$0,\$0,\$sp
+ 596:	00 f5       	sbvck3 \$0,\$0,\$sp
+ 598:	0f f7       	advck3 \$0,\$sp,\$sp
+ 59a:	0f f5       	sbvck3 \$0,\$sp,\$sp
+ 59c:	00 04       	sub \$0,\$0
+ 59e:	00 01       	neg \$0,\$0
+ 5a0:	0f 04       	sub \$sp,\$0
+ 5a2:	0f 01       	neg \$sp,\$0
+ 5a4:	00 f4       	sub \$0,\$sp
+ 5a6:	00 f1       	neg \$0,\$sp
+ 5a8:	0f f4       	sub \$sp,\$sp
+ 5aa:	0f f1       	neg \$sp,\$sp
+ 5ac:	00 02       	slt3 \$0,\$0,\$0
+ 5ae:	00 03       	sltu3 \$0,\$0,\$0
+ 5b0:	20 06       	sl1ad3 \$0,\$0,\$0
+ 5b2:	20 07       	sl2ad3 \$0,\$0,\$0
+ 5b4:	0f 02       	slt3 \$0,\$sp,\$0
+ 5b6:	0f 03       	sltu3 \$0,\$sp,\$0
+ 5b8:	2f 06       	sl1ad3 \$0,\$sp,\$0
+ 5ba:	2f 07       	sl2ad3 \$0,\$sp,\$0
+ 5bc:	00 f2       	slt3 \$0,\$0,\$sp
+ 5be:	00 f3       	sltu3 \$0,\$0,\$sp
+ 5c0:	20 f6       	sl1ad3 \$0,\$0,\$sp
+ 5c2:	20 f7       	sl2ad3 \$0,\$0,\$sp
+ 5c4:	0f f2       	slt3 \$0,\$sp,\$sp
+ 5c6:	0f f3       	sltu3 \$0,\$sp,\$sp
+ 5c8:	2f f6       	sl1ad3 \$0,\$sp,\$sp
+ 5ca:	2f f7       	sl2ad3 \$0,\$sp,\$sp
+ 5cc:	c0 00 80 00 	add3 \$0,\$0,-32768
+ 5d0:	cf 00 80 00 	add3 \$sp,\$0,-32768
+ 5d4:	c0 f0 80 00 	add3 \$0,\$sp,-32768
+ 5d8:	cf f0 80 00 	add3 \$sp,\$sp,-32768
+ 5dc:	c0 00 7f ff 	add3 \$0,\$0,32767
+ 5e0:	cf 00 7f ff 	add3 \$sp,\$0,32767
+ 5e4:	c0 f0 7f ff 	add3 \$0,\$sp,32767
+ 5e8:	cf f0 7f ff 	add3 \$sp,\$sp,32767
+ 5ec:	c0 00 00 00 	add3 \$0,\$0,0
+			5ec: R_MEP_LOW16	symbol
+ 5f0:	cf 00 00 00 	add3 \$sp,\$0,0
+			5f0: R_MEP_LOW16	symbol
+ 5f4:	c0 f0 00 00 	add3 \$0,\$sp,0
+			5f4: R_MEP_LOW16	symbol
+ 5f8:	cf f0 00 00 	add3 \$sp,\$sp,0
+			5f8: R_MEP_LOW16	symbol
+ 5fc:	60 01       	slt3 \$0,\$0,0x0
+ 5fe:	60 05       	sltu3 \$0,\$0,0x0
+ 600:	6f 01       	slt3 \$0,\$sp,0x0
+ 602:	6f 05       	sltu3 \$0,\$sp,0x0
+ 604:	60 f9       	slt3 \$0,\$0,0x1f
+ 606:	60 fd       	sltu3 \$0,\$0,0x1f
+ 608:	6f f9       	slt3 \$0,\$sp,0x1f
+ 60a:	6f fd       	sltu3 \$0,\$sp,0x1f
+ 60c:	10 00       	or \$0,\$0
+ 60e:	10 01       	and \$0,\$0
+ 610:	10 02       	xor \$0,\$0
+ 612:	10 03       	nor \$0,\$0
+ 614:	1f 00       	or \$sp,\$0
+ 616:	1f 01       	and \$sp,\$0
+ 618:	1f 02       	xor \$sp,\$0
+ 61a:	1f 03       	nor \$sp,\$0
+ 61c:	10 f0       	or \$0,\$sp
+ 61e:	10 f1       	and \$0,\$sp
+ 620:	10 f2       	xor \$0,\$sp
+ 622:	10 f3       	nor \$0,\$sp
+ 624:	1f f0       	or \$sp,\$sp
+ 626:	1f f1       	and \$sp,\$sp
+ 628:	1f f2       	xor \$sp,\$sp
+ 62a:	1f f3       	nor \$sp,\$sp
+ 62c:	c0 04 00 00 	or3 \$0,\$0,0x0
+ 630:	c0 05 00 00 	and3 \$0,\$0,0x0
+ 634:	c0 06 00 00 	xor3 \$0,\$0,0x0
+ 638:	cf 04 00 00 	or3 \$sp,\$0,0x0
+ 63c:	cf 05 00 00 	and3 \$sp,\$0,0x0
+ 640:	cf 06 00 00 	xor3 \$sp,\$0,0x0
+ 644:	c0 f4 00 00 	or3 \$0,\$sp,0x0
+ 648:	c0 f5 00 00 	and3 \$0,\$sp,0x0
+ 64c:	c0 f6 00 00 	xor3 \$0,\$sp,0x0
+ 650:	cf f4 00 00 	or3 \$sp,\$sp,0x0
+ 654:	cf f5 00 00 	and3 \$sp,\$sp,0x0
+ 658:	cf f6 00 00 	xor3 \$sp,\$sp,0x0
+ 65c:	c0 04 ff ff 	or3 \$0,\$0,0xffff
+ 660:	c0 05 ff ff 	and3 \$0,\$0,0xffff
+ 664:	c0 06 ff ff 	xor3 \$0,\$0,0xffff
+ 668:	cf 04 ff ff 	or3 \$sp,\$0,0xffff
+ 66c:	cf 05 ff ff 	and3 \$sp,\$0,0xffff
+ 670:	cf 06 ff ff 	xor3 \$sp,\$0,0xffff
+ 674:	c0 f4 ff ff 	or3 \$0,\$sp,0xffff
+ 678:	c0 f5 ff ff 	and3 \$0,\$sp,0xffff
+ 67c:	c0 f6 ff ff 	xor3 \$0,\$sp,0xffff
+ 680:	cf f4 ff ff 	or3 \$sp,\$sp,0xffff
+ 684:	cf f5 ff ff 	and3 \$sp,\$sp,0xffff
+ 688:	cf f6 ff ff 	xor3 \$sp,\$sp,0xffff
+ 68c:	c0 04 00 00 	or3 \$0,\$0,0x0
+			68c: R_MEP_LOW16	symbol
+ 690:	c0 05 00 00 	and3 \$0,\$0,0x0
+			690: R_MEP_LOW16	symbol
+ 694:	c0 06 00 00 	xor3 \$0,\$0,0x0
+			694: R_MEP_LOW16	symbol
+ 698:	cf 04 00 00 	or3 \$sp,\$0,0x0
+			698: R_MEP_LOW16	symbol
+ 69c:	cf 05 00 00 	and3 \$sp,\$0,0x0
+			69c: R_MEP_LOW16	symbol
+ 6a0:	cf 06 00 00 	xor3 \$sp,\$0,0x0
+			6a0: R_MEP_LOW16	symbol
+ 6a4:	c0 f4 00 00 	or3 \$0,\$sp,0x0
+			6a4: R_MEP_LOW16	symbol
+ 6a8:	c0 f5 00 00 	and3 \$0,\$sp,0x0
+			6a8: R_MEP_LOW16	symbol
+ 6ac:	c0 f6 00 00 	xor3 \$0,\$sp,0x0
+			6ac: R_MEP_LOW16	symbol
+ 6b0:	cf f4 00 00 	or3 \$sp,\$sp,0x0
+			6b0: R_MEP_LOW16	symbol
+ 6b4:	cf f5 00 00 	and3 \$sp,\$sp,0x0
+			6b4: R_MEP_LOW16	symbol
+ 6b8:	cf f6 00 00 	xor3 \$sp,\$sp,0x0
+			6b8: R_MEP_LOW16	symbol
+ 6bc:	20 0d       	sra \$0,\$0
+ 6be:	20 0c       	srl \$0,\$0
+ 6c0:	20 0e       	sll \$0,\$0
+ 6c2:	20 0f       	fsft \$0,\$0
+ 6c4:	2f 0d       	sra \$sp,\$0
+ 6c6:	2f 0c       	srl \$sp,\$0
+ 6c8:	2f 0e       	sll \$sp,\$0
+ 6ca:	2f 0f       	fsft \$sp,\$0
+ 6cc:	20 fd       	sra \$0,\$sp
+ 6ce:	20 fc       	srl \$0,\$sp
+ 6d0:	20 fe       	sll \$0,\$sp
+ 6d2:	20 ff       	fsft \$0,\$sp
+ 6d4:	2f fd       	sra \$sp,\$sp
+ 6d6:	2f fc       	srl \$sp,\$sp
+ 6d8:	2f fe       	sll \$sp,\$sp
+ 6da:	2f ff       	fsft \$sp,\$sp
+ 6dc:	60 03       	sra \$0,0x0
+ 6de:	60 02       	srl \$0,0x0
+ 6e0:	60 06       	sll \$0,0x0
+ 6e2:	6f 03       	sra \$sp,0x0
+ 6e4:	6f 02       	srl \$sp,0x0
+ 6e6:	6f 06       	sll \$sp,0x0
+ 6e8:	60 fb       	sra \$0,0x1f
+ 6ea:	60 fa       	srl \$0,0x1f
+ 6ec:	60 fe       	sll \$0,0x1f
+ 6ee:	6f fb       	sra \$sp,0x1f
+ 6f0:	6f fa       	srl \$sp,0x1f
+ 6f2:	6f fe       	sll \$sp,0x1f
+ 6f4:	60 07       	sll3 \$0,\$0,0x0
+ 6f6:	6f 07       	sll3 \$0,\$sp,0x0
+ 6f8:	60 ff       	sll3 \$0,\$0,0x1f
+ 6fa:	6f ff       	sll3 \$0,\$sp,0x1f
+ 6fc:	b8 02       	bra 0xfffffefe
+ 6fe:	e0 01 04 00 	beq \$0,\$0,0xefe
+ 702:	b0 00       	bra 0x702
+			702: R_MEP_PCREL12A2	symbol
+ 704:	a0 82       	beqz \$0,0x686
+ 706:	a0 83       	bnez \$0,0x688
+ 708:	af 82       	beqz \$sp,0x68a
+ 70a:	af 83       	bnez \$sp,0x68c
+ 70c:	e0 00 00 40 	beqi \$0,0x0,0x78c
+ 710:	e0 04 00 40 	bnei \$0,0x0,0x790
+ 714:	ef 00 00 40 	beqi \$sp,0x0,0x794
+ 718:	ef 04 00 40 	bnei \$sp,0x0,0x798
+ 71c:	a0 00       	beqz \$0,0x71c
+			71c: R_MEP_PCREL8A2	symbol
+ 71e:	a0 01       	bnez \$0,0x71e
+			71e: R_MEP_PCREL8A2	symbol
+ 720:	af 00       	beqz \$sp,0x720
+			720: R_MEP_PCREL8A2	symbol
+ 722:	af 01       	bnez \$sp,0x722
+			722: R_MEP_PCREL8A2	symbol
+ 724:	e0 00 80 02 	beqi \$0,0x0,0xffff0728
+ 728:	e0 04 80 02 	bnei \$0,0x0,0xffff072c
+ 72c:	e0 0c 80 02 	blti \$0,0x0,0xffff0730
+ 730:	e0 08 80 02 	bgei \$0,0x0,0xffff0734
+ 734:	ef 00 80 02 	beqi \$sp,0x0,0xffff0738
+ 738:	ef 04 80 02 	bnei \$sp,0x0,0xffff073c
+ 73c:	ef 0c 80 02 	blti \$sp,0x0,0xffff0740
+ 740:	ef 08 80 02 	bgei \$sp,0x0,0xffff0744
+ 744:	e0 f0 80 02 	beqi \$0,0xf,0xffff0748
+ 748:	e0 f4 80 02 	bnei \$0,0xf,0xffff074c
+ 74c:	e0 fc 80 02 	blti \$0,0xf,0xffff0750
+ 750:	e0 f8 80 02 	bgei \$0,0xf,0xffff0754
+ 754:	ef f0 80 02 	beqi \$sp,0xf,0xffff0758
+ 758:	ef f4 80 02 	bnei \$sp,0xf,0xffff075c
+ 75c:	ef fc 80 02 	blti \$sp,0xf,0xffff0760
+ 760:	ef f8 80 02 	bgei \$sp,0xf,0xffff0764
+ 764:	e0 00 3f ff 	beqi \$0,0x0,0x8762
+ 768:	e0 04 3f ff 	bnei \$0,0x0,0x8766
+ 76c:	e0 0c 3f ff 	blti \$0,0x0,0x876a
+ 770:	e0 08 3f ff 	bgei \$0,0x0,0x876e
+ 774:	ef 00 3f ff 	beqi \$sp,0x0,0x8772
+ 778:	ef 04 3f ff 	bnei \$sp,0x0,0x8776
+ 77c:	ef 0c 3f ff 	blti \$sp,0x0,0x877a
+ 780:	ef 08 3f ff 	bgei \$sp,0x0,0x877e
+ 784:	e0 f0 3f ff 	beqi \$0,0xf,0x8782
+ 788:	e0 f4 3f ff 	bnei \$0,0xf,0x8786
+ 78c:	e0 fc 3f ff 	blti \$0,0xf,0x878a
+ 790:	e0 f8 3f ff 	bgei \$0,0xf,0x878e
+ 794:	ef f0 3f ff 	beqi \$sp,0xf,0x8792
+ 798:	ef f4 3f ff 	bnei \$sp,0xf,0x8796
+ 79c:	ef fc 3f ff 	blti \$sp,0xf,0x879a
+ 7a0:	ef f8 3f ff 	bgei \$sp,0xf,0x879e
+ 7a4:	e0 00 00 00 	beqi \$0,0x0,0x7a4
+			7a4: R_MEP_PCREL17A2	symbol
+ 7a8:	e0 04 00 00 	bnei \$0,0x0,0x7a8
+			7a8: R_MEP_PCREL17A2	symbol
+ 7ac:	e0 0c 00 00 	blti \$0,0x0,0x7ac
+			7ac: R_MEP_PCREL17A2	symbol
+ 7b0:	e0 08 00 00 	bgei \$0,0x0,0x7b0
+			7b0: R_MEP_PCREL17A2	symbol
+ 7b4:	ef 00 00 00 	beqi \$sp,0x0,0x7b4
+			7b4: R_MEP_PCREL17A2	symbol
+ 7b8:	ef 04 00 00 	bnei \$sp,0x0,0x7b8
+			7b8: R_MEP_PCREL17A2	symbol
+ 7bc:	ef 0c 00 00 	blti \$sp,0x0,0x7bc
+			7bc: R_MEP_PCREL17A2	symbol
+ 7c0:	ef 08 00 00 	bgei \$sp,0x0,0x7c0
+			7c0: R_MEP_PCREL17A2	symbol
+ 7c4:	e0 f0 00 00 	beqi \$0,0xf,0x7c4
+			7c4: R_MEP_PCREL17A2	symbol
+ 7c8:	e0 f4 00 00 	bnei \$0,0xf,0x7c8
+			7c8: R_MEP_PCREL17A2	symbol
+ 7cc:	e0 fc 00 00 	blti \$0,0xf,0x7cc
+			7cc: R_MEP_PCREL17A2	symbol
+ 7d0:	e0 f8 00 00 	bgei \$0,0xf,0x7d0
+			7d0: R_MEP_PCREL17A2	symbol
+ 7d4:	ef f0 00 00 	beqi \$sp,0xf,0x7d4
+			7d4: R_MEP_PCREL17A2	symbol
+ 7d8:	ef f4 00 00 	bnei \$sp,0xf,0x7d8
+			7d8: R_MEP_PCREL17A2	symbol
+ 7dc:	ef fc 00 00 	blti \$sp,0xf,0x7dc
+			7dc: R_MEP_PCREL17A2	symbol
+ 7e0:	ef f8 00 00 	bgei \$sp,0xf,0x7e0
+			7e0: R_MEP_PCREL17A2	symbol
+ 7e4:	e0 01 80 02 	beq \$0,\$0,0xffff07e8
+ 7e8:	e0 05 80 02 	bne \$0,\$0,0xffff07ec
+ 7ec:	ef 01 80 02 	beq \$sp,\$0,0xffff07f0
+ 7f0:	ef 05 80 02 	bne \$sp,\$0,0xffff07f4
+ 7f4:	e0 f1 80 02 	beq \$0,\$sp,0xffff07f8
+ 7f8:	e0 f5 80 02 	bne \$0,\$sp,0xffff07fc
+ 7fc:	ef f1 80 02 	beq \$sp,\$sp,0xffff0800
+ 800:	ef f5 80 02 	bne \$sp,\$sp,0xffff0804
+ 804:	e0 01 3f ff 	beq \$0,\$0,0x8802
+ 808:	e0 05 3f ff 	bne \$0,\$0,0x8806
+ 80c:	ef 01 3f ff 	beq \$sp,\$0,0x880a
+ 810:	ef 05 3f ff 	bne \$sp,\$0,0x880e
+ 814:	e0 f1 3f ff 	beq \$0,\$sp,0x8812
+ 818:	e0 f5 3f ff 	bne \$0,\$sp,0x8816
+ 81c:	ef f1 3f ff 	beq \$sp,\$sp,0x881a
+ 820:	ef f5 3f ff 	bne \$sp,\$sp,0x881e
+ 824:	e0 01 00 00 	beq \$0,\$0,0x824
+			824: R_MEP_PCREL17A2	symbol
+ 828:	e0 05 00 00 	bne \$0,\$0,0x828
+			828: R_MEP_PCREL17A2	symbol
+ 82c:	ef 01 00 00 	beq \$sp,\$0,0x82c
+			82c: R_MEP_PCREL17A2	symbol
+ 830:	ef 05 00 00 	bne \$sp,\$0,0x830
+			830: R_MEP_PCREL17A2	symbol
+ 834:	e0 f1 00 00 	beq \$0,\$sp,0x834
+			834: R_MEP_PCREL17A2	symbol
+ 838:	e0 f5 00 00 	bne \$0,\$sp,0x838
+			838: R_MEP_PCREL17A2	symbol
+ 83c:	ef f1 00 00 	beq \$sp,\$sp,0x83c
+			83c: R_MEP_PCREL17A2	symbol
+ 840:	ef f5 00 00 	bne \$sp,\$sp,0x840
+			840: R_MEP_PCREL17A2	symbol
+ 844:	d8 29 80 00 	bsr 0xff800848
+ 848:	b8 03       	bsr 0x4a
+ 84a:	d8 09 00 08 	bsr 0x104a
+ 84e:	d8 19 80 00 	bsr 0xff800850
+ 852:	d8 09 00 00 	bsr 0x852
+			852: R_MEP_PCREL24A2	symbol
+ 856:	10 0e       	jmp \$0
+ 858:	10 fe       	jmp \$sp
+ 85a:	d8 08 00 00 	jmp 0x0
+ 85e:	df f8 ff ff 	jmp 0xfffffe
+ 862:	d8 08 00 00 	jmp 0x0
+			862: R_MEP_PCABS24A2	symbol
+ 866:	10 0f       	jsr \$0
+ 868:	10 ff       	jsr \$sp
+ 86a:	70 02       	ret
+ 86c:	e0 09 80 02 	repeat \$0,0xffff0870
+ 870:	ef 09 80 02 	repeat \$sp,0xffff0874
+ 874:	e0 09 3f ff 	repeat \$0,0x8872
+ 878:	ef 09 3f ff 	repeat \$sp,0x8876
+ 87c:	e0 09 00 00 	repeat \$0,0x87c
+			87c: R_MEP_PCREL17A2	symbol
+ 880:	ef 09 00 00 	repeat \$sp,0x880
+			880: R_MEP_PCREL17A2	symbol
+ 884:	e0 19 80 02 	erepeat 0xffff0888
+ 888:	e0 19 3f ff 	erepeat 0x8886
+ 88c:	e0 19 00 00 	erepeat 0x88c
+			88c: R_MEP_PCREL17A2	symbol
+ 890:	70 08       	stc \$0,\$pc
+ 892:	70 0a       	ldc \$0,\$pc
+ 894:	7f 08       	stc \$sp,\$pc
+ 896:	7f 0a       	ldc \$sp,\$pc
+ 898:	70 18       	stc \$0,\$lp
+ 89a:	70 1a       	ldc \$0,\$lp
+ 89c:	7f 18       	stc \$sp,\$lp
+ 89e:	7f 1a       	ldc \$sp,\$lp
+ 8a0:	70 28       	stc \$0,\$sar
+ 8a2:	70 2a       	ldc \$0,\$sar
+ 8a4:	7f 28       	stc \$sp,\$sar
+ 8a6:	7f 2a       	ldc \$sp,\$sar
+ 8a8:	70 48       	stc \$0,\$rpb
+ 8aa:	70 4a       	ldc \$0,\$rpb
+ 8ac:	7f 48       	stc \$sp,\$rpb
+ 8ae:	7f 4a       	ldc \$sp,\$rpb
+ 8b0:	70 58       	stc \$0,\$rpe
+ 8b2:	70 5a       	ldc \$0,\$rpe
+ 8b4:	7f 58       	stc \$sp,\$rpe
+ 8b6:	7f 5a       	ldc \$sp,\$rpe
+ 8b8:	70 68       	stc \$0,\$rpc
+ 8ba:	70 6a       	ldc \$0,\$rpc
+ 8bc:	7f 68       	stc \$sp,\$rpc
+ 8be:	7f 6a       	ldc \$sp,\$rpc
+ 8c0:	70 78       	stc \$0,\$hi
+ 8c2:	70 7a       	ldc \$0,\$hi
+ 8c4:	7f 78       	stc \$sp,\$hi
+ 8c6:	7f 7a       	ldc \$sp,\$hi
+ 8c8:	70 88       	stc \$0,\$lo
+ 8ca:	70 8a       	ldc \$0,\$lo
+ 8cc:	7f 88       	stc \$sp,\$lo
+ 8ce:	7f 8a       	ldc \$sp,\$lo
+ 8d0:	70 c8       	stc \$0,\$mb0
+ 8d2:	70 ca       	ldc \$0,\$mb0
+ 8d4:	7f c8       	stc \$sp,\$mb0
+ 8d6:	7f ca       	ldc \$sp,\$mb0
+ 8d8:	70 d8       	stc \$0,\$me0
+ 8da:	70 da       	ldc \$0,\$me0
+ 8dc:	7f d8       	stc \$sp,\$me0
+ 8de:	7f da       	ldc \$sp,\$me0
+ 8e0:	70 e8       	stc \$0,\$mb1
+ 8e2:	70 ea       	ldc \$0,\$mb1
+ 8e4:	7f e8       	stc \$sp,\$mb1
+ 8e6:	7f ea       	ldc \$sp,\$mb1
+ 8e8:	70 f8       	stc \$0,\$me1
+ 8ea:	70 fa       	ldc \$0,\$me1
+ 8ec:	7f f8       	stc \$sp,\$me1
+ 8ee:	7f fa       	ldc \$sp,\$me1
+ 8f0:	70 09       	stc \$0,\$psw
+ 8f2:	70 0b       	ldc \$0,\$psw
+ 8f4:	7f 09       	stc \$sp,\$psw
+ 8f6:	7f 0b       	ldc \$sp,\$psw
+ 8f8:	70 19       	stc \$0,\$id
+ 8fa:	70 1b       	ldc \$0,\$id
+ 8fc:	7f 19       	stc \$sp,\$id
+ 8fe:	7f 1b       	ldc \$sp,\$id
+ 900:	70 29       	stc \$0,\$tmp
+ 902:	70 2b       	ldc \$0,\$tmp
+ 904:	7f 29       	stc \$sp,\$tmp
+ 906:	7f 2b       	ldc \$sp,\$tmp
+ 908:	70 39       	stc \$0,\$epc
+ 90a:	70 3b       	ldc \$0,\$epc
+ 90c:	7f 39       	stc \$sp,\$epc
+ 90e:	7f 3b       	ldc \$sp,\$epc
+ 910:	70 49       	stc \$0,\$exc
+ 912:	70 4b       	ldc \$0,\$exc
+ 914:	7f 49       	stc \$sp,\$exc
+ 916:	7f 4b       	ldc \$sp,\$exc
+ 918:	70 59       	stc \$0,\$cfg
+ 91a:	70 5b       	ldc \$0,\$cfg
+ 91c:	7f 59       	stc \$sp,\$cfg
+ 91e:	7f 5b       	ldc \$sp,\$cfg
+ 920:	70 79       	stc \$0,\$npc
+ 922:	70 7b       	ldc \$0,\$npc
+ 924:	7f 79       	stc \$sp,\$npc
+ 926:	7f 7b       	ldc \$sp,\$npc
+ 928:	70 89       	stc \$0,\$dbg
+ 92a:	70 8b       	ldc \$0,\$dbg
+ 92c:	7f 89       	stc \$sp,\$dbg
+ 92e:	7f 8b       	ldc \$sp,\$dbg
+ 930:	70 99       	stc \$0,\$depc
+ 932:	70 9b       	ldc \$0,\$depc
+ 934:	7f 99       	stc \$sp,\$depc
+ 936:	7f 9b       	ldc \$sp,\$depc
+ 938:	70 a9       	stc \$0,\$opt
+ 93a:	70 ab       	ldc \$0,\$opt
+ 93c:	7f a9       	stc \$sp,\$opt
+ 93e:	7f ab       	ldc \$sp,\$opt
+ 940:	70 b9       	stc \$0,\$rcfg
+ 942:	70 bb       	ldc \$0,\$rcfg
+ 944:	7f b9       	stc \$sp,\$rcfg
+ 946:	7f bb       	ldc \$sp,\$rcfg
+ 948:	70 c9       	stc \$0,\$ccfg
+ 94a:	70 cb       	ldc \$0,\$ccfg
+ 94c:	7f c9       	stc \$sp,\$ccfg
+ 94e:	7f cb       	ldc \$sp,\$ccfg
+ 950:	70 00       	di
+ 952:	70 10       	ei
+ 954:	70 12       	reti
+ 956:	70 22       	halt
+ 958:	70 32       	break
+ 95a:	70 11       	syncm
+ 95c:	70 06       	swi 0x0
+ 95e:	70 36       	swi 0x3
+ 960:	f0 04 00 00 	stcb \$0,0x0
+ 964:	f0 14 00 00 	ldcb \$0,0x0
+ 968:	ff 04 00 00 	stcb \$sp,0x0
+ 96c:	ff 14 00 00 	ldcb \$sp,0x0
+ 970:	f0 04 ff ff 	stcb \$0,0xffff
+ 974:	f0 14 ff ff 	ldcb \$0,0xffff
+ 978:	ff 04 ff ff 	stcb \$sp,0xffff
+ 97c:	ff 14 ff ff 	ldcb \$sp,0xffff
+ 980:	f0 04 00 00 	stcb \$0,0x0
+			982: R_MEP_16	symbol
+ 984:	f0 14 00 00 	ldcb \$0,0x0
+			986: R_MEP_16	symbol
+ 988:	ff 04 00 00 	stcb \$sp,0x0
+			98a: R_MEP_16	symbol
+ 98c:	ff 14 00 00 	ldcb \$sp,0x0
+			98e: R_MEP_16	symbol
+ 990:	20 00       	bsetm \(\$0\),0x0
+ 992:	20 01       	bclrm \(\$0\),0x0
+ 994:	20 02       	bnotm \(\$0\),0x0
+ 996:	20 f0       	bsetm \(\$sp\),0x0
+ 998:	20 f1       	bclrm \(\$sp\),0x0
+ 99a:	20 f2       	bnotm \(\$sp\),0x0
+ 99c:	27 00       	bsetm \(\$0\),0x7
+ 99e:	27 01       	bclrm \(\$0\),0x7
+ 9a0:	27 02       	bnotm \(\$0\),0x7
+ 9a2:	27 f0       	bsetm \(\$sp\),0x7
+ 9a4:	27 f1       	bclrm \(\$sp\),0x7
+ 9a6:	27 f2       	bnotm \(\$sp\),0x7
+ 9a8:	20 03       	btstm \$0,\(\$0\),0x0
+ 9aa:	20 f3       	btstm \$0,\(\$sp\),0x0
+ 9ac:	27 03       	btstm \$0,\(\$0\),0x7
+ 9ae:	27 f3       	btstm \$0,\(\$sp\),0x7
+ 9b0:	20 04       	tas \$0,\(\$0\)
+ 9b2:	2f 04       	tas \$sp,\(\$0\)
+ 9b4:	20 f4       	tas \$0,\(\$sp\)
+ 9b6:	2f f4       	tas \$sp,\(\$sp\)
+ 9b8:	70 04       	cache 0x0,\(\$0\)
+ 9ba:	73 04       	cache 0x3,\(\$0\)
+ 9bc:	70 f4       	cache 0x0,\(\$sp\)
+ 9be:	73 f4       	cache 0x3,\(\$sp\)
+ 9c0:	10 04       	mul \$0,\$0
+ 9c2:	f0 01 30 04 	madd \$0,\$0
+ 9c6:	10 06       	mulr \$0,\$0
+ 9c8:	f0 01 30 06 	maddr \$0,\$0
+ 9cc:	10 05       	mulu \$0,\$0
+ 9ce:	f0 01 30 05 	maddu \$0,\$0
+ 9d2:	10 07       	mulru \$0,\$0
+ 9d4:	f0 01 30 07 	maddru \$0,\$0
+ 9d8:	1f 04       	mul \$sp,\$0
+ 9da:	ff 01 30 04 	madd \$sp,\$0
+ 9de:	1f 06       	mulr \$sp,\$0
+ 9e0:	ff 01 30 06 	maddr \$sp,\$0
+ 9e4:	1f 05       	mulu \$sp,\$0
+ 9e6:	ff 01 30 05 	maddu \$sp,\$0
+ 9ea:	1f 07       	mulru \$sp,\$0
+ 9ec:	ff 01 30 07 	maddru \$sp,\$0
+ 9f0:	10 f4       	mul \$0,\$sp
+ 9f2:	f0 f1 30 04 	madd \$0,\$sp
+ 9f6:	10 f6       	mulr \$0,\$sp
+ 9f8:	f0 f1 30 06 	maddr \$0,\$sp
+ 9fc:	10 f5       	mulu \$0,\$sp
+ 9fe:	f0 f1 30 05 	maddu \$0,\$sp
+ a02:	10 f7       	mulru \$0,\$sp
+ a04:	f0 f1 30 07 	maddru \$0,\$sp
+ a08:	1f f4       	mul \$sp,\$sp
+ a0a:	ff f1 30 04 	madd \$sp,\$sp
+ a0e:	1f f6       	mulr \$sp,\$sp
+ a10:	ff f1 30 06 	maddr \$sp,\$sp
+ a14:	1f f5       	mulu \$sp,\$sp
+ a16:	ff f1 30 05 	maddu \$sp,\$sp
+ a1a:	1f f7       	mulru \$sp,\$sp
+ a1c:	ff f1 30 07 	maddru \$sp,\$sp
+ a20:	10 08       	div \$0,\$0
+ a22:	10 09       	divu \$0,\$0
+ a24:	1f 08       	div \$sp,\$0
+ a26:	1f 09       	divu \$sp,\$0
+ a28:	10 f8       	div \$0,\$sp
+ a2a:	10 f9       	divu \$0,\$sp
+ a2c:	1f f8       	div \$sp,\$sp
+ a2e:	1f f9       	divu \$sp,\$sp
+ a30:	70 13       	dret
+ a32:	70 33       	dbreak
+ a34:	f0 01 00 00 	ldz \$0,\$0
+ a38:	f0 01 00 03 	abs \$0,\$0
+ a3c:	f0 01 00 02 	ave \$0,\$0
+ a40:	ff 01 00 00 	ldz \$sp,\$0
+ a44:	ff 01 00 03 	abs \$sp,\$0
+ a48:	ff 01 00 02 	ave \$sp,\$0
+ a4c:	f0 f1 00 00 	ldz \$0,\$sp
+ a50:	f0 f1 00 03 	abs \$0,\$sp
+ a54:	f0 f1 00 02 	ave \$0,\$sp
+ a58:	ff f1 00 00 	ldz \$sp,\$sp
+ a5c:	ff f1 00 03 	abs \$sp,\$sp
+ a60:	ff f1 00 02 	ave \$sp,\$sp
+ a64:	f0 01 00 04 	min \$0,\$0
+ a68:	f0 01 00 05 	max \$0,\$0
+ a6c:	f0 01 00 06 	minu \$0,\$0
+ a70:	f0 01 00 07 	maxu \$0,\$0
+ a74:	ff 01 00 04 	min \$sp,\$0
+ a78:	ff 01 00 05 	max \$sp,\$0
+ a7c:	ff 01 00 06 	minu \$sp,\$0
+ a80:	ff 01 00 07 	maxu \$sp,\$0
+ a84:	f0 f1 00 04 	min \$0,\$sp
+ a88:	f0 f1 00 05 	max \$0,\$sp
+ a8c:	f0 f1 00 06 	minu \$0,\$sp
+ a90:	f0 f1 00 07 	maxu \$0,\$sp
+ a94:	ff f1 00 04 	min \$sp,\$sp
+ a98:	ff f1 00 05 	max \$sp,\$sp
+ a9c:	ff f1 00 06 	minu \$sp,\$sp
+ aa0:	ff f1 00 07 	maxu \$sp,\$sp
+ aa4:	f0 01 10 00 	clip \$0,0x0
+ aa8:	f0 01 10 01 	clipu \$0,0x0
+ aac:	ff 01 10 00 	clip \$sp,0x0
+ ab0:	ff 01 10 01 	clipu \$sp,0x0
+ ab4:	f0 01 10 f8 	clip \$0,0x1f
+ ab8:	f0 01 10 f9 	clipu \$0,0x1f
+ abc:	ff 01 10 f8 	clip \$sp,0x1f
+ ac0:	ff 01 10 f9 	clipu \$sp,0x1f
+ ac4:	f0 01 00 08 	sadd \$0,\$0
+ ac8:	f0 01 00 0a 	ssub \$0,\$0
+ acc:	f0 01 00 09 	saddu \$0,\$0
+ ad0:	f0 01 00 0b 	ssubu \$0,\$0
+ ad4:	ff 01 00 08 	sadd \$sp,\$0
+ ad8:	ff 01 00 0a 	ssub \$sp,\$0
+ adc:	ff 01 00 09 	saddu \$sp,\$0
+ ae0:	ff 01 00 0b 	ssubu \$sp,\$0
+ ae4:	f0 f1 00 08 	sadd \$0,\$sp
+ ae8:	f0 f1 00 0a 	ssub \$0,\$sp
+ aec:	f0 f1 00 09 	saddu \$0,\$sp
+ af0:	f0 f1 00 0b 	ssubu \$0,\$sp
+ af4:	ff f1 00 08 	sadd \$sp,\$sp
+ af8:	ff f1 00 0a 	ssub \$sp,\$sp
+ afc:	ff f1 00 09 	saddu \$sp,\$sp
+ b00:	ff f1 00 0b 	ssubu \$sp,\$sp
+ b04:	30 08       	swcp \$c0,\(\$0\)
+ b06:	30 09       	lwcp \$c0,\(\$0\)
+ b08:	30 0a       	smcp \$c0,\(\$0\)
+ b0a:	30 0b       	lmcp \$c0,\(\$0\)
+ b0c:	3f 08       	swcp \$c15,\(\$0\)
+ b0e:	3f 09       	lwcp \$c15,\(\$0\)
+ b10:	3f 0a       	smcp \$c15,\(\$0\)
+ b12:	3f 0b       	lmcp \$c15,\(\$0\)
+ b14:	30 f8       	swcp \$c0,\(\$sp\)
+ b16:	30 f9       	lwcp \$c0,\(\$sp\)
+ b18:	30 fa       	smcp \$c0,\(\$sp\)
+ b1a:	30 fb       	lmcp \$c0,\(\$sp\)
+ b1c:	3f f8       	swcp \$c15,\(\$sp\)
+ b1e:	3f f9       	lwcp \$c15,\(\$sp\)
+ b20:	3f fa       	smcp \$c15,\(\$sp\)
+ b22:	3f fb       	lmcp \$c15,\(\$sp\)
+ b24:	30 00       	swcpi \$c0,\(\$0\+\)
+ b26:	30 01       	lwcpi \$c0,\(\$0\+\)
+ b28:	30 02       	smcpi \$c0,\(\$0\+\)
+ b2a:	30 03       	lmcpi \$c0,\(\$0\+\)
+ b2c:	3f 00       	swcpi \$c15,\(\$0\+\)
+ b2e:	3f 01       	lwcpi \$c15,\(\$0\+\)
+ b30:	3f 02       	smcpi \$c15,\(\$0\+\)
+ b32:	3f 03       	lmcpi \$c15,\(\$0\+\)
+ b34:	30 f0       	swcpi \$c0,\(\$sp\+\)
+ b36:	30 f1       	lwcpi \$c0,\(\$sp\+\)
+ b38:	30 f2       	smcpi \$c0,\(\$sp\+\)
+ b3a:	30 f3       	lmcpi \$c0,\(\$sp\+\)
+ b3c:	3f f0       	swcpi \$c15,\(\$sp\+\)
+ b3e:	3f f1       	lwcpi \$c15,\(\$sp\+\)
+ b40:	3f f2       	smcpi \$c15,\(\$sp\+\)
+ b42:	3f f3       	lmcpi \$c15,\(\$sp\+\)
+ b44:	f0 05 00 80 	sbcpa \$c0,\(\$0\+\),-128
+ b48:	f0 05 40 80 	lbcpa \$c0,\(\$0\+\),-128
+ b4c:	f0 05 08 80 	sbcpm0 \$c0,\(\$0\+\),-128
+ b50:	f0 05 48 80 	lbcpm0 \$c0,\(\$0\+\),-128
+ b54:	f0 05 0c 80 	sbcpm1 \$c0,\(\$0\+\),-128
+ b58:	f0 05 4c 80 	lbcpm1 \$c0,\(\$0\+\),-128
+ b5c:	ff 05 00 80 	sbcpa \$c15,\(\$0\+\),-128
+ b60:	ff 05 40 80 	lbcpa \$c15,\(\$0\+\),-128
+ b64:	ff 05 08 80 	sbcpm0 \$c15,\(\$0\+\),-128
+ b68:	ff 05 48 80 	lbcpm0 \$c15,\(\$0\+\),-128
+ b6c:	ff 05 0c 80 	sbcpm1 \$c15,\(\$0\+\),-128
+ b70:	ff 05 4c 80 	lbcpm1 \$c15,\(\$0\+\),-128
+ b74:	f0 f5 00 80 	sbcpa \$c0,\(\$sp\+\),-128
+ b78:	f0 f5 40 80 	lbcpa \$c0,\(\$sp\+\),-128
+ b7c:	f0 f5 08 80 	sbcpm0 \$c0,\(\$sp\+\),-128
+ b80:	f0 f5 48 80 	lbcpm0 \$c0,\(\$sp\+\),-128
+ b84:	f0 f5 0c 80 	sbcpm1 \$c0,\(\$sp\+\),-128
+ b88:	f0 f5 4c 80 	lbcpm1 \$c0,\(\$sp\+\),-128
+ b8c:	ff f5 00 80 	sbcpa \$c15,\(\$sp\+\),-128
+ b90:	ff f5 40 80 	lbcpa \$c15,\(\$sp\+\),-128
+ b94:	ff f5 08 80 	sbcpm0 \$c15,\(\$sp\+\),-128
+ b98:	ff f5 48 80 	lbcpm0 \$c15,\(\$sp\+\),-128
+ b9c:	ff f5 0c 80 	sbcpm1 \$c15,\(\$sp\+\),-128
+ ba0:	ff f5 4c 80 	lbcpm1 \$c15,\(\$sp\+\),-128
+ ba4:	f0 05 00 7f 	sbcpa \$c0,\(\$0\+\),127
+ ba8:	f0 05 40 7f 	lbcpa \$c0,\(\$0\+\),127
+ bac:	f0 05 08 7f 	sbcpm0 \$c0,\(\$0\+\),127
+ bb0:	f0 05 48 7f 	lbcpm0 \$c0,\(\$0\+\),127
+ bb4:	f0 05 0c 7f 	sbcpm1 \$c0,\(\$0\+\),127
+ bb8:	f0 05 4c 7f 	lbcpm1 \$c0,\(\$0\+\),127
+ bbc:	ff 05 00 7f 	sbcpa \$c15,\(\$0\+\),127
+ bc0:	ff 05 40 7f 	lbcpa \$c15,\(\$0\+\),127
+ bc4:	ff 05 08 7f 	sbcpm0 \$c15,\(\$0\+\),127
+ bc8:	ff 05 48 7f 	lbcpm0 \$c15,\(\$0\+\),127
+ bcc:	ff 05 0c 7f 	sbcpm1 \$c15,\(\$0\+\),127
+ bd0:	ff 05 4c 7f 	lbcpm1 \$c15,\(\$0\+\),127
+ bd4:	f0 f5 00 7f 	sbcpa \$c0,\(\$sp\+\),127
+ bd8:	f0 f5 40 7f 	lbcpa \$c0,\(\$sp\+\),127
+ bdc:	f0 f5 08 7f 	sbcpm0 \$c0,\(\$sp\+\),127
+ be0:	f0 f5 48 7f 	lbcpm0 \$c0,\(\$sp\+\),127
+ be4:	f0 f5 0c 7f 	sbcpm1 \$c0,\(\$sp\+\),127
+ be8:	f0 f5 4c 7f 	lbcpm1 \$c0,\(\$sp\+\),127
+ bec:	ff f5 00 7f 	sbcpa \$c15,\(\$sp\+\),127
+ bf0:	ff f5 40 7f 	lbcpa \$c15,\(\$sp\+\),127
+ bf4:	ff f5 08 7f 	sbcpm0 \$c15,\(\$sp\+\),127
+ bf8:	ff f5 48 7f 	lbcpm0 \$c15,\(\$sp\+\),127
+ bfc:	ff f5 0c 7f 	sbcpm1 \$c15,\(\$sp\+\),127
+ c00:	ff f5 4c 7f 	lbcpm1 \$c15,\(\$sp\+\),127
+ c04:	f0 05 10 80 	shcpa \$c0,\(\$0\+\),-128
+ c08:	f0 05 50 80 	lhcpa \$c0,\(\$0\+\),-128
+ c0c:	f0 05 18 80 	shcpm0 \$c0,\(\$0\+\),-128
+ c10:	f0 05 58 80 	lhcpm0 \$c0,\(\$0\+\),-128
+ c14:	f0 05 1c 80 	shcpm1 \$c0,\(\$0\+\),-128
+ c18:	f0 05 5c 80 	lhcpm1 \$c0,\(\$0\+\),-128
+ c1c:	ff 05 10 80 	shcpa \$c15,\(\$0\+\),-128
+ c20:	ff 05 50 80 	lhcpa \$c15,\(\$0\+\),-128
+ c24:	ff 05 18 80 	shcpm0 \$c15,\(\$0\+\),-128
+ c28:	ff 05 58 80 	lhcpm0 \$c15,\(\$0\+\),-128
+ c2c:	ff 05 1c 80 	shcpm1 \$c15,\(\$0\+\),-128
+ c30:	ff 05 5c 80 	lhcpm1 \$c15,\(\$0\+\),-128
+ c34:	f0 f5 10 80 	shcpa \$c0,\(\$sp\+\),-128
+ c38:	f0 f5 50 80 	lhcpa \$c0,\(\$sp\+\),-128
+ c3c:	f0 f5 18 80 	shcpm0 \$c0,\(\$sp\+\),-128
+ c40:	f0 f5 58 80 	lhcpm0 \$c0,\(\$sp\+\),-128
+ c44:	f0 f5 1c 80 	shcpm1 \$c0,\(\$sp\+\),-128
+ c48:	f0 f5 5c 80 	lhcpm1 \$c0,\(\$sp\+\),-128
+ c4c:	ff f5 10 80 	shcpa \$c15,\(\$sp\+\),-128
+ c50:	ff f5 50 80 	lhcpa \$c15,\(\$sp\+\),-128
+ c54:	ff f5 18 80 	shcpm0 \$c15,\(\$sp\+\),-128
+ c58:	ff f5 58 80 	lhcpm0 \$c15,\(\$sp\+\),-128
+ c5c:	ff f5 1c 80 	shcpm1 \$c15,\(\$sp\+\),-128
+ c60:	ff f5 5c 80 	lhcpm1 \$c15,\(\$sp\+\),-128
+ c64:	f0 05 10 7e 	shcpa \$c0,\(\$0\+\),126
+ c68:	f0 05 50 7e 	lhcpa \$c0,\(\$0\+\),126
+ c6c:	f0 05 18 7e 	shcpm0 \$c0,\(\$0\+\),126
+ c70:	f0 05 58 7e 	lhcpm0 \$c0,\(\$0\+\),126
+ c74:	f0 05 1c 7e 	shcpm1 \$c0,\(\$0\+\),126
+ c78:	f0 05 5c 7e 	lhcpm1 \$c0,\(\$0\+\),126
+ c7c:	ff 05 10 7e 	shcpa \$c15,\(\$0\+\),126
+ c80:	ff 05 50 7e 	lhcpa \$c15,\(\$0\+\),126
+ c84:	ff 05 18 7e 	shcpm0 \$c15,\(\$0\+\),126
+ c88:	ff 05 58 7e 	lhcpm0 \$c15,\(\$0\+\),126
+ c8c:	ff 05 1c 7e 	shcpm1 \$c15,\(\$0\+\),126
+ c90:	ff 05 5c 7e 	lhcpm1 \$c15,\(\$0\+\),126
+ c94:	f0 f5 10 7e 	shcpa \$c0,\(\$sp\+\),126
+ c98:	f0 f5 50 7e 	lhcpa \$c0,\(\$sp\+\),126
+ c9c:	f0 f5 18 7e 	shcpm0 \$c0,\(\$sp\+\),126
+ ca0:	f0 f5 58 7e 	lhcpm0 \$c0,\(\$sp\+\),126
+ ca4:	f0 f5 1c 7e 	shcpm1 \$c0,\(\$sp\+\),126
+ ca8:	f0 f5 5c 7e 	lhcpm1 \$c0,\(\$sp\+\),126
+ cac:	ff f5 10 7e 	shcpa \$c15,\(\$sp\+\),126
+ cb0:	ff f5 50 7e 	lhcpa \$c15,\(\$sp\+\),126
+ cb4:	ff f5 18 7e 	shcpm0 \$c15,\(\$sp\+\),126
+ cb8:	ff f5 58 7e 	lhcpm0 \$c15,\(\$sp\+\),126
+ cbc:	ff f5 1c 7e 	shcpm1 \$c15,\(\$sp\+\),126
+ cc0:	ff f5 5c 7e 	lhcpm1 \$c15,\(\$sp\+\),126
+ cc4:	f0 05 20 80 	swcpa \$c0,\(\$0\+\),-128
+ cc8:	f0 05 60 80 	lwcpa \$c0,\(\$0\+\),-128
+ ccc:	f0 05 28 80 	swcpm0 \$c0,\(\$0\+\),-128
+ cd0:	f0 05 68 80 	lwcpm0 \$c0,\(\$0\+\),-128
+ cd4:	f0 05 2c 80 	swcpm1 \$c0,\(\$0\+\),-128
+ cd8:	f0 05 6c 80 	lwcpm1 \$c0,\(\$0\+\),-128
+ cdc:	ff 05 20 80 	swcpa \$c15,\(\$0\+\),-128
+ ce0:	ff 05 60 80 	lwcpa \$c15,\(\$0\+\),-128
+ ce4:	ff 05 28 80 	swcpm0 \$c15,\(\$0\+\),-128
+ ce8:	ff 05 68 80 	lwcpm0 \$c15,\(\$0\+\),-128
+ cec:	ff 05 2c 80 	swcpm1 \$c15,\(\$0\+\),-128
+ cf0:	ff 05 6c 80 	lwcpm1 \$c15,\(\$0\+\),-128
+ cf4:	f0 f5 20 80 	swcpa \$c0,\(\$sp\+\),-128
+ cf8:	f0 f5 60 80 	lwcpa \$c0,\(\$sp\+\),-128
+ cfc:	f0 f5 28 80 	swcpm0 \$c0,\(\$sp\+\),-128
+ d00:	f0 f5 68 80 	lwcpm0 \$c0,\(\$sp\+\),-128
+ d04:	f0 f5 2c 80 	swcpm1 \$c0,\(\$sp\+\),-128
+ d08:	f0 f5 6c 80 	lwcpm1 \$c0,\(\$sp\+\),-128
+ d0c:	ff f5 20 80 	swcpa \$c15,\(\$sp\+\),-128
+ d10:	ff f5 60 80 	lwcpa \$c15,\(\$sp\+\),-128
+ d14:	ff f5 28 80 	swcpm0 \$c15,\(\$sp\+\),-128
+ d18:	ff f5 68 80 	lwcpm0 \$c15,\(\$sp\+\),-128
+ d1c:	ff f5 2c 80 	swcpm1 \$c15,\(\$sp\+\),-128
+ d20:	ff f5 6c 80 	lwcpm1 \$c15,\(\$sp\+\),-128
+ d24:	f0 05 20 7c 	swcpa \$c0,\(\$0\+\),124
+ d28:	f0 05 60 7c 	lwcpa \$c0,\(\$0\+\),124
+ d2c:	f0 05 28 7c 	swcpm0 \$c0,\(\$0\+\),124
+ d30:	f0 05 68 7c 	lwcpm0 \$c0,\(\$0\+\),124
+ d34:	f0 05 2c 7c 	swcpm1 \$c0,\(\$0\+\),124
+ d38:	f0 05 6c 7c 	lwcpm1 \$c0,\(\$0\+\),124
+ d3c:	ff 05 20 7c 	swcpa \$c15,\(\$0\+\),124
+ d40:	ff 05 60 7c 	lwcpa \$c15,\(\$0\+\),124
+ d44:	ff 05 28 7c 	swcpm0 \$c15,\(\$0\+\),124
+ d48:	ff 05 68 7c 	lwcpm0 \$c15,\(\$0\+\),124
+ d4c:	ff 05 2c 7c 	swcpm1 \$c15,\(\$0\+\),124
+ d50:	ff 05 6c 7c 	lwcpm1 \$c15,\(\$0\+\),124
+ d54:	f0 f5 20 7c 	swcpa \$c0,\(\$sp\+\),124
+ d58:	f0 f5 60 7c 	lwcpa \$c0,\(\$sp\+\),124
+ d5c:	f0 f5 28 7c 	swcpm0 \$c0,\(\$sp\+\),124
+ d60:	f0 f5 68 7c 	lwcpm0 \$c0,\(\$sp\+\),124
+ d64:	f0 f5 2c 7c 	swcpm1 \$c0,\(\$sp\+\),124
+ d68:	f0 f5 6c 7c 	lwcpm1 \$c0,\(\$sp\+\),124
+ d6c:	ff f5 20 7c 	swcpa \$c15,\(\$sp\+\),124
+ d70:	ff f5 60 7c 	lwcpa \$c15,\(\$sp\+\),124
+ d74:	ff f5 28 7c 	swcpm0 \$c15,\(\$sp\+\),124
+ d78:	ff f5 68 7c 	lwcpm0 \$c15,\(\$sp\+\),124
+ d7c:	ff f5 2c 7c 	swcpm1 \$c15,\(\$sp\+\),124
+ d80:	ff f5 6c 7c 	lwcpm1 \$c15,\(\$sp\+\),124
+ d84:	f0 05 30 80 	smcpa \$c0,\(\$0\+\),-128
+ d88:	f0 05 70 80 	lmcpa \$c0,\(\$0\+\),-128
+ d8c:	f0 05 38 80 	smcpm0 \$c0,\(\$0\+\),-128
+ d90:	f0 05 78 80 	lmcpm0 \$c0,\(\$0\+\),-128
+ d94:	f0 05 3c 80 	smcpm1 \$c0,\(\$0\+\),-128
+ d98:	f0 05 7c 80 	lmcpm1 \$c0,\(\$0\+\),-128
+ d9c:	ff 05 30 80 	smcpa \$c15,\(\$0\+\),-128
+ da0:	ff 05 70 80 	lmcpa \$c15,\(\$0\+\),-128
+ da4:	ff 05 38 80 	smcpm0 \$c15,\(\$0\+\),-128
+ da8:	ff 05 78 80 	lmcpm0 \$c15,\(\$0\+\),-128
+ dac:	ff 05 3c 80 	smcpm1 \$c15,\(\$0\+\),-128
+ db0:	ff 05 7c 80 	lmcpm1 \$c15,\(\$0\+\),-128
+ db4:	f0 f5 30 80 	smcpa \$c0,\(\$sp\+\),-128
+ db8:	f0 f5 70 80 	lmcpa \$c0,\(\$sp\+\),-128
+ dbc:	f0 f5 38 80 	smcpm0 \$c0,\(\$sp\+\),-128
+ dc0:	f0 f5 78 80 	lmcpm0 \$c0,\(\$sp\+\),-128
+ dc4:	f0 f5 3c 80 	smcpm1 \$c0,\(\$sp\+\),-128
+ dc8:	f0 f5 7c 80 	lmcpm1 \$c0,\(\$sp\+\),-128
+ dcc:	ff f5 30 80 	smcpa \$c15,\(\$sp\+\),-128
+ dd0:	ff f5 70 80 	lmcpa \$c15,\(\$sp\+\),-128
+ dd4:	ff f5 38 80 	smcpm0 \$c15,\(\$sp\+\),-128
+ dd8:	ff f5 78 80 	lmcpm0 \$c15,\(\$sp\+\),-128
+ ddc:	ff f5 3c 80 	smcpm1 \$c15,\(\$sp\+\),-128
+ de0:	ff f5 7c 80 	lmcpm1 \$c15,\(\$sp\+\),-128
+ de4:	f0 05 30 78 	smcpa \$c0,\(\$0\+\),120
+ de8:	f0 05 70 78 	lmcpa \$c0,\(\$0\+\),120
+ dec:	f0 05 38 78 	smcpm0 \$c0,\(\$0\+\),120
+ df0:	f0 05 78 78 	lmcpm0 \$c0,\(\$0\+\),120
+ df4:	f0 05 3c 78 	smcpm1 \$c0,\(\$0\+\),120
+ df8:	f0 05 7c 78 	lmcpm1 \$c0,\(\$0\+\),120
+ dfc:	ff 05 30 78 	smcpa \$c15,\(\$0\+\),120
+ e00:	ff 05 70 78 	lmcpa \$c15,\(\$0\+\),120
+ e04:	ff 05 38 78 	smcpm0 \$c15,\(\$0\+\),120
+ e08:	ff 05 78 78 	lmcpm0 \$c15,\(\$0\+\),120
+ e0c:	ff 05 3c 78 	smcpm1 \$c15,\(\$0\+\),120
+ e10:	ff 05 7c 78 	lmcpm1 \$c15,\(\$0\+\),120
+ e14:	f0 f5 30 78 	smcpa \$c0,\(\$sp\+\),120
+ e18:	f0 f5 70 78 	lmcpa \$c0,\(\$sp\+\),120
+ e1c:	f0 f5 38 78 	smcpm0 \$c0,\(\$sp\+\),120
+ e20:	f0 f5 78 78 	lmcpm0 \$c0,\(\$sp\+\),120
+ e24:	f0 f5 3c 78 	smcpm1 \$c0,\(\$sp\+\),120
+ e28:	f0 f5 7c 78 	lmcpm1 \$c0,\(\$sp\+\),120
+ e2c:	ff f5 30 78 	smcpa \$c15,\(\$sp\+\),120
+ e30:	ff f5 70 78 	lmcpa \$c15,\(\$sp\+\),120
+ e34:	ff f5 38 78 	smcpm0 \$c15,\(\$sp\+\),120
+ e38:	ff f5 78 78 	lmcpm0 \$c15,\(\$sp\+\),120
+ e3c:	ff f5 3c 78 	smcpm1 \$c15,\(\$sp\+\),120
+ e40:	ff f5 7c 78 	lmcpm1 \$c15,\(\$sp\+\),120
+ e44:	d8 04 80 02 	bcpeq 0x0,0xffff0e48
+ e48:	d8 05 80 02 	bcpne 0x0,0xffff0e4c
+ e4c:	d8 06 80 02 	bcpat 0x0,0xffff0e50
+ e50:	d8 07 80 02 	bcpaf 0x0,0xffff0e54
+ e54:	d8 f4 80 02 	bcpeq 0xf,0xffff0e58
+ e58:	d8 f5 80 02 	bcpne 0xf,0xffff0e5c
+ e5c:	d8 f6 80 02 	bcpat 0xf,0xffff0e60
+ e60:	d8 f7 80 02 	bcpaf 0xf,0xffff0e64
+ e64:	d8 04 3f ff 	bcpeq 0x0,0x8e62
+ e68:	d8 05 3f ff 	bcpne 0x0,0x8e66
+ e6c:	d8 06 3f ff 	bcpat 0x0,0x8e6a
+ e70:	d8 07 3f ff 	bcpaf 0x0,0x8e6e
+ e74:	d8 f4 3f ff 	bcpeq 0xf,0x8e72
+ e78:	d8 f5 3f ff 	bcpne 0xf,0x8e76
+ e7c:	d8 f6 3f ff 	bcpat 0xf,0x8e7a
+ e80:	d8 f7 3f ff 	bcpaf 0xf,0x8e7e
+ e84:	d8 04 00 00 	bcpeq 0x0,0xe84
+			e84: R_MEP_PCREL17A2	symbol
+ e88:	d8 05 00 00 	bcpne 0x0,0xe88
+			e88: R_MEP_PCREL17A2	symbol
+ e8c:	d8 06 00 00 	bcpat 0x0,0xe8c
+			e8c: R_MEP_PCREL17A2	symbol
+ e90:	d8 07 00 00 	bcpaf 0x0,0xe90
+			e90: R_MEP_PCREL17A2	symbol
+ e94:	d8 f4 00 00 	bcpeq 0xf,0xe94
+			e94: R_MEP_PCREL17A2	symbol
+ e98:	d8 f5 00 00 	bcpne 0xf,0xe98
+			e98: R_MEP_PCREL17A2	symbol
+ e9c:	d8 f6 00 00 	bcpat 0xf,0xe9c
+			e9c: R_MEP_PCREL17A2	symbol
+ ea0:	d8 f7 00 00 	bcpaf 0xf,0xea0
+			ea0: R_MEP_PCREL17A2	symbol
+ ea4:	70 21       	synccp
+ ea6:	18 0f       	jsrv \$0
+ ea8:	18 ff       	jsrv \$sp
+ eaa:	d8 2b 80 00 	bsrv 0xff800eae
+ eae:	df fb 7f ff 	bsrv 0x800eac
+ eb2:	d8 0b 00 00 	bsrv 0xeb2
+			eb2: R_MEP_PCREL24A2	symbol
+ eb6:	00 00       	nop
+			eb6: R_MEP_8	symbol
+			eb7: R_MEP_16	symbol
+ eb8:	00 00       	nop
+			eb9: R_MEP_32	symbol
+ eba:	00 00       	nop
+.*
+
diff --git a/gas/testsuite/gas/mep/dj1.le.d b/gas/testsuite/gas/mep/dj1.le.d
new file mode 100644
index 000000000000..c860c5be0fa0
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj1.le.d
@@ -0,0 +1,1393 @@
+#as: -EL
+#objdump: -dr
+#source: dj1.s
+#name: dj1.le
+
+dump.o:     file format elf32-mep-little
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 00       	nop
+   2:	00 01       	mov \$1,\$0
+   4:	00 02       	mov \$2,\$0
+   6:	00 03       	mov \$3,\$0
+   8:	00 04       	mov \$4,\$0
+   a:	00 05       	mov \$5,\$0
+   c:	00 06       	mov \$6,\$0
+   e:	00 07       	mov \$7,\$0
+  10:	00 08       	mov \$8,\$0
+  12:	00 09       	mov \$9,\$0
+  14:	00 0a       	mov \$10,\$0
+  16:	00 0b       	mov \$11,\$0
+  18:	00 0c       	mov \$12,\$0
+  1a:	00 0d       	mov \$tp,\$0
+  1c:	00 0e       	mov \$gp,\$0
+  1e:	00 0f       	mov \$sp,\$0
+  20:	00 08       	mov \$8,\$0
+  22:	00 0d       	mov \$tp,\$0
+  24:	00 0e       	mov \$gp,\$0
+  26:	00 0f       	mov \$sp,\$0
+  28:	08 00       	sb \$0,\(\$0\)
+  2a:	09 00       	sh \$0,\(\$0\)
+  2c:	0a 00       	sw \$0,\(\$0\)
+  2e:	0c 00       	lb \$0,\(\$0\)
+  30:	0d 00       	lh \$0,\(\$0\)
+  32:	0e 00       	lw \$0,\(\$0\)
+  34:	0b 00       	lbu \$0,\(\$0\)
+  36:	0f 00       	lhu \$0,\(\$0\)
+  38:	08 0f       	sb \$sp,\(\$0\)
+  3a:	09 0f       	sh \$sp,\(\$0\)
+  3c:	0a 0f       	sw \$sp,\(\$0\)
+  3e:	0c 0f       	lb \$sp,\(\$0\)
+  40:	0d 0f       	lh \$sp,\(\$0\)
+  42:	0e 0f       	lw \$sp,\(\$0\)
+  44:	0b 0f       	lbu \$sp,\(\$0\)
+  46:	0f 0f       	lhu \$sp,\(\$0\)
+  48:	f8 00       	sb \$0,\(\$sp\)
+  4a:	f9 00       	sh \$0,\(\$sp\)
+  4c:	fa 00       	sw \$0,\(\$sp\)
+  4e:	fc 00       	lb \$0,\(\$sp\)
+  50:	fd 00       	lh \$0,\(\$sp\)
+  52:	fe 00       	lw \$0,\(\$sp\)
+  54:	fb 00       	lbu \$0,\(\$sp\)
+  56:	ff 00       	lhu \$0,\(\$sp\)
+  58:	f8 0f       	sb \$sp,\(\$sp\)
+  5a:	f9 0f       	sh \$sp,\(\$sp\)
+  5c:	fa 0f       	sw \$sp,\(\$sp\)
+  5e:	fc 0f       	lb \$sp,\(\$sp\)
+  60:	fd 0f       	lh \$sp,\(\$sp\)
+  62:	fe 0f       	lw \$sp,\(\$sp\)
+  64:	fb 0f       	lbu \$sp,\(\$sp\)
+  66:	ff 0f       	lhu \$sp,\(\$sp\)
+  68:	fa 00       	sw \$0,\(\$sp\)
+  6a:	fe 00       	lw \$0,\(\$sp\)
+  6c:	fa 0f       	sw \$sp,\(\$sp\)
+  6e:	fe 0f       	lw \$sp,\(\$sp\)
+  70:	7e 40       	sw \$0,0x7c\(\$sp\)
+  72:	7f 40       	lw \$0,0x7c\(\$sp\)
+  74:	7e 4f       	sw \$sp,0x7c\(\$sp\)
+  76:	7f 4f       	lw \$sp,0x7c\(\$sp\)
+  78:	fa 00       	sw \$0,\(\$sp\)
+  7a:	fe 00       	lw \$0,\(\$sp\)
+  7c:	fa 0f       	sw \$sp,\(\$sp\)
+  7e:	fe 0f       	lw \$sp,\(\$sp\)
+  80:	7e 40       	sw \$0,0x7c\(\$sp\)
+  82:	7f 40       	lw \$0,0x7c\(\$sp\)
+  84:	7e 4f       	sw \$sp,0x7c\(\$sp\)
+  86:	7f 4f       	lw \$sp,0x7c\(\$sp\)
+  88:	d8 00       	sb \$0,\(\$tp\)
+  8a:	dc 00       	lb \$0,\(\$tp\)
+  8c:	db 00       	lbu \$0,\(\$tp\)
+  8e:	d8 07       	sb \$7,\(\$tp\)
+  90:	dc 07       	lb \$7,\(\$tp\)
+  92:	db 07       	lbu \$7,\(\$tp\)
+  94:	7f 80       	sb \$0,0x7f\(\$tp\)
+  96:	7f 88       	lb \$0,0x7f\(\$tp\)
+  98:	ff 48       	lbu \$0,0x7f\(\$tp\)
+  9a:	7f 87       	sb \$7,0x7f\(\$tp\)
+  9c:	7f 8f       	lb \$7,0x7f\(\$tp\)
+  9e:	ff 4f       	lbu \$7,0x7f\(\$tp\)
+  a0:	00 80       	sb \$0,0x0\(\$tp\)
+			a0: R_MEP_TPREL7	symbol
+  a2:	00 88       	lb \$0,0x0\(\$tp\)
+			a2: R_MEP_TPREL7	symbol
+  a4:	80 48       	lbu \$0,0x0\(\$tp\)
+			a4: R_MEP_TPREL7	symbol
+  a6:	00 87       	sb \$7,0x0\(\$tp\)
+			a6: R_MEP_TPREL7	symbol
+  a8:	00 8f       	lb \$7,0x0\(\$tp\)
+			a8: R_MEP_TPREL7	symbol
+  aa:	80 4f       	lbu \$7,0x0\(\$tp\)
+			aa: R_MEP_TPREL7	symbol
+  ac:	d8 00       	sb \$0,\(\$tp\)
+  ae:	dc 00       	lb \$0,\(\$tp\)
+  b0:	db 00       	lbu \$0,\(\$tp\)
+  b2:	d8 07       	sb \$7,\(\$tp\)
+  b4:	dc 07       	lb \$7,\(\$tp\)
+  b6:	db 07       	lbu \$7,\(\$tp\)
+  b8:	7f 80       	sb \$0,0x7f\(\$tp\)
+  ba:	7f 88       	lb \$0,0x7f\(\$tp\)
+  bc:	ff 48       	lbu \$0,0x7f\(\$tp\)
+  be:	7f 87       	sb \$7,0x7f\(\$tp\)
+  c0:	7f 8f       	lb \$7,0x7f\(\$tp\)
+  c2:	ff 4f       	lbu \$7,0x7f\(\$tp\)
+  c4:	00 80       	sb \$0,0x0\(\$tp\)
+			c4: R_MEP_TPREL7	symbol
+  c6:	00 88       	lb \$0,0x0\(\$tp\)
+			c6: R_MEP_TPREL7	symbol
+  c8:	80 48       	lbu \$0,0x0\(\$tp\)
+			c8: R_MEP_TPREL7	symbol
+  ca:	00 87       	sb \$7,0x0\(\$tp\)
+			ca: R_MEP_TPREL7	symbol
+  cc:	00 8f       	lb \$7,0x0\(\$tp\)
+			cc: R_MEP_TPREL7	symbol
+  ce:	80 4f       	lbu \$7,0x0\(\$tp\)
+			ce: R_MEP_TPREL7	symbol
+  d0:	d9 00       	sh \$0,\(\$tp\)
+  d2:	dd 00       	lh \$0,\(\$tp\)
+  d4:	df 00       	lhu \$0,\(\$tp\)
+  d6:	d9 07       	sh \$7,\(\$tp\)
+  d8:	dd 07       	lh \$7,\(\$tp\)
+  da:	df 07       	lhu \$7,\(\$tp\)
+  dc:	fe 80       	sh \$0,0x7e\(\$tp\)
+  de:	fe 88       	lh \$0,0x7e\(\$tp\)
+  e0:	ff 88       	lhu \$0,0x7e\(\$tp\)
+  e2:	fe 87       	sh \$7,0x7e\(\$tp\)
+  e4:	fe 8f       	lh \$7,0x7e\(\$tp\)
+  e6:	ff 8f       	lhu \$7,0x7e\(\$tp\)
+  e8:	80 80       	sh \$0,0x0\(\$tp\)
+			e8: R_MEP_TPREL7A2	symbol
+  ea:	80 88       	lh \$0,0x0\(\$tp\)
+			ea: R_MEP_TPREL7A2	symbol
+  ec:	81 88       	lhu \$0,0x0\(\$tp\)
+			ec: R_MEP_TPREL7A2	symbol
+  ee:	80 87       	sh \$7,0x0\(\$tp\)
+			ee: R_MEP_TPREL7A2	symbol
+  f0:	80 8f       	lh \$7,0x0\(\$tp\)
+			f0: R_MEP_TPREL7A2	symbol
+  f2:	81 8f       	lhu \$7,0x0\(\$tp\)
+			f2: R_MEP_TPREL7A2	symbol
+  f4:	d9 00       	sh \$0,\(\$tp\)
+  f6:	dd 00       	lh \$0,\(\$tp\)
+  f8:	df 00       	lhu \$0,\(\$tp\)
+  fa:	d9 07       	sh \$7,\(\$tp\)
+  fc:	dd 07       	lh \$7,\(\$tp\)
+  fe:	df 07       	lhu \$7,\(\$tp\)
+ 100:	fe 80       	sh \$0,0x7e\(\$tp\)
+ 102:	fe 88       	lh \$0,0x7e\(\$tp\)
+ 104:	ff 88       	lhu \$0,0x7e\(\$tp\)
+ 106:	fe 87       	sh \$7,0x7e\(\$tp\)
+ 108:	fe 8f       	lh \$7,0x7e\(\$tp\)
+ 10a:	ff 8f       	lhu \$7,0x7e\(\$tp\)
+ 10c:	80 80       	sh \$0,0x0\(\$tp\)
+			10c: R_MEP_TPREL7A2	symbol
+ 10e:	80 88       	lh \$0,0x0\(\$tp\)
+			10e: R_MEP_TPREL7A2	symbol
+ 110:	81 88       	lhu \$0,0x0\(\$tp\)
+			110: R_MEP_TPREL7A2	symbol
+ 112:	80 87       	sh \$7,0x0\(\$tp\)
+			112: R_MEP_TPREL7A2	symbol
+ 114:	80 8f       	lh \$7,0x0\(\$tp\)
+			114: R_MEP_TPREL7A2	symbol
+ 116:	81 8f       	lhu \$7,0x0\(\$tp\)
+			116: R_MEP_TPREL7A2	symbol
+ 118:	da 00       	sw \$0,\(\$tp\)
+ 11a:	de 00       	lw \$0,\(\$tp\)
+ 11c:	da 07       	sw \$7,\(\$tp\)
+ 11e:	de 07       	lw \$7,\(\$tp\)
+ 120:	fe 40       	sw \$0,0x7c\(\$tp\)
+ 122:	ff 40       	lw \$0,0x7c\(\$tp\)
+ 124:	fe 47       	sw \$7,0x7c\(\$tp\)
+ 126:	ff 47       	lw \$7,0x7c\(\$tp\)
+ 128:	82 40       	sw \$0,0x0\(\$tp\)
+			128: R_MEP_TPREL7A4	symbol
+ 12a:	83 40       	lw \$0,0x0\(\$tp\)
+			12a: R_MEP_TPREL7A4	symbol
+ 12c:	82 47       	sw \$7,0x0\(\$tp\)
+			12c: R_MEP_TPREL7A4	symbol
+ 12e:	83 47       	lw \$7,0x0\(\$tp\)
+			12e: R_MEP_TPREL7A4	symbol
+ 130:	da 00       	sw \$0,\(\$tp\)
+ 132:	de 00       	lw \$0,\(\$tp\)
+ 134:	da 07       	sw \$7,\(\$tp\)
+ 136:	de 07       	lw \$7,\(\$tp\)
+ 138:	fe 40       	sw \$0,0x7c\(\$tp\)
+ 13a:	ff 40       	lw \$0,0x7c\(\$tp\)
+ 13c:	fe 47       	sw \$7,0x7c\(\$tp\)
+ 13e:	ff 47       	lw \$7,0x7c\(\$tp\)
+ 140:	82 40       	sw \$0,0x0\(\$tp\)
+			140: R_MEP_TPREL7A4	symbol
+ 142:	83 40       	lw \$0,0x0\(\$tp\)
+			142: R_MEP_TPREL7A4	symbol
+ 144:	82 47       	sw \$7,0x0\(\$tp\)
+			144: R_MEP_TPREL7A4	symbol
+ 146:	83 47       	lw \$7,0x0\(\$tp\)
+			146: R_MEP_TPREL7A4	symbol
+ 148:	08 c0 00 80 	sb \$0,-32768\(\$0\)
+ 14c:	09 c0 00 80 	sh \$0,-32768\(\$0\)
+ 150:	0a c0 00 80 	sw \$0,-32768\(\$0\)
+ 154:	0c c0 00 80 	lb \$0,-32768\(\$0\)
+ 158:	0d c0 00 80 	lh \$0,-32768\(\$0\)
+ 15c:	0e c0 00 80 	lw \$0,-32768\(\$0\)
+ 160:	0b c0 00 80 	lbu \$0,-32768\(\$0\)
+ 164:	0f c0 00 80 	lhu \$0,-32768\(\$0\)
+ 168:	08 cf 00 80 	sb \$sp,-32768\(\$0\)
+ 16c:	09 cf 00 80 	sh \$sp,-32768\(\$0\)
+ 170:	0a cf 00 80 	sw \$sp,-32768\(\$0\)
+ 174:	0c cf 00 80 	lb \$sp,-32768\(\$0\)
+ 178:	0d cf 00 80 	lh \$sp,-32768\(\$0\)
+ 17c:	0e cf 00 80 	lw \$sp,-32768\(\$0\)
+ 180:	0b cf 00 80 	lbu \$sp,-32768\(\$0\)
+ 184:	0f cf 00 80 	lhu \$sp,-32768\(\$0\)
+ 188:	08 c0 ff 7f 	sb \$0,32767\(\$0\)
+ 18c:	09 c0 ff 7f 	sh \$0,32767\(\$0\)
+ 190:	0a c0 ff 7f 	sw \$0,32767\(\$0\)
+ 194:	0c c0 ff 7f 	lb \$0,32767\(\$0\)
+ 198:	0d c0 ff 7f 	lh \$0,32767\(\$0\)
+ 19c:	0e c0 ff 7f 	lw \$0,32767\(\$0\)
+ 1a0:	0b c0 ff 7f 	lbu \$0,32767\(\$0\)
+ 1a4:	0f c0 ff 7f 	lhu \$0,32767\(\$0\)
+ 1a8:	08 cf ff 7f 	sb \$sp,32767\(\$0\)
+ 1ac:	09 cf ff 7f 	sh \$sp,32767\(\$0\)
+ 1b0:	0a cf ff 7f 	sw \$sp,32767\(\$0\)
+ 1b4:	0c cf ff 7f 	lb \$sp,32767\(\$0\)
+ 1b8:	0d cf ff 7f 	lh \$sp,32767\(\$0\)
+ 1bc:	0e cf ff 7f 	lw \$sp,32767\(\$0\)
+ 1c0:	0b cf ff 7f 	lbu \$sp,32767\(\$0\)
+ 1c4:	0f cf ff 7f 	lhu \$sp,32767\(\$0\)
+ 1c8:	08 c0 00 00 	sb \$0,0\(\$0\)
+			1c8: R_MEP_GPREL	symbol
+ 1cc:	09 c0 00 00 	sh \$0,0\(\$0\)
+			1cc: R_MEP_GPREL	symbol
+ 1d0:	0a c0 00 00 	sw \$0,0\(\$0\)
+			1d0: R_MEP_GPREL	symbol
+ 1d4:	0c c0 00 00 	lb \$0,0\(\$0\)
+			1d4: R_MEP_GPREL	symbol
+ 1d8:	0d c0 00 00 	lh \$0,0\(\$0\)
+			1d8: R_MEP_GPREL	symbol
+ 1dc:	0e c0 00 00 	lw \$0,0\(\$0\)
+			1dc: R_MEP_GPREL	symbol
+ 1e0:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			1e0: R_MEP_GPREL	symbol
+ 1e4:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			1e4: R_MEP_GPREL	symbol
+ 1e8:	08 cf 00 00 	sb \$sp,0\(\$0\)
+			1e8: R_MEP_GPREL	symbol
+ 1ec:	09 cf 00 00 	sh \$sp,0\(\$0\)
+			1ec: R_MEP_GPREL	symbol
+ 1f0:	0a cf 00 00 	sw \$sp,0\(\$0\)
+			1f0: R_MEP_GPREL	symbol
+ 1f4:	0c cf 00 00 	lb \$sp,0\(\$0\)
+			1f4: R_MEP_GPREL	symbol
+ 1f8:	0d cf 00 00 	lh \$sp,0\(\$0\)
+			1f8: R_MEP_GPREL	symbol
+ 1fc:	0e cf 00 00 	lw \$sp,0\(\$0\)
+			1fc: R_MEP_GPREL	symbol
+ 200:	0b cf 00 00 	lbu \$sp,0\(\$0\)
+			200: R_MEP_GPREL	symbol
+ 204:	0f cf 00 00 	lhu \$sp,0\(\$0\)
+			204: R_MEP_GPREL	symbol
+ 208:	08 c0 00 80 	sb \$0,-32768\(\$0\)
+ 20c:	09 c0 00 80 	sh \$0,-32768\(\$0\)
+ 210:	0a c0 00 80 	sw \$0,-32768\(\$0\)
+ 214:	0c c0 00 80 	lb \$0,-32768\(\$0\)
+ 218:	0d c0 00 80 	lh \$0,-32768\(\$0\)
+ 21c:	0e c0 00 80 	lw \$0,-32768\(\$0\)
+ 220:	0b c0 00 80 	lbu \$0,-32768\(\$0\)
+ 224:	0f c0 00 80 	lhu \$0,-32768\(\$0\)
+ 228:	08 cf 00 80 	sb \$sp,-32768\(\$0\)
+ 22c:	09 cf 00 80 	sh \$sp,-32768\(\$0\)
+ 230:	0a cf 00 80 	sw \$sp,-32768\(\$0\)
+ 234:	0c cf 00 80 	lb \$sp,-32768\(\$0\)
+ 238:	0d cf 00 80 	lh \$sp,-32768\(\$0\)
+ 23c:	0e cf 00 80 	lw \$sp,-32768\(\$0\)
+ 240:	0b cf 00 80 	lbu \$sp,-32768\(\$0\)
+ 244:	0f cf 00 80 	lhu \$sp,-32768\(\$0\)
+ 248:	08 c0 ff 7f 	sb \$0,32767\(\$0\)
+ 24c:	09 c0 ff 7f 	sh \$0,32767\(\$0\)
+ 250:	0a c0 ff 7f 	sw \$0,32767\(\$0\)
+ 254:	0c c0 ff 7f 	lb \$0,32767\(\$0\)
+ 258:	0d c0 ff 7f 	lh \$0,32767\(\$0\)
+ 25c:	0e c0 ff 7f 	lw \$0,32767\(\$0\)
+ 260:	0b c0 ff 7f 	lbu \$0,32767\(\$0\)
+ 264:	0f c0 ff 7f 	lhu \$0,32767\(\$0\)
+ 268:	08 cf ff 7f 	sb \$sp,32767\(\$0\)
+ 26c:	09 cf ff 7f 	sh \$sp,32767\(\$0\)
+ 270:	0a cf ff 7f 	sw \$sp,32767\(\$0\)
+ 274:	0c cf ff 7f 	lb \$sp,32767\(\$0\)
+ 278:	0d cf ff 7f 	lh \$sp,32767\(\$0\)
+ 27c:	0e cf ff 7f 	lw \$sp,32767\(\$0\)
+ 280:	0b cf ff 7f 	lbu \$sp,32767\(\$0\)
+ 284:	0f cf ff 7f 	lhu \$sp,32767\(\$0\)
+ 288:	08 c0 00 00 	sb \$0,0\(\$0\)
+			288: R_MEP_TPREL	symbol
+ 28c:	09 c0 00 00 	sh \$0,0\(\$0\)
+			28c: R_MEP_TPREL	symbol
+ 290:	0a c0 00 00 	sw \$0,0\(\$0\)
+			290: R_MEP_TPREL	symbol
+ 294:	0c c0 00 00 	lb \$0,0\(\$0\)
+			294: R_MEP_TPREL	symbol
+ 298:	0d c0 00 00 	lh \$0,0\(\$0\)
+			298: R_MEP_TPREL	symbol
+ 29c:	0e c0 00 00 	lw \$0,0\(\$0\)
+			29c: R_MEP_TPREL	symbol
+ 2a0:	0b c0 00 00 	lbu \$0,0\(\$0\)
+			2a0: R_MEP_TPREL	symbol
+ 2a4:	0f c0 00 00 	lhu \$0,0\(\$0\)
+			2a4: R_MEP_TPREL	symbol
+ 2a8:	08 cf 00 00 	sb \$sp,0\(\$0\)
+			2a8: R_MEP_TPREL	symbol
+ 2ac:	09 cf 00 00 	sh \$sp,0\(\$0\)
+			2ac: R_MEP_TPREL	symbol
+ 2b0:	0a cf 00 00 	sw \$sp,0\(\$0\)
+			2b0: R_MEP_TPREL	symbol
+ 2b4:	0c cf 00 00 	lb \$sp,0\(\$0\)
+			2b4: R_MEP_TPREL	symbol
+ 2b8:	0d cf 00 00 	lh \$sp,0\(\$0\)
+			2b8: R_MEP_TPREL	symbol
+ 2bc:	0e cf 00 00 	lw \$sp,0\(\$0\)
+			2bc: R_MEP_TPREL	symbol
+ 2c0:	0b cf 00 00 	lbu \$sp,0\(\$0\)
+			2c0: R_MEP_TPREL	symbol
+ 2c4:	0f cf 00 00 	lhu \$sp,0\(\$0\)
+			2c4: R_MEP_TPREL	symbol
+ 2c8:	f8 c0 00 80 	sb \$0,-32768\(\$sp\)
+ 2cc:	f9 c0 00 80 	sh \$0,-32768\(\$sp\)
+ 2d0:	fa c0 00 80 	sw \$0,-32768\(\$sp\)
+ 2d4:	fc c0 00 80 	lb \$0,-32768\(\$sp\)
+ 2d8:	fd c0 00 80 	lh \$0,-32768\(\$sp\)
+ 2dc:	fe c0 00 80 	lw \$0,-32768\(\$sp\)
+ 2e0:	fb c0 00 80 	lbu \$0,-32768\(\$sp\)
+ 2e4:	ff c0 00 80 	lhu \$0,-32768\(\$sp\)
+ 2e8:	f8 cf 00 80 	sb \$sp,-32768\(\$sp\)
+ 2ec:	f9 cf 00 80 	sh \$sp,-32768\(\$sp\)
+ 2f0:	fa cf 00 80 	sw \$sp,-32768\(\$sp\)
+ 2f4:	fc cf 00 80 	lb \$sp,-32768\(\$sp\)
+ 2f8:	fd cf 00 80 	lh \$sp,-32768\(\$sp\)
+ 2fc:	fe cf 00 80 	lw \$sp,-32768\(\$sp\)
+ 300:	fb cf 00 80 	lbu \$sp,-32768\(\$sp\)
+ 304:	ff cf 00 80 	lhu \$sp,-32768\(\$sp\)
+ 308:	f8 c0 ff 7f 	sb \$0,32767\(\$sp\)
+ 30c:	f9 c0 ff 7f 	sh \$0,32767\(\$sp\)
+ 310:	fa c0 ff 7f 	sw \$0,32767\(\$sp\)
+ 314:	fc c0 ff 7f 	lb \$0,32767\(\$sp\)
+ 318:	fd c0 ff 7f 	lh \$0,32767\(\$sp\)
+ 31c:	fe c0 ff 7f 	lw \$0,32767\(\$sp\)
+ 320:	fb c0 ff 7f 	lbu \$0,32767\(\$sp\)
+ 324:	ff c0 ff 7f 	lhu \$0,32767\(\$sp\)
+ 328:	f8 cf ff 7f 	sb \$sp,32767\(\$sp\)
+ 32c:	f9 cf ff 7f 	sh \$sp,32767\(\$sp\)
+ 330:	fa cf ff 7f 	sw \$sp,32767\(\$sp\)
+ 334:	fc cf ff 7f 	lb \$sp,32767\(\$sp\)
+ 338:	fd cf ff 7f 	lh \$sp,32767\(\$sp\)
+ 33c:	fe cf ff 7f 	lw \$sp,32767\(\$sp\)
+ 340:	fb cf ff 7f 	lbu \$sp,32767\(\$sp\)
+ 344:	ff cf ff 7f 	lhu \$sp,32767\(\$sp\)
+ 348:	f8 c0 00 00 	sb \$0,0\(\$sp\)
+			348: R_MEP_GPREL	symbol
+ 34c:	f9 c0 00 00 	sh \$0,0\(\$sp\)
+			34c: R_MEP_GPREL	symbol
+ 350:	fa c0 00 00 	sw \$0,0\(\$sp\)
+			350: R_MEP_GPREL	symbol
+ 354:	fc c0 00 00 	lb \$0,0\(\$sp\)
+			354: R_MEP_GPREL	symbol
+ 358:	fd c0 00 00 	lh \$0,0\(\$sp\)
+			358: R_MEP_GPREL	symbol
+ 35c:	fe c0 00 00 	lw \$0,0\(\$sp\)
+			35c: R_MEP_GPREL	symbol
+ 360:	fb c0 00 00 	lbu \$0,0\(\$sp\)
+			360: R_MEP_GPREL	symbol
+ 364:	ff c0 00 00 	lhu \$0,0\(\$sp\)
+			364: R_MEP_GPREL	symbol
+ 368:	f8 cf 00 00 	sb \$sp,0\(\$sp\)
+			368: R_MEP_GPREL	symbol
+ 36c:	f9 cf 00 00 	sh \$sp,0\(\$sp\)
+			36c: R_MEP_GPREL	symbol
+ 370:	fa cf 00 00 	sw \$sp,0\(\$sp\)
+			370: R_MEP_GPREL	symbol
+ 374:	fc cf 00 00 	lb \$sp,0\(\$sp\)
+			374: R_MEP_GPREL	symbol
+ 378:	fd cf 00 00 	lh \$sp,0\(\$sp\)
+			378: R_MEP_GPREL	symbol
+ 37c:	fe cf 00 00 	lw \$sp,0\(\$sp\)
+			37c: R_MEP_GPREL	symbol
+ 380:	fb cf 00 00 	lbu \$sp,0\(\$sp\)
+			380: R_MEP_GPREL	symbol
+ 384:	ff cf 00 00 	lhu \$sp,0\(\$sp\)
+			384: R_MEP_GPREL	symbol
+ 388:	f8 c0 00 80 	sb \$0,-32768\(\$sp\)
+ 38c:	f9 c0 00 80 	sh \$0,-32768\(\$sp\)
+ 390:	fa c0 00 80 	sw \$0,-32768\(\$sp\)
+ 394:	fc c0 00 80 	lb \$0,-32768\(\$sp\)
+ 398:	fd c0 00 80 	lh \$0,-32768\(\$sp\)
+ 39c:	fe c0 00 80 	lw \$0,-32768\(\$sp\)
+ 3a0:	fb c0 00 80 	lbu \$0,-32768\(\$sp\)
+ 3a4:	ff c0 00 80 	lhu \$0,-32768\(\$sp\)
+ 3a8:	f8 cf 00 80 	sb \$sp,-32768\(\$sp\)
+ 3ac:	f9 cf 00 80 	sh \$sp,-32768\(\$sp\)
+ 3b0:	fa cf 00 80 	sw \$sp,-32768\(\$sp\)
+ 3b4:	fc cf 00 80 	lb \$sp,-32768\(\$sp\)
+ 3b8:	fd cf 00 80 	lh \$sp,-32768\(\$sp\)
+ 3bc:	fe cf 00 80 	lw \$sp,-32768\(\$sp\)
+ 3c0:	fb cf 00 80 	lbu \$sp,-32768\(\$sp\)
+ 3c4:	ff cf 00 80 	lhu \$sp,-32768\(\$sp\)
+ 3c8:	f8 c0 ff 7f 	sb \$0,32767\(\$sp\)
+ 3cc:	f9 c0 ff 7f 	sh \$0,32767\(\$sp\)
+ 3d0:	fa c0 ff 7f 	sw \$0,32767\(\$sp\)
+ 3d4:	fc c0 ff 7f 	lb \$0,32767\(\$sp\)
+ 3d8:	fd c0 ff 7f 	lh \$0,32767\(\$sp\)
+ 3dc:	fe c0 ff 7f 	lw \$0,32767\(\$sp\)
+ 3e0:	fb c0 ff 7f 	lbu \$0,32767\(\$sp\)
+ 3e4:	ff c0 ff 7f 	lhu \$0,32767\(\$sp\)
+ 3e8:	f8 cf ff 7f 	sb \$sp,32767\(\$sp\)
+ 3ec:	f9 cf ff 7f 	sh \$sp,32767\(\$sp\)
+ 3f0:	fa cf ff 7f 	sw \$sp,32767\(\$sp\)
+ 3f4:	fc cf ff 7f 	lb \$sp,32767\(\$sp\)
+ 3f8:	fd cf ff 7f 	lh \$sp,32767\(\$sp\)
+ 3fc:	fe cf ff 7f 	lw \$sp,32767\(\$sp\)
+ 400:	fb cf ff 7f 	lbu \$sp,32767\(\$sp\)
+ 404:	ff cf ff 7f 	lhu \$sp,32767\(\$sp\)
+ 408:	f8 c0 00 00 	sb \$0,0\(\$sp\)
+			408: R_MEP_TPREL	symbol
+ 40c:	f9 c0 00 00 	sh \$0,0\(\$sp\)
+			40c: R_MEP_TPREL	symbol
+ 410:	02 40       	sw \$0,0x0\(\$sp\)
+			410: R_MEP_TPREL7A4	symbol
+ 412:	fc c0 00 00 	lb \$0,0\(\$sp\)
+			412: R_MEP_TPREL	symbol
+ 416:	fd c0 00 00 	lh \$0,0\(\$sp\)
+			416: R_MEP_TPREL	symbol
+ 41a:	03 40       	lw \$0,0x0\(\$sp\)
+			41a: R_MEP_TPREL7A4	symbol
+ 41c:	fb c0 00 00 	lbu \$0,0\(\$sp\)
+			41c: R_MEP_TPREL	symbol
+ 420:	ff c0 00 00 	lhu \$0,0\(\$sp\)
+			420: R_MEP_TPREL	symbol
+ 424:	f8 cf 00 00 	sb \$sp,0\(\$sp\)
+			424: R_MEP_TPREL	symbol
+ 428:	f9 cf 00 00 	sh \$sp,0\(\$sp\)
+			428: R_MEP_TPREL	symbol
+ 42c:	02 4f       	sw \$sp,0x0\(\$sp\)
+			42c: R_MEP_TPREL7A4	symbol
+ 42e:	fc cf 00 00 	lb \$sp,0\(\$sp\)
+			42e: R_MEP_TPREL	symbol
+ 432:	fd cf 00 00 	lh \$sp,0\(\$sp\)
+			432: R_MEP_TPREL	symbol
+ 436:	03 4f       	lw \$sp,0x0\(\$sp\)
+			436: R_MEP_TPREL7A4	symbol
+ 438:	fb cf 00 00 	lbu \$sp,0\(\$sp\)
+			438: R_MEP_TPREL	symbol
+ 43c:	ff cf 00 00 	lhu \$sp,0\(\$sp\)
+			43c: R_MEP_TPREL	symbol
+ 440:	02 e0 00 00 	sw \$0,\(0x0\)
+ 444:	03 e0 00 00 	lw \$0,\(0x0\)
+ 448:	02 ef 00 00 	sw \$sp,\(0x0\)
+ 44c:	03 ef 00 00 	lw \$sp,\(0x0\)
+ 450:	fe e0 ff ff 	sw \$0,\(0xfffffc\)
+ 454:	ff e0 ff ff 	lw \$0,\(0xfffffc\)
+ 458:	fe ef ff ff 	sw \$sp,\(0xfffffc\)
+ 45c:	ff ef ff ff 	lw \$sp,\(0xfffffc\)
+ 460:	02 e0 00 00 	sw \$0,\(0x0\)
+			460: R_MEP_ADDR24A4	symbol
+ 464:	03 e0 00 00 	lw \$0,\(0x0\)
+			464: R_MEP_ADDR24A4	symbol
+ 468:	02 ef 00 00 	sw \$sp,\(0x0\)
+			468: R_MEP_ADDR24A4	symbol
+ 46c:	03 ef 00 00 	lw \$sp,\(0x0\)
+			46c: R_MEP_ADDR24A4	symbol
+ 470:	0d 10       	extb \$0
+ 472:	8d 10       	extub \$0
+ 474:	2d 10       	exth \$0
+ 476:	ad 10       	extuh \$0
+ 478:	0d 1f       	extb \$sp
+ 47a:	8d 1f       	extub \$sp
+ 47c:	2d 1f       	exth \$sp
+ 47e:	ad 1f       	extuh \$sp
+ 480:	0c 10       	ssarb 0\(\$0\)
+ 482:	0c 13       	ssarb 3\(\$0\)
+ 484:	fc 10       	ssarb 0\(\$sp\)
+ 486:	fc 13       	ssarb 3\(\$sp\)
+ 488:	00 00       	nop
+ 48a:	00 0f       	mov \$sp,\$0
+ 48c:	f0 00       	mov \$0,\$sp
+ 48e:	f0 0f       	mov \$sp,\$sp
+ 490:	01 c0 00 80 	mov \$0,-32768
+ 494:	01 cf 00 80 	mov \$sp,-32768
+ 498:	80 50       	mov \$0,-128
+ 49a:	80 5f       	mov \$sp,-128
+ 49c:	00 50       	mov \$0,0
+ 49e:	00 5f       	mov \$sp,0
+ 4a0:	7f 50       	mov \$0,127
+ 4a2:	7f 5f       	mov \$sp,127
+ 4a4:	01 c0 ff 7f 	mov \$0,32767
+ 4a8:	01 cf ff 7f 	mov \$sp,32767
+ 4ac:	01 c0 00 00 	mov \$0,0
+			4ac: R_MEP_LOW16	symbol
+ 4b0:	01 c0 00 00 	mov \$0,0
+			4b0: R_MEP_HI16S	symbol
+ 4b4:	01 c0 00 00 	mov \$0,0
+			4b4: R_MEP_HI16U	symbol
+ 4b8:	01 c0 00 00 	mov \$0,0
+			4b8: R_MEP_GPREL	symbol
+ 4bc:	01 c0 00 00 	mov \$0,0
+			4bc: R_MEP_TPREL	symbol
+ 4c0:	00 d0 00 00 	movu \$0,0x0
+ 4c4:	00 d7 00 00 	movu \$7,0x0
+ 4c8:	ff d0 ff ff 	movu \$0,0xffffff
+ 4cc:	ff d7 ff ff 	movu \$7,0xffffff
+ 4d0:	11 c0 00 00 	movu \$0,0x0
+			4d0: R_MEP_LOW16	symbol
+ 4d4:	11 c7 00 00 	movu \$7,0x0
+			4d4: R_MEP_LOW16	symbol
+ 4d8:	00 d0 00 00 	movu \$0,0x0
+			4d8: R_MEP_UIMM24	symbol
+ 4dc:	00 d7 00 00 	movu \$7,0x0
+			4dc: R_MEP_UIMM24	symbol
+ 4e0:	00 d0 00 00 	movu \$0,0x0
+ 4e4:	21 c0 00 00 	movh \$0,0x0
+ 4e8:	11 cf 00 00 	movu \$sp,0x0
+ 4ec:	21 cf 00 00 	movh \$sp,0x0
+ 4f0:	ff d0 ff 00 	movu \$0,0xffff
+ 4f4:	21 c0 ff ff 	movh \$0,0xffff
+ 4f8:	11 cf ff ff 	movu \$sp,0xffff
+ 4fc:	21 cf ff ff 	movh \$sp,0xffff
+ 500:	11 c0 00 00 	movu \$0,0x0
+			500: R_MEP_LOW16	symbol
+ 504:	21 c0 00 00 	movh \$0,0x0
+			504: R_MEP_LOW16	symbol
+ 508:	11 cf 00 00 	movu \$sp,0x0
+			508: R_MEP_LOW16	symbol
+ 50c:	21 cf 00 00 	movh \$sp,0x0
+			50c: R_MEP_LOW16	symbol
+ 510:	11 c0 00 00 	movu \$0,0x0
+			510: R_MEP_HI16S	symbol
+ 514:	21 c0 00 00 	movh \$0,0x0
+			514: R_MEP_HI16S	symbol
+ 518:	11 cf 00 00 	movu \$sp,0x0
+			518: R_MEP_HI16S	symbol
+ 51c:	21 cf 00 00 	movh \$sp,0x0
+			51c: R_MEP_HI16S	symbol
+ 520:	11 c0 00 00 	movu \$0,0x0
+			520: R_MEP_HI16U	symbol
+ 524:	21 c0 00 00 	movh \$0,0x0
+			524: R_MEP_HI16U	symbol
+ 528:	11 cf 00 00 	movu \$sp,0x0
+			528: R_MEP_HI16U	symbol
+ 52c:	21 cf 00 00 	movh \$sp,0x0
+			52c: R_MEP_HI16U	symbol
+ 530:	11 c0 78 56 	movu \$0,0x5678
+ 534:	21 c0 78 56 	movh \$0,0x5678
+ 538:	11 cf 78 56 	movu \$sp,0x5678
+ 53c:	21 cf 78 56 	movh \$sp,0x5678
+ 540:	11 c0 34 12 	movu \$0,0x1234
+ 544:	21 c0 34 12 	movh \$0,0x1234
+ 548:	11 cf 34 12 	movu \$sp,0x1234
+ 54c:	21 cf 34 12 	movh \$sp,0x1234
+ 550:	11 c0 34 12 	movu \$0,0x1234
+ 554:	21 c0 34 12 	movh \$0,0x1234
+ 558:	11 cf 34 12 	movu \$sp,0x1234
+ 55c:	21 cf 34 12 	movh \$sp,0x1234
+ 560:	00 90       	add3 \$0,\$0,\$0
+ 562:	0f 90       	add3 \$sp,\$0,\$0
+ 564:	00 9f       	add3 \$0,\$sp,\$0
+ 566:	0f 9f       	add3 \$sp,\$sp,\$0
+ 568:	f0 90       	add3 \$0,\$0,\$sp
+ 56a:	ff 90       	add3 \$sp,\$0,\$sp
+ 56c:	f0 9f       	add3 \$0,\$sp,\$sp
+ 56e:	ff 9f       	add3 \$sp,\$sp,\$sp
+ 570:	c0 60       	add \$0,-16
+ 572:	c0 6f       	add \$sp,-16
+ 574:	00 60       	add \$0,0
+ 576:	00 6f       	add \$sp,0
+ 578:	3c 60       	add \$0,15
+ 57a:	3c 6f       	add \$sp,15
+ 57c:	00 40       	add3 \$0,\$sp,0x0
+ 57e:	00 4f       	add3 \$sp,\$sp,0x0
+ 580:	7c 40       	add3 \$0,\$sp,0x7c
+ 582:	7c 4f       	add3 \$sp,\$sp,0x7c
+ 584:	f0 c0 01 00 	add3 \$0,\$sp,1
+ 588:	f0 cf 01 00 	add3 \$sp,\$sp,1
+ 58c:	07 00       	advck3 \$0,\$0,\$0
+ 58e:	05 00       	sbvck3 \$0,\$0,\$0
+ 590:	07 0f       	advck3 \$0,\$sp,\$0
+ 592:	05 0f       	sbvck3 \$0,\$sp,\$0
+ 594:	f7 00       	advck3 \$0,\$0,\$sp
+ 596:	f5 00       	sbvck3 \$0,\$0,\$sp
+ 598:	f7 0f       	advck3 \$0,\$sp,\$sp
+ 59a:	f5 0f       	sbvck3 \$0,\$sp,\$sp
+ 59c:	04 00       	sub \$0,\$0
+ 59e:	01 00       	neg \$0,\$0
+ 5a0:	04 0f       	sub \$sp,\$0
+ 5a2:	01 0f       	neg \$sp,\$0
+ 5a4:	f4 00       	sub \$0,\$sp
+ 5a6:	f1 00       	neg \$0,\$sp
+ 5a8:	f4 0f       	sub \$sp,\$sp
+ 5aa:	f1 0f       	neg \$sp,\$sp
+ 5ac:	02 00       	slt3 \$0,\$0,\$0
+ 5ae:	03 00       	sltu3 \$0,\$0,\$0
+ 5b0:	06 20       	sl1ad3 \$0,\$0,\$0
+ 5b2:	07 20       	sl2ad3 \$0,\$0,\$0
+ 5b4:	02 0f       	slt3 \$0,\$sp,\$0
+ 5b6:	03 0f       	sltu3 \$0,\$sp,\$0
+ 5b8:	06 2f       	sl1ad3 \$0,\$sp,\$0
+ 5ba:	07 2f       	sl2ad3 \$0,\$sp,\$0
+ 5bc:	f2 00       	slt3 \$0,\$0,\$sp
+ 5be:	f3 00       	sltu3 \$0,\$0,\$sp
+ 5c0:	f6 20       	sl1ad3 \$0,\$0,\$sp
+ 5c2:	f7 20       	sl2ad3 \$0,\$0,\$sp
+ 5c4:	f2 0f       	slt3 \$0,\$sp,\$sp
+ 5c6:	f3 0f       	sltu3 \$0,\$sp,\$sp
+ 5c8:	f6 2f       	sl1ad3 \$0,\$sp,\$sp
+ 5ca:	f7 2f       	sl2ad3 \$0,\$sp,\$sp
+ 5cc:	00 c0 00 80 	add3 \$0,\$0,-32768
+ 5d0:	00 cf 00 80 	add3 \$sp,\$0,-32768
+ 5d4:	f0 c0 00 80 	add3 \$0,\$sp,-32768
+ 5d8:	f0 cf 00 80 	add3 \$sp,\$sp,-32768
+ 5dc:	00 c0 ff 7f 	add3 \$0,\$0,32767
+ 5e0:	00 cf ff 7f 	add3 \$sp,\$0,32767
+ 5e4:	f0 c0 ff 7f 	add3 \$0,\$sp,32767
+ 5e8:	f0 cf ff 7f 	add3 \$sp,\$sp,32767
+ 5ec:	00 c0 00 00 	add3 \$0,\$0,0
+			5ec: R_MEP_LOW16	symbol
+ 5f0:	00 cf 00 00 	add3 \$sp,\$0,0
+			5f0: R_MEP_LOW16	symbol
+ 5f4:	f0 c0 00 00 	add3 \$0,\$sp,0
+			5f4: R_MEP_LOW16	symbol
+ 5f8:	f0 cf 00 00 	add3 \$sp,\$sp,0
+			5f8: R_MEP_LOW16	symbol
+ 5fc:	01 60       	slt3 \$0,\$0,0x0
+ 5fe:	05 60       	sltu3 \$0,\$0,0x0
+ 600:	01 6f       	slt3 \$0,\$sp,0x0
+ 602:	05 6f       	sltu3 \$0,\$sp,0x0
+ 604:	f9 60       	slt3 \$0,\$0,0x1f
+ 606:	fd 60       	sltu3 \$0,\$0,0x1f
+ 608:	f9 6f       	slt3 \$0,\$sp,0x1f
+ 60a:	fd 6f       	sltu3 \$0,\$sp,0x1f
+ 60c:	00 10       	or \$0,\$0
+ 60e:	01 10       	and \$0,\$0
+ 610:	02 10       	xor \$0,\$0
+ 612:	03 10       	nor \$0,\$0
+ 614:	00 1f       	or \$sp,\$0
+ 616:	01 1f       	and \$sp,\$0
+ 618:	02 1f       	xor \$sp,\$0
+ 61a:	03 1f       	nor \$sp,\$0
+ 61c:	f0 10       	or \$0,\$sp
+ 61e:	f1 10       	and \$0,\$sp
+ 620:	f2 10       	xor \$0,\$sp
+ 622:	f3 10       	nor \$0,\$sp
+ 624:	f0 1f       	or \$sp,\$sp
+ 626:	f1 1f       	and \$sp,\$sp
+ 628:	f2 1f       	xor \$sp,\$sp
+ 62a:	f3 1f       	nor \$sp,\$sp
+ 62c:	04 c0 00 00 	or3 \$0,\$0,0x0
+ 630:	05 c0 00 00 	and3 \$0,\$0,0x0
+ 634:	06 c0 00 00 	xor3 \$0,\$0,0x0
+ 638:	04 cf 00 00 	or3 \$sp,\$0,0x0
+ 63c:	05 cf 00 00 	and3 \$sp,\$0,0x0
+ 640:	06 cf 00 00 	xor3 \$sp,\$0,0x0
+ 644:	f4 c0 00 00 	or3 \$0,\$sp,0x0
+ 648:	f5 c0 00 00 	and3 \$0,\$sp,0x0
+ 64c:	f6 c0 00 00 	xor3 \$0,\$sp,0x0
+ 650:	f4 cf 00 00 	or3 \$sp,\$sp,0x0
+ 654:	f5 cf 00 00 	and3 \$sp,\$sp,0x0
+ 658:	f6 cf 00 00 	xor3 \$sp,\$sp,0x0
+ 65c:	04 c0 ff ff 	or3 \$0,\$0,0xffff
+ 660:	05 c0 ff ff 	and3 \$0,\$0,0xffff
+ 664:	06 c0 ff ff 	xor3 \$0,\$0,0xffff
+ 668:	04 cf ff ff 	or3 \$sp,\$0,0xffff
+ 66c:	05 cf ff ff 	and3 \$sp,\$0,0xffff
+ 670:	06 cf ff ff 	xor3 \$sp,\$0,0xffff
+ 674:	f4 c0 ff ff 	or3 \$0,\$sp,0xffff
+ 678:	f5 c0 ff ff 	and3 \$0,\$sp,0xffff
+ 67c:	f6 c0 ff ff 	xor3 \$0,\$sp,0xffff
+ 680:	f4 cf ff ff 	or3 \$sp,\$sp,0xffff
+ 684:	f5 cf ff ff 	and3 \$sp,\$sp,0xffff
+ 688:	f6 cf ff ff 	xor3 \$sp,\$sp,0xffff
+ 68c:	04 c0 00 00 	or3 \$0,\$0,0x0
+			68c: R_MEP_LOW16	symbol
+ 690:	05 c0 00 00 	and3 \$0,\$0,0x0
+			690: R_MEP_LOW16	symbol
+ 694:	06 c0 00 00 	xor3 \$0,\$0,0x0
+			694: R_MEP_LOW16	symbol
+ 698:	04 cf 00 00 	or3 \$sp,\$0,0x0
+			698: R_MEP_LOW16	symbol
+ 69c:	05 cf 00 00 	and3 \$sp,\$0,0x0
+			69c: R_MEP_LOW16	symbol
+ 6a0:	06 cf 00 00 	xor3 \$sp,\$0,0x0
+			6a0: R_MEP_LOW16	symbol
+ 6a4:	f4 c0 00 00 	or3 \$0,\$sp,0x0
+			6a4: R_MEP_LOW16	symbol
+ 6a8:	f5 c0 00 00 	and3 \$0,\$sp,0x0
+			6a8: R_MEP_LOW16	symbol
+ 6ac:	f6 c0 00 00 	xor3 \$0,\$sp,0x0
+			6ac: R_MEP_LOW16	symbol
+ 6b0:	f4 cf 00 00 	or3 \$sp,\$sp,0x0
+			6b0: R_MEP_LOW16	symbol
+ 6b4:	f5 cf 00 00 	and3 \$sp,\$sp,0x0
+			6b4: R_MEP_LOW16	symbol
+ 6b8:	f6 cf 00 00 	xor3 \$sp,\$sp,0x0
+			6b8: R_MEP_LOW16	symbol
+ 6bc:	0d 20       	sra \$0,\$0
+ 6be:	0c 20       	srl \$0,\$0
+ 6c0:	0e 20       	sll \$0,\$0
+ 6c2:	0f 20       	fsft \$0,\$0
+ 6c4:	0d 2f       	sra \$sp,\$0
+ 6c6:	0c 2f       	srl \$sp,\$0
+ 6c8:	0e 2f       	sll \$sp,\$0
+ 6ca:	0f 2f       	fsft \$sp,\$0
+ 6cc:	fd 20       	sra \$0,\$sp
+ 6ce:	fc 20       	srl \$0,\$sp
+ 6d0:	fe 20       	sll \$0,\$sp
+ 6d2:	ff 20       	fsft \$0,\$sp
+ 6d4:	fd 2f       	sra \$sp,\$sp
+ 6d6:	fc 2f       	srl \$sp,\$sp
+ 6d8:	fe 2f       	sll \$sp,\$sp
+ 6da:	ff 2f       	fsft \$sp,\$sp
+ 6dc:	03 60       	sra \$0,0x0
+ 6de:	02 60       	srl \$0,0x0
+ 6e0:	06 60       	sll \$0,0x0
+ 6e2:	03 6f       	sra \$sp,0x0
+ 6e4:	02 6f       	srl \$sp,0x0
+ 6e6:	06 6f       	sll \$sp,0x0
+ 6e8:	fb 60       	sra \$0,0x1f
+ 6ea:	fa 60       	srl \$0,0x1f
+ 6ec:	fe 60       	sll \$0,0x1f
+ 6ee:	fb 6f       	sra \$sp,0x1f
+ 6f0:	fa 6f       	srl \$sp,0x1f
+ 6f2:	fe 6f       	sll \$sp,0x1f
+ 6f4:	07 60       	sll3 \$0,\$0,0x0
+ 6f6:	07 6f       	sll3 \$0,\$sp,0x0
+ 6f8:	ff 60       	sll3 \$0,\$0,0x1f
+ 6fa:	ff 6f       	sll3 \$0,\$sp,0x1f
+ 6fc:	02 b8       	bra 0xfffffefe
+ 6fe:	01 e0 00 04 	beq \$0,\$0,0xefe
+ 702:	00 b0       	bra 0x702
+			702: R_MEP_PCREL12A2	symbol
+ 704:	82 a0       	beqz \$0,0x686
+ 706:	83 a0       	bnez \$0,0x688
+ 708:	82 af       	beqz \$sp,0x68a
+ 70a:	83 af       	bnez \$sp,0x68c
+ 70c:	00 e0 40 00 	beqi \$0,0x0,0x78c
+ 710:	04 e0 40 00 	bnei \$0,0x0,0x790
+ 714:	00 ef 40 00 	beqi \$sp,0x0,0x794
+ 718:	04 ef 40 00 	bnei \$sp,0x0,0x798
+ 71c:	00 a0       	beqz \$0,0x71c
+			71c: R_MEP_PCREL8A2	symbol
+ 71e:	01 a0       	bnez \$0,0x71e
+			71e: R_MEP_PCREL8A2	symbol
+ 720:	00 af       	beqz \$sp,0x720
+			720: R_MEP_PCREL8A2	symbol
+ 722:	01 af       	bnez \$sp,0x722
+			722: R_MEP_PCREL8A2	symbol
+ 724:	00 e0 02 80 	beqi \$0,0x0,0xffff0728
+ 728:	04 e0 02 80 	bnei \$0,0x0,0xffff072c
+ 72c:	0c e0 02 80 	blti \$0,0x0,0xffff0730
+ 730:	08 e0 02 80 	bgei \$0,0x0,0xffff0734
+ 734:	00 ef 02 80 	beqi \$sp,0x0,0xffff0738
+ 738:	04 ef 02 80 	bnei \$sp,0x0,0xffff073c
+ 73c:	0c ef 02 80 	blti \$sp,0x0,0xffff0740
+ 740:	08 ef 02 80 	bgei \$sp,0x0,0xffff0744
+ 744:	f0 e0 02 80 	beqi \$0,0xf,0xffff0748
+ 748:	f4 e0 02 80 	bnei \$0,0xf,0xffff074c
+ 74c:	fc e0 02 80 	blti \$0,0xf,0xffff0750
+ 750:	f8 e0 02 80 	bgei \$0,0xf,0xffff0754
+ 754:	f0 ef 02 80 	beqi \$sp,0xf,0xffff0758
+ 758:	f4 ef 02 80 	bnei \$sp,0xf,0xffff075c
+ 75c:	fc ef 02 80 	blti \$sp,0xf,0xffff0760
+ 760:	f8 ef 02 80 	bgei \$sp,0xf,0xffff0764
+ 764:	00 e0 ff 3f 	beqi \$0,0x0,0x8762
+ 768:	04 e0 ff 3f 	bnei \$0,0x0,0x8766
+ 76c:	0c e0 ff 3f 	blti \$0,0x0,0x876a
+ 770:	08 e0 ff 3f 	bgei \$0,0x0,0x876e
+ 774:	00 ef ff 3f 	beqi \$sp,0x0,0x8772
+ 778:	04 ef ff 3f 	bnei \$sp,0x0,0x8776
+ 77c:	0c ef ff 3f 	blti \$sp,0x0,0x877a
+ 780:	08 ef ff 3f 	bgei \$sp,0x0,0x877e
+ 784:	f0 e0 ff 3f 	beqi \$0,0xf,0x8782
+ 788:	f4 e0 ff 3f 	bnei \$0,0xf,0x8786
+ 78c:	fc e0 ff 3f 	blti \$0,0xf,0x878a
+ 790:	f8 e0 ff 3f 	bgei \$0,0xf,0x878e
+ 794:	f0 ef ff 3f 	beqi \$sp,0xf,0x8792
+ 798:	f4 ef ff 3f 	bnei \$sp,0xf,0x8796
+ 79c:	fc ef ff 3f 	blti \$sp,0xf,0x879a
+ 7a0:	f8 ef ff 3f 	bgei \$sp,0xf,0x879e
+ 7a4:	00 e0 00 00 	beqi \$0,0x0,0x7a4
+			7a4: R_MEP_PCREL17A2	symbol
+ 7a8:	04 e0 00 00 	bnei \$0,0x0,0x7a8
+			7a8: R_MEP_PCREL17A2	symbol
+ 7ac:	0c e0 00 00 	blti \$0,0x0,0x7ac
+			7ac: R_MEP_PCREL17A2	symbol
+ 7b0:	08 e0 00 00 	bgei \$0,0x0,0x7b0
+			7b0: R_MEP_PCREL17A2	symbol
+ 7b4:	00 ef 00 00 	beqi \$sp,0x0,0x7b4
+			7b4: R_MEP_PCREL17A2	symbol
+ 7b8:	04 ef 00 00 	bnei \$sp,0x0,0x7b8
+			7b8: R_MEP_PCREL17A2	symbol
+ 7bc:	0c ef 00 00 	blti \$sp,0x0,0x7bc
+			7bc: R_MEP_PCREL17A2	symbol
+ 7c0:	08 ef 00 00 	bgei \$sp,0x0,0x7c0
+			7c0: R_MEP_PCREL17A2	symbol
+ 7c4:	f0 e0 00 00 	beqi \$0,0xf,0x7c4
+			7c4: R_MEP_PCREL17A2	symbol
+ 7c8:	f4 e0 00 00 	bnei \$0,0xf,0x7c8
+			7c8: R_MEP_PCREL17A2	symbol
+ 7cc:	fc e0 00 00 	blti \$0,0xf,0x7cc
+			7cc: R_MEP_PCREL17A2	symbol
+ 7d0:	f8 e0 00 00 	bgei \$0,0xf,0x7d0
+			7d0: R_MEP_PCREL17A2	symbol
+ 7d4:	f0 ef 00 00 	beqi \$sp,0xf,0x7d4
+			7d4: R_MEP_PCREL17A2	symbol
+ 7d8:	f4 ef 00 00 	bnei \$sp,0xf,0x7d8
+			7d8: R_MEP_PCREL17A2	symbol
+ 7dc:	fc ef 00 00 	blti \$sp,0xf,0x7dc
+			7dc: R_MEP_PCREL17A2	symbol
+ 7e0:	f8 ef 00 00 	bgei \$sp,0xf,0x7e0
+			7e0: R_MEP_PCREL17A2	symbol
+ 7e4:	01 e0 02 80 	beq \$0,\$0,0xffff07e8
+ 7e8:	05 e0 02 80 	bne \$0,\$0,0xffff07ec
+ 7ec:	01 ef 02 80 	beq \$sp,\$0,0xffff07f0
+ 7f0:	05 ef 02 80 	bne \$sp,\$0,0xffff07f4
+ 7f4:	f1 e0 02 80 	beq \$0,\$sp,0xffff07f8
+ 7f8:	f5 e0 02 80 	bne \$0,\$sp,0xffff07fc
+ 7fc:	f1 ef 02 80 	beq \$sp,\$sp,0xffff0800
+ 800:	f5 ef 02 80 	bne \$sp,\$sp,0xffff0804
+ 804:	01 e0 ff 3f 	beq \$0,\$0,0x8802
+ 808:	05 e0 ff 3f 	bne \$0,\$0,0x8806
+ 80c:	01 ef ff 3f 	beq \$sp,\$0,0x880a
+ 810:	05 ef ff 3f 	bne \$sp,\$0,0x880e
+ 814:	f1 e0 ff 3f 	beq \$0,\$sp,0x8812
+ 818:	f5 e0 ff 3f 	bne \$0,\$sp,0x8816
+ 81c:	f1 ef ff 3f 	beq \$sp,\$sp,0x881a
+ 820:	f5 ef ff 3f 	bne \$sp,\$sp,0x881e
+ 824:	01 e0 00 00 	beq \$0,\$0,0x824
+			824: R_MEP_PCREL17A2	symbol
+ 828:	05 e0 00 00 	bne \$0,\$0,0x828
+			828: R_MEP_PCREL17A2	symbol
+ 82c:	01 ef 00 00 	beq \$sp,\$0,0x82c
+			82c: R_MEP_PCREL17A2	symbol
+ 830:	05 ef 00 00 	bne \$sp,\$0,0x830
+			830: R_MEP_PCREL17A2	symbol
+ 834:	f1 e0 00 00 	beq \$0,\$sp,0x834
+			834: R_MEP_PCREL17A2	symbol
+ 838:	f5 e0 00 00 	bne \$0,\$sp,0x838
+			838: R_MEP_PCREL17A2	symbol
+ 83c:	f1 ef 00 00 	beq \$sp,\$sp,0x83c
+			83c: R_MEP_PCREL17A2	symbol
+ 840:	f5 ef 00 00 	bne \$sp,\$sp,0x840
+			840: R_MEP_PCREL17A2	symbol
+ 844:	29 d8 00 80 	bsr 0xff800848
+ 848:	03 b8       	bsr 0x4a
+ 84a:	09 d8 08 00 	bsr 0x104a
+ 84e:	19 d8 00 80 	bsr 0xff800850
+ 852:	09 d8 00 00 	bsr 0x852
+			852: R_MEP_PCREL24A2	symbol
+ 856:	0e 10       	jmp \$0
+ 858:	fe 10       	jmp \$sp
+ 85a:	08 d8 00 00 	jmp 0x0
+ 85e:	f8 df ff ff 	jmp 0xfffffe
+ 862:	08 d8 00 00 	jmp 0x0
+			862: R_MEP_PCABS24A2	symbol
+ 866:	0f 10       	jsr \$0
+ 868:	ff 10       	jsr \$sp
+ 86a:	02 70       	ret
+ 86c:	09 e0 02 80 	repeat \$0,0xffff0870
+ 870:	09 ef 02 80 	repeat \$sp,0xffff0874
+ 874:	09 e0 ff 3f 	repeat \$0,0x8872
+ 878:	09 ef ff 3f 	repeat \$sp,0x8876
+ 87c:	09 e0 00 00 	repeat \$0,0x87c
+			87c: R_MEP_PCREL17A2	symbol
+ 880:	09 ef 00 00 	repeat \$sp,0x880
+			880: R_MEP_PCREL17A2	symbol
+ 884:	19 e0 02 80 	erepeat 0xffff0888
+ 888:	19 e0 ff 3f 	erepeat 0x8886
+ 88c:	19 e0 00 00 	erepeat 0x88c
+			88c: R_MEP_PCREL17A2	symbol
+ 890:	08 70       	stc \$0,\$pc
+ 892:	0a 70       	ldc \$0,\$pc
+ 894:	08 7f       	stc \$sp,\$pc
+ 896:	0a 7f       	ldc \$sp,\$pc
+ 898:	18 70       	stc \$0,\$lp
+ 89a:	1a 70       	ldc \$0,\$lp
+ 89c:	18 7f       	stc \$sp,\$lp
+ 89e:	1a 7f       	ldc \$sp,\$lp
+ 8a0:	28 70       	stc \$0,\$sar
+ 8a2:	2a 70       	ldc \$0,\$sar
+ 8a4:	28 7f       	stc \$sp,\$sar
+ 8a6:	2a 7f       	ldc \$sp,\$sar
+ 8a8:	48 70       	stc \$0,\$rpb
+ 8aa:	4a 70       	ldc \$0,\$rpb
+ 8ac:	48 7f       	stc \$sp,\$rpb
+ 8ae:	4a 7f       	ldc \$sp,\$rpb
+ 8b0:	58 70       	stc \$0,\$rpe
+ 8b2:	5a 70       	ldc \$0,\$rpe
+ 8b4:	58 7f       	stc \$sp,\$rpe
+ 8b6:	5a 7f       	ldc \$sp,\$rpe
+ 8b8:	68 70       	stc \$0,\$rpc
+ 8ba:	6a 70       	ldc \$0,\$rpc
+ 8bc:	68 7f       	stc \$sp,\$rpc
+ 8be:	6a 7f       	ldc \$sp,\$rpc
+ 8c0:	78 70       	stc \$0,\$hi
+ 8c2:	7a 70       	ldc \$0,\$hi
+ 8c4:	78 7f       	stc \$sp,\$hi
+ 8c6:	7a 7f       	ldc \$sp,\$hi
+ 8c8:	88 70       	stc \$0,\$lo
+ 8ca:	8a 70       	ldc \$0,\$lo
+ 8cc:	88 7f       	stc \$sp,\$lo
+ 8ce:	8a 7f       	ldc \$sp,\$lo
+ 8d0:	c8 70       	stc \$0,\$mb0
+ 8d2:	ca 70       	ldc \$0,\$mb0
+ 8d4:	c8 7f       	stc \$sp,\$mb0
+ 8d6:	ca 7f       	ldc \$sp,\$mb0
+ 8d8:	d8 70       	stc \$0,\$me0
+ 8da:	da 70       	ldc \$0,\$me0
+ 8dc:	d8 7f       	stc \$sp,\$me0
+ 8de:	da 7f       	ldc \$sp,\$me0
+ 8e0:	e8 70       	stc \$0,\$mb1
+ 8e2:	ea 70       	ldc \$0,\$mb1
+ 8e4:	e8 7f       	stc \$sp,\$mb1
+ 8e6:	ea 7f       	ldc \$sp,\$mb1
+ 8e8:	f8 70       	stc \$0,\$me1
+ 8ea:	fa 70       	ldc \$0,\$me1
+ 8ec:	f8 7f       	stc \$sp,\$me1
+ 8ee:	fa 7f       	ldc \$sp,\$me1
+ 8f0:	09 70       	stc \$0,\$psw
+ 8f2:	0b 70       	ldc \$0,\$psw
+ 8f4:	09 7f       	stc \$sp,\$psw
+ 8f6:	0b 7f       	ldc \$sp,\$psw
+ 8f8:	19 70       	stc \$0,\$id
+ 8fa:	1b 70       	ldc \$0,\$id
+ 8fc:	19 7f       	stc \$sp,\$id
+ 8fe:	1b 7f       	ldc \$sp,\$id
+ 900:	29 70       	stc \$0,\$tmp
+ 902:	2b 70       	ldc \$0,\$tmp
+ 904:	29 7f       	stc \$sp,\$tmp
+ 906:	2b 7f       	ldc \$sp,\$tmp
+ 908:	39 70       	stc \$0,\$epc
+ 90a:	3b 70       	ldc \$0,\$epc
+ 90c:	39 7f       	stc \$sp,\$epc
+ 90e:	3b 7f       	ldc \$sp,\$epc
+ 910:	49 70       	stc \$0,\$exc
+ 912:	4b 70       	ldc \$0,\$exc
+ 914:	49 7f       	stc \$sp,\$exc
+ 916:	4b 7f       	ldc \$sp,\$exc
+ 918:	59 70       	stc \$0,\$cfg
+ 91a:	5b 70       	ldc \$0,\$cfg
+ 91c:	59 7f       	stc \$sp,\$cfg
+ 91e:	5b 7f       	ldc \$sp,\$cfg
+ 920:	79 70       	stc \$0,\$npc
+ 922:	7b 70       	ldc \$0,\$npc
+ 924:	79 7f       	stc \$sp,\$npc
+ 926:	7b 7f       	ldc \$sp,\$npc
+ 928:	89 70       	stc \$0,\$dbg
+ 92a:	8b 70       	ldc \$0,\$dbg
+ 92c:	89 7f       	stc \$sp,\$dbg
+ 92e:	8b 7f       	ldc \$sp,\$dbg
+ 930:	99 70       	stc \$0,\$depc
+ 932:	9b 70       	ldc \$0,\$depc
+ 934:	99 7f       	stc \$sp,\$depc
+ 936:	9b 7f       	ldc \$sp,\$depc
+ 938:	a9 70       	stc \$0,\$opt
+ 93a:	ab 70       	ldc \$0,\$opt
+ 93c:	a9 7f       	stc \$sp,\$opt
+ 93e:	ab 7f       	ldc \$sp,\$opt
+ 940:	b9 70       	stc \$0,\$rcfg
+ 942:	bb 70       	ldc \$0,\$rcfg
+ 944:	b9 7f       	stc \$sp,\$rcfg
+ 946:	bb 7f       	ldc \$sp,\$rcfg
+ 948:	c9 70       	stc \$0,\$ccfg
+ 94a:	cb 70       	ldc \$0,\$ccfg
+ 94c:	c9 7f       	stc \$sp,\$ccfg
+ 94e:	cb 7f       	ldc \$sp,\$ccfg
+ 950:	00 70       	di
+ 952:	10 70       	ei
+ 954:	12 70       	reti
+ 956:	22 70       	halt
+ 958:	32 70       	break
+ 95a:	11 70       	syncm
+ 95c:	06 70       	swi 0x0
+ 95e:	36 70       	swi 0x3
+ 960:	04 f0 00 00 	stcb \$0,0x0
+ 964:	14 f0 00 00 	ldcb \$0,0x0
+ 968:	04 ff 00 00 	stcb \$sp,0x0
+ 96c:	14 ff 00 00 	ldcb \$sp,0x0
+ 970:	04 f0 ff ff 	stcb \$0,0xffff
+ 974:	14 f0 ff ff 	ldcb \$0,0xffff
+ 978:	04 ff ff ff 	stcb \$sp,0xffff
+ 97c:	14 ff ff ff 	ldcb \$sp,0xffff
+ 980:	04 f0 00 00 	stcb \$0,0x0
+			982: R_MEP_16	symbol
+ 984:	14 f0 00 00 	ldcb \$0,0x0
+			986: R_MEP_16	symbol
+ 988:	04 ff 00 00 	stcb \$sp,0x0
+			98a: R_MEP_16	symbol
+ 98c:	14 ff 00 00 	ldcb \$sp,0x0
+			98e: R_MEP_16	symbol
+ 990:	00 20       	bsetm \(\$0\),0x0
+ 992:	01 20       	bclrm \(\$0\),0x0
+ 994:	02 20       	bnotm \(\$0\),0x0
+ 996:	f0 20       	bsetm \(\$sp\),0x0
+ 998:	f1 20       	bclrm \(\$sp\),0x0
+ 99a:	f2 20       	bnotm \(\$sp\),0x0
+ 99c:	00 27       	bsetm \(\$0\),0x7
+ 99e:	01 27       	bclrm \(\$0\),0x7
+ 9a0:	02 27       	bnotm \(\$0\),0x7
+ 9a2:	f0 27       	bsetm \(\$sp\),0x7
+ 9a4:	f1 27       	bclrm \(\$sp\),0x7
+ 9a6:	f2 27       	bnotm \(\$sp\),0x7
+ 9a8:	03 20       	btstm \$0,\(\$0\),0x0
+ 9aa:	f3 20       	btstm \$0,\(\$sp\),0x0
+ 9ac:	03 27       	btstm \$0,\(\$0\),0x7
+ 9ae:	f3 27       	btstm \$0,\(\$sp\),0x7
+ 9b0:	04 20       	tas \$0,\(\$0\)
+ 9b2:	04 2f       	tas \$sp,\(\$0\)
+ 9b4:	f4 20       	tas \$0,\(\$sp\)
+ 9b6:	f4 2f       	tas \$sp,\(\$sp\)
+ 9b8:	04 70       	cache 0x0,\(\$0\)
+ 9ba:	04 73       	cache 0x3,\(\$0\)
+ 9bc:	f4 70       	cache 0x0,\(\$sp\)
+ 9be:	f4 73       	cache 0x3,\(\$sp\)
+ 9c0:	04 10       	mul \$0,\$0
+ 9c2:	01 f0 04 30 	madd \$0,\$0
+ 9c6:	06 10       	mulr \$0,\$0
+ 9c8:	01 f0 06 30 	maddr \$0,\$0
+ 9cc:	05 10       	mulu \$0,\$0
+ 9ce:	01 f0 05 30 	maddu \$0,\$0
+ 9d2:	07 10       	mulru \$0,\$0
+ 9d4:	01 f0 07 30 	maddru \$0,\$0
+ 9d8:	04 1f       	mul \$sp,\$0
+ 9da:	01 ff 04 30 	madd \$sp,\$0
+ 9de:	06 1f       	mulr \$sp,\$0
+ 9e0:	01 ff 06 30 	maddr \$sp,\$0
+ 9e4:	05 1f       	mulu \$sp,\$0
+ 9e6:	01 ff 05 30 	maddu \$sp,\$0
+ 9ea:	07 1f       	mulru \$sp,\$0
+ 9ec:	01 ff 07 30 	maddru \$sp,\$0
+ 9f0:	f4 10       	mul \$0,\$sp
+ 9f2:	f1 f0 04 30 	madd \$0,\$sp
+ 9f6:	f6 10       	mulr \$0,\$sp
+ 9f8:	f1 f0 06 30 	maddr \$0,\$sp
+ 9fc:	f5 10       	mulu \$0,\$sp
+ 9fe:	f1 f0 05 30 	maddu \$0,\$sp
+ a02:	f7 10       	mulru \$0,\$sp
+ a04:	f1 f0 07 30 	maddru \$0,\$sp
+ a08:	f4 1f       	mul \$sp,\$sp
+ a0a:	f1 ff 04 30 	madd \$sp,\$sp
+ a0e:	f6 1f       	mulr \$sp,\$sp
+ a10:	f1 ff 06 30 	maddr \$sp,\$sp
+ a14:	f5 1f       	mulu \$sp,\$sp
+ a16:	f1 ff 05 30 	maddu \$sp,\$sp
+ a1a:	f7 1f       	mulru \$sp,\$sp
+ a1c:	f1 ff 07 30 	maddru \$sp,\$sp
+ a20:	08 10       	div \$0,\$0
+ a22:	09 10       	divu \$0,\$0
+ a24:	08 1f       	div \$sp,\$0
+ a26:	09 1f       	divu \$sp,\$0
+ a28:	f8 10       	div \$0,\$sp
+ a2a:	f9 10       	divu \$0,\$sp
+ a2c:	f8 1f       	div \$sp,\$sp
+ a2e:	f9 1f       	divu \$sp,\$sp
+ a30:	13 70       	dret
+ a32:	33 70       	dbreak
+ a34:	01 f0 00 00 	ldz \$0,\$0
+ a38:	01 f0 03 00 	abs \$0,\$0
+ a3c:	01 f0 02 00 	ave \$0,\$0
+ a40:	01 ff 00 00 	ldz \$sp,\$0
+ a44:	01 ff 03 00 	abs \$sp,\$0
+ a48:	01 ff 02 00 	ave \$sp,\$0
+ a4c:	f1 f0 00 00 	ldz \$0,\$sp
+ a50:	f1 f0 03 00 	abs \$0,\$sp
+ a54:	f1 f0 02 00 	ave \$0,\$sp
+ a58:	f1 ff 00 00 	ldz \$sp,\$sp
+ a5c:	f1 ff 03 00 	abs \$sp,\$sp
+ a60:	f1 ff 02 00 	ave \$sp,\$sp
+ a64:	01 f0 04 00 	min \$0,\$0
+ a68:	01 f0 05 00 	max \$0,\$0
+ a6c:	01 f0 06 00 	minu \$0,\$0
+ a70:	01 f0 07 00 	maxu \$0,\$0
+ a74:	01 ff 04 00 	min \$sp,\$0
+ a78:	01 ff 05 00 	max \$sp,\$0
+ a7c:	01 ff 06 00 	minu \$sp,\$0
+ a80:	01 ff 07 00 	maxu \$sp,\$0
+ a84:	f1 f0 04 00 	min \$0,\$sp
+ a88:	f1 f0 05 00 	max \$0,\$sp
+ a8c:	f1 f0 06 00 	minu \$0,\$sp
+ a90:	f1 f0 07 00 	maxu \$0,\$sp
+ a94:	f1 ff 04 00 	min \$sp,\$sp
+ a98:	f1 ff 05 00 	max \$sp,\$sp
+ a9c:	f1 ff 06 00 	minu \$sp,\$sp
+ aa0:	f1 ff 07 00 	maxu \$sp,\$sp
+ aa4:	01 f0 00 10 	clip \$0,0x0
+ aa8:	01 f0 01 10 	clipu \$0,0x0
+ aac:	01 ff 00 10 	clip \$sp,0x0
+ ab0:	01 ff 01 10 	clipu \$sp,0x0
+ ab4:	01 f0 f8 10 	clip \$0,0x1f
+ ab8:	01 f0 f9 10 	clipu \$0,0x1f
+ abc:	01 ff f8 10 	clip \$sp,0x1f
+ ac0:	01 ff f9 10 	clipu \$sp,0x1f
+ ac4:	01 f0 08 00 	sadd \$0,\$0
+ ac8:	01 f0 0a 00 	ssub \$0,\$0
+ acc:	01 f0 09 00 	saddu \$0,\$0
+ ad0:	01 f0 0b 00 	ssubu \$0,\$0
+ ad4:	01 ff 08 00 	sadd \$sp,\$0
+ ad8:	01 ff 0a 00 	ssub \$sp,\$0
+ adc:	01 ff 09 00 	saddu \$sp,\$0
+ ae0:	01 ff 0b 00 	ssubu \$sp,\$0
+ ae4:	f1 f0 08 00 	sadd \$0,\$sp
+ ae8:	f1 f0 0a 00 	ssub \$0,\$sp
+ aec:	f1 f0 09 00 	saddu \$0,\$sp
+ af0:	f1 f0 0b 00 	ssubu \$0,\$sp
+ af4:	f1 ff 08 00 	sadd \$sp,\$sp
+ af8:	f1 ff 0a 00 	ssub \$sp,\$sp
+ afc:	f1 ff 09 00 	saddu \$sp,\$sp
+ b00:	f1 ff 0b 00 	ssubu \$sp,\$sp
+ b04:	08 30       	swcp \$c0,\(\$0\)
+ b06:	09 30       	lwcp \$c0,\(\$0\)
+ b08:	0a 30       	smcp \$c0,\(\$0\)
+ b0a:	0b 30       	lmcp \$c0,\(\$0\)
+ b0c:	08 3f       	swcp \$c15,\(\$0\)
+ b0e:	09 3f       	lwcp \$c15,\(\$0\)
+ b10:	0a 3f       	smcp \$c15,\(\$0\)
+ b12:	0b 3f       	lmcp \$c15,\(\$0\)
+ b14:	f8 30       	swcp \$c0,\(\$sp\)
+ b16:	f9 30       	lwcp \$c0,\(\$sp\)
+ b18:	fa 30       	smcp \$c0,\(\$sp\)
+ b1a:	fb 30       	lmcp \$c0,\(\$sp\)
+ b1c:	f8 3f       	swcp \$c15,\(\$sp\)
+ b1e:	f9 3f       	lwcp \$c15,\(\$sp\)
+ b20:	fa 3f       	smcp \$c15,\(\$sp\)
+ b22:	fb 3f       	lmcp \$c15,\(\$sp\)
+ b24:	00 30       	swcpi \$c0,\(\$0\+\)
+ b26:	01 30       	lwcpi \$c0,\(\$0\+\)
+ b28:	02 30       	smcpi \$c0,\(\$0\+\)
+ b2a:	03 30       	lmcpi \$c0,\(\$0\+\)
+ b2c:	00 3f       	swcpi \$c15,\(\$0\+\)
+ b2e:	01 3f       	lwcpi \$c15,\(\$0\+\)
+ b30:	02 3f       	smcpi \$c15,\(\$0\+\)
+ b32:	03 3f       	lmcpi \$c15,\(\$0\+\)
+ b34:	f0 30       	swcpi \$c0,\(\$sp\+\)
+ b36:	f1 30       	lwcpi \$c0,\(\$sp\+\)
+ b38:	f2 30       	smcpi \$c0,\(\$sp\+\)
+ b3a:	f3 30       	lmcpi \$c0,\(\$sp\+\)
+ b3c:	f0 3f       	swcpi \$c15,\(\$sp\+\)
+ b3e:	f1 3f       	lwcpi \$c15,\(\$sp\+\)
+ b40:	f2 3f       	smcpi \$c15,\(\$sp\+\)
+ b42:	f3 3f       	lmcpi \$c15,\(\$sp\+\)
+ b44:	05 f0 80 00 	sbcpa \$c0,\(\$0\+\),-128
+ b48:	05 f0 80 40 	lbcpa \$c0,\(\$0\+\),-128
+ b4c:	05 f0 80 08 	sbcpm0 \$c0,\(\$0\+\),-128
+ b50:	05 f0 80 48 	lbcpm0 \$c0,\(\$0\+\),-128
+ b54:	05 f0 80 0c 	sbcpm1 \$c0,\(\$0\+\),-128
+ b58:	05 f0 80 4c 	lbcpm1 \$c0,\(\$0\+\),-128
+ b5c:	05 ff 80 00 	sbcpa \$c15,\(\$0\+\),-128
+ b60:	05 ff 80 40 	lbcpa \$c15,\(\$0\+\),-128
+ b64:	05 ff 80 08 	sbcpm0 \$c15,\(\$0\+\),-128
+ b68:	05 ff 80 48 	lbcpm0 \$c15,\(\$0\+\),-128
+ b6c:	05 ff 80 0c 	sbcpm1 \$c15,\(\$0\+\),-128
+ b70:	05 ff 80 4c 	lbcpm1 \$c15,\(\$0\+\),-128
+ b74:	f5 f0 80 00 	sbcpa \$c0,\(\$sp\+\),-128
+ b78:	f5 f0 80 40 	lbcpa \$c0,\(\$sp\+\),-128
+ b7c:	f5 f0 80 08 	sbcpm0 \$c0,\(\$sp\+\),-128
+ b80:	f5 f0 80 48 	lbcpm0 \$c0,\(\$sp\+\),-128
+ b84:	f5 f0 80 0c 	sbcpm1 \$c0,\(\$sp\+\),-128
+ b88:	f5 f0 80 4c 	lbcpm1 \$c0,\(\$sp\+\),-128
+ b8c:	f5 ff 80 00 	sbcpa \$c15,\(\$sp\+\),-128
+ b90:	f5 ff 80 40 	lbcpa \$c15,\(\$sp\+\),-128
+ b94:	f5 ff 80 08 	sbcpm0 \$c15,\(\$sp\+\),-128
+ b98:	f5 ff 80 48 	lbcpm0 \$c15,\(\$sp\+\),-128
+ b9c:	f5 ff 80 0c 	sbcpm1 \$c15,\(\$sp\+\),-128
+ ba0:	f5 ff 80 4c 	lbcpm1 \$c15,\(\$sp\+\),-128
+ ba4:	05 f0 7f 00 	sbcpa \$c0,\(\$0\+\),127
+ ba8:	05 f0 7f 40 	lbcpa \$c0,\(\$0\+\),127
+ bac:	05 f0 7f 08 	sbcpm0 \$c0,\(\$0\+\),127
+ bb0:	05 f0 7f 48 	lbcpm0 \$c0,\(\$0\+\),127
+ bb4:	05 f0 7f 0c 	sbcpm1 \$c0,\(\$0\+\),127
+ bb8:	05 f0 7f 4c 	lbcpm1 \$c0,\(\$0\+\),127
+ bbc:	05 ff 7f 00 	sbcpa \$c15,\(\$0\+\),127
+ bc0:	05 ff 7f 40 	lbcpa \$c15,\(\$0\+\),127
+ bc4:	05 ff 7f 08 	sbcpm0 \$c15,\(\$0\+\),127
+ bc8:	05 ff 7f 48 	lbcpm0 \$c15,\(\$0\+\),127
+ bcc:	05 ff 7f 0c 	sbcpm1 \$c15,\(\$0\+\),127
+ bd0:	05 ff 7f 4c 	lbcpm1 \$c15,\(\$0\+\),127
+ bd4:	f5 f0 7f 00 	sbcpa \$c0,\(\$sp\+\),127
+ bd8:	f5 f0 7f 40 	lbcpa \$c0,\(\$sp\+\),127
+ bdc:	f5 f0 7f 08 	sbcpm0 \$c0,\(\$sp\+\),127
+ be0:	f5 f0 7f 48 	lbcpm0 \$c0,\(\$sp\+\),127
+ be4:	f5 f0 7f 0c 	sbcpm1 \$c0,\(\$sp\+\),127
+ be8:	f5 f0 7f 4c 	lbcpm1 \$c0,\(\$sp\+\),127
+ bec:	f5 ff 7f 00 	sbcpa \$c15,\(\$sp\+\),127
+ bf0:	f5 ff 7f 40 	lbcpa \$c15,\(\$sp\+\),127
+ bf4:	f5 ff 7f 08 	sbcpm0 \$c15,\(\$sp\+\),127
+ bf8:	f5 ff 7f 48 	lbcpm0 \$c15,\(\$sp\+\),127
+ bfc:	f5 ff 7f 0c 	sbcpm1 \$c15,\(\$sp\+\),127
+ c00:	f5 ff 7f 4c 	lbcpm1 \$c15,\(\$sp\+\),127
+ c04:	05 f0 80 10 	shcpa \$c0,\(\$0\+\),-128
+ c08:	05 f0 80 50 	lhcpa \$c0,\(\$0\+\),-128
+ c0c:	05 f0 80 18 	shcpm0 \$c0,\(\$0\+\),-128
+ c10:	05 f0 80 58 	lhcpm0 \$c0,\(\$0\+\),-128
+ c14:	05 f0 80 1c 	shcpm1 \$c0,\(\$0\+\),-128
+ c18:	05 f0 80 5c 	lhcpm1 \$c0,\(\$0\+\),-128
+ c1c:	05 ff 80 10 	shcpa \$c15,\(\$0\+\),-128
+ c20:	05 ff 80 50 	lhcpa \$c15,\(\$0\+\),-128
+ c24:	05 ff 80 18 	shcpm0 \$c15,\(\$0\+\),-128
+ c28:	05 ff 80 58 	lhcpm0 \$c15,\(\$0\+\),-128
+ c2c:	05 ff 80 1c 	shcpm1 \$c15,\(\$0\+\),-128
+ c30:	05 ff 80 5c 	lhcpm1 \$c15,\(\$0\+\),-128
+ c34:	f5 f0 80 10 	shcpa \$c0,\(\$sp\+\),-128
+ c38:	f5 f0 80 50 	lhcpa \$c0,\(\$sp\+\),-128
+ c3c:	f5 f0 80 18 	shcpm0 \$c0,\(\$sp\+\),-128
+ c40:	f5 f0 80 58 	lhcpm0 \$c0,\(\$sp\+\),-128
+ c44:	f5 f0 80 1c 	shcpm1 \$c0,\(\$sp\+\),-128
+ c48:	f5 f0 80 5c 	lhcpm1 \$c0,\(\$sp\+\),-128
+ c4c:	f5 ff 80 10 	shcpa \$c15,\(\$sp\+\),-128
+ c50:	f5 ff 80 50 	lhcpa \$c15,\(\$sp\+\),-128
+ c54:	f5 ff 80 18 	shcpm0 \$c15,\(\$sp\+\),-128
+ c58:	f5 ff 80 58 	lhcpm0 \$c15,\(\$sp\+\),-128
+ c5c:	f5 ff 80 1c 	shcpm1 \$c15,\(\$sp\+\),-128
+ c60:	f5 ff 80 5c 	lhcpm1 \$c15,\(\$sp\+\),-128
+ c64:	05 f0 7e 10 	shcpa \$c0,\(\$0\+\),126
+ c68:	05 f0 7e 50 	lhcpa \$c0,\(\$0\+\),126
+ c6c:	05 f0 7e 18 	shcpm0 \$c0,\(\$0\+\),126
+ c70:	05 f0 7e 58 	lhcpm0 \$c0,\(\$0\+\),126
+ c74:	05 f0 7e 1c 	shcpm1 \$c0,\(\$0\+\),126
+ c78:	05 f0 7e 5c 	lhcpm1 \$c0,\(\$0\+\),126
+ c7c:	05 ff 7e 10 	shcpa \$c15,\(\$0\+\),126
+ c80:	05 ff 7e 50 	lhcpa \$c15,\(\$0\+\),126
+ c84:	05 ff 7e 18 	shcpm0 \$c15,\(\$0\+\),126
+ c88:	05 ff 7e 58 	lhcpm0 \$c15,\(\$0\+\),126
+ c8c:	05 ff 7e 1c 	shcpm1 \$c15,\(\$0\+\),126
+ c90:	05 ff 7e 5c 	lhcpm1 \$c15,\(\$0\+\),126
+ c94:	f5 f0 7e 10 	shcpa \$c0,\(\$sp\+\),126
+ c98:	f5 f0 7e 50 	lhcpa \$c0,\(\$sp\+\),126
+ c9c:	f5 f0 7e 18 	shcpm0 \$c0,\(\$sp\+\),126
+ ca0:	f5 f0 7e 58 	lhcpm0 \$c0,\(\$sp\+\),126
+ ca4:	f5 f0 7e 1c 	shcpm1 \$c0,\(\$sp\+\),126
+ ca8:	f5 f0 7e 5c 	lhcpm1 \$c0,\(\$sp\+\),126
+ cac:	f5 ff 7e 10 	shcpa \$c15,\(\$sp\+\),126
+ cb0:	f5 ff 7e 50 	lhcpa \$c15,\(\$sp\+\),126
+ cb4:	f5 ff 7e 18 	shcpm0 \$c15,\(\$sp\+\),126
+ cb8:	f5 ff 7e 58 	lhcpm0 \$c15,\(\$sp\+\),126
+ cbc:	f5 ff 7e 1c 	shcpm1 \$c15,\(\$sp\+\),126
+ cc0:	f5 ff 7e 5c 	lhcpm1 \$c15,\(\$sp\+\),126
+ cc4:	05 f0 80 20 	swcpa \$c0,\(\$0\+\),-128
+ cc8:	05 f0 80 60 	lwcpa \$c0,\(\$0\+\),-128
+ ccc:	05 f0 80 28 	swcpm0 \$c0,\(\$0\+\),-128
+ cd0:	05 f0 80 68 	lwcpm0 \$c0,\(\$0\+\),-128
+ cd4:	05 f0 80 2c 	swcpm1 \$c0,\(\$0\+\),-128
+ cd8:	05 f0 80 6c 	lwcpm1 \$c0,\(\$0\+\),-128
+ cdc:	05 ff 80 20 	swcpa \$c15,\(\$0\+\),-128
+ ce0:	05 ff 80 60 	lwcpa \$c15,\(\$0\+\),-128
+ ce4:	05 ff 80 28 	swcpm0 \$c15,\(\$0\+\),-128
+ ce8:	05 ff 80 68 	lwcpm0 \$c15,\(\$0\+\),-128
+ cec:	05 ff 80 2c 	swcpm1 \$c15,\(\$0\+\),-128
+ cf0:	05 ff 80 6c 	lwcpm1 \$c15,\(\$0\+\),-128
+ cf4:	f5 f0 80 20 	swcpa \$c0,\(\$sp\+\),-128
+ cf8:	f5 f0 80 60 	lwcpa \$c0,\(\$sp\+\),-128
+ cfc:	f5 f0 80 28 	swcpm0 \$c0,\(\$sp\+\),-128
+ d00:	f5 f0 80 68 	lwcpm0 \$c0,\(\$sp\+\),-128
+ d04:	f5 f0 80 2c 	swcpm1 \$c0,\(\$sp\+\),-128
+ d08:	f5 f0 80 6c 	lwcpm1 \$c0,\(\$sp\+\),-128
+ d0c:	f5 ff 80 20 	swcpa \$c15,\(\$sp\+\),-128
+ d10:	f5 ff 80 60 	lwcpa \$c15,\(\$sp\+\),-128
+ d14:	f5 ff 80 28 	swcpm0 \$c15,\(\$sp\+\),-128
+ d18:	f5 ff 80 68 	lwcpm0 \$c15,\(\$sp\+\),-128
+ d1c:	f5 ff 80 2c 	swcpm1 \$c15,\(\$sp\+\),-128
+ d20:	f5 ff 80 6c 	lwcpm1 \$c15,\(\$sp\+\),-128
+ d24:	05 f0 7c 20 	swcpa \$c0,\(\$0\+\),124
+ d28:	05 f0 7c 60 	lwcpa \$c0,\(\$0\+\),124
+ d2c:	05 f0 7c 28 	swcpm0 \$c0,\(\$0\+\),124
+ d30:	05 f0 7c 68 	lwcpm0 \$c0,\(\$0\+\),124
+ d34:	05 f0 7c 2c 	swcpm1 \$c0,\(\$0\+\),124
+ d38:	05 f0 7c 6c 	lwcpm1 \$c0,\(\$0\+\),124
+ d3c:	05 ff 7c 20 	swcpa \$c15,\(\$0\+\),124
+ d40:	05 ff 7c 60 	lwcpa \$c15,\(\$0\+\),124
+ d44:	05 ff 7c 28 	swcpm0 \$c15,\(\$0\+\),124
+ d48:	05 ff 7c 68 	lwcpm0 \$c15,\(\$0\+\),124
+ d4c:	05 ff 7c 2c 	swcpm1 \$c15,\(\$0\+\),124
+ d50:	05 ff 7c 6c 	lwcpm1 \$c15,\(\$0\+\),124
+ d54:	f5 f0 7c 20 	swcpa \$c0,\(\$sp\+\),124
+ d58:	f5 f0 7c 60 	lwcpa \$c0,\(\$sp\+\),124
+ d5c:	f5 f0 7c 28 	swcpm0 \$c0,\(\$sp\+\),124
+ d60:	f5 f0 7c 68 	lwcpm0 \$c0,\(\$sp\+\),124
+ d64:	f5 f0 7c 2c 	swcpm1 \$c0,\(\$sp\+\),124
+ d68:	f5 f0 7c 6c 	lwcpm1 \$c0,\(\$sp\+\),124
+ d6c:	f5 ff 7c 20 	swcpa \$c15,\(\$sp\+\),124
+ d70:	f5 ff 7c 60 	lwcpa \$c15,\(\$sp\+\),124
+ d74:	f5 ff 7c 28 	swcpm0 \$c15,\(\$sp\+\),124
+ d78:	f5 ff 7c 68 	lwcpm0 \$c15,\(\$sp\+\),124
+ d7c:	f5 ff 7c 2c 	swcpm1 \$c15,\(\$sp\+\),124
+ d80:	f5 ff 7c 6c 	lwcpm1 \$c15,\(\$sp\+\),124
+ d84:	05 f0 80 30 	smcpa \$c0,\(\$0\+\),-128
+ d88:	05 f0 80 70 	lmcpa \$c0,\(\$0\+\),-128
+ d8c:	05 f0 80 38 	smcpm0 \$c0,\(\$0\+\),-128
+ d90:	05 f0 80 78 	lmcpm0 \$c0,\(\$0\+\),-128
+ d94:	05 f0 80 3c 	smcpm1 \$c0,\(\$0\+\),-128
+ d98:	05 f0 80 7c 	lmcpm1 \$c0,\(\$0\+\),-128
+ d9c:	05 ff 80 30 	smcpa \$c15,\(\$0\+\),-128
+ da0:	05 ff 80 70 	lmcpa \$c15,\(\$0\+\),-128
+ da4:	05 ff 80 38 	smcpm0 \$c15,\(\$0\+\),-128
+ da8:	05 ff 80 78 	lmcpm0 \$c15,\(\$0\+\),-128
+ dac:	05 ff 80 3c 	smcpm1 \$c15,\(\$0\+\),-128
+ db0:	05 ff 80 7c 	lmcpm1 \$c15,\(\$0\+\),-128
+ db4:	f5 f0 80 30 	smcpa \$c0,\(\$sp\+\),-128
+ db8:	f5 f0 80 70 	lmcpa \$c0,\(\$sp\+\),-128
+ dbc:	f5 f0 80 38 	smcpm0 \$c0,\(\$sp\+\),-128
+ dc0:	f5 f0 80 78 	lmcpm0 \$c0,\(\$sp\+\),-128
+ dc4:	f5 f0 80 3c 	smcpm1 \$c0,\(\$sp\+\),-128
+ dc8:	f5 f0 80 7c 	lmcpm1 \$c0,\(\$sp\+\),-128
+ dcc:	f5 ff 80 30 	smcpa \$c15,\(\$sp\+\),-128
+ dd0:	f5 ff 80 70 	lmcpa \$c15,\(\$sp\+\),-128
+ dd4:	f5 ff 80 38 	smcpm0 \$c15,\(\$sp\+\),-128
+ dd8:	f5 ff 80 78 	lmcpm0 \$c15,\(\$sp\+\),-128
+ ddc:	f5 ff 80 3c 	smcpm1 \$c15,\(\$sp\+\),-128
+ de0:	f5 ff 80 7c 	lmcpm1 \$c15,\(\$sp\+\),-128
+ de4:	05 f0 78 30 	smcpa \$c0,\(\$0\+\),120
+ de8:	05 f0 78 70 	lmcpa \$c0,\(\$0\+\),120
+ dec:	05 f0 78 38 	smcpm0 \$c0,\(\$0\+\),120
+ df0:	05 f0 78 78 	lmcpm0 \$c0,\(\$0\+\),120
+ df4:	05 f0 78 3c 	smcpm1 \$c0,\(\$0\+\),120
+ df8:	05 f0 78 7c 	lmcpm1 \$c0,\(\$0\+\),120
+ dfc:	05 ff 78 30 	smcpa \$c15,\(\$0\+\),120
+ e00:	05 ff 78 70 	lmcpa \$c15,\(\$0\+\),120
+ e04:	05 ff 78 38 	smcpm0 \$c15,\(\$0\+\),120
+ e08:	05 ff 78 78 	lmcpm0 \$c15,\(\$0\+\),120
+ e0c:	05 ff 78 3c 	smcpm1 \$c15,\(\$0\+\),120
+ e10:	05 ff 78 7c 	lmcpm1 \$c15,\(\$0\+\),120
+ e14:	f5 f0 78 30 	smcpa \$c0,\(\$sp\+\),120
+ e18:	f5 f0 78 70 	lmcpa \$c0,\(\$sp\+\),120
+ e1c:	f5 f0 78 38 	smcpm0 \$c0,\(\$sp\+\),120
+ e20:	f5 f0 78 78 	lmcpm0 \$c0,\(\$sp\+\),120
+ e24:	f5 f0 78 3c 	smcpm1 \$c0,\(\$sp\+\),120
+ e28:	f5 f0 78 7c 	lmcpm1 \$c0,\(\$sp\+\),120
+ e2c:	f5 ff 78 30 	smcpa \$c15,\(\$sp\+\),120
+ e30:	f5 ff 78 70 	lmcpa \$c15,\(\$sp\+\),120
+ e34:	f5 ff 78 38 	smcpm0 \$c15,\(\$sp\+\),120
+ e38:	f5 ff 78 78 	lmcpm0 \$c15,\(\$sp\+\),120
+ e3c:	f5 ff 78 3c 	smcpm1 \$c15,\(\$sp\+\),120
+ e40:	f5 ff 78 7c 	lmcpm1 \$c15,\(\$sp\+\),120
+ e44:	04 d8 02 80 	bcpeq 0x0,0xffff0e48
+ e48:	05 d8 02 80 	bcpne 0x0,0xffff0e4c
+ e4c:	06 d8 02 80 	bcpat 0x0,0xffff0e50
+ e50:	07 d8 02 80 	bcpaf 0x0,0xffff0e54
+ e54:	f4 d8 02 80 	bcpeq 0xf,0xffff0e58
+ e58:	f5 d8 02 80 	bcpne 0xf,0xffff0e5c
+ e5c:	f6 d8 02 80 	bcpat 0xf,0xffff0e60
+ e60:	f7 d8 02 80 	bcpaf 0xf,0xffff0e64
+ e64:	04 d8 ff 3f 	bcpeq 0x0,0x8e62
+ e68:	05 d8 ff 3f 	bcpne 0x0,0x8e66
+ e6c:	06 d8 ff 3f 	bcpat 0x0,0x8e6a
+ e70:	07 d8 ff 3f 	bcpaf 0x0,0x8e6e
+ e74:	f4 d8 ff 3f 	bcpeq 0xf,0x8e72
+ e78:	f5 d8 ff 3f 	bcpne 0xf,0x8e76
+ e7c:	f6 d8 ff 3f 	bcpat 0xf,0x8e7a
+ e80:	f7 d8 ff 3f 	bcpaf 0xf,0x8e7e
+ e84:	04 d8 00 00 	bcpeq 0x0,0xe84
+			e84: R_MEP_PCREL17A2	symbol
+ e88:	05 d8 00 00 	bcpne 0x0,0xe88
+			e88: R_MEP_PCREL17A2	symbol
+ e8c:	06 d8 00 00 	bcpat 0x0,0xe8c
+			e8c: R_MEP_PCREL17A2	symbol
+ e90:	07 d8 00 00 	bcpaf 0x0,0xe90
+			e90: R_MEP_PCREL17A2	symbol
+ e94:	f4 d8 00 00 	bcpeq 0xf,0xe94
+			e94: R_MEP_PCREL17A2	symbol
+ e98:	f5 d8 00 00 	bcpne 0xf,0xe98
+			e98: R_MEP_PCREL17A2	symbol
+ e9c:	f6 d8 00 00 	bcpat 0xf,0xe9c
+			e9c: R_MEP_PCREL17A2	symbol
+ ea0:	f7 d8 00 00 	bcpaf 0xf,0xea0
+			ea0: R_MEP_PCREL17A2	symbol
+ ea4:	21 70       	synccp
+ ea6:	0f 18       	jsrv \$0
+ ea8:	ff 18       	jsrv \$sp
+ eaa:	2b d8 00 80 	bsrv 0xff800eae
+ eae:	fb df ff 7f 	bsrv 0x800eac
+ eb2:	0b d8 00 00 	bsrv 0xeb2
+			eb2: R_MEP_PCREL24A2	symbol
+ eb6:	00 00       	nop
+			eb6: R_MEP_8	symbol
+			eb7: R_MEP_16	symbol
+ eb8:	00 00       	nop
+			eb9: R_MEP_32	symbol
+ eba:	00 00       	nop
+.*
diff --git a/gas/testsuite/gas/mep/dj1.s b/gas/testsuite/gas/mep/dj1.s
new file mode 100644
index 000000000000..e281cb8fa9b1
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj1.s
@@ -0,0 +1,1306 @@
+
+	mov	$0,$0
+	mov	$1,$0
+	mov	$2,$0
+	mov	$3,$0
+	mov	$4,$0
+	mov	$5,$0
+	mov	$6,$0
+	mov	$7,$0
+	mov	$8,$0
+	mov	$9,$0
+	mov	$10,$0
+	mov	$11,$0
+	mov	$12,$0
+	mov	$13,$0
+	mov	$14,$0
+	mov	$15,$0
+
+	mov	$fp,$0
+	mov	$tp,$0
+	mov	$gp,$0
+	mov	$sp,$0
+
+
+	sb	$0,($0)
+	sh	$0,($0)
+	sw	$0,($0)
+	lb	$0,($0)
+	lh	$0,($0)
+	lw	$0,($0)
+	lbu	$0,($0)
+	lhu	$0,($0)
+	sb	$15,($0)
+	sh	$15,($0)
+	sw	$15,($0)
+	lb	$15,($0)
+	lh	$15,($0)
+	lw	$15,($0)
+	lbu	$15,($0)
+	lhu	$15,($0)
+	sb	$0,($15)
+	sh	$0,($15)
+	sw	$0,($15)
+	lb	$0,($15)
+	lh	$0,($15)
+	lw	$0,($15)
+	lbu	$0,($15)
+	lhu	$0,($15)
+	sb	$15,($15)
+	sh	$15,($15)
+	sw	$15,($15)
+	lb	$15,($15)
+	lh	$15,($15)
+	lw	$15,($15)
+	lbu	$15,($15)
+	lhu	$15,($15)
+
+	sw	$0,0($sp)
+	lw	$0,0($sp)
+	sw	$15,0($sp)
+	lw	$15,0($sp)
+	sw	$0,124($sp)
+	lw	$0,124($sp)
+	sw	$15,124($sp)
+	lw	$15,124($sp)
+	sw	$0,0($15)
+	lw	$0,0($15)
+	sw	$15,0($15)
+	lw	$15,0($15)
+	sw	$0,124($15)
+	lw	$0,124($15)
+	sw	$15,124($15)
+	lw	$15,124($15)
+
+	sb	$0,0($tp)
+	lb	$0,0($tp)
+	lbu	$0,0($tp)
+	sb	$7,0($tp)
+	lb	$7,0($tp)
+	lbu	$7,0($tp)
+	sb	$0,127($tp)
+	lb	$0,127($tp)
+	lbu	$0,127($tp)
+	sb	$7,127($tp)
+	lb	$7,127($tp)
+	lbu	$7,127($tp)
+	sb	$0,%tpoff(symbol)($tp)
+	lb	$0,%tpoff(symbol)($tp)
+	lbu	$0,%tpoff(symbol)($tp)
+	sb	$7,%tpoff(symbol)($tp)
+	lb	$7,%tpoff(symbol)($tp)
+	lbu	$7,%tpoff(symbol)($tp)
+	sb	$0,0($13)
+	lb	$0,0($13)
+	lbu	$0,0($13)
+	sb	$7,0($13)
+	lb	$7,0($13)
+	lbu	$7,0($13)
+	sb	$0,127($13)
+	lb	$0,127($13)
+	lbu	$0,127($13)
+	sb	$7,127($13)
+	lb	$7,127($13)
+	lbu	$7,127($13)
+	sb	$0,%tpoff(symbol)($13)
+	lb	$0,%tpoff(symbol)($13)
+	lbu	$0,%tpoff(symbol)($13)
+	sb	$7,%tpoff(symbol)($13)
+	lb	$7,%tpoff(symbol)($13)
+	lbu	$7,%tpoff(symbol)($13)
+
+	sh	$0,0($tp)
+	lh	$0,0($tp)
+	lhu	$0,0($tp)
+	sh	$7,0($tp)
+	lh	$7,0($tp)
+	lhu	$7,0($tp)
+	sh	$0,126($tp)
+	lh	$0,126($tp)
+	lhu	$0,126($tp)
+	sh	$7,126($tp)
+	lh	$7,126($tp)
+	lhu	$7,126($tp)
+	sh	$0,%tpoff(symbol)($tp)
+	lh	$0,%tpoff(symbol)($tp)
+	lhu	$0,%tpoff(symbol)($tp)
+	sh	$7,%tpoff(symbol)($tp)
+	lh	$7,%tpoff(symbol)($tp)
+	lhu	$7,%tpoff(symbol)($tp)
+	sh	$0,0($13)
+	lh	$0,0($13)
+	lhu	$0,0($13)
+	sh	$7,0($13)
+	lh	$7,0($13)
+	lhu	$7,0($13)
+	sh	$0,126($13)
+	lh	$0,126($13)
+	lhu	$0,126($13)
+	sh	$7,126($13)
+	lh	$7,126($13)
+	lhu	$7,126($13)
+	sh	$0,%tpoff(symbol)($13)
+	lh	$0,%tpoff(symbol)($13)
+	lhu	$0,%tpoff(symbol)($13)
+	sh	$7,%tpoff(symbol)($13)
+	lh	$7,%tpoff(symbol)($13)
+	lhu	$7,%tpoff(symbol)($13)
+
+	sw	$0,0($tp)
+	lw	$0,0($tp)
+	sw	$7,0($tp)
+	lw	$7,0($tp)
+	sw	$0,124($tp)
+	lw	$0,124($tp)
+	sw	$7,124($tp)
+	lw	$7,124($tp)
+	sw	$0,%tpoff(symbol)($tp)
+	lw	$0,%tpoff(symbol)($tp)
+	sw	$7,%tpoff(symbol)($tp)
+	lw	$7,%tpoff(symbol)($tp)
+	sw	$0,0($13)
+	lw	$0,0($13)
+	sw	$7,0($13)
+	lw	$7,0($13)
+	sw	$0,124($13)
+	lw	$0,124($13)
+	sw	$7,124($13)
+	lw	$7,124($13)
+	sw	$0,%tpoff(symbol)($13)
+	lw	$0,%tpoff(symbol)($13)
+	sw	$7,%tpoff(symbol)($13)
+	lw	$7,%tpoff(symbol)($13)
+
+	sb	$0,-32768($0)
+	sh	$0,-32768($0)
+	sw	$0,-32768($0)
+	lb	$0,-32768($0)
+	lh	$0,-32768($0)
+	lw	$0,-32768($0)
+	lbu	$0,-32768($0)
+	lhu	$0,-32768($0)
+	sb	$15,-32768($0)
+	sh	$15,-32768($0)
+	sw	$15,-32768($0)
+	lb	$15,-32768($0)
+	lh	$15,-32768($0)
+	lw	$15,-32768($0)
+	lbu	$15,-32768($0)
+	lhu	$15,-32768($0)
+	sb	$0,32767($0)
+	sh	$0,32767($0)
+	sw	$0,32767($0)
+	lb	$0,32767($0)
+	lh	$0,32767($0)
+	lw	$0,32767($0)
+	lbu	$0,32767($0)
+	lhu	$0,32767($0)
+	sb	$15,32767($0)
+	sh	$15,32767($0)
+	sw	$15,32767($0)
+	lb	$15,32767($0)
+	lh	$15,32767($0)
+	lw	$15,32767($0)
+	lbu	$15,32767($0)
+	lhu	$15,32767($0)
+	sb	$0,%sdaoff(symbol)($0)
+	sh	$0,%sdaoff(symbol)($0)
+	sw	$0,%sdaoff(symbol)($0)
+	lb	$0,%sdaoff(symbol)($0)
+	lh	$0,%sdaoff(symbol)($0)
+	lw	$0,%sdaoff(symbol)($0)
+	lbu	$0,%sdaoff(symbol)($0)
+	lhu	$0,%sdaoff(symbol)($0)
+	sb	$15,%sdaoff(symbol)($0)
+	sh	$15,%sdaoff(symbol)($0)
+	sw	$15,%sdaoff(symbol)($0)
+	lb	$15,%sdaoff(symbol)($0)
+	lh	$15,%sdaoff(symbol)($0)
+	lw	$15,%sdaoff(symbol)($0)
+	lbu	$15,%sdaoff(symbol)($0)
+	lhu	$15,%sdaoff(symbol)($0)
+	sb	$0,-32768($0)
+	sh	$0,-32768($0)
+	sw	$0,-32768($0)
+	lb	$0,-32768($0)
+	lh	$0,-32768($0)
+	lw	$0,-32768($0)
+	lbu	$0,-32768($0)
+	lhu	$0,-32768($0)
+	sb	$15,-32768($0)
+	sh	$15,-32768($0)
+	sw	$15,-32768($0)
+	lb	$15,-32768($0)
+	lh	$15,-32768($0)
+	lw	$15,-32768($0)
+	lbu	$15,-32768($0)
+	lhu	$15,-32768($0)
+	sb	$0,32767($0)
+	sh	$0,32767($0)
+	sw	$0,32767($0)
+	lb	$0,32767($0)
+	lh	$0,32767($0)
+	lw	$0,32767($0)
+	lbu	$0,32767($0)
+	lhu	$0,32767($0)
+	sb	$15,32767($0)
+	sh	$15,32767($0)
+	sw	$15,32767($0)
+	lb	$15,32767($0)
+	lh	$15,32767($0)
+	lw	$15,32767($0)
+	lbu	$15,32767($0)
+	lhu	$15,32767($0)
+	sb	$0,%tpoff(symbol)($0)
+	sh	$0,%tpoff(symbol)($0)
+	sw	$0,%tpoff(symbol)($0)
+	lb	$0,%tpoff(symbol)($0)
+	lh	$0,%tpoff(symbol)($0)
+	lw	$0,%tpoff(symbol)($0)
+	lbu	$0,%tpoff(symbol)($0)
+	lhu	$0,%tpoff(symbol)($0)
+	sb	$15,%tpoff(symbol)($0)
+	sh	$15,%tpoff(symbol)($0)
+	sw	$15,%tpoff(symbol)($0)
+	lb	$15,%tpoff(symbol)($0)
+	lh	$15,%tpoff(symbol)($0)
+	lw	$15,%tpoff(symbol)($0)
+	lbu	$15,%tpoff(symbol)($0)
+	lhu	$15,%tpoff(symbol)($0)
+	sb	$0,-32768($15)
+	sh	$0,-32768($15)
+	sw	$0,-32768($15)
+	lb	$0,-32768($15)
+	lh	$0,-32768($15)
+	lw	$0,-32768($15)
+	lbu	$0,-32768($15)
+	lhu	$0,-32768($15)
+	sb	$15,-32768($15)
+	sh	$15,-32768($15)
+	sw	$15,-32768($15)
+	lb	$15,-32768($15)
+	lh	$15,-32768($15)
+	lw	$15,-32768($15)
+	lbu	$15,-32768($15)
+	lhu	$15,-32768($15)
+	sb	$0,32767($15)
+	sh	$0,32767($15)
+	sw	$0,32767($15)
+	lb	$0,32767($15)
+	lh	$0,32767($15)
+	lw	$0,32767($15)
+	lbu	$0,32767($15)
+	lhu	$0,32767($15)
+	sb	$15,32767($15)
+	sh	$15,32767($15)
+	sw	$15,32767($15)
+	lb	$15,32767($15)
+	lh	$15,32767($15)
+	lw	$15,32767($15)
+	lbu	$15,32767($15)
+	lhu	$15,32767($15)
+	sb	$0,%sdaoff(symbol)($15)
+	sh	$0,%sdaoff(symbol)($15)
+	sw	$0,%sdaoff(symbol)($15)
+	lb	$0,%sdaoff(symbol)($15)
+	lh	$0,%sdaoff(symbol)($15)
+	lw	$0,%sdaoff(symbol)($15)
+	lbu	$0,%sdaoff(symbol)($15)
+	lhu	$0,%sdaoff(symbol)($15)
+	sb	$15,%sdaoff(symbol)($15)
+	sh	$15,%sdaoff(symbol)($15)
+	sw	$15,%sdaoff(symbol)($15)
+	lb	$15,%sdaoff(symbol)($15)
+	lh	$15,%sdaoff(symbol)($15)
+	lw	$15,%sdaoff(symbol)($15)
+	lbu	$15,%sdaoff(symbol)($15)
+	lhu	$15,%sdaoff(symbol)($15)
+	sb	$0,-32768($15)
+	sh	$0,-32768($15)
+	sw	$0,-32768($15)
+	lb	$0,-32768($15)
+	lh	$0,-32768($15)
+	lw	$0,-32768($15)
+	lbu	$0,-32768($15)
+	lhu	$0,-32768($15)
+	sb	$15,-32768($15)
+	sh	$15,-32768($15)
+	sw	$15,-32768($15)
+	lb	$15,-32768($15)
+	lh	$15,-32768($15)
+	lw	$15,-32768($15)
+	lbu	$15,-32768($15)
+	lhu	$15,-32768($15)
+	sb	$0,32767($15)
+	sh	$0,32767($15)
+	sw	$0,32767($15)
+	lb	$0,32767($15)
+	lh	$0,32767($15)
+	lw	$0,32767($15)
+	lbu	$0,32767($15)
+	lhu	$0,32767($15)
+	sb	$15,32767($15)
+	sh	$15,32767($15)
+	sw	$15,32767($15)
+	lb	$15,32767($15)
+	lh	$15,32767($15)
+	lw	$15,32767($15)
+	lbu	$15,32767($15)
+	lhu	$15,32767($15)
+	sb	$0,%tpoff(symbol)($15)
+	sh	$0,%tpoff(symbol)($15)
+	sw	$0,%tpoff(symbol)($15)
+	lb	$0,%tpoff(symbol)($15)
+	lh	$0,%tpoff(symbol)($15)
+	lw	$0,%tpoff(symbol)($15)
+	lbu	$0,%tpoff(symbol)($15)
+	lhu	$0,%tpoff(symbol)($15)
+	sb	$15,%tpoff(symbol)($15)
+	sh	$15,%tpoff(symbol)($15)
+	sw	$15,%tpoff(symbol)($15)
+	lb	$15,%tpoff(symbol)($15)
+	lh	$15,%tpoff(symbol)($15)
+	lw	$15,%tpoff(symbol)($15)
+	lbu	$15,%tpoff(symbol)($15)
+	lhu	$15,%tpoff(symbol)($15)
+
+	sw	$0,(0)
+	lw	$0,(0)
+	sw	$15,(0)
+	lw	$15,(0)
+	sw	$0,(0xfffffc)
+	lw	$0,(0xfffffc)
+	sw	$15,(0xfffffc)
+	lw	$15,(0xfffffc)
+	sw	$0,(symbol)
+	lw	$0,(symbol)
+	sw	$15,(symbol)
+	lw	$15,(symbol)
+
+
+	extb	$0
+	extub	$0
+	exth	$0
+	extuh	$0
+	extb	$15
+	extub	$15
+	exth	$15
+	extuh	$15
+
+
+	ssarb	0($0)
+	ssarb	3($0)
+	ssarb	0($15)
+	ssarb	3($15)
+
+
+	mov	$0,$0
+	mov	$15,$0
+	mov	$0,$15
+	mov	$15,$15
+	mov	$0,-32768
+	mov	$15,-32768
+	mov	$0,-128
+	mov	$15,-128
+	mov	$0,0
+	mov	$15,0
+	mov	$0,127
+	mov	$15,127
+	mov	$0,32767
+	mov	$15,32767
+
+	mov	$0,%lo(symbol)
+	mov	$0,%hi(symbol)
+	mov	$0,%uhi(symbol)
+	mov	$0,%sdaoff(symbol)
+	mov	$0,%tpoff(symbol)
+
+	movu	$0,0
+	movu	$7,0
+	movu	$0,0xffffff
+	movu	$7,0xffffff
+	movu	$0,%lo(symbol)
+	movu	$7,%lo(symbol)
+	movu	$0,symbol
+	movu	$7,symbol
+
+	movu	$0,0
+	movh	$0,0
+	movu	$15,0
+	movh	$15,0
+	movu	$0,0xffff
+	movh	$0,0xffff
+	movu	$15,0xffff
+	movh	$15,0xffff
+
+	movu	$0,%lo(symbol)
+	movh	$0,%lo(symbol)
+	movu	$15,%lo(symbol)
+	movh	$15,%lo(symbol)
+	movu	$0,%hi(symbol)
+	movh	$0,%hi(symbol)
+	movu	$15,%hi(symbol)
+	movh	$15,%hi(symbol)
+	movu	$0,%uhi(symbol)
+	movh	$0,%uhi(symbol)
+	movu	$15,%uhi(symbol)
+	movh	$15,%uhi(symbol)
+	movu	$0,%lo(0x12345678)
+	movh	$0,%lo(0x12345678)
+	movu	$15,%lo(0x12345678)
+	movh	$15,%lo(0x12345678)
+	movu	$0,%hi(0x12345678)
+	movh	$0,%hi(0x12345678)
+	movu	$15,%hi(0x12345678)
+	movh	$15,%hi(0x12345678)
+	movu	$0,%uhi(0x12345678)
+	movh	$0,%uhi(0x12345678)
+	movu	$15,%uhi(0x12345678)
+	movh	$15,%uhi(0x12345678)
+
+
+	add3	$0,$0,$0
+	add3	$15,$0,$0
+	add3	$0,$15,$0
+	add3	$15,$15,$0
+	add3	$0,$0,$15
+	add3	$15,$0,$15
+	add3	$0,$15,$15
+	add3	$15,$15,$15
+
+	add	$0,-16
+	add	$15,-16
+	add	$0,0
+	add	$15,0
+	add	$0,15
+	add	$15,15
+
+	add3	$0,$sp,0
+	add3	$15,$sp,0
+	add3	$0,$sp,124
+	add3	$15,$sp,124
+	add3	$0,$sp,1
+	add3	$15,$sp,1
+
+	advck3	$0,$0,$0
+	sbvck3	$0,$0,$0
+	advck3	$0,$15,$0
+	sbvck3	$0,$15,$0
+	advck3	$0,$0,$15
+	sbvck3	$0,$0,$15
+	advck3	$0,$15,$15
+	sbvck3	$0,$15,$15
+
+	sub	$0,$0
+	neg	$0,$0
+	sub	$15,$0
+	neg	$15,$0
+	sub	$0,$15
+	neg	$0,$15
+	sub	$15,$15
+	neg	$15,$15
+
+	slt3	$0,$0,$0
+	sltu3	$0,$0,$0
+	sl1ad3	$0,$0,$0
+	sl2ad3	$0,$0,$0
+	slt3	$0,$15,$0
+	sltu3	$0,$15,$0
+	sl1ad3	$0,$15,$0
+	sl2ad3	$0,$15,$0
+	slt3	$0,$0,$15
+	sltu3	$0,$0,$15
+	sl1ad3	$0,$0,$15
+	sl2ad3	$0,$0,$15
+	slt3	$0,$15,$15
+	sltu3	$0,$15,$15
+	sl1ad3	$0,$15,$15
+	sl2ad3	$0,$15,$15
+
+	add3	$0,$0,-32768
+	add3	$15,$0,-32768
+	add3	$0,$15,-32768
+	add3	$15,$15,-32768
+	add3	$0,$0,32767
+	add3	$15,$0,32767
+	add3	$0,$15,32767
+	add3	$15,$15,32767
+	add3	$0,$0,%lo(symbol)
+	add3	$15,$0,%lo(symbol)
+	add3	$0,$15,%lo(symbol)
+	add3	$15,$15,%lo(symbol)
+
+	slt3	$0,$0,0
+	sltu3	$0,$0,0
+	slt3	$0,$15,0
+	sltu3	$0,$15,0
+	slt3	$0,$0,31
+	sltu3	$0,$0,31
+	slt3	$0,$15,31
+	sltu3	$0,$15,31
+
+
+	or	$0,$0
+	and	$0,$0
+	xor	$0,$0
+	nor	$0,$0
+	or	$15,$0
+	and	$15,$0
+	xor	$15,$0
+	nor	$15,$0
+	or	$0,$15
+	and	$0,$15
+	xor	$0,$15
+	nor	$0,$15
+	or	$15,$15
+	and	$15,$15
+	xor	$15,$15
+	nor	$15,$15
+
+	or3	$0,$0,0
+	and3	$0,$0,0
+	xor3	$0,$0,0
+	or3	$15,$0,0
+	and3	$15,$0,0
+	xor3	$15,$0,0
+	or3	$0,$15,0
+	and3	$0,$15,0
+	xor3	$0,$15,0
+	or3	$15,$15,0
+	and3	$15,$15,0
+	xor3	$15,$15,0
+	or3	$0,$0,65535
+	and3	$0,$0,65535
+	xor3	$0,$0,65535
+	or3	$15,$0,65535
+	and3	$15,$0,65535
+	xor3	$15,$0,65535
+	or3	$0,$15,65535
+	and3	$0,$15,65535
+	xor3	$0,$15,65535
+	or3	$15,$15,65535
+	and3	$15,$15,65535
+	xor3	$15,$15,65535
+	or3	$0,$0,%lo(symbol)
+	and3	$0,$0,%lo(symbol)
+	xor3	$0,$0,%lo(symbol)
+	or3	$15,$0,%lo(symbol)
+	and3	$15,$0,%lo(symbol)
+	xor3	$15,$0,%lo(symbol)
+	or3	$0,$15,%lo(symbol)
+	and3	$0,$15,%lo(symbol)
+	xor3	$0,$15,%lo(symbol)
+	or3	$15,$15,%lo(symbol)
+	and3	$15,$15,%lo(symbol)
+	xor3	$15,$15,%lo(symbol)
+
+
+	sra	$0,$0
+	srl	$0,$0
+	sll	$0,$0
+	fsft	$0,$0
+	sra	$15,$0
+	srl	$15,$0
+	sll	$15,$0
+	fsft	$15,$0
+	sra	$0,$15
+	srl	$0,$15
+	sll	$0,$15
+	fsft	$0,$15
+	sra	$15,$15
+	srl	$15,$15
+	sll	$15,$15
+	fsft	$15,$15
+
+	sra	$0,0
+	srl	$0,0
+	sll	$0,0
+	sra	$15,0
+	srl	$15,0
+	sll	$15,0
+	sra	$0,31
+	srl	$0,31
+	sll	$0,31
+	sra	$15,31
+	srl	$15,31
+	sll	$15,31
+
+	sll3	$0,$0,0
+	sll3	$0,$15,0
+	sll3	$0,$0,31
+	sll3	$0,$15,31
+
+
+	bra	.-2048+2
+	bra	.+2046+2
+	bra	symbol
+
+	beqz	$0,.-128+2
+	bnez	$0,.-128+2
+	beqz	$15,.-128+2
+	bnez	$15,.-128+2
+	beqz	$0,.+126+2
+	bnez	$0,.+126+2
+	beqz	$15,.+126+2
+	bnez	$15,.+126+2
+	beqz	$0,symbol
+	bnez	$0,symbol
+	beqz	$15,symbol
+	bnez	$15,symbol
+
+	beqi	$0,0,.-65536+4
+	bnei	$0,0,.-65536+4
+	blti	$0,0,.-65536+4
+	bgei	$0,0,.-65536+4
+	beqi	$15,0,.-65536+4
+	bnei	$15,0,.-65536+4
+	blti	$15,0,.-65536+4
+	bgei	$15,0,.-65536+4
+	beqi	$0,15,.-65536+4
+	bnei	$0,15,.-65536+4
+	blti	$0,15,.-65536+4
+	bgei	$0,15,.-65536+4
+	beqi	$15,15,.-65536+4
+	bnei	$15,15,.-65536+4
+	blti	$15,15,.-65536+4
+	bgei	$15,15,.-65536+4
+	beqi	$0,0,.+32763+4
+	bnei	$0,0,.+32763+4
+	blti	$0,0,.+32763+4
+	bgei	$0,0,.+32763+4
+	beqi	$15,0,.+32763+4
+	bnei	$15,0,.+32763+4
+	blti	$15,0,.+32763+4
+	bgei	$15,0,.+32763+4
+	beqi	$0,15,.+32763+4
+	bnei	$0,15,.+32763+4
+	blti	$0,15,.+32763+4
+	bgei	$0,15,.+32763+4
+	beqi	$15,15,.+32763+4
+	bnei	$15,15,.+32763+4
+	blti	$15,15,.+32763+4
+	bgei	$15,15,.+32763+4
+	beqi	$0,0,symbol
+	bnei	$0,0,symbol
+	blti	$0,0,symbol
+	bgei	$0,0,symbol
+	beqi	$15,0,symbol
+	bnei	$15,0,symbol
+	blti	$15,0,symbol
+	bgei	$15,0,symbol
+	beqi	$0,15,symbol
+	bnei	$0,15,symbol
+	blti	$0,15,symbol
+	bgei	$0,15,symbol
+	beqi	$15,15,symbol
+	bnei	$15,15,symbol
+	blti	$15,15,symbol
+	bgei	$15,15,symbol
+
+	beq	$0,$0,.-65536+4
+	bne	$0,$0,.-65536+4
+	beq	$15,$0,.-65536+4
+	bne	$15,$0,.-65536+4
+	beq	$0,$15,.-65536+4
+	bne	$0,$15,.-65536+4
+	beq	$15,$15,.-65536+4
+	bne	$15,$15,.-65536+4
+	beq	$0,$0,.+32763+4
+	bne	$0,$0,.+32763+4
+	beq	$15,$0,.+32763+4
+	bne	$15,$0,.+32763+4
+	beq	$0,$15,.+32763+4
+	bne	$0,$15,.+32763+4
+	beq	$15,$15,.+32763+4
+	bne	$15,$15,.+32763+4
+	beq	$0,$0,symbol
+	bne	$0,$0,symbol
+	beq	$15,$0,symbol
+	bne	$15,$0,symbol
+	beq	$0,$15,symbol
+	bne	$0,$15,symbol
+	beq	$15,$15,symbol
+	bne	$15,$15,symbol
+
+	bsr	.-0x800000+4
+	bsr	.-2048+2
+	bsr	.+2046+2
+	bsr	.+0x7ffffe+4
+	bsr	symbol
+
+	jmp	$0
+	jmp	$15
+	jmp	0
+	jmp	0xfffffe
+	jmp	symbol
+
+	jsr	$0
+	jsr	$15
+
+	ret
+
+	repeat	$0,.-65536+4
+	repeat	$15,.-65536+4
+	repeat	$0,.+32763+4
+	repeat	$15,.+32763+4
+	repeat	$0,symbol
+	repeat	$15,symbol
+
+	erepeat	.-65536+4
+	erepeat	.+32763+4
+	erepeat	symbol
+
+
+	stc	$0,$pc
+	ldc	$0,$pc
+	stc	$15,$pc
+	ldc	$15,$pc
+	stc	$0,$lp
+	ldc	$0,$lp
+	stc	$15,$lp
+	ldc	$15,$lp
+	stc	$0,$sar
+	ldc	$0,$sar
+	stc	$15,$sar
+	ldc	$15,$sar
+	stc	$0,$rpb
+	ldc	$0,$rpb
+	stc	$15,$rpb
+	ldc	$15,$rpb
+	stc	$0,$rpe
+	ldc	$0,$rpe
+	stc	$15,$rpe
+	ldc	$15,$rpe
+	stc	$0,$rpc
+	ldc	$0,$rpc
+	stc	$15,$rpc
+	ldc	$15,$rpc
+	stc	$0,$hi
+	ldc	$0,$hi
+	stc	$15,$hi
+	ldc	$15,$hi
+	stc	$0,$lo
+	ldc	$0,$lo
+	stc	$15,$lo
+	ldc	$15,$lo
+	stc	$0,$mb0
+	ldc	$0,$mb0
+	stc	$15,$mb0
+	ldc	$15,$mb0
+	stc	$0,$me0
+	ldc	$0,$me0
+	stc	$15,$me0
+	ldc	$15,$me0
+	stc	$0,$mb1
+	ldc	$0,$mb1
+	stc	$15,$mb1
+	ldc	$15,$mb1
+	stc	$0,$me1
+	ldc	$0,$me1
+	stc	$15,$me1
+	ldc	$15,$me1
+
+	stc	$0,$psw
+	ldc	$0,$psw
+	stc	$15,$psw
+	ldc	$15,$psw
+	stc	$0,$id
+	ldc	$0,$id
+	stc	$15,$id
+	ldc	$15,$id
+	stc	$0,$tmp
+	ldc	$0,$tmp
+	stc	$15,$tmp
+	ldc	$15,$tmp
+	stc	$0,$epc
+	ldc	$0,$epc
+	stc	$15,$epc
+	ldc	$15,$epc
+	stc	$0,$exc
+	ldc	$0,$exc
+	stc	$15,$exc
+	ldc	$15,$exc
+	stc	$0,$cfg
+	ldc	$0,$cfg
+	stc	$15,$cfg
+	ldc	$15,$cfg
+	stc	$0,$npc
+	ldc	$0,$npc
+	stc	$15,$npc
+	ldc	$15,$npc
+	stc	$0,$dbg
+	ldc	$0,$dbg
+	stc	$15,$dbg
+	ldc	$15,$dbg
+	stc	$0,$depc
+	ldc	$0,$depc
+	stc	$15,$depc
+	ldc	$15,$depc
+	stc	$0,$opt
+	ldc	$0,$opt
+	stc	$15,$opt
+	ldc	$15,$opt
+	stc	$0,$rcfg
+	ldc	$0,$rcfg
+	stc	$15,$rcfg
+	ldc	$15,$rcfg
+	stc	$0,$ccfg
+	ldc	$0,$ccfg
+	stc	$15,$ccfg
+	ldc	$15,$ccfg
+
+	di
+	ei
+	reti
+	halt
+	break
+	syncm
+
+	swi	0
+	swi	3
+
+	stcb	$0,0
+	ldcb	$0,0
+	stcb	$15,0
+	ldcb	$15,0
+	stcb	$0,65535
+	ldcb	$0,65535
+	stcb	$15,65535
+	ldcb	$15,65535
+	stcb	$0,symbol
+	ldcb	$0,symbol
+	stcb	$15,symbol
+	ldcb	$15,symbol
+
+
+	bsetm	($0),0
+	bclrm	($0),0
+	bnotm	($0),0
+	bsetm	($15),0
+	bclrm	($15),0
+	bnotm	($15),0
+	bsetm	($0),7
+	bclrm	($0),7
+	bnotm	($0),7
+	bsetm	($15),7
+	bclrm	($15),7
+	bnotm	($15),7
+
+	btstm	$0,($0),0
+	btstm	$0,($15),0
+	btstm	$0,($0),7
+	btstm	$0,($15),7
+
+	tas	$0,($0)
+	tas	$15,($0)
+	tas	$0,($15)
+	tas	$15,($15)
+
+
+	cache	0,($0)
+	cache	3,($0)
+	cache	0,($15)
+	cache	3,($15)
+
+	mul	$0,$0
+	madd	$0,$0
+	mulr	$0,$0
+	maddr	$0,$0
+	mulu	$0,$0
+	maddu	$0,$0
+	mulru	$0,$0
+	maddru	$0,$0
+	mul	$15,$0
+	madd	$15,$0
+	mulr	$15,$0
+	maddr	$15,$0
+	mulu	$15,$0
+	maddu	$15,$0
+	mulru	$15,$0
+	maddru	$15,$0
+	mul	$0,$15
+	madd	$0,$15
+	mulr	$0,$15
+	maddr	$0,$15
+	mulu	$0,$15
+	maddu	$0,$15
+	mulru	$0,$15
+	maddru	$0,$15
+	mul	$15,$15
+	madd	$15,$15
+	mulr	$15,$15
+	maddr	$15,$15
+	mulu	$15,$15
+	maddu	$15,$15
+	mulru	$15,$15
+	maddru	$15,$15
+
+	div	$0,$0
+	divu	$0,$0
+	div	$15,$0
+	divu	$15,$0
+	div	$0,$15
+	divu	$0,$15
+	div	$15,$15
+	divu	$15,$15
+
+	dret
+	dbreak
+
+	ldz	$0,$0
+	abs	$0,$0
+	ave	$0,$0
+	ldz	$15,$0
+	abs	$15,$0
+	ave	$15,$0
+	ldz	$0,$15
+	abs	$0,$15
+	ave	$0,$15
+	ldz	$15,$15
+	abs	$15,$15
+	ave	$15,$15
+
+	min	$0,$0
+	max	$0,$0
+	minu	$0,$0
+	maxu	$0,$0
+	min	$15,$0
+	max	$15,$0
+	minu	$15,$0
+	maxu	$15,$0
+	min	$0,$15
+	max	$0,$15
+	minu	$0,$15
+	maxu	$0,$15
+	min	$15,$15
+	max	$15,$15
+	minu	$15,$15
+	maxu	$15,$15
+
+	clip	$0,0
+	clipu	$0,0
+	clip	$15,0
+	clipu	$15,0
+	clip	$0,31
+	clipu	$0,31
+	clip	$15,31
+	clipu	$15,31
+
+	sadd	$0,$0
+	ssub	$0,$0
+	saddu	$0,$0
+	ssubu	$0,$0
+	sadd	$15,$0
+	ssub	$15,$0
+	saddu	$15,$0
+	ssubu	$15,$0
+	sadd	$0,$15
+	ssub	$0,$15
+	saddu	$0,$15
+	ssubu	$0,$15
+	sadd	$15,$15
+	ssub	$15,$15
+	saddu	$15,$15
+	ssubu	$15,$15
+
+	swcp	$c0,($0)
+	lwcp	$c0,($0)
+	smcp	$c0,($0)
+	lmcp	$c0,($0)
+	swcp	$c15,($0)
+	lwcp	$c15,($0)
+	smcp	$c15,($0)
+	lmcp	$c15,($0)
+	swcp	$c0,($15)
+	lwcp	$c0,($15)
+	smcp	$c0,($15)
+	lmcp	$c0,($15)
+	swcp	$c15,($15)
+	lwcp	$c15,($15)
+	smcp	$c15,($15)
+	lmcp	$c15,($15)
+
+	swcpi	$c0,($0+)
+	lwcpi	$c0,($0+)
+	smcpi	$c0,($0+)
+	lmcpi	$c0,($0+)
+	swcpi	$c15,($0+)
+	lwcpi	$c15,($0+)
+	smcpi	$c15,($0+)
+	lmcpi	$c15,($0+)
+	swcpi	$c0,($15+)
+	lwcpi	$c0,($15+)
+	smcpi	$c0,($15+)
+	lmcpi	$c0,($15+)
+	swcpi	$c15,($15+)
+	lwcpi	$c15,($15+)
+	smcpi	$c15,($15+)
+	lmcpi	$c15,($15+)
+
+	sbcpa	$c0,($0+),-128
+	lbcpa	$c0,($0+),-128
+	sbcpm0	$c0,($0+),-128
+	lbcpm0	$c0,($0+),-128
+	sbcpm1	$c0,($0+),-128
+	lbcpm1	$c0,($0+),-128
+	sbcpa	$c15,($0+),-128
+	lbcpa	$c15,($0+),-128
+	sbcpm0	$c15,($0+),-128
+	lbcpm0	$c15,($0+),-128
+	sbcpm1	$c15,($0+),-128
+	lbcpm1	$c15,($0+),-128
+	sbcpa	$c0,($15+),-128
+	lbcpa	$c0,($15+),-128
+	sbcpm0	$c0,($15+),-128
+	lbcpm0	$c0,($15+),-128
+	sbcpm1	$c0,($15+),-128
+	lbcpm1	$c0,($15+),-128
+	sbcpa	$c15,($15+),-128
+	lbcpa	$c15,($15+),-128
+	sbcpm0	$c15,($15+),-128
+	lbcpm0	$c15,($15+),-128
+	sbcpm1	$c15,($15+),-128
+	lbcpm1	$c15,($15+),-128
+	sbcpa	$c0,($0+),127
+	lbcpa	$c0,($0+),127
+	sbcpm0	$c0,($0+),127
+	lbcpm0	$c0,($0+),127
+	sbcpm1	$c0,($0+),127
+	lbcpm1	$c0,($0+),127
+	sbcpa	$c15,($0+),127
+	lbcpa	$c15,($0+),127
+	sbcpm0	$c15,($0+),127
+	lbcpm0	$c15,($0+),127
+	sbcpm1	$c15,($0+),127
+	lbcpm1	$c15,($0+),127
+	sbcpa	$c0,($15+),127
+	lbcpa	$c0,($15+),127
+	sbcpm0	$c0,($15+),127
+	lbcpm0	$c0,($15+),127
+	sbcpm1	$c0,($15+),127
+	lbcpm1	$c0,($15+),127
+	sbcpa	$c15,($15+),127
+	lbcpa	$c15,($15+),127
+	sbcpm0	$c15,($15+),127
+	lbcpm0	$c15,($15+),127
+	sbcpm1	$c15,($15+),127
+	lbcpm1	$c15,($15+),127
+
+	shcpa	$c0,($0+),-128
+	lhcpa	$c0,($0+),-128
+	shcpm0	$c0,($0+),-128
+	lhcpm0	$c0,($0+),-128
+	shcpm1	$c0,($0+),-128
+	lhcpm1	$c0,($0+),-128
+	shcpa	$c15,($0+),-128
+	lhcpa	$c15,($0+),-128
+	shcpm0	$c15,($0+),-128
+	lhcpm0	$c15,($0+),-128
+	shcpm1	$c15,($0+),-128
+	lhcpm1	$c15,($0+),-128
+	shcpa	$c0,($15+),-128
+	lhcpa	$c0,($15+),-128
+	shcpm0	$c0,($15+),-128
+	lhcpm0	$c0,($15+),-128
+	shcpm1	$c0,($15+),-128
+	lhcpm1	$c0,($15+),-128
+	shcpa	$c15,($15+),-128
+	lhcpa	$c15,($15+),-128
+	shcpm0	$c15,($15+),-128
+	lhcpm0	$c15,($15+),-128
+	shcpm1	$c15,($15+),-128
+	lhcpm1	$c15,($15+),-128
+	shcpa	$c0,($0+),126
+	lhcpa	$c0,($0+),126
+	shcpm0	$c0,($0+),126
+	lhcpm0	$c0,($0+),126
+	shcpm1	$c0,($0+),126
+	lhcpm1	$c0,($0+),126
+	shcpa	$c15,($0+),126
+	lhcpa	$c15,($0+),126
+	shcpm0	$c15,($0+),126
+	lhcpm0	$c15,($0+),126
+	shcpm1	$c15,($0+),126
+	lhcpm1	$c15,($0+),126
+	shcpa	$c0,($15+),126
+	lhcpa	$c0,($15+),126
+	shcpm0	$c0,($15+),126
+	lhcpm0	$c0,($15+),126
+	shcpm1	$c0,($15+),126
+	lhcpm1	$c0,($15+),126
+	shcpa	$c15,($15+),126
+	lhcpa	$c15,($15+),126
+	shcpm0	$c15,($15+),126
+	lhcpm0	$c15,($15+),126
+	shcpm1	$c15,($15+),126
+	lhcpm1	$c15,($15+),126
+
+	swcpa	$c0,($0+),-128
+	lwcpa	$c0,($0+),-128
+	swcpm0	$c0,($0+),-128
+	lwcpm0	$c0,($0+),-128
+	swcpm1	$c0,($0+),-128
+	lwcpm1	$c0,($0+),-128
+	swcpa	$c15,($0+),-128
+	lwcpa	$c15,($0+),-128
+	swcpm0	$c15,($0+),-128
+	lwcpm0	$c15,($0+),-128
+	swcpm1	$c15,($0+),-128
+	lwcpm1	$c15,($0+),-128
+	swcpa	$c0,($15+),-128
+	lwcpa	$c0,($15+),-128
+	swcpm0	$c0,($15+),-128
+	lwcpm0	$c0,($15+),-128
+	swcpm1	$c0,($15+),-128
+	lwcpm1	$c0,($15+),-128
+	swcpa	$c15,($15+),-128
+	lwcpa	$c15,($15+),-128
+	swcpm0	$c15,($15+),-128
+	lwcpm0	$c15,($15+),-128
+	swcpm1	$c15,($15+),-128
+	lwcpm1	$c15,($15+),-128
+	swcpa	$c0,($0+),124
+	lwcpa	$c0,($0+),124
+	swcpm0	$c0,($0+),124
+	lwcpm0	$c0,($0+),124
+	swcpm1	$c0,($0+),124
+	lwcpm1	$c0,($0+),124
+	swcpa	$c15,($0+),124
+	lwcpa	$c15,($0+),124
+	swcpm0	$c15,($0+),124
+	lwcpm0	$c15,($0+),124
+	swcpm1	$c15,($0+),124
+	lwcpm1	$c15,($0+),124
+	swcpa	$c0,($15+),124
+	lwcpa	$c0,($15+),124
+	swcpm0	$c0,($15+),124
+	lwcpm0	$c0,($15+),124
+	swcpm1	$c0,($15+),124
+	lwcpm1	$c0,($15+),124
+	swcpa	$c15,($15+),124
+	lwcpa	$c15,($15+),124
+	swcpm0	$c15,($15+),124
+	lwcpm0	$c15,($15+),124
+	swcpm1	$c15,($15+),124
+	lwcpm1	$c15,($15+),124
+
+	smcpa	$c0,($0+),-128
+	lmcpa	$c0,($0+),-128
+	smcpm0	$c0,($0+),-128
+	lmcpm0	$c0,($0+),-128
+	smcpm1	$c0,($0+),-128
+	lmcpm1	$c0,($0+),-128
+	smcpa	$c15,($0+),-128
+	lmcpa	$c15,($0+),-128
+	smcpm0	$c15,($0+),-128
+	lmcpm0	$c15,($0+),-128
+	smcpm1	$c15,($0+),-128
+	lmcpm1	$c15,($0+),-128
+	smcpa	$c0,($15+),-128
+	lmcpa	$c0,($15+),-128
+	smcpm0	$c0,($15+),-128
+	lmcpm0	$c0,($15+),-128
+	smcpm1	$c0,($15+),-128
+	lmcpm1	$c0,($15+),-128
+	smcpa	$c15,($15+),-128
+	lmcpa	$c15,($15+),-128
+	smcpm0	$c15,($15+),-128
+	lmcpm0	$c15,($15+),-128
+	smcpm1	$c15,($15+),-128
+	lmcpm1	$c15,($15+),-128
+	smcpa	$c0,($0+),120
+	lmcpa	$c0,($0+),120
+	smcpm0	$c0,($0+),120
+	lmcpm0	$c0,($0+),120
+	smcpm1	$c0,($0+),120
+	lmcpm1	$c0,($0+),120
+	smcpa	$c15,($0+),120
+	lmcpa	$c15,($0+),120
+	smcpm0	$c15,($0+),120
+	lmcpm0	$c15,($0+),120
+	smcpm1	$c15,($0+),120
+	lmcpm1	$c15,($0+),120
+	smcpa	$c0,($15+),120
+	lmcpa	$c0,($15+),120
+	smcpm0	$c0,($15+),120
+	lmcpm0	$c0,($15+),120
+	smcpm1	$c0,($15+),120
+	lmcpm1	$c0,($15+),120
+	smcpa	$c15,($15+),120
+	lmcpa	$c15,($15+),120
+	smcpm0	$c15,($15+),120
+	lmcpm0	$c15,($15+),120
+	smcpm1	$c15,($15+),120
+	lmcpm1	$c15,($15+),120
+
+/*	
+	cmov	$c0,$0
+	cmov	$c15,$0
+	cmov	$c0,$15
+	cmov	$c15,$15
+
+	cmov	$0,$c0
+	cmov	$15,$c0
+	cmov	$0,$c15
+	cmov	$15,$c15
+
+	cmovc	$ccr0,$0
+	cmovc	$ccr15,$0
+	cmovc	$ccr0,$15
+	cmovc	$ccr15,$15
+
+	cmovc	$0,$ccr0
+	cmovc	$15,$ccr0
+	cmovc	$0,$ccr15
+	cmovc	$15,$ccr15
+
+	cmovh	$c0,$0
+	cmovh	$c15,$0
+	cmovh	$c0,$15
+	cmovh	$c15,$15
+
+	cmovh	$0,$c0
+	cmovh	$15,$c0
+	cmovh	$0,$c15
+	cmovh	$15,$c15
+*/
+	bcpeq	0,.-65536+4
+	bcpne	0,.-65536+4
+	bcpat	0,.-65536+4
+	bcpaf	0,.-65536+4
+	bcpeq	15,.-65536+4
+	bcpne	15,.-65536+4
+	bcpat	15,.-65536+4
+	bcpaf	15,.-65536+4
+	bcpeq	0,.+32763+4
+	bcpne	0,.+32763+4
+	bcpat	0,.+32763+4
+	bcpaf	0,.+32763+4
+	bcpeq	15,.+32763+4
+	bcpne	15,.+32763+4
+	bcpat	15,.+32763+4
+	bcpaf	15,.+32763+4
+	bcpeq	0,symbol
+	bcpne	0,symbol
+	bcpat	0,symbol
+	bcpaf	0,symbol
+	bcpeq	15,symbol
+	bcpne	15,symbol
+	bcpat	15,symbol
+	bcpaf	15,symbol
+
+	synccp
+
+	jsrv	$0
+	jsrv	$15
+
+	bsrv	.+4-0x800000
+	bsrv	.+4+0x7ffffb
+	bsrv	symbol
+
+
+	.byte	symbol
+	.short	symbol
+	.long	symbol
+
+
diff --git a/gas/testsuite/gas/mep/dj2.d b/gas/testsuite/gas/mep/dj2.d
new file mode 100644
index 000000000000..9634cf4c4327
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj2.d
@@ -0,0 +1,11 @@
+#as:
+#objdump: -dr
+#name: dj2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	07 88       	sb \$7,\(\$8\)
+   2:	05 98       	sb \$5,\(\$9\)
diff --git a/gas/testsuite/gas/mep/dj2.le.d b/gas/testsuite/gas/mep/dj2.le.d
new file mode 100644
index 000000000000..1c1053c51a9e
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj2.le.d
@@ -0,0 +1,12 @@
+#as: -EL
+#objdump: -dr
+#source: dj2.s
+#name: dj2.le
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	88 07       	sb \$7,\(\$8\)
+   2:	98 05       	sb \$5,\(\$9\)
diff --git a/gas/testsuite/gas/mep/dj2.s b/gas/testsuite/gas/mep/dj2.s
new file mode 100644
index 000000000000..4eabf82b0f08
--- /dev/null
+++ b/gas/testsuite/gas/mep/dj2.s
@@ -0,0 +1,5 @@
+
+	.text
+	sb $7,($fp)
+	sb $5,($9)
+
diff --git a/gas/testsuite/gas/mep/relocs-bad3.s b/gas/testsuite/gas/mep/relocs-bad3.s
new file mode 100644
index 000000000000..1e80a6b0dda3
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs-bad3.s
@@ -0,0 +1,15 @@
+	.global main
+
+test:
+	mov     $0,0
+
+# negative test from case 106708
+
+L1:
+        mov     $1,1
+        mov     $1,((L1 & 0x00007fff) | 0x00008000)
+        ret
+        mov     $0,0
+main:
+	mov     $0,0
+	ret
diff --git a/gas/testsuite/gas/mep/relocs-junk1.s b/gas/testsuite/gas/mep/relocs-junk1.s
new file mode 100644
index 000000000000..6e9c6c2be09b
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs-junk1.s
@@ -0,0 +1,8 @@
+junk1:
+	nop
+	nop
+	nop
+	nop
+	nop
+ .data
+foodata: .word 42
diff --git a/gas/testsuite/gas/mep/relocs-junk2.s b/gas/testsuite/gas/mep/relocs-junk2.s
new file mode 100644
index 000000000000..361ad6ec7cf7
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs-junk2.s
@@ -0,0 +1,7 @@
+junk2:
+	nop
+	nop
+	nop
+	nop
+	nop
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/mep/relocs-refs.s b/gas/testsuite/gas/mep/relocs-refs.s
new file mode 100644
index 000000000000..43dc77ee64b9
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs-refs.s
@@ -0,0 +1,55 @@
+
+	.global main
+	.global foo
+	.global bar
+main:
+	nop
+	nop
+	lb $5, foo($3)
+	bsr foo
+	repeat $5, foo
+	
+	nop
+	nop
+	lb $5, (-foo & 0xffff)($3)
+	bsr -foo
+	repeat $5, -foo
+
+	nop
+	nop
+	lb $5, (foo + bar)($3)
+	bsr (foo + bar)
+	repeat $5, (foo + bar)
+
+	jmp (foo << 3)
+	jmp (foo >> 3)
+	jmp (foo - bar) & 0x7fffff
+	jmp (foo - main) & 0x7fffff
+	jmp (.text - foo) & 0x7fffff
+	jmp (.data - foo) & 0x7fffff
+	jmp (foo - %sizeof(.text))
+	jmp (foo * 7)
+	jmp (foo / 7)
+	jmp (foo % 7)
+	jmp (foo ^ bar)
+	jmp (foo | bar)
+	jmp (foo & bar)
+	jmp (foo == bar) << 5
+	jmp (foo < bar) << 5
+	jmp (foo <= bar) << 5
+	jmp (foo > bar) << 5
+	jmp (foo >= bar) << 5
+        # jmp (foo != bar)	# FIXME this appears to not work atm.
+	jmp (foo && bar) << 5
+	jmp (foo || bar) << 5
+
+	nop
+	nop
+	nop
+	nop
+
+	jmp %sizeof(.data) >> (((main ^ (bar + 0xf)) - ((foo | .text) << 2)) / 3)
+
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/mep/relocs-syms.s b/gas/testsuite/gas/mep/relocs-syms.s
new file mode 100644
index 000000000000..508efaf10327
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs-syms.s
@@ -0,0 +1,18 @@
+	.global foo
+	.global bar
+	nop
+	nop
+	nop
+	nop
+foo:
+	nop
+	nop
+	nop
+	nop
+bar:
+	nop
+	nop
+	nop
+	nop
+	nop
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/mep/relocs.d b/gas/testsuite/gas/mep/relocs.d
new file mode 100644
index 000000000000..602545a316e5
--- /dev/null
+++ b/gas/testsuite/gas/mep/relocs.d
@@ -0,0 +1,98 @@
+
+relocs.x:     file format elf32-mep
+
+Contents of section .text:
+ 1000 00000000 00000000 00000000 00000000  ................
+ 1010 00000000 00000000 00000000 00000000  ................
+ 1020 00000000 00000000 00000000 00000000  ................
+ 1030 0000c53c 1012dee9 ffffe509 ffec0000  ...<............
+ 1040 0000c53c efeedd49 ffdfe509 efd20000  ...<...I........
+ 1050 0000c53c 202cdeb9 000fe509 07e9dc88  ...< ,..........
+ 1060 0080d818 0002dfc8 7fffdf28 7fffdf78  ...........\(...x
+ 1070 7fffdd98 0001da98 000fdbf8 0070da58  .............p.X
+ 1080 0002d828 0000d848 0000d8d8 0010d898  ...\(...H........
+ 1090 0010d808 0000d908 0000d908 0000d808  ................
+ 10a0 0000d808 0000d908 0000d908 00000000  ................
+ 10b0 00000000 0000d808 00000000 00000000  ................
+Contents of section .rostacktab:
+ 10c0 001ffff0                             ....            
+Contents of section .data:
+ 11c4 0000002a                             ...*            
+Disassembly of section .text:
+
+00001000 <junk1>:
+    1000:	00 00       	nop
+    1002:	00 00       	nop
+    1004:	00 00       	nop
+    1006:	00 00       	nop
+    1008:	00 00       	nop
+    100a:	00 00       	nop
+    100c:	00 00       	nop
+    100e:	00 00       	nop
+    1010:	00 00       	nop
+
+00001012 <foo>:
+    1012:	00 00       	nop
+    1014:	00 00       	nop
+    1016:	00 00       	nop
+    1018:	00 00       	nop
+
+0000101a <bar>:
+    101a:	00 00       	nop
+    101c:	00 00       	nop
+    101e:	00 00       	nop
+    1020:	00 00       	nop
+    1022:	00 00       	nop
+
+00001024 <junk2>:
+    1024:	00 00       	nop
+    1026:	00 00       	nop
+    1028:	00 00       	nop
+    102a:	00 00       	nop
+    102c:	00 00       	nop
+
+0000102e <main>:
+    102e:	00 00       	nop
+    1030:	00 00       	nop
+    1032:	c5 3c 10 12 	lb \$5,4114\(\$3\)
+    1036:	de e9 ff ff 	bsr 1012 <&:s3:foo:s3:bar>
+    103a:	e5 09 ff ec 	repeat \$5,1012 <&:s3:foo:s3:bar>
+    103e:	00 00       	nop
+    1040:	00 00       	nop
+    1042:	c5 3c ef ee 	lb \$5,-4114\(\$3\)
+    1046:	dd 49 ff df 	bsr ffffefee <0-:s3:foo>
+    104a:	e5 09 ef d2 	repeat \$5,ffffefee <0-:s3:foo>
+    104e:	00 00       	nop
+    1050:	00 00       	nop
+    1052:	c5 3c 20 2c 	lb \$5,8236\(\$3\)
+    1056:	de b9 00 0f 	bsr 202c <\+:s3:foo:s3:bar>
+    105a:	e5 09 07 e9 	repeat \$5,202c <\+:s3:foo:s3:bar>
+    105e:	dc 88 00 80 	jmp 8090 <<<:s3:foo:#00000003>
+    1062:	d8 18 00 02 	jmp 202 <>>:s3:foo:#00000003>
+    1066:	df c8 7f ff 	jmp 7ffff8 <&:-:s3:foo:s3:bar:#007fffff>
+    106a:	df 28 7f ff 	jmp 7fffe4 <&:-:s3:foo:s4:main:#007fffff>
+    106e:	df 78 7f ff 	jmp 7fffee <&:-:S5:.text:s3:foo:#007fffff>
+    1072:	dd 98 00 01 	jmp 1b2 <&:-:S5:.data:s3:foo:#007fffff>
+    1076:	da 98 00 0f 	jmp f52 <-:s3:foo:\+:s9:.text.end:0-:S5:.text>
+    107a:	db f8 00 70 	jmp 707e <\*:s3:foo:#00000007>
+    107e:	da 58 00 02 	jmp 24a <>>:s3:foo:#00000003\+0x48>
+    1082:	d8 28 00 00 	jmp 4 <__assert_based_size\+0x3>
+    1086:	d8 48 00 00 	jmp 8 <\^:s3:foo:s3:bar>
+    108a:	d8 d8 00 10 	jmp 101a <|:s3:foo:s3:bar>
+    108e:	d8 98 00 10 	jmp 1012 <&:s3:foo:s3:bar>
+    1092:	d8 08 00 00 	jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+    1096:	d9 08 00 00 	jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+    109a:	d9 08 00 00 	jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+    109e:	d8 08 00 00 	jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+    10a2:	d8 08 00 00 	jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+    10a6:	d9 08 00 00 	jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+    10aa:	d9 08 00 00 	jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+    10ae:	00 00       	nop
+    10b0:	00 00       	nop
+    10b2:	00 00       	nop
+    10b4:	00 00       	nop
+    10b6:	d8 08 00 00 	jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+    10ba:	00 00       	nop
+    10bc:	00 00       	nop
+    10be:	00 00       	nop
+#pass
diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
index 6f3660d4ca76..aa4c8a5e3d9c 100644
--- a/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
+++ b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d
@@ -8,27 +8,27 @@
 .*: +file format .*mips.*
 
 Disassembly of section .text:
-0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
-0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
-0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+0000 <[^>]*> 40800001 	mtc0	\$0,c0_mvpcontrol
+0+0004 <[^>]*> 40800002 	mtc0	\$0,c0_mvpconf0
+0+0008 <[^>]*> 40800003 	mtc0	\$0,c0_mvpconf1
 0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
 0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
 0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
 0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
-0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
-0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
-0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
-0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
-0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
-0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+001c <[^>]*> 40800801 	mtc0	\$0,c0_vpecontrol
+0+0020 <[^>]*> 40800802 	mtc0	\$0,c0_vpeconf0
+0+0024 <[^>]*> 40800803 	mtc0	\$0,c0_vpeconf1
+0+0028 <[^>]*> 40800804 	mtc0	\$0,c0_yqmask
+0+002c <[^>]*> 40800805 	mtc0	\$0,c0_vpeschedule
+0+0030 <[^>]*> 40800806 	mtc0	\$0,c0_vpeschefback
 0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
-0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
-0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
-0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
-0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
-0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
-0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
-0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,c0_tcstatus
+0+003c <[^>]*> 40801002 	mtc0	\$0,c0_tcbind
+0+0040 <[^>]*> 40801003 	mtc0	\$0,c0_tcrestart
+0+0044 <[^>]*> 40801004 	mtc0	\$0,c0_tchalt
+0+0048 <[^>]*> 40801005 	mtc0	\$0,c0_tccontext
+0+004c <[^>]*> 40801006 	mtc0	\$0,c0_tcschedule
+0+0050 <[^>]*> 40801007 	mtc0	\$0,c0_tcschefback
 0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
 0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
 0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
@@ -50,11 +50,11 @@ Disassembly of section .text:
 0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
 0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
 0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
-0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
-0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
-0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
-0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
-0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,c0_srsconf0
+0+00ac <[^>]*> 40803002 	mtc0	\$0,c0_srsconf1
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,c0_srsconf2
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,c0_srsconf3
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,c0_srsconf4
 0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
 0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
 0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d
index 9222800a67be..22aa180ee235 100644
--- a/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d
+++ b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d
@@ -8,27 +8,27 @@
 .*: +file format .*mips.*
 
 Disassembly of section .text:
-0+0000 <[^>]*> 40800001 	mtc0	\$0,\$0,1
-0+0004 <[^>]*> 40800002 	mtc0	\$0,\$0,2
-0+0008 <[^>]*> 40800003 	mtc0	\$0,\$0,3
+0+0000 <[^>]*> 40800001 	mtc0	\$0,c0_mvpcontrol
+0+0004 <[^>]*> 40800002 	mtc0	\$0,c0_mvpconf0
+0+0008 <[^>]*> 40800003 	mtc0	\$0,c0_mvpconf1
 0+000c <[^>]*> 40800004 	mtc0	\$0,\$0,4
 0+0010 <[^>]*> 40800005 	mtc0	\$0,\$0,5
 0+0014 <[^>]*> 40800006 	mtc0	\$0,\$0,6
 0+0018 <[^>]*> 40800007 	mtc0	\$0,\$0,7
-0+001c <[^>]*> 40800801 	mtc0	\$0,\$1,1
-0+0020 <[^>]*> 40800802 	mtc0	\$0,\$1,2
-0+0024 <[^>]*> 40800803 	mtc0	\$0,\$1,3
-0+0028 <[^>]*> 40800804 	mtc0	\$0,\$1,4
-0+002c <[^>]*> 40800805 	mtc0	\$0,\$1,5
-0+0030 <[^>]*> 40800806 	mtc0	\$0,\$1,6
+0+001c <[^>]*> 40800801 	mtc0	\$0,c0_vpecontrol
+0+0020 <[^>]*> 40800802 	mtc0	\$0,c0_vpeconf0
+0+0024 <[^>]*> 40800803 	mtc0	\$0,c0_vpeconf1
+0+0028 <[^>]*> 40800804 	mtc0	\$0,c0_yqmask
+0+002c <[^>]*> 40800805 	mtc0	\$0,c0_vpeschedule
+0+0030 <[^>]*> 40800806 	mtc0	\$0,c0_vpeschefback
 0+0034 <[^>]*> 40800807 	mtc0	\$0,\$1,7
-0+0038 <[^>]*> 40801001 	mtc0	\$0,\$2,1
-0+003c <[^>]*> 40801002 	mtc0	\$0,\$2,2
-0+0040 <[^>]*> 40801003 	mtc0	\$0,\$2,3
-0+0044 <[^>]*> 40801004 	mtc0	\$0,\$2,4
-0+0048 <[^>]*> 40801005 	mtc0	\$0,\$2,5
-0+004c <[^>]*> 40801006 	mtc0	\$0,\$2,6
-0+0050 <[^>]*> 40801007 	mtc0	\$0,\$2,7
+0+0038 <[^>]*> 40801001 	mtc0	\$0,c0_tcstatus
+0+003c <[^>]*> 40801002 	mtc0	\$0,c0_tcbind
+0+0040 <[^>]*> 40801003 	mtc0	\$0,c0_tcrestart
+0+0044 <[^>]*> 40801004 	mtc0	\$0,c0_tchalt
+0+0048 <[^>]*> 40801005 	mtc0	\$0,c0_tccontext
+0+004c <[^>]*> 40801006 	mtc0	\$0,c0_tcschedule
+0+0050 <[^>]*> 40801007 	mtc0	\$0,c0_tcschefback
 0+0054 <[^>]*> 40801801 	mtc0	\$0,\$3,1
 0+0058 <[^>]*> 40801802 	mtc0	\$0,\$3,2
 0+005c <[^>]*> 40801803 	mtc0	\$0,\$3,3
@@ -50,11 +50,11 @@ Disassembly of section .text:
 0+009c <[^>]*> 40802805 	mtc0	\$0,\$5,5
 0+00a0 <[^>]*> 40802806 	mtc0	\$0,\$5,6
 0+00a4 <[^>]*> 40802807 	mtc0	\$0,\$5,7
-0+00a8 <[^>]*> 40803001 	mtc0	\$0,\$6,1
-0+00ac <[^>]*> 40803002 	mtc0	\$0,\$6,2
-0+00b0 <[^>]*> 40803003 	mtc0	\$0,\$6,3
-0+00b4 <[^>]*> 40803004 	mtc0	\$0,\$6,4
-0+00b8 <[^>]*> 40803005 	mtc0	\$0,\$6,5
+0+00a8 <[^>]*> 40803001 	mtc0	\$0,c0_srsconf0
+0+00ac <[^>]*> 40803002 	mtc0	\$0,c0_srsconf1
+0+00b0 <[^>]*> 40803003 	mtc0	\$0,c0_srsconf2
+0+00b4 <[^>]*> 40803004 	mtc0	\$0,c0_srsconf3
+0+00b8 <[^>]*> 40803005 	mtc0	\$0,c0_srsconf4
 0+00bc <[^>]*> 40803006 	mtc0	\$0,\$6,6
 0+00c0 <[^>]*> 40803007 	mtc0	\$0,\$6,7
 0+00c4 <[^>]*> 40803801 	mtc0	\$0,\$7,1
diff --git a/gas/testsuite/gas/mips/e32-rel2.d b/gas/testsuite/gas/mips/e32-rel2.d
index 3983c7fd6f91..a43fd33059a5 100644
--- a/gas/testsuite/gas/mips/e32-rel2.d
+++ b/gas/testsuite/gas/mips/e32-rel2.d
@@ -1,5 +1,6 @@
 #objdump: -sr -j .text
 #name: MIPS ELF reloc 2 (32-bit)
+#as: -mabi=32
 #source: elf-rel2.s
 
 # Test the GPREL and LITERAL generation.
diff --git a/gas/testsuite/gas/mips/e32-rel4.d b/gas/testsuite/gas/mips/e32-rel4.d
index 81ae4e7fc1b2..35deea45efca 100644
--- a/gas/testsuite/gas/mips/e32-rel4.d
+++ b/gas/testsuite/gas/mips/e32-rel4.d
@@ -1,5 +1,6 @@
 #objdump: --prefix-addresses -dr
-#name: MIPS ELF reloc 4
+#name: MIPS ELF reloc 4 (32-bit)
+#as: -mabi=32
 #source: elf-rel4.s
 
 .*: +file format.*
diff --git a/gas/testsuite/gas/mips/elf-rel26.d b/gas/testsuite/gas/mips/elf-rel26.d
new file mode 100644
index 000000000000..d176acbf52c2
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel26.d
@@ -0,0 +1,22 @@
+#as: -mips32 -EL -KPIC
+#readelf: --relocs
+#name: MIPS ELF reloc 26
+
+Relocation section '\.rel\.pdr' .*
+ *Offset.*
+00.*
+
+Relocation section '\.rel\.text\.foo' at offset .* contains 11 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name
+0+000 * .+ * R_MIPS_HI16 * 0+0 * _gp_disp
+0+004 * .+ * R_MIPS_LO16 * 0+0 * _gp_disp
+0+014 * .+ * R_MIPS_GOT16 * 0+0 * \$LC28
+0+01c * .+ * R_MIPS_LO16 * 0+0 * \$LC28
+0+020 * .+ * R_MIPS_CALL16 * 0+0 * bar
+0+030 * .+ * R_MIPS_PC16 * 0+0 * \$L846
+0+034 * .+ * R_MIPS_GOT16 * 0+0 * \$LC27
+0+038 * .+ * R_MIPS_PC16 * 0+0 * \$L848
+0+048 * .+ * R_MIPS_PC16 * 0+0 * \$L925
+0+010 * .+ * R_MIPS_GOT16 * 0+0 * \.rodata\.foo
+0+05c * .+ * R_MIPS_LO16 * 0+0 * \.rodata\.foo
+#pass
diff --git a/gas/testsuite/gas/mips/elf-rel26.s b/gas/testsuite/gas/mips/elf-rel26.s
new file mode 100644
index 000000000000..ed6984a169e0
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel26.s
@@ -0,0 +1,62 @@
+	.section	.text.foo,"axG",@progbits,foo,comdat
+	.align	2
+	.weak	foo
+	.ent	foo
+	.type	foo, @function
+foo:
+$LFB308:
+	.frame	$fp,136,$31		# vars= 72, regs= 10/0, args= 16, gp= 8
+	.mask	0xc0ff0000,-4
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload	$25
+
+	.set	nomacro
+	bne	$3,$0,$L924
+	lw	$25,%got($L874)($28)
+	.set	macro
+	.set	reorder
+	lw	$5,%got($LC28)($28)
+	lw	$4,136($fp)
+	addiu	$5,$5,%lo($LC28)
+	lw	$25,%call16(bar)($28)
+	.set	noreorder
+	.set	nomacro
+	jalr	$25
+	li	$6,-1			# 0xffffffffffffffff
+	.set	macro
+	.set	reorder
+	lw	$25,64($fp)
+	.set	noreorder
+	.set	nomacro
+	bne	$25,$0,$L846
+	lw	$5,%got($LC27)($28)
+	b	$L848
+	sw	$0,68($fp)
+	.set	macro
+	.set	reorder
+$L920:
+	lb	$3,0($18)
+	li	$2,59			# 0x3b
+	.set	noreorder
+	.set	nomacro
+	beq	$3,$2,$L925
+	lw	$25,76($fp)
+	b	$L920
+	addiu	$18,$18,1
+	.set	macro
+	.set	reorder
+
+$L924:
+	sll	$2,$2,2
+	addiu	$25,$25,%lo($L874)
+	addu	$2,$2,$25
+	lw	$3,0($2)
+	addu	$3,$3,$28
+	j	$3
+	.end foo
+	.section	.rodata.foo,"aG",@progbits,foo,comdat
+	.align	2
+	.align	2
+$L874:
+	.gpword	$L924
diff --git a/gas/testsuite/gas/mips/elf-rel6-n32.d b/gas/testsuite/gas/mips/elf-rel6-n32.d
new file mode 100644
index 000000000000..258fcf656b67
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel6-n32.d
@@ -0,0 +1,16 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS ELF reloc 6 n32
+#as: -mabi=n32 -march=mips64
+#source: elf-rel6.s
+
+.*: +file format elf.*mips.*
+
+Disassembly of section \.text:
+0+00 <.*> lb	v0,0\(v1\)
+			0: R_MIPS16_GPREL	bar
+0+04 <.*> lb	v0,0\(v1\)
+			4: R_MIPS16_GPREL	bar\+0x1
+0+08 <.*> lb	v0,0\(v1\)
+			8: R_MIPS16_GPREL	bar\+0x1234
+0+0c <[^>]*> nop
+0+0e <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/elf-rel6-n64.d b/gas/testsuite/gas/mips/elf-rel6-n64.d
new file mode 100644
index 000000000000..d65b10ab3133
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel6-n64.d
@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS ELF reloc 6 n64
+#as: -mabi=64 -march=mips64
+#source: elf-rel6.s
+
+.*: +file format elf.*mips.*
+
+Disassembly of section \.text:
+0+00 <.*> lb	v0,0\(v1\)
+			0: R_MIPS16_GPREL	bar
+			0: R_MIPS_NONE	\*ABS\*
+			0: R_MIPS_NONE	\*ABS\*
+0+04 <.*> lb	v0,0\(v1\)
+			4: R_MIPS16_GPREL	bar\+0x1
+			4: R_MIPS_NONE	\*ABS\*\+0x1
+			4: R_MIPS_NONE	\*ABS\*\+0x1
+0+08 <.*> lb	v0,0\(v1\)
+			8: R_MIPS16_GPREL	bar\+0x1234
+			8: R_MIPS_NONE	\*ABS\*\+0x1234
+			8: R_MIPS_NONE	\*ABS\*\+0x1234
+0+0c <[^>]*> nop
+0+0e <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/elf-rel6.d b/gas/testsuite/gas/mips/elf-rel6.d
index 85efe9d0aed0..cea8d7fd81b9 100644
--- a/gas/testsuite/gas/mips/elf-rel6.d
+++ b/gas/testsuite/gas/mips/elf-rel6.d
@@ -9,7 +9,7 @@ Disassembly of section \.text:
 			0: R_MIPS16_GPREL	bar
 0+04 <.*> lb	v0,1\(v1\)
 			4: R_MIPS16_GPREL	bar
-0+08 <[^>]*> nop
-0+0a <[^>]*> nop
+0+08 <.*> lb	v0,4660\(v1\)
+			8: R_MIPS16_GPREL	bar
 0+0c <[^>]*> nop
 0+0e <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/elf-rel6.s b/gas/testsuite/gas/mips/elf-rel6.s
index 6735d7555fad..34c3a84b6ff8 100644
--- a/gas/testsuite/gas/mips/elf-rel6.s
+++ b/gas/testsuite/gas/mips/elf-rel6.s
@@ -13,6 +13,7 @@ bar:	.byte	3
 f:
 	lb	$2,%gprel(bar)($3)
 	lb	$2,%gprel(bar+1)($3)
+	lb	$2,%gprel(bar+0x1234)($3)
 	.end	f
 
 # align section end to 16-byte boundary for easier testing on multiple targets
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
index 52c1701bd411..3ebbe3f4cf4c 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
@@ -1,6 +1,7 @@
 #objdump: -d -mmips:8000
 #as: -32 -march=8000 -EB -mgp32 -mfp64 -KPIC
 #name: MIPS -mgp32 -mfp64 (SVR4 PIC)
+#stderr: mips-gp32-fp64.l
 
 .*: +file format.*
 
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.d b/gas/testsuite/gas/mips/mips-gp32-fp64.d
index b266f702f6d4..8fcd56380fa8 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp64.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64.d
@@ -1,6 +1,7 @@
 #objdump: -d -mmips:8000
 #as: -32 -march=8000 -EB -mgp32 -mfp64
 #name: MIPS -mgp32 -mfp64
+#stderr: mips-gp32-fp64.l
 
 .*: +file format.*
 
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.l b/gas/testsuite/gas/mips/mips-gp32-fp64.l
new file mode 100644
index 000000000000..de3f3b06ce28
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64.l
@@ -0,0 +1,2 @@
+Assembler messages:
+Warning: -mfp64 used with a 32-bit ABI
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
index f5a8e8963942..52fe8afd013a 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
@@ -1,6 +1,7 @@
 #objdump: -d -mmips:8000
 #as: -mabi=o64 -march=8000 -EB -mfp32 -KPIC
 #name: MIPS -mgp64 -mfp32 (SVR4 PIC)
+#stderr: mips-gp64-fp32-pic.l
 
 .*: +file format.*
 
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l
new file mode 100644
index 000000000000..2d3730301237
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l
@@ -0,0 +1,2 @@
+Assembler messages:
+Warning: -mfp32 used with a 64-bit ABI
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32.l b/gas/testsuite/gas/mips/mips-gp64-fp32.l
index 4f26b42dce1a..3668a25e3b20 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp32.l
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32.l
@@ -1,4 +1,5 @@
-.*: Assembler messages:
+Assembler messages:
+Warning: -mfp32 used with a 64-bit ABI
 .*:92: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
 .*:96: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
 .*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp64.d b/gas/testsuite/gas/mips/mips-gp64-fp64.d
index bf3e44f84f0e..3e1bfd5d5b8e 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp64.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp64.d
@@ -1,7 +1,7 @@
 #objdump: -d -mmips:8000
 #as: -mabi=o64 -march=8000 -EB
 #name: MIPS -mgp64 -mfp64
-#stderr: mips-gp64-fp32.l
+#stderr: mips-gp64-fp64.l
 
 .*: +file format.*
 
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 7843f2a9742b..523a7738242a 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -292,27 +292,6 @@ proc run_dump_test_arches { name arch_list } {
     }
 }
 
-# run_list_test NAME OPTS (optional): TESTNAME
-#
-# Assemble the file "NAME.d" and compare the assembler standard error
-# output against the regular expressions given in the file "NAME.l".
-# The assembler is passed the flags given in OPTS.  If TESTNAME is
-# provided, it will be used as the name of the test.
-proc run_list_test { name opts {testname {}} } {
-    global srcdir subdir
-    if { [string length $testname] == 0 } then {
-	    set testname "MIPS $name"
-    }
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 # run_list_test_arch NAME OPTS ARCH
 #
 # Invoke "run_list_test" for test NAME with options OPTS, with extra
@@ -390,6 +369,8 @@ mips_arch_create sb1 	64	mips64	{ mips3d } \
 if { [istarget mips*-*-vxworks*] } {
     run_dump_test "vxworks1"
     run_dump_test "vxworks1-xgot"
+    run_dump_test "vxworks1-el"
+    run_dump_test "vxworks1-xgot-el"
 } elseif { [istarget mips*-*-*] } {
     set no_mips16 0
     set elf [expr [istarget *-*-elf*] || [istarget *-*-irix5*] || [istarget *-*-irix6* ] || [istarget *-*-linux*] || [istarget *-*-netbsd*] ]
@@ -400,7 +381,7 @@ if { [istarget mips*-*-vxworks*] } {
     set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*]]
     set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
 
-    if { [istarget "mips*-*-*linux*"] } then {
+    if { [istarget "mips*-*-*linux*"] || [istarget "mips*-sde-elf*"] } then {
 	set tmips "t"
     } else {
 	set tmips ""
@@ -531,6 +512,8 @@ if { [istarget mips*-*-vxworks*] } {
     if { $elf && !$no_mips16 } {
 	run_dump_test "mips16"
 	run_dump_test "mips16-64"
+	# Check MIPS16e extensions
+	run_dump_test_arches "mips16e" 	[mips_arch_list_matching mips32]
 	# Check jalx handling
 	run_dump_test "mips16-jalx"
 	run_dump_test "mips-jalx"
@@ -559,6 +542,8 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_dump_test_arches "mips32"	[mips_arch_list_matching mips32]
 
+    run_dump_test_arches "mips32-sf32"	[mips_arch_list_matching mips32]
+
     run_dump_test_arches "mips32r2"	[mips_arch_list_matching mips32r2]
     run_list_test_arches "mips32r2-ill" "-32" \
 			 [mips_arch_list_matching mips32r2 gpr32]
@@ -633,20 +618,17 @@ if { [istarget mips*-*-vxworks*] } {
   	run_dump_test "mips-abi32-pic2"
 
 	run_dump_test "elf${el}-rel"
-	if {[istarget mips64*-*-*] || [istarget mipsisa32*-*-*]
-	    || [istarget mipsisa64*-*-*]} { 
-	    run_dump_test "elf${el}-rel2"
-	} else {
-	    run_dump_test "e32${el}-rel2"
-	}
+	run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64]
+	run_dump_test "e32${el}-rel2"
 	run_dump_test "elf${el}-rel3"
-	if {[istarget mips64*-*-*]} {
-	    run_dump_test "elf-rel4"
-	} else {
-	    run_dump_test "e32-rel4"
-	}
+	run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64]
+	run_dump_test "e32-rel4"
 	run_dump_test "elf-rel5"
 	run_dump_test "elf-rel6"
+	if $has_newabi {
+	    run_dump_test "elf-rel6-n32"
+	    run_dump_test "elf-rel6-n64"
+	}
 	run_dump_test "elf-rel7"
 	run_dump_test "elf-rel8"
 	run_dump_test "elf-rel9"
@@ -684,6 +666,7 @@ if { [istarget mips*-*-vxworks*] } {
 
 	run_dump_test "elf-rel25"
 	run_dump_test "elf-rel25a"
+	run_dump_test "elf-rel26"
 
 	if { !$no_mips16 } {
 	    run_dump_test "${tmips}mips${el}16-e"
@@ -766,7 +749,10 @@ if { [istarget mips*-*-vxworks*] } {
     run_list_test "noat-6" ""
     run_list_test "noat-7" ""
 
-    run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32 !sb1]
+    run_dump_test_arches "smartmips"	[mips_arch_list_matching mips32 !gpr64]
+    run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "mips32-dspr2"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "mips64-dsp"	[mips_arch_list_matching mips64r2]
     run_dump_test_arches "mips32-mt"	[mips_arch_list_matching mips32r2 !gpr64]
 
     if { $elf && !$no_mips16 } {
@@ -778,7 +764,14 @@ if { [istarget mips*-*-vxworks*] } {
     if { !$no_mips16 } { 
         run_dump_test "mips16e-jrc"
         run_dump_test "mips16e-save"
+        run_dump_test "mips16e-64"
+        run_list_test "mips16e-64" "-march=mips32 -32"
+        run_dump_test "mips16-intermix"
     }
     run_dump_test "vxworks1"
     run_dump_test "vxworks1-xgot"
+    run_dump_test "vxworks1-el"
+    run_dump_test "vxworks1-xgot-el"
+
+    run_dump_test "noreorder"
 }
diff --git a/gas/testsuite/gas/mips/mips16-intermix.d b/gas/testsuite/gas/mips/mips16-intermix.d
new file mode 100644
index 000000000000..9b541eefebcf
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-intermix.d
@@ -0,0 +1,164 @@
+#objdump: -t
+#as: -mips32r2
+#name: MIPS16 intermix
+
+.*: +file format .*mips.*
+
+SYMBOL TABLE:
+#...
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_l
+0+[0-9a-f]+ l    d  .mips16.fn.m16_d	0+[0-9a-f]+ .mips16.fn.m16_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_d	0+[0-9a-f]+ __fn_stub_m16_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static_d	0+[0-9a-f]+ .mips16.fn.m16_static_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static_d	0+[0-9a-f]+ __fn_stub_m16_static_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static1_d	0+[0-9a-f]+ .mips16.fn.m16_static1_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static1_d	0+[0-9a-f]+ __fn_stub_m16_static1_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static32_d	0+[0-9a-f]+ .mips16.fn.m16_static32_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static32_d	0+[0-9a-f]+ __fn_stub_m16_static32_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static16_d	0+[0-9a-f]+ .mips16.fn.m16_static16_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static16_d	0+[0-9a-f]+ __fn_stub_m16_static16_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_ld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_ld
+0+[0-9a-f]+ l    d  .mips16.fn.m16_dl	0+[0-9a-f]+ .mips16.fn.m16_dl
+0+[0-9a-f]+ l     F .mips16.fn.m16_dl	0+[0-9a-f]+ __fn_stub_m16_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dl
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static_dl	0+[0-9a-f]+ .mips16.fn.m16_static_dl
+0+[0-9a-f]+ l     F .mips16.fn.m16_static_dl	0+[0-9a-f]+ __fn_stub_m16_static_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dl
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static1_dl	0+[0-9a-f]+ .mips16.fn.m16_static1_dl
+0+[0-9a-f]+ l     F .mips16.fn.m16_static1_dl	0+[0-9a-f]+ __fn_stub_m16_static1_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dl
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static32_dl	0+[0-9a-f]+ .mips16.fn.m16_static32_dl
+0+[0-9a-f]+ l     F .mips16.fn.m16_static32_dl	0+[0-9a-f]+ __fn_stub_m16_static32_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_dl
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dl
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static16_dl	0+[0-9a-f]+ .mips16.fn.m16_static16_dl
+0+[0-9a-f]+ l     F .mips16.fn.m16_static16_dl	0+[0-9a-f]+ __fn_stub_m16_static16_dl
+0+[0-9a-f]+ l    d  .mips16.fn.m16_dlld	0+[0-9a-f]+ .mips16.fn.m16_dlld
+0+[0-9a-f]+ l     F .mips16.fn.m16_dlld	0+[0-9a-f]+ __fn_stub_m16_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dlld
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static_dlld	0+[0-9a-f]+ .mips16.fn.m16_static_dlld
+0+[0-9a-f]+ l     F .mips16.fn.m16_static_dlld	0+[0-9a-f]+ __fn_stub_m16_static_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dlld
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static1_dlld	0+[0-9a-f]+ .mips16.fn.m16_static1_dlld
+0+[0-9a-f]+ l     F .mips16.fn.m16_static1_dlld	0+[0-9a-f]+ __fn_stub_m16_static1_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dlld
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static32_dlld	0+[0-9a-f]+ .mips16.fn.m16_static32_dlld
+0+[0-9a-f]+ l     F .mips16.fn.m16_static32_dlld	0+[0-9a-f]+ __fn_stub_m16_static32_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dlld
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static16_dlld	0+[0-9a-f]+ .mips16.fn.m16_static16_dlld
+0+[0-9a-f]+ l     F .mips16.fn.m16_static16_dlld	0+[0-9a-f]+ __fn_stub_m16_static16_dlld
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_d_l
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_l
+0+[0-9a-f]+ l    d  .mips16.fn.m16_d_d	0+[0-9a-f]+ .mips16.fn.m16_d_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_d_d	0+[0-9a-f]+ __fn_stub_m16_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static_d_d	0+[0-9a-f]+ .mips16.fn.m16_static_d_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static_d_d	0+[0-9a-f]+ __fn_stub_m16_static_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static1_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static1_d_d	0+[0-9a-f]+ .mips16.fn.m16_static1_d_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static1_d_d	0+[0-9a-f]+ __fn_stub_m16_static1_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static32_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static32_d_d	0+[0-9a-f]+ .mips16.fn.m16_static32_d_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static32_d_d	0+[0-9a-f]+ __fn_stub_m16_static32_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ m32_static16_d_d
+0+[0-9a-f]+ l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_d
+0+[0-9a-f]+ l    d  .mips16.fn.m16_static16_d_d	0+[0-9a-f]+ .mips16.fn.m16_static16_d_d
+0+[0-9a-f]+ l     F .mips16.fn.m16_static16_d_d	0+[0-9a-f]+ __fn_stub_m16_static16_d_d
+0+[0-9a-f]+ l    d  .mips16.call.m32_static1_d	0+[0-9a-f]+ .mips16.call.m32_static1_d
+0+[0-9a-f]+ l     F .mips16.call.m32_static1_d	0+[0-9a-f]+ __call_stub_m32_static1_d
+0+[0-9a-f]+ l    d  .mips16.call.m16_static1_d	0+[0-9a-f]+ .mips16.call.m16_static1_d
+0+[0-9a-f]+ l     F .mips16.call.m16_static1_d	0+[0-9a-f]+ __call_stub_m16_static1_d
+0+[0-9a-f]+ l    d  .mips16.call.m32_static1_dl	0+[0-9a-f]+ .mips16.call.m32_static1_dl
+0+[0-9a-f]+ l     F .mips16.call.m32_static1_dl	0+[0-9a-f]+ __call_stub_m32_static1_dl
+0+[0-9a-f]+ l    d  .mips16.call.m16_static1_dl	0+[0-9a-f]+ .mips16.call.m16_static1_dl
+0+[0-9a-f]+ l     F .mips16.call.m16_static1_dl	0+[0-9a-f]+ __call_stub_m16_static1_dl
+0+[0-9a-f]+ l    d  .mips16.call.m32_static1_dlld	0+[0-9a-f]+ .mips16.call.m32_static1_dlld
+0+[0-9a-f]+ l     F .mips16.call.m32_static1_dlld	0+[0-9a-f]+ __call_stub_m32_static1_dlld
+0+[0-9a-f]+ l    d  .mips16.call.m16_static1_dlld	0+[0-9a-f]+ .mips16.call.m16_static1_dlld
+0+[0-9a-f]+ l     F .mips16.call.m16_static1_dlld	0+[0-9a-f]+ __call_stub_m16_static1_dlld
+0+[0-9a-f]+ l    d  .mips16.call.fp.m32_static1_d_l	0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_l
+0+[0-9a-f]+ l     F .mips16.call.fp.m32_static1_d_l	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l
+0+[0-9a-f]+ l    d  .mips16.call.fp.m16_static1_d_l	0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_l
+0+[0-9a-f]+ l     F .mips16.call.fp.m16_static1_d_l	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l
+0+[0-9a-f]+ l    d  .mips16.call.fp.m32_static1_d_d	0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_d
+0+[0-9a-f]+ l     F .mips16.call.fp.m32_static1_d_d	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d
+0+[0-9a-f]+ l    d  .mips16.call.fp.m16_static1_d_d	0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_d
+0+[0-9a-f]+ l     F .mips16.call.fp.m16_static1_d_d	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d
+0+[0-9a-f]+ l    d  .mips16.call.m32_static16_d	0+[0-9a-f]+ .mips16.call.m32_static16_d
+0+[0-9a-f]+ l     F .mips16.call.m32_static16_d	0+[0-9a-f]+ __call_stub_m32_static16_d
+0+[0-9a-f]+ l    d  .mips16.call.m16_static16_d	0+[0-9a-f]+ .mips16.call.m16_static16_d
+0+[0-9a-f]+ l     F .mips16.call.m16_static16_d	0+[0-9a-f]+ __call_stub_m16_static16_d
+0+[0-9a-f]+ l    d  .mips16.call.m32_static16_dl	0+[0-9a-f]+ .mips16.call.m32_static16_dl
+0+[0-9a-f]+ l     F .mips16.call.m32_static16_dl	0+[0-9a-f]+ __call_stub_m32_static16_dl
+0+[0-9a-f]+ l    d  .mips16.call.m16_static16_dl	0+[0-9a-f]+ .mips16.call.m16_static16_dl
+0+[0-9a-f]+ l     F .mips16.call.m16_static16_dl	0+[0-9a-f]+ __call_stub_m16_static16_dl
+0+[0-9a-f]+ l    d  .mips16.call.m32_static16_dlld	0+[0-9a-f]+ .mips16.call.m32_static16_dlld
+0+[0-9a-f]+ l     F .mips16.call.m32_static16_dlld	0+[0-9a-f]+ __call_stub_m32_static16_dlld
+0+[0-9a-f]+ l    d  .mips16.call.m16_static16_dlld	0+[0-9a-f]+ .mips16.call.m16_static16_dlld
+0+[0-9a-f]+ l     F .mips16.call.m16_static16_dlld	0+[0-9a-f]+ __call_stub_m16_static16_dlld
+0+[0-9a-f]+ l    d  .mips16.call.fp.m32_static16_d_l	0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_l
+0+[0-9a-f]+ l     F .mips16.call.fp.m32_static16_d_l	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l
+0+[0-9a-f]+ l    d  .mips16.call.fp.m16_static16_d_l	0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_l
+0+[0-9a-f]+ l     F .mips16.call.fp.m16_static16_d_l	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l
+0+[0-9a-f]+ l    d  .mips16.call.fp.m32_static16_d_d	0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_d
+0+[0-9a-f]+ l     F .mips16.call.fp.m32_static16_d_d	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d
+0+[0-9a-f]+ l    d  .mips16.call.fp.m16_static16_d_d	0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_d
+0+[0-9a-f]+ l     F .mips16.call.fp.m16_static16_d_d	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d
+#...
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_l
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_l
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_d
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_d
+#...
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_ld
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_ld
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_dl
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_dl
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_dlld
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_dlld
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_d_l
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_d_l
+#...
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ m32_d_d
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 m16_d_d
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ f32
+0+[0-9a-f]+ g     F .text	0+[0-9a-f]+ 0xf0 f16
+#pass
diff --git a/gas/testsuite/gas/mips/mips16-intermix.s b/gas/testsuite/gas/mips/mips16-intermix.s
new file mode 100644
index 000000000000..49b0cc97668e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-intermix.s
@@ -0,0 +1,2631 @@
+	.text
+	.align	2
+	.globl	m32_l
+	.set	nomips16
+	.ent	m32_l
+m32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_l
+
+	.align	2
+	.globl	m16_l
+	.set	mips16
+	.ent	m16_l
+m16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_l
+m32_static_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_l
+m16_static_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_l
+m32_static1_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_l
+m16_static1_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static1_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_l
+m32_static32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_l
+m16_static32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static32_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_l
+m32_static16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_l
+m16_static16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static16_l
+
+	.align	2
+	.globl	m32_d
+	.set	nomips16
+	.ent	m32_d
+m32_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_d
+
+	.align	2
+	.globl	m16_d
+	.set	mips16
+	.ent	m16_d
+m16_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_d
+	# Stub function for m16_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_d
+__fn_stub_m16_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d
+m32_static_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d
+m16_static_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static_d
+	# Stub function for m16_static_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_d
+__fn_stub_m16_static_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d
+m32_static1_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d
+m16_static1_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static1_d
+	# Stub function for m16_static1_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_d
+__fn_stub_m16_static1_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d
+m32_static32_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d
+m16_static32_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static32_d
+	# Stub function for m16_static32_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_d
+__fn_stub_m16_static32_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d
+m32_static16_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d
+m16_static16_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static16_d
+	# Stub function for m16_static16_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_d
+__fn_stub_m16_static16_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_d
+	.previous
+
+	.align	2
+	.globl	m32_ld
+	.set	nomips16
+	.ent	m32_ld
+m32_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_ld
+
+	.align	2
+	.globl	m16_ld
+	.set	mips16
+	.ent	m16_ld
+m16_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_ld
+m32_static_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_ld
+m16_static_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_ld
+m32_static1_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_ld
+m16_static1_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static1_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_ld
+m32_static32_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_ld
+m16_static32_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static32_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_ld
+m32_static16_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_ld
+m16_static16_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static16_ld
+
+	.align	2
+	.globl	m32_dl
+	.set	nomips16
+	.ent	m32_dl
+m32_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_dl
+
+	.align	2
+	.globl	m16_dl
+	.set	mips16
+	.ent	m16_dl
+m16_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_dl
+	# Stub function for m16_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_dl
+__fn_stub_m16_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_dl
+m32_static_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_dl
+m16_static_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static_dl
+	# Stub function for m16_static_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_dl
+__fn_stub_m16_static_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_dl
+m32_static1_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_dl
+m16_static1_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static1_dl
+	# Stub function for m16_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_dl
+__fn_stub_m16_static1_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_dl
+m32_static32_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_dl
+m16_static32_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static32_dl
+	# Stub function for m16_static32_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_dl
+__fn_stub_m16_static32_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_dl
+m32_static16_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_dl
+m16_static16_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static16_dl
+	# Stub function for m16_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_dl
+__fn_stub_m16_static16_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_dl
+	.previous
+
+	.align	2
+	.globl	m32_dlld
+	.set	nomips16
+	.ent	m32_dlld
+m32_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_dlld
+
+	.align	2
+	.globl	m16_dlld
+	.set	mips16
+	.ent	m16_dlld
+m16_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_dlld
+	# Stub function for m16_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_dlld
+__fn_stub_m16_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_dlld
+m32_static_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_dlld
+m16_static_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static_dlld
+	# Stub function for m16_static_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_dlld
+__fn_stub_m16_static_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_dlld
+m32_static1_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_dlld
+m16_static1_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static1_dlld
+	# Stub function for m16_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_dlld
+__fn_stub_m16_static1_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_dlld
+m32_static32_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_dlld
+m16_static32_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static32_dlld
+	# Stub function for m16_static32_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_dlld
+__fn_stub_m16_static32_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_dlld
+m32_static16_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_dlld
+m16_static16_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static16_dlld
+	# Stub function for m16_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_dlld
+__fn_stub_m16_static16_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_dlld
+	.previous
+
+	.align	2
+	.globl	m32_d_l
+	.set	nomips16
+	.ent	m32_d_l
+m32_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_d_l
+
+	.align	2
+	.globl	m16_d_l
+	.set	mips16
+	.ent	m16_d_l
+m16_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_floatsidf
+	jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d_l
+m32_static_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d_l
+m16_static_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_floatsidf
+	jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d_l
+m32_static1_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d_l
+m16_static1_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_floatsidf
+	jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static1_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d_l
+m32_static32_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d_l
+m16_static32_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_floatsidf
+	jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static32_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d_l
+m32_static16_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d_l
+m16_static16_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	jal	__mips16_floatsidf
+	jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static16_d_l
+
+	.align	2
+	.globl	m32_d_d
+	.set	nomips16
+	.ent	m32_d_d
+m32_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_d_d
+
+	.align	2
+	.globl	m16_d_d
+	.set	mips16
+	.ent	m16_d_d
+m16_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_d_d
+	# Stub function for m16_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_d_d
+__fn_stub_m16_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d_d
+m32_static_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d_d
+m16_static_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static_d_d
+	# Stub function for m16_static_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_d_d
+__fn_stub_m16_static_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d_d
+m32_static1_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d_d
+m16_static1_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static1_d_d
+	# Stub function for m16_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_d_d
+__fn_stub_m16_static1_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d_d
+m32_static32_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d_d
+m16_static32_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static32_d_d
+	# Stub function for m16_static32_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_d_d
+__fn_stub_m16_static32_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d_d
+m32_static16_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d_d
+m16_static16_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static16_d_d
+	# Stub function for m16_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_d_d
+__fn_stub_m16_static16_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_d_d
+	.previous
+
+	.align	2
+	.globl	f32
+	.set	nomips16
+	.ent	f32
+f32:
+	.frame	$sp,64,$31		# vars= 0, regs= 3/3, args= 24, gp= 0
+	.mask	0x80030000,-32
+	.fmask	0x03f00000,-8
+	.set	noreorder
+	.set	nomacro
+	
+	addiu	$sp,$sp,-64
+	sw	$17,28($sp)
+	move	$17,$4
+	sw	$31,32($sp)
+	sdc1	$f24,56($sp)
+	sw	$16,24($sp)
+	sdc1	$f22,48($sp)
+	sdc1	$f20,40($sp)
+	mtc1	$7,$f22
+	jal	m32_static1_l
+	mtc1	$6,$f23
+
+	move	$4,$17
+	jal	m16_static1_l
+	move	$16,$2
+
+	addu	$16,$16,$2
+	jal	m32_static1_d
+	mov.d	$f12,$f22
+
+	addu	$16,$16,$2
+	jal	m16_static1_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m32_static1_ld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m16_static1_ld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m32_static1_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m16_static1_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	sdc1	$f22,16($sp)
+	mov.d	$f12,$f22
+	jal	m32_static1_dlld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	mov.d	$f12,$f22
+	sdc1	$f22,16($sp)
+	jal	m16_static1_dlld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m32_static1_d_l
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m16_static1_d_l
+	mov.d	$f20,$f0
+
+	add.d	$f20,$f20,$f0
+	jal	m32_static1_d_d
+	mov.d	$f12,$f22
+
+	add.d	$f20,$f20,$f0
+	jal	m16_static1_d_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	jal	m32_static32_l
+	add.d	$f20,$f20,$f0
+
+	move	$4,$17
+	jal	m16_static32_l
+	addu	$16,$16,$2
+
+	addu	$16,$16,$2
+	jal	m32_static32_d
+	mov.d	$f12,$f22
+
+	addu	$16,$16,$2
+	jal	m16_static32_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m32_static32_ld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m16_static32_ld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m32_static32_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m16_static32_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	sdc1	$f22,16($sp)
+	mov.d	$f12,$f22
+	jal	m32_static32_dlld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	mov.d	$f12,$f22
+	sdc1	$f22,16($sp)
+	jal	m16_static32_dlld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m32_static32_d_l
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m16_static32_d_l
+	add.d	$f20,$f20,$f0
+
+	add.d	$f20,$f20,$f0
+	jal	m32_static32_d_d
+	mov.d	$f12,$f22
+
+	mtc1	$16,$f24
+	add.d	$f20,$f20,$f0
+	jal	m16_static32_d_d
+	mov.d	$f12,$f22
+
+	lw	$31,32($sp)
+	lw	$17,28($sp)
+	lw	$16,24($sp)
+	add.d	$f20,$f20,$f0
+	ldc1	$f22,48($sp)
+	cvt.d.w	$f0,$f24
+	ldc1	$f24,56($sp)
+	add.d	$f0,$f0,$f20
+	ldc1	$f20,40($sp)
+	j	$31
+	addiu	$sp,$sp,64
+
+	.set	macro
+	.set	reorder
+	.end	f32
+
+	# Stub function to call m32_static1_d (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_d
+__call_stub_m32_static1_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_d
+	.previous
+
+	# Stub function to call m16_static1_d (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_d
+__call_stub_m16_static1_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_d
+	.previous
+
+	# Stub function to call m32_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_dl
+__call_stub_m32_static1_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_dl
+	.previous
+
+	# Stub function to call m16_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_dl
+__call_stub_m16_static1_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_dl
+	.previous
+
+	# Stub function to call m32_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_dlld
+__call_stub_m32_static1_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_dlld
+	.previous
+
+	# Stub function to call m16_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_dlld
+__call_stub_m16_static1_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_dlld
+	.previous
+
+	# Stub function to call double m32_static1_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static1_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static1_d_l
+__call_stub_fp_m32_static1_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m32_static1_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static1_d_l
+	.previous
+
+	# Stub function to call double m16_static1_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static1_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static1_d_l
+__call_stub_fp_m16_static1_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m16_static1_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static1_d_l
+	.previous
+
+	# Stub function to call double m32_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static1_d_d
+__call_stub_fp_m32_static1_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m32_static1_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static1_d_d
+	.previous
+
+	# Stub function to call double m16_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static1_d_d
+__call_stub_fp_m16_static1_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m16_static1_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static1_d_d
+	.previous
+
+	# Stub function to call m32_static16_d (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_d
+__call_stub_m32_static16_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_d
+	.previous
+
+	# Stub function to call m16_static16_d (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_d
+__call_stub_m16_static16_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_d
+	.previous
+
+	# Stub function to call m32_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_dl
+__call_stub_m32_static16_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_dl
+	.previous
+
+	# Stub function to call m16_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_dl
+__call_stub_m16_static16_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_dl
+	.previous
+
+	# Stub function to call m32_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_dlld
+__call_stub_m32_static16_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_dlld
+	.previous
+
+	# Stub function to call m16_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_dlld
+__call_stub_m16_static16_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_dlld
+	.previous
+
+	# Stub function to call double m32_static16_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static16_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static16_d_l
+__call_stub_fp_m32_static16_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m32_static16_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static16_d_l
+	.previous
+
+	# Stub function to call double m16_static16_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static16_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static16_d_l
+__call_stub_fp_m16_static16_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m16_static16_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static16_d_l
+	.previous
+
+	# Stub function to call double m32_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static16_d_d
+__call_stub_fp_m32_static16_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m32_static16_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static16_d_d
+	.previous
+
+	# Stub function to call double m16_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static16_d_d
+__call_stub_fp_m16_static16_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m16_static16_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static16_d_d
+	.previous
+
+	.align	2
+	.globl	f16
+	.set	mips16
+	.ent	f16
+f16:
+	.frame	$sp,104,$31		# vars= 64, regs= 4/0, args= 24, gp= 0
+	.mask	0x80070000,-4
+	.fmask	0x00000000,0
+	save	104,$16,$17,$18,$31
+	move	$17,$4
+	sw	$7,116($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_l
+	sw	$6,112($sp)
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_l
+	move	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$3,116($sp)
+	lw	$6,112($sp)
+	sw	$3,20($sp)
+	move	$5,$3
+	sw	$6,16($sp)
+	move	$4,$6
+	move	$7,$17
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_dlld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	addu	$16,$2
+	lw	$7,112($sp)
+	lw	$2,116($sp)
+	move	$6,$17
+	move	$5,$2
+	sw	$7,16($sp)
+	move	$4,$7
+	sw	$2,20($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_dlld
+	move	$7,$17
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,28($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d_l
+	sw	$2,24($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,28($sp)
+	lw	$4,24($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,36($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d_d
+	sw	$2,32($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,36($sp)
+	lw	$4,32($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,44($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d_d
+	sw	$2,40($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,44($sp)
+	lw	$4,40($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,52($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_l
+	sw	$2,48($sp)
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$4,116($sp)
+	lw	$6,112($sp)
+	sw	$4,20($sp)
+	sw	$6,16($sp)
+	move	$5,$4
+	move	$7,$17
+	move	$4,$6
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_dlld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	addu	$16,$2
+	lw	$3,116($sp)
+	lw	$2,112($sp)
+	move	$6,$17
+	move	$7,$17
+	sw	$3,20($sp)
+	move	$5,$3
+	sw	$2,16($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_dlld
+	move	$4,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,60($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d_l
+	sw	$2,56($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,60($sp)
+	lw	$4,56($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,68($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d_d
+	sw	$2,64($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,68($sp)
+	lw	$4,64($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,76($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d_d
+	sw	$2,72($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,76($sp)
+	lw	$4,72($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$16
+	sw	$3,84($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_floatsidf
+	sw	$2,80($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$7,84($sp)
+	lw	$6,80($sp)
+	move	$5,$3
+	.set	noreorder
+	.set	nomacro
+	jal	__mips16_adddf3
+	move	$4,$2
+	.set	macro
+	.set	reorder
+
+	jal	__mips16_ret_df
+	restore	104,$16,$17,$18,$31
+	j	$31
+	.end	f16
diff --git a/gas/testsuite/gas/mips/mips16e-64.d b/gas/testsuite/gas/mips/mips16e-64.d
new file mode 100644
index 000000000000..9eb098f60a2f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -mmips:16
+#as: -march=mips64
+#name: MIPS16e-64
+#source: mips16e-64.s
+
+# Test the 64bit instructions of mips16e.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+0x00000000 ecd1      	sew	\$4
+0x00000002 ec51      	zew	\$4
+0x00000004 6500      	nop
+0x00000006 6500      	nop
+0x00000008 6500      	nop
+0x0000000a 6500      	nop
+0x0000000c 6500      	nop
+0x0000000e 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e-64.l b/gas/testsuite/gas/mips/mips16e-64.l
new file mode 100644
index 000000000000..8df0c0575a51
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Error: opcode not supported on this processor: .* (.*) `sew'
+.*: Error: opcode not supported on this processor: .* (.*) `zew'
diff --git a/gas/testsuite/gas/mips/mips16e-64.s b/gas/testsuite/gas/mips/mips16e-64.s
new file mode 100644
index 000000000000..39b359731442
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-64.s
@@ -0,0 +1,9 @@
+# Test the 64bit instructions of mips16e.
+
+	.text
+	.set	mips16
+
+	sew	$4
+	zew	$4
+
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/mips16e-save.d b/gas/testsuite/gas/mips/mips16e-save.d
index 6e18d8c32060..5f836866b9bc 100644
--- a/gas/testsuite/gas/mips/mips16e-save.d
+++ b/gas/testsuite/gas/mips/mips16e-save.d
@@ -39,5 +39,5 @@ Disassembly of section .text:
   60:[ 	]+6470[ 	]+restore[ 	]+128,ra,s0-s1
   62:[ 	]+f010 6441[ 	]+restore[ 	]+136,ra
   66:[ 	]+f100 6408[ 	]+restore[ 	]+64,s2
-  6a:[ 	]+f71b 6470[ 	]+restore[ 	]+128,ra,s0-s8,a0-a3
+  6a:[ 	]+f71a 6470[ 	]+restore[ 	]+a0-a1,128,ra,s0-s8,a2-a3
   6e:[ 	]+6500[ 	]+nop
diff --git a/gas/testsuite/gas/mips/mips16e.d b/gas/testsuite/gas/mips/mips16e.d
new file mode 100644
index 000000000000..53aa0d32aad6
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.d
@@ -0,0 +1,50 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS16e
+#as: -32
+
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> eac0      	jalrc	\$2
+0+0002 <[^>]*> eac0      	jalrc	\$2
+0+0004 <[^>]*> e8a0      	jrc	\$31
+0+0006 <[^>]*> ea80      	jrc	\$2
+0+0008 <[^>]*> eac0      	jalrc	\$2
+0+000a <[^>]*> eac0      	jalrc	\$2
+0+000c <[^>]*> eac0      	jalrc	\$2
+0+000e <[^>]*> eac0      	jalrc	\$2
+0+0010 <[^>]*> e8a0      	jrc	\$31
+0+0012 <[^>]*> ea80      	jrc	\$2
+0+0014 <[^>]*> e8a0      	jrc	\$31
+0+0016 <[^>]*> ea80      	jrc	\$2
+0+0018 <[^>]*> eac0      	jalrc	\$2
+0+001a <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			1a: R_MIPS16_26	foo
+0+001e <[^>]*> 4281      	addiu	\$4,\$2,1
+0+0020 <[^>]*> eac0      	jalrc	\$2
+0+0022 <[^>]*> 1800 0000 	jal	00000000 <[^>]*>
+			22: R_MIPS16_26	foo
+0+0026 <[^>]*> 6500      	nop
+0+0028 <[^>]*> 6782      	move	\$4,\$2
+0+002a <[^>]*> eac0      	jalrc	\$2
+0+002c <[^>]*> 6782      	move	\$4,\$2
+0+002e <[^>]*> ea80      	jrc	\$2
+0+0030 <[^>]*> 6782      	move	\$4,\$2
+0+0032 <[^>]*> e8a0      	jrc	\$31
+0+0034 <[^>]*> ec91      	seb	\$4
+0+0036 <[^>]*> ecb1      	seh	\$4
+0+0038 <[^>]*> ec11      	zeb	\$4
+0+003a <[^>]*> ec31      	zeh	\$4
+0+003c <[^>]*> 64c1      	save	8,\$31
+0+003e <[^>]*> 64c0      	save	128,\$31
+0+0040 <[^>]*> 64e2      	save	16,\$31,\$16
+0+0042 <[^>]*> 64f2      	save	16,\$31,\$16-\$17
+0+0044 <[^>]*> 64df      	save	120,\$31,\$17
+0+0046 <[^>]*> f010 64e1 	save	136,\$31,\$16
+0+004a <[^>]*> f004 64f2 	save	\$4,16,\$31,\$16-\$17
+0+004e <[^>]*> f308 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20
+0+0052 <[^>]*> f30c 64f2 	save	\$4-\$6,16,\$31,\$16-\$20
+0+0056 <[^>]*> f70e 64d2 	save	\$4-\$7,16,\$31,\$17-\$30
+0+005a <[^>]*> f30a 64e2 	save	\$4-\$5,16,\$31,\$16,\$18-\$20,\$6-\$7
+0+005e <[^>]*> 6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16e.s b/gas/testsuite/gas/mips/mips16e.s
new file mode 100644
index 000000000000..72e2d0928fb1
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e.s
@@ -0,0 +1,58 @@
+# Test the mips16e instruction set.
+
+	.set	mips16
+	.text
+stuff:
+	# explicit compact jumps
+	jalrc	$2
+	jalrc	$31,$2
+	jrc	$31
+	jrc	$2
+	
+	# these jumps should all be converted to compact versions
+	jalr	$2
+	jalr	$31,$2
+	jal	$2
+	jal	$31,$2
+	jr	$31
+	jr	$2
+	j	$31
+	j	$2
+	
+	# make sure unconditional jumps don't swap with compact jumps
+	# and vice versa.
+	jalr	$2
+	.set	noreorder
+	jal	foo		# mustn't swap with previous jalr
+	addu	$4,$2,1
+	.set	reorder
+	jalr	$2
+	jal	foo
+	
+	move	$4,$2
+1:	jal	$2		# can't swap with move
+		
+	move	$4,$2
+1:	jr	$2		# can't swap with move
+	
+	move	$4,$2
+1:	jr	$31		# can't swap with move
+	
+	seb	$4
+	seh	$4
+	zeb	$4
+	zeh	$4
+
+	save	$31,8
+	save	$31,128
+	save	$31,$16,16
+	save	$31,$16-$17,16
+	save	$31,$17,120
+	save	$31,$16,136
+	save	$4,$31,$16-$17,16
+	save	$4-$5,$31,$16,$18,$19,$20,16
+	save	$4-$6,$31,$16-$20,16
+	save	$4-$7,$31,$17,$18-$30,16
+	save	$4-$5,$31,$16,$18,$19,$20,16,$6-$7
+	
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/mips32-dsp.d b/gas/testsuite/gas/mips/mips32-dsp.d
index 486f630ac942..d538abd5abe4 100644
--- a/gas/testsuite/gas/mips/mips32-dsp.d
+++ b/gas/testsuite/gas/mips/mips32-dsp.d
@@ -1,7 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: MIPS DSP ASE for MIPS32
 #as: -mdsp -32
-#stderr: mips32-dsp.l
 
 # Check MIPS DSP ASE for MIPS32 Instruction Assembly
 
@@ -38,141 +37,103 @@ Disassembly of section .text:
 0+006c <[^>]*> 7c1cdf52 	preceu\.ph\.qbr	k1,gp
 0+0070 <[^>]*> 7c1de792 	preceu\.ph\.qbla	gp,sp
 0+0074 <[^>]*> 7c1eefd2 	preceu\.ph\.qbra	sp,s8
-0+0078 <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
-0+007c <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
-0+0080 <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
-0+0084 <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
-0+0088 <[^>]*> 7c20f893 	shllv\.qb	ra,zero,at
-0+008c <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
-0+0090 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
-0+0094 <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
-0+0098 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
-0+009c <[^>]*> 7c620a93 	shllv\.ph	at,v0,v1
-0+00a0 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
-0+00a4 <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
-0+00a8 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
-0+00ac <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
-0+00b0 <[^>]*> 7ca41b93 	shllv_s\.ph	v1,a0,a1
-0+00b4 <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
-0+00b8 <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
-0+00bc <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
-0+00c0 <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
-0+00c4 <[^>]*> 7ce62d93 	shllv_s\.w	a1,a2,a3
-0+00c8 <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
-0+00cc <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
-0+00d0 <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
-0+00d4 <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
-0+00d8 <[^>]*> 7d2838d3 	shrlv\.qb	a3,t0,t1
-0+00dc <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
-0+00e0 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
-0+00e4 <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
-0+00e8 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
-0+00ec <[^>]*> 7d6a4ad3 	shrav\.ph	t1,t2,t3
-0+00f0 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
-0+00f4 <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
-0+00f8 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
-0+00fc <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
-0+0100 <[^>]*> 7dac5bd3 	shrav_r\.ph	t3,t4,t5
-0+0104 <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
-0+0108 <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
-0+010c <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
-0+0110 <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
-0+0114 <[^>]*> 7dee6dd3 	shrav_r\.w	t5,t6,t7
-0+0118 <[^>]*> 7df07190 	muleu_s\.ph\.qbl	t6,t7,s0
-0+011c <[^>]*> 7e1179d0 	muleu_s\.ph\.qbr	t7,s0,s1
-0+0120 <[^>]*> 7e3287d0 	mulq_rs\.ph	s0,s1,s2
-0+0124 <[^>]*> 7e538f10 	muleq_s\.w\.phl	s1,s2,s3
-0+0128 <[^>]*> 7e749750 	muleq_s\.w\.phr	s2,s3,s4
-0+012c <[^>]*> 7e7400f0 	dpau\.h\.qbl	\$ac0,s3,s4
-0+0130 <[^>]*> 7e9509f0 	dpau\.h\.qbr	\$ac1,s4,s5
-0+0134 <[^>]*> 7eb612f0 	dpsu\.h\.qbl	\$ac2,s5,s6
-0+0138 <[^>]*> 7ed71bf0 	dpsu\.h\.qbr	\$ac3,s6,s7
-0+013c <[^>]*> 7ef80130 	dpaq_s\.w\.ph	\$ac0,s7,t8
-0+0140 <[^>]*> 7f190970 	dpsq_s\.w\.ph	\$ac1,t8,t9
-0+0144 <[^>]*> 7f3a11b0 	mulsaq_s\.w\.ph	\$ac2,t9,k0
-0+0148 <[^>]*> 7f5b1b30 	dpaq_sa\.l\.w	\$ac3,k0,k1
-0+014c <[^>]*> 7f7c0370 	dpsq_sa\.l\.w	\$ac0,k1,gp
-0+0150 <[^>]*> 7f9d0d30 	maq_s\.w\.phl	\$ac1,gp,sp
-0+0154 <[^>]*> 7fbe15b0 	maq_s\.w\.phr	\$ac2,sp,s8
-0+0158 <[^>]*> 7fdf1c30 	maq_sa\.w\.phl	\$ac3,s8,ra
-0+015c <[^>]*> 7fe004b0 	maq_sa\.w\.phr	\$ac0,ra,zero
-0+0160 <[^>]*> 7c0106d2 	bitrev	zero,at
-0+0164 <[^>]*> 7c41000c 	insv	at,v0
-0+0168 <[^>]*> 7cff1092 	repl\.qb	v0,0xff
-0+016c <[^>]*> 7c001092 	repl\.qb	v0,0x0
-0+0170 <[^>]*> 7cff1092 	repl\.qb	v0,0xff
-0+0174 <[^>]*> 7c001092 	repl\.qb	v0,0x0
-0+0178 <[^>]*> 7c0418d2 	replv\.qb	v1,a0
-0+017c <[^>]*> 7dff2292 	repl\.ph	a0,511
-0+0180 <[^>]*> 7e002292 	repl\.ph	a0,-512
-0+0184 <[^>]*> 7dff2292 	repl\.ph	a0,511
-0+0188 <[^>]*> 7e002292 	repl\.ph	a0,-512
-0+018c <[^>]*> 7c062ad2 	replv\.ph	a1,a2
-0+0190 <[^>]*> 7cc70011 	cmpu\.eq\.qb	a2,a3
-0+0194 <[^>]*> 7ce80051 	cmpu\.lt\.qb	a3,t0
-0+0198 <[^>]*> 7d090091 	cmpu\.le\.qb	t0,t1
-0+019c <[^>]*> 7d4b4911 	cmpgu\.eq\.qb	t1,t2,t3
-0+01a0 <[^>]*> 7d6c5151 	cmpgu\.lt\.qb	t2,t3,t4
-0+01a4 <[^>]*> 7d8d5991 	cmpgu\.le\.qb	t3,t4,t5
-0+01a8 <[^>]*> 7d8d0211 	cmp\.eq\.ph	t4,t5
-0+01ac <[^>]*> 7dae0251 	cmp\.lt\.ph	t5,t6
-0+01b0 <[^>]*> 7dcf0291 	cmp\.le\.ph	t6,t7
-0+01b4 <[^>]*> 7e1178d1 	pick\.qb	t7,s0,s1
-0+01b8 <[^>]*> 7e3282d1 	pick\.ph	s0,s1,s2
-0+01bc <[^>]*> 7e538b91 	packrl\.ph	s1,s2,s3
-0+01c0 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
-0+01c4 <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
-0+01c8 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
-0+01cc <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
-0+01d0 <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
-0+01d4 <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
-0+01d8 <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
-0+01dc <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
-0+01e0 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
-0+01e4 <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
-0+01e8 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
-0+01ec <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
-0+01f0 <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
-0+01f4 <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
-0+01f8 <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
-0+01fc <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
-0+0200 <[^>]*> 7ef60bf8 	extrv_s\.h	s6,\$ac1,s7
-0+0204 <[^>]*> 7f171078 	extrv\.w	s7,\$ac2,t8
-0+0208 <[^>]*> 7f381978 	extrv_r\.w	t8,\$ac3,t9
-0+020c <[^>]*> 7f5901f8 	extrv_rs\.w	t9,\$ac0,k0
-0+0210 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
-0+0214 <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
-0+0218 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
-0+021c <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
-0+0220 <[^>]*> 7f9b10f8 	extpv	k1,\$ac2,gp
-0+0224 <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
-0+0228 <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
-0+022c <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
-0+0230 <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
-0+0234 <[^>]*> 7fdd02f8 	extpdpv	sp,\$ac0,s8
-0+0238 <[^>]*> 7df00eb8 	shilo	\$ac1,31
-0+023c <[^>]*> 7e000eb8 	shilo	\$ac1,-32
-0+0240 <[^>]*> 7df00eb8 	shilo	\$ac1,31
-0+0244 <[^>]*> 7e000eb8 	shilo	\$ac1,-32
-0+0248 <[^>]*> 7fc016f8 	shilov	\$ac2,s8
-0+024c <[^>]*> 7fe01ff8 	mthlip	ra,\$ac3
-0+0250 <[^>]*> 00000010 	mfhi	zero
-0+0254 <[^>]*> 00200812 	mflo	at,\$ac1
-0+0258 <[^>]*> 00401011 	mthi	v0,\$ac2
-0+025c <[^>]*> 00601813 	mtlo	v1,\$ac3
-0+0260 <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
-0+0264 <[^>]*> 7c8004f8 	wrdsp	a0,0x0
-0+0268 <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
-0+026c <[^>]*> 7c8004f8 	wrdsp	a0,0x0
-0+0270 <[^>]*> 7cbffcf8 	wrdsp	a1
-0+0274 <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
-0+0278 <[^>]*> 7c0034b8 	rddsp	a2,0x0
-0+027c <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
-0+0280 <[^>]*> 7c0034b8 	rddsp	a2,0x0
-0+0284 <[^>]*> 7fff3cb8 	rddsp	a3
-0+0288 <[^>]*> 7d49418a 	lbux	t0,t1\(t2\)
-0+028c <[^>]*> 7d6a490a 	lhx	t1,t2\(t3\)
-0+0290 <[^>]*> 7d8b500a 	lwx	t2,t3\(t4\)
-0+0294 <[^>]*> 041cff5a 	bposge32	0+0000 <text_label>
-0+0298 <[^>]*> 00000000 	nop
-	...
+0+0078 <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
+0+007c <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
+0+0080 <[^>]*> 7c20f893 	shllv\.qb	ra,zero,at
+0+0084 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
+0+0088 <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
+0+008c <[^>]*> 7c620a93 	shllv\.ph	at,v0,v1
+0+0090 <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
+0+0094 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
+0+0098 <[^>]*> 7ca41b93 	shllv_s\.ph	v1,a0,a1
+0+009c <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
+0+00a0 <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
+0+00a4 <[^>]*> 7ce62d93 	shllv_s\.w	a1,a2,a3
+0+00a8 <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
+0+00ac <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
+0+00b0 <[^>]*> 7d2838d3 	shrlv\.qb	a3,t0,t1
+0+00b4 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
+0+00b8 <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
+0+00bc <[^>]*> 7d6a4ad3 	shrav\.ph	t1,t2,t3
+0+00c0 <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
+0+00c4 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
+0+00c8 <[^>]*> 7dac5bd3 	shrav_r\.ph	t3,t4,t5
+0+00cc <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
+0+00d0 <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
+0+00d4 <[^>]*> 7dee6dd3 	shrav_r\.w	t5,t6,t7
+0+00d8 <[^>]*> 7df07190 	muleu_s\.ph\.qbl	t6,t7,s0
+0+00dc <[^>]*> 7e1179d0 	muleu_s\.ph\.qbr	t7,s0,s1
+0+00e0 <[^>]*> 7e3287d0 	mulq_rs\.ph	s0,s1,s2
+0+00e4 <[^>]*> 7e538f10 	muleq_s\.w\.phl	s1,s2,s3
+0+00e8 <[^>]*> 7e749750 	muleq_s\.w\.phr	s2,s3,s4
+0+00ec <[^>]*> 7e7400f0 	dpau\.h\.qbl	\$ac0,s3,s4
+0+00f0 <[^>]*> 7e9509f0 	dpau\.h\.qbr	\$ac1,s4,s5
+0+00f4 <[^>]*> 7eb612f0 	dpsu\.h\.qbl	\$ac2,s5,s6
+0+00f8 <[^>]*> 7ed71bf0 	dpsu\.h\.qbr	\$ac3,s6,s7
+0+00fc <[^>]*> 7ef80130 	dpaq_s\.w\.ph	\$ac0,s7,t8
+0+0100 <[^>]*> 7f190970 	dpsq_s\.w\.ph	\$ac1,t8,t9
+0+0104 <[^>]*> 7f3a11b0 	mulsaq_s\.w\.ph	\$ac2,t9,k0
+0+0108 <[^>]*> 7f5b1b30 	dpaq_sa\.l\.w	\$ac3,k0,k1
+0+010c <[^>]*> 7f7c0370 	dpsq_sa\.l\.w	\$ac0,k1,gp
+0+0110 <[^>]*> 7f9d0d30 	maq_s\.w\.phl	\$ac1,gp,sp
+0+0114 <[^>]*> 7fbe15b0 	maq_s\.w\.phr	\$ac2,sp,s8
+0+0118 <[^>]*> 7fdf1c30 	maq_sa\.w\.phl	\$ac3,s8,ra
+0+011c <[^>]*> 7fe004b0 	maq_sa\.w\.phr	\$ac0,ra,zero
+0+0120 <[^>]*> 7c0106d2 	bitrev	zero,at
+0+0124 <[^>]*> 7c41000c 	insv	at,v0
+0+0128 <[^>]*> 7c001092 	repl\.qb	v0,0x0
+0+012c <[^>]*> 7cff1092 	repl\.qb	v0,0xff
+0+0130 <[^>]*> 7c0418d2 	replv\.qb	v1,a0
+0+0134 <[^>]*> 7e002292 	repl\.ph	a0,-512
+0+0138 <[^>]*> 7dff2292 	repl\.ph	a0,511
+0+013c <[^>]*> 7c062ad2 	replv\.ph	a1,a2
+0+0140 <[^>]*> 7cc70011 	cmpu\.eq\.qb	a2,a3
+0+0144 <[^>]*> 7ce80051 	cmpu\.lt\.qb	a3,t0
+0+0148 <[^>]*> 7d090091 	cmpu\.le\.qb	t0,t1
+0+014c <[^>]*> 7d4b4911 	cmpgu\.eq\.qb	t1,t2,t3
+0+0150 <[^>]*> 7d6c5151 	cmpgu\.lt\.qb	t2,t3,t4
+0+0154 <[^>]*> 7d8d5991 	cmpgu\.le\.qb	t3,t4,t5
+0+0158 <[^>]*> 7d8d0211 	cmp\.eq\.ph	t4,t5
+0+015c <[^>]*> 7dae0251 	cmp\.lt\.ph	t5,t6
+0+0160 <[^>]*> 7dcf0291 	cmp\.le\.ph	t6,t7
+0+0164 <[^>]*> 7e1178d1 	pick\.qb	t7,s0,s1
+0+0168 <[^>]*> 7e3282d1 	pick\.ph	s0,s1,s2
+0+016c <[^>]*> 7e538b91 	packrl\.ph	s1,s2,s3
+0+0170 <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
+0+0174 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
+0+0178 <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
+0+017c <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
+0+0180 <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
+0+0184 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
+0+0188 <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
+0+018c <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
+0+0190 <[^>]*> 7ef60bf8 	extrv_s\.h	s6,\$ac1,s7
+0+0194 <[^>]*> 7f171078 	extrv\.w	s7,\$ac2,t8
+0+0198 <[^>]*> 7f381978 	extrv_r\.w	t8,\$ac3,t9
+0+019c <[^>]*> 7f5901f8 	extrv_rs\.w	t9,\$ac0,k0
+0+01a0 <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
+0+01a4 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
+0+01a8 <[^>]*> 7f9b10f8 	extpv	k1,\$ac2,gp
+0+01ac <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
+0+01b0 <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
+0+01b4 <[^>]*> 7fdd02f8 	extpdpv	sp,\$ac0,s8
+0+01b8 <[^>]*> 7e000eb8 	shilo	\$ac1,-32
+0+01bc <[^>]*> 7df00eb8 	shilo	\$ac1,31
+0+01c0 <[^>]*> 7fc016f8 	shilov	\$ac2,s8
+0+01c4 <[^>]*> 7fe01ff8 	mthlip	ra,\$ac3
+0+01c8 <[^>]*> 00000010 	mfhi	zero
+0+01cc <[^>]*> 00200812 	mflo	at,\$ac1
+0+01d0 <[^>]*> 00401011 	mthi	v0,\$ac2
+0+01d4 <[^>]*> 00601813 	mtlo	v1,\$ac3
+0+01d8 <[^>]*> 7c8004f8 	wrdsp	a0,0x0
+0+01dc <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
+0+01e0 <[^>]*> 7cbffcf8 	wrdsp	a1
+0+01e4 <[^>]*> 7c0034b8 	rddsp	a2,0x0
+0+01e8 <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
+0+01ec <[^>]*> 7fff3cb8 	rddsp	a3
+0+01f0 <[^>]*> 7d49418a 	lbux	t0,t1\(t2\)
+0+01f4 <[^>]*> 7d6a490a 	lhx	t1,t2\(t3\)
+0+01f8 <[^>]*> 7d8b500a 	lwx	t2,t3\(t4\)
+0+01fc <[^>]*> 041cff80 	bposge32	00000000 <text_label>
+0+0200 <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-dsp.l b/gas/testsuite/gas/mips/mips32-dsp.l
deleted file mode 100644
index c7d3e7a14cfe..000000000000
--- a/gas/testsuite/gas/mips/mips32-dsp.l
+++ /dev/null
@@ -1,39 +0,0 @@
-.*: Assembler messages:
-.*:39: Warning: DSP immediate not in range 0..7 \([0-9]*\)
-.*:42: Warning: DSP immediate not in range 0..7 \(8\)
-.*:44: Warning: DSP immediate not in range 0..15 \([0-9]*\)
-.*:47: Warning: DSP immediate not in range 0..15 \(16\)
-.*:49: Warning: DSP immediate not in range 0..15 \([0-9]*\)
-.*:52: Warning: DSP immediate not in range 0..15 \(16\)
-.*:54: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:57: Warning: DSP immediate not in range 0..31 \(32\)
-.*:59: Warning: DSP immediate not in range 0..7 \([0-9]*\)
-.*:62: Warning: DSP immediate not in range 0..7 \(8\)
-.*:64: Warning: DSP immediate not in range 0..15 \([0-9]*\)
-.*:67: Warning: DSP immediate not in range 0..15 \(16\)
-.*:69: Warning: DSP immediate not in range 0..15 \([0-9]*\)
-.*:72: Warning: DSP immediate not in range 0..15 \(16\)
-.*:74: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:77: Warning: DSP immediate not in range 0..31 \(32\)
-.*:99: Warning: DSP immediate not in range 0..255 \([0-9]*\)
-.*:102: Warning: DSP immediate not in range 0..255 \(256\)
-.*:104: Warning: DSP immediate not in range -512..511 \(-513\)
-.*:107: Warning: DSP immediate not in range -512..511 \(512\)
-.*:121: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:124: Warning: DSP immediate not in range 0..31 \(32\)
-.*:125: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:128: Warning: DSP immediate not in range 0..31 \(32\)
-.*:129: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:132: Warning: DSP immediate not in range 0..31 \(32\)
-.*:133: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:136: Warning: DSP immediate not in range 0..31 \(32\)
-.*:141: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:144: Warning: DSP immediate not in range 0..31 \(32\)
-.*:146: Warning: DSP immediate not in range 0..31 \([0-9]*\)
-.*:149: Warning: DSP immediate not in range 0..31 \(32\)
-.*:151: Warning: DSP immediate not in range -32..31 \(-33\)
-.*:154: Warning: DSP immediate not in range -32..31 \(32\)
-.*:161: Warning: DSP immediate not in range 0..63 \([0-9]*\)
-.*:164: Warning: DSP immediate not in range 0..63 \(64\)
-.*:166: Warning: DSP immediate not in range 0..63 \([0-9]*\)
-.*:169: Warning: DSP immediate not in range 0..63 \(64\)
diff --git a/gas/testsuite/gas/mips/mips32-dsp.s b/gas/testsuite/gas/mips/mips32-dsp.s
index aa818ce85138..8c5d46cad0e9 100644
--- a/gas/testsuite/gas/mips/mips32-dsp.s
+++ b/gas/testsuite/gas/mips/mips32-dsp.s
@@ -1,6 +1,7 @@
 # source file to test assembly of MIPS DSP ASE for MIPS32 instructions
 
 	.set noreorder
+	.set nomacro
 	.set noat
 
 	.text
@@ -36,45 +37,29 @@ text_label:
 	preceu.ph.qbr	$27,$28
 	preceu.ph.qbla	$28,$29
 	preceu.ph.qbra	$29,$30
-	shll.qb		$30,$31,-1
 	shll.qb		$30,$31,0
 	shll.qb		$30,$31,7
-	shll.qb		$30,$31,8
 	shllv.qb	$31,$0,$1
-	shll.ph		$0,$1,-1
 	shll.ph		$0,$1,0
 	shll.ph		$0,$1,15
-	shll.ph		$0,$1,16
 	shllv.ph	$1,$2,$3
-	shll_s.ph	$2,$3,-1
 	shll_s.ph	$2,$3,0
 	shll_s.ph	$2,$3,15
-	shll_s.ph	$2,$3,16
 	shllv_s.ph	$3,$4,$5
-	shll_s.w	$4,$5,-1
 	shll_s.w	$4,$5,0
 	shll_s.w	$4,$5,31
-	shll_s.w	$4,$5,32
 	shllv_s.w	$5,$6,$7
-	shrl.qb		$6,$7,-1
 	shrl.qb		$6,$7,0
 	shrl.qb		$6,$7,7
-	shrl.qb		$6,$7,8
 	shrlv.qb	$7,$8,$9
-	shra.ph		$8,$9,-1
 	shra.ph		$8,$9,0
 	shra.ph		$8,$9,15
-	shra.ph		$8,$9,16
 	shrav.ph	$9,$10,$11
-	shra_r.ph	$10,$11,-1
 	shra_r.ph	$10,$11,0
 	shra_r.ph	$10,$11,15
-	shra_r.ph	$10,$11,16
 	shrav_r.ph	$11,$12,$13
-	shra_r.w	$12,$13,-1
 	shra_r.w	$12,$13,0
 	shra_r.w	$12,$13,31
-	shra_r.w	$12,$13,32
 	shrav_r.w	$13,$14,$15
 	muleu_s.ph.qbl	$14,$15,$16
 	muleu_s.ph.qbr	$15,$16,$17
@@ -96,15 +81,11 @@ text_label:
 	maq_sa.w.phr	$ac0,$31,$0
 	bitrev		$0,$1
 	insv		$1,$2
-	repl.qb		$2,-1
 	repl.qb		$2,0
 	repl.qb		$2,255
-	repl.qb		$2,256
 	replv.qb	$3,$4
-	repl.ph		$4,-513
 	repl.ph		$4,-512
 	repl.ph		$4,511
-	repl.ph		$4,512
 	replv.ph	$5,$6
 	cmpu.eq.qb	$6,$7
 	cmpu.lt.qb	$7,$8
@@ -118,55 +99,37 @@ text_label:
 	pick.qb		$15,$16,$17
 	pick.ph		$16,$17,$18
 	packrl.ph	$17,$18,$19
-	extr.w		$18,$ac1,-1
 	extr.w		$18,$ac1,0
 	extr.w		$18,$ac1,31
-	extr.w		$18,$ac1,32
-	extr_r.w	$19,$ac2,-1
 	extr_r.w	$19,$ac2,0
 	extr_r.w	$19,$ac2,31
-	extr_r.w	$19,$ac2,32
-	extr_rs.w	$20,$ac3,-1
 	extr_rs.w	$20,$ac3,0
 	extr_rs.w	$20,$ac3,31
-	extr_rs.w	$20,$ac3,32
-	extr_s.h	$21,$ac0,-1
 	extr_s.h	$21,$ac0,0
 	extr_s.h	$21,$ac0,31
-	extr_s.h	$21,$ac0,32
 	extrv_s.h	$22,$ac1,$23
 	extrv.w		$23,$ac2,$24
 	extrv_r.w	$24,$ac3,$25
 	extrv_rs.w	$25,$ac0,$26
-	extp		$26,$ac1,-1
 	extp		$26,$ac1,0
 	extp		$26,$ac1,31
-	extp		$26,$ac1,32
 	extpv		$27,$ac2,$28
-	extpdp		$28,$ac3,-1
 	extpdp		$28,$ac3,0
 	extpdp		$28,$ac3,31
-	extpdp		$28,$ac3,32
 	extpdpv		$29,$ac0,$30
-	shilo		$ac1,-33
 	shilo		$ac1,-32
 	shilo		$ac1,31
-	shilo		$ac1,32
 	shilov		$ac2,$30
 	mthlip		$31,$ac3
 	mfhi		$0,$ac0
 	mflo		$1,$ac1
 	mthi		$2,$ac2
 	mtlo		$3,$ac3
-	wrdsp		$4,-1
 	wrdsp		$4,0
 	wrdsp		$4,63
-	wrdsp		$4,64
 	wrdsp		$5
-	rddsp		$6,-1
 	rddsp		$6,0
 	rddsp		$6,63
-	rddsp		$6,64
 	rddsp		$7
 	lbux		$8,$9($10)
 	lhx		$9,$10($11)
diff --git a/gas/testsuite/gas/mips/mips32-dspr2.d b/gas/testsuite/gas/mips/mips32-dspr2.d
new file mode 100644
index 000000000000..90c20ef711c3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr2.d
@@ -0,0 +1,72 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev2 for MIPS32
+#as: -mdspr2 -32
+
+# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c010052 	absq_s\.qb	zero,at
+0+0004 <[^>]*> 7c430a10 	addu\.ph	at,v0,v1
+0+0008 <[^>]*> 7c641310 	addu_s\.ph	v0,v1,a0
+0+000c <[^>]*> 7c851818 	adduh\.qb	v1,a0,a1
+0+0010 <[^>]*> 7ca62098 	adduh_r\.qb	a0,a1,a2
+0+0014 <[^>]*> 7cc50031 	append	a1,a2,0x0
+0+0018 <[^>]*> 7cc5f831 	append	a1,a2,0x1f
+0+001c <[^>]*> 00000000 	nop
+0+0020 <[^>]*> 7ce60c31 	balign	a2,a3,0x1
+0+0024 <[^>]*> 7cc73391 	packrl.ph	a2,a2,a3
+0+0028 <[^>]*> 7ce61c31 	balign	a2,a3,0x3
+0+002c <[^>]*> 7ce83611 	cmpgdu\.eq\.qb	a2,a3,t0
+0+0030 <[^>]*> 7d093e51 	cmpgdu\.lt\.qb	a3,t0,t1
+0+0034 <[^>]*> 7d2a4691 	cmpgdu\.le\.qb	t0,t1,t2
+0+0038 <[^>]*> 7d2a0030 	dpa\.w\.ph	\$ac0,t1,t2
+0+003c <[^>]*> 7d4b0870 	dps\.w\.ph	\$ac1,t2,t3
+0+0040 <[^>]*> 716c1000 	madd	\$ac2,t3,t4
+0+0044 <[^>]*> 718d1801 	maddu	\$ac3,t4,t5
+0+0048 <[^>]*> 71ae0004 	msub	t5,t6
+0+004c <[^>]*> 71cf0805 	msubu	\$ac1,t6,t7
+0+0050 <[^>]*> 7e117b18 	mul\.ph	t7,s0,s1
+0+0054 <[^>]*> 7e328398 	mul_s\.ph	s0,s1,s2
+0+0058 <[^>]*> 7e538dd8 	mulq_rs\.w	s1,s2,s3
+0+005c <[^>]*> 7e749790 	mulq_s\.ph	s2,s3,s4
+0+0060 <[^>]*> 7e959d98 	mulq_s\.w	s3,s4,s5
+0+0064 <[^>]*> 7e9510b0 	mulsa\.w\.ph	\$ac2,s4,s5
+0+0068 <[^>]*> 02b61818 	mult	\$ac3,s5,s6
+0+006c <[^>]*> 02d70019 	multu	s6,s7
+0+0070 <[^>]*> 7f19bb51 	precr\.qb\.ph	s7,t8,t9
+0+0074 <[^>]*> 7f380791 	precr_sra\.ph\.w	t8,t9,0x0
+0+0078 <[^>]*> 7f38ff91 	precr_sra\.ph\.w	t8,t9,0x1f
+0+007c <[^>]*> 7f5907d1 	precr_sra_r\.ph\.w	t9,k0,0x0
+0+0080 <[^>]*> 7f59ffd1 	precr_sra_r\.ph\.w	t9,k0,0x1f
+0+0084 <[^>]*> 7f7a0071 	prepend	k0,k1,0x0
+0+0088 <[^>]*> 7f7af871 	prepend	k0,k1,0x1f
+0+008c <[^>]*> 7c1cd913 	shra\.qb	k1,gp,0x0
+0+0090 <[^>]*> 7cfcd913 	shra\.qb	k1,gp,0x7
+0+0094 <[^>]*> 7c1de153 	shra_r\.qb	gp,sp,0x0
+0+0098 <[^>]*> 7cfde153 	shra_r\.qb	gp,sp,0x7
+0+009c <[^>]*> 7ffee993 	shrav\.qb	sp,s8,ra
+0+00a0 <[^>]*> 7c1ff1d3 	shrav_r\.qb	s8,ra,zero
+0+00a4 <[^>]*> 7c00fe53 	shrl\.ph	ra,zero,0x0
+0+00a8 <[^>]*> 7de0fe53 	shrl\.ph	ra,zero,0xf
+0+00ac <[^>]*> 7c4106d3 	shrlv\.ph	zero,at,v0
+0+00b0 <[^>]*> 7c430a50 	subu\.ph	at,v0,v1
+0+00b4 <[^>]*> 7c641350 	subu_s\.ph	v0,v1,a0
+0+00b8 <[^>]*> 7c851858 	subuh\.qb	v1,a0,a1
+0+00bc <[^>]*> 7ca620d8 	subuh_r\.qb	a0,a1,a2
+0+00c0 <[^>]*> 7cc72a18 	addqh\.ph	a1,a2,a3
+0+00c4 <[^>]*> 7ce83298 	addqh_r\.ph	a2,a3,t0
+0+00c8 <[^>]*> 7d093c18 	addqh\.w	a3,t0,t1
+0+00cc <[^>]*> 7d2a4498 	addqh_r\.w	t0,t1,t2
+0+00d0 <[^>]*> 7d4b4a58 	subqh\.ph	t1,t2,t3
+0+00d4 <[^>]*> 7d6c52d8 	subqh_r\.ph	t2,t3,t4
+0+00d8 <[^>]*> 7d8d5c58 	subqh\.w	t3,t4,t5
+0+00dc <[^>]*> 7dae64d8 	subqh_r\.w	t4,t5,t6
+0+00e0 <[^>]*> 7dae0a30 	dpax\.w\.ph	\$ac1,t5,t6
+0+00e4 <[^>]*> 7dcf1270 	dpsx\.w\.ph	\$ac2,t6,t7
+0+00e8 <[^>]*> 7df01e30 	dpaqx_s\.w\.ph	\$ac3,t7,s0
+0+00ec <[^>]*> 7e1106b0 	dpaqx_sa\.w\.ph	\$ac0,s0,s1
+0+00f0 <[^>]*> 7e320e70 	dpsqx_s\.w\.ph	\$ac1,s1,s2
+0+00f4 <[^>]*> 7e5316f0 	dpsqx_sa\.w\.ph	\$ac2,s2,s3
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-dspr2.s b/gas/testsuite/gas/mips/mips32-dspr2.s
new file mode 100644
index 000000000000..e22d79807292
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr2.s
@@ -0,0 +1,73 @@
+# source file to test assembly of MIPS DSP ASE Rev2 for MIPS32 instructions
+
+	.set noreorder
+	.set noat
+
+	.text
+text_label:
+
+	absq_s.qb	$0,$1
+	addu.ph		$1,$2,$3
+	addu_s.ph	$2,$3,$4
+	adduh.qb	$3,$4,$5
+	adduh_r.qb	$4,$5,$6
+	append		$5,$6,0
+	append		$5,$6,31
+	balign		$6,$7,0
+	balign		$6,$7,1
+	balign		$6,$7,2
+	balign		$6,$7,3
+	cmpgdu.eq.qb	$6,$7,$8
+	cmpgdu.lt.qb	$7,$8,$9
+	cmpgdu.le.qb	$8,$9,$10
+	dpa.w.ph	$ac0,$9,$10
+	dps.w.ph	$ac1,$10,$11
+	madd		$ac2,$11,$12
+	maddu		$ac3,$12,$13
+	msub		$ac0,$13,$14
+	msubu		$ac1,$14,$15
+	mul.ph		$15,$16,$17
+	mul_s.ph	$16,$17,$18
+	mulq_rs.w	$17,$18,$19
+	mulq_s.ph	$18,$19,$20
+	mulq_s.w	$19,$20,$21
+	mulsa.w.ph	$ac2,$20,$21
+	mult		$ac3,$21,$22
+	multu		$ac0,$22,$23
+	precr.qb.ph	$23,$24,$25
+	precr_sra.ph.w	$24,$25,0
+	precr_sra.ph.w	$24,$25,31
+	precr_sra_r.ph.w	$25,$26,0
+	precr_sra_r.ph.w	$25,$26,31
+	prepend		$26,$27,0
+	prepend		$26,$27,31
+	shra.qb		$27,$28,0
+	shra.qb		$27,$28,7
+	shra_r.qb	$28,$29,0
+	shra_r.qb	$28,$29,7
+	shrav.qb	$29,$30,$31
+	shrav_r.qb	$30,$31,$0
+	shrl.ph		$31,$0,0
+	shrl.ph		$31,$0,15
+	shrlv.ph	$0,$1,$2
+	subu.ph		$1,$2,$3
+	subu_s.ph	$2,$3,$4
+	subuh.qb	$3,$4,$5
+	subuh_r.qb	$4,$5,$6
+	addqh.ph        $5,$6,$7
+	addqh_r.ph      $6,$7,$8
+	addqh.w         $7,$8,$9
+	addqh_r.w       $8,$9,$10
+	subqh.ph        $9,$10,$11
+	subqh_r.ph      $10,$11,$12
+	subqh.w         $11,$12,$13
+	subqh_r.w       $12,$13,$14
+	dpax.w.ph       $ac1,$13,$14
+	dpsx.w.ph       $ac2,$14,$15
+	dpaqx_s.w.ph    $ac3,$15,$16
+	dpaqx_sa.w.ph   $ac0,$16,$17
+	dpsqx_s.w.ph    $ac1,$17,$18
+	dpsqx_sa.w.ph   $ac2,$18,$19
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8
diff --git a/gas/testsuite/gas/mips/mips32-mt.d b/gas/testsuite/gas/mips/mips32-mt.d
index ffb3e975362e..c64073271b33 100644
--- a/gas/testsuite/gas/mips/mips32-mt.d
+++ b/gas/testsuite/gas/mips/mips32-mt.d
@@ -567,260 +567,68 @@ Disassembly of section .text:
 0+08b0 <[^>]*> 418a5824 	mttc2	t2,\$11
 0+08b4 <[^>]*> 418b6034 	mtthc2	t3,\$12
 0+08b8 <[^>]*> 418c6825 	cttc2	t4,\$13
-0+08bc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
-0+08c0 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
-0+08c4 <[^>]*> 410e6832 	mfthc1	t5,\$f14
-0+08c8 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
-0+08cc <[^>]*> 410e6834 	mfthc2	t5,\$14
-0+08d0 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
-0+08d4 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
-0+08d8 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
-0+08dc <[^>]*> 410e6820 	mftgpr	t5,t6
-0+08e0 <[^>]*> 410e6821 	mftacx	t5,\$ac3
-0+08e4 <[^>]*> 410e6822 	mftc1	t5,\$f14
-0+08e8 <[^>]*> 410e6823 	cftc1	t5,\$14
-0+08ec <[^>]*> 410e6824 	mftc2	t5,\$14
-0+08f0 <[^>]*> 410e6825 	cftc2	t5,\$14
-0+08f4 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
-0+08f8 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
-0+08fc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
-0+0900 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
-0+0904 <[^>]*> 410e6832 	mfthc1	t5,\$f14
-0+0908 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
-0+090c <[^>]*> 410e6834 	mfthc2	t5,\$14
-0+0910 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
-0+0914 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
-0+0918 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
-0+091c <[^>]*> 410e6820 	mftgpr	t5,t6
-0+0920 <[^>]*> 410e6821 	mftacx	t5,\$ac3
-0+0924 <[^>]*> 410e6822 	mftc1	t5,\$f14
-0+0928 <[^>]*> 410e6823 	cftc1	t5,\$14
-0+092c <[^>]*> 410e6824 	mftc2	t5,\$14
-0+0930 <[^>]*> 410e6825 	cftc2	t5,\$14
-0+0934 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
-0+0938 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
-0+093c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
-0+0940 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
-0+0944 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
-0+0948 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
-0+094c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
-0+0950 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
-0+0954 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
-0+0958 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
-0+095c <[^>]*> 410e6800 	mftc0	t5,c0_epc
-0+0960 <[^>]*> 410e6801 	mftc0	t5,\$14,1
-0+0964 <[^>]*> 410e6802 	mftc0	t5,\$14,2
-0+0968 <[^>]*> 410e6803 	mftc0	t5,\$14,3
-0+096c <[^>]*> 410e6804 	mftc0	t5,\$14,4
-0+0970 <[^>]*> 410e6805 	mftc0	t5,\$14,5
-0+0974 <[^>]*> 410e6806 	mftc0	t5,\$14,6
-0+0978 <[^>]*> 410e6807 	mftc0	t5,\$14,7
-0+097c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
-0+0980 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
-0+0984 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
-0+0988 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
-0+098c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
-0+0990 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
-0+0994 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
-0+0998 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
-0+099c <[^>]*> 410e6800 	mftc0	t5,c0_epc
-0+09a0 <[^>]*> 410e6801 	mftc0	t5,\$14,1
-0+09a4 <[^>]*> 410e6802 	mftc0	t5,\$14,2
-0+09a8 <[^>]*> 410e6803 	mftc0	t5,\$14,3
-0+09ac <[^>]*> 410e6804 	mftc0	t5,\$14,4
-0+09b0 <[^>]*> 410e6805 	mftc0	t5,\$14,5
-0+09b4 <[^>]*> 410e6806 	mftc0	t5,\$14,6
-0+09b8 <[^>]*> 410e6807 	mftc0	t5,\$14,7
-0+09bc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
-0+09c0 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
-0+09c4 <[^>]*> 410e6832 	mfthc1	t5,\$f14
-0+09c8 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
-0+09cc <[^>]*> 410e6834 	mfthc2	t5,\$14
-0+09d0 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
-0+09d4 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
-0+09d8 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
-0+09dc <[^>]*> 410e6820 	mftgpr	t5,t6
-0+09e0 <[^>]*> 410e6821 	mftacx	t5,\$ac3
-0+09e4 <[^>]*> 410e6822 	mftc1	t5,\$f14
-0+09e8 <[^>]*> 410e6823 	cftc1	t5,\$14
-0+09ec <[^>]*> 410e6824 	mftc2	t5,\$14
-0+09f0 <[^>]*> 410e6825 	cftc2	t5,\$14
-0+09f4 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
-0+09f8 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
-0+09fc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
-0+0a00 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
-0+0a04 <[^>]*> 410e6832 	mfthc1	t5,\$f14
-0+0a08 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
-0+0a0c <[^>]*> 410e6834 	mfthc2	t5,\$14
-0+0a10 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
-0+0a14 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
-0+0a18 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
-0+0a1c <[^>]*> 410e6820 	mftgpr	t5,t6
-0+0a20 <[^>]*> 410e6821 	mftacx	t5,\$ac3
-0+0a24 <[^>]*> 410e6822 	mftc1	t5,\$f14
-0+0a28 <[^>]*> 410e6823 	cftc1	t5,\$14
-0+0a2c <[^>]*> 410e6824 	mftc2	t5,\$14
-0+0a30 <[^>]*> 410e6825 	cftc2	t5,\$14
-0+0a34 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
-0+0a38 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
-0+0a3c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
-0+0a40 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
-0+0a44 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
-0+0a48 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
-0+0a4c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
-0+0a50 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
-0+0a54 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
-0+0a58 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
-0+0a5c <[^>]*> 410e6800 	mftc0	t5,c0_epc
-0+0a60 <[^>]*> 410e6801 	mftc0	t5,\$14,1
-0+0a64 <[^>]*> 410e6802 	mftc0	t5,\$14,2
-0+0a68 <[^>]*> 410e6803 	mftc0	t5,\$14,3
-0+0a6c <[^>]*> 410e6804 	mftc0	t5,\$14,4
-0+0a70 <[^>]*> 410e6805 	mftc0	t5,\$14,5
-0+0a74 <[^>]*> 410e6806 	mftc0	t5,\$14,6
-0+0a78 <[^>]*> 410e6807 	mftc0	t5,\$14,7
-0+0a7c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
-0+0a80 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
-0+0a84 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
-0+0a88 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
-0+0a8c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
-0+0a90 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
-0+0a94 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
-0+0a98 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
-0+0a9c <[^>]*> 410e6800 	mftc0	t5,c0_epc
-0+0aa0 <[^>]*> 410e6801 	mftc0	t5,\$14,1
-0+0aa4 <[^>]*> 410e6802 	mftc0	t5,\$14,2
-0+0aa8 <[^>]*> 410e6803 	mftc0	t5,\$14,3
-0+0aac <[^>]*> 410e6804 	mftc0	t5,\$14,4
-0+0ab0 <[^>]*> 410e6805 	mftc0	t5,\$14,5
-0+0ab4 <[^>]*> 410e6806 	mftc0	t5,\$14,6
-0+0ab8 <[^>]*> 410e6807 	mftc0	t5,\$14,7
-0+0abc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
-0+0ac0 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
-0+0ac4 <[^>]*> 418d7032 	mtthc1	t5,\$f14
-0+0ac8 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
-0+0acc <[^>]*> 418d7034 	mtthc2	t5,\$14
-0+0ad0 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
-0+0ad4 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
-0+0ad8 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
-0+0adc <[^>]*> 418d7020 	mttgpr	t5,t6
-0+0ae0 <[^>]*> 418d7021 	mttacx	t5,\$ac3
-0+0ae4 <[^>]*> 418d7022 	mttc1	t5,\$f14
-0+0ae8 <[^>]*> 418d7023 	cttc1	t5,\$14
-0+0aec <[^>]*> 418d7024 	mttc2	t5,\$14
-0+0af0 <[^>]*> 418d7025 	cttc2	t5,\$14
-0+0af4 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
-0+0af8 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
-0+0afc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
-0+0b00 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
-0+0b04 <[^>]*> 418d7032 	mtthc1	t5,\$f14
-0+0b08 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
-0+0b0c <[^>]*> 418d7034 	mtthc2	t5,\$14
-0+0b10 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
-0+0b14 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
-0+0b18 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
-0+0b1c <[^>]*> 418d7020 	mttgpr	t5,t6
-0+0b20 <[^>]*> 418d7021 	mttacx	t5,\$ac3
-0+0b24 <[^>]*> 418d7022 	mttc1	t5,\$f14
-0+0b28 <[^>]*> 418d7023 	cttc1	t5,\$14
-0+0b2c <[^>]*> 418d7024 	mttc2	t5,\$14
-0+0b30 <[^>]*> 418d7025 	cttc2	t5,\$14
-0+0b34 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
-0+0b38 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
-0+0b3c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
-0+0b40 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
-0+0b44 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
-0+0b48 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
-0+0b4c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
-0+0b50 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
-0+0b54 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
-0+0b58 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
-0+0b5c <[^>]*> 418d7000 	mttc0	t5,c0_epc
-0+0b60 <[^>]*> 418d7001 	mttc0	t5,\$14,1
-0+0b64 <[^>]*> 418d7002 	mttc0	t5,\$14,2
-0+0b68 <[^>]*> 418d7003 	mttc0	t5,\$14,3
-0+0b6c <[^>]*> 418d7004 	mttc0	t5,\$14,4
-0+0b70 <[^>]*> 418d7005 	mttc0	t5,\$14,5
-0+0b74 <[^>]*> 418d7006 	mttc0	t5,\$14,6
-0+0b78 <[^>]*> 418d7007 	mttc0	t5,\$14,7
-0+0b7c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
-0+0b80 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
-0+0b84 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
-0+0b88 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
-0+0b8c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
-0+0b90 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
-0+0b94 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
-0+0b98 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
-0+0b9c <[^>]*> 418d7000 	mttc0	t5,c0_epc
-0+0ba0 <[^>]*> 418d7001 	mttc0	t5,\$14,1
-0+0ba4 <[^>]*> 418d7002 	mttc0	t5,\$14,2
-0+0ba8 <[^>]*> 418d7003 	mttc0	t5,\$14,3
-0+0bac <[^>]*> 418d7004 	mttc0	t5,\$14,4
-0+0bb0 <[^>]*> 418d7005 	mttc0	t5,\$14,5
-0+0bb4 <[^>]*> 418d7006 	mttc0	t5,\$14,6
-0+0bb8 <[^>]*> 418d7007 	mttc0	t5,\$14,7
-0+0bbc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
-0+0bc0 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
-0+0bc4 <[^>]*> 418d7032 	mtthc1	t5,\$f14
-0+0bc8 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
-0+0bcc <[^>]*> 418d7034 	mtthc2	t5,\$14
-0+0bd0 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
-0+0bd4 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
-0+0bd8 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
-0+0bdc <[^>]*> 418d7020 	mttgpr	t5,t6
-0+0be0 <[^>]*> 418d7021 	mttacx	t5,\$ac3
-0+0be4 <[^>]*> 418d7022 	mttc1	t5,\$f14
-0+0be8 <[^>]*> 418d7023 	cttc1	t5,\$14
-0+0bec <[^>]*> 418d7024 	mttc2	t5,\$14
-0+0bf0 <[^>]*> 418d7025 	cttc2	t5,\$14
-0+0bf4 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
-0+0bf8 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
-0+0bfc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
-0+0c00 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
-0+0c04 <[^>]*> 418d7032 	mtthc1	t5,\$f14
-0+0c08 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
-0+0c0c <[^>]*> 418d7034 	mtthc2	t5,\$14
-0+0c10 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
-0+0c14 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
-0+0c18 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
-0+0c1c <[^>]*> 418d7020 	mttgpr	t5,t6
-0+0c20 <[^>]*> 418d7021 	mttacx	t5,\$ac3
-0+0c24 <[^>]*> 418d7022 	mttc1	t5,\$f14
-0+0c28 <[^>]*> 418d7023 	cttc1	t5,\$14
-0+0c2c <[^>]*> 418d7024 	mttc2	t5,\$14
-0+0c30 <[^>]*> 418d7025 	cttc2	t5,\$14
-0+0c34 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
-0+0c38 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
-0+0c3c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
-0+0c40 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
-0+0c44 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
-0+0c48 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
-0+0c4c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
-0+0c50 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
-0+0c54 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
-0+0c58 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
-0+0c5c <[^>]*> 418d7000 	mttc0	t5,c0_epc
-0+0c60 <[^>]*> 418d7001 	mttc0	t5,\$14,1
-0+0c64 <[^>]*> 418d7002 	mttc0	t5,\$14,2
-0+0c68 <[^>]*> 418d7003 	mttc0	t5,\$14,3
-0+0c6c <[^>]*> 418d7004 	mttc0	t5,\$14,4
-0+0c70 <[^>]*> 418d7005 	mttc0	t5,\$14,5
-0+0c74 <[^>]*> 418d7006 	mttc0	t5,\$14,6
-0+0c78 <[^>]*> 418d7007 	mttc0	t5,\$14,7
-0+0c7c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
-0+0c80 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
-0+0c84 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
-0+0c88 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
-0+0c8c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
-0+0c90 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
-0+0c94 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
-0+0c98 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
-0+0c9c <[^>]*> 418d7000 	mttc0	t5,c0_epc
-0+0ca0 <[^>]*> 418d7001 	mttc0	t5,\$14,1
-0+0ca4 <[^>]*> 418d7002 	mttc0	t5,\$14,2
-0+0ca8 <[^>]*> 418d7003 	mttc0	t5,\$14,3
-0+0cac <[^>]*> 418d7004 	mttc0	t5,\$14,4
-0+0cb0 <[^>]*> 418d7005 	mttc0	t5,\$14,5
-0+0cb4 <[^>]*> 418d7006 	mttc0	t5,\$14,6
-0+0cb8 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+0+08bc <[^>]*> 410e6800 	mftc0	t5,c0_epc
+0+08c0 <[^>]*> 410e6801 	mftc0	t5,\$14,1
+0+08c4 <[^>]*> 410e6802 	mftc0	t5,\$14,2
+0+08c8 <[^>]*> 410e6803 	mftc0	t5,\$14,3
+0+08cc <[^>]*> 410e6804 	mftc0	t5,\$14,4
+0+08d0 <[^>]*> 410e6805 	mftc0	t5,\$14,5
+0+08d4 <[^>]*> 410e6806 	mftc0	t5,\$14,6
+0+08d8 <[^>]*> 410e6807 	mftc0	t5,\$14,7
+0+08dc <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
+0+08e0 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
+0+08e4 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
+0+08e8 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
+0+08ec <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
+0+08f0 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
+0+08f4 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
+0+08f8 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
+0+08fc <[^>]*> 410e6820 	mftgpr	t5,t6
+0+0900 <[^>]*> 410e6821 	mftacx	t5,\$ac3
+0+0904 <[^>]*> 410e6822 	mftc1	t5,\$f14
+0+0908 <[^>]*> 410e6823 	cftc1	t5,\$14
+0+090c <[^>]*> 410e6824 	mftc2	t5,\$14
+0+0910 <[^>]*> 410e6825 	cftc2	t5,\$14
+0+0914 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
+0+0918 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
+0+091c <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
+0+0920 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
+0+0924 <[^>]*> 410e6832 	mfthc1	t5,\$f14
+0+0928 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
+0+092c <[^>]*> 410e6834 	mfthc2	t5,\$14
+0+0930 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
+0+0934 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
+0+0938 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
+0+093c <[^>]*> 418d7000 	mttc0	t5,c0_epc
+0+0940 <[^>]*> 418d7001 	mttc0	t5,\$14,1
+0+0944 <[^>]*> 418d7002 	mttc0	t5,\$14,2
+0+0948 <[^>]*> 418d7003 	mttc0	t5,\$14,3
+0+094c <[^>]*> 418d7004 	mttc0	t5,\$14,4
+0+0950 <[^>]*> 418d7005 	mttc0	t5,\$14,5
+0+0954 <[^>]*> 418d7006 	mttc0	t5,\$14,6
+0+0958 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+0+095c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
+0+0960 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
+0+0964 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
+0+0968 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
+0+096c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
+0+0970 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
+0+0974 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
+0+0978 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
+0+097c <[^>]*> 418d7020 	mttgpr	t5,t6
+0+0980 <[^>]*> 418d7021 	mttacx	t5,\$ac3
+0+0984 <[^>]*> 418d7022 	mttc1	t5,\$f14
+0+0988 <[^>]*> 418d7023 	cttc1	t5,\$14
+0+098c <[^>]*> 418d7024 	mttc2	t5,\$14
+0+0990 <[^>]*> 418d7025 	cttc2	t5,\$14
+0+0994 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
+0+0998 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
+0+099c <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
+0+09a0 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
+0+09a4 <[^>]*> 418d7032 	mtthc1	t5,\$f14
+0+09a8 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
+0+09ac <[^>]*> 418d7034 	mtthc2	t5,\$14
+0+09b0 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
+0+09b4 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
+0+09b8 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-mt.l b/gas/testsuite/gas/mips/mips32-mt.l
deleted file mode 100644
index a3f32f27de12..000000000000
--- a/gas/testsuite/gas/mips/mips32-mt.l
+++ /dev/null
@@ -1,257 +0,0 @@
-.*: Assembler messages:
-.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:576: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:577: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:578: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:579: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:580: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:581: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:582: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:583: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:584: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:585: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:586: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:587: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:588: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:589: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:590: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:591: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:592: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:592: Warning: MT immediate not in range 0..1 \(2\)
-.*:593: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:593: Warning: MT immediate not in range 0..1 \(2\)
-.*:594: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:594: Warning: MT immediate not in range 0..1 \(2\)
-.*:595: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:595: Warning: MT immediate not in range 0..1 \(2\)
-.*:596: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:596: Warning: MT immediate not in range 0..1 \(2\)
-.*:597: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:597: Warning: MT immediate not in range 0..1 \(2\)
-.*:598: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:598: Warning: MT immediate not in range 0..1 \(2\)
-.*:599: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:599: Warning: MT immediate not in range 0..1 \(2\)
-.*:600: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:601: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:602: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:603: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:604: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:605: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:606: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:607: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:624: Warning: MT immediate not in range 0..1 \(2\)
-.*:625: Warning: MT immediate not in range 0..1 \(2\)
-.*:626: Warning: MT immediate not in range 0..1 \(2\)
-.*:627: Warning: MT immediate not in range 0..1 \(2\)
-.*:628: Warning: MT immediate not in range 0..1 \(2\)
-.*:629: Warning: MT immediate not in range 0..1 \(2\)
-.*:630: Warning: MT immediate not in range 0..1 \(2\)
-.*:631: Warning: MT immediate not in range 0..1 \(2\)
-.*:632: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:633: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:634: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:635: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:636: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:637: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:638: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:639: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:656: Warning: MT immediate not in range 0..1 \(2\)
-.*:657: Warning: MT immediate not in range 0..1 \(2\)
-.*:658: Warning: MT immediate not in range 0..1 \(2\)
-.*:659: Warning: MT immediate not in range 0..1 \(2\)
-.*:660: Warning: MT immediate not in range 0..1 \(2\)
-.*:661: Warning: MT immediate not in range 0..1 \(2\)
-.*:662: Warning: MT immediate not in range 0..1 \(2\)
-.*:663: Warning: MT immediate not in range 0..1 \(2\)
-.*:664: Warning: MT immediate not in range 0..1 \(2\)
-.*:664: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:665: Warning: MT immediate not in range 0..1 \(2\)
-.*:665: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:666: Warning: MT immediate not in range 0..1 \(2\)
-.*:666: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:667: Warning: MT immediate not in range 0..1 \(2\)
-.*:667: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:668: Warning: MT immediate not in range 0..1 \(2\)
-.*:668: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:669: Warning: MT immediate not in range 0..1 \(2\)
-.*:669: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:670: Warning: MT immediate not in range 0..1 \(2\)
-.*:670: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:671: Warning: MT immediate not in range 0..1 \(2\)
-.*:671: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:672: Warning: MT immediate not in range 0..1 \(2\)
-.*:673: Warning: MT immediate not in range 0..1 \(2\)
-.*:674: Warning: MT immediate not in range 0..1 \(2\)
-.*:675: Warning: MT immediate not in range 0..1 \(2\)
-.*:676: Warning: MT immediate not in range 0..1 \(2\)
-.*:677: Warning: MT immediate not in range 0..1 \(2\)
-.*:678: Warning: MT immediate not in range 0..1 \(2\)
-.*:679: Warning: MT immediate not in range 0..1 \(2\)
-.*:680: Warning: MT immediate not in range 0..1 \(2\)
-.*:681: Warning: MT immediate not in range 0..1 \(2\)
-.*:682: Warning: MT immediate not in range 0..1 \(2\)
-.*:683: Warning: MT immediate not in range 0..1 \(2\)
-.*:684: Warning: MT immediate not in range 0..1 \(2\)
-.*:685: Warning: MT immediate not in range 0..1 \(2\)
-.*:686: Warning: MT immediate not in range 0..1 \(2\)
-.*:687: Warning: MT immediate not in range 0..1 \(2\)
-.*:688: Warning: MT immediate not in range 0..1 \(2\)
-.*:688: Warning: MT immediate not in range 0..1 \(2\)
-.*:689: Warning: MT immediate not in range 0..1 \(2\)
-.*:689: Warning: MT immediate not in range 0..1 \(2\)
-.*:690: Warning: MT immediate not in range 0..1 \(2\)
-.*:690: Warning: MT immediate not in range 0..1 \(2\)
-.*:691: Warning: MT immediate not in range 0..1 \(2\)
-.*:691: Warning: MT immediate not in range 0..1 \(2\)
-.*:692: Warning: MT immediate not in range 0..1 \(2\)
-.*:692: Warning: MT immediate not in range 0..1 \(2\)
-.*:693: Warning: MT immediate not in range 0..1 \(2\)
-.*:693: Warning: MT immediate not in range 0..1 \(2\)
-.*:694: Warning: MT immediate not in range 0..1 \(2\)
-.*:694: Warning: MT immediate not in range 0..1 \(2\)
-.*:695: Warning: MT immediate not in range 0..1 \(2\)
-.*:695: Warning: MT immediate not in range 0..1 \(2\)
-.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:704: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:705: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:706: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:707: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:708: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:709: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:710: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:711: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:712: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:713: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:714: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:715: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:716: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:717: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:718: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:719: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:720: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:720: Warning: MT immediate not in range 0..1 \(2\)
-.*:721: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:721: Warning: MT immediate not in range 0..1 \(2\)
-.*:722: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:722: Warning: MT immediate not in range 0..1 \(2\)
-.*:723: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:723: Warning: MT immediate not in range 0..1 \(2\)
-.*:724: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:724: Warning: MT immediate not in range 0..1 \(2\)
-.*:725: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:725: Warning: MT immediate not in range 0..1 \(2\)
-.*:726: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:726: Warning: MT immediate not in range 0..1 \(2\)
-.*:727: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:727: Warning: MT immediate not in range 0..1 \(2\)
-.*:728: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:729: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:730: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:731: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:732: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:733: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:734: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:735: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:752: Warning: MT immediate not in range 0..1 \(2\)
-.*:753: Warning: MT immediate not in range 0..1 \(2\)
-.*:754: Warning: MT immediate not in range 0..1 \(2\)
-.*:755: Warning: MT immediate not in range 0..1 \(2\)
-.*:756: Warning: MT immediate not in range 0..1 \(2\)
-.*:757: Warning: MT immediate not in range 0..1 \(2\)
-.*:758: Warning: MT immediate not in range 0..1 \(2\)
-.*:759: Warning: MT immediate not in range 0..1 \(2\)
-.*:760: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:761: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:762: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:763: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:764: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:765: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:766: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:767: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:784: Warning: MT immediate not in range 0..1 \(2\)
-.*:785: Warning: MT immediate not in range 0..1 \(2\)
-.*:786: Warning: MT immediate not in range 0..1 \(2\)
-.*:787: Warning: MT immediate not in range 0..1 \(2\)
-.*:788: Warning: MT immediate not in range 0..1 \(2\)
-.*:789: Warning: MT immediate not in range 0..1 \(2\)
-.*:790: Warning: MT immediate not in range 0..1 \(2\)
-.*:791: Warning: MT immediate not in range 0..1 \(2\)
-.*:792: Warning: MT immediate not in range 0..1 \(2\)
-.*:792: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:793: Warning: MT immediate not in range 0..1 \(2\)
-.*:793: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:794: Warning: MT immediate not in range 0..1 \(2\)
-.*:794: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:795: Warning: MT immediate not in range 0..1 \(2\)
-.*:795: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:796: Warning: MT immediate not in range 0..1 \(2\)
-.*:796: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:797: Warning: MT immediate not in range 0..1 \(2\)
-.*:797: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:798: Warning: MT immediate not in range 0..1 \(2\)
-.*:798: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:799: Warning: MT immediate not in range 0..1 \(2\)
-.*:799: Warning: MT immediate not in range 0..1 \([0-9]*\)
-.*:800: Warning: MT immediate not in range 0..1 \(2\)
-.*:801: Warning: MT immediate not in range 0..1 \(2\)
-.*:802: Warning: MT immediate not in range 0..1 \(2\)
-.*:803: Warning: MT immediate not in range 0..1 \(2\)
-.*:804: Warning: MT immediate not in range 0..1 \(2\)
-.*:805: Warning: MT immediate not in range 0..1 \(2\)
-.*:806: Warning: MT immediate not in range 0..1 \(2\)
-.*:807: Warning: MT immediate not in range 0..1 \(2\)
-.*:808: Warning: MT immediate not in range 0..1 \(2\)
-.*:809: Warning: MT immediate not in range 0..1 \(2\)
-.*:810: Warning: MT immediate not in range 0..1 \(2\)
-.*:811: Warning: MT immediate not in range 0..1 \(2\)
-.*:812: Warning: MT immediate not in range 0..1 \(2\)
-.*:813: Warning: MT immediate not in range 0..1 \(2\)
-.*:814: Warning: MT immediate not in range 0..1 \(2\)
-.*:815: Warning: MT immediate not in range 0..1 \(2\)
-.*:816: Warning: MT immediate not in range 0..1 \(2\)
-.*:816: Warning: MT immediate not in range 0..1 \(2\)
-.*:817: Warning: MT immediate not in range 0..1 \(2\)
-.*:817: Warning: MT immediate not in range 0..1 \(2\)
-.*:818: Warning: MT immediate not in range 0..1 \(2\)
-.*:818: Warning: MT immediate not in range 0..1 \(2\)
-.*:819: Warning: MT immediate not in range 0..1 \(2\)
-.*:819: Warning: MT immediate not in range 0..1 \(2\)
-.*:820: Warning: MT immediate not in range 0..1 \(2\)
-.*:820: Warning: MT immediate not in range 0..1 \(2\)
-.*:821: Warning: MT immediate not in range 0..1 \(2\)
-.*:821: Warning: MT immediate not in range 0..1 \(2\)
-.*:822: Warning: MT immediate not in range 0..1 \(2\)
-.*:822: Warning: MT immediate not in range 0..1 \(2\)
-.*:823: Warning: MT immediate not in range 0..1 \(2\)
-.*:823: Warning: MT immediate not in range 0..1 \(2\)
diff --git a/gas/testsuite/gas/mips/mips32-mt.s b/gas/testsuite/gas/mips/mips32-mt.s
index a3d8eeda0de3..8363256c6834 100644
--- a/gas/testsuite/gas/mips/mips32-mt.s
+++ b/gas/testsuite/gas/mips/mips32-mt.s
@@ -565,46 +565,6 @@ text_label:
 	mttc2		$10,$11
 	mtthc2		$11,$12
 	cttc2		$12,$13
-	mftr		$13,$14,-1,0,-1
-	mftr		$13,$14,-1,1,-1
-	mftr		$13,$14,-1,2,-1
-	mftr		$13,$14,-1,3,-1
-	mftr		$13,$14,-1,4,-1
-	mftr		$13,$14,-1,5,-1
-	mftr		$13,$14,-1,6,-1
-	mftr		$13,$14,-1,7,-1
-	mftr		$13,$14,-1,0,0
-	mftr		$13,$14,-1,1,0
-	mftr		$13,$14,-1,2,0
-	mftr		$13,$14,-1,3,0
-	mftr		$13,$14,-1,4,0
-	mftr		$13,$14,-1,5,0
-	mftr		$13,$14,-1,6,0
-	mftr		$13,$14,-1,7,0
-	mftr		$13,$14,-1,0,1
-	mftr		$13,$14,-1,1,1
-	mftr		$13,$14,-1,2,1
-	mftr		$13,$14,-1,3,1
-	mftr		$13,$14,-1,4,1
-	mftr		$13,$14,-1,5,1
-	mftr		$13,$14,-1,6,1
-	mftr		$13,$14,-1,7,1
-	mftr		$13,$14,-1,0,2
-	mftr		$13,$14,-1,1,2
-	mftr		$13,$14,-1,2,2
-	mftr		$13,$14,-1,3,2
-	mftr		$13,$14,-1,4,2
-	mftr		$13,$14,-1,5,2
-	mftr		$13,$14,-1,6,2
-	mftr		$13,$14,-1,7,2
-	mftr		$13,$14,0,0,-1
-	mftr		$13,$14,0,1,-1
-	mftr		$13,$14,0,2,-1
-	mftr		$13,$14,0,3,-1
-	mftr		$13,$14,0,4,-1
-	mftr		$13,$14,0,5,-1
-	mftr		$13,$14,0,6,-1
-	mftr		$13,$14,0,7,-1
 	mftr		$13,$14,0,0,0
 	mftr		$13,$14,0,1,0
 	mftr		$13,$14,0,2,0
@@ -621,22 +581,6 @@ text_label:
 	mftr		$13,$14,0,5,1
 	mftr		$13,$14,0,6,1
 	mftr		$13,$14,0,7,1
-	mftr		$13,$14,0,0,2
-	mftr		$13,$14,0,1,2
-	mftr		$13,$14,0,2,2
-	mftr		$13,$14,0,3,2
-	mftr		$13,$14,0,4,2
-	mftr		$13,$14,0,5,2
-	mftr		$13,$14,0,6,2
-	mftr		$13,$14,0,7,2
-	mftr		$13,$14,1,0,-1
-	mftr		$13,$14,1,1,-1
-	mftr		$13,$14,1,2,-1
-	mftr		$13,$14,1,3,-1
-	mftr		$13,$14,1,4,-1
-	mftr		$13,$14,1,5,-1
-	mftr		$13,$14,1,6,-1
-	mftr		$13,$14,1,7,-1
 	mftr		$13,$14,1,0,0
 	mftr		$13,$14,1,1,0
 	mftr		$13,$14,1,2,0
@@ -653,86 +597,6 @@ text_label:
 	mftr		$13,$14,1,5,1
 	mftr		$13,$14,1,6,1
 	mftr		$13,$14,1,7,1
-	mftr		$13,$14,1,0,2
-	mftr		$13,$14,1,1,2
-	mftr		$13,$14,1,2,2
-	mftr		$13,$14,1,3,2
-	mftr		$13,$14,1,4,2
-	mftr		$13,$14,1,5,2
-	mftr		$13,$14,1,6,2
-	mftr		$13,$14,1,7,2
-	mftr		$13,$14,2,0,-1
-	mftr		$13,$14,2,1,-1
-	mftr		$13,$14,2,2,-1
-	mftr		$13,$14,2,3,-1
-	mftr		$13,$14,2,4,-1
-	mftr		$13,$14,2,5,-1
-	mftr		$13,$14,2,6,-1
-	mftr		$13,$14,2,7,-1
-	mftr		$13,$14,2,0,0
-	mftr		$13,$14,2,1,0
-	mftr		$13,$14,2,2,0
-	mftr		$13,$14,2,3,0
-	mftr		$13,$14,2,4,0
-	mftr		$13,$14,2,5,0
-	mftr		$13,$14,2,6,0
-	mftr		$13,$14,2,7,0
-	mftr		$13,$14,2,0,1
-	mftr		$13,$14,2,1,1
-	mftr		$13,$14,2,2,1
-	mftr		$13,$14,2,3,1
-	mftr		$13,$14,2,4,1
-	mftr		$13,$14,2,5,1
-	mftr		$13,$14,2,6,1
-	mftr		$13,$14,2,7,1
-	mftr		$13,$14,2,0,2
-	mftr		$13,$14,2,1,2
-	mftr		$13,$14,2,2,2
-	mftr		$13,$14,2,3,2
-	mftr		$13,$14,2,4,2
-	mftr		$13,$14,2,5,2
-	mftr		$13,$14,2,6,2
-	mftr		$13,$14,2,7,2
-	mttr		$13,$14,-1,0,-1
-	mttr		$13,$14,-1,1,-1
-	mttr		$13,$14,-1,2,-1
-	mttr		$13,$14,-1,3,-1
-	mttr		$13,$14,-1,4,-1
-	mttr		$13,$14,-1,5,-1
-	mttr		$13,$14,-1,6,-1
-	mttr		$13,$14,-1,7,-1
-	mttr		$13,$14,-1,0,0
-	mttr		$13,$14,-1,1,0
-	mttr		$13,$14,-1,2,0
-	mttr		$13,$14,-1,3,0
-	mttr		$13,$14,-1,4,0
-	mttr		$13,$14,-1,5,0
-	mttr		$13,$14,-1,6,0
-	mttr		$13,$14,-1,7,0
-	mttr		$13,$14,-1,0,1
-	mttr		$13,$14,-1,1,1
-	mttr		$13,$14,-1,2,1
-	mttr		$13,$14,-1,3,1
-	mttr		$13,$14,-1,4,1
-	mttr		$13,$14,-1,5,1
-	mttr		$13,$14,-1,6,1
-	mttr		$13,$14,-1,7,1
-	mttr		$13,$14,-1,0,2
-	mttr		$13,$14,-1,1,2
-	mttr		$13,$14,-1,2,2
-	mttr		$13,$14,-1,3,2
-	mttr		$13,$14,-1,4,2
-	mttr		$13,$14,-1,5,2
-	mttr		$13,$14,-1,6,2
-	mttr		$13,$14,-1,7,2
-	mttr		$13,$14,0,0,-1
-	mttr		$13,$14,0,1,-1
-	mttr		$13,$14,0,2,-1
-	mttr		$13,$14,0,3,-1
-	mttr		$13,$14,0,4,-1
-	mttr		$13,$14,0,5,-1
-	mttr		$13,$14,0,6,-1
-	mttr		$13,$14,0,7,-1
 	mttr		$13,$14,0,0,0
 	mttr		$13,$14,0,1,0
 	mttr		$13,$14,0,2,0
@@ -749,22 +613,6 @@ text_label:
 	mttr		$13,$14,0,5,1
 	mttr		$13,$14,0,6,1
 	mttr		$13,$14,0,7,1
-	mttr		$13,$14,0,0,2
-	mttr		$13,$14,0,1,2
-	mttr		$13,$14,0,2,2
-	mttr		$13,$14,0,3,2
-	mttr		$13,$14,0,4,2
-	mttr		$13,$14,0,5,2
-	mttr		$13,$14,0,6,2
-	mttr		$13,$14,0,7,2
-	mttr		$13,$14,1,0,-1
-	mttr		$13,$14,1,1,-1
-	mttr		$13,$14,1,2,-1
-	mttr		$13,$14,1,3,-1
-	mttr		$13,$14,1,4,-1
-	mttr		$13,$14,1,5,-1
-	mttr		$13,$14,1,6,-1
-	mttr		$13,$14,1,7,-1
 	mttr		$13,$14,1,0,0
 	mttr		$13,$14,1,1,0
 	mttr		$13,$14,1,2,0
@@ -781,46 +629,6 @@ text_label:
 	mttr		$13,$14,1,5,1
 	mttr		$13,$14,1,6,1
 	mttr		$13,$14,1,7,1
-	mttr		$13,$14,1,0,2
-	mttr		$13,$14,1,1,2
-	mttr		$13,$14,1,2,2
-	mttr		$13,$14,1,3,2
-	mttr		$13,$14,1,4,2
-	mttr		$13,$14,1,5,2
-	mttr		$13,$14,1,6,2
-	mttr		$13,$14,1,7,2
-	mttr		$13,$14,2,0,-1
-	mttr		$13,$14,2,1,-1
-	mttr		$13,$14,2,2,-1
-	mttr		$13,$14,2,3,-1
-	mttr		$13,$14,2,4,-1
-	mttr		$13,$14,2,5,-1
-	mttr		$13,$14,2,6,-1
-	mttr		$13,$14,2,7,-1
-	mttr		$13,$14,2,0,0
-	mttr		$13,$14,2,1,0
-	mttr		$13,$14,2,2,0
-	mttr		$13,$14,2,3,0
-	mttr		$13,$14,2,4,0
-	mttr		$13,$14,2,5,0
-	mttr		$13,$14,2,6,0
-	mttr		$13,$14,2,7,0
-	mttr		$13,$14,2,0,1
-	mttr		$13,$14,2,1,1
-	mttr		$13,$14,2,2,1
-	mttr		$13,$14,2,3,1
-	mttr		$13,$14,2,4,1
-	mttr		$13,$14,2,5,1
-	mttr		$13,$14,2,6,1
-	mttr		$13,$14,2,7,1
-	mttr		$13,$14,2,0,2
-	mttr		$13,$14,2,1,2
-	mttr		$13,$14,2,2,2
-	mttr		$13,$14,2,3,2
-	mttr		$13,$14,2,4,2
-	mttr		$13,$14,2,5,2
-	mttr		$13,$14,2,6,2
-	mttr		$13,$14,2,7,2
 
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
 	.space	8
diff --git a/gas/testsuite/gas/mips/mips32-sf32.d b/gas/testsuite/gas/mips/mips32-sf32.d
new file mode 100644
index 000000000000..4de9844d2615
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-sf32.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS32 odd single-precision float registers
+#as: -32 
+
+# Check MIPS32 instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 3c013f80 	lui	\$1,0x3f80
+0+0004 <[^>]*> 44810800 	mtc1	\$1,\$f1
+0+0008 <[^>]*> c783c000 	lwc1	\$f3,-16384\(\$28\)
+			8: R_MIPS_LITERAL	\.lit4\+0x4000
+0+000c <[^>]*> 46030940 	add.s	\$f5,\$f1,\$f3
+0+0010 <[^>]*> 46003a21 	cvt.d.s	\$f8,\$f7
+0+0014 <[^>]*> 46803a21 	cvt.d.w	\$f8,\$f7
+0+0018 <[^>]*> 462041e0 	cvt.s.d	\$f7,\$f8
+0+001c <[^>]*> 462041cd 	trunc.w.d	\$f7,\$f8
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-sf32.s b/gas/testsuite/gas/mips/mips32-sf32.s
new file mode 100644
index 000000000000..68b7e4ea7603
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-sf32.s
@@ -0,0 +1,14 @@
+
+	.text
+func:
+	.set noreorder
+	li.s	$f1, 1.0	
+	li.s	$f3, 1.9	
+	add.s	$f5, $f1, $f3
+	cvt.d.s	$f8,$f7
+	cvt.d.w	$f8,$f7
+	cvt.s.d	$f7,$f8
+	trunc.w.d $f7,$f8
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8
diff --git a/gas/testsuite/gas/mips/mips32.d b/gas/testsuite/gas/mips/mips32.d
index cb226d8f43b0..14693fc84ecc 100644
--- a/gas/testsuite/gas/mips/mips32.d
+++ b/gas/testsuite/gas/mips/mips32.d
@@ -38,19 +38,37 @@ Disassembly of section .text:
 0+0070 <[^>]*> bc250000 	cache	0x5,0\(at\)
 0+0074 <[^>]*> bc457fff 	cache	0x5,32767\(v0\)
 0+0078 <[^>]*> bc658000 	cache	0x5,-32768\(v1\)
-0+007c <[^>]*> 42000018 	eret
-0+0080 <[^>]*> 42000008 	tlbp
-0+0084 <[^>]*> 42000001 	tlbr
-0+0088 <[^>]*> 42000002 	tlbwi
-0+008c <[^>]*> 42000006 	tlbwr
-0+0090 <[^>]*> 42000020 	wait
-0+0094 <[^>]*> 42000020 	wait
-0+0098 <[^>]*> 4359e260 	wait	0x56789
-0+009c <[^>]*> 0000000d 	break
-0+00a0 <[^>]*> 0000000d 	break
-0+00a4 <[^>]*> 0345000d 	break	0x345
-0+00a8 <[^>]*> 0048d14d 	break	0x48,0x345
-0+00ac <[^>]*> 7000003f 	sdbbp
-0+00b0 <[^>]*> 7000003f 	sdbbp
-0+00b4 <[^>]*> 7159e27f 	sdbbp	0x56789
-	...
+0+007c <[^>]*> 3c010001 	lui	at,0x1
+0+0080 <[^>]*> 00240821 	addu	at,at,a0
+0+0084 <[^>]*> bc258000 	cache	0x5,-32768\(at\)
+0+0088 <[^>]*> 3c01ffff 	lui	at,0xffff
+0+008c <[^>]*> 00250821 	addu	at,at,a1
+0+0090 <[^>]*> bc257fff 	cache	0x5,32767\(at\)
+0+0094 <[^>]*> 3c010001 	lui	at,0x1
+0+0098 <[^>]*> bc258000 	cache	0x5,-32768\(at\)
+0+009c <[^>]*> 3c01ffff 	lui	at,0xffff
+0+00a0 <[^>]*> bc257fff 	cache	0x5,32767\(at\)
+0+00a4 <[^>]*> 42000018 	eret
+0+00a8 <[^>]*> 42000008 	tlbp
+0+00ac <[^>]*> 42000001 	tlbr
+0+00b0 <[^>]*> 42000002 	tlbwi
+0+00b4 <[^>]*> 42000006 	tlbwr
+0+00b8 <[^>]*> 42000020 	wait
+0+00bc <[^>]*> 42000020 	wait
+0+00c0 <[^>]*> 4359e260 	wait	0x56789
+0+00c4 <[^>]*> 0000000d 	break
+0+00c8 <[^>]*> 0000000d 	break
+0+00cc <[^>]*> 0345000d 	break	0x345
+0+00d0 <[^>]*> 0048d14d 	break	0x48,0x345
+0+00d4 <[^>]*> 7000003f 	sdbbp
+0+00d8 <[^>]*> 7000003f 	sdbbp
+0+00dc <[^>]*> 7159e27f 	sdbbp	0x56789
+0+00e0 <[^>]*> 4900ffc7 	bc2f	0+0000 <text_label>
+0+00e4 <[^>]*> 00000000 	nop
+0+00e8 <[^>]*> 4906ffc5 	bc2fl	\$cc1,0+0000 <text_label>
+0+00ec <[^>]*> 00000000 	nop
+0+00f0 <[^>]*> 4919ffc3 	bc2t	\$cc6,0+0000 <text_label>
+0+00f4 <[^>]*> 00000000 	nop
+0+00f8 <[^>]*> 491fffc1 	bc2tl	\$cc7,0+0000 <text_label>
+0+00fc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s
index b3fb6fe13bf6..f54265805439 100644
--- a/gas/testsuite/gas/mips/mips32.s
+++ b/gas/testsuite/gas/mips/mips32.s
@@ -49,6 +49,12 @@ text_label:
       cache   5, ($1)
       cache   5, 32767($2)
       cache   5, -32768($3)
+      .set at
+      cache   5, 32768($4)
+      cache   5, -32769($5)
+      cache   5, 32768
+      cache   5, -32769
+      .set noat
       eret
       tlbp
       tlbr
@@ -73,5 +79,15 @@ text_label:
       sdbbp   0                       # disassembles without code
       sdbbp   0x56789
 
+      # Cop2 branches with cond code number, like bc1t/f
+      bc2f    $cc0,text_label
+      nop
+      bc2fl   $cc1,text_label
+      nop
+      bc2t    $cc6,text_label
+      nop
+      bc2tl   $cc7,text_label
+      nop
+
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
       .space  8
diff --git a/gas/testsuite/gas/mips/mips4.d b/gas/testsuite/gas/mips/mips4.d
index bc3e924948d3..1dfcb3983d1a 100644
--- a/gas/testsuite/gas/mips/mips4.d
+++ b/gas/testsuite/gas/mips/mips4.d
@@ -21,7 +21,7 @@ Disassembly of section .text:
 0+0030 <[^>]*> ldxc1	\$f2,a0\(a1\)
 0+0034 <[^>]*> lwxc1	\$f2,a0\(a1\)
 0+0038 <[^>]*> madd.d	\$f0,\$f2,\$f4,\$f6
-0+003c <[^>]*> madd.s	\$f0,\$f2,\$f4,\$f6
+0+003c <[^>]*> madd.s	\$f10,\$f8,\$f2,\$f0
 0+0040 <[^>]*> movf	a0,a1,\$fcc4
 0+0044 <[^>]*> movf.d	\$f4,\$f6,\$fcc0
 0+0048 <[^>]*> movf.s	\$f4,\$f6,\$fcc0
@@ -40,11 +40,12 @@ Disassembly of section .text:
 0+007c <[^>]*> nmadd.s	\$f0,\$f2,\$f4,\$f6
 0+0080 <[^>]*> nmsub.d	\$f0,\$f2,\$f4,\$f6
 0+0084 <[^>]*> nmsub.s	\$f0,\$f2,\$f4,\$f6
-0+0088 <[^>]*> prefx	0x4,a0\(a1\)
-0+008c <[^>]*> recip.d	\$f4,\$f6
-0+0090 <[^>]*> recip.s	\$f4,\$f6
-0+0094 <[^>]*> rsqrt.d	\$f4,\$f6
-0+0098 <[^>]*> rsqrt.s	\$f4,\$f6
-0+009c <[^>]*> sdxc1	\$f4,a0\(a1\)
-0+00a0 <[^>]*> swxc1	\$f4,a0\(a1\)
+0+0088 <[^>]*> pref	0x4,0\(a0\)
+0+008c <[^>]*> prefx	0x4,a0\(a1\)
+0+0090 <[^>]*> recip.d	\$f4,\$f6
+0+0094 <[^>]*> recip.s	\$f4,\$f6
+0+0098 <[^>]*> rsqrt.d	\$f4,\$f6
+0+009c <[^>]*> rsqrt.s	\$f4,\$f6
+0+00a0 <[^>]*> sdxc1	\$f4,a0\(a1\)
+0+00a4 <[^>]*> swxc1	\$f4,a0\(a1\)
 	...
diff --git a/gas/testsuite/gas/mips/mips4.s b/gas/testsuite/gas/mips/mips4.s
index 591292bb6b34..d346c2af2b9f 100644
--- a/gas/testsuite/gas/mips/mips4.s
+++ b/gas/testsuite/gas/mips/mips4.s
@@ -11,7 +11,8 @@ text_label:
 	ldxc1	$f2,$4($5)
 	lwxc1	$f2,$4($5)
 	madd.d	$f0,$f2,$f4,$f6
-	madd.s	$f0,$f2,$f4,$f6
+	# This choice of arguments is so that it matches bc3f on pre-mips4.
+	madd.s	$f10,$f8,$f2,$f0
 	movf	$4,$5,$fcc4
 	movf.d	$f4,$f6,$fcc0
 	movf.s	$f4,$f6,$fcc0
@@ -30,14 +31,8 @@ text_label:
 	nmadd.s	$f0,$f2,$f4,$f6
 	nmsub.d	$f0,$f2,$f4,$f6
 	nmsub.s	$f0,$f2,$f4,$f6
-
-	# We don't test pref because currently the disassembler will
-	# disassemble it as lwc3.  lwc3 is correct for mips1 to mips3,
-	# while pref is correct for mips4.  Unfortunately, the
-	# disassembler does not know which architecture it is
-	# disassembling for.
-	# pref	4,0($4)
-
+	# It used to be disabled due to a clash with lwc3.
+	pref	4,0($4)
 	prefx	4,$4($5)
 	recip.d	$f4,$f6
 	recip.s	$f4,$f6
diff --git a/gas/testsuite/gas/mips/mips64-dsp.d b/gas/testsuite/gas/mips/mips64-dsp.d
new file mode 100644
index 000000000000..11009a012c52
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-dsp.d
@@ -0,0 +1,172 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=32
+#name: MIPS DSP ASE for MIPS64
+#as: -mdsp
+
+# Check MIPS DSP ASE for MIPS64 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c010456 	absq_s\.pw	zero,at
+0+0004 <[^>]*> 7c1ff256 	absq_s\.qh	s8,ra
+0+0008 <[^>]*> 7cc72c94 	addq\.pw	a1,a2,a3
+0+000c <[^>]*> 7ce83594 	addq_s\.pw	a2,a3,t0
+0+0010 <[^>]*> 7c641294 	addq\.qh	v0,v1,a0
+0+0014 <[^>]*> 7c851b94 	addq_s\.qh	v1,a0,a1
+0+0018 <[^>]*> 7d4b4814 	addu\.ob	t1,t2,t3
+0+001c <[^>]*> 7d6c5114 	addu_s\.ob	t2,t3,t4
+0+0020 <[^>]*> 041dfff7 	bposge64	00000000 <text_label>
+0+0024 <[^>]*> 00000000 	nop
+0+0028 <[^>]*> 7e950415 	cmp\.eq\.pw	s4,s5
+0+002c <[^>]*> 7eb60455 	cmp\.lt\.pw	s5,s6
+0+0030 <[^>]*> 7ed70495 	cmp\.le\.pw	s6,s7
+0+0034 <[^>]*> 7e320215 	cmp\.eq\.qh	s1,s2
+0+0038 <[^>]*> 7e530255 	cmp\.lt\.qh	s2,s3
+0+003c <[^>]*> 7e740295 	cmp\.le\.qh	s3,s4
+0+0040 <[^>]*> 7dcf0015 	cmpu\.eq\.ob	t6,t7
+0+0044 <[^>]*> 7df00055 	cmpu\.lt\.ob	t7,s0
+0+0048 <[^>]*> 7e110095 	cmpu\.le\.ob	s0,s1
+0+004c <[^>]*> 7d2a4115 	cmpgu\.eq\.ob	t0,t1,t2
+0+0050 <[^>]*> 7d4b4955 	cmpgu\.lt\.ob	t1,t2,t3
+0+0054 <[^>]*> 7d6c5195 	cmpgu\.le\.ob	t2,t3,t4
+0+0058 <[^>]*> 7c1f1abc 	dextpdp	ra,\$ac3,0x0
+0+005c <[^>]*> 7c3f1abc 	dextpdp	ra,\$ac3,0x1
+0+0060 <[^>]*> 7fff1abc 	dextpdp	ra,\$ac3,0x1f
+0+0064 <[^>]*> 7c2002fc 	dextpdpv	zero,\$ac0,at
+0+0068 <[^>]*> 7c1d08bc 	dextp	sp,\$ac1,0x0
+0+006c <[^>]*> 7c3d08bc 	dextp	sp,\$ac1,0x1
+0+0070 <[^>]*> 7ffd08bc 	dextp	sp,\$ac1,0x1f
+0+0074 <[^>]*> 7ffe10fc 	dextpv	s8,\$ac2,ra
+0+0078 <[^>]*> 7c031c3c 	dextr\.l	v1,\$ac3,0x0
+0+007c <[^>]*> 7c231c3c 	dextr\.l	v1,\$ac3,0x1
+0+0080 <[^>]*> 7fe31c3c 	dextr\.l	v1,\$ac3,0x1f
+0+0084 <[^>]*> 7c04053c 	dextr_r\.l	a0,\$ac0,0x0
+0+0088 <[^>]*> 7c24053c 	dextr_r\.l	a0,\$ac0,0x1
+0+008c <[^>]*> 7fe4053c 	dextr_r\.l	a0,\$ac0,0x1f
+0+0090 <[^>]*> 7c050dbc 	dextr_rs\.l	a1,\$ac1,0x0
+0+0094 <[^>]*> 7c250dbc 	dextr_rs\.l	a1,\$ac1,0x1
+0+0098 <[^>]*> 7fe50dbc 	dextr_rs\.l	a1,\$ac1,0x1f
+0+009c <[^>]*> 7c01093c 	dextr_r\.w	at,\$ac1,0x0
+0+00a0 <[^>]*> 7c21093c 	dextr_r\.w	at,\$ac1,0x1
+0+00a4 <[^>]*> 7fe1093c 	dextr_r\.w	at,\$ac1,0x1f
+0+00a8 <[^>]*> 7c0211bc 	dextr_rs\.w	v0,\$ac2,0x0
+0+00ac <[^>]*> 7c2211bc 	dextr_rs\.w	v0,\$ac2,0x1
+0+00b0 <[^>]*> 7fe211bc 	dextr_rs\.w	v0,\$ac2,0x1f
+0+00b4 <[^>]*> 7c0213bc 	dextr_s\.h	v0,\$ac2,0x0
+0+00b8 <[^>]*> 7c2213bc 	dextr_s\.h	v0,\$ac2,0x1
+0+00bc <[^>]*> 7fe213bc 	dextr_s\.h	v0,\$ac2,0x1f
+0+00c0 <[^>]*> 7c00003c 	dextr\.w	zero,\$ac0,0x0
+0+00c4 <[^>]*> 7c20003c 	dextr\.w	zero,\$ac0,0x1
+0+00c8 <[^>]*> 7fe0003c 	dextr\.w	zero,\$ac0,0x1f
+0+00cc <[^>]*> 7d8b187c 	dextrv\.w	t3,\$ac3,t4
+0+00d0 <[^>]*> 7dac017c 	dextrv_r\.w	t4,\$ac0,t5
+0+00d4 <[^>]*> 7dcd09fc 	dextrv_rs\.w	t5,\$ac1,t6
+0+00d8 <[^>]*> 7dee147c 	dextrv\.l	t6,\$ac2,t7
+0+00dc <[^>]*> 7e0f1d7c 	dextrv_r\.l	t7,\$ac3,s0
+0+00e0 <[^>]*> 7e3005fc 	dextrv_rs\.l	s0,\$ac0,s1
+0+00e4 <[^>]*> 7f7a000d 	dinsv	k0,k1
+0+00e8 <[^>]*> 7e950e74 	dmadd	\$ac1,s4,s5
+0+00ec <[^>]*> 7eb61774 	dmaddu	\$ac2,s5,s6
+0+00f0 <[^>]*> 7ed71ef4 	dmsub	\$ac3,s6,s7
+0+00f4 <[^>]*> 7ef807f4 	dmsubu	\$ac0,s7,t8
+0+00f8 <[^>]*> 7c8017fc 	dmthlip	a0,\$ac2
+0+00fc <[^>]*> 7c010b34 	dpaq_sa\.l\.pw	\$ac1,zero,at
+0+0100 <[^>]*> 7eb61134 	dpaq_s\.w\.qh	\$ac2,s5,s6
+0+0104 <[^>]*> 7df000f4 	dpau\.h\.obl	\$ac0,t7,s0
+0+0108 <[^>]*> 7e1109f4 	dpau\.h\.obr	\$ac1,s0,s1
+0+010c <[^>]*> 7c640374 	dpsq_sa\.l\.pw	\$ac0,v1,a0
+0+0110 <[^>]*> 7f190974 	dpsq_s\.w\.qh	\$ac1,t8,t9
+0+0114 <[^>]*> 7e3212f4 	dpsu\.h\.obl	\$ac2,s1,s2
+0+0118 <[^>]*> 7e531bf4 	dpsu\.h\.obr	\$ac3,s2,s3
+0+011c <[^>]*> 7e001ebc 	dshilo	\$ac3,-64
+0+0120 <[^>]*> 7df81ebc 	dshilo	\$ac3,63
+0+0124 <[^>]*> 7c4006fc 	dshilov	\$ac0,v0
+0+0128 <[^>]*> 7e51820a 	ldx	s0,s1\(s2\)
+0+012c <[^>]*> 7d4b1c34 	maq_sa\.w\.qhll	\$ac3,t2,t3
+0+0130 <[^>]*> 7d6c0474 	maq_sa\.w\.qhlr	\$ac0,t3,t4
+0+0134 <[^>]*> 7d8d0cb4 	maq_sa\.w\.qhrl	\$ac1,t4,t5
+0+0138 <[^>]*> 7dae14f4 	maq_sa\.w\.qhrr	\$ac2,t5,t6
+0+013c <[^>]*> 7e110f34 	maq_s\.l\.pwl	\$ac1,s0,s1
+0+0140 <[^>]*> 7e3217b4 	maq_s\.l\.pwr	\$ac2,s1,s2
+0+0144 <[^>]*> 7d4b1d34 	maq_s\.w\.qhll	\$ac3,t2,t3
+0+0148 <[^>]*> 7d6c0574 	maq_s\.w\.qhlr	\$ac0,t3,t4
+0+014c <[^>]*> 7d8d0db4 	maq_s\.w\.qhrl	\$ac1,t4,t5
+0+0150 <[^>]*> 7dae15f4 	maq_s\.w\.qhrr	\$ac2,t5,t6
+0+0154 <[^>]*> 7d8d5f14 	muleq_s\.pw\.qhl	t3,t4,t5
+0+0158 <[^>]*> 7dae6754 	muleq_s\.pw\.qhr	t4,t5,t6
+0+015c <[^>]*> 7ca62194 	muleu_s\.qh\.obl	a0,a1,a2
+0+0160 <[^>]*> 7cc729d4 	muleu_s\.qh\.obr	a1,a2,a3
+0+0164 <[^>]*> 7ce837d0 	mulq_rs\.ph	a2,a3,t0
+0+0168 <[^>]*> 7d2a47d4 	mulq_rs\.qh	t0,t1,t2
+0+016c <[^>]*> 7f7c01b4 	mulsaq_s\.w\.qh	\$ac0,k1,gp
+0+0170 <[^>]*> 7fbe13b4 	mulsaq_s\.l\.pw	\$ac2,sp,s8
+0+0174 <[^>]*> 7fbee395 	packrl\.pw	gp,sp,s8
+0+0178 <[^>]*> 7f5bc8d5 	pick\.ob	t9,k0,k1
+0+017c <[^>]*> 7f7cd2d5 	pick\.qh	k0,k1,gp
+0+0180 <[^>]*> 7f9ddcd5 	pick\.pw	k1,gp,sp
+0+0184 <[^>]*> 7c0f7316 	preceq\.pw\.qhl	t6,t7
+0+0188 <[^>]*> 7c107b56 	preceq\.pw\.qhr	t7,s0
+0+018c <[^>]*> 7c118396 	preceq\.pw\.qhla	s0,s1
+0+0190 <[^>]*> 7c128bd6 	preceq\.pw\.qhra	s1,s2
+0+0194 <[^>]*> 7c139516 	preceq\.s\.l\.pwl	s2,s3
+0+0198 <[^>]*> 7c149d56 	preceq\.s\.l\.pwr	s3,s4
+0+019c <[^>]*> 7c19c116 	precequ\.pw\.qhl	t8,t9
+0+01a0 <[^>]*> 7c1ac956 	precequ\.pw\.qhr	t9,k0
+0+01a4 <[^>]*> 7c1bd196 	precequ\.pw\.qhla	k0,k1
+0+01a8 <[^>]*> 7c1cd9d6 	precequ\.pw\.qhra	k1,gp
+0+01ac <[^>]*> 7c1de716 	preceu\.qh\.obl	gp,sp
+0+01b0 <[^>]*> 7c1eef56 	preceu\.qh\.obr	sp,s8
+0+01b4 <[^>]*> 7c1ff796 	preceu\.qh\.obla	s8,ra
+0+01b8 <[^>]*> 7c00ffd6 	preceu\.qh\.obra	ra,zero
+0+01bc <[^>]*> 7ca62315 	precrq\.ob\.qh	a0,a1,a2
+0+01c0 <[^>]*> 7d093f15 	precrq\.pw\.l	a3,t0,t1
+0+01c4 <[^>]*> 7cc72d15 	precrq\.qh\.pw	a1,a2,a3
+0+01c8 <[^>]*> 7ce83555 	precrq_rs\.qh\.pw	a2,a3,t0
+0+01cc <[^>]*> 7d4b4bd5 	precrqu_s\.ob\.qh	t1,t2,t3
+0+01d0 <[^>]*> 7f60d514 	raddu\.l\.ob	k0,k1
+0+01d4 <[^>]*> 7c00e896 	repl\.ob	sp,0x0
+0+01d8 <[^>]*> 7cffe896 	repl\.ob	sp,0xff
+0+01dc <[^>]*> 7c1ff0d6 	replv\.ob	s8,ra
+0+01e0 <[^>]*> 7e000a96 	repl\.qh	at,-512
+0+01e4 <[^>]*> 7dff0a96 	repl\.qh	at,511
+0+01e8 <[^>]*> 7c0312d6 	replv\.qh	v0,v1
+0+01ec <[^>]*> 7e001c96 	repl\.pw	v1,-512
+0+01f0 <[^>]*> 7dff1c96 	repl\.pw	v1,511
+0+01f4 <[^>]*> 7c0524d6 	replv\.pw	a0,a1
+0+01f8 <[^>]*> 7c031017 	shll\.ob	v0,v1,0x0
+0+01fc <[^>]*> 7ce31017 	shll\.ob	v0,v1,0x7
+0+0200 <[^>]*> 7ca41897 	shllv\.ob	v1,a0,a1
+0+0204 <[^>]*> 7c094217 	shll\.qh	t0,t1,0x0
+0+0208 <[^>]*> 7de94217 	shll\.qh	t0,t1,0xf
+0+020c <[^>]*> 7d6a4a97 	shllv\.qh	t1,t2,t3
+0+0210 <[^>]*> 7c0b5317 	shll_s\.qh	t2,t3,0x0
+0+0214 <[^>]*> 7deb5317 	shll_s\.qh	t2,t3,0xf
+0+0218 <[^>]*> 7dac5b97 	shllv_s\.qh	t3,t4,t5
+0+021c <[^>]*> 7c0f7417 	shll\.pw	t6,t7,0x0
+0+0220 <[^>]*> 7fef7417 	shll\.pw	t6,t7,0x1f
+0+0224 <[^>]*> 7e307c97 	shllv\.pw	t7,s0,s1
+0+0228 <[^>]*> 7c118517 	shll_s\.pw	s0,s1,0x0
+0+022c <[^>]*> 7ff18517 	shll_s\.pw	s0,s1,0x1f
+0+0230 <[^>]*> 7e728d97 	shllv_s\.pw	s1,s2,s3
+0+0234 <[^>]*> 7c1de257 	shra\.qh	gp,sp,0x0
+0+0238 <[^>]*> 7dfde257 	shra\.qh	gp,sp,0xf
+0+023c <[^>]*> 7ffeead7 	shrav\.qh	sp,s8,ra
+0+0240 <[^>]*> 7c1ff357 	shra_r\.qh	s8,ra,0x0
+0+0244 <[^>]*> 7dfff357 	shra_r\.qh	s8,ra,0xf
+0+0248 <[^>]*> 7c20fbd7 	shrav_r\.qh	ra,zero,at
+0+024c <[^>]*> 7c010457 	shra\.pw	zero,at,0x0
+0+0250 <[^>]*> 7fe10457 	shra\.pw	zero,at,0x1f
+0+0254 <[^>]*> 7c620cd7 	shrav\.pw	at,v0,v1
+0+0258 <[^>]*> 7c031557 	shra_r\.pw	v0,v1,0x0
+0+025c <[^>]*> 7fe31557 	shra_r\.pw	v0,v1,0x1f
+0+0260 <[^>]*> 7ca41dd7 	shrav_r\.pw	v1,a0,a1
+0+0264 <[^>]*> 7c15a057 	shrl\.ob	s4,s5,0x0
+0+0268 <[^>]*> 7cf5a057 	shrl\.ob	s4,s5,0x7
+0+026c <[^>]*> 7ef6a8d7 	shrlv\.ob	s5,s6,s7
+0+0270 <[^>]*> 7e3282d4 	subq\.qh	s0,s1,s2
+0+0274 <[^>]*> 7e538bd4 	subq_s\.qh	s1,s2,s3
+0+0278 <[^>]*> 7e7494d4 	subq\.pw	s2,s3,s4
+0+027c <[^>]*> 7e959dd4 	subq_s\.pw	s3,s4,s5
+0+0280 <[^>]*> 7eb6a054 	subu\.ob	s4,s5,s6
+0+0284 <[^>]*> 7ed7a954 	subu_s\.ob	s5,s6,s7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips64-dsp.s b/gas/testsuite/gas/mips/mips64-dsp.s
new file mode 100644
index 000000000000..b372e651bbc8
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips64-dsp.s
@@ -0,0 +1,174 @@
+# source file to test assembly of MIPS DSP ASE for MIPS64 instructions
+
+	.set noreorder
+	.set nomacro
+	.set noat
+
+	.text
+text_label:
+
+	absq_s.pw	$0,$1
+	absq_s.qh	$30,$31
+	addq.pw		$5,$6,$7
+	addq_s.pw	$6,$7,$8
+	addq.qh		$2,$3,$4
+	addq_s.qh	$3,$4,$5
+	addu.ob		$9,$10,$11
+	addu_s.ob	$10,$11,$12
+	bposge64	text_label
+	nop
+	cmp.eq.pw	$20,$21
+	cmp.lt.pw	$21,$22
+	cmp.le.pw	$22,$23
+	cmp.eq.qh	$17,$18
+	cmp.lt.qh	$18,$19
+	cmp.le.qh	$19,$20
+	cmpu.eq.ob	$14,$15
+	cmpu.lt.ob	$15,$16
+	cmpu.le.ob	$16,$17
+	cmpgu.eq.ob	$8,$9,$10
+	cmpgu.lt.ob	$9,$10,$11
+	cmpgu.le.ob	$10,$11,$12
+	dextpdp		$31,$ac3,0
+	dextpdp		$31,$ac3,1
+	dextpdp		$31,$ac3,31
+	dextpdpv	$0,$ac0,$1
+	dextp		$29,$ac1,0
+	dextp		$29,$ac1,1
+	dextp		$29,$ac1,31
+	dextpv		$30,$ac2,$31
+	dextr.l		$3,$ac3,0
+	dextr.l		$3,$ac3,1
+	dextr.l		$3,$ac3,31
+	dextr_r.l	$4,$ac0,0
+	dextr_r.l	$4,$ac0,1
+	dextr_r.l	$4,$ac0,31
+	dextr_rs.l	$5,$ac1,0
+	dextr_rs.l	$5,$ac1,1
+	dextr_rs.l	$5,$ac1,31
+	dextr_r.w	$1,$ac1,0
+	dextr_r.w	$1,$ac1,1
+	dextr_r.w	$1,$ac1,31
+	dextr_rs.w	$2,$ac2,0
+	dextr_rs.w	$2,$ac2,1
+	dextr_rs.w	$2,$ac2,31
+	dextr_s.h	$2,$ac2,0
+	dextr_s.h	$2,$ac2,1
+	dextr_s.h	$2,$ac2,31
+	dextr.w		$0,$ac0,0
+	dextr.w		$0,$ac0,1
+	dextr.w		$0,$ac0,31
+	dextrv.w	$11,$ac3,$12
+	dextrv_r.w	$12,$ac0,$13
+	dextrv_rs.w	$13,$ac1,$14
+	dextrv.l	$14,$ac2,$15
+	dextrv_r.l	$15,$ac3,$16
+	dextrv_rs.l	$16,$ac0,$17
+	dinsv		$26,$27
+	dmadd		$ac1,$20,$21
+	dmaddu		$ac2,$21,$22
+	dmsub		$ac3,$22,$23
+	dmsubu		$ac0,$23,$24
+	dmthlip		$4,$ac2
+	dpaq_sa.l.pw	$ac1,$0,$1
+	dpaq_s.w.qh	$ac2,$21,$22
+	dpau.h.obl	$ac0,$15,$16
+	dpau.h.obr	$ac1,$16,$17
+	dpsq_sa.l.pw	$ac0,$3,$4
+	dpsq_s.w.qh	$ac1,$24,$25
+	dpsu.h.obl	$ac2,$17,$18
+	dpsu.h.obr	$ac3,$18,$19
+	dshilo		$ac3,-64
+	dshilo		$ac3,63
+	dshilov		$ac0,$2
+	ldx		$16,$17($18)
+	maq_sa.w.qhll	$ac3,$10,$11
+	maq_sa.w.qhlr	$ac0,$11,$12
+	maq_sa.w.qhrl	$ac1,$12,$13
+	maq_sa.w.qhrr	$ac2,$13,$14
+	maq_s.l.pwl	$ac1,$16,$17
+	maq_s.l.pwr	$ac2,$17,$18
+	maq_s.w.qhll	$ac3,$10,$11
+	maq_s.w.qhlr	$ac0,$11,$12
+	maq_s.w.qhrl	$ac1,$12,$13
+	maq_s.w.qhrr	$ac2,$13,$14
+	muleq_s.pw.qhl	$11,$12,$13
+	muleq_s.pw.qhr	$12,$13,$14
+	muleu_s.qh.obl	$4,$5,$6
+	muleu_s.qh.obr	$5,$6,$7
+	mulq_rs.ph	$6,$7,$8
+	mulq_rs.qh	$8,$9,$10
+	mulsaq_s.w.qh	$ac0,$27,$28
+	mulsaq_s.l.pw	$ac2,$29,$30
+	packrl.pw	$28,$29,$30
+	pick.ob		$25,$26,$27
+	pick.qh		$26,$27,$28
+	pick.pw		$27,$28,$29
+	preceq.pw.qhl	$14,$15
+	preceq.pw.qhr	$15,$16
+	preceq.pw.qhla	$16,$17
+	preceq.pw.qhra	$17,$18
+	preceq.s.l.pwl	$18,$19
+	preceq.s.l.pwr	$19,$20
+	precequ.pw.qhl	$24,$25
+	precequ.pw.qhr	$25,$26
+	precequ.pw.qhla	$26,$27
+	precequ.pw.qhra	$27,$28
+	preceu.qh.obl	$28,$29
+	preceu.qh.obr	$29,$30
+	preceu.qh.obla	$30,$31
+	preceu.qh.obra	$31,$0
+	precrq.ob.qh	$4,$5,$6
+	precrq.pw.l	$7,$8,$9
+	precrq.qh.pw	$5,$6,$7
+	precrq_rs.qh.pw	$6,$7,$8
+	precrqu_s.ob.qh	$9,$10,$11
+	raddu.l.ob	$26,$27
+	repl.ob		$29,0
+	repl.ob		$29,255
+	replv.ob	$30,$31
+	repl.qh		$1,-512
+	repl.qh		$1,511
+	replv.qh	$2,$3
+	repl.pw		$3,-512
+	repl.pw		$3,511
+	replv.pw	$4,$5
+	shll.ob		$2,$3,0
+	shll.ob		$2,$3,7
+	shllv.ob	$3,$4,$5
+	shll.qh		$8,$9,0
+	shll.qh		$8,$9,15
+	shllv.qh	$9,$10,$11
+	shll_s.qh	$10,$11,0
+	shll_s.qh	$10,$11,15
+	shllv_s.qh	$11,$12,$13
+	shll.pw		$14,$15,0
+	shll.pw		$14,$15,31
+	shllv.pw	$15,$16,$17
+	shll_s.pw	$16,$17,0
+	shll_s.pw	$16,$17,31
+	shllv_s.pw	$17,$18,$19
+	shra.qh		$28,$29,0
+	shra.qh		$28,$29,15
+	shrav.qh	$29,$30,$31
+	shra_r.qh	$30,$31,0
+	shra_r.qh	$30,$31,15
+	shrav_r.qh	$31,$0,$1
+	shra.pw		$0,$1,0
+	shra.pw		$0,$1,31
+	shrav.pw	$1,$2,$3
+	shra_r.pw	$2,$3,0
+	shra_r.pw	$2,$3,31
+	shrav_r.pw	$3,$4,$5
+	shrl.ob		$20,$21,0
+	shrl.ob		$20,$21,7
+	shrlv.ob	$21,$22,$23
+	subq.qh		$16,$17,$18
+	subq_s.qh	$17,$18,$19
+	subq.pw		$18,$19,$20
+	subq_s.pw	$19,$20,$21
+	subu.ob		$20,$21,$22
+	subu_s.ob	$21,$22,$23
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8
diff --git a/gas/testsuite/gas/mips/noreorder.d b/gas/testsuite/gas/mips/noreorder.d
new file mode 100644
index 000000000000..0866ca018314
--- /dev/null
+++ b/gas/testsuite/gas/mips/noreorder.d
@@ -0,0 +1,23 @@
+#objdump: -dr --disassemble-zeroes
+#as: -march=mips2 -mabi=32
+#name: noreorder test
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+00000000 <per_cpu_trap_init>:
+   0:	00000000 	nop
+   4:	00000000 	nop
+   8:	0c000000 	jal	0 <per_cpu_trap_init>
+			8: R_MIPS_26	cpu_cache_init
+   c:	00000000 	nop
+  10:	8fbf0010 	lw	ra,16\(sp\)
+  14:	08000000 	j	0 <per_cpu_trap_init>
+			14: R_MIPS_26	tlb_init
+  18:	27bd0018 	addiu	sp,sp,24
+  1c:	00000000 	nop
+  20:	00000000 	nop
+  24:	1000fff6 	b	0 <per_cpu_trap_init>
+  28:	00000000 	nop
+  2c:	00000000 	nop
diff --git a/gas/testsuite/gas/mips/noreorder.s b/gas/testsuite/gas/mips/noreorder.s
new file mode 100644
index 000000000000..71e92efacf21
--- /dev/null
+++ b/gas/testsuite/gas/mips/noreorder.s
@@ -0,0 +1,25 @@
+	.text
+	.globl	per_cpu_trap_init
+	.ent	per_cpu_trap_init
+	.type	per_cpu_trap_init, @function
+per_cpu_trap_init:
+$L807:
+	nop
+	nop
+	# Removing this .align make the code assemble correctly
+	.align	3
+	jal	cpu_cache_init
+	lw	$31,16($sp)
+	.set	noreorder
+	j	tlb_init
+	addiu	$sp,$sp,24
+	# Replacing this .word with a nop causes the code to be assembled corrrectly
+	.word	0
+	# Removing this nop causes the code to be compiled correctly
+	nop
+	.set	reorder					
+
+	b	$L807
+	.end	per_cpu_trap_init
+
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/set-arch.d b/gas/testsuite/gas/mips/set-arch.d
index 66e52654b9e0..7639adb2822f 100644
--- a/gas/testsuite/gas/mips/set-arch.d
+++ b/gas/testsuite/gas/mips/set-arch.d
@@ -168,9 +168,9 @@ Disassembly of section \.text:
 00000280 <[^>]*> 000000c0 	sll	zero,zero,0x3
 00000284 <[^>]*> 7ca43980 	0x7ca43980
 00000288 <[^>]*> 7ca46984 	0x7ca46984
-0000028c <[^>]*> 0100fc09 	0x100fc09
-00000290 <[^>]*> 0120a409 	0x120a409
-00000294 <[^>]*> 01000408 	0x1000408
+0000028c <[^>]*> 0100fc09 	jalr.hb	t0
+00000290 <[^>]*> 0120a409 	jalr.hb	s4,t1
+00000294 <[^>]*> 01000408 	jr.hb	t0
 00000298 <[^>]*> 7c0a003b 	0x7c0a003b
 0000029c <[^>]*> 7c0b083b 	0x7c0b083b
 000002a0 <[^>]*> 7c0c103b 	0x7c0c103b
@@ -334,7 +334,7 @@ Disassembly of section \.text:
 00000518 <[^>]*> 48a41018 	0x48a41018
 0000051c <[^>]*> 4984101f 	0x4984101f
 00000520 <[^>]*> 49c4101f 	0x49c4101f
-00000524 <[^>]*> 4904101f 	0x4904101f
+00000524 <[^>]*> 4904101f 	bc2f	\$cc1,000045a4 <[^>]*>
 00000528 <[^>]*> 4944101f 	0x4944101f
 0000052c <[^>]*> 48c62090 	0x48c62090
 00000530 <[^>]*> 4bce3110 	c2	0x1ce3110
diff --git a/gas/testsuite/gas/mips/smartmips.d b/gas/testsuite/gas/mips/smartmips.d
new file mode 100644
index 000000000000..8bff68285d49
--- /dev/null
+++ b/gas/testsuite/gas/mips/smartmips.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: SmartMIPS
+#as: -msmartmips -32
+
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <[^>]*> 00c52046 	rorv	\$4,\$5,\$6
+0+0004 <[^>]*> 00c52046 	rorv	\$4,\$5,\$6
+0+0008 <[^>]*> 00c52046 	rorv	\$4,\$5,\$6
+0+000c <[^>]*> 00c52046 	rorv	\$4,\$5,\$6
+0+0010 <[^>]*> 002527c2 	ror	\$4,\$5,0x1f
+0+0014 <[^>]*> 00252202 	ror	\$4,\$5,0x8
+0+0018 <[^>]*> 00252042 	ror	\$4,\$5,0x1
+0+001c <[^>]*> 00252002 	ror	\$4,\$5,0x0
+0+0020 <[^>]*> 002527c2 	ror	\$4,\$5,0x1f
+0+0024 <[^>]*> 00252042 	ror	\$4,\$5,0x1
+0+0028 <[^>]*> 00252602 	ror	\$4,\$5,0x18
+0+002c <[^>]*> 002527c2 	ror	\$4,\$5,0x1f
+0+0030 <[^>]*> 00252002 	ror	\$4,\$5,0x0
+0+0034 <[^>]*> 70a41088 	lwxs	\$2,\$4\(\$5\)
+0+0038 <[^>]*> 72110441 	maddp	\$16,\$17
+0+003c <[^>]*> 016c0459 	multp	\$11,\$12
+0+0040 <[^>]*> 00004052 	mflhxu	\$8
+0+0044 <[^>]*> 00800053 	mtlhx	\$4
+0+0048 <[^>]*> 70d80481 	pperm	\$6,\$24
+0+004c <[^>]*> 00000000 	nop
diff --git a/gas/testsuite/gas/mips/smartmips.s b/gas/testsuite/gas/mips/smartmips.s
new file mode 100644
index 000000000000..00e9895bd013
--- /dev/null
+++ b/gas/testsuite/gas/mips/smartmips.s
@@ -0,0 +1,31 @@
+# Source file used to test SmartMIPS instruction set
+	
+	.text
+stuff:
+	ror	$4,$5,$6
+	rorv	$4,$5,$6
+	rotr	$4,$5,$6
+	rotrv	$4,$5,$6
+	
+	ror	$4,$5,31
+	ror	$4,$5,8
+	ror	$4,$5,1
+	ror	$4,$5,0
+	rotr	$4,$5,31
+	
+	rol	$4,$5,31
+	rol	$4,$5,8
+	rol	$4,$5,1
+	rol	$4,$5,0
+	
+	lwxs	$2,$4($5)
+	
+	maddp	$16,$17
+	multp	$11,$12
+	
+	mflhxu	$8
+	mtlhx	$4
+	
+	pperm	$6,$24
+
+	.p2align 4
diff --git a/gas/testsuite/gas/mmix/bspec-1.d b/gas/testsuite/gas/mmix/bspec-1.d
index 2b15a4c443d0..c648a02f676d 100644
--- a/gas/testsuite/gas/mmix/bspec-1.d
+++ b/gas/testsuite/gas/mmix/bspec-1.d
@@ -23,4 +23,5 @@ Hex dump of section '\.text':
   0x0+ fd010203                            .*
 
 Hex dump of section '\.MMIX\.spec_data\.2':
+ NOTE: This section has relocations against it, but these have NOT been applied to this dump.
   0x0+ 00000000                            .*
diff --git a/gas/testsuite/gas/mmix/bspec-2.d b/gas/testsuite/gas/mmix/bspec-2.d
index 04fdbdd5e5ff..73cf96c8b972 100644
--- a/gas/testsuite/gas/mmix/bspec-2.d
+++ b/gas/testsuite/gas/mmix/bspec-2.d
@@ -23,4 +23,5 @@ Hex dump of section '\.text':
   0x0+ fd010203                            .*
 
 Hex dump of section '\.MMIX\.spec_data\.2':
+ NOTE: This section has relocations against it, but these have NOT been applied to this dump.
   0x0+ 00000000 0000002a 00000000 00000000 .*
diff --git a/gas/testsuite/gas/mmix/comment-1.d b/gas/testsuite/gas/mmix/comment-1.d
index 142dca78fe8a..22ffdf5160a4 100644
--- a/gas/testsuite/gas/mmix/comment-1.d
+++ b/gas/testsuite/gas/mmix/comment-1.d
@@ -31,6 +31,7 @@ Symbol table '\.symtab' contains 12 entries:
     11: 0+     0 NOTYPE  GLOBAL DEFAULT  UND target3
 
 Hex dump of section '\.text':
+ NOTE: This section has relocations against it, but these have NOT been applied to this dump.
   0x0+ 0000007b 00010017 00010203 01030201 .*
   0x0+10 09050006 09070208 0509000a 050b030c .*
   0x0+20 230f1011 23121300 23141516 34170018 .*
diff --git a/gas/testsuite/gas/mmix/mmix-list.exp b/gas/testsuite/gas/mmix/mmix-list.exp
index 8d2a294f7c5b..e4a98d0cd80b 100644
--- a/gas/testsuite/gas/mmix/mmix-list.exp
+++ b/gas/testsuite/gas/mmix/mmix-list.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 2001 Free Software Foundation, Inc.
+# Copyright (C) 2001, 2007 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -18,24 +18,6 @@ if { ! [istarget "mmix-*"] } {
     return
 }
 
-proc run_list_test { name opts } {
-    global srcdir subdir runtests
-
-    if ![runtest_file_p $runtests $name] then {
-	return
-    }
-
-    set testname "mmix list $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
 proc run_mmix_list_tests { } {
     global srcdir subdir runtests
     foreach test_name [lsort [find ${srcdir}/${subdir} *.l]] {
diff --git a/gas/testsuite/gas/mn10300/basic.exp b/gas/testsuite/gas/mn10300/basic.exp
index b80e006cd215..37c1972738ff 100644
--- a/gas/testsuite/gas/mn10300/basic.exp
+++ b/gas/testsuite/gas/mn10300/basic.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1996, 2000, 2002, 2004 Free Software Foundation, Inc.
+# Copyright (C) 1996, 2000, 2002, 2004, 2007 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -1768,20 +1768,6 @@ proc do_am33_8 {} {
     if [expr $x==67] then { pass $testname } else { fail $testname }
 }
 
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "mn10300 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
-
 if [istarget mn10300*-*-*] then {
     # Test the basic instruction parser.
     do_add
diff --git a/gas/testsuite/gas/msp430/msp430.exp b/gas/testsuite/gas/msp430/msp430.exp
index a45ae4b630b5..c5e8052e0422 100644
--- a/gas/testsuite/gas/msp430/msp430.exp
+++ b/gas/testsuite/gas/msp430/msp430.exp
@@ -1,19 +1,6 @@
 #
 # msp430 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "msp430 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	exit
-	return
-    }
-    pass $testname
-}
 
 if [expr [istarget "msp430-*-*"]]  then {
     run_dump_test "opcode"
diff --git a/gas/testsuite/gas/pdp11/pdp11.exp b/gas/testsuite/gas/pdp11/pdp11.exp
index 9ee6435df12a..91ccddbb2ef2 100644
--- a/gas/testsuite/gas/pdp11/pdp11.exp
+++ b/gas/testsuite/gas/pdp11/pdp11.exp
@@ -1,19 +1,6 @@
 #
 # pdp11/pdp11 tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "pdp11 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	exit
-	return
-    }
-    pass $testname
-}
 
 if [expr [istarget "pdp11-*-*"]]  then {
 
diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index 56c7d5e3ae45..b07033f675e5 100644
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -142,11 +142,15 @@ Disassembly of section \.text:
  1c0:	7c 00 06 ac 	mbar    
  1c4:	7c 00 06 ac 	mbar    
  1c8:	7c 20 06 ac 	mbar    1
- 1cc:	7c 12 42 a6 	mfsprg  r0,2
- 1d0:	7c 12 42 a6 	mfsprg  r0,2
- 1d4:	7c 12 43 a6 	mtsprg  2,r0
- 1d8:	7c 12 43 a6 	mtsprg  2,r0
- 1dc:	7c 07 42 a6 	mfsprg  r0,7
- 1e0:	7c 07 42 a6 	mfsprg  r0,7
- 1e4:	7c 17 43 a6 	mtsprg  7,r0
- 1e8:	7c 17 43 a6 	mtsprg  7,r0
+ 1cc:	7d 8d 77 24 	tlbsx   r12,r13,r14
+ 1d0:	7d 8d 77 25 	tlbsx\.  r12,r13,r14
+ 1d4:	7d 8d 77 26 	tlbsxe  r12,r13,r14
+ 1d8:	7d 8d 77 27 	tlbsxe\. r12,r13,r14
+ 1dc:	7c 12 42 a6 	mfsprg  r0,2
+ 1e0:	7c 12 42 a6 	mfsprg  r0,2
+ 1e4:	7c 12 43 a6 	mtsprg  2,r0
+ 1e8:	7c 12 43 a6 	mtsprg  2,r0
+ 1ec:	7c 07 42 a6 	mfsprg  r0,7
+ 1f0:	7c 07 42 a6 	mfsprg  r0,7
+ 1f4:	7c 17 43 a6 	mtsprg  7,r0
+ 1f8:	7c 17 43 a6 	mtsprg  7,r0
diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s
index 0c6cf88f66a4..fa53c019b674 100644
--- a/gas/testsuite/gas/ppc/booke.s
+++ b/gas/testsuite/gas/ppc/booke.s
@@ -135,6 +135,11 @@ branch_target_8:
 	mbar	0
 	mbar	1
 
+	tlbsx	12, 13, 14
+	tlbsx.	12, 13, 14
+	tlbsxe	12, 13, 14
+	tlbsxe.	12, 13, 14
+
 	mfsprg 0, 2
 	mfsprg2 0
 	mtsprg 2, 0
diff --git a/gas/testsuite/gas/ppc/cell.d b/gas/testsuite/gas/ppc/cell.d
new file mode 100644
index 000000000000..799a8e09aba8
--- /dev/null
+++ b/gas/testsuite/gas/ppc/cell.d
@@ -0,0 +1,31 @@
+#as: -mcell
+#objdump: -dr -Mcell
+#name: Cell tests
+
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+   0:	7c 01 14 0e 	lvlx    v0,r1,r2
+   4:	7c 00 14 0e 	lvlx    v0,0,r2
+   8:	7c 01 16 0e 	lvlxl   v0,r1,r2
+   c:	7c 00 16 0e 	lvlxl   v0,0,r2
+  10:	7c 01 14 4e 	lvrx    v0,r1,r2
+  14:	7c 00 14 4e 	lvrx    v0,0,r2
+  18:	7c 01 16 4e 	lvrxl   v0,r1,r2
+  1c:	7c 00 16 4e 	lvrxl   v0,0,r2
+  20:	7c 01 15 0e 	stvlx   v0,r1,r2
+  24:	7c 00 15 0e 	stvlx   v0,0,r2
+  28:	7c 01 17 0e 	stvlxl  v0,r1,r2
+  2c:	7c 00 17 0e 	stvlxl  v0,0,r2
+  30:	7c 01 15 4e 	stvrx   v0,r1,r2
+  34:	7c 00 15 4e 	stvrx   v0,0,r2
+  38:	7c 01 17 4e 	stvrxl  v0,r1,r2
+  3c:	7c 00 17 4e 	stvrxl  v0,0,r2
+  40:	7c 00 0c 28 	ldbrx   r0,0,r1
+  44:	7c 01 14 28 	ldbrx   r0,r1,r2
+  48:	7c 00 0d 28 	stdbrx  r0,0,r1
+  4c:	7c 01 15 28 	stdbrx  r0,r1,r2
diff --git a/gas/testsuite/gas/ppc/cell.s b/gas/testsuite/gas/ppc/cell.s
new file mode 100644
index 000000000000..29853866147e
--- /dev/null
+++ b/gas/testsuite/gas/ppc/cell.s
@@ -0,0 +1,24 @@
+	.section	".text"
+	lvlx %r0, %r1, %r2
+	lvlx %r0, 0, %r2
+	lvlxl %r0, %r1, %r2
+	lvlxl %r0, 0, %r2
+	lvrx %r0, %r1, %r2
+	lvrx %r0, 0, %r2
+	lvrxl %r0, %r1, %r2
+	lvrxl %r0, 0, %r2
+
+	stvlx %r0, %r1, %r2
+	stvlx %r0, 0, %r2
+	stvlxl %r0, %r1, %r2
+	stvlxl %r0, 0, %r2
+	stvrx %r0, %r1, %r2
+	stvrx %r0, 0, %r2
+	stvrxl %r0, %r1, %r2
+	stvrxl %r0, 0, %r2
+
+	ldbrx %r0, 0, %r1
+	ldbrx %r0, %r1, %r2
+
+	stdbrx %r0, 0, %r1
+	stdbrx %r0, %r1, %r2
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 0dd4648f021d..0e2db22c66ee 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -11,6 +11,8 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
     run_dump_test "astest2_64"
     run_dump_test "test1elf64"
     run_dump_test "power4"
+    run_dump_test "cell"
+    run_list_test "range64" "-a64"
 } elseif { [istarget powerpc*-*aix*] } then {
     run_dump_test "test1xcoff32"
 } elseif { [istarget powerpc*-*-*bsd*] \
@@ -38,5 +40,6 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "altivec"
 	run_dump_test "booke"
 	run_dump_test "e500"
+	run_list_test "range" "-a32"
     }
 }
diff --git a/gas/testsuite/gas/ppc/range.l b/gas/testsuite/gas/ppc/range.l
new file mode 100644
index 000000000000..9a71ca4f88f3
--- /dev/null
+++ b/gas/testsuite/gas/ppc/range.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: operand out of range.*
+.*:7: Error: operand out of range.*
diff --git a/gas/testsuite/gas/ppc/range.s b/gas/testsuite/gas/ppc/range.s
new file mode 100644
index 000000000000..04251e5e93bf
--- /dev/null
+++ b/gas/testsuite/gas/ppc/range.s
@@ -0,0 +1,7 @@
+ .text
+ lbz 4,-32768(3)
+ lbz 5,-1(3)
+ lbz 6,2(3)
+ lbz 7,32767(3)
+ lbz 8,32768(3)
+ lbz 9,-32769(3)
diff --git a/gas/testsuite/gas/ppc/range64.l b/gas/testsuite/gas/ppc/range64.l
new file mode 100644
index 000000000000..6e28b7c7e9fc
--- /dev/null
+++ b/gas/testsuite/gas/ppc/range64.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*:3: Error: operand out of domain \(-1 is not a multiple of 4\)
+.*:4: Error: operand out of domain \(2 is not a multiple of 4\)
+.*:5: Error: operand out of range.*
+.*:6: Error: operand out of range.*
+.*:7: Error: operand out of range.*
diff --git a/gas/testsuite/gas/ppc/range64.s b/gas/testsuite/gas/ppc/range64.s
new file mode 100644
index 000000000000..b4a04cf76314
--- /dev/null
+++ b/gas/testsuite/gas/ppc/range64.s
@@ -0,0 +1,7 @@
+ .text
+ ld 4,-32768(3)
+ ld 5,-1(3)
+ ld 6,2(3)
+ ld 7,32767(3)
+ ld 8,32768(3)
+ ld 9,-32769(3)
diff --git a/gas/testsuite/gas/ppc/reloc.d b/gas/testsuite/gas/ppc/reloc.d
new file mode 100644
index 000000000000..006604b12b9c
--- /dev/null
+++ b/gas/testsuite/gas/ppc/reloc.d
@@ -0,0 +1,12 @@
+#readelf: -r --wide
+#name: reloc
+
+Relocation section '\.rela\.data' at .* contains 2 entries:
+ Offset     Info    Type                Sym\. Value  Symbol's Name \+ Addend
+0+08 .* R_PPC_ADDR32 .* y \+ f+fc
+0+0c .* R_PPC_ADDR32 .* y \+ 0
+
+Relocation section '\.rela\.data\.other' at .* contains 2 entries:
+ Offset     Info    Type                Sym\. Value  Symbol's Name \+ Addend
+0+00 .* R_PPC_ADDR32 .* x \+ 0
+0+04 .* R_PPC_ADDR32 .* x \+ f+fc
diff --git a/gas/testsuite/gas/ppc/reloc.s b/gas/testsuite/gas/ppc/reloc.s
new file mode 100644
index 000000000000..19e4355eb71f
--- /dev/null
+++ b/gas/testsuite/gas/ppc/reloc.s
@@ -0,0 +1,13 @@
+ .reloc x+8, R_PPC_ADDR32, y-4
+
+ .data
+x:
+ .long 0,0,0,0
+
+ .section .data.other,"aw",@progbits
+y:
+ .long 0,0,0,0
+
+ .reloc 0, R_PPC_ADDR32, x
+ .reloc y+4, R_PPC_ADDR32, x-4
+ .reloc x+12, R_PPC_ADDR32, y
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 0c38e419b82b..16021f6e93ef 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -104,9 +104,9 @@ Disassembly of section .text:
 .*:	b3 b4 00 69 [	 ]*cefr	%r6,%f9
 .*:	39 69 [	 ]*cer	%f6,%f9
 .*:	b2 1a 5f ff [	 ]*cfc	4095\(%r5\)
-.*:	b3 99 50 69 [	 ]*cfdbr	%f6,5,%r9
-.*:	b3 98 50 69 [	 ]*cfebr	%f6,5,%r9
-.*:	b3 9a 50 69 [	 ]*cfxbr	%f6,5,%r9
+.*:	b3 99 50 69 [	 ]*cfdbr	%r6,5,%f9
+.*:	b3 98 50 69 [	 ]*cfebr	%r6,5,%f9
+.*:	b3 9a 50 69 [	 ]*cfxbr	%r6,5,%f9
 .*:	49 65 af ff [	 ]*ch	%r6,4095\(%r5,%r10\)
 .*:	a7 6e 80 01 [	 ]*chi	%r6,-32767
 .*:	b2 41 00 69 [	 ]*cksm	%r6,%r9
@@ -341,7 +341,7 @@ Disassembly of section .text:
 .*:	b2 18 5f ff [	 ]*pc	4095\(%r5\)
 .*:	b2 2e 00 69 [	 ]*pgin	%r6,%r9
 .*:	b2 2f 00 69 [	 ]*pgout	%r6,%r9
-.*:	e9 ff 5f ff af ff [	 ]*pka	4095\(256,%r5\),4095\(%r10\)
+.*:	e9 1f 5f ff af ff [	 ]*pka	4095\(%r5\),4095\(32,%r10\)
 .*:	e1 ff 5f ff af ff [	 ]*pku	4095\(256,%r5\),4095\(%r10\)
 .*:	ee 69 5f ff af ff [	 ]*plo	%r6,4095\(%r5\),%r9,4095\(%r10\)
 .*:	01 01 [	 ]*pr
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index 314cbbb09640..3ff0b5343600 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -98,9 +98,9 @@ foo:
 	cefr	%r6,%f9
 	cer	%f6,%f9
 	cfc	4095(%r5)
-	cfdbr	%r6,5,%r9
-	cfebr	%r6,5,%r9
-	cfxbr	%r6,5,%r9
+	cfdbr	%r6,5,%f9
+	cfebr	%r6,5,%f9
+	cfxbr	%r6,5,%f9
 	ch	%r6,4095(%r5,%r10)
 	chi	%r6,-32767
 	cksm	%r6,%r9
@@ -335,7 +335,7 @@ foo:
 	pc	4095(%r5)
 	pgin	%r6,%r9
 	pgout	%r6,%r9
-	pka	4095(256,%r5),4095(%r10)
+	pka	4095(%r5),4095(32,%r10)
 	pku	4095(256,%r5),4095(%r10)
 	plo	%r6,4095(%r5),%r9,4095(%r10)
 	pr
diff --git a/gas/testsuite/gas/s390/operands.d b/gas/testsuite/gas/s390/operands.d
deleted file mode 100644
index d1744086ba26..000000000000
--- a/gas/testsuite/gas/s390/operands.d
+++ /dev/null
@@ -1,23 +0,0 @@
-#name: s390 operands
-#objdump: -dr
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-.* <foo>:
-   0:	01 01 [ 	]*pr
-   2:	a7 1a 80 01 [ 	]*ahi	%r1,-32767
-   6:	18 12 [ 	]*lr	%r1,%r2
-   8:	b2 5e 00 12 [ 	]*srst	%r1,%r2
-   c:	b3 5b 93 12 [ 	]*didbr	%f1,%f9,%f2,3
-  10:	ba 12 40 03 [ 	]*cs	%r1,%r2,3\(%r4\)
-  14:	84 12 00 00 [ 	]*brxh	%r1,%r2,14 <foo\+0x14>
-[ 	]*16: R_390_PC16DBL	test_rsi\+0x2
-  18:	58 13 40 02 [ 	]*l	%r1,2\(%r3,%r4\)
-  1c:	ed 10 30 02 00 1a [ 	]*adb	%f1,2\(%r3\)
-  22:	ed 24 50 03 10 1e [ 	]*madb	%f1,%f2,3\(%r4,%r5\)
-  28:	b2 33 20 01 [ 	]*ssch	1\(%r2\)
-  2c:	92 03 20 01 [ 	]*mvi	1\(%r2\),3
-  30:	d2 26 30 01 50 04 [ 	]*mvc	1\(39,%r3\),4\(%r5\)
-  36:	e5 01 20 01 40 03 [ 	]*tprot	1\(%r2\),3\(%r4\)
diff --git a/gas/testsuite/gas/s390/operands.s b/gas/testsuite/gas/s390/operands.s
deleted file mode 100644
index 9f030e835f75..000000000000
--- a/gas/testsuite/gas/s390/operands.s
+++ /dev/null
@@ -1,16 +0,0 @@
-.text
-foo:
-	.insn e,0x0101
-	.insn ri,0xa70a0000,%r1,-32767
-	.insn rr,0x1800,%r1,%r2
-	.insn rre,0xb25e0000,%r1,%r2
-	.insn rrf,0xb35b0000,%f1,%f2,9,%f3
-	.insn rs,0xba000000,%r1,%r2,3(%r4)
-	.insn rsi,0x84000000,%r1,%r2,test_rsi
-	.insn rx,0x58000000,%r1,2(%r3,%r4)
-	.insn rxe,0xed000000001a,%f1,2(%r3)
-	.insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5)
-	.insn s,0xb2330000,1(%r2)
-	.insn si,0x92000000,1(%r2),3
-	.insn ss,0xd20000000000,1(2,%r3),4(%r5),6
-	.insn sse,0xe50100000000,1(%r2),3(%r4)
diff --git a/gas/testsuite/gas/s390/operands64.d b/gas/testsuite/gas/s390/operands64.d
deleted file mode 100644
index 5cae0553e146..000000000000
--- a/gas/testsuite/gas/s390/operands64.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#name: s390x operands
-#objdump: -dr
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-.* <foo>:
-   0:	ec 12 00 00 00 45 [ 	]*brxlg	%r1,%r2,0 <foo>
-[ 	]*2: R_390_PC16DBL	test_rie\+0x2
-   6:	c0 e5 00 00 00 00 [ 	]*brasl	%r14,6 <foo\+0x6>
-[ 	]*8: R_390_PC32DBL	test_ril\+0x2
-   c:	eb 12 40 03 00 0d [ 	]*sllg	%r1,%r2,3\(%r4\)
-  12:	07 07 [ 	]*bcr	0,%r7
diff --git a/gas/testsuite/gas/s390/operands64.s b/gas/testsuite/gas/s390/operands64.s
deleted file mode 100644
index 6313cb275a00..000000000000
--- a/gas/testsuite/gas/s390/operands64.s
+++ /dev/null
@@ -1,6 +0,0 @@
-.text
-foo:
-	.insn rie,0xec0000000045,%r1,%r2,test_rie
-	.insn ril,0xc00500000000,%r14,test_ril
-	.insn rse,0xeb000000000d,%r1,%r2,3(%r4)
-	
diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp
index 3d9a4a135c80..8739bdd93272 100644
--- a/gas/testsuite/gas/s390/s390.exp
+++ b/gas/testsuite/gas/s390/s390.exp
@@ -1,19 +1,6 @@
 #
 # s390/s390x tests
 #
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "s390 $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	exit
-	return
-    }
-    pass $testname
-}
 
 if [expr [istarget "s390-*-*"] ||  [istarget "s390x-*-*"]]  then {
 
@@ -32,6 +19,7 @@ if [expr [istarget "s390-*-*"] ||  [istarget "s390x-*-*"]]  then {
     run_dump_test "zarch-z900" "{as -m64}"
     run_dump_test "zarch-z990" "{as -m64} {as -march=z990}"
     run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}"
+    run_dump_test "zarch-z9-ec" "{as -m64} {as -march=z9-ec}"
     run_dump_test "zarch-reloc" "{as -m64}"
     run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
 }
diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.d b/gas/testsuite/gas/s390/zarch-z9-ec.d
new file mode 100644
index 000000000000..142ec0db7506
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z9-ec.d
@@ -0,0 +1,76 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	b3 70 00 62 [	 ]*lpdfr	%f6,%f2
+.*:	b3 71 00 62 [	 ]*lndfr	%f6,%f2
+.*:	b3 72 10 62 [	 ]*cpsdr	%f6,%f1,%f2
+.*:	b3 73 00 62 [	 ]*lcdfr	%f6,%f2
+.*:	b3 c1 00 62 [	 ]*ldgr	%f6,%r2
+.*:	b3 cd 00 26 [	 ]*lgdr	%r2,%f6
+.*:	b3 d2 40 62 [	 ]*adtr	%f6,%f2,%f4
+.*:	b3 da 40 62 [	 ]*axtr	%f6,%f2,%f4
+.*:	b3 e4 00 62 [	 ]*cdtr	%f6,%f2
+.*:	b3 ec 00 62 [	 ]*cxtr	%f6,%f2
+.*:	b3 e0 00 62 [	 ]*kdtr	%f6,%f2
+.*:	b3 e8 00 62 [	 ]*kxtr	%f6,%f2
+.*:	b3 f4 00 62 [	 ]*cedtr	%f6,%f2
+.*:	b3 fc 00 62 [	 ]*cextr	%f6,%f2
+.*:	b3 f1 00 62 [	 ]*cdgtr	%f6,%r2
+.*:	b3 f9 00 62 [	 ]*cxgtr	%f6,%r2
+.*:	b3 f3 00 62 [	 ]*cdstr	%f6,%r2
+.*:	b3 fb 00 62 [	 ]*cxstr	%f6,%r2
+.*:	b3 f2 00 62 [	 ]*cdutr	%f6,%r2
+.*:	b3 fa 00 62 [	 ]*cxutr	%f6,%r2
+.*:	b3 e1 10 26 [	 ]*cgdtr	%r2,1,%f6
+.*:	b3 e9 10 26 [	 ]*cgxtr	%r2,1,%f6
+.*:	b3 e3 00 26 [	 ]*csdtr	%r2,%f6
+.*:	b3 eb 00 26 [	 ]*csxtr	%r2,%f6
+.*:	b3 e2 00 26 [	 ]*cudtr	%r2,%f6
+.*:	b3 ea 00 26 [	 ]*cuxtr	%r2,%f6
+.*:	b3 d1 40 62 [	 ]*ddtr	%f6,%f2,%f4
+.*:	b3 d9 40 62 [	 ]*dxtr	%f6,%f2,%f4
+.*:	b3 e5 00 26 [	 ]*eedtr	%r2,%f6
+.*:	b3 ed 00 26 [	 ]*eextr	%r2,%f6
+.*:	b3 e7 00 26 [	 ]*esdtr	%r2,%f6
+.*:	b3 ef 00 26 [	 ]*esxtr	%r2,%f6
+.*:	b3 f6 20 64 [	 ]*iedtr	%f6,%f2,%r4
+.*:	b3 fe 20 64 [	 ]*iextr	%f6,%f2,%r4
+.*:	b3 d6 00 62 [	 ]*ltdtr	%f6,%f2
+.*:	b3 de 00 62 [	 ]*ltxtr	%f6,%f2
+.*:	b3 d7 13 62 [	 ]*fidtr	%f6,1,%f2,3
+.*:	b3 df 13 62 [	 ]*fixtr	%f6,1,%f2,3
+.*:	b2 bd 10 03 [	 ]*lfas	3\(%r1\)
+.*:	b3 d4 01 62 [	 ]*ldetr	%f6,%f2,1
+.*:	b3 dc 01 62 [	 ]*lxdtr	%f6,%f2,1
+.*:	b3 d5 13 62 [	 ]*ledtr	%f6,1,%f2,3
+.*:	b3 dd 13 62 [	 ]*ldxtr	%f6,1,%f2,3
+.*:	b3 d0 40 62 [	 ]*mdtr	%f6,%f2,%f4
+.*:	b3 d8 40 62 [	 ]*mxtr	%f6,%f2,%f4
+.*:	b3 f5 21 64 [	 ]*qadtr	%f6,%f2,%f4,1
+.*:	b3 fd 21 64 [	 ]*qaxtr	%f6,%f2,%f4,1
+.*:	b3 f7 21 64 [	 ]*rrdtr	%f6,%f2,%f4,1
+.*:	b3 ff 21 64 [	 ]*rrxtr	%f6,%f2,%f4,1
+.*:	b2 b9 10 03 [	 ]*srnmt	3\(%r1\)
+.*:	b3 85 00 20 [	 ]*sfasr	%r2
+.*:	ed 21 40 03 60 40 [	 ]*sldt	%f6,%f2,3\(%r1,%r4\)
+.*:	ed 21 40 03 60 48 [	 ]*slxt	%f6,%f2,3\(%r1,%r4\)
+.*:	ed 21 40 03 60 41 [	 ]*srdt	%f6,%f2,3\(%r1,%r4\)
+.*:	ed 21 40 03 60 49 [	 ]*srxt	%f6,%f2,3\(%r1,%r4\)
+.*:	b3 d3 40 62 [	 ]*sdtr	%f6,%f2,%f4
+.*:	b3 db 40 62 [	 ]*sxtr	%f6,%f2,%f4
+.*:	ed 61 20 03 00 50 [	 ]*tcet	%f6,3\(%r1,%r2\)
+.*:	ed 61 20 03 00 54 [	 ]*tcdt	%f6,3\(%r1,%r2\)
+.*:	ed 61 20 03 00 58 [	 ]*tcxt	%f6,3\(%r1,%r2\)
+.*:	ed 61 20 03 00 51 [	 ]*tget	%f6,3\(%r1,%r2\)
+.*:	ed 61 20 03 00 55 [	 ]*tgdt	%f6,3\(%r1,%r2\)
+.*:	ed 61 20 03 00 59 [	 ]*tgxt	%f6,3\(%r1,%r2\)
+.*:	01 0a [	 ]*pfpo
+.*:	c8 31 10 0a 20 14 [	 ]*ectg	10\(%r1\),20\(%r2\),%r3
+.*:	c8 32 10 0a 20 14 [	 ]*csst	10\(%r1\),20\(%r2\),%r3
+# Expect 2 bytes of padding.
+.*:	07 07 [	 ]*bcr	0,%r7
diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.s b/gas/testsuite/gas/s390/zarch-z9-ec.s
new file mode 100644
index 000000000000..9139b7543a8a
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z9-ec.s
@@ -0,0 +1,72 @@
+.text
+foo:
+	lpdfr	%f6,%f2
+	lndfr	%f6,%f2
+	cpsdr	%f6,%f1,%f2
+	lcdfr	%f6,%f2
+	ldgr	%f6,%r2
+	lgdr	%r2,%f6
+	adtr	%f6,%f2,%f4
+	axtr	%f6,%f2,%f4
+	cdtr	%f6,%f2
+	cxtr	%f6,%f2
+	kdtr	%f6,%f2
+	kxtr	%f6,%f2
+	cedtr	%f6,%f2
+	cextr	%f6,%f2
+	cdgtr	%f6,%r2
+	cxgtr	%f6,%r2
+	cdstr	%f6,%r2
+	cxstr	%f6,%r2
+	cdutr	%f6,%r2
+	cxutr	%f6,%r2
+	cgdtr	%r2,1,%f6
+	cgxtr	%r2,1,%f6
+	csdtr	%r2,%f6
+	csxtr	%r2,%f6
+	cudtr	%r2,%f6
+	cuxtr	%r2,%f6
+	ddtr	%f6,%f2,%f4
+	dxtr	%f6,%f2,%f4
+	eedtr	%r2,%f6
+	eextr	%r2,%f6
+	esdtr	%r2,%f6
+	esxtr	%r2,%f6
+	iedtr	%f6,%f2,%r4
+	iextr	%f6,%f2,%r4
+	ltdtr	%f6,%f2
+	ltxtr	%f6,%f2
+	fidtr	%f6,1,%f2,3
+	fixtr	%f6,1,%f2,3
+	lfas	3(%r1)
+	ldetr	%f6,%f2,1
+	lxdtr	%f6,%f2,1
+	ledtr	%f6,1,%f2,3
+	ldxtr	%f6,1,%f2,3
+	mdtr	%f6,%f2,%f4
+	mxtr	%f6,%f2,%f4
+	qadtr	%f6,%f2,%f4,1
+	qaxtr	%f6,%f2,%f4,1
+	rrdtr	%f6,%f2,%f4,1
+	rrxtr	%f6,%f2,%f4,1
+	srnmt	3(%r1)
+	sfasr	%r2
+	sldt	%f6,%f2,3(%r1,%r4)
+	slxt	%f6,%f2,3(%r1,%r4)
+	srdt	%f6,%f2,3(%r1,%r4)
+	srxt	%f6,%f2,3(%r1,%r4)
+	sdtr	%f6,%f2,%f4
+	sxtr	%f6,%f2,%f4
+	tcet	%f6,3(%r1,%r2)
+	tcdt	%f6,3(%r1,%r2)
+	tcxt	%f6,3(%r1,%r2)
+	tget	%f6,3(%r1,%r2)
+	tgdt	%f6,3(%r1,%r2)
+	tgxt	%f6,3(%r1,%r2)
+	pfpo
+	ectg	10(%r1),20(%r2),%r3
+	csst	10(%r1),20(%r2),%r3
+	/* The following .data section is 4 byte aligned.
+	   So we get 2 additional bytes of 07 07 wherefor
+	   we have to provide an instruction.  */
+	bcr	0,%r7
diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d
index 0f701282acf9..dc21077dedfd 100644
--- a/gas/testsuite/gas/s390/zarch-z900.d
+++ b/gas/testsuite/gas/s390/zarch-z900.d
@@ -29,20 +29,20 @@ Disassembly of section .text:
 .*:	eb 96 5f ff 00 3e [ 	]*cdsg	%r9,%r6,4095\(%r5\)
 .*:	b3 a4 00 96 [ 	]*cegbr	%r9,%r6
 .*:	b3 c4 00 96 [ 	]*cegr	%r9,%r6
-.*:	b3 b9 90 65 [	 ]*cfdr	%f6,9,%r5
-.*:	b3 b8 90 65 [	 ]*cfer	%f6,9,%r5
-.*:	b3 ba 90 65 [	 ]*cfxr	%f6,9,%r5
+.*:	b3 b9 90 65 [	 ]*cfdr	%r6,9,%f5
+.*:	b3 b8 90 65 [	 ]*cfer	%r6,9,%f5
+.*:	b3 ba 90 65 [	 ]*cfxr	%r6,9,%f5
 .*:	e3 95 af ff 00 20 [ 	]*cg	%r9,4095\(%r5,%r10\)
-.*:	b3 a9 f0 65 [ 	]*cgdbr	%f6,15,%r5
-.*:	b3 c9 f0 65 [ 	]*cgdr	%f6,15,%r5
-.*:	b3 a8 f0 65 [ 	]*cgebr	%f6,15,%r5
-.*:	b3 c8 f0 65 [ 	]*cger	%f6,15,%r5
+.*:	b3 a9 f0 65 [ 	]*cgdbr	%r6,15,%f5
+.*:	b3 c9 f0 65 [ 	]*cgdr	%r6,15,%f5
+.*:	b3 a8 f0 65 [ 	]*cgebr	%r6,15,%f5
+.*:	b3 c8 f0 65 [ 	]*cger	%r6,15,%f5
 .*:	e3 95 af ff 00 30 [ 	]*cgf	%r9,4095\(%r5,%r10\)
 .*:	b9 30 00 96 [ 	]*cgfr	%r9,%r6
 .*:	a7 9f 80 01 [ 	]*cghi	%r9,-32767
 .*:	b9 20 00 96 [ 	]*cgr	%r9,%r6
-.*:	b3 aa f0 65 [ 	]*cgxbr	%f6,15,%r5
-.*:	b3 ca f0 65 [ 	]*cgxr	%f6,15,%r5
+.*:	b3 aa f0 65 [ 	]*cgxbr	%r6,15,%f5
+.*:	b3 ca f0 65 [ 	]*cgxr	%r6,15,%f5
 .*:	e3 95 af ff 00 21 [ 	]*clg	%r9,4095\(%r5,%r10\)
 .*:	e3 95 af ff 00 31 [ 	]*clgf	%r9,4095\(%r5,%r10\)
 .*:	b9 31 00 96 [ 	]*clgfr	%r9,%r6
diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s
index f5e737113c5e..688033a32e91 100644
--- a/gas/testsuite/gas/s390/zarch-z900.s
+++ b/gas/testsuite/gas/s390/zarch-z900.s
@@ -23,20 +23,20 @@ foo:
 	cdsg	%r9,%r6,4095(%r5)
 	cegbr	%r9,%r6
 	cegr	%r9,%r6
-	cfdr	%f6,9,%r5
-	cfer	%f6,9,%r5
-	cfxr	%f6,9,%r5
+	cfdr	%r6,9,%f5
+	cfer	%r6,9,%f5
+	cfxr	%r6,9,%f5
 	cg	%r9,4095(%r5,%r10)
-	cgdbr	%f6,15,%r5
-	cgdr	%f6,15,%r5
-	cgebr	%f6,15,%r5
-	cger	%f6,15,%r5
+	cgdbr	%r6,15,%f5
+	cgdr	%r6,15,%f5
+	cgebr	%r6,15,%f5
+	cger	%r6,15,%f5
 	cgf	%r9,4095(%r5,%r10)
 	cgfr	%r9,%r6
 	cghi	%r9,-32767
 	cgr	%r9,%r6
-	cgxbr	%f6,15,%r5
-	cgxr	%f6,15,%r5
+	cgxbr	%r6,15,%f5
+	cgxr	%r6,15,%f5
 	clg	%r9,4095(%r5,%r10)
 	clgf	%r9,4095(%r5,%r10)
 	clgfr	%r9,%r6
diff --git a/gas/testsuite/gas/score/addi.d b/gas/testsuite/gas/score/addi.d
new file mode 100644
index 000000000000..148ecd714339
--- /dev/null
+++ b/gas/testsuite/gas/score/addi.d
@@ -0,0 +1,33 @@
+#as:
+#objdump: -d
+#source: addi.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+   0:	84008003 	addi.c		r0, 1
+   4:	84008003 	addi.c		r0, 1
+   8:	85e08021 	addi.c		r15, 16
+   c:	85e08021 	addi.c		r15, 16
+  10:	85e18001 	addi.c		r15, 16384
+  14:	85e18001 	addi.c		r15, 16384
+  18:	6818      	addei!		r8, 3
+  1a:	6818      	addei!		r8, 3
+  1c:	6f78      	addei!		r15, 15
+  1e:	0000      	nop!
+  20:	85e1ffff 	addi.c		r15, 32767
+	...
+  30:	8403ffff 	addi.c		r0, -1
+  34:	8403ffff 	addi.c		r0, -1
+  38:	85e3ffe1 	addi.c		r15, -16
+  3c:	85e3ffe1 	addi.c		r15, -16
+  40:	85e38001 	addi.c		r15, -16384
+  44:	85e38001 	addi.c		r15, -16384
+  48:	6898      	subei!		r8, 3
+  4a:	6898      	subei!		r8, 3
+  4c:	6ff8      	subei!		r15, 15
+  4e:	0000      	nop!
+  50:	85e1ffff 	addi.c		r15, 32767
+#pass
diff --git a/gas/testsuite/gas/score/addi.s b/gas/testsuite/gas/score/addi.s
new file mode 100644
index 000000000000..e87620e5c590
--- /dev/null
+++ b/gas/testsuite/gas/score/addi.s
@@ -0,0 +1,37 @@
+/*
+ * test relax
+ * addi <-> addei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b
+ *   (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
+ *   (2)addei! rD, imm4 : rD = rD + 2**imm4
+ * addi <-> subei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b
+ *   (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
+ *   (2)subei! rD, imm4 : rD = rD + 2**imm4
+	
+ * Author: ligang
+ */
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16, sign
+.align 4
+	
+  \insn16 r0, 0                  #16b -> 32b
+  \insn32 r0, \sign * 1         
+
+  \insn16 r15, 4                 #16b -> 32b
+  \insn32 r15, \sign * 16
+
+  \insn16 r15, 14                #16b -> 32b
+  \insn32 r15, \sign * 1024 * 16
+
+  \insn16 r8, 3                  #No transform
+  \insn16 r8, 3                  #No transform
+
+  \insn16 r15, 15                #No transform. Because 2**15 = 32768, extend range of addi
+  \insn32 r15, 0x7FFF
+
+.endm
+
+.text
+
+  tran1632 "addi.c", "addei!", 1
+  tran1632 "addi.c", "subei!", -1
diff --git a/gas/testsuite/gas/score/b.d b/gas/testsuite/gas/score/b.d
new file mode 100644
index 000000000000..133540e4673d
--- /dev/null
+++ b/gas/testsuite/gas/score/b.d
@@ -0,0 +1,18 @@
+#as:
+#objdump: -d
+#source: b.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <L1>:
+   0:	4f00      	b!		0 <L1>
+   2:	4fff      	b!		0 <L1>
+   4:	4ffe      	b!		0 <L1>
+   6:	4ffd      	b!		0 <L1>
+   8:	4ffc      	b!		0 <L1>
+   a:	4ffb      	b!		0 <L1>
+   c:	93ffbff4 	b		0 <L1>
+  10:	8254e010 	add		r18, r20, r24
+#pass
diff --git a/gas/testsuite/gas/score/b.s b/gas/testsuite/gas/score/b.s
new file mode 100644
index 000000000000..002347c04f38
--- /dev/null
+++ b/gas/testsuite/gas/score/b.s
@@ -0,0 +1,30 @@
+/*
+ * test relax
+ * b <-> b! : jump range must be in 8 bit, only 32b -> 16b
+	
+ * Author: ligang
+ */
+
+.macro tran insn32, insn16
+/* This block transform 32b instruction to 16b. */
+.align 4
+
+  \insn32               #32b -> 16b
+  \insn16
+
+  \insn32               #32b -> 16b
+  \insn32               #32b -> 16b
+
+  \insn16      
+  \insn32               #32b -> 16b
+
+  \insn32               #No transform
+  add r18, r20, r24
+
+.endm
+
+L1:
+	
+  tran "b L1", "b! L1"
+  #tran "b 0x8", "b! 0x8"
+ 
diff --git a/gas/testsuite/gas/score/bittst.d b/gas/testsuite/gas/score/bittst.d
new file mode 100644
index 000000000000..0bb6651b30a3
--- /dev/null
+++ b/gas/testsuite/gas/score/bittst.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -d
+#source: bittst.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	6016      	bittst!		r0, 0x2
+   2:	6016      	bittst!		r0, 0x2
+   4:	6f26      	bittst!		r15, 0x4
+   6:	6f26      	bittst!		r15, 0x4
+   8:	6f0e      	bittst!		r15, 0x1
+   a:	6f0e      	bittst!		r15, 0x1
+   c:	6f1e      	bittst!		r15, 0x3
+   e:	6f1e      	bittst!		r15, 0x3
+  10:	6816      	bittst!		r8, 0x2
+  12:	6816      	bittst!		r8, 0x2
+  14:	800f842d 	bittst.c	r15, 0x1
+  18:	801a902d 	bittst.c	r26, 0x4
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	8000882d 	bittst.c	r0, 0x2
+  24:	8014882d 	bittst.c	r20, 0x2
+  28:	81ef902d 	bittst.c	r15, 0x4
+  2c:	8019902d 	bittst.c	r25, 0x4
+  30:	81ef842d 	bittst.c	r15, 0x1
+  34:	8019842d 	bittst.c	r25, 0x1
+  38:	680e      	bittst!		r8, 0x1
+  3a:	680e      	bittst!		r8, 0x1
+  3c:	6626      	bittst!		r6, 0x4
+  3e:	6626      	bittst!		r6, 0x4
+  40:	671e      	bittst!		r7, 0x3
+  42:	671e      	bittst!		r7, 0x3
+#pass
diff --git a/gas/testsuite/gas/score/bittst.s b/gas/testsuite/gas/score/bittst.s
new file mode 100644
index 000000000000..b6657b9a5d5d
--- /dev/null
+++ b/gas/testsuite/gas/score/bittst.s
@@ -0,0 +1,59 @@
+/*
+ * test relax
+ * bittst.c <-> bittst! : register number must be in 0-15
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+
+  \insn32 r0, 2         #32b -> 16b
+  \insn16 r0, 2
+
+  \insn32 r15, 4        #32b -> 16b
+  \insn16 r15, 4
+
+  \insn32 r15, 1        #32b -> 16b
+  \insn16 r15, 1
+
+  \insn16 r15, 3
+  \insn32 r15, 3        #32b -> 16b
+
+  \insn32 r8,  2        #32b -> 16b
+  \insn32 r8,  2        #32b -> 16b
+
+  \insn32 r15, 1        #No transform
+  \insn32 r26, 4
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, 2         #16b -> 32b
+  \insn32 r20, 2         
+
+  \insn16 r15, 4        #16b -> 32b
+  \insn32 r25, 4
+
+  \insn16 r15, 1        #16b -> 32b
+  \insn32 r25, 1
+
+  \insn16 r8, 1         #No transform
+  \insn16 r8, 1         #No transform
+	
+  \insn16 r6, 4         #No transform
+  \insn32 r6, 4         #32b -> 16b
+
+  \insn32 r7, 3         #32b -> 16b
+  \insn16 r7, 3         #No transform
+	
+.endm
+
+.text
+
+  tran3216 "bittst.c", "bittst!"
+  tran1632 "bittst.c", "bittst!"
+	
diff --git a/gas/testsuite/gas/score/br.d b/gas/testsuite/gas/score/br.d
new file mode 100644
index 000000000000..273632fbd03f
--- /dev/null
+++ b/gas/testsuite/gas/score/br.d
@@ -0,0 +1,49 @@
+#as:
+#objdump: -d
+#source: br.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+   0:	0f04      	br!		r0
+   2:	0f04      	br!		r0
+   4:	0ff4      	br!		r15
+   6:	0ff4      	br!		r15
+   8:	0f34      	br!		r3
+   a:	0f34      	br!		r3
+   c:	0f54      	br!		r5
+   e:	0f54      	br!		r5
+  10:	8003bc08 	br		r3
+  14:	801fbc08 	br		r31
+	...
+  20:	0f0c      	brl!		r0
+  22:	0f0c      	brl!		r0
+  24:	0ffc      	brl!		r15
+  26:	0ffc      	brl!		r15
+  28:	0f3c      	brl!		r3
+  2a:	0f3c      	brl!		r3
+  2c:	0f5c      	brl!		r5
+  2e:	0f5c      	brl!		r5
+  30:	8003bc09 	brl		r3
+  34:	801fbc09 	brl		r31
+	...
+  40:	8000bc08 	br		r0
+  44:	8017bc08 	br		r23
+  48:	800fbc08 	br		r15
+  4c:	801bbc08 	br		r27
+  50:	0f64      	br!		r6
+  52:	0f64      	br!		r6
+  54:	0f34      	br!		r3
+  56:	0f34      	br!		r3
+	...
+  60:	8000bc09 	brl		r0
+  64:	8017bc09 	brl		r23
+  68:	800fbc09 	brl		r15
+  6c:	801bbc09 	brl		r27
+  70:	0f6c      	brl!		r6
+  72:	0f6c      	brl!		r6
+  74:	0f3c      	brl!		r3
+  76:	0f3c      	brl!		r3
+#pass
diff --git a/gas/testsuite/gas/score/br.s b/gas/testsuite/gas/score/br.s
new file mode 100644
index 000000000000..e60e058d8190
--- /dev/null
+++ b/gas/testsuite/gas/score/br.s
@@ -0,0 +1,53 @@
+/*
+ * test relax
+ * br <-> br!   : register number must be in 0-15
+ * brl <-> brl! : register number must be in 0-15
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0      #32b -> 16b
+  \insn16 r0
+
+  \insn32 r15     #32b -> 16b
+  \insn16 r15
+
+  \insn32 r3      #32b -> 16b
+  \insn32 r3      #32b -> 16b
+
+  \insn16 r5      
+  \insn32 r5      #32b -> 16b
+
+  \insn32 r3      #No transform
+  \insn32 r31     #No transform
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0        #16b -> 32b
+  \insn32 r23    
+
+  \insn16 r15       #16b -> 32b
+  \insn32 r27     
+
+  \insn16 r6        #No transform
+  \insn32 r6
+
+  \insn16 r3        #No transform
+  \insn16 r3
+
+.endm
+
+  tran3216 "br", "br!"
+  tran3216 "brl", "brl!"
+
+  tran1632 "br", "br!"
+  tran1632 "brl", "brl!"
+
diff --git a/gas/testsuite/gas/score/ldi.d b/gas/testsuite/gas/score/ldi.d
new file mode 100644
index 000000000000..edd806d7b40c
--- /dev/null
+++ b/gas/testsuite/gas/score/ldi.d
@@ -0,0 +1,29 @@
+#as:
+#objdump: -d
+#source: ldi.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	5200      	ldiu!		r2, 0
+   2:	5200      	ldiu!		r2, 0
+   4:	53ff      	ldiu!		r3, 255
+   6:	53ff      	ldiu!		r3, 255
+   8:	5409      	ldiu!		r4, 9
+   a:	5409      	ldiu!		r4, 9
+   c:	53ff      	ldiu!		r3, 255
+   e:	53ff      	ldiu!		r3, 255
+  10:	85188006 	ldi		r8, 0x3\(3\)
+  14:	87388006 	ldi		r25, 0x3\(3\)
+	...
+  20:	84588000 	ldi		r2, 0x0\(0\)
+  24:	87388000 	ldi		r25, 0x0\(0\)
+  28:	847881fe 	ldi		r3, 0xff\(255\)
+  2c:	86f88002 	ldi		r23, 0x1\(1\)
+  30:	5fff      	ldiu!		r15, 255
+  32:	5fff      	ldiu!		r15, 255
+  34:	5803      	ldiu!		r8, 3
+  36:	5803      	ldiu!		r8, 3
+#pass
diff --git a/gas/testsuite/gas/score/ldi.s b/gas/testsuite/gas/score/ldi.s
new file mode 100644
index 000000000000..d180da34d56d
--- /dev/null
+++ b/gas/testsuite/gas/score/ldi.s
@@ -0,0 +1,53 @@
+/*
+ * test relax
+ * ldi <-> ldiu! : for ldiu! : register number must be in 0-15, simm16:	[0-255]
+ *   (1)ldi rD, simm16 : rD = simm16
+ *   (2)ldiu! rD, imm8 : rD = ZE(imm8)
+ 	
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+	
+  \insn32 r2, 0                  #32b -> 16b
+  \insn16 r2, 0
+
+  \insn32 r3, 255                #32b -> 16b
+  \insn16 r3, 255
+
+  \insn32 r4, 9                  #32b -> 16b
+  \insn32 r4, 9                  #32b -> 16b
+
+  \insn16 r3, 255
+  \insn32 r3, 255                #32b -> 16b
+	
+  \insn32 r8, 3                  #No transform
+  \insn32 r25, 3                 #No transform
+
+	
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+	
+  \insn16 r2, 0                  #16b -> 32b
+  \insn32 r25, 0  
+
+  \insn16 r3, 255                #16b -> 32b
+  \insn32 r23, 1  
+
+  \insn16 r15, 255               #No transform
+  \insn32 r15, 255
+
+  \insn16 r8, 3                  #No transform
+  \insn16 r8, 3                  #No transform
+
+.endm
+
+.text
+
+  tran3216 "ldi", "ldiu!"
+  tran1632 "ldi", "ldiu!"
diff --git a/gas/testsuite/gas/score/ls32ls16.d b/gas/testsuite/gas/score/ls32ls16.d
new file mode 100644
index 000000000000..a6ddfa60e1f8
--- /dev/null
+++ b/gas/testsuite/gas/score/ls32ls16.d
@@ -0,0 +1,145 @@
+#as:
+#objdump: -d
+#source: ls32ls16.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+	...
+  10:	2038      	lw!		r0, \[r3\]
+  12:	2038      	lw!		r0, \[r3\]
+  14:	23f8      	lw!		r3, \[r15\]
+  16:	23f8      	lw!		r3, \[r15\]
+  18:	2f88      	lw!		r15, \[r8\]
+  1a:	2f88      	lw!		r15, \[r8\]
+  1c:	c0888000 	lw		r4, \[r8, 0\]
+  20:	c3338000 	lw		r25, \[r19, 0\]
+  24:	2578      	lw!		r5, \[r7\]
+  26:	2578      	lw!		r5, \[r7\]
+  28:	2238      	lw!		r2, \[r3\]
+  2a:	2238      	lw!		r2, \[r3\]
+	...
+  40:	2039      	lh!		r0, \[r3\]
+  42:	2039      	lh!		r0, \[r3\]
+  44:	23f9      	lh!		r3, \[r15\]
+  46:	23f9      	lh!		r3, \[r15\]
+  48:	2f89      	lh!		r15, \[r8\]
+  4a:	2f89      	lh!		r15, \[r8\]
+  4c:	c4888000 	lh		r4, \[r8, 0\]
+  50:	c7338000 	lh		r25, \[r19, 0\]
+  54:	2579      	lh!		r5, \[r7\]
+  56:	2579      	lh!		r5, \[r7\]
+  58:	2239      	lh!		r2, \[r3\]
+  5a:	2239      	lh!		r2, \[r3\]
+	...
+ 110:	203b      	lbu!		r0, \[r3\]
+ 112:	203b      	lbu!		r0, \[r3\]
+ 114:	23fb      	lbu!		r3, \[r15\]
+ 116:	23fb      	lbu!		r3, \[r15\]
+ 118:	2f8b      	lbu!		r15, \[r8\]
+ 11a:	2f8b      	lbu!		r15, \[r8\]
+ 11c:	d8888000 	lbu		r4, \[r8, 0\]
+ 120:	db338000 	lbu		r25, \[r19, 0\]
+ 124:	257b      	lbu!		r5, \[r7\]
+ 126:	257b      	lbu!		r5, \[r7\]
+ 128:	223b      	lbu!		r2, \[r3\]
+ 12a:	223b      	lbu!		r2, \[r3\]
+	...
+ 210:	203c      	sw!		r0, \[r3\]
+ 212:	203c      	sw!		r0, \[r3\]
+ 214:	23fc      	sw!		r3, \[r15\]
+ 216:	23fc      	sw!		r3, \[r15\]
+ 218:	2f8c      	sw!		r15, \[r8\]
+ 21a:	2f8c      	sw!		r15, \[r8\]
+ 21c:	d0888000 	sw		r4, \[r8, 0\]
+ 220:	d3338000 	sw		r25, \[r19, 0\]
+ 224:	257c      	sw!		r5, \[r7\]
+ 226:	257c      	sw!		r5, \[r7\]
+ 228:	223c      	sw!		r2, \[r3\]
+ 22a:	223c      	sw!		r2, \[r3\]
+ 22c:	0000      	nop!
+ 22e:	0000      	nop!
+ 230:	203d      	sh!		r0, \[r3\]
+ 232:	203d      	sh!		r0, \[r3\]
+ 234:	23fd      	sh!		r3, \[r15\]
+ 236:	23fd      	sh!		r3, \[r15\]
+ 238:	2f8d      	sh!		r15, \[r8\]
+ 23a:	2f8d      	sh!		r15, \[r8\]
+ 23c:	d4888000 	sh		r4, \[r8, 0\]
+ 240:	d7338000 	sh		r25, \[r19, 0\]
+ 244:	257d      	sh!		r5, \[r7\]
+ 246:	257d      	sh!		r5, \[r7\]
+ 248:	223d      	sh!		r2, \[r3\]
+ 24a:	223d      	sh!		r2, \[r3\]
+ 24c:	0000      	nop!
+ 24e:	0000      	nop!
+ 250:	203f      	sb!		r0, \[r3\]
+ 252:	203f      	sb!		r0, \[r3\]
+ 254:	23ff      	sb!		r3, \[r15\]
+ 256:	23ff      	sb!		r3, \[r15\]
+ 258:	2f8f      	sb!		r15, \[r8\]
+ 25a:	2f8f      	sb!		r15, \[r8\]
+ 25c:	dc888000 	sb		r4, \[r8, 0\]
+ 260:	df338000 	sb		r25, \[r19, 0\]
+ 264:	257f      	sb!		r5, \[r7\]
+ 266:	257f      	sb!		r5, \[r7\]
+ 268:	223f      	sb!		r2, \[r3\]
+ 26a:	223f      	sb!		r2, \[r3\]
+ 26c:	0000      	nop!
+ 26e:	0000      	nop!
+ 270:	c0038000 	lw		r0, \[r3, 0\]
+ 274:	c257800a 	lw		r18, \[r23, 10\]
+ 278:	c1e08000 	lw		r15, \[r0, 0\]
+ 27c:	c23a800a 	lw		r17, \[r26, 10\]
+ 280:	2688      	lw!		r6, \[r8\]
+ 282:	2688      	lw!		r6, \[r8\]
+ 284:	2378      	lw!		r3, \[r7\]
+ 286:	2378      	lw!		r3, \[r7\]
+	...
+ 290:	c4038000 	lh		r0, \[r3, 0\]
+ 294:	c657800a 	lh		r18, \[r23, 10\]
+ 298:	c5e08000 	lh		r15, \[r0, 0\]
+ 29c:	c63a800a 	lh		r17, \[r26, 10\]
+ 2a0:	2689      	lh!		r6, \[r8\]
+ 2a2:	2689      	lh!		r6, \[r8\]
+ 2a4:	2379      	lh!		r3, \[r7\]
+ 2a6:	2379      	lh!		r3, \[r7\]
+	...
+ 2b0:	d8038000 	lbu		r0, \[r3, 0\]
+ 2b4:	da57800a 	lbu		r18, \[r23, 10\]
+ 2b8:	d9e08000 	lbu		r15, \[r0, 0\]
+ 2bc:	da3a800a 	lbu		r17, \[r26, 10\]
+ 2c0:	268b      	lbu!		r6, \[r8\]
+ 2c2:	268b      	lbu!		r6, \[r8\]
+ 2c4:	237b      	lbu!		r3, \[r7\]
+ 2c6:	237b      	lbu!		r3, \[r7\]
+	...
+ 2d0:	d0038000 	sw		r0, \[r3, 0\]
+ 2d4:	d257800a 	sw		r18, \[r23, 10\]
+ 2d8:	d1e08000 	sw		r15, \[r0, 0\]
+ 2dc:	d23a800a 	sw		r17, \[r26, 10\]
+ 2e0:	268c      	sw!		r6, \[r8\]
+ 2e2:	268c      	sw!		r6, \[r8\]
+ 2e4:	237c      	sw!		r3, \[r7\]
+ 2e6:	237c      	sw!		r3, \[r7\]
+	...
+ 2f0:	d4038000 	sh		r0, \[r3, 0\]
+ 2f4:	d657800a 	sh		r18, \[r23, 10\]
+ 2f8:	d5e08000 	sh		r15, \[r0, 0\]
+ 2fc:	d63a800a 	sh		r17, \[r26, 10\]
+ 300:	268d      	sh!		r6, \[r8\]
+ 302:	268d      	sh!		r6, \[r8\]
+ 304:	237d      	sh!		r3, \[r7\]
+ 306:	237d      	sh!		r3, \[r7\]
+	...
+ 310:	dc038000 	sb		r0, \[r3, 0\]
+ 314:	de57800a 	sb		r18, \[r23, 10\]
+ 318:	dde08000 	sb		r15, \[r0, 0\]
+ 31c:	de3a800a 	sb		r17, \[r26, 10\]
+ 320:	268f      	sb!		r6, \[r8\]
+ 322:	268f      	sb!		r6, \[r8\]
+ 324:	237f      	sb!		r3, \[r7\]
+ 326:	237f      	sb!		r3, \[r7\]
+#pass
diff --git a/gas/testsuite/gas/score/ls32ls16.s b/gas/testsuite/gas/score/ls32ls16.s
new file mode 100644
index 000000000000..387d41dab9e9
--- /dev/null
+++ b/gas/testsuite/gas/score/ls32ls16.s
@@ -0,0 +1,70 @@
+/*
+ * test relax
+ * lw <-> lw!   : register number must be in 0-15, offset == 0
+ * lh <-> lh!   : register number must be in 0-15, offset == 0
+ * lbu <-> lbu! : register number must be in 0-15, offset == 0
+ * sw <-> sw!   : register number must be in 0-15, offset == 0
+ * sh <-> sh!   : register number must be in 0-15, offset == 0
+ * sb <-> sb!   : register number must be in 0-15, offset == 0
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0, [r3, 0]     #32b -> 16b
+  \insn16 r0, [r3]
+
+  \insn32 r3, [r15, 0]    #32b -> 16b
+  \insn16 r3, [r15]
+
+  \insn32 r15, [r8, 0]    #32b -> 16b
+  \insn16 r15, [r8]
+
+  \insn32 r4, [r8, 0]     #No transform
+  \insn32 r25, [r19, 0]
+
+  \insn32 r5, [r7, 0]     #32b -> 16b
+  \insn32 r5, [r7, 0]     #32b -> 16b
+
+  \insn16 r2, [r3]  
+  \insn32 r2, [r3, 0]     #32b -> 16b
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, [r3]        #16b -> 32b
+  \insn32 r18, [r23, 10]     
+
+  \insn16 r15, [r0]       #16b -> 32b
+  \insn32 r17, [r26, 10]     
+
+  \insn16 r6, [r8]        #No transform
+  \insn16 r6, [r8]        #No transform
+
+  \insn16 r3, [r7]        #No transform
+  \insn32 r3, [r7, 0]
+
+.endm
+.space 1
+  tran3216 "lw", "lw!"
+.fill 10, 1
+  tran3216 "lh", "lh!"
+.org 0x101
+  tran3216 "lbu", "lbu!"
+.org 0x203
+  tran3216 "sw", "sw!"
+  tran3216 "sh", "sh!"
+  tran3216 "sb", "sb!"
+
+  tran1632 "lw", "lw!"
+  tran1632 "lh", "lh!"
+  tran1632 "lbu", "lbu!"
+  tran1632 "sw", "sw!"
+  tran1632 "sh", "sh!"
+  tran1632 "sb", "sb!"
diff --git a/gas/testsuite/gas/score/ls32ls16p.d b/gas/testsuite/gas/score/ls32ls16p.d
new file mode 100644
index 000000000000..aa1d3a64de66
--- /dev/null
+++ b/gas/testsuite/gas/score/ls32ls16p.d
@@ -0,0 +1,135 @@
+#as:
+#objdump: -d
+#source: ls32ls16p.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+   0:	7320      	lwp!		r3, 16
+   2:	7320      	lwp!		r3, 16
+   4:	7460      	lwp!		r4, 48
+   6:	7460      	lwp!		r4, 48
+   8:	7790      	lwp!		r7, 72
+   a:	7790      	lwp!		r7, 72
+   c:	7840      	lwp!		r8, 32
+   e:	7840      	lwp!		r8, 32
+  10:	c0a28080 	lw		r5, \[r2, 128\]
+  14:	c0a28080 	lw		r5, \[r2, 128\]
+  18:	c0c68020 	lw		r6, \[r6, 32\]
+  1c:	c0c68020 	lw		r6, \[r6, 32\]
+  20:	7321      	lhp!		r3, 8
+  22:	7321      	lhp!		r3, 8
+  24:	7461      	lhp!		r4, 24
+  26:	7461      	lhp!		r4, 24
+  28:	7791      	lhp!		r7, 36
+  2a:	7791      	lhp!		r7, 36
+  2c:	7841      	lhp!		r8, 16
+  2e:	7841      	lhp!		r8, 16
+  30:	c4a28040 	lh		r5, \[r2, 64\]
+  34:	c4a28040 	lh		r5, \[r2, 64\]
+  38:	c4c68010 	lh		r6, \[r6, 16\]
+  3c:	c4c68010 	lh		r6, \[r6, 16\]
+  40:	7323      	lbup!		r3, 4
+  42:	7323      	lbup!		r3, 4
+  44:	7463      	lbup!		r4, 12
+  46:	7463      	lbup!		r4, 12
+  48:	7793      	lbup!		r7, 18
+  4a:	7793      	lbup!		r7, 18
+  4c:	7843      	lbup!		r8, 8
+  4e:	7843      	lbup!		r8, 8
+  50:	d8a28020 	lbu		r5, \[r2, 32\]
+  54:	d8a28020 	lbu		r5, \[r2, 32\]
+  58:	d8c68008 	lbu		r6, \[r6, 8\]
+  5c:	d8c68008 	lbu		r6, \[r6, 8\]
+  60:	7324      	swp!		r3, 16
+  62:	7324      	swp!		r3, 16
+  64:	7464      	swp!		r4, 48
+  66:	7464      	swp!		r4, 48
+  68:	7794      	swp!		r7, 72
+  6a:	7794      	swp!		r7, 72
+  6c:	7844      	swp!		r8, 32
+  6e:	7844      	swp!		r8, 32
+  70:	d0a28080 	sw		r5, \[r2, 128\]
+  74:	d0a28080 	sw		r5, \[r2, 128\]
+  78:	d0c68020 	sw		r6, \[r6, 32\]
+  7c:	d0c68020 	sw		r6, \[r6, 32\]
+  80:	7325      	shp!		r3, 8
+  82:	7325      	shp!		r3, 8
+  84:	7465      	shp!		r4, 24
+  86:	7465      	shp!		r4, 24
+  88:	7795      	shp!		r7, 36
+  8a:	7795      	shp!		r7, 36
+  8c:	7845      	shp!		r8, 16
+  8e:	7845      	shp!		r8, 16
+  90:	d4a28040 	sh		r5, \[r2, 64\]
+  94:	d4a28040 	sh		r5, \[r2, 64\]
+  98:	d4c68010 	sh		r6, \[r6, 16\]
+  9c:	d4c68010 	sh		r6, \[r6, 16\]
+  a0:	7327      	sbp!		r3, 4
+  a2:	7327      	sbp!		r3, 4
+  a4:	7467      	sbp!		r4, 12
+  a6:	7467      	sbp!		r4, 12
+  a8:	7797      	sbp!		r7, 18
+  aa:	7797      	sbp!		r7, 18
+  ac:	7847      	sbp!		r8, 8
+  ae:	7847      	sbp!		r8, 8
+  b0:	dca28020 	sb		r5, \[r2, 32\]
+  b4:	dca28020 	sb		r5, \[r2, 32\]
+  b8:	dcc68008 	sb		r6, \[r6, 8\]
+  bc:	dcc68008 	sb		r6, \[r6, 8\]
+  c0:	c002800c 	lw		r0, \[r2, 12\]
+  c4:	c00580ff 	lw		r0, \[r5, 255\]
+  c8:	c1e28000 	lw		r15, \[r2, 0\]
+  cc:	c1e480ff 	lw		r15, \[r4, 255\]
+  d0:	7410      	lwp!		r4, 8
+  d2:	7410      	lwp!		r4, 8
+  d4:	7710      	lwp!		r7, 8
+  d6:	7740      	lwp!		r7, 32
+	...
+  e0:	c402800c 	lh		r0, \[r2, 12\]
+  e4:	c40580ff 	lh		r0, \[r5, 255\]
+  e8:	c5e28000 	lh		r15, \[r2, 0\]
+  ec:	c5e480ff 	lh		r15, \[r4, 255\]
+  f0:	7421      	lhp!		r4, 8
+  f2:	7421      	lhp!		r4, 8
+  f4:	7721      	lhp!		r7, 8
+  f6:	7741      	lhp!		r7, 16
+	...
+ 100:	d802800c 	lbu		r0, \[r2, 12\]
+ 104:	d80580ff 	lbu		r0, \[r5, 255\]
+ 108:	d9e28000 	lbu		r15, \[r2, 0\]
+ 10c:	d9e480ff 	lbu		r15, \[r4, 255\]
+ 110:	7443      	lbup!		r4, 8
+ 112:	7443      	lbup!		r4, 8
+ 114:	7743      	lbup!		r7, 8
+ 116:	7743      	lbup!		r7, 8
+	...
+ 120:	d002800c 	sw		r0, \[r2, 12\]
+ 124:	d00580ff 	sw		r0, \[r5, 255\]
+ 128:	d1e28000 	sw		r15, \[r2, 0\]
+ 12c:	d1e480ff 	sw		r15, \[r4, 255\]
+ 130:	7414      	swp!		r4, 8
+ 132:	7414      	swp!		r4, 8
+ 134:	7714      	swp!		r7, 8
+ 136:	7744      	swp!		r7, 32
+	...
+ 140:	d402800c 	sh		r0, \[r2, 12\]
+ 144:	d40580ff 	sh		r0, \[r5, 255\]
+ 148:	d5e28000 	sh		r15, \[r2, 0\]
+ 14c:	d5e480ff 	sh		r15, \[r4, 255\]
+ 150:	7425      	shp!		r4, 8
+ 152:	7425      	shp!		r4, 8
+ 154:	7725      	shp!		r7, 8
+ 156:	7745      	shp!		r7, 16
+	...
+ 160:	dc02800c 	sb		r0, \[r2, 12\]
+ 164:	dc0580ff 	sb		r0, \[r5, 255\]
+ 168:	dde28000 	sb		r15, \[r2, 0\]
+ 16c:	dde480ff 	sb		r15, \[r4, 255\]
+ 170:	7447      	sbp!		r4, 8
+ 172:	7447      	sbp!		r4, 8
+ 174:	7747      	sbp!		r7, 8
+ 176:	7747      	sbp!		r7, 8
+#pass
diff --git a/gas/testsuite/gas/score/ls32ls16p.s b/gas/testsuite/gas/score/ls32ls16p.s
new file mode 100644
index 000000000000..72aa6125c769
--- /dev/null
+++ b/gas/testsuite/gas/score/ls32ls16p.s
@@ -0,0 +1,68 @@
+/*
+ * test relax
+ * lw <-> lwp!  : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
+ * lh <-> lhp!  : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b
+ * lbu <-> lbu! : rs = r2, offset != 0, offset : 5b
+ * sw <-> swp!  : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b
+ * sh <-> shp!  : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b
+ * sb <-> sb!   : rs = r2, offset != 0, offset : 5b
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16, shift
+.align 4
+
+  \insn32 r3, [r2, 0x4 << \shift]     #32b -> 16b
+  \insn16 r3, 0x4 << \shift
+
+  \insn32 r4, [r2, 0xC << \shift]      #32b -> 16b
+  \insn16 r4, 0xC << \shift
+
+  \insn32 r7, [r2, 0x12 << \shift]     #32b -> 16b
+  \insn32 r7, [r2, 0x12 << \shift]     #32b -> 16b
+
+  \insn16 r8, 0x8 << \shift
+  \insn32 r8, [r2, 0x8 << \shift]      #32b -> 16b
+
+  \insn32 r5, [r2, 0x20 << \shift]     #No transform
+  \insn32 r5, [r2, 0x20 << \shift]     #No transform
+
+  \insn32 r6, [r6, 0x8 << \shift]      #No transform
+  \insn32 r6, [r6, 0x8 << \shift]      #No transform
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16, shift
+.align 4
+
+  \insn16 r0, 0xC                      #16b -> 32b
+  \insn32 r0, [r5, 0xFF]       
+
+  \insn16 r15, 0x0                     #16b -> 32b
+  \insn32 r15, [r4, 0xFF]       
+ 
+  \insn16 r4, 0x8                      #No transform
+  \insn16 r4, 0x8                      #No transform
+
+  \insn16 r7, 0x8                      #No transform
+  \insn32 r7, [r2, 0x8 << \shift]
+
+.endm
+
+  tran3216 "lw", "lwp!", 2
+  tran3216 "lh", "lhp!", 1
+  tran3216 "lbu", "lbup!", 0
+  tran3216 "sw", "swp!", 2
+  tran3216 "sh", "shp!", 1
+  tran3216 "sb", "sbp!", 0
+
+  tran1632 "lw", "lwp!", 2
+  tran1632 "lh", "lhp!", 1
+  tran1632 "lbu", "lbup!", 0
+  tran1632 "sw", "swp!", 2
+  tran1632 "sh", "shp!", 1
+  tran1632 "sb", "sbp!", 0
+
diff --git a/gas/testsuite/gas/score/move.d b/gas/testsuite/gas/score/move.d
new file mode 100644
index 000000000000..0bec506ec8eb
--- /dev/null
+++ b/gas/testsuite/gas/score/move.d
@@ -0,0 +1,60 @@
+#as:
+#objdump: -d
+#source: move.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+   0:	00f3      	mv!		r0, r15
+   2:	00f3      	mv!		r0, r15
+   4:	0ff3      	mv!		r15, r15
+   6:	0ff3      	mv!		r15, r15
+   8:	0353      	mv!		r3, r5
+   a:	0353      	mv!		r3, r5
+   c:	0673      	mv!		r6, r7
+   e:	0673      	mv!		r6, r7
+  10:	810abc56 	mv		r8, r10
+  14:	82b7bc56 	mv		r21, r23
+	...
+  20:	800fbc56 	mv		r0, r15
+  24:	82fbbc56 	mv		r23, r27
+  28:	0283      	mv!		r2, r8
+  2a:	0283      	mv!		r2, r8
+  2c:	0283      	mv!		r2, r8
+  2e:	0283      	mv!		r2, r8
+  30:	0f02      	mhfl!		r31, r0
+  32:	0f02      	mhfl!		r31, r0
+  34:	00f2      	mhfl!		r16, r15
+  36:	00f2      	mhfl!		r16, r15
+  38:	0752      	mhfl!		r23, r5
+  3a:	0752      	mhfl!		r23, r5
+  3c:	0a72      	mhfl!		r26, r7
+  3e:	0a72      	mhfl!		r26, r7
+  40:	838abc56 	mv		gp, r10
+  44:	82b7bc56 	mv		r21, r23
+	...
+  50:	83e0bc56 	mv		r31, r0
+  54:	82fbbc56 	mv		r23, r27
+  58:	0682      	mhfl!		r22, r8
+  5a:	0682      	mhfl!		r22, r8
+  5c:	07f2      	mhfl!		r23, r15
+  5e:	07f2      	mhfl!		r23, r15
+  60:	00f1      	mlfh!		r0, r31
+  62:	00f1      	mlfh!		r0, r31
+  64:	0f01      	mlfh!		r15, r16
+  66:	0f01      	mlfh!		r15, r16
+  68:	0571      	mlfh!		r5, r23
+  6a:	0571      	mlfh!		r5, r23
+  6c:	07a1      	mlfh!		r7, r26
+  6e:	07a1      	mlfh!		r7, r26
+  70:	815cbc56 	mv		r10, gp
+  74:	82b7bc56 	mv		r21, r23
+	...
+  80:	801fbc56 	mv		r0, r31
+  84:	82fbbc56 	mv		r23, r27
+  88:	0861      	mlfh!		r8, r22
+  8a:	0861      	mlfh!		r8, r22
+  8c:	0f71      	mlfh!		r15, r23
+  8e:	0f71      	mlfh!		r15, r23
diff --git a/gas/testsuite/gas/score/move.s b/gas/testsuite/gas/score/move.s
new file mode 100644
index 000000000000..3a4623eda45e
--- /dev/null
+++ b/gas/testsuite/gas/score/move.s
@@ -0,0 +1,98 @@
+/*
+ * test relax
+ * mv <-> mv!   : for mv! : register number must be in 0-15
+ * mv <-> mhfl! : for mhfl! : rD must be in 16-31, rS must be in 0-15
+ * mv <-> mlfh! : for mhfl! : rD must be in 0-15, rS must be in 16-31
+
+ * Author: ligang
+ */
+
+/* This block test mv -> mv! */
+.align 4
+
+  mv  r0, r15      #32b -> 16b
+  mv! r0, r15
+
+  mv  r15, r15     #32b -> 16b
+  mv! r15, r15
+
+  mv  r3, r5       #32b -> 16b
+  mv  r3, r5       #32b -> 16b
+
+  mv! r6, r7
+  mv  r6, r7       #32b -> 16b
+
+  mv  r8, r10      #No transform
+  mv  r21, r23
+
+/* This block test mv! -> mv */
+.align 4
+
+  mv! r0, r15      #16b -> 32b      
+  mv  r23, r27
+
+  mv! r2, r8       #No transform      
+  mv! r2, r8       #No transform
+
+  mv! r2, r8       #No transform      
+  mv  r2, r8       
+
+/* This block test mv -> mhfl! */
+.align 4
+
+  mv    r31, r0        #32b -> 16b
+  mhfl! r31, r0
+
+  mv    r16, r15       #32b -> 16b
+  mv!   r16, r15
+
+  mv    r23, r5        #32b -> 16b
+  mv    r23, r5        #32b -> 16b
+
+  mhfl! r26, r7
+  mv    r26, r7        #32b -> 16b
+
+  mv    r28, r10       #No transform
+  mv    r21, r23
+
+/* This block test mhfl! -> mv */
+.align 4
+
+  mhfl! r31, r0       #16b -> 32b      
+  mv    r23, r27
+
+  mhfl! r22, r8       #No transform      
+  mhfl! r22, r8       #No transform
+
+  mhfl! r23, r15      #No transform      
+  mv    r23, r15       
+
+/* This block test mv -> mlfh! */
+.align 4
+
+  mv    r0, r31        #32b -> 16b
+  mlfh! r0, r31
+
+  mv    r15, r16       #32b -> 16b
+  mv!   r15, r16
+
+  mv    r5, r23        #32b -> 16b
+  mv    r5, r23        #32b -> 16b
+
+  mlfh! r7, r26
+  mv    r7, r26        #32b -> 16b
+
+  mv    r10, r28       #No transform
+  mv    r21, r23
+
+/* This block test mhfl! -> mv */
+.align 4
+
+  mlfh! r0, r31       #16b -> 32b      
+  mv    r23, r27
+
+  mlfh! r8, r22       #No transform      
+  mlfh! r8, r22       #No transform
+
+  mlfh! r15, r23      #No transform      
+  mv    r15, r23       
diff --git a/gas/testsuite/gas/score/nop.d b/gas/testsuite/gas/score/nop.d
new file mode 100644
index 000000000000..83e98b7faa03
--- /dev/null
+++ b/gas/testsuite/gas/score/nop.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -d
+#source: nop.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+	...
+   c:	80008000 	nop
+  10:	8254e010 	add		r18, r20, r24
+	...
+  28:	80008000 	nop
+  2c:	8254e026 	xor		r18, r20, r24
diff --git a/gas/testsuite/gas/score/nop.s b/gas/testsuite/gas/score/nop.s
new file mode 100644
index 000000000000..26955528ae12
--- /dev/null
+++ b/gas/testsuite/gas/score/nop.s
@@ -0,0 +1,38 @@
+/*
+ * test relax
+ * nop <-> nop!
+	
+ * Author: ligang
+ */
+
+.macro tran insn32, insn16
+/* This block transform 32b instruction to 16b. */
+.align 4
+	
+  \insn32               #32b -> 16b
+  \insn16
+
+  \insn32               #32b -> 16b
+  \insn32               #32b -> 16b
+
+  \insn16      
+  \insn32               #32b -> 16b
+
+  \insn32               #No transform
+  add r18, r20, r24
+
+/* This block transform 16b instruction to 32b. */
+.align 4
+	
+  \insn16               #No transform
+  \insn32
+
+  \insn16               #No transform
+  \insn16
+
+  \insn16               #16b -> 32b
+  xor r18, r20, r24
+	
+.endm
+
+  tran "nop", "nop!"
diff --git a/gas/testsuite/gas/score/postlw.d b/gas/testsuite/gas/score/postlw.d
new file mode 100644
index 000000000000..25867f4edc34
--- /dev/null
+++ b/gas/testsuite/gas/score/postlw.d
@@ -0,0 +1,32 @@
+#as:
+#objdump: -d
+#source: postlw.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	27fa      	pop!		r23, \[r7\]
+   2:	27fa      	pop!		r23, \[r7\]
+   4:	202a      	pop!		r0, \[r2\]
+   6:	202a      	pop!		r0, \[r2\]
+   8:	2f0a      	pop!		r15, \[r0\]
+   a:	2f0a      	pop!		r15, \[r0\]
+   c:	2f7a      	pop!		r15, \[r7\]
+   e:	2f7a      	pop!		r15, \[r7\]
+  10:	29ba      	pop!		r25, \[r3\]
+  12:	29ba      	pop!		r25, \[r3\]
+  14:	9f0d8020 	lw		r24, \[r13\]\+, 4
+  18:	9ee78028 	lw		r23, \[r7\]\+, 5
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	9c078020 	lw		r0, \[r7\]\+, 4
+  24:	9f2d8020 	lw		r25, \[r13\]\+, 4
+  28:	9f208020 	lw		r25, \[r0\]\+, 4
+  2c:	9e578020 	lw		r18, \[r23\]\+, 4
+  30:	263a      	pop!		r6, \[r3\]
+  32:	263a      	pop!		r6, \[r3\]
+  34:	237a      	pop!		r3, \[r7\]
+  36:	237a      	pop!		r3, \[r7\]
+#pass
diff --git a/gas/testsuite/gas/score/postlw.s b/gas/testsuite/gas/score/postlw.s
new file mode 100644
index 000000000000..499ea94a5956
--- /dev/null
+++ b/gas/testsuite/gas/score/postlw.s
@@ -0,0 +1,54 @@
+/*
+ * test relax
+ * post lw <-> pop! : offset == 4
+ * syntax:	
+   lw rD, [rA]+, simm12 : rD and rA can be 0-31
+   pop! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r23, [r7]+, 4    #32b -> 16b
+  \insn16 r23, [r7]
+
+  \insn32 r0, [r2]+, 4     #32b -> 16b
+  \insn16 r0, [r2]
+
+  \insn32 r15, [r0]+, 4    #32b -> 16b
+  \insn16 r15, [r0]
+
+  \insn16 r15, [r7]
+  \insn32 r15, [r7]+, 4    #32b -> 16b
+	
+  \insn32 r25, [r3]+, 4    #32b -> 16b
+  \insn32 r25, [r3]+, 4    #32b -> 16b
+
+  \insn32 r24, [r13]+, 4   #No transform
+  \insn32 r23, [r7]+, 5    #No transform
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, [r7]         #16b -> 32b
+  \insn32 r25, [r13]+, 4
+
+  \insn16 r25, [r0]        #16b -> 32b
+  \insn32 r18, [r23]+, 4
+
+  \insn16 r6, [r3]         #No transform
+  \insn16 r6, [r3]         #No transform
+
+  \insn16 r3, [r7]         #No transform
+  \insn32 r3, [r7]+, 4
+
+.endm
+
+  tran3216 "lw", "pop!"
+  tran1632 "lw", "pop!"
diff --git a/gas/testsuite/gas/score/presw.d b/gas/testsuite/gas/score/presw.d
new file mode 100644
index 000000000000..cc4092fdcc82
--- /dev/null
+++ b/gas/testsuite/gas/score/presw.d
@@ -0,0 +1,32 @@
+#as:
+#objdump: -d
+#source: presw.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <.text>:
+   0:	202e      	push!		r0, \[r2\]
+   2:	202e      	push!		r0, \[r2\]
+   4:	27fe      	push!		r23, \[r7\]
+   6:	27fe      	push!		r23, \[r7\]
+   8:	2f0e      	push!		r15, \[r0\]
+   a:	2f0e      	push!		r15, \[r0\]
+   c:	2f7e      	push!		r15, \[r7\]
+   e:	2f7e      	push!		r15, \[r7\]
+  10:	29be      	push!		r25, \[r3\]
+  12:	29be      	push!		r25, \[r3\]
+  14:	8f0dffe4 	sw		r24, \[r13, -4\]\+
+  18:	8ee7ffdc 	sw		r23, \[r7, -5\]\+
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	8c07ffe4 	sw		r0, \[r7, -4\]\+
+  24:	8f2dffe4 	sw		r25, \[r13, -4\]\+
+  28:	8f20ffe4 	sw		r25, \[r0, -4\]\+
+  2c:	8e57ffe4 	sw		r18, \[r23, -4\]\+
+  30:	263e      	push!		r6, \[r3\]
+  32:	263e      	push!		r6, \[r3\]
+  34:	237e      	push!		r3, \[r7\]
+  36:	237e      	push!		r3, \[r7\]
+#pass
diff --git a/gas/testsuite/gas/score/presw.s b/gas/testsuite/gas/score/presw.s
new file mode 100644
index 000000000000..bcc11d102c89
--- /dev/null
+++ b/gas/testsuite/gas/score/presw.s
@@ -0,0 +1,54 @@
+/*
+ * test relax
+ * pre sw <-> push! : offset == -4
+ * syntax:	
+   sw rD, [rA, simm12]+ : rD and rA can be 0-31
+   push! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0, [r2, -4]+     #32b -> 16b
+  \insn16 r0, [r2]
+
+  \insn32 r23, [r7, -4]+    #32b -> 16b
+  \insn16 r23, [r7]
+
+  \insn32 r15, [r0, -4]+    #32b -> 16b
+  \insn16 r15, [r0]
+
+  \insn16 r15, [r7]
+  \insn32 r15, [r7, -4]+    #32b -> 16b
+	
+  \insn32 r25, [r3, -4]+    #32b -> 16b
+  \insn32 r25, [r3, -4]+    #32b -> 16b
+
+  \insn32 r24, [r13, -4]+   #No transform
+  \insn32 r23, [r7, -5]+    #No transform
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, [r7]         #16b -> 32b
+  \insn32 r25, [r13, -4]+
+
+  \insn16 r25, [r0]        #16b -> 32b
+  \insn32 r18, [r23, -4]+
+
+  \insn16 r6, [r3]         #No transform
+  \insn16 r6, [r3]         #No transform
+
+  \insn16 r3, [r7]         #No transform
+  \insn32 r3, [r7, -4]+
+
+.endm
+
+  tran3216 "sw", "push!"
+  tran1632 "sw", "push!"
diff --git a/gas/testsuite/gas/score/rD_rA.d b/gas/testsuite/gas/score/rD_rA.d
new file mode 100644
index 000000000000..36f29f65c101
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA.d
@@ -0,0 +1,90 @@
+#as:
+#objdump: -d
+#source: rD_rA.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	2076      	not!		r0, r7
+   2:	2076      	not!		r0, r7
+   4:	2f46      	not!		r15, r4
+   6:	2f46      	not!		r15, r4
+   8:	2ff6      	not!		r15, r15
+   a:	2ff6      	not!		r15, r15
+   c:	2f36      	not!		r15, r3
+   e:	2f36      	not!		r15, r3
+  10:	2826      	not!		r8, r2
+  12:	2826      	not!		r8, r2
+  14:	81e58025 	not.c		r15, r5
+  18:	83578025 	not.c		r26, r23
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	2072      	neg!		r0, r7
+  22:	2072      	neg!		r0, r7
+  24:	2f42      	neg!		r15, r4
+  26:	2f42      	neg!		r15, r4
+  28:	2ff2      	neg!		r15, r15
+  2a:	2ff2      	neg!		r15, r15
+  2c:	2f32      	neg!		r15, r3
+  2e:	2f32      	neg!		r15, r3
+  30:	2822      	neg!		r8, r2
+  32:	2822      	neg!		r8, r2
+  34:	81e0941f 	neg.c		r15, r5
+  38:	8340dc1f 	neg.c		r26, r23
+  3c:	0000      	nop!
+  3e:	0000      	nop!
+  40:	2073      	cmp!		r0, r7
+  42:	2073      	cmp!		r0, r7
+  44:	2f43      	cmp!		r15, r4
+  46:	2f43      	cmp!		r15, r4
+  48:	2ff3      	cmp!		r15, r15
+  4a:	2ff3      	cmp!		r15, r15
+  4c:	2f33      	cmp!		r15, r3
+  4e:	2f33      	cmp!		r15, r3
+  50:	2823      	cmp!		r8, r2
+  52:	2823      	cmp!		r8, r2
+  54:	806f9419 	cmp.c		r15, r5
+  58:	807adc19 	cmp.c		r26, r23
+  5c:	0000      	nop!
+  5e:	0000      	nop!
+  60:	80028025 	not.c		r0, r2
+  64:	82958025 	not.c		r20, r21
+  68:	81e48025 	not.c		r15, r4
+  6c:	83358025 	not.c		r25, r21
+  70:	81e38025 	not.c		r15, r3
+  74:	83368025 	not.c		r25, r22
+  78:	2836      	not!		r8, r3
+  7a:	2836      	not!		r8, r3
+  7c:	2626      	not!		r6, r2
+  7e:	2626      	not!		r6, r2
+  80:	2746      	not!		r7, r4
+  82:	2746      	not!		r7, r4
+	...
+  90:	8000881f 	neg.c		r0, r2
+  94:	8280d41f 	neg.c		r20, r21
+  98:	81ef901f 	neg.c		r15, r4
+  9c:	8320d41f 	neg.c		r25, r21
+  a0:	81ef8c1f 	neg.c		r15, r3
+  a4:	8320d81f 	neg.c		r25, r22
+  a8:	2832      	neg!		r8, r3
+  aa:	2832      	neg!		r8, r3
+  ac:	2622      	neg!		r6, r2
+  ae:	2622      	neg!		r6, r2
+  b0:	2742      	neg!		r7, r4
+  b2:	2742      	neg!		r7, r4
+	...
+  c0:	80608819 	cmp.c		r0, r2
+  c4:	8074d419 	cmp.c		r20, r21
+  c8:	806f9019 	cmp.c		r15, r4
+  cc:	8079d419 	cmp.c		r25, r21
+  d0:	806f8c19 	cmp.c		r15, r3
+  d4:	8079d819 	cmp.c		r25, r22
+  d8:	2833      	cmp!		r8, r3
+  da:	2833      	cmp!		r8, r3
+  dc:	2623      	cmp!		r6, r2
+  de:	2623      	cmp!		r6, r2
+  e0:	2743      	cmp!		r7, r4
+  e2:	2743      	cmp!		r7, r4
+#pass
diff --git a/gas/testsuite/gas/score/rD_rA.s b/gas/testsuite/gas/score/rD_rA.s
new file mode 100644
index 000000000000..0f1c0d43ae01
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA.s
@@ -0,0 +1,66 @@
+/*
+ * test relax
+ * not.c <-> not! : register number must be in 0-15
+ * neg.c <-> neg! : register number must be in 0-15
+ * cmp.c <-> cmp! : register number must be in 0-15
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0, r7          #32b -> 16b
+  \insn16 r0, r7
+
+  \insn32 r15, r4         #32b -> 16b
+  \insn16 r15, r4
+
+  \insn32 r15, r15        #32b -> 16b
+  \insn16 r15, r15
+
+  \insn16 r15, r3
+  \insn32 r15, r3         #32b -> 16b
+
+  \insn32 r8,  r2         #32b -> 16b
+  \insn32 r8,  r2         #32b -> 16b
+	
+  \insn32 r15, r5         #No transform
+  \insn32 r26, r23
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+	
+  \insn16 r0, r2         #16b -> 32b
+  \insn32 r20, r21
+	
+  \insn16 r15, r4        #16b -> 32b
+  \insn32 r25, r21
+	
+  \insn16 r15, r3        #16b -> 32b
+  \insn32 r25, r22
+
+  \insn16 r8, r3         #No transform
+  \insn16 r8, r3         #No transform
+	
+  \insn16 r6, r2         #No transform
+  \insn32 r6, r2         #32b -> 16b
+	
+  \insn32 r7, r4         #32b -> 16b
+  \insn16 r7, r4         #No transform
+	
+.endm
+		
+.text
+	
+  tran3216 "not.c", "not!"
+  tran3216 "neg.c", "neg!"
+  tran3216 "cmp.c", "cmp!"
+
+  tran1632 "not.c", "not!"
+  tran1632 "neg.c", "neg!"
+  tran1632 "cmp.c", "cmp!"
diff --git a/gas/testsuite/gas/score/rD_rA_BN.d b/gas/testsuite/gas/score/rD_rA_BN.d
new file mode 100644
index 000000000000..505e458fd55e
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA_BN.d
@@ -0,0 +1,144 @@
+#as:
+#objdump: -d
+#source: rD_rA_BN.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	6014      	bitclr!		r0, 0x2
+   2:	6014      	bitclr!		r0, 0x2
+   4:	6f24      	bitclr!		r15, 0x4
+   6:	6f24      	bitclr!		r15, 0x4
+   8:	6f0c      	bitclr!		r15, 0x1
+   a:	6f0c      	bitclr!		r15, 0x1
+   c:	6f1c      	bitclr!		r15, 0x3
+   e:	6f1c      	bitclr!		r15, 0x3
+  10:	681c      	bitclr!		r8, 0x3
+  12:	681c      	bitclr!		r8, 0x3
+  14:	81ef8429 	bitclr.c	r15, r15, 0x1
+  18:	83579029 	bitclr.c	r26, r23, 0x4
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	6015      	bitset!		r0, 0x2
+  22:	6015      	bitset!		r0, 0x2
+  24:	6f25      	bitset!		r15, 0x4
+  26:	6f25      	bitset!		r15, 0x4
+  28:	6f0d      	bitset!		r15, 0x1
+  2a:	6f0d      	bitset!		r15, 0x1
+  2c:	6f1d      	bitset!		r15, 0x3
+  2e:	6f1d      	bitset!		r15, 0x3
+  30:	681d      	bitset!		r8, 0x3
+  32:	681d      	bitset!		r8, 0x3
+  34:	81ef842b 	bitset.c	r15, r15, 0x1
+  38:	8357902b 	bitset.c	r26, r23, 0x4
+  3c:	0000      	nop!
+  3e:	0000      	nop!
+  40:	6017      	bittgl!		r0, 0x2
+  42:	6017      	bittgl!		r0, 0x2
+  44:	6f27      	bittgl!		r15, 0x4
+  46:	6f27      	bittgl!		r15, 0x4
+  48:	6f0f      	bittgl!		r15, 0x1
+  4a:	6f0f      	bittgl!		r15, 0x1
+  4c:	6f1f      	bittgl!		r15, 0x3
+  4e:	6f1f      	bittgl!		r15, 0x3
+  50:	681f      	bittgl!		r8, 0x3
+  52:	681f      	bittgl!		r8, 0x3
+  54:	81ef842f 	bittgl.c	r15, r15, 0x1
+  58:	8357902f 	bittgl.c	r26, r23, 0x4
+  5c:	0000      	nop!
+  5e:	0000      	nop!
+  60:	6011      	slli!		r0, 2
+  62:	6011      	slli!		r0, 2
+  64:	6f21      	slli!		r15, 4
+  66:	6f21      	slli!		r15, 4
+  68:	6f09      	slli!		r15, 1
+  6a:	6f09      	slli!		r15, 1
+  6c:	6f19      	slli!		r15, 3
+  6e:	6f19      	slli!		r15, 3
+  70:	6819      	slli!		r8, 3
+  72:	6819      	slli!		r8, 3
+  74:	81ef8471 	slli.c		r15, r15, 1
+  78:	83579071 	slli.c		r26, r23, 4
+  7c:	0000      	nop!
+  7e:	0000      	nop!
+  80:	6013      	srli!		r0, 2
+  82:	6013      	srli!		r0, 2
+  84:	6f23      	srli!		r15, 4
+  86:	6f23      	srli!		r15, 4
+  88:	6f0b      	srli!		r15, 1
+  8a:	6f0b      	srli!		r15, 1
+  8c:	6f1b      	srli!		r15, 3
+  8e:	6f1b      	srli!		r15, 3
+  90:	681b      	srli!		r8, 3
+  92:	681b      	srli!		r8, 3
+  94:	81ef8475 	srli.c		r15, r15, 1
+  98:	83579075 	srli.c		r26, r23, 4
+  9c:	0000      	nop!
+  9e:	0000      	nop!
+  a0:	80008829 	bitclr.c	r0, r0, 0x2
+  a4:	82958829 	bitclr.c	r20, r21, 0x2
+  a8:	81ef9029 	bitclr.c	r15, r15, 0x4
+  ac:	83359029 	bitclr.c	r25, r21, 0x4
+  b0:	81ef8429 	bitclr.c	r15, r15, 0x1
+  b4:	83368429 	bitclr.c	r25, r22, 0x1
+  b8:	681c      	bitclr!		r8, 0x3
+  ba:	681c      	bitclr!		r8, 0x3
+  bc:	6624      	bitclr!		r6, 0x4
+  be:	6624      	bitclr!		r6, 0x4
+  c0:	6914      	bitclr!		r9, 0x2
+  c2:	6914      	bitclr!		r9, 0x2
+	...
+  d0:	8000882b 	bitset.c	r0, r0, 0x2
+  d4:	8295882b 	bitset.c	r20, r21, 0x2
+  d8:	81ef902b 	bitset.c	r15, r15, 0x4
+  dc:	8335902b 	bitset.c	r25, r21, 0x4
+  e0:	81ef842b 	bitset.c	r15, r15, 0x1
+  e4:	8336842b 	bitset.c	r25, r22, 0x1
+  e8:	681d      	bitset!		r8, 0x3
+  ea:	681d      	bitset!		r8, 0x3
+  ec:	6625      	bitset!		r6, 0x4
+  ee:	6625      	bitset!		r6, 0x4
+  f0:	6915      	bitset!		r9, 0x2
+  f2:	6915      	bitset!		r9, 0x2
+	...
+ 100:	8000882f 	bittgl.c	r0, r0, 0x2
+ 104:	8295882f 	bittgl.c	r20, r21, 0x2
+ 108:	81ef902f 	bittgl.c	r15, r15, 0x4
+ 10c:	8335902f 	bittgl.c	r25, r21, 0x4
+ 110:	81ef842f 	bittgl.c	r15, r15, 0x1
+ 114:	8336842f 	bittgl.c	r25, r22, 0x1
+ 118:	681f      	bittgl!		r8, 0x3
+ 11a:	681f      	bittgl!		r8, 0x3
+ 11c:	6627      	bittgl!		r6, 0x4
+ 11e:	6627      	bittgl!		r6, 0x4
+ 120:	6917      	bittgl!		r9, 0x2
+ 122:	6917      	bittgl!		r9, 0x2
+	...
+ 130:	80008871 	slli.c		r0, r0, 2
+ 134:	82958871 	slli.c		r20, r21, 2
+ 138:	81ef9071 	slli.c		r15, r15, 4
+ 13c:	83359071 	slli.c		r25, r21, 4
+ 140:	81ef8471 	slli.c		r15, r15, 1
+ 144:	83368471 	slli.c		r25, r22, 1
+ 148:	6819      	slli!		r8, 3
+ 14a:	6819      	slli!		r8, 3
+ 14c:	6621      	slli!		r6, 4
+ 14e:	6621      	slli!		r6, 4
+ 150:	6911      	slli!		r9, 2
+ 152:	6911      	slli!		r9, 2
+	...
+ 160:	80008875 	srli.c		r0, r0, 2
+ 164:	82958875 	srli.c		r20, r21, 2
+ 168:	81ef9075 	srli.c		r15, r15, 4
+ 16c:	83359075 	srli.c		r25, r21, 4
+ 170:	81ef8475 	srli.c		r15, r15, 1
+ 174:	83368475 	srli.c		r25, r22, 1
+ 178:	681b      	srli!		r8, 3
+ 17a:	681b      	srli!		r8, 3
+ 17c:	6623      	srli!		r6, 4
+ 17e:	6623      	srli!		r6, 4
+ 180:	6913      	srli!		r9, 2
+ 182:	6913      	srli!		r9, 2
+#pass
diff --git a/gas/testsuite/gas/score/rD_rA_BN.s b/gas/testsuite/gas/score/rD_rA_BN.s
new file mode 100644
index 000000000000..224438f85b23
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA_BN.s
@@ -0,0 +1,73 @@
+/*
+ * test relax
+ * bitclr.c <-> bitclr! : register number must be in 0-15
+ * bitset.c <-> bitset! : register number must be in 0-15
+ * bittgl.c <-> bittgl! : register number must be in 0-15
+ * slli.c <-> slli!     : register number must be in 0-15
+ * srli.c <-> srli!     : register number must be in 0-15
+
+ * Author: ligang
+ */
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0, r0, 2          #32b -> 16b
+  \insn16 r0, 2
+
+  \insn32 r15, r15, 4        #32b -> 16b
+  \insn16 r15, 4
+
+  \insn32 r15, r15, 1        #32b -> 16b
+  \insn16 r15, 1
+
+  \insn16 r15, 3
+  \insn32 r15, r15, 3        #32b -> 16b
+
+  \insn32 r8, r8, 3          #32b -> 16b
+  \insn32 r8, r8, 3          #32b -> 16b
+	
+  \insn32 r15, r15, 1        #No transform
+  \insn32 r26, r23, 4
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, 2         #16b -> 32b
+  \insn32 r20, r21, 2
+	
+  \insn16 r15, 4        #16b -> 32b
+  \insn32 r25, r21, 4
+
+  \insn16 r15, 1        #16b -> 32b
+  \insn32 r25, r22, 1
+
+  \insn16 r8, 3         #No transform
+  \insn16 r8, 3         #No transform
+	
+  \insn16 r6, 4         #No transform
+  \insn32 r6, r6, 4     #32b -> 16b
+
+  \insn32 r9, r9, 2     #32b -> 16b
+  \insn16 r9, 2         #No transform  
+	
+.endm
+		
+.text
+
+  tran3216 "bitclr.c", "bitclr!"
+  tran3216 "bitset.c", "bitset!"
+  tran3216 "bittgl.c", "bittgl!"
+  tran3216 "slli.c", "slli!"
+  tran3216 "srli.c", "srli!"
+
+  tran1632 "bitclr.c", "bitclr!"
+  tran1632 "bitset.c", "bitset!"
+  tran1632 "bittgl.c", "bittgl!"
+  tran1632 "slli.c", "slli!"
+  tran1632 "srli.c", "srli!"
+	
diff --git a/gas/testsuite/gas/score/rD_rA_rB.d b/gas/testsuite/gas/score/rD_rA_rB.d
new file mode 100644
index 000000000000..d897ebc7391b
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA_rB.d
@@ -0,0 +1,252 @@
+#as:
+#objdump: -d
+#source: rD_rA_rB.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	2020      	add!		r0, r2
+   2:	2020      	add!		r0, r2
+   4:	2540      	add!		r5, r4
+   6:	2540      	add!		r5, r4
+   8:	2f40      	add!		r15, r4
+   a:	2f40      	add!		r15, r4
+   c:	2f30      	add!		r15, r3
+   e:	2f30      	add!		r15, r3
+  10:	2830      	add!		r8, r3
+  12:	2830      	add!		r8, r3
+  14:	81ef9811 	add.c		r15, r15, r6
+  18:	83579011 	add.c		r26, r23, r4
+  1c:	0000      	nop!
+  1e:	0000      	nop!
+  20:	0029      	addc!		r0, r2
+  22:	0029      	addc!		r0, r2
+  24:	0549      	addc!		r5, r4
+  26:	0549      	addc!		r5, r4
+  28:	0f49      	addc!		r15, r4
+  2a:	0f49      	addc!		r15, r4
+  2c:	0f39      	addc!		r15, r3
+  2e:	0f39      	addc!		r15, r3
+  30:	0839      	addc!		r8, r3
+  32:	0839      	addc!		r8, r3
+  34:	81ef9813 	addc.c		r15, r15, r6
+  38:	83579013 	addc.c		r26, r23, r4
+  3c:	0000      	nop!
+  3e:	0000      	nop!
+  40:	2021      	sub!		r0, r2
+  42:	2021      	sub!		r0, r2
+  44:	2541      	sub!		r5, r4
+  46:	2541      	sub!		r5, r4
+  48:	2f41      	sub!		r15, r4
+  4a:	2f41      	sub!		r15, r4
+  4c:	2f31      	sub!		r15, r3
+  4e:	2f31      	sub!		r15, r3
+  50:	2831      	sub!		r8, r3
+  52:	2831      	sub!		r8, r3
+  54:	81ef9815 	sub.c		r15, r15, r6
+  58:	83579015 	sub.c		r26, r23, r4
+  5c:	0000      	nop!
+  5e:	0000      	nop!
+  60:	2024      	and!		r0, r2
+  62:	2024      	and!		r0, r2
+  64:	2544      	and!		r5, r4
+  66:	2544      	and!		r5, r4
+  68:	2f44      	and!		r15, r4
+  6a:	2f44      	and!		r15, r4
+  6c:	2f34      	and!		r15, r3
+  6e:	2f34      	and!		r15, r3
+  70:	2834      	and!		r8, r3
+  72:	2834      	and!		r8, r3
+  74:	81ef9821 	and.c		r15, r15, r6
+  78:	83579021 	and.c		r26, r23, r4
+  7c:	0000      	nop!
+  7e:	0000      	nop!
+  80:	2025      	or!		r0, r2
+  82:	2025      	or!		r0, r2
+  84:	2545      	or!		r5, r4
+  86:	2545      	or!		r5, r4
+  88:	2f45      	or!		r15, r4
+  8a:	2f45      	or!		r15, r4
+  8c:	2f35      	or!		r15, r3
+  8e:	2f35      	or!		r15, r3
+  90:	2835      	or!		r8, r3
+  92:	2835      	or!		r8, r3
+  94:	81ef9823 	or.c		r15, r15, r6
+  98:	83579023 	or.c		r26, r23, r4
+  9c:	0000      	nop!
+  9e:	0000      	nop!
+  a0:	2027      	xor!		r0, r2
+  a2:	2027      	xor!		r0, r2
+  a4:	2547      	xor!		r5, r4
+  a6:	2547      	xor!		r5, r4
+  a8:	2f47      	xor!		r15, r4
+  aa:	2f47      	xor!		r15, r4
+  ac:	2f37      	xor!		r15, r3
+  ae:	2f37      	xor!		r15, r3
+  b0:	2837      	xor!		r8, r3
+  b2:	2837      	xor!		r8, r3
+  b4:	81ef9827 	xor.c		r15, r15, r6
+  b8:	83579027 	xor.c		r26, r23, r4
+  bc:	0000      	nop!
+  be:	0000      	nop!
+  c0:	002b      	sra!		r0, r2
+  c2:	002b      	sra!		r0, r2
+  c4:	054b      	sra!		r5, r4
+  c6:	054b      	sra!		r5, r4
+  c8:	0f4b      	sra!		r15, r4
+  ca:	0f4b      	sra!		r15, r4
+  cc:	0f3b      	sra!		r15, r3
+  ce:	0f3b      	sra!		r15, r3
+  d0:	083b      	sra!		r8, r3
+  d2:	083b      	sra!		r8, r3
+  d4:	81ef9837 	sra.c		r15, r15, r6
+  d8:	83579037 	sra.c		r26, r23, r4
+  dc:	0000      	nop!
+  de:	0000      	nop!
+  e0:	002a      	srl!		r0, r2
+  e2:	002a      	srl!		r0, r2
+  e4:	054a      	srl!		r5, r4
+  e6:	054a      	srl!		r5, r4
+  e8:	0f4a      	srl!		r15, r4
+  ea:	0f4a      	srl!		r15, r4
+  ec:	0f3a      	srl!		r15, r3
+  ee:	0f3a      	srl!		r15, r3
+  f0:	083a      	srl!		r8, r3
+  f2:	083a      	srl!		r8, r3
+  f4:	81ef9835 	srl.c		r15, r15, r6
+  f8:	83579035 	srl.c		r26, r23, r4
+  fc:	0000      	nop!
+  fe:	0000      	nop!
+ 100:	0028      	sll!		r0, r2
+ 102:	0028      	sll!		r0, r2
+ 104:	0548      	sll!		r5, r4
+ 106:	0548      	sll!		r5, r4
+ 108:	0f48      	sll!		r15, r4
+ 10a:	0f48      	sll!		r15, r4
+ 10c:	0f38      	sll!		r15, r3
+ 10e:	0f38      	sll!		r15, r3
+ 110:	0838      	sll!		r8, r3
+ 112:	0838      	sll!		r8, r3
+ 114:	81ef9831 	sll.c		r15, r15, r6
+ 118:	83579031 	sll.c		r26, r23, r4
+ 11c:	0000      	nop!
+ 11e:	0000      	nop!
+ 120:	80008811 	add.c		r0, r0, r2
+ 124:	82958811 	add.c		r20, r21, r2
+ 128:	81ef9011 	add.c		r15, r15, r4
+ 12c:	83359011 	add.c		r25, r21, r4
+ 130:	81ef8c11 	add.c		r15, r15, r3
+ 134:	83368c11 	add.c		r25, r22, r3
+ 138:	2870      	add!		r8, r7
+ 13a:	2870      	add!		r8, r7
+ 13c:	2640      	add!		r6, r4
+ 13e:	2640      	add!		r6, r4
+ 140:	2740      	add!		r7, r4
+ 142:	2740      	add!		r7, r4
+	...
+ 150:	80008813 	addc.c		r0, r0, r2
+ 154:	82958813 	addc.c		r20, r21, r2
+ 158:	81ef9013 	addc.c		r15, r15, r4
+ 15c:	83359013 	addc.c		r25, r21, r4
+ 160:	81ef8c13 	addc.c		r15, r15, r3
+ 164:	83368c13 	addc.c		r25, r22, r3
+ 168:	0879      	addc!		r8, r7
+ 16a:	0879      	addc!		r8, r7
+ 16c:	0649      	addc!		r6, r4
+ 16e:	0649      	addc!		r6, r4
+ 170:	0749      	addc!		r7, r4
+ 172:	0749      	addc!		r7, r4
+	...
+ 180:	80008815 	sub.c		r0, r0, r2
+ 184:	82958815 	sub.c		r20, r21, r2
+ 188:	81ef9015 	sub.c		r15, r15, r4
+ 18c:	83359015 	sub.c		r25, r21, r4
+ 190:	81ef8c15 	sub.c		r15, r15, r3
+ 194:	83368c15 	sub.c		r25, r22, r3
+ 198:	2871      	sub!		r8, r7
+ 19a:	2871      	sub!		r8, r7
+ 19c:	2641      	sub!		r6, r4
+ 19e:	2641      	sub!		r6, r4
+ 1a0:	2741      	sub!		r7, r4
+ 1a2:	2741      	sub!		r7, r4
+	...
+ 1b0:	80008821 	and.c		r0, r0, r2
+ 1b4:	82958821 	and.c		r20, r21, r2
+ 1b8:	81ef9021 	and.c		r15, r15, r4
+ 1bc:	83359021 	and.c		r25, r21, r4
+ 1c0:	81ef8c21 	and.c		r15, r15, r3
+ 1c4:	83368c21 	and.c		r25, r22, r3
+ 1c8:	2874      	and!		r8, r7
+ 1ca:	2874      	and!		r8, r7
+ 1cc:	2644      	and!		r6, r4
+ 1ce:	2644      	and!		r6, r4
+ 1d0:	2744      	and!		r7, r4
+ 1d2:	2744      	and!		r7, r4
+	...
+ 1e0:	80008823 	or.c		r0, r0, r2
+ 1e4:	82958823 	or.c		r20, r21, r2
+ 1e8:	81ef9023 	or.c		r15, r15, r4
+ 1ec:	83359023 	or.c		r25, r21, r4
+ 1f0:	81ef8c23 	or.c		r15, r15, r3
+ 1f4:	83368c23 	or.c		r25, r22, r3
+ 1f8:	2875      	or!		r8, r7
+ 1fa:	2875      	or!		r8, r7
+ 1fc:	2645      	or!		r6, r4
+ 1fe:	2645      	or!		r6, r4
+ 200:	2745      	or!		r7, r4
+ 202:	2745      	or!		r7, r4
+	...
+ 210:	80008827 	xor.c		r0, r0, r2
+ 214:	82958827 	xor.c		r20, r21, r2
+ 218:	81ef9027 	xor.c		r15, r15, r4
+ 21c:	83359027 	xor.c		r25, r21, r4
+ 220:	81ef8c27 	xor.c		r15, r15, r3
+ 224:	83368c27 	xor.c		r25, r22, r3
+ 228:	2877      	xor!		r8, r7
+ 22a:	2877      	xor!		r8, r7
+ 22c:	2647      	xor!		r6, r4
+ 22e:	2647      	xor!		r6, r4
+ 230:	2747      	xor!		r7, r4
+ 232:	2747      	xor!		r7, r4
+	...
+ 240:	80008837 	sra.c		r0, r0, r2
+ 244:	82958837 	sra.c		r20, r21, r2
+ 248:	81ef9037 	sra.c		r15, r15, r4
+ 24c:	83359037 	sra.c		r25, r21, r4
+ 250:	81ef8c37 	sra.c		r15, r15, r3
+ 254:	83368c37 	sra.c		r25, r22, r3
+ 258:	087b      	sra!		r8, r7
+ 25a:	087b      	sra!		r8, r7
+ 25c:	064b      	sra!		r6, r4
+ 25e:	064b      	sra!		r6, r4
+ 260:	074b      	sra!		r7, r4
+ 262:	074b      	sra!		r7, r4
+	...
+ 270:	80008835 	srl.c		r0, r0, r2
+ 274:	82958835 	srl.c		r20, r21, r2
+ 278:	81ef9035 	srl.c		r15, r15, r4
+ 27c:	83359035 	srl.c		r25, r21, r4
+ 280:	81ef8c35 	srl.c		r15, r15, r3
+ 284:	83368c35 	srl.c		r25, r22, r3
+ 288:	087a      	srl!		r8, r7
+ 28a:	087a      	srl!		r8, r7
+ 28c:	064a      	srl!		r6, r4
+ 28e:	064a      	srl!		r6, r4
+ 290:	074a      	srl!		r7, r4
+ 292:	074a      	srl!		r7, r4
+	...
+ 2a0:	80008831 	sll.c		r0, r0, r2
+ 2a4:	82958831 	sll.c		r20, r21, r2
+ 2a8:	81ef9031 	sll.c		r15, r15, r4
+ 2ac:	83359031 	sll.c		r25, r21, r4
+ 2b0:	81ef8c31 	sll.c		r15, r15, r3
+ 2b4:	83368c31 	sll.c		r25, r22, r3
+ 2b8:	0878      	sll!		r8, r7
+ 2ba:	0878      	sll!		r8, r7
+ 2bc:	0648      	sll!		r6, r4
+ 2be:	0648      	sll!		r6, r4
+ 2c0:	0748      	sll!		r7, r4
+ 2c2:	0748      	sll!		r7, r4
+#pass
diff --git a/gas/testsuite/gas/score/rD_rA_rB.s b/gas/testsuite/gas/score/rD_rA_rB.s
new file mode 100644
index 000000000000..1a72b131109c
--- /dev/null
+++ b/gas/testsuite/gas/score/rD_rA_rB.s
@@ -0,0 +1,86 @@
+/*
+ * test relax
+ * add.c  <-> add!  : register number must be in 0-15
+ * addc.c <-> addc! : register number must be in 0-15
+ * sub.c  <-> sub!  : register number must be in 0-15
+ * and.c  <-> and!  : register number must be in 0-15
+ * or.c   <-> or!   : register number must be in 0-15
+ * xor.c  <-> xor!  : register number must be in 0-15
+ * sra.c  <-> sra!  : register number must be in 0-15
+ * srl.c  <-> srl!  : register number must be in 0-15
+ * sll.c  <-> sll!  : register number must be in 0-15
+
+ * Author: ligang
+ */
+
+
+/* This macro transform 32b instruction to 16b. */
+.macro tran3216 insn32, insn16
+.align 4
+
+  \insn32 r0, r0, r2          #32b -> 16b
+  \insn16 r0, r2
+
+  \insn32 r5, r5, r4          #32b -> 16b
+  \insn16 r5, r4
+
+  \insn32 r15, r15, r4        #32b -> 16b
+  \insn16 r15, r4
+
+  \insn16 r15, r3
+  \insn32 r15, r15, r3        #32b -> 16b
+
+  \insn32 r8, r8, r3          #32b -> 16b
+  \insn32 r8, r8, r3          #32b -> 16b
+	
+  \insn32 r15, r15, r6        #No transform
+  \insn32 r26, r23, r4
+
+.endm
+
+/* This macro transform 16b instruction to 32b. */
+.macro tran1632 insn32, insn16
+.align 4
+
+  \insn16 r0, r2         #16b -> 32b
+  \insn32 r20, r21, r2
+
+  \insn16 r15, r4        #16b -> 32b
+  \insn32 r25, r21, r4
+	
+  \insn16 r15, r3        #16b -> 32b
+  \insn32 r25, r22, r3
+
+  \insn16 r8, r7         #No transform
+  \insn16 r8, r7         #No transform
+		
+  \insn16 r6, r4         #No transform
+  \insn32 r6, r6, r4
+	
+  \insn32 r7, r7, r4     #32b -> 16b
+  \insn16 r7, r4         #No transform
+	
+.endm
+		
+.text
+	
+  tran3216 "add.c", "add!"
+  tran3216 "addc.c", "addc!"
+  tran3216 "sub.c", "sub!"
+  tran3216 "and.c", "and!"
+  tran3216 "or.c", "or!"
+  tran3216 "xor.c", "xor!"
+  tran3216 "sra.c", "sra!"
+  tran3216 "srl.c", "srl!"
+  tran3216 "sll.c", "sll!"	
+
+  tran1632 "add.c", "add!"
+  tran1632 "addc.c", "addc!"
+  tran1632 "sub.c", "sub!"
+  tran1632 "and.c", "and!"
+  tran1632 "or.c", "or!"
+  tran1632 "xor.c", "xor!"
+  tran1632 "sra.c", "sra!"
+  tran1632 "srl.c", "srl!"
+  tran1632 "sll.c", "sll!"	
+
diff --git a/gas/testsuite/gas/score/relax.exp b/gas/testsuite/gas/score/relax.exp
new file mode 100644
index 000000000000..6a8f2b838bcb
--- /dev/null
+++ b/gas/testsuite/gas/score/relax.exp
@@ -0,0 +1,20 @@
+# test relax
+
+if [istarget score-*-*] then {
+    run_dump_test "ldi"
+    run_dump_test "nop"
+    run_dump_test "tcond"
+    run_dump_test "ls32ls16"
+    run_dump_test "ls32ls16p"
+    run_dump_test "postlw"
+    run_dump_test "presw"
+    run_dump_test "rD_rA_rB"
+    run_dump_test "bittst"
+    run_dump_test "addi"
+    run_dump_test "br"
+    run_dump_test "b"
+    run_dump_test "move"
+    run_dump_test "rD_rA_BN"
+    run_dump_test "rD_rA"
+}
+
diff --git a/gas/testsuite/gas/score/tcond.d b/gas/testsuite/gas/score/tcond.d
new file mode 100644
index 000000000000..04460cfcb0a1
--- /dev/null
+++ b/gas/testsuite/gas/score/tcond.d
@@ -0,0 +1,264 @@
+#as:
+#objdump: -d
+#source: tcond.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	0f05      	tset!
+   2:	0f05      	tset!
+   4:	0f05      	tset!
+   6:	0f05      	tset!
+   8:	0f05      	tset!
+   a:	0f05      	tset!
+   c:	8000bc54 	tset
+  10:	8254e010 	add		r18, r20, r24
+	...
+  20:	0f05      	tset!
+  22:	0f05      	tset!
+  24:	0f05      	tset!
+  26:	0f05      	tset!
+  28:	8000bc54 	tset
+  2c:	8254e026 	xor		r18, r20, r24
+  30:	0005      	tcs!
+  32:	0005      	tcs!
+  34:	0005      	tcs!
+  36:	0005      	tcs!
+  38:	0005      	tcs!
+  3a:	0005      	tcs!
+  3c:	80008054 	tcs
+  40:	8254e010 	add		r18, r20, r24
+	...
+  50:	0005      	tcs!
+  52:	0005      	tcs!
+  54:	0005      	tcs!
+  56:	0005      	tcs!
+  58:	80008054 	tcs
+  5c:	8254e026 	xor		r18, r20, r24
+  60:	0105      	tcc!
+  62:	0105      	tcc!
+  64:	0105      	tcc!
+  66:	0105      	tcc!
+  68:	0105      	tcc!
+  6a:	0105      	tcc!
+  6c:	80008454 	tcc
+  70:	8254e010 	add		r18, r20, r24
+	...
+  80:	0105      	tcc!
+  82:	0105      	tcc!
+  84:	0105      	tcc!
+  86:	0105      	tcc!
+  88:	80008454 	tcc
+  8c:	8254e026 	xor		r18, r20, r24
+  90:	0205      	tgtu!
+  92:	0205      	tgtu!
+  94:	0205      	tgtu!
+  96:	0205      	tgtu!
+  98:	0205      	tgtu!
+  9a:	0205      	tgtu!
+  9c:	80008854 	tgtu
+  a0:	8254e010 	add		r18, r20, r24
+	...
+  b0:	0205      	tgtu!
+  b2:	0205      	tgtu!
+  b4:	0205      	tgtu!
+  b6:	0205      	tgtu!
+  b8:	80008854 	tgtu
+  bc:	8254e026 	xor		r18, r20, r24
+  c0:	0305      	tleu!
+  c2:	0305      	tleu!
+  c4:	0305      	tleu!
+  c6:	0305      	tleu!
+  c8:	0305      	tleu!
+  ca:	0305      	tleu!
+  cc:	80008c54 	tleu
+  d0:	8254e010 	add		r18, r20, r24
+	...
+  e0:	0305      	tleu!
+  e2:	0305      	tleu!
+  e4:	0305      	tleu!
+  e6:	0305      	tleu!
+  e8:	80008c54 	tleu
+  ec:	8254e026 	xor		r18, r20, r24
+  f0:	0405      	teq!
+  f2:	0405      	teq!
+  f4:	0405      	teq!
+  f6:	0405      	teq!
+  f8:	0405      	teq!
+  fa:	0405      	teq!
+  fc:	80009054 	teq
+ 100:	8254e010 	add		r18, r20, r24
+	...
+ 110:	0405      	teq!
+ 112:	0405      	teq!
+ 114:	0405      	teq!
+ 116:	0405      	teq!
+ 118:	80009054 	teq
+ 11c:	8254e026 	xor		r18, r20, r24
+ 120:	0505      	tne!
+ 122:	0505      	tne!
+ 124:	0505      	tne!
+ 126:	0505      	tne!
+ 128:	0505      	tne!
+ 12a:	0505      	tne!
+ 12c:	80009454 	tne
+ 130:	8254e010 	add		r18, r20, r24
+	...
+ 140:	0505      	tne!
+ 142:	0505      	tne!
+ 144:	0505      	tne!
+ 146:	0505      	tne!
+ 148:	80009454 	tne
+ 14c:	8254e026 	xor		r18, r20, r24
+ 150:	0605      	tgt!
+ 152:	0605      	tgt!
+ 154:	0605      	tgt!
+ 156:	0605      	tgt!
+ 158:	0605      	tgt!
+ 15a:	0605      	tgt!
+ 15c:	80009854 	tgt
+ 160:	8254e010 	add		r18, r20, r24
+	...
+ 170:	0605      	tgt!
+ 172:	0605      	tgt!
+ 174:	0605      	tgt!
+ 176:	0605      	tgt!
+ 178:	80009854 	tgt
+ 17c:	8254e026 	xor		r18, r20, r24
+ 180:	0705      	tle!
+ 182:	0705      	tle!
+ 184:	0705      	tle!
+ 186:	0705      	tle!
+ 188:	0705      	tle!
+ 18a:	0705      	tle!
+ 18c:	80009c54 	tle
+ 190:	8254e010 	add		r18, r20, r24
+	...
+ 1a0:	0705      	tle!
+ 1a2:	0705      	tle!
+ 1a4:	0705      	tle!
+ 1a6:	0705      	tle!
+ 1a8:	80009c54 	tle
+ 1ac:	8254e026 	xor		r18, r20, r24
+ 1b0:	0805      	tge!
+ 1b2:	0805      	tge!
+ 1b4:	0805      	tge!
+ 1b6:	0805      	tge!
+ 1b8:	0805      	tge!
+ 1ba:	0805      	tge!
+ 1bc:	8000a054 	tge
+ 1c0:	8254e010 	add		r18, r20, r24
+	...
+ 1d0:	0805      	tge!
+ 1d2:	0805      	tge!
+ 1d4:	0805      	tge!
+ 1d6:	0805      	tge!
+ 1d8:	8000a054 	tge
+ 1dc:	8254e026 	xor		r18, r20, r24
+ 1e0:	0905      	tlt!
+ 1e2:	0905      	tlt!
+ 1e4:	0905      	tlt!
+ 1e6:	0905      	tlt!
+ 1e8:	0905      	tlt!
+ 1ea:	0905      	tlt!
+ 1ec:	8000a454 	tlt
+ 1f0:	8254e010 	add		r18, r20, r24
+	...
+ 200:	0905      	tlt!
+ 202:	0905      	tlt!
+ 204:	0905      	tlt!
+ 206:	0905      	tlt!
+ 208:	8000a454 	tlt
+ 20c:	8254e026 	xor		r18, r20, r24
+ 210:	0a05      	tmi!
+ 212:	0a05      	tmi!
+ 214:	0a05      	tmi!
+ 216:	0a05      	tmi!
+ 218:	0a05      	tmi!
+ 21a:	0a05      	tmi!
+ 21c:	8000a854 	tmi
+ 220:	8254e010 	add		r18, r20, r24
+	...
+ 230:	0a05      	tmi!
+ 232:	0a05      	tmi!
+ 234:	0a05      	tmi!
+ 236:	0a05      	tmi!
+ 238:	8000a854 	tmi
+ 23c:	8254e026 	xor		r18, r20, r24
+ 240:	0b05      	tpl!
+ 242:	0b05      	tpl!
+ 244:	0b05      	tpl!
+ 246:	0b05      	tpl!
+ 248:	0b05      	tpl!
+ 24a:	0b05      	tpl!
+ 24c:	8000ac54 	tpl
+ 250:	8254e010 	add		r18, r20, r24
+	...
+ 260:	0b05      	tpl!
+ 262:	0b05      	tpl!
+ 264:	0b05      	tpl!
+ 266:	0b05      	tpl!
+ 268:	8000ac54 	tpl
+ 26c:	8254e026 	xor		r18, r20, r24
+ 270:	0c05      	tvs!
+ 272:	0c05      	tvs!
+ 274:	0c05      	tvs!
+ 276:	0c05      	tvs!
+ 278:	0c05      	tvs!
+ 27a:	0c05      	tvs!
+ 27c:	8000b054 	tvs
+ 280:	8254e010 	add		r18, r20, r24
+	...
+ 290:	0c05      	tvs!
+ 292:	0c05      	tvs!
+ 294:	0c05      	tvs!
+ 296:	0c05      	tvs!
+ 298:	8000b054 	tvs
+ 29c:	8254e026 	xor		r18, r20, r24
+ 2a0:	0d05      	tvc!
+ 2a2:	0d05      	tvc!
+ 2a4:	0d05      	tvc!
+ 2a6:	0d05      	tvc!
+ 2a8:	0d05      	tvc!
+ 2aa:	0d05      	tvc!
+ 2ac:	8000b454 	tvc
+ 2b0:	8254e010 	add		r18, r20, r24
+	...
+ 2c0:	0d05      	tvc!
+ 2c2:	0d05      	tvc!
+ 2c4:	0d05      	tvc!
+ 2c6:	0d05      	tvc!
+ 2c8:	8000b454 	tvc
+ 2cc:	8254e026 	xor		r18, r20, r24
+ 2d0:	0e05      	tcnz!
+ 2d2:	0e05      	tcnz!
+ 2d4:	0e05      	tcnz!
+ 2d6:	0e05      	tcnz!
+ 2d8:	0e05      	tcnz!
+ 2da:	0e05      	tcnz!
+ 2dc:	8000b854 	tcnz
+ 2e0:	8254e010 	add		r18, r20, r24
+	...
+ 2f0:	0e05      	tcnz!
+ 2f2:	0e05      	tcnz!
+ 2f4:	0e05      	tcnz!
+ 2f6:	0e05      	tcnz!
+ 2f8:	8000b854 	tcnz
+ 2fc:	8254e026 	xor		r18, r20, r24
+ 300:	6062      	sdbbp!		12
+ 302:	6062      	sdbbp!		12
+ 304:	6062      	sdbbp!		12
+ 306:	6062      	sdbbp!		12
+ 308:	6062      	sdbbp!		12
+ 30a:	6062      	sdbbp!		12
+ 30c:	800c8006 	sdbbp		12
+ 310:	8254e010 	add		r18, r20, r24
+	...
+ 320:	6062      	sdbbp!		12
+ 322:	6062      	sdbbp!		12
+ 324:	6062      	sdbbp!		12
+ 326:	6062      	sdbbp!		12
+ 328:	800c8006 	sdbbp		12
+ 32c:	8254e026 	xor		r18, r20, r24
diff --git a/gas/testsuite/gas/score/tcond.s b/gas/testsuite/gas/score/tcond.s
new file mode 100644
index 000000000000..fe89bad3a1d7
--- /dev/null
+++ b/gas/testsuite/gas/score/tcond.s
@@ -0,0 +1,55 @@
+/*
+ * test relax
+ * Tcond <-> Tcond!
+ * sdbbp <-> sdbbp!
+	
+ * Author: ligang
+ */
+
+.macro tran insn32, insn16
+/* This block transform 32b instruction to 16b. */
+.align 4
+	
+  \insn32               #32b -> 16b
+  \insn16
+
+  \insn32               #32b -> 16b
+  \insn32               #32b -> 16b
+
+  \insn16      
+  \insn32               #32b -> 16b
+
+  \insn32               #No transform
+  add r18, r20, r24
+
+/* This block transform 16b instruction to 32b. */
+.align 4
+	
+  \insn16               #No transform
+  \insn32
+
+  \insn16               #No transform
+  \insn16
+
+  \insn16               #16b -> 32b
+  xor r18, r20, r24
+	
+.endm
+
+  tran "tset", "tset!"
+  tran "tcs",  "tcs!"
+  tran "tcc",  "tcc!"
+  tran "tgtu", "tgtu!"
+  tran "tleu", "tleu!"
+  tran "teq",  "teq!"
+  tran "tne",  "tne!"
+  tran "tgt",  "tgt!"
+  tran "tle",  "tle!"
+  tran "tge",  "tge!"
+  tran "tlt",  "tlt!"
+  tran "tmi",  "tmi!"
+  tran "tpl",  "tpl!"
+  tran "tvs",  "tvs!"
+  tran "tvc",  "tvc!"
+  tran "tcnz", "tcnz!"
+  tran "sdbbp 12", "sdbbp! 12"
diff --git a/gas/testsuite/gas/sh/basic.exp b/gas/testsuite/gas/sh/basic.exp
index 093048b87dc9..2f9424d98e6f 100644
--- a/gas/testsuite/gas/sh/basic.exp
+++ b/gas/testsuite/gas/sh/basic.exp
@@ -167,6 +167,8 @@ if [istarget sh*-*-*] then {
 
 	# Test --allow-reg-prefix.
 	run_dump_test "reg-prefix"
+
+	run_dump_test "too_large"
     }
 }
 
diff --git a/gas/testsuite/gas/sh/pcrel-coff.d b/gas/testsuite/gas/sh/pcrel-coff.d
index eaca1fd7cea2..9946bf51e151 100644
--- a/gas/testsuite/gas/sh/pcrel-coff.d
+++ b/gas/testsuite/gas/sh/pcrel-coff.d
@@ -7,11 +7,11 @@
 Disassembly of section .text:
 
 00000000 <code>:
-   0:	d1 03       	mov\.l	10 <litpool>,r1	! 0xfffffff0
-   2:	d1 03       	mov\.l	10 <litpool>,r1	! 0xfffffff0
+   0:	d1 03       	mov\.l	10 <litpool>,r1	! fffffff0
+   2:	d1 03       	mov\.l	10 <litpool>,r1	! fffffff0
    4:	c7 02       	mova	10 <litpool>,r0
    6:	61 02       	mov\.l	@r0,r1
-   8:	d1 01       	mov\.l	10 <litpool>,r1	! 0xfffffff0
+   8:	d1 01       	mov\.l	10 <litpool>,r1	! fffffff0
    a:	01 03       	bsrf	r1
    c:	00 09       	nop	
    e:	00 09       	nop	
diff --git a/gas/testsuite/gas/sh/pcrel-hms.d b/gas/testsuite/gas/sh/pcrel-hms.d
index 12df66771932..233886d88568 100644
--- a/gas/testsuite/gas/sh/pcrel-hms.d
+++ b/gas/testsuite/gas/sh/pcrel-hms.d
@@ -9,13 +9,13 @@
 Disassembly of section .text:
 
 00000000 <code>:
-   0:	d0 04       	mov\.l	14 <litpool>,r0	! 0xffffffec
-   2:	d1 05       	mov\.l	18 <litpool\+0x4>,r1	! 0x90009
-   4:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
-   6:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   0:	d0 04       	mov\.l	14 <litpool>,r0	! ffffffec
+   2:	d1 05       	mov\.l	18 <litpool\+0x4>,r1	! 90009
+   4:	d1 03       	mov\.l	14 <litpool>,r1	! ffffffec
+   6:	d1 03       	mov\.l	14 <litpool>,r1	! ffffffec
    8:	c7 02       	mova	14 <litpool>,r0
    a:	61 02       	mov\.l	@r0,r1
-   c:	d1 01       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   c:	d1 01       	mov\.l	14 <litpool>,r1	! ffffffec
    e:	01 03       	bsrf	r1
   10:	00 09       	nop	
   12:	00 09       	nop	
diff --git a/gas/testsuite/gas/sh/pcrel.d b/gas/testsuite/gas/sh/pcrel.d
index 9e81b60cdf8f..b9f8fcd5560c 100644
--- a/gas/testsuite/gas/sh/pcrel.d
+++ b/gas/testsuite/gas/sh/pcrel.d
@@ -8,13 +8,13 @@
 Disassembly of section .text:
 
 00000000 <code>:
-   0:	d0 04       	mov\.l	14 <litpool>,r0	! 0xffffffec
+   0:	d0 04       	mov\.l	14 <litpool>,r0	! ffffffec
    2:	d1 05       	mov\.l	18 <litpool\+0x4>,r1
-   4:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
-   6:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   4:	d1 03       	mov\.l	14 <litpool>,r1	! ffffffec
+   6:	d1 03       	mov\.l	14 <litpool>,r1	! ffffffec
    8:	c7 02       	mova	14 <litpool>,r0
    a:	61 02       	mov\.l	@r0,r1
-   c:	d1 01       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   c:	d1 01       	mov\.l	14 <litpool>,r1	! ffffffec
    e:	01 03       	bsrf	r1
   10:	00 09       	nop	
   12:	00 09       	nop	
diff --git a/gas/testsuite/gas/sh/pcrel2.d b/gas/testsuite/gas/sh/pcrel2.d
index 21df0aa7d2f2..519214a45c64 100644
--- a/gas/testsuite/gas/sh/pcrel2.d
+++ b/gas/testsuite/gas/sh/pcrel2.d
@@ -8,8 +8,8 @@ Disassembly of section \.text:
 
 00000000 <code>:
    0:	8b 01       	bf	6 <foo>
-   2:	d0 02       	mov\.l	c <bar>,r0	! 0x6 .*
-   4:	90 02       	mov\.w	c <bar>,r0	! 0x0 .*
+   2:	d0 02       	mov\.l	c <bar>,r0	! 6 .*
+   4:	90 02       	mov\.w	c <bar>,r0	! 0 .*
 
 00000006 <foo>:
    6:	af fe       	bra	6 <foo>
diff --git a/gas/testsuite/gas/sh/pic.d b/gas/testsuite/gas/sh/pic.d
index 9a2d0cecdde6..8d3e69fa69df 100644
--- a/gas/testsuite/gas/sh/pic.d
+++ b/gas/testsuite/gas/sh/pic.d
@@ -6,25 +6,25 @@
 
 Disassembly of section \.text:
 0x00000000 c7 0a       	mova	0x0000002c,r0
-0x00000002 dc 0a       	mov\.l	0x0000002c,r12	! 0x0
+0x00000002 dc 0a       	mov\.l	0x0000002c,r12	! 0
 0x00000004 3c 0c       	add	r0,r12
-0x00000006 d0 0a       	mov\.l	0x00000030,r0	! 0x0
+0x00000006 d0 0a       	mov\.l	0x00000030,r0	! 0
 0x00000008 00 ce       	mov\.l	@\(r0,r12\),r0
 0x0000000a 40 0b       	jsr	@r0
 0x0000000c 00 09       	nop	
-0x0000000e d0 09       	mov\.l	0x00000034,r0	! 0x0
+0x0000000e d0 09       	mov\.l	0x00000034,r0	! 0
 0x00000010 30 cc       	add	r12,r0
 0x00000012 40 0b       	jsr	@r0
 0x00000014 00 09       	nop	
-0x00000016 d1 08       	mov\.l	0x00000038,r1	! 0x0
+0x00000016 d1 08       	mov\.l	0x00000038,r1	! 0
 0x00000018 c7 07       	mova	0x00000038,r0
 0x0000001a 30 1c       	add	r1,r0
 0x0000001c 40 0b       	jsr	@r0
 0x0000001e 00 09       	nop	
-0x00000020 d0 06       	mov\.l	0x0000003c,r0	! 0x16
+0x00000020 d0 06       	mov\.l	0x0000003c,r0	! 16
 0x00000022 40 0b       	jsr	@r0
 0x00000024 00 09       	nop	
-0x00000026 d0 06       	mov\.l	0x00000040,r0	! 0x14
+0x00000026 d0 06       	mov\.l	0x00000040,r0	! 14
 0x00000028 40 0b       	jsr	@r0
 0x0000002a 00 09       	nop	
 	\.\.\.
diff --git a/gas/testsuite/gas/sh/sh64/syntax-1.d b/gas/testsuite/gas/sh/sh64/syntax-1.d
index 84a9c2552102..b48329324ad6 100644
--- a/gas/testsuite/gas/sh/sh64/syntax-1.d
+++ b/gas/testsuite/gas/sh/sh64/syntax-1.d
@@ -85,7 +85,7 @@ Disassembly of section .text:
  104:	e00107f0 	prefi	r0,32
 
 0000000000000108 <.*>:
- 108:	90 01       	mov.w	10e <.*>,r0	! 0x8101
+ 108:	90 01       	mov.w	10e <.*>,r0	! 8101
  10a:	85 01       	mov.w	@\(2,r0\),r0
  10c:	c5 01       	mov.w	@\(2,gbr\),r0
  10e:	81 01       	mov.w	r0,@\(2,r0\)
@@ -94,7 +94,7 @@ Disassembly of section .text:
  114:	89 01       	bt	11a <.*>
  116:	a0 01       	bra	11c <.*>
  118:	b0 01       	bsr	11e <.*>
- 11a:	d0 00       	mov.l	11c <.*>,r0	! 0x5001c601
+ 11a:	d0 00       	mov.l	11c <.*>,r0	! 5001c601
  11c:	50 01       	mov.l	@\(4,r0\),r0
  11e:	c6 01       	mov.l	@\(4,gbr\),r0
  120:	c7 01       	mova	128 <.*>,r0
diff --git a/gas/testsuite/gas/sh/tlsd.d b/gas/testsuite/gas/sh/tlsd.d
index b4d75974c85e..055b5a7c6ece 100644
--- a/gas/testsuite/gas/sh/tlsd.d
+++ b/gas/testsuite/gas/sh/tlsd.d
@@ -11,12 +11,12 @@ Disassembly of section .text:
    2:	2f e6 [ 	]*mov\.l	r14,@-r15
    4:	4f 22 [ 	]*sts\.l	pr,@-r15
    6:	c7 14 [ 	]*mova	58 <fn\+0x58>,r0
-   8:	dc 13 [ 	]*mov\.l	58 <fn\+0x58>,r12[ 	]+! 0x0 .*
+   8:	dc 13 [ 	]*mov\.l	58 <fn\+0x58>,r12[ 	]+! 0 .*
    a:	3c 0c [ 	]*add	r0,r12
    c:	6e f3 [ 	]*mov	r15,r14
-   e:	d4 04 [ 	]*mov\.l	20 <fn\+0x20>,r4[ 	]+! 0x0 .*
+   e:	d4 04 [ 	]*mov\.l	20 <fn\+0x20>,r4[ 	]+! 0 .*
   10:	c7 04 [ 	]*mova	24 <fn\+0x24>,r0
-  12:	d1 04 [ 	]*mov\.l	24 <fn\+0x24>,r1[ 	]+! 0x0 .*
+  12:	d1 04 [ 	]*mov\.l	24 <fn\+0x24>,r1[ 	]+! 0 .*
   14:	31 0c [ 	]*add	r0,r1
   16:	41 0b [ 	]*jsr	@r1
   18:	34 cc [ 	]*add	r12,r4
@@ -26,9 +26,9 @@ Disassembly of section .text:
 	\.\.\.
 [ 	]+20: R_SH_TLS_GD_32	foo
 [ 	]+24: R_SH_PLT32	__tls_get_addr
-  28:	d4 03 [ 	]*mov\.l	38 <fn\+0x38>,r4[ 	]+! 0x0 .*
+  28:	d4 03 [ 	]*mov\.l	38 <fn\+0x38>,r4[ 	]+! 0 .*
   2a:	c7 04 [ 	]*mova	3c <fn\+0x3c>,r0
-  2c:	d1 03 [ 	]*mov\.l	3c <fn\+0x3c>,r1[ 	]+! 0x0 .*
+  2c:	d1 03 [ 	]*mov\.l	3c <fn\+0x3c>,r1[ 	]+! 0 .*
   2e:	31 0c [ 	]*add	r0,r1
   30:	41 0b [ 	]*jsr	@r1
   32:	34 cc [ 	]*add	r12,r4
@@ -38,10 +38,10 @@ Disassembly of section .text:
 [ 	]+38: R_SH_TLS_LD_32	bar
 [ 	]+3c: R_SH_PLT32	__tls_get_addr
   40:	e2 01 [ 	]*mov	#1,r2
-  42:	d1 06 [ 	]*mov\.l	5c <fn\+0x5c>,r1[ 	]+! 0x0 .*
+  42:	d1 06 [ 	]*mov\.l	5c <fn\+0x5c>,r1[ 	]+! 0 .*
   44:	30 1c [ 	]*add	r1,r0
   46:	20 22 [ 	]*mov\.l	r2,@r0
-  48:	d1 05 [ 	]*mov\.l	60 <fn\+0x60>,r1[ 	]+! 0x0 .*
+  48:	d1 05 [ 	]*mov\.l	60 <fn\+0x60>,r1[ 	]+! 0 .*
   4a:	30 1c [ 	]*add	r1,r0
   4c:	6f e3 [ 	]*mov	r14,r15
   4e:	4f 26 [ 	]*lds\.l	@r15\+,pr
diff --git a/gas/testsuite/gas/sh/tlsnopic.d b/gas/testsuite/gas/sh/tlsnopic.d
index 69131276ccee..739f48de879c 100644
--- a/gas/testsuite/gas/sh/tlsnopic.d
+++ b/gas/testsuite/gas/sh/tlsnopic.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
    0:	2f e6 [ 	]*mov\.l	r14,@-r15
    2:	6e f3 [ 	]*mov	r15,r14
    4:	01 12 [ 	]*stc	gbr,r1
-   6:	d0 02 [ 	]*mov\.l	10 <fn\+0x10>,r0[ 	]+! 0x0 .*
+   6:	d0 02 [ 	]*mov\.l	10 <fn\+0x10>,r0[ 	]+! 0 .*
    8:	30 1c [ 	]*add	r1,r0
    a:	6f e3 [ 	]*mov	r14,r15
    c:	00 0b [ 	]*rts	
diff --git a/gas/testsuite/gas/sh/tlspic.d b/gas/testsuite/gas/sh/tlspic.d
index 207ab1a2f4b2..66043ba1839e 100644
--- a/gas/testsuite/gas/sh/tlspic.d
+++ b/gas/testsuite/gas/sh/tlspic.d
@@ -11,9 +11,9 @@ Disassembly of section .text:
    2:	2f e6 [ 	]*mov\.l	r14,@-r15
    4:	6e f3 [ 	]*mov	r15,r14
    6:	c7 08 [ 	]*mova	28 <fn\+0x28>,r0
-   8:	dc 07 [ 	]*mov\.l	28 <fn\+0x28>,r12[ 	]+! 0x0 .*
+   8:	dc 07 [ 	]*mov\.l	28 <fn\+0x28>,r12[ 	]+! 0 .*
    a:	3c 0c [ 	]*add	r0,r12
-   c:	d0 02 [ 	]*mov\.l	18 <fn\+0x18>,r0[ 	]+! 0x0 .*
+   c:	d0 02 [ 	]*mov\.l	18 <fn\+0x18>,r0[ 	]+! 0 .*
    e:	01 12 [ 	]*stc	gbr,r1
   10:	00 ce [ 	]*mov\.l	@\(r0,r12\),r0
   12:	a0 03 [ 	]*bra	1c <fn\+0x1c>
diff --git a/gas/testsuite/gas/sh/too_large.d b/gas/testsuite/gas/sh/too_large.d
new file mode 100644
index 000000000000..597e74516e01
--- /dev/null
+++ b/gas/testsuite/gas/sh/too_large.d
@@ -0,0 +1,9 @@
+#name: Check for bogus overflow errors in .byte directives
+#as: -big -relax -isa=sh4a
+#nm: -n
+
+[ 	]*U \.L318
+[ 	]*U \.L319
+[ 	]*U \.L320
+[ 	]*U \.L321
+0+00100 t \.L307
diff --git a/gas/testsuite/gas/sh/too_large.s b/gas/testsuite/gas/sh/too_large.s
new file mode 100644
index 000000000000..b67b8f716d07
--- /dev/null
+++ b/gas/testsuite/gas/sh/too_large.s
@@ -0,0 +1,39 @@
+	.file	"too_large.c"
+	.text
+	nop
+	.align 8
+.L307:
+	.byte	.L302-.L307
+	.byte	.L303-.L307
+	.byte	.L304-.L307
+	.byte	.L305-.L307
+.L304:
+	mov.l	.L318,r1	
+	jsr	@r1	
+	mov	r8,r4	
+	lds	r0,fpul	
+	fsts	fpul,fr1	
+	flds	fr1,fpul	
+	sts	fpul,r0	
+	mov	r14,r15	
+	lds.l	@r15+,pr	
+	mov.l	@r15+,r14	
+	mov.l	@r15+,r8	
+	rts	
+	nop	
+.L305:
+	mov.l	.L319,r7	
+	jsr	@r7	
+	mov	r8,r4	
+	lds	r0,fpul	
+	bra	.L307	
+	fsts	fpul,fr1	
+.L303:
+	mov.l	.L320,r6	
+	jsr	@r6	
+	mov	r8,r4	
+	lds	r0,fpul	
+	bra	.L307	
+	fsts	fpul,fr1	
+.L302:
+	mov.l	.L321,r5	
diff --git a/gas/testsuite/gas/sparc/pr4587.l b/gas/testsuite/gas/sparc/pr4587.l
new file mode 100644
index 000000000000..fd05091b1e27
--- /dev/null
+++ b/gas/testsuite/gas/sparc/pr4587.l
@@ -0,0 +1,2 @@
+.*pr4587.s: Assembler messages:
+.*pr4587.s:18: Error: Illegal operands
diff --git a/gas/testsuite/gas/sparc/pr4587.s b/gas/testsuite/gas/sparc/pr4587.s
new file mode 100644
index 000000000000..a058c1d07a38
--- /dev/null
+++ b/gas/testsuite/gas/sparc/pr4587.s
@@ -0,0 +1,22 @@
+	.section .data
+	.align 4
+zero: .single 0.0
+
+	.section .text
+	.align 4
+	.global main
+main:
+    save %sp, -96, %sp
+
+    ! Zero-out the first FP register
+    set zero, %l0
+    ld [%l0], %f0
+
+    ! Compare it to itself
+    ! The third reg (%f0) will cause a segfault in as
+    ! fcmps only takes two regs... this should be illegal operand error
+    fcmps %f0, %f0, %f0
+
+    ! Return 0
+    ret
+    restore %g0, %g0, %o0
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index a2e362dbba11..876f9acf8011 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -48,6 +48,13 @@ if [istarget sparc*-*-*] {
 	run_dump_test "pcrel64"
 	run_dump_test "plt64"
     }
+    run_dump_test "v9branch1"
+    run_dump_test "v9branch2"
+    run_dump_test "v9branch3"
+    run_dump_test "v9branch4"
+    run_dump_test "v9branch5"
+
+    run_list_test "pr4587" ""
 }
 
 if [istarget sparc-*-vxworks*] {
diff --git a/gas/testsuite/gas/sparc/v9branch1.d b/gas/testsuite/gas/sparc/v9branch1.d
new file mode 100644
index 000000000000..c2c05e4d88b4
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch1.d
@@ -0,0 +1,23 @@
+#as: -Av9
+#objdump: -dr --prefix-addresses
+#name: v9branch1
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+0x0+000000 brz  %o0, 0x0+01fffc
+0x0+000004 nop 
+	...
+0x0+01fff8 nop 
+0x0+01fffc nop 
+	...
+0x0+03fffc brz  %o0, 0x0+01fffc
+0x0+040000 nop 
+0x0+040004 bne  %icc, 0x0+140000
+0x0+040008 nop 
+	...
+0x0+13fffc nop 
+0x0+140000 nop 
+	...
+0x0+240000 bne  %icc, 0x0+140000
+0x0+240004 nop 
diff --git a/gas/testsuite/gas/sparc/v9branch1.s b/gas/testsuite/gas/sparc/v9branch1.s
new file mode 100644
index 000000000000..15c4a6aecd60
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch1.s
@@ -0,0 +1,18 @@
+   # Check if maximum possible branch distances for v9 branches are accepted
+   .text
+   brz,pt %o0, 1f
+   nop
+   .skip (128 * 1024 - 16)
+   nop
+1: nop
+   .skip (128 * 1024 - 4)
+   brz,pt %o0, 1b
+   nop
+   bne,pt %icc, 2f
+   nop
+   .skip (1024 * 1024 - 16)
+   nop
+2: nop
+   .skip (1024 * 1024 - 4)
+   bne,pt %icc, 2b
+   nop
diff --git a/gas/testsuite/gas/sparc/v9branch2.d b/gas/testsuite/gas/sparc/v9branch2.d
new file mode 100644
index 000000000000..dcad03b336f5
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch2.d
@@ -0,0 +1,3 @@
+#as: -Av9
+#name: v9branch2
+#error: :3:.*relocation.*overflow
diff --git a/gas/testsuite/gas/sparc/v9branch2.s b/gas/testsuite/gas/sparc/v9branch2.s
new file mode 100644
index 000000000000..6048a82d7b8d
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch2.s
@@ -0,0 +1,7 @@
+   # Text for relocation overflow diagnostic
+   .text
+   brz,pt %o0, 1f
+   nop
+   .skip (128 * 1024 - 12)
+   nop
+1: nop
diff --git a/gas/testsuite/gas/sparc/v9branch3.d b/gas/testsuite/gas/sparc/v9branch3.d
new file mode 100644
index 000000000000..f8105fd70399
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch3.d
@@ -0,0 +1,3 @@
+#as: -Av9
+#name: v9branch3
+#error: :5:.*relocation.*overflow
diff --git a/gas/testsuite/gas/sparc/v9branch3.s b/gas/testsuite/gas/sparc/v9branch3.s
new file mode 100644
index 000000000000..6bcfea08313b
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch3.s
@@ -0,0 +1,6 @@
+   # Text for relocation overflow diagnostic
+   .text
+1: nop
+   .skip (128 * 1024)
+   brz,pt %o0, 1b
+   nop
diff --git a/gas/testsuite/gas/sparc/v9branch4.d b/gas/testsuite/gas/sparc/v9branch4.d
new file mode 100644
index 000000000000..4379388eb576
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch4.d
@@ -0,0 +1,3 @@
+#as: -Av9
+#name: v9branch4
+#error: :3:.*relocation.*overflow
diff --git a/gas/testsuite/gas/sparc/v9branch4.s b/gas/testsuite/gas/sparc/v9branch4.s
new file mode 100644
index 000000000000..bf2306f34f01
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch4.s
@@ -0,0 +1,7 @@
+   # Text for relocation overflow diagnostic
+   .text
+   bne,pt %icc, 1f
+   nop
+   .skip (1024 * 1024 - 12)
+   nop
+1: nop
diff --git a/gas/testsuite/gas/sparc/v9branch5.d b/gas/testsuite/gas/sparc/v9branch5.d
new file mode 100644
index 000000000000..937a3eacb7ec
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch5.d
@@ -0,0 +1,3 @@
+#as: -Av9
+#name: v9branch5
+#error: :5:.*relocation.*overflow
diff --git a/gas/testsuite/gas/sparc/v9branch5.s b/gas/testsuite/gas/sparc/v9branch5.s
new file mode 100644
index 000000000000..733aa2a3ed28
--- /dev/null
+++ b/gas/testsuite/gas/sparc/v9branch5.s
@@ -0,0 +1,6 @@
+   # Text for relocation overflow diagnostic
+   .text
+1: nop
+   .skip (1024 * 1024)
+   bne,pt %icc, 1b
+   nop
diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d
index 3f176d13c3bd..9fb689b5d3c7 100644
--- a/gas/testsuite/gas/v850/v850e1.d
+++ b/gas/testsuite/gas/v850/v850e1.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
 0x0+04 e0 1f 40 23 [ 	]*bsw	sp, gp
 0x0+08 05 02  [ 	]*callt	5
 0x0+0a e8 3f e4 00 [ 	]*clr1	r7, r8
-0x0+0e f6 17 14 1b [ 	]*cmov	nz, 22, r2, sp
+0x0+0e f6 17 14 1b [ 	]*cmov	nz, -10, r2, sp
 0x0+12 e1 17 34 1b [ 	]*cmov	nz, r1, r2, sp
 0x0+16 e0 07 44 01 [ 	]*ctret	
 0x0+1a e0 07 46 01 [ 	]*dbret	
diff --git a/gas/testsuite/gas/z8k/calr.d b/gas/testsuite/gas/z8k/calr.d
index fd6f7d8293db..5ba3db904b4f 100644
--- a/gas/testsuite/gas/z8k/calr.d
+++ b/gas/testsuite/gas/z8k/calr.d
@@ -6,16 +6,16 @@
 
 Disassembly of section \.text:
 
-00000000 <label1>:
+0*00000000 <label1>:
        0:	d803           	calr	0xffc
        2:	d800           	calr	0x1004
 	\.\.\.
 
-00000ffc <label2>:
+0*00000ffc <label2>:
      ffc:	d7ff           	calr	0x0
      ffe:	8d07           	nop	
     1000:	8d07           	nop	
     1002:	8d07           	nop	
 
-00001004 <label3>:
+0*00001004 <label3>:
     1004:	8d07           	nop	
diff --git a/gas/testsuite/gas/z8k/ctrl-names.d b/gas/testsuite/gas/z8k/ctrl-names.d
index ecf004fa89bb..ae69e97749b4 100644
--- a/gas/testsuite/gas/z8k/ctrl-names.d
+++ b/gas/testsuite/gas/z8k/ctrl-names.d
@@ -1,12 +1,12 @@
 #as:
 #objdump: -d
-#name: jmp cc
+#name: control register names
 
 .*: +file format coff-z8k
 
 Disassembly of section \.text:
 
-00000000 <\.text>:
+0*00000000 <\.text>:
    0:	7d02           	ldctl	r0,fcw
    2:	7d0a           	ldctl	fcw,r0
    4:	7d03           	ldctl	r0,refresh
diff --git a/gas/testsuite/gas/z8k/djnz.d b/gas/testsuite/gas/z8k/djnz.d
index 5b6eca73cafc..053a7d03fc28 100644
--- a/gas/testsuite/gas/z8k/djnz.d
+++ b/gas/testsuite/gas/z8k/djnz.d
@@ -6,14 +6,14 @@
 
 Disassembly of section \.text:
 
-00000000 <label1>:
+0*00000000 <label1>:
    0:	8d07           	nop	
 	\.\.\.
   fa:	f0fe           	djnz	r0,0x0
   fc:	f87f           	dbjnz	rl0,0x0
   fe:	8d07           	nop	
 
-00000100 <label2>:
+0*00000100 <label2>:
  100:	8d07           	nop	
 	\.\.\.
  1fa:	f87e           	dbjnz	rl0,0x100
diff --git a/gas/testsuite/gas/z8k/inout.d b/gas/testsuite/gas/z8k/inout.d
index 0f0f772940b7..7b9696bb0290 100644
--- a/gas/testsuite/gas/z8k/inout.d
+++ b/gas/testsuite/gas/z8k/inout.d
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-00000000 <\.text>:
+0*00000000 <\.text>:
    0:	3b14 4444      	in	r1,#0x4444
    4:	3a34 0123      	inb	rh3,#0x123
    8:	3d08           	in	r8,@r0
diff --git a/gas/testsuite/gas/z8k/jmp-cc.d b/gas/testsuite/gas/z8k/jmp-cc.d
index 012e97f7b14b..11940500ed89 100644
--- a/gas/testsuite/gas/z8k/jmp-cc.d
+++ b/gas/testsuite/gas/z8k/jmp-cc.d
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-00000000 <\.text>:
+0*00000000 <\.text>:
    0:	e01f           	jr	f,0x40
    2:	e11e           	jr	lt,0x40
    4:	e21d           	jr	le,0x40
@@ -37,7 +37,7 @@ Disassembly of section \.text:
   3c:	e801           	jr	t,0x40
   3e:	e800           	jr	t,0x40
 
-00000040 <dd>:
+0*00000040 <dd>:
   40:	e8ff           	jr	t,0x40
   42:	e8fe           	jr	t,0x40
   44:	8d07           	nop	
diff --git a/gas/testsuite/gas/z8k/jr-back.d b/gas/testsuite/gas/z8k/jr-back.d
index 0b80140380f6..bc244332a543 100644
--- a/gas/testsuite/gas/z8k/jr-back.d
+++ b/gas/testsuite/gas/z8k/jr-back.d
@@ -6,7 +6,7 @@
 
 Disassembly of section \.text:
 
-00000000 <start>:
+0*00000000 <start>:
    0:	8d07           	nop	
 	\.\.\.
   fa:	e882           	jr	t,0x0
diff --git a/gas/testsuite/gas/z8k/jr-forw.d b/gas/testsuite/gas/z8k/jr-forw.d
index 6d2f4680f006..a0de55c96311 100644
--- a/gas/testsuite/gas/z8k/jr-forw.d
+++ b/gas/testsuite/gas/z8k/jr-forw.d
@@ -6,11 +6,11 @@
 
 Disassembly of section \.text:
 
-00000000 <.text>:
+0*00000000 <.text>:
    0:	e87f           	jr	t,0x100
    2:	e87e           	jr	t,0x100
    4:	e87d           	jr	t,0x100
 	\.\.\.
 
-00000100 <dest>:
+0*00000100 <dest>:
  100:	8d07           	nop	
diff --git a/gas/testsuite/gas/z8k/reglabel.d b/gas/testsuite/gas/z8k/reglabel.d
new file mode 100644
index 000000000000..a16cad502eca
--- /dev/null
+++ b/gas/testsuite/gas/z8k/reglabel.d
@@ -0,0 +1,268 @@
+#as:
+#objdump: -d
+#name: reglabel
+
+.*: +file format coff-z8k
+
+Disassembly of section \.text:
+
+0*00000000 <sp_label>:
+   0:	7600 0000      	lda	r0,0x0
+
+0*00000004 <r0_label>:
+   4:	7600 0004      	lda	r0,0x4
+
+0*00000008 <r1_label>:
+   8:	7600 0008      	lda	r0,0x8
+
+0*0000000c <r2_label>:
+   c:	7600 000c      	lda	r0,0xc
+
+0*00000010 <r3_label>:
+  10:	7600 0010      	lda	r0,0x10
+
+0*00000014 <r4_label>:
+  14:	7600 0014      	lda	r0,0x14
+
+0*00000018 <r5_label>:
+  18:	7600 0018      	lda	r0,0x18
+
+0*0000001c <r6_label>:
+  1c:	7600 001c      	lda	r0,0x1c
+
+0*00000020 <r7_label>:
+  20:	7600 0020      	lda	r0,0x20
+
+0*00000024 <r8_label>:
+  24:	7600 0024      	lda	r0,0x24
+
+0*00000028 <r9_label>:
+  28:	7600 0028      	lda	r0,0x28
+
+0*0000002c <r10_label>:
+  2c:	7600 002c      	lda	r0,0x2c
+
+0*00000030 <r11_label>:
+  30:	7600 0030      	lda	r0,0x30
+
+0*00000034 <r12_label>:
+  34:	7600 0034      	lda	r0,0x34
+
+0*00000038 <r13_label>:
+  38:	7600 0038      	lda	r0,0x38
+
+0*0000003c <r14_label>:
+  3c:	7600 003c      	lda	r0,0x3c
+
+0*00000040 <r15_label>:
+  40:	7600 0040      	lda	r0,0x40
+
+0*00000044 <r16_label>:
+  44:	7600 0044      	lda	r0,0x44
+
+0*00000048 <rr0_label>:
+  48:	7600 0048      	lda	r0,0x48
+
+0*0000004c <rr1_label>:
+  4c:	7600 004c      	lda	r0,0x4c
+
+0*00000050 <rr2_label>:
+  50:	7600 0050      	lda	r0,0x50
+
+0*00000054 <rr3_label>:
+  54:	7600 0054      	lda	r0,0x54
+
+0*00000058 <rr4_label>:
+  58:	7600 0058      	lda	r0,0x58
+
+0*0000005c <rr5_label>:
+  5c:	7600 005c      	lda	r0,0x5c
+
+0*00000060 <rr6_label>:
+  60:	7600 0060      	lda	r0,0x60
+
+0*00000064 <rr7_label>:
+  64:	7600 0064      	lda	r0,0x64
+
+0*00000068 <rr8_label>:
+  68:	7600 0068      	lda	r0,0x68
+
+0*0000006c <rr9_label>:
+  6c:	7600 006c      	lda	r0,0x6c
+
+0*00000070 <rr10_label>:
+  70:	7600 0070      	lda	r0,0x70
+
+0*00000074 <rr11_label>:
+  74:	7600 0074      	lda	r0,0x74
+
+0*00000078 <rr12_label>:
+  78:	7600 0078      	lda	r0,0x78
+
+0*0000007c <rr13_label>:
+  7c:	7600 007c      	lda	r0,0x7c
+
+0*00000080 <rr14_label>:
+  80:	7600 0080      	lda	r0,0x80
+
+0*00000084 <rr15_label>:
+  84:	7600 0084      	lda	r0,0x84
+
+0*00000088 <rr16_label>:
+  88:	7600 0088      	lda	r0,0x88
+
+0*0000008c <rq0_label>:
+  8c:	7600 008c      	lda	r0,0x8c
+
+0*00000090 <rq1_label>:
+  90:	7600 0090      	lda	r0,0x90
+
+0*00000094 <rq2_label>:
+  94:	7600 0094      	lda	r0,0x94
+
+0*00000098 <rq3_label>:
+  98:	7600 0098      	lda	r0,0x98
+
+0*0000009c <rq4_label>:
+  9c:	7600 009c      	lda	r0,0x9c
+
+0*000000a0 <rq5_label>:
+  a0:	7600 00a0      	lda	r0,0xa0
+
+0*000000a4 <rq6_label>:
+  a4:	7600 00a4      	lda	r0,0xa4
+
+0*000000a8 <rq7_label>:
+  a8:	7600 00a8      	lda	r0,0xa8
+
+0*000000ac <rq8_label>:
+  ac:	7600 00ac      	lda	r0,0xac
+
+0*000000b0 <rq9_label>:
+  b0:	7600 00b0      	lda	r0,0xb0
+
+0*000000b4 <rq10_label>:
+  b4:	7600 00b4      	lda	r0,0xb4
+
+0*000000b8 <rq11_label>:
+  b8:	7600 00b8      	lda	r0,0xb8
+
+0*000000bc <rq12_label>:
+  bc:	7600 00bc      	lda	r0,0xbc
+
+0*000000c0 <rq13_label>:
+  c0:	7600 00c0      	lda	r0,0xc0
+
+0*000000c4 <rq14_label>:
+  c4:	7600 00c4      	lda	r0,0xc4
+
+0*000000c8 <rq15_label>:
+  c8:	7600 00c8      	lda	r0,0xc8
+
+0*000000cc <rq16_label>:
+  cc:	7600 00cc      	lda	r0,0xcc
+
+0*000000d0 <rh0_label>:
+  d0:	7600 00d0      	lda	r0,0xd0
+
+0*000000d4 <rh1_label>:
+  d4:	7600 00d4      	lda	r0,0xd4
+
+0*000000d8 <rh2_label>:
+  d8:	7600 00d8      	lda	r0,0xd8
+
+0*000000dc <rh3_label>:
+  dc:	7600 00dc      	lda	r0,0xdc
+
+0*000000e0 <rh4_label>:
+  e0:	7600 00e0      	lda	r0,0xe0
+
+0*000000e4 <rh5_label>:
+  e4:	7600 00e4      	lda	r0,0xe4
+
+0*000000e8 <rh6_label>:
+  e8:	7600 00e8      	lda	r0,0xe8
+
+0*000000ec <rh7_label>:
+  ec:	7600 00ec      	lda	r0,0xec
+
+0*000000f0 <rh8_label>:
+  f0:	7600 00f0      	lda	r0,0xf0
+
+0*000000f4 <rh9_label>:
+  f4:	7600 00f4      	lda	r0,0xf4
+
+0*000000f8 <rh10_label>:
+  f8:	7600 00f8      	lda	r0,0xf8
+
+0*000000fc <rh11_label>:
+  fc:	7600 00fc      	lda	r0,0xfc
+
+0*00000100 <rh12_label>:
+ 100:	7600 0100      	lda	r0,0x100
+
+0*00000104 <rh13_label>:
+ 104:	7600 0104      	lda	r0,0x104
+
+0*00000108 <rh14_label>:
+ 108:	7600 0108      	lda	r0,0x108
+
+0*0000010c <rh15_label>:
+ 10c:	7600 010c      	lda	r0,0x10c
+
+0*00000110 <rh16_label>:
+ 110:	7600 0110      	lda	r0,0x110
+
+0*00000114 <rl0_label>:
+ 114:	7600 0114      	lda	r0,0x114
+
+0*00000118 <rl1_label>:
+ 118:	7600 0118      	lda	r0,0x118
+
+0*0000011c <rl2_label>:
+ 11c:	7600 011c      	lda	r0,0x11c
+
+0*00000120 <rl3_label>:
+ 120:	7600 0120      	lda	r0,0x120
+
+0*00000124 <rl4_label>:
+ 124:	7600 0124      	lda	r0,0x124
+
+0*00000128 <rl5_label>:
+ 128:	7600 0128      	lda	r0,0x128
+
+0*0000012c <rl6_label>:
+ 12c:	7600 012c      	lda	r0,0x12c
+
+0*00000130 <rl7_label>:
+ 130:	7600 0130      	lda	r0,0x130
+
+0*00000134 <rl8_label>:
+ 134:	7600 0134      	lda	r0,0x134
+
+0*00000138 <rl9_label>:
+ 138:	7600 0138      	lda	r0,0x138
+
+0*0000013c <rl10_label>:
+ 13c:	7600 013c      	lda	r0,0x13c
+
+0*00000140 <rl11_label>:
+ 140:	7600 0140      	lda	r0,0x140
+
+0*00000144 <rl12_label>:
+ 144:	7600 0144      	lda	r0,0x144
+
+0*00000148 <rl13_label>:
+ 148:	7600 0148      	lda	r0,0x148
+
+0*0000014c <rl14_label>:
+ 14c:	7600 014c      	lda	r0,0x14c
+
+0*00000150 <rl15_label>:
+ 150:	7600 0150      	lda	r0,0x150
+
+0*00000154 <rl16_label>:
+ 154:	7600 0154      	lda	r0,0x154
+
+0*00000158 <r00_label>:
+ 158:	7600 0158      	lda	r0,0x158
diff --git a/gas/testsuite/gas/z8k/reglabel.s b/gas/testsuite/gas/z8k/reglabel.s
new file mode 100644
index 000000000000..b722b14b9b6e
--- /dev/null
+++ b/gas/testsuite/gas/z8k/reglabel.s
@@ -0,0 +1,99 @@
+! labels starting with a valid register name
+
+.text
+
+sp_label:	lda	r0,sp_label
+
+r0_label:	lda	r0,r0_label
+r1_label:	lda	r0,r1_label
+r2_label:	lda	r0,r2_label
+r3_label:	lda	r0,r3_label
+r4_label:	lda	r0,r4_label
+r5_label:	lda	r0,r5_label
+r6_label:	lda	r0,r6_label
+r7_label:	lda	r0,r7_label
+r8_label:	lda	r0,r8_label
+r9_label:	lda	r0,r9_label
+r10_label:	lda	r0,r10_label
+r11_label:	lda	r0,r11_label
+r12_label:	lda	r0,r12_label
+r13_label:	lda	r0,r13_label
+r14_label:	lda	r0,r14_label
+r15_label:	lda	r0,r15_label
+r16_label:	lda	r0,r16_label	! not a valid register name anyway
+
+rr0_label:	lda	r0,rr0_label
+rr1_label:	lda	r0,rr1_label	! not a valid register name anyway
+rr2_label:	lda	r0,rr2_label
+rr3_label:	lda	r0,rr3_label	! not a valid register name anyway
+rr4_label:	lda	r0,rr4_label
+rr5_label:	lda	r0,rr5_label	! not a valid register name anyway
+rr6_label:	lda	r0,rr6_label
+rr7_label:	lda	r0,rr7_label	! not a valid register name anyway
+rr8_label:	lda	r0,rr8_label
+rr9_label:	lda	r0,rr9_label	! not a valid register name anyway
+rr10_label:	lda	r0,rr10_label
+rr11_label:	lda	r0,rr11_label	! not a valid register name anyway
+rr12_label:	lda	r0,rr12_label
+rr13_label:	lda	r0,rr13_label	! not a valid register name anyway
+rr14_label:	lda	r0,rr14_label
+rr15_label:	lda	r0,rr15_label	! not a valid register name anyway
+rr16_label:	lda	r0,rr16_label	! not a valid register name anyway
+
+rq0_label:	lda	r0,rq0_label
+rq1_label:	lda	r0,rq1_label	! not a valid register name anyway
+rq2_label:	lda	r0,rq2_label	! not a valid register name anyway
+rq3_label:	lda	r0,rq3_label	! not a valid register name anyway
+rq4_label:	lda	r0,rq4_label
+rq5_label:	lda	r0,rq5_label	! not a valid register name anyway
+rq6_label:	lda	r0,rq6_label	! not a valid register name anyway
+rq7_label:	lda	r0,rq7_label	! not a valid register name anyway
+rq8_label:	lda	r0,rq8_label
+rq9_label:	lda	r0,rq9_label	! not a valid register name anyway
+rq10_label:	lda	r0,rq10_label	! not a valid register name anyway
+rq11_label:	lda	r0,rq11_label	! not a valid register name anyway
+rq12_label:	lda	r0,rq12_label
+rq13_label:	lda	r0,rq13_label	! not a valid register name anyway
+rq14_label:	lda	r0,rq14_label	! not a valid register name anyway
+rq15_label:	lda	r0,rq15_label	! not a valid register name anyway
+rq16_label:	lda	r0,rq16_label	! not a valid register name anyway
+
+
+rh0_label:	lda	r0,rh0_label
+rh1_label:	lda	r0,rh1_label
+rh2_label:	lda	r0,rh2_label
+rh3_label:	lda	r0,rh3_label
+rh4_label:	lda	r0,rh4_label
+rh5_label:	lda	r0,rh5_label
+rh6_label:	lda	r0,rh6_label
+rh7_label:	lda	r0,rh7_label
+rh8_label:	lda	r0,rh8_label	! not a valid register name anyway
+rh9_label:	lda	r0,rh9_label	! not a valid register name anyway
+rh10_label:	lda	r0,rh10_label	! not a valid register name anyway
+rh11_label:	lda	r0,rh11_label	! not a valid register name anyway
+rh12_label:	lda	r0,rh12_label	! not a valid register name anyway
+rh13_label:	lda	r0,rh13_label	! not a valid register name anyway
+rh14_label:	lda	r0,rh14_label	! not a valid register name anyway
+rh15_label:	lda	r0,rh15_label	! not a valid register name anyway
+rh16_label:	lda	r0,rh16_label	! not a valid register name anyway
+
+rl0_label:	lda	r0,rl0_label
+rl1_label:	lda	r0,rl1_label
+rl2_label:	lda	r0,rl2_label
+rl3_label:	lda	r0,rl3_label
+rl4_label:	lda	r0,rl4_label
+rl5_label:	lda	r0,rl5_label
+rl6_label:	lda	r0,rl6_label
+rl7_label:	lda	r0,rl7_label
+rl8_label:	lda	r0,rl8_label	! not a valid register name anyway
+rl9_label:	lda	r0,rl9_label	! not a valid register name anyway
+rl10_label:	lda	r0,rl10_label	! not a valid register name anyway
+rl11_label:	lda	r0,rl11_label	! not a valid register name anyway
+rl12_label:	lda	r0,rl12_label	! not a valid register name anyway
+rl13_label:	lda	r0,rl13_label	! not a valid register name anyway
+rl14_label:	lda	r0,rl14_label	! not a valid register name anyway
+rl15_label:	lda	r0,rl15_label	! not a valid register name anyway
+rl16_label:	lda	r0,rl16_label	! not a valid register name anyway
+
+r00_label:	lda	r0,r00_label	! not a valid register name anyway
+
diff --git a/gas/testsuite/gas/z8k/ret-cc.d b/gas/testsuite/gas/z8k/ret-cc.d
index 86ccc1e68f95..6b8d0c317713 100644
--- a/gas/testsuite/gas/z8k/ret-cc.d
+++ b/gas/testsuite/gas/z8k/ret-cc.d
@@ -1,12 +1,12 @@
 #as:
 #objdump: -d
-#name: jmp cc
+#name: return on condition code
 
 .*: +file format coff-z8k
 
 Disassembly of section \.text:
 
-00000000 <\.text>:
+0*00000000 <\.text>:
    0:	9e00           	ret	f
    2:	9e01           	ret	lt
    4:	9e02           	ret	le
@@ -37,7 +37,7 @@ Disassembly of section \.text:
   36:	9e08           	ret	t
   38:	9e08           	ret	t
 
-0000003a <dd>:
+0*0000003a <dd>:
   3a:	e8ff           	jr	t,0x3a
   3c:	e8fe           	jr	t,0x3a
   3e:	8d07           	nop	
diff --git a/gas/testsuite/gas/z8k/z8k.exp b/gas/testsuite/gas/z8k/z8k.exp
index 60cbca5776ac..3f966328faef 100644
--- a/gas/testsuite/gas/z8k/z8k.exp
+++ b/gas/testsuite/gas/z8k/z8k.exp
@@ -45,4 +45,8 @@ if [istarget z8k-*-*] then {
 # ctrl names test
 
      run_dump_test "ctrl-names"
+
+# labels starting with register names test
+
+     run_dump_test "reglabel"
 }
diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp
index 827e22f70f07..eabd018add9e 100644
--- a/gas/testsuite/lib/gas-defs.exp
+++ b/gas/testsuite/lib/gas-defs.exp
@@ -1,5 +1,5 @@
 # Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-# 2004, 2005 Free Software Foundation, Inc.
+# 2004, 2005, 2007 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -53,12 +53,21 @@ proc all_ones { args } {
     return 1
 }
 
+# ${tool}_finish (gas_finish) will be called by runtest.exp.  But
+# gas_finish should only be used with gas_start.  We use gas_started
+# to tell gas_finish if gas_start has been called so that runtest.exp
+# can call gas_finish without closing the wrong fd.
+set gas_started 0
+
 proc gas_start { prog as_opts } {
     global AS
     global ASFLAGS
     global srcdir
     global subdir
     global spawn_id
+    global gas_started
+
+    set gas_started 1
 
     verbose -log "Starting $AS $ASFLAGS $as_opts $prog" 2
     catch {
@@ -71,9 +80,13 @@ proc gas_start { prog as_opts } {
 
 proc gas_finish { } {
     global spawn_id
+    global gas_started
 
-    catch "close"
-    catch "wait"
+    if { $gas_started == 1 } {
+	catch "close"
+	catch "wait"
+	set gas_started 0
+    }
 }
 
 proc want_no_output { testname } {
@@ -875,3 +888,25 @@ if ![string length [info proc prune_warnings]] {
 	return $text
     }
 }
+
+# run_list_test NAME OPTS (optional): TESTNAME
+#
+# Assemble the file "NAME.d" with command line options OPTS and
+# compare the assembler standard error output against thee regular
+# expressions given in the file "NAME.l".  If TESTNAME is provided,
+# it will be used as the name of the test.
+
+proc run_list_test { name opts {testname {}} } {
+    global srcdir subdir
+    if { [string length $testname] == 0 } then {
+	set testname "[file tail $subdir] $name"
+    }
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
diff --git a/gas/testsuite/lib/gas-dg.exp b/gas/testsuite/lib/gas-dg.exp
index 92f7f3136c17..801b9b4e93c1 100644
--- a/gas/testsuite/lib/gas-dg.exp
+++ b/gas/testsuite/lib/gas-dg.exp
@@ -36,7 +36,8 @@ proc gas-dg-test { prog do_what tool_flags } {
     regsub -all "//" $dir "/" dir
     regsub -all "//" $prog "/" prog
     if [string match "$dir/*" $prog] {
-	regsub "$dir" $prog "" prog
+	# We use (?q) to treat $dir as a literal.
+	regsub "(?q)$dir" $prog "" prog
     }
 
     # FIXME: This should be gas_start but it doesn't set comp_output.
diff --git a/gas/write.c b/gas/write.c
index 9186717c4f85..29ea2843857f 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -1,6 +1,6 @@
 /* write.c - emit .o file
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -27,6 +27,7 @@
 #include "obstack.h"
 #include "output-file.h"
 #include "dwarf2dbg.h"
+#include "libbfd.h"
 
 #ifndef TC_ADJUST_RELOC_COUNT
 #define TC_ADJUST_RELOC_COUNT(FIX, COUNT)
@@ -45,7 +46,6 @@
 #ifndef TC_FORCE_RELOCATION_LOCAL
 #define TC_FORCE_RELOCATION_LOCAL(FIX)		\
   (!(FIX)->fx_pcrel				\
-   || (FIX)->fx_plt				\
    || TC_FORCE_RELOCATION (FIX))
 #endif
 
@@ -97,6 +97,16 @@
 #define TC_FAKE_LABEL(NAME) (strcmp ((NAME), FAKE_LABEL_NAME) == 0)
 #endif
 
+/* Positive values of TC_FX_SIZE_SLACK allow a target to define
+   fixups that far past the end of a frag.  Having such fixups
+   is of course most most likely a bug in setting fx_size correctly.
+   A negative value disables the fixup check entirely, which is
+   appropriate for something like the Renesas / SuperH SH_COUNT
+   reloc.  */
+#ifndef TC_FX_SIZE_SLACK
+#define TC_FX_SIZE_SLACK(FIX) 0
+#endif
+
 /* Used to control final evaluation of expressions.  */
 int finalize_syms = 0;
 
@@ -107,9 +117,10 @@ symbolS *abs_section_sym;
 /* Remember the value of dot when parsing expressions.  */
 addressT dot_value;
 
-void print_fixup (fixS *);
+/* Relocs generated by ".reloc" pseudo.  */
+struct reloc_list* reloc_list;
 
-static void renumber_sections (bfd *, asection *, PTR);
+void print_fixup (fixS *);
 
 /* We generally attach relocs to frag chains.  However, after we have
    chained these all together into a segment, any relocs we add after
@@ -121,22 +132,6 @@ static int n_fixups;
 
 #define RELOC_ENUM enum bfd_reloc_code_real
 
-static fixS *fix_new_internal (fragS *, int where, int size,
-			       symbolS *add, symbolS *sub,
-			       offsetT offset, int pcrel,
-			       RELOC_ENUM r_type);
-static long fixup_segment (fixS *, segT);
-static relax_addressT relax_align (relax_addressT addr, int align);
-static fragS *chain_frchains_together_1 (segT, struct frchain *);
-static void chain_frchains_together (bfd *, segT, PTR);
-static void cvt_frag_to_fill (segT, fragS *);
-static void adjust_reloc_syms (bfd *, asection *, PTR);
-static void fix_segment (bfd *, asection *, PTR);
-static void write_relocs (bfd *, asection *, PTR);
-static void write_contents (bfd *, asection *, PTR);
-static void set_symtab (void);
-static void merge_data_into_text (void);
-
 /* Create a fixS in obstack 'notes'.  */
 
 static fixS *
@@ -153,7 +148,7 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
 
   n_fixups++;
 
-  fixP = (fixS *) obstack_alloc (&notes, sizeof (fixS));
+  fixP = obstack_alloc (&notes, sizeof (fixS));
 
   fixP->fx_frag = frag;
   fixP->fx_where = where;
@@ -169,13 +164,13 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
   fixP->fx_offset = offset;
   fixP->fx_dot_value = dot_value;
   fixP->fx_pcrel = pcrel;
-  fixP->fx_plt = 0;
   fixP->fx_r_type = r_type;
   fixP->fx_im_disp = 0;
   fixP->fx_pcrel_adjust = 0;
   fixP->fx_bit_fixP = 0;
   fixP->fx_addnumber = 0;
   fixP->fx_tcbit = 0;
+  fixP->fx_tcbit2 = 0;
   fixP->fx_done = 0;
   fixP->fx_no_overflow = 0;
   fixP->fx_signed = 0;
@@ -365,7 +360,7 @@ get_recorded_alignment (segT seg)
 /* Reset the section indices after removing the gas created sections.  */
 
 static void
-renumber_sections (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, PTR countparg)
+renumber_sections (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *countparg)
 {
   int *countp = (int *) countparg;
 
@@ -379,7 +374,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
   fragS dummy, *prev_frag = &dummy;
   fixS fix_dummy, *prev_fix = &fix_dummy;
 
-  for (; frchp && frchp->frch_seg == section; frchp = frchp->frch_next)
+  for (; frchp; frchp = frchp->frch_next)
     {
       prev_frag->fr_next = frchp->frch_root;
       prev_frag = frchp->frch_last;
@@ -394,6 +389,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
 	}
     }
   assert (prev_frag->fr_type != 0);
+  assert (prev_frag != &dummy);
   prev_frag->fr_next = 0;
   return prev_frag;
 }
@@ -401,7 +397,7 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
 static void
 chain_frchains_together (bfd *abfd ATTRIBUTE_UNUSED,
 			 segT section,
-			 PTR xxx ATTRIBUTE_UNUSED)
+			 void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *info;
 
@@ -529,10 +525,8 @@ relax_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx)
     info->changed = 1;
 }
 
-static void size_seg (bfd *, asection *, PTR);
-
 static void
-size_seg (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
+size_seg (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
 {
   flagword flags;
   fragS *fragp;
@@ -562,11 +556,7 @@ size_seg (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
   if (size > 0 && ! seginfo->bss)
     flags |= SEC_HAS_CONTENTS;
 
-  /* @@ This is just an approximation.  */
-  if (seginfo && seginfo->fix_root)
-    flags |= SEC_RELOC;
-  else
-    flags &= ~SEC_RELOC;
+  flags &= ~SEC_RELOC;
   x = bfd_set_section_flags (abfd, sec, flags);
   assert (x);
 
@@ -637,13 +627,93 @@ dump_section_relocs (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, FILE *stream)
 #define EMIT_SECTION_SYMBOLS 1
 #endif
 
+/* Resolve U.A.OFFSET_SYM and U.A.SYM fields of RELOC_LIST entries,
+   and check for validity.  Convert RELOC_LIST from using U.A fields
+   to U.B fields.  */
+static void
+resolve_reloc_expr_symbols (void)
+{
+  struct reloc_list *r;
+
+  for (r = reloc_list; r; r = r->next)
+    {
+      expressionS *symval;
+      symbolS *sym;
+      bfd_vma offset, addend;
+      asection *sec;
+      reloc_howto_type *howto;
+
+      resolve_symbol_value (r->u.a.offset_sym);
+      symval = symbol_get_value_expression (r->u.a.offset_sym);
+
+      offset = 0;
+      sym = NULL;
+      if (symval->X_op == O_constant)
+	sym = r->u.a.offset_sym;
+      else if (symval->X_op == O_symbol)
+	{
+	  sym = symval->X_add_symbol;
+	  offset = symval->X_add_number;
+	  symval = symbol_get_value_expression (symval->X_add_symbol);
+	}
+      if (sym == NULL
+	  || symval->X_op != O_constant
+	  || (sec = S_GET_SEGMENT (sym)) == NULL
+	  || !SEG_NORMAL (sec))
+	{
+	  as_bad_where (r->file, r->line, _("invalid offset expression"));
+	  sec = NULL;
+	}
+      else
+	offset += S_GET_VALUE (sym);
+
+      sym = NULL;
+      addend = r->u.a.addend;
+      if (r->u.a.sym != NULL)
+	{
+	  resolve_symbol_value (r->u.a.sym);
+	  symval = symbol_get_value_expression (r->u.a.sym);
+	  if (symval->X_op == O_constant)
+	    sym = r->u.a.sym;
+	  else if (symval->X_op == O_symbol)
+	    {
+	      sym = symval->X_add_symbol;
+	      addend += symval->X_add_number;
+	      symval = symbol_get_value_expression (symval->X_add_symbol);
+	    }
+	  if (symval->X_op != O_constant)
+	    {
+	      as_bad_where (r->file, r->line, _("invalid reloc expression"));
+	      sec = NULL;
+	    }
+	  else if (sym != NULL)
+	    symbol_mark_used_in_reloc (sym);
+	}
+      if (sym == NULL)
+	{
+	  if (abs_section_sym == NULL)
+	    abs_section_sym = section_symbol (absolute_section);
+	  sym = abs_section_sym;
+	}
+
+      howto = r->u.a.howto;
+
+      r->u.b.sec = sec;
+      r->u.b.s = symbol_get_bfdsym (sym);
+      r->u.b.r.sym_ptr_ptr = &r->u.b.s;
+      r->u.b.r.address = offset;
+      r->u.b.r.addend = addend;
+      r->u.b.r.howto = howto;
+    }
+}
+
 /* This pass over fixups decides whether symbols can be replaced with
    section symbols.  */
 
 static void
 adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 		   asection *sec,
-		   PTR xxx ATTRIBUTE_UNUSED)
+		   void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   fixS *fixp;
@@ -680,17 +750,21 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 
 	/* If this symbol is equated to an undefined or common symbol,
 	   convert the fixup to being against that symbol.  */
-	if (symbol_equated_reloc_p (sym)
-	    || S_IS_WEAKREFR (sym))
+	while (symbol_equated_reloc_p (sym)
+	       || S_IS_WEAKREFR (sym))
 	  {
+	    symbolS *newsym = symbol_get_value_expression (sym)->X_add_symbol;
+	    if (sym == newsym)
+	      break;
 	    fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	    sym = symbol_get_value_expression (sym)->X_add_symbol;
-	    fixp->fx_addsy = sym;
+	    fixp->fx_addsy = newsym;
+	    sym = newsym;
 	  }
 
 	if (symbol_mri_common_p (sym))
 	  {
-	    /* These symbols are handled specially in fixup_segment.  */
+	    fixp->fx_offset += S_GET_VALUE (sym);
+	    fixp->fx_addsy = symbol_get_value_expression (sym)->X_add_symbol;
 	    continue;
 	  }
 
@@ -719,14 +793,14 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 	if (bfd_is_abs_section (symsec))
 	  {
 	    /* The fixup_segment routine normally will not use this
-               symbol in a relocation.  */
+	       symbol in a relocation.  */
 	    continue;
 	  }
 
 	/* Don't try to reduce relocs which refer to non-local symbols
-           in .linkonce sections.  It can lead to confusion when a
-           debugging section refers to a .linkonce section.  I hope
-           this will always be correct.  */
+	   in .linkonce sections.  It can lead to confusion when a
+	   debugging section refers to a .linkonce section.  I hope
+	   this will always be correct.  */
 	if (symsec != sec && ! S_IS_LOCAL (sym))
 	  {
 	    if ((symsec->flags & SEC_LINK_ONCE) != 0
@@ -763,10 +837,241 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
   dump_section_relocs (abfd, sec, stderr);
 }
 
+/* fixup_segment()
+
+   Go through all the fixS's in a segment and see which ones can be
+   handled now.  (These consist of fixS where we have since discovered
+   the value of a symbol, or the address of the frag involved.)
+   For each one, call md_apply_fix to put the fix into the frag data.
+
+   Result is a count of how many relocation structs will be needed to
+   handle the remaining fixS's that we couldn't completely handle here.
+   These will be output later by emit_relocations().  */
+
+static long
+fixup_segment (fixS *fixP, segT this_segment)
+{
+  long seg_reloc_count = 0;
+  valueT add_number;
+  fragS *fragP;
+  segT add_symbol_segment = absolute_section;
+
+  if (fixP != NULL && abs_section_sym == NULL)
+    abs_section_sym = section_symbol (absolute_section);
+
+  /* If the linker is doing the relaxing, we must not do any fixups.
+
+     Well, strictly speaking that's not true -- we could do any that
+     are PC-relative and don't cross regions that could change size.
+     And for the i960 we might be able to turn callx/callj into bal
+     anyways in cases where we know the maximum displacement.  */
+  if (linkrelax && TC_LINKRELAX_FIXUP (this_segment))
+    {
+      for (; fixP; fixP = fixP->fx_next)
+	if (!fixP->fx_done)
+	  {
+	    if (fixP->fx_addsy == NULL)
+	      {
+		/* There was no symbol required by this relocation.
+		   However, BFD doesn't really handle relocations
+		   without symbols well. So fake up a local symbol in
+		   the absolute section.  */
+		fixP->fx_addsy = abs_section_sym;
+	      }
+	    symbol_mark_used_in_reloc (fixP->fx_addsy);
+	    if (fixP->fx_subsy != NULL)
+	      symbol_mark_used_in_reloc (fixP->fx_subsy);
+	    seg_reloc_count++;
+	  }
+      TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
+      return seg_reloc_count;
+    }
+
+  for (; fixP; fixP = fixP->fx_next)
+    {
+#ifdef DEBUG5
+      fprintf (stderr, "\nprocessing fixup:\n");
+      print_fixup (fixP);
+#endif
+
+      fragP = fixP->fx_frag;
+      know (fragP);
+#ifdef TC_VALIDATE_FIX
+      TC_VALIDATE_FIX (fixP, this_segment, skip);
+#endif
+      add_number = fixP->fx_offset;
+
+      if (fixP->fx_addsy != NULL)
+	add_symbol_segment = S_GET_SEGMENT (fixP->fx_addsy);
+
+      if (fixP->fx_subsy != NULL)
+	{
+	  segT sub_symbol_segment;
+	  resolve_symbol_value (fixP->fx_subsy);
+	  sub_symbol_segment = S_GET_SEGMENT (fixP->fx_subsy);
+	  if (fixP->fx_addsy != NULL
+	      && sub_symbol_segment == add_symbol_segment
+	      && !TC_FORCE_RELOCATION_SUB_SAME (fixP, add_symbol_segment))
+	    {
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_addsy = NULL;
+	      fixP->fx_subsy = NULL;
+#ifdef TC_M68K
+	      /* See the comment below about 68k weirdness.  */
+	      fixP->fx_pcrel = 0;
+#endif
+	    }
+	  else if (sub_symbol_segment == absolute_section
+		   && !TC_FORCE_RELOCATION_SUB_ABS (fixP))
+	    {
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_subsy = NULL;
+	    }
+	  else if (sub_symbol_segment == this_segment
+		   && !TC_FORCE_RELOCATION_SUB_LOCAL (fixP))
+	    {
+	      add_number -= S_GET_VALUE (fixP->fx_subsy);
+	      fixP->fx_offset = (add_number + fixP->fx_dot_value
+				 + fixP->fx_frag->fr_address);
+
+	      /* Make it pc-relative.  If the back-end code has not
+		 selected a pc-relative reloc, cancel the adjustment
+		 we do later on all pc-relative relocs.  */
+	      if (0
+#ifdef TC_M68K
+		  /* Do this for m68k even if it's already described
+		     as pc-relative.  On the m68k, an operand of
+		     "pc@(foo-.-2)" should address "foo" in a
+		     pc-relative mode.  */
+		  || 1
+#endif
+		  || !fixP->fx_pcrel)
+		add_number += MD_PCREL_FROM_SECTION (fixP, this_segment);
+	      fixP->fx_subsy = NULL;
+	      fixP->fx_pcrel = 1;
+	    }
+	  else if (!TC_VALIDATE_FIX_SUB (fixP))
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+			    fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+			    segment_name (add_symbol_segment),
+			    S_GET_NAME (fixP->fx_subsy),
+			    segment_name (sub_symbol_segment));
+	    }
+	}
+
+      if (fixP->fx_addsy)
+	{
+	  if (add_symbol_segment == this_segment
+	      && !TC_FORCE_RELOCATION_LOCAL (fixP))
+	    {
+	      /* This fixup was made when the symbol's segment was
+		 SEG_UNKNOWN, but it is now in the local segment.
+		 So we know how to do the address without relocation.  */
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      fixP->fx_offset = add_number;
+	      if (fixP->fx_pcrel)
+		add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
+	      fixP->fx_addsy = NULL;
+	      fixP->fx_pcrel = 0;
+	    }
+	  else if (add_symbol_segment == absolute_section
+		   && !TC_FORCE_RELOCATION_ABS (fixP))
+	    {
+	      add_number += S_GET_VALUE (fixP->fx_addsy);
+	      fixP->fx_offset = add_number;
+	      fixP->fx_addsy = NULL;
+	    }
+	  else if (add_symbol_segment != undefined_section
+		   && ! bfd_is_com_section (add_symbol_segment)
+		   && MD_APPLY_SYM_VALUE (fixP))
+	    add_number += S_GET_VALUE (fixP->fx_addsy);
+	}
+
+      if (fixP->fx_pcrel)
+	{
+	  add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
+	  if (!fixP->fx_done && fixP->fx_addsy == NULL)
+	    {
+	      /* There was no symbol required by this relocation.
+		 However, BFD doesn't really handle relocations
+		 without symbols well. So fake up a local symbol in
+		 the absolute section.  */
+	      fixP->fx_addsy = abs_section_sym;
+	    }
+	}
+
+      if (!fixP->fx_done)
+	md_apply_fix (fixP, &add_number, this_segment);
+
+      if (!fixP->fx_done)
+	{
+	  ++seg_reloc_count;
+	  if (fixP->fx_addsy == NULL)
+	    fixP->fx_addsy = abs_section_sym;
+	  symbol_mark_used_in_reloc (fixP->fx_addsy);
+	  if (fixP->fx_subsy != NULL)
+	    symbol_mark_used_in_reloc (fixP->fx_subsy);
+	}
+
+      if (!fixP->fx_bit_fixP && !fixP->fx_no_overflow && fixP->fx_size != 0)
+	{
+	  if (fixP->fx_size < sizeof (valueT))
+	    {
+	      valueT mask;
+
+	      mask = 0;
+	      mask--;		/* Set all bits to one.  */
+	      mask <<= fixP->fx_size * 8 - (fixP->fx_signed ? 1 : 0);
+	      if ((add_number & mask) != 0 && (add_number & mask) != mask)
+		{
+		  char buf[50], buf2[50];
+		  sprint_value (buf, fragP->fr_address + fixP->fx_where);
+		  if (add_number > 1000)
+		    sprint_value (buf2, add_number);
+		  else
+		    sprintf (buf2, "%ld", (long) add_number);
+		  as_bad_where (fixP->fx_file, fixP->fx_line,
+				_("value of %s too large for field of %d bytes at %s"),
+				buf2, fixP->fx_size, buf);
+		} /* Generic error checking.  */
+	    }
+#ifdef WARN_SIGNED_OVERFLOW_WORD
+	  /* Warn if a .word value is too large when treated as a signed
+	     number.  We already know it is not too negative.  This is to
+	     catch over-large switches generated by gcc on the 68k.  */
+	  if (!flag_signed_overflow_ok
+	      && fixP->fx_size == 2
+	      && add_number > 0x7fff)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("signed .word overflow; switch may be too large; %ld at 0x%lx"),
+			  (long) add_number,
+			  (long) (fragP->fr_address + fixP->fx_where));
+#endif
+	}			/* Not a bit fix.  */
+
+#ifdef TC_VALIDATE_FIX
+    skip:  ATTRIBUTE_UNUSED_LABEL
+      ;
+#endif
+#ifdef DEBUG5
+      fprintf (stderr, "result:\n");
+      print_fixup (fixP);
+#endif
+    }				/* For each fixS in this segment.  */
+
+  TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
+  return seg_reloc_count;
+}
+
 static void
 fix_segment (bfd *abfd ATTRIBUTE_UNUSED,
 	     asection *sec,
-	     PTR xxx ATTRIBUTE_UNUSED)
+	     void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
 
@@ -774,14 +1079,40 @@ fix_segment (bfd *abfd ATTRIBUTE_UNUSED,
 }
 
 static void
-write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
+install_reloc (asection *sec, arelent *reloc, fragS *fragp,
+	       char *file, unsigned int line)
+{
+  char *err;
+  bfd_reloc_status_type s;
+
+  s = bfd_install_relocation (stdoutput, reloc,
+			      fragp->fr_literal, fragp->fr_address,
+			      sec, &err);
+  switch (s)
+    {
+    case bfd_reloc_ok:
+      break;
+    case bfd_reloc_overflow:
+      as_bad_where (file, line, _("relocation overflow"));
+      break;
+    case bfd_reloc_outofrange:
+      as_bad_where (file, line, _("relocation out of range"));
+      break;
+    default:
+      as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
+		file, line, s);
+    }
+}
+
+static void
+write_relocs (bfd *abfd, asection *sec, void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   unsigned int i;
   unsigned int n;
+  struct reloc_list *my_reloc_list, **rp, *r;
   arelent **relocs;
   fixS *fixp;
-  char *err;
 
   /* If seginfo is NULL, we did not create this section; don't do
      anything with it.  */
@@ -790,153 +1121,73 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 
   n = 0;
   for (fixp = seginfo->fix_root; fixp; fixp = fixp->fx_next)
-    n++;
+    if (!fixp->fx_done)
+      n++;
 
-#ifndef RELOC_EXPANSION_POSSIBLE
-  /* Set up reloc information as well.  */
-  relocs = (arelent **) xcalloc (n, sizeof (arelent *));
+#ifdef RELOC_EXPANSION_POSSIBLE
+  n *= MAX_RELOC_EXPANSION;
+#endif
 
-  i = 0;
-  for (fixp = seginfo->fix_root; fixp != (fixS *) NULL; fixp = fixp->fx_next)
+  /* Extract relocs for this section from reloc_list.  */
+  rp = &reloc_list;
+  my_reloc_list = NULL;
+  while ((r = *rp) != NULL)
     {
-      arelent *reloc;
-      bfd_reloc_status_type s;
-      symbolS *sym;
-
-      if (fixp->fx_done)
-	{
-	  n--;
-	  continue;
-	}
-
-      /* If this is an undefined symbol which was equated to another
-         symbol, then generate the reloc against the latter symbol
-         rather than the former.  */
-      sym = fixp->fx_addsy;
-      while (symbol_equated_reloc_p (sym))
-	{
-	  symbolS *n;
-
-	  /* We must avoid looping, as that can occur with a badly
-	     written program.  */
-	  n = symbol_get_value_expression (sym)->X_add_symbol;
-	  if (n == sym)
-	    break;
-	  fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	  sym = n;
-	}
-      fixp->fx_addsy = sym;
-
-      reloc = tc_gen_reloc (sec, fixp);
-      if (!reloc)
+      if (r->u.b.sec == sec)
 	{
-	  n--;
-	  continue;
+	  *rp = r->next;
+	  r->next = my_reloc_list;
+	  my_reloc_list = r;
+	  n++;
 	}
-
-      /*
-	This test is triggered inappropriately for the SH:
-         if (fixp->fx_where + fixp->fx_size
-	     > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
-	     abort ();
-      */
-
-      s = bfd_install_relocation (stdoutput, reloc,
-				  fixp->fx_frag->fr_literal,
-				  fixp->fx_frag->fr_address,
-				  sec, &err);
-      switch (s)
-	{
-	case bfd_reloc_ok:
-	  break;
-	case bfd_reloc_overflow:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("relocation overflow"));
-	  break;
-	case bfd_reloc_outofrange:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("relocation out of range"));
-	  break;
-	default:
-	  as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
-		    fixp->fx_file, fixp->fx_line, s);
-	}
-      relocs[i++] = reloc;
+      else
+	rp = &r->next;
     }
-#else
-  n = n * MAX_RELOC_EXPANSION;
-  /* Set up reloc information as well.  */
-  relocs = (arelent **) xcalloc (n, sizeof (arelent *));
+
+  relocs = xcalloc (n, sizeof (arelent *));
 
   i = 0;
   for (fixp = seginfo->fix_root; fixp != (fixS *) NULL; fixp = fixp->fx_next)
     {
-      arelent **reloc;
-      bfd_reloc_status_type s;
-      symbolS *sym;
       int j;
+      int fx_size, slack;
+      offsetT loc;
 
       if (fixp->fx_done)
-	{
-	  n--;
-	  continue;
-	}
+	continue;
+
+      fx_size = fixp->fx_size;
+      slack = TC_FX_SIZE_SLACK (fixp);
+      if (slack > 0)
+	fx_size = fx_size > slack ? fx_size - slack : 0;
+      loc = fixp->fx_where + fx_size;
+      if (slack >= 0 && loc > fixp->fx_frag->fr_fix)
+	as_bad_where (fixp->fx_file, fixp->fx_line,
+		      _("internal error: fixup not contained within frag"));
 
-      /* If this is an undefined symbol which was equated to another
-         symbol, then generate the reloc against the latter symbol
-         rather than the former.  */
-      sym = fixp->fx_addsy;
-      while (symbol_equated_reloc_p (sym))
-	{
-	  symbolS *n;
-
-	  /* We must avoid looping, as that can occur with a badly
-	     written program.  */
-	  n = symbol_get_value_expression (sym)->X_add_symbol;
-	  if (n == sym)
-	    break;
-	  fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
-	  sym = n;
-	}
-      fixp->fx_addsy = sym;
+#ifndef RELOC_EXPANSION_POSSIBLE
+      {
+	arelent *reloc = tc_gen_reloc (sec, fixp);
 
-      reloc = tc_gen_reloc (sec, fixp);
+	if (!reloc)
+	  continue;
+	relocs[i++] = reloc;
+	j = 1;
+      }
+#else
+      {
+	arelent **reloc = tc_gen_reloc (sec, fixp);
 
-      for (j = 0; reloc[j]; j++)
-	{
+	for (j = 0; reloc[j]; j++)
 	  relocs[i++] = reloc[j];
-	  assert (i <= n);
-	}
-      if (fixp->fx_where + fixp->fx_size
-	  > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
-	as_bad_where (fixp->fx_file, fixp->fx_line,
-		      _("internal error: fixup not contained within frag"));
-      for (j = 0; reloc[j]; j++)
-	{
-	  s = bfd_install_relocation (stdoutput, reloc[j],
-				      fixp->fx_frag->fr_literal,
-				      fixp->fx_frag->fr_address,
-				      sec, &err);
-	  switch (s)
-	    {
-	    case bfd_reloc_ok:
-	      break;
-	    case bfd_reloc_overflow:
-	      as_bad_where (fixp->fx_file, fixp->fx_line,
-			    _("relocation overflow"));
-	      break;
-	    case bfd_reloc_outofrange:
-	      as_bad_where (fixp->fx_file, fixp->fx_line,
-			    _("relocation out of range"));
-	      break;
-	    default:
-	      as_fatal (_("%s:%u: bad return from bfd_install_relocation: %x"),
-			fixp->fx_file, fixp->fx_line, s);
-	    }
-	}
+      }
+#endif
+
+      for ( ; j != 0; --j)
+	install_reloc (sec, relocs[i - j], fixp->fx_frag,
+		       fixp->fx_file, fixp->fx_line);
     }
   n = i;
-#endif
 
 #ifdef DEBUG4
   {
@@ -956,12 +1207,30 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
   }
 #endif
 
+  for (r = my_reloc_list; r != NULL; r = r->next)
+    {
+      fragS *f;
+      for (f = seginfo->frchainP->frch_root; f; f = f->fr_next)
+	if (f->fr_address <= r->u.b.r.address
+	    && r->u.b.r.address < f->fr_address + f->fr_fix)
+	  break;
+      if (f == NULL)
+	as_bad_where (r->file, r->line,
+		      _("reloc not within (fixed part of) section"));
+      else
+	{
+	  relocs[n++] = &r->u.b.r;
+	  install_reloc (sec, &r->u.b.r, f, r->file, r->line);
+	}
+    }
+
   if (n)
-    bfd_set_reloc (stdoutput, sec, relocs, n);
-  else
-    bfd_set_section_flags (abfd, sec,
-			   (bfd_get_section_flags (abfd, sec)
-			    & (flagword) ~SEC_RELOC));
+    {
+      flagword flags = bfd_get_section_flags (abfd, sec);
+      flags |= SEC_RELOC;
+      bfd_set_section_flags (abfd, sec, flags);
+      bfd_set_reloc (stdoutput, sec, relocs, n);
+    }
 
 #ifdef SET_SECTION_RELOCS
   SET_SECTION_RELOCS (sec, relocs, n);
@@ -987,7 +1256,7 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 static void
 write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 		asection *sec,
-		PTR xxx ATTRIBUTE_UNUSED)
+		void *xxx ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   addressT offset = 0;
@@ -1014,11 +1283,8 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 					f->fr_literal, (file_ptr) offset,
 					(bfd_size_type) f->fr_fix);
 	  if (!x)
-	    {
-	      bfd_perror (stdoutput->filename);
-	      as_perror (_("FATAL: Can't write %s"), stdoutput->filename);
-	      exit (EXIT_FAILURE);
-	    }
+	    as_fatal (_("can't write %s: %s"), stdoutput->filename,
+		      bfd_errmsg (bfd_get_error ()));
 	  offset += f->fr_fix;
 	}
       fill_literal = f->fr_literal + f->fr_fix;
@@ -1038,12 +1304,8 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 						(file_ptr) offset,
 						(bfd_size_type) fill_size);
 		  if (!x)
-		    {
-		      bfd_perror (stdoutput->filename);
-		      as_perror (_("FATAL: Can't write %s"),
-				 stdoutput->filename);
-		      exit (EXIT_FAILURE);
-		    }
+		    as_fatal (_("can't write %s: %s"), stdoutput->filename,
+			      bfd_errmsg (bfd_get_error ()));
 		  offset += fill_size;
 		}
 	    }
@@ -1097,7 +1359,6 @@ set_symtab (void)
   asymbol **asympp;
   symbolS *symp;
   bfd_boolean result;
-  extern PTR bfd_alloc (bfd *, bfd_size_type);
 
   /* Count symbols.  We can't rely on a count made by the loop in
      write_object_file, because *_frob_file may add a new symbol or
@@ -1111,7 +1372,7 @@ set_symtab (void)
       int i;
       bfd_size_type amt = (bfd_size_type) nsyms * sizeof (asymbol *);
 
-      asympp = (asymbol **) bfd_alloc (stdoutput, amt);
+      asympp = bfd_alloc (stdoutput, amt);
       symp = symbol_rootP;
       for (i = 0; i < nsyms; i++, symp = symbol_next (symp))
 	{
@@ -1138,8 +1399,7 @@ set_symtab (void)
    of the section.  This allows proper nop-filling at the end of
    code-bearing sections.  */
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)					\
-  (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
-   ? get_recorded_alignment (SEG) : 0)
+  (!(FRCHAIN)->frch_next ? get_recorded_alignment (SEG) : 0)
 #else
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 #endif
@@ -1149,48 +1409,58 @@ void
 subsegs_finish (void)
 {
   struct frchain *frchainP;
+  asection *s;
 
-  for (frchainP = frchain_root; frchainP; frchainP = frchainP->frch_next)
+  for (s = stdoutput->sections; s; s = s->next)
     {
-      int alignment = 0;
-
-      subseg_set (frchainP->frch_seg, frchainP->frch_subseg);
+      segment_info_type *seginfo = seg_info (s);
+      if (!seginfo)
+	continue;
 
-      /* This now gets called even if we had errors.  In that case,
-         any alignment is meaningless, and, moreover, will look weird
-         if we are generating a listing.  */
-      if (!had_errors ())
+      for (frchainP = seginfo->frchainP;
+	   frchainP != NULL;
+	   frchainP = frchainP->frch_next)
 	{
-	  alignment = SUB_SEGMENT_ALIGN (now_seg, frchainP);
-	  if ((bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE)
-	      && now_seg->entsize)
-	    {
-	      unsigned int entsize = now_seg->entsize;
-	      int entalign = 0;
+	  int alignment = 0;
+
+	  subseg_set (s, frchainP->frch_subseg);
 
-	      while ((entsize & 1) == 0)
+	  /* This now gets called even if we had errors.  In that case,
+	     any alignment is meaningless, and, moreover, will look weird
+	     if we are generating a listing.  */
+	  if (!had_errors ())
+	    {
+	      alignment = SUB_SEGMENT_ALIGN (now_seg, frchainP);
+	      if ((bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE)
+		  && now_seg->entsize)
 		{
-		  ++entalign;
-		  entsize >>= 1;
+		  unsigned int entsize = now_seg->entsize;
+		  int entalign = 0;
+
+		  while ((entsize & 1) == 0)
+		    {
+		      ++entalign;
+		      entsize >>= 1;
+		    }
+		  if (entalign > alignment)
+		    alignment = entalign;
 		}
-	      if (entalign > alignment)
-		alignment = entalign;
 	    }
-	}
 
-      if (subseg_text_p (now_seg))
-	frag_align_code (alignment, 0);
-      else
-	frag_align (alignment, 0, 0);
+	  if (subseg_text_p (now_seg))
+	    frag_align_code (alignment, 0);
+	  else
+	    frag_align (alignment, 0, 0);
 
-      /* frag_align will have left a new frag.
-	 Use this last frag for an empty ".fill".
+	  /* frag_align will have left a new frag.
+	     Use this last frag for an empty ".fill".
 
-	 For this segment ...
-	 Create a last frag. Do not leave a "being filled in frag".  */
-      frag_wane (frag_now);
-      frag_now->fr_fix = 0;
-      know (frag_now->fr_next == NULL);
+	     For this segment ...
+	     Create a last frag. Do not leave a "being filled in frag".  */
+	  frag_wane (frag_now);
+	  frag_now->fr_fix = 0;
+	  know (frag_now->fr_next == NULL);
+	}
     }
 }
 
@@ -1411,6 +1681,7 @@ write_object_file (void)
 	resolve_symbol_value (symp);
     }
   resolve_local_symbol_values ();
+  resolve_reloc_expr_symbols ();
 
   PROGRESS (1);
 
@@ -1478,7 +1749,7 @@ write_object_file (void)
 	  resolve_symbol_value (symp);
 
 	  /* Skip symbols which were equated to undefined or common
-             symbols.  */
+	     symbols.  */
 	  if (symbol_equated_reloc_p (symp)
 	      || S_IS_WEAKREFR (symp))
 	    {
@@ -1807,23 +2078,48 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
   /* Do relax().  */
   {
     unsigned long max_iterations;
-    offsetT stretch;	/* May be any size, 0 or negative.  */
-    /* Cumulative number of addresses we have relaxed this pass.
-       We may have relaxed more than one address.  */
-    int stretched;	/* Have we stretched on this pass?  */
-    /* This is 'cuz stretch may be zero, when, in fact some piece of code
-       grew, and another shrank.  If a branch instruction doesn't fit anymore,
-       we could be scrod.  */
+
+    /* Cumulative address adjustment.  */
+    offsetT stretch;
+
+    /* Have we made any adjustment this pass?  We can't just test
+       stretch because one piece of code may have grown and another
+       shrank.  */
+    int stretched;
+
+    /* Most horrible, but gcc may give us some exception data that
+       is impossible to assemble, of the form
+
+       .align 4
+       .byte 0, 0
+       .uleb128 end - start
+       start:
+       .space 128*128 - 1
+       .align 4
+       end:
+
+       If the leb128 is two bytes in size, then end-start is 128*128,
+       which requires a three byte leb128.  If the leb128 is three
+       bytes in size, then end-start is 128*128-1, which requires a
+       two byte leb128.  We work around this dilemma by inserting
+       an extra 4 bytes of alignment just after the .align.  This
+       works because the data after the align is accessed relative to
+       the end label.
+
+       This counter is used in a tiny state machine to detect
+       whether a leb128 followed by an align is impossible to
+       relax.  */
+    int rs_leb128_fudge = 0;
 
     /* We want to prevent going into an infinite loop where one frag grows
        depending upon the location of a symbol which is in turn moved by
        the growing frag.  eg:
 
-         foo = .
-         .org foo+16
-         foo = .
+	 foo = .
+	 .org foo+16
+	 foo = .
 
-	So we dictate that this algorithm can be at most O2.  */
+       So we dictate that this algorithm can be at most O2.  */
     max_iterations = frag_count * frag_count;
     /* Check for overflow.  */
     if (max_iterations < frag_count)
@@ -1936,6 +2232,49 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 		    }
 
 		  growth = newoff - oldoff;
+
+		  /* If this align happens to follow a leb128 and
+		     we have determined that the leb128 is bouncing
+		     in size, then break the cycle by inserting an
+		     extra alignment.  */
+		  if (growth < 0
+		      && (rs_leb128_fudge & 16) != 0
+		      && (rs_leb128_fudge & 15) >= 2)
+		    {
+		      segment_info_type *seginfo = seg_info (segment);
+		      struct obstack *ob = &seginfo->frchainP->frch_obstack;
+		      struct frag *newf;
+
+		      newf = frag_alloc (ob);
+		      obstack_blank_fast (ob, fragP->fr_var);
+		      obstack_finish (ob);
+		      memcpy (newf, fragP, SIZEOF_STRUCT_FRAG);
+		      memcpy (newf->fr_literal,
+			      fragP->fr_literal + fragP->fr_fix,
+			      fragP->fr_var);
+		      newf->fr_type = rs_fill;
+		      newf->fr_fix = 0;
+		      newf->fr_offset = (((offsetT) 1 << fragP->fr_offset)
+					 / fragP->fr_var);
+		      if (newf->fr_offset * newf->fr_var
+			  != (offsetT) 1 << fragP->fr_offset)
+			{
+			  newf->fr_offset = (offsetT) 1 << fragP->fr_offset;
+			  newf->fr_var = 1;
+			}
+		      /* Include growth of new frag, because rs_fill
+			 frags don't normally grow.  */
+		      growth += newf->fr_offset * newf->fr_var;
+		      /* The new frag address is newoff.  Adjust this
+			 for the amount we'll add when we process the
+			 new frag.  */
+		      newf->fr_address = newoff - stretch - growth;
+		      newf->relax_marker ^= 1;
+		      fragP->fr_next = newf;
+#ifdef DEBUG
+		      as_warn (_("padding added"));
+#endif
+		    }
 		}
 		break;
 
@@ -1946,11 +2285,11 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 
 		  if (symbolP)
 		    {
-                      /* Convert from an actual address to an octet offset
-                         into the section.  Here it is assumed that the
-                         section's VMA is zero, and can omit subtracting it
-                         from the symbol's value to get the address offset.  */
-                      know (S_GET_SEGMENT (symbolP)->vma == 0);
+		      /* Convert from an actual address to an octet offset
+			 into the section.  Here it is assumed that the
+			 section's VMA is zero, and can omit subtracting it
+			 from the symbol's value to get the address offset.  */
+		      know (S_GET_SEGMENT (symbolP)->vma == 0);
 		      target += S_GET_VALUE (symbolP) * OCTETS_PER_BYTE;
 		    }
 
@@ -1986,7 +2325,7 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 				    _("attempt to move .org backwards"));
 
 		      /* We've issued an error message.  Change the
-                         frag to avoid cascading errors.  */
+			 frag to avoid cascading errors.  */
 		      fragP->fr_type = rs_align;
 		      fragP->fr_subtype = 0;
 		      fragP->fr_offset = 0;
@@ -2075,8 +2414,23 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 	      {
 		stretch += growth;
 		stretched = 1;
+		if (fragP->fr_type == rs_leb128)
+		  rs_leb128_fudge += 16;
+		else if (fragP->fr_type == rs_align
+			 && (rs_leb128_fudge & 16) != 0
+			 && stretch == 0)
+		  rs_leb128_fudge += 16;
+		else
+		  rs_leb128_fudge = 0;
 	      }
 	  }
+
+	if (stretch == 0
+	    && (rs_leb128_fudge & 16) == 0
+	    && (rs_leb128_fudge & -16) != 0)
+	  rs_leb128_fudge += 1;
+	else
+	  rs_leb128_fudge = 0;
       }
     /* Until nothing further to relax.  */
     while (stretched && -- max_iterations);
@@ -2095,246 +2449,6 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
   return ret;
 }
 
-/* fixup_segment()
-
-   Go through all the fixS's in a segment and see which ones can be
-   handled now.  (These consist of fixS where we have since discovered
-   the value of a symbol, or the address of the frag involved.)
-   For each one, call md_apply_fix to put the fix into the frag data.
-
-   Result is a count of how many relocation structs will be needed to
-   handle the remaining fixS's that we couldn't completely handle here.
-   These will be output later by emit_relocations().  */
-
-static long
-fixup_segment (fixS *fixP, segT this_segment)
-{
-  long seg_reloc_count = 0;
-  valueT add_number;
-  fragS *fragP;
-  segT add_symbol_segment = absolute_section;
-
-  if (fixP != NULL && abs_section_sym == NULL)
-    abs_section_sym = section_symbol (absolute_section);
-
-  /* If the linker is doing the relaxing, we must not do any fixups.
-
-     Well, strictly speaking that's not true -- we could do any that
-     are PC-relative and don't cross regions that could change size.
-     And for the i960 we might be able to turn callx/callj into bal
-     anyways in cases where we know the maximum displacement.  */
-  if (linkrelax && TC_LINKRELAX_FIXUP (this_segment))
-    {
-      for (; fixP; fixP = fixP->fx_next)
-	if (!fixP->fx_done)
-	  {
-	    if (fixP->fx_addsy == NULL)
-	      {
-		/* There was no symbol required by this relocation.
-		   However, BFD doesn't really handle relocations
-		   without symbols well. So fake up a local symbol in
-		   the absolute section.  */
-		fixP->fx_addsy = abs_section_sym;
-	      }
-	    symbol_mark_used_in_reloc (fixP->fx_addsy);
-	    if (fixP->fx_subsy != NULL)
-	      symbol_mark_used_in_reloc (fixP->fx_subsy);
-	    seg_reloc_count++;
-	  }
-      TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
-      return seg_reloc_count;
-    }
-
-  for (; fixP; fixP = fixP->fx_next)
-    {
-#ifdef DEBUG5
-      fprintf (stderr, "\nprocessing fixup:\n");
-      print_fixup (fixP);
-#endif
-
-      fragP = fixP->fx_frag;
-      know (fragP);
-#ifdef TC_VALIDATE_FIX
-      TC_VALIDATE_FIX (fixP, this_segment, skip);
-#endif
-      add_number = fixP->fx_offset;
-
-      if (fixP->fx_addsy != NULL
-	  && symbol_mri_common_p (fixP->fx_addsy))
-	{
-	  add_number += S_GET_VALUE (fixP->fx_addsy);
-	  fixP->fx_offset = add_number;
-	  fixP->fx_addsy
-	    = symbol_get_value_expression (fixP->fx_addsy)->X_add_symbol;
-	}
-
-      if (fixP->fx_addsy != NULL)
-	add_symbol_segment = S_GET_SEGMENT (fixP->fx_addsy);
-
-      if (fixP->fx_subsy != NULL)
-	{
-	  segT sub_symbol_segment;
-	  resolve_symbol_value (fixP->fx_subsy);
-	  sub_symbol_segment = S_GET_SEGMENT (fixP->fx_subsy);
-	  if (fixP->fx_addsy != NULL
-	      && sub_symbol_segment == add_symbol_segment
-	      && !TC_FORCE_RELOCATION_SUB_SAME (fixP, add_symbol_segment))
-	    {
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_addsy = NULL;
-	      fixP->fx_subsy = NULL;
-#ifdef TC_M68K
-	      /* See the comment below about 68k weirdness.  */
-	      fixP->fx_pcrel = 0;
-#endif
-	    }
-	  else if (sub_symbol_segment == absolute_section
-		   && !TC_FORCE_RELOCATION_SUB_ABS (fixP))
-	    {
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_subsy = NULL;
-	    }
-	  else if (sub_symbol_segment == this_segment
-		   && !TC_FORCE_RELOCATION_SUB_LOCAL (fixP))
-	    {
-	      add_number -= S_GET_VALUE (fixP->fx_subsy);
-	      fixP->fx_offset = (add_number + fixP->fx_dot_value
-				 + fixP->fx_frag->fr_address);
-
-	      /* Make it pc-relative.  If the back-end code has not
-		 selected a pc-relative reloc, cancel the adjustment
-		 we do later on all pc-relative relocs.  */
-	      if (0
-#ifdef TC_M68K
-		  /* Do this for m68k even if it's already described
-		     as pc-relative.  On the m68k, an operand of
-		     "pc@(foo-.-2)" should address "foo" in a
-		     pc-relative mode.  */
-		  || 1
-#endif
-		  || !fixP->fx_pcrel)
-		add_number += MD_PCREL_FROM_SECTION (fixP, this_segment);
-	      fixP->fx_subsy = NULL;
-	      fixP->fx_pcrel = 1;
-	    }
-	  else if (!TC_VALIDATE_FIX_SUB (fixP))
-	    {
-	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("can't resolve `%s' {%s section} - `%s' {%s section}"),
-			    fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
-			    segment_name (add_symbol_segment),
-			    S_GET_NAME (fixP->fx_subsy),
-			    segment_name (sub_symbol_segment));
-	    }
-	}
-
-      if (fixP->fx_addsy)
-	{
-	  if (add_symbol_segment == this_segment
-	      && !TC_FORCE_RELOCATION_LOCAL (fixP))
-	    {
-	      /* This fixup was made when the symbol's segment was
-		 SEG_UNKNOWN, but it is now in the local segment.
-		 So we know how to do the address without relocation.  */
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      fixP->fx_offset = add_number;
-	      if (fixP->fx_pcrel)
-		add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
-	      fixP->fx_addsy = NULL;
-	      fixP->fx_pcrel = 0;
-	    }
-	  else if (add_symbol_segment == absolute_section
-		   && !TC_FORCE_RELOCATION_ABS (fixP))
-	    {
-	      add_number += S_GET_VALUE (fixP->fx_addsy);
-	      fixP->fx_offset = add_number;
-	      fixP->fx_addsy = NULL;
-	    }
-	  else if (add_symbol_segment != undefined_section
-		   && ! bfd_is_com_section (add_symbol_segment)
-		   && MD_APPLY_SYM_VALUE (fixP))
-	    add_number += S_GET_VALUE (fixP->fx_addsy);
-	}
-
-      if (fixP->fx_pcrel)
-	{
-	  add_number -= MD_PCREL_FROM_SECTION (fixP, this_segment);
-	  if (!fixP->fx_done && fixP->fx_addsy == NULL)
-	    {
-	      /* There was no symbol required by this relocation.
-		 However, BFD doesn't really handle relocations
-		 without symbols well. So fake up a local symbol in
-		 the absolute section.  */
-	      fixP->fx_addsy = abs_section_sym;
-	    }
-	}
-
-      if (!fixP->fx_done)
-	md_apply_fix (fixP, &add_number, this_segment);
-
-      if (!fixP->fx_done)
-	{
-	  ++seg_reloc_count;
-	  if (fixP->fx_addsy == NULL)
-	    fixP->fx_addsy = abs_section_sym;
-	  symbol_mark_used_in_reloc (fixP->fx_addsy);
-	  if (fixP->fx_subsy != NULL)
-	    symbol_mark_used_in_reloc (fixP->fx_subsy);
-	}
-
-      if (!fixP->fx_bit_fixP && !fixP->fx_no_overflow && fixP->fx_size != 0)
-	{
-	  if (fixP->fx_size < sizeof (valueT))
-	    {
-	      valueT mask;
-
-	      mask = 0;
-	      mask--;		/* Set all bits to one.  */
-	      mask <<= fixP->fx_size * 8 - (fixP->fx_signed ? 1 : 0);
-	      if ((add_number & mask) != 0 && (add_number & mask) != mask)
-		{
-		  char buf[50], buf2[50];
-		  sprint_value (buf, fragP->fr_address + fixP->fx_where);
-		  if (add_number > 1000)
-		    sprint_value (buf2, add_number);
-		  else
-		    sprintf (buf2, "%ld", (long) add_number);
-		  as_bad_where (fixP->fx_file, fixP->fx_line,
-				_("value of %s too large for field of %d bytes at %s"),
-				buf2, fixP->fx_size, buf);
-		} /* Generic error checking.  */
-	    }
-#ifdef WARN_SIGNED_OVERFLOW_WORD
-	  /* Warn if a .word value is too large when treated as a signed
-	     number.  We already know it is not too negative.  This is to
-	     catch over-large switches generated by gcc on the 68k.  */
-	  if (!flag_signed_overflow_ok
-	      && fixP->fx_size == 2
-	      && add_number > 0x7fff)
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("signed .word overflow; switch may be too large; %ld at 0x%lx"),
-			  (long) add_number,
-			  (long) (fragP->fr_address + fixP->fx_where));
-#endif
-	}			/* Not a bit fix.  */
-
-#ifdef TC_VALIDATE_FIX
-    skip:  ATTRIBUTE_UNUSED_LABEL
-      ;
-#endif
-#ifdef DEBUG5
-      fprintf (stderr, "result:\n");
-      print_fixup (fixP);
-#endif
-    }				/* For each fixS in this segment.  */
-
-  TC_ADJUST_RELOC_COUNT (fixP, seg_reloc_count);
-  return seg_reloc_count;
-}
-
 void
 number_to_chars_bigendian (char *buf, valueT val, int n)
 {
diff --git a/gas/write.h b/gas/write.h
index 1f9b72dbf265..4f75eb6d611a 100644
--- a/gas/write.h
+++ b/gas/write.h
@@ -1,6 +1,7 @@
 /* write.h
    Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001,
-   2002, 2003, 2005, 2006 Free Software Foundation, Inc.
+   2002, 2003, 2005, 2006, 2007
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -22,12 +23,6 @@
 #ifndef __write_h__
 #define __write_h__
 
-#ifndef TC_I960
-#ifdef hpux
-#define EXEC_MACHINE_TYPE HP9000S200_ID
-#endif
-#endif /* TC_I960 */
-
 /* This is the name of a fake symbol which will never appear in the
    assembler output.  S_IS_LOCAL detects it because of the \001.  */
 #ifndef FAKE_LABEL_NAME
@@ -45,29 +40,16 @@ struct fix
   /* These small fields are grouped together for compactness of
      this structure, and efficiency of access on some architectures.  */
 
-  /* pc-relative offset adjust (only used by m68k) */
-  char fx_pcrel_adjust;
-
-  /* How many bytes are involved? */
-  unsigned char fx_size;
-
   /* Is this a pc-relative relocation?  */
   unsigned fx_pcrel : 1;
 
-  /* Is this a relocation to a procedure linkage table entry?  If so,
-     some of the reductions we try to apply are invalid.  A better way
-     might be to represent PLT entries with different kinds of
-     symbols, and use normal relocations (with undefined symbols);
-     look into it for version 2.6.  */
-  unsigned fx_plt : 1;
-
   /* Is this value an immediate displacement?  */
-  /* Only used on i960 and ns32k; merge it into TC_FIX_TYPE sometime.  */
+  /* Only used on ns32k; merge it into TC_FIX_TYPE sometime.  */
   unsigned fx_im_disp : 2;
 
-  /* A bit for the CPU specific code.
-     This probably can be folded into tc_fix_data, below.  */
+  /* Some bits for the CPU specific code.  */
   unsigned fx_tcbit : 1;
+  unsigned fx_tcbit2 : 1;
 
   /* Has this relocation already been applied?  */
   unsigned fx_done : 1;
@@ -82,6 +64,12 @@ struct fix
   /* The value is signed when checking for overflow.  */
   unsigned fx_signed : 1;
 
+  /* pc-relative offset adjust (only used by m68k and m68hc11) */
+  char fx_pcrel_adjust;
+
+  /* How many bytes are involved? */
+  unsigned char fx_size;
+
   /* Which frag does this fix apply to?  */
   fragS *fx_frag;
 
@@ -132,6 +120,10 @@ struct fix
     const struct cgen_insn *insn;
     /* Target specific data, usually reloc number.  */
     int opinfo;
+    /* Which ifield this fixup applies to. */
+    struct cgen_maybe_multi_ifield * field;
+    /* is this field is the MSB field in a set? */
+    int msb_field_p;
   } fx_cgen;
 #endif
 
@@ -144,11 +136,33 @@ struct fix
 
 typedef struct fix fixS;
 
+struct reloc_list
+{
+  struct reloc_list *next;
+  union
+  {
+    struct
+    {
+      symbolS *offset_sym;
+      reloc_howto_type *howto;
+      symbolS *sym;
+      bfd_vma addend;
+    } a;
+    struct
+    {
+      asection *sec;
+      asymbol *s;
+      arelent r;
+    } b;
+  } u;
+  char *file;
+  unsigned int line;
+};
+
 extern int finalize_syms;
 extern symbolS *abs_section_sym;
 extern addressT dot_value;
-extern long string_byte_count;
-extern int section_alignment[];
+extern struct reloc_list* reloc_list;
 
 extern void append (char **charPP, char *fromP, unsigned long length);
 extern void record_alignment (segT seg, int align);