diff options
Diffstat (limited to 'sys/arm64/include')
| -rw-r--r-- | sys/arm64/include/_armreg.h | 28 | ||||
| -rw-r--r-- | sys/arm64/include/_stdint.h | 8 | ||||
| -rw-r--r-- | sys/arm64/include/_types.h | 1 | ||||
| -rw-r--r-- | sys/arm64/include/armreg.h | 220 | ||||
| -rw-r--r-- | sys/arm64/include/cpu.h | 21 | ||||
| -rw-r--r-- | sys/arm64/include/cpu_feat.h | 7 | ||||
| -rw-r--r-- | sys/arm64/include/cpufunc.h | 3 | ||||
| -rw-r--r-- | sys/arm64/include/elf.h | 27 | ||||
| -rw-r--r-- | sys/arm64/include/hypervisor.h | 1873 | ||||
| -rw-r--r-- | sys/arm64/include/ifunc.h | 28 | ||||
| -rw-r--r-- | sys/arm64/include/machdep.h | 3 | ||||
| -rw-r--r-- | sys/arm64/include/param.h | 1 | ||||
| -rw-r--r-- | sys/arm64/include/pcpu.h | 11 | ||||
| -rw-r--r-- | sys/arm64/include/pmap.h | 19 | ||||
| -rw-r--r-- | sys/arm64/include/proc.h | 7 | ||||
| -rw-r--r-- | sys/arm64/include/rsi.h | 129 | ||||
| -rw-r--r-- | sys/arm64/include/sf_buf.h | 4 | ||||
| -rw-r--r-- | sys/arm64/include/stack.h | 11 | ||||
| -rw-r--r-- | sys/arm64/include/ucontext.h | 4 | ||||
| -rw-r--r-- | sys/arm64/include/vm.h | 31 | ||||
| -rw-r--r-- | sys/arm64/include/vmm.h | 116 | ||||
| -rw-r--r-- | sys/arm64/include/vmm_instruction_emul.h | 8 | ||||
| -rw-r--r-- | sys/arm64/include/vmparam.h | 22 |
23 files changed, 2417 insertions, 165 deletions
diff --git a/sys/arm64/include/_armreg.h b/sys/arm64/include/_armreg.h index 0f5134e5a978..0ade9e6168c9 100644 --- a/sys/arm64/include/_armreg.h +++ b/sys/arm64/include/_armreg.h @@ -52,6 +52,34 @@ #define WRITE_SPECIALREG(reg, _val) \ __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) + +#define __SYS_ALT_NAME(op1, crn, crm, op2) \ + "#" #op1 ", C" #crn ", C" #crm ", #" #op2 +#define _SYS_ALT_NAME(op1, crn, crm, op2) \ + __SYS_ALT_NAME(op1, crn, crm, op2) +#define SYS_ALT_NAME(insn) \ + _SYS_ALT_NAME(insn##_op1, insn##_CRn, insn##_CRm, insn##_op2) + +#define SYS(insn) do { \ + _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ + __asm __volatile("sys " SYS_ALT_NAME(insn)); \ +} while (0) + +#define SYS_ARG(insn, _val) do { \ + _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ + __asm __volatile("sys " SYS_ALT_NAME(insn) ", %0" \ + : : "r"((uint64_t)_val)); \ +} while (0) + +#define SYSL(insn) \ +({ \ + uint64_t _val; \ + _Static_assert(insn##_op0 == 1, "Invalid SYS instruction"); \ + __asm __volatile("sysl %0, " SYS_ALT_NAME(insn) \ + : "=&r"(_val)); \ + _val; \ +}) + #define UL(x) UINT64_C(x) #endif /* !_MACHINE__ARMREG_H_ */ diff --git a/sys/arm64/include/_stdint.h b/sys/arm64/include/_stdint.h index 0b360b8ab460..621e5ce53721 100644 --- a/sys/arm64/include/_stdint.h +++ b/sys/arm64/include/_stdint.h @@ -35,8 +35,6 @@ #ifndef _MACHINE__STDINT_H_ #define _MACHINE__STDINT_H_ -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) - #define INT8_C(c) (c) #define INT16_C(c) (c) #define INT32_C(c) (c) @@ -50,10 +48,6 @@ #define INTMAX_C(c) INT64_C(c) #define UINTMAX_C(c) UINT64_C(c) -#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) - /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types @@ -178,8 +172,6 @@ #define WINT_WIDTH INT32_WIDTH #endif /* __ISO_C_VISIBLE >= 2023 */ -#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ - #endif /* !_MACHINE__STDINT_H_ */ #endif /* !__arm__ */ diff --git a/sys/arm64/include/_types.h b/sys/arm64/include/_types.h index 98f7dea67520..c46f64b2b252 100644 --- a/sys/arm64/include/_types.h +++ b/sys/arm64/include/_types.h @@ -55,6 +55,7 @@ typedef __int64_t __int_fast64_t; typedef __int64_t __register_t; typedef __int64_t __segsz_t; /* segment size (in pages) */ typedef __int64_t __time_t; /* time()... */ +#define __SIZEOF_TIME_T __SIZEOF_INT64_T typedef __uint32_t __uint_fast8_t; typedef __uint32_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 27b02c44cd76..4233a01d143c 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -167,30 +167,76 @@ #define APIBKeyLo_EL1_op2 2 /* CCSIDR_EL1 - Cache Size ID Register */ -#define CCSIDR_NumSets_MASK 0x0FFFE000 -#define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 -#define CCSIDR_NumSets_SHIFT 13 -#define CCSIDR_NumSets64_SHIFT 32 -#define CCSIDR_Assoc_MASK 0x00001FF8 -#define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 +#define CCSIDR_EL1_REG MRS_REG_ALT_NAME(CCSIDR_EL1) +#define CCSIDR_EL1_op0 2 +#define CCSIDR_EL1_op1 1 +#define CCSIDR_EL1_CRn 0 +#define CCSIDR_EL1_CRm 0 +#define CCSIDR_EL1_op2 0 +#define CCSIDR_LineSize_SHIFT 0 +#define CCSIDR_LineSize_WIDTH 3 +#define CCSIDR_LineSize_MASK (UL(0x7) << CCSIDR_LineSize_SHIFT) +#define CCSIDR_LineSize_VAL(x) ((x) & CCSIDR_LineSize_MASK) #define CCSIDR_Assoc_SHIFT 3 +#define CCSIDR_Assoc_WIDTH 10 +#define CCSIDR_Assoc_MASK (UL(0x3ff) << CCSIDR_Assoc_SHIFT) +#define CCSIDR_Assoc_VAL(x) ((x) & CCSIDR_Assoc_MASK) +#define CCSIDR_NumSets_SHIFT 13 +#define CCSIDR_NumSets_WIDTH 15 +#define CCSIDR_NumSets_MASK (UL(0x7fff) << CCSIDR_NumSets_SHIFT) +#define CCSIDR_NumSets_VAL(x) ((x) & CCSIDR_NumSets_MASK) +/* FEAT_CCIDX - Extended Cache Index */ #define CCSIDR_Assoc64_SHIFT 3 -#define CCSIDR_LineSize_MASK 0x7 -#define CCSIDR_NSETS(idr) \ +#define CCSIDR_Assoc64_WIDTH 20 +#define CCSIDR_Assoc64_MASK (UL(0x1fffff) << CCSIDR_Assoc64_SHIFT) +#define CCSIDR_Assoc64_VAL(x) ((x) & CCSIDR_Assoc64_MASK) +#define CCSIDR_NumSets64_SHIFT 32 +#define CCSIDR_NumSets64_WIDTH 23 +#define CCSIDR_NumSets64_MASK (UL(0xffffff) << CCSIDR_NumSets64_SHIFT) +#define CCSIDR_NumSets64_VAL(x) ((x) & CCSIDR_NumSets64_MASK) +#define CCSIDR_NumSets(idr) \ (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) -#define CCSIDR_ASSOC(idr) \ - (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) -#define CCSIDR_NSETS_64(idr) \ +#define CCSIDR_NumSets64(idr) \ (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) -#define CCSIDR_ASSOC_64(idr) \ +#define CCSIDR_Assoc(idr) \ + (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) +#define CCSIDR_Assoc64(idr) \ (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) /* CLIDR_EL1 - Cache level ID register */ -#define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ -#define CLIDR_CTYPE_IO 0x1 /* Instruction only */ -#define CLIDR_CTYPE_DO 0x2 /* Data only */ -#define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ -#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ +#define CLIDR_EL1_REG MRS_REG_ALT_NAME(CLIDR_EL1) +#define CLIDR_EL1_op0 2 +#define CLIDR_EL1_op1 1 +#define CLIDR_EL1_CRn 0 +#define CLIDR_EL1_CRm 0 +#define CLIDR_EL1_op2 1 +#define CLIDR_CTYPE_MASK UL(0x7) +#define CLIDR_CTYPE_NONE 0x0 /* No cache */ +#define CLIDR_CTYPE_IC 0x1 /* Instruction cache only */ +#define CLIDR_CTYPE_DC 0x2 /* Data cache only */ +#define CLIDR_CTYPE_IO 0x3 /* Separate instruction & data cache */ +#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified cache */ +#define CLIDR_LoUIS_SHIFT 21 +#define CLIDR_LoUIS_WIDTH 3 +#define CLIDR_LoUIS_MASK (UL(0x7) << CLIDR_LoUIS_SHIFT) +#define CLIDR_LoUIS_VAL(x) ((x) & CLIDR_LoUIS_MASK) +#define CLIDR_LoC_SHIFT 24 +#define CLIDR_LoC_WIDTH 3 +#define CLIDR_LoC_MASK (UL(0x7) << CLIDR_LoC_SHIFT) +#define CLIDR_LoC_VAL(x) ((x) & CLIDR_LoC_MASK) +#define CLIDR_LoUU_SHIFT 27 +#define CLIDR_LoUU_WIDTH 3 +#define CLIDR_LoUU_MASK (UL(0x7) << CLIDR_LoUU_SHIFT) +#define CLIDR_LoUU_VAL(x) ((x) & CLIDR_LoUU_MASK) +#define CLIDR_ICB_SHIFT 30 +#define CLIDR_ICB_WIDTH 3 +#define CLIDR_ICB_MASK (UL(0x7) << CLIDR_ICB_SHIFT) +#define CLIDR_ICB_VAL(x) ((x) & CLIDR_ICB_MASK) +#define CLIDR_TTYPE_MASK UL(0x7) +#define CLIDR_TTYPE_NONE 0x0 /* No tag cache */ +#define CLIDR_TTYPE_SAT 0x1 /* Separate Allocation Tag cache */ +#define CLIDR_TTYPE_UATU 0x2 /* Unified Allocation Tag, unified lines */ +#define CLIDR_TTYPE_UATS 0x3 /* Unified Allocation Tag, separate lines */ /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ #define CNTKCTL_EL1_op0 3 @@ -342,8 +388,28 @@ #define CPACR_EL12_op2 2 /* CSSELR_EL1 - Cache size selection register */ -#define CSSELR_Level(i) (i << 1) -#define CSSELR_InD 0x00000001 +#define CSSELR_EL1_REG MRS_REG_ALT_NAME(CSSELR_EL1) +#define CSSELR_EL1_op0 3 +#define CSSELR_EL1_op1 2 +#define CSSELR_EL1_CRn 0 +#define CSSELR_EL1_CRm 0 +#define CSSELR_EL1_op2 0 +#define CSSELR_InD_SHIFT 0 +#define CSSELR_InD_WIDTH 1 +#define CSSELR_InD_MASK (UL(0x1) << CSSELR_InD_SHIFT) +#define CSSELR_InD_VAL(x) ((x) & CSSELR_InD_MASK) +#define CSSELR_InD_DC (0x0 << CSSELR_InD_SHIFT) /* Data or unified cache */ +#define CSSELR_InD_IC (0x1 << CSSELR_InD_SHIFT) /* Instruction cache */ +#define CSSELR_Level_SHIFT 1 +#define CSSELR_Level_WIDTH 3 +#define CSSELR_Level_MASK (UL(0x7) << CSSELR_Level_SHIFT) +#define CSSELR_Level(i) (i << CSSELR_Level_SHIFT) +#define CSSELR_TnD_SHIFT 4 +#define CSSELR_TnD_WIDTH 1 +#define CSSELR_TnD_MASK (UL(0x1) << CSSELR_TnD_SHIFT) +#define CSSELR_TnD_VAL(x) ((x) & CSSELR_TnD_MASK) +#define CSSELR_TnD_DIU (0x0 << CSSELR_TnD_SHIFT) /* Data, Instruction or Unified cache */ +#define CSSELR_TnD_SAT (0x1 << CSSELR_TnD_SHIFT) /* Separate Allocation Tag cache */ /* CTR_EL0 - Cache Type Register */ #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0) @@ -592,6 +658,27 @@ #define ISS_MSR_REG(reg) \ __ISS_MSR_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) +#define ISS_MOE_MEMINST_SHIFT 24 +#define ISS_MOE_MEMINST (0x01 << ISS_MOE_MEMINST_SHIFT) +#define ISS_MOE_isSETG_SHIFT 24 +#define ISS_MOE_isSETG (0x01 << ISS_MOE_isSETG_SHIFT) +#define ISS_MOE_OPTIONS_SHIFT 19 +#define ISS_MOE_OPTIONS_MASK (0x0f << ISS_MOE_OPTIONS_SHIFT) +#define ISS_MOE_FROM_EPILOGUE_SHIFT 18 +#define ISS_MOE_FROM_EPILOGUE (0x01 << ISS_MOE_FROM_EPILOGUE_SHIFT) +#define ISS_MOE_FORMAT_OPTION_SHIFT 16 +#define ISS_MOE_FORMAT_OPTION_MASK (0x03 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_B (0x00 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_A (0x01 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_A2 (0x02 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_FORMAT_OPTION_B2 (0x03 << ISS_MOE_FORMAT_OPTION_SHIFT) +#define ISS_MOE_DESTREG_SHIFT 10 +#define ISS_MOE_DESTREG_MASK (0x1f << ISS_MOE_DESTREG_SHIFT) +#define ISS_MOE_SRCREG_SHIFT 5 +#define ISS_MOE_SRCREG_MASK (0x1f << ISS_MOE_SRCREG_SHIFT) +#define ISS_MOE_SIZEREG_SHIFT 0 +#define ISS_MOE_SIZEREG_MASK (0x1f << ISS_MOE_SIZEREG_SHIFT) + #define ISS_DATA_ISV_SHIFT 24 #define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) #define ISS_DATA_SAS_SHIFT 22 @@ -624,6 +711,7 @@ #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) #define ISS_DATA_DFSC_EXT (0x10 << 0) +#define ISS_DATA_DFSC_TAG (0x11 << 0) #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) @@ -637,7 +725,7 @@ #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) #define ESR_ELx_IL (0x01 << 25) #define ESR_ELx_EC_SHIFT 26 -#define ESR_ELx_EC_MASK (0x3f << 26) +#define ESR_ELx_EC_MASK (UL(0x3f) << 26) #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ @@ -656,6 +744,7 @@ #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ #define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ +#define EXCP_MOE 0x27 /* Memory Operation Exception */ #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ #define EXCP_SERROR 0x2f /* SError interrupt */ #define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ @@ -699,6 +788,30 @@ #define FAR_EL12_CRm 0 #define FAR_EL12_op2 0 +/* GCR_EL1 - Tag Control Register */ +#define GCR_EL1_REG MRS_REG_ALT_NAME(GCR_EL1) +#define GCR_EL1_op0 3 +#define GCR_EL1_op1 0 +#define GCR_EL1_CRn 1 +#define GCR_EL1_CRm 0 +#define GCR_EL1_op2 6 +#define GCR_Exclude_SHIFT 0 +#define GCR_Exclude_MASK (UL(0xffff) << GCR_Exclude_SHIFT) +#define GCR_RRND_SHIFT 16 +#define GCR_RRND (UL(0x1) << GCR_RRND_SHIFT) + +/* GMID_EL1 - Multiple tag transfer ID Register */ +#define GMID_EL1_REG MRS_REG_ALT_NAME(GMID_EL1) +#define GMID_EL1_op0 3 +#define GMID_EL1_op1 1 +#define GMID_EL1_CRn 0 +#define GMID_EL1_CRm 0 +#define GMID_EL1_op2 4 +#define GMID_BS_SHIFT 0 +#define GMID_BS_WIDTH 4 +#define GMID_BS_MASK (UL(0xf) << GMID_BS_SHIFT) +#define GMID_BS_SIZE(reg) (((reg) & GMID_BS_MASK) >> GMID_BS_SHIFT) + /* ICC_CTLR_EL1 */ #define ICC_CTLR_EL1_EOIMODE (1U << 1) @@ -1960,12 +2073,13 @@ #define MAIR_EL1_CRn 10 #define MAIR_EL1_CRm 2 #define MAIR_EL1_op2 0 -#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) +#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((idx) * 8)) #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_DEVICE_nGnRnE UL(0x00) #define MAIR_DEVICE_nGnRE UL(0x04) #define MAIR_NORMAL_NC UL(0x44) #define MAIR_NORMAL_WT UL(0xbb) +#define MAIR_NORMAL_TG UL(0xf0) #define MAIR_NORMAL_WB UL(0xff) /* MAIR_EL12 */ @@ -2579,6 +2693,18 @@ #define PMXEVTYPER_EL0_CRm 13 #define PMXEVTYPER_EL0_op2 1 +/* RGSR_EL1 - Random Allocation Tag Seed Register */ +#define RGSR_EL1_REG MRS_REG_ALT_NAME(RGSR_EL1) +#define RGSR_EL1_op0 3 +#define RGSR_EL1_op1 0 +#define RGSR_EL1_CRn 1 +#define RGSR_EL1_CRm 0 +#define RGSR_EL1_op2 5 +#define RGSR_TAG_SHIFT 0 +#define RGSR_TAG_MASK (UL(0xf) << RGSR_TAG_SHIFT) +#define RGSR_SEED_SHIFT 8 +#define RGSR_SEED_MASK (UL(0xffff) << RGSR_SEED_SHIFT) + /* RNDRRS */ #define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS) #define RNDRRS_op0 3 @@ -2627,12 +2753,24 @@ #define SCTLR_LSMAOE (UL(0x1) << 29) #define SCTLR_EnIB (UL(0x1) << 30) #define SCTLR_EnIA (UL(0x1) << 31) -/* Bits 34:32 are reserved */ +/* Bit 32 is reserved */ +#define SCTLR_MSCEn (UL(0x1) << 33) +/* Bit 34 is reserved */ #define SCTLR_BT0 (UL(0x1) << 35) #define SCTLR_BT1 (UL(0x1) << 36) #define SCTLR_ITFSB (UL(0x1) << 37) -#define SCTLR_TCF0_MASK (UL(0x3) << 38) -#define SCTLR_TCF_MASK (UL(0x3) << 40) +#define SCTLR_TCF0_SHIFT 38 +#define SCTLR_TCF0_MASK (UL(0x3) << SCTLR_TCF0_SHIFT) +#define SCTLR_TCF0_NONE (UL(0x0) << SCTLR_TCF0_SHIFT) +#define SCTLR_TCF0_SYNC (UL(0x1) << SCTLR_TCF0_SHIFT) +#define SCTLR_TCF0_ASYNC (UL(0x2) << SCTLR_TCF0_SHIFT) +#define SCTLR_TCF0_ASYM (UL(0x3) << SCTLR_TCF0_SHIFT) +#define SCTLR_TCF_SHIFT 40 +#define SCTLR_TCF_MASK (UL(0x3) << SCTLR_TCF_SHIFT) +#define SCTLR_TCF_NONE (UL(0x0) << SCTLR_TCF_SHIFT) +#define SCTLR_TCF_SYNC (UL(0x1) << SCTLR_TCF_SHIFT) +#define SCTLR_TCF_ASYNC (UL(0x2) << SCTLR_TCF_SHIFT) +#define SCTLR_TCF_ASYM (UL(0x3) << SCTLR_TCF_SHIFT) #define SCTLR_ATA0 (UL(0x1) << 42) #define SCTLR_ATA (UL(0x1) << 43) #define SCTLR_DSSBS (UL(0x1) << 44) @@ -2665,6 +2803,7 @@ SCTLR_SA | \ SCTLR_C | \ SCTLR_M) +#define SCTLR_USER_MASK (SCTLR_ATA0 | SCTLR_TCF0_MASK) /* SCTLR_EL12 */ #define SCTLR_EL12_REG MRS_REG_ALT_NAME(SCTLR_EL12) @@ -2742,6 +2881,15 @@ #define REVIDR_EL1_CRm 0 #define REVIDR_EL1_op2 6 +/* TCO - Tag Check Override */ +#define TCO MRS(TCO) +#define TCO_REG MRS_REG_ALT_NAME(TCO) +#define TCO_op0 3 +#define TCO_op1 3 +#define TCO_CRn 4 +#define TCO_CRm 2 +#define TCO_op2 7 + /* TCR_EL1 - Translation Control Register */ #define TCR_EL1_REG MRS_REG_ALT_NAME(TCR_EL1) #define TCR_EL1_op0 3 @@ -2857,6 +3005,30 @@ #define TCR_EL12_CRm 0 #define TCR_EL12_op2 2 +/* TFSRE0_EL1 - Tag Fault Status Register (EL0) */ +#define TFSRE0_EL1_REG MRS_REG_ALT_NAME(TFSRE0_EL1) +#define TFSRE0_EL1_op0 3 +#define TFSRE0_EL1_op1 0 +#define TFSRE0_EL1_CRn 5 +#define TFSRE0_EL1_CRm 6 +#define TFSRE0_EL1_op2 1 +#define TFSRE0_TF0_SHIFT 0 +#define TFSRE0_TF0_MASK (UL(0x1) << TFSRE0_TF0_SHIFT) +#define TFSRE0_TF1_SHIFT 1 +#define TFSRE0_TF1_MASK (UL(0x1) << TFSRE0_TF1_SHIFT) + +/* TFSR_EL1 - Tag Fault Status Register */ +#define TFSR_EL1_REG MRS_REG_ALT_NAME(TFSR_EL1) +#define TFSR_EL1_op0 3 +#define TFSR_EL1_op1 0 +#define TFSR_EL1_CRn 5 +#define TFSR_EL1_CRm 6 +#define TFSR_EL1_op2 0 +#define TFSR_TF0_SHIFT 0 +#define TFSR_TF0_MASK (UL(0x1) << TFSR_TF0_SHIFT) +#define TFSR_TF1_SHIFT 1 +#define TFSR_TF1_MASK (UL(0x1) << TFSR_TF1_SHIFT) + /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ #define TTBR_ASID_SHIFT 48 #define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) diff --git a/sys/arm64/include/cpu.h b/sys/arm64/include/cpu.h index b15210633d37..bdbc601edd26 100644 --- a/sys/arm64/include/cpu.h +++ b/sys/arm64/include/cpu.h @@ -277,15 +277,25 @@ void ptrauth_thread0(struct thread *); void ptrauth_mp_start(uint64_t); #endif +/* Memory Tagging Extension (MTE) support */ +void mte_fork(struct thread *, struct thread *); +void mte_exec(struct thread *); +void mte_copy_thread(struct thread *, struct thread *); +void mte_thread_alloc(struct thread *); +void mte_thread0(struct thread *); + +void mte_sync_tags(vm_page_t page); +void mte_copy_tags(vm_page_t, vm_page_t, char *, char *); + /* Functions to read the sanitised view of the special registers */ void update_special_regs(u_int); void update_special_reg_iss(u_int, uint64_t, uint64_t); #define update_special_reg(reg, clear, set) \ update_special_reg_iss(reg ## _ISS, clear, set) -bool get_kernel_reg_iss(u_int, uint64_t *); +void get_kernel_reg_iss(u_int, uint64_t *); #define get_kernel_reg(reg, valp) \ get_kernel_reg_iss(reg ## _ISS, valp) -bool get_kernel_reg_iss_masked(u_int, uint64_t *, uint64_t); +void get_kernel_reg_iss_masked(u_int, uint64_t *, uint64_t); #define get_kernel_reg_masked(reg, valp, mask) \ get_kernel_reg_iss_masked(reg ## _ISS, valp, mask) bool get_user_reg_iss(u_int, uint64_t *, bool); @@ -328,7 +338,12 @@ ADDRESS_TRANSLATE_FUNC(s1e1r) ADDRESS_TRANSLATE_FUNC(s1e1w) #endif /* !__ASSEMBLER__ */ -#endif + +#define MEMSET_EARLY_FUNC memset_std +#define MEMCPY_EARLY_FUNC memcpy_std +#define MEMMOVE_EARLY_FUNC memmove_std + +#endif /* _KERNEL */ #endif /* !_MACHINE_CPU_H_ */ diff --git a/sys/arm64/include/cpu_feat.h b/sys/arm64/include/cpu_feat.h index 6a311d4000bb..5eff7f589d8b 100644 --- a/sys/arm64/include/cpu_feat.h +++ b/sys/arm64/include/cpu_feat.h @@ -62,7 +62,12 @@ typedef enum { */ FEAT_DEFAULT_ENABLE, - /* We could add FEAT_ALWAYS_ENABLE if a need was found. */ + /* + * Always enabled. Used when there is no way for the kernel to + * work without the feature, e.g. configuring the interrupt + * controller. + */ + FEAT_ALWAYS_ENABLE, } cpu_feat_en; #define CPU_FEAT_STAGE_MASK 0x00000001 diff --git a/sys/arm64/include/cpufunc.h b/sys/arm64/include/cpufunc.h index e9eee643216b..f600b30edf5f 100644 --- a/sys/arm64/include/cpufunc.h +++ b/sys/arm64/include/cpufunc.h @@ -196,8 +196,6 @@ extern int64_t dczva_line_size; #define cpu_nullop() arm64_nullop() #define cpufunc_nullop() arm64_nullop() -#define cpu_tlb_flushID() arm64_tlb_flushID() - #define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s)) #define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s)) #define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s)) @@ -208,7 +206,6 @@ extern void (*arm64_icache_sync_range)(void *, vm_size_t); #define cpu_icache_sync_range_checked(a, s) arm64_icache_sync_range_checked((a), (s)) void arm64_nullop(void); -void arm64_tlb_flushID(void); void arm64_dic_idc_icache_sync_range(void *, vm_size_t); void arm64_idc_aliasing_icache_sync_range(void *, vm_size_t); void arm64_aliasing_icache_sync_range(void *, vm_size_t); diff --git a/sys/arm64/include/elf.h b/sys/arm64/include/elf.h index 81ee7392f866..7940bb259256 100644 --- a/sys/arm64/include/elf.h +++ b/sys/arm64/include/elf.h @@ -96,6 +96,12 @@ __ElfType(Auxinfo); /* First __FreeBSD_version that supports Top Byte Ignore (TBI) */ #define TBI_VERSION 1500058 +/* + * The HWCAP values must be identical to Linux. Many userspace programs + * will define missing HWCAP values to the Linux version. To keep these + * working when we add the HWCAP it must be the same. + */ + /* HWCAP */ #define HWCAP_FP (1 << 0) #define HWCAP_ASIMD (1 << 1) @@ -135,6 +141,21 @@ __ElfType(Auxinfo); #define HWCAP_PACA (1 << 30) #define HWCAP_PACG (1UL << 31) #define HWCAP_GCS (1UL << 32) +#define HWCAP_CMPBR (1UL << 33) +#define HWCAP_FPRCVT (1UL << 34) +#define HWCAP_F8MM8 (1UL << 35) +#define HWCAP_F8MM4 (1UL << 36) +#define HWCAP_SVE_F16MM (1UL << 37) +#define HWCAP_SVE_ELTPERM (1UL << 38) +#define HWCAP_SVE_AES2 (1UL << 39) +#define HWCAP_SVE_BFSCALE (1UL << 40) +#define HWCAP_SVE2P2 (1UL << 41) +#define HWCAP_SME2P2 (1UL << 42) +#define HWCAP_SME_SBITPERM (1UL << 43) +#define HWCAP_SME_AES (1UL << 44) +#define HWCAP_SME_SFEXPA (1UL << 45) +#define HWCAP_SME_STMOP (1UL << 46) +#define HWCAP_SME_SMOP4 (1UL << 47) /* HWCAP2 */ #define HWCAP2_DCPODP (1 << 0) @@ -202,6 +223,12 @@ __ElfType(Auxinfo); #define HWCAP2_SME_SF8DP2 (1UL << 62) #define HWCAP2_POE (1UL << 63) +/* HWCAP3 */ +#define HWCAP3_MTE_FAR (1 << 0) +#define HWCAP3_MTE_STORE_ONLY (1 << 1) +#define HWCAP3_LSFE (1 << 2) +#define HWCAP3_LS64 (1 << 3) + #ifdef COMPAT_FREEBSD32 /* ARM HWCAP */ #define HWCAP32_HALF 0x00000002 /* Always set. */ diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index f3d7027269c9..0b6492785a0a 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -134,6 +134,15 @@ /* Unconditionally valid */ #define CPTR_TCPAC 0x80000000 +/* HAFGRTR_EL2 */ +#define HAFGRTR_EL2_REG MRS_REG_ALT_NAME(HAFGRTR_EL2) +#define HAFGRTR_EL2_op0 3 +#define HAFGRTR_EL2_op1 4 +#define HAFGRTR_EL2_CRn 3 +#define HAFGRTR_EL2_CRm 1 +#define HAFGRTR_EL2_op2 6 +#define HAFGRTR_EL2_TRAP_ALL UL(0x0003fffffffe001f) + /* HCR_EL2 - Hypervisor Config Register */ #define HCR_VM (UL(0x1) << 0) #define HCR_SWIO (UL(0x1) << 1) @@ -234,6 +243,1741 @@ /* Bit 25 is reserved */ #define HCRX_SRMASKEn (UL(0x1) << 26) +/* HDFGRTR2_EL2 */ +#define HDFGRTR2_EL2_REG MRS_REG_ALT_NAME(HDFGRTR2_EL2) +#define HDFGRTR2_EL2_op0 3 +#define HDFGRTR2_EL2_op1 4 +#define HDFGRTR2_EL2_CRn 3 +#define HDFGRTR2_EL2_CRm 1 +#define HDFGRTR2_EL2_op2 0 +#define HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT 23 +#define HDFGRTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGRTR2_EL2_nMDSTEPOP_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nMDSTEPOP_EL1_MASK) +#define HDFGRTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGRTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT 22 +#define HDFGRTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRBMPAM_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nTRBMPAM_EL1_MASK) +#define HDFGRTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT 20 +#define HDFGRTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRCITECR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nTRCITECR_EL1_MASK) +#define HDFGRTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGRTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT 19 +#define HDFGRTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSDSFR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMSDSFR_EL1_MASK) +#define HDFGRTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT 18 +#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMDEVAFF_EL1_MASK) +#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMID_SHIFT 17 +#define HDFGRTR2_EL2_nSPMID_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT) +#define HDFGRTR2_EL2_nSPMID_VAL(x) ((x) & HDFGRTR2_EL2_nSPMID_MASK) +#define HDFGRTR2_EL2_nSPMID_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMID_SHIFT) +#define HDFGRTR2_EL2_nSPMID_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT) +#define HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT 16 +#define HDFGRTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMSCR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMSCR_EL1_MASK) +#define HDFGRTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT 15 +#define HDFGRTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMACCESSR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nSPMACCESSR_EL1_MASK) +#define HDFGRTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGRTR2_EL2_nSPMCR_EL0_SHIFT 14 +#define HDFGRTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMCR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMCR_EL0_MASK) +#define HDFGRTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMOVS_SHIFT 13 +#define HDFGRTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT) +#define HDFGRTR2_EL2_nSPMOVS_VAL(x) ((x) & HDFGRTR2_EL2_nSPMOVS_MASK) +#define HDFGRTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMOVS_SHIFT) +#define HDFGRTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT) +#define HDFGRTR2_EL2_nSPMINTEN_SHIFT 12 +#define HDFGRTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMINTEN_VAL(x) ((x) & HDFGRTR2_EL2_nSPMINTEN_MASK) +#define HDFGRTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMCNTEN_SHIFT 11 +#define HDFGRTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMCNTEN_VAL(x) ((x) & HDFGRTR2_EL2_nSPMCNTEN_MASK) +#define HDFGRTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT 10 +#define HDFGRTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMSELR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMSELR_EL0_MASK) +#define HDFGRTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT 9 +#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMEVTYPERn_EL0_MASK) +#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT 8 +#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nSPMEVCNTRn_EL0_MASK) +#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT 7 +#define HDFGRTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSSCR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMSSCR_EL1_MASK) +#define HDFGRTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMSSDATA_SHIFT 6 +#define HDFGRTR2_EL2_nPMSSDATA_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) +#define HDFGRTR2_EL2_nPMSSDATA_VAL(x) ((x) & HDFGRTR2_EL2_nPMSSDATA_MASK) +#define HDFGRTR2_EL2_nPMSSDATA_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) +#define HDFGRTR2_EL2_nPMSSDATA_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT) +#define HDFGRTR2_EL2_nMDSELR_EL1_SHIFT 5 +#define HDFGRTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGRTR2_EL2_nMDSELR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nMDSELR_EL1_MASK) +#define HDFGRTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGRTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMUACR_EL1_SHIFT 4 +#define HDFGRTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMUACR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMUACR_EL1_MASK) +#define HDFGRTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT 3 +#define HDFGRTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMICFILTR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nPMICFILTR_EL0_MASK) +#define HDFGRTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT 2 +#define HDFGRTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMICNTR_EL0_VAL(x) ((x) & HDFGRTR2_EL2_nPMICNTR_EL0_MASK) +#define HDFGRTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGRTR2_EL2_nPMIAR_EL1_SHIFT 1 +#define HDFGRTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMIAR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMIAR_EL1_MASK) +#define HDFGRTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMECR_EL1_SHIFT 0 +#define HDFGRTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMECR_EL1_VAL(x) ((x) & HDFGRTR2_EL2_nPMECR_EL1_MASK) +#define HDFGRTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) +#define HDFGRTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT) + +/* HDFGRTR_EL2 */ +#define HDFGRTR_EL2_REG MRS_REG_ALT_NAME(HDFGRTR_EL2) +#define HDFGRTR_EL2_op0 3 +#define HDFGRTR_EL2_op1 4 +#define HDFGRTR_EL2_CRn 3 +#define HDFGRTR_EL2_CRm 1 +#define HDFGRTR_EL2_op2 4 +#define HDFGRTR_EL2_PMBIDR_EL1_SHIFT 63 +#define HDFGRTR_EL2_PMBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBIDR_EL1_MASK) +#define HDFGRTR_EL2_PMBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT 62 +#define HDFGRTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_nPMSNEVFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_nPMSNEVFR_EL1_MASK) +#define HDFGRTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_nBRBDATA_SHIFT 61 +#define HDFGRTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT) +#define HDFGRTR_EL2_nBRBDATA_VAL(x) ((x) & HDFGRTR_EL2_nBRBDATA_MASK) +#define HDFGRTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBDATA_SHIFT) +#define HDFGRTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT) +#define HDFGRTR_EL2_nBRBCTL_SHIFT 60 +#define HDFGRTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT) +#define HDFGRTR_EL2_nBRBCTL_VAL(x) ((x) & HDFGRTR_EL2_nBRBCTL_MASK) +#define HDFGRTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBCTL_SHIFT) +#define HDFGRTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT) +#define HDFGRTR_EL2_nBRBIDR_SHIFT 59 +#define HDFGRTR_EL2_nBRBIDR_MASK (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT) +#define HDFGRTR_EL2_nBRBIDR_VAL(x) ((x) & HDFGRTR_EL2_nBRBIDR_MASK) +#define HDFGRTR_EL2_nBRBIDR_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBIDR_SHIFT) +#define HDFGRTR_EL2_nBRBIDR_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT) +#define HDFGRTR_EL2_PMCEIDn_EL0_SHIFT 58 +#define HDFGRTR_EL2_PMCEIDn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) +#define HDFGRTR_EL2_PMCEIDn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCEIDn_EL0_MASK) +#define HDFGRTR_EL2_PMCEIDn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) +#define HDFGRTR_EL2_PMCEIDn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT) +#define HDFGRTR_EL2_PMUSERENR_EL0_SHIFT 57 +#define HDFGRTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGRTR_EL2_PMUSERENR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMUSERENR_EL0_MASK) +#define HDFGRTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGRTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGRTR_EL2_TRBTRG_EL1_SHIFT 56 +#define HDFGRTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGRTR_EL2_TRBTRG_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBTRG_EL1_MASK) +#define HDFGRTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGRTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGRTR_EL2_TRBSR_EL1_SHIFT 55 +#define HDFGRTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBSR_EL1_MASK) +#define HDFGRTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBPTR_EL1_SHIFT 54 +#define HDFGRTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBPTR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBPTR_EL1_MASK) +#define HDFGRTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBMAR_EL1_SHIFT 53 +#define HDFGRTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBMAR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBMAR_EL1_MASK) +#define HDFGRTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT 52 +#define HDFGRTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBLIMITR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBLIMITR_EL1_MASK) +#define HDFGRTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBIDR_EL1_SHIFT 51 +#define HDFGRTR_EL2_TRBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBIDR_EL1_MASK) +#define HDFGRTR_EL2_TRBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT) +#define HDFGRTR_EL2_TRBBASER_EL1_SHIFT 50 +#define HDFGRTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGRTR_EL2_TRBBASER_EL1_VAL(x) ((x) & HDFGRTR_EL2_TRBBASER_EL1_MASK) +#define HDFGRTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGRTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGRTR_EL2_TRCVICTLR_SHIFT 48 +#define HDFGRTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT) +#define HDFGRTR_EL2_TRCVICTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCVICTLR_MASK) +#define HDFGRTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCVICTLR_SHIFT) +#define HDFGRTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT) +#define HDFGRTR_EL2_TRCSTATR_SHIFT 47 +#define HDFGRTR_EL2_TRCSTATR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT) +#define HDFGRTR_EL2_TRCSTATR_VAL(x) ((x) & HDFGRTR_EL2_TRCSTATR_MASK) +#define HDFGRTR_EL2_TRCSTATR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSTATR_SHIFT) +#define HDFGRTR_EL2_TRCSTATR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT) +#define HDFGRTR_EL2_TRCSSCSRn_SHIFT 46 +#define HDFGRTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGRTR_EL2_TRCSSCSRn_VAL(x) ((x) & HDFGRTR_EL2_TRCSSCSRn_MASK) +#define HDFGRTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGRTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGRTR_EL2_TRCSEQSTR_SHIFT 45 +#define HDFGRTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGRTR_EL2_TRCSEQSTR_VAL(x) ((x) & HDFGRTR_EL2_TRCSEQSTR_MASK) +#define HDFGRTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGRTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGRTR_EL2_TRCPRGCTLR_SHIFT 44 +#define HDFGRTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGRTR_EL2_TRCPRGCTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCPRGCTLR_MASK) +#define HDFGRTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGRTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGRTR_EL2_TRCOSLSR_SHIFT 43 +#define HDFGRTR_EL2_TRCOSLSR_MASK (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT) +#define HDFGRTR_EL2_TRCOSLSR_VAL(x) ((x) & HDFGRTR_EL2_TRCOSLSR_MASK) +#define HDFGRTR_EL2_TRCOSLSR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCOSLSR_SHIFT) +#define HDFGRTR_EL2_TRCOSLSR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT) +#define HDFGRTR_EL2_TRCIMSPECn_SHIFT 41 +#define HDFGRTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGRTR_EL2_TRCIMSPECn_VAL(x) ((x) & HDFGRTR_EL2_TRCIMSPECn_MASK) +#define HDFGRTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGRTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGRTR_EL2_TRCID_SHIFT 40 +#define HDFGRTR_EL2_TRCID_MASK (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT) +#define HDFGRTR_EL2_TRCID_VAL(x) ((x) & HDFGRTR_EL2_TRCID_MASK) +#define HDFGRTR_EL2_TRCID_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCID_SHIFT) +#define HDFGRTR_EL2_TRCID_TRAP (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT) +#define HDFGRTR_EL2_TRCCNTVRn_SHIFT 37 +#define HDFGRTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGRTR_EL2_TRCCNTVRn_VAL(x) ((x) & HDFGRTR_EL2_TRCCNTVRn_MASK) +#define HDFGRTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGRTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGRTR_EL2_TRCCLAIM_SHIFT 36 +#define HDFGRTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT) +#define HDFGRTR_EL2_TRCCLAIM_VAL(x) ((x) & HDFGRTR_EL2_TRCCLAIM_MASK) +#define HDFGRTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCLAIM_SHIFT) +#define HDFGRTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT) +#define HDFGRTR_EL2_TRCAUXCTLR_SHIFT 35 +#define HDFGRTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGRTR_EL2_TRCAUXCTLR_VAL(x) ((x) & HDFGRTR_EL2_TRCAUXCTLR_MASK) +#define HDFGRTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGRTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT 34 +#define HDFGRTR_EL2_TRCAUTHSTATUS_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) +#define HDFGRTR_EL2_TRCAUTHSTATUS_VAL(x) ((x) & HDFGRTR_EL2_TRCAUTHSTATUS_MASK) +#define HDFGRTR_EL2_TRCAUTHSTATUS_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) +#define HDFGRTR_EL2_TRCAUTHSTATUS_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT) +#define HDFGRTR_EL2_TRC_SHIFT 33 +#define HDFGRTR_EL2_TRC_MASK (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT) +#define HDFGRTR_EL2_TRC_VAL(x) ((x) & HDFGRTR_EL2_TRC_MASK) +#define HDFGRTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRC_SHIFT) +#define HDFGRTR_EL2_TRC_TRAP (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT) +#define HDFGRTR_EL2_PMSLATFR_EL1_SHIFT 32 +#define HDFGRTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSLATFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSLATFR_EL1_MASK) +#define HDFGRTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIRR_EL1_SHIFT 31 +#define HDFGRTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIRR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSIRR_EL1_MASK) +#define HDFGRTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIDR_EL1_SHIFT 30 +#define HDFGRTR_EL2_PMSIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIDR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSIDR_EL1_MASK) +#define HDFGRTR_EL2_PMSIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSICR_EL1_SHIFT 29 +#define HDFGRTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSICR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSICR_EL1_MASK) +#define HDFGRTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSFCR_EL1_SHIFT 28 +#define HDFGRTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSFCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSFCR_EL1_MASK) +#define HDFGRTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSEVFR_EL1_SHIFT 27 +#define HDFGRTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSEVFR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSEVFR_EL1_MASK) +#define HDFGRTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSCR_EL1_SHIFT 26 +#define HDFGRTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMSCR_EL1_MASK) +#define HDFGRTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBSR_EL1_SHIFT 25 +#define HDFGRTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBSR_EL1_MASK) +#define HDFGRTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBPTR_EL1_SHIFT 24 +#define HDFGRTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBPTR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBPTR_EL1_MASK) +#define HDFGRTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT 23 +#define HDFGRTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBLIMITR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMBLIMITR_EL1_MASK) +#define HDFGRTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGRTR_EL2_PMMIR_EL1_SHIFT 22 +#define HDFGRTR_EL2_PMMIR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) +#define HDFGRTR_EL2_PMMIR_EL1_VAL(x) ((x) & HDFGRTR_EL2_PMMIR_EL1_MASK) +#define HDFGRTR_EL2_PMMIR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) +#define HDFGRTR_EL2_PMMIR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT) +#define HDFGRTR_EL2_PMSELR_EL0_SHIFT 19 +#define HDFGRTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGRTR_EL2_PMSELR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMSELR_EL0_MASK) +#define HDFGRTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGRTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGRTR_EL2_PMOVS_SHIFT 18 +#define HDFGRTR_EL2_PMOVS_MASK (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT) +#define HDFGRTR_EL2_PMOVS_VAL(x) ((x) & HDFGRTR_EL2_PMOVS_MASK) +#define HDFGRTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMOVS_SHIFT) +#define HDFGRTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT) +#define HDFGRTR_EL2_PMINTEN_SHIFT 17 +#define HDFGRTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT) +#define HDFGRTR_EL2_PMINTEN_VAL(x) ((x) & HDFGRTR_EL2_PMINTEN_MASK) +#define HDFGRTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMINTEN_SHIFT) +#define HDFGRTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT) +#define HDFGRTR_EL2_PMCNTEN_SHIFT 16 +#define HDFGRTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT) +#define HDFGRTR_EL2_PMCNTEN_VAL(x) ((x) & HDFGRTR_EL2_PMCNTEN_MASK) +#define HDFGRTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCNTEN_SHIFT) +#define HDFGRTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT) +#define HDFGRTR_EL2_PMCCNTR_EL0_SHIFT 15 +#define HDFGRTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMCCNTR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCCNTR_EL0_MASK) +#define HDFGRTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT 14 +#define HDFGRTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMCCFILTR_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMCCFILTR_EL0_MASK) +#define HDFGRTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT 13 +#define HDFGRTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVTYPERn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMEVTYPERn_EL0_MASK) +#define HDFGRTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT 12 +#define HDFGRTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVCNTRn_EL0_VAL(x) ((x) & HDFGRTR_EL2_PMEVCNTRn_EL0_MASK) +#define HDFGRTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGRTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGRTR_EL2_OSDLR_EL1_SHIFT 11 +#define HDFGRTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGRTR_EL2_OSDLR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSDLR_EL1_MASK) +#define HDFGRTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGRTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGRTR_EL2_OSECCR_EL1_SHIFT 10 +#define HDFGRTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGRTR_EL2_OSECCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSECCR_EL1_MASK) +#define HDFGRTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGRTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGRTR_EL2_OSLSR_EL1_SHIFT 9 +#define HDFGRTR_EL2_OSLSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) +#define HDFGRTR_EL2_OSLSR_EL1_VAL(x) ((x) & HDFGRTR_EL2_OSLSR_EL1_MASK) +#define HDFGRTR_EL2_OSLSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) +#define HDFGRTR_EL2_OSLSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT) +#define HDFGRTR_EL2_DBGPRCR_EL1_SHIFT 7 +#define HDFGRTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGRTR_EL2_DBGPRCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGPRCR_EL1_MASK) +#define HDFGRTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGRTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT 6 +#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) +#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK) +#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) +#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT) +#define HDFGRTR_EL2_DBGCLAIM_SHIFT 5 +#define HDFGRTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT) +#define HDFGRTR_EL2_DBGCLAIM_VAL(x) ((x) & HDFGRTR_EL2_DBGCLAIM_MASK) +#define HDFGRTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGCLAIM_SHIFT) +#define HDFGRTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT) +#define HDFGRTR_EL2_MDSCR_EL1_SHIFT 4 +#define HDFGRTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGRTR_EL2_MDSCR_EL1_VAL(x) ((x) & HDFGRTR_EL2_MDSCR_EL1_MASK) +#define HDFGRTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGRTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWVRn_EL1_SHIFT 3 +#define HDFGRTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWVRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGWVRn_EL1_MASK) +#define HDFGRTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWCRn_EL1_SHIFT 2 +#define HDFGRTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWCRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGWCRn_EL1_MASK) +#define HDFGRTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBVRn_EL1_SHIFT 1 +#define HDFGRTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBVRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGBVRn_EL1_MASK) +#define HDFGRTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBCRn_EL1_SHIFT 0 +#define HDFGRTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBCRn_EL1_VAL(x) ((x) & HDFGRTR_EL2_DBGBCRn_EL1_MASK) +#define HDFGRTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) +#define HDFGRTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT) + +/* HDFGWTR2_EL2 */ +#define HDFGWTR2_EL2_REG MRS_REG_ALT_NAME(HDFGWTR2_EL2) +#define HDFGWTR2_EL2_op0 3 +#define HDFGWTR2_EL2_op1 4 +#define HDFGWTR2_EL2_CRn 3 +#define HDFGWTR2_EL2_CRm 1 +#define HDFGWTR2_EL2_op2 1 +#define HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT 23 +#define HDFGWTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGWTR2_EL2_nMDSTEPOP_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nMDSTEPOP_EL1_MASK) +#define HDFGWTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGWTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT) +#define HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT 22 +#define HDFGWTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGWTR2_EL2_nTRBMPAM_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nTRBMPAM_EL1_MASK) +#define HDFGWTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGWTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMZR_EL0_SHIFT 21 +#define HDFGWTR2_EL2_nPMZR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMZR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMZR_EL0_MASK) +#define HDFGWTR2_EL2_nPMZR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMZR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT) +#define HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT 20 +#define HDFGWTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGWTR2_EL2_nTRCITECR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nTRCITECR_EL1_MASK) +#define HDFGWTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGWTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT 19 +#define HDFGWTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMSDSFR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMSDSFR_EL1_MASK) +#define HDFGWTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT 16 +#define HDFGWTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMSCR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nSPMSCR_EL1_MASK) +#define HDFGWTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT 15 +#define HDFGWTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMACCESSR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nSPMACCESSR_EL1_MASK) +#define HDFGWTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT) +#define HDFGWTR2_EL2_nSPMCR_EL0_SHIFT 14 +#define HDFGWTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMCR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMCR_EL0_MASK) +#define HDFGWTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMOVS_SHIFT 13 +#define HDFGWTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT) +#define HDFGWTR2_EL2_nSPMOVS_VAL(x) ((x) & HDFGWTR2_EL2_nSPMOVS_MASK) +#define HDFGWTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMOVS_SHIFT) +#define HDFGWTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT) +#define HDFGWTR2_EL2_nSPMINTEN_SHIFT 12 +#define HDFGWTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMINTEN_VAL(x) ((x) & HDFGWTR2_EL2_nSPMINTEN_MASK) +#define HDFGWTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMCNTEN_SHIFT 11 +#define HDFGWTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMCNTEN_VAL(x) ((x) & HDFGWTR2_EL2_nSPMCNTEN_MASK) +#define HDFGWTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT) +#define HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT 10 +#define HDFGWTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMSELR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMSELR_EL0_MASK) +#define HDFGWTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT 9 +#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMEVTYPERn_EL0_MASK) +#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT 8 +#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nSPMEVCNTRn_EL0_MASK) +#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT 7 +#define HDFGWTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMSSCR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMSSCR_EL1_MASK) +#define HDFGWTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT) +#define HDFGWTR2_EL2_nMDSELR_EL1_SHIFT 5 +#define HDFGWTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGWTR2_EL2_nMDSELR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nMDSELR_EL1_MASK) +#define HDFGWTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGWTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMUACR_EL1_SHIFT 4 +#define HDFGWTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMUACR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMUACR_EL1_MASK) +#define HDFGWTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT 3 +#define HDFGWTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMICFILTR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMICFILTR_EL0_MASK) +#define HDFGWTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT 2 +#define HDFGWTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMICNTR_EL0_VAL(x) ((x) & HDFGWTR2_EL2_nPMICNTR_EL0_MASK) +#define HDFGWTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT) +#define HDFGWTR2_EL2_nPMIAR_EL1_SHIFT 1 +#define HDFGWTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMIAR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMIAR_EL1_MASK) +#define HDFGWTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMECR_EL1_SHIFT 0 +#define HDFGWTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMECR_EL1_VAL(x) ((x) & HDFGWTR2_EL2_nPMECR_EL1_MASK) +#define HDFGWTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) +#define HDFGWTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT) + +/* HDFGWTR_EL2 */ +#define HDFGWTR_EL2_REG MRS_REG_ALT_NAME(HDFGWTR_EL2) +#define HDFGWTR_EL2_op0 3 +#define HDFGWTR_EL2_op1 4 +#define HDFGWTR_EL2_CRn 3 +#define HDFGWTR_EL2_CRm 1 +#define HDFGWTR_EL2_op2 5 +#define HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT 62 +#define HDFGWTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_nPMSNEVFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_nPMSNEVFR_EL1_MASK) +#define HDFGWTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_nBRBDATA_SHIFT 61 +#define HDFGWTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT) +#define HDFGWTR_EL2_nBRBDATA_VAL(x) ((x) & HDFGWTR_EL2_nBRBDATA_MASK) +#define HDFGWTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBDATA_SHIFT) +#define HDFGWTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT) +#define HDFGWTR_EL2_nBRBCTL_SHIFT 60 +#define HDFGWTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT) +#define HDFGWTR_EL2_nBRBCTL_VAL(x) ((x) & HDFGWTR_EL2_nBRBCTL_MASK) +#define HDFGWTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBCTL_SHIFT) +#define HDFGWTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT) +#define HDFGWTR_EL2_PMUSERENR_EL0_SHIFT 57 +#define HDFGWTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGWTR_EL2_PMUSERENR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMUSERENR_EL0_MASK) +#define HDFGWTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGWTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT) +#define HDFGWTR_EL2_TRBTRG_EL1_SHIFT 56 +#define HDFGWTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGWTR_EL2_TRBTRG_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBTRG_EL1_MASK) +#define HDFGWTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGWTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT) +#define HDFGWTR_EL2_TRBSR_EL1_SHIFT 55 +#define HDFGWTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBSR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBSR_EL1_MASK) +#define HDFGWTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBPTR_EL1_SHIFT 54 +#define HDFGWTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBPTR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBPTR_EL1_MASK) +#define HDFGWTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBMAR_EL1_SHIFT 53 +#define HDFGWTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBMAR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBMAR_EL1_MASK) +#define HDFGWTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT 52 +#define HDFGWTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBLIMITR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBLIMITR_EL1_MASK) +#define HDFGWTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_TRBBASER_EL1_SHIFT 50 +#define HDFGWTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGWTR_EL2_TRBBASER_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRBBASER_EL1_MASK) +#define HDFGWTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGWTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT) +#define HDFGWTR_EL2_TRFCR_EL1_SHIFT 49 +#define HDFGWTR_EL2_TRFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) +#define HDFGWTR_EL2_TRFCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_TRFCR_EL1_MASK) +#define HDFGWTR_EL2_TRFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) +#define HDFGWTR_EL2_TRFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT) +#define HDFGWTR_EL2_TRCVICTLR_SHIFT 48 +#define HDFGWTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT) +#define HDFGWTR_EL2_TRCVICTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCVICTLR_MASK) +#define HDFGWTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCVICTLR_SHIFT) +#define HDFGWTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT) +#define HDFGWTR_EL2_TRCSSCSRn_SHIFT 46 +#define HDFGWTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGWTR_EL2_TRCSSCSRn_VAL(x) ((x) & HDFGWTR_EL2_TRCSSCSRn_MASK) +#define HDFGWTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGWTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT) +#define HDFGWTR_EL2_TRCSEQSTR_SHIFT 45 +#define HDFGWTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGWTR_EL2_TRCSEQSTR_VAL(x) ((x) & HDFGWTR_EL2_TRCSEQSTR_MASK) +#define HDFGWTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGWTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT) +#define HDFGWTR_EL2_TRCPRGCTLR_SHIFT 44 +#define HDFGWTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGWTR_EL2_TRCPRGCTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCPRGCTLR_MASK) +#define HDFGWTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGWTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT) +#define HDFGWTR_EL2_TRCOSLAR_SHIFT 42 +#define HDFGWTR_EL2_TRCOSLAR_MASK (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT) +#define HDFGWTR_EL2_TRCOSLAR_VAL(x) ((x) & HDFGWTR_EL2_TRCOSLAR_MASK) +#define HDFGWTR_EL2_TRCOSLAR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCOSLAR_SHIFT) +#define HDFGWTR_EL2_TRCOSLAR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT) +#define HDFGWTR_EL2_TRCIMSPECn_SHIFT 41 +#define HDFGWTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGWTR_EL2_TRCIMSPECn_VAL(x) ((x) & HDFGWTR_EL2_TRCIMSPECn_MASK) +#define HDFGWTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGWTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT) +#define HDFGWTR_EL2_TRCCNTVRn_SHIFT 37 +#define HDFGWTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGWTR_EL2_TRCCNTVRn_VAL(x) ((x) & HDFGWTR_EL2_TRCCNTVRn_MASK) +#define HDFGWTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGWTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT) +#define HDFGWTR_EL2_TRCCLAIM_SHIFT 36 +#define HDFGWTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT) +#define HDFGWTR_EL2_TRCCLAIM_VAL(x) ((x) & HDFGWTR_EL2_TRCCLAIM_MASK) +#define HDFGWTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCLAIM_SHIFT) +#define HDFGWTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT) +#define HDFGWTR_EL2_TRCAUXCTLR_SHIFT 35 +#define HDFGWTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGWTR_EL2_TRCAUXCTLR_VAL(x) ((x) & HDFGWTR_EL2_TRCAUXCTLR_MASK) +#define HDFGWTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGWTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT) +#define HDFGWTR_EL2_TRC_SHIFT 33 +#define HDFGWTR_EL2_TRC_MASK (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT) +#define HDFGWTR_EL2_TRC_VAL(x) ((x) & HDFGWTR_EL2_TRC_MASK) +#define HDFGWTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRC_SHIFT) +#define HDFGWTR_EL2_TRC_TRAP (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT) +#define HDFGWTR_EL2_PMSLATFR_EL1_SHIFT 32 +#define HDFGWTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSLATFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSLATFR_EL1_MASK) +#define HDFGWTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSIRR_EL1_SHIFT 31 +#define HDFGWTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSIRR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSIRR_EL1_MASK) +#define HDFGWTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSICR_EL1_SHIFT 29 +#define HDFGWTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSICR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSICR_EL1_MASK) +#define HDFGWTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSFCR_EL1_SHIFT 28 +#define HDFGWTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSFCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSFCR_EL1_MASK) +#define HDFGWTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSEVFR_EL1_SHIFT 27 +#define HDFGWTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSEVFR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSEVFR_EL1_MASK) +#define HDFGWTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSCR_EL1_SHIFT 26 +#define HDFGWTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMSCR_EL1_MASK) +#define HDFGWTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBSR_EL1_SHIFT 25 +#define HDFGWTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBSR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBSR_EL1_MASK) +#define HDFGWTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBPTR_EL1_SHIFT 24 +#define HDFGWTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBPTR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBPTR_EL1_MASK) +#define HDFGWTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT 23 +#define HDFGWTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBLIMITR_EL1_VAL(x) ((x) & HDFGWTR_EL2_PMBLIMITR_EL1_MASK) +#define HDFGWTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT) +#define HDFGWTR_EL2_PMCR_EL0_SHIFT 21 +#define HDFGWTR_EL2_PMCR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCR_EL0_MASK) +#define HDFGWTR_EL2_PMCR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT) +#define HDFGWTR_EL2_PMSWINC_EL0_SHIFT 20 +#define HDFGWTR_EL2_PMSWINC_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) +#define HDFGWTR_EL2_PMSWINC_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMSWINC_EL0_MASK) +#define HDFGWTR_EL2_PMSWINC_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) +#define HDFGWTR_EL2_PMSWINC_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT) +#define HDFGWTR_EL2_PMSELR_EL0_SHIFT 19 +#define HDFGWTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGWTR_EL2_PMSELR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMSELR_EL0_MASK) +#define HDFGWTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGWTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT) +#define HDFGWTR_EL2_PMOVS_SHIFT 18 +#define HDFGWTR_EL2_PMOVS_MASK (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT) +#define HDFGWTR_EL2_PMOVS_VAL(x) ((x) & HDFGWTR_EL2_PMOVS_MASK) +#define HDFGWTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMOVS_SHIFT) +#define HDFGWTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT) +#define HDFGWTR_EL2_PMINTEN_SHIFT 17 +#define HDFGWTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT) +#define HDFGWTR_EL2_PMINTEN_VAL(x) ((x) & HDFGWTR_EL2_PMINTEN_MASK) +#define HDFGWTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMINTEN_SHIFT) +#define HDFGWTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT) +#define HDFGWTR_EL2_PMCNTEN_SHIFT 16 +#define HDFGWTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT) +#define HDFGWTR_EL2_PMCNTEN_VAL(x) ((x) & HDFGWTR_EL2_PMCNTEN_MASK) +#define HDFGWTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCNTEN_SHIFT) +#define HDFGWTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT) +#define HDFGWTR_EL2_PMCCNTR_EL0_SHIFT 15 +#define HDFGWTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCCNTR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCCNTR_EL0_MASK) +#define HDFGWTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT 14 +#define HDFGWTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCCFILTR_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMCCFILTR_EL0_MASK) +#define HDFGWTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT 13 +#define HDFGWTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVTYPERn_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMEVTYPERn_EL0_MASK) +#define HDFGWTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT 12 +#define HDFGWTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVCNTRn_EL0_VAL(x) ((x) & HDFGWTR_EL2_PMEVCNTRn_EL0_MASK) +#define HDFGWTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGWTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT) +#define HDFGWTR_EL2_OSDLR_EL1_SHIFT 11 +#define HDFGWTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGWTR_EL2_OSDLR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSDLR_EL1_MASK) +#define HDFGWTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGWTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT) +#define HDFGWTR_EL2_OSECCR_EL1_SHIFT 10 +#define HDFGWTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGWTR_EL2_OSECCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSECCR_EL1_MASK) +#define HDFGWTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGWTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT) +#define HDFGWTR_EL2_OSLAR_EL1_SHIFT 8 +#define HDFGWTR_EL2_OSLAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) +#define HDFGWTR_EL2_OSLAR_EL1_VAL(x) ((x) & HDFGWTR_EL2_OSLAR_EL1_MASK) +#define HDFGWTR_EL2_OSLAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) +#define HDFGWTR_EL2_OSLAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT) +#define HDFGWTR_EL2_DBGPRCR_EL1_SHIFT 7 +#define HDFGWTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGWTR_EL2_DBGPRCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGPRCR_EL1_MASK) +#define HDFGWTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGWTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT) +#define HDFGWTR_EL2_DBGCLAIM_SHIFT 5 +#define HDFGWTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT) +#define HDFGWTR_EL2_DBGCLAIM_VAL(x) ((x) & HDFGWTR_EL2_DBGCLAIM_MASK) +#define HDFGWTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGCLAIM_SHIFT) +#define HDFGWTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT) +#define HDFGWTR_EL2_MDSCR_EL1_SHIFT 4 +#define HDFGWTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGWTR_EL2_MDSCR_EL1_VAL(x) ((x) & HDFGWTR_EL2_MDSCR_EL1_MASK) +#define HDFGWTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGWTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWVRn_EL1_SHIFT 3 +#define HDFGWTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWVRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGWVRn_EL1_MASK) +#define HDFGWTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWCRn_EL1_SHIFT 2 +#define HDFGWTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWCRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGWCRn_EL1_MASK) +#define HDFGWTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBVRn_EL1_SHIFT 1 +#define HDFGWTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBVRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGBVRn_EL1_MASK) +#define HDFGWTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBCRn_EL1_SHIFT 0 +#define HDFGWTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBCRn_EL1_VAL(x) ((x) & HDFGWTR_EL2_DBGBCRn_EL1_MASK) +#define HDFGWTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) +#define HDFGWTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT) + +/* HFGITR2_EL2 */ +#define HFGITR2_EL2_REG MRS_REG_ALT_NAME(HFGITR2_EL2) +#define HFGITR2_EL2_op0 3 +#define HFGITR2_EL2_op1 4 +#define HFGITR2_EL2_CRn 3 +#define HFGITR2_EL2_CRm 1 +#define HFGITR2_EL2_op2 7 + +/* HFGITR_EL2 */ +#define HFGITR_EL2_REG MRS_REG_ALT_NAME(HFGITR_EL2) +#define HFGITR_EL2_op0 3 +#define HFGITR_EL2_op1 4 +#define HFGITR_EL2_CRn 1 +#define HFGITR_EL2_CRm 1 +#define HFGITR_EL2_op2 6 +#define HFGITR_EL2_ATS1E1A_SHIFT 62 +#define HFGITR_EL2_ATS1E1A_MASK (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT) +#define HFGITR_EL2_ATS1E1A_VAL(x) ((x) & HFGITR_EL2_ATS1E1A_MASK) +#define HFGITR_EL2_ATS1E1A_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1A_SHIFT) +#define HFGITR_EL2_ATS1E1A_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT) +#define HFGITR_EL2_COSPRCTX_SHIFT 60 +#define HFGITR_EL2_COSPRCTX_MASK (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT) +#define HFGITR_EL2_COSPRCTX_VAL(x) ((x) & HFGITR_EL2_COSPRCTX_MASK) +#define HFGITR_EL2_COSPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_COSPRCTX_SHIFT) +#define HFGITR_EL2_COSPRCTX_TRAP (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT) +#define HFGITR_EL2_nGCSEPP_SHIFT 59 +#define HFGITR_EL2_nGCSEPP_MASK (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT) +#define HFGITR_EL2_nGCSEPP_VAL(x) ((x) & HFGITR_EL2_nGCSEPP_MASK) +#define HFGITR_EL2_nGCSEPP_TRAP (UL(0x0) << HFGITR_EL2_nGCSEPP_SHIFT) +#define HFGITR_EL2_nGCSEPP_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT) +#define HFGITR_EL2_nGCSSTR_EL1_SHIFT 58 +#define HFGITR_EL2_nGCSSTR_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) +#define HFGITR_EL2_nGCSSTR_EL1_VAL(x) ((x) & HFGITR_EL2_nGCSSTR_EL1_MASK) +#define HFGITR_EL2_nGCSSTR_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) +#define HFGITR_EL2_nGCSSTR_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT) +#define HFGITR_EL2_nGCSPUSHM_EL1_SHIFT 57 +#define HFGITR_EL2_nGCSPUSHM_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) +#define HFGITR_EL2_nGCSPUSHM_EL1_VAL(x) ((x) & HFGITR_EL2_nGCSPUSHM_EL1_MASK) +#define HFGITR_EL2_nGCSPUSHM_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) +#define HFGITR_EL2_nGCSPUSHM_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT) +#define HFGITR_EL2_nBRBIALL_SHIFT 56 +#define HFGITR_EL2_nBRBIALL_MASK (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT) +#define HFGITR_EL2_nBRBIALL_VAL(x) ((x) & HFGITR_EL2_nBRBIALL_MASK) +#define HFGITR_EL2_nBRBIALL_TRAP (UL(0x0) << HFGITR_EL2_nBRBIALL_SHIFT) +#define HFGITR_EL2_nBRBIALL_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT) +#define HFGITR_EL2_nBRBINJ_SHIFT 55 +#define HFGITR_EL2_nBRBINJ_MASK (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT) +#define HFGITR_EL2_nBRBINJ_VAL(x) ((x) & HFGITR_EL2_nBRBINJ_MASK) +#define HFGITR_EL2_nBRBINJ_TRAP (UL(0x0) << HFGITR_EL2_nBRBINJ_SHIFT) +#define HFGITR_EL2_nBRBINJ_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT) +#define HFGITR_EL2_DCCVAC_SHIFT 54 +#define HFGITR_EL2_DCCVAC_MASK (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT) +#define HFGITR_EL2_DCCVAC_VAL(x) ((x) & HFGITR_EL2_DCCVAC_MASK) +#define HFGITR_EL2_DCCVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAC_SHIFT) +#define HFGITR_EL2_DCCVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT) +#define HFGITR_EL2_SVC_EL1_SHIFT 53 +#define HFGITR_EL2_SVC_EL1_MASK (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT) +#define HFGITR_EL2_SVC_EL1_VAL(x) ((x) & HFGITR_EL2_SVC_EL1_MASK) +#define HFGITR_EL2_SVC_EL1_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL1_SHIFT) +#define HFGITR_EL2_SVC_EL1_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT) +#define HFGITR_EL2_SVC_EL0_SHIFT 52 +#define HFGITR_EL2_SVC_EL0_MASK (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT) +#define HFGITR_EL2_SVC_EL0_VAL(x) ((x) & HFGITR_EL2_SVC_EL0_MASK) +#define HFGITR_EL2_SVC_EL0_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL0_SHIFT) +#define HFGITR_EL2_SVC_EL0_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT) +#define HFGITR_EL2_ERET_SHIFT 51 +#define HFGITR_EL2_ERET_MASK (UL(0x1) << HFGITR_EL2_ERET_SHIFT) +#define HFGITR_EL2_ERET_VAL(x) ((x) & HFGITR_EL2_ERET_MASK) +#define HFGITR_EL2_ERET_NOTRAP (UL(0x0) << HFGITR_EL2_ERET_SHIFT) +#define HFGITR_EL2_ERET_TRAP (UL(0x1) << HFGITR_EL2_ERET_SHIFT) +#define HFGITR_EL2_CPPRCTX_SHIFT 50 +#define HFGITR_EL2_CPPRCTX_MASK (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT) +#define HFGITR_EL2_CPPRCTX_VAL(x) ((x) & HFGITR_EL2_CPPRCTX_MASK) +#define HFGITR_EL2_CPPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CPPRCTX_SHIFT) +#define HFGITR_EL2_CPPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT) +#define HFGITR_EL2_DVPRCTX_SHIFT 49 +#define HFGITR_EL2_DVPRCTX_MASK (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT) +#define HFGITR_EL2_DVPRCTX_VAL(x) ((x) & HFGITR_EL2_DVPRCTX_MASK) +#define HFGITR_EL2_DVPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_DVPRCTX_SHIFT) +#define HFGITR_EL2_DVPRCTX_TRAP (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT) +#define HFGITR_EL2_CFPRCTX_SHIFT 48 +#define HFGITR_EL2_CFPRCTX_MASK (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT) +#define HFGITR_EL2_CFPRCTX_VAL(x) ((x) & HFGITR_EL2_CFPRCTX_MASK) +#define HFGITR_EL2_CFPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CFPRCTX_SHIFT) +#define HFGITR_EL2_CFPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT) +#define HFGITR_EL2_TLBIVAALE1_SHIFT 47 +#define HFGITR_EL2_TLBIVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT) +#define HFGITR_EL2_TLBIVAALE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1_MASK) +#define HFGITR_EL2_TLBIVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1_SHIFT) +#define HFGITR_EL2_TLBIVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT) +#define HFGITR_EL2_TLBIVALE1_SHIFT 46 +#define HFGITR_EL2_TLBIVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT) +#define HFGITR_EL2_TLBIVALE1_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1_MASK) +#define HFGITR_EL2_TLBIVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1_SHIFT) +#define HFGITR_EL2_TLBIVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT) +#define HFGITR_EL2_TLBIVAAE1_SHIFT 45 +#define HFGITR_EL2_TLBIVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT) +#define HFGITR_EL2_TLBIVAAE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1_MASK) +#define HFGITR_EL2_TLBIVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1_SHIFT) +#define HFGITR_EL2_TLBIVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT) +#define HFGITR_EL2_TLBIASIDE1_SHIFT 44 +#define HFGITR_EL2_TLBIASIDE1_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT) +#define HFGITR_EL2_TLBIASIDE1_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1_MASK) +#define HFGITR_EL2_TLBIASIDE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1_SHIFT) +#define HFGITR_EL2_TLBIASIDE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT) +#define HFGITR_EL2_TLBIVAE1_SHIFT 43 +#define HFGITR_EL2_TLBIVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT) +#define HFGITR_EL2_TLBIVAE1_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1_MASK) +#define HFGITR_EL2_TLBIVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1_SHIFT) +#define HFGITR_EL2_TLBIVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1_SHIFT 42 +#define HFGITR_EL2_TLBIVMALLE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1_MASK) +#define HFGITR_EL2_TLBIVMALLE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1_SHIFT 41 +#define HFGITR_EL2_TLBIRVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1_MASK) +#define HFGITR_EL2_TLBIRVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT) +#define HFGITR_EL2_TLBIRVALE1_SHIFT 40 +#define HFGITR_EL2_TLBIRVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT) +#define HFGITR_EL2_TLBIRVALE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1_MASK) +#define HFGITR_EL2_TLBIRVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1_SHIFT) +#define HFGITR_EL2_TLBIRVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1_SHIFT 39 +#define HFGITR_EL2_TLBIRVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1_MASK) +#define HFGITR_EL2_TLBIRVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAE1_SHIFT 38 +#define HFGITR_EL2_TLBIRVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAE1_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1_MASK) +#define HFGITR_EL2_TLBIRVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1IS_SHIFT 37 +#define HFGITR_EL2_TLBIRVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1IS_MASK) +#define HFGITR_EL2_TLBIRVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1IS_SHIFT 36 +#define HFGITR_EL2_TLBIRVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1IS_MASK) +#define HFGITR_EL2_TLBIRVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1IS_SHIFT 35 +#define HFGITR_EL2_TLBIRVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1IS_MASK) +#define HFGITR_EL2_TLBIRVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1IS_SHIFT 34 +#define HFGITR_EL2_TLBIRVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1IS_MASK) +#define HFGITR_EL2_TLBIRVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1IS_SHIFT 33 +#define HFGITR_EL2_TLBIVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1IS_MASK) +#define HFGITR_EL2_TLBIVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVALE1IS_SHIFT 32 +#define HFGITR_EL2_TLBIVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVALE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1IS_MASK) +#define HFGITR_EL2_TLBIVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1IS_SHIFT 31 +#define HFGITR_EL2_TLBIVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1IS_MASK) +#define HFGITR_EL2_TLBIVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1IS_SHIFT 30 +#define HFGITR_EL2_TLBIASIDE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1IS_MASK) +#define HFGITR_EL2_TLBIASIDE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAE1IS_SHIFT 29 +#define HFGITR_EL2_TLBIVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1IS_MASK) +#define HFGITR_EL2_TLBIVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1IS_SHIFT 28 +#define HFGITR_EL2_TLBIVMALLE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1IS_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1IS_MASK) +#define HFGITR_EL2_TLBIVMALLE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1OS_SHIFT 27 +#define HFGITR_EL2_TLBIRVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAALE1OS_MASK) +#define HFGITR_EL2_TLBIRVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1OS_SHIFT 26 +#define HFGITR_EL2_TLBIRVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVALE1OS_MASK) +#define HFGITR_EL2_TLBIRVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1OS_SHIFT 25 +#define HFGITR_EL2_TLBIRVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAAE1OS_MASK) +#define HFGITR_EL2_TLBIRVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1OS_SHIFT 24 +#define HFGITR_EL2_TLBIRVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIRVAE1OS_MASK) +#define HFGITR_EL2_TLBIRVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIRVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1OS_SHIFT 23 +#define HFGITR_EL2_TLBIVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAALE1OS_MASK) +#define HFGITR_EL2_TLBIVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVALE1OS_SHIFT 22 +#define HFGITR_EL2_TLBIVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVALE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVALE1OS_MASK) +#define HFGITR_EL2_TLBIVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1OS_SHIFT 21 +#define HFGITR_EL2_TLBIVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAAE1OS_MASK) +#define HFGITR_EL2_TLBIVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1OS_SHIFT 20 +#define HFGITR_EL2_TLBIASIDE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIASIDE1OS_MASK) +#define HFGITR_EL2_TLBIASIDE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) +#define HFGITR_EL2_TLBIASIDE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAE1OS_SHIFT 19 +#define HFGITR_EL2_TLBIVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVAE1OS_MASK) +#define HFGITR_EL2_TLBIVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1OS_SHIFT 18 +#define HFGITR_EL2_TLBIVMALLE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1OS_VAL(x) ((x) & HFGITR_EL2_TLBIVMALLE1OS_MASK) +#define HFGITR_EL2_TLBIVMALLE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) +#define HFGITR_EL2_TLBIVMALLE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT) +#define HFGITR_EL2_ATS1E1WP_SHIFT 17 +#define HFGITR_EL2_ATS1E1WP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT) +#define HFGITR_EL2_ATS1E1WP_VAL(x) ((x) & HFGITR_EL2_ATS1E1WP_MASK) +#define HFGITR_EL2_ATS1E1WP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1WP_SHIFT) +#define HFGITR_EL2_ATS1E1WP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT) +#define HFGITR_EL2_ATS1E1RP_SHIFT 16 +#define HFGITR_EL2_ATS1E1RP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT) +#define HFGITR_EL2_ATS1E1RP_VAL(x) ((x) & HFGITR_EL2_ATS1E1RP_MASK) +#define HFGITR_EL2_ATS1E1RP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1RP_SHIFT) +#define HFGITR_EL2_ATS1E1RP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT) +#define HFGITR_EL2_ATS1E0W_SHIFT 15 +#define HFGITR_EL2_ATS1E0W_MASK (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT) +#define HFGITR_EL2_ATS1E0W_VAL(x) ((x) & HFGITR_EL2_ATS1E0W_MASK) +#define HFGITR_EL2_ATS1E0W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0W_SHIFT) +#define HFGITR_EL2_ATS1E0W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT) +#define HFGITR_EL2_ATS1E0R_SHIFT 14 +#define HFGITR_EL2_ATS1E0R_MASK (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT) +#define HFGITR_EL2_ATS1E0R_VAL(x) ((x) & HFGITR_EL2_ATS1E0R_MASK) +#define HFGITR_EL2_ATS1E0R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0R_SHIFT) +#define HFGITR_EL2_ATS1E0R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT) +#define HFGITR_EL2_ATS1E1W_SHIFT 13 +#define HFGITR_EL2_ATS1E1W_MASK (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT) +#define HFGITR_EL2_ATS1E1W_VAL(x) ((x) & HFGITR_EL2_ATS1E1W_MASK) +#define HFGITR_EL2_ATS1E1W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1W_SHIFT) +#define HFGITR_EL2_ATS1E1W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT) +#define HFGITR_EL2_ATS1E1R_SHIFT 12 +#define HFGITR_EL2_ATS1E1R_MASK (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT) +#define HFGITR_EL2_ATS1E1R_VAL(x) ((x) & HFGITR_EL2_ATS1E1R_MASK) +#define HFGITR_EL2_ATS1E1R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1R_SHIFT) +#define HFGITR_EL2_ATS1E1R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT) +#define HFGITR_EL2_DCZVA_SHIFT 11 +#define HFGITR_EL2_DCZVA_MASK (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT) +#define HFGITR_EL2_DCZVA_VAL(x) ((x) & HFGITR_EL2_DCZVA_MASK) +#define HFGITR_EL2_DCZVA_NOTRAP (UL(0x0) << HFGITR_EL2_DCZVA_SHIFT) +#define HFGITR_EL2_DCZVA_TRAP (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT) +#define HFGITR_EL2_DCCIVAC_SHIFT 10 +#define HFGITR_EL2_DCCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT) +#define HFGITR_EL2_DCCIVAC_VAL(x) ((x) & HFGITR_EL2_DCCIVAC_MASK) +#define HFGITR_EL2_DCCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCIVAC_SHIFT) +#define HFGITR_EL2_DCCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT) +#define HFGITR_EL2_DCCVADP_SHIFT 9 +#define HFGITR_EL2_DCCVADP_MASK (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT) +#define HFGITR_EL2_DCCVADP_VAL(x) ((x) & HFGITR_EL2_DCCVADP_MASK) +#define HFGITR_EL2_DCCVADP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVADP_SHIFT) +#define HFGITR_EL2_DCCVADP_TRAP (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT) +#define HFGITR_EL2_DCCVAP_SHIFT 8 +#define HFGITR_EL2_DCCVAP_MASK (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT) +#define HFGITR_EL2_DCCVAP_VAL(x) ((x) & HFGITR_EL2_DCCVAP_MASK) +#define HFGITR_EL2_DCCVAP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAP_SHIFT) +#define HFGITR_EL2_DCCVAP_TRAP (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT) +#define HFGITR_EL2_DCCVAU_SHIFT 7 +#define HFGITR_EL2_DCCVAU_MASK (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT) +#define HFGITR_EL2_DCCVAU_VAL(x) ((x) & HFGITR_EL2_DCCVAU_MASK) +#define HFGITR_EL2_DCCVAU_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAU_SHIFT) +#define HFGITR_EL2_DCCVAU_TRAP (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT) +#define HFGITR_EL2_DCCISW_SHIFT 6 +#define HFGITR_EL2_DCCISW_MASK (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT) +#define HFGITR_EL2_DCCISW_VAL(x) ((x) & HFGITR_EL2_DCCISW_MASK) +#define HFGITR_EL2_DCCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCISW_SHIFT) +#define HFGITR_EL2_DCCISW_TRAP (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT) +#define HFGITR_EL2_DCCSW_SHIFT 5 +#define HFGITR_EL2_DCCSW_MASK (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT) +#define HFGITR_EL2_DCCSW_VAL(x) ((x) & HFGITR_EL2_DCCSW_MASK) +#define HFGITR_EL2_DCCSW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCSW_SHIFT) +#define HFGITR_EL2_DCCSW_TRAP (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT) +#define HFGITR_EL2_DCISW_SHIFT 4 +#define HFGITR_EL2_DCISW_MASK (UL(0x1) << HFGITR_EL2_DCISW_SHIFT) +#define HFGITR_EL2_DCISW_VAL(x) ((x) & HFGITR_EL2_DCISW_MASK) +#define HFGITR_EL2_DCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCISW_SHIFT) +#define HFGITR_EL2_DCISW_TRAP (UL(0x1) << HFGITR_EL2_DCISW_SHIFT) +#define HFGITR_EL2_DCIVAC_SHIFT 3 +#define HFGITR_EL2_DCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT) +#define HFGITR_EL2_DCIVAC_VAL(x) ((x) & HFGITR_EL2_DCIVAC_MASK) +#define HFGITR_EL2_DCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCIVAC_SHIFT) +#define HFGITR_EL2_DCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT) +#define HFGITR_EL2_ICIVAU_SHIFT 2 +#define HFGITR_EL2_ICIVAU_MASK (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT) +#define HFGITR_EL2_ICIVAU_VAL(x) ((x) & HFGITR_EL2_ICIVAU_MASK) +#define HFGITR_EL2_ICIVAU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIVAU_SHIFT) +#define HFGITR_EL2_ICIVAU_TRAP (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT) +#define HFGITR_EL2_ICIALLU_SHIFT 1 +#define HFGITR_EL2_ICIALLU_MASK (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT) +#define HFGITR_EL2_ICIALLU_VAL(x) ((x) & HFGITR_EL2_ICIALLU_MASK) +#define HFGITR_EL2_ICIALLU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLU_SHIFT) +#define HFGITR_EL2_ICIALLU_TRAP (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT) +#define HFGITR_EL2_ICIALLUIS_SHIFT 0 +#define HFGITR_EL2_ICIALLUIS_MASK (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT) +#define HFGITR_EL2_ICIALLUIS_VAL(x) ((x) & HFGITR_EL2_ICIALLUIS_MASK) +#define HFGITR_EL2_ICIALLUIS_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLUIS_SHIFT) +#define HFGITR_EL2_ICIALLUIS_TRAP (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT) + +/* HFGRTR2_EL2 */ +#define HFGRTR2_EL2_REG MRS_REG_ALT_NAME(HFGRTR2_EL2) +#define HFGRTR2_EL2_op0 3 +#define HFGRTR2_EL2_op1 4 +#define HFGRTR2_EL2_CRn 3 +#define HFGRTR2_EL2_CRm 1 +#define HFGRTR2_EL2_op2 2 +#define HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT 2 +#define HFGRTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGRTR2_EL2_nRCWSMASK_EL1_VAL(x) ((x) & HFGRTR2_EL2_nRCWSMASK_EL1_MASK) +#define HFGRTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGRTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGRTR2_EL2_nERXGSR_EL1_SHIFT 1 +#define HFGRTR2_EL2_nERXGSR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) +#define HFGRTR2_EL2_nERXGSR_EL1_VAL(x) ((x) & HFGRTR2_EL2_nERXGSR_EL1_MASK) +#define HFGRTR2_EL2_nERXGSR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) +#define HFGRTR2_EL2_nERXGSR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT) +#define HFGRTR2_EL2_nPFAR_EL1_SHIFT 0 +#define HFGRTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) +#define HFGRTR2_EL2_nPFAR_EL1_VAL(x) ((x) & HFGRTR2_EL2_nPFAR_EL1_MASK) +#define HFGRTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) +#define HFGRTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT) + +/* HFGRTR_EL2 */ +#define HFGRTR_EL2_REG MRS_REG_ALT_NAME(HFGRTR_EL2) +#define HFGRTR_EL2_op0 3 +#define HFGRTR_EL2_op1 4 +#define HFGRTR_EL2_CRn 1 +#define HFGRTR_EL2_CRm 1 +#define HFGRTR_EL2_op2 4 +#define HFGRTR_EL2_nAMAIR2_EL1_SHIFT 63 +#define HFGRTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nAMAIR2_EL1_VAL(x) ((x) & HFGRTR_EL2_nAMAIR2_EL1_MASK) +#define HFGRTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nMAIR2_EL1_SHIFT 62 +#define HFGRTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nMAIR2_EL1_VAL(x) ((x) & HFGRTR_EL2_nMAIR2_EL1_MASK) +#define HFGRTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGRTR_EL2_nS2POR_EL1_SHIFT 61 +#define HFGRTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT) +#define HFGRTR_EL2_nS2POR_EL1_VAL(x) ((x) & HFGRTR_EL2_nS2POR_EL1_MASK) +#define HFGRTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nS2POR_EL1_SHIFT) +#define HFGRTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT) +#define HFGRTR_EL2_nPOR_EL1_SHIFT 60 +#define HFGRTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT) +#define HFGRTR_EL2_nPOR_EL1_VAL(x) ((x) & HFGRTR_EL2_nPOR_EL1_MASK) +#define HFGRTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL1_SHIFT) +#define HFGRTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT) +#define HFGRTR_EL2_nPOR_EL0_SHIFT 59 +#define HFGRTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT) +#define HFGRTR_EL2_nPOR_EL0_VAL(x) ((x) & HFGRTR_EL2_nPOR_EL0_MASK) +#define HFGRTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL0_SHIFT) +#define HFGRTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT) +#define HFGRTR_EL2_nPIR_EL1_SHIFT 58 +#define HFGRTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT) +#define HFGRTR_EL2_nPIR_EL1_VAL(x) ((x) & HFGRTR_EL2_nPIR_EL1_MASK) +#define HFGRTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIR_EL1_SHIFT) +#define HFGRTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT) +#define HFGRTR_EL2_nPIRE0_EL1_SHIFT 57 +#define HFGRTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGRTR_EL2_nPIRE0_EL1_VAL(x) ((x) & HFGRTR_EL2_nPIRE0_EL1_MASK) +#define HFGRTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGRTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGRTR_EL2_nRCWMASK_EL1_SHIFT 56 +#define HFGRTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGRTR_EL2_nRCWMASK_EL1_VAL(x) ((x) & HFGRTR_EL2_nRCWMASK_EL1_MASK) +#define HFGRTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGRTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGRTR_EL2_nTPIDR2_EL0_SHIFT 55 +#define HFGRTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGRTR_EL2_nTPIDR2_EL0_VAL(x) ((x) & HFGRTR_EL2_nTPIDR2_EL0_MASK) +#define HFGRTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGRTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGRTR_EL2_nSMPRI_EL1_SHIFT 54 +#define HFGRTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGRTR_EL2_nSMPRI_EL1_VAL(x) ((x) & HFGRTR_EL2_nSMPRI_EL1_MASK) +#define HFGRTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGRTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGRTR_EL2_nGCS_EL1_SHIFT 53 +#define HFGRTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT) +#define HFGRTR_EL2_nGCS_EL1_VAL(x) ((x) & HFGRTR_EL2_nGCS_EL1_MASK) +#define HFGRTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL1_SHIFT) +#define HFGRTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT) +#define HFGRTR_EL2_nGCS_EL0_SHIFT 52 +#define HFGRTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT) +#define HFGRTR_EL2_nGCS_EL0_VAL(x) ((x) & HFGRTR_EL2_nGCS_EL0_MASK) +#define HFGRTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL0_SHIFT) +#define HFGRTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT) +#define HFGRTR_EL2_nACCDATA_EL1_SHIFT 50 +#define HFGRTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGRTR_EL2_nACCDATA_EL1_VAL(x) ((x) & HFGRTR_EL2_nACCDATA_EL1_MASK) +#define HFGRTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGRTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGRTR_EL2_ERXADDR_EL1_SHIFT 49 +#define HFGRTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGRTR_EL2_ERXADDR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXADDR_EL1_MASK) +#define HFGRTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGRTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT 48 +#define HFGRTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCDN_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGCDN_EL1_MASK) +#define HFGRTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT 47 +#define HFGRTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCTL_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGCTL_EL1_MASK) +#define HFGRTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGF_EL1_SHIFT 46 +#define HFGRTR_EL2_ERXPFGF_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGF_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXPFGF_EL1_MASK) +#define HFGRTR_EL2_ERXPFGF_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) +#define HFGRTR_EL2_ERXPFGF_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT) +#define HFGRTR_EL2_ERXMISCn_EL1_SHIFT 45 +#define HFGRTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGRTR_EL2_ERXMISCn_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXMISCn_EL1_MASK) +#define HFGRTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGRTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGRTR_EL2_ERXSTATUS_EL1_SHIFT 44 +#define HFGRTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGRTR_EL2_ERXSTATUS_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXSTATUS_EL1_MASK) +#define HFGRTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGRTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGRTR_EL2_ERXCTLR_EL1_SHIFT 43 +#define HFGRTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGRTR_EL2_ERXCTLR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXCTLR_EL1_MASK) +#define HFGRTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGRTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGRTR_EL2_ERXFR_EL1_SHIFT 42 +#define HFGRTR_EL2_ERXFR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT) +#define HFGRTR_EL2_ERXFR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERXFR_EL1_MASK) +#define HFGRTR_EL2_ERXFR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXFR_EL1_SHIFT) +#define HFGRTR_EL2_ERXFR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT) +#define HFGRTR_EL2_ERRSELR_EL1_SHIFT 41 +#define HFGRTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGRTR_EL2_ERRSELR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERRSELR_EL1_MASK) +#define HFGRTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGRTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGRTR_EL2_ERRIDR_EL1_SHIFT 40 +#define HFGRTR_EL2_ERRIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) +#define HFGRTR_EL2_ERRIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_ERRIDR_EL1_MASK) +#define HFGRTR_EL2_ERRIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) +#define HFGRTR_EL2_ERRIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT) +#define HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT 39 +#define HFGRTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGRTR_EL2_ICC_IGRPENn_EL1_VAL(x) ((x) & HFGRTR_EL2_ICC_IGRPENn_EL1_MASK) +#define HFGRTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGRTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGRTR_EL2_VBAR_EL1_SHIFT 38 +#define HFGRTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT) +#define HFGRTR_EL2_VBAR_EL1_VAL(x) ((x) & HFGRTR_EL2_VBAR_EL1_MASK) +#define HFGRTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_VBAR_EL1_SHIFT) +#define HFGRTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT) +#define HFGRTR_EL2_TTBR1_EL1_SHIFT 37 +#define HFGRTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT) +#define HFGRTR_EL2_TTBR1_EL1_VAL(x) ((x) & HFGRTR_EL2_TTBR1_EL1_MASK) +#define HFGRTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR1_EL1_SHIFT) +#define HFGRTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT) +#define HFGRTR_EL2_TTBR0_EL1_SHIFT 36 +#define HFGRTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT) +#define HFGRTR_EL2_TTBR0_EL1_VAL(x) ((x) & HFGRTR_EL2_TTBR0_EL1_MASK) +#define HFGRTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR0_EL1_SHIFT) +#define HFGRTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT) +#define HFGRTR_EL2_TPIDR_EL0_SHIFT 35 +#define HFGRTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT) +#define HFGRTR_EL2_TPIDR_EL0_VAL(x) ((x) & HFGRTR_EL2_TPIDR_EL0_MASK) +#define HFGRTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL0_SHIFT) +#define HFGRTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT) +#define HFGRTR_EL2_TPIDRRO_EL0_SHIFT 34 +#define HFGRTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGRTR_EL2_TPIDRRO_EL0_VAL(x) ((x) & HFGRTR_EL2_TPIDRRO_EL0_MASK) +#define HFGRTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGRTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGRTR_EL2_TPIDR_EL1_SHIFT 33 +#define HFGRTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT) +#define HFGRTR_EL2_TPIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_TPIDR_EL1_MASK) +#define HFGRTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL1_SHIFT) +#define HFGRTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT) +#define HFGRTR_EL2_TCR_EL1_SHIFT 32 +#define HFGRTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT) +#define HFGRTR_EL2_TCR_EL1_VAL(x) ((x) & HFGRTR_EL2_TCR_EL1_MASK) +#define HFGRTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TCR_EL1_SHIFT) +#define HFGRTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL0_SHIFT 31 +#define HFGRTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL0_VAL(x) ((x) & HFGRTR_EL2_SCXTNUM_EL0_MASK) +#define HFGRTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL1_SHIFT 30 +#define HFGRTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL1_VAL(x) ((x) & HFGRTR_EL2_SCXTNUM_EL1_MASK) +#define HFGRTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGRTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGRTR_EL2_SCTLR_EL1_SHIFT 29 +#define HFGRTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT) +#define HFGRTR_EL2_SCTLR_EL1_VAL(x) ((x) & HFGRTR_EL2_SCTLR_EL1_MASK) +#define HFGRTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCTLR_EL1_SHIFT) +#define HFGRTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT) +#define HFGRTR_EL2_REVIDR_EL1_SHIFT 28 +#define HFGRTR_EL2_REVIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT) +#define HFGRTR_EL2_REVIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_REVIDR_EL1_MASK) +#define HFGRTR_EL2_REVIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_REVIDR_EL1_SHIFT) +#define HFGRTR_EL2_REVIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT) +#define HFGRTR_EL2_PAR_EL1_SHIFT 27 +#define HFGRTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT) +#define HFGRTR_EL2_PAR_EL1_VAL(x) ((x) & HFGRTR_EL2_PAR_EL1_MASK) +#define HFGRTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_PAR_EL1_SHIFT) +#define HFGRTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT) +#define HFGRTR_EL2_MPIDR_EL1_SHIFT 26 +#define HFGRTR_EL2_MPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT) +#define HFGRTR_EL2_MPIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_MPIDR_EL1_MASK) +#define HFGRTR_EL2_MPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MPIDR_EL1_SHIFT) +#define HFGRTR_EL2_MPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT) +#define HFGRTR_EL2_MIDR_EL1_SHIFT 25 +#define HFGRTR_EL2_MIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT) +#define HFGRTR_EL2_MIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_MIDR_EL1_MASK) +#define HFGRTR_EL2_MIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MIDR_EL1_SHIFT) +#define HFGRTR_EL2_MIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT) +#define HFGRTR_EL2_MAIR_EL1_SHIFT 24 +#define HFGRTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT) +#define HFGRTR_EL2_MAIR_EL1_VAL(x) ((x) & HFGRTR_EL2_MAIR_EL1_MASK) +#define HFGRTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MAIR_EL1_SHIFT) +#define HFGRTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT) +#define HFGRTR_EL2_LORSA_EL1_SHIFT 23 +#define HFGRTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT) +#define HFGRTR_EL2_LORSA_EL1_VAL(x) ((x) & HFGRTR_EL2_LORSA_EL1_MASK) +#define HFGRTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORSA_EL1_SHIFT) +#define HFGRTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT) +#define HFGRTR_EL2_LORN_EL1_SHIFT 22 +#define HFGRTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT) +#define HFGRTR_EL2_LORN_EL1_VAL(x) ((x) & HFGRTR_EL2_LORN_EL1_MASK) +#define HFGRTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORN_EL1_SHIFT) +#define HFGRTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT) +#define HFGRTR_EL2_LORID_EL1_SHIFT 21 +#define HFGRTR_EL2_LORID_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT) +#define HFGRTR_EL2_LORID_EL1_VAL(x) ((x) & HFGRTR_EL2_LORID_EL1_MASK) +#define HFGRTR_EL2_LORID_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORID_EL1_SHIFT) +#define HFGRTR_EL2_LORID_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT) +#define HFGRTR_EL2_LOREA_EL1_SHIFT 20 +#define HFGRTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT) +#define HFGRTR_EL2_LOREA_EL1_VAL(x) ((x) & HFGRTR_EL2_LOREA_EL1_MASK) +#define HFGRTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LOREA_EL1_SHIFT) +#define HFGRTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT) +#define HFGRTR_EL2_LORC_EL1_SHIFT 19 +#define HFGRTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT) +#define HFGRTR_EL2_LORC_EL1_VAL(x) ((x) & HFGRTR_EL2_LORC_EL1_MASK) +#define HFGRTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORC_EL1_SHIFT) +#define HFGRTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT) +#define HFGRTR_EL2_ISR_EL1_SHIFT 18 +#define HFGRTR_EL2_ISR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT) +#define HFGRTR_EL2_ISR_EL1_VAL(x) ((x) & HFGRTR_EL2_ISR_EL1_MASK) +#define HFGRTR_EL2_ISR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ISR_EL1_SHIFT) +#define HFGRTR_EL2_ISR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT) +#define HFGRTR_EL2_FAR_EL1_SHIFT 17 +#define HFGRTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT) +#define HFGRTR_EL2_FAR_EL1_VAL(x) ((x) & HFGRTR_EL2_FAR_EL1_MASK) +#define HFGRTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_FAR_EL1_SHIFT) +#define HFGRTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT) +#define HFGRTR_EL2_ESR_EL1_SHIFT 16 +#define HFGRTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT) +#define HFGRTR_EL2_ESR_EL1_VAL(x) ((x) & HFGRTR_EL2_ESR_EL1_MASK) +#define HFGRTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ESR_EL1_SHIFT) +#define HFGRTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT) +#define HFGRTR_EL2_DCZID_EL0_SHIFT 15 +#define HFGRTR_EL2_DCZID_EL0_MASK (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT) +#define HFGRTR_EL2_DCZID_EL0_VAL(x) ((x) & HFGRTR_EL2_DCZID_EL0_MASK) +#define HFGRTR_EL2_DCZID_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_DCZID_EL0_SHIFT) +#define HFGRTR_EL2_DCZID_EL0_TRAP (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT) +#define HFGRTR_EL2_CTR_EL0_SHIFT 14 +#define HFGRTR_EL2_CTR_EL0_MASK (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT) +#define HFGRTR_EL2_CTR_EL0_VAL(x) ((x) & HFGRTR_EL2_CTR_EL0_MASK) +#define HFGRTR_EL2_CTR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_CTR_EL0_SHIFT) +#define HFGRTR_EL2_CTR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT) +#define HFGRTR_EL2_CSSELR_EL1_SHIFT 13 +#define HFGRTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT) +#define HFGRTR_EL2_CSSELR_EL1_VAL(x) ((x) & HFGRTR_EL2_CSSELR_EL1_MASK) +#define HFGRTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CSSELR_EL1_SHIFT) +#define HFGRTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT) +#define HFGRTR_EL2_CPACR_EL1_SHIFT 12 +#define HFGRTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT) +#define HFGRTR_EL2_CPACR_EL1_VAL(x) ((x) & HFGRTR_EL2_CPACR_EL1_MASK) +#define HFGRTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CPACR_EL1_SHIFT) +#define HFGRTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT) +#define HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT 11 +#define HFGRTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGRTR_EL2_CONTEXTIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CONTEXTIDR_EL1_MASK) +#define HFGRTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGRTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGRTR_EL2_CLIDR_EL1_SHIFT 10 +#define HFGRTR_EL2_CLIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT) +#define HFGRTR_EL2_CLIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CLIDR_EL1_MASK) +#define HFGRTR_EL2_CLIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CLIDR_EL1_SHIFT) +#define HFGRTR_EL2_CLIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT) +#define HFGRTR_EL2_CCSIDR_EL1_SHIFT 9 +#define HFGRTR_EL2_CCSIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) +#define HFGRTR_EL2_CCSIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_CCSIDR_EL1_MASK) +#define HFGRTR_EL2_CCSIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) +#define HFGRTR_EL2_CCSIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT) +#define HFGRTR_EL2_APIBKey_SHIFT 8 +#define HFGRTR_EL2_APIBKey_MASK (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT) +#define HFGRTR_EL2_APIBKey_VAL(x) ((x) & HFGRTR_EL2_APIBKey_MASK) +#define HFGRTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIBKey_SHIFT) +#define HFGRTR_EL2_APIBKey_TRAP (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT) +#define HFGRTR_EL2_APIAKey_SHIFT 7 +#define HFGRTR_EL2_APIAKey_MASK (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT) +#define HFGRTR_EL2_APIAKey_VAL(x) ((x) & HFGRTR_EL2_APIAKey_MASK) +#define HFGRTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIAKey_SHIFT) +#define HFGRTR_EL2_APIAKey_TRAP (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT) +#define HFGRTR_EL2_APGAKey_SHIFT 6 +#define HFGRTR_EL2_APGAKey_MASK (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT) +#define HFGRTR_EL2_APGAKey_VAL(x) ((x) & HFGRTR_EL2_APGAKey_MASK) +#define HFGRTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APGAKey_SHIFT) +#define HFGRTR_EL2_APGAKey_TRAP (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT) +#define HFGRTR_EL2_APDBKey_SHIFT 5 +#define HFGRTR_EL2_APDBKey_MASK (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT) +#define HFGRTR_EL2_APDBKey_VAL(x) ((x) & HFGRTR_EL2_APDBKey_MASK) +#define HFGRTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDBKey_SHIFT) +#define HFGRTR_EL2_APDBKey_TRAP (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT) +#define HFGRTR_EL2_APDAKey_SHIFT 4 +#define HFGRTR_EL2_APDAKey_MASK (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT) +#define HFGRTR_EL2_APDAKey_VAL(x) ((x) & HFGRTR_EL2_APDAKey_MASK) +#define HFGRTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDAKey_SHIFT) +#define HFGRTR_EL2_APDAKey_TRAP (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT) +#define HFGRTR_EL2_AMAIR_EL1_SHIFT 3 +#define HFGRTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT) +#define HFGRTR_EL2_AMAIR_EL1_VAL(x) ((x) & HFGRTR_EL2_AMAIR_EL1_MASK) +#define HFGRTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AMAIR_EL1_SHIFT) +#define HFGRTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT) +#define HFGRTR_EL2_AIDR_EL1_SHIFT 2 +#define HFGRTR_EL2_AIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT) +#define HFGRTR_EL2_AIDR_EL1_VAL(x) ((x) & HFGRTR_EL2_AIDR_EL1_MASK) +#define HFGRTR_EL2_AIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AIDR_EL1_SHIFT) +#define HFGRTR_EL2_AIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT) +#define HFGRTR_EL2_AFSR1_EL1_SHIFT 1 +#define HFGRTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT) +#define HFGRTR_EL2_AFSR1_EL1_VAL(x) ((x) & HFGRTR_EL2_AFSR1_EL1_MASK) +#define HFGRTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR1_EL1_SHIFT) +#define HFGRTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT) +#define HFGRTR_EL2_AFSR0_EL1_SHIFT 0 +#define HFGRTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT) +#define HFGRTR_EL2_AFSR0_EL1_VAL(x) ((x) & HFGRTR_EL2_AFSR0_EL1_MASK) +#define HFGRTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR0_EL1_SHIFT) +#define HFGRTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT) + +/* HFGWTR2_EL2 */ +#define HFGWTR2_EL2_REG MRS_REG_ALT_NAME(HFGWTR2_EL2) +#define HFGWTR2_EL2_op0 3 +#define HFGWTR2_EL2_op1 4 +#define HFGWTR2_EL2_CRn 3 +#define HFGWTR2_EL2_CRm 1 +#define HFGWTR2_EL2_op2 3 +#define HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT 2 +#define HFGWTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGWTR2_EL2_nRCWSMASK_EL1_VAL(x) ((x) & HFGWTR2_EL2_nRCWSMASK_EL1_MASK) +#define HFGWTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGWTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT) +#define HFGWTR2_EL2_nPFAR_EL1_SHIFT 0 +#define HFGWTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) +#define HFGWTR2_EL2_nPFAR_EL1_VAL(x) ((x) & HFGWTR2_EL2_nPFAR_EL1_MASK) +#define HFGWTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) +#define HFGWTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT) + +/* HFGWTR_EL2 */ +#define HFGWTR_EL2_REG MRS_REG_ALT_NAME(HFGWTR_EL2) +#define HFGWTR_EL2_op0 3 +#define HFGWTR_EL2_op1 4 +#define HFGWTR_EL2_CRn 1 +#define HFGWTR_EL2_CRm 1 +#define HFGWTR_EL2_op2 5 +#define HFGWTR_EL2_nAMAIR2_EL1_SHIFT 63 +#define HFGWTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nAMAIR2_EL1_VAL(x) ((x) & HFGWTR_EL2_nAMAIR2_EL1_MASK) +#define HFGWTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nMAIR2_EL1_SHIFT 62 +#define HFGWTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nMAIR2_EL1_VAL(x) ((x) & HFGWTR_EL2_nMAIR2_EL1_MASK) +#define HFGWTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT) +#define HFGWTR_EL2_nS2POR_EL1_SHIFT 61 +#define HFGWTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT) +#define HFGWTR_EL2_nS2POR_EL1_VAL(x) ((x) & HFGWTR_EL2_nS2POR_EL1_MASK) +#define HFGWTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nS2POR_EL1_SHIFT) +#define HFGWTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT) +#define HFGWTR_EL2_nPOR_EL1_SHIFT 60 +#define HFGWTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT) +#define HFGWTR_EL2_nPOR_EL1_VAL(x) ((x) & HFGWTR_EL2_nPOR_EL1_MASK) +#define HFGWTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL1_SHIFT) +#define HFGWTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT) +#define HFGWTR_EL2_nPOR_EL0_SHIFT 59 +#define HFGWTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT) +#define HFGWTR_EL2_nPOR_EL0_VAL(x) ((x) & HFGWTR_EL2_nPOR_EL0_MASK) +#define HFGWTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL0_SHIFT) +#define HFGWTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT) +#define HFGWTR_EL2_nPIR_EL1_SHIFT 58 +#define HFGWTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT) +#define HFGWTR_EL2_nPIR_EL1_VAL(x) ((x) & HFGWTR_EL2_nPIR_EL1_MASK) +#define HFGWTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIR_EL1_SHIFT) +#define HFGWTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT) +#define HFGWTR_EL2_nPIRE0_EL1_SHIFT 57 +#define HFGWTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGWTR_EL2_nPIRE0_EL1_VAL(x) ((x) & HFGWTR_EL2_nPIRE0_EL1_MASK) +#define HFGWTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGWTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT) +#define HFGWTR_EL2_nRCWMASK_EL1_SHIFT 56 +#define HFGWTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGWTR_EL2_nRCWMASK_EL1_VAL(x) ((x) & HFGWTR_EL2_nRCWMASK_EL1_MASK) +#define HFGWTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGWTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT) +#define HFGWTR_EL2_nTPIDR2_EL0_SHIFT 55 +#define HFGWTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGWTR_EL2_nTPIDR2_EL0_VAL(x) ((x) & HFGWTR_EL2_nTPIDR2_EL0_MASK) +#define HFGWTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGWTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT) +#define HFGWTR_EL2_nSMPRI_EL1_SHIFT 54 +#define HFGWTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGWTR_EL2_nSMPRI_EL1_VAL(x) ((x) & HFGWTR_EL2_nSMPRI_EL1_MASK) +#define HFGWTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGWTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT) +#define HFGWTR_EL2_nGCS_EL1_SHIFT 53 +#define HFGWTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT) +#define HFGWTR_EL2_nGCS_EL1_VAL(x) ((x) & HFGWTR_EL2_nGCS_EL1_MASK) +#define HFGWTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL1_SHIFT) +#define HFGWTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT) +#define HFGWTR_EL2_nGCS_EL0_SHIFT 52 +#define HFGWTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT) +#define HFGWTR_EL2_nGCS_EL0_VAL(x) ((x) & HFGWTR_EL2_nGCS_EL0_MASK) +#define HFGWTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL0_SHIFT) +#define HFGWTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT) +#define HFGWTR_EL2_nACCDATA_EL1_SHIFT 50 +#define HFGWTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGWTR_EL2_nACCDATA_EL1_VAL(x) ((x) & HFGWTR_EL2_nACCDATA_EL1_MASK) +#define HFGWTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGWTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT) +#define HFGWTR_EL2_ERXADDR_EL1_SHIFT 49 +#define HFGWTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGWTR_EL2_ERXADDR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXADDR_EL1_MASK) +#define HFGWTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGWTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT 48 +#define HFGWTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCDN_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXPFGCDN_EL1_MASK) +#define HFGWTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT 47 +#define HFGWTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCTL_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXPFGCTL_EL1_MASK) +#define HFGWTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGWTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT) +#define HFGWTR_EL2_ERXMISCn_EL1_SHIFT 45 +#define HFGWTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGWTR_EL2_ERXMISCn_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXMISCn_EL1_MASK) +#define HFGWTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGWTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT) +#define HFGWTR_EL2_ERXSTATUS_EL1_SHIFT 44 +#define HFGWTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGWTR_EL2_ERXSTATUS_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXSTATUS_EL1_MASK) +#define HFGWTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGWTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT) +#define HFGWTR_EL2_ERXCTLR_EL1_SHIFT 43 +#define HFGWTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGWTR_EL2_ERXCTLR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERXCTLR_EL1_MASK) +#define HFGWTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGWTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT) +#define HFGWTR_EL2_ERRSELR_EL1_SHIFT 41 +#define HFGWTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGWTR_EL2_ERRSELR_EL1_VAL(x) ((x) & HFGWTR_EL2_ERRSELR_EL1_MASK) +#define HFGWTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGWTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT) +#define HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT 39 +#define HFGWTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGWTR_EL2_ICC_IGRPENn_EL1_VAL(x) ((x) & HFGWTR_EL2_ICC_IGRPENn_EL1_MASK) +#define HFGWTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGWTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT) +#define HFGWTR_EL2_VBAR_EL1_SHIFT 38 +#define HFGWTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT) +#define HFGWTR_EL2_VBAR_EL1_VAL(x) ((x) & HFGWTR_EL2_VBAR_EL1_MASK) +#define HFGWTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_VBAR_EL1_SHIFT) +#define HFGWTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT) +#define HFGWTR_EL2_TTBR1_EL1_SHIFT 37 +#define HFGWTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT) +#define HFGWTR_EL2_TTBR1_EL1_VAL(x) ((x) & HFGWTR_EL2_TTBR1_EL1_MASK) +#define HFGWTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR1_EL1_SHIFT) +#define HFGWTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT) +#define HFGWTR_EL2_TTBR0_EL1_SHIFT 36 +#define HFGWTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT) +#define HFGWTR_EL2_TTBR0_EL1_VAL(x) ((x) & HFGWTR_EL2_TTBR0_EL1_MASK) +#define HFGWTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR0_EL1_SHIFT) +#define HFGWTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT) +#define HFGWTR_EL2_TPIDR_EL0_SHIFT 35 +#define HFGWTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT) +#define HFGWTR_EL2_TPIDR_EL0_VAL(x) ((x) & HFGWTR_EL2_TPIDR_EL0_MASK) +#define HFGWTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL0_SHIFT) +#define HFGWTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT) +#define HFGWTR_EL2_TPIDRRO_EL0_SHIFT 34 +#define HFGWTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGWTR_EL2_TPIDRRO_EL0_VAL(x) ((x) & HFGWTR_EL2_TPIDRRO_EL0_MASK) +#define HFGWTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGWTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT) +#define HFGWTR_EL2_TPIDR_EL1_SHIFT 33 +#define HFGWTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT) +#define HFGWTR_EL2_TPIDR_EL1_VAL(x) ((x) & HFGWTR_EL2_TPIDR_EL1_MASK) +#define HFGWTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL1_SHIFT) +#define HFGWTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT) +#define HFGWTR_EL2_TCR_EL1_SHIFT 32 +#define HFGWTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT) +#define HFGWTR_EL2_TCR_EL1_VAL(x) ((x) & HFGWTR_EL2_TCR_EL1_MASK) +#define HFGWTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TCR_EL1_SHIFT) +#define HFGWTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL0_SHIFT 31 +#define HFGWTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL0_VAL(x) ((x) & HFGWTR_EL2_SCXTNUM_EL0_MASK) +#define HFGWTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL1_SHIFT 30 +#define HFGWTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL1_VAL(x) ((x) & HFGWTR_EL2_SCXTNUM_EL1_MASK) +#define HFGWTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGWTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT) +#define HFGWTR_EL2_SCTLR_EL1_SHIFT 29 +#define HFGWTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT) +#define HFGWTR_EL2_SCTLR_EL1_VAL(x) ((x) & HFGWTR_EL2_SCTLR_EL1_MASK) +#define HFGWTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCTLR_EL1_SHIFT) +#define HFGWTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT) +#define HFGWTR_EL2_PAR_EL1_SHIFT 27 +#define HFGWTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT) +#define HFGWTR_EL2_PAR_EL1_VAL(x) ((x) & HFGWTR_EL2_PAR_EL1_MASK) +#define HFGWTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_PAR_EL1_SHIFT) +#define HFGWTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT) +#define HFGWTR_EL2_MAIR_EL1_SHIFT 24 +#define HFGWTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT) +#define HFGWTR_EL2_MAIR_EL1_VAL(x) ((x) & HFGWTR_EL2_MAIR_EL1_MASK) +#define HFGWTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_MAIR_EL1_SHIFT) +#define HFGWTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT) +#define HFGWTR_EL2_LORSA_EL1_SHIFT 23 +#define HFGWTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT) +#define HFGWTR_EL2_LORSA_EL1_VAL(x) ((x) & HFGWTR_EL2_LORSA_EL1_MASK) +#define HFGWTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORSA_EL1_SHIFT) +#define HFGWTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT) +#define HFGWTR_EL2_LORN_EL1_SHIFT 22 +#define HFGWTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT) +#define HFGWTR_EL2_LORN_EL1_VAL(x) ((x) & HFGWTR_EL2_LORN_EL1_MASK) +#define HFGWTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORN_EL1_SHIFT) +#define HFGWTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT) +#define HFGWTR_EL2_LOREA_EL1_SHIFT 20 +#define HFGWTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT) +#define HFGWTR_EL2_LOREA_EL1_VAL(x) ((x) & HFGWTR_EL2_LOREA_EL1_MASK) +#define HFGWTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LOREA_EL1_SHIFT) +#define HFGWTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT) +#define HFGWTR_EL2_LORC_EL1_SHIFT 19 +#define HFGWTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT) +#define HFGWTR_EL2_LORC_EL1_VAL(x) ((x) & HFGWTR_EL2_LORC_EL1_MASK) +#define HFGWTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORC_EL1_SHIFT) +#define HFGWTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT) +#define HFGWTR_EL2_FAR_EL1_SHIFT 17 +#define HFGWTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT) +#define HFGWTR_EL2_FAR_EL1_VAL(x) ((x) & HFGWTR_EL2_FAR_EL1_MASK) +#define HFGWTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_FAR_EL1_SHIFT) +#define HFGWTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT) +#define HFGWTR_EL2_ESR_EL1_SHIFT 16 +#define HFGWTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT) +#define HFGWTR_EL2_ESR_EL1_VAL(x) ((x) & HFGWTR_EL2_ESR_EL1_MASK) +#define HFGWTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ESR_EL1_SHIFT) +#define HFGWTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT) +#define HFGWTR_EL2_CSSELR_EL1_SHIFT 13 +#define HFGWTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT) +#define HFGWTR_EL2_CSSELR_EL1_VAL(x) ((x) & HFGWTR_EL2_CSSELR_EL1_MASK) +#define HFGWTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CSSELR_EL1_SHIFT) +#define HFGWTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT) +#define HFGWTR_EL2_CPACR_EL1_SHIFT 12 +#define HFGWTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT) +#define HFGWTR_EL2_CPACR_EL1_VAL(x) ((x) & HFGWTR_EL2_CPACR_EL1_MASK) +#define HFGWTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CPACR_EL1_SHIFT) +#define HFGWTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT) +#define HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT 11 +#define HFGWTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGWTR_EL2_CONTEXTIDR_EL1_VAL(x) ((x) & HFGWTR_EL2_CONTEXTIDR_EL1_MASK) +#define HFGWTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGWTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT) +#define HFGWTR_EL2_APIBKey_SHIFT 8 +#define HFGWTR_EL2_APIBKey_MASK (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT) +#define HFGWTR_EL2_APIBKey_VAL(x) ((x) & HFGWTR_EL2_APIBKey_MASK) +#define HFGWTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIBKey_SHIFT) +#define HFGWTR_EL2_APIBKey_TRAP (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT) +#define HFGWTR_EL2_APIAKey_SHIFT 7 +#define HFGWTR_EL2_APIAKey_MASK (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT) +#define HFGWTR_EL2_APIAKey_VAL(x) ((x) & HFGWTR_EL2_APIAKey_MASK) +#define HFGWTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIAKey_SHIFT) +#define HFGWTR_EL2_APIAKey_TRAP (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT) +#define HFGWTR_EL2_APGAKey_SHIFT 6 +#define HFGWTR_EL2_APGAKey_MASK (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT) +#define HFGWTR_EL2_APGAKey_VAL(x) ((x) & HFGWTR_EL2_APGAKey_MASK) +#define HFGWTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APGAKey_SHIFT) +#define HFGWTR_EL2_APGAKey_TRAP (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT) +#define HFGWTR_EL2_APDBKey_SHIFT 5 +#define HFGWTR_EL2_APDBKey_MASK (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT) +#define HFGWTR_EL2_APDBKey_VAL(x) ((x) & HFGWTR_EL2_APDBKey_MASK) +#define HFGWTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDBKey_SHIFT) +#define HFGWTR_EL2_APDBKey_TRAP (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT) +#define HFGWTR_EL2_APDAKey_SHIFT 4 +#define HFGWTR_EL2_APDAKey_MASK (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT) +#define HFGWTR_EL2_APDAKey_VAL(x) ((x) & HFGWTR_EL2_APDAKey_MASK) +#define HFGWTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDAKey_SHIFT) +#define HFGWTR_EL2_APDAKey_TRAP (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT) +#define HFGWTR_EL2_AMAIR_EL1_SHIFT 3 +#define HFGWTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT) +#define HFGWTR_EL2_AMAIR_EL1_VAL(x) ((x) & HFGWTR_EL2_AMAIR_EL1_MASK) +#define HFGWTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AMAIR_EL1_SHIFT) +#define HFGWTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT) +#define HFGWTR_EL2_AFSR1_EL1_SHIFT 1 +#define HFGWTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT) +#define HFGWTR_EL2_AFSR1_EL1_VAL(x) ((x) & HFGWTR_EL2_AFSR1_EL1_MASK) +#define HFGWTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR1_EL1_SHIFT) +#define HFGWTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT) +#define HFGWTR_EL2_AFSR0_EL1_SHIFT 0 +#define HFGWTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT) +#define HFGWTR_EL2_AFSR0_EL1_VAL(x) ((x) & HFGWTR_EL2_AFSR0_EL1_MASK) +#define HFGWTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR0_EL1_SHIFT) +#define HFGWTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT) + /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */ #define HPFAR_EL2_FIPA_SHIFT 4 #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 @@ -318,6 +2062,16 @@ #define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT) #define SCTLR_EL2_EE_SHIFT 25 #define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) +#define SCTLR_EL2_ITFSB_SHIFT 37 +#define SCTLR_EL2_ITFSB (0x1UL << SCTLR_EL2_ITFSB_SHIFT) +#define SCTLR_EL2_TCF0_SHIFT 38 +#define SCTLR_EL2_TCF0 (0x2UL << SCTLR_EL2_TCF0_SHIFT) +#define SCTLR_EL2_TCF_SHIFT 40 +#define SCTLR_EL2_TCF (0x2UL << SCTLR_EL2_TCF_SHIFT) +#define SCTLR_EL2_ATA0_SHIFT 42 +#define SCTLR_EL2_ATA0 (0x1UL << SCTLR_EL2_ATA0_SHIFT) +#define SCTLR_EL2_ATA_SHIFT 43 +#define SCTLR_EL2_ATA (0x1UL << SCTLR_EL2_ATA_SHIFT) /* TCR_EL2 - Translation Control Register */ #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) @@ -360,12 +2114,34 @@ #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT) #define TCR_EL2_HWU \ (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62) +#define TCR_EL2_TCMA_SHIFT 30 +#define TCR_EL2_TCMA (1UL << TCR_EL2_TCMA_SHIFT) + +/* TFSR_EL2 - Tag Fault Status Register EL2 */ +#define TFSR_EL2_REG MRS_REG_ALT_NAME(TFSR_EL2) +#define TFSR_EL2_op0 3 +#define TFSR_EL2_op1 4 +#define TFSR_EL2_CRn 5 +#define TFSR_EL2_CRm 6 +#define TFSR_EL2_op2 0 +#define TFSR_TF0_SHIFT 0 +#define TFSR_TF0_MASK (UL(0x1) << TFSR_TF0_SHIFT) +#define TFSR_TF1_SHIFT 1 +#define TFSR_TF1_MASK (UL(0x1) << TFSR_TF1_SHIFT) /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ #define VMPIDR_EL2_U 0x0000000040000000 #define VMPIDR_EL2_MT 0x0000000001000000 #define VMPIDR_EL2_RES1 0x0000000080000000 +/* VNCR_EL2 - Virtual Nested Control Register */ +#define VNCR_EL2_REG MRS_REG_ALT_NAME(VNCR_EL2) +#define VNCR_EL2_op0 3 +#define VNCR_EL2_op1 4 +#define VNCR_EL2_CRn 2 +#define VNCR_EL2_CRm 2 +#define VNCR_EL2_op2 0 + /* VTCR_EL2 - Virtualization Translation Control Register */ #define VTCR_EL2_RES1 (0x1UL << 31) #define VTCR_EL2_T0SZ_SHIFT 0 @@ -398,6 +2174,8 @@ #define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) #define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) #define VTCR_EL2_PS_52BIT (0x6UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_VS_SHIFT 19 +#define VTCR_EL2_VS (1UL << VTCR_EL2_VS_SHIFT) #define VTCR_EL2_DS_SHIFT 32 #define VTCR_EL2_DS (0x1UL << VTCR_EL2_DS_SHIFT) @@ -407,4 +2185,99 @@ /* Assumed to be 0 by locore.S */ #define VTTBR_HOST 0x0000000000000000 +/* Size of the memory page pointed to by VNCR_EL2 */ +#define VNCR_PAGE_SIZE 4096 +/* + * Memory offsets of registers redirected to memory by HCR_EL2.NV2 + * relative to the base address stored in VNCR_EL2. + */ +#define VNCR_VTTBR_EL2 0x20 +#define VNCR_VSTTBR_EL2 0x30 +#define VNCR_VTCR_EL2 0x40 +#define VNCR_VSTCR_EL2 0x48 +#define VNCR_VMPIDR_EL2 0x50 +#define VNCR_CNTVOFF_EL2 0x60 +#define VNCR_HCR_EL2 0x78 +#define VNCR_HSTR_EL2 0x80 +#define VNCR_VPIDR_EL2 0x88 +#define VNCR_TPIDR_EL2 0x90 +#define VNCR_HCRX_EL2 0xA0 +#define VNCR_VNCR_EL2 0xB0 +#define VNCR_CPACR_EL1 0x100 /* Architectural Feature Access Control Register */ +#define VNCR_CONTEXTIDR_EL1 0x108 /* Current Process Identifier */ +#define VNCR_SCTLR_EL1 0x110 /* System Control Register */ +#define VNCR_ACTLR_EL1 0x118 /* Auxiliary Control Register */ +#define VNCR_TCR_EL1 0x120 /* Translation Control Register */ +#define VNCR_AFSR0_EL1 0x128 /* Auxiliary Fault Status Register 0 */ +#define VNCR_AFSR1_EL1 0x130 /* Auxiliary Fault Status Register 1 */ +#define VNCR_ESR_EL1 0x138 /* Exception Syndrome Register */ +#define VNCR_MAIR_EL1 0x140 /* Memory Attribute Indirection Register */ +#define VNCR_AMAIR_EL1 0x148 /* Auxiliary Memory Attribute Indirection Register */ +#define VNCR_MDSCR_EL1 0x158 /* Monitor Debug System Control Register */ +#define VNCR_SPSR_EL1 0x160 /* Saved Program Status Register */ +#define VNCR_CNTV_CVAL_EL0 0x168 +#define VNCR_CNTV_CTL_EL0 0x170 +#define VNCR_CNTP_CVAL_EL0 0x178 +#define VNCR_CNTP_CTL_EL0 0x180 +#define VNCR_SCXTNUM_EL1 0x188 +#define VNCR_TFSR_EL1 0x190 +#define VNCR_HDFGRTR2_EL2 0x1A0 +#define VNCR_CNTPOFF_EL2 0x1A8 +#define VNCR_HDFGWTR2_EL2 0x1B0 +#define VNCR_HFGRTR_EL2 0x1B8 +#define VNCR_HFGWTR_EL2 0x1C0 +#define VNCR_HFGITR_EL2 0x1C8 +#define VNCR_HDFGRTR_EL2 0x1D0 +#define VNCR_HDFGWTR_EL2 0x1D8 +#define VNCR_ZCR_EL1 0x1E0 +#define VNCR_HAFGRTR_EL2 0x1E8 +#define VNCR_SMCR_EL1 0x1F0 +#define VNCR_SMPRIMAP_EL2 0x1F8 +#define VNCR_TTBR0_EL1 0x200 /* Translation Table Base Register 0 */ +#define VNCR_TTBR1_EL1 0x210 /* Translation Table Base Register 1 */ +#define VNCR_FAR_EL1 0x220 /* Fault Address Register */ +#define VNCR_ELR_EL1 0x230 /* Exception Link Register */ +#define VNCR_SP_EL1 0x240 +#define VNCR_VBAR_EL1 0x250 /* Vector Base Address Register */ +#define VNCR_TCR2_EL1 0x270 /* Translation Control Register 2 */ +#define VNCR_SCTLR2_EL1 0x278 +#define VNCR_MAIR2_EL1 0x280 +#define VNCR_AMAIR2_EL1 0x288 +#define VNCR_PIRE0_EL1 0x290 +#define VNCR_PIRE0_EL2 0x298 +#define VNCR_PIR_EL1 0x2A0 +#define VNCR_POR_EL1 0x2A8 +#define VNCR_S2PIR_EL2 0x2B0 +#define VNCR_S2POR_EL1 0x2B8 +#define VNCR_HFGRTR2_EL2 0x2C0 +#define VNCR_HFGWTR2_EL2 0x2C8 +#define VNCR_PFAR_EL1 0x2D0 +#define VNCR_HFGITR2_EL2 0x310 +#define VNCR_SCTLRMASK_EL1 0x318 +#define VNCR_CPACRMASK_EL1 0x320 +#define VNCR_SCTLR2MASK_EL1 0x328 +#define VNCR_TCRMASK_EL1 0x330 +#define VNCR_TCR2MASK_EL1 0x338 +#define VNCR_ACTLRMASK_EL1 0x340 +#define VNCR_ICH_HCR_EL2 0x4C0 +#define VNCR_ICH_VMCR_EL2 0x4C8 +#define VNCR_VDISR_EL2 0x500 +#define VNCR_VSESR_EL2 0x508 +#define VNCR_PMBLIMITR_EL1 0x800 +#define VNCR_PMBPTR_EL1 0x810 +#define VNCR_PMBSR_EL1 0x820 +#define VNCR_PMSCR_EL1 0x828 +#define VNCR_PMSEVFR_EL1 0x830 +#define VNCR_PMSICR_EL1 0x838 +#define VNCR_PMSIRR_EL1 0x840 +#define VNCR_PMSLATFR_EL1 0x848 +#define VNCR_PMSNEVFR_EL1 0x850 +#define VNCR_PMSDSFR_EL1 0x858 +#define VNCR_TRFCR_EL1 0x880 +#define VNCR_TRCITECR_EL1 0x888 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 +#define VNCR_BRBCR_EL1 0x8E0 +#define VNCR_SPMACCESSR_EL1 0x8E8 + #endif /* !_MACHINE_HYPERVISOR_H_ */ diff --git a/sys/arm64/include/ifunc.h b/sys/arm64/include/ifunc.h index de452ad34c8f..34e783df8fe5 100644 --- a/sys/arm64/include/ifunc.h +++ b/sys/arm64/include/ifunc.h @@ -29,20 +29,38 @@ #ifndef __ARM64_IFUNC_H #define __ARM64_IFUNC_H +struct __ifunc_arg_t +{ + unsigned long _size; /* Size of the struct, so it can grow. */ + unsigned long _hwcap; + unsigned long _hwcap2; + unsigned long _hwcap3; + unsigned long _hwcap4; +}; + +typedef struct __ifunc_arg_t __ifunc_arg_t; + +#define _IFUNC_ARG_HWCAP (1ULL << 62) + #define DEFINE_IFUNC(qual, ret_type, name, args) \ static ret_type (*name##_resolver(void))args __used; \ qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \ static ret_type (*name##_resolver(void))args #define DEFINE_UIFUNC(qual, ret_type, name, args) \ - static ret_type (*name##_resolver(uint64_t, uint64_t, \ + static ret_type (*name##_resolver(uint64_t, \ + const struct __ifunc_arg_t *ifunc_arg, \ uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, \ uint64_t))args __used; \ qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \ - static ret_type (*name##_resolver(uint64_t _arg1 __unused, \ - uint64_t _arg2 __unused, uint64_t _arg3 __unused, \ - uint64_t _arg4 __unused, uint64_t _arg5 __unused, \ - uint64_t _arg6 __unused, uint64_t _arg7 __unused, \ + static ret_type (*name##_resolver( \ + uint64_t at_hwcap __unused, \ + const struct __ifunc_arg_t *ifunc_arg __unused, \ + uint64_t _arg3 __unused, \ + uint64_t _arg4 __unused, \ + uint64_t _arg5 __unused, \ + uint64_t _arg6 __unused, \ + uint64_t _arg7 __unused, \ uint64_t _arg8 __unused))args #endif diff --git a/sys/arm64/include/machdep.h b/sys/arm64/include/machdep.h index 4fa80219da42..aea8b89b4f32 100644 --- a/sys/arm64/include/machdep.h +++ b/sys/arm64/include/machdep.h @@ -31,7 +31,7 @@ struct arm64_bootparams { vm_offset_t modulep; - vm_offset_t kern_stack; + void *kern_stack; vm_paddr_t kern_ttbr0; int boot_el; /* EL the kernel booted from */ int pad; @@ -54,7 +54,6 @@ vm_offset_t parse_boot_param(struct arm64_bootparams *abp); void parse_fdt_bootargs(void); #endif int memory_mapping_mode(vm_paddr_t pa); -extern void (*pagezero)(void *); #ifdef SOCDEV_PA /* diff --git a/sys/arm64/include/param.h b/sys/arm64/include/param.h index f3cdd4e44bc0..919dea4fb3cf 100644 --- a/sys/arm64/include/param.h +++ b/sys/arm64/include/param.h @@ -41,7 +41,6 @@ #include <sys/_align.h> #define STACKALIGNBYTES (16 - 1) -#define STACKALIGN(p) ((uint64_t)(p) & ~STACKALIGNBYTES) #ifndef MACHINE #define MACHINE "arm64" diff --git a/sys/arm64/include/pcpu.h b/sys/arm64/include/pcpu.h index 73399d2c3f8c..d04f975350d8 100644 --- a/sys/arm64/include/pcpu.h +++ b/sys/arm64/include/pcpu.h @@ -55,11 +55,8 @@ struct debug_monitor_state; #ifdef _KERNEL -struct pcb; struct pcpu; -register struct pcpu *pcpup __asm ("x18"); - static inline struct pcpu * get_pcpu(void) { @@ -80,10 +77,10 @@ get_curthread(void) #define curthread get_curthread() -#define PCPU_GET(member) (pcpup->pc_ ## member) -#define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value)) -#define PCPU_PTR(member) (&pcpup->pc_ ## member) -#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value)) +#define PCPU_GET(member) (get_pcpu()->pc_ ## member) +#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value)) +#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member) +#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value)) #define PCPU_GET_MPIDR(pc) ((pc)->pc_mpidr) diff --git a/sys/arm64/include/pmap.h b/sys/arm64/include/pmap.h index 406b6e2c5e0a..cf20827fa666 100644 --- a/sys/arm64/include/pmap.h +++ b/sys/arm64/include/pmap.h @@ -43,6 +43,7 @@ #ifndef LOCORE #include <sys/queue.h> +#include <sys/systm.h> #include <sys/_lock.h> #include <sys/_mutex.h> #include <sys/_pv_entry.h> @@ -69,9 +70,13 @@ struct md_page { TAILQ_HEAD(,pv_entry) pv_list; int pv_gen; vm_memattr_t pv_memattr; - uint8_t pv_reserve[3]; + uint8_t pv_flags; + uint8_t pv_reserve[2]; }; +/* machine page flags */ +#define PV_MTE_TAGGED 0x01 /* page is tagged with MTE */ + enum pmap_stage { PM_INVALID, PM_STAGE1, @@ -132,6 +137,8 @@ extern vm_offset_t virtual_end; extern pt_entry_t pmap_sh_attr; +extern __read_mostly uint64_t prot_ns_shared_pa; + /* * Macros to test if a mapping is mappable with an L1 Section mapping * or an L2 Large Page mapping. @@ -144,8 +151,9 @@ extern pt_entry_t pmap_sh_attr; void pmap_activate_vm(pmap_t); void pmap_bootstrap_dmap(vm_size_t); void pmap_bootstrap(void); -int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode); -int pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot); +int pmap_change_attr(void *va, vm_size_t size, int mode); +int pmap_change_dmap_attr(int); +int pmap_change_prot(void *va, vm_size_t size, vm_prot_t prot); void pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode); void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t); bool pmap_klookup(vm_offset_t va, vm_paddr_t *pa); @@ -156,6 +164,7 @@ void *pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma); bool pmap_page_is_mapped(vm_page_t m); int pmap_pinit_stage(pmap_t, enum pmap_stage, int); bool pmap_ps_enabled(pmap_t pmap); +bool pmap_vs_enabled(void); uint64_t pmap_to_ttbr0(pmap_t pmap); void pmap_disable_promotion(vm_offset_t sva, vm_size_t size); void pmap_map_delete(pmap_t, vm_offset_t, vm_offset_t); @@ -165,8 +174,8 @@ void *pmap_mapbios(vm_paddr_t, vm_size_t); void pmap_unmapdev(void *, vm_size_t); void pmap_unmapbios(void *, vm_size_t); -bool pmap_map_io_transient(vm_page_t *, vm_offset_t *, int, bool); -void pmap_unmap_io_transient(vm_page_t *, vm_offset_t *, int, bool); +bool pmap_map_io_transient(vm_page_t *, void **, int, bool); +void pmap_unmap_io_transient(vm_page_t *, void **, int, bool); bool pmap_get_tables(pmap_t, vm_offset_t, pd_entry_t **, pd_entry_t **, pd_entry_t **, pt_entry_t **); diff --git a/sys/arm64/include/proc.h b/sys/arm64/include/proc.h index b40990e89385..22ceb614413d 100644 --- a/sys/arm64/include/proc.h +++ b/sys/arm64/include/proc.h @@ -69,8 +69,11 @@ struct mdthread { uint64_t md_efirt_tmp; int md_efirt_dis_pf; - int md_reserved0; - uint64_t md_reserved[2]; + u_int md_flags; +#define MD_FLAG_MTE_ASYNC_FAULT_SHIFT 0 +#define MD_FLAG_MTE_ASYNC_FAULT (1u << 0) + uint64_t md_sctlr; + uint64_t md_gcr; /* FEAT_MTE: Tag Control Register */ }; struct mdproc { diff --git a/sys/arm64/include/rsi.h b/sys/arm64/include/rsi.h new file mode 100644 index 000000000000..82e54f9c57e3 --- /dev/null +++ b/sys/arm64/include/rsi.h @@ -0,0 +1,129 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2026 Arm Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_RSI_H_ +#define _MACHINE_RSI_H_ + +extern uint64_t prot_ns_shared; + +bool in_realm(void); + +void arm64_rsi_setup_memory(void); + +/* + * The major version number of the RSI implementation. This is increased when + * the binary format or semantics of the SMC calls change. + */ +#define RSI_ABI_VERSION_MAJOR UL(1) + +/* + * The minor version number of the RSI implementation. This is increased when + * a bug is fixed, or a feature is added without breaking binary compatibility. + */ +#define RSI_ABI_VERSION_MINOR UL(0) + +#define RSI_ABI_VERSION ((RSI_ABI_VERSION_MAJOR << 16) | \ + RSI_ABI_VERSION_MINOR) + +#define RSI_ABI_VERSION_GET_MAJOR(_version) ((_version) >> 16) +#define RSI_ABI_VERSION_GET_MINOR(_version) ((_version) & 0xFFFF) + +#define RSI_SUCCESS UL(0) +#define RSI_ERROR_INPUT UL(1) +#define RSI_ERROR_STATE UL(2) +#define RSI_INCOMPLETE UL(3) +#define RSI_ERROR_UNKNOWN UL(4) + +#define SMC_RSI_FID(n) SMCCC_FUNC_ID(SMCCC_FAST_CALL, \ + SMCCC_64BIT_CALL, \ + SMCCC_STD_SECURE_SERVICE_CALLS, \ + n) + +/* + * Returns RSI version. + * + * arg1 == Requested interface revision + * ret0 == Status / error + * ret1 == Lower implemented interface revision + * ret2 == Higher implemented interface revision + */ +#define SMC_RSI_ABI_VERSION SMC_RSI_FID(0x190) + +/* + * Read configuration for the current Realm. + * + * arg1 == struct realm_config addr + * ret0 == Status / error + */ +#define SMC_RSI_REALM_CONFIG SMC_RSI_FID(0x196) + +struct realm_config { + union { + struct { + unsigned long ipa_bits; /* Width of IPA in bits */ + unsigned long hash_algo; /* Hash algorithm */ + }; + uint8_t pad[0x200]; + }; + union { + uint8_t rpv[64]; /* Realm Personalization Value */ + uint8_t pad2[0xe00]; + }; + /* + * The RMM requires the configuration structure to be aligned to a 4k + * boundary, ensure this happens by aligning this structure. + */ +} __aligned(0x1000); + +/* + * Request RIPAS of a target IPA range to be changed to a specified value. + * + * arg1 == Base IPA address of target region + * arg2 == Top of the region + * arg3 == RIPAS value + * arg4 == flags + * ret0 == Status / error + * ret1 == Top of modified IPA range + * ret2 == Whether the Host accepted or rejected the request + */ +#define SMC_RSI_IPA_STATE_SET SMC_RSI_FID(0x197) + +#define RSI_NO_CHANGE_DESTROYED UL(0) +#define RSI_CHANGE_DESTROYED UL(1) + +#define RSI_ACCEPT UL(0) +#define RSI_REJECT UL(1) + +enum ripas { + RSI_RIPAS_EMPTY = 0, + RSI_RIPAS_RAM +}; + +unsigned long rsi_set_addr_range_state(vm_paddr_t start, vm_paddr_t end, + enum ripas state, unsigned long flags, vm_paddr_t *top); + +#endif /* !_MACHINE_RSI_H_ */ diff --git a/sys/arm64/include/sf_buf.h b/sys/arm64/include/sf_buf.h index 00ed0e9d7456..c476dc75852b 100644 --- a/sys/arm64/include/sf_buf.h +++ b/sys/arm64/include/sf_buf.h @@ -37,11 +37,11 @@ * That pointer references the vm_page that is "mapped" by the sf_buf. The * actual mapping is provided by the direct virtual-to-physical mapping. */ -static inline vm_offset_t +static inline void * sf_buf_kva(struct sf_buf *sf) { - return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS((vm_page_t)sf))); + return (VM_PAGE_TO_DMAP((vm_page_t)sf)); } static inline vm_page_t diff --git a/sys/arm64/include/stack.h b/sys/arm64/include/stack.h index 3aa1e235884d..23e7a5af27de 100644 --- a/sys/arm64/include/stack.h +++ b/sys/arm64/include/stack.h @@ -39,20 +39,17 @@ bool unwind_frame(struct thread *, struct unwind_state *); #ifdef _SYS_PROC_H_ -#include <machine/pcb.h> - #define GET_STACK_USAGE(total, used) do { \ struct thread *td = curthread; \ - (total) = td->td_kstack_pages * PAGE_SIZE - sizeof(struct pcb); \ - (used) = td->td_kstack + (total) - (vm_offset_t)&td; \ + (total) = ptoa(td->td_kstack_pages); \ + (used) = td->td_kstack + (total) - (char *)&td; \ } while (0) static __inline bool kstack_contains(struct thread *td, vm_offset_t va, size_t len) { - return (va >= td->td_kstack && va + len >= va && - va + len <= td->td_kstack + td->td_kstack_pages * PAGE_SIZE - - sizeof(struct pcb)); + return (va >= (vm_offset_t)td->td_kstack && va + len >= va && + va + len <= (vm_offset_t)td_kstack_top(td)); } #endif /* _SYS_PROC_H_ */ diff --git a/sys/arm64/include/ucontext.h b/sys/arm64/include/ucontext.h index a4f0ee243b3a..11befe4e3023 100644 --- a/sys/arm64/include/ucontext.h +++ b/sys/arm64/include/ucontext.h @@ -76,9 +76,11 @@ struct __mcontext { struct fpregs mc_fpregs; int mc_flags; #define _MC_FP_VALID 0x1 /* Set when mc_fpregs has valid data */ +#define _MC_ESR_VALID 0x2 /* Set when mc_esr has valid data */ int mc_pad; /* Padding */ __uint64_t mc_ptr; /* Address of extra_regs struct */ - __uint64_t mc_spare[7]; /* Space for expansion, set to zero */ + __register_t mc_esr; /* Exception syndrome register */ + __uint64_t mc_spare[6]; /* Space for expansion, set to zero */ }; diff --git a/sys/arm64/include/vm.h b/sys/arm64/include/vm.h index 342143c57246..91e70aeb980a 100644 --- a/sys/arm64/include/vm.h +++ b/sys/arm64/include/vm.h @@ -33,15 +33,42 @@ #define VM_MEMATTR_WRITE_BACK 2 #define VM_MEMATTR_WRITE_THROUGH 3 #define VM_MEMATTR_DEVICE_nGnRE 4 +#define VM_MEMATTR_TAGGED 5 +#define VM_MEMATTR_END (VM_MEMATTR_TAGGED + 1) #define VM_MEMATTR_DEVICE VM_MEMATTR_DEVICE_nGnRE #define VM_MEMATTR_DEVICE_NP VM_MEMATTR_DEVICE_nGnRnE +#define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK + #ifdef _KERNEL /* If defined vmstat will try to use both of these in a switch statement */ #define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WRITE_THROUGH -#endif -#define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK +#ifndef LOCORE +#include <sys/_null.h> + +static inline const char * +vm_memattr_name(vm_memattr_t memattr) +{ + switch (memattr) { + case VM_MEMATTR_DEVICE_nGnRnE: + return ("device-nGnRnE"); + case VM_MEMATTR_UNCACHEABLE: + return ("uncacheable"); + case VM_MEMATTR_WRITE_BACK: + return ("write-back"); + case VM_MEMATTR_WRITE_THROUGH: + return ("write-through"); + case VM_MEMATTR_DEVICE_nGnRE: + return ("device-nGnRE"); + case VM_MEMATTR_TAGGED: + return ("tagged"); + default: + return (NULL); + } +} +#endif +#endif #endif /* !_MACHINE_VM_H_ */ diff --git a/sys/arm64/include/vmm.h b/sys/arm64/include/vmm.h index e67540eac66d..f076bd07f323 100644 --- a/sys/arm64/include/vmm.h +++ b/sys/arm64/include/vmm.h @@ -107,7 +107,39 @@ enum vm_reg_name { #define VM_GUEST_BASE_IPA 0x80000000UL /* Guest kernel start ipa */ #ifdef _KERNEL +#include <machine/vmm_instruction_emul.h> + +#define VMM_VCPU_MD_FIELDS \ + struct vm_exit exitinfo; \ + uint64_t nextpc; /* (x) next instruction to execute */ \ + struct vfpstate *guestfpu /* (a,i) guest fpu state */ + +#define VMM_VM_MD_FIELDS \ + struct vmm_mmio_region mmio_region[VM_MAX_MMIO_REGIONS]; \ + struct vmm_special_reg special_reg[VM_MAX_SPECIAL_REGS] + +struct vmm_mmio_region { + uint64_t start; + uint64_t end; + mem_region_read_t read; + mem_region_write_t write; +}; +#define VM_MAX_MMIO_REGIONS 4 + +struct vmm_special_reg { + uint32_t esr_iss; + uint32_t esr_mask; + reg_read_t reg_read; + reg_write_t reg_write; + void *arg; +}; +#define VM_MAX_SPECIAL_REGS 16 + +#define DECLARE_VMMOPS_FUNC(ret_type, opname, args) \ + ret_type vmmops_##opname args + struct vm; +struct vm_eventinfo; struct vm_exception; struct vm_exit; struct vm_run; @@ -116,15 +148,6 @@ struct vm_guest_paging; struct vm_vgic_descr; struct pmap; -struct vm_eventinfo { - void *rptr; /* rendezvous cookie */ - int *sptr; /* suspend cookie */ - int *iptr; /* reqidle cookie */ -}; - -#define DECLARE_VMMOPS_FUNC(ret_type, opname, args) \ - ret_type vmmops_##opname args - DECLARE_VMMOPS_FUNC(int, modinit, (int ipinum)); DECLARE_VMMOPS_FUNC(int, modcleanup, (void)); DECLARE_VMMOPS_FUNC(void *, init, (struct vm *vm, struct pmap *pmap)); @@ -153,34 +176,13 @@ DECLARE_VMMOPS_FUNC(int, restore_tsc, (void *vcpui, uint64_t now)); #endif #endif -int vm_create(const char *name, struct vm **retvm); -struct vcpu *vm_alloc_vcpu(struct vm *vm, int vcpuid); -void vm_disable_vcpu_creation(struct vm *vm); -void vm_lock_vcpus(struct vm *vm); -void vm_unlock_vcpus(struct vm *vm); -void vm_destroy(struct vm *vm); -int vm_reinit(struct vm *vm); -const char *vm_name(struct vm *vm); - -uint16_t vm_get_maxcpus(struct vm *vm); -void vm_get_topology(struct vm *vm, uint16_t *sockets, uint16_t *cores, - uint16_t *threads, uint16_t *maxcpus); -int vm_set_topology(struct vm *vm, uint16_t sockets, uint16_t cores, - uint16_t threads, uint16_t maxcpus); int vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval); int vm_set_register(struct vcpu *vcpu, int reg, uint64_t val); int vm_run(struct vcpu *vcpu); -int vm_suspend(struct vm *vm, enum vm_suspend_how how); void* vm_get_cookie(struct vm *vm); -int vcpu_vcpuid(struct vcpu *vcpu); void *vcpu_get_cookie(struct vcpu *vcpu); -struct vm *vcpu_vm(struct vcpu *vcpu); -struct vcpu *vm_vcpu(struct vm *vm, int cpu); int vm_get_capability(struct vcpu *vcpu, int type, int *val); int vm_set_capability(struct vcpu *vcpu, int type, int val); -int vm_activate_cpu(struct vcpu *vcpu); -int vm_suspend_cpu(struct vm *vm, struct vcpu *vcpu); -int vm_resume_cpu(struct vm *vm, struct vcpu *vcpu); int vm_inject_exception(struct vcpu *vcpu, uint64_t esr, uint64_t far); int vm_attach_vgic(struct vm *vm, struct vm_vgic_descr *descr); int vm_assert_irq(struct vm *vm, uint32_t irq); @@ -190,62 +192,8 @@ int vm_raise_msi(struct vm *vm, uint64_t msg, uint64_t addr, int bus, int slot, struct vm_exit *vm_exitinfo(struct vcpu *vcpu); void vm_exit_suspended(struct vcpu *vcpu, uint64_t pc); void vm_exit_debug(struct vcpu *vcpu, uint64_t pc); -void vm_exit_rendezvous(struct vcpu *vcpu, uint64_t pc); void vm_exit_astpending(struct vcpu *vcpu, uint64_t pc); -cpuset_t vm_active_cpus(struct vm *vm); -cpuset_t vm_debug_cpus(struct vm *vm); -cpuset_t vm_suspended_cpus(struct vm *vm); - -static __inline int -vcpu_rendezvous_pending(struct vm_eventinfo *info) -{ - - return (*((uintptr_t *)(info->rptr)) != 0); -} - -static __inline int -vcpu_suspended(struct vm_eventinfo *info) -{ - - return (*info->sptr); -} - -int vcpu_debugged(struct vcpu *vcpu); - -enum vcpu_state { - VCPU_IDLE, - VCPU_FROZEN, - VCPU_RUNNING, - VCPU_SLEEPING, -}; - -int vcpu_set_state(struct vcpu *vcpu, enum vcpu_state state, bool from_idle); -enum vcpu_state vcpu_get_state(struct vcpu *vcpu, int *hostcpu); - -static int __inline -vcpu_is_running(struct vcpu *vcpu, int *hostcpu) -{ - return (vcpu_get_state(vcpu, hostcpu) == VCPU_RUNNING); -} - -#ifdef _SYS_PROC_H_ -static int __inline -vcpu_should_yield(struct vcpu *vcpu) -{ - struct thread *td; - - td = curthread; - return (td->td_ast != 0 || td->td_owepreempt != 0); -} -#endif - -void *vcpu_stats(struct vcpu *vcpu); -void vcpu_notify_event(struct vcpu *vcpu); -struct vm_mem *vm_mem(struct vm *vm); - -enum vm_reg_name vm_segment_name(int seg_encoding); - struct vm_copyinfo { uint64_t gpa; size_t len; diff --git a/sys/arm64/include/vmm_instruction_emul.h b/sys/arm64/include/vmm_instruction_emul.h index a295f7cce127..dc281f442543 100644 --- a/sys/arm64/include/vmm_instruction_emul.h +++ b/sys/arm64/include/vmm_instruction_emul.h @@ -27,6 +27,14 @@ #ifndef _VMM_INSTRUCTION_EMUL_H_ #define _VMM_INSTRUCTION_EMUL_H_ +#include <sys/types.h> + +struct vcpu; +struct vm; +struct vie; +struct vre; +struct vm_guest_paging; + /* * Callback functions to read and write memory regions. */ diff --git a/sys/arm64/include/vmparam.h b/sys/arm64/include/vmparam.h index 781602306436..f33cde5894f3 100644 --- a/sys/arm64/include/vmparam.h +++ b/sys/arm64/include/vmparam.h @@ -254,26 +254,32 @@ #define PHYS_IN_DMAP_RANGE(pa) ((pa) >= DMAP_MIN_PHYSADDR && \ (pa) < DMAP_MAX_PHYSADDR) #define PHYS_IN_DMAP(pa) (PHYS_IN_DMAP_RANGE(pa) && \ - pmap_klookup(PHYS_TO_DMAP(pa), NULL)) + pmap_klookup(PHYS_TO_DMAP_ADDR(pa), NULL)) /* True if va is in the dmap range */ -#define VIRT_IN_DMAP(va) ((va) >= DMAP_MIN_ADDRESS && \ - (va) < (dmap_max_addr)) +#define VIRT_IN_DMAP(va) \ +({ \ + uintptr_t __va = (uintptr_t)(va); \ + \ + __va >= DMAP_MIN_ADDRESS && __va < (dmap_max_addr); \ +}) #define PMAP_HAS_DMAP 1 -#define PHYS_TO_DMAP(pa) \ +#define PHYS_TO_DMAP_ADDR(pa) \ ({ \ KASSERT(PHYS_IN_DMAP_RANGE(pa), \ ("%s: PA out of range, PA: 0x%lx", __func__, \ (vm_paddr_t)(pa))); \ ((pa) - dmap_phys_base) + DMAP_MIN_ADDRESS; \ }) +#define PHYS_TO_DMAP(x) ((void *)PHYS_TO_DMAP_ADDR(x)) #define DMAP_TO_PHYS(va) \ ({ \ - KASSERT(VIRT_IN_DMAP(va), \ - ("%s: VA out of range, VA: 0x%lx", __func__, \ - (vm_offset_t)(va))); \ - ((va) - DMAP_MIN_ADDRESS) + dmap_phys_base; \ + uintptr_t _va = (uintptr_t)(va); \ + \ + KASSERT(VIRT_IN_DMAP(_va), \ + ("%s: VA out of range, VA: %p", __func__, (void *)_va)); \ + (_va - DMAP_MIN_ADDRESS) + dmap_phys_base; \ }) #define VM_MIN_USER_ADDRESS (0x0000000000000000UL) |