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path: root/sys/arm64/include/armreg.h
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* arm64: Add EL1 hardware breakpoint exceptionsAndrew Turner2024-03-211-0/+1
* arm64: Add ISS_MSR_REG for ESR_ELx.ISS valuesAndrew Turner2024-02-211-0/+6
* arm64: Add more spsr_el1 register valuesAndrew Turner2024-02-211-0/+7
* arm64: Add CurrentEL register definitionsAndrew Turner2024-02-211-0/+8
* armv8rng: Don't require toolchain to support FEAT_RNGJessica Clarke2023-12-011-0/+9
* Add BTI exceptionsAndrew Turner2023-09-221-0/+1
* arm64: Add TCR register masksAndrew Turner2023-09-081-1/+4
* arm64: Fix the TCR_TBI0 macro to use ULAndrew Turner2023-09-081-1/+1
* arm64: Fix the TCR_EPD0 definitionAndrew Turner2023-09-061-1/+1
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
* arm64: Add constants for decoding ISS fields for WF* exceptionsMark Johnston2023-07-281-0/+20
* arm64: Decode the ID_AA64PFR2_EL1 registerAndrew Turner2023-07-281-0/+8
* arm64: Update the ID_AA64PFR1_EL1 fieldsAndrew Turner2023-07-281-9/+37
* arm64: Update the ID_AA64PFR0_EL1 fieldsAndrew Turner2023-07-281-5/+12
* arm64: Decode the ID_AA64MMFR4_EL1 registerAndrew Turner2023-07-281-0/+8
* arm64: Decode the ID_AA64MMFR3_EL1 registerAndrew Turner2023-07-281-0/+28
* arm64: Don't use hex for ID_AA64MMFR2_EL1_op/CR*Andrew Turner2023-07-281-5/+5
* arm64: Update the ID_AA64MMFR1_EL1 fieldsAndrew Turner2023-07-281-0/+36
* arm64: Update the ID_AA64MMFR0_EL1 fieldsAndrew Turner2023-07-281-10/+25
* arm64: Update the ID_AA64ISAR1_EL1 fieldsAndrew Turner2023-07-281-5/+18
* arm64: Update the ID_AA64ISAR0_EL1 fieldsAndrew Turner2023-07-281-5/+9
* arm64: Update the ID_AA64DFR0_EL1 fieldsAndrew Turner2023-07-281-6/+38
* arm64 lib32: prepare arm64 headers to redirect to armMike Karels2023-07-251-0/+6
* Add more arm64 special register valuesAndrew Turner2023-06-121-0/+16
* arm64: Fix the definition of ID_AA64DFR1_EL1Andrew Turner2023-06-021-1/+1
* Add more arm64 ID registersAndrew Turner2023-06-021-0/+16
* arm64: Remove CNTHCTL_EL2 from arm64.hAndrew Turner2023-05-241-7/+0
* Add more arm64 special registersAndrew Turner2023-05-241-2/+46
* Mark the arm64 PSR register fields with ULAndrew Turner2023-03-231-23/+23
* Mark arm64 mair_el1 fields as unsigned longAndrew Turner2023-03-161-6/+6
* Decode the arm64 ID_AA64ISAR1_EL1 registerAndrew Turner2022-09-061-0/+47
* Decode the arm64 SVE ID registerAndrew Turner2022-06-291-0/+56
* Allow use of the arm64 unnamed register formAndrew Turner2022-06-291-0/+6
* Add the SVE reigster definitionsAndrew Turner2022-06-241-0/+10
* Trap SVE instructions until we have SVE supportAndrew Turner2022-06-241-0/+1
* arm64: Print per-CPU cache summaryJustin Hibbits2022-06-061-0/+30
* Decode all Arm GIC feature ID bitsAndrew Turner2022-05-241-0/+1
* arm64: Enable the floating-point exception trapsDmitry Chagin2022-05-191-0/+8
* aarch64: Add constants for fields in the PMEVTYPERn_EL0 event registers.John Baldwin2022-03-111-1/+10
* Revert "Add the PMCR_EL0.N arm64 register field"Andrew Turner2022-03-111-2/+0
* Add more arm64 register op* and CR* valuesAndrew Turner2022-03-111-0/+293
* Add the PMCR_EL0.N arm64 register fieldAndrew Turner2022-03-111-0/+2
* Correct the location of the arm64 PMCR registerAndrew Turner2022-03-111-28/+27
* Sort the M* and P* arm64 registersAndrew Turner2022-03-111-141/+141
* Fix the TCR_TG0 valuesAndrew Turner2022-03-101-3/+3
* Add more arm64 PAC identification fieldsAndrew Turner2022-03-101-0/+6
* Stop single stepping in signal handers on arm64Andrew Turner2022-02-071-0/+3
* Sort the names of the arm64 debug registersAndrew Turner2022-02-041-46/+46
* Add the Armv8.3-SPE registersAndrew Turner2022-01-191-0/+186
* Add arm64 pointer authentication supportAndrew Turner2022-01-121-0/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-24 05:16:33 +0000