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path: root/sys/sparc64/sparc64/cache.c
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* Now that we have a working OF_printf() since r230631 and a OF_panic()Marius Strobl2012-01-271-6/+6
* - For Cheetah- and Zeus-class CPUs don't flush all unlocked entries fromMarius Strobl2011-07-021-3/+3
* For CPUs which ignore TD_CV and support hardware unaliasing don'tMarius Strobl2010-08-081-3/+11
* Add support for SPARC64 V (and where it already makes sense for otherMarius Strobl2010-05-021-3/+17
* Starting with UltraSPARC IV CPUs the CPU caches are described with differentMarius Strobl2010-02-201-19/+37
* Some machines can not only consist of CPUs running at different speedsMarius Strobl2010-02-201-1/+1
* - USIII-based machines can consist of CPUs having different cacheMarius Strobl2008-09-021-21/+28
* - Do as the comment in pmap_bootstrap() suggests and flush all non-lockedMarius Strobl2008-03-091-2/+5
* /* -> /*- for license, minor formatting changesWarner Losh2005-01-071-1/+1
* Remove advertising clause from University of California Regent'sWarner Losh2004-04-071-4/+0
* Fix a bug in the data access error recorvery. Before re-enabling the dataJake Burkholder2003-11-111-0/+6
* - Move the routine for flushing all user mappings from the tlb from pmap toJake Burkholder2003-04-131-0/+3
* - Remove unused cache flushing routines. These will not necessary workJake Burkholder2003-03-191-376/+9
* - Reorganize PMAP_STATS to scale a little better.Jake Burkholder2003-01-051-28/+4
* Correct typos, mostly s/ a / an / where appropriate. Some whitespace cleanup,Jens Schweikhardt2003-01-011-3/+3
* Fix typos, mostly s/ an / a / where appropriate and a few s/an/and/Jens Schweikhardt2002-12-301-1/+1
* - Add a spin lock to single thread cache invalidation and tlb flush ipis,Jake Burkholder2002-12-221-4/+2
* Add some statistic gathering for cache flushes.Jake Burkholder2002-07-311-2/+41
* The data cache on UltraSPARC III is not directly mapped, so don't assertJake Burkholder2002-07-301-2/+0
* Panic if the data cache has too many virtual colors (more than 2).Jake Burkholder2002-07-301-0/+2
* Add SMP aware cache flushing functions, which operate on a single physicalJake Burkholder2002-05-201-2/+61
* Decruft some #if 0'ed code.Thomas Moestl2002-03-231-2/+0
* Use stxa_sync() when accessing the diagnostic registers to invalidateThomas Moestl2002-02-131-22/+21
* Implement dcache_inval_phys, which shoots the cache lines that correspondJake Burkholder2001-12-291-4/+29
* 1. Split fp.h into fp.h and fsr.h so that the latter can be includedJake Burkholder2001-11-181-0/+1
* Add cache handling code for sparc64.Thomas Moestl2001-11-091-0/+405