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authorPawel Pekala <pawel@FreeBSD.org>2011-10-30 12:42:28 +0000
committerPawel Pekala <pawel@FreeBSD.org>2011-10-30 12:42:28 +0000
commit7149ddb9e9bf63cbade14ce97240b1bf7fe54eff (patch)
treeb70e194d7f1ac7da5e45d7490883e6eddf35c3ad /cad/iverilog
parent3c2476fa4bb8cf6daf4c64dc57e19049933175bd (diff)
downloadports-7149ddb9e9bf63cbade14ce97240b1bf7fe54eff.tar.gz
ports-7149ddb9e9bf63cbade14ce97240b1bf7fe54eff.zip
- Update to version 0.9.4
- Give maintainership to submitter PR: ports/162069 Submitted by: Niclas Zeising <niclas.zeising@gmail.com>
Notes
Notes: svn path=/head/; revision=284713
Diffstat (limited to 'cad/iverilog')
-rw-r--r--cad/iverilog/Makefile5
-rw-r--r--cad/iverilog/distinfo4
2 files changed, 4 insertions, 5 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index bfed7bb7bb0a..21b72674f0cf 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -7,14 +7,13 @@
#
PORTNAME= iverilog
-PORTVERSION= 0.9.2
-PORTREVISION= 0
+PORTVERSION= 0.9.4
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
ftp://ftp.geda.seul.org/pub/geda/dist/
DISTNAME= verilog-${PORTVERSION}
-MAINTAINER= ports@FreeBSD.org
+MAINTAINER= niclas.zeising@gmail.com
COMMENT= A Verilog simulation and synthesis tool
GNU_CONFIGURE= yes
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index e9a2af230217..7f3d37efdf4c 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,2 +1,2 @@
-SHA256 (verilog-0.9.2.tar.gz) = 321b6f32b5608d7cdd745a9ff8e21f3e2ec1feba9f0e3f92d8bd7042d80647c3
-SIZE (verilog-0.9.2.tar.gz) = 1127067
+SHA256 (verilog-0.9.4.tar.gz) = b4eac7276975cf2d7c2c94246f733dc187feb4d5944034d053c5094279511eb1
+SIZE (verilog-0.9.4.tar.gz) = 1200614