diff options
Diffstat (limited to 'gas/testsuite/gas/arm')
155 files changed, 9338 insertions, 575 deletions
diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d index 0fdaa8fdecbe..f7e343f03bc1 100644 --- a/gas/testsuite/gas/arm/arch4t.d +++ b/gas/testsuite/gas/arm/arch4t.d @@ -11,14 +11,14 @@ Disassembly of section .text: 0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! -0+18 <[^>]+> 011510d3 ? ldreqsb r1, \[r5, -r3\] -0+1c <[^>]+> 109620b7 ? ldrneh r2, \[r6\], r7 -0+20 <[^>]+> 309720f8 ? ldrccsh r2, \[r7\], r8 +0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] +0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 +0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\] 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\] 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\] 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strneh r3, \[r3\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d index 992948b83314..9cf73edf1891 100644 --- a/gas/testsuite/gas/arm/arch7.d +++ b/gas/testsuite/gas/arm/arch7.d @@ -1,6 +1,5 @@ #name: ARM V7 instructions #as: -march=armv7r -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* #objdump: -dr --prefix-addresses --show-raw-insn .*: +file format .*arm.* @@ -29,8 +28,8 @@ Disassembly of section .text: 0+050 <[^>]*> f995 f000 pli \[r5\] 0+054 <[^>]*> f995 ffff pli \[r5, #4095\] 0+058 <[^>]*> f915 fcff pli \[r5, #-255\] -0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0000105f <[^>]*> -0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; fffff065 <[^>]*> +0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*> +0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*> 0+064 <[^>]*> f3af 80f0 dbg #0 0+068 <[^>]*> f3af 80ff dbg #15 0+06c <[^>]*> f3bf 8f5f dmb sy diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d index 1dbaad3a714f..6015a4707ec9 100644 --- a/gas/testsuite/gas/arm/archv6.d +++ b/gas/testsuite/gas/arm/archv6.d @@ -13,13 +13,13 @@ Disassembly of section .text: 0+014 <[^>]*> fc4570c3 ? mcrr2 0, 12, r7, r5, cr3 0+018 <[^>]*> fc5570c3 ? mrrc2 0, 12, r7, r5, cr3 0+01c <[^>]*> e6852018 ? pkhbt r2, r5, r8 -0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, LSL #3 +0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, lsl #3 0+02c <[^>]*> e6882015 ? pkhbt r2, r8, r5 -0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, ASR #3 +0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, asr #3 0+03c <[^>]*> e6242f17 ? qadd16 r2, r4, r7 0+040 <[^>]*> 16242f17 ? qadd16ne r2, r4, r7 0+044 <[^>]*> e6242f97 ? qadd8 r2, r4, r7 @@ -49,19 +49,19 @@ Disassembly of section .text: 0+0a4 <[^>]*> e6142f17 ? sadd16 r2, r4, r7 0+0a8 <[^>]*> 16142f17 ? sadd16ne r2, r4, r7 0+0ac <[^>]*> e6b42075 ? sxtah r2, r4, r5 -0+0b0 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ROR #8 +0+0b0 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ror #8 0+0b4 <[^>]*> 16b42075 ? sxtahne r2, r4, r5 -0+0b8 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ROR #8 +0+0b8 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ror #8 0+0bc <[^>]*> e6142f97 ? sadd8 r2, r4, r7 0+0c0 <[^>]*> 16142f97 ? sadd8ne r2, r4, r7 0+0c4 <[^>]*> e6842075 ? sxtab16 r2, r4, r5 -0+0c8 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ROR #8 +0+0c8 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ror #8 0+0cc <[^>]*> 16842075 ? sxtab16ne r2, r4, r5 -0+0d0 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ROR #8 +0+0d0 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ror #8 0+0d4 <[^>]*> e6a42075 ? sxtab r2, r4, r5 -0+0d8 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ROR #8 +0+0d8 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ror #8 0+0dc <[^>]*> 16a42075 ? sxtabne r2, r4, r5 -0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8 +0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ror #8 0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7 0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7 0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3 @@ -116,11 +116,11 @@ Disassembly of section .text: 0+1b0 <[^>]*> d701f352 ? smusdle r1, r2, r3 0+1b4 <[^>]*> e701f372 ? smusdx r1, r2, r3 0+1b8 <[^>]*> d701f372 ? smusdxle r1, r2, r3 -0+1bc <[^>]*> f8cd0510 ? srsia #16 -0+1c0 <[^>]*> f9ed0510 ? srsib #16! +0+1bc <[^>]*> f8cd0510 ? srsia sp, #16 +0+1c0 <[^>]*> f9ed0510 ? srsib sp!, #16 0+1c4 <[^>]*> e6a01012 ? ssat r1, #1, r2 -0+1c8 <[^>]*> e6a01152 ? ssat r1, #1, r2, ASR #2 -0+1cc <[^>]*> e6a01112 ? ssat r1, #1, r2, LSL #2 +0+1c8 <[^>]*> e6a01152 ? ssat r1, #1, r2, asr #2 +0+1cc <[^>]*> e6a01112 ? ssat r1, #1, r2, lsl #2 0+1d0 <[^>]*> e6a01f31 ? ssat16 r1, #1, r1 0+1d4 <[^>]*> d6a01f31 ? ssat16le r1, #1, r1 0+1d8 <[^>]*> e6142f77 ? ssub16 r2, r4, r7 @@ -131,34 +131,34 @@ Disassembly of section .text: 0+1ec <[^>]*> 16142f57 ? ssubaddxne r2, r4, r7 0+1f0 <[^>]*> e1831f92 ? strex r1, r2, \[r3\] 0+1f4 <[^>]*> 11831f92 ? strexne r1, r2, \[r3\] -0+1f8 <[^>]*> e6bf2075 ? sxth r2,r5 -0+1fc <[^>]*> e6bf2475 ? sxth r2,r5, ROR #8 -0+200 <[^>]*> 16bf2075 ? sxthne r2,r5 -0+204 <[^>]*> 16bf2475 ? sxthne r2,r5, ROR #8 -0+208 <[^>]*> e68f2075 ? sxtb16 r2,r5 -0+20c <[^>]*> e68f2475 ? sxtb16 r2,r5, ROR #8 -0+210 <[^>]*> 168f2075 ? sxtb16ne r2,r5 -0+214 <[^>]*> 168f2475 ? sxtb16ne r2,r5, ROR #8 -0+218 <[^>]*> e6af2075 ? sxtb r2,r5 -0+21c <[^>]*> e6af2475 ? sxtb r2,r5, ROR #8 -0+220 <[^>]*> 16af2075 ? sxtbne r2,r5 -0+224 <[^>]*> 16af2475 ? sxtbne r2,r5, ROR #8 +0+1f8 <[^>]*> e6bf2075 ? sxth r2, r5 +0+1fc <[^>]*> e6bf2475 ? sxth r2, r5, ror #8 +0+200 <[^>]*> 16bf2075 ? sxthne r2, r5 +0+204 <[^>]*> 16bf2475 ? sxthne r2, r5, ror #8 +0+208 <[^>]*> e68f2075 ? sxtb16 r2, r5 +0+20c <[^>]*> e68f2475 ? sxtb16 r2, r5, ror #8 +0+210 <[^>]*> 168f2075 ? sxtb16ne r2, r5 +0+214 <[^>]*> 168f2475 ? sxtb16ne r2, r5, ror #8 +0+218 <[^>]*> e6af2075 ? sxtb r2, r5 +0+21c <[^>]*> e6af2475 ? sxtb r2, r5, ror #8 +0+220 <[^>]*> 16af2075 ? sxtbne r2, r5 +0+224 <[^>]*> 16af2475 ? sxtbne r2, r5, ror #8 0+228 <[^>]*> e6542f17 ? uadd16 r2, r4, r7 0+22c <[^>]*> 16542f17 ? uadd16ne r2, r4, r7 0+230 <[^>]*> e6f32075 ? uxtah r2, r3, r5 -0+234 <[^>]*> e6f32475 ? uxtah r2, r3, r5, ROR #8 +0+234 <[^>]*> e6f32475 ? uxtah r2, r3, r5, ror #8 0+238 <[^>]*> 16f32075 ? uxtahne r2, r3, r5 -0+23c <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ROR #8 +0+23c <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ror #8 0+240 <[^>]*> e6542f97 ? uadd8 r2, r4, r7 0+244 <[^>]*> 16542f97 ? uadd8ne r2, r4, r7 0+248 <[^>]*> e6c32075 ? uxtab16 r2, r3, r5 -0+24c <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ROR #8 +0+24c <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ror #8 0+250 <[^>]*> 16c32075 ? uxtab16ne r2, r3, r5 -0+254 <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ROR #8 +0+254 <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ror #8 0+258 <[^>]*> e6e32075 ? uxtab r2, r3, r5 -0+25c <[^>]*> e6e32475 ? uxtab r2, r3, r5, ROR #8 +0+25c <[^>]*> e6e32475 ? uxtab r2, r3, r5, ror #8 0+260 <[^>]*> 16e32075 ? uxtabne r2, r3, r5 -0+264 <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ROR #8 +0+264 <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ror #8 0+268 <[^>]*> e6542f37 ? uaddsubx r2, r4, r7 0+26c <[^>]*> 16542f37 ? uaddsubxne r2, r4, r7 0+270 <[^>]*> e6742f17 ? uhadd16 r2, r4, r7 @@ -192,28 +192,32 @@ Disassembly of section .text: 0+2e0 <[^>]*> e7814312 ? usada8 r1, r2, r3, r4 0+2e4 <[^>]*> 17814312 ? usada8ne r1, r2, r3, r4 0+2e8 <[^>]*> e6ef1012 ? usat r1, #15, r2 -0+2ec <[^>]*> e6ef1252 ? usat r1, #15, r2, ASR #4 -0+2f0 <[^>]*> e6ef1212 ? usat r1, #15, r2, LSL #4 +0+2ec <[^>]*> e6ef1252 ? usat r1, #15, r2, asr #4 +0+2f0 <[^>]*> e6ef1212 ? usat r1, #15, r2, lsl #4 0+2f4 <[^>]*> e6ef1f32 ? usat16 r1, #15, r2 0+2f8 <[^>]*> d6ef1f32 ? usat16le r1, #15, r2 0+2fc <[^>]*> d6ef1012 ? usatle r1, #15, r2 -0+300 <[^>]*> d6ef1252 ? usatle r1, #15, r2, ASR #4 -0+304 <[^>]*> d6ef1212 ? usatle r1, #15, r2, LSL #4 +0+300 <[^>]*> d6ef1252 ? usatle r1, #15, r2, asr #4 +0+304 <[^>]*> d6ef1212 ? usatle r1, #15, r2, lsl #4 0+308 <[^>]*> e6542f77 ? usub16 r2, r4, r7 0+30c <[^>]*> 16542f77 ? usub16ne r2, r4, r7 0+310 <[^>]*> e6542ff7 ? usub8 r2, r4, r7 0+314 <[^>]*> 16542ff7 ? usub8ne r2, r4, r7 0+318 <[^>]*> e6542f57 ? usubaddx r2, r4, r7 0+31c <[^>]*> 16542f57 ? usubaddxne r2, r4, r7 -0+320 <[^>]*> e6ff2075 ? uxth r2,r5 -0+324 <[^>]*> e6ff2475 ? uxth r2,r5, ROR #8 -0+328 <[^>]*> 16ff2075 ? uxthne r2,r5 -0+32c <[^>]*> 16ff2475 ? uxthne r2,r5, ROR #8 -0+330 <[^>]*> e6cf2075 ? uxtb16 r2,r5 -0+334 <[^>]*> e6cf2475 ? uxtb16 r2,r5, ROR #8 -0+338 <[^>]*> 16cf2075 ? uxtb16ne r2,r5 -0+33c <[^>]*> 16cf2475 ? uxtb16ne r2,r5, ROR #8 -0+340 <[^>]*> e6ef2075 ? uxtb r2,r5 -0+344 <[^>]*> e6ef2475 ? uxtb r2,r5, ROR #8 -0+348 <[^>]*> 16ef2075 ? uxtbne r2,r5 -0+34c <[^>]*> 16ef2475 ? uxtbne r2,r5, ROR #8 +0+320 <[^>]*> e6ff2075 ? uxth r2, r5 +0+324 <[^>]*> e6ff2475 ? uxth r2, r5, ror #8 +0+328 <[^>]*> 16ff2075 ? uxthne r2, r5 +0+32c <[^>]*> 16ff2475 ? uxthne r2, r5, ror #8 +0+330 <[^>]*> e6cf2075 ? uxtb16 r2, r5 +0+334 <[^>]*> e6cf2475 ? uxtb16 r2, r5, ror #8 +0+338 <[^>]*> 16cf2075 ? uxtb16ne r2, r5 +0+33c <[^>]*> 16cf2475 ? uxtb16ne r2, r5, ror #8 +0+340 <[^>]*> e6ef2075 ? uxtb r2, r5 +0+344 <[^>]*> e6ef2475 ? uxtb r2, r5, ror #8 +0+348 <[^>]*> 16ef2075 ? uxtbne r2, r5 +0+34c <[^>]*> 16ef2475 ? uxtbne r2, r5, ror #8 +0+350 <[^>]*> f10a00ca ? cpsie if,#10 +0+354 <[^>]*> f10a00d5 ? cpsie if,#21 +0+358 <[^>]*> f8cd0510 ? srsia sp, #16 +0+35c <[^>]*> f9ed0510 ? srsib sp!, #16 diff --git a/gas/testsuite/gas/arm/archv6.s b/gas/testsuite/gas/arm/archv6.s index 50378b7c3798..85f05c185d02 100644 --- a/gas/testsuite/gas/arm/archv6.s +++ b/gas/testsuite/gas/arm/archv6.s @@ -214,3 +214,7 @@ label: uxtb r2, r5, ROR #8 uxtbne r2, r5 uxtbne r2, r5, ROR #8 + cpsie if, #10 + cpsie if, #21 + srsia sp, #16 + srsib sp!, #16 diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d index 8e8b0387a336..e6e57c843b90 100644 --- a/gas/testsuite/gas/arm/archv6t2.d +++ b/gas/testsuite/gas/arm/archv6t2.d @@ -24,10 +24,10 @@ Disassembly of section .text: 0+40 <[^>]+> e7a00059 sbfx r0, r9, #0, #1 0+44 <[^>]+> e7a008d0 sbfx r0, r0, #17, #1 0+48 <[^>]+> e7b10050 sbfx r0, r0, #0, #18 -0+4c <[^>]+> e3ff0f30 rbit r0, r0 -0+50 <[^>]+> 13ff0f30 rbitne r0, r0 -0+54 <[^>]+> e3ff9f30 rbit r9, r0 -0+58 <[^>]+> e3ff0f39 rbit r0, r9 +0+4c <[^>]+> e6ff0f30 rbit r0, r0 +0+50 <[^>]+> 16ff0f30 rbitne r0, r0 +0+54 <[^>]+> e6ff9f30 rbit r9, r0 +0+58 <[^>]+> e6ff0f39 rbit r0, r9 0+5c <[^>]+> e0600090 mls r0, r0, r0, r0 0+60 <[^>]+> 10600090 mlsne r0, r0, r0, r0 0+64 <[^>]+> e0690090 mls r9, r0, r0, r0 @@ -44,7 +44,7 @@ Disassembly of section .text: 0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\] 0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\] 0+98 <[^>]+> e0e900b0 strht r0, \[r9\] -0+9c <[^>]+> 10f900b0 ldrneht r0, \[r9\] +0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\] 0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153 diff --git a/gas/testsuite/gas/arm/arm-it.d b/gas/testsuite/gas/arm/arm-it.d new file mode 100644 index 000000000000..674f815f1dec --- /dev/null +++ b/gas/testsuite/gas/arm/arm-it.d @@ -0,0 +1,9 @@ +#name: ARM IT instruction +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 +0+004 <[^>]*> e1a0f00e ? mov pc, lr diff --git a/gas/testsuite/gas/arm/arm-it.s b/gas/testsuite/gas/arm/arm-it.s new file mode 100644 index 000000000000..f3c56e8c4b70 --- /dev/null +++ b/gas/testsuite/gas/arm/arm-it.s @@ -0,0 +1,8 @@ + # Check that IT is accepted in ARM mode on older architectures + .text + .syntax unified + .arch armv4 +label1: + it eq + moveq r0, #0 + mov pc, lr diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d index 06323b1c0cdf..41b6b7eb8fdc 100644 --- a/gas/testsuite/gas/arm/arm3.d +++ b/gas/testsuite/gas/arm/arm3.d @@ -7,5 +7,5 @@ Disassembly of section .text: 0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\] 0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\] -0+8 <[^>]*> a1454091 ? swpgeb r4, r1, \[r5\] +0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\] 0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d index ef47ca6c6689..43f64204e97a 100644 --- a/gas/testsuite/gas/arm/arm7dm.d +++ b/gas/testsuite/gas/arm/arm7dm.d @@ -11,7 +11,7 @@ Disassembly of section .text: 0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3 0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4 0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp -0+18 <[^>]+> 00b92994 ? umlaleqs r2, r9, r4, r9 +0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9 0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr 0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0 0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d index 17e4e9d4fb5e..37abd7a7781f 100644 --- a/gas/testsuite/gas/arm/arm7t.d +++ b/gas/testsuite/gas/arm/arm7t.d @@ -49,20 +49,20 @@ Disassembly of section .text: 0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*> 0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*> 0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+a8 <[^>]*> 119100b2 ? ldrneh r0, \[r1, r2\] -0+ac <[^>]*> 819100b2 ? ldrhih r0, \[r1, r2\] -0+b0 <[^>]*> b19100b2 ? ldrlth r0, \[r1, r2\] +0+a8 <[^>]*> 119100b2 ? ldrhne r0, \[r1, r2\] +0+ac <[^>]*> 819100b2 ? ldrhhi r0, \[r1, r2\] +0+b0 <[^>]*> b19100b2 ? ldrhlt r0, \[r1, r2\] 0+b4 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+b8 <[^>]*> 119100f2 ? ldrnesh r0, \[r1, r2\] -0+bc <[^>]*> 819100f2 ? ldrhish r0, \[r1, r2\] -0+c0 <[^>]*> b19100f2 ? ldrltsh r0, \[r1, r2\] +0+b8 <[^>]*> 119100f2 ? ldrshne r0, \[r1, r2\] +0+bc <[^>]*> 819100f2 ? ldrshhi r0, \[r1, r2\] +0+c0 <[^>]*> b19100f2 ? ldrshlt r0, \[r1, r2\] 0+c4 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+c8 <[^>]*> 119100d2 ? ldrnesb r0, \[r1, r2\] -0+cc <[^>]*> 819100d2 ? ldrhisb r0, \[r1, r2\] -0+d0 <[^>]*> b19100d2 ? ldrltsb r0, \[r1, r2\] +0+c8 <[^>]*> 119100d2 ? ldrsbne r0, \[r1, r2\] +0+cc <[^>]*> 819100d2 ? ldrsbhi r0, \[r1, r2\] +0+d0 <[^>]*> b19100d2 ? ldrsblt r0, \[r1, r2\] 0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*> 0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*> -0+dc <[^>]*> 00000000 ? andeq r0, r0, r0 +0+dc <[^>]*> 00000000 ? .* [ ]*dc:.*fred 0+e0 <[^>]*> 0000c0de ? .* 0+e4 <[^>]*> 0000dead ? .* diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 4e4c91376179..99e8471e2222 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -1,6 +1,7 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: ARM v1 instructions #as: -mcpu=arm7t +#error-output: armv1.l # Test the ARM v1 instructions @@ -52,19 +53,19 @@ Disassembly of section .text: 0+a8 <[^>]*> e5c00000 ? strb r0, \[r0\] 0+ac <[^>]*> e4a10000 ? strt r0, \[r1\] 0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\] -0+b4 <[^>]*> e8800001 ? stmia r0, {r0} +0+b4 <[^>]*> e8800001 ? stm r0, {r0} 0+b8 <[^>]*> e9800001 ? stmib r0, {r0} 0+bc <[^>]*> e8000001 ? stmda r0, {r0} 0+c0 <[^>]*> e9000001 ? stmdb r0, {r0} 0+c4 <[^>]*> e9000001 ? stmdb r0, {r0} 0+c8 <[^>]*> e9800001 ? stmib r0, {r0} -0+cc <[^>]*> e8800001 ? stmia r0, {r0} +0+cc <[^>]*> e8800001 ? stm r0, {r0} 0+d0 <[^>]*> e8000001 ? stmda r0, {r0} -0+d4 <[^>]*> e8900001 ? ldmia r0, {r0} +0+d4 <[^>]*> e8900001 ? ldm r0, {r0} 0+d8 <[^>]*> e9900001 ? ldmib r0, {r0} 0+dc <[^>]*> e8100001 ? ldmda r0, {r0} 0+e0 <[^>]*> e9100001 ? ldmdb r0, {r0} -0+e4 <[^>]*> e8900001 ? ldmia r0, {r0} +0+e4 <[^>]*> e8900001 ? ldm r0, {r0} 0+e8 <[^>]*> e8100001 ? ldmda r0, {r0} 0+ec <[^>]*> e9100001 ? ldmdb r0, {r0} 0+f0 <[^>]*> e9900001 ? ldmib r0, {r0} diff --git a/gas/testsuite/gas/arm/armv1.l b/gas/testsuite/gas/arm/armv1.l new file mode 100644 index 000000000000..369f9d4a5105 --- /dev/null +++ b/gas/testsuite/gas/arm/armv1.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:26: Warning: s suffix on comparison instruction is deprecated +[^:]*:29: Warning: s suffix on comparison instruction is deprecated +[^:]*:32: Warning: s suffix on comparison instruction is deprecated +[^:]*:35: Warning: s suffix on comparison instruction is deprecated diff --git a/gas/testsuite/gas/arm/backslash-at.d b/gas/testsuite/gas/arm/backslash-at.d new file mode 100644 index 000000000000..a8992bdb4fac --- /dev/null +++ b/gas/testsuite/gas/arm/backslash-at.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Backslash-at for ARM + +.*: file format .*arm.* + +Disassembly of section .text: +0+000 <.*>.*615c.* +0+002 <foo> e3a00000 mov r0, #0 ; 0x0 +0+006 <foo\+0x4> e3a00000 mov r0, #0 ; 0x0 +0+00a <foo\+0x8> e3a00000 mov r0, #0 ; 0x0 +0+00e <foo\+0xc> e3a00001 mov r0, #1 ; 0x1 +0+012 <foo\+0x10> e3a00001 mov r0, #1 ; 0x1 +0+016 <foo\+0x14> e3a00001 mov r0, #1 ; 0x1 +0+01a <foo\+0x18> e3a00002 mov r0, #2 ; 0x2 +0+01e <foo\+0x1c> e3a00002 mov r0, #2 ; 0x2 +0+022 <foo\+0x20> e3a00002 mov r0, #2 ; 0x2 +#... diff --git a/gas/testsuite/gas/arm/backslash-at.s b/gas/testsuite/gas/arm/backslash-at.s new file mode 100644 index 000000000000..4975aea688f8 --- /dev/null +++ b/gas/testsuite/gas/arm/backslash-at.s @@ -0,0 +1,16 @@ +@ Check that \@ is not destroyed when assembling for the ARM. + +.macro bar + mov r0, #\@ + mov r0, #\@@comment + mov r0, #\@ @comment +.endm + +.byte '\\ +.byte '\a + +foo: + bar + bar + bar + diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d index 5f5dd110e99a..37d0f2d6fdb5 100644 --- a/gas/testsuite/gas/arm/copro.d +++ b/gas/testsuite/gas/arm/copro.d @@ -12,7 +12,7 @@ Disassembly of section .text: 0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] 0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] 0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]! -0+014 <[^>]*> 5cf31710 ldcpll 7, cr1, \[r3\], #64 +0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64 0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] 0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] 0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] @@ -31,7 +31,7 @@ Disassembly of section .text: 0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\} 0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\} 0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\} -0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\} +0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\} 0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\} 0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4 0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s index 334b000f4409..e6976329c756 100644 --- a/gas/testsuite/gas/arm/copro.s +++ b/gas/testsuite/gas/arm/copro.s @@ -33,7 +33,8 @@ bar: stcl p8, c2, [r5], {5} ldc2l 9, c1, [r6], {6} stc2l p10, c0, [r7], {7} - ldcl 11, c8, [r8], {255} + @ using '11' below results in an (invalid) Neon vldmia instruction. + ldcl 12, c8, [r8], {255} stcl p12, c9, [r9], {254} mrrc 13, 0, r7, r0, cr4 mcrr p14, 0, r7, r0, cr5 diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d new file mode 100644 index 000000000000..e10a6a7589ba --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-alu-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l new file mode 100644 index 000000000000..fe8827cec78b --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l @@ -0,0 +1,81 @@ +[^:]*: Assembler messages: +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s new file mode 100644 index 000000000000..bdde4ad45068 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s @@ -0,0 +1,35 @@ +@ Tests that should fail for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym + \offset) + \insn r0, r0, #:pc_g1:(\sym + \offset) + \insn r0, r0, #:pc_g2:(\sym + \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym + \offset) + \insn r0, r0, #:pc_g1_nc:(\sym + \offset) + + \insn r0, r0, #:sb_g0:(\sym + \offset) + \insn r0, r0, #:sb_g1:(\sym + \offset) + \insn r0, r0, #:sb_g2:(\sym + \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym + \offset) + \insn r0, r0, #:sb_g1_nc:(\sym + \offset) + + .endm + + alutest add f 0x11001 + alutest add localsym 0x11001 + alutest adds f 0x11001 + alutest adds localsym 0x11001 + + alutest add f "-0x11001" + alutest add localsym "-0x11001" + alutest adds f "-0x11001" + alutest adds localsym "-0x11001" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d new file mode 100644 index 000000000000..808bc05f0805 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-alu-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l new file mode 100644 index 000000000000..1c27ad02ffc9 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)' +[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)' +[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)' +[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)' diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s new file mode 100644 index 000000000000..70a62acefa60 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s @@ -0,0 +1,12 @@ +@ Tests that should fail for ALU group relocations. + + .text + +@ Group relocs aren't allowed on SUB(S) instructions... + sub r0, r0, #:pc_g0:(foo) + subs r0, r0, #:pc_g0:(foo) + +@ Some nonexistent relocations: + add r0, r0, #:pc_g2_nc:(foo) + add r0, r0, #:sb_g2_nc:(foo) + diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d new file mode 100644 index 000000000000..40e502588375 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.d @@ -0,0 +1,168 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (alu) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 10: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 14: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 18: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 1c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 20: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 24: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 28: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 2c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 30: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 34: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 38: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 3c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 40: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 44: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 48: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 50: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 54: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 58: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 5c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 60: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 64: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 68: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 6c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 70: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 74: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 78: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 7c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 80: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 84: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 88: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 8c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 90: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 94: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 98: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 9c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ac: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b0: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b4: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b8: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + bc: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c0: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c4: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c8: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + cc: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d0: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d4: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d8: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + dc: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e0: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e4: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e8: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ec: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + fc: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 100: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 104: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 108: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 10c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 110: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 114: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 118: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 11c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 120: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 124: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 128: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 12c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 130: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 134: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 138: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 13c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-alu.s b/gas/testsuite/gas/arm/group-reloc-alu.s new file mode 100644 index 000000000000..696f1dac0cc4 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.s @@ -0,0 +1,39 @@ +@ Tests for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym \offset) + \insn r0, r0, #:pc_g1:(\sym \offset) + +@ Try this one without the hash; it should still work. + \insn r0, r0, :pc_g2:(\sym \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym \offset) + \insn r0, r0, #:pc_g1_nc:(\sym \offset) + + \insn r0, r0, #:sb_g0:(\sym \offset) + \insn r0, r0, #:sb_g1:(\sym \offset) + \insn r0, r0, #:sb_g2:(\sym \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym \offset) + \insn r0, r0, #:sb_g1_nc:(\sym \offset) + + .endm + + alutest add f "+ 0x100" + alutest add localsym "+ 0x100" + alutest adds f "+ 0x100" + alutest adds localsym "+ 0x100" + +@ The following should cause the insns to be switched to SUB(S). + + alutest add f "- 0x100" + alutest add localsym "- 0x100" + alutest adds f "- 0x100" + alutest adds localsym "- 0x100" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d new file mode 100644 index 000000000000..52ee2e55b653 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldc-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l new file mode 100644 index 000000000000..22e53a5901d6 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l @@ -0,0 +1,721 @@ +[^:]*: Assembler messages: +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s new file mode 100644 index 000000000000..5ab27c25fb7a --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s @@ -0,0 +1,169 @@ +@ LDC group relocation tests that are supposed to fail during encoding. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store cst + + \load 0, c0, [r0, #:pc_g0:(f + \cst)] + \load 0, c0, [r0, #:pc_g1:(f + \cst)] + \load 0, c0, [r0, #:pc_g2:(f + \cst)] + + \load 0, c0, [r0, #:sb_g0:(f + \cst)] + \load 0, c0, [r0, #:sb_g1:(f + \cst)] + \load 0, c0, [r0, #:sb_g2:(f + \cst)] + + \store 0, c0, [r0, #:pc_g0:(f + \cst)] + \store 0, c0, [r0, #:pc_g1:(f + \cst)] + \store 0, c0, [r0, #:pc_g2:(f + \cst)] + + \store 0, c0, [r0, #:sb_g0:(f + \cst)] + \store 0, c0, [r0, #:sb_g1:(f + \cst)] + \store 0, c0, [r0, #:sb_g2:(f + \cst)] + + \load 0, c0, [r0, #:pc_g0:(f - \cst)] + \load 0, c0, [r0, #:pc_g1:(f - \cst)] + \load 0, c0, [r0, #:pc_g2:(f - \cst)] + + \load 0, c0, [r0, #:sb_g0:(f - \cst)] + \load 0, c0, [r0, #:sb_g1:(f - \cst)] + \load 0, c0, [r0, #:sb_g2:(f - \cst)] + + \store 0, c0, [r0, #:pc_g0:(f - \cst)] + \store 0, c0, [r0, #:pc_g1:(f - \cst)] + \store 0, c0, [r0, #:pc_g2:(f - \cst)] + + \store 0, c0, [r0, #:sb_g0:(f - \cst)] + \store 0, c0, [r0, #:sb_g1:(f - \cst)] + \store 0, c0, [r0, #:sb_g2:(f - \cst)] + + .endm + + ldctest ldc stc 0x1 + ldctest ldcl stcl 0x1 + ldctest ldc2 stc2 0x1 + ldctest ldc2l stc2l 0x1 + + ldctest ldc stc 0x808 + ldctest ldcl stcl 0x808 + ldctest ldc2 stc2 0x808 + ldctest ldc2l stc2l 0x808 + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store cst + + \load f0, [r0, #:pc_g0:(f + \cst)] + \load f0, [r0, #:pc_g1:(f + \cst)] + \load f0, [r0, #:pc_g2:(f + \cst)] + + \load f0, [r0, #:sb_g0:(f + \cst)] + \load f0, [r0, #:sb_g1:(f + \cst)] + \load f0, [r0, #:sb_g2:(f + \cst)] + + \store f0, [r0, #:pc_g0:(f + \cst)] + \store f0, [r0, #:pc_g1:(f + \cst)] + \store f0, [r0, #:pc_g2:(f + \cst)] + + \store f0, [r0, #:sb_g0:(f + \cst)] + \store f0, [r0, #:sb_g1:(f + \cst)] + \store f0, [r0, #:sb_g2:(f + \cst)] + + \load f0, [r0, #:pc_g0:(f - \cst)] + \load f0, [r0, #:pc_g1:(f - \cst)] + \load f0, [r0, #:pc_g2:(f - \cst)] + + \load f0, [r0, #:sb_g0:(f - \cst)] + \load f0, [r0, #:sb_g1:(f - \cst)] + \load f0, [r0, #:sb_g2:(f - \cst)] + + \store f0, [r0, #:pc_g0:(f - \cst)] + \store f0, [r0, #:pc_g1:(f - \cst)] + \store f0, [r0, #:pc_g2:(f - \cst)] + + \store f0, [r0, #:sb_g0:(f - \cst)] + \store f0, [r0, #:sb_g1:(f - \cst)] + \store f0, [r0, #:sb_g2:(f - \cst)] + + .endm + + fpa_test ldfs stfs 0x1 + fpa_test ldfd stfd 0x1 + fpa_test ldfe stfe 0x1 + fpa_test ldfp stfp 0x1 + + fpa_test ldfs stfs 0x808 + fpa_test ldfd stfd 0x808 + fpa_test ldfe stfe 0x808 + fpa_test ldfp stfp 0x808 + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg cst + + \load \reg, [r0, #:pc_g0:(f + \cst)] + \load \reg, [r0, #:pc_g1:(f + \cst)] + \load \reg, [r0, #:pc_g2:(f + \cst)] + + \load \reg, [r0, #:sb_g0:(f + \cst)] + \load \reg, [r0, #:sb_g1:(f + \cst)] + \load \reg, [r0, #:sb_g2:(f + \cst)] + + \store \reg, [r0, #:pc_g0:(f + \cst)] + \store \reg, [r0, #:pc_g1:(f + \cst)] + \store \reg, [r0, #:pc_g2:(f + \cst)] + + \store \reg, [r0, #:sb_g0:(f + \cst)] + \store \reg, [r0, #:sb_g1:(f + \cst)] + \store \reg, [r0, #:sb_g2:(f + \cst)] + + \load \reg, [r0, #:pc_g0:(f - \cst)] + \load \reg, [r0, #:pc_g1:(f - \cst)] + \load \reg, [r0, #:pc_g2:(f - \cst)] + + \load \reg, [r0, #:sb_g0:(f - \cst)] + \load \reg, [r0, #:sb_g1:(f - \cst)] + \load \reg, [r0, #:sb_g2:(f - \cst)] + + \store \reg, [r0, #:pc_g0:(f - \cst)] + \store \reg, [r0, #:pc_g1:(f - \cst)] + \store \reg, [r0, #:pc_g2:(f - \cst)] + + \store \reg, [r0, #:sb_g0:(f - \cst)] + \store \reg, [r0, #:sb_g1:(f - \cst)] + \store \reg, [r0, #:sb_g2:(f - \cst)] + + .endm + + vfp_test flds fsts s0 0x1 + vfp_test flds fsts s0 0x808 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 0x1 + vfp_test fldd fstd d0 0x808 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 0x1 + vfp_test vldr vstr d0 0x808 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 0x1 + vfp_test cfldrd cfstrd mvd0 0x1 + vfp_test cfldr32 cfstr32 mvfx0 0x1 + vfp_test cfldr64 cfstr64 mvdx0 0x1 + + vfp_test cfldrs cfstrs mvf0 0x808 + vfp_test cfldrd cfstrd mvd0 0x808 + vfp_test cfldr32 cfstr32 mvfx0 0x808 + vfp_test cfldr64 cfstr64 mvdx0 0x808 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d new file mode 100644 index 000000000000..09e32997e855 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldc-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l new file mode 100644 index 000000000000..238d94db1d94 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l @@ -0,0 +1,147 @@ +[^:]*: Assembler messages: +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:54: Error: too many positional arguments +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s new file mode 100644 index 000000000000..a815f5de75b5 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s @@ -0,0 +1,67 @@ +@ Tests for LDC group relocations that are meant to fail during parsing. + + .macro ldctest insn reg + + \insn 0, \reg, [r0, #:pc_g0_nc:(sym)] + \insn 0, \reg, [r0, #:pc_g1_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g0_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g1_nc:(sym)] + + \insn 0, \reg, [r0, #:foo:(sym)] + + .endm + + .macro ldctest2 insn reg + + \insn \reg, [r0, #:pc_g0_nc:(sym)] + \insn \reg, [r0, #:pc_g1_nc:(sym)] + \insn \reg, [r0, #:sb_g0_nc:(sym)] + \insn \reg, [r0, #:sb_g1_nc:(sym)] + + \insn \reg, [r0, #:foo:(sym)] + + .endm + + ldctest ldc c0 + ldctest ldcl c0 + ldctest ldc2 c0 + ldctest ldc2l c0 + + ldctest stc c0 + ldctest stcl c0 + ldctest stc2 c0 + ldctest stc2l c0 + + .fpu fpa + + ldctest2 ldfs f0 + ldctest2 stfs f0 + ldctest2 ldfd f0 + ldctest2 stfd f0 + ldctest2 ldfe f0 + ldctest2 stfe f0 + ldctest2 ldfp f0 + ldctest2 stfp f0 + + .fpu vfp + + ldctest2 flds s0 + ldctest2 fsts s0 + + ldctest2 fldd d0 + ldctest2 fstd d0 + + ldctest2 vldr d0 FIXME + ldctest2 vstr d0 + + .cpu ep9312 + + ldctest2 cfldrs mvf0 + ldctest2 cfstrs mvf0 + ldctest2 cfldrd mvd0 + ldctest2 cfstrd mvd0 + ldctest2 cfldr32 mvfx0 + ldctest2 cfstr32 mvfx0 + ldctest2 cfldr64 mvdx0 + ldctest2 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/arm/group-reloc-ldc.d new file mode 100644 index 000000000000..731a025f0441 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.d @@ -0,0 +1,727 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldc) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 10: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 14: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 18: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 1c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 20: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 24: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 28: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 2c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 30: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 34: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 38: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 3c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 40: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 44: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 48: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 4c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 50: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 54: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 58: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 5c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 60: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 64: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 68: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 6c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 70: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 74: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 78: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 7c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 80: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 84: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 88: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 8c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 90: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 94: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 98: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 9c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 100: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 104: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 108: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 10c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 110: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 114: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 118: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 11c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 120: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 124: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 128: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 12c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 130: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 134: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 138: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 13c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 140: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 144: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 148: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 14c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 150: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 154: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 158: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 15c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 160: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 164: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 168: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 16c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 170: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 174: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 178: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 17c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 180: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 184: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 188: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 18c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 190: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 194: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 198: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 19c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 200: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 204: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 208: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 20c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 210: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 214: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 218: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 21c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 220: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 224: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 228: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 22c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 230: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 234: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 238: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 23c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 240: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 244: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 248: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 24c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 250: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 254: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 258: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 25c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 260: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 264: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 268: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 26c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 270: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 274: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 278: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 27c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 280: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 284: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 288: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 28c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 290: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 294: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 298: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 29c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2ac: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2b8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2bc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2cc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2dc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2e8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2ec: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2fc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 300: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 304: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 308: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 30c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 310: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 314: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 318: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 31c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 320: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 324: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 328: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 32c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 330: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 334: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 338: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 33c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 340: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 344: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 348: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 34c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 350: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 354: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 358: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 35c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 360: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 364: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 368: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 36c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 370: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 374: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 378: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 37c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 380: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 384: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 388: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 38c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 390: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 394: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 398: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 39c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 400: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 404: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 408: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 40c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 410: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 414: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 418: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 41c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 420: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 424: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 428: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 42c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 430: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 434: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 438: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 43c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 440: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 444: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 448: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 44c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 450: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 454: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 458: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 45c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 460: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 464: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 468: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 46c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 470: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 474: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 478: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 47c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 480: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 484: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 488: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 48c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 490: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 494: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 498: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 49c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 500: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 504: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 508: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 50c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 510: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 514: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 518: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 51c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 520: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 524: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 528: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 52c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 530: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 534: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 538: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 53c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 540: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 544: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 548: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 54c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 550: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 554: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 558: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 55c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 560: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 564: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 568: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 56c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 570: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 574: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 578: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 57c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 580: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 584: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 588: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 58c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 590: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 594: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 598: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 59c: R_ARM_LDC_SB_G2 f diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/arm/group-reloc-ldc.s new file mode 100644 index 000000000000..df27aaf55e07 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.s @@ -0,0 +1,151 @@ +@ LDC group relocation tests. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store + + \load 0, c0, [r0, #:pc_g0:(f + 0x214)] + \load 0, c0, [r0, #:pc_g1:(f + 0x214)] + \load 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f + 0x214)] + \load 0, c0, [r0, #:sb_g1:(f + 0x214)] + \load 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f + 0x214)] + \store 0, c0, [r0, #:pc_g1:(f + 0x214)] + \store 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f + 0x214)] + \store 0, c0, [r0, #:sb_g1:(f + 0x214)] + \store 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \load 0, c0, [r0, #:pc_g0:(f - 0x214)] + \load 0, c0, [r0, #:pc_g1:(f - 0x214)] + \load 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f - 0x214)] + \load 0, c0, [r0, #:sb_g1:(f - 0x214)] + \load 0, c0, [r0, #:sb_g2:(f - 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f - 0x214)] + \store 0, c0, [r0, #:pc_g1:(f - 0x214)] + \store 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f - 0x214)] + \store 0, c0, [r0, #:sb_g1:(f - 0x214)] + \store 0, c0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + ldctest ldc stc + ldctest ldcl stcl + ldctest ldc2 stc2 + ldctest ldc2l stc2l + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store + + \load f0, [r0, #:pc_g0:(f + 0x214)] + \load f0, [r0, #:pc_g1:(f + 0x214)] + \load f0, [r0, #:pc_g2:(f + 0x214)] + + \load f0, [r0, #:sb_g0:(f + 0x214)] + \load f0, [r0, #:sb_g1:(f + 0x214)] + \load f0, [r0, #:sb_g2:(f + 0x214)] + + \store f0, [r0, #:pc_g0:(f + 0x214)] + \store f0, [r0, #:pc_g1:(f + 0x214)] + \store f0, [r0, #:pc_g2:(f + 0x214)] + + \store f0, [r0, #:sb_g0:(f + 0x214)] + \store f0, [r0, #:sb_g1:(f + 0x214)] + \store f0, [r0, #:sb_g2:(f + 0x214)] + + \load f0, [r0, #:pc_g0:(f - 0x214)] + \load f0, [r0, #:pc_g1:(f - 0x214)] + \load f0, [r0, #:pc_g2:(f - 0x214)] + + \load f0, [r0, #:sb_g0:(f - 0x214)] + \load f0, [r0, #:sb_g1:(f - 0x214)] + \load f0, [r0, #:sb_g2:(f - 0x214)] + + \store f0, [r0, #:pc_g0:(f - 0x214)] + \store f0, [r0, #:pc_g1:(f - 0x214)] + \store f0, [r0, #:pc_g2:(f - 0x214)] + + \store f0, [r0, #:sb_g0:(f - 0x214)] + \store f0, [r0, #:sb_g1:(f - 0x214)] + \store f0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + fpa_test ldfs stfs + fpa_test ldfd stfd + fpa_test ldfe stfe + fpa_test ldfp stfp + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg + + \load \reg, [r0, #:pc_g0:(f + 0x214)] + \load \reg, [r0, #:pc_g1:(f + 0x214)] + \load \reg, [r0, #:pc_g2:(f + 0x214)] + + \load \reg, [r0, #:sb_g0:(f + 0x214)] + \load \reg, [r0, #:sb_g1:(f + 0x214)] + \load \reg, [r0, #:sb_g2:(f + 0x214)] + + \store \reg, [r0, #:pc_g0:(f + 0x214)] + \store \reg, [r0, #:pc_g1:(f + 0x214)] + \store \reg, [r0, #:pc_g2:(f + 0x214)] + + \store \reg, [r0, #:sb_g0:(f + 0x214)] + \store \reg, [r0, #:sb_g1:(f + 0x214)] + \store \reg, [r0, #:sb_g2:(f + 0x214)] + + \load \reg, [r0, #:pc_g0:(f - 0x214)] + \load \reg, [r0, #:pc_g1:(f - 0x214)] + \load \reg, [r0, #:pc_g2:(f - 0x214)] + + \load \reg, [r0, #:sb_g0:(f - 0x214)] + \load \reg, [r0, #:sb_g1:(f - 0x214)] + \load \reg, [r0, #:sb_g2:(f - 0x214)] + + \store \reg, [r0, #:pc_g0:(f - 0x214)] + \store \reg, [r0, #:pc_g1:(f - 0x214)] + \store \reg, [r0, #:pc_g2:(f - 0x214)] + + \store \reg, [r0, #:sb_g0:(f - 0x214)] + \store \reg, [r0, #:sb_g1:(f - 0x214)] + \store \reg, [r0, #:sb_g2:(f - 0x214)] + + .endm + + vfp_test flds fsts s0 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 + vfp_test cfldrd cfstrd mvd0 + vfp_test cfldr32 cfstr32 mvfx0 + vfp_test cfldr64 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d new file mode 100644 index 000000000000..49ba77478e44 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldr-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l new file mode 100644 index 000000000000..276a341dc34d --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l @@ -0,0 +1,97 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s new file mode 100644 index 000000000000..3c528f19975b --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s @@ -0,0 +1,39 @@ +@ Tests that are supposed to fail during encoding +@ for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all fail. + + ldrtest ldr str f "+ 4096" + ldrtest ldrb strb f "+ 4096" + ldrtest ldr str f "- 4096" + ldrtest ldrb strb f "- 4096" + + ldrtest ldr str localsym "+ 4096" + ldrtest ldrb strb localsym "+ 4096" + ldrtest ldr str localsym "- 4096" + ldrtest ldrb strb localsym "- 4096" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d new file mode 100644 index 000000000000..fa0941e80a9e --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldr-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l new file mode 100644 index 000000000000..316a6a6c8d8d --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]' +[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]' +[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]' +[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s new file mode 100644 index 000000000000..c7d0ba759651 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s @@ -0,0 +1,33 @@ +@ Tests that are supposed to fail during parsing of LDR group relocations. + + .text + +@ No NC variants exist for the LDR relocations. + + ldr r0, [r0, #:pc_g0_nc:(f)] + ldr r0, [r0, #:pc_g1_nc:(f)] + ldr r0, [r0, #:sb_g0_nc:(f)] + ldr r0, [r0, #:sb_g1_nc:(f)] + + str r0, [r0, #:pc_g0_nc:(f)] + str r0, [r0, #:pc_g1_nc:(f)] + str r0, [r0, #:sb_g0_nc:(f)] + str r0, [r0, #:sb_g1_nc:(f)] + + ldrb r0, [r0, #:pc_g0_nc:(f)] + ldrb r0, [r0, #:pc_g1_nc:(f)] + ldrb r0, [r0, #:sb_g0_nc:(f)] + ldrb r0, [r0, #:sb_g1_nc:(f)] + + strb r0, [r0, #:pc_g0_nc:(f)] + strb r0, [r0, #:pc_g1_nc:(f)] + strb r0, [r0, #:sb_g0_nc:(f)] + strb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + + ldr r0, [r0, #:foo:(f)] + str r0, [r0, #:foo:(f)] + ldrb r0, [r0, #:foo:(f)] + strb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.d b/gas/testsuite/gas/arm/group-reloc-ldr.d new file mode 100644 index 000000000000..cfc1b235cb6c --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.d @@ -0,0 +1,200 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldr) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 0: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 4: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 8: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 10: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 14: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 18: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 1c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 20: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 24: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 28: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 2c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 30: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 34: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 38: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 3c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 40: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 44: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 48: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 4c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 50: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 54: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 58: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 5c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 60: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 64: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 68: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 6c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 70: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 74: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 78: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 7c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 80: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 84: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 88: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 8c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 90: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 94: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 98: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 9c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a0: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a4: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + a8: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + ac: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b0: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b4: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b8: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + bc: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + cc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d0: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d4: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + d8: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + dc: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e0: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e4: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e8: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + ec: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + fc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 100: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 104: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 108: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 10c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 110: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 114: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 118: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 11c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 120: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 124: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 128: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 12c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 130: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 134: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 138: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 13c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 140: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 144: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 148: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 14c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 150: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 154: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 158: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 15c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 160: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 164: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 168: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 16c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 170: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 174: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 178: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 17c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.s b/gas/testsuite/gas/arm/group-reloc-ldr.s new file mode 100644 index 000000000000..389042d70aff --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.s @@ -0,0 +1,41 @@ +@ Tests for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all (just) work. + + ldrtest ldr str f "+ 4095" + ldrtest ldrb strb f "+ 4095" + ldrtest ldr str f "- 4095" + ldrtest ldrb strb f "- 4095" + +@ The same as the above, but for a local symbol. These should not be +@ resolved by the assembler but instead left to the linker. + + ldrtest ldr str localsym "+ 4095" + ldrtest ldrb strb localsym "+ 4095" + ldrtest ldr str localsym "- 4095" + ldrtest ldrb strb localsym "- 4095" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d new file mode 100644 index 000000000000..ff8babf8d5a3 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldrs-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l new file mode 100644 index 000000000000..2621002d2ee4 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l @@ -0,0 +1,121 @@ +[^:]*: Assembler messages: +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s new file mode 100644 index 000000000000..ac7a90f0e9e2 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s @@ -0,0 +1,54 @@ +@ Tests that are meant to fail during encoding of LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) fail. + + ldrtest ldrd strd f "+ 256" + ldrtest ldrh strh f "+ 256" + ldrtest2 ldrsh f "+ 256" + ldrtest2 ldrsb f "+ 256" + + ldrtest ldrd strd f "- 256" + ldrtest ldrh strh f "- 256" + ldrtest2 ldrsh f "- 256" + ldrtest2 ldrsb f "- 256" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 256" + ldrtest ldrh strh localsym "+ 256" + ldrtest2 ldrsh localsym "+ 256" + ldrtest2 ldrsb localsym "+ 256" + + ldrtest ldrd strd localsym "- 256" + ldrtest ldrh strh localsym "- 256" + ldrtest2 ldrsh localsym "- 256" + ldrtest2 ldrsb localsym "- 256" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d new file mode 100644 index 000000000000..cb46d8465d1e --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldrs-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l new file mode 100644 index 000000000000..b3d60351f198 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]' +[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]' +[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]' +[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]' +[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]' +[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s new file mode 100644 index 000000000000..16c1bea5ecfc --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s @@ -0,0 +1,44 @@ +@ Tests that are supposed to fail during parsing of LDRS group relocations. + + .text + +@ No NC variants exist for the LDRS relocations. + + ldrd r0, [r0, #:pc_g0_nc:(f)] + ldrd r0, [r0, #:pc_g1_nc:(f)] + ldrd r0, [r0, #:sb_g0_nc:(f)] + ldrd r0, [r0, #:sb_g1_nc:(f)] + + strd r0, [r0, #:pc_g0_nc:(f)] + strd r0, [r0, #:pc_g1_nc:(f)] + strd r0, [r0, #:sb_g0_nc:(f)] + strd r0, [r0, #:sb_g1_nc:(f)] + + ldrh r0, [r0, #:pc_g0_nc:(f)] + ldrh r0, [r0, #:pc_g1_nc:(f)] + ldrh r0, [r0, #:sb_g0_nc:(f)] + ldrh r0, [r0, #:sb_g1_nc:(f)] + + strh r0, [r0, #:pc_g0_nc:(f)] + strh r0, [r0, #:pc_g1_nc:(f)] + strh r0, [r0, #:sb_g0_nc:(f)] + strh r0, [r0, #:sb_g1_nc:(f)] + + ldrsh r0, [r0, #:pc_g0_nc:(f)] + ldrsh r0, [r0, #:pc_g1_nc:(f)] + ldrsh r0, [r0, #:sb_g0_nc:(f)] + ldrsh r0, [r0, #:sb_g1_nc:(f)] + + ldrsb r0, [r0, #:pc_g0_nc:(f)] + ldrsb r0, [r0, #:pc_g1_nc:(f)] + ldrsb r0, [r0, #:sb_g0_nc:(f)] + ldrsb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + ldrd r0, [r0, #:foo:(f)] + strd r0, [r0, #:foo:(f)] + ldrh r0, [r0, #:foo:(f)] + strh r0, [r0, #:foo:(f)] + ldrsh r0, [r0, #:foo:(f)] + ldrsb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d new file mode 100644 index 000000000000..9896f4bdb6f6 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d @@ -0,0 +1,248 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldrs) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 10: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 14: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 18: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 1c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 20: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 24: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 28: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 2c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 30: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 34: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 38: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 3c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 40: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 44: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 48: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 4c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 50: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 54: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 58: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 5c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 60: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 64: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 68: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 6c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 70: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 74: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 78: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 7c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 80: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 84: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 88: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 8c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 90: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 94: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 98: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 9c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + ac: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + b0: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b4: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b8: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + bc: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c0: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c4: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + c8: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + cc: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d0: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d4: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d8: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + dc: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e0: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e4: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e8: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + ec: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f0: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f4: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f8: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + fc: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 100: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 104: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 108: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 10c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 110: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 114: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 118: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 11c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 120: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 124: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 128: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 12c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 130: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 134: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 138: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 13c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 140: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 144: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 148: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 14c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 150: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 154: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 158: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 15c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 160: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 164: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 168: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 16c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 170: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 174: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 178: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 17c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 180: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 184: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 188: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 18c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 190: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 194: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 198: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 19c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 1a0: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a4: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a8: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1ac: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b0: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b4: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1b8: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1bc: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c0: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c4: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c8: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1cc: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d0: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d4: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d8: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1dc: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.s b/gas/testsuite/gas/arm/group-reloc-ldrs.s new file mode 100644 index 000000000000..fa74e7eabe0a --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.s @@ -0,0 +1,54 @@ +@ Tests for LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) work. + + ldrtest ldrd strd f "+ 255" + ldrtest ldrh strh f "+ 255" + ldrtest2 ldrsh f "+ 255" + ldrtest2 ldrsb f "+ 255" + + ldrtest ldrd strd f "- 255" + ldrtest ldrh strh f "- 255" + ldrtest2 ldrsh f "- 255" + ldrtest2 ldrsb f "- 255" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 255" + ldrtest ldrh strh localsym "+ 255" + ldrtest2 ldrsh localsym "+ 255" + ldrtest2 ldrsb localsym "+ 255" + + ldrtest ldrd strd localsym "- 255" + ldrtest ldrh strh localsym "- 255" + ldrtest2 ldrsh localsym "- 255" + ldrtest2 ldrsb localsym "- 255" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index fbf27b4ab8db..4d56e8eca3d2 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -11,11 +11,11 @@ Disassembly of section .text: 0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 0+004 <[^>]*> e1a01002 ? mov r1, r2 -0+008 <[^>]*> e1a03184 ? mov r3, r4, lsl #3 -0+00c <[^>]*> e1a05736 ? mov r5, r6, lsr r7 -0+010 <[^>]*> e1a08a59 ? mov r8, r9, asr sl -0+014 <[^>]*> e1a0bd1c ? mov fp, ip, lsl sp -0+018 <[^>]*> e1a0e06f ? mov lr, pc, rrx +0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 +0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 +0+010 <[^>]*> e1a08a59 ? asr r8, r9, sl +0+014 <[^>]*> e1a0bd1c ? lsl fp, ip, sp +0+018 <[^>]*> e1a0e06f ? rrx lr, pc 0+01c <[^>]*> e1a01002 ? mov r1, r2 0+020 <[^>]*> 01a02003 ? moveq r2, r3 0+024 <[^>]*> 11a04005 ? movne r4, r5 @@ -28,13 +28,13 @@ Disassembly of section .text: 0+040 <[^>]*> 41a03006 ? movmi r3, r6 0+044 <[^>]*> 51a07009 ? movpl r7, r9 0+048 <[^>]*> 61a01008 ? movvs r1, r8 -0+04c <[^>]*> 71a09fa1 ? movvc r9, r1, lsr #31 +0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31 0+050 <[^>]*> 81a0800f ? movhi r8, pc 0+054 <[^>]*> 91a0f00e ? movls pc, lr 0+058 <[^>]*> 21a09008 ? movcs r9, r8 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 @@ -114,11 +114,11 @@ Disassembly of section .text: 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp 0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip 0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr 0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] 0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] 0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! @@ -130,7 +130,7 @@ Disassembly of section .text: 0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> 0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\] 0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] 0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] 0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! @@ -143,21 +143,21 @@ Disassembly of section .text: 0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> 0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] 0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} 0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} 0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} 0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} 0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} 0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} 0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ 0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 @@ -169,35 +169,35 @@ Disassembly of section .text: [ ]*268:.*_wibble.* 0+26c <[^>]*> da...... ? ble 0[0123456789abcdef]+ <[^>]*> [ ]*26c:.*testerfunc.* -0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 +0+270 <[^>]*> e1a01102 ? lsl r1, r2, #2 0+274 <[^>]*> e1a01002 ? mov r1, r2 -0+278 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+27c <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+280 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+284 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+288 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+28c <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+290 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+294 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+298 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+29c <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2a0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2a4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2a8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ac <[^>]*> e1a01062 ? mov r1, r2, rrx -0+2b0 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 +0+278 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+27c <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+280 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+284 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+288 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+28c <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+290 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+294 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+298 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+29c <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2a0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2a4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2a8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ac <[^>]*> e1a01062 ? rrx r1, r2 +0+2b0 <[^>]*> e1a01102 ? lsl r1, r2, #2 0+2b4 <[^>]*> e1a01002 ? mov r1, r2 -0+2b8 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+2bc <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+2c0 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+2c4 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+2c8 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+2cc <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+2d0 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+2d4 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+2d8 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+2dc <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2e0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2e4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2e8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ec <[^>]*> e1a01062 ? mov r1, r2, rrx +0+2b8 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+2bc <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+2c0 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+2c4 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+2c8 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+2cc <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+2d0 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+2d4 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+2d8 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+2dc <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2e0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2e4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2e8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ec <[^>]*> e1a01062 ? rrx r1, r2 diff --git a/gas/testsuite/gas/arm/itblock.s b/gas/testsuite/gas/arm/itblock.s new file mode 100644 index 000000000000..0fb3c198d744 --- /dev/null +++ b/gas/testsuite/gas/arm/itblock.s @@ -0,0 +1,21 @@ +# All-true IT block macro. + + .macro itblock num cond="" + .if x\cond != x + .if \num == 4 + itttt \cond + .else + .if \num == 3 + ittt \cond + .else + .if \num == 2 + itt \cond + .else + .if \num == 1 + .it \cond + .endif + .endif + .endif + .endif + .endif + .endm diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.l b/gas/testsuite/gas/arm/iwmmxt-bad.l index 65889380cf1b..d030a6da46ae 100644 --- a/gas/testsuite/gas/arm/iwmmxt-bad.l +++ b/gas/testsuite/gas/arm/iwmmxt-bad.l @@ -8,3 +8,5 @@ [^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]' [^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]' [^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1' +[^:]*:10: Error: iWMMXt data or control register expected -- `wldrw wibble,\[r1\]' +[^:]*:11: Error: iWMMXt data or control register expected -- `wstrw wibble,\[r1\]' diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.s b/gas/testsuite/gas/arm/iwmmxt-bad.s index 47d8d71f8656..98fc239374b7 100644 --- a/gas/testsuite/gas/arm/iwmmxt-bad.s +++ b/gas/testsuite/gas/arm/iwmmxt-bad.s @@ -7,3 +7,5 @@ wstrh wcgr0,[r1] wstrd wcgr0,[r1] tmcr wibble,r1 + wldrw wibble,[r1] + wstrw wibble,[r1] diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d new file mode 100644 index 000000000000..c17a1d858a10 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d @@ -0,0 +1,11 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 1 +#as: -mcpu=xscale+iwmmxt -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt> ecb11000[ ]+wldrb[ ]+wr1, \[r1\] +0+004 <[^>]*> ecf11000[ ]+wldrh[ ]+wr1, \[r1\] +0+008 <[^>]*> eca11000[ ]+wstrb[ ]+wr1, \[r1\] +0+00c <[^>]*> ece11000[ ]+wstrh[ ]+wr1, \[r1\] diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s new file mode 100644 index 000000000000..fd58c105de50 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s @@ -0,0 +1,8 @@ + .text + .global iwmmxt +iwmmxt: + + wldrb wr1, [r1], #0 + wldrh wr1, [r1], #0 + wstrb wr1, [r1], #0 + wstrh wr1, [r1], #0 diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d index 494199d2bc45..85f4ac2e84e4 100644 --- a/gas/testsuite/gas/arm/iwmmxt.d +++ b/gas/testsuite/gas/arm/iwmmxt.d @@ -166,6 +166,6 @@ Disassembly of section .text: 0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10 0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5 0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7 -0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) -0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) +0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0 +0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2 0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s index 0ebbad5cd3c7..42bbb7ab4ceb 100644 --- a/gas/testsuite/gas/arm/iwmmxt.s +++ b/gas/testsuite/gas/arm/iwmmxt.s @@ -203,7 +203,8 @@ iwmmxt: wzeroge wr7 + tmcr wcgr0, r0 + tmrc r1, wcgr2 + @ a.out-required section size padding nop - nop - nop diff --git a/gas/testsuite/gas/arm/iwmmxt2.d b/gas/testsuite/gas/arm/iwmmxt2.d new file mode 100644 index 000000000000..7c1bbeb921e3 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt2.d @@ -0,0 +1,119 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 2 +#as: -mcpu=xscale+iwmmxt+iwmmxt2 -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt2> ee654186[ ]+waddhc[ ]+wr4, wr5, wr6 +0+004 <[^>]*> eea87189[ ]+waddwc[ ]+wr7, wr8, wr9 +0+008 <[^>]*> ce954106[ ]+wmadduxgt[ ]+wr4, wr5, wr6 +0+00c <[^>]*> 0ec87109[ ]+wmadduneq[ ]+wr7, wr8, wr9 +0+010 <[^>]*> 1eb54106[ ]+wmaddsxne[ ]+wr4, wr5, wr6 +0+014 <[^>]*> aee87109[ ]+wmaddsnge[ ]+wr7, wr8, wr9 +0+018 <[^>]*> eed21103[ ]+wmulumr[ ]+wr1, wr2, wr3 +0+01c <[^>]*> eef21103[ ]+wmulsmr[ ]+wr1, wr2, wr3 +0+020 <[^>]*> ce13f190[ ]+torvscbgt[ ]+pc +0+024 <[^>]*> 1e53f190[ ]+torvschne[ ]+pc +0+028 <[^>]*> 0e93f190[ ]+torvscweq[ ]+pc +0+02c <[^>]*> ee2211c0[ ]+wabsb[ ]+wr1, wr2 +0+030 <[^>]*> ee6431c0[ ]+wabsh[ ]+wr3, wr4 +0+034 <[^>]*> eea651c0[ ]+wabsw[ ]+wr5, wr6 +0+038 <[^>]*> ce2211c0[ ]+wabsbgt[ ]+wr1, wr2 +0+03c <[^>]*> ee1211c3[ ]+wabsdiffb[ ]+wr1, wr2, wr3 +0+040 <[^>]*> ee5541c6[ ]+wabsdiffh[ ]+wr4, wr5, wr6 +0+044 <[^>]*> ee9871c9[ ]+wabsdiffw[ ]+wr7, wr8, wr9 +0+048 <[^>]*> ce1211c3[ ]+wabsdiffbgt[ ]+wr1, wr2, wr3 +0+04c <[^>]*> ee6211a3[ ]+waddbhusm[ ]+wr1, wr2, wr3 +0+050 <[^>]*> ee2541a6[ ]+waddbhusl[ ]+wr4, wr5, wr6 +0+054 <[^>]*> ce6211a3[ ]+waddbhusmgt[ ]+wr1, wr2, wr3 +0+058 <[^>]*> ce2541a6[ ]+waddbhuslgt[ ]+wr4, wr5, wr6 +0+05c <[^>]*> ee421003[ ]+wavg4[ ]+wr1, wr2, wr3 +0+060 <[^>]*> ce454006[ ]+wavg4gt[ ]+wr4, wr5, wr6 +0+064 <[^>]*> ee521003[ ]+wavg4r[ ]+wr1, wr2, wr3 +0+068 <[^>]*> ce554006[ ]+wavg4rgt[ ]+wr4, wr5, wr6 +0+06c <[^>]*> fc711102[ ]+wldrd[ ]+wr1, \[r1\], -r2 +0+070 <[^>]*> fc712132[ ]+wldrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+074 <[^>]*> fcf13102[ ]+wldrd[ ]+wr3, \[r1\], \+r2 +0+078 <[^>]*> fcf14142[ ]+wldrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+07c <[^>]*> fd515102[ ]+wldrd[ ]+wr5, \[r1, -r2\] +0+080 <[^>]*> fd516132[ ]+wldrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+084 <[^>]*> fdd17102[ ]+wldrd[ ]wr7, \[r1, \+r2\] +0+088 <[^>]*> fdd18142[ ]+wldrd[ ]wr8, \[r1, \+r2, lsl #4\] +0+08c <[^>]*> fd719102[ ]+wldrd[ ]wr9, \[r1, -r2\]! +0+090 <[^>]*> fd71a132[ ]+wldrd[ ]wr10, \[r1, -r2, lsl #3\]! +0+094 <[^>]*> fdf1b102[ ]+wldrd[ ]wr11, \[r1, \+r2\]! +0+098 <[^>]*> fdf1c142[ ]+wldrd[ ]wr12, \[r1, \+r2, lsl #4\]! +0+09c <[^>]*> ee821083[ ]+wmerge[ ]wr1, wr2, wr3, #4 +0+0a0 <[^>]*> ce821083[ ]+wmergegt[ ]wr1, wr2, wr3, #4 +0+0a4 <[^>]*> 0e3210a3[ ]+wmiatteq[ ]wr1, wr2, wr3 +0+0a8 <[^>]*> ce2210a3[ ]+wmiatbgt[ ]wr1, wr2, wr3 +0+0ac <[^>]*> 1e1210a3[ ]+wmiabtne[ ]wr1, wr2, wr3 +0+0b0 <[^>]*> ce0210a3[ ]+wmiabbgt[ ]wr1, wr2, wr3 +0+0b4 <[^>]*> 0e7210a3[ ]+wmiattneq[ ]wr1, wr2, wr3 +0+0b8 <[^>]*> 1e6210a3[ ]+wmiatbnne[ ]wr1, wr2, wr3 +0+0bc <[^>]*> ce5210a3[ ]+wmiabtngt[ ]wr1, wr2, wr3 +0+0c0 <[^>]*> 0e4210a3[ ]+wmiabbneq[ ]wr1, wr2, wr3 +0+0c4 <[^>]*> 0eb21123[ ]+wmiawtteq[ ]wr1, wr2, wr3 +0+0c8 <[^>]*> cea21123[ ]+wmiawtbgt[ ]wr1, wr2, wr3 +0+0cc <[^>]*> 1e921123[ ]+wmiawbtne[ ]wr1, wr2, wr3 +0+0d0 <[^>]*> ce821123[ ]+wmiawbbgt[ ]wr1, wr2, wr3 +0+0d4 <[^>]*> 1ef21123[ ]+wmiawttnne[ ]wr1, wr2, wr3 +0+0d8 <[^>]*> cee21123[ ]+wmiawtbngt[ ]wr1, wr2, wr3 +0+0dc <[^>]*> 0ed21123[ ]+wmiawbtneq[ ]wr1, wr2, wr3 +0+0e0 <[^>]*> 1ec21123[ ]+wmiawbbnne[ ]wr1, wr2, wr3 +0+0e4 <[^>]*> 0ed210c3[ ]+wmulwumeq[ ]wr1, wr2, wr3 +0+0e8 <[^>]*> cec210c3[ ]+wmulwumrgt[ ]wr1, wr2, wr3 +0+0ec <[^>]*> 1ef210c3[ ]+wmulwsmne[ ]wr1, wr2, wr3 +0+0f0 <[^>]*> 0ee210c3[ ]+wmulwsmreq[ ]wr1, wr2, wr3 +0+0f4 <[^>]*> ceb210c3[ ]+wmulwlgt[ ]wr1, wr2, wr3 +0+0f8 <[^>]*> aeb210c3[ ]+wmulwlge[ ]wr1, wr2, wr3 +0+0fc <[^>]*> 1eb210a3[ ]+wqmiattne[ ]wr1, wr2, wr3 +0+100 <[^>]*> 0ef210a3[ ]+wqmiattneq[ ]wr1, wr2, wr3 +0+104 <[^>]*> cea210a3[ ]+wqmiatbgt[ ]wr1, wr2, wr3 +0+108 <[^>]*> aee210a3[ ]+wqmiatbnge[ ]wr1, wr2, wr3 +0+10c <[^>]*> 1e9210a3[ ]+wqmiabtne[ ]wr1, wr2, wr3 +0+110 <[^>]*> 0ed210a3[ ]+wqmiabtneq[ ]wr1, wr2, wr3 +0+114 <[^>]*> ce8210a3[ ]+wqmiabbgt[ ]wr1, wr2, wr3 +0+118 <[^>]*> 1ec210a3[ ]+wqmiabbnne[ ]wr1, wr2, wr3 +0+11c <[^>]*> ce121083[ ]+wqmulmgt[ ]wr1, wr2, wr3 +0+120 <[^>]*> 0e321083[ ]+wqmulmreq[ ]wr1, wr2, wr3 +0+124 <[^>]*> cec210e3[ ]+wqmulwmgt[ ]wr1, wr2, wr3 +0+128 <[^>]*> 0ee210e3[ ]+wqmulwmreq[ ]wr1, wr2, wr3 +0+12c <[^>]*> fc611102[ ]+wstrd[ ]+wr1, \[r1\], -r2 +0+130 <[^>]*> fc612132[ ]+wstrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+134 <[^>]*> fce13102[ ]+wstrd[ ]+wr3, \[r1\], \+r2 +0+138 <[^>]*> fce14142[ ]+wstrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+13c <[^>]*> fd415102[ ]+wstrd[ ]+wr5, \[r1, -r2\] +0+140 <[^>]*> fd416132[ ]+wstrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+144 <[^>]*> fdc17102[ ]+wstrd[ ]wr7, \[r1, \+r2\] +0+148 <[^>]*> fdc18142[ ]+wstrd[ ]wr8, \[r1, \+r2, lsl #4\] +0+14c <[^>]*> fd619102[ ]+wstrd[ ]wr9, \[r1, -r2\]! +0+150 <[^>]*> fd61a132[ ]+wstrd[ ]wr10, \[r1, -r2, lsl #3\]! +0+154 <[^>]*> fde1b102[ ]+wstrd[ ]wr11, \[r1, \+r2\]! +0+158 <[^>]*> fde1c142[ ]+wstrd[ ]wr12, \[r1, \+r2, lsl #4\]! +0+15c <[^>]*> ced211c3[ ]+wsubaddhxgt[ ]wr1, wr2, wr3 +0+160 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+164 <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+168 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+16c <[^>]*> fe721145[ ]+wrorh[ ]wr1, wr2, #21 +0+170 <[^>]*> feb2104d[ ]+wrorw[ ]wr1, wr2, #13 +0+174 <[^>]*> fef2104e[ ]+wrord[ ]wr1, wr2, #14 +0+178 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+17c <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+180 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+184 <[^>]*> fe59204b[ ]+wsllh[ ]wr2, wr9, #11 +0+188 <[^>]*> fe95304d[ ]+wsllw[ ]wr3, wr5, #13 +0+18c <[^>]*> fed8304f[ ]+wslld[ ]wr3, wr8, #15 +0+190 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+194 <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+198 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+19c <[^>]*> fe49204c[ ]+wsrah[ ]wr2, wr9, #12 +0+1a0 <[^>]*> fe85304e[ ]+wsraw[ ]wr3, wr5, #14 +0+1a4 <[^>]*> fec83140[ ]+wsrad[ ]wr3, wr8, #16 +0+1a8 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+1ac <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+1b0 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+1b4 <[^>]*> fe69204c[ ]+wsrlh[ ]wr2, wr9, #12 +0+1b8 <[^>]*> fea5304e[ ]+wsrlw[ ]wr3, wr5, #14 +0+1bc <[^>]*> fee83140[ ]+wsrld[ ]wr3, wr8, #16 diff --git a/gas/testsuite/gas/arm/iwmmxt2.s b/gas/testsuite/gas/arm/iwmmxt2.s new file mode 100644 index 000000000000..314f64f11e0b --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt2.s @@ -0,0 +1,137 @@ + .text + .global iwmmxt2 +iwmmxt2: + + waddhc wr4, wr5, wr6 + waddwc wr7, wr8, wr9 + + wmadduxgt wr4, wr5, wr6 + wmadduneq wr7, wr8, wr9 + wmaddsxne wr4, wr5, wr6 + wmaddsnge wr7, wr8, wr9 + + wmulumr wr1, wr2, wr3 + wmulsmr wr1, wr2, wr3 + + torvscbgt r15 + torvschne r15 + torvscweq r15 + + wabsb wr1, wr2 + wabsh wr3, wr4 + wabsw wr5, wr6 + wabsbgt wr1, wr2 + + wabsdiffb wr1, wr2, wr3 + wabsdiffh wr4, wr5, wr6 + wabsdiffw wr7, wr8, wr9 + wabsdiffbgt wr1, wr2, wr3 + + waddbhusm wr1, wr2, wr3 + waddbhusl wr4, wr5, wr6 + waddbhusmgt wr1, wr2, wr3 + waddbhuslgt wr4, wr5, wr6 + + wavg4 wr1, wr2, wr3 + wavg4gt wr4, wr5, wr6 + wavg4r wr1, wr2, wr3 + wavg4rgt wr4, wr5, wr6 + + wldrd wr1, [r1], -r2 + wldrd wr2, [r1], -r2,lsl #3 + wldrd wr3, [r1], +r2 + wldrd wr4, [r1], +r2,lsl #4 + wldrd wr5, [r1, -r2] + wldrd wr6, [r1, -r2,lsl #3] + wldrd wr7, [r1, +r2] + wldrd wr8, [r1, +r2,lsl #4] + wldrd wr9, [r1, -r2]! + wldrd wr10, [r1, -r2,lsl #3]! + wldrd wr11, [r1, +r2]! + wldrd wr12, [r1, +r2,lsl #4]! + + wmerge wr1, wr2, wr3, #4 + wmergegt wr1, wr2, wr3, #4 + + wmiatteq wr1, wr2, wr3 + wmiatbgt wr1, wr2, wr3 + wmiabtne wr1, wr2, wr3 + wmiabbgt wr1, wr2, wr3 + wmiattneq wr1, wr2, wr3 + wmiatbnne wr1, wr2, wr3 + wmiabtngt wr1, wr2, wr3 + wmiabbneq wr1, wr2, wr3 + + wmiawtteq wr1, wr2, wr3 + wmiawtbgt wr1, wr2, wr3 + wmiawbtne wr1, wr2, wr3 + wmiawbbgt wr1, wr2, wr3 + wmiawttnne wr1, wr2, wr3 + wmiawtbngt wr1, wr2, wr3 + wmiawbtneq wr1, wr2, wr3 + wmiawbbnne wr1, wr2, wr3 + + wmulwumeq wr1, wr2, wr3 + wmulwumrgt wr1, wr2, wr3 + wmulwsmne wr1, wr2, wr3 + wmulwsmreq wr1, wr2, wr3 + wmulwlgt wr1, wr2, wr3 + wmulwlge wr1, wr2, wr3 + + wqmiattne wr1, wr2, wr3 + wqmiattneq wr1, wr2, wr3 + wqmiatbgt wr1, wr2, wr3 + wqmiatbnge wr1, wr2, wr3 + wqmiabtne wr1, wr2, wr3 + wqmiabtneq wr1, wr2, wr3 + wqmiabbgt wr1, wr2, wr3 + wqmiabbnne wr1, wr2, wr3 + + wqmulmgt wr1, wr2, wr3 + wqmulmreq wr1, wr2, wr3 + + wqmulwmgt wr1, wr2, wr3 + wqmulwmreq wr1, wr2, wr3 + + wstrd wr1, [r1], -r2 + wstrd wr2, [r1], -r2,lsl #3 + wstrd wr3, [r1], +r2 + wstrd wr4, [r1], +r2,lsl #4 + wstrd wr5, [r1, -r2] + wstrd wr6, [r1, -r2,lsl #3] + wstrd wr7, [r1, +r2] + wstrd wr8, [r1, +r2,lsl #4] + wstrd wr9, [r1, -r2]! + wstrd wr10, [r1, -r2,lsl #3]! + wstrd wr11, [r1, +r2]! + wstrd wr12, [r1, +r2,lsl #4]! + + wsubaddhxgt wr1, wr2, wr3 + + wrorh wr1, wr2, #0 + wrorw wr1, wr2, #0 + wrord wr1, wr2, #0 + wrorh wr1, wr2, #21 + wrorw wr1, wr2, #13 + wrord wr1, wr2, #14 + + wsllh wr1, wr2, #0 + wsllw wr1, wr2, #0 + wslld wr1, wr2, #0 + wsllh wr2, wr9, #11 + wsllw wr3, wr5, #13 + wslld wr3, wr8, #15 + + wsrah wr1, wr2, #0 + wsraw wr1, wr2, #0 + wsrad wr1, wr2, #0 + wsrah wr2, wr9, #12 + wsraw wr3, wr5, #14 + wsrad wr3, wr8, #16 + + wsrlh wr1, wr2, #0 + wsrlw wr1, wr2, #0 + wsrld wr1, wr2, #0 + wsrlh wr2, wr9, #12 + wsrlw wr3, wr5, #14 + wsrld wr3, wr8, #16 diff --git a/gas/testsuite/gas/arm/local_function.d b/gas/testsuite/gas/arm/local_function.d new file mode 100644 index 000000000000..46da8eceb6c7 --- /dev/null +++ b/gas/testsuite/gas/arm/local_function.d @@ -0,0 +1,10 @@ +#objdump: -r +#name: Relocations agains local function symbols +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000000 R_ARM_(CALL|PC24) bar diff --git a/gas/testsuite/gas/arm/local_function.s b/gas/testsuite/gas/arm/local_function.s new file mode 100644 index 000000000000..1d98a37425cc --- /dev/null +++ b/gas/testsuite/gas/arm/local_function.s @@ -0,0 +1,10 @@ + .text + .type foo, %function +foo: + bl bar + + .section .text.bar + nop + .type bar, %function +bar: + nop diff --git a/gas/testsuite/gas/arm/local_label_coff.d b/gas/testsuite/gas/arm/local_label_coff.d new file mode 100644 index 000000000000..5e45ac8c479c --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_coff.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (COFF) +# This test is only valid on COFF based targets, except Windows CE. +# There are ELF and Windows CE versions of this test. +#not-skip: *-unknown-pe *-epoc-pe *-*-*coff + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/gas/testsuite/gas/arm/local_label_coff.s b/gas/testsuite/gas/arm/local_label_coff.s new file mode 100644 index 000000000000..985f568ac3f0 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_coff.s @@ -0,0 +1,3 @@ + .text +Lused_label: + .word Lused_label diff --git a/gas/testsuite/gas/arm/local_label_elf.d b/gas/testsuite/gas/arm/local_label_elf.d new file mode 100644 index 000000000000..d4a8c8ea73f7 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_elf.d @@ -0,0 +1,9 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (ELF) +# This test is only valid on ELF targets. +# There are COFF and Windows CE versions of this test. +#skip: *-*-*coff *-*-pe *-wince-* *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. + diff --git a/gas/testsuite/gas/arm/local_label_elf.s b/gas/testsuite/gas/arm/local_label_elf.s new file mode 100644 index 000000000000..e9f5467d4122 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_elf.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/gas/testsuite/gas/arm/local_label_wince.d b/gas/testsuite/gas/arm/local_label_wince.d new file mode 100644 index 000000000000..97fc58aea824 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_wince.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (WinCE) +# This test is only valid on Windows CE. +# There are ELF and COFF versions of this test. +#not-skip: *-*-wince *-wince-* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/gas/testsuite/gas/arm/local_label_wince.s b/gas/testsuite/gas/arm/local_label_wince.s new file mode 100644 index 000000000000..e9f5467d4122 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_wince.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d index 2384594fc545..c29bb626156e 100644 --- a/gas/testsuite/gas/arm/macro1.d +++ b/gas/testsuite/gas/arm/macro1.d @@ -6,7 +6,7 @@ Disassembly of section .text: -0+0 <[^>]*> e8bd8030 ? ldmia sp!, {r4, r5, pc} +0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc} 0+4 <[^>]*> e1a00000 ? nop \(mov r0,r0\) 0+8 <[^>]*> e1a00000 ? nop \(mov r0,r0\) 0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/mapshort-eabi.d b/gas/testsuite/gas/arm/mapshort-eabi.d new file mode 100644 index 000000000000..9cbfc3eacd4a --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort-eabi.d @@ -0,0 +1,45 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (EABI version) +# This test is only valid on EABI based ports. +#target: *-*-*eabi *-*-symbianelf +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l .data 00000000 \$d +0+00 l d .ARM.attributes 00000000 .ARM.attributes + + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop \(mov r0,r0\) + 4: 46c0 nop \(mov r8, r8\) + 6: 46c0 nop \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop \(mov r8, r8\) + 14: 46c0 nop \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/gas/testsuite/gas/arm/mapshort-elf.d b/gas/testsuite/gas/arm/mapshort-elf.d new file mode 100644 index 000000000000..09602f08091e --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort-elf.d @@ -0,0 +1,44 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (ELF version) +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi *-*-syymbianelf +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l .data 00000000 \$d +# The ELF based port does not generate a .ARM.attributes symbol + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop \(mov r0,r0\) + 4: 46c0 nop \(mov r8, r8\) + 6: 46c0 nop \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop \(mov r8, r8\) + 14: 46c0 nop \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/gas/testsuite/gas/arm/mapshort.s b/gas/testsuite/gas/arm/mapshort.s new file mode 100644 index 000000000000..741cb8251053 --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort.s @@ -0,0 +1,24 @@ + .text + .type foo, %function +foo: + .code 32 + nop + .code 16 + nop + nop + .long 2 + .short 1 + .short 1 + .short 3 + nop + nop + .short 1 + .code 32 + bl foo + .short 8 + .byte 9 +bar: + .byte 10 + .data +wibble: + .word 0 diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.d b/gas/testsuite/gas/arm/mul-overlap-v6.d new file mode 100644 index 000000000000..ff42190a5d0d --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap-v6.d @@ -0,0 +1,10 @@ +# name: Overlapping multiplication operands for ARMv6 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e0000090 mul r0, r0, r0 +0[0-9a-f]+ <[^>]+> e0202190 mla r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e0602190 mls r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e12fff1e bx lr diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.s b/gas/testsuite/gas/arm/mul-overlap-v6.s new file mode 100644 index 000000000000..f35c124ae39f --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap-v6.s @@ -0,0 +1,9 @@ + .arch armv6t2 + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + bx lr diff --git a/gas/testsuite/gas/arm/mul-overlap.d b/gas/testsuite/gas/arm/mul-overlap.d new file mode 100644 index 000000000000..53406e3f413b --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.d @@ -0,0 +1,2 @@ +# name: Overlapping multiplication operands without architecture specification +# error-output: mul-overlap.l diff --git a/gas/testsuite/gas/arm/mul-overlap.l b/gas/testsuite/gas/arm/mul-overlap.l new file mode 100644 index 000000000000..a895c0102a3f --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:5: Rd and Rm should be different in mul +[^:]*:6: Rd and Rm should be different in mla diff --git a/gas/testsuite/gas/arm/mul-overlap.s b/gas/testsuite/gas/arm/mul-overlap.s new file mode 100644 index 000000000000..6932eaeb13fe --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.s @@ -0,0 +1,8 @@ + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + bx lr diff --git a/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/gas/testsuite/gas/arm/neon-cond-bad-inc.s new file mode 100644 index 000000000000..a92d19675e1c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad-inc.s @@ -0,0 +1,57 @@ +# Check for illegal conditional Neon instructions in ARM mode. The instructions +# which overlap with VFP are the tricky cases, so test those. + + .include "itblock.s" + + .syntax unified + .text +func: + itblock 4 eq + vmoveq q0,q1 + vmoveq d0,d1 + vmoveq.i32 q0,#0 + vmoveq.i32 d0,#0 + @ Following four *can* be conditional. + itblock 4 eq + vmoveq.32 d0[1], r2 + vmoveq d0,r1,r2 + vmoveq.32 r2,d1[0] + vmoveq r0,r1,d2 + + .macro dyadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1,d2 + \op\eq\f32 q0,q1,q2 + .endm + + dyadic_eq vmul + dyadic_eq vmla + dyadic_eq vmls + dyadic_eq vadd + dyadic_eq vsub + + .macro monadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1 + \op\eq\f32 q0,q1 + .endm + + monadic_eq vabs + monadic_eq vneg + + .macro cvt to from dot="." + itblock 2 eq + vcvteq\dot\to\dot\from d0,d1 + vcvteq\dot\to\dot\from q0,q1 + .endm + + cvt s32 f32 + cvt u32 f32 + cvt f32 s32 + cvt f32 u32 + + itblock 4 eq + vdupeq.32 d0,r1 + vdupeq.32 q0,r1 + vdupeq.32 d0,d1[0] + vdupeq.32 q0,d1[1] diff --git a/gas/testsuite/gas/arm/neon-cond-bad.d b/gas/testsuite/gas/arm/neon-cond-bad.d new file mode 100644 index 000000000000..105ba4d7f26e --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.d @@ -0,0 +1,3 @@ +# name: Illegal conditions in Neon instructions, ARM mode +# as: -mfpu=neon -I$srcdir/$subdir +# error-output: neon-cond-bad.l diff --git a/gas/testsuite/gas/arm/neon-cond-bad.l b/gas/testsuite/gas/arm/neon-cond-bad.l new file mode 100644 index 000000000000..a79f79d64f83 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1' +[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1' +[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0' +[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1' +[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]' +[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]' diff --git a/gas/testsuite/gas/arm/neon-cond-bad.s b/gas/testsuite/gas/arm/neon-cond-bad.s new file mode 100644 index 000000000000..16afd8635e91 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.s @@ -0,0 +1,2 @@ + .arm + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/gas/testsuite/gas/arm/neon-cond-bad_t2.d new file mode 100644 index 000000000000..517caa758ee4 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.d @@ -0,0 +1,55 @@ +# name: Conditions in Neon instructions, Thumb mode (illegal in ARM). +# as: -mfpu=neon -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1 +0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1 +0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2 +0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2 +0[0-9a-f]+ <[^>]+> ee11 2b10 vmoveq\.32 r2, d1\[0\] +0[0-9a-f]+ <[^>]+> ec51 0b12 vmoveq r0, r1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0701 vabseq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 0742 vabseq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0781 vnegeq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 07c2 vnegeq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0701 vcvteq\.s32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0742 vcvteq\.s32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0781 vcvteq\.u32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 07c2 vcvteq\.u32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0601 vcvteq\.f32\.s32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0642 vcvteq\.f32\.s32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0681 vcvteq\.f32\.u32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 06c2 vcvteq\.f32\.u32 q0, q1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee80 1b10 vdupeq\.32 d0, r1 +0[0-9a-f]+ <[^>]+> eea0 1b10 vdupeq\.32 q0, r1 +0[0-9a-f]+ <[^>]+> ffb4 0c01 vdupeq\.32 d0, d1\[0\] +0[0-9a-f]+ <[^>]+> ffbc 0c41 vdupeq\.32 q0, d1\[1\] diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.s b/gas/testsuite/gas/arm/neon-cond-bad_t2.s new file mode 100644 index 000000000000..2655d11a049d --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/neon-cond.d b/gas/testsuite/gas/arm/neon-cond.d new file mode 100644 index 000000000000..0b7d8ede73b6 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond.d @@ -0,0 +1,14 @@ +# name: Conditional Neon instructions +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> 0d943b00 vldreq d3, \[r4\] +0[0-9a-f]+ <[^>]+> be035b70 vmovlt\.16 d3\[1\], r5 +0[0-9a-f]+ <[^>]+> ac474b13 vmovge d3, r4, r7 +0[0-9a-f]+ <[^>]+> 3c543b3e vmovcc r3, r4, d30 +0[0-9a-f]+ <[^>]+> 1e223b10 vmovne\.32 d2\[1\], r3 +0[0-9a-f]+ <[^>]+> 2c521b13 vmovcs r1, r2, d3 +0[0-9a-f]+ <[^>]+> 3c421b14 vmovcc d4, r1, r2 diff --git a/gas/testsuite/gas/arm/neon-cond.s b/gas/testsuite/gas/arm/neon-cond.s new file mode 100644 index 000000000000..8f62575aa5e5 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond.s @@ -0,0 +1,13 @@ +@ test conditional compilation + + .arm + .text + .syntax unified + + vldreq.32 d3,[r4] + vmovlt.16 d3[1], r5 + vmovge d3, r4, r7 + vmovcc r3, r4, d30 + vmovne.32 d2[1],r3 + vmovcs r1,r2,d3 + vmovcc d4,r1,r2 diff --git a/gas/testsuite/gas/arm/neon-const.d b/gas/testsuite/gas/arm/neon-const.d new file mode 100644 index 000000000000..a1bc97cf381f --- /dev/null +++ b/gas/testsuite/gas/arm/neon-const.d @@ -0,0 +1,265 @@ +# name: Neon floating-point constants +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000 +0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000 +0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000 +0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000 +0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000 +0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000 +0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000 +0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000 +0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000 +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 ; 0x41080000 +0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 ; 0x41880000 +0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 ; 0x3e080000 +0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 ; 0x3e880000 +0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 ; 0x3f080000 +0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 ; 0x3f880000 +0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 ; 0x40100000 +0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 ; 0x40900000 +0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 ; 0x41100000 +0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 ; 0x41900000 +0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 ; 0x3e100000 +0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 ; 0x3e900000 +0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 ; 0x3f100000 +0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 ; 0x3f900000 +0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 ; 0x40180000 +0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 ; 0x40980000 +0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 ; 0x41180000 +0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 ; 0x41980000 +0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 ; 0x3e180000 +0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 ; 0x3e980000 +0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 ; 0x3f180000 +0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 ; 0x3f980000 +0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 ; 0x40200000 +0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 ; 0x40a00000 +0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 ; 0x41200000 +0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 ; 0x41a00000 +0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 ; 0x3e200000 +0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 ; 0x3ea00000 +0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 ; 0x3f200000 +0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 ; 0x3fa00000 +0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 ; 0x40280000 +0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 ; 0x40a80000 +0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 ; 0x41280000 +0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 ; 0x41a80000 +0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 ; 0x3e280000 +0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 ; 0x3ea80000 +0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 ; 0x3f280000 +0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 ; 0x3fa80000 +0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 ; 0x40300000 +0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 ; 0x40b00000 +0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 ; 0x41300000 +0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 ; 0x41b00000 +0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 ; 0x3e300000 +0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 ; 0x3eb00000 +0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 ; 0x3f300000 +0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 ; 0x3fb00000 +0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 ; 0x40380000 +0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 ; 0x40b80000 +0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 ; 0x41380000 +0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 ; 0x41b80000 +0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 ; 0x3e380000 +0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 ; 0x3eb80000 +0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 ; 0x3f380000 +0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 ; 0x3fb80000 +0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 ; 0x40400000 +0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 ; 0x40c00000 +0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 ; 0x41400000 +0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 ; 0x41c00000 +0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 ; 0x3e400000 +0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 ; 0x3ec00000 +0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 ; 0x3f400000 +0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 ; 0x3fc00000 +0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 ; 0x40480000 +0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 ; 0x40c80000 +0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 ; 0x41480000 +0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 ; 0x41c80000 +0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 ; 0x3e480000 +0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 ; 0x3ec80000 +0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 ; 0x3f480000 +0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 ; 0x3fc80000 +0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 ; 0x40500000 +0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 ; 0x40d00000 +0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 ; 0x41500000 +0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 ; 0x41d00000 +0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 ; 0x3e500000 +0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 ; 0x3ed00000 +0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 ; 0x3f500000 +0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 ; 0x3fd00000 +0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 ; 0x40580000 +0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 ; 0x40d80000 +0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 ; 0x41580000 +0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 ; 0x41d80000 +0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 ; 0x3e580000 +0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 ; 0x3ed80000 +0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 ; 0x3f580000 +0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 ; 0x3fd80000 +0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 ; 0x40600000 +0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 ; 0x40e00000 +0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 ; 0x41600000 +0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 ; 0x41e00000 +0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 ; 0x3e600000 +0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 ; 0x3ee00000 +0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 ; 0x3f600000 +0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 ; 0x3fe00000 +0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 ; 0x40680000 +0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 ; 0x40e80000 +0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 ; 0x41680000 +0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 ; 0x41e80000 +0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 ; 0x3e680000 +0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 ; 0x3ee80000 +0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 ; 0x3f680000 +0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 ; 0x3fe80000 +0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 ; 0x40700000 +0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 ; 0x40f00000 +0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 ; 0x41700000 +0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 ; 0x41f00000 +0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 ; 0x3e700000 +0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 ; 0x3ef00000 +0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 ; 0x3f700000 +0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 ; 0x3ff00000 +0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 ; 0x40780000 +0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 ; 0x40f80000 +0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 ; 0x41780000 +0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 ; 0x41f80000 +0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 ; 0x3e780000 +0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 ; 0x3ef80000 +0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 ; 0x3f780000 +0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 ; 0x3ff80000 +0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 ; 0x80000000 +0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 ; 0xc0000000 +0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 ; 0xc0800000 +0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 ; 0xc1000000 +0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 ; 0xc1800000 +0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 ; 0xbe000000 +0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 ; 0xbe800000 +0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 ; 0xbf000000 +0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 ; 0xbf800000 +0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 ; 0xc0080000 +0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 ; 0xc0880000 +0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 ; 0xc1080000 +0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 ; 0xc1880000 +0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 ; 0xbe080000 +0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 ; 0xbe880000 +0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 ; 0xbf080000 +0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 ; 0xbf880000 +0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 ; 0xc0100000 +0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 ; 0xc0900000 +0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 ; 0xc1100000 +0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 ; 0xc1900000 +0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 ; 0xbe100000 +0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 ; 0xbe900000 +0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 ; 0xbf100000 +0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 ; 0xbf900000 +0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 ; 0xc0180000 +0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 ; 0xc0980000 +0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 ; 0xc1180000 +0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 ; 0xc1980000 +0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 ; 0xbe180000 +0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 ; 0xbe980000 +0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 ; 0xbf180000 +0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 ; 0xbf980000 +0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 ; 0xc0200000 +0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 ; 0xc0a00000 +0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 ; 0xc1200000 +0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 ; 0xc1a00000 +0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 ; 0xbe200000 +0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 ; 0xbea00000 +0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 ; 0xbf200000 +0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 ; 0xbfa00000 +0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 ; 0xc0280000 +0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 ; 0xc0a80000 +0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 ; 0xc1280000 +0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 ; 0xc1a80000 +0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 ; 0xbe280000 +0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 ; 0xbea80000 +0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 ; 0xbf280000 +0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 ; 0xbfa80000 +0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 ; 0xc0300000 +0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 ; 0xc0b00000 +0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 ; 0xc1300000 +0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 ; 0xc1b00000 +0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 ; 0xbe300000 +0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 ; 0xbeb00000 +0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 ; 0xbf300000 +0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 ; 0xbfb00000 +0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 ; 0xc0380000 +0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 ; 0xc0b80000 +0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 ; 0xc1380000 +0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 ; 0xc1b80000 +0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 ; 0xbe380000 +0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 ; 0xbeb80000 +0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 ; 0xbf380000 +0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 ; 0xbfb80000 +0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 ; 0xc0400000 +0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 ; 0xc0c00000 +0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 ; 0xc1400000 +0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 ; 0xc1c00000 +0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 ; 0xbe400000 +0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 ; 0xbec00000 +0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 ; 0xbf400000 +0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 ; 0xbfc00000 +0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 ; 0xc0480000 +0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 ; 0xc0c80000 +0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 ; 0xc1480000 +0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 ; 0xc1c80000 +0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 ; 0xbe480000 +0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 ; 0xbec80000 +0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 ; 0xbf480000 +0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 ; 0xbfc80000 +0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 ; 0xc0500000 +0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 ; 0xc0d00000 +0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 ; 0xc1500000 +0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 ; 0xc1d00000 +0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 ; 0xbe500000 +0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 ; 0xbed00000 +0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 ; 0xbf500000 +0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 ; 0xbfd00000 +0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 ; 0xc0580000 +0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 ; 0xc0d80000 +0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 ; 0xc1580000 +0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 ; 0xc1d80000 +0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 ; 0xbe580000 +0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 ; 0xbed80000 +0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 ; 0xbf580000 +0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 ; 0xbfd80000 +0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 ; 0xc0600000 +0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 ; 0xc0e00000 +0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 ; 0xc1600000 +0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 ; 0xc1e00000 +0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 ; 0xbe600000 +0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 ; 0xbee00000 +0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 ; 0xbf600000 +0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 ; 0xbfe00000 +0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 ; 0xc0680000 +0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 ; 0xc0e80000 +0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 ; 0xc1680000 +0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 ; 0xc1e80000 +0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 ; 0xbe680000 +0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 ; 0xbee80000 +0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 ; 0xbf680000 +0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 ; 0xbfe80000 +0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 ; 0xc0700000 +0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 ; 0xc0f00000 +0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 ; 0xc1700000 +0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 ; 0xc1f00000 +0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 ; 0xbe700000 +0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 ; 0xbef00000 +0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 ; 0xbf700000 +0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 ; 0xbff00000 +0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 ; 0xc0780000 +0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 ; 0xc0f80000 +0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 ; 0xc1780000 +0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 ; 0xc1f80000 +0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 ; 0xbe780000 +0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 ; 0xbef80000 +0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 ; 0xbf780000 +0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 ; 0xbff80000 diff --git a/gas/testsuite/gas/arm/neon-const.s b/gas/testsuite/gas/arm/neon-const.s new file mode 100644 index 000000000000..a6fb55075a93 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-const.s @@ -0,0 +1,297 @@ +@ test floating-point constant parsing. + + .arm + .text + .syntax unified + + vmov.f32 q0, 0.0 + + vmov.f32 q0, 2.0 + vmov.f32 q0, 4.0 + vmov.f32 q0, 8.0 + vmov.f32 q0, 16.0 + vmov.f32 q0, 0.125 + vmov.f32 q0, 0.25 + vmov.f32 q0, 0.5 + vmov.f32 q0, 1.0 + + vmov.f32 q0, 2.125 + vmov.f32 q0, 4.25 + vmov.f32 q0, 8.5 + vmov.f32 q0, 17.0 + vmov.f32 q0, 0.1328125 + vmov.f32 q0, 0.265625 + vmov.f32 q0, 0.53125 + vmov.f32 q0, 1.0625 + + vmov.f32 q0, 2.25 + vmov.f32 q0, 4.5 + vmov.f32 q0, 9.0 + vmov.f32 q0, 18.0 + vmov.f32 q0, 0.140625 + vmov.f32 q0, 0.28125 + vmov.f32 q0, 0.5625 + vmov.f32 q0, 1.125 + + vmov.f32 q0, 2.375 + vmov.f32 q0, 4.75 + vmov.f32 q0, 9.5 + vmov.f32 q0, 19.0 + vmov.f32 q0, 0.1484375 + vmov.f32 q0, 0.296875 + vmov.f32 q0, 0.59375 + vmov.f32 q0, 1.1875 + + vmov.f32 q0, 2.5 + vmov.f32 q0, 5.0 + vmov.f32 q0, 10.0 + vmov.f32 q0, 20.0 + vmov.f32 q0, 0.15625 + vmov.f32 q0, 0.3125 + vmov.f32 q0, 0.625 + vmov.f32 q0, 1.25 + + vmov.f32 q0, 2.625 + vmov.f32 q0, 5.25 + vmov.f32 q0, 10.5 + vmov.f32 q0, 21.0 + vmov.f32 q0, 0.1640625 + vmov.f32 q0, 0.328125 + vmov.f32 q0, 0.65625 + vmov.f32 q0, 1.3125 + + vmov.f32 q0, 2.75 + vmov.f32 q0, 5.5 + vmov.f32 q0, 11.0 + vmov.f32 q0, 22.0 + vmov.f32 q0, 0.171875 + vmov.f32 q0, 0.34375 + vmov.f32 q0, 0.6875 + vmov.f32 q0, 1.375 + + vmov.f32 q0, 2.875 + vmov.f32 q0, 5.75 + vmov.f32 q0, 11.5 + vmov.f32 q0, 23.0 + vmov.f32 q0, 0.1796875 + vmov.f32 q0, 0.359375 + vmov.f32 q0, 0.71875 + vmov.f32 q0, 1.4375 + + vmov.f32 q0, 3.0 + vmov.f32 q0, 6.0 + vmov.f32 q0, 12.0 + vmov.f32 q0, 24.0 + vmov.f32 q0, 0.1875 + vmov.f32 q0, 0.375 + vmov.f32 q0, 0.75 + vmov.f32 q0, 1.5 + + vmov.f32 q0, 3.125 + vmov.f32 q0, 6.25 + vmov.f32 q0, 12.5 + vmov.f32 q0, 25.0 + vmov.f32 q0, 0.1953125 + vmov.f32 q0, 0.390625 + vmov.f32 q0, 0.78125 + vmov.f32 q0, 1.5625 + + vmov.f32 q0, 3.25 + vmov.f32 q0, 6.5 + vmov.f32 q0, 13.0 + vmov.f32 q0, 26.0 + vmov.f32 q0, 0.203125 + vmov.f32 q0, 0.40625 + vmov.f32 q0, 0.8125 + vmov.f32 q0, 1.625 + + vmov.f32 q0, 3.375 + vmov.f32 q0, 6.75 + vmov.f32 q0, 13.5 + vmov.f32 q0, 27.0 + vmov.f32 q0, 0.2109375 + vmov.f32 q0, 0.421875 + vmov.f32 q0, 0.84375 + vmov.f32 q0, 1.6875 + + vmov.f32 q0, 3.5 + vmov.f32 q0, 7.0 + vmov.f32 q0, 14.0 + vmov.f32 q0, 28.0 + vmov.f32 q0, 0.21875 + vmov.f32 q0, 0.4375 + vmov.f32 q0, 0.875 + vmov.f32 q0, 1.75 + + vmov.f32 q0, 3.625 + vmov.f32 q0, 7.25 + vmov.f32 q0, 14.5 + vmov.f32 q0, 29.0 + vmov.f32 q0, 0.2265625 + vmov.f32 q0, 0.453125 + vmov.f32 q0, 0.90625 + vmov.f32 q0, 1.8125 + + vmov.f32 q0, 3.75 + vmov.f32 q0, 7.5 + vmov.f32 q0, 15.0 + vmov.f32 q0, 30.0 + vmov.f32 q0, 0.234375 + vmov.f32 q0, 0.46875 + vmov.f32 q0, 0.9375 + vmov.f32 q0, 1.875 + + vmov.f32 q0, 3.875 + vmov.f32 q0, 7.75 + vmov.f32 q0, 15.5 + vmov.f32 q0, 31.0 + vmov.f32 q0, 0.2421875 + vmov.f32 q0, 0.484375 + vmov.f32 q0, 0.96875 + vmov.f32 q0, 1.9375 + + vmov.f32 q0, -0.0 + + vmov.f32 q0, -2.0 + vmov.f32 q0, -4.0 + vmov.f32 q0, -8.0 + vmov.f32 q0, -16.0 + vmov.f32 q0, -0.125 + vmov.f32 q0, -0.25 + vmov.f32 q0, -0.5 + vmov.f32 q0, -1.0 + + vmov.f32 q0, -2.125 + vmov.f32 q0, -4.25 + vmov.f32 q0, -8.5 + vmov.f32 q0, -17.0 + vmov.f32 q0, -0.1328125 + vmov.f32 q0, -0.265625 + vmov.f32 q0, -0.53125 + vmov.f32 q0, -1.0625 + + vmov.f32 q0, -2.25 + vmov.f32 q0, -4.5 + vmov.f32 q0, -9.0 + vmov.f32 q0, -18.0 + vmov.f32 q0, -0.140625 + vmov.f32 q0, -0.28125 + vmov.f32 q0, -0.5625 + vmov.f32 q0, -1.125 + + vmov.f32 q0, -2.375 + vmov.f32 q0, -4.75 + vmov.f32 q0, -9.5 + vmov.f32 q0, -19.0 + vmov.f32 q0, -0.1484375 + vmov.f32 q0, -0.296875 + vmov.f32 q0, -0.59375 + vmov.f32 q0, -1.1875 + + vmov.f32 q0, -2.5 + vmov.f32 q0, -5.0 + vmov.f32 q0, -10.0 + vmov.f32 q0, -20.0 + vmov.f32 q0, -0.15625 + vmov.f32 q0, -0.3125 + vmov.f32 q0, -0.625 + vmov.f32 q0, -1.25 + + vmov.f32 q0, -2.625 + vmov.f32 q0, -5.25 + vmov.f32 q0, -10.5 + vmov.f32 q0, -21.0 + vmov.f32 q0, -0.1640625 + vmov.f32 q0, -0.328125 + vmov.f32 q0, -0.65625 + vmov.f32 q0, -1.3125 + + vmov.f32 q0, -2.75 + vmov.f32 q0, -5.5 + vmov.f32 q0, -11.0 + vmov.f32 q0, -22.0 + vmov.f32 q0, -0.171875 + vmov.f32 q0, -0.34375 + vmov.f32 q0, -0.6875 + vmov.f32 q0, -1.375 + + vmov.f32 q0, -2.875 + vmov.f32 q0, -5.75 + vmov.f32 q0, -11.5 + vmov.f32 q0, -23.0 + vmov.f32 q0, -0.1796875 + vmov.f32 q0, -0.359375 + vmov.f32 q0, -0.71875 + vmov.f32 q0, -1.4375 + + vmov.f32 q0, -3.0 + vmov.f32 q0, -6.0 + vmov.f32 q0, -12.0 + vmov.f32 q0, -24.0 + vmov.f32 q0, -0.1875 + vmov.f32 q0, -0.375 + vmov.f32 q0, -0.75 + vmov.f32 q0, -1.5 + + vmov.f32 q0, -3.125 + vmov.f32 q0, -6.25 + vmov.f32 q0, -12.5 + vmov.f32 q0, -25.0 + vmov.f32 q0, -0.1953125 + vmov.f32 q0, -0.390625 + vmov.f32 q0, -0.78125 + vmov.f32 q0, -1.5625 + + vmov.f32 q0, -3.25 + vmov.f32 q0, -6.5 + vmov.f32 q0, -13.0 + vmov.f32 q0, -26.0 + vmov.f32 q0, -0.203125 + vmov.f32 q0, -0.40625 + vmov.f32 q0, -0.8125 + vmov.f32 q0, -1.625 + + vmov.f32 q0, -3.375 + vmov.f32 q0, -6.75 + vmov.f32 q0, -13.5 + vmov.f32 q0, -27.0 + vmov.f32 q0, -0.2109375 + vmov.f32 q0, -0.421875 + vmov.f32 q0, -0.84375 + vmov.f32 q0, -1.6875 + + vmov.f32 q0, -3.5 + vmov.f32 q0, -7.0 + vmov.f32 q0, -14.0 + vmov.f32 q0, -28.0 + vmov.f32 q0, -0.21875 + vmov.f32 q0, -0.4375 + vmov.f32 q0, -0.875 + vmov.f32 q0, -1.75 + + vmov.f32 q0, -3.625 + vmov.f32 q0, -7.25 + vmov.f32 q0, -14.5 + vmov.f32 q0, -29.0 + vmov.f32 q0, -0.2265625 + vmov.f32 q0, -0.453125 + vmov.f32 q0, -0.90625 + vmov.f32 q0, -1.8125 + + vmov.f32 q0, -3.75 + vmov.f32 q0, -7.5 + vmov.f32 q0, -15.0 + vmov.f32 q0, -30.0 + vmov.f32 q0, -0.234375 + vmov.f32 q0, -0.46875 + vmov.f32 q0, -0.9375 + vmov.f32 q0, -1.875 + + vmov.f32 q0, -3.875 + vmov.f32 q0, -7.75 + vmov.f32 q0, -15.5 + vmov.f32 q0, -31.0 + vmov.f32 q0, -0.2421875 + vmov.f32 q0, -0.484375 + vmov.f32 q0, -0.96875 + vmov.f32 q0, -1.9375 diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d new file mode 100644 index 000000000000..e3f02f811f14 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cov.d @@ -0,0 +1,1522 @@ +# name: Neon instruction coverage +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000710 vaba\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100710 vaba\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200710 vaba\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000710 vaba\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100710 vaba\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200710 vaba\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000000 vhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100000 vhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200000 vhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000000 vhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100000 vhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200000 vhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000100 vrhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100100 vrhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200100 vrhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000100 vrhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100100 vrhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200100 vrhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000200 vhsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100200 vhsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200200 vhsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000200 vhsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100200 vhsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200200 vhsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000010 vqadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100010 vqadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200010 vqadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300010 vqadd\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000010 vqadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100010 vqadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200010 vqadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300010 vqadd\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000210 vqsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100210 vqsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200210 vqsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300210 vqsub\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000210 vqsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100210 vqsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200210 vqsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300210 vqsub\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000500 vrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100500 vrshl\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200500 vrshl\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300500 vrshl\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000500 vrshl\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100500 vrshl\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200500 vrshl\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300500 vrshl\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000510 vqrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, 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q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200110 vbit d0, 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+0[0-9a-f]+ <[^>]+> f3000f00 vpmax\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000a10 vpmin\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100a10 vpmin\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200a10 vpmin\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000a10 vpmin\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100a10 vpmin\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200a10 vpmin\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200f00 vpmin\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000940 vmla\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000940 vmla\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000900 vmla\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100940 vmla\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100940 vmla\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100900 vmla\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d10 vmla\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900040 vmla\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900040 vmla\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900040 vmla\.i16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00140 vmla\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000900 vmls\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100900 vmls\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d10 vmls\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900440 vmls\.i16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00540 vmls\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2000b10 vpadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b10 vpadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d00 vpadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000800 vadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100800 vadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300800 vadd\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d00 vadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000800 vsub\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100800 vsub\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300800 vsub\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d00 vsub\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000810 vtst\.8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100810 vtst\.16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200810 vtst\.32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000910 vmul\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100910 vmul\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d10 vmul\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000910 vmul\.p8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b00 vqdmulh\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b40 vqdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200b40 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<[^>]+> f3a00d40 vqrdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00d40 vqrdmulh\.s32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f10 vrecps\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> 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q0, #31 +0[0-9a-f]+ <[^>]+> f3890910 vqshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910910 vqshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10910 vqshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890950 vqrshrn\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910950 vqrshrn\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10950 vqrshrn\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890950 vqrshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910950 vqrshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10950 vqrshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890810 vqshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910810 vqshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10810 vqshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890850 vqrshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910850 vqrshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10850 vqrshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890810 vshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10810 vshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890850 vrshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f2a10a10 vshll\.s32 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3890a10 vshll\.u8 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3910a10 vshll\.u16 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3a10a10 vshll\.u32 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8 +0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0700 vcvt\.s32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0780 vcvt\.u32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0600 vcvt\.f32\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0680 vcvt\.f32\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f10 vcvt\.s32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f10 vcvt\.u32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e10 vcvt\.f32\.s32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e10 vcvt\.f32\.u32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2200150 vorr q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200110 vorr d0, d0, d0 +0[0-9a-f]+ <[^>]+> ee400b10 vmov\.8 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b30 vmov\.16 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ec400b10 vmov d0, r0, r0 +0[0-9a-f]+ <[^>]+> ee500b10 vmov\.s8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> eed00b10 vmov\.u8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee900b30 vmov\.u16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f3810e71 vmov\.i64 q0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0 +0[0-9a-f]+ <[^>]+> f2800500 vabal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900500 vabal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00500 vabal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800500 vabal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900500 vabal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00500 vabal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800700 vabdl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900700 vabdl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00700 vabdl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800700 vabdl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900700 vabdl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00700 vabdl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800000 vaddl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900000 vaddl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00000 vaddl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800000 vaddl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900000 vaddl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00000 vaddl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800200 vsubl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900200 vsubl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00200 vsubl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800200 vsubl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900200 vsubl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00200 vsubl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800800 vmlal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900800 vmlal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00800 vmlal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800800 vmlal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900800 vmlal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00800 vmlal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900240 vmlal\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00240 vmlal\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900240 vmlal\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00240 vmlal\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800a00 vmlsl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900a00 vmlsl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00a00 vmlsl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800a00 vmlsl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900a00 vmlsl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00a00 vmlsl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900640 vmlsl\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00640 vmlsl\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900640 vmlsl\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00640 vmlsl\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800100 vaddw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900100 vaddw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00100 vaddw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800100 vaddw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900100 vaddw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00100 vaddw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800300 vsubw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900300 vsubw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00300 vsubw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800300 vsubw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900300 vsubw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00300 vsubw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800400 vaddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2a00400 vaddhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3800400 vraddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 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vpaddl\.u16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80280 vpaddl\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0400 vrecpe\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0500 vrecpe\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0480 vrsqrte\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0580 vrsqrte\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00400 vcls\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40400 vcls\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80400 vcls\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00480 vclz\.i8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40480 vclz\.i16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00500 vcnt\.8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20001 vswp d0, d1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20081 vtrn\.8 d0, d1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60081 vtrn\.16 d0, d1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0081 vtrn\.32 d0, d1 +0[0-9a-f]+ <[^>]+> f3b00800 vtbl\.8 d0, {d0}, d0 +0[0-9a-f]+ <[^>]+> f3b00840 vtbx\.8 d0, {d0}, d0 diff --git a/gas/testsuite/gas/arm/neon-cov.s b/gas/testsuite/gas/arm/neon-cov.s new file mode 100644 index 000000000000..04194a83eb07 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cov.s @@ -0,0 +1,666 @@ +@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as +@ possible, but without causing instructions to be badly-formed. + + .arm + .syntax unified + .text + + .macro regs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro dregs3_1 op vtype + \op\vtype d0,d0,d0 + .endm + + .macro regn3_1 op operand2 vtype + \op\vtype d0,q0,\operand2 + .endm + + .macro regl3_1 op operand2 vtype + \op\vtype q0,d0,\operand2 + .endm + + .macro regw3_1 op operand2 vtype + \op\vtype q0,q0,\operand2 + .endm + + .macro regs2_1 op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + .macro regs3_su_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + .endm + + regs3_su_32 vaba vabaq + regs3_su_32 vhadd vhaddq + regs3_su_32 vrhadd vrhaddq + regs3_su_32 vhsub vhsubq + + .macro regs3_su_64 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .s64 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .u64 + .endm + + regs3_su_64 vqadd vqaddq + regs3_su_64 vqsub vqsubq + regs3_su_64 vrshl vrshlq + regs3_su_64 vqrshl vqrshlq + + regs3_su_64 vshl vshlq + regs3_su_64 vqshl vqshlq + + .macro regs2i_1 op opq imm vtype + \op\vtype q0,q0,\imm + \opq\vtype q0,q0,\imm + \op\vtype d0,d0,\imm + .endm + + .macro regs2i_su_64 op opq imm + regs2i_1 \op \opq \imm .s8 + regs2i_1 \op \opq \imm .s16 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .s64 + regs2i_1 \op \opq \imm .u8 + regs2i_1 \op \opq \imm .u16 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .u64 + .endm + + .macro regs2i_i_64 op opq imm + regs2i_1 \op \opq \imm .i8 + regs2i_1 \op \opq \imm .i16 + regs2i_1 \op \opq \imm .i32 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .i64 + .endm + + regs2i_i_64 vshl vshlq 0 + regs2i_su_64 vqshl vqshlq 0 + + .macro regs3_ntyp op opq + regs3_1 \op \opq .8 + .endm + + regs3_ntyp vand vandq + regs3_ntyp vbic vbicq + regs3_ntyp vorr vorrq + regs3_ntyp vorn vornq + regs3_ntyp veor veorq + + .macro logic_imm_1 op opq imm vtype + \op\vtype q0,\imm + \opq\vtype q0,\imm + \op\vtype d0,\imm + .endm + + .macro logic_imm op opq + logic_imm_1 \op \opq 0x000000a5000000a5 .i64 + logic_imm_1 \op \opq 0x0000a5000000a500 .i64 + logic_imm_1 \op \opq 0x00a5000000a50000 .i64 + logic_imm_1 \op \opq 0xa5000000a5000000 .i64 + logic_imm_1 \op \opq 0x00a500a500a500a5 .i64 + logic_imm_1 \op \opq 0xa500a500a500a500 .i64 + logic_imm_1 \op \opq 0x000000ff .i32 + logic_imm_1 \op \opq 0x000000ff .s32 + logic_imm_1 \op \opq 0x000000ff .u32 + logic_imm_1 \op \opq 0x0000ff00 .i32 + logic_imm_1 \op \opq 0x00ff0000 .i32 + logic_imm_1 \op \opq 0xff000000 .i32 + logic_imm_1 \op \opq 0x00a500a5 .i32 + logic_imm_1 \op \opq 0xa500a500 .i32 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00 .i8 + .endm + + logic_imm vbic vbicq + logic_imm vorr vorrq + + .macro logic_inv_imm op opq + logic_imm_1 \op \opq 0xffffff5affffff5a .i64 + logic_imm_1 \op \opq 0xffff5affffff5aff .i64 + logic_imm_1 \op \opq 0xff5affffff5affff .i64 + logic_imm_1 \op \opq 0x5affffff5affffff .i64 + logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64 + logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64 + logic_imm_1 \op \opq 0xffffff00 .i32 + logic_imm_1 \op \opq 0xffffff00 .s32 + logic_imm_1 \op \opq 0xffffff00 .u32 + logic_imm_1 \op \opq 0xffff00ff .i32 + logic_imm_1 \op \opq 0xff00ffff .i32 + logic_imm_1 \op \opq 0x00ffffff .i32 + logic_imm_1 \op \opq 0xff5aff5a .i32 + logic_imm_1 \op \opq 0x5aff5aff .i32 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff .i8 + .endm + + logic_inv_imm vand vandq + logic_inv_imm vorn vornq + + regs3_ntyp vbsl vbslq + regs3_ntyp vbit vbitq + regs3_ntyp vbif vbifq + + .macro regs3_suf_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + .macro regs3_if_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + regs3_suf_32 vabd vabdq + regs3_suf_32 vmax vmaxq + regs3_suf_32 vmin vminq + + regs3_suf_32 vcge vcgeq + regs3_suf_32 vcgt vcgtq + regs3_suf_32 vcle vcleq + regs3_suf_32 vclt vcltq + + regs3_if_32 vceq vceqq + + .macro regs2i_sf_0 op opq + regs2i_1 \op \opq 0 .s8 + regs2i_1 \op \opq 0 .s16 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_sf_0 vcge vcgeq + regs2i_sf_0 vcgt vcgtq + regs2i_sf_0 vcle vcleq + regs2i_sf_0 vclt vcltq + + .macro regs2i_if_0 op opq + regs2i_1 \op \opq 0 .i8 + regs2i_1 \op \opq 0 .i16 + regs2i_1 \op \opq 0 .i32 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .u32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_if_0 vceq vceqq + + .macro dregs3_suf_32 op + dregs3_1 \op .s8 + dregs3_1 \op .s16 + dregs3_1 \op .s32 + dregs3_1 \op .u8 + dregs3_1 \op .u16 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_suf_32 vpmax + dregs3_suf_32 vpmin + + .macro sregs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro sclr21_1 op opq vtype + \op\vtype q0,q0,d0[0] + \opq\vtype q0,q0,d0[0] + \op\vtype d0,d0,d0[0] + .endm + + .macro mul_incl_scalar op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + sclr21_1 \op \opq .i16 + sclr21_1 \op \opq .i32 + sclr21_1 \op \opq .s32 + sclr21_1 \op \opq .u32 + sclr21_1 \op \opq .f32 + .endm + + mul_incl_scalar vmla vmlaq + mul_incl_scalar vmls vmlsq + + .macro dregs3_if_32 op + dregs3_1 \op .i8 + dregs3_1 \op .i16 + dregs3_1 \op .i32 + dregs3_1 \op .s32 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_if_32 vpadd + + .macro regs3_if_64 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .i64 + regs3_1 \op \opq .f32 + .endm + + regs3_if_64 vadd vaddq + regs3_if_64 vsub vsubq + + .macro regs3_sz_32 op opq + regs3_1 \op \opq .8 + regs3_1 \op \opq .16 + regs3_1 \op \opq .32 + .endm + + regs3_sz_32 vtst vtstq + + .macro regs3_ifp_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + regs3_1 \op \opq .p8 + .endm + + regs3_ifp_32 vmul vmulq + + .macro dqmulhs op opq + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + sclr21_1 \op \opq .s16 + sclr21_1 \op \opq .s32 + .endm + + dqmulhs vqdmulh vqdmulhq + dqmulhs vqrdmulh vqrdmulhq + + regs3_1 vacge vacgeq .f32 + regs3_1 vacgt vacgtq .f32 + regs3_1 vacle vacleq .f32 + regs3_1 vaclt vacltq .f32 + regs3_1 vrecps vrecpsq .f32 + regs3_1 vrsqrts vrsqrtsq .f32 + + .macro regs2_sf_32 op opq + regs2_1 \op \opq .s8 + regs2_1 \op \opq .s16 + regs2_1 \op \opq .s32 + regs2_1 \op \opq .f32 + .endm + + regs2_sf_32 vabs vabsq + regs2_sf_32 vneg vnegq + + .macro rshift_imm op opq + regs2i_1 \op \opq 7 .s8 + regs2i_1 \op \opq 15 .s16 + regs2i_1 \op \opq 31 .s32 + regs2i_1 \op \opq 63 .s64 + regs2i_1 \op \opq 7 .u8 + regs2i_1 \op \opq 15 .u16 + regs2i_1 \op \opq 31 .u32 + regs2i_1 \op \opq 63 .u64 + .endm + + rshift_imm vshr vshrq + rshift_imm vrshr vrshrq + rshift_imm vsra vsraq + rshift_imm vrsra vrsraq + + regs2i_1 vsli vsliq 0 .8 + regs2i_1 vsli vsliq 0 .16 + regs2i_1 vsli vsliq 0 .32 + regs2i_1 vsli vsliq 0 .64 + + regs2i_1 vsri vsriq 7 .8 + regs2i_1 vsri vsriq 15 .16 + regs2i_1 vsri vsriq 31 .32 + regs2i_1 vsri vsriq 63 .64 + + regs2i_1 vqshlu vqshluq 0 .s8 + regs2i_1 vqshlu vqshluq 0 .s16 + regs2i_1 vqshlu vqshluq 0 .s32 + regs2i_1 vqshlu vqshluq 0 .s64 + + .macro qrshift_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + regn3_1 \op 7 .u16 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .u64 + .endm + + .macro qrshiftu_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + .endm + + .macro qrshifti_imm op + regn3_1 \op 7 .i16 + regn3_1 \op 15 .i32 + regn3_1 \op 15 .s32 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .i64 + .endm + + qrshift_imm vqshrn + qrshift_imm vqrshrn + qrshiftu_imm vqshrun + qrshiftu_imm vqrshrun + + qrshifti_imm vshrn + qrshifti_imm vrshrn + + regl3_1 vshll 1 .s8 + regl3_1 vshll 1 .s16 + regl3_1 vshll 1 .s32 + regl3_1 vshll 1 .u8 + regl3_1 vshll 1 .u16 + regl3_1 vshll 1 .u32 + + regl3_1 vshll 8 .i8 + regl3_1 vshll 16 .i16 + regl3_1 vshll 32 .i32 + regl3_1 vshll 32 .s32 + regl3_1 vshll 32 .u32 + + .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32" + \op\t1 \opr,\opr\arg + \op\t2 \opr,\opr\arg + \op\t3 \opr,\opr\arg + \op\t4 \opr,\opr\arg + .endm + + convert vcvt q0 + convert vcvtq q0 + convert vcvt d0 + convert vcvt q0 ",1" + convert vcvtq q0 ",1" + convert vcvt d0 ",1" + + vmov q0,q0 + vmov d0,d0 + vmov.8 d0[0],r0 + vmov.16 d0[0],r0 + vmov.32 d0[0],r0 + vmov d0,r0,r0 + vmov.s8 r0,d0[0] + vmov.s16 r0,d0[0] + vmov.u8 r0,d0[0] + vmov.u16 r0,d0[0] + vmov.32 r0,d0[0] + vmov r0,r1,d0 + + .macro mov_imm op imm vtype + \op\vtype q0,\imm + \op\vtype d0,\imm + .endm + + mov_imm vmov 0x00000077 .i32 + mov_imm vmov 0x00000077 .s32 + mov_imm vmov 0x00000077 .u32 + mov_imm vmvn 0x00000077 .i32 + mov_imm vmvn 0x00000077 .s32 + mov_imm vmvn 0x00000077 .u32 + mov_imm vmov 0x00007700 .i32 + mov_imm vmvn 0x00007700 .i32 + mov_imm vmov 0x00770000 .i32 + mov_imm vmvn 0x00770000 .i32 + mov_imm vmov 0x77000000 .i32 + mov_imm vmvn 0x77000000 .i32 + mov_imm vmov 0x0077 .i16 + mov_imm vmvn 0x0077 .i16 + mov_imm vmov 0x7700 .i16 + mov_imm vmvn 0x7700 .i16 + mov_imm vmov 0x000077ff .i32 + mov_imm vmvn 0x000077ff .i32 + mov_imm vmov 0x0077ffff .i32 + mov_imm vmvn 0x0077ffff .i32 + mov_imm vmov 0x77 .i8 + mov_imm vmov 0xff0000ff000000ff .i64 + mov_imm vmov 4.25 .f32 + + mov_imm vmov 0xa5a5 .i16 + mov_imm vmvn 0xa5a5 .i16 + mov_imm vmov 0xa5a5a5a5 .i32 + mov_imm vmvn 0xa5a5a5a5 .i32 + mov_imm vmov 0x00a500a5 .i32 + mov_imm vmov 0xa500a500 .i32 + mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmov 0x00a500a500a500a5 .i64 + mov_imm vmov 0xa500a500a500a500 .i64 + mov_imm vmov 0x000000a5000000a5 .i64 + mov_imm vmov 0x0000a5000000a500 .i64 + mov_imm vmov 0x00a5000000a50000 .i64 + mov_imm vmov 0xa5000000a5000000 .i64 + mov_imm vmov 0x0000a5ff0000a5ff .i64 + mov_imm vmov 0x00a5ffff00a5ffff .i64 + mov_imm vmov 0xa5ffffffa5ffffff .i64 + + vmvn q0,q0 + vmvnq q0,q0 + vmvn d0,d0 + + .macro long_ops op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + .endm + + long_ops vabal + long_ops vabdl + long_ops vaddl + long_ops vsubl + + .macro long_mac op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + regl3_1 \op "d0[0]" .u16 + regl3_1 \op "d0[0]" .u32 + .endm + + long_mac vmlal + long_mac vmlsl + + .macro wide_ops op + regw3_1 \op d0 .s8 + regw3_1 \op d0 .s16 + regw3_1 \op d0 .s32 + regw3_1 \op d0 .u8 + regw3_1 \op d0 .u16 + regw3_1 \op d0 .u32 + .endm + + wide_ops vaddw + wide_ops vsubw + + .macro narr_ops op + regn3_1 \op q0 .i16 + regn3_1 \op q0 .i32 + regn3_1 \op q0 .s32 + regn3_1 \op q0 .u32 + regn3_1 \op q0 .i64 + .endm + + narr_ops vaddhn + narr_ops vraddhn + narr_ops vsubhn + narr_ops vrsubhn + + .macro long_dmac op + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + .endm + + long_dmac vqdmlal + long_dmac vqdmlsl + long_dmac vqdmull + + regl3_1 vmull d0 .s8 + regl3_1 vmull d0 .s16 + regl3_1 vmull d0 .s32 + regl3_1 vmull d0 .u8 + regl3_1 vmull d0 .u16 + regl3_1 vmull d0 .u32 + regl3_1 vmull d0 .p8 + regl3_1 vmull "d0[0]" .s16 + regl3_1 vmull "d0[0]" .s32 + regl3_1 vmull "d0[0]" .u16 + regl3_1 vmull "d0[0]" .u32 + + vext.8 q0,q0,q0,0 + vextq.8 q0,q0,q0,0 + vext.8 d0,d0,d0,0 + vext.8 q0,q0,q0,8 + + .macro revs op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + revs vrev64 vrev64q .8 + revs vrev64 vrev64q .16 + revs vrev64 vrev64q .32 + revs vrev32 vrev32q .8 + revs vrev32 vrev32q .16 + revs vrev16 vrev16q .8 + + .macro dups op opq vtype + \op\vtype q0,r0 + \opq\vtype q0,r0 + \op\vtype d0,r0 + \op\vtype q0,d0[0] + \opq\vtype q0,d0[0] + \op\vtype d0,d0[0] + .endm + + dups vdup vdupq .8 + dups vdup vdupq .16 + dups vdup vdupq .32 + + .macro binop_3typ op op1 op2 t1 t2 t3 + \op\t1 \op1,\op2 + \op\t2 \op1,\op2 + \op\t3 \op1,\op2 + .endm + + binop_3typ vmovl q0 d0 .s8 .s16 .s32 + binop_3typ vmovl q0 d0 .u8 .u16 .u32 + binop_3typ vmovn d0 q0 .i16 .i32 .i64 + vmovn.s32 d0, q0 + vmovn.u32 d0, q0 + binop_3typ vqmovn d0 q0 .s16 .s32 .s64 + binop_3typ vqmovn d0 q0 .u16 .u32 .u64 + binop_3typ vqmovun d0 q0 .s16 .s32 .s64 + + .macro binops op opq vtype="" rhs="0" + \op\vtype q0,q\rhs + \opq\vtype q0,q\rhs + \op\vtype d0,d\rhs + .endm + + .macro regs2_sz_32 op opq + binops \op \opq .8 1 + binops \op \opq .16 1 + binops \op \opq .32 1 + .endm + + regs2_sz_32 vzip vzipq + regs2_sz_32 vuzp vuzpq + + .macro regs2_s_32 op opq + binops \op \opq .s8 + binops \op \opq .s16 + binops \op \opq .s32 + .endm + + regs2_s_32 vqabs vqabsq + regs2_s_32 vqneg vqnegq + + .macro regs2_su_32 op opq + regs2_s_32 \op \opq + binops \op \opq .u8 + binops \op \opq .u16 + binops \op \opq .u32 + .endm + + regs2_su_32 vpadal vpadalq + regs2_su_32 vpaddl vpaddlq + + binops vrecpe vrecpeq .u32 + binops vrecpe vrecpeq .f32 + binops vrsqrte vrsqrteq .u32 + binops vrsqrte vrsqrteq .f32 + + regs2_s_32 vcls vclsq + + .macro regs2_i_32 op opq + binops \op \opq .i8 + binops \op \opq .i16 + binops \op \opq .i32 + binops \op \opq .s32 + binops \op \opq .u32 + .endm + + regs2_i_32 vclz vclzq + + binops vcnt vcntq .8 + + binops vswp vswpq "" 1 + + regs2_sz_32 vtrn vtrnq + + vtbl.8 d0,{d0},d0 + vtbx.8 d0,{d0},d0 + diff --git a/gas/testsuite/gas/arm/neon-ldst-es.d b/gas/testsuite/gas/arm/neon-ldst-es.d new file mode 100644 index 000000000000..c520ac93116b --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-es.d @@ -0,0 +1,57 @@ +# name: Neon element and structure loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f406282f vst2\.8 {d2-d3}, \[r6, :128\] +0[0-9a-f]+ <[^>]+> f427140d vld3\.8 {d1-d3}, \[r7\]! +0[0-9a-f]+ <[^>]+> f4091553 vst3\.16 {d1,d3,d5}, \[r9, :64\], r3 +0[0-9a-f]+ <[^>]+> f42a208f vld4\.32 {d2-d5}, \[sl\] +0[0-9a-f]+ <[^>]+> f40a114f vst4\.16 {d1,d3,d5,d7}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c6f vld1\.16 {d1\[\]-d2\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c5f vld1\.16 {d1\[\]}, \[sl, :16\] +0[0-9a-f]+ <[^>]+> f4aa1dbf vld2\.32 {d1\[\],d3\[\]}, \[sl, :64\] +0[0-9a-f]+ <[^>]+> f4aa3e0c vld3\.8 {d3\[\]-d5\[\]}, \[sl\], ip +0[0-9a-f]+ <[^>]+> f4a9af6d vld4\.16 {d10\[\],d12\[\],d14\[\],d16\[\]}, \[r9\]! +0[0-9a-f]+ <[^>]+> f4a9af5f vld4\.16 {d10\[\]-d13\[\]}, \[r9, :64\] +0[0-9a-f]+ <[^>]+> f4a9af9f vld4\.32 {d10\[\]-d13\[\]}, \[r9, :64\] +0[0-9a-f]+ <[^>]+> f4a9afdf vld4\.32 {d10\[\]-d13\[\]}, \[r9, :128\] +0[0-9a-f]+ <[^>]+> f4a530ed vld1\.8 {d3\[7\]}, \[r5\]! +0[0-9a-f]+ <[^>]+> f48554df vst1\.16 {d5\[3\]}, \[r5, :16\] +0[0-9a-f]+ <[^>]+> f4a535dd vld2\.16 {d3\[3\],d4\[3\]}, \[r5, :32\]! +0[0-9a-f]+ <[^>]+> f4858a83 vst3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r5\], r3 +0[0-9a-f]+ <[^>]+> f4a7804f vld1\.8 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7848f vld1\.16 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7849f vld1\.16 {d8\[2\]}, \[r7, :16\] +0[0-9a-f]+ <[^>]+> f4a7888f vld1\.32 {d8\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a788bf vld1\.32 {d8\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7812f vld2\.8 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7813f vld2\.8 {d8\[1\],d9\[1\]}, \[r7, :16\] +0[0-9a-f]+ <[^>]+> f4a7854f vld2\.16 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7855f vld2\.16 {d8\[1\],d9\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7856f vld2\.16 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7857f vld2\.16 {d8\[1\],d10\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7898f vld2\.32 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7899f vld2\.32 {d8\[1\],d9\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a789cf vld2\.32 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a789df vld2\.32 {d8\[1\],d10\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a7822f vld3\.8 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7864f vld3\.16 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7866f vld3\.16 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78a8f vld3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78acf vld3\.32 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7834f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7835f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7876f vld4\.16 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7875f vld4\.16 {d8\[1\],d9\[1\],d10\[1\],d11\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a78bcf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78bdf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a78bef vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :128\] +0[0-9a-f]+ <[^>]+> f3b43805 vtbl\.8 d3, {d4}, d5 +0[0-9a-f]+ <[^>]+> f3b23b05 vtbl\.8 d3, {d2-d5}, d5 +0[0-9a-f]+ <[^>]+> f3be3985 vtbl\.8 d3, {d30-d31}, d5 +0[0-9a-f]+ <[^>]+> f427288f vld2\.32 {d2-d3}, \[r7\] +0[0-9a-f]+ <[^>]+> f427208f vld4\.32 {d2-d5}, \[r7\] +0[0-9a-f]+ <[^>]+> f467c08f vld4\.32 {d28-d31}, \[r7\] diff --git a/gas/testsuite/gas/arm/neon-ldst-es.s b/gas/testsuite/gas/arm/neon-ldst-es.s new file mode 100644 index 000000000000..5a29a4379390 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-es.s @@ -0,0 +1,59 @@ +@ test element and structure loads and stores. + + .text + .arm + .syntax unified + + vst2.8 {d2,d3},[r6,:128] + vld3.8 {d1,d2,d3},[r7]! + vst3.16 {d1,d3,d5},[r9,:64],r3 + vld4.32 {d2,d3,d4,d5},[r10] + vst4.16 {d1,d3,d5,d7},[r10] + vld1.16 {d1[],d2[]},[r10] + vld1.16 {d1[]},[r10,:16] + vld2.32 {d1[],d3[]},[r10,:64] + vld3.s8 {d3[],d4[],d5[]},[r10],r12 + vld4.16 {d10[],d12[],d14[],d16[]},[r9]! + vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128] + vld1.8 {d3[7]},[r5]! + vst1.16 {d5[3]},[r5,:16] + vld2.16 {d3[3],d4[3]},[r5,:32]! + vst3.32 {d8[1],d9[1],d10[1]},[r5],r3 + + vld1.8 {d8[2]},[r7] + vld1.16 {d8[2]},[r7] + vld1.16 {d8[2]},[r7,:16] + vld1.32 {d8[1]},[r7] + vld1.32 {d8[1]},[r7,:32] + vld2.8 {d8[1],d9[1]},[r7] + vld2.8 {d8[1],d9[1]},[r7,:16] + vld2.16 {d8[1],d9[1]},[r7] + vld2.16 {d8[1],d9[1]},[r7,:32] + vld2.16 {d8[1],d10[1]},[r7] + vld2.16 {d8[1],d10[1]},[r7,:32] + vld2.32 {d8[1],d9[1]},[r7] + vld2.32 {d8[1],d9[1]},[r7,:64] + vld2.32 {d8[1],d10[1]},[r7] + vld2.32 {d8[1],d10[1]},[r7,:64] + vld3.8 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d10[1],d12[1]},[r7] + vld3.32 {d8[1],d9[1],d10[1]},[r7] + vld3.32 {d8[1],d10[1],d12[1]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7,:32] + vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7,:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:128] + + vtbl.8 d3,{d4},d5 + vtbl.8 d3,{q1-q2},d5 + vtbl.8 d3,{q15},d5 + + vld2.32 {q1},[r7] + vld4.32 {q1-q2},[r7] + vld4.32 {q14-q15},[r7] diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.d b/gas/testsuite/gas/arm/neon-ldst-rm.d new file mode 100644 index 000000000000..86285d6dc35c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-rm.d @@ -0,0 +1,63 @@ +# name: Neon single and multiple register loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ecb22b02 vldmia r2!, {d2} +0[0-9a-f]+ <[^>]+> ecb22b04 vldmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ecb24b08 vldmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ecf28b10 vldmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ecb23b20 vldmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed322b02 vldmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed322b04 vldmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed324b08 vldmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed728b10 vldmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed323b20 vldmdb r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> eca22b02 vstmia r2!, {d2} +0[0-9a-f]+ <[^>]+> eca22b04 vstmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> eca24b08 vstmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ece28b10 vstmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> eca23b20 vstmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed222b02 vstmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed222b04 vstmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed224b08 vstmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18} +0[0-9a-f]+ <backward> 000001f4 .* +0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward> +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b01 vstr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed835b01 vstr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\] +0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\] +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\] +0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\] +0[0-9a-f]+ <forward> 000002bc .* +0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward> diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.s b/gas/testsuite/gas/arm/neon-ldst-rm.s new file mode 100644 index 000000000000..f9421ac5563c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-rm.s @@ -0,0 +1,44 @@ +@ test register and multi-register loads and stores. + + .text + .arm + .syntax unified + + .macro multi op dir="" wb="" + \op\dir r2\wb,{d2} + \op\dir r2\wb,{d2-d3} + \op\dir r2\wb,{q2-q3} + \op\dir r2\wb,{q12-q14,q15} + \op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18} + .endm + + multi vldm + multi vldm ia + multi vldm ia "!" + multi vldm db "!" + + multi vstm + multi vstm ia + multi vstm ia "!" + multi vstm db "!" + +backward: + .word 500 + + .macro single op offset="" + \op d5,[r3] + \op d5,[r3,#-\offset] + \op d5,[r3,#\offset] + .endm + + vldr d22, forward + + single vldr 4 + single vstr 4 + single vldr 256 + single vstr 256 + +forward: + .word 700 + + vldr d7, backward diff --git a/gas/testsuite/gas/arm/neon-omit.d b/gas/testsuite/gas/arm/neon-omit.d new file mode 100644 index 000000000000..fa7fa2cc75fe --- /dev/null +++ b/gas/testsuite/gas/arm/neon-omit.d @@ -0,0 +1,95 @@ +# name: Neon optional register operands +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3022746 vabd\.u8 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f26cc0c6 vhadd\.s32 q14, q14, q3 +0[0-9a-f]+ <[^>]+> f2222144 vrhadd\.s32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f22aa24e vhsub\.s32 q5, q5, q7 +0[0-9a-f]+ <[^>]+> f3186446 vshl\.u16 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f32ca45a vqshl\.u32 q5, q5, q6 +0[0-9a-f]+ <[^>]+> f20ee170 vand q7, q7, q8 +0[0-9a-f]+ <[^>]+> f30ee170 veor q7, q7, q8 +0[0-9a-f]+ <[^>]+> f3b5a14a vceq\.i16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f31aa85a vceq\.i16 q5, q5, q5 +0[0-9a-f]+ <[^>]+> f3b5a24a vclt\.s16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f3b5a34c vabs\.s16 q5, q6 +0[0-9a-f]+ <[^>]+> f3b57388 vneg\.s16 d7, d8 +0[0-9a-f]+ <[^>]+> f3b97708 vabs\.f32 d7, d8 +0[0-9a-f]+ <[^>]+> f3f927e4 vneg\.f32 q9, q10 +0[0-9a-f]+ <[^>]+> f2211a03 vpmax\.s32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f2255a17 vpmin\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3011f03 vpmax\.f32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f3255f07 vpmin\.f32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2122b46 vqdmulh\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f3255b07 vqrdmulh\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3922c6d vqdmulh\.s16 q1, q1, d5\[3\] +0[0-9a-f]+ <[^>]+> f2122056 vqadd\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f2255017 vqadd\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2222944 vmla\.i32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f2133b14 vpadd\.i16 d3, d3, d4 +0[0-9a-f]+ <[^>]+> f3266948 vmls\.i32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f3022e54 vacge\.f32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f3266e58 vacgt\.f32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5 +0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f32ee360 vcgt\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f320e3ce vcgt\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2 +0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4 +0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3 +0[0-9a-f]+ <[^>]+> f2011f12 vrecps\.f32 d1, d1, d2 +0[0-9a-f]+ <[^>]+> f29c2052 vshr\.s16 q1, q1, #4 +0[0-9a-f]+ <[^>]+> f28b4254 vrshr\.s8 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6 +0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6 +0[0-9a-f]+ <[^>]+> f3954554 vsli\.16 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63 +0[0-9a-f]+ <[^>]+> f2b55306 vext\.8 d5, d5, d6, #3 +0[0-9a-f]+ <[^>]+> f3042746 vabd\.u8 q1, q2, q3 +0[0-9a-f]+ <[^>]+> f262c0c6 vhadd\.s32 q14, q9, q3 +0[0-9a-f]+ <[^>]+> f22a2144 vrhadd\.s32 q1, q5, q2 +0[0-9a-f]+ <[^>]+> f220a2ce vhsub\.s32 q5, q8, q7 +0[0-9a-f]+ <[^>]+> f31a6448 vshl\.u16 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f322a45c vqshl\.u32 q5, q6, q1 +0[0-9a-f]+ <[^>]+> f200e1dc vand q7, q8, q6 +0[0-9a-f]+ <[^>]+> f300e1dc veor q7, q8, q6 +0[0-9a-f]+ <[^>]+> f3b5a146 vceq\.i16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f316a85a vceq\.i16 q5, q3, q5 +0[0-9a-f]+ <[^>]+> f3b5a246 vclt\.s16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f2231a20 vpmax\.s32 d1, d3, d16 +0[0-9a-f]+ <[^>]+> f2275a34 vpmin\.s32 d5, d7, d20 +0[0-9a-f]+ <[^>]+> f3031f07 vpmax\.f32 d1, d3, d7 +0[0-9a-f]+ <[^>]+> f32c5f07 vpmin\.f32 d5, d12, d7 +0[0-9a-f]+ <[^>]+> f2162b60 vqdmulh\.s16 q1, q3, q8 +0[0-9a-f]+ <[^>]+> f3275b09 vqrdmulh\.s32 d5, d7, d9 +0[0-9a-f]+ <[^>]+> f39c2c6d vqdmulh\.s16 q1, q6, d5\[3\] +0[0-9a-f]+ <[^>]+> f21620d6 vqadd\.s16 q1, q11, q3 +0[0-9a-f]+ <[^>]+> f227503f vqadd\.s32 d5, d7, d31 +0[0-9a-f]+ <[^>]+> f2242962 vmla\.i32 q1, q2, q9 +0[0-9a-f]+ <[^>]+> f21a3b94 vpadd\.i16 d3, d26, d4 +0[0-9a-f]+ <[^>]+> f328694a vmls\.i32 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f3082e54 vacge\.f32 q1, q4, q2 +0[0-9a-f]+ <[^>]+> f3226e58 vacgt\.f32 q3, q1, q4 +0[0-9a-f]+ <[^>]+> f30cae72 vacge\.f32 q5, q6, q9 +0[0-9a-f]+ <[^>]+> f320eed2 vacgt\.f32 q7, q8, q1 +0[0-9a-f]+ <[^>]+> f320e3d6 vcge\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f320e3c6 vcgt\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f326e370 vcge\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f326e360 vcgt\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f3aa2102 vaddw\.u32 q1, q5, d2 +0[0-9a-f]+ <[^>]+> f2a26304 vsubw\.s32 q3, q1, d4 +0[0-9a-f]+ <[^>]+> f22648d6 vtst\.32 q2, q11, q3 +0[0-9a-f]+ <[^>]+> f20e1f92 vrecps\.f32 d1, d30, d2 +0[0-9a-f]+ <[^>]+> f29c207a vshr\.s16 q1, q13, #4 +0[0-9a-f]+ <[^>]+> f28b4272 vrshr\.s8 q2, q9, #5 +0[0-9a-f]+ <[^>]+> f39a6152 vsra\.u16 q3, q1, #6 +0[0-9a-f]+ <[^>]+> f3dae358 vrsra\.u16 q15, q4, #6 +0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5 +0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63 +0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3 diff --git a/gas/testsuite/gas/arm/neon-omit.s b/gas/testsuite/gas/arm/neon-omit.s new file mode 100644 index 000000000000..42a7e8903b16 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-omit.s @@ -0,0 +1,97 @@ +@ test omitted optional arguments + + .text + .arm + .syntax unified + + vabd.u8 q1,q3 + vhadd.s32 q14, q3 + vrhadd.s32 q1,q2 + vhsub.s32 q5,q7 + vshl.u16 q3,q4 + vqshl.u32 q5,q6 + vand.64 q7,q8 + veor.64 q7,q8 + vceq.i16 q5,#0 + vceq.i16 q5,q5 + vclt.s16 q5,#0 + vabs.s16 q5,q6 + vneg.s16 d7,d8 + vabs.f d7,d8 + vneg.f q9,q10 + vpmax.s32 d1,d3 + vpmin.s32 d5,d7 + vpmax.f32 d1,d3 + vpmin.f32 d5,d7 + vqdmulh.s16 q1,q3 + vqrdmulh.s32 d5,d7 + vqdmulh.s16 q1,d5[3] + vqadd.s16 q1,q3 + vqadd.s32 d5,d7 + vmla.i32 q1,q2 + vpadd.i16 d3,d4 + vmls.s32 q3,q4 + vacge.f q1,q2 + vacgt.f q3,q4 + vacle.f q5,q6 + vaclt.f q7,q8 + vcge.u32 q7,q8 + vcgt.u32 q7,q8 + vcle.u32 q7,q8 + vclt.u32 q7,q8 + vaddw.u32 q1,d2 + vsubw.s32 q3,d4 + vtst.i32 q2,q3 + vrecps.f d1,d2 + vshr.s16 q1,#4 + vrshr.s8 q2,#5 + vsra.u16 q3,#6 + vrsra.u16 q4,#6 + vsli.16 q2,#5 + vqshlu.s64 d15,#63 + vext.8 d5,d6,#3 + +@ Also test three-argument forms without omitted arguments + + vabd.u8 q1,q2,q3 + vhadd.s32 q14,q9,q3 + vrhadd.s32 q1,q5,q2 + vhsub.s32 q5,q8,q7 + vshl.u16 q3,q4,q5 + vqshl.u32 q5,q6,q1 + vand.64 q7,q8,q6 + veor.64 q7,q8,q6 + vceq.i16 q5,q3,#0 + vceq.i16 q5,q3,q5 + vclt.s16 q5,q3,#0 + vpmax.s32 d1,d3,d16 + vpmin.s32 d5,d7,d20 + vpmax.f32 d1,d3,d7 + vpmin.f32 d5,d12,d7 + vqdmulh.s16 q1,q3,q8 + vqrdmulh.s32 d5,d7,d9 + vqdmulh.s16 q1,q6,d5[3] + vqadd.s16 q1,q11,q3 + vqadd.s32 d5,d7,d31 + vmla.i32 q1,q2,q9 + vpadd.i16 d3,d26,d4 + vmls.s32 q3,q4,q5 + vacge.f q1,q4,q2 + vacgt.f q3,q1,q4 + vacle.f q5,q9,q6 + vaclt.f q7,q1,q8 + vcge.u32 q7,q8,q3 + vcgt.u32 q7,q8,q3 + vcle.u32 q7,q8,q3 + vclt.u32 q7,q8,q3 + vaddw.u32 q1,q5,d2 + vsubw.s32 q3,q1,d4 + vtst.i32 q2,q11,q3 + vrecps.f d1,d30,d2 + vshr.s16 q1,q13,#4 + vrshr.s8 q2,q9,#5 + vsra.u16 q3,q1,#6 + vrsra.u16 q15,q4,#6 + vsli.16 q2,q3,#5 + vqshlu.s64 d15,d23,#63 + vext.8 d5,d18,d6,#3 diff --git a/gas/testsuite/gas/arm/neon-psyn.d b/gas/testsuite/gas/arm/neon-psyn.d new file mode 100644 index 000000000000..c318672f72b4 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-psyn.d @@ -0,0 +1,37 @@ +# name: Neon programmers syntax +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2144954 vmul\.i16 q2, q2, q2 +0[0-9a-f]+ <[^>]+> f2a33862 vmul\.i32 d3, d3, d2\[1\] +0[0-9a-f]+ <[^>]+> f2233912 vmul\.i32 d3, d3, d2 +0[0-9a-f]+ <[^>]+> f2222803 vadd\.i32 d2, d2, d3 +0[0-9a-f]+ <[^>]+> f3924a4a vmull\.u16 q2, d2, d2\[1\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2255805 vadd\.i32 d5, d5, d5 +0[0-9a-f]+ <[^>]+> f2275117 vorr d5, d7, d7 +0[0-9a-f]+ <[^>]+> ee021b70 vmov\.16 d2\[1\], r1 +0[0-9a-f]+ <[^>]+> ee251b10 vmov\.32 d5\[1\], r1 +0[0-9a-f]+ <[^>]+> ec432b15 vmov d5, r2, r3 +0[0-9a-f]+ <[^>]+> ee554b30 vmov\.s8 r4, d5\[1\] +0[0-9a-f]+ <[^>]+> ec565b15 vmov r5, r6, d5 +0[0-9a-f]+ <[^>]+> f396a507 vabal\.u16 q5, d6, d7 +0[0-9a-f]+ <[^>]+> f3bb2744 vcvt\.s32\.f32 q1, q2 +0[0-9a-f]+ <[^>]+> f3bb4e15 vcvt\.f32\.u32 d4, d5, #5 +0[0-9a-f]+ <[^>]+> f3bc7c05 vdup\.32 d7, d5\[1\] +0[0-9a-f]+ <[^>]+> f3ba1904 vtbl\.8 d1, {d10-d11}, d4 +0[0-9a-f]+ <[^>]+> f4aa698f vld2\.32 {d6\[1\],d7\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa476f vld4\.16 {d4\[1\],d6\[1\],d8\[1\],d10\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa6e4f vld3\.16 {d6\[\]-d8\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> f42a604f vld4\.16 {d6-d9}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa266f vld3\.16 {d2\[1\],d4\[1\],d6\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f3b47908 vtbl\.8 d7, {d4-d5}, d8 +0[0-9a-f]+ <[^>]+> f3142156 vbsl q1, q2, q3 +0[0-9a-f]+ <[^>]+> f3032e04 vcge\.f32 d2, d3, d4 +0[0-9a-f]+ <[^>]+> f3b52083 vcge\.s16 d2, d3, #0 +0[0-9a-f]+ <[^>]+> ee823b30 vdup\.16 d2, r3 diff --git a/gas/testsuite/gas/arm/neon-psyn.s b/gas/testsuite/gas/arm/neon-psyn.s new file mode 100644 index 000000000000..5d412a8552f0 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-psyn.s @@ -0,0 +1,78 @@ + .arm + .syntax unified + +fish .qn q2 +cow .dn d2[1] +chips .dn d2 +banana .dn d3 + + vmul fish.s16, fish.s16, fish.s16 + + vmul banana, banana, cow.s32 + vmul d3.s32, d3.s32, d2.s32 + vadd d2.s32, d3.s32 + vmull fish.u32, chips.u16, chips.u16[1] + +X .dn D0.S16 +Y .dn D1.S16 +Z .dn Y[2] + + VMLA X, Y, Z + VMLA X, Y, Y[2] + +foo .dn d5 +bar .dn d7 +foos .dn foo[1] + + vadd foo, foo, foo.u32 + + vmov foo, bar + vmov d2.s16[1], r1 + vmov d5.s32[1], r1 + vmov foo, r2, r3 + vmov r4, foos.s8 + vmov r5, r6, foo + +baa .qn q5 +moo .dn d6 +sheep .dn d7 +chicken .dn d8 + + vabal baa, moo.u16, sheep.u16 + + vcvt q1.s32, q2.f32 + vcvt d4.f, d5.u32, #5 + + vdup bar, foos.32 + vtbl d1, {baa}, d4.8 + +el1 .dn d4.16[1] +el2 .dn d6.16[1] +el3 .dn d8.16[1] +el4 .dn d10.16[1] + + vld2 {moo.32[1], sheep.32[1]}, [r10] + vld4 {el1, el2, el3, el4}, [r10] + vld3 {moo.16[], sheep.16[], chicken.16[]}, [r10] + + vmov r0,d0.s16[0] + +el5 .qn q3.16 +el6 .qn q4.16 + + vld4 {el5,el6}, [r10] + + vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10] + +chicken8 .dn chicken.8 + + vtbl d7.8, {d4, d5}, chicken8 + + vbsl q1.8, q2.16, q3.8 + + vcge d2.32, d3.f, d4.f + vcge d2.16, d3.s16, #0 + +dupme .dn d2.s16 + + vdup dupme, r3 diff --git a/gas/testsuite/gas/arm/noarm.d b/gas/testsuite/gas/arm/noarm.d new file mode 100644 index 000000000000..ae34f8342f95 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.d @@ -0,0 +1,3 @@ +# name: Disallow ARM instructions on V7M +# as: +# error-output: noarm.l diff --git a/gas/testsuite/gas/arm/noarm.l b/gas/testsuite/gas/arm/noarm.l new file mode 100644 index 000000000000..edc59a2d5374 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: selected processor does not support ARM opcodes +[^:]*:13: Error: attempt to use an ARM instruction on a Thumb-only processor -- `nop' diff --git a/gas/testsuite/gas/arm/noarm.s b/gas/testsuite/gas/arm/noarm.s new file mode 100644 index 000000000000..3dadd4468f14 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.s @@ -0,0 +1,13 @@ + .arch armv7a + .syntax unified + .text +func: + nop + movw r0, #0 + + .arch armv7 + .thumb + nop + movw r0, #0 + .arm + nop diff --git a/gas/testsuite/gas/arm/relax_branch_align.d b/gas/testsuite/gas/arm/relax_branch_align.d new file mode 100644 index 000000000000..e23b0951584d --- /dev/null +++ b/gas/testsuite/gas/arm/relax_branch_align.d @@ -0,0 +1,13 @@ +#name: Branch relaxation with alignment. +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf00 nop +0+002 <[^>]+> f000 8080 beq.w 0+106 <[^>]*> +0+006 <[^>]+> bf00 nop +#... +0+100 <[^>]+> bf00 nop +0+102 <[^>]+> f47f af80 bne.w 0+006 <[^>]*> +0+106 <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/relax_branch_align.s b/gas/testsuite/gas/arm/relax_branch_align.s new file mode 100644 index 000000000000..718ce4982139 --- /dev/null +++ b/gas/testsuite/gas/arm/relax_branch_align.s @@ -0,0 +1,17 @@ + .syntax unified + .thumb +fn: + nop +.L191: + beq .L192 +.L46: + nop + .align 2 +.L54: + .rept 62 + .word 0 + .endr + nop + bne .L46 +.L192: + nop diff --git a/gas/testsuite/gas/arm/srs-arm.d b/gas/testsuite/gas/arm/srs-arm.d new file mode 100644 index 000000000000..844c692dd9fc --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.d @@ -0,0 +1,2 @@ +# name: SRS instruction in ARM mode +# error-output: srs-arm.l diff --git a/gas/testsuite/gas/arm/srs-arm.l b/gas/testsuite/gas/arm/srs-arm.l new file mode 100644 index 000000000000..ad992f8f7177 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:13: Error: SRS base register must be r13 -- `srsda r4,#13' +[^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13' +[^:]*:15: Error: SRS base register must be r13 -- `srsib r4,#13' diff --git a/gas/testsuite/gas/arm/srs-arm.s b/gas/testsuite/gas/arm/srs-arm.s new file mode 100644 index 000000000000..7d00fc8f0d6c --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.s @@ -0,0 +1,16 @@ + .arch armv6 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsda r13, #13 + srsda r13!, #13 + srsib r13, #13 + srsib r13!, #13 + srsdb r4, #13 + srsda r4, #13 + srsia r4, #13 + srsib r4, #13 + diff --git a/gas/testsuite/gas/arm/srs-t2.d b/gas/testsuite/gas/arm/srs-t2.d new file mode 100644 index 000000000000..dfa57dbd8af3 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.d @@ -0,0 +1,2 @@ +# name: SRS instruction in Thumb-2 mode +# error-output: srs-t2.l diff --git a/gas/testsuite/gas/arm/srs-t2.l b/gas/testsuite/gas/arm/srs-t2.l new file mode 100644 index 000000000000..f0703759193c --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:9: Error: SRS base register must be r13 -- `srsia r4,#13' diff --git a/gas/testsuite/gas/arm/srs-t2.s b/gas/testsuite/gas/arm/srs-t2.s new file mode 100644 index 000000000000..7132626a59a7 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.s @@ -0,0 +1,10 @@ + .arch armv6t2 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsdb r4, #13 + srsia r4, #13 + diff --git a/gas/testsuite/gas/arm/svc.d b/gas/testsuite/gas/arm/svc.d index fdeb9302083b..697756c7965d 100644 --- a/gas/testsuite/gas/arm/svc.d +++ b/gas/testsuite/gas/arm/svc.d @@ -1,6 +1,5 @@ # name: SWI/SVC instructions # objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d index 47e9d89d9f94..be7afae7a40c 100644 --- a/gas/testsuite/gas/arm/tcompat.d +++ b/gas/testsuite/gas/arm/tcompat.d @@ -12,30 +12,30 @@ Disassembly of section .text: 0+04 <[^>]*> e1a09000 ? mov r9, r0 0+08 <[^>]*> e1a00009 ? mov r0, r9 0+0c <[^>]*> e1a0c00e ? mov ip, lr -0+10 <[^>]*> 91b09019 ? movlss r9, r9, lsl r0 -0+14 <[^>]*> 91a00910 ? movls r0, r0, lsl r9 -0+18 <[^>]*> e1b00880 ? movs r0, r0, lsl #17 -0+1c <[^>]*> e1a00889 ? mov r0, r9, lsl #17 -0+20 <[^>]*> 91b09039 ? movlss r9, r9, lsr r0 -0+24 <[^>]*> 91a00930 ? movls r0, r0, lsr r9 -0+28 <[^>]*> e1b008a0 ? movs r0, r0, lsr #17 -0+2c <[^>]*> e1a008a9 ? mov r0, r9, lsr #17 -0+30 <[^>]*> 91b09059 ? movlss r9, r9, asr r0 -0+34 <[^>]*> 91a00950 ? movls r0, r0, asr r9 -0+38 <[^>]*> e1b008c0 ? movs r0, r0, asr #17 -0+3c <[^>]*> e1a008c9 ? mov r0, r9, asr #17 -0+40 <[^>]*> 91b09079 ? movlss r9, r9, ror r0 -0+44 <[^>]*> 91a00970 ? movls r0, r0, ror r9 -0+48 <[^>]*> e1b008e0 ? movs r0, r0, ror #17 -0+4c <[^>]*> e1a008e9 ? mov r0, r9, ror #17 +0+10 <[^>]*> 91b09019 ? lslsls r9, r9, r0 +0+14 <[^>]*> 91a00910 ? lslls r0, r0, r9 +0+18 <[^>]*> e1b00880 ? lsls r0, r0, #17 +0+1c <[^>]*> e1a00889 ? lsl r0, r9, #17 +0+20 <[^>]*> 91b09039 ? lsrsls r9, r9, r0 +0+24 <[^>]*> 91a00930 ? lsrls r0, r0, r9 +0+28 <[^>]*> e1b008a0 ? lsrs r0, r0, #17 +0+2c <[^>]*> e1a008a9 ? lsr r0, r9, #17 +0+30 <[^>]*> 91b09059 ? asrsls r9, r9, r0 +0+34 <[^>]*> 91a00950 ? asrls r0, r0, r9 +0+38 <[^>]*> e1b008c0 ? asrs r0, r0, #17 +0+3c <[^>]*> e1a008c9 ? asr r0, r9, #17 +0+40 <[^>]*> 91b09079 ? rorsls r9, r9, r0 +0+44 <[^>]*> 91a00970 ? rorls r0, r0, r9 +0+48 <[^>]*> e1b008e0 ? rors r0, r0, #17 +0+4c <[^>]*> e1a008e9 ? ror r0, r9, #17 0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 ; 0x0 0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 ; 0x0 0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 ; 0x0 -0+5c <[^>]*> 92799000 ? rsblss r9, r9, #0 ; 0x0 -0+60 <[^>]*> e92d000e ? stmdb sp!, {r1, r2, r3} -0+64 <[^>]*> 992d8154 ? stmlsdb sp!, {r2, r4, r6, r8, pc} -0+68 <[^>]*> e8bd000e ? ldmia sp!, {r1, r2, r3} -0+6c <[^>]*> 98bd8154 ? ldmlsia sp!, {r2, r4, r6, r8, pc} +0+5c <[^>]*> 92799000 ? rsbsls r9, r9, #0 ; 0x0 +0+60 <[^>]*> e92d000e ? push {r1, r2, r3} +0+64 <[^>]*> 992d8154 ? pushls {r2, r4, r6, r8, pc} +0+68 <[^>]*> e8bd000e ? pop {r1, r2, r3} +0+6c <[^>]*> 98bd8154 ? popls {r2, r4, r6, r8, pc} 0+70 <[^>]*> e0000001 ? and r0, r0, r1 0+74 <[^>]*> e0200001 ? eor r0, r0, r1 0+78 <[^>]*> e0400001 ? sub r0, r0, r1 diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d index d3f815a2986a..7f9b253a443f 100644 --- a/gas/testsuite/gas/arm/thumb.d +++ b/gas/testsuite/gas/arm/thumb.d @@ -50,7 +50,7 @@ Disassembly of section \.text: 0+050 <[^>]+> 46c0 nop \(mov r8, r8\) 0+052 <[^>]+> 4738 bx r7 0+054 <[^>]+> 4740 bx r8 -0+056 <[^>]+> 0000 lsls r0, r0, #0 +0+056 <[^>]+> 46c0 nop \(mov r8, r8\) 0+058 <[^>]+> 4778 bx pc 0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\) 0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\) @@ -58,7 +58,7 @@ Disassembly of section \.text: 0+060 <[^>]+> 5511 strb r1, \[r2, r4\] 0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] 0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] - \.\.\. +0+066 <[^>]+> 46c0 nop \(mov r8, r8\) 0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] 0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] 0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] @@ -75,7 +75,7 @@ Disassembly of section \.text: 0+082 <[^>]+> 93ff str r3, \[sp, #1020\] 0+084 <[^>]+> 990b ldr r1, \[sp, #44\] 0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] -0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7,0+488 <[^>]+>\) +0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\) 0+08a <[^>]+> ac80 add r4, sp, #512 0+08c <[^>]+> b043 add sp, #268 0+08e <[^>]+> b09a sub sp, #104 @@ -111,11 +111,11 @@ Disassembly of section \.text: 0+0ca <[^>]+> b07f add sp, #508 0+0cc <[^>]+> b0ff sub sp, #508 0+0ce <[^>]+> a8ff add r0, sp, #1020 -0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0,0+4d0 <[^>]+>\) +0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\) 0+0d2 <[^>]+> b01a add sp, #104 0+0d4 <[^>]+> b09a sub sp, #104 0+0d6 <[^>]+> a81a add r0, sp, #104 -0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0,0+144 <[^>]+>\) +0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\) 0+0da <[^>]+> 3168 adds r1, #104 0+0dc <[^>]+> 2668 movs r6, #104 0+0de <[^>]+> 2f68 cmp r7, #104 @@ -127,14 +127,14 @@ Disassembly of section \.text: 0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> 0+0f4 <[^>]+> e12fff10 bx r0 0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0,0+110 <[^>]+>\) +0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0, 0+110 <[^>]+>\) 0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> 0+100 <[^>]+> e018 b.n 0+134 <[^>]+> 0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> 0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> 0+10a <[^>]+> 4700 bx r0 0+10c <[^>]+> dfff (swi|svc) 255 - \.\.\. +0+10e <[^>]+> 46c0 nop \(mov r8, r8\) 0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> 0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> 0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> diff --git a/gas/testsuite/gas/arm/thumb1_unified.d b/gas/testsuite/gas/arm/thumb1_unified.d new file mode 100644 index 000000000000..c2fdf306325a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb1_unified.d @@ -0,0 +1,20 @@ +# name: Thumb-1 unified +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> 200c movs r0, #12 +0[0-9a-f]+ <[^>]+> 1cd1 adds r1, r2, #3 +0[0-9a-f]+ <[^>]+> 1ed1 subs r1, r2, #3 +0[0-9a-f]+ <[^>]+> 3364 adds r3, #100 +0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131 +0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39 +0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 \(adr [^)]*\) +0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] \([^)]*\) +0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\] +0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\] +0[0-9a-f]+ <[^>]+> b001 add sp, #4 +0[0-9a-f]+ <[^>]+> b081 sub sp, #4 +0[0-9a-f]+ <[^>]+> af01 add r7, sp, #4 +0[0-9a-f]+ <[^>]+> 4251 negs r1, r2 diff --git a/gas/testsuite/gas/arm/thumb1_unified.s b/gas/testsuite/gas/arm/thumb1_unified.s new file mode 100644 index 000000000000..c8da6ec5aa8e --- /dev/null +++ b/gas/testsuite/gas/arm/thumb1_unified.s @@ -0,0 +1,25 @@ +.text +.arch armv4t +.syntax unified +.thumb +foo: +movs r0, #12 +adds r1, r2, #3 +subs r1, r2, #3 +adds r3, r3, #0x64 +subs r4, r4, #0x83 +cmp r5, #0x27 + +adr r1, bar +ldr r2, bar +ldr r3, [r4, #4] +ldr r5, [sp, #4] +add sp, sp, #4 +sub sp, sp, #4 +add r7, sp, #4 + +rsbs r1, r2, #0 + +.align 2 +bar: + diff --git a/gas/testsuite/gas/arm/thumb2_add.d b/gas/testsuite/gas/arm/thumb2_add.d new file mode 100644 index 000000000000..5100bb691a7a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_add.d @@ -0,0 +1,30 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800 +0+004 <[^>]+> f20f 0900 addw r9, pc, #0 ; 0x0 +0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400 +0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400 +0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101 +0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101 +0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800 +0+01c <[^>]+> f2af 0900 subw r9, pc, #0 ; 0x0 +0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400 +0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400 +0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101 +0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101 +0+030 <[^>]+> f103 0301 add.w r3, r3, #1 ; 0x1 +0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 ; 0x1 +0+038 <[^>]+> b0c0 sub sp, #256 +0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200 +0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101 +0+042 <[^>]+> b040 add sp, #256 +0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200 +0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101 +0+04c <[^>]+> a840 add r0, sp, #256 +0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400 +0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101 +0+056 <[^>]+> 4271 negs r1, r6 diff --git a/gas/testsuite/gas/arm/thumb2_add.s b/gas/testsuite/gas/arm/thumb2_add.s new file mode 100644 index 000000000000..a3b178a05291 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_add.s @@ -0,0 +1,31 @@ + .syntax unified + .text + .align 2 + .global thumb2_add + .thumb + .thumb_func +thumb2_add: + add r0, pc, #0x800 + add r9, pc, #0 + add r9, pc, #0x400 + add r8, r9, #0x400 + add r8, r9, #0x101 + add r3, r1, #0x101 + sub r0, pc, #0x800 + sub r9, pc, #0 + sub r9, pc, #0x400 + sub r8, r9, #0x400 + sub r8, r9, #0x101 + sub r3, r1, #0x101 + add r3, #1 + sub r3, #1 + sub sp, sp, #0x100 + sub sp, sp, #0x200 + sub sp, sp, #0x101 + add sp, sp, #0x100 + add sp, sp, #0x200 + add sp, sp, #0x101 + add r0, sp, #0x100 + add r5, sp, #0x400 + add r9, sp, #0x101 + rsbs r1, r6, #0 diff --git a/gas/testsuite/gas/arm/thumb2_bcond.d b/gas/testsuite/gas/arm/thumb2_bcond.d index 8ab75320e1a3..02903a954191 100644 --- a/gas/testsuite/gas/arm/thumb2_bcond.d +++ b/gas/testsuite/gas/arm/thumb2_bcond.d @@ -1,26 +1,25 @@ # as: # objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* Disassembly of section .text: 0+000 <[^>]+> bf18 it ne -0+002 <[^>]+> e7fd b(|ne).n 0+0 <[^>]+> +0+002 <[^>]+> e7fd bne.n 0+0 <[^>]+> 0+004 <[^>]+> bf38 it cc -0+006 <[^>]+> f7ff bffb b(|cc).w 0+0 <[^>]+> +0+006 <[^>]+> f7ff bffb bcc.w 0+0 <[^>]+> 0+00a <[^>]+> bf28 it cs -0+00c <[^>]+> f7ff fff8 bl(|cs) 0+0 <[^>]+> +0+00c <[^>]+> f7ff fff8 blcs 0+0 <[^>]+> 0+010 <[^>]+> bfb8 it lt -0+012 <[^>]+> 47a8 blx(|lr) r5 +0+012 <[^>]+> 47a8 blxlt r5 0+014 <[^>]+> bf08 it eq -0+016 <[^>]+> 4740 bx(|eq) r8 +0+016 <[^>]+> 4740 bxeq r8 0+018 <[^>]+> bfc8 it gt -0+01a <[^>]+> e8d4 f001 tbb(|gt) \[r4, r1\] +0+01a <[^>]+> e8d4 f001 tbbgt \[r4, r1\] 0+01e <[^>]+> bfb8 it lt -0+020 <[^>]+> df00 svc(|lt) 0 +0+020 <[^>]+> df00 svclt 0 0+022 <[^>]+> bfdc itt le 0+024 <[^>]+> be00 bkpt 0x0000 -0+026 <[^>]+> bf00 nop +0+026 <[^>]+> bf00 nople 0+028 <[^>]+> bf00 nop 0+02a <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.d b/gas/testsuite/gas/arm/thumb2_it_bad.d index f905c9f5e73b..1cca8b9650cb 100644 --- a/gas/testsuite/gas/arm/thumb2_it_bad.d +++ b/gas/testsuite/gas/arm/thumb2_it_bad.d @@ -1,4 +1,3 @@ #name: Invalid IT instructions #as: -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* #error-output: thumb2_it_bad.l diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.d b/gas/testsuite/gas/arm/thumb2_ldmstm.d new file mode 100644 index 000000000000..2f50486489c2 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldmstm.d @@ -0,0 +1,27 @@ +# name: Thumb-2 LDM/STM single reg +# as: -march=armv6t2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> bc01 pop {r0} +0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8d1 9000 ldr.w r9, \[r1\] +0[0-9a-f]+ <[^>]+> f852 cb04 ldr.w ip, \[r2\], #4 +0[0-9a-f]+ <[^>]+> f85d 2d04 ldr.w r2, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f85d 8d04 ldr.w r8, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f856 4c04 ldr.w r4, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f856 8c04 ldr.w r8, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f852 4d04 ldr.w r4, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> f852 cd04 ldr.w ip, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> b408 push {r3} +0[0-9a-f]+ <[^>]+> f84d 9b04 str.w r9, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8c3 c000 str.w ip, \[r3\] +0[0-9a-f]+ <[^>]+> f844 cb04 str.w ip, \[r4\], #4 +0[0-9a-f]+ <[^>]+> f84d 3d04 str.w r3, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f84d 9d04 str.w r9, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f847 5c04 str.w r5, \[r7, #-4\] +0[0-9a-f]+ <[^>]+> f846 cc04 str.w ip, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f846 bd04 str.w fp, \[r6, #-4\]! +0[0-9a-f]+ <[^>]+> f845 8d04 str.w r8, \[r5, #-4\]! diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.s b/gas/testsuite/gas/arm/thumb2_ldmstm.s new file mode 100644 index 000000000000..fd4410af3c4a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldmstm.s @@ -0,0 +1,24 @@ +.syntax unified +.thumb +ldmstm: + ldmia sp!, {r0} + ldmia sp!, {r8} + ldmia r1, {r9} + ldmia r2!, {ip} + ldmdb sp!, {r2} + ldmdb sp!, {r8} + ldmdb r6, {r4} + ldmdb r6, {r8} + ldmdb r2!, {r4} + ldmdb r2!, {ip} + stmia sp!, {r3} + stmia sp!, {r9} + stmia r3, {ip} + stmia r4!, {ip} + stmdb sp!, {r3} + stmdb sp!, {r9} + stmdb r7, {r5} + stmdb r6, {ip} + stmdb r6!, {fp} + stmdb r5!, {r8} + diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d index 7bf0c605d5fd..752da7fb6aa7 100644 --- a/gas/testsuite/gas/arm/thumb2_pool.d +++ b/gas/testsuite/gas/arm/thumb2_pool.d @@ -1,5 +1,7 @@ # as: -march=armv6t2 # objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* @@ -11,5 +13,4 @@ Disassembly of section .text: 0+00c <[^>]+> bf00 nop 0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> 0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] \(00+14 <[^>]+>\) -0+014 <[^>]+> (5678|1234) .* -0+016 <[^>]+> (1234|5678) .* +0+014 <[^>]+> 12345678 ? .word 0x12345678 diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d index 48cd1f21f806..327ef42b5347 100644 --- a/gas/testsuite/gas/arm/thumb2_relax.d +++ b/gas/testsuite/gas/arm/thumb2_relax.d @@ -20,7 +20,7 @@ Disassembly of section .text: 0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+> 0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+> 0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+> -0+03a <[^>]+> 0000 lsls r0, r0, #0 +0+03a <[^>]+> 46c0 nop \(mov r8, r8\) 0+03c <[^>]+> bf00 nop 0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\] 0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\] @@ -89,7 +89,7 @@ Disassembly of section .text: 0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+> 0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+> 0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+> -0+132 <[^>]+> 0000 lsls r0, r0, #0 +0+132 <[^>]+> 46c0 nop \(mov r8, r8\) 0+134 <[^>]+> bf00 nop 0+136 <[^>]+> 7029 strb r1, \[r5, #0\] 0+138 <[^>]+> f885 1023 strb.w r1, \[r5, #35\] @@ -142,7 +142,7 @@ Disassembly of section .text: 0+1e0 <[^>]+> f8cf 1006 str.w r1, \[pc, #6\] ; 0+1ea <[^>]+> 0+1e4 <[^>]+> f84f 103a str.w r1, \[pc, #-58\] ; 0+1ae <[^>]+> 0+1e8 <[^>]+> bf00 nop -0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1,0+1fc <[^>]+>\) +0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1, 0+1fc <[^>]+>\) 0+1ec <[^>]+> f20f 010c addw r1, pc, #12 ; 0xc 0+1f0 <[^>]+> f20f 0808 addw r8, pc, #8 ; 0x8 0+1f4 <[^>]+> f20f 0106 addw r1, pc, #6 ; 0x6 diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d index 2977779aefdd..0d96818858e2 100644 --- a/gas/testsuite/gas/arm/thumb32.d +++ b/gas/testsuite/gas/arm/thumb32.d @@ -3,6 +3,7 @@ # objdump: -dr --prefix-addresses --show-raw-insn # The arm-aout and arm-pe ports do not support Thumb branch relocations. # not-target: *-*-*aout* *-*-pe +# stderr: thumb32.l .*: +file format .*arm.* @@ -62,9 +63,9 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0 0[0-9a-f]+ <[^>]+> 4401 add r1, r0 0[0-9a-f]+ <[^>]+> 4408 add r0, r1 -0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0,[0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0, [0-9a-f]+ <[^>]+>\) 0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0 0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0 0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516 @@ -349,163 +350,163 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> bf90 nop \{9\} 0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\} 0[0-9a-f]+ <[^>]+> bf08 it eq -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf18 it ne -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcs 0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcs 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf48 it mi -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopmi 0[0-9a-f]+ <[^>]+> bf58 it pl -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 noppl 0[0-9a-f]+ <[^>]+> bf68 it vs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopvs 0[0-9a-f]+ <[^>]+> bf78 it vc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopvc 0[0-9a-f]+ <[^>]+> bf88 it hi -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nophi 0[0-9a-f]+ <[^>]+> bfa8 it ge -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopge 0[0-9a-f]+ <[^>]+> bfb8 it lt -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 noplt 0[0-9a-f]+ <[^>]+> bfc8 it gt -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopgt 0[0-9a-f]+ <[^>]+> bfd8 it le -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nople 0[0-9a-f]+ <[^>]+> bfe8 it al -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopal 0[0-9a-f]+ <[^>]+> bf04 itt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0c ite eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf02 ittt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0a itet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf06 itte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0e itee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf09 itett eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf05 ittet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf03 ittte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf07 ittee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0b itete eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0d iteet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0f iteee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1c itt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf14 ite ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf1e ittt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf16 itet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1a itte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf12 itee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf1f itttt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf17 itett ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1b ittet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1d ittte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf19 ittee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf15 itete ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf13 iteet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf11 iteee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> f895 f000 pld \[r5\] 0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\] 0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\] @@ -949,8 +950,83 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} 0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} 0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> c806 ldmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> c006 stmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> c806 ldmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> c006 stmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> e890 0300 ldmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> e880 0300 stmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> e98d c010 srsia sp, #16 +0[0-9a-f]+ <[^>]+> e80d c010 srsdb sp, #16 +0[0-9a-f]+ <[^>]+> e9ad c015 srsia sp!, #21 +0[0-9a-f]+ <[^>]+> e9ad c00a srsia sp!, #10 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f04 subs pc, lr, #4 +0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255 +0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f855 1009 ldr.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f815 1009 ldrb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f915 1009 ldrsb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f835 1009 ldrh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f935 1009 ldrsh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> 00a1 lsls r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0389 movs.w r3, r9, lsl #2 +0[0-9a-f]+ <[^>]+> fa12 f103 lsls.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4099 lsls r1, r3 +0[0-9a-f]+ <[^>]+> fa11 f109 lsls.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa02 f103 lsl.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa01 f103 lsl.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 08a1 lsrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0399 movs.w r3, r9, lsr #2 +0[0-9a-f]+ <[^>]+> fa32 f103 lsrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 40d9 lsrs r1, r3 +0[0-9a-f]+ <[^>]+> fa31 f109 lsrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa22 f103 lsr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa21 f103 lsr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 10a1 asrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 03a9 movs.w r3, r9, asr #2 +0[0-9a-f]+ <[^>]+> fa52 f103 asrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4119 asrs r1, r3 +0[0-9a-f]+ <[^>]+> fa51 f109 asrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa42 f103 asr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa41 f103 asr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> ea5f 01b4 movs.w r1, r4, ror #2 +0[0-9a-f]+ <[^>]+> ea5f 03b9 movs.w r3, r9, ror #2 +0[0-9a-f]+ <[^>]+> fa72 f103 rors.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 41d9 rors r1, r3 +0[0-9a-f]+ <[^>]+> fa71 f109 rors.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3 0[0-9a-f]+ <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/thumb32.l b/gas/testsuite/gas/arm/thumb32.l new file mode 100644 index 000000000000..c687beac79e8 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb32.l @@ -0,0 +1,17 @@ +[^;]*: Assembler messages: +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s index b75a0850f384..697dfd240f34 100644 --- a/gas/testsuite/gas/arm/thumb32.s +++ b/gas/testsuite/gas/arm/thumb32.s @@ -769,3 +769,51 @@ xta: ldmeq r0, {r8, r9} stmeq r0, {r8, r9} nop + +srs: + srsia sp, #16 + srsdb sp, #16 + srsia sp!, #21 + srsia sp!, #10 + + movs pc, lr + subs pc, lr, #0 + subs pc, lr, #4 + subs pc, lr, #255 + + ldrd r2, r4, [r9, #48]! + ldrd r2, r4, [r9, #-48]! + strd r2, r4, [r9, #48]! + strd r2, r4, [r9, #-48]! + ldrd r2, r4, [r9], #48 + ldrd r2, r4, [r9], #-48 + strd r2, r4, [r9], #48 + strd r2, r4, [r9], #-48 + + .macro ldaddr op + ldr\op r1, [r5, #0x301] + ldr\op r1, [r5, #0x30]! + ldr\op r1, [r5, #-0x30]! + ldr\op r1, [r5], #0x30 + ldr\op r1, [r5], #-0x30 + ldr\op r1, [r5, r9] + .endm + ldaddr + ldaddr b + ldaddr sb + ldaddr h + ldaddr sh + .macro movshift op s="s" + movs r1, r4, \op #2 + movs r3, r9, \op #2 + movs r1, r2, \op r3 + movs r1, r1, \op r3 + movs r1, r1, \op r9 + mov r1, r2, \op r3 + mov r1, r1, \op r3 + .endm + movshift lsl + movshift lsr + movshift asr + movshift ror + nop diff --git a/gas/testsuite/gas/arm/thumbrel.d b/gas/testsuite/gas/arm/thumbrel.d new file mode 100644 index 000000000000..fff41af9cc98 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbrel.d @@ -0,0 +1,14 @@ +#objdump: -sr +# This test is only valid on EABI based ports. +#target: *-*-*eabi *-*-symbianelf + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000004 R_ARM_REL32 b + +Contents of section .text: + 0000 00000000 (00000004|04000000) 00000000 00000000 .* +# Ignore .ARM.attributes section +#... diff --git a/gas/testsuite/gas/arm/thumbrel.s b/gas/testsuite/gas/arm/thumbrel.s new file mode 100644 index 000000000000..769da16156c7 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbrel.s @@ -0,0 +1,11 @@ +@ Check that PC-relative relocs against local function symbols are +@ generated correctly. +.text +.thumb +a: +.word 0 +.word b - a +.word 0 +.word 0 +.type b, %function +b: diff --git a/gas/testsuite/gas/arm/thumbver.d b/gas/testsuite/gas/arm/thumbver.d new file mode 100644 index 000000000000..ddc46df56d42 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbver.d @@ -0,0 +1,15 @@ +# as: -meabi=4 +# readelf: -s +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Symbol table '\.symtab' contains .* entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND + 1: 00000000 0 SECTION LOCAL DEFAULT 1 +#... + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_alias + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_body + .*: 00000000 0 NOTYPE LOCAL DEFAULT 1 \$t + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_export@VERSION +#... diff --git a/gas/testsuite/gas/arm/thumbver.s b/gas/testsuite/gas/arm/thumbver.s new file mode 100644 index 000000000000..ad81395ee40c --- /dev/null +++ b/gas/testsuite/gas/arm/thumbver.s @@ -0,0 +1,9 @@ +@ Check that symbols created by .symver are marked as Thumb. + + .thumb_set a_alias, a_body + .symver a_alias, a_export@VERSION + .type a_body, %function + .code 16 + .thumb_func +a_body: + nop diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d index 5b41109292cb..5189dfff01f4 100644 --- a/gas/testsuite/gas/arm/tls.d +++ b/gas/testsuite/gas/arm/tls.d @@ -15,11 +15,11 @@ Disassembly of section .text: 0: e1a00000 nop \(mov r0,r0\) 4: e1a00000 nop \(mov r0,r0\) 8: e1a0f00e mov pc, lr - c: 00000000 andeq r0, r0, r0 + c: 00000000 .word 0x00000000 c: R_ARM_TLS_GD32 a - 10: 00000004 andeq r0, r0, r4 + 10: 00000004 .word 0x00000004 10: R_ARM_TLS_LDM32 b - 14: 00000008 andeq r0, r0, r8 + 14: 00000008 .word 0x00000008 14: R_ARM_TLS_IE32 c - 18: 00000000 andeq r0, r0, r0 + 18: 00000000 .word 0x00000000 18: R_ARM_TLS_LE32 d diff --git a/gas/testsuite/gas/arm/undefined.d b/gas/testsuite/gas/arm/undefined.d index 6a6149561cc3..e3e9bb08929c 100644 --- a/gas/testsuite/gas/arm/undefined.d +++ b/gas/testsuite/gas/arm/undefined.d @@ -1,4 +1,5 @@ #name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* #error-output: undefined.l diff --git a/gas/testsuite/gas/arm/undefined_coff.d b/gas/testsuite/gas/arm/undefined_coff.d index ab0bbcdc6672..d2800275b078 100644 --- a/gas/testsuite/gas/arm/undefined_coff.d +++ b/gas/testsuite/gas/arm/undefined_coff.d @@ -1,4 +1,5 @@ #name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#not-skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* #error-output: undefined_coff.l diff --git a/gas/testsuite/gas/arm/unwind.d b/gas/testsuite/gas/arm/unwind.d index cd4a7c7995c2..060f7ba56afe 100644 --- a/gas/testsuite/gas/arm/unwind.d +++ b/gas/testsuite/gas/arm/unwind.d @@ -25,18 +25,22 @@ OFFSET TYPE VALUE 0000001c R_ARM_PREL31 .ARM.extab.* 00000020 R_ARM_PREL31 .text.* 00000028 R_ARM_PREL31 .text.* +00000030 R_ARM_PREL31 .text.* +00000034 R_ARM_PREL31 .ARM.extab.* Contents of section .text: 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* - 0010 (04200520|20052004) .* + 0010 (04200520 0600a0e3|20052004 e3a00006) .* Contents of section .ARM.extab: 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* Contents of section .ARM.exidx: 0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000 .* 0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c) .* 0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0) .* + 0030 (14000000 2c000000|00000014 0000002c) .* # Ignore .ARM.attributes section #... diff --git a/gas/testsuite/gas/arm/unwind.s b/gas/testsuite/gas/arm/unwind.s index 7d0f126954f1..bbd73a157d94 100644 --- a/gas/testsuite/gas/arm/unwind.s +++ b/gas/testsuite/gas/arm/unwind.s @@ -27,6 +27,8 @@ foo2: @ Custom personality routine .fnend foo3: @ Saving iwmmxt registers .fnstart + .save {wr12} + .save {wr13} .save {wr11} .save {wr10} .save {wr10, wr11} @@ -49,3 +51,17 @@ foo5: @ Save r0-r3 only. .save {r0, r1, r2, r3} mov r0, #5 .fnend + .code 32 +foo6: @ Nested function with frame pointer + .fnstart + .pad #4 + @push {ip} + .movsp ip, #4 + @mov ip, sp + .pad #4 + .save {fp, ip, lr} + @stmfd sp!, {fp, ip, lr, pc} + .setfp fp, ip, #-8 + @sub fp, ip, #8 + mov r0, #6 + .fnend diff --git a/gas/testsuite/gas/arm/unwind_vxworks.d b/gas/testsuite/gas/arm/unwind_vxworks.d index ccd16a65cc9a..11817cf48c16 100644 --- a/gas/testsuite/gas/arm/unwind_vxworks.d +++ b/gas/testsuite/gas/arm/unwind_vxworks.d @@ -24,6 +24,8 @@ OFFSET TYPE VALUE 0000001c R_ARM_PREL31 .ARM.extab.*\+0x0000001c 00000020 R_ARM_PREL31 .text.*\+0x00000010 00000028 R_ARM_PREL31 .text.*\+0x00000012 +00000030 R_ARM_PREL31 .text.*\+0x00000014 +00000034 R_ARM_PREL31 .ARM.extab.*\+0x0000002c Contents of section .text: @@ -31,11 +33,13 @@ Contents of section .text: 0010 (04200520|20052004) .* Contents of section .ARM.extab: 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* Contents of section .ARM.exidx: 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000 .* 0010 00000000 00000000 00000000 00000000 .* 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0) .* + 0030 00000000 00000000 .* # Ignore .ARM.attributes section #... diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.d b/gas/testsuite/gas/arm/vfp-neon-overlap.d new file mode 100644 index 000000000000..b7815640089d --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-overlap.d @@ -0,0 +1,35 @@ +# name: VFP/Neon overlapping instructions +# as: -mfpu=vfp +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.s b/gas/testsuite/gas/arm/vfp-neon-overlap.s new file mode 100644 index 000000000000..19c286afca43 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-overlap.s @@ -0,0 +1,41 @@ +@ VFP/Neon overlapping instructions + + .arm + .text + .syntax unified + + fmdrr d0,r0,r1 + vmov d0,r0,r1 + fmrrd r0,r1,d0 + vmov r0,r1,d0 + + @ the 'x' versions should disassemble as VFP instructions, because + @ they can't be represented in Neon syntax. + + fldmiax r0,{d0-d3} + fldmdbx r0!,{d0-d3} + fstmiax r0,{d0-d3} + fstmdbx r0!,{d0-d3} + + fldd d0,[r0] + vldr d0,[r0] + fstd d0,[r0] + vstr d0,[r0] + + fldmiad r0,{d0-d3} + vldmia r0,{d0-d3} + fldmdbd r0!,{d0-d3} + vldmdb r0!,{d0-d3} + fstmiad r0,{d0-d3} + vstmia r0,{d0-d3} + fstmdbd r0!,{d0-d3} + vstmdb r0!,{d0-d3} + + fmrdh r0,d0 + vmov.32 r0,d0[1] + fmrdl r0,d0 + vmov.32 r0,d0[0] + fmdhr d0,r0 + vmov.32 d0[1],r0 + fmdlr d0,r0 + vmov.32 d0[0],r0 diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s new file mode 100644 index 000000000000..fad0bded369c --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s @@ -0,0 +1,162 @@ +@ VFP with Neon-style syntax + .syntax unified + + .include "itblock.s" + +func: + .macro testvmov cond="" f32=".f32" f64=".f64" + itblock 4 \cond + vmov\cond\f32 s0,s1 + vmov\cond\f64 d0,d1 + vmov\cond\f32 s0,#0.25 + vmov\cond\f64 d0,#1.0 + itblock 4 \cond + vmov\cond r0,s1 + vmov\cond s0,r1 + vmov\cond r0,r1,s2,s3 + vmov\cond s0,s1,r2,r4 + .endm + + @ Test VFP vmov variants. These can all be conditional. + testvmov + testvmov eq + + .macro monadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1 + \op\cond\f64 d0,d1 + .endm + + .macro monadic_c op + monadic \op + monadic \op eq + .endm + + .macro dyadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1,s2 + \op\cond\f64 d0,d1,d2 + .endm + + .macro dyadic_c op + dyadic \op + dyadic \op eq + .endm + + .macro dyadicz op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,#0 + \op\cond\f64 d0,#0 + .endm + + .macro dyadicz_c op + dyadicz \op + dyadicz \op eq + .endm + + monadic_c vsqrt + monadic_c vabs + monadic_c vneg + monadic_c vcmp + monadic_c vcmpe + + dyadic_c vnmul + dyadic_c vnmla + dyadic_c vnmls + + dyadic_c vmul + dyadic_c vmla + dyadic_c vmls + + dyadic_c vadd + dyadic_c vsub + + dyadic_c vdiv + + dyadicz_c vcmp + dyadicz_c vcmpe + + .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvtz\cond\s32\f32 s0,s1 + vcvtz\cond\u32\f32 s0,s1 + vcvtz\cond\s32\f64 s0,d1 + vcvtz\cond\u32\f64 s0,d1 + .endm + + cvtz + cvtz eq + + .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s1 + vcvt\cond\u32\f32 s0,s1 + vcvt\cond\f32\s32 s0,s1 + vcvt\cond\f32\u32 s0,s1 + itblock 4 \cond + vcvt\cond\f32\f64 s0,d1 + vcvt\cond\f64\f32 d0,s1 + vcvt\cond\s32\f64 s0,d1 + vcvt\cond\u32\f64 s0,d1 + itblock 2 \cond + vcvt\cond\f64\s32 d0,s1 + vcvt\cond\f64\u32 d0,s1 + .endm + + cvt + cvt eq + + .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s0,#1 + vcvt\cond\u32\f32 s0,s0,#1 + vcvt\cond\f32\s32 s0,s0,#1 + vcvt\cond\f32\u32 s0,s0,#1 + itblock 4 \cond + vcvt\cond\s32\f64 d0,d0,#1 + vcvt\cond\u32\f64 d0,d0,#1 + vcvt\cond\f64\s32 d0,d0,#1 + vcvt\cond\f64\u32 d0,d0,#1 + itblock 4 \cond + vcvt\cond\f32\s16 s0,s0,#1 + vcvt\cond\f32\u16 s0,s0,#1 + vcvt\cond\f64\s16 d0,d0,#1 + vcvt\cond\f64\u16 d0,d0,#1 + itblock 4 \cond + vcvt\cond\s16\f32 s0,s0,#1 + vcvt\cond\u16\f32 s0,s0,#1 + vcvt\cond\s16\f64 d0,d0,#1 + vcvt\cond\u16\f64 d0,d0,#1 + .endm + + cvti + cvti eq + + .macro multi op cond="" n="" ia="ia" db="db" + itblock 4 \cond + \op\n\cond r0,{s3-s6} + \op\ia\cond r0,{s3-s6} + \op\ia\cond r0!,{s3-s6} + \op\db\cond r0!,{s3-s6} + itblock 4 \cond + \op\n\cond r0,{d3-d6} + \op\ia\cond r0,{d3-d6} + \op\ia\cond r0!,{d3-d6} + \op\db\cond r0!,{d3-d6} + .endm + + multi vldm + multi vldm eq + multi vstm + multi vstm eq + + .macro single op cond="" + itblock 2 \cond + \op\cond s0,[r0,#4] + \op\cond d0,[r0,#4] + .endm + + single vldr + single vldr eq + single vstr + single vstr eq diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.d b/gas/testsuite/gas/arm/vfp-neon-syntax.d new file mode 100644 index 000000000000..8d9743527bca --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.d @@ -0,0 +1,187 @@ +# name: VFP Neon-style syntax, ARM mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eeb00a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb00b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb50a00 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb70b00 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee100a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee001a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec510a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec442a10 fmsrr {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> 0eb00a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> 0eb50a00 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> 0eb70b00 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> 0e100a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> 0e001a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> 0c510a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> 0c442a10 fmsrreq {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> eeb10ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb10bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb00ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb00bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb00ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb10a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb10b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb40b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb40bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee200ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee200a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee800a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee810b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e800a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e810b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb50a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb50b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> 0eb50a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> 0eb50b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb50ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb50bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> 0eb50ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> 0eb50bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> 0ebd0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb80ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb80a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb70bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb70ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb80be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb80b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb70bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb70ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb80be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> 0eb80b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf01a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed701a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb03b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed303b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cf01a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d701a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cb03b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d303b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece01a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed601a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca03b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed203b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0ce01a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d601a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0ca03b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d203b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed900a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed900b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.s b/gas/testsuite/gas/arm/vfp-neon-syntax.s new file mode 100644 index 000000000000..7c0bc633ed10 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.s @@ -0,0 +1,2 @@ + .arm + .include "vfp-neon-syntax-inc.s" diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d new file mode 100644 index 000000000000..5c0223528583 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d @@ -0,0 +1,219 @@ +# name: VFP Neon-style syntax, Thumb mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb7 0b00 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrr {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> eeb7 0b00 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrreq {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee20 0a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe 0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed90 0a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed90 0a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed80 0a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s new file mode 100644 index 000000000000..00f78d01cef7 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "vfp-neon-syntax-inc.s" diff --git a/gas/testsuite/gas/arm/vfp1.d b/gas/testsuite/gas/arm/vfp1.d index 672b23de31d5..3894909539bb 100644 --- a/gas/testsuite/gas/arm/vfp1.d +++ b/gas/testsuite/gas/arm/vfp1.d @@ -24,20 +24,20 @@ Disassembly of section .text: 0+038 <[^>]*> ee100b40 fnmscd d0, d0, d0 0+03c <[^>]*> ee200b40 fnmuld d0, d0, d0 0+040 <[^>]*> ee300b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed900b00 fldd d0, \[r0\] -0+048 <[^>]*> ed800b00 fstd d0, \[r0\] -0+04c <[^>]*> ec900b02 fldmiad r0, {d0} -0+050 <[^>]*> ec900b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec800b02 fstmiad r0, {d0} -0+068 <[^>]*> ec800b02 fstmiad r0, {d0} -0+06c <[^>]*> eca00b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca00b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed200b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed200b02 fstmdbd r0!, {d0} +0+044 <[^>]*> ed900b00 vldr d0, \[r0\] +0+048 <[^>]*> ed800b00 vstr d0, \[r0\] +0+04c <[^>]*> ec900b02 vldmia r0, {d0} +0+050 <[^>]*> ec900b02 vldmia r0, {d0} +0+054 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+05c <[^>]*> ed300b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed300b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec800b02 vstmia r0, {d0} +0+068 <[^>]*> ec800b02 vstmia r0, {d0} +0+06c <[^>]*> eca00b02 vstmia r0!, {d0} +0+070 <[^>]*> eca00b02 vstmia r0!, {d0} +0+074 <[^>]*> ed200b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed200b02 vstmdb r0!, {d0} 0+07c <[^>]*> eeb80bc0 fsitod d0, s0 0+080 <[^>]*> eeb80b40 fuitod d0, s0 0+084 <[^>]*> eebd0b40 ftosid s0, d0 @@ -46,10 +46,10 @@ Disassembly of section .text: 0+090 <[^>]*> eebc0bc0 ftouizd s0, d0 0+094 <[^>]*> eeb70ac0 fcvtds d0, s0 0+098 <[^>]*> eeb70bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee300b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee100b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee200b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee000b10 fmdlr d0, r0 +0+09c <[^>]*> ee300b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee100b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee200b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee000b10 vmov\.32 d0\[0\], r0 0+0ac <[^>]*> eeb51b40 fcmpzd d1 0+0b0 <[^>]*> eeb52b40 fcmpzd d2 0+0b4 <[^>]*> eeb5fb40 fcmpzd d15 @@ -89,46 +89,46 @@ Disassembly of section .text: 0+13c <[^>]*> eeb70bc1 fcvtsd s0, d1 0+140 <[^>]*> eeb70bc2 fcvtsd s0, d2 0+144 <[^>]*> eeb70bcf fcvtsd s0, d15 -0+148 <[^>]*> ee301b10 fmrdh r1, d0 -0+14c <[^>]*> ee30eb10 fmrdh lr, d0 -0+150 <[^>]*> ee310b10 fmrdh r0, d1 -0+154 <[^>]*> ee320b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f0b10 fmrdh r0, d15 -0+15c <[^>]*> ee101b10 fmrdl r1, d0 -0+160 <[^>]*> ee10eb10 fmrdl lr, d0 -0+164 <[^>]*> ee110b10 fmrdl r0, d1 -0+168 <[^>]*> ee120b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f0b10 fmrdl r0, d15 -0+170 <[^>]*> ee201b10 fmdhr d0, r1 -0+174 <[^>]*> ee20eb10 fmdhr d0, lr -0+178 <[^>]*> ee210b10 fmdhr d1, r0 -0+17c <[^>]*> ee220b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f0b10 fmdhr d15, r0 -0+184 <[^>]*> ee001b10 fmdlr d0, r1 -0+188 <[^>]*> ee00eb10 fmdlr d0, lr -0+18c <[^>]*> ee010b10 fmdlr d1, r0 -0+190 <[^>]*> ee020b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f0b10 fmdlr d15, r0 -0+198 <[^>]*> ed910b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed900b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed900bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed100bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed901b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed902b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8ccbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec901b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec902b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec900b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec900b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec900b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec901b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec902b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec910b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e0b02 fldmiad lr, {d0} +0+148 <[^>]*> ee301b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee310b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee320b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee101b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee110b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee120b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee201b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee210b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee220b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee001b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee010b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee020b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed910b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\] +0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\] +0+1ac <[^>]*> ed901b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\] +0+1bc <[^>]*> ec901b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec902b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec900b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec900b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec900b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec901b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec902b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec910b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e0b02 vldmia lr, {d0} 0+1e8 <[^>]*> eeb50b40 fcmpzd d0 0+1ec <[^>]*> eeb51b40 fcmpzd d1 0+1f0 <[^>]*> eeb52b40 fcmpzd d2 @@ -162,20 +162,20 @@ Disassembly of section .text: 0+260 <[^>]*> 0e167b4b fnmscdeq d7, d6, d11 0+264 <[^>]*> 0e245b4c fnmuldeq d5, d4, d12 0+268 <[^>]*> 0e3d3b4e fsubdeq d3, d13, d14 -0+26c <[^>]*> 0d952b00 flddeq d2, \[r5\] -0+270 <[^>]*> 0d8c1b00 fstdeq d1, \[ip\] -0+274 <[^>]*> 0c911b02 fldmiadeq r1, {d1} -0+278 <[^>]*> 0c922b02 fldmiadeq r2, {d2} -0+27c <[^>]*> 0cb33b02 fldmiadeq r3!, {d3} -0+280 <[^>]*> 0cb44b02 fldmiadeq r4!, {d4} -0+284 <[^>]*> 0d355b02 fldmdbdeq r5!, {d5} -0+288 <[^>]*> 0d366b02 fldmdbdeq r6!, {d6} -0+28c <[^>]*> 0c87fb02 fstmiadeq r7, {d15} -0+290 <[^>]*> 0c88eb02 fstmiadeq r8, {d14} -0+294 <[^>]*> 0ca9db02 fstmiadeq r9!, {d13} -0+298 <[^>]*> 0caacb02 fstmiadeq sl!, {d12} -0+29c <[^>]*> 0d2bbb02 fstmdbdeq fp!, {d11} -0+2a0 <[^>]*> 0d2cab02 fstmdbdeq ip!, {d10} +0+26c <[^>]*> 0d952b00 vldreq d2, \[r5\] +0+270 <[^>]*> 0d8c1b00 vstreq d1, \[ip\] +0+274 <[^>]*> 0c911b02 vldmiaeq r1, {d1} +0+278 <[^>]*> 0c922b02 vldmiaeq r2, {d2} +0+27c <[^>]*> 0cb33b02 vldmiaeq r3!, {d3} +0+280 <[^>]*> 0cb44b02 vldmiaeq r4!, {d4} +0+284 <[^>]*> 0d355b02 vldmdbeq r5!, {d5} +0+288 <[^>]*> 0d366b02 vldmdbeq r6!, {d6} +0+28c <[^>]*> 0c87fb02 vstmiaeq r7, {d15} +0+290 <[^>]*> 0c88eb02 vstmiaeq r8, {d14} +0+294 <[^>]*> 0ca9db02 vstmiaeq r9!, {d13} +0+298 <[^>]*> 0caacb02 vstmiaeq sl!, {d12} +0+29c <[^>]*> 0d2bbb02 vstmdbeq fp!, {d11} +0+2a0 <[^>]*> 0d2cab02 vstmdbeq ip!, {d10} 0+2a4 <[^>]*> 0eb8fbe0 fsitodeq d15, s1 0+2a8 <[^>]*> 0eb81b6f fuitodeq d1, s31 0+2ac <[^>]*> 0efd0b4f ftosideq s1, d15 @@ -184,10 +184,10 @@ Disassembly of section .text: 0+2b8 <[^>]*> 0efc5bc3 ftouizdeq s11, d3 0+2bc <[^>]*> 0eb71ac5 fcvtdseq d1, s10 0+2c0 <[^>]*> 0ef75bc1 fcvtsdeq s11, d1 -0+2c4 <[^>]*> 0e318b10 fmrdheq r8, d1 -0+2c8 <[^>]*> 0e1f7b10 fmrdleq r7, d15 -0+2cc <[^>]*> 0e21fb10 fmdhreq d1, pc -0+2d0 <[^>]*> 0e0f1b10 fmdlreq d15, r1 +0+2c4 <[^>]*> 0e318b10 vmoveq\.32 r8, d1\[1\] +0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\] +0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc +0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1 0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) 0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) 0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d index 22c4fd6f01dc..3bf1f9a9d74b 100644 --- a/gas/testsuite/gas/arm/vfp1_t2.d +++ b/gas/testsuite/gas/arm/vfp1_t2.d @@ -24,20 +24,20 @@ Disassembly of section .text: 0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0 0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0 0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\] -0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} +0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\] +0+04c <[^>]*> ec90 0b02 vldmia r0, {d0} +0+050 <[^>]*> ec90 0b02 vldmia r0, {d0} +0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+068 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0} 0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0 0+080 <[^>]*> eeb8 0b40 fuitod d0, s0 0+084 <[^>]*> eebd 0b40 ftosid s0, d0 @@ -46,10 +46,10 @@ Disassembly of section .text: 0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0 0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0 0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee30 0b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0 +0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0 0+0ac <[^>]*> eeb5 1b40 fcmpzd d1 0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2 0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15 @@ -89,46 +89,46 @@ Disassembly of section .text: 0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1 0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2 0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15 -0+148 <[^>]*> ee30 1b10 fmrdh r1, d0 -0+14c <[^>]*> ee30 eb10 fmrdh lr, d0 -0+150 <[^>]*> ee31 0b10 fmrdh r0, d1 -0+154 <[^>]*> ee32 0b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15 -0+15c <[^>]*> ee10 1b10 fmrdl r1, d0 -0+160 <[^>]*> ee10 eb10 fmrdl lr, d0 -0+164 <[^>]*> ee11 0b10 fmrdl r0, d1 -0+168 <[^>]*> ee12 0b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15 -0+170 <[^>]*> ee20 1b10 fmdhr d0, r1 -0+174 <[^>]*> ee20 eb10 fmdhr d0, lr -0+178 <[^>]*> ee21 0b10 fmdhr d1, r0 -0+17c <[^>]*> ee22 0b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0 -0+184 <[^>]*> ee00 1b10 fmdlr d0, r1 -0+188 <[^>]*> ee00 eb10 fmdlr d0, lr -0+18c <[^>]*> ee01 0b10 fmdlr d1, r0 -0+190 <[^>]*> ee02 0b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0 -0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0} +0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\] +0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\] +0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\] +0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0} 0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0 0+1ec <[^>]*> eeb5 1b40 fcmpzd d1 0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2 @@ -145,61 +145,60 @@ Disassembly of section .text: 0+21c <[^>]*> eeb5 db40 fcmpzd d13 0+220 <[^>]*> eeb5 eb40 fcmpzd d14 0+224 <[^>]*> eeb5 fb40 fcmpzd d15 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. 0+228 <[^>]*> bf01 itttt eq -0+22a <[^>]*> eeb4 1bcf fcmped(eq|) d1, d15 -0+22e <[^>]*> eeb5 2bc0 fcmpezd(eq|) d2 -0+232 <[^>]*> eeb4 3b4e fcmpd(eq|) d3, d14 -0+236 <[^>]*> eeb5 4b40 fcmpzd(eq|) d4 +0+22a <[^>]*> eeb4 1bcf fcmpedeq d1, d15 +0+22e <[^>]*> eeb5 2bc0 fcmpezdeq d2 +0+232 <[^>]*> eeb4 3b4e fcmpdeq d3, d14 +0+236 <[^>]*> eeb5 4b40 fcmpzdeq d4 0+23a <[^>]*> bf01 itttt eq -0+23c <[^>]*> eeb0 5bcd fabsd(eq|) d5, d13 -0+240 <[^>]*> eeb0 6b4c fcpyd(eq|) d6, d12 -0+244 <[^>]*> eeb1 7b4b fnegd(eq|) d7, d11 -0+248 <[^>]*> eeb1 8bca fsqrtd(eq|) d8, d10 +0+23c <[^>]*> eeb0 5bcd fabsdeq d5, d13 +0+240 <[^>]*> eeb0 6b4c fcpydeq d6, d12 +0+244 <[^>]*> eeb1 7b4b fnegdeq d7, d11 +0+248 <[^>]*> eeb1 8bca fsqrtdeq d8, d10 0+24c <[^>]*> bf01 itttt eq -0+24e <[^>]*> ee31 9b0f faddd(eq|) d9, d1, d15 -0+252 <[^>]*> ee83 2b0e fdivd(eq|) d2, d3, d14 -0+256 <[^>]*> ee0d 4b0c fmacd(eq|) d4, d13, d12 -0+25a <[^>]*> ee16 5b0b fmscd(eq|) d5, d6, d11 +0+24e <[^>]*> ee31 9b0f fadddeq d9, d1, d15 +0+252 <[^>]*> ee83 2b0e fdivdeq d2, d3, d14 +0+256 <[^>]*> ee0d 4b0c fmacdeq d4, d13, d12 +0+25a <[^>]*> ee16 5b0b fmscdeq d5, d6, d11 0+25e <[^>]*> bf01 itttt eq -0+260 <[^>]*> ee2a 7b09 fmuld(eq|) d7, d10, d9 -0+264 <[^>]*> ee09 8b4a fnmacd(eq|) d8, d9, d10 -0+268 <[^>]*> ee16 7b4b fnmscd(eq|) d7, d6, d11 -0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12 +0+260 <[^>]*> ee2a 7b09 fmuldeq d7, d10, d9 +0+264 <[^>]*> ee09 8b4a fnmacdeq d8, d9, d10 +0+268 <[^>]*> ee16 7b4b fnmscdeq d7, d6, d11 +0+26c <[^>]*> ee24 5b4c fnmuldeq d5, d4, d12 0+270 <[^>]*> bf02 ittt eq -0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14 -0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\] -0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\] +0+272 <[^>]*> ee3d 3b4e fsubdeq d3, d13, d14 +0+276 <[^>]*> ed95 2b00 vldreq d2, \[r5\] +0+27a <[^>]*> ed8c 1b00 vstreq d1, \[ip\] 0+27e <[^>]*> bf01 itttt eq -0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1} -0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2} -0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3} -0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4} +0+280 <[^>]*> ec91 1b02 vldmiaeq r1, {d1} +0+284 <[^>]*> ec92 2b02 vldmiaeq r2, {d2} +0+288 <[^>]*> ecb3 3b02 vldmiaeq r3!, {d3} +0+28c <[^>]*> ecb4 4b02 vldmiaeq r4!, {d4} 0+290 <[^>]*> bf01 itttt eq -0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5} -0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6} -0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15} -0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14} +0+292 <[^>]*> ed35 5b02 vldmdbeq r5!, {d5} +0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6} +0+29a <[^>]*> ec87 fb02 vstmiaeq r7, {d15} +0+29e <[^>]*> ec88 eb02 vstmiaeq r8, {d14} 0+2a2 <[^>]*> bf01 itttt eq -0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13} -0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12} -0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11} -0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10} +0+2a4 <[^>]*> eca9 db02 vstmiaeq r9!, {d13} +0+2a8 <[^>]*> ecaa cb02 vstmiaeq sl!, {d12} +0+2ac <[^>]*> ed2b bb02 vstmdbeq fp!, {d11} +0+2b0 <[^>]*> ed2c ab02 vstmdbeq ip!, {d10} 0+2b4 <[^>]*> bf01 itttt eq -0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1 -0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31 -0+2be <[^>]*> eefd 0b4f ftosid(eq|) s1, d15 -0+2c2 <[^>]*> eefd fbc2 ftosizd(eq|) s31, d2 +0+2b6 <[^>]*> eeb8 fbe0 fsitodeq d15, s1 +0+2ba <[^>]*> eeb8 1b6f fuitodeq d1, s31 +0+2be <[^>]*> eefd 0b4f ftosideq s1, d15 +0+2c2 <[^>]*> eefd fbc2 ftosizdeq s31, d2 0+2c6 <[^>]*> bf01 itttt eq -0+2c8 <[^>]*> eefc 7b42 ftouid(eq|) s15, d2 -0+2cc <[^>]*> eefc 5bc3 ftouizd(eq|) s11, d3 -0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10 -0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1 +0+2c8 <[^>]*> eefc 7b42 ftouideq s15, d2 +0+2cc <[^>]*> eefc 5bc3 ftouizdeq s11, d3 +0+2d0 <[^>]*> eeb7 1ac5 fcvtdseq d1, s10 +0+2d4 <[^>]*> eef7 5bc1 fcvtsdeq s11, d1 0+2d8 <[^>]*> bf01 itttt eq -0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1 -0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15 -0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc -0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1 +0+2da <[^>]*> ee31 8b10 vmoveq\.32 r8, d1\[1\] +0+2de <[^>]*> ee1f 7b10 vmoveq\.32 r7, d15\[0\] +0+2e2 <[^>]*> ee21 fb10 vmoveq\.32 d1\[1\], pc +0+2e6 <[^>]*> ee0f 1b10 vmoveq\.32 d15\[0\], r1 0+2ea <[^>]*> bf00 nop 0+2ec <[^>]*> bf00 nop 0+2ee <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d index 096b46c86e4c..22932e5284c0 100644 --- a/gas/testsuite/gas/arm/vfp1xD.d +++ b/gas/testsuite/gas/arm/vfp1xD.d @@ -239,3 +239,15 @@ Disassembly of section .text: 0+394 <[^>]*> 0ef09a10 fmrxeq r9, fpsid 0+398 <[^>]*> 0e019a90 fmsreq s3, r9 0+39c <[^>]*> 0ee08a10 fmxreq fpsid, r8 +0+3a0 <[^>]*> eef90a10 fmrx r0, fpinst @ Impl def +0+3a4 <[^>]*> eefa0a10 fmrx r0, fpinst2 @ Impl def +0+3a8 <[^>]*> eef70a10 fmrx r0, mvfr0 +0+3ac <[^>]*> eef60a10 fmrx r0, mvfr1 +0+3b0 <[^>]*> eefc0a10 fmrx r0, <impl def 0xc> +0+3b4 <[^>]*> eee90a10 fmxr fpinst, r0 @ Impl def +0+3b8 <[^>]*> eeea0a10 fmxr fpinst2, r0 @ Impl def +0+3bc <[^>]*> eee70a10 fmxr mvfr0, r0 +0+3c0 <[^>]*> eee60a10 fmxr mvfr1, r0 +0+3c4 <[^>]*> eeec0a10 fmxr <impl def 0xc>, r0 +0+3c8 <[^>]*> e1a00000 nop \(mov r0,r0\) +0+3cc <[^>]*> e1a00000 nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s index 82f080f499b0..ecc022638158 100644 --- a/gas/testsuite/gas/arm/vfp1xD.s +++ b/gas/testsuite/gas/arm/vfp1xD.s @@ -337,3 +337,17 @@ F: fmsreq s3, r9 fmxreq fpsid, r8 + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + nop + nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d index 327383d01c5b..d2943114d6c0 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.d +++ b/gas/testsuite/gas/arm/vfp1xD_t2.d @@ -185,74 +185,87 @@ Disassembly of section .text: 0+2bc <[^>]*> eef5 ea40 fcmpzs s29 0+2c0 <[^>]*> eeb5 fa40 fcmpzs s30 0+2c4 <[^>]*> eef5 fa40 fcmpzs s31 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. 0+2c8 <[^>]*> bf01 itttt eq -0+2ca <[^>]*> eef1 fa10 fmstat(eq|) -0+2ce <[^>]*> eef4 1ae3 fcmpes(eq|) s3, s7 -0+2d2 <[^>]*> eef5 2ac0 fcmpezs(eq|) s5 -0+2d6 <[^>]*> eef4 0a41 fcmps(eq|) s1, s2 +0+2ca <[^>]*> eef1 fa10 fmstateq +0+2ce <[^>]*> eef4 1ae3 fcmpeseq s3, s7 +0+2d2 <[^>]*> eef5 2ac0 fcmpezseq s5 +0+2d6 <[^>]*> eef4 0a41 fcmpseq s1, s2 0+2da <[^>]*> bf01 itttt eq -0+2dc <[^>]*> eef5 0a40 fcmpzs(eq|) s1 -0+2e0 <[^>]*> eef0 0ae1 fabss(eq|) s1, s3 -0+2e4 <[^>]*> eef0 fa69 fcpys(eq|) s31, s19 -0+2e8 <[^>]*> eeb1 aa44 fnegs(eq|) s20, s8 +0+2dc <[^>]*> eef5 0a40 fcmpzseq s1 +0+2e0 <[^>]*> eef0 0ae1 fabsseq s1, s3 +0+2e4 <[^>]*> eef0 fa69 fcpyseq s31, s19 +0+2e8 <[^>]*> eeb1 aa44 fnegseq s20, s8 0+2ec <[^>]*> bf01 itttt eq -0+2ee <[^>]*> eef1 2ae3 fsqrts(eq|) s5, s7 -0+2f2 <[^>]*> ee32 3a82 fadds(eq|) s6, s5, s4 -0+2f6 <[^>]*> eec1 1a20 fdivs(eq|) s3, s2, s1 -0+2fa <[^>]*> ee4f fa2e fmacs(eq|) s31, s30, s29 +0+2ee <[^>]*> eef1 2ae3 fsqrtseq s5, s7 +0+2f2 <[^>]*> ee32 3a82 faddseq s6, s5, s4 +0+2f6 <[^>]*> eec1 1a20 fdivseq s3, s2, s1 +0+2fa <[^>]*> ee4f fa2e fmacseq s31, s30, s29 0+2fe <[^>]*> bf01 itttt eq -0+300 <[^>]*> ee1d ea8d fmscs(eq|) s28, s27, s26 -0+304 <[^>]*> ee6c ca2b fmuls(eq|) s25, s24, s23 -0+308 <[^>]*> ee0a baca fnmacs(eq|) s22, s21, s20 -0+30c <[^>]*> ee59 9a68 fnmscs(eq|) s19, s18, s17 +0+300 <[^>]*> ee1d ea8d fmscseq s28, s27, s26 +0+304 <[^>]*> ee6c ca2b fmulseq s25, s24, s23 +0+308 <[^>]*> ee0a baca fnmacseq s22, s21, s20 +0+30c <[^>]*> ee59 9a68 fnmscseq s19, s18, s17 0+310 <[^>]*> bf01 itttt eq -0+312 <[^>]*> ee27 8ac7 fnmuls(eq|) s16, s15, s14 -0+316 <[^>]*> ee76 6a65 fsubs(eq|) s13, s12, s11 -0+31a <[^>]*> ed98 5a00 flds(eq|) s10, \[r8\] -0+31e <[^>]*> edc7 4a00 fsts(eq|) s9, \[r7\] +0+312 <[^>]*> ee27 8ac7 fnmulseq s16, s15, s14 +0+316 <[^>]*> ee76 6a65 fsubseq s13, s12, s11 +0+31a <[^>]*> ed98 5a00 fldseq s10, \[r8\] +0+31e <[^>]*> edc7 4a00 fstseq s9, \[r7\] 0+322 <[^>]*> bf01 itttt eq -0+324 <[^>]*> ec91 4a01 fldmias(eq|) r1, {s8} -0+328 <[^>]*> ecd2 3a01 fldmias(eq|) r2, {s7} -0+32c <[^>]*> ecb3 3a01 fldmias(eq|) r3!, {s6} -0+330 <[^>]*> ecf4 2a01 fldmias(eq|) r4!, {s5} +0+324 <[^>]*> ec91 4a01 fldmiaseq r1, {s8} +0+328 <[^>]*> ecd2 3a01 fldmiaseq r2, {s7} +0+32c <[^>]*> ecb3 3a01 fldmiaseq r3!, {s6} +0+330 <[^>]*> ecf4 2a01 fldmiaseq r4!, {s5} 0+334 <[^>]*> bf01 itttt eq -0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4} -0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3} -0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1} -0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2} +0+336 <[^>]*> ed35 2a01 fldmdbseq r5!, {s4} +0+33a <[^>]*> ed76 1a01 fldmdbseq r6!, {s3} +0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1} +0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2} 0+346 <[^>]*> bf01 itttt eq -0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3} -0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4} -0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5} -0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6} +0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3} +0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4} +0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5} +0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6} 0+358 <[^>]*> bf01 itttt eq -0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2} -0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1} -0+362 <[^>]*> ece1 fa01 fstmias(eq|) r1!, {s31} -0+366 <[^>]*> eca2 fa01 fstmias(eq|) r2!, {s30} +0+35a <[^>]*> ec8d 1a01 fstmiaseq sp, {s2} +0+35e <[^>]*> ecce 0a01 fstmiaseq lr, {s1} +0+362 <[^>]*> ece1 fa01 fstmiaseq r1!, {s31} +0+366 <[^>]*> eca2 fa01 fstmiaseq r2!, {s30} 0+36a <[^>]*> bf01 itttt eq -0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29} -0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28} -0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7} -0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8} +0+36c <[^>]*> ed63 ea01 fstmdbseq r3!, {s29} +0+370 <[^>]*> ed24 ea01 fstmdbseq r4!, {s28} +0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7} +0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8} 0+37c <[^>]*> bf01 itttt eq -0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9} -0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10} -0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11} -0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12} +0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9} +0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10} +0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11} +0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12} 0+38e <[^>]*> bf01 itttt eq -0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6 -0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5 -0+398 <[^>]*> eefd bac2 ftosizs(eq|) s23, s4 -0+39c <[^>]*> eefc aa61 ftouis(eq|) s21, s3 +0+390 <[^>]*> eef8 dac3 fsitoseq s27, s6 +0+394 <[^>]*> eefd ca62 ftosiseq s25, s5 +0+398 <[^>]*> eefd bac2 ftosizseq s23, s4 +0+39c <[^>]*> eefc aa61 ftouiseq s21, s3 0+3a0 <[^>]*> bf01 itttt eq -0+3a2 <[^>]*> eefc 9ac1 ftouizs(eq|) s19, s2 -0+3a6 <[^>]*> eef8 8a60 fuitos(eq|) s17, s1 -0+3aa <[^>]*> ee11 ba90 fmrs(eq|) fp, s3 -0+3ae <[^>]*> eef0 9a10 fmrx(eq|) r9, fpsid +0+3a2 <[^>]*> eefc 9ac1 ftouizseq s19, s2 +0+3a6 <[^>]*> eef8 8a60 fuitoseq s17, s1 +0+3aa <[^>]*> ee11 ba90 fmrseq fp, s3 +0+3ae <[^>]*> eef0 9a10 fmrxeq r9, fpsid 0+3b2 <[^>]*> bf04 itt eq -0+3b4 <[^>]*> ee01 9a90 fmsr(eq|) s3, r9 -0+3b8 <[^>]*> eee0 8a10 fmxr(eq|) fpsid, r8 -0+3bc <[^>]*> bf00 nop -0+3be <[^>]*> bf00 nop +0+3b4 <[^>]*> ee01 9a90 fmsreq s3, r9 +0+3b8 <[^>]*> eee0 8a10 fmxreq fpsid, r8 +0+3bc <[^>]*> eef9 0a10 fmrx r0, fpinst @ Impl def +0+3c0 <[^>]*> eefa 0a10 fmrx r0, fpinst2 @ Impl def +0+3c4 <[^>]*> eef7 0a10 fmrx r0, mvfr0 +0+3c8 <[^>]*> eef6 0a10 fmrx r0, mvfr1 +0+3cc <[^>]*> eefc 0a10 fmrx r0, <impl def 0xc> +0+3d0 <[^>]*> eee9 0a10 fmxr fpinst, r0 @ Impl def +0+3d4 <[^>]*> eeea 0a10 fmxr fpinst2, r0 @ Impl def +0+3d8 <[^>]*> eee7 0a10 fmxr mvfr0, r0 +0+3dc <[^>]*> eee6 0a10 fmxr mvfr1, r0 +0+3e0 <[^>]*> eeec 0a10 fmxr <impl def 0xc>, r0 +0+3e4 <[^>]*> bf00 nop +0+3e6 <[^>]*> bf00 nop +0+3e8 <[^>]*> bf00 nop +0+3ea <[^>]*> bf00 nop +0+3ec <[^>]*> bf00 nop +0+3ee <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s index f3087a37ee96..8e962c07e3e9 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.s +++ b/gas/testsuite/gas/arm/vfp1xD_t2.s @@ -354,6 +354,21 @@ F: fmsreq s3, r9 fmxreq fpsid, r8 - @ 2 nops to pad to 16-byte boundary + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + nop + nop + nop + nop nop nop diff --git a/gas/testsuite/gas/arm/vfp2.d b/gas/testsuite/gas/arm/vfp2.d index f9b6096081eb..438019fc12ed 100644 --- a/gas/testsuite/gas/arm/vfp2.d +++ b/gas/testsuite/gas/arm/vfp2.d @@ -7,11 +7,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16} +0+000 <[^>]*> ec4a5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a5a37 fmsrr {s15, s16}, r5, sl 0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18} +0+010 <[^>]*> ec45ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45aa38 fmsrr {s17, s18}, sl, r5 0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18} diff --git a/gas/testsuite/gas/arm/vfp2_t2.d b/gas/testsuite/gas/arm/vfp2_t2.d index bb988e5472e2..f07b6a58bcba 100644 --- a/gas/testsuite/gas/arm/vfp2_t2.d +++ b/gas/testsuite/gas/arm/vfp2_t2.d @@ -7,11 +7,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16} +0+000 <[^>]*> ec4a 5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a 5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a 5a37 fmsrr {s15, s16}, r5, sl 0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18} +0+010 <[^>]*> ec45 ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55 ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45 aa38 fmsrr {s17, s18}, sl, r5 0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18} diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.d b/gas/testsuite/gas/arm/vfpv3-32drs.d new file mode 100644 index 000000000000..f42c373f4c3d --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-32drs.d @@ -0,0 +1,73 @@ +# name: VFPv3 extra D registers +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb03b66 fcpyd d3, d22 +0[0-9a-f]+ <[^>]+> eef06b43 fcpyd d22, d3 +0[0-9a-f]+ <[^>]+> eef76acb fcvtds d22, s22 +0[0-9a-f]+ <[^>]+> eeb7bbe6 fcvtsd s22, d22 +0[0-9a-f]+ <[^>]+> ee254b90 vmov\.32 d21\[1\], r4 +0[0-9a-f]+ <[^>]+> ee0b5b90 vmov\.32 d27\[0\], r5 +0[0-9a-f]+ <[^>]+> ee376b90 vmov\.32 r6, d23\[1\] +0[0-9a-f]+ <[^>]+> ee197b90 vmov\.32 r7, d25\[0\] +0[0-9a-f]+ <[^>]+> eef86bcb fsitod d22, s22 +0[0-9a-f]+ <[^>]+> eef85b6a fuitod d21, s21 +0[0-9a-f]+ <[^>]+> eebdab64 ftosid s20, d20 +0[0-9a-f]+ <[^>]+> eebdabe4 ftosizd s20, d20 +0[0-9a-f]+ <[^>]+> eefc9b63 ftouid s19, d19 +0[0-9a-f]+ <[^>]+> eefc9be3 ftouizd s19, d19 +0[0-9a-f]+ <[^>]+> edda3b01 vldr d19, \[sl, #4\] +0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\] +0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6} +0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20} +0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6} +0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20} +0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19} +0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24} +0[0-9a-f]+ <[^>]+> eeb03bc5 fabsd d3, d5 +0[0-9a-f]+ <[^>]+> eeb0cbe2 fabsd d12, d18 +0[0-9a-f]+ <[^>]+> eef02be3 fabsd d18, d19 +0[0-9a-f]+ <[^>]+> eeb13b45 fnegd d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cb62 fnegd d12, d18 +0[0-9a-f]+ <[^>]+> eef12b63 fnegd d18, d19 +0[0-9a-f]+ <[^>]+> eeb13bc5 fsqrtd d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cbe2 fsqrtd d12, d18 +0[0-9a-f]+ <[^>]+> eef12be3 fsqrtd d18, d19 +0[0-9a-f]+ <[^>]+> ee353b06 faddd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cb84 faddd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732ba4 faddd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee353b46 fsubd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cbc4 fsubd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732be4 fsubd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b06 fmuld d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cb84 fmuld d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632ba4 fmuld d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee853b06 fdivd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee82cb84 fdivd d12, d18, d4 +0[0-9a-f]+ <[^>]+> eec32ba4 fdivd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b06 fmacd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cb84 fmacd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432ba4 fmacd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b06 fmscd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cb84 fmscd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532ba4 fmscd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b46 fnmuld d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cbc4 fnmuld d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632be4 fnmuld d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b46 fnmacd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cbc4 fnmacd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432be4 fnmacd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b46 fnmscd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cbc4 fnmscd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532be4 fnmscd d18, d19, d20 +0[0-9a-f]+ <[^>]+> eeb43b62 fcmpd d3, d18 +0[0-9a-f]+ <[^>]+> eef42b43 fcmpd d18, d3 +0[0-9a-f]+ <[^>]+> eef53b40 fcmpzd d19 +0[0-9a-f]+ <[^>]+> eeb43be2 fcmped d3, d18 +0[0-9a-f]+ <[^>]+> eef42bc3 fcmped d18, d3 +0[0-9a-f]+ <[^>]+> eef53bc0 fcmpezd d19 +0[0-9a-f]+ <[^>]+> ec443b3f vmov d31, r3, r4 +0[0-9a-f]+ <[^>]+> ec565b3e vmov r5, r6, d30 diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.s b/gas/testsuite/gas/arm/vfpv3-32drs.s new file mode 100644 index 000000000000..ef72c24eb5ad --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-32drs.s @@ -0,0 +1,68 @@ +.arm +.syntax unified + fcpyd d3,d22 + fcpyd d22,d3 + fcvtds d22,s22 + fcvtsd s22,d22 + fmdhr d21,r4 + fmdlr d27,r5 + fmrdh r6,d23 + fmrdl r7,d25 + fsitod d22,s22 + fuitod d21,s21 + ftosid s20,d20 + ftosizd s20,d20 + ftouid s19,d19 + ftouizd s19,d19 + fldd d19,[r10,#4] + fstd d21,[r10,#4] + fldmiad r10!,{d5,d6} + fldmiad r10!,{d18,d19,d20} + fldmiax r10!,{d5,d6} + fldmiax r10!,{d18,d19,d20} + fldmdbx r10!,{d18,d19} + fstmiad r9,{d20,d21,d22,d23,d24} + fabsd d3,d5 + fabsd d12,d18 + fabsd d18,d19 + fnegd d3,d5 + fnegd d12,d18 + fnegd d18,d19 + fsqrtd d3,d5 + fsqrtd d12,d18 + fsqrtd d18,d19 + faddd d3,d5,d6 + faddd d12,d18,d4 + faddd d18,d19,d20 + fsubd d3,d5,d6 + fsubd d12,d18,d4 + fsubd d18,d19,d20 + fmuld d3,d5,d6 + fmuld d12,d18,d4 + fmuld d18,d19,d20 + fdivd d3,d5,d6 + fdivd d12,d18,d4 + fdivd d18,d19,d20 + fmacd d3,d5,d6 + fmacd d12,d18,d4 + fmacd d18,d19,d20 + fmscd d3,d5,d6 + fmscd d12,d18,d4 + fmscd d18,d19,d20 + fnmuld d3,d5,d6 + fnmuld d12,d18,d4 + fnmuld d18,d19,d20 + fnmacd d3,d5,d6 + fnmacd d12,d18,d4 + fnmacd d18,d19,d20 + fnmscd d3,d5,d6 + fnmscd d12,d18,d4 + fnmscd d18,d19,d20 + fcmpd d3,d18 + fcmpd d18,d3 + fcmpzd d19 + fcmped d3,d18 + fcmped d18,d3 + fcmpezd d19 + fmdrr d31,r3,r4 + fmrrd r5,r6,d30 diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.d b/gas/testsuite/gas/arm/vfpv3-const-conv.d new file mode 100644 index 000000000000..9515feff7133 --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-const-conv.d @@ -0,0 +1,29 @@ +# name: VFPv3 additional constant and conversion ops +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eef08a04 fconsts s17, #4 +0[0-9a-f]+ <[^>]+> eeba9a05 fconsts s18, #165 +0[0-9a-f]+ <[^>]+> eef49a00 fconsts s19, #64 +0[0-9a-f]+ <[^>]+> eef01b04 fconstd d17, #4 +0[0-9a-f]+ <[^>]+> eefa2b05 fconstd d18, #165 +0[0-9a-f]+ <[^>]+> eef43b00 fconstd d19, #64 +0[0-9a-f]+ <[^>]+> eefa8a63 fshtos s17, #9 +0[0-9a-f]+ <[^>]+> eefa1b63 fshtod d17, #9 +0[0-9a-f]+ <[^>]+> eefa8aeb fsltos s17, #9 +0[0-9a-f]+ <[^>]+> eefa1beb fsltod d17, #9 +0[0-9a-f]+ <[^>]+> eefb8a63 fuhtos s17, #9 +0[0-9a-f]+ <[^>]+> eefb1b63 fuhtod d17, #9 +0[0-9a-f]+ <[^>]+> eefb8aeb fultos s17, #9 +0[0-9a-f]+ <[^>]+> eefb1beb fultod d17, #9 +0[0-9a-f]+ <[^>]+> eefe9a64 ftoshs s19, #7 +0[0-9a-f]+ <[^>]+> eefe3b64 ftoshd d19, #7 +0[0-9a-f]+ <[^>]+> eefe9aec ftosls s19, #7 +0[0-9a-f]+ <[^>]+> eefe3bec ftosld d19, #7 +0[0-9a-f]+ <[^>]+> eeff9a64 ftouhs s19, #7 +0[0-9a-f]+ <[^>]+> eeff3b64 ftouhd d19, #7 +0[0-9a-f]+ <[^>]+> eeff9aec ftouls s19, #7 +0[0-9a-f]+ <[^>]+> eeff3bec ftould d19, #7 diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.s b/gas/testsuite/gas/arm/vfpv3-const-conv.s new file mode 100644 index 000000000000..d726d14b568e --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-const-conv.s @@ -0,0 +1,25 @@ +.arm +.syntax unified + fconsts s17, #4 + fconsts s18, #0xa5 + fconsts s19, #0x40 + fconstd d17, #4 + fconstd d18, #0xa5 + fconstd d19, #0x40 + fshtos s17, 9 + fshtod d17, 9 + fsltos s17, 9 + fsltod d17, 9 + fuhtos s17, 9 + fuhtod d17, 9 + fultos s17, 9 + fultod d17, 9 + + ftoshs s19, 7 + ftoshd d19, 7 + ftosls s19, 7 + ftosld d19, 7 + ftouhs s19, 7 + ftouhd d19, 7 + ftouls s19, 7 + ftould d19, 7 diff --git a/gas/testsuite/gas/arm/wince.d b/gas/testsuite/gas/arm/wince.d new file mode 100644 index 000000000000..1770cacd4f14 --- /dev/null +++ b/gas/testsuite/gas/arm/wince.d @@ -0,0 +1,30 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM WinCE basic tests +#as: -mcpu=arm7m -EL +#source: wince.s +#not-skip: *-wince-* + +# Some WinCE specific tests. + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <global_data> 00000007 andeq r0, r0, r7 + 0: ARM_32 global_data +0+004 <global_sym> e1a00000 nop \(mov r0,r0\) +0+008 <global_sym\+0x4> e1a00000 nop \(mov r0,r0\) +0+000c <global_sym\+0x8> e1a00000 nop \(mov r0,r0\) +0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4> + 10: ARM_26D global_sym\+0xf+ffc +0+018 <global_sym\+0x14> ebfffffa bl f+ff4 <global_sym\+0xf+ff0> + 14: ARM_26D global_sym\+0xf+ffc +0+01c <global_sym\+0x18> 0afffff9 beq f+ff0 <global_sym\+0xf+fec> + 18: ARM_26D global_sym\+0xf+ffc +0+020 <global_sym\+0x1c> eafffff8 b 0+008 <global_sym\+0x4> +0+024 <global_sym\+0x20> ebfffff7 bl 0+008 <global_sym\+0x4> +0+028 <global_sym\+0x24> 0afffff6 beq 0+008 <global_sym\+0x4> +0+02c <global_sym\+0x28> eafffff5 b 0+008 <global_sym\+0x4> +0+030 <global_sym\+0x2c> ebfffff4 bl 0+008 <global_sym\+0x4> +0+034 <global_sym\+0x30> e51f0034 ldr r0, \[pc, #-52\] ; 0+008 <global_sym\+0x4> +0+038 <global_sym\+0x34> e51f0038 ldr r0, \[pc, #-56\] ; 0+008 <global_sym\+0x4> +0+03c <global_sym\+0x38> e51f003c ldr r0, \[pc, #-60\] ; 0+008 <global_sym\+0x4> diff --git a/gas/testsuite/gas/arm/wince.s b/gas/testsuite/gas/arm/wince.s new file mode 100644 index 000000000000..e8b76a045901 --- /dev/null +++ b/gas/testsuite/gas/arm/wince.s @@ -0,0 +1,25 @@ + .global global_data + .text + .global global_sym + .def global_sym; .scl 2; .type 32; .endef + +global_data: + .word global_data+7 + +global_sym: +def_sym: +undef_sym: + nop + nop + nop + b global_sym + bl global_sym + beq global_sym + b def_sym + bl def_sym + beq def_sym + b undef_sym + bl undef_sym + ldr r0, global_sym + ldr r0, def_sym + ldr r0, undef_sym diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index a9852e0394b8..e3f060d90db0 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -36,7 +36,7 @@ Disassembly of section .text: 0+058 <[^>]*> 21a09008 ? movcs r9, r8 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 @@ -116,11 +116,11 @@ Disassembly of section .text: 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp 0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip 0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr 0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] 0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] 0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! @@ -132,7 +132,7 @@ Disassembly of section .text: 0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> 0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\] 0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] 0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] 0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! @@ -145,31 +145,31 @@ Disassembly of section .text: 0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> 0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] 0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} 0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} 0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} 0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} 0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} 0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} 0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ 0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 -0+260 <[^>]*> eb000000 ? bl 0+268 <[^>]*> +0+260 <[^>]*> eb000000 ? bl 0.* <[^>]*> [ ]*260:.*_wombat.* -0+264 <[^>]*> 5b000000 ? blpl 0+26c <[^>]*> +0+264 <[^>]*> 5b000000 ? blpl 0.* <[^>]*> [ ]*264:.*ARM.*hohum -0+268 <[^>]*> ea000000 ? b 0+270 <[^>]*> +0+268 <[^>]*> ea000000 ? b 0.* <[^>]*> [ ]*268:.*_wibble.* -0+26c <[^>]*> da000000 ? ble 0+274 <[^>]*> +0+26c <[^>]*> da000000 ? ble 0.* <[^>]*> [ ]*26c:.*testerfunc.* 0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 0+274 <[^>]*> e1a01002 ? mov r1, r2 diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d index fc38ba14e57e..32ecf1f3354a 100644 --- a/gas/testsuite/gas/arm/xscale.d +++ b/gas/testsuite/gas/arm/xscale.d @@ -24,12 +24,12 @@ Disassembly of section .text: 0+38 <[^>]*> f7d2f003 pld \[r2, r3\] 0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] 0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] -0+44 <[^>]*> 01c327d8 ldreqd r2, \[r3, #120\] -0+48 <[^>]*> b10540d6 ldrltd r4, \[r5, -r6\] +0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\] +0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] 0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]! 0+50 <[^>]*> e1ac00fd strd r0, \[ip, sp\]! -0+54 <[^>]*> 30ce21f0 strccd r2, \[lr\], #16 -0+58 <[^>]*> 708640f8 strvcd r4, \[r6\], r8 +0+54 <[^>]*> 30ce21f0 strdcc r2, \[lr\], #16 +0+58 <[^>]*> 708640f8 strdvc r4, \[r6\], r8 0+5c <[^>]*> e5910000 ldr r0, \[r1\] 0+60 <[^>]*> e5832000 str r2, \[r3\] 0+64 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11 |