diff options
Diffstat (limited to 'gas/testsuite/gas')
615 files changed, 38356 insertions, 3045 deletions
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 928dd88348e2..cb8c6777a432 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -16,7 +16,10 @@ gas_test "p2425.s" "" "" "pcrel values in assignment" # The ".space" directive is taken care of in the C54x-specific tests, so fail # here # -if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] } then { +# The test also doesn't work on mep targets, since they use RELC, and it +# will avoid simplifying the expression since it conservatively assumes +# ugly expressions can be saved until link-time. +if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] || [istarget mep*-*-*]} then { setup_xfail *-*-* fail "simplifiable double subtraction" } else { @@ -80,13 +83,18 @@ case $target_triplet in { default { setup_xfail "*c30*-*-*" "*c4x*-*-*" "pdp11-*-*" run_dump_test redef + # The next two tests can fail if the target does not convert fixups + # against ordinary symbols into relocations against section symbols. + # This is usually revealed by the error message: + # symbol `sym' required but not present setup_xfail "*c30*-*-*" "*c4x*-*-*" "*arm*-*-*aout*" "*arm*-*-*coff" \ "*arm*-*-pe" "crx*-*-*" "h8300*-*-*" "m68hc*-*-*" "maxq-*-*" \ - "pdp11-*-*" "vax*-*-*" "z8k-*-*" + "mn10300-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*" "cr16-*-*" run_dump_test redef2 setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \ "bfin-*-*" "*c4x*-*-*" "crx*-*-*" "h8300*-*-*" "hppa*-*-hpux*" \ - "m68hc*-*-*" "maxq-*-*" "or32-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*" + "m68hc*-*-*" "maxq-*-*" "mn10300-*-*" "or32-*-*" "pdp11-*-*" \ + "vax*-*-*" "z8k-*-*" "cr16-*-*" run_dump_test redef3 setup_xfail "*c4x*-*-*" gas_test_error "redef4.s" "" ".set for symbol already used as label" @@ -207,6 +215,7 @@ if { ([istarget *-*-coff*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*- || [istarget i*86-*-isc*] \ || [istarget i*86-*-go32*] \ || [istarget i*86-*-cygwin*] \ + || [istarget x86_64-*-mingw*] \ || [istarget i*86-*-*nt] \ || [istarget i*86-*-interix*] \ || ([istarget i960-*-vxworks5.*] && ![istarget i960-*-vxworks5.0*]) } { @@ -256,6 +265,11 @@ if { ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \ run_dump_test assign run_dump_test sleb128 +# .byte is 32 bits on tic4x, and .p2align isn't supported on tic54x +if { ![istarget "tic4x*-*-*"] && ![istarget "tic54x*-*-*"] } { + run_dump_test relax +} + # .quad is 16 bytes on i960. if { ![istarget "i960-*-*"] } { run_dump_test quad diff --git a/gas/testsuite/gas/all/relax.d b/gas/testsuite/gas/all/relax.d new file mode 100644 index 000000000000..1e581c2695b0 --- /dev/null +++ b/gas/testsuite/gas/all/relax.d @@ -0,0 +1,13 @@ +#objdump : -s -j .data -j "\$DATA\$" +#name : relax .uleb128 + +.*: .* + +Contents of section .* + 0000 01020381 01000000 00000000 00000000.* +#... + 0080 00000004 ffff0500 06078380 01000000.* +#... + 4080 00000000 00000000 00000008 ffffffff.* + 4090 09090909 09090909 09090909 09090909.* +#pass diff --git a/gas/testsuite/gas/all/relax.s b/gas/testsuite/gas/all/relax.s new file mode 100644 index 000000000000..104a8956bd6a --- /dev/null +++ b/gas/testsuite/gas/all/relax.s @@ -0,0 +1,20 @@ + .data + .byte 1, 2, 3 + .uleb128 L2 - L1 +L1: + .space 128 - 2 + .byte 4 + .p2align 1, 0xff +L2: + .byte 5 + + .p2align 2 + .byte 6, 7 + .uleb128 L4 - L3 +L3: + .space 128*128 - 2 + .byte 8 + .p2align 2, 0xff +L4: + .byte 9 + .p2align 4, 9 diff --git a/gas/testsuite/gas/alpha/alpha.exp b/gas/testsuite/gas/alpha/alpha.exp index da785ae04043..04d99329dd7a 100644 --- a/gas/testsuite/gas/alpha/alpha.exp +++ b/gas/testsuite/gas/alpha/alpha.exp @@ -2,19 +2,6 @@ # Some generic alpha tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "alpha $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if { [istarget alpha*-*-*] } then { set elf [expr [istarget *-*-elf*] \ diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d index 0fdaa8fdecbe..f7e343f03bc1 100644 --- a/gas/testsuite/gas/arm/arch4t.d +++ b/gas/testsuite/gas/arm/arch4t.d @@ -11,14 +11,14 @@ Disassembly of section .text: 0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] 0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] 0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! -0+18 <[^>]+> 011510d3 ? ldreqsb r1, \[r5, -r3\] -0+1c <[^>]+> 109620b7 ? ldrneh r2, \[r6\], r7 -0+20 <[^>]+> 309720f8 ? ldrccsh r2, \[r7\], r8 +0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] +0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 +0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\] 0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\] 0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\] 0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strneh r3, \[r3\] +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2 0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d index 992948b83314..9cf73edf1891 100644 --- a/gas/testsuite/gas/arm/arch7.d +++ b/gas/testsuite/gas/arm/arch7.d @@ -1,6 +1,5 @@ #name: ARM V7 instructions #as: -march=armv7r -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* #objdump: -dr --prefix-addresses --show-raw-insn .*: +file format .*arm.* @@ -29,8 +28,8 @@ Disassembly of section .text: 0+050 <[^>]*> f995 f000 pli \[r5\] 0+054 <[^>]*> f995 ffff pli \[r5, #4095\] 0+058 <[^>]*> f915 fcff pli \[r5, #-255\] -0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0000105f <[^>]*> -0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; fffff065 <[^>]*> +0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*> +0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*> 0+064 <[^>]*> f3af 80f0 dbg #0 0+068 <[^>]*> f3af 80ff dbg #15 0+06c <[^>]*> f3bf 8f5f dmb sy diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d index 1dbaad3a714f..6015a4707ec9 100644 --- a/gas/testsuite/gas/arm/archv6.d +++ b/gas/testsuite/gas/arm/archv6.d @@ -13,13 +13,13 @@ Disassembly of section .text: 0+014 <[^>]*> fc4570c3 ? mcrr2 0, 12, r7, r5, cr3 0+018 <[^>]*> fc5570c3 ? mrrc2 0, 12, r7, r5, cr3 0+01c <[^>]*> e6852018 ? pkhbt r2, r5, r8 -0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, LSL #3 +0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, lsl #3 0+02c <[^>]*> e6882015 ? pkhbt r2, r8, r5 -0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, ASR #3 +0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, asr #3 0+03c <[^>]*> e6242f17 ? qadd16 r2, r4, r7 0+040 <[^>]*> 16242f17 ? qadd16ne r2, r4, r7 0+044 <[^>]*> e6242f97 ? qadd8 r2, r4, r7 @@ -49,19 +49,19 @@ Disassembly of section .text: 0+0a4 <[^>]*> e6142f17 ? sadd16 r2, r4, r7 0+0a8 <[^>]*> 16142f17 ? sadd16ne r2, r4, r7 0+0ac <[^>]*> e6b42075 ? sxtah r2, r4, r5 -0+0b0 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ROR #8 +0+0b0 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ror #8 0+0b4 <[^>]*> 16b42075 ? sxtahne r2, r4, r5 -0+0b8 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ROR #8 +0+0b8 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ror #8 0+0bc <[^>]*> e6142f97 ? sadd8 r2, r4, r7 0+0c0 <[^>]*> 16142f97 ? sadd8ne r2, r4, r7 0+0c4 <[^>]*> e6842075 ? sxtab16 r2, r4, r5 -0+0c8 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ROR #8 +0+0c8 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ror #8 0+0cc <[^>]*> 16842075 ? sxtab16ne r2, r4, r5 -0+0d0 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ROR #8 +0+0d0 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ror #8 0+0d4 <[^>]*> e6a42075 ? sxtab r2, r4, r5 -0+0d8 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ROR #8 +0+0d8 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ror #8 0+0dc <[^>]*> 16a42075 ? sxtabne r2, r4, r5 -0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8 +0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ror #8 0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7 0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7 0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3 @@ -116,11 +116,11 @@ Disassembly of section .text: 0+1b0 <[^>]*> d701f352 ? smusdle r1, r2, r3 0+1b4 <[^>]*> e701f372 ? smusdx r1, r2, r3 0+1b8 <[^>]*> d701f372 ? smusdxle r1, r2, r3 -0+1bc <[^>]*> f8cd0510 ? srsia #16 -0+1c0 <[^>]*> f9ed0510 ? srsib #16! +0+1bc <[^>]*> f8cd0510 ? srsia sp, #16 +0+1c0 <[^>]*> f9ed0510 ? srsib sp!, #16 0+1c4 <[^>]*> e6a01012 ? ssat r1, #1, r2 -0+1c8 <[^>]*> e6a01152 ? ssat r1, #1, r2, ASR #2 -0+1cc <[^>]*> e6a01112 ? ssat r1, #1, r2, LSL #2 +0+1c8 <[^>]*> e6a01152 ? ssat r1, #1, r2, asr #2 +0+1cc <[^>]*> e6a01112 ? ssat r1, #1, r2, lsl #2 0+1d0 <[^>]*> e6a01f31 ? ssat16 r1, #1, r1 0+1d4 <[^>]*> d6a01f31 ? ssat16le r1, #1, r1 0+1d8 <[^>]*> e6142f77 ? ssub16 r2, r4, r7 @@ -131,34 +131,34 @@ Disassembly of section .text: 0+1ec <[^>]*> 16142f57 ? ssubaddxne r2, r4, r7 0+1f0 <[^>]*> e1831f92 ? strex r1, r2, \[r3\] 0+1f4 <[^>]*> 11831f92 ? strexne r1, r2, \[r3\] -0+1f8 <[^>]*> e6bf2075 ? sxth r2,r5 -0+1fc <[^>]*> e6bf2475 ? sxth r2,r5, ROR #8 -0+200 <[^>]*> 16bf2075 ? sxthne r2,r5 -0+204 <[^>]*> 16bf2475 ? sxthne r2,r5, ROR #8 -0+208 <[^>]*> e68f2075 ? sxtb16 r2,r5 -0+20c <[^>]*> e68f2475 ? sxtb16 r2,r5, ROR #8 -0+210 <[^>]*> 168f2075 ? sxtb16ne r2,r5 -0+214 <[^>]*> 168f2475 ? sxtb16ne r2,r5, ROR #8 -0+218 <[^>]*> e6af2075 ? sxtb r2,r5 -0+21c <[^>]*> e6af2475 ? sxtb r2,r5, ROR #8 -0+220 <[^>]*> 16af2075 ? sxtbne r2,r5 -0+224 <[^>]*> 16af2475 ? sxtbne r2,r5, ROR #8 +0+1f8 <[^>]*> e6bf2075 ? sxth r2, r5 +0+1fc <[^>]*> e6bf2475 ? sxth r2, r5, ror #8 +0+200 <[^>]*> 16bf2075 ? sxthne r2, r5 +0+204 <[^>]*> 16bf2475 ? sxthne r2, r5, ror #8 +0+208 <[^>]*> e68f2075 ? sxtb16 r2, r5 +0+20c <[^>]*> e68f2475 ? sxtb16 r2, r5, ror #8 +0+210 <[^>]*> 168f2075 ? sxtb16ne r2, r5 +0+214 <[^>]*> 168f2475 ? sxtb16ne r2, r5, ror #8 +0+218 <[^>]*> e6af2075 ? sxtb r2, r5 +0+21c <[^>]*> e6af2475 ? sxtb r2, r5, ror #8 +0+220 <[^>]*> 16af2075 ? sxtbne r2, r5 +0+224 <[^>]*> 16af2475 ? sxtbne r2, r5, ror #8 0+228 <[^>]*> e6542f17 ? uadd16 r2, r4, r7 0+22c <[^>]*> 16542f17 ? uadd16ne r2, r4, r7 0+230 <[^>]*> e6f32075 ? uxtah r2, r3, r5 -0+234 <[^>]*> e6f32475 ? uxtah r2, r3, r5, ROR #8 +0+234 <[^>]*> e6f32475 ? uxtah r2, r3, r5, ror #8 0+238 <[^>]*> 16f32075 ? uxtahne r2, r3, r5 -0+23c <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ROR #8 +0+23c <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ror #8 0+240 <[^>]*> e6542f97 ? uadd8 r2, r4, r7 0+244 <[^>]*> 16542f97 ? uadd8ne r2, r4, r7 0+248 <[^>]*> e6c32075 ? uxtab16 r2, r3, r5 -0+24c <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ROR #8 +0+24c <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ror #8 0+250 <[^>]*> 16c32075 ? uxtab16ne r2, r3, r5 -0+254 <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ROR #8 +0+254 <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ror #8 0+258 <[^>]*> e6e32075 ? uxtab r2, r3, r5 -0+25c <[^>]*> e6e32475 ? uxtab r2, r3, r5, ROR #8 +0+25c <[^>]*> e6e32475 ? uxtab r2, r3, r5, ror #8 0+260 <[^>]*> 16e32075 ? uxtabne r2, r3, r5 -0+264 <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ROR #8 +0+264 <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ror #8 0+268 <[^>]*> e6542f37 ? uaddsubx r2, r4, r7 0+26c <[^>]*> 16542f37 ? uaddsubxne r2, r4, r7 0+270 <[^>]*> e6742f17 ? uhadd16 r2, r4, r7 @@ -192,28 +192,32 @@ Disassembly of section .text: 0+2e0 <[^>]*> e7814312 ? usada8 r1, r2, r3, r4 0+2e4 <[^>]*> 17814312 ? usada8ne r1, r2, r3, r4 0+2e8 <[^>]*> e6ef1012 ? usat r1, #15, r2 -0+2ec <[^>]*> e6ef1252 ? usat r1, #15, r2, ASR #4 -0+2f0 <[^>]*> e6ef1212 ? usat r1, #15, r2, LSL #4 +0+2ec <[^>]*> e6ef1252 ? usat r1, #15, r2, asr #4 +0+2f0 <[^>]*> e6ef1212 ? usat r1, #15, r2, lsl #4 0+2f4 <[^>]*> e6ef1f32 ? usat16 r1, #15, r2 0+2f8 <[^>]*> d6ef1f32 ? usat16le r1, #15, r2 0+2fc <[^>]*> d6ef1012 ? usatle r1, #15, r2 -0+300 <[^>]*> d6ef1252 ? usatle r1, #15, r2, ASR #4 -0+304 <[^>]*> d6ef1212 ? usatle r1, #15, r2, LSL #4 +0+300 <[^>]*> d6ef1252 ? usatle r1, #15, r2, asr #4 +0+304 <[^>]*> d6ef1212 ? usatle r1, #15, r2, lsl #4 0+308 <[^>]*> e6542f77 ? usub16 r2, r4, r7 0+30c <[^>]*> 16542f77 ? usub16ne r2, r4, r7 0+310 <[^>]*> e6542ff7 ? usub8 r2, r4, r7 0+314 <[^>]*> 16542ff7 ? usub8ne r2, r4, r7 0+318 <[^>]*> e6542f57 ? usubaddx r2, r4, r7 0+31c <[^>]*> 16542f57 ? usubaddxne r2, r4, r7 -0+320 <[^>]*> e6ff2075 ? uxth r2,r5 -0+324 <[^>]*> e6ff2475 ? uxth r2,r5, ROR #8 -0+328 <[^>]*> 16ff2075 ? uxthne r2,r5 -0+32c <[^>]*> 16ff2475 ? uxthne r2,r5, ROR #8 -0+330 <[^>]*> e6cf2075 ? uxtb16 r2,r5 -0+334 <[^>]*> e6cf2475 ? uxtb16 r2,r5, ROR #8 -0+338 <[^>]*> 16cf2075 ? uxtb16ne r2,r5 -0+33c <[^>]*> 16cf2475 ? uxtb16ne r2,r5, ROR #8 -0+340 <[^>]*> e6ef2075 ? uxtb r2,r5 -0+344 <[^>]*> e6ef2475 ? uxtb r2,r5, ROR #8 -0+348 <[^>]*> 16ef2075 ? uxtbne r2,r5 -0+34c <[^>]*> 16ef2475 ? uxtbne r2,r5, ROR #8 +0+320 <[^>]*> e6ff2075 ? uxth r2, r5 +0+324 <[^>]*> e6ff2475 ? uxth r2, r5, ror #8 +0+328 <[^>]*> 16ff2075 ? uxthne r2, r5 +0+32c <[^>]*> 16ff2475 ? uxthne r2, r5, ror #8 +0+330 <[^>]*> e6cf2075 ? uxtb16 r2, r5 +0+334 <[^>]*> e6cf2475 ? uxtb16 r2, r5, ror #8 +0+338 <[^>]*> 16cf2075 ? uxtb16ne r2, r5 +0+33c <[^>]*> 16cf2475 ? uxtb16ne r2, r5, ror #8 +0+340 <[^>]*> e6ef2075 ? uxtb r2, r5 +0+344 <[^>]*> e6ef2475 ? uxtb r2, r5, ror #8 +0+348 <[^>]*> 16ef2075 ? uxtbne r2, r5 +0+34c <[^>]*> 16ef2475 ? uxtbne r2, r5, ror #8 +0+350 <[^>]*> f10a00ca ? cpsie if,#10 +0+354 <[^>]*> f10a00d5 ? cpsie if,#21 +0+358 <[^>]*> f8cd0510 ? srsia sp, #16 +0+35c <[^>]*> f9ed0510 ? srsib sp!, #16 diff --git a/gas/testsuite/gas/arm/archv6.s b/gas/testsuite/gas/arm/archv6.s index 50378b7c3798..85f05c185d02 100644 --- a/gas/testsuite/gas/arm/archv6.s +++ b/gas/testsuite/gas/arm/archv6.s @@ -214,3 +214,7 @@ label: uxtb r2, r5, ROR #8 uxtbne r2, r5 uxtbne r2, r5, ROR #8 + cpsie if, #10 + cpsie if, #21 + srsia sp, #16 + srsib sp!, #16 diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d index 8e8b0387a336..e6e57c843b90 100644 --- a/gas/testsuite/gas/arm/archv6t2.d +++ b/gas/testsuite/gas/arm/archv6t2.d @@ -24,10 +24,10 @@ Disassembly of section .text: 0+40 <[^>]+> e7a00059 sbfx r0, r9, #0, #1 0+44 <[^>]+> e7a008d0 sbfx r0, r0, #17, #1 0+48 <[^>]+> e7b10050 sbfx r0, r0, #0, #18 -0+4c <[^>]+> e3ff0f30 rbit r0, r0 -0+50 <[^>]+> 13ff0f30 rbitne r0, r0 -0+54 <[^>]+> e3ff9f30 rbit r9, r0 -0+58 <[^>]+> e3ff0f39 rbit r0, r9 +0+4c <[^>]+> e6ff0f30 rbit r0, r0 +0+50 <[^>]+> 16ff0f30 rbitne r0, r0 +0+54 <[^>]+> e6ff9f30 rbit r9, r0 +0+58 <[^>]+> e6ff0f39 rbit r0, r9 0+5c <[^>]+> e0600090 mls r0, r0, r0, r0 0+60 <[^>]+> 10600090 mlsne r0, r0, r0, r0 0+64 <[^>]+> e0690090 mls r9, r0, r0, r0 @@ -44,7 +44,7 @@ Disassembly of section .text: 0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\] 0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\] 0+98 <[^>]+> e0e900b0 strht r0, \[r9\] -0+9c <[^>]+> 10f900b0 ldrneht r0, \[r9\] +0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\] 0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153 diff --git a/gas/testsuite/gas/arm/arm-it.d b/gas/testsuite/gas/arm/arm-it.d new file mode 100644 index 000000000000..674f815f1dec --- /dev/null +++ b/gas/testsuite/gas/arm/arm-it.d @@ -0,0 +1,9 @@ +#name: ARM IT instruction +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 +0+004 <[^>]*> e1a0f00e ? mov pc, lr diff --git a/gas/testsuite/gas/arm/arm-it.s b/gas/testsuite/gas/arm/arm-it.s new file mode 100644 index 000000000000..f3c56e8c4b70 --- /dev/null +++ b/gas/testsuite/gas/arm/arm-it.s @@ -0,0 +1,8 @@ + # Check that IT is accepted in ARM mode on older architectures + .text + .syntax unified + .arch armv4 +label1: + it eq + moveq r0, #0 + mov pc, lr diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d index 06323b1c0cdf..41b6b7eb8fdc 100644 --- a/gas/testsuite/gas/arm/arm3.d +++ b/gas/testsuite/gas/arm/arm3.d @@ -7,5 +7,5 @@ Disassembly of section .text: 0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\] 0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\] -0+8 <[^>]*> a1454091 ? swpgeb r4, r1, \[r5\] +0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\] 0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d index ef47ca6c6689..43f64204e97a 100644 --- a/gas/testsuite/gas/arm/arm7dm.d +++ b/gas/testsuite/gas/arm/arm7dm.d @@ -11,7 +11,7 @@ Disassembly of section .text: 0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3 0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4 0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp -0+18 <[^>]+> 00b92994 ? umlaleqs r2, r9, r4, r9 +0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9 0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr 0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0 0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d index 17e4e9d4fb5e..37abd7a7781f 100644 --- a/gas/testsuite/gas/arm/arm7t.d +++ b/gas/testsuite/gas/arm/arm7t.d @@ -49,20 +49,20 @@ Disassembly of section .text: 0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*> 0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*> 0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+a8 <[^>]*> 119100b2 ? ldrneh r0, \[r1, r2\] -0+ac <[^>]*> 819100b2 ? ldrhih r0, \[r1, r2\] -0+b0 <[^>]*> b19100b2 ? ldrlth r0, \[r1, r2\] +0+a8 <[^>]*> 119100b2 ? ldrhne r0, \[r1, r2\] +0+ac <[^>]*> 819100b2 ? ldrhhi r0, \[r1, r2\] +0+b0 <[^>]*> b19100b2 ? ldrhlt r0, \[r1, r2\] 0+b4 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+b8 <[^>]*> 119100f2 ? ldrnesh r0, \[r1, r2\] -0+bc <[^>]*> 819100f2 ? ldrhish r0, \[r1, r2\] -0+c0 <[^>]*> b19100f2 ? ldrltsh r0, \[r1, r2\] +0+b8 <[^>]*> 119100f2 ? ldrshne r0, \[r1, r2\] +0+bc <[^>]*> 819100f2 ? ldrshhi r0, \[r1, r2\] +0+c0 <[^>]*> b19100f2 ? ldrshlt r0, \[r1, r2\] 0+c4 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+c8 <[^>]*> 119100d2 ? ldrnesb r0, \[r1, r2\] -0+cc <[^>]*> 819100d2 ? ldrhisb r0, \[r1, r2\] -0+d0 <[^>]*> b19100d2 ? ldrltsb r0, \[r1, r2\] +0+c8 <[^>]*> 119100d2 ? ldrsbne r0, \[r1, r2\] +0+cc <[^>]*> 819100d2 ? ldrsbhi r0, \[r1, r2\] +0+d0 <[^>]*> b19100d2 ? ldrsblt r0, \[r1, r2\] 0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*> 0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*> -0+dc <[^>]*> 00000000 ? andeq r0, r0, r0 +0+dc <[^>]*> 00000000 ? .* [ ]*dc:.*fred 0+e0 <[^>]*> 0000c0de ? .* 0+e4 <[^>]*> 0000dead ? .* diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d index 4e4c91376179..99e8471e2222 100644 --- a/gas/testsuite/gas/arm/armv1.d +++ b/gas/testsuite/gas/arm/armv1.d @@ -1,6 +1,7 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: ARM v1 instructions #as: -mcpu=arm7t +#error-output: armv1.l # Test the ARM v1 instructions @@ -52,19 +53,19 @@ Disassembly of section .text: 0+a8 <[^>]*> e5c00000 ? strb r0, \[r0\] 0+ac <[^>]*> e4a10000 ? strt r0, \[r1\] 0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\] -0+b4 <[^>]*> e8800001 ? stmia r0, {r0} +0+b4 <[^>]*> e8800001 ? stm r0, {r0} 0+b8 <[^>]*> e9800001 ? stmib r0, {r0} 0+bc <[^>]*> e8000001 ? stmda r0, {r0} 0+c0 <[^>]*> e9000001 ? stmdb r0, {r0} 0+c4 <[^>]*> e9000001 ? stmdb r0, {r0} 0+c8 <[^>]*> e9800001 ? stmib r0, {r0} -0+cc <[^>]*> e8800001 ? stmia r0, {r0} +0+cc <[^>]*> e8800001 ? stm r0, {r0} 0+d0 <[^>]*> e8000001 ? stmda r0, {r0} -0+d4 <[^>]*> e8900001 ? ldmia r0, {r0} +0+d4 <[^>]*> e8900001 ? ldm r0, {r0} 0+d8 <[^>]*> e9900001 ? ldmib r0, {r0} 0+dc <[^>]*> e8100001 ? ldmda r0, {r0} 0+e0 <[^>]*> e9100001 ? ldmdb r0, {r0} -0+e4 <[^>]*> e8900001 ? ldmia r0, {r0} +0+e4 <[^>]*> e8900001 ? ldm r0, {r0} 0+e8 <[^>]*> e8100001 ? ldmda r0, {r0} 0+ec <[^>]*> e9100001 ? ldmdb r0, {r0} 0+f0 <[^>]*> e9900001 ? ldmib r0, {r0} diff --git a/gas/testsuite/gas/arm/armv1.l b/gas/testsuite/gas/arm/armv1.l new file mode 100644 index 000000000000..369f9d4a5105 --- /dev/null +++ b/gas/testsuite/gas/arm/armv1.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:26: Warning: s suffix on comparison instruction is deprecated +[^:]*:29: Warning: s suffix on comparison instruction is deprecated +[^:]*:32: Warning: s suffix on comparison instruction is deprecated +[^:]*:35: Warning: s suffix on comparison instruction is deprecated diff --git a/gas/testsuite/gas/arm/backslash-at.d b/gas/testsuite/gas/arm/backslash-at.d new file mode 100644 index 000000000000..a8992bdb4fac --- /dev/null +++ b/gas/testsuite/gas/arm/backslash-at.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Backslash-at for ARM + +.*: file format .*arm.* + +Disassembly of section .text: +0+000 <.*>.*615c.* +0+002 <foo> e3a00000 mov r0, #0 ; 0x0 +0+006 <foo\+0x4> e3a00000 mov r0, #0 ; 0x0 +0+00a <foo\+0x8> e3a00000 mov r0, #0 ; 0x0 +0+00e <foo\+0xc> e3a00001 mov r0, #1 ; 0x1 +0+012 <foo\+0x10> e3a00001 mov r0, #1 ; 0x1 +0+016 <foo\+0x14> e3a00001 mov r0, #1 ; 0x1 +0+01a <foo\+0x18> e3a00002 mov r0, #2 ; 0x2 +0+01e <foo\+0x1c> e3a00002 mov r0, #2 ; 0x2 +0+022 <foo\+0x20> e3a00002 mov r0, #2 ; 0x2 +#... diff --git a/gas/testsuite/gas/arm/backslash-at.s b/gas/testsuite/gas/arm/backslash-at.s new file mode 100644 index 000000000000..4975aea688f8 --- /dev/null +++ b/gas/testsuite/gas/arm/backslash-at.s @@ -0,0 +1,16 @@ +@ Check that \@ is not destroyed when assembling for the ARM. + +.macro bar + mov r0, #\@ + mov r0, #\@@comment + mov r0, #\@ @comment +.endm + +.byte '\\ +.byte '\a + +foo: + bar + bar + bar + diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d index 5f5dd110e99a..37d0f2d6fdb5 100644 --- a/gas/testsuite/gas/arm/copro.d +++ b/gas/testsuite/gas/arm/copro.d @@ -12,7 +12,7 @@ Disassembly of section .text: 0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] 0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] 0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]! -0+014 <[^>]*> 5cf31710 ldcpll 7, cr1, \[r3\], #64 +0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64 0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] 0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] 0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] @@ -31,7 +31,7 @@ Disassembly of section .text: 0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\} 0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\} 0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\} -0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\} +0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\} 0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\} 0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4 0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 diff --git a/gas/testsuite/gas/arm/copro.s b/gas/testsuite/gas/arm/copro.s index 334b000f4409..e6976329c756 100644 --- a/gas/testsuite/gas/arm/copro.s +++ b/gas/testsuite/gas/arm/copro.s @@ -33,7 +33,8 @@ bar: stcl p8, c2, [r5], {5} ldc2l 9, c1, [r6], {6} stc2l p10, c0, [r7], {7} - ldcl 11, c8, [r8], {255} + @ using '11' below results in an (invalid) Neon vldmia instruction. + ldcl 12, c8, [r8], {255} stcl p12, c9, [r9], {254} mrrc 13, 0, r7, r0, cr4 mcrr p14, 0, r7, r0, cr5 diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d new file mode 100644 index 000000000000..e10a6a7589ba --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-alu-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l new file mode 100644 index 000000000000..fe8827cec78b --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l @@ -0,0 +1,81 @@ +[^:]*: Assembler messages: +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable diff --git a/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s new file mode 100644 index 000000000000..bdde4ad45068 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s @@ -0,0 +1,35 @@ +@ Tests that should fail for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym + \offset) + \insn r0, r0, #:pc_g1:(\sym + \offset) + \insn r0, r0, #:pc_g2:(\sym + \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym + \offset) + \insn r0, r0, #:pc_g1_nc:(\sym + \offset) + + \insn r0, r0, #:sb_g0:(\sym + \offset) + \insn r0, r0, #:sb_g1:(\sym + \offset) + \insn r0, r0, #:sb_g2:(\sym + \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym + \offset) + \insn r0, r0, #:sb_g1_nc:(\sym + \offset) + + .endm + + alutest add f 0x11001 + alutest add localsym 0x11001 + alutest adds f 0x11001 + alutest adds localsym 0x11001 + + alutest add f "-0x11001" + alutest add localsym "-0x11001" + alutest adds f "-0x11001" + alutest adds localsym "-0x11001" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d new file mode 100644 index 000000000000..808bc05f0805 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-alu-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l new file mode 100644 index 000000000000..1c27ad02ffc9 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)' +[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)' +[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)' +[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)' diff --git a/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s new file mode 100644 index 000000000000..70a62acefa60 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s @@ -0,0 +1,12 @@ +@ Tests that should fail for ALU group relocations. + + .text + +@ Group relocs aren't allowed on SUB(S) instructions... + sub r0, r0, #:pc_g0:(foo) + subs r0, r0, #:pc_g0:(foo) + +@ Some nonexistent relocations: + add r0, r0, #:pc_g2_nc:(foo) + add r0, r0, #:sb_g2_nc:(foo) + diff --git a/gas/testsuite/gas/arm/group-reloc-alu.d b/gas/testsuite/gas/arm/group-reloc-alu.d new file mode 100644 index 000000000000..40e502588375 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.d @@ -0,0 +1,168 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (alu) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 10: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 14: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 18: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 1c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 20: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 24: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 28: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 2c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 30: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 34: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 38: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 3c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 40: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 44: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 48: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 50: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 54: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 58: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 5c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 60: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 64: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 68: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 6c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 70: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 74: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 78: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 7c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 80: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 84: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 88: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 8c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 90: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 94: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 98: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 9c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ac: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b0: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b4: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b8: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + bc: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c0: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c4: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c8: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + cc: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d0: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d4: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d8: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + dc: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e0: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e4: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e8: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ec: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + fc: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 100: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 104: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 108: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 10c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 110: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 114: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 118: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 11c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 120: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 124: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 128: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 12c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 130: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 134: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 138: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 13c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-alu.s b/gas/testsuite/gas/arm/group-reloc-alu.s new file mode 100644 index 000000000000..696f1dac0cc4 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-alu.s @@ -0,0 +1,39 @@ +@ Tests for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym \offset) + \insn r0, r0, #:pc_g1:(\sym \offset) + +@ Try this one without the hash; it should still work. + \insn r0, r0, :pc_g2:(\sym \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym \offset) + \insn r0, r0, #:pc_g1_nc:(\sym \offset) + + \insn r0, r0, #:sb_g0:(\sym \offset) + \insn r0, r0, #:sb_g1:(\sym \offset) + \insn r0, r0, #:sb_g2:(\sym \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym \offset) + \insn r0, r0, #:sb_g1_nc:(\sym \offset) + + .endm + + alutest add f "+ 0x100" + alutest add localsym "+ 0x100" + alutest adds f "+ 0x100" + alutest adds localsym "+ 0x100" + +@ The following should cause the insns to be switched to SUB(S). + + alutest add f "- 0x100" + alutest add localsym "- 0x100" + alutest adds f "- 0x100" + alutest adds localsym "- 0x100" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d new file mode 100644 index 000000000000..52ee2e55b653 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldc-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l new file mode 100644 index 000000000000..22e53a5901d6 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l @@ -0,0 +1,721 @@ +[^:]*: Assembler messages: +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s new file mode 100644 index 000000000000..5ab27c25fb7a --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s @@ -0,0 +1,169 @@ +@ LDC group relocation tests that are supposed to fail during encoding. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store cst + + \load 0, c0, [r0, #:pc_g0:(f + \cst)] + \load 0, c0, [r0, #:pc_g1:(f + \cst)] + \load 0, c0, [r0, #:pc_g2:(f + \cst)] + + \load 0, c0, [r0, #:sb_g0:(f + \cst)] + \load 0, c0, [r0, #:sb_g1:(f + \cst)] + \load 0, c0, [r0, #:sb_g2:(f + \cst)] + + \store 0, c0, [r0, #:pc_g0:(f + \cst)] + \store 0, c0, [r0, #:pc_g1:(f + \cst)] + \store 0, c0, [r0, #:pc_g2:(f + \cst)] + + \store 0, c0, [r0, #:sb_g0:(f + \cst)] + \store 0, c0, [r0, #:sb_g1:(f + \cst)] + \store 0, c0, [r0, #:sb_g2:(f + \cst)] + + \load 0, c0, [r0, #:pc_g0:(f - \cst)] + \load 0, c0, [r0, #:pc_g1:(f - \cst)] + \load 0, c0, [r0, #:pc_g2:(f - \cst)] + + \load 0, c0, [r0, #:sb_g0:(f - \cst)] + \load 0, c0, [r0, #:sb_g1:(f - \cst)] + \load 0, c0, [r0, #:sb_g2:(f - \cst)] + + \store 0, c0, [r0, #:pc_g0:(f - \cst)] + \store 0, c0, [r0, #:pc_g1:(f - \cst)] + \store 0, c0, [r0, #:pc_g2:(f - \cst)] + + \store 0, c0, [r0, #:sb_g0:(f - \cst)] + \store 0, c0, [r0, #:sb_g1:(f - \cst)] + \store 0, c0, [r0, #:sb_g2:(f - \cst)] + + .endm + + ldctest ldc stc 0x1 + ldctest ldcl stcl 0x1 + ldctest ldc2 stc2 0x1 + ldctest ldc2l stc2l 0x1 + + ldctest ldc stc 0x808 + ldctest ldcl stcl 0x808 + ldctest ldc2 stc2 0x808 + ldctest ldc2l stc2l 0x808 + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store cst + + \load f0, [r0, #:pc_g0:(f + \cst)] + \load f0, [r0, #:pc_g1:(f + \cst)] + \load f0, [r0, #:pc_g2:(f + \cst)] + + \load f0, [r0, #:sb_g0:(f + \cst)] + \load f0, [r0, #:sb_g1:(f + \cst)] + \load f0, [r0, #:sb_g2:(f + \cst)] + + \store f0, [r0, #:pc_g0:(f + \cst)] + \store f0, [r0, #:pc_g1:(f + \cst)] + \store f0, [r0, #:pc_g2:(f + \cst)] + + \store f0, [r0, #:sb_g0:(f + \cst)] + \store f0, [r0, #:sb_g1:(f + \cst)] + \store f0, [r0, #:sb_g2:(f + \cst)] + + \load f0, [r0, #:pc_g0:(f - \cst)] + \load f0, [r0, #:pc_g1:(f - \cst)] + \load f0, [r0, #:pc_g2:(f - \cst)] + + \load f0, [r0, #:sb_g0:(f - \cst)] + \load f0, [r0, #:sb_g1:(f - \cst)] + \load f0, [r0, #:sb_g2:(f - \cst)] + + \store f0, [r0, #:pc_g0:(f - \cst)] + \store f0, [r0, #:pc_g1:(f - \cst)] + \store f0, [r0, #:pc_g2:(f - \cst)] + + \store f0, [r0, #:sb_g0:(f - \cst)] + \store f0, [r0, #:sb_g1:(f - \cst)] + \store f0, [r0, #:sb_g2:(f - \cst)] + + .endm + + fpa_test ldfs stfs 0x1 + fpa_test ldfd stfd 0x1 + fpa_test ldfe stfe 0x1 + fpa_test ldfp stfp 0x1 + + fpa_test ldfs stfs 0x808 + fpa_test ldfd stfd 0x808 + fpa_test ldfe stfe 0x808 + fpa_test ldfp stfp 0x808 + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg cst + + \load \reg, [r0, #:pc_g0:(f + \cst)] + \load \reg, [r0, #:pc_g1:(f + \cst)] + \load \reg, [r0, #:pc_g2:(f + \cst)] + + \load \reg, [r0, #:sb_g0:(f + \cst)] + \load \reg, [r0, #:sb_g1:(f + \cst)] + \load \reg, [r0, #:sb_g2:(f + \cst)] + + \store \reg, [r0, #:pc_g0:(f + \cst)] + \store \reg, [r0, #:pc_g1:(f + \cst)] + \store \reg, [r0, #:pc_g2:(f + \cst)] + + \store \reg, [r0, #:sb_g0:(f + \cst)] + \store \reg, [r0, #:sb_g1:(f + \cst)] + \store \reg, [r0, #:sb_g2:(f + \cst)] + + \load \reg, [r0, #:pc_g0:(f - \cst)] + \load \reg, [r0, #:pc_g1:(f - \cst)] + \load \reg, [r0, #:pc_g2:(f - \cst)] + + \load \reg, [r0, #:sb_g0:(f - \cst)] + \load \reg, [r0, #:sb_g1:(f - \cst)] + \load \reg, [r0, #:sb_g2:(f - \cst)] + + \store \reg, [r0, #:pc_g0:(f - \cst)] + \store \reg, [r0, #:pc_g1:(f - \cst)] + \store \reg, [r0, #:pc_g2:(f - \cst)] + + \store \reg, [r0, #:sb_g0:(f - \cst)] + \store \reg, [r0, #:sb_g1:(f - \cst)] + \store \reg, [r0, #:sb_g2:(f - \cst)] + + .endm + + vfp_test flds fsts s0 0x1 + vfp_test flds fsts s0 0x808 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 0x1 + vfp_test fldd fstd d0 0x808 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 0x1 + vfp_test vldr vstr d0 0x808 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 0x1 + vfp_test cfldrd cfstrd mvd0 0x1 + vfp_test cfldr32 cfstr32 mvfx0 0x1 + vfp_test cfldr64 cfstr64 mvdx0 0x1 + + vfp_test cfldrs cfstrs mvf0 0x808 + vfp_test cfldrd cfstrd mvd0 0x808 + vfp_test cfldr32 cfstr32 mvfx0 0x808 + vfp_test cfldr64 cfstr64 mvdx0 0x808 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d new file mode 100644 index 000000000000..09e32997e855 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldc-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l new file mode 100644 index 000000000000..238d94db1d94 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l @@ -0,0 +1,147 @@ +[^:]*: Assembler messages: +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:54: Error: too many positional arguments +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s new file mode 100644 index 000000000000..a815f5de75b5 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s @@ -0,0 +1,67 @@ +@ Tests for LDC group relocations that are meant to fail during parsing. + + .macro ldctest insn reg + + \insn 0, \reg, [r0, #:pc_g0_nc:(sym)] + \insn 0, \reg, [r0, #:pc_g1_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g0_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g1_nc:(sym)] + + \insn 0, \reg, [r0, #:foo:(sym)] + + .endm + + .macro ldctest2 insn reg + + \insn \reg, [r0, #:pc_g0_nc:(sym)] + \insn \reg, [r0, #:pc_g1_nc:(sym)] + \insn \reg, [r0, #:sb_g0_nc:(sym)] + \insn \reg, [r0, #:sb_g1_nc:(sym)] + + \insn \reg, [r0, #:foo:(sym)] + + .endm + + ldctest ldc c0 + ldctest ldcl c0 + ldctest ldc2 c0 + ldctest ldc2l c0 + + ldctest stc c0 + ldctest stcl c0 + ldctest stc2 c0 + ldctest stc2l c0 + + .fpu fpa + + ldctest2 ldfs f0 + ldctest2 stfs f0 + ldctest2 ldfd f0 + ldctest2 stfd f0 + ldctest2 ldfe f0 + ldctest2 stfe f0 + ldctest2 ldfp f0 + ldctest2 stfp f0 + + .fpu vfp + + ldctest2 flds s0 + ldctest2 fsts s0 + + ldctest2 fldd d0 + ldctest2 fstd d0 + + ldctest2 vldr d0 FIXME + ldctest2 vstr d0 + + .cpu ep9312 + + ldctest2 cfldrs mvf0 + ldctest2 cfstrs mvf0 + ldctest2 cfldrd mvd0 + ldctest2 cfstrd mvd0 + ldctest2 cfldr32 mvfx0 + ldctest2 cfstr32 mvfx0 + ldctest2 cfldr64 mvdx0 + ldctest2 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.d b/gas/testsuite/gas/arm/group-reloc-ldc.d new file mode 100644 index 000000000000..731a025f0441 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.d @@ -0,0 +1,727 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldc) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 10: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\] + 14: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 18: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 1c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 20: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 24: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 28: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\] + 2c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 30: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 34: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 38: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 3c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 40: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\] + 44: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 48: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 4c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 50: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 54: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 58: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\] + 5c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 60: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 64: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 68: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 6c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 70: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\] + 74: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 78: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 7c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 80: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 84: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 88: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\] + 8c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 90: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 94: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 98: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + 9c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\] + a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\] + bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\] + d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\] + ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 100: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\] + 104: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 108: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 10c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 110: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 114: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 118: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\] + 11c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 120: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 124: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 128: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 12c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 130: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\] + 134: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 138: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 13c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 140: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 144: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 148: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\] + 14c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 150: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 154: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 158: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 15c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 160: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\] + 164: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 168: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 16c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 170: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 174: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 178: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\] + 17c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 180: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 184: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 188: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 18c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 190: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\] + 194: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 198: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 19c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\] + 1ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\] + 1c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\] + 1dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\] + 1f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 1fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 200: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 204: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 208: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\] + 20c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 210: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 214: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 218: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 21c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 220: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\] + 224: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 228: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 22c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 230: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 234: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 238: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\] + 23c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 240: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 244: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 248: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 24c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 250: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\] + 254: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 258: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 25c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 260: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 264: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 268: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\] + 26c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 270: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 274: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 278: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 27c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 280: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\] + 284: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 288: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 28c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 290: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 294: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 298: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\] + 29c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2a8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2ac: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\] + 2b4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2b8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2bc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2c8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\] + 2cc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2d8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2dc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\] + 2e4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2e8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2ec: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2f8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\] + 2fc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 300: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 304: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 308: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 30c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 310: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\] + 314: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 318: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 31c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 320: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 324: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 328: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\] + 32c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 330: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 334: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 338: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 33c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 340: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\] + 344: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 348: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 34c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 350: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 354: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 358: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\] + 35c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 360: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 364: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 368: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 36c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 370: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 374: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 378: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 37c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 380: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 384: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 388: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 38c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 390: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 394: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 398: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 39c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 3bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\] + 3d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\] + 3ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 3fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 400: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\] + 404: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 408: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 40c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 410: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 414: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 418: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\] + 41c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 420: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 424: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 428: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 42c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 430: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\] + 434: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 438: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 43c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 440: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 444: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 448: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\] + 44c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 450: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 454: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 458: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 45c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 460: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\] + 464: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 468: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 46c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 470: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 474: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 478: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\] + 47c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 480: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 484: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 488: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 48c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 490: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\] + 494: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 498: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 49c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\] + 4ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\] + 4c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\] + 4dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\] + 4f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 4fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 500: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 504: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 508: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\] + 50c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 510: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 514: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 518: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 51c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 520: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\] + 524: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 528: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 52c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 530: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 534: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 538: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\] + 53c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 540: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 544: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 548: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 54c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 550: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\] + 554: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 558: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 55c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 560: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 564: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 568: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\] + 56c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 570: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 574: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 578: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 57c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 580: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\] + 584: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 588: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 58c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 590: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 594: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 598: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\] + 59c: R_ARM_LDC_SB_G2 f diff --git a/gas/testsuite/gas/arm/group-reloc-ldc.s b/gas/testsuite/gas/arm/group-reloc-ldc.s new file mode 100644 index 000000000000..df27aaf55e07 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldc.s @@ -0,0 +1,151 @@ +@ LDC group relocation tests. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store + + \load 0, c0, [r0, #:pc_g0:(f + 0x214)] + \load 0, c0, [r0, #:pc_g1:(f + 0x214)] + \load 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f + 0x214)] + \load 0, c0, [r0, #:sb_g1:(f + 0x214)] + \load 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f + 0x214)] + \store 0, c0, [r0, #:pc_g1:(f + 0x214)] + \store 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f + 0x214)] + \store 0, c0, [r0, #:sb_g1:(f + 0x214)] + \store 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \load 0, c0, [r0, #:pc_g0:(f - 0x214)] + \load 0, c0, [r0, #:pc_g1:(f - 0x214)] + \load 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f - 0x214)] + \load 0, c0, [r0, #:sb_g1:(f - 0x214)] + \load 0, c0, [r0, #:sb_g2:(f - 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f - 0x214)] + \store 0, c0, [r0, #:pc_g1:(f - 0x214)] + \store 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f - 0x214)] + \store 0, c0, [r0, #:sb_g1:(f - 0x214)] + \store 0, c0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + ldctest ldc stc + ldctest ldcl stcl + ldctest ldc2 stc2 + ldctest ldc2l stc2l + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store + + \load f0, [r0, #:pc_g0:(f + 0x214)] + \load f0, [r0, #:pc_g1:(f + 0x214)] + \load f0, [r0, #:pc_g2:(f + 0x214)] + + \load f0, [r0, #:sb_g0:(f + 0x214)] + \load f0, [r0, #:sb_g1:(f + 0x214)] + \load f0, [r0, #:sb_g2:(f + 0x214)] + + \store f0, [r0, #:pc_g0:(f + 0x214)] + \store f0, [r0, #:pc_g1:(f + 0x214)] + \store f0, [r0, #:pc_g2:(f + 0x214)] + + \store f0, [r0, #:sb_g0:(f + 0x214)] + \store f0, [r0, #:sb_g1:(f + 0x214)] + \store f0, [r0, #:sb_g2:(f + 0x214)] + + \load f0, [r0, #:pc_g0:(f - 0x214)] + \load f0, [r0, #:pc_g1:(f - 0x214)] + \load f0, [r0, #:pc_g2:(f - 0x214)] + + \load f0, [r0, #:sb_g0:(f - 0x214)] + \load f0, [r0, #:sb_g1:(f - 0x214)] + \load f0, [r0, #:sb_g2:(f - 0x214)] + + \store f0, [r0, #:pc_g0:(f - 0x214)] + \store f0, [r0, #:pc_g1:(f - 0x214)] + \store f0, [r0, #:pc_g2:(f - 0x214)] + + \store f0, [r0, #:sb_g0:(f - 0x214)] + \store f0, [r0, #:sb_g1:(f - 0x214)] + \store f0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + fpa_test ldfs stfs + fpa_test ldfd stfd + fpa_test ldfe stfe + fpa_test ldfp stfp + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg + + \load \reg, [r0, #:pc_g0:(f + 0x214)] + \load \reg, [r0, #:pc_g1:(f + 0x214)] + \load \reg, [r0, #:pc_g2:(f + 0x214)] + + \load \reg, [r0, #:sb_g0:(f + 0x214)] + \load \reg, [r0, #:sb_g1:(f + 0x214)] + \load \reg, [r0, #:sb_g2:(f + 0x214)] + + \store \reg, [r0, #:pc_g0:(f + 0x214)] + \store \reg, [r0, #:pc_g1:(f + 0x214)] + \store \reg, [r0, #:pc_g2:(f + 0x214)] + + \store \reg, [r0, #:sb_g0:(f + 0x214)] + \store \reg, [r0, #:sb_g1:(f + 0x214)] + \store \reg, [r0, #:sb_g2:(f + 0x214)] + + \load \reg, [r0, #:pc_g0:(f - 0x214)] + \load \reg, [r0, #:pc_g1:(f - 0x214)] + \load \reg, [r0, #:pc_g2:(f - 0x214)] + + \load \reg, [r0, #:sb_g0:(f - 0x214)] + \load \reg, [r0, #:sb_g1:(f - 0x214)] + \load \reg, [r0, #:sb_g2:(f - 0x214)] + + \store \reg, [r0, #:pc_g0:(f - 0x214)] + \store \reg, [r0, #:pc_g1:(f - 0x214)] + \store \reg, [r0, #:pc_g2:(f - 0x214)] + + \store \reg, [r0, #:sb_g0:(f - 0x214)] + \store \reg, [r0, #:sb_g1:(f - 0x214)] + \store \reg, [r0, #:sb_g2:(f - 0x214)] + + .endm + + vfp_test flds fsts s0 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 + vfp_test cfldrd cfstrd mvd0 + vfp_test cfldr32 cfstr32 mvfx0 + vfp_test cfldr64 cfstr64 mvdx0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d new file mode 100644 index 000000000000..49ba77478e44 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldr-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l new file mode 100644 index 000000000000..276a341dc34d --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l @@ -0,0 +1,97 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s new file mode 100644 index 000000000000..3c528f19975b --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s @@ -0,0 +1,39 @@ +@ Tests that are supposed to fail during encoding +@ for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all fail. + + ldrtest ldr str f "+ 4096" + ldrtest ldrb strb f "+ 4096" + ldrtest ldr str f "- 4096" + ldrtest ldrb strb f "- 4096" + + ldrtest ldr str localsym "+ 4096" + ldrtest ldrb strb localsym "+ 4096" + ldrtest ldr str localsym "- 4096" + ldrtest ldrb strb localsym "- 4096" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d new file mode 100644 index 000000000000..fa0941e80a9e --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldr-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l new file mode 100644 index 000000000000..316a6a6c8d8d --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]' +[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]' +[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]' +[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s new file mode 100644 index 000000000000..c7d0ba759651 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s @@ -0,0 +1,33 @@ +@ Tests that are supposed to fail during parsing of LDR group relocations. + + .text + +@ No NC variants exist for the LDR relocations. + + ldr r0, [r0, #:pc_g0_nc:(f)] + ldr r0, [r0, #:pc_g1_nc:(f)] + ldr r0, [r0, #:sb_g0_nc:(f)] + ldr r0, [r0, #:sb_g1_nc:(f)] + + str r0, [r0, #:pc_g0_nc:(f)] + str r0, [r0, #:pc_g1_nc:(f)] + str r0, [r0, #:sb_g0_nc:(f)] + str r0, [r0, #:sb_g1_nc:(f)] + + ldrb r0, [r0, #:pc_g0_nc:(f)] + ldrb r0, [r0, #:pc_g1_nc:(f)] + ldrb r0, [r0, #:sb_g0_nc:(f)] + ldrb r0, [r0, #:sb_g1_nc:(f)] + + strb r0, [r0, #:pc_g0_nc:(f)] + strb r0, [r0, #:pc_g1_nc:(f)] + strb r0, [r0, #:sb_g0_nc:(f)] + strb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + + ldr r0, [r0, #:foo:(f)] + str r0, [r0, #:foo:(f)] + ldrb r0, [r0, #:foo:(f)] + strb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.d b/gas/testsuite/gas/arm/group-reloc-ldr.d new file mode 100644 index 000000000000..cfc1b235cb6c --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.d @@ -0,0 +1,200 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldr) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 0: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 4: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 8: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 10: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + 14: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 18: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 1c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 20: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 24: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 28: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + 2c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 30: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 34: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 38: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 3c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 40: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 44: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 48: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 4c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 50: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 54: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 58: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 5c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 60: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 64: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 68: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 6c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 70: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 74: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 78: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 7c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 80: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 84: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 88: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 8c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 90: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 94: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 98: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 9c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a0: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + a4: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + a8: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + ac: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b0: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b4: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + b8: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + bc: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + c8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + cc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d0: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\] + d4: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + d8: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + dc: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e0: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e4: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + e8: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\] + ec: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + f8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + fc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 100: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\] + 104: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 108: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 10c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 110: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 114: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 118: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\] + 11c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 120: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 124: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 128: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 12c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 130: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\] + 134: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 138: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 13c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 140: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 144: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 148: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\] + 14c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 150: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 154: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 158: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 15c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 160: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\] + 164: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 168: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 16c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 170: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 174: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 178: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\] + 17c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldr.s b/gas/testsuite/gas/arm/group-reloc-ldr.s new file mode 100644 index 000000000000..389042d70aff --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldr.s @@ -0,0 +1,41 @@ +@ Tests for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all (just) work. + + ldrtest ldr str f "+ 4095" + ldrtest ldrb strb f "+ 4095" + ldrtest ldr str f "- 4095" + ldrtest ldrb strb f "- 4095" + +@ The same as the above, but for a local symbol. These should not be +@ resolved by the assembler but instead left to the linker. + + ldrtest ldr str localsym "+ 4095" + ldrtest ldrb strb localsym "+ 4095" + ldrtest ldr str localsym "- 4095" + ldrtest ldrb strb localsym "- 4095" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d new file mode 100644 index 000000000000..ff8babf8d5a3 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldrs-encoding-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l new file mode 100644 index 000000000000..2621002d2ee4 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l @@ -0,0 +1,121 @@ +[^:]*: Assembler messages: +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s new file mode 100644 index 000000000000..ac7a90f0e9e2 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s @@ -0,0 +1,54 @@ +@ Tests that are meant to fail during encoding of LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) fail. + + ldrtest ldrd strd f "+ 256" + ldrtest ldrh strh f "+ 256" + ldrtest2 ldrsh f "+ 256" + ldrtest2 ldrsb f "+ 256" + + ldrtest ldrd strd f "- 256" + ldrtest ldrh strh f "- 256" + ldrtest2 ldrsh f "- 256" + ldrtest2 ldrsb f "- 256" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 256" + ldrtest ldrh strh localsym "+ 256" + ldrtest2 ldrsh localsym "+ 256" + ldrtest2 ldrsb localsym "+ 256" + + ldrtest ldrd strd localsym "- 256" + ldrtest ldrh strh localsym "- 256" + ldrtest2 ldrsh localsym "- 256" + ldrtest2 ldrsb localsym "- 256" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d new file mode 100644 index 000000000000..cb46d8465d1e --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldrs-parsing-bad.l diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l new file mode 100644 index 000000000000..b3d60351f198 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]' +[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]' +[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]' +[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]' +[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]' +[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]' diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s new file mode 100644 index 000000000000..16c1bea5ecfc --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s @@ -0,0 +1,44 @@ +@ Tests that are supposed to fail during parsing of LDRS group relocations. + + .text + +@ No NC variants exist for the LDRS relocations. + + ldrd r0, [r0, #:pc_g0_nc:(f)] + ldrd r0, [r0, #:pc_g1_nc:(f)] + ldrd r0, [r0, #:sb_g0_nc:(f)] + ldrd r0, [r0, #:sb_g1_nc:(f)] + + strd r0, [r0, #:pc_g0_nc:(f)] + strd r0, [r0, #:pc_g1_nc:(f)] + strd r0, [r0, #:sb_g0_nc:(f)] + strd r0, [r0, #:sb_g1_nc:(f)] + + ldrh r0, [r0, #:pc_g0_nc:(f)] + ldrh r0, [r0, #:pc_g1_nc:(f)] + ldrh r0, [r0, #:sb_g0_nc:(f)] + ldrh r0, [r0, #:sb_g1_nc:(f)] + + strh r0, [r0, #:pc_g0_nc:(f)] + strh r0, [r0, #:pc_g1_nc:(f)] + strh r0, [r0, #:sb_g0_nc:(f)] + strh r0, [r0, #:sb_g1_nc:(f)] + + ldrsh r0, [r0, #:pc_g0_nc:(f)] + ldrsh r0, [r0, #:pc_g1_nc:(f)] + ldrsh r0, [r0, #:sb_g0_nc:(f)] + ldrsh r0, [r0, #:sb_g1_nc:(f)] + + ldrsb r0, [r0, #:pc_g0_nc:(f)] + ldrsb r0, [r0, #:pc_g1_nc:(f)] + ldrsb r0, [r0, #:sb_g0_nc:(f)] + ldrsb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + ldrd r0, [r0, #:foo:(f)] + strd r0, [r0, #:foo:(f)] + ldrh r0, [r0, #:foo:(f)] + strh r0, [r0, #:foo:(f)] + ldrsh r0, [r0, #:foo:(f)] + ldrsb r0, [r0, #:foo:(f)] + diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.d b/gas/testsuite/gas/arm/group-reloc-ldrs.d new file mode 100644 index 000000000000..9896f4bdb6f6 --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.d @@ -0,0 +1,248 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: Group relocation tests (ldrs) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 10: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 14: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 18: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 1c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 20: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 24: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 28: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 2c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 30: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 34: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 38: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 3c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 40: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 44: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 48: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 4c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 50: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 54: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 58: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 5c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 60: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 64: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 68: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 6c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 70: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 74: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 78: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 7c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 80: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 84: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 88: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 8c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 90: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 94: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 98: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 9c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + a8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + ac: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + b0: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b4: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + b8: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + bc: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c0: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + c4: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + c8: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + cc: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d0: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d4: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + d8: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + dc: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e0: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e4: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + e8: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + ec: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f0: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f4: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + f8: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + fc: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] + 100: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 104: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 108: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 10c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 110: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] + 114: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 118: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 11c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 120: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 124: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] + 128: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 12c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 130: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 134: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 138: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] + 13c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 140: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 144: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 148: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 14c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] + 150: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 154: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 158: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 15c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 160: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] + 164: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 168: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 16c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 170: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 174: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] + 178: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 17c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 180: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 184: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 188: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] + 18c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 190: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 194: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 198: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 19c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] + 1a0: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a4: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1a8: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1ac: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b0: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] + 1b4: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1b8: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1bc: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c0: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c4: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] + 1c8: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1cc: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d0: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d4: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1d8: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] + 1dc: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0 diff --git a/gas/testsuite/gas/arm/group-reloc-ldrs.s b/gas/testsuite/gas/arm/group-reloc-ldrs.s new file mode 100644 index 000000000000..fa74e7eabe0a --- /dev/null +++ b/gas/testsuite/gas/arm/group-reloc-ldrs.s @@ -0,0 +1,54 @@ +@ Tests for LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) work. + + ldrtest ldrd strd f "+ 255" + ldrtest ldrh strh f "+ 255" + ldrtest2 ldrsh f "+ 255" + ldrtest2 ldrsb f "+ 255" + + ldrtest ldrd strd f "- 255" + ldrtest ldrh strh f "- 255" + ldrtest2 ldrsh f "- 255" + ldrtest2 ldrsb f "- 255" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 255" + ldrtest ldrh strh localsym "+ 255" + ldrtest2 ldrsh localsym "+ 255" + ldrtest2 ldrsb localsym "+ 255" + + ldrtest ldrd strd localsym "- 255" + ldrtest ldrh strh localsym "- 255" + ldrtest2 ldrsh localsym "- 255" + ldrtest2 ldrsb localsym "- 255" + +localsym: + mov r0, #0 + diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d index fbf27b4ab8db..4d56e8eca3d2 100644 --- a/gas/testsuite/gas/arm/inst.d +++ b/gas/testsuite/gas/arm/inst.d @@ -11,11 +11,11 @@ Disassembly of section .text: 0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 0+004 <[^>]*> e1a01002 ? mov r1, r2 -0+008 <[^>]*> e1a03184 ? mov r3, r4, lsl #3 -0+00c <[^>]*> e1a05736 ? mov r5, r6, lsr r7 -0+010 <[^>]*> e1a08a59 ? mov r8, r9, asr sl -0+014 <[^>]*> e1a0bd1c ? mov fp, ip, lsl sp -0+018 <[^>]*> e1a0e06f ? mov lr, pc, rrx +0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 +0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 +0+010 <[^>]*> e1a08a59 ? asr r8, r9, sl +0+014 <[^>]*> e1a0bd1c ? lsl fp, ip, sp +0+018 <[^>]*> e1a0e06f ? rrx lr, pc 0+01c <[^>]*> e1a01002 ? mov r1, r2 0+020 <[^>]*> 01a02003 ? moveq r2, r3 0+024 <[^>]*> 11a04005 ? movne r4, r5 @@ -28,13 +28,13 @@ Disassembly of section .text: 0+040 <[^>]*> 41a03006 ? movmi r3, r6 0+044 <[^>]*> 51a07009 ? movpl r7, r9 0+048 <[^>]*> 61a01008 ? movvs r1, r8 -0+04c <[^>]*> 71a09fa1 ? movvc r9, r1, lsr #31 +0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31 0+050 <[^>]*> 81a0800f ? movhi r8, pc 0+054 <[^>]*> 91a0f00e ? movls pc, lr 0+058 <[^>]*> 21a09008 ? movcs r9, r8 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 @@ -114,11 +114,11 @@ Disassembly of section .text: 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp 0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip 0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr 0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] 0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] 0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! @@ -130,7 +130,7 @@ Disassembly of section .text: 0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> 0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\] 0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] 0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] 0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! @@ -143,21 +143,21 @@ Disassembly of section .text: 0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> 0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] 0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} 0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} 0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} 0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} 0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} 0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} 0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ 0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 @@ -169,35 +169,35 @@ Disassembly of section .text: [ ]*268:.*_wibble.* 0+26c <[^>]*> da...... ? ble 0[0123456789abcdef]+ <[^>]*> [ ]*26c:.*testerfunc.* -0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 +0+270 <[^>]*> e1a01102 ? lsl r1, r2, #2 0+274 <[^>]*> e1a01002 ? mov r1, r2 -0+278 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+27c <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+280 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+284 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+288 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+28c <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+290 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+294 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+298 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+29c <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2a0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2a4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2a8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ac <[^>]*> e1a01062 ? mov r1, r2, rrx -0+2b0 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 +0+278 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+27c <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+280 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+284 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+288 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+28c <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+290 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+294 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+298 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+29c <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2a0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2a4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2a8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ac <[^>]*> e1a01062 ? rrx r1, r2 +0+2b0 <[^>]*> e1a01102 ? lsl r1, r2, #2 0+2b4 <[^>]*> e1a01002 ? mov r1, r2 -0+2b8 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+2bc <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+2c0 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+2c4 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+2c8 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+2cc <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+2d0 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+2d4 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+2d8 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+2dc <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2e0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2e4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2e8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ec <[^>]*> e1a01062 ? mov r1, r2, rrx +0+2b8 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+2bc <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+2c0 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+2c4 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+2c8 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+2cc <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+2d0 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+2d4 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+2d8 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+2dc <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2e0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2e4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2e8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ec <[^>]*> e1a01062 ? rrx r1, r2 diff --git a/gas/testsuite/gas/arm/itblock.s b/gas/testsuite/gas/arm/itblock.s new file mode 100644 index 000000000000..0fb3c198d744 --- /dev/null +++ b/gas/testsuite/gas/arm/itblock.s @@ -0,0 +1,21 @@ +# All-true IT block macro. + + .macro itblock num cond="" + .if x\cond != x + .if \num == 4 + itttt \cond + .else + .if \num == 3 + ittt \cond + .else + .if \num == 2 + itt \cond + .else + .if \num == 1 + .it \cond + .endif + .endif + .endif + .endif + .endif + .endm diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.l b/gas/testsuite/gas/arm/iwmmxt-bad.l index 65889380cf1b..d030a6da46ae 100644 --- a/gas/testsuite/gas/arm/iwmmxt-bad.l +++ b/gas/testsuite/gas/arm/iwmmxt-bad.l @@ -8,3 +8,5 @@ [^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]' [^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]' [^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1' +[^:]*:10: Error: iWMMXt data or control register expected -- `wldrw wibble,\[r1\]' +[^:]*:11: Error: iWMMXt data or control register expected -- `wstrw wibble,\[r1\]' diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.s b/gas/testsuite/gas/arm/iwmmxt-bad.s index 47d8d71f8656..98fc239374b7 100644 --- a/gas/testsuite/gas/arm/iwmmxt-bad.s +++ b/gas/testsuite/gas/arm/iwmmxt-bad.s @@ -7,3 +7,5 @@ wstrh wcgr0,[r1] wstrd wcgr0,[r1] tmcr wibble,r1 + wldrw wibble,[r1] + wstrw wibble,[r1] diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d new file mode 100644 index 000000000000..c17a1d858a10 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d @@ -0,0 +1,11 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 1 +#as: -mcpu=xscale+iwmmxt -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt> ecb11000[ ]+wldrb[ ]+wr1, \[r1\] +0+004 <[^>]*> ecf11000[ ]+wldrh[ ]+wr1, \[r1\] +0+008 <[^>]*> eca11000[ ]+wstrb[ ]+wr1, \[r1\] +0+00c <[^>]*> ece11000[ ]+wstrh[ ]+wr1, \[r1\] diff --git a/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s new file mode 100644 index 000000000000..fd58c105de50 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s @@ -0,0 +1,8 @@ + .text + .global iwmmxt +iwmmxt: + + wldrb wr1, [r1], #0 + wldrh wr1, [r1], #0 + wstrb wr1, [r1], #0 + wstrh wr1, [r1], #0 diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d index 494199d2bc45..85f4ac2e84e4 100644 --- a/gas/testsuite/gas/arm/iwmmxt.d +++ b/gas/testsuite/gas/arm/iwmmxt.d @@ -166,6 +166,6 @@ Disassembly of section .text: 0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10 0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5 0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7 -0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) -0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) +0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0 +0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2 0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s index 0ebbad5cd3c7..42bbb7ab4ceb 100644 --- a/gas/testsuite/gas/arm/iwmmxt.s +++ b/gas/testsuite/gas/arm/iwmmxt.s @@ -203,7 +203,8 @@ iwmmxt: wzeroge wr7 + tmcr wcgr0, r0 + tmrc r1, wcgr2 + @ a.out-required section size padding nop - nop - nop diff --git a/gas/testsuite/gas/arm/iwmmxt2.d b/gas/testsuite/gas/arm/iwmmxt2.d new file mode 100644 index 000000000000..7c1bbeb921e3 --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt2.d @@ -0,0 +1,119 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 2 +#as: -mcpu=xscale+iwmmxt+iwmmxt2 -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt2> ee654186[ ]+waddhc[ ]+wr4, wr5, wr6 +0+004 <[^>]*> eea87189[ ]+waddwc[ ]+wr7, wr8, wr9 +0+008 <[^>]*> ce954106[ ]+wmadduxgt[ ]+wr4, wr5, wr6 +0+00c <[^>]*> 0ec87109[ ]+wmadduneq[ ]+wr7, wr8, wr9 +0+010 <[^>]*> 1eb54106[ ]+wmaddsxne[ ]+wr4, wr5, wr6 +0+014 <[^>]*> aee87109[ ]+wmaddsnge[ ]+wr7, wr8, wr9 +0+018 <[^>]*> eed21103[ ]+wmulumr[ ]+wr1, wr2, wr3 +0+01c <[^>]*> eef21103[ ]+wmulsmr[ ]+wr1, wr2, wr3 +0+020 <[^>]*> ce13f190[ ]+torvscbgt[ ]+pc +0+024 <[^>]*> 1e53f190[ ]+torvschne[ ]+pc +0+028 <[^>]*> 0e93f190[ ]+torvscweq[ ]+pc +0+02c <[^>]*> ee2211c0[ ]+wabsb[ ]+wr1, wr2 +0+030 <[^>]*> ee6431c0[ ]+wabsh[ ]+wr3, wr4 +0+034 <[^>]*> eea651c0[ ]+wabsw[ ]+wr5, wr6 +0+038 <[^>]*> ce2211c0[ ]+wabsbgt[ ]+wr1, wr2 +0+03c <[^>]*> ee1211c3[ ]+wabsdiffb[ ]+wr1, wr2, wr3 +0+040 <[^>]*> ee5541c6[ ]+wabsdiffh[ ]+wr4, wr5, wr6 +0+044 <[^>]*> ee9871c9[ ]+wabsdiffw[ ]+wr7, wr8, wr9 +0+048 <[^>]*> ce1211c3[ ]+wabsdiffbgt[ ]+wr1, wr2, wr3 +0+04c <[^>]*> ee6211a3[ ]+waddbhusm[ ]+wr1, wr2, wr3 +0+050 <[^>]*> ee2541a6[ ]+waddbhusl[ ]+wr4, wr5, wr6 +0+054 <[^>]*> ce6211a3[ ]+waddbhusmgt[ ]+wr1, wr2, wr3 +0+058 <[^>]*> ce2541a6[ ]+waddbhuslgt[ ]+wr4, wr5, wr6 +0+05c <[^>]*> ee421003[ ]+wavg4[ ]+wr1, wr2, wr3 +0+060 <[^>]*> ce454006[ ]+wavg4gt[ ]+wr4, wr5, wr6 +0+064 <[^>]*> ee521003[ ]+wavg4r[ ]+wr1, wr2, wr3 +0+068 <[^>]*> ce554006[ ]+wavg4rgt[ ]+wr4, wr5, wr6 +0+06c <[^>]*> fc711102[ ]+wldrd[ ]+wr1, \[r1\], -r2 +0+070 <[^>]*> fc712132[ ]+wldrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+074 <[^>]*> fcf13102[ ]+wldrd[ ]+wr3, \[r1\], \+r2 +0+078 <[^>]*> fcf14142[ ]+wldrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+07c <[^>]*> fd515102[ ]+wldrd[ ]+wr5, \[r1, -r2\] +0+080 <[^>]*> fd516132[ ]+wldrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+084 <[^>]*> fdd17102[ ]+wldrd[ ]wr7, \[r1, \+r2\] +0+088 <[^>]*> fdd18142[ ]+wldrd[ ]wr8, \[r1, \+r2, lsl #4\] +0+08c <[^>]*> fd719102[ ]+wldrd[ ]wr9, \[r1, -r2\]! +0+090 <[^>]*> fd71a132[ ]+wldrd[ ]wr10, \[r1, -r2, lsl #3\]! +0+094 <[^>]*> fdf1b102[ ]+wldrd[ ]wr11, \[r1, \+r2\]! +0+098 <[^>]*> fdf1c142[ ]+wldrd[ ]wr12, \[r1, \+r2, lsl #4\]! +0+09c <[^>]*> ee821083[ ]+wmerge[ ]wr1, wr2, wr3, #4 +0+0a0 <[^>]*> ce821083[ ]+wmergegt[ ]wr1, wr2, wr3, #4 +0+0a4 <[^>]*> 0e3210a3[ ]+wmiatteq[ ]wr1, wr2, wr3 +0+0a8 <[^>]*> ce2210a3[ ]+wmiatbgt[ ]wr1, wr2, wr3 +0+0ac <[^>]*> 1e1210a3[ ]+wmiabtne[ ]wr1, wr2, wr3 +0+0b0 <[^>]*> ce0210a3[ ]+wmiabbgt[ ]wr1, wr2, wr3 +0+0b4 <[^>]*> 0e7210a3[ ]+wmiattneq[ ]wr1, wr2, wr3 +0+0b8 <[^>]*> 1e6210a3[ ]+wmiatbnne[ ]wr1, wr2, wr3 +0+0bc <[^>]*> ce5210a3[ ]+wmiabtngt[ ]wr1, wr2, wr3 +0+0c0 <[^>]*> 0e4210a3[ ]+wmiabbneq[ ]wr1, wr2, wr3 +0+0c4 <[^>]*> 0eb21123[ ]+wmiawtteq[ ]wr1, wr2, wr3 +0+0c8 <[^>]*> cea21123[ ]+wmiawtbgt[ ]wr1, wr2, wr3 +0+0cc <[^>]*> 1e921123[ ]+wmiawbtne[ ]wr1, wr2, wr3 +0+0d0 <[^>]*> ce821123[ ]+wmiawbbgt[ ]wr1, wr2, wr3 +0+0d4 <[^>]*> 1ef21123[ ]+wmiawttnne[ ]wr1, wr2, wr3 +0+0d8 <[^>]*> cee21123[ ]+wmiawtbngt[ ]wr1, wr2, wr3 +0+0dc <[^>]*> 0ed21123[ ]+wmiawbtneq[ ]wr1, wr2, wr3 +0+0e0 <[^>]*> 1ec21123[ ]+wmiawbbnne[ ]wr1, wr2, wr3 +0+0e4 <[^>]*> 0ed210c3[ ]+wmulwumeq[ ]wr1, wr2, wr3 +0+0e8 <[^>]*> cec210c3[ ]+wmulwumrgt[ ]wr1, wr2, wr3 +0+0ec <[^>]*> 1ef210c3[ ]+wmulwsmne[ ]wr1, wr2, wr3 +0+0f0 <[^>]*> 0ee210c3[ ]+wmulwsmreq[ ]wr1, wr2, wr3 +0+0f4 <[^>]*> ceb210c3[ ]+wmulwlgt[ ]wr1, wr2, wr3 +0+0f8 <[^>]*> aeb210c3[ ]+wmulwlge[ ]wr1, wr2, wr3 +0+0fc <[^>]*> 1eb210a3[ ]+wqmiattne[ ]wr1, wr2, wr3 +0+100 <[^>]*> 0ef210a3[ ]+wqmiattneq[ ]wr1, wr2, wr3 +0+104 <[^>]*> cea210a3[ ]+wqmiatbgt[ ]wr1, wr2, wr3 +0+108 <[^>]*> aee210a3[ ]+wqmiatbnge[ ]wr1, wr2, wr3 +0+10c <[^>]*> 1e9210a3[ ]+wqmiabtne[ ]wr1, wr2, wr3 +0+110 <[^>]*> 0ed210a3[ ]+wqmiabtneq[ ]wr1, wr2, wr3 +0+114 <[^>]*> ce8210a3[ ]+wqmiabbgt[ ]wr1, wr2, wr3 +0+118 <[^>]*> 1ec210a3[ ]+wqmiabbnne[ ]wr1, wr2, wr3 +0+11c <[^>]*> ce121083[ ]+wqmulmgt[ ]wr1, wr2, wr3 +0+120 <[^>]*> 0e321083[ ]+wqmulmreq[ ]wr1, wr2, wr3 +0+124 <[^>]*> cec210e3[ ]+wqmulwmgt[ ]wr1, wr2, wr3 +0+128 <[^>]*> 0ee210e3[ ]+wqmulwmreq[ ]wr1, wr2, wr3 +0+12c <[^>]*> fc611102[ ]+wstrd[ ]+wr1, \[r1\], -r2 +0+130 <[^>]*> fc612132[ ]+wstrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+134 <[^>]*> fce13102[ ]+wstrd[ ]+wr3, \[r1\], \+r2 +0+138 <[^>]*> fce14142[ ]+wstrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+13c <[^>]*> fd415102[ ]+wstrd[ ]+wr5, \[r1, -r2\] +0+140 <[^>]*> fd416132[ ]+wstrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+144 <[^>]*> fdc17102[ ]+wstrd[ ]wr7, \[r1, \+r2\] +0+148 <[^>]*> fdc18142[ ]+wstrd[ ]wr8, \[r1, \+r2, lsl #4\] +0+14c <[^>]*> fd619102[ ]+wstrd[ ]wr9, \[r1, -r2\]! +0+150 <[^>]*> fd61a132[ ]+wstrd[ ]wr10, \[r1, -r2, lsl #3\]! +0+154 <[^>]*> fde1b102[ ]+wstrd[ ]wr11, \[r1, \+r2\]! +0+158 <[^>]*> fde1c142[ ]+wstrd[ ]wr12, \[r1, \+r2, lsl #4\]! +0+15c <[^>]*> ced211c3[ ]+wsubaddhxgt[ ]wr1, wr2, wr3 +0+160 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+164 <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+168 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+16c <[^>]*> fe721145[ ]+wrorh[ ]wr1, wr2, #21 +0+170 <[^>]*> feb2104d[ ]+wrorw[ ]wr1, wr2, #13 +0+174 <[^>]*> fef2104e[ ]+wrord[ ]wr1, wr2, #14 +0+178 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+17c <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+180 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+184 <[^>]*> fe59204b[ ]+wsllh[ ]wr2, wr9, #11 +0+188 <[^>]*> fe95304d[ ]+wsllw[ ]wr3, wr5, #13 +0+18c <[^>]*> fed8304f[ ]+wslld[ ]wr3, wr8, #15 +0+190 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+194 <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+198 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+19c <[^>]*> fe49204c[ ]+wsrah[ ]wr2, wr9, #12 +0+1a0 <[^>]*> fe85304e[ ]+wsraw[ ]wr3, wr5, #14 +0+1a4 <[^>]*> fec83140[ ]+wsrad[ ]wr3, wr8, #16 +0+1a8 <[^>]*> fe721140[ ]+wrorh[ ]wr1, wr2, #16 +0+1ac <[^>]*> feb21040[ ]+wrorw[ ]wr1, wr2, #32 +0+1b0 <[^>]*> ee021002[ ]+wor[ ]wr1, wr2, wr2 +0+1b4 <[^>]*> fe69204c[ ]+wsrlh[ ]wr2, wr9, #12 +0+1b8 <[^>]*> fea5304e[ ]+wsrlw[ ]wr3, wr5, #14 +0+1bc <[^>]*> fee83140[ ]+wsrld[ ]wr3, wr8, #16 diff --git a/gas/testsuite/gas/arm/iwmmxt2.s b/gas/testsuite/gas/arm/iwmmxt2.s new file mode 100644 index 000000000000..314f64f11e0b --- /dev/null +++ b/gas/testsuite/gas/arm/iwmmxt2.s @@ -0,0 +1,137 @@ + .text + .global iwmmxt2 +iwmmxt2: + + waddhc wr4, wr5, wr6 + waddwc wr7, wr8, wr9 + + wmadduxgt wr4, wr5, wr6 + wmadduneq wr7, wr8, wr9 + wmaddsxne wr4, wr5, wr6 + wmaddsnge wr7, wr8, wr9 + + wmulumr wr1, wr2, wr3 + wmulsmr wr1, wr2, wr3 + + torvscbgt r15 + torvschne r15 + torvscweq r15 + + wabsb wr1, wr2 + wabsh wr3, wr4 + wabsw wr5, wr6 + wabsbgt wr1, wr2 + + wabsdiffb wr1, wr2, wr3 + wabsdiffh wr4, wr5, wr6 + wabsdiffw wr7, wr8, wr9 + wabsdiffbgt wr1, wr2, wr3 + + waddbhusm wr1, wr2, wr3 + waddbhusl wr4, wr5, wr6 + waddbhusmgt wr1, wr2, wr3 + waddbhuslgt wr4, wr5, wr6 + + wavg4 wr1, wr2, wr3 + wavg4gt wr4, wr5, wr6 + wavg4r wr1, wr2, wr3 + wavg4rgt wr4, wr5, wr6 + + wldrd wr1, [r1], -r2 + wldrd wr2, [r1], -r2,lsl #3 + wldrd wr3, [r1], +r2 + wldrd wr4, [r1], +r2,lsl #4 + wldrd wr5, [r1, -r2] + wldrd wr6, [r1, -r2,lsl #3] + wldrd wr7, [r1, +r2] + wldrd wr8, [r1, +r2,lsl #4] + wldrd wr9, [r1, -r2]! + wldrd wr10, [r1, -r2,lsl #3]! + wldrd wr11, [r1, +r2]! + wldrd wr12, [r1, +r2,lsl #4]! + + wmerge wr1, wr2, wr3, #4 + wmergegt wr1, wr2, wr3, #4 + + wmiatteq wr1, wr2, wr3 + wmiatbgt wr1, wr2, wr3 + wmiabtne wr1, wr2, wr3 + wmiabbgt wr1, wr2, wr3 + wmiattneq wr1, wr2, wr3 + wmiatbnne wr1, wr2, wr3 + wmiabtngt wr1, wr2, wr3 + wmiabbneq wr1, wr2, wr3 + + wmiawtteq wr1, wr2, wr3 + wmiawtbgt wr1, wr2, wr3 + wmiawbtne wr1, wr2, wr3 + wmiawbbgt wr1, wr2, wr3 + wmiawttnne wr1, wr2, wr3 + wmiawtbngt wr1, wr2, wr3 + wmiawbtneq wr1, wr2, wr3 + wmiawbbnne wr1, wr2, wr3 + + wmulwumeq wr1, wr2, wr3 + wmulwumrgt wr1, wr2, wr3 + wmulwsmne wr1, wr2, wr3 + wmulwsmreq wr1, wr2, wr3 + wmulwlgt wr1, wr2, wr3 + wmulwlge wr1, wr2, wr3 + + wqmiattne wr1, wr2, wr3 + wqmiattneq wr1, wr2, wr3 + wqmiatbgt wr1, wr2, wr3 + wqmiatbnge wr1, wr2, wr3 + wqmiabtne wr1, wr2, wr3 + wqmiabtneq wr1, wr2, wr3 + wqmiabbgt wr1, wr2, wr3 + wqmiabbnne wr1, wr2, wr3 + + wqmulmgt wr1, wr2, wr3 + wqmulmreq wr1, wr2, wr3 + + wqmulwmgt wr1, wr2, wr3 + wqmulwmreq wr1, wr2, wr3 + + wstrd wr1, [r1], -r2 + wstrd wr2, [r1], -r2,lsl #3 + wstrd wr3, [r1], +r2 + wstrd wr4, [r1], +r2,lsl #4 + wstrd wr5, [r1, -r2] + wstrd wr6, [r1, -r2,lsl #3] + wstrd wr7, [r1, +r2] + wstrd wr8, [r1, +r2,lsl #4] + wstrd wr9, [r1, -r2]! + wstrd wr10, [r1, -r2,lsl #3]! + wstrd wr11, [r1, +r2]! + wstrd wr12, [r1, +r2,lsl #4]! + + wsubaddhxgt wr1, wr2, wr3 + + wrorh wr1, wr2, #0 + wrorw wr1, wr2, #0 + wrord wr1, wr2, #0 + wrorh wr1, wr2, #21 + wrorw wr1, wr2, #13 + wrord wr1, wr2, #14 + + wsllh wr1, wr2, #0 + wsllw wr1, wr2, #0 + wslld wr1, wr2, #0 + wsllh wr2, wr9, #11 + wsllw wr3, wr5, #13 + wslld wr3, wr8, #15 + + wsrah wr1, wr2, #0 + wsraw wr1, wr2, #0 + wsrad wr1, wr2, #0 + wsrah wr2, wr9, #12 + wsraw wr3, wr5, #14 + wsrad wr3, wr8, #16 + + wsrlh wr1, wr2, #0 + wsrlw wr1, wr2, #0 + wsrld wr1, wr2, #0 + wsrlh wr2, wr9, #12 + wsrlw wr3, wr5, #14 + wsrld wr3, wr8, #16 diff --git a/gas/testsuite/gas/arm/local_function.d b/gas/testsuite/gas/arm/local_function.d new file mode 100644 index 000000000000..46da8eceb6c7 --- /dev/null +++ b/gas/testsuite/gas/arm/local_function.d @@ -0,0 +1,10 @@ +#objdump: -r +#name: Relocations agains local function symbols +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000000 R_ARM_(CALL|PC24) bar diff --git a/gas/testsuite/gas/arm/local_function.s b/gas/testsuite/gas/arm/local_function.s new file mode 100644 index 000000000000..1d98a37425cc --- /dev/null +++ b/gas/testsuite/gas/arm/local_function.s @@ -0,0 +1,10 @@ + .text + .type foo, %function +foo: + bl bar + + .section .text.bar + nop + .type bar, %function +bar: + nop diff --git a/gas/testsuite/gas/arm/local_label_coff.d b/gas/testsuite/gas/arm/local_label_coff.d new file mode 100644 index 000000000000..5e45ac8c479c --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_coff.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (COFF) +# This test is only valid on COFF based targets, except Windows CE. +# There are ELF and Windows CE versions of this test. +#not-skip: *-unknown-pe *-epoc-pe *-*-*coff + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/gas/testsuite/gas/arm/local_label_coff.s b/gas/testsuite/gas/arm/local_label_coff.s new file mode 100644 index 000000000000..985f568ac3f0 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_coff.s @@ -0,0 +1,3 @@ + .text +Lused_label: + .word Lused_label diff --git a/gas/testsuite/gas/arm/local_label_elf.d b/gas/testsuite/gas/arm/local_label_elf.d new file mode 100644 index 000000000000..d4a8c8ea73f7 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_elf.d @@ -0,0 +1,9 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (ELF) +# This test is only valid on ELF targets. +# There are COFF and Windows CE versions of this test. +#skip: *-*-*coff *-*-pe *-wince-* *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. + diff --git a/gas/testsuite/gas/arm/local_label_elf.s b/gas/testsuite/gas/arm/local_label_elf.s new file mode 100644 index 000000000000..e9f5467d4122 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_elf.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/gas/testsuite/gas/arm/local_label_wince.d b/gas/testsuite/gas/arm/local_label_wince.d new file mode 100644 index 000000000000..97fc58aea824 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_wince.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (WinCE) +# This test is only valid on Windows CE. +# There are ELF and COFF versions of this test. +#not-skip: *-*-wince *-wince-* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/gas/testsuite/gas/arm/local_label_wince.s b/gas/testsuite/gas/arm/local_label_wince.s new file mode 100644 index 000000000000..e9f5467d4122 --- /dev/null +++ b/gas/testsuite/gas/arm/local_label_wince.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d index 2384594fc545..c29bb626156e 100644 --- a/gas/testsuite/gas/arm/macro1.d +++ b/gas/testsuite/gas/arm/macro1.d @@ -6,7 +6,7 @@ Disassembly of section .text: -0+0 <[^>]*> e8bd8030 ? ldmia sp!, {r4, r5, pc} +0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc} 0+4 <[^>]*> e1a00000 ? nop \(mov r0,r0\) 0+8 <[^>]*> e1a00000 ? nop \(mov r0,r0\) 0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/mapshort-eabi.d b/gas/testsuite/gas/arm/mapshort-eabi.d new file mode 100644 index 000000000000..9cbfc3eacd4a --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort-eabi.d @@ -0,0 +1,45 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (EABI version) +# This test is only valid on EABI based ports. +#target: *-*-*eabi *-*-symbianelf +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l .data 00000000 \$d +0+00 l d .ARM.attributes 00000000 .ARM.attributes + + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop \(mov r0,r0\) + 4: 46c0 nop \(mov r8, r8\) + 6: 46c0 nop \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop \(mov r8, r8\) + 14: 46c0 nop \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/gas/testsuite/gas/arm/mapshort-elf.d b/gas/testsuite/gas/arm/mapshort-elf.d new file mode 100644 index 000000000000..09602f08091e --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort-elf.d @@ -0,0 +1,44 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (ELF version) +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi *-*-syymbianelf +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l .data 00000000 \$d +# The ELF based port does not generate a .ARM.attributes symbol + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop \(mov r0,r0\) + 4: 46c0 nop \(mov r8, r8\) + 6: 46c0 nop \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop \(mov r8, r8\) + 14: 46c0 nop \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/gas/testsuite/gas/arm/mapshort.s b/gas/testsuite/gas/arm/mapshort.s new file mode 100644 index 000000000000..741cb8251053 --- /dev/null +++ b/gas/testsuite/gas/arm/mapshort.s @@ -0,0 +1,24 @@ + .text + .type foo, %function +foo: + .code 32 + nop + .code 16 + nop + nop + .long 2 + .short 1 + .short 1 + .short 3 + nop + nop + .short 1 + .code 32 + bl foo + .short 8 + .byte 9 +bar: + .byte 10 + .data +wibble: + .word 0 diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.d b/gas/testsuite/gas/arm/mul-overlap-v6.d new file mode 100644 index 000000000000..ff42190a5d0d --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap-v6.d @@ -0,0 +1,10 @@ +# name: Overlapping multiplication operands for ARMv6 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e0000090 mul r0, r0, r0 +0[0-9a-f]+ <[^>]+> e0202190 mla r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e0602190 mls r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e12fff1e bx lr diff --git a/gas/testsuite/gas/arm/mul-overlap-v6.s b/gas/testsuite/gas/arm/mul-overlap-v6.s new file mode 100644 index 000000000000..f35c124ae39f --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap-v6.s @@ -0,0 +1,9 @@ + .arch armv6t2 + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + bx lr diff --git a/gas/testsuite/gas/arm/mul-overlap.d b/gas/testsuite/gas/arm/mul-overlap.d new file mode 100644 index 000000000000..53406e3f413b --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.d @@ -0,0 +1,2 @@ +# name: Overlapping multiplication operands without architecture specification +# error-output: mul-overlap.l diff --git a/gas/testsuite/gas/arm/mul-overlap.l b/gas/testsuite/gas/arm/mul-overlap.l new file mode 100644 index 000000000000..a895c0102a3f --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:5: Rd and Rm should be different in mul +[^:]*:6: Rd and Rm should be different in mla diff --git a/gas/testsuite/gas/arm/mul-overlap.s b/gas/testsuite/gas/arm/mul-overlap.s new file mode 100644 index 000000000000..6932eaeb13fe --- /dev/null +++ b/gas/testsuite/gas/arm/mul-overlap.s @@ -0,0 +1,8 @@ + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + bx lr diff --git a/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/gas/testsuite/gas/arm/neon-cond-bad-inc.s new file mode 100644 index 000000000000..a92d19675e1c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad-inc.s @@ -0,0 +1,57 @@ +# Check for illegal conditional Neon instructions in ARM mode. The instructions +# which overlap with VFP are the tricky cases, so test those. + + .include "itblock.s" + + .syntax unified + .text +func: + itblock 4 eq + vmoveq q0,q1 + vmoveq d0,d1 + vmoveq.i32 q0,#0 + vmoveq.i32 d0,#0 + @ Following four *can* be conditional. + itblock 4 eq + vmoveq.32 d0[1], r2 + vmoveq d0,r1,r2 + vmoveq.32 r2,d1[0] + vmoveq r0,r1,d2 + + .macro dyadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1,d2 + \op\eq\f32 q0,q1,q2 + .endm + + dyadic_eq vmul + dyadic_eq vmla + dyadic_eq vmls + dyadic_eq vadd + dyadic_eq vsub + + .macro monadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1 + \op\eq\f32 q0,q1 + .endm + + monadic_eq vabs + monadic_eq vneg + + .macro cvt to from dot="." + itblock 2 eq + vcvteq\dot\to\dot\from d0,d1 + vcvteq\dot\to\dot\from q0,q1 + .endm + + cvt s32 f32 + cvt u32 f32 + cvt f32 s32 + cvt f32 u32 + + itblock 4 eq + vdupeq.32 d0,r1 + vdupeq.32 q0,r1 + vdupeq.32 d0,d1[0] + vdupeq.32 q0,d1[1] diff --git a/gas/testsuite/gas/arm/neon-cond-bad.d b/gas/testsuite/gas/arm/neon-cond-bad.d new file mode 100644 index 000000000000..105ba4d7f26e --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.d @@ -0,0 +1,3 @@ +# name: Illegal conditions in Neon instructions, ARM mode +# as: -mfpu=neon -I$srcdir/$subdir +# error-output: neon-cond-bad.l diff --git a/gas/testsuite/gas/arm/neon-cond-bad.l b/gas/testsuite/gas/arm/neon-cond-bad.l new file mode 100644 index 000000000000..a79f79d64f83 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1' +[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1' +[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0' +[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1' +[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]' +[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]' diff --git a/gas/testsuite/gas/arm/neon-cond-bad.s b/gas/testsuite/gas/arm/neon-cond-bad.s new file mode 100644 index 000000000000..16afd8635e91 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad.s @@ -0,0 +1,2 @@ + .arm + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/gas/testsuite/gas/arm/neon-cond-bad_t2.d new file mode 100644 index 000000000000..517caa758ee4 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.d @@ -0,0 +1,55 @@ +# name: Conditions in Neon instructions, Thumb mode (illegal in ARM). +# as: -mfpu=neon -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1 +0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1 +0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2 +0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2 +0[0-9a-f]+ <[^>]+> ee11 2b10 vmoveq\.32 r2, d1\[0\] +0[0-9a-f]+ <[^>]+> ec51 0b12 vmoveq r0, r1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0701 vabseq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 0742 vabseq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0781 vnegeq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 07c2 vnegeq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0701 vcvteq\.s32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0742 vcvteq\.s32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0781 vcvteq\.u32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 07c2 vcvteq\.u32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0601 vcvteq\.f32\.s32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0642 vcvteq\.f32\.s32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0681 vcvteq\.f32\.u32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 06c2 vcvteq\.f32\.u32 q0, q1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee80 1b10 vdupeq\.32 d0, r1 +0[0-9a-f]+ <[^>]+> eea0 1b10 vdupeq\.32 q0, r1 +0[0-9a-f]+ <[^>]+> ffb4 0c01 vdupeq\.32 d0, d1\[0\] +0[0-9a-f]+ <[^>]+> ffbc 0c41 vdupeq\.32 q0, d1\[1\] diff --git a/gas/testsuite/gas/arm/neon-cond-bad_t2.s b/gas/testsuite/gas/arm/neon-cond-bad_t2.s new file mode 100644 index 000000000000..2655d11a049d --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond-bad_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "neon-cond-bad-inc.s" diff --git a/gas/testsuite/gas/arm/neon-cond.d b/gas/testsuite/gas/arm/neon-cond.d new file mode 100644 index 000000000000..0b7d8ede73b6 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond.d @@ -0,0 +1,14 @@ +# name: Conditional Neon instructions +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> 0d943b00 vldreq d3, \[r4\] +0[0-9a-f]+ <[^>]+> be035b70 vmovlt\.16 d3\[1\], r5 +0[0-9a-f]+ <[^>]+> ac474b13 vmovge d3, r4, r7 +0[0-9a-f]+ <[^>]+> 3c543b3e vmovcc r3, r4, d30 +0[0-9a-f]+ <[^>]+> 1e223b10 vmovne\.32 d2\[1\], r3 +0[0-9a-f]+ <[^>]+> 2c521b13 vmovcs r1, r2, d3 +0[0-9a-f]+ <[^>]+> 3c421b14 vmovcc d4, r1, r2 diff --git a/gas/testsuite/gas/arm/neon-cond.s b/gas/testsuite/gas/arm/neon-cond.s new file mode 100644 index 000000000000..8f62575aa5e5 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cond.s @@ -0,0 +1,13 @@ +@ test conditional compilation + + .arm + .text + .syntax unified + + vldreq.32 d3,[r4] + vmovlt.16 d3[1], r5 + vmovge d3, r4, r7 + vmovcc r3, r4, d30 + vmovne.32 d2[1],r3 + vmovcs r1,r2,d3 + vmovcc d4,r1,r2 diff --git a/gas/testsuite/gas/arm/neon-const.d b/gas/testsuite/gas/arm/neon-const.d new file mode 100644 index 000000000000..a1bc97cf381f --- /dev/null +++ b/gas/testsuite/gas/arm/neon-const.d @@ -0,0 +1,265 @@ +# name: Neon floating-point constants +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000 +0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000 +0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000 +0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000 +0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000 +0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000 +0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000 +0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000 +0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000 +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 ; 0x41080000 +0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 ; 0x41880000 +0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 ; 0x3e080000 +0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 ; 0x3e880000 +0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 ; 0x3f080000 +0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 ; 0x3f880000 +0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 ; 0x40100000 +0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 ; 0x40900000 +0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 ; 0x41100000 +0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 ; 0x41900000 +0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 ; 0x3e100000 +0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 ; 0x3e900000 +0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 ; 0x3f100000 +0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 ; 0x3f900000 +0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 ; 0x40180000 +0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 ; 0x40980000 +0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 ; 0x41180000 +0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 ; 0x41980000 +0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 ; 0x3e180000 +0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 ; 0x3e980000 +0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 ; 0x3f180000 +0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 ; 0x3f980000 +0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 ; 0x40200000 +0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 ; 0x40a00000 +0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 ; 0x41200000 +0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 ; 0x41a00000 +0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 ; 0x3e200000 +0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 ; 0x3ea00000 +0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 ; 0x3f200000 +0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 ; 0x3fa00000 +0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 ; 0x40280000 +0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 ; 0x40a80000 +0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 ; 0x41280000 +0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 ; 0x41a80000 +0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 ; 0x3e280000 +0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 ; 0x3ea80000 +0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 ; 0x3f280000 +0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 ; 0x3fa80000 +0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 ; 0x40300000 +0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 ; 0x40b00000 +0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 ; 0x41300000 +0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 ; 0x41b00000 +0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 ; 0x3e300000 +0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 ; 0x3eb00000 +0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 ; 0x3f300000 +0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 ; 0x3fb00000 +0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 ; 0x40380000 +0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 ; 0x40b80000 +0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 ; 0x41380000 +0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 ; 0x41b80000 +0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 ; 0x3e380000 +0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 ; 0x3eb80000 +0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 ; 0x3f380000 +0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 ; 0x3fb80000 +0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 ; 0x40400000 +0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 ; 0x40c00000 +0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 ; 0x41400000 +0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 ; 0x41c00000 +0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 ; 0x3e400000 +0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 ; 0x3ec00000 +0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 ; 0x3f400000 +0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 ; 0x3fc00000 +0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 ; 0x40480000 +0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 ; 0x40c80000 +0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 ; 0x41480000 +0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 ; 0x41c80000 +0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 ; 0x3e480000 +0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 ; 0x3ec80000 +0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 ; 0x3f480000 +0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 ; 0x3fc80000 +0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 ; 0x40500000 +0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 ; 0x40d00000 +0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 ; 0x41500000 +0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 ; 0x41d00000 +0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 ; 0x3e500000 +0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 ; 0x3ed00000 +0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 ; 0x3f500000 +0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 ; 0x3fd00000 +0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 ; 0x40580000 +0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 ; 0x40d80000 +0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 ; 0x41580000 +0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 ; 0x41d80000 +0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 ; 0x3e580000 +0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 ; 0x3ed80000 +0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 ; 0x3f580000 +0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 ; 0x3fd80000 +0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 ; 0x40600000 +0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 ; 0x40e00000 +0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 ; 0x41600000 +0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 ; 0x41e00000 +0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 ; 0x3e600000 +0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 ; 0x3ee00000 +0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 ; 0x3f600000 +0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 ; 0x3fe00000 +0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 ; 0x40680000 +0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 ; 0x40e80000 +0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 ; 0x41680000 +0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 ; 0x41e80000 +0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 ; 0x3e680000 +0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 ; 0x3ee80000 +0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 ; 0x3f680000 +0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 ; 0x3fe80000 +0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 ; 0x40700000 +0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 ; 0x40f00000 +0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 ; 0x41700000 +0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 ; 0x41f00000 +0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 ; 0x3e700000 +0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 ; 0x3ef00000 +0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 ; 0x3f700000 +0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 ; 0x3ff00000 +0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 ; 0x40780000 +0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 ; 0x40f80000 +0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 ; 0x41780000 +0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 ; 0x41f80000 +0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 ; 0x3e780000 +0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 ; 0x3ef80000 +0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 ; 0x3f780000 +0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 ; 0x3ff80000 +0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 ; 0x80000000 +0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 ; 0xc0000000 +0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 ; 0xc0800000 +0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 ; 0xc1000000 +0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 ; 0xc1800000 +0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 ; 0xbe000000 +0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 ; 0xbe800000 +0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 ; 0xbf000000 +0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 ; 0xbf800000 +0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 ; 0xc0080000 +0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 ; 0xc0880000 +0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 ; 0xc1080000 +0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 ; 0xc1880000 +0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 ; 0xbe080000 +0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 ; 0xbe880000 +0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 ; 0xbf080000 +0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 ; 0xbf880000 +0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 ; 0xc0100000 +0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 ; 0xc0900000 +0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 ; 0xc1100000 +0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 ; 0xc1900000 +0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 ; 0xbe100000 +0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 ; 0xbe900000 +0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 ; 0xbf100000 +0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 ; 0xbf900000 +0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 ; 0xc0180000 +0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 ; 0xc0980000 +0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 ; 0xc1180000 +0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 ; 0xc1980000 +0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 ; 0xbe180000 +0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 ; 0xbe980000 +0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 ; 0xbf180000 +0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 ; 0xbf980000 +0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 ; 0xc0200000 +0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 ; 0xc0a00000 +0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 ; 0xc1200000 +0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 ; 0xc1a00000 +0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 ; 0xbe200000 +0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 ; 0xbea00000 +0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 ; 0xbf200000 +0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 ; 0xbfa00000 +0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 ; 0xc0280000 +0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 ; 0xc0a80000 +0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 ; 0xc1280000 +0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 ; 0xc1a80000 +0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 ; 0xbe280000 +0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 ; 0xbea80000 +0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 ; 0xbf280000 +0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 ; 0xbfa80000 +0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 ; 0xc0300000 +0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 ; 0xc0b00000 +0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 ; 0xc1300000 +0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 ; 0xc1b00000 +0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 ; 0xbe300000 +0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 ; 0xbeb00000 +0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 ; 0xbf300000 +0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 ; 0xbfb00000 +0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 ; 0xc0380000 +0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 ; 0xc0b80000 +0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 ; 0xc1380000 +0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 ; 0xc1b80000 +0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 ; 0xbe380000 +0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 ; 0xbeb80000 +0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 ; 0xbf380000 +0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 ; 0xbfb80000 +0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 ; 0xc0400000 +0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 ; 0xc0c00000 +0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 ; 0xc1400000 +0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 ; 0xc1c00000 +0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 ; 0xbe400000 +0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 ; 0xbec00000 +0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 ; 0xbf400000 +0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 ; 0xbfc00000 +0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 ; 0xc0480000 +0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 ; 0xc0c80000 +0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 ; 0xc1480000 +0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 ; 0xc1c80000 +0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 ; 0xbe480000 +0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 ; 0xbec80000 +0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 ; 0xbf480000 +0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 ; 0xbfc80000 +0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 ; 0xc0500000 +0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 ; 0xc0d00000 +0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 ; 0xc1500000 +0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 ; 0xc1d00000 +0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 ; 0xbe500000 +0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 ; 0xbed00000 +0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 ; 0xbf500000 +0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 ; 0xbfd00000 +0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 ; 0xc0580000 +0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 ; 0xc0d80000 +0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 ; 0xc1580000 +0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 ; 0xc1d80000 +0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 ; 0xbe580000 +0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 ; 0xbed80000 +0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 ; 0xbf580000 +0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 ; 0xbfd80000 +0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 ; 0xc0600000 +0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 ; 0xc0e00000 +0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 ; 0xc1600000 +0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 ; 0xc1e00000 +0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 ; 0xbe600000 +0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 ; 0xbee00000 +0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 ; 0xbf600000 +0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 ; 0xbfe00000 +0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 ; 0xc0680000 +0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 ; 0xc0e80000 +0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 ; 0xc1680000 +0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 ; 0xc1e80000 +0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 ; 0xbe680000 +0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 ; 0xbee80000 +0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 ; 0xbf680000 +0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 ; 0xbfe80000 +0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 ; 0xc0700000 +0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 ; 0xc0f00000 +0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 ; 0xc1700000 +0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 ; 0xc1f00000 +0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 ; 0xbe700000 +0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 ; 0xbef00000 +0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 ; 0xbf700000 +0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 ; 0xbff00000 +0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 ; 0xc0780000 +0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 ; 0xc0f80000 +0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 ; 0xc1780000 +0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 ; 0xc1f80000 +0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 ; 0xbe780000 +0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 ; 0xbef80000 +0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 ; 0xbf780000 +0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 ; 0xbff80000 diff --git a/gas/testsuite/gas/arm/neon-const.s b/gas/testsuite/gas/arm/neon-const.s new file mode 100644 index 000000000000..a6fb55075a93 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-const.s @@ -0,0 +1,297 @@ +@ test floating-point constant parsing. + + .arm + .text + .syntax unified + + vmov.f32 q0, 0.0 + + vmov.f32 q0, 2.0 + vmov.f32 q0, 4.0 + vmov.f32 q0, 8.0 + vmov.f32 q0, 16.0 + vmov.f32 q0, 0.125 + vmov.f32 q0, 0.25 + vmov.f32 q0, 0.5 + vmov.f32 q0, 1.0 + + vmov.f32 q0, 2.125 + vmov.f32 q0, 4.25 + vmov.f32 q0, 8.5 + vmov.f32 q0, 17.0 + vmov.f32 q0, 0.1328125 + vmov.f32 q0, 0.265625 + vmov.f32 q0, 0.53125 + vmov.f32 q0, 1.0625 + + vmov.f32 q0, 2.25 + vmov.f32 q0, 4.5 + vmov.f32 q0, 9.0 + vmov.f32 q0, 18.0 + vmov.f32 q0, 0.140625 + vmov.f32 q0, 0.28125 + vmov.f32 q0, 0.5625 + vmov.f32 q0, 1.125 + + vmov.f32 q0, 2.375 + vmov.f32 q0, 4.75 + vmov.f32 q0, 9.5 + vmov.f32 q0, 19.0 + vmov.f32 q0, 0.1484375 + vmov.f32 q0, 0.296875 + vmov.f32 q0, 0.59375 + vmov.f32 q0, 1.1875 + + vmov.f32 q0, 2.5 + vmov.f32 q0, 5.0 + vmov.f32 q0, 10.0 + vmov.f32 q0, 20.0 + vmov.f32 q0, 0.15625 + vmov.f32 q0, 0.3125 + vmov.f32 q0, 0.625 + vmov.f32 q0, 1.25 + + vmov.f32 q0, 2.625 + vmov.f32 q0, 5.25 + vmov.f32 q0, 10.5 + vmov.f32 q0, 21.0 + vmov.f32 q0, 0.1640625 + vmov.f32 q0, 0.328125 + vmov.f32 q0, 0.65625 + vmov.f32 q0, 1.3125 + + vmov.f32 q0, 2.75 + vmov.f32 q0, 5.5 + vmov.f32 q0, 11.0 + vmov.f32 q0, 22.0 + vmov.f32 q0, 0.171875 + vmov.f32 q0, 0.34375 + vmov.f32 q0, 0.6875 + vmov.f32 q0, 1.375 + + vmov.f32 q0, 2.875 + vmov.f32 q0, 5.75 + vmov.f32 q0, 11.5 + vmov.f32 q0, 23.0 + vmov.f32 q0, 0.1796875 + vmov.f32 q0, 0.359375 + vmov.f32 q0, 0.71875 + vmov.f32 q0, 1.4375 + + vmov.f32 q0, 3.0 + vmov.f32 q0, 6.0 + vmov.f32 q0, 12.0 + vmov.f32 q0, 24.0 + vmov.f32 q0, 0.1875 + vmov.f32 q0, 0.375 + vmov.f32 q0, 0.75 + vmov.f32 q0, 1.5 + + vmov.f32 q0, 3.125 + vmov.f32 q0, 6.25 + vmov.f32 q0, 12.5 + vmov.f32 q0, 25.0 + vmov.f32 q0, 0.1953125 + vmov.f32 q0, 0.390625 + vmov.f32 q0, 0.78125 + vmov.f32 q0, 1.5625 + + vmov.f32 q0, 3.25 + vmov.f32 q0, 6.5 + vmov.f32 q0, 13.0 + vmov.f32 q0, 26.0 + vmov.f32 q0, 0.203125 + vmov.f32 q0, 0.40625 + vmov.f32 q0, 0.8125 + vmov.f32 q0, 1.625 + + vmov.f32 q0, 3.375 + vmov.f32 q0, 6.75 + vmov.f32 q0, 13.5 + vmov.f32 q0, 27.0 + vmov.f32 q0, 0.2109375 + vmov.f32 q0, 0.421875 + vmov.f32 q0, 0.84375 + vmov.f32 q0, 1.6875 + + vmov.f32 q0, 3.5 + vmov.f32 q0, 7.0 + vmov.f32 q0, 14.0 + vmov.f32 q0, 28.0 + vmov.f32 q0, 0.21875 + vmov.f32 q0, 0.4375 + vmov.f32 q0, 0.875 + vmov.f32 q0, 1.75 + + vmov.f32 q0, 3.625 + vmov.f32 q0, 7.25 + vmov.f32 q0, 14.5 + vmov.f32 q0, 29.0 + vmov.f32 q0, 0.2265625 + vmov.f32 q0, 0.453125 + vmov.f32 q0, 0.90625 + vmov.f32 q0, 1.8125 + + vmov.f32 q0, 3.75 + vmov.f32 q0, 7.5 + vmov.f32 q0, 15.0 + vmov.f32 q0, 30.0 + vmov.f32 q0, 0.234375 + vmov.f32 q0, 0.46875 + vmov.f32 q0, 0.9375 + vmov.f32 q0, 1.875 + + vmov.f32 q0, 3.875 + vmov.f32 q0, 7.75 + vmov.f32 q0, 15.5 + vmov.f32 q0, 31.0 + vmov.f32 q0, 0.2421875 + vmov.f32 q0, 0.484375 + vmov.f32 q0, 0.96875 + vmov.f32 q0, 1.9375 + + vmov.f32 q0, -0.0 + + vmov.f32 q0, -2.0 + vmov.f32 q0, -4.0 + vmov.f32 q0, -8.0 + vmov.f32 q0, -16.0 + vmov.f32 q0, -0.125 + vmov.f32 q0, -0.25 + vmov.f32 q0, -0.5 + vmov.f32 q0, -1.0 + + vmov.f32 q0, -2.125 + vmov.f32 q0, -4.25 + vmov.f32 q0, -8.5 + vmov.f32 q0, -17.0 + vmov.f32 q0, -0.1328125 + vmov.f32 q0, -0.265625 + vmov.f32 q0, -0.53125 + vmov.f32 q0, -1.0625 + + vmov.f32 q0, -2.25 + vmov.f32 q0, -4.5 + vmov.f32 q0, -9.0 + vmov.f32 q0, -18.0 + vmov.f32 q0, -0.140625 + vmov.f32 q0, -0.28125 + vmov.f32 q0, -0.5625 + vmov.f32 q0, -1.125 + + vmov.f32 q0, -2.375 + vmov.f32 q0, -4.75 + vmov.f32 q0, -9.5 + vmov.f32 q0, -19.0 + vmov.f32 q0, -0.1484375 + vmov.f32 q0, -0.296875 + vmov.f32 q0, -0.59375 + vmov.f32 q0, -1.1875 + + vmov.f32 q0, -2.5 + vmov.f32 q0, -5.0 + vmov.f32 q0, -10.0 + vmov.f32 q0, -20.0 + vmov.f32 q0, -0.15625 + vmov.f32 q0, -0.3125 + vmov.f32 q0, -0.625 + vmov.f32 q0, -1.25 + + vmov.f32 q0, -2.625 + vmov.f32 q0, -5.25 + vmov.f32 q0, -10.5 + vmov.f32 q0, -21.0 + vmov.f32 q0, -0.1640625 + vmov.f32 q0, -0.328125 + vmov.f32 q0, -0.65625 + vmov.f32 q0, -1.3125 + + vmov.f32 q0, -2.75 + vmov.f32 q0, -5.5 + vmov.f32 q0, -11.0 + vmov.f32 q0, -22.0 + vmov.f32 q0, -0.171875 + vmov.f32 q0, -0.34375 + vmov.f32 q0, -0.6875 + vmov.f32 q0, -1.375 + + vmov.f32 q0, -2.875 + vmov.f32 q0, -5.75 + vmov.f32 q0, -11.5 + vmov.f32 q0, -23.0 + vmov.f32 q0, -0.1796875 + vmov.f32 q0, -0.359375 + vmov.f32 q0, -0.71875 + vmov.f32 q0, -1.4375 + + vmov.f32 q0, -3.0 + vmov.f32 q0, -6.0 + vmov.f32 q0, -12.0 + vmov.f32 q0, -24.0 + vmov.f32 q0, -0.1875 + vmov.f32 q0, -0.375 + vmov.f32 q0, -0.75 + vmov.f32 q0, -1.5 + + vmov.f32 q0, -3.125 + vmov.f32 q0, -6.25 + vmov.f32 q0, -12.5 + vmov.f32 q0, -25.0 + vmov.f32 q0, -0.1953125 + vmov.f32 q0, -0.390625 + vmov.f32 q0, -0.78125 + vmov.f32 q0, -1.5625 + + vmov.f32 q0, -3.25 + vmov.f32 q0, -6.5 + vmov.f32 q0, -13.0 + vmov.f32 q0, -26.0 + vmov.f32 q0, -0.203125 + vmov.f32 q0, -0.40625 + vmov.f32 q0, -0.8125 + vmov.f32 q0, -1.625 + + vmov.f32 q0, -3.375 + vmov.f32 q0, -6.75 + vmov.f32 q0, -13.5 + vmov.f32 q0, -27.0 + vmov.f32 q0, -0.2109375 + vmov.f32 q0, -0.421875 + vmov.f32 q0, -0.84375 + vmov.f32 q0, -1.6875 + + vmov.f32 q0, -3.5 + vmov.f32 q0, -7.0 + vmov.f32 q0, -14.0 + vmov.f32 q0, -28.0 + vmov.f32 q0, -0.21875 + vmov.f32 q0, -0.4375 + vmov.f32 q0, -0.875 + vmov.f32 q0, -1.75 + + vmov.f32 q0, -3.625 + vmov.f32 q0, -7.25 + vmov.f32 q0, -14.5 + vmov.f32 q0, -29.0 + vmov.f32 q0, -0.2265625 + vmov.f32 q0, -0.453125 + vmov.f32 q0, -0.90625 + vmov.f32 q0, -1.8125 + + vmov.f32 q0, -3.75 + vmov.f32 q0, -7.5 + vmov.f32 q0, -15.0 + vmov.f32 q0, -30.0 + vmov.f32 q0, -0.234375 + vmov.f32 q0, -0.46875 + vmov.f32 q0, -0.9375 + vmov.f32 q0, -1.875 + + vmov.f32 q0, -3.875 + vmov.f32 q0, -7.75 + vmov.f32 q0, -15.5 + vmov.f32 q0, -31.0 + vmov.f32 q0, -0.2421875 + vmov.f32 q0, -0.484375 + vmov.f32 q0, -0.96875 + vmov.f32 q0, -1.9375 diff --git a/gas/testsuite/gas/arm/neon-cov.d b/gas/testsuite/gas/arm/neon-cov.d new file mode 100644 index 000000000000..e3f02f811f14 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cov.d @@ -0,0 +1,1522 @@ +# name: Neon instruction coverage +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000710 vaba\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100710 vaba\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200710 vaba\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000710 vaba\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100710 vaba\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200710 vaba\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000000 vhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100000 vhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200000 vhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000000 vhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100000 vhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200000 vhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000100 vrhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100100 vrhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200100 vrhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000100 vrhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100100 vrhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200100 vrhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000200 vhsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100200 vhsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200200 vhsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000200 vhsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100200 vhsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200200 vhsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000010 vqadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100010 vqadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200010 vqadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300010 vqadd\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000010 vqadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100010 vqadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200010 vqadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300010 vqadd\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000210 vqsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100210 vqsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200210 vqsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300210 vqsub\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000210 vqsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100210 vqsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200210 vqsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300210 vqsub\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000500 vrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100500 vrshl\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200500 vrshl\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300500 vrshl\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000500 vrshl\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100500 vrshl\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200500 vrshl\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300500 vrshl\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000510 vqrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, 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q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200110 vbit d0, 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+0[0-9a-f]+ <[^>]+> f3000f00 vpmax\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000a10 vpmin\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100a10 vpmin\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200a10 vpmin\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000a10 vpmin\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100a10 vpmin\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200a10 vpmin\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200f00 vpmin\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000940 vmla\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000940 vmla\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000900 vmla\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100940 vmla\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100940 vmla\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100900 vmla\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200940 vmla\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200900 vmla\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d50 vmla\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d10 vmla\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900040 vmla\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900040 vmla\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900040 vmla\.i16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00140 vmla\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000900 vmls\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100900 vmls\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d10 vmls\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900440 vmls\.i16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00540 vmls\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2000b10 vpadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b10 vpadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d00 vpadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000800 vadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100800 vadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300800 vadd\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d00 vadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000800 vsub\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100800 vsub\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300800 vsub\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d00 vsub\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000810 vtst\.8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100810 vtst\.16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200810 vtst\.32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000910 vmul\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100910 vmul\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d10 vmul\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000910 vmul\.p8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b00 vqdmulh\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b40 vqdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200b40 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<[^>]+> f3a00d40 vqrdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00d40 vqrdmulh\.s32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f10 vrecps\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> 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q0, #31 +0[0-9a-f]+ <[^>]+> f3890910 vqshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910910 vqshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10910 vqshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890950 vqrshrn\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910950 vqrshrn\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10950 vqrshrn\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890950 vqrshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910950 vqrshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10950 vqrshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890810 vqshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910810 vqshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10810 vqshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890850 vqrshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910850 vqrshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10850 vqrshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890810 vshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10810 vshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890850 vrshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f2a10a10 vshll\.s32 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3890a10 vshll\.u8 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3910a10 vshll\.u16 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3a10a10 vshll\.u32 d0, q0, #1 +0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8 +0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0700 vcvt\.s32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0780 vcvt\.u32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0600 vcvt\.f32\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0680 vcvt\.f32\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f10 vcvt\.s32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f10 vcvt\.u32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e10 vcvt\.f32\.s32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e10 vcvt\.f32\.u32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2200150 vorr q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200110 vorr d0, d0, d0 +0[0-9a-f]+ <[^>]+> ee400b10 vmov\.8 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b30 vmov\.16 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ec400b10 vmov d0, r0, r0 +0[0-9a-f]+ <[^>]+> ee500b10 vmov\.s8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> eed00b10 vmov\.u8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee900b30 vmov\.u16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f3810e71 vmov\.i64 q0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0 +0[0-9a-f]+ <[^>]+> f2800500 vabal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900500 vabal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00500 vabal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800500 vabal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900500 vabal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00500 vabal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800700 vabdl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900700 vabdl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00700 vabdl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800700 vabdl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900700 vabdl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00700 vabdl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800000 vaddl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900000 vaddl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00000 vaddl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800000 vaddl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900000 vaddl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00000 vaddl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800200 vsubl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900200 vsubl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00200 vsubl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800200 vsubl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900200 vsubl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00200 vsubl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800800 vmlal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900800 vmlal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00800 vmlal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800800 vmlal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900800 vmlal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00800 vmlal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900240 vmlal\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00240 vmlal\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900240 vmlal\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00240 vmlal\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800a00 vmlsl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900a00 vmlsl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00a00 vmlsl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800a00 vmlsl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900a00 vmlsl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00a00 vmlsl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900640 vmlsl\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00640 vmlsl\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900640 vmlsl\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00640 vmlsl\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800100 vaddw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900100 vaddw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00100 vaddw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800100 vaddw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900100 vaddw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00100 vaddw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800300 vsubw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900300 vsubw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00300 vsubw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800300 vsubw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900300 vsubw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00300 vsubw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800400 vaddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2a00400 vaddhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3800400 vraddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 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vpaddl\.u16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80280 vpaddl\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0400 vrecpe\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0500 vrecpe\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0480 vrsqrte\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0580 vrsqrte\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00400 vcls\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40400 vcls\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80400 vcls\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00480 vclz\.i8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40480 vclz\.i16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00500 vcnt\.8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20001 vswp d0, d1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20081 vtrn\.8 d0, d1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60081 vtrn\.16 d0, d1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0081 vtrn\.32 d0, d1 +0[0-9a-f]+ <[^>]+> f3b00800 vtbl\.8 d0, {d0}, d0 +0[0-9a-f]+ <[^>]+> f3b00840 vtbx\.8 d0, {d0}, d0 diff --git a/gas/testsuite/gas/arm/neon-cov.s b/gas/testsuite/gas/arm/neon-cov.s new file mode 100644 index 000000000000..04194a83eb07 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-cov.s @@ -0,0 +1,666 @@ +@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as +@ possible, but without causing instructions to be badly-formed. + + .arm + .syntax unified + .text + + .macro regs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro dregs3_1 op vtype + \op\vtype d0,d0,d0 + .endm + + .macro regn3_1 op operand2 vtype + \op\vtype d0,q0,\operand2 + .endm + + .macro regl3_1 op operand2 vtype + \op\vtype q0,d0,\operand2 + .endm + + .macro regw3_1 op operand2 vtype + \op\vtype q0,q0,\operand2 + .endm + + .macro regs2_1 op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + .macro regs3_su_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + .endm + + regs3_su_32 vaba vabaq + regs3_su_32 vhadd vhaddq + regs3_su_32 vrhadd vrhaddq + regs3_su_32 vhsub vhsubq + + .macro regs3_su_64 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .s64 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .u64 + .endm + + regs3_su_64 vqadd vqaddq + regs3_su_64 vqsub vqsubq + regs3_su_64 vrshl vrshlq + regs3_su_64 vqrshl vqrshlq + + regs3_su_64 vshl vshlq + regs3_su_64 vqshl vqshlq + + .macro regs2i_1 op opq imm vtype + \op\vtype q0,q0,\imm + \opq\vtype q0,q0,\imm + \op\vtype d0,d0,\imm + .endm + + .macro regs2i_su_64 op opq imm + regs2i_1 \op \opq \imm .s8 + regs2i_1 \op \opq \imm .s16 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .s64 + regs2i_1 \op \opq \imm .u8 + regs2i_1 \op \opq \imm .u16 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .u64 + .endm + + .macro regs2i_i_64 op opq imm + regs2i_1 \op \opq \imm .i8 + regs2i_1 \op \opq \imm .i16 + regs2i_1 \op \opq \imm .i32 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .i64 + .endm + + regs2i_i_64 vshl vshlq 0 + regs2i_su_64 vqshl vqshlq 0 + + .macro regs3_ntyp op opq + regs3_1 \op \opq .8 + .endm + + regs3_ntyp vand vandq + regs3_ntyp vbic vbicq + regs3_ntyp vorr vorrq + regs3_ntyp vorn vornq + regs3_ntyp veor veorq + + .macro logic_imm_1 op opq imm vtype + \op\vtype q0,\imm + \opq\vtype q0,\imm + \op\vtype d0,\imm + .endm + + .macro logic_imm op opq + logic_imm_1 \op \opq 0x000000a5000000a5 .i64 + logic_imm_1 \op \opq 0x0000a5000000a500 .i64 + logic_imm_1 \op \opq 0x00a5000000a50000 .i64 + logic_imm_1 \op \opq 0xa5000000a5000000 .i64 + logic_imm_1 \op \opq 0x00a500a500a500a5 .i64 + logic_imm_1 \op \opq 0xa500a500a500a500 .i64 + logic_imm_1 \op \opq 0x000000ff .i32 + logic_imm_1 \op \opq 0x000000ff .s32 + logic_imm_1 \op \opq 0x000000ff .u32 + logic_imm_1 \op \opq 0x0000ff00 .i32 + logic_imm_1 \op \opq 0x00ff0000 .i32 + logic_imm_1 \op \opq 0xff000000 .i32 + logic_imm_1 \op \opq 0x00a500a5 .i32 + logic_imm_1 \op \opq 0xa500a500 .i32 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00 .i8 + .endm + + logic_imm vbic vbicq + logic_imm vorr vorrq + + .macro logic_inv_imm op opq + logic_imm_1 \op \opq 0xffffff5affffff5a .i64 + logic_imm_1 \op \opq 0xffff5affffff5aff .i64 + logic_imm_1 \op \opq 0xff5affffff5affff .i64 + logic_imm_1 \op \opq 0x5affffff5affffff .i64 + logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64 + logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64 + logic_imm_1 \op \opq 0xffffff00 .i32 + logic_imm_1 \op \opq 0xffffff00 .s32 + logic_imm_1 \op \opq 0xffffff00 .u32 + logic_imm_1 \op \opq 0xffff00ff .i32 + logic_imm_1 \op \opq 0xff00ffff .i32 + logic_imm_1 \op \opq 0x00ffffff .i32 + logic_imm_1 \op \opq 0xff5aff5a .i32 + logic_imm_1 \op \opq 0x5aff5aff .i32 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff .i8 + .endm + + logic_inv_imm vand vandq + logic_inv_imm vorn vornq + + regs3_ntyp vbsl vbslq + regs3_ntyp vbit vbitq + regs3_ntyp vbif vbifq + + .macro regs3_suf_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + .macro regs3_if_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + regs3_suf_32 vabd vabdq + regs3_suf_32 vmax vmaxq + regs3_suf_32 vmin vminq + + regs3_suf_32 vcge vcgeq + regs3_suf_32 vcgt vcgtq + regs3_suf_32 vcle vcleq + regs3_suf_32 vclt vcltq + + regs3_if_32 vceq vceqq + + .macro regs2i_sf_0 op opq + regs2i_1 \op \opq 0 .s8 + regs2i_1 \op \opq 0 .s16 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_sf_0 vcge vcgeq + regs2i_sf_0 vcgt vcgtq + regs2i_sf_0 vcle vcleq + regs2i_sf_0 vclt vcltq + + .macro regs2i_if_0 op opq + regs2i_1 \op \opq 0 .i8 + regs2i_1 \op \opq 0 .i16 + regs2i_1 \op \opq 0 .i32 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .u32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_if_0 vceq vceqq + + .macro dregs3_suf_32 op + dregs3_1 \op .s8 + dregs3_1 \op .s16 + dregs3_1 \op .s32 + dregs3_1 \op .u8 + dregs3_1 \op .u16 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_suf_32 vpmax + dregs3_suf_32 vpmin + + .macro sregs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro sclr21_1 op opq vtype + \op\vtype q0,q0,d0[0] + \opq\vtype q0,q0,d0[0] + \op\vtype d0,d0,d0[0] + .endm + + .macro mul_incl_scalar op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + sclr21_1 \op \opq .i16 + sclr21_1 \op \opq .i32 + sclr21_1 \op \opq .s32 + sclr21_1 \op \opq .u32 + sclr21_1 \op \opq .f32 + .endm + + mul_incl_scalar vmla vmlaq + mul_incl_scalar vmls vmlsq + + .macro dregs3_if_32 op + dregs3_1 \op .i8 + dregs3_1 \op .i16 + dregs3_1 \op .i32 + dregs3_1 \op .s32 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_if_32 vpadd + + .macro regs3_if_64 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .i64 + regs3_1 \op \opq .f32 + .endm + + regs3_if_64 vadd vaddq + regs3_if_64 vsub vsubq + + .macro regs3_sz_32 op opq + regs3_1 \op \opq .8 + regs3_1 \op \opq .16 + regs3_1 \op \opq .32 + .endm + + regs3_sz_32 vtst vtstq + + .macro regs3_ifp_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + regs3_1 \op \opq .p8 + .endm + + regs3_ifp_32 vmul vmulq + + .macro dqmulhs op opq + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + sclr21_1 \op \opq .s16 + sclr21_1 \op \opq .s32 + .endm + + dqmulhs vqdmulh vqdmulhq + dqmulhs vqrdmulh vqrdmulhq + + regs3_1 vacge vacgeq .f32 + regs3_1 vacgt vacgtq .f32 + regs3_1 vacle vacleq .f32 + regs3_1 vaclt vacltq .f32 + regs3_1 vrecps vrecpsq .f32 + regs3_1 vrsqrts vrsqrtsq .f32 + + .macro regs2_sf_32 op opq + regs2_1 \op \opq .s8 + regs2_1 \op \opq .s16 + regs2_1 \op \opq .s32 + regs2_1 \op \opq .f32 + .endm + + regs2_sf_32 vabs vabsq + regs2_sf_32 vneg vnegq + + .macro rshift_imm op opq + regs2i_1 \op \opq 7 .s8 + regs2i_1 \op \opq 15 .s16 + regs2i_1 \op \opq 31 .s32 + regs2i_1 \op \opq 63 .s64 + regs2i_1 \op \opq 7 .u8 + regs2i_1 \op \opq 15 .u16 + regs2i_1 \op \opq 31 .u32 + regs2i_1 \op \opq 63 .u64 + .endm + + rshift_imm vshr vshrq + rshift_imm vrshr vrshrq + rshift_imm vsra vsraq + rshift_imm vrsra vrsraq + + regs2i_1 vsli vsliq 0 .8 + regs2i_1 vsli vsliq 0 .16 + regs2i_1 vsli vsliq 0 .32 + regs2i_1 vsli vsliq 0 .64 + + regs2i_1 vsri vsriq 7 .8 + regs2i_1 vsri vsriq 15 .16 + regs2i_1 vsri vsriq 31 .32 + regs2i_1 vsri vsriq 63 .64 + + regs2i_1 vqshlu vqshluq 0 .s8 + regs2i_1 vqshlu vqshluq 0 .s16 + regs2i_1 vqshlu vqshluq 0 .s32 + regs2i_1 vqshlu vqshluq 0 .s64 + + .macro qrshift_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + regn3_1 \op 7 .u16 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .u64 + .endm + + .macro qrshiftu_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + .endm + + .macro qrshifti_imm op + regn3_1 \op 7 .i16 + regn3_1 \op 15 .i32 + regn3_1 \op 15 .s32 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .i64 + .endm + + qrshift_imm vqshrn + qrshift_imm vqrshrn + qrshiftu_imm vqshrun + qrshiftu_imm vqrshrun + + qrshifti_imm vshrn + qrshifti_imm vrshrn + + regl3_1 vshll 1 .s8 + regl3_1 vshll 1 .s16 + regl3_1 vshll 1 .s32 + regl3_1 vshll 1 .u8 + regl3_1 vshll 1 .u16 + regl3_1 vshll 1 .u32 + + regl3_1 vshll 8 .i8 + regl3_1 vshll 16 .i16 + regl3_1 vshll 32 .i32 + regl3_1 vshll 32 .s32 + regl3_1 vshll 32 .u32 + + .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32" + \op\t1 \opr,\opr\arg + \op\t2 \opr,\opr\arg + \op\t3 \opr,\opr\arg + \op\t4 \opr,\opr\arg + .endm + + convert vcvt q0 + convert vcvtq q0 + convert vcvt d0 + convert vcvt q0 ",1" + convert vcvtq q0 ",1" + convert vcvt d0 ",1" + + vmov q0,q0 + vmov d0,d0 + vmov.8 d0[0],r0 + vmov.16 d0[0],r0 + vmov.32 d0[0],r0 + vmov d0,r0,r0 + vmov.s8 r0,d0[0] + vmov.s16 r0,d0[0] + vmov.u8 r0,d0[0] + vmov.u16 r0,d0[0] + vmov.32 r0,d0[0] + vmov r0,r1,d0 + + .macro mov_imm op imm vtype + \op\vtype q0,\imm + \op\vtype d0,\imm + .endm + + mov_imm vmov 0x00000077 .i32 + mov_imm vmov 0x00000077 .s32 + mov_imm vmov 0x00000077 .u32 + mov_imm vmvn 0x00000077 .i32 + mov_imm vmvn 0x00000077 .s32 + mov_imm vmvn 0x00000077 .u32 + mov_imm vmov 0x00007700 .i32 + mov_imm vmvn 0x00007700 .i32 + mov_imm vmov 0x00770000 .i32 + mov_imm vmvn 0x00770000 .i32 + mov_imm vmov 0x77000000 .i32 + mov_imm vmvn 0x77000000 .i32 + mov_imm vmov 0x0077 .i16 + mov_imm vmvn 0x0077 .i16 + mov_imm vmov 0x7700 .i16 + mov_imm vmvn 0x7700 .i16 + mov_imm vmov 0x000077ff .i32 + mov_imm vmvn 0x000077ff .i32 + mov_imm vmov 0x0077ffff .i32 + mov_imm vmvn 0x0077ffff .i32 + mov_imm vmov 0x77 .i8 + mov_imm vmov 0xff0000ff000000ff .i64 + mov_imm vmov 4.25 .f32 + + mov_imm vmov 0xa5a5 .i16 + mov_imm vmvn 0xa5a5 .i16 + mov_imm vmov 0xa5a5a5a5 .i32 + mov_imm vmvn 0xa5a5a5a5 .i32 + mov_imm vmov 0x00a500a5 .i32 + mov_imm vmov 0xa500a500 .i32 + mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmov 0x00a500a500a500a5 .i64 + mov_imm vmov 0xa500a500a500a500 .i64 + mov_imm vmov 0x000000a5000000a5 .i64 + mov_imm vmov 0x0000a5000000a500 .i64 + mov_imm vmov 0x00a5000000a50000 .i64 + mov_imm vmov 0xa5000000a5000000 .i64 + mov_imm vmov 0x0000a5ff0000a5ff .i64 + mov_imm vmov 0x00a5ffff00a5ffff .i64 + mov_imm vmov 0xa5ffffffa5ffffff .i64 + + vmvn q0,q0 + vmvnq q0,q0 + vmvn d0,d0 + + .macro long_ops op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + .endm + + long_ops vabal + long_ops vabdl + long_ops vaddl + long_ops vsubl + + .macro long_mac op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + regl3_1 \op "d0[0]" .u16 + regl3_1 \op "d0[0]" .u32 + .endm + + long_mac vmlal + long_mac vmlsl + + .macro wide_ops op + regw3_1 \op d0 .s8 + regw3_1 \op d0 .s16 + regw3_1 \op d0 .s32 + regw3_1 \op d0 .u8 + regw3_1 \op d0 .u16 + regw3_1 \op d0 .u32 + .endm + + wide_ops vaddw + wide_ops vsubw + + .macro narr_ops op + regn3_1 \op q0 .i16 + regn3_1 \op q0 .i32 + regn3_1 \op q0 .s32 + regn3_1 \op q0 .u32 + regn3_1 \op q0 .i64 + .endm + + narr_ops vaddhn + narr_ops vraddhn + narr_ops vsubhn + narr_ops vrsubhn + + .macro long_dmac op + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + .endm + + long_dmac vqdmlal + long_dmac vqdmlsl + long_dmac vqdmull + + regl3_1 vmull d0 .s8 + regl3_1 vmull d0 .s16 + regl3_1 vmull d0 .s32 + regl3_1 vmull d0 .u8 + regl3_1 vmull d0 .u16 + regl3_1 vmull d0 .u32 + regl3_1 vmull d0 .p8 + regl3_1 vmull "d0[0]" .s16 + regl3_1 vmull "d0[0]" .s32 + regl3_1 vmull "d0[0]" .u16 + regl3_1 vmull "d0[0]" .u32 + + vext.8 q0,q0,q0,0 + vextq.8 q0,q0,q0,0 + vext.8 d0,d0,d0,0 + vext.8 q0,q0,q0,8 + + .macro revs op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + revs vrev64 vrev64q .8 + revs vrev64 vrev64q .16 + revs vrev64 vrev64q .32 + revs vrev32 vrev32q .8 + revs vrev32 vrev32q .16 + revs vrev16 vrev16q .8 + + .macro dups op opq vtype + \op\vtype q0,r0 + \opq\vtype q0,r0 + \op\vtype d0,r0 + \op\vtype q0,d0[0] + \opq\vtype q0,d0[0] + \op\vtype d0,d0[0] + .endm + + dups vdup vdupq .8 + dups vdup vdupq .16 + dups vdup vdupq .32 + + .macro binop_3typ op op1 op2 t1 t2 t3 + \op\t1 \op1,\op2 + \op\t2 \op1,\op2 + \op\t3 \op1,\op2 + .endm + + binop_3typ vmovl q0 d0 .s8 .s16 .s32 + binop_3typ vmovl q0 d0 .u8 .u16 .u32 + binop_3typ vmovn d0 q0 .i16 .i32 .i64 + vmovn.s32 d0, q0 + vmovn.u32 d0, q0 + binop_3typ vqmovn d0 q0 .s16 .s32 .s64 + binop_3typ vqmovn d0 q0 .u16 .u32 .u64 + binop_3typ vqmovun d0 q0 .s16 .s32 .s64 + + .macro binops op opq vtype="" rhs="0" + \op\vtype q0,q\rhs + \opq\vtype q0,q\rhs + \op\vtype d0,d\rhs + .endm + + .macro regs2_sz_32 op opq + binops \op \opq .8 1 + binops \op \opq .16 1 + binops \op \opq .32 1 + .endm + + regs2_sz_32 vzip vzipq + regs2_sz_32 vuzp vuzpq + + .macro regs2_s_32 op opq + binops \op \opq .s8 + binops \op \opq .s16 + binops \op \opq .s32 + .endm + + regs2_s_32 vqabs vqabsq + regs2_s_32 vqneg vqnegq + + .macro regs2_su_32 op opq + regs2_s_32 \op \opq + binops \op \opq .u8 + binops \op \opq .u16 + binops \op \opq .u32 + .endm + + regs2_su_32 vpadal vpadalq + regs2_su_32 vpaddl vpaddlq + + binops vrecpe vrecpeq .u32 + binops vrecpe vrecpeq .f32 + binops vrsqrte vrsqrteq .u32 + binops vrsqrte vrsqrteq .f32 + + regs2_s_32 vcls vclsq + + .macro regs2_i_32 op opq + binops \op \opq .i8 + binops \op \opq .i16 + binops \op \opq .i32 + binops \op \opq .s32 + binops \op \opq .u32 + .endm + + regs2_i_32 vclz vclzq + + binops vcnt vcntq .8 + + binops vswp vswpq "" 1 + + regs2_sz_32 vtrn vtrnq + + vtbl.8 d0,{d0},d0 + vtbx.8 d0,{d0},d0 + diff --git a/gas/testsuite/gas/arm/neon-ldst-es.d b/gas/testsuite/gas/arm/neon-ldst-es.d new file mode 100644 index 000000000000..c520ac93116b --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-es.d @@ -0,0 +1,57 @@ +# name: Neon element and structure loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f406282f vst2\.8 {d2-d3}, \[r6, :128\] +0[0-9a-f]+ <[^>]+> f427140d vld3\.8 {d1-d3}, \[r7\]! +0[0-9a-f]+ <[^>]+> f4091553 vst3\.16 {d1,d3,d5}, \[r9, :64\], r3 +0[0-9a-f]+ <[^>]+> f42a208f vld4\.32 {d2-d5}, \[sl\] +0[0-9a-f]+ <[^>]+> f40a114f vst4\.16 {d1,d3,d5,d7}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c6f vld1\.16 {d1\[\]-d2\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c5f vld1\.16 {d1\[\]}, \[sl, :16\] +0[0-9a-f]+ <[^>]+> f4aa1dbf vld2\.32 {d1\[\],d3\[\]}, \[sl, :64\] +0[0-9a-f]+ <[^>]+> f4aa3e0c vld3\.8 {d3\[\]-d5\[\]}, \[sl\], ip +0[0-9a-f]+ <[^>]+> f4a9af6d vld4\.16 {d10\[\],d12\[\],d14\[\],d16\[\]}, \[r9\]! +0[0-9a-f]+ <[^>]+> f4a9af5f vld4\.16 {d10\[\]-d13\[\]}, \[r9, :64\] +0[0-9a-f]+ <[^>]+> f4a9af9f vld4\.32 {d10\[\]-d13\[\]}, \[r9, :64\] +0[0-9a-f]+ <[^>]+> f4a9afdf vld4\.32 {d10\[\]-d13\[\]}, \[r9, :128\] +0[0-9a-f]+ <[^>]+> f4a530ed vld1\.8 {d3\[7\]}, \[r5\]! +0[0-9a-f]+ <[^>]+> f48554df vst1\.16 {d5\[3\]}, \[r5, :16\] +0[0-9a-f]+ <[^>]+> f4a535dd vld2\.16 {d3\[3\],d4\[3\]}, \[r5, :32\]! +0[0-9a-f]+ <[^>]+> f4858a83 vst3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r5\], r3 +0[0-9a-f]+ <[^>]+> f4a7804f vld1\.8 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7848f vld1\.16 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7849f vld1\.16 {d8\[2\]}, \[r7, :16\] +0[0-9a-f]+ <[^>]+> f4a7888f vld1\.32 {d8\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a788bf vld1\.32 {d8\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7812f vld2\.8 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7813f vld2\.8 {d8\[1\],d9\[1\]}, \[r7, :16\] +0[0-9a-f]+ <[^>]+> f4a7854f vld2\.16 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7855f vld2\.16 {d8\[1\],d9\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7856f vld2\.16 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7857f vld2\.16 {d8\[1\],d10\[1\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7898f vld2\.32 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7899f vld2\.32 {d8\[1\],d9\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a789cf vld2\.32 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a789df vld2\.32 {d8\[1\],d10\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a7822f vld3\.8 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7864f vld3\.16 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7866f vld3\.16 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78a8f vld3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78acf vld3\.32 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7834f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7835f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7, :32\] +0[0-9a-f]+ <[^>]+> f4a7876f vld4\.16 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7875f vld4\.16 {d8\[1\],d9\[1\],d10\[1\],d11\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a78bcf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78bdf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :64\] +0[0-9a-f]+ <[^>]+> f4a78bef vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7, :128\] +0[0-9a-f]+ <[^>]+> f3b43805 vtbl\.8 d3, {d4}, d5 +0[0-9a-f]+ <[^>]+> f3b23b05 vtbl\.8 d3, {d2-d5}, d5 +0[0-9a-f]+ <[^>]+> f3be3985 vtbl\.8 d3, {d30-d31}, d5 +0[0-9a-f]+ <[^>]+> f427288f vld2\.32 {d2-d3}, \[r7\] +0[0-9a-f]+ <[^>]+> f427208f vld4\.32 {d2-d5}, \[r7\] +0[0-9a-f]+ <[^>]+> f467c08f vld4\.32 {d28-d31}, \[r7\] diff --git a/gas/testsuite/gas/arm/neon-ldst-es.s b/gas/testsuite/gas/arm/neon-ldst-es.s new file mode 100644 index 000000000000..5a29a4379390 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-es.s @@ -0,0 +1,59 @@ +@ test element and structure loads and stores. + + .text + .arm + .syntax unified + + vst2.8 {d2,d3},[r6,:128] + vld3.8 {d1,d2,d3},[r7]! + vst3.16 {d1,d3,d5},[r9,:64],r3 + vld4.32 {d2,d3,d4,d5},[r10] + vst4.16 {d1,d3,d5,d7},[r10] + vld1.16 {d1[],d2[]},[r10] + vld1.16 {d1[]},[r10,:16] + vld2.32 {d1[],d3[]},[r10,:64] + vld3.s8 {d3[],d4[],d5[]},[r10],r12 + vld4.16 {d10[],d12[],d14[],d16[]},[r9]! + vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128] + vld1.8 {d3[7]},[r5]! + vst1.16 {d5[3]},[r5,:16] + vld2.16 {d3[3],d4[3]},[r5,:32]! + vst3.32 {d8[1],d9[1],d10[1]},[r5],r3 + + vld1.8 {d8[2]},[r7] + vld1.16 {d8[2]},[r7] + vld1.16 {d8[2]},[r7,:16] + vld1.32 {d8[1]},[r7] + vld1.32 {d8[1]},[r7,:32] + vld2.8 {d8[1],d9[1]},[r7] + vld2.8 {d8[1],d9[1]},[r7,:16] + vld2.16 {d8[1],d9[1]},[r7] + vld2.16 {d8[1],d9[1]},[r7,:32] + vld2.16 {d8[1],d10[1]},[r7] + vld2.16 {d8[1],d10[1]},[r7,:32] + vld2.32 {d8[1],d9[1]},[r7] + vld2.32 {d8[1],d9[1]},[r7,:64] + vld2.32 {d8[1],d10[1]},[r7] + vld2.32 {d8[1],d10[1]},[r7,:64] + vld3.8 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d10[1],d12[1]},[r7] + vld3.32 {d8[1],d9[1],d10[1]},[r7] + vld3.32 {d8[1],d10[1],d12[1]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7,:32] + vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7,:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7,:128] + + vtbl.8 d3,{d4},d5 + vtbl.8 d3,{q1-q2},d5 + vtbl.8 d3,{q15},d5 + + vld2.32 {q1},[r7] + vld4.32 {q1-q2},[r7] + vld4.32 {q14-q15},[r7] diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.d b/gas/testsuite/gas/arm/neon-ldst-rm.d new file mode 100644 index 000000000000..86285d6dc35c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-rm.d @@ -0,0 +1,63 @@ +# name: Neon single and multiple register loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ecb22b02 vldmia r2!, {d2} +0[0-9a-f]+ <[^>]+> ecb22b04 vldmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ecb24b08 vldmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ecf28b10 vldmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ecb23b20 vldmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed322b02 vldmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed322b04 vldmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed324b08 vldmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed728b10 vldmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed323b20 vldmdb r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> eca22b02 vstmia r2!, {d2} +0[0-9a-f]+ <[^>]+> eca22b04 vstmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> eca24b08 vstmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ece28b10 vstmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> eca23b20 vstmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed222b02 vstmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed222b04 vstmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed224b08 vstmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18} +0[0-9a-f]+ <backward> 000001f4 .* +0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward> +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b01 vstr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed835b01 vstr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\] +0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\] +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\] +0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\] +0[0-9a-f]+ <forward> 000002bc .* +0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward> diff --git a/gas/testsuite/gas/arm/neon-ldst-rm.s b/gas/testsuite/gas/arm/neon-ldst-rm.s new file mode 100644 index 000000000000..f9421ac5563c --- /dev/null +++ b/gas/testsuite/gas/arm/neon-ldst-rm.s @@ -0,0 +1,44 @@ +@ test register and multi-register loads and stores. + + .text + .arm + .syntax unified + + .macro multi op dir="" wb="" + \op\dir r2\wb,{d2} + \op\dir r2\wb,{d2-d3} + \op\dir r2\wb,{q2-q3} + \op\dir r2\wb,{q12-q14,q15} + \op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18} + .endm + + multi vldm + multi vldm ia + multi vldm ia "!" + multi vldm db "!" + + multi vstm + multi vstm ia + multi vstm ia "!" + multi vstm db "!" + +backward: + .word 500 + + .macro single op offset="" + \op d5,[r3] + \op d5,[r3,#-\offset] + \op d5,[r3,#\offset] + .endm + + vldr d22, forward + + single vldr 4 + single vstr 4 + single vldr 256 + single vstr 256 + +forward: + .word 700 + + vldr d7, backward diff --git a/gas/testsuite/gas/arm/neon-omit.d b/gas/testsuite/gas/arm/neon-omit.d new file mode 100644 index 000000000000..fa7fa2cc75fe --- /dev/null +++ b/gas/testsuite/gas/arm/neon-omit.d @@ -0,0 +1,95 @@ +# name: Neon optional register operands +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3022746 vabd\.u8 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f26cc0c6 vhadd\.s32 q14, q14, q3 +0[0-9a-f]+ <[^>]+> f2222144 vrhadd\.s32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f22aa24e vhsub\.s32 q5, q5, q7 +0[0-9a-f]+ <[^>]+> f3186446 vshl\.u16 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f32ca45a vqshl\.u32 q5, q5, q6 +0[0-9a-f]+ <[^>]+> f20ee170 vand q7, q7, q8 +0[0-9a-f]+ <[^>]+> f30ee170 veor q7, q7, q8 +0[0-9a-f]+ <[^>]+> f3b5a14a vceq\.i16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f31aa85a vceq\.i16 q5, q5, q5 +0[0-9a-f]+ <[^>]+> f3b5a24a vclt\.s16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f3b5a34c vabs\.s16 q5, q6 +0[0-9a-f]+ <[^>]+> f3b57388 vneg\.s16 d7, d8 +0[0-9a-f]+ <[^>]+> f3b97708 vabs\.f32 d7, d8 +0[0-9a-f]+ <[^>]+> f3f927e4 vneg\.f32 q9, q10 +0[0-9a-f]+ <[^>]+> f2211a03 vpmax\.s32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f2255a17 vpmin\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3011f03 vpmax\.f32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f3255f07 vpmin\.f32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2122b46 vqdmulh\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f3255b07 vqrdmulh\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3922c6d vqdmulh\.s16 q1, q1, d5\[3\] +0[0-9a-f]+ <[^>]+> f2122056 vqadd\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f2255017 vqadd\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2222944 vmla\.i32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f2133b14 vpadd\.i16 d3, d3, d4 +0[0-9a-f]+ <[^>]+> f3266948 vmls\.i32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f3022e54 vacge\.f32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f3266e58 vacgt\.f32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5 +0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f32ee360 vcgt\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f320e3ce vcgt\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2 +0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4 +0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3 +0[0-9a-f]+ <[^>]+> f2011f12 vrecps\.f32 d1, d1, d2 +0[0-9a-f]+ <[^>]+> f29c2052 vshr\.s16 q1, q1, #4 +0[0-9a-f]+ <[^>]+> f28b4254 vrshr\.s8 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6 +0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6 +0[0-9a-f]+ <[^>]+> f3954554 vsli\.16 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63 +0[0-9a-f]+ <[^>]+> f2b55306 vext\.8 d5, d5, d6, #3 +0[0-9a-f]+ <[^>]+> f3042746 vabd\.u8 q1, q2, q3 +0[0-9a-f]+ <[^>]+> f262c0c6 vhadd\.s32 q14, q9, q3 +0[0-9a-f]+ <[^>]+> f22a2144 vrhadd\.s32 q1, q5, q2 +0[0-9a-f]+ <[^>]+> f220a2ce vhsub\.s32 q5, q8, q7 +0[0-9a-f]+ <[^>]+> f31a6448 vshl\.u16 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f322a45c vqshl\.u32 q5, q6, q1 +0[0-9a-f]+ <[^>]+> f200e1dc vand q7, q8, q6 +0[0-9a-f]+ <[^>]+> f300e1dc veor q7, q8, q6 +0[0-9a-f]+ <[^>]+> f3b5a146 vceq\.i16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f316a85a vceq\.i16 q5, q3, q5 +0[0-9a-f]+ <[^>]+> f3b5a246 vclt\.s16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f2231a20 vpmax\.s32 d1, d3, d16 +0[0-9a-f]+ <[^>]+> f2275a34 vpmin\.s32 d5, d7, d20 +0[0-9a-f]+ <[^>]+> f3031f07 vpmax\.f32 d1, d3, d7 +0[0-9a-f]+ <[^>]+> f32c5f07 vpmin\.f32 d5, d12, d7 +0[0-9a-f]+ <[^>]+> f2162b60 vqdmulh\.s16 q1, q3, q8 +0[0-9a-f]+ <[^>]+> f3275b09 vqrdmulh\.s32 d5, d7, d9 +0[0-9a-f]+ <[^>]+> f39c2c6d vqdmulh\.s16 q1, q6, d5\[3\] +0[0-9a-f]+ <[^>]+> f21620d6 vqadd\.s16 q1, q11, q3 +0[0-9a-f]+ <[^>]+> f227503f vqadd\.s32 d5, d7, d31 +0[0-9a-f]+ <[^>]+> f2242962 vmla\.i32 q1, q2, q9 +0[0-9a-f]+ <[^>]+> f21a3b94 vpadd\.i16 d3, d26, d4 +0[0-9a-f]+ <[^>]+> f328694a vmls\.i32 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f3082e54 vacge\.f32 q1, q4, q2 +0[0-9a-f]+ <[^>]+> f3226e58 vacgt\.f32 q3, q1, q4 +0[0-9a-f]+ <[^>]+> f30cae72 vacge\.f32 q5, q6, q9 +0[0-9a-f]+ <[^>]+> f320eed2 vacgt\.f32 q7, q8, q1 +0[0-9a-f]+ <[^>]+> f320e3d6 vcge\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f320e3c6 vcgt\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f326e370 vcge\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f326e360 vcgt\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f3aa2102 vaddw\.u32 q1, q5, d2 +0[0-9a-f]+ <[^>]+> f2a26304 vsubw\.s32 q3, q1, d4 +0[0-9a-f]+ <[^>]+> f22648d6 vtst\.32 q2, q11, q3 +0[0-9a-f]+ <[^>]+> f20e1f92 vrecps\.f32 d1, d30, d2 +0[0-9a-f]+ <[^>]+> f29c207a vshr\.s16 q1, q13, #4 +0[0-9a-f]+ <[^>]+> f28b4272 vrshr\.s8 q2, q9, #5 +0[0-9a-f]+ <[^>]+> f39a6152 vsra\.u16 q3, q1, #6 +0[0-9a-f]+ <[^>]+> f3dae358 vrsra\.u16 q15, q4, #6 +0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5 +0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63 +0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3 diff --git a/gas/testsuite/gas/arm/neon-omit.s b/gas/testsuite/gas/arm/neon-omit.s new file mode 100644 index 000000000000..42a7e8903b16 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-omit.s @@ -0,0 +1,97 @@ +@ test omitted optional arguments + + .text + .arm + .syntax unified + + vabd.u8 q1,q3 + vhadd.s32 q14, q3 + vrhadd.s32 q1,q2 + vhsub.s32 q5,q7 + vshl.u16 q3,q4 + vqshl.u32 q5,q6 + vand.64 q7,q8 + veor.64 q7,q8 + vceq.i16 q5,#0 + vceq.i16 q5,q5 + vclt.s16 q5,#0 + vabs.s16 q5,q6 + vneg.s16 d7,d8 + vabs.f d7,d8 + vneg.f q9,q10 + vpmax.s32 d1,d3 + vpmin.s32 d5,d7 + vpmax.f32 d1,d3 + vpmin.f32 d5,d7 + vqdmulh.s16 q1,q3 + vqrdmulh.s32 d5,d7 + vqdmulh.s16 q1,d5[3] + vqadd.s16 q1,q3 + vqadd.s32 d5,d7 + vmla.i32 q1,q2 + vpadd.i16 d3,d4 + vmls.s32 q3,q4 + vacge.f q1,q2 + vacgt.f q3,q4 + vacle.f q5,q6 + vaclt.f q7,q8 + vcge.u32 q7,q8 + vcgt.u32 q7,q8 + vcle.u32 q7,q8 + vclt.u32 q7,q8 + vaddw.u32 q1,d2 + vsubw.s32 q3,d4 + vtst.i32 q2,q3 + vrecps.f d1,d2 + vshr.s16 q1,#4 + vrshr.s8 q2,#5 + vsra.u16 q3,#6 + vrsra.u16 q4,#6 + vsli.16 q2,#5 + vqshlu.s64 d15,#63 + vext.8 d5,d6,#3 + +@ Also test three-argument forms without omitted arguments + + vabd.u8 q1,q2,q3 + vhadd.s32 q14,q9,q3 + vrhadd.s32 q1,q5,q2 + vhsub.s32 q5,q8,q7 + vshl.u16 q3,q4,q5 + vqshl.u32 q5,q6,q1 + vand.64 q7,q8,q6 + veor.64 q7,q8,q6 + vceq.i16 q5,q3,#0 + vceq.i16 q5,q3,q5 + vclt.s16 q5,q3,#0 + vpmax.s32 d1,d3,d16 + vpmin.s32 d5,d7,d20 + vpmax.f32 d1,d3,d7 + vpmin.f32 d5,d12,d7 + vqdmulh.s16 q1,q3,q8 + vqrdmulh.s32 d5,d7,d9 + vqdmulh.s16 q1,q6,d5[3] + vqadd.s16 q1,q11,q3 + vqadd.s32 d5,d7,d31 + vmla.i32 q1,q2,q9 + vpadd.i16 d3,d26,d4 + vmls.s32 q3,q4,q5 + vacge.f q1,q4,q2 + vacgt.f q3,q1,q4 + vacle.f q5,q9,q6 + vaclt.f q7,q1,q8 + vcge.u32 q7,q8,q3 + vcgt.u32 q7,q8,q3 + vcle.u32 q7,q8,q3 + vclt.u32 q7,q8,q3 + vaddw.u32 q1,q5,d2 + vsubw.s32 q3,q1,d4 + vtst.i32 q2,q11,q3 + vrecps.f d1,d30,d2 + vshr.s16 q1,q13,#4 + vrshr.s8 q2,q9,#5 + vsra.u16 q3,q1,#6 + vrsra.u16 q15,q4,#6 + vsli.16 q2,q3,#5 + vqshlu.s64 d15,d23,#63 + vext.8 d5,d18,d6,#3 diff --git a/gas/testsuite/gas/arm/neon-psyn.d b/gas/testsuite/gas/arm/neon-psyn.d new file mode 100644 index 000000000000..c318672f72b4 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-psyn.d @@ -0,0 +1,37 @@ +# name: Neon programmers syntax +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2144954 vmul\.i16 q2, q2, q2 +0[0-9a-f]+ <[^>]+> f2a33862 vmul\.i32 d3, d3, d2\[1\] +0[0-9a-f]+ <[^>]+> f2233912 vmul\.i32 d3, d3, d2 +0[0-9a-f]+ <[^>]+> f2222803 vadd\.i32 d2, d2, d3 +0[0-9a-f]+ <[^>]+> f3924a4a vmull\.u16 q2, d2, d2\[1\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2255805 vadd\.i32 d5, d5, d5 +0[0-9a-f]+ <[^>]+> f2275117 vorr d5, d7, d7 +0[0-9a-f]+ <[^>]+> ee021b70 vmov\.16 d2\[1\], r1 +0[0-9a-f]+ <[^>]+> ee251b10 vmov\.32 d5\[1\], r1 +0[0-9a-f]+ <[^>]+> ec432b15 vmov d5, r2, r3 +0[0-9a-f]+ <[^>]+> ee554b30 vmov\.s8 r4, d5\[1\] +0[0-9a-f]+ <[^>]+> ec565b15 vmov r5, r6, d5 +0[0-9a-f]+ <[^>]+> f396a507 vabal\.u16 q5, d6, d7 +0[0-9a-f]+ <[^>]+> f3bb2744 vcvt\.s32\.f32 q1, q2 +0[0-9a-f]+ <[^>]+> f3bb4e15 vcvt\.f32\.u32 d4, d5, #5 +0[0-9a-f]+ <[^>]+> f3bc7c05 vdup\.32 d7, d5\[1\] +0[0-9a-f]+ <[^>]+> f3ba1904 vtbl\.8 d1, {d10-d11}, d4 +0[0-9a-f]+ <[^>]+> f4aa698f vld2\.32 {d6\[1\],d7\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa476f vld4\.16 {d4\[1\],d6\[1\],d8\[1\],d10\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa6e4f vld3\.16 {d6\[\]-d8\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> f42a604f vld4\.16 {d6-d9}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa266f vld3\.16 {d2\[1\],d4\[1\],d6\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f3b47908 vtbl\.8 d7, {d4-d5}, d8 +0[0-9a-f]+ <[^>]+> f3142156 vbsl q1, q2, q3 +0[0-9a-f]+ <[^>]+> f3032e04 vcge\.f32 d2, d3, d4 +0[0-9a-f]+ <[^>]+> f3b52083 vcge\.s16 d2, d3, #0 +0[0-9a-f]+ <[^>]+> ee823b30 vdup\.16 d2, r3 diff --git a/gas/testsuite/gas/arm/neon-psyn.s b/gas/testsuite/gas/arm/neon-psyn.s new file mode 100644 index 000000000000..5d412a8552f0 --- /dev/null +++ b/gas/testsuite/gas/arm/neon-psyn.s @@ -0,0 +1,78 @@ + .arm + .syntax unified + +fish .qn q2 +cow .dn d2[1] +chips .dn d2 +banana .dn d3 + + vmul fish.s16, fish.s16, fish.s16 + + vmul banana, banana, cow.s32 + vmul d3.s32, d3.s32, d2.s32 + vadd d2.s32, d3.s32 + vmull fish.u32, chips.u16, chips.u16[1] + +X .dn D0.S16 +Y .dn D1.S16 +Z .dn Y[2] + + VMLA X, Y, Z + VMLA X, Y, Y[2] + +foo .dn d5 +bar .dn d7 +foos .dn foo[1] + + vadd foo, foo, foo.u32 + + vmov foo, bar + vmov d2.s16[1], r1 + vmov d5.s32[1], r1 + vmov foo, r2, r3 + vmov r4, foos.s8 + vmov r5, r6, foo + +baa .qn q5 +moo .dn d6 +sheep .dn d7 +chicken .dn d8 + + vabal baa, moo.u16, sheep.u16 + + vcvt q1.s32, q2.f32 + vcvt d4.f, d5.u32, #5 + + vdup bar, foos.32 + vtbl d1, {baa}, d4.8 + +el1 .dn d4.16[1] +el2 .dn d6.16[1] +el3 .dn d8.16[1] +el4 .dn d10.16[1] + + vld2 {moo.32[1], sheep.32[1]}, [r10] + vld4 {el1, el2, el3, el4}, [r10] + vld3 {moo.16[], sheep.16[], chicken.16[]}, [r10] + + vmov r0,d0.s16[0] + +el5 .qn q3.16 +el6 .qn q4.16 + + vld4 {el5,el6}, [r10] + + vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10] + +chicken8 .dn chicken.8 + + vtbl d7.8, {d4, d5}, chicken8 + + vbsl q1.8, q2.16, q3.8 + + vcge d2.32, d3.f, d4.f + vcge d2.16, d3.s16, #0 + +dupme .dn d2.s16 + + vdup dupme, r3 diff --git a/gas/testsuite/gas/arm/noarm.d b/gas/testsuite/gas/arm/noarm.d new file mode 100644 index 000000000000..ae34f8342f95 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.d @@ -0,0 +1,3 @@ +# name: Disallow ARM instructions on V7M +# as: +# error-output: noarm.l diff --git a/gas/testsuite/gas/arm/noarm.l b/gas/testsuite/gas/arm/noarm.l new file mode 100644 index 000000000000..edc59a2d5374 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: selected processor does not support ARM opcodes +[^:]*:13: Error: attempt to use an ARM instruction on a Thumb-only processor -- `nop' diff --git a/gas/testsuite/gas/arm/noarm.s b/gas/testsuite/gas/arm/noarm.s new file mode 100644 index 000000000000..3dadd4468f14 --- /dev/null +++ b/gas/testsuite/gas/arm/noarm.s @@ -0,0 +1,13 @@ + .arch armv7a + .syntax unified + .text +func: + nop + movw r0, #0 + + .arch armv7 + .thumb + nop + movw r0, #0 + .arm + nop diff --git a/gas/testsuite/gas/arm/relax_branch_align.d b/gas/testsuite/gas/arm/relax_branch_align.d new file mode 100644 index 000000000000..e23b0951584d --- /dev/null +++ b/gas/testsuite/gas/arm/relax_branch_align.d @@ -0,0 +1,13 @@ +#name: Branch relaxation with alignment. +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf00 nop +0+002 <[^>]+> f000 8080 beq.w 0+106 <[^>]*> +0+006 <[^>]+> bf00 nop +#... +0+100 <[^>]+> bf00 nop +0+102 <[^>]+> f47f af80 bne.w 0+006 <[^>]*> +0+106 <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/relax_branch_align.s b/gas/testsuite/gas/arm/relax_branch_align.s new file mode 100644 index 000000000000..718ce4982139 --- /dev/null +++ b/gas/testsuite/gas/arm/relax_branch_align.s @@ -0,0 +1,17 @@ + .syntax unified + .thumb +fn: + nop +.L191: + beq .L192 +.L46: + nop + .align 2 +.L54: + .rept 62 + .word 0 + .endr + nop + bne .L46 +.L192: + nop diff --git a/gas/testsuite/gas/arm/srs-arm.d b/gas/testsuite/gas/arm/srs-arm.d new file mode 100644 index 000000000000..844c692dd9fc --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.d @@ -0,0 +1,2 @@ +# name: SRS instruction in ARM mode +# error-output: srs-arm.l diff --git a/gas/testsuite/gas/arm/srs-arm.l b/gas/testsuite/gas/arm/srs-arm.l new file mode 100644 index 000000000000..ad992f8f7177 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:13: Error: SRS base register must be r13 -- `srsda r4,#13' +[^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13' +[^:]*:15: Error: SRS base register must be r13 -- `srsib r4,#13' diff --git a/gas/testsuite/gas/arm/srs-arm.s b/gas/testsuite/gas/arm/srs-arm.s new file mode 100644 index 000000000000..7d00fc8f0d6c --- /dev/null +++ b/gas/testsuite/gas/arm/srs-arm.s @@ -0,0 +1,16 @@ + .arch armv6 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsda r13, #13 + srsda r13!, #13 + srsib r13, #13 + srsib r13!, #13 + srsdb r4, #13 + srsda r4, #13 + srsia r4, #13 + srsib r4, #13 + diff --git a/gas/testsuite/gas/arm/srs-t2.d b/gas/testsuite/gas/arm/srs-t2.d new file mode 100644 index 000000000000..dfa57dbd8af3 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.d @@ -0,0 +1,2 @@ +# name: SRS instruction in Thumb-2 mode +# error-output: srs-t2.l diff --git a/gas/testsuite/gas/arm/srs-t2.l b/gas/testsuite/gas/arm/srs-t2.l new file mode 100644 index 000000000000..f0703759193c --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:9: Error: SRS base register must be r13 -- `srsia r4,#13' diff --git a/gas/testsuite/gas/arm/srs-t2.s b/gas/testsuite/gas/arm/srs-t2.s new file mode 100644 index 000000000000..7132626a59a7 --- /dev/null +++ b/gas/testsuite/gas/arm/srs-t2.s @@ -0,0 +1,10 @@ + .arch armv6t2 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsdb r4, #13 + srsia r4, #13 + diff --git a/gas/testsuite/gas/arm/svc.d b/gas/testsuite/gas/arm/svc.d index fdeb9302083b..697756c7965d 100644 --- a/gas/testsuite/gas/arm/svc.d +++ b/gas/testsuite/gas/arm/svc.d @@ -1,6 +1,5 @@ # name: SWI/SVC instructions # objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d index 47e9d89d9f94..be7afae7a40c 100644 --- a/gas/testsuite/gas/arm/tcompat.d +++ b/gas/testsuite/gas/arm/tcompat.d @@ -12,30 +12,30 @@ Disassembly of section .text: 0+04 <[^>]*> e1a09000 ? mov r9, r0 0+08 <[^>]*> e1a00009 ? mov r0, r9 0+0c <[^>]*> e1a0c00e ? mov ip, lr -0+10 <[^>]*> 91b09019 ? movlss r9, r9, lsl r0 -0+14 <[^>]*> 91a00910 ? movls r0, r0, lsl r9 -0+18 <[^>]*> e1b00880 ? movs r0, r0, lsl #17 -0+1c <[^>]*> e1a00889 ? mov r0, r9, lsl #17 -0+20 <[^>]*> 91b09039 ? movlss r9, r9, lsr r0 -0+24 <[^>]*> 91a00930 ? movls r0, r0, lsr r9 -0+28 <[^>]*> e1b008a0 ? movs r0, r0, lsr #17 -0+2c <[^>]*> e1a008a9 ? mov r0, r9, lsr #17 -0+30 <[^>]*> 91b09059 ? movlss r9, r9, asr r0 -0+34 <[^>]*> 91a00950 ? movls r0, r0, asr r9 -0+38 <[^>]*> e1b008c0 ? movs r0, r0, asr #17 -0+3c <[^>]*> e1a008c9 ? mov r0, r9, asr #17 -0+40 <[^>]*> 91b09079 ? movlss r9, r9, ror r0 -0+44 <[^>]*> 91a00970 ? movls r0, r0, ror r9 -0+48 <[^>]*> e1b008e0 ? movs r0, r0, ror #17 -0+4c <[^>]*> e1a008e9 ? mov r0, r9, ror #17 +0+10 <[^>]*> 91b09019 ? lslsls r9, r9, r0 +0+14 <[^>]*> 91a00910 ? lslls r0, r0, r9 +0+18 <[^>]*> e1b00880 ? lsls r0, r0, #17 +0+1c <[^>]*> e1a00889 ? lsl r0, r9, #17 +0+20 <[^>]*> 91b09039 ? lsrsls r9, r9, r0 +0+24 <[^>]*> 91a00930 ? lsrls r0, r0, r9 +0+28 <[^>]*> e1b008a0 ? lsrs r0, r0, #17 +0+2c <[^>]*> e1a008a9 ? lsr r0, r9, #17 +0+30 <[^>]*> 91b09059 ? asrsls r9, r9, r0 +0+34 <[^>]*> 91a00950 ? asrls r0, r0, r9 +0+38 <[^>]*> e1b008c0 ? asrs r0, r0, #17 +0+3c <[^>]*> e1a008c9 ? asr r0, r9, #17 +0+40 <[^>]*> 91b09079 ? rorsls r9, r9, r0 +0+44 <[^>]*> 91a00970 ? rorls r0, r0, r9 +0+48 <[^>]*> e1b008e0 ? rors r0, r0, #17 +0+4c <[^>]*> e1a008e9 ? ror r0, r9, #17 0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 ; 0x0 0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 ; 0x0 0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 ; 0x0 -0+5c <[^>]*> 92799000 ? rsblss r9, r9, #0 ; 0x0 -0+60 <[^>]*> e92d000e ? stmdb sp!, {r1, r2, r3} -0+64 <[^>]*> 992d8154 ? stmlsdb sp!, {r2, r4, r6, r8, pc} -0+68 <[^>]*> e8bd000e ? ldmia sp!, {r1, r2, r3} -0+6c <[^>]*> 98bd8154 ? ldmlsia sp!, {r2, r4, r6, r8, pc} +0+5c <[^>]*> 92799000 ? rsbsls r9, r9, #0 ; 0x0 +0+60 <[^>]*> e92d000e ? push {r1, r2, r3} +0+64 <[^>]*> 992d8154 ? pushls {r2, r4, r6, r8, pc} +0+68 <[^>]*> e8bd000e ? pop {r1, r2, r3} +0+6c <[^>]*> 98bd8154 ? popls {r2, r4, r6, r8, pc} 0+70 <[^>]*> e0000001 ? and r0, r0, r1 0+74 <[^>]*> e0200001 ? eor r0, r0, r1 0+78 <[^>]*> e0400001 ? sub r0, r0, r1 diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d index d3f815a2986a..7f9b253a443f 100644 --- a/gas/testsuite/gas/arm/thumb.d +++ b/gas/testsuite/gas/arm/thumb.d @@ -50,7 +50,7 @@ Disassembly of section \.text: 0+050 <[^>]+> 46c0 nop \(mov r8, r8\) 0+052 <[^>]+> 4738 bx r7 0+054 <[^>]+> 4740 bx r8 -0+056 <[^>]+> 0000 lsls r0, r0, #0 +0+056 <[^>]+> 46c0 nop \(mov r8, r8\) 0+058 <[^>]+> 4778 bx pc 0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\) 0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\) @@ -58,7 +58,7 @@ Disassembly of section \.text: 0+060 <[^>]+> 5511 strb r1, \[r2, r4\] 0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] 0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] - \.\.\. +0+066 <[^>]+> 46c0 nop \(mov r8, r8\) 0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] 0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] 0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] @@ -75,7 +75,7 @@ Disassembly of section \.text: 0+082 <[^>]+> 93ff str r3, \[sp, #1020\] 0+084 <[^>]+> 990b ldr r1, \[sp, #44\] 0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] -0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7,0+488 <[^>]+>\) +0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7, 0+488 <[^>]+>\) 0+08a <[^>]+> ac80 add r4, sp, #512 0+08c <[^>]+> b043 add sp, #268 0+08e <[^>]+> b09a sub sp, #104 @@ -111,11 +111,11 @@ Disassembly of section \.text: 0+0ca <[^>]+> b07f add sp, #508 0+0cc <[^>]+> b0ff sub sp, #508 0+0ce <[^>]+> a8ff add r0, sp, #1020 -0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0,0+4d0 <[^>]+>\) +0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0, 0+4d0 <[^>]+>\) 0+0d2 <[^>]+> b01a add sp, #104 0+0d4 <[^>]+> b09a sub sp, #104 0+0d6 <[^>]+> a81a add r0, sp, #104 -0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0,0+144 <[^>]+>\) +0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0, 0+144 <[^>]+>\) 0+0da <[^>]+> 3168 adds r1, #104 0+0dc <[^>]+> 2668 movs r6, #104 0+0de <[^>]+> 2f68 cmp r7, #104 @@ -127,14 +127,14 @@ Disassembly of section \.text: 0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> 0+0f4 <[^>]+> e12fff10 bx r0 0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0,0+110 <[^>]+>\) +0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0, 0+110 <[^>]+>\) 0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> 0+100 <[^>]+> e018 b.n 0+134 <[^>]+> 0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> 0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> 0+10a <[^>]+> 4700 bx r0 0+10c <[^>]+> dfff (swi|svc) 255 - \.\.\. +0+10e <[^>]+> 46c0 nop \(mov r8, r8\) 0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> 0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> 0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> diff --git a/gas/testsuite/gas/arm/thumb1_unified.d b/gas/testsuite/gas/arm/thumb1_unified.d new file mode 100644 index 000000000000..c2fdf306325a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb1_unified.d @@ -0,0 +1,20 @@ +# name: Thumb-1 unified +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> 200c movs r0, #12 +0[0-9a-f]+ <[^>]+> 1cd1 adds r1, r2, #3 +0[0-9a-f]+ <[^>]+> 1ed1 subs r1, r2, #3 +0[0-9a-f]+ <[^>]+> 3364 adds r3, #100 +0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131 +0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39 +0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 \(adr [^)]*\) +0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] \([^)]*\) +0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\] +0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\] +0[0-9a-f]+ <[^>]+> b001 add sp, #4 +0[0-9a-f]+ <[^>]+> b081 sub sp, #4 +0[0-9a-f]+ <[^>]+> af01 add r7, sp, #4 +0[0-9a-f]+ <[^>]+> 4251 negs r1, r2 diff --git a/gas/testsuite/gas/arm/thumb1_unified.s b/gas/testsuite/gas/arm/thumb1_unified.s new file mode 100644 index 000000000000..c8da6ec5aa8e --- /dev/null +++ b/gas/testsuite/gas/arm/thumb1_unified.s @@ -0,0 +1,25 @@ +.text +.arch armv4t +.syntax unified +.thumb +foo: +movs r0, #12 +adds r1, r2, #3 +subs r1, r2, #3 +adds r3, r3, #0x64 +subs r4, r4, #0x83 +cmp r5, #0x27 + +adr r1, bar +ldr r2, bar +ldr r3, [r4, #4] +ldr r5, [sp, #4] +add sp, sp, #4 +sub sp, sp, #4 +add r7, sp, #4 + +rsbs r1, r2, #0 + +.align 2 +bar: + diff --git a/gas/testsuite/gas/arm/thumb2_add.d b/gas/testsuite/gas/arm/thumb2_add.d new file mode 100644 index 000000000000..5100bb691a7a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_add.d @@ -0,0 +1,30 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800 +0+004 <[^>]+> f20f 0900 addw r9, pc, #0 ; 0x0 +0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400 +0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400 +0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101 +0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101 +0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800 +0+01c <[^>]+> f2af 0900 subw r9, pc, #0 ; 0x0 +0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400 +0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400 +0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101 +0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101 +0+030 <[^>]+> f103 0301 add.w r3, r3, #1 ; 0x1 +0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 ; 0x1 +0+038 <[^>]+> b0c0 sub sp, #256 +0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200 +0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101 +0+042 <[^>]+> b040 add sp, #256 +0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200 +0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101 +0+04c <[^>]+> a840 add r0, sp, #256 +0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400 +0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101 +0+056 <[^>]+> 4271 negs r1, r6 diff --git a/gas/testsuite/gas/arm/thumb2_add.s b/gas/testsuite/gas/arm/thumb2_add.s new file mode 100644 index 000000000000..a3b178a05291 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_add.s @@ -0,0 +1,31 @@ + .syntax unified + .text + .align 2 + .global thumb2_add + .thumb + .thumb_func +thumb2_add: + add r0, pc, #0x800 + add r9, pc, #0 + add r9, pc, #0x400 + add r8, r9, #0x400 + add r8, r9, #0x101 + add r3, r1, #0x101 + sub r0, pc, #0x800 + sub r9, pc, #0 + sub r9, pc, #0x400 + sub r8, r9, #0x400 + sub r8, r9, #0x101 + sub r3, r1, #0x101 + add r3, #1 + sub r3, #1 + sub sp, sp, #0x100 + sub sp, sp, #0x200 + sub sp, sp, #0x101 + add sp, sp, #0x100 + add sp, sp, #0x200 + add sp, sp, #0x101 + add r0, sp, #0x100 + add r5, sp, #0x400 + add r9, sp, #0x101 + rsbs r1, r6, #0 diff --git a/gas/testsuite/gas/arm/thumb2_bcond.d b/gas/testsuite/gas/arm/thumb2_bcond.d index 8ab75320e1a3..02903a954191 100644 --- a/gas/testsuite/gas/arm/thumb2_bcond.d +++ b/gas/testsuite/gas/arm/thumb2_bcond.d @@ -1,26 +1,25 @@ # as: # objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* Disassembly of section .text: 0+000 <[^>]+> bf18 it ne -0+002 <[^>]+> e7fd b(|ne).n 0+0 <[^>]+> +0+002 <[^>]+> e7fd bne.n 0+0 <[^>]+> 0+004 <[^>]+> bf38 it cc -0+006 <[^>]+> f7ff bffb b(|cc).w 0+0 <[^>]+> +0+006 <[^>]+> f7ff bffb bcc.w 0+0 <[^>]+> 0+00a <[^>]+> bf28 it cs -0+00c <[^>]+> f7ff fff8 bl(|cs) 0+0 <[^>]+> +0+00c <[^>]+> f7ff fff8 blcs 0+0 <[^>]+> 0+010 <[^>]+> bfb8 it lt -0+012 <[^>]+> 47a8 blx(|lr) r5 +0+012 <[^>]+> 47a8 blxlt r5 0+014 <[^>]+> bf08 it eq -0+016 <[^>]+> 4740 bx(|eq) r8 +0+016 <[^>]+> 4740 bxeq r8 0+018 <[^>]+> bfc8 it gt -0+01a <[^>]+> e8d4 f001 tbb(|gt) \[r4, r1\] +0+01a <[^>]+> e8d4 f001 tbbgt \[r4, r1\] 0+01e <[^>]+> bfb8 it lt -0+020 <[^>]+> df00 svc(|lt) 0 +0+020 <[^>]+> df00 svclt 0 0+022 <[^>]+> bfdc itt le 0+024 <[^>]+> be00 bkpt 0x0000 -0+026 <[^>]+> bf00 nop +0+026 <[^>]+> bf00 nople 0+028 <[^>]+> bf00 nop 0+02a <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.d b/gas/testsuite/gas/arm/thumb2_it_bad.d index f905c9f5e73b..1cca8b9650cb 100644 --- a/gas/testsuite/gas/arm/thumb2_it_bad.d +++ b/gas/testsuite/gas/arm/thumb2_it_bad.d @@ -1,4 +1,3 @@ #name: Invalid IT instructions #as: -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* #error-output: thumb2_it_bad.l diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.d b/gas/testsuite/gas/arm/thumb2_ldmstm.d new file mode 100644 index 000000000000..2f50486489c2 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldmstm.d @@ -0,0 +1,27 @@ +# name: Thumb-2 LDM/STM single reg +# as: -march=armv6t2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> bc01 pop {r0} +0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8d1 9000 ldr.w r9, \[r1\] +0[0-9a-f]+ <[^>]+> f852 cb04 ldr.w ip, \[r2\], #4 +0[0-9a-f]+ <[^>]+> f85d 2d04 ldr.w r2, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f85d 8d04 ldr.w r8, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f856 4c04 ldr.w r4, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f856 8c04 ldr.w r8, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f852 4d04 ldr.w r4, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> f852 cd04 ldr.w ip, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> b408 push {r3} +0[0-9a-f]+ <[^>]+> f84d 9b04 str.w r9, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8c3 c000 str.w ip, \[r3\] +0[0-9a-f]+ <[^>]+> f844 cb04 str.w ip, \[r4\], #4 +0[0-9a-f]+ <[^>]+> f84d 3d04 str.w r3, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f84d 9d04 str.w r9, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f847 5c04 str.w r5, \[r7, #-4\] +0[0-9a-f]+ <[^>]+> f846 cc04 str.w ip, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f846 bd04 str.w fp, \[r6, #-4\]! +0[0-9a-f]+ <[^>]+> f845 8d04 str.w r8, \[r5, #-4\]! diff --git a/gas/testsuite/gas/arm/thumb2_ldmstm.s b/gas/testsuite/gas/arm/thumb2_ldmstm.s new file mode 100644 index 000000000000..fd4410af3c4a --- /dev/null +++ b/gas/testsuite/gas/arm/thumb2_ldmstm.s @@ -0,0 +1,24 @@ +.syntax unified +.thumb +ldmstm: + ldmia sp!, {r0} + ldmia sp!, {r8} + ldmia r1, {r9} + ldmia r2!, {ip} + ldmdb sp!, {r2} + ldmdb sp!, {r8} + ldmdb r6, {r4} + ldmdb r6, {r8} + ldmdb r2!, {r4} + ldmdb r2!, {ip} + stmia sp!, {r3} + stmia sp!, {r9} + stmia r3, {ip} + stmia r4!, {ip} + stmdb sp!, {r3} + stmdb sp!, {r9} + stmdb r7, {r5} + stmdb r6, {ip} + stmdb r6!, {fp} + stmdb r5!, {r8} + diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d index 7bf0c605d5fd..752da7fb6aa7 100644 --- a/gas/testsuite/gas/arm/thumb2_pool.d +++ b/gas/testsuite/gas/arm/thumb2_pool.d @@ -1,5 +1,7 @@ # as: -march=armv6t2 # objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* @@ -11,5 +13,4 @@ Disassembly of section .text: 0+00c <[^>]+> bf00 nop 0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> 0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] \(00+14 <[^>]+>\) -0+014 <[^>]+> (5678|1234) .* -0+016 <[^>]+> (1234|5678) .* +0+014 <[^>]+> 12345678 ? .word 0x12345678 diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d index 48cd1f21f806..327ef42b5347 100644 --- a/gas/testsuite/gas/arm/thumb2_relax.d +++ b/gas/testsuite/gas/arm/thumb2_relax.d @@ -20,7 +20,7 @@ Disassembly of section .text: 0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+> 0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+> 0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+> -0+03a <[^>]+> 0000 lsls r0, r0, #0 +0+03a <[^>]+> 46c0 nop \(mov r8, r8\) 0+03c <[^>]+> bf00 nop 0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\] 0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\] @@ -89,7 +89,7 @@ Disassembly of section .text: 0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+> 0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+> 0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+> -0+132 <[^>]+> 0000 lsls r0, r0, #0 +0+132 <[^>]+> 46c0 nop \(mov r8, r8\) 0+134 <[^>]+> bf00 nop 0+136 <[^>]+> 7029 strb r1, \[r5, #0\] 0+138 <[^>]+> f885 1023 strb.w r1, \[r5, #35\] @@ -142,7 +142,7 @@ Disassembly of section .text: 0+1e0 <[^>]+> f8cf 1006 str.w r1, \[pc, #6\] ; 0+1ea <[^>]+> 0+1e4 <[^>]+> f84f 103a str.w r1, \[pc, #-58\] ; 0+1ae <[^>]+> 0+1e8 <[^>]+> bf00 nop -0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1,0+1fc <[^>]+>\) +0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1, 0+1fc <[^>]+>\) 0+1ec <[^>]+> f20f 010c addw r1, pc, #12 ; 0xc 0+1f0 <[^>]+> f20f 0808 addw r8, pc, #8 ; 0x8 0+1f4 <[^>]+> f20f 0106 addw r1, pc, #6 ; 0x6 diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d index 2977779aefdd..0d96818858e2 100644 --- a/gas/testsuite/gas/arm/thumb32.d +++ b/gas/testsuite/gas/arm/thumb32.d @@ -3,6 +3,7 @@ # objdump: -dr --prefix-addresses --show-raw-insn # The arm-aout and arm-pe ports do not support Thumb branch relocations. # not-target: *-*-*aout* *-*-pe +# stderr: thumb32.l .*: +file format .*arm.* @@ -62,9 +63,9 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0 0[0-9a-f]+ <[^>]+> 4401 add r1, r0 0[0-9a-f]+ <[^>]+> 4408 add r0, r1 -0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0,[0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0, [0-9a-f]+ <[^>]+>\) 0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0 0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0 0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516 @@ -349,163 +350,163 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> bf90 nop \{9\} 0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\} 0[0-9a-f]+ <[^>]+> bf08 it eq -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf18 it ne -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcs 0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcs 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopcc 0[0-9a-f]+ <[^>]+> bf48 it mi -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopmi 0[0-9a-f]+ <[^>]+> bf58 it pl -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 noppl 0[0-9a-f]+ <[^>]+> bf68 it vs -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopvs 0[0-9a-f]+ <[^>]+> bf78 it vc -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopvc 0[0-9a-f]+ <[^>]+> bf88 it hi -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nophi 0[0-9a-f]+ <[^>]+> bfa8 it ge -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopge 0[0-9a-f]+ <[^>]+> bfb8 it lt -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 noplt 0[0-9a-f]+ <[^>]+> bfc8 it gt -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopgt 0[0-9a-f]+ <[^>]+> bfd8 it le -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nople 0[0-9a-f]+ <[^>]+> bfe8 it al -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopal 0[0-9a-f]+ <[^>]+> bf04 itt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0c ite eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf02 ittt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0a itet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf06 itte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0e itee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf09 itett eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf05 ittet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf03 ittte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf07 ittee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0b itete eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf0d iteet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf0f iteee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1c itt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf14 ite ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf1e ittt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf16 itet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1a itte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf12 itee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf1f itttt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf17 itett ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1b ittet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf1d ittte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf19 ittee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf15 itete ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> bf13 iteet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne 0[0-9a-f]+ <[^>]+> bf11 iteee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq 0[0-9a-f]+ <[^>]+> f895 f000 pld \[r5\] 0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\] 0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\] @@ -949,8 +950,83 @@ Disassembly of section .text: 0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} 0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} 0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> c806 ldmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> c006 stmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> c806 ldmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> c006 stmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> e890 0300 ldmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> e880 0300 stmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> e98d c010 srsia sp, #16 +0[0-9a-f]+ <[^>]+> e80d c010 srsdb sp, #16 +0[0-9a-f]+ <[^>]+> e9ad c015 srsia sp!, #21 +0[0-9a-f]+ <[^>]+> e9ad c00a srsia sp!, #10 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f04 subs pc, lr, #4 +0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255 +0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]! +0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]! +0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48 +0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48 +0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f855 1009 ldr.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f815 1009 ldrb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f915 1009 ldrsb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f835 1009 ldrh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769] +0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]! +0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]! +0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48 +0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48 +0[0-9a-f]+ <[^>]+> f935 1009 ldrsh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> 00a1 lsls r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0389 movs.w r3, r9, lsl #2 +0[0-9a-f]+ <[^>]+> fa12 f103 lsls.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4099 lsls r1, r3 +0[0-9a-f]+ <[^>]+> fa11 f109 lsls.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa02 f103 lsl.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa01 f103 lsl.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 08a1 lsrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0399 movs.w r3, r9, lsr #2 +0[0-9a-f]+ <[^>]+> fa32 f103 lsrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 40d9 lsrs r1, r3 +0[0-9a-f]+ <[^>]+> fa31 f109 lsrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa22 f103 lsr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa21 f103 lsr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 10a1 asrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 03a9 movs.w r3, r9, asr #2 +0[0-9a-f]+ <[^>]+> fa52 f103 asrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4119 asrs r1, r3 +0[0-9a-f]+ <[^>]+> fa51 f109 asrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa42 f103 asr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa41 f103 asr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> ea5f 01b4 movs.w r1, r4, ror #2 +0[0-9a-f]+ <[^>]+> ea5f 03b9 movs.w r3, r9, ror #2 +0[0-9a-f]+ <[^>]+> fa72 f103 rors.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 41d9 rors r1, r3 +0[0-9a-f]+ <[^>]+> fa71 f109 rors.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3 0[0-9a-f]+ <[^>]+> bf00 nop diff --git a/gas/testsuite/gas/arm/thumb32.l b/gas/testsuite/gas/arm/thumb32.l new file mode 100644 index 000000000000..c687beac79e8 --- /dev/null +++ b/gas/testsuite/gas/arm/thumb32.l @@ -0,0 +1,17 @@ +[^;]*: Assembler messages: +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:446: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:447: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:448: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated +[^;]*:449: Warning: s suffix on comparison instruction is deprecated diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s index b75a0850f384..697dfd240f34 100644 --- a/gas/testsuite/gas/arm/thumb32.s +++ b/gas/testsuite/gas/arm/thumb32.s @@ -769,3 +769,51 @@ xta: ldmeq r0, {r8, r9} stmeq r0, {r8, r9} nop + +srs: + srsia sp, #16 + srsdb sp, #16 + srsia sp!, #21 + srsia sp!, #10 + + movs pc, lr + subs pc, lr, #0 + subs pc, lr, #4 + subs pc, lr, #255 + + ldrd r2, r4, [r9, #48]! + ldrd r2, r4, [r9, #-48]! + strd r2, r4, [r9, #48]! + strd r2, r4, [r9, #-48]! + ldrd r2, r4, [r9], #48 + ldrd r2, r4, [r9], #-48 + strd r2, r4, [r9], #48 + strd r2, r4, [r9], #-48 + + .macro ldaddr op + ldr\op r1, [r5, #0x301] + ldr\op r1, [r5, #0x30]! + ldr\op r1, [r5, #-0x30]! + ldr\op r1, [r5], #0x30 + ldr\op r1, [r5], #-0x30 + ldr\op r1, [r5, r9] + .endm + ldaddr + ldaddr b + ldaddr sb + ldaddr h + ldaddr sh + .macro movshift op s="s" + movs r1, r4, \op #2 + movs r3, r9, \op #2 + movs r1, r2, \op r3 + movs r1, r1, \op r3 + movs r1, r1, \op r9 + mov r1, r2, \op r3 + mov r1, r1, \op r3 + .endm + movshift lsl + movshift lsr + movshift asr + movshift ror + nop diff --git a/gas/testsuite/gas/arm/thumbrel.d b/gas/testsuite/gas/arm/thumbrel.d new file mode 100644 index 000000000000..fff41af9cc98 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbrel.d @@ -0,0 +1,14 @@ +#objdump: -sr +# This test is only valid on EABI based ports. +#target: *-*-*eabi *-*-symbianelf + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000004 R_ARM_REL32 b + +Contents of section .text: + 0000 00000000 (00000004|04000000) 00000000 00000000 .* +# Ignore .ARM.attributes section +#... diff --git a/gas/testsuite/gas/arm/thumbrel.s b/gas/testsuite/gas/arm/thumbrel.s new file mode 100644 index 000000000000..769da16156c7 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbrel.s @@ -0,0 +1,11 @@ +@ Check that PC-relative relocs against local function symbols are +@ generated correctly. +.text +.thumb +a: +.word 0 +.word b - a +.word 0 +.word 0 +.type b, %function +b: diff --git a/gas/testsuite/gas/arm/thumbver.d b/gas/testsuite/gas/arm/thumbver.d new file mode 100644 index 000000000000..ddc46df56d42 --- /dev/null +++ b/gas/testsuite/gas/arm/thumbver.d @@ -0,0 +1,15 @@ +# as: -meabi=4 +# readelf: -s +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Symbol table '\.symtab' contains .* entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND + 1: 00000000 0 SECTION LOCAL DEFAULT 1 +#... + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_alias + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_body + .*: 00000000 0 NOTYPE LOCAL DEFAULT 1 \$t + .*: 00000001 0 FUNC LOCAL DEFAULT 1 a_export@VERSION +#... diff --git a/gas/testsuite/gas/arm/thumbver.s b/gas/testsuite/gas/arm/thumbver.s new file mode 100644 index 000000000000..ad81395ee40c --- /dev/null +++ b/gas/testsuite/gas/arm/thumbver.s @@ -0,0 +1,9 @@ +@ Check that symbols created by .symver are marked as Thumb. + + .thumb_set a_alias, a_body + .symver a_alias, a_export@VERSION + .type a_body, %function + .code 16 + .thumb_func +a_body: + nop diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d index 5b41109292cb..5189dfff01f4 100644 --- a/gas/testsuite/gas/arm/tls.d +++ b/gas/testsuite/gas/arm/tls.d @@ -15,11 +15,11 @@ Disassembly of section .text: 0: e1a00000 nop \(mov r0,r0\) 4: e1a00000 nop \(mov r0,r0\) 8: e1a0f00e mov pc, lr - c: 00000000 andeq r0, r0, r0 + c: 00000000 .word 0x00000000 c: R_ARM_TLS_GD32 a - 10: 00000004 andeq r0, r0, r4 + 10: 00000004 .word 0x00000004 10: R_ARM_TLS_LDM32 b - 14: 00000008 andeq r0, r0, r8 + 14: 00000008 .word 0x00000008 14: R_ARM_TLS_IE32 c - 18: 00000000 andeq r0, r0, r0 + 18: 00000000 .word 0x00000000 18: R_ARM_TLS_LE32 d diff --git a/gas/testsuite/gas/arm/undefined.d b/gas/testsuite/gas/arm/undefined.d index 6a6149561cc3..e3e9bb08929c 100644 --- a/gas/testsuite/gas/arm/undefined.d +++ b/gas/testsuite/gas/arm/undefined.d @@ -1,4 +1,5 @@ #name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* #error-output: undefined.l diff --git a/gas/testsuite/gas/arm/undefined_coff.d b/gas/testsuite/gas/arm/undefined_coff.d index ab0bbcdc6672..d2800275b078 100644 --- a/gas/testsuite/gas/arm/undefined_coff.d +++ b/gas/testsuite/gas/arm/undefined_coff.d @@ -1,4 +1,5 @@ #name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#not-skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* #error-output: undefined_coff.l diff --git a/gas/testsuite/gas/arm/unwind.d b/gas/testsuite/gas/arm/unwind.d index cd4a7c7995c2..060f7ba56afe 100644 --- a/gas/testsuite/gas/arm/unwind.d +++ b/gas/testsuite/gas/arm/unwind.d @@ -25,18 +25,22 @@ OFFSET TYPE VALUE 0000001c R_ARM_PREL31 .ARM.extab.* 00000020 R_ARM_PREL31 .text.* 00000028 R_ARM_PREL31 .text.* +00000030 R_ARM_PREL31 .text.* +00000034 R_ARM_PREL31 .ARM.extab.* Contents of section .text: 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* - 0010 (04200520|20052004) .* + 0010 (04200520 0600a0e3|20052004 e3a00006) .* Contents of section .ARM.extab: 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* Contents of section .ARM.exidx: 0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000 .* 0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c) .* 0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0) .* + 0030 (14000000 2c000000|00000014 0000002c) .* # Ignore .ARM.attributes section #... diff --git a/gas/testsuite/gas/arm/unwind.s b/gas/testsuite/gas/arm/unwind.s index 7d0f126954f1..bbd73a157d94 100644 --- a/gas/testsuite/gas/arm/unwind.s +++ b/gas/testsuite/gas/arm/unwind.s @@ -27,6 +27,8 @@ foo2: @ Custom personality routine .fnend foo3: @ Saving iwmmxt registers .fnstart + .save {wr12} + .save {wr13} .save {wr11} .save {wr10} .save {wr10, wr11} @@ -49,3 +51,17 @@ foo5: @ Save r0-r3 only. .save {r0, r1, r2, r3} mov r0, #5 .fnend + .code 32 +foo6: @ Nested function with frame pointer + .fnstart + .pad #4 + @push {ip} + .movsp ip, #4 + @mov ip, sp + .pad #4 + .save {fp, ip, lr} + @stmfd sp!, {fp, ip, lr, pc} + .setfp fp, ip, #-8 + @sub fp, ip, #8 + mov r0, #6 + .fnend diff --git a/gas/testsuite/gas/arm/unwind_vxworks.d b/gas/testsuite/gas/arm/unwind_vxworks.d index ccd16a65cc9a..11817cf48c16 100644 --- a/gas/testsuite/gas/arm/unwind_vxworks.d +++ b/gas/testsuite/gas/arm/unwind_vxworks.d @@ -24,6 +24,8 @@ OFFSET TYPE VALUE 0000001c R_ARM_PREL31 .ARM.extab.*\+0x0000001c 00000020 R_ARM_PREL31 .text.*\+0x00000010 00000028 R_ARM_PREL31 .text.*\+0x00000012 +00000030 R_ARM_PREL31 .text.*\+0x00000014 +00000034 R_ARM_PREL31 .ARM.extab.*\+0x0000002c Contents of section .text: @@ -31,11 +33,13 @@ Contents of section .text: 0010 (04200520|20052004) .* Contents of section .ARM.extab: 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* Contents of section .ARM.exidx: 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000 .* 0010 00000000 00000000 00000000 00000000 .* 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0) .* + 0030 00000000 00000000 .* # Ignore .ARM.attributes section #... diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.d b/gas/testsuite/gas/arm/vfp-neon-overlap.d new file mode 100644 index 000000000000..b7815640089d --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-overlap.d @@ -0,0 +1,35 @@ +# name: VFP/Neon overlapping instructions +# as: -mfpu=vfp +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 diff --git a/gas/testsuite/gas/arm/vfp-neon-overlap.s b/gas/testsuite/gas/arm/vfp-neon-overlap.s new file mode 100644 index 000000000000..19c286afca43 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-overlap.s @@ -0,0 +1,41 @@ +@ VFP/Neon overlapping instructions + + .arm + .text + .syntax unified + + fmdrr d0,r0,r1 + vmov d0,r0,r1 + fmrrd r0,r1,d0 + vmov r0,r1,d0 + + @ the 'x' versions should disassemble as VFP instructions, because + @ they can't be represented in Neon syntax. + + fldmiax r0,{d0-d3} + fldmdbx r0!,{d0-d3} + fstmiax r0,{d0-d3} + fstmdbx r0!,{d0-d3} + + fldd d0,[r0] + vldr d0,[r0] + fstd d0,[r0] + vstr d0,[r0] + + fldmiad r0,{d0-d3} + vldmia r0,{d0-d3} + fldmdbd r0!,{d0-d3} + vldmdb r0!,{d0-d3} + fstmiad r0,{d0-d3} + vstmia r0,{d0-d3} + fstmdbd r0!,{d0-d3} + vstmdb r0!,{d0-d3} + + fmrdh r0,d0 + vmov.32 r0,d0[1] + fmrdl r0,d0 + vmov.32 r0,d0[0] + fmdhr d0,r0 + vmov.32 d0[1],r0 + fmdlr d0,r0 + vmov.32 d0[0],r0 diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s new file mode 100644 index 000000000000..fad0bded369c --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s @@ -0,0 +1,162 @@ +@ VFP with Neon-style syntax + .syntax unified + + .include "itblock.s" + +func: + .macro testvmov cond="" f32=".f32" f64=".f64" + itblock 4 \cond + vmov\cond\f32 s0,s1 + vmov\cond\f64 d0,d1 + vmov\cond\f32 s0,#0.25 + vmov\cond\f64 d0,#1.0 + itblock 4 \cond + vmov\cond r0,s1 + vmov\cond s0,r1 + vmov\cond r0,r1,s2,s3 + vmov\cond s0,s1,r2,r4 + .endm + + @ Test VFP vmov variants. These can all be conditional. + testvmov + testvmov eq + + .macro monadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1 + \op\cond\f64 d0,d1 + .endm + + .macro monadic_c op + monadic \op + monadic \op eq + .endm + + .macro dyadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1,s2 + \op\cond\f64 d0,d1,d2 + .endm + + .macro dyadic_c op + dyadic \op + dyadic \op eq + .endm + + .macro dyadicz op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,#0 + \op\cond\f64 d0,#0 + .endm + + .macro dyadicz_c op + dyadicz \op + dyadicz \op eq + .endm + + monadic_c vsqrt + monadic_c vabs + monadic_c vneg + monadic_c vcmp + monadic_c vcmpe + + dyadic_c vnmul + dyadic_c vnmla + dyadic_c vnmls + + dyadic_c vmul + dyadic_c vmla + dyadic_c vmls + + dyadic_c vadd + dyadic_c vsub + + dyadic_c vdiv + + dyadicz_c vcmp + dyadicz_c vcmpe + + .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvtz\cond\s32\f32 s0,s1 + vcvtz\cond\u32\f32 s0,s1 + vcvtz\cond\s32\f64 s0,d1 + vcvtz\cond\u32\f64 s0,d1 + .endm + + cvtz + cvtz eq + + .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s1 + vcvt\cond\u32\f32 s0,s1 + vcvt\cond\f32\s32 s0,s1 + vcvt\cond\f32\u32 s0,s1 + itblock 4 \cond + vcvt\cond\f32\f64 s0,d1 + vcvt\cond\f64\f32 d0,s1 + vcvt\cond\s32\f64 s0,d1 + vcvt\cond\u32\f64 s0,d1 + itblock 2 \cond + vcvt\cond\f64\s32 d0,s1 + vcvt\cond\f64\u32 d0,s1 + .endm + + cvt + cvt eq + + .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s0,#1 + vcvt\cond\u32\f32 s0,s0,#1 + vcvt\cond\f32\s32 s0,s0,#1 + vcvt\cond\f32\u32 s0,s0,#1 + itblock 4 \cond + vcvt\cond\s32\f64 d0,d0,#1 + vcvt\cond\u32\f64 d0,d0,#1 + vcvt\cond\f64\s32 d0,d0,#1 + vcvt\cond\f64\u32 d0,d0,#1 + itblock 4 \cond + vcvt\cond\f32\s16 s0,s0,#1 + vcvt\cond\f32\u16 s0,s0,#1 + vcvt\cond\f64\s16 d0,d0,#1 + vcvt\cond\f64\u16 d0,d0,#1 + itblock 4 \cond + vcvt\cond\s16\f32 s0,s0,#1 + vcvt\cond\u16\f32 s0,s0,#1 + vcvt\cond\s16\f64 d0,d0,#1 + vcvt\cond\u16\f64 d0,d0,#1 + .endm + + cvti + cvti eq + + .macro multi op cond="" n="" ia="ia" db="db" + itblock 4 \cond + \op\n\cond r0,{s3-s6} + \op\ia\cond r0,{s3-s6} + \op\ia\cond r0!,{s3-s6} + \op\db\cond r0!,{s3-s6} + itblock 4 \cond + \op\n\cond r0,{d3-d6} + \op\ia\cond r0,{d3-d6} + \op\ia\cond r0!,{d3-d6} + \op\db\cond r0!,{d3-d6} + .endm + + multi vldm + multi vldm eq + multi vstm + multi vstm eq + + .macro single op cond="" + itblock 2 \cond + \op\cond s0,[r0,#4] + \op\cond d0,[r0,#4] + .endm + + single vldr + single vldr eq + single vstr + single vstr eq diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.d b/gas/testsuite/gas/arm/vfp-neon-syntax.d new file mode 100644 index 000000000000..8d9743527bca --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.d @@ -0,0 +1,187 @@ +# name: VFP Neon-style syntax, ARM mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eeb00a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb00b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb50a00 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb70b00 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee100a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee001a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec510a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec442a10 fmsrr {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> 0eb00a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> 0eb50a00 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> 0eb70b00 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> 0e100a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> 0e001a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> 0c510a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> 0c442a10 fmsrreq {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> eeb10ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb10bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb00ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb00bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb00ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb10a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb10b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb40b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb40ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb40bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee200ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee200a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee800a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee810b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e800a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e810b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb50a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb50b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> 0eb50a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> 0eb50b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb50ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb50bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> 0eb50ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> 0eb50bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> 0ebd0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb80ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb80a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb70bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb70ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb80be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb80b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> 0eb70bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb70ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> 0eb80be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> 0eb80b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0eba0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> 0eba0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebb0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> 0ebe0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> 0ebf0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd01a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf01a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed701a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb03b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed303b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cd01a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cf01a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d701a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cb03b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d303b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc01a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece01a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed601a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca03b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed203b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cc01a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0ce01a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d601a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0ca03b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d203b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed900a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed900b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax.s b/gas/testsuite/gas/arm/vfp-neon-syntax.s new file mode 100644 index 000000000000..7c0bc633ed10 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax.s @@ -0,0 +1,2 @@ + .arm + .include "vfp-neon-syntax-inc.s" diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d new file mode 100644 index 000000000000..5c0223528583 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d @@ -0,0 +1,219 @@ +# name: VFP Neon-style syntax, Thumb mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpys s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpyd d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 fconsts s0, #80 +0[0-9a-f]+ <[^>]+> eeb7 0b00 fconstd d0, #112 +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrs r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsr s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrs r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrr {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb0 0a60 fcpyseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 fcpydeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 fconstseq s0, #80 +0[0-9a-f]+ <[^>]+> eeb7 0b00 fconstdeq d0, #112 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee10 0a90 fmrseq r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 fmsreq s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 fmrrseq r0, r1, {s2, s3} +0[0-9a-f]+ <[^>]+> ec44 2a10 fmsrreq {s0, s1}, r2, r4 +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrts s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0ae0 fsqrtseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 fsqrtdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabss s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb0 0ae0 fabsseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 fabsdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegs s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0a60 fnegseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 fnegdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmps s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpd d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0a60 fcmpseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 fcmpdeq d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpes s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmped d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0ae0 fcmpeseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 fcmpedeq d0, d1 +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0ac1 fnmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 fnmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0ac1 fnmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 fnmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0ac1 fnmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 fnmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee20 0a81 fmuls s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuld d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0a81 fmulseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 fmuldeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0a81 fmacseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 fmacdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0a81 fmscseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 fmscdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0a81 fadds s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 faddd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0a81 faddseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 fadddeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0ac1 fsubseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 fsubdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivs s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivd d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee80 0a81 fdivseq s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 fdivdeq d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzs s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0a40 fcmpzseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0b40 fcmpzdeq d0 +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezs s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezd d0 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0ac0 fcmpezseq s0 +0[0-9a-f]+ <[^>]+> eeb5 0bc0 fcmpezdeq d0 +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizs s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizs s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizd s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizd s0, d1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0ae0 ftosizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 ftouizseq s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 ftosizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 ftouizdeq s0, d1 +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosis s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouis s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitos s0, s1 +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsd s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtds d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosid s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouid s0, d1 +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitod d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitod d0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0a60 ftosiseq s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0a60 ftouiseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 fsitoseq s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 fuitoseq s0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb7 0bc1 fcvtsdeq s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 fcvtdseq d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0b41 ftosideq s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0b41 ftouideq s0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb8 0be0 fsitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 fuitodeq d0, s1 +0[0-9a-f]+ <[^>]+> eebe 0aef ftosls s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftouls s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultos s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0bef ftosld d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftould d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultod d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtos s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtos s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtod d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtod d0, #1 +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshs s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhs s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshd d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhd d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0aef ftoslseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0aef ftoulseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0aef fsltoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0aef fultoseq s0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0bef ftosldeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0bef ftouldeq d0, #1 +0[0-9a-f]+ <[^>]+> eeba 0bef fsltodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0bef fultodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeba 0a67 fshtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eebb 0a67 fuhtoseq s0, #1 +0[0-9a-f]+ <[^>]+> eeba 0b67 fshtodeq d0, #1 +0[0-9a-f]+ <[^>]+> eebb 0b67 fuhtodeq d0, #1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0a67 ftoshseq s0, #1 +0[0-9a-f]+ <[^>]+> eebf 0a67 ftouhseq s0, #1 +0[0-9a-f]+ <[^>]+> eebe 0b67 ftoshdeq d0, #1 +0[0-9a-f]+ <[^>]+> eebf 0b67 ftouhdeq d0, #1 +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 fldmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 fldmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 fldmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmias r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmias r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbs r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 fstmiaseq r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 fstmiaseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 fstmdbseq r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed90 0a01 flds s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed90 0a01 fldseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0a01 fsts s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed80 0a01 fstseq s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstreq d0, \[r0, #4\] diff --git a/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s new file mode 100644 index 000000000000..00f78d01cef7 --- /dev/null +++ b/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "vfp-neon-syntax-inc.s" diff --git a/gas/testsuite/gas/arm/vfp1.d b/gas/testsuite/gas/arm/vfp1.d index 672b23de31d5..3894909539bb 100644 --- a/gas/testsuite/gas/arm/vfp1.d +++ b/gas/testsuite/gas/arm/vfp1.d @@ -24,20 +24,20 @@ Disassembly of section .text: 0+038 <[^>]*> ee100b40 fnmscd d0, d0, d0 0+03c <[^>]*> ee200b40 fnmuld d0, d0, d0 0+040 <[^>]*> ee300b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed900b00 fldd d0, \[r0\] -0+048 <[^>]*> ed800b00 fstd d0, \[r0\] -0+04c <[^>]*> ec900b02 fldmiad r0, {d0} -0+050 <[^>]*> ec900b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec800b02 fstmiad r0, {d0} -0+068 <[^>]*> ec800b02 fstmiad r0, {d0} -0+06c <[^>]*> eca00b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca00b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed200b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed200b02 fstmdbd r0!, {d0} +0+044 <[^>]*> ed900b00 vldr d0, \[r0\] +0+048 <[^>]*> ed800b00 vstr d0, \[r0\] +0+04c <[^>]*> ec900b02 vldmia r0, {d0} +0+050 <[^>]*> ec900b02 vldmia r0, {d0} +0+054 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+05c <[^>]*> ed300b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed300b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec800b02 vstmia r0, {d0} +0+068 <[^>]*> ec800b02 vstmia r0, {d0} +0+06c <[^>]*> eca00b02 vstmia r0!, {d0} +0+070 <[^>]*> eca00b02 vstmia r0!, {d0} +0+074 <[^>]*> ed200b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed200b02 vstmdb r0!, {d0} 0+07c <[^>]*> eeb80bc0 fsitod d0, s0 0+080 <[^>]*> eeb80b40 fuitod d0, s0 0+084 <[^>]*> eebd0b40 ftosid s0, d0 @@ -46,10 +46,10 @@ Disassembly of section .text: 0+090 <[^>]*> eebc0bc0 ftouizd s0, d0 0+094 <[^>]*> eeb70ac0 fcvtds d0, s0 0+098 <[^>]*> eeb70bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee300b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee100b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee200b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee000b10 fmdlr d0, r0 +0+09c <[^>]*> ee300b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee100b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee200b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee000b10 vmov\.32 d0\[0\], r0 0+0ac <[^>]*> eeb51b40 fcmpzd d1 0+0b0 <[^>]*> eeb52b40 fcmpzd d2 0+0b4 <[^>]*> eeb5fb40 fcmpzd d15 @@ -89,46 +89,46 @@ Disassembly of section .text: 0+13c <[^>]*> eeb70bc1 fcvtsd s0, d1 0+140 <[^>]*> eeb70bc2 fcvtsd s0, d2 0+144 <[^>]*> eeb70bcf fcvtsd s0, d15 -0+148 <[^>]*> ee301b10 fmrdh r1, d0 -0+14c <[^>]*> ee30eb10 fmrdh lr, d0 -0+150 <[^>]*> ee310b10 fmrdh r0, d1 -0+154 <[^>]*> ee320b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f0b10 fmrdh r0, d15 -0+15c <[^>]*> ee101b10 fmrdl r1, d0 -0+160 <[^>]*> ee10eb10 fmrdl lr, d0 -0+164 <[^>]*> ee110b10 fmrdl r0, d1 -0+168 <[^>]*> ee120b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f0b10 fmrdl r0, d15 -0+170 <[^>]*> ee201b10 fmdhr d0, r1 -0+174 <[^>]*> ee20eb10 fmdhr d0, lr -0+178 <[^>]*> ee210b10 fmdhr d1, r0 -0+17c <[^>]*> ee220b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f0b10 fmdhr d15, r0 -0+184 <[^>]*> ee001b10 fmdlr d0, r1 -0+188 <[^>]*> ee00eb10 fmdlr d0, lr -0+18c <[^>]*> ee010b10 fmdlr d1, r0 -0+190 <[^>]*> ee020b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f0b10 fmdlr d15, r0 -0+198 <[^>]*> ed910b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed900b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed900bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed100bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed901b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed902b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8ccbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec901b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec902b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec900b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec900b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec900b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec901b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec902b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec910b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e0b02 fldmiad lr, {d0} +0+148 <[^>]*> ee301b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee310b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee320b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee101b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee110b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee120b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee201b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee210b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee220b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee001b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee010b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee020b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed910b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\] +0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\] +0+1ac <[^>]*> ed901b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\] +0+1bc <[^>]*> ec901b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec902b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec900b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec900b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec900b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec901b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec902b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec910b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e0b02 vldmia lr, {d0} 0+1e8 <[^>]*> eeb50b40 fcmpzd d0 0+1ec <[^>]*> eeb51b40 fcmpzd d1 0+1f0 <[^>]*> eeb52b40 fcmpzd d2 @@ -162,20 +162,20 @@ Disassembly of section .text: 0+260 <[^>]*> 0e167b4b fnmscdeq d7, d6, d11 0+264 <[^>]*> 0e245b4c fnmuldeq d5, d4, d12 0+268 <[^>]*> 0e3d3b4e fsubdeq d3, d13, d14 -0+26c <[^>]*> 0d952b00 flddeq d2, \[r5\] -0+270 <[^>]*> 0d8c1b00 fstdeq d1, \[ip\] -0+274 <[^>]*> 0c911b02 fldmiadeq r1, {d1} -0+278 <[^>]*> 0c922b02 fldmiadeq r2, {d2} -0+27c <[^>]*> 0cb33b02 fldmiadeq r3!, {d3} -0+280 <[^>]*> 0cb44b02 fldmiadeq r4!, {d4} -0+284 <[^>]*> 0d355b02 fldmdbdeq r5!, {d5} -0+288 <[^>]*> 0d366b02 fldmdbdeq r6!, {d6} -0+28c <[^>]*> 0c87fb02 fstmiadeq r7, {d15} -0+290 <[^>]*> 0c88eb02 fstmiadeq r8, {d14} -0+294 <[^>]*> 0ca9db02 fstmiadeq r9!, {d13} -0+298 <[^>]*> 0caacb02 fstmiadeq sl!, {d12} -0+29c <[^>]*> 0d2bbb02 fstmdbdeq fp!, {d11} -0+2a0 <[^>]*> 0d2cab02 fstmdbdeq ip!, {d10} +0+26c <[^>]*> 0d952b00 vldreq d2, \[r5\] +0+270 <[^>]*> 0d8c1b00 vstreq d1, \[ip\] +0+274 <[^>]*> 0c911b02 vldmiaeq r1, {d1} +0+278 <[^>]*> 0c922b02 vldmiaeq r2, {d2} +0+27c <[^>]*> 0cb33b02 vldmiaeq r3!, {d3} +0+280 <[^>]*> 0cb44b02 vldmiaeq r4!, {d4} +0+284 <[^>]*> 0d355b02 vldmdbeq r5!, {d5} +0+288 <[^>]*> 0d366b02 vldmdbeq r6!, {d6} +0+28c <[^>]*> 0c87fb02 vstmiaeq r7, {d15} +0+290 <[^>]*> 0c88eb02 vstmiaeq r8, {d14} +0+294 <[^>]*> 0ca9db02 vstmiaeq r9!, {d13} +0+298 <[^>]*> 0caacb02 vstmiaeq sl!, {d12} +0+29c <[^>]*> 0d2bbb02 vstmdbeq fp!, {d11} +0+2a0 <[^>]*> 0d2cab02 vstmdbeq ip!, {d10} 0+2a4 <[^>]*> 0eb8fbe0 fsitodeq d15, s1 0+2a8 <[^>]*> 0eb81b6f fuitodeq d1, s31 0+2ac <[^>]*> 0efd0b4f ftosideq s1, d15 @@ -184,10 +184,10 @@ Disassembly of section .text: 0+2b8 <[^>]*> 0efc5bc3 ftouizdeq s11, d3 0+2bc <[^>]*> 0eb71ac5 fcvtdseq d1, s10 0+2c0 <[^>]*> 0ef75bc1 fcvtsdeq s11, d1 -0+2c4 <[^>]*> 0e318b10 fmrdheq r8, d1 -0+2c8 <[^>]*> 0e1f7b10 fmrdleq r7, d15 -0+2cc <[^>]*> 0e21fb10 fmdhreq d1, pc -0+2d0 <[^>]*> 0e0f1b10 fmdlreq d15, r1 +0+2c4 <[^>]*> 0e318b10 vmoveq\.32 r8, d1\[1\] +0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\] +0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc +0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1 0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) 0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) 0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d index 22c4fd6f01dc..3bf1f9a9d74b 100644 --- a/gas/testsuite/gas/arm/vfp1_t2.d +++ b/gas/testsuite/gas/arm/vfp1_t2.d @@ -24,20 +24,20 @@ Disassembly of section .text: 0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0 0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0 0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\] -0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} +0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\] +0+04c <[^>]*> ec90 0b02 vldmia r0, {d0} +0+050 <[^>]*> ec90 0b02 vldmia r0, {d0} +0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+068 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0} 0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0 0+080 <[^>]*> eeb8 0b40 fuitod d0, s0 0+084 <[^>]*> eebd 0b40 ftosid s0, d0 @@ -46,10 +46,10 @@ Disassembly of section .text: 0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0 0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0 0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee30 0b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0 +0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0 0+0ac <[^>]*> eeb5 1b40 fcmpzd d1 0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2 0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15 @@ -89,46 +89,46 @@ Disassembly of section .text: 0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1 0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2 0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15 -0+148 <[^>]*> ee30 1b10 fmrdh r1, d0 -0+14c <[^>]*> ee30 eb10 fmrdh lr, d0 -0+150 <[^>]*> ee31 0b10 fmrdh r0, d1 -0+154 <[^>]*> ee32 0b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15 -0+15c <[^>]*> ee10 1b10 fmrdl r1, d0 -0+160 <[^>]*> ee10 eb10 fmrdl lr, d0 -0+164 <[^>]*> ee11 0b10 fmrdl r0, d1 -0+168 <[^>]*> ee12 0b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15 -0+170 <[^>]*> ee20 1b10 fmdhr d0, r1 -0+174 <[^>]*> ee20 eb10 fmdhr d0, lr -0+178 <[^>]*> ee21 0b10 fmdhr d1, r0 -0+17c <[^>]*> ee22 0b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0 -0+184 <[^>]*> ee00 1b10 fmdlr d0, r1 -0+188 <[^>]*> ee00 eb10 fmdlr d0, lr -0+18c <[^>]*> ee01 0b10 fmdlr d1, r0 -0+190 <[^>]*> ee02 0b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0 -0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0} +0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\] +0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\] +0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\] +0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0} 0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0 0+1ec <[^>]*> eeb5 1b40 fcmpzd d1 0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2 @@ -145,61 +145,60 @@ Disassembly of section .text: 0+21c <[^>]*> eeb5 db40 fcmpzd d13 0+220 <[^>]*> eeb5 eb40 fcmpzd d14 0+224 <[^>]*> eeb5 fb40 fcmpzd d15 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. 0+228 <[^>]*> bf01 itttt eq -0+22a <[^>]*> eeb4 1bcf fcmped(eq|) d1, d15 -0+22e <[^>]*> eeb5 2bc0 fcmpezd(eq|) d2 -0+232 <[^>]*> eeb4 3b4e fcmpd(eq|) d3, d14 -0+236 <[^>]*> eeb5 4b40 fcmpzd(eq|) d4 +0+22a <[^>]*> eeb4 1bcf fcmpedeq d1, d15 +0+22e <[^>]*> eeb5 2bc0 fcmpezdeq d2 +0+232 <[^>]*> eeb4 3b4e fcmpdeq d3, d14 +0+236 <[^>]*> eeb5 4b40 fcmpzdeq d4 0+23a <[^>]*> bf01 itttt eq -0+23c <[^>]*> eeb0 5bcd fabsd(eq|) d5, d13 -0+240 <[^>]*> eeb0 6b4c fcpyd(eq|) d6, d12 -0+244 <[^>]*> eeb1 7b4b fnegd(eq|) d7, d11 -0+248 <[^>]*> eeb1 8bca fsqrtd(eq|) d8, d10 +0+23c <[^>]*> eeb0 5bcd fabsdeq d5, d13 +0+240 <[^>]*> eeb0 6b4c fcpydeq d6, d12 +0+244 <[^>]*> eeb1 7b4b fnegdeq d7, d11 +0+248 <[^>]*> eeb1 8bca fsqrtdeq d8, d10 0+24c <[^>]*> bf01 itttt eq -0+24e <[^>]*> ee31 9b0f faddd(eq|) d9, d1, d15 -0+252 <[^>]*> ee83 2b0e fdivd(eq|) d2, d3, d14 -0+256 <[^>]*> ee0d 4b0c fmacd(eq|) d4, d13, d12 -0+25a <[^>]*> ee16 5b0b fmscd(eq|) d5, d6, d11 +0+24e <[^>]*> ee31 9b0f fadddeq d9, d1, d15 +0+252 <[^>]*> ee83 2b0e fdivdeq d2, d3, d14 +0+256 <[^>]*> ee0d 4b0c fmacdeq d4, d13, d12 +0+25a <[^>]*> ee16 5b0b fmscdeq d5, d6, d11 0+25e <[^>]*> bf01 itttt eq -0+260 <[^>]*> ee2a 7b09 fmuld(eq|) d7, d10, d9 -0+264 <[^>]*> ee09 8b4a fnmacd(eq|) d8, d9, d10 -0+268 <[^>]*> ee16 7b4b fnmscd(eq|) d7, d6, d11 -0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12 +0+260 <[^>]*> ee2a 7b09 fmuldeq d7, d10, d9 +0+264 <[^>]*> ee09 8b4a fnmacdeq d8, d9, d10 +0+268 <[^>]*> ee16 7b4b fnmscdeq d7, d6, d11 +0+26c <[^>]*> ee24 5b4c fnmuldeq d5, d4, d12 0+270 <[^>]*> bf02 ittt eq -0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14 -0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\] -0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\] +0+272 <[^>]*> ee3d 3b4e fsubdeq d3, d13, d14 +0+276 <[^>]*> ed95 2b00 vldreq d2, \[r5\] +0+27a <[^>]*> ed8c 1b00 vstreq d1, \[ip\] 0+27e <[^>]*> bf01 itttt eq -0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1} -0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2} -0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3} -0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4} +0+280 <[^>]*> ec91 1b02 vldmiaeq r1, {d1} +0+284 <[^>]*> ec92 2b02 vldmiaeq r2, {d2} +0+288 <[^>]*> ecb3 3b02 vldmiaeq r3!, {d3} +0+28c <[^>]*> ecb4 4b02 vldmiaeq r4!, {d4} 0+290 <[^>]*> bf01 itttt eq -0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5} -0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6} -0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15} -0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14} +0+292 <[^>]*> ed35 5b02 vldmdbeq r5!, {d5} +0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6} +0+29a <[^>]*> ec87 fb02 vstmiaeq r7, {d15} +0+29e <[^>]*> ec88 eb02 vstmiaeq r8, {d14} 0+2a2 <[^>]*> bf01 itttt eq -0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13} -0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12} -0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11} -0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10} +0+2a4 <[^>]*> eca9 db02 vstmiaeq r9!, {d13} +0+2a8 <[^>]*> ecaa cb02 vstmiaeq sl!, {d12} +0+2ac <[^>]*> ed2b bb02 vstmdbeq fp!, {d11} +0+2b0 <[^>]*> ed2c ab02 vstmdbeq ip!, {d10} 0+2b4 <[^>]*> bf01 itttt eq -0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1 -0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31 -0+2be <[^>]*> eefd 0b4f ftosid(eq|) s1, d15 -0+2c2 <[^>]*> eefd fbc2 ftosizd(eq|) s31, d2 +0+2b6 <[^>]*> eeb8 fbe0 fsitodeq d15, s1 +0+2ba <[^>]*> eeb8 1b6f fuitodeq d1, s31 +0+2be <[^>]*> eefd 0b4f ftosideq s1, d15 +0+2c2 <[^>]*> eefd fbc2 ftosizdeq s31, d2 0+2c6 <[^>]*> bf01 itttt eq -0+2c8 <[^>]*> eefc 7b42 ftouid(eq|) s15, d2 -0+2cc <[^>]*> eefc 5bc3 ftouizd(eq|) s11, d3 -0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10 -0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1 +0+2c8 <[^>]*> eefc 7b42 ftouideq s15, d2 +0+2cc <[^>]*> eefc 5bc3 ftouizdeq s11, d3 +0+2d0 <[^>]*> eeb7 1ac5 fcvtdseq d1, s10 +0+2d4 <[^>]*> eef7 5bc1 fcvtsdeq s11, d1 0+2d8 <[^>]*> bf01 itttt eq -0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1 -0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15 -0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc -0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1 +0+2da <[^>]*> ee31 8b10 vmoveq\.32 r8, d1\[1\] +0+2de <[^>]*> ee1f 7b10 vmoveq\.32 r7, d15\[0\] +0+2e2 <[^>]*> ee21 fb10 vmoveq\.32 d1\[1\], pc +0+2e6 <[^>]*> ee0f 1b10 vmoveq\.32 d15\[0\], r1 0+2ea <[^>]*> bf00 nop 0+2ec <[^>]*> bf00 nop 0+2ee <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d index 096b46c86e4c..22932e5284c0 100644 --- a/gas/testsuite/gas/arm/vfp1xD.d +++ b/gas/testsuite/gas/arm/vfp1xD.d @@ -239,3 +239,15 @@ Disassembly of section .text: 0+394 <[^>]*> 0ef09a10 fmrxeq r9, fpsid 0+398 <[^>]*> 0e019a90 fmsreq s3, r9 0+39c <[^>]*> 0ee08a10 fmxreq fpsid, r8 +0+3a0 <[^>]*> eef90a10 fmrx r0, fpinst @ Impl def +0+3a4 <[^>]*> eefa0a10 fmrx r0, fpinst2 @ Impl def +0+3a8 <[^>]*> eef70a10 fmrx r0, mvfr0 +0+3ac <[^>]*> eef60a10 fmrx r0, mvfr1 +0+3b0 <[^>]*> eefc0a10 fmrx r0, <impl def 0xc> +0+3b4 <[^>]*> eee90a10 fmxr fpinst, r0 @ Impl def +0+3b8 <[^>]*> eeea0a10 fmxr fpinst2, r0 @ Impl def +0+3bc <[^>]*> eee70a10 fmxr mvfr0, r0 +0+3c0 <[^>]*> eee60a10 fmxr mvfr1, r0 +0+3c4 <[^>]*> eeec0a10 fmxr <impl def 0xc>, r0 +0+3c8 <[^>]*> e1a00000 nop \(mov r0,r0\) +0+3cc <[^>]*> e1a00000 nop \(mov r0,r0\) diff --git a/gas/testsuite/gas/arm/vfp1xD.s b/gas/testsuite/gas/arm/vfp1xD.s index 82f080f499b0..ecc022638158 100644 --- a/gas/testsuite/gas/arm/vfp1xD.s +++ b/gas/testsuite/gas/arm/vfp1xD.s @@ -337,3 +337,17 @@ F: fmsreq s3, r9 fmxreq fpsid, r8 + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + nop + nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d index 327383d01c5b..d2943114d6c0 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.d +++ b/gas/testsuite/gas/arm/vfp1xD_t2.d @@ -185,74 +185,87 @@ Disassembly of section .text: 0+2bc <[^>]*> eef5 ea40 fcmpzs s29 0+2c0 <[^>]*> eeb5 fa40 fcmpzs s30 0+2c4 <[^>]*> eef5 fa40 fcmpzs s31 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. 0+2c8 <[^>]*> bf01 itttt eq -0+2ca <[^>]*> eef1 fa10 fmstat(eq|) -0+2ce <[^>]*> eef4 1ae3 fcmpes(eq|) s3, s7 -0+2d2 <[^>]*> eef5 2ac0 fcmpezs(eq|) s5 -0+2d6 <[^>]*> eef4 0a41 fcmps(eq|) s1, s2 +0+2ca <[^>]*> eef1 fa10 fmstateq +0+2ce <[^>]*> eef4 1ae3 fcmpeseq s3, s7 +0+2d2 <[^>]*> eef5 2ac0 fcmpezseq s5 +0+2d6 <[^>]*> eef4 0a41 fcmpseq s1, s2 0+2da <[^>]*> bf01 itttt eq -0+2dc <[^>]*> eef5 0a40 fcmpzs(eq|) s1 -0+2e0 <[^>]*> eef0 0ae1 fabss(eq|) s1, s3 -0+2e4 <[^>]*> eef0 fa69 fcpys(eq|) s31, s19 -0+2e8 <[^>]*> eeb1 aa44 fnegs(eq|) s20, s8 +0+2dc <[^>]*> eef5 0a40 fcmpzseq s1 +0+2e0 <[^>]*> eef0 0ae1 fabsseq s1, s3 +0+2e4 <[^>]*> eef0 fa69 fcpyseq s31, s19 +0+2e8 <[^>]*> eeb1 aa44 fnegseq s20, s8 0+2ec <[^>]*> bf01 itttt eq -0+2ee <[^>]*> eef1 2ae3 fsqrts(eq|) s5, s7 -0+2f2 <[^>]*> ee32 3a82 fadds(eq|) s6, s5, s4 -0+2f6 <[^>]*> eec1 1a20 fdivs(eq|) s3, s2, s1 -0+2fa <[^>]*> ee4f fa2e fmacs(eq|) s31, s30, s29 +0+2ee <[^>]*> eef1 2ae3 fsqrtseq s5, s7 +0+2f2 <[^>]*> ee32 3a82 faddseq s6, s5, s4 +0+2f6 <[^>]*> eec1 1a20 fdivseq s3, s2, s1 +0+2fa <[^>]*> ee4f fa2e fmacseq s31, s30, s29 0+2fe <[^>]*> bf01 itttt eq -0+300 <[^>]*> ee1d ea8d fmscs(eq|) s28, s27, s26 -0+304 <[^>]*> ee6c ca2b fmuls(eq|) s25, s24, s23 -0+308 <[^>]*> ee0a baca fnmacs(eq|) s22, s21, s20 -0+30c <[^>]*> ee59 9a68 fnmscs(eq|) s19, s18, s17 +0+300 <[^>]*> ee1d ea8d fmscseq s28, s27, s26 +0+304 <[^>]*> ee6c ca2b fmulseq s25, s24, s23 +0+308 <[^>]*> ee0a baca fnmacseq s22, s21, s20 +0+30c <[^>]*> ee59 9a68 fnmscseq s19, s18, s17 0+310 <[^>]*> bf01 itttt eq -0+312 <[^>]*> ee27 8ac7 fnmuls(eq|) s16, s15, s14 -0+316 <[^>]*> ee76 6a65 fsubs(eq|) s13, s12, s11 -0+31a <[^>]*> ed98 5a00 flds(eq|) s10, \[r8\] -0+31e <[^>]*> edc7 4a00 fsts(eq|) s9, \[r7\] +0+312 <[^>]*> ee27 8ac7 fnmulseq s16, s15, s14 +0+316 <[^>]*> ee76 6a65 fsubseq s13, s12, s11 +0+31a <[^>]*> ed98 5a00 fldseq s10, \[r8\] +0+31e <[^>]*> edc7 4a00 fstseq s9, \[r7\] 0+322 <[^>]*> bf01 itttt eq -0+324 <[^>]*> ec91 4a01 fldmias(eq|) r1, {s8} -0+328 <[^>]*> ecd2 3a01 fldmias(eq|) r2, {s7} -0+32c <[^>]*> ecb3 3a01 fldmias(eq|) r3!, {s6} -0+330 <[^>]*> ecf4 2a01 fldmias(eq|) r4!, {s5} +0+324 <[^>]*> ec91 4a01 fldmiaseq r1, {s8} +0+328 <[^>]*> ecd2 3a01 fldmiaseq r2, {s7} +0+32c <[^>]*> ecb3 3a01 fldmiaseq r3!, {s6} +0+330 <[^>]*> ecf4 2a01 fldmiaseq r4!, {s5} 0+334 <[^>]*> bf01 itttt eq -0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4} -0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3} -0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1} -0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2} +0+336 <[^>]*> ed35 2a01 fldmdbseq r5!, {s4} +0+33a <[^>]*> ed76 1a01 fldmdbseq r6!, {s3} +0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1} +0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2} 0+346 <[^>]*> bf01 itttt eq -0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3} -0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4} -0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5} -0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6} +0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3} +0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4} +0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5} +0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6} 0+358 <[^>]*> bf01 itttt eq -0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2} -0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1} -0+362 <[^>]*> ece1 fa01 fstmias(eq|) r1!, {s31} -0+366 <[^>]*> eca2 fa01 fstmias(eq|) r2!, {s30} +0+35a <[^>]*> ec8d 1a01 fstmiaseq sp, {s2} +0+35e <[^>]*> ecce 0a01 fstmiaseq lr, {s1} +0+362 <[^>]*> ece1 fa01 fstmiaseq r1!, {s31} +0+366 <[^>]*> eca2 fa01 fstmiaseq r2!, {s30} 0+36a <[^>]*> bf01 itttt eq -0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29} -0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28} -0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7} -0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8} +0+36c <[^>]*> ed63 ea01 fstmdbseq r3!, {s29} +0+370 <[^>]*> ed24 ea01 fstmdbseq r4!, {s28} +0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7} +0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8} 0+37c <[^>]*> bf01 itttt eq -0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9} -0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10} -0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11} -0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12} +0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9} +0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10} +0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11} +0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12} 0+38e <[^>]*> bf01 itttt eq -0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6 -0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5 -0+398 <[^>]*> eefd bac2 ftosizs(eq|) s23, s4 -0+39c <[^>]*> eefc aa61 ftouis(eq|) s21, s3 +0+390 <[^>]*> eef8 dac3 fsitoseq s27, s6 +0+394 <[^>]*> eefd ca62 ftosiseq s25, s5 +0+398 <[^>]*> eefd bac2 ftosizseq s23, s4 +0+39c <[^>]*> eefc aa61 ftouiseq s21, s3 0+3a0 <[^>]*> bf01 itttt eq -0+3a2 <[^>]*> eefc 9ac1 ftouizs(eq|) s19, s2 -0+3a6 <[^>]*> eef8 8a60 fuitos(eq|) s17, s1 -0+3aa <[^>]*> ee11 ba90 fmrs(eq|) fp, s3 -0+3ae <[^>]*> eef0 9a10 fmrx(eq|) r9, fpsid +0+3a2 <[^>]*> eefc 9ac1 ftouizseq s19, s2 +0+3a6 <[^>]*> eef8 8a60 fuitoseq s17, s1 +0+3aa <[^>]*> ee11 ba90 fmrseq fp, s3 +0+3ae <[^>]*> eef0 9a10 fmrxeq r9, fpsid 0+3b2 <[^>]*> bf04 itt eq -0+3b4 <[^>]*> ee01 9a90 fmsr(eq|) s3, r9 -0+3b8 <[^>]*> eee0 8a10 fmxr(eq|) fpsid, r8 -0+3bc <[^>]*> bf00 nop -0+3be <[^>]*> bf00 nop +0+3b4 <[^>]*> ee01 9a90 fmsreq s3, r9 +0+3b8 <[^>]*> eee0 8a10 fmxreq fpsid, r8 +0+3bc <[^>]*> eef9 0a10 fmrx r0, fpinst @ Impl def +0+3c0 <[^>]*> eefa 0a10 fmrx r0, fpinst2 @ Impl def +0+3c4 <[^>]*> eef7 0a10 fmrx r0, mvfr0 +0+3c8 <[^>]*> eef6 0a10 fmrx r0, mvfr1 +0+3cc <[^>]*> eefc 0a10 fmrx r0, <impl def 0xc> +0+3d0 <[^>]*> eee9 0a10 fmxr fpinst, r0 @ Impl def +0+3d4 <[^>]*> eeea 0a10 fmxr fpinst2, r0 @ Impl def +0+3d8 <[^>]*> eee7 0a10 fmxr mvfr0, r0 +0+3dc <[^>]*> eee6 0a10 fmxr mvfr1, r0 +0+3e0 <[^>]*> eeec 0a10 fmxr <impl def 0xc>, r0 +0+3e4 <[^>]*> bf00 nop +0+3e6 <[^>]*> bf00 nop +0+3e8 <[^>]*> bf00 nop +0+3ea <[^>]*> bf00 nop +0+3ec <[^>]*> bf00 nop +0+3ee <[^>]*> bf00 nop diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s index f3087a37ee96..8e962c07e3e9 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.s +++ b/gas/testsuite/gas/arm/vfp1xD_t2.s @@ -354,6 +354,21 @@ F: fmsreq s3, r9 fmxreq fpsid, r8 - @ 2 nops to pad to 16-byte boundary + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + nop + nop + nop + nop nop nop diff --git a/gas/testsuite/gas/arm/vfp2.d b/gas/testsuite/gas/arm/vfp2.d index f9b6096081eb..438019fc12ed 100644 --- a/gas/testsuite/gas/arm/vfp2.d +++ b/gas/testsuite/gas/arm/vfp2.d @@ -7,11 +7,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16} +0+000 <[^>]*> ec4a5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a5a37 fmsrr {s15, s16}, r5, sl 0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18} +0+010 <[^>]*> ec45ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45aa38 fmsrr {s17, s18}, sl, r5 0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18} diff --git a/gas/testsuite/gas/arm/vfp2_t2.d b/gas/testsuite/gas/arm/vfp2_t2.d index bb988e5472e2..f07b6a58bcba 100644 --- a/gas/testsuite/gas/arm/vfp2_t2.d +++ b/gas/testsuite/gas/arm/vfp2_t2.d @@ -7,11 +7,11 @@ .*: +file format .*arm.* Disassembly of section .text: -0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16} +0+000 <[^>]*> ec4a 5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a 5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a 5a37 fmsrr {s15, s16}, r5, sl 0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18} +0+010 <[^>]*> ec45 ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55 ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45 aa38 fmsrr {s17, s18}, sl, r5 0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18} diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.d b/gas/testsuite/gas/arm/vfpv3-32drs.d new file mode 100644 index 000000000000..f42c373f4c3d --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-32drs.d @@ -0,0 +1,73 @@ +# name: VFPv3 extra D registers +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb03b66 fcpyd d3, d22 +0[0-9a-f]+ <[^>]+> eef06b43 fcpyd d22, d3 +0[0-9a-f]+ <[^>]+> eef76acb fcvtds d22, s22 +0[0-9a-f]+ <[^>]+> eeb7bbe6 fcvtsd s22, d22 +0[0-9a-f]+ <[^>]+> ee254b90 vmov\.32 d21\[1\], r4 +0[0-9a-f]+ <[^>]+> ee0b5b90 vmov\.32 d27\[0\], r5 +0[0-9a-f]+ <[^>]+> ee376b90 vmov\.32 r6, d23\[1\] +0[0-9a-f]+ <[^>]+> ee197b90 vmov\.32 r7, d25\[0\] +0[0-9a-f]+ <[^>]+> eef86bcb fsitod d22, s22 +0[0-9a-f]+ <[^>]+> eef85b6a fuitod d21, s21 +0[0-9a-f]+ <[^>]+> eebdab64 ftosid s20, d20 +0[0-9a-f]+ <[^>]+> eebdabe4 ftosizd s20, d20 +0[0-9a-f]+ <[^>]+> eefc9b63 ftouid s19, d19 +0[0-9a-f]+ <[^>]+> eefc9be3 ftouizd s19, d19 +0[0-9a-f]+ <[^>]+> edda3b01 vldr d19, \[sl, #4\] +0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\] +0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6} +0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20} +0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6} +0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20} +0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19} +0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24} +0[0-9a-f]+ <[^>]+> eeb03bc5 fabsd d3, d5 +0[0-9a-f]+ <[^>]+> eeb0cbe2 fabsd d12, d18 +0[0-9a-f]+ <[^>]+> eef02be3 fabsd d18, d19 +0[0-9a-f]+ <[^>]+> eeb13b45 fnegd d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cb62 fnegd d12, d18 +0[0-9a-f]+ <[^>]+> eef12b63 fnegd d18, d19 +0[0-9a-f]+ <[^>]+> eeb13bc5 fsqrtd d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cbe2 fsqrtd d12, d18 +0[0-9a-f]+ <[^>]+> eef12be3 fsqrtd d18, d19 +0[0-9a-f]+ <[^>]+> ee353b06 faddd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cb84 faddd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732ba4 faddd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee353b46 fsubd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cbc4 fsubd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732be4 fsubd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b06 fmuld d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cb84 fmuld d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632ba4 fmuld d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee853b06 fdivd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee82cb84 fdivd d12, d18, d4 +0[0-9a-f]+ <[^>]+> eec32ba4 fdivd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b06 fmacd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cb84 fmacd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432ba4 fmacd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b06 fmscd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cb84 fmscd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532ba4 fmscd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b46 fnmuld d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cbc4 fnmuld d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632be4 fnmuld d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b46 fnmacd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cbc4 fnmacd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432be4 fnmacd d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b46 fnmscd d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cbc4 fnmscd d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532be4 fnmscd d18, d19, d20 +0[0-9a-f]+ <[^>]+> eeb43b62 fcmpd d3, d18 +0[0-9a-f]+ <[^>]+> eef42b43 fcmpd d18, d3 +0[0-9a-f]+ <[^>]+> eef53b40 fcmpzd d19 +0[0-9a-f]+ <[^>]+> eeb43be2 fcmped d3, d18 +0[0-9a-f]+ <[^>]+> eef42bc3 fcmped d18, d3 +0[0-9a-f]+ <[^>]+> eef53bc0 fcmpezd d19 +0[0-9a-f]+ <[^>]+> ec443b3f vmov d31, r3, r4 +0[0-9a-f]+ <[^>]+> ec565b3e vmov r5, r6, d30 diff --git a/gas/testsuite/gas/arm/vfpv3-32drs.s b/gas/testsuite/gas/arm/vfpv3-32drs.s new file mode 100644 index 000000000000..ef72c24eb5ad --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-32drs.s @@ -0,0 +1,68 @@ +.arm +.syntax unified + fcpyd d3,d22 + fcpyd d22,d3 + fcvtds d22,s22 + fcvtsd s22,d22 + fmdhr d21,r4 + fmdlr d27,r5 + fmrdh r6,d23 + fmrdl r7,d25 + fsitod d22,s22 + fuitod d21,s21 + ftosid s20,d20 + ftosizd s20,d20 + ftouid s19,d19 + ftouizd s19,d19 + fldd d19,[r10,#4] + fstd d21,[r10,#4] + fldmiad r10!,{d5,d6} + fldmiad r10!,{d18,d19,d20} + fldmiax r10!,{d5,d6} + fldmiax r10!,{d18,d19,d20} + fldmdbx r10!,{d18,d19} + fstmiad r9,{d20,d21,d22,d23,d24} + fabsd d3,d5 + fabsd d12,d18 + fabsd d18,d19 + fnegd d3,d5 + fnegd d12,d18 + fnegd d18,d19 + fsqrtd d3,d5 + fsqrtd d12,d18 + fsqrtd d18,d19 + faddd d3,d5,d6 + faddd d12,d18,d4 + faddd d18,d19,d20 + fsubd d3,d5,d6 + fsubd d12,d18,d4 + fsubd d18,d19,d20 + fmuld d3,d5,d6 + fmuld d12,d18,d4 + fmuld d18,d19,d20 + fdivd d3,d5,d6 + fdivd d12,d18,d4 + fdivd d18,d19,d20 + fmacd d3,d5,d6 + fmacd d12,d18,d4 + fmacd d18,d19,d20 + fmscd d3,d5,d6 + fmscd d12,d18,d4 + fmscd d18,d19,d20 + fnmuld d3,d5,d6 + fnmuld d12,d18,d4 + fnmuld d18,d19,d20 + fnmacd d3,d5,d6 + fnmacd d12,d18,d4 + fnmacd d18,d19,d20 + fnmscd d3,d5,d6 + fnmscd d12,d18,d4 + fnmscd d18,d19,d20 + fcmpd d3,d18 + fcmpd d18,d3 + fcmpzd d19 + fcmped d3,d18 + fcmped d18,d3 + fcmpezd d19 + fmdrr d31,r3,r4 + fmrrd r5,r6,d30 diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.d b/gas/testsuite/gas/arm/vfpv3-const-conv.d new file mode 100644 index 000000000000..9515feff7133 --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-const-conv.d @@ -0,0 +1,29 @@ +# name: VFPv3 additional constant and conversion ops +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eef08a04 fconsts s17, #4 +0[0-9a-f]+ <[^>]+> eeba9a05 fconsts s18, #165 +0[0-9a-f]+ <[^>]+> eef49a00 fconsts s19, #64 +0[0-9a-f]+ <[^>]+> eef01b04 fconstd d17, #4 +0[0-9a-f]+ <[^>]+> eefa2b05 fconstd d18, #165 +0[0-9a-f]+ <[^>]+> eef43b00 fconstd d19, #64 +0[0-9a-f]+ <[^>]+> eefa8a63 fshtos s17, #9 +0[0-9a-f]+ <[^>]+> eefa1b63 fshtod d17, #9 +0[0-9a-f]+ <[^>]+> eefa8aeb fsltos s17, #9 +0[0-9a-f]+ <[^>]+> eefa1beb fsltod d17, #9 +0[0-9a-f]+ <[^>]+> eefb8a63 fuhtos s17, #9 +0[0-9a-f]+ <[^>]+> eefb1b63 fuhtod d17, #9 +0[0-9a-f]+ <[^>]+> eefb8aeb fultos s17, #9 +0[0-9a-f]+ <[^>]+> eefb1beb fultod d17, #9 +0[0-9a-f]+ <[^>]+> eefe9a64 ftoshs s19, #7 +0[0-9a-f]+ <[^>]+> eefe3b64 ftoshd d19, #7 +0[0-9a-f]+ <[^>]+> eefe9aec ftosls s19, #7 +0[0-9a-f]+ <[^>]+> eefe3bec ftosld d19, #7 +0[0-9a-f]+ <[^>]+> eeff9a64 ftouhs s19, #7 +0[0-9a-f]+ <[^>]+> eeff3b64 ftouhd d19, #7 +0[0-9a-f]+ <[^>]+> eeff9aec ftouls s19, #7 +0[0-9a-f]+ <[^>]+> eeff3bec ftould d19, #7 diff --git a/gas/testsuite/gas/arm/vfpv3-const-conv.s b/gas/testsuite/gas/arm/vfpv3-const-conv.s new file mode 100644 index 000000000000..d726d14b568e --- /dev/null +++ b/gas/testsuite/gas/arm/vfpv3-const-conv.s @@ -0,0 +1,25 @@ +.arm +.syntax unified + fconsts s17, #4 + fconsts s18, #0xa5 + fconsts s19, #0x40 + fconstd d17, #4 + fconstd d18, #0xa5 + fconstd d19, #0x40 + fshtos s17, 9 + fshtod d17, 9 + fsltos s17, 9 + fsltod d17, 9 + fuhtos s17, 9 + fuhtod d17, 9 + fultos s17, 9 + fultod d17, 9 + + ftoshs s19, 7 + ftoshd d19, 7 + ftosls s19, 7 + ftosld d19, 7 + ftouhs s19, 7 + ftouhd d19, 7 + ftouls s19, 7 + ftould d19, 7 diff --git a/gas/testsuite/gas/arm/wince.d b/gas/testsuite/gas/arm/wince.d new file mode 100644 index 000000000000..1770cacd4f14 --- /dev/null +++ b/gas/testsuite/gas/arm/wince.d @@ -0,0 +1,30 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM WinCE basic tests +#as: -mcpu=arm7m -EL +#source: wince.s +#not-skip: *-wince-* + +# Some WinCE specific tests. + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <global_data> 00000007 andeq r0, r0, r7 + 0: ARM_32 global_data +0+004 <global_sym> e1a00000 nop \(mov r0,r0\) +0+008 <global_sym\+0x4> e1a00000 nop \(mov r0,r0\) +0+000c <global_sym\+0x8> e1a00000 nop \(mov r0,r0\) +0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4> + 10: ARM_26D global_sym\+0xf+ffc +0+018 <global_sym\+0x14> ebfffffa bl f+ff4 <global_sym\+0xf+ff0> + 14: ARM_26D global_sym\+0xf+ffc +0+01c <global_sym\+0x18> 0afffff9 beq f+ff0 <global_sym\+0xf+fec> + 18: ARM_26D global_sym\+0xf+ffc +0+020 <global_sym\+0x1c> eafffff8 b 0+008 <global_sym\+0x4> +0+024 <global_sym\+0x20> ebfffff7 bl 0+008 <global_sym\+0x4> +0+028 <global_sym\+0x24> 0afffff6 beq 0+008 <global_sym\+0x4> +0+02c <global_sym\+0x28> eafffff5 b 0+008 <global_sym\+0x4> +0+030 <global_sym\+0x2c> ebfffff4 bl 0+008 <global_sym\+0x4> +0+034 <global_sym\+0x30> e51f0034 ldr r0, \[pc, #-52\] ; 0+008 <global_sym\+0x4> +0+038 <global_sym\+0x34> e51f0038 ldr r0, \[pc, #-56\] ; 0+008 <global_sym\+0x4> +0+03c <global_sym\+0x38> e51f003c ldr r0, \[pc, #-60\] ; 0+008 <global_sym\+0x4> diff --git a/gas/testsuite/gas/arm/wince.s b/gas/testsuite/gas/arm/wince.s new file mode 100644 index 000000000000..e8b76a045901 --- /dev/null +++ b/gas/testsuite/gas/arm/wince.s @@ -0,0 +1,25 @@ + .global global_data + .text + .global global_sym + .def global_sym; .scl 2; .type 32; .endef + +global_data: + .word global_data+7 + +global_sym: +def_sym: +undef_sym: + nop + nop + nop + b global_sym + bl global_sym + beq global_sym + b def_sym + bl def_sym + beq def_sym + b undef_sym + bl undef_sym + ldr r0, global_sym + ldr r0, def_sym + ldr r0, undef_sym diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d index a9852e0394b8..e3f060d90db0 100644 --- a/gas/testsuite/gas/arm/wince_inst.d +++ b/gas/testsuite/gas/arm/wince_inst.d @@ -36,7 +36,7 @@ Disassembly of section .text: 0+058 <[^>]*> 21a09008 ? movcs r9, r8 0+05c <[^>]*> 31a01003 ? movcc r1, r3 0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa 0+06c <[^>]*> e0832004 ? add r2, r3, r4 0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 @@ -116,11 +116,11 @@ Disassembly of section .text: 0+198 <[^>]*> e0000291 ? mul r0, r1, r2 0+19c <[^>]*> e0110392 ? muls r1, r2, r3 0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp 0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip 0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr 0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] 0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] 0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! @@ -132,7 +132,7 @@ Disassembly of section .text: 0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> 0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\] 0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] 0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] 0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! @@ -145,31 +145,31 @@ Disassembly of section .text: 0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> 0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] 0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} 0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} 0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} 0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} 0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ 0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} 0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} 0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} 0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ 0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 -0+260 <[^>]*> eb000000 ? bl 0+268 <[^>]*> +0+260 <[^>]*> eb000000 ? bl 0.* <[^>]*> [ ]*260:.*_wombat.* -0+264 <[^>]*> 5b000000 ? blpl 0+26c <[^>]*> +0+264 <[^>]*> 5b000000 ? blpl 0.* <[^>]*> [ ]*264:.*ARM.*hohum -0+268 <[^>]*> ea000000 ? b 0+270 <[^>]*> +0+268 <[^>]*> ea000000 ? b 0.* <[^>]*> [ ]*268:.*_wibble.* -0+26c <[^>]*> da000000 ? ble 0+274 <[^>]*> +0+26c <[^>]*> da000000 ? ble 0.* <[^>]*> [ ]*26c:.*testerfunc.* 0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 0+274 <[^>]*> e1a01002 ? mov r1, r2 diff --git a/gas/testsuite/gas/arm/xscale.d b/gas/testsuite/gas/arm/xscale.d index fc38ba14e57e..32ecf1f3354a 100644 --- a/gas/testsuite/gas/arm/xscale.d +++ b/gas/testsuite/gas/arm/xscale.d @@ -24,12 +24,12 @@ Disassembly of section .text: 0+38 <[^>]*> f7d2f003 pld \[r2, r3\] 0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] 0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] -0+44 <[^>]*> 01c327d8 ldreqd r2, \[r3, #120\] -0+48 <[^>]*> b10540d6 ldrltd r4, \[r5, -r6\] +0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\] +0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] 0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]! 0+50 <[^>]*> e1ac00fd strd r0, \[ip, sp\]! -0+54 <[^>]*> 30ce21f0 strccd r2, \[lr\], #16 -0+58 <[^>]*> 708640f8 strvcd r4, \[r6\], r8 +0+54 <[^>]*> 30ce21f0 strdcc r2, \[lr\], #16 +0+58 <[^>]*> 708640f8 strdvc r4, \[r6\], r8 0+5c <[^>]*> e5910000 ldr r0, \[r1\] 0+60 <[^>]*> e5832000 str r2, \[r3\] 0+64 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11 diff --git a/gas/testsuite/gas/bfin/bfin.exp b/gas/testsuite/gas/bfin/bfin.exp index 51690a16fe05..9f7849b27b9a 100644 --- a/gas/testsuite/gas/bfin/bfin.exp +++ b/gas/testsuite/gas/bfin/bfin.exp @@ -1,17 +1,5 @@ # Blackfin assembler testsuite -proc run_list_test { name opts } { - global srcdir subdir - set testname "bfin $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} if [istarget bfin*-*-*] { run_dump_test "arithmetic" run_dump_test "bit" diff --git a/gas/testsuite/gas/bfin/load.d b/gas/testsuite/gas/bfin/load.d index 58d97c2a82f4..07af13973295 100644 --- a/gas/testsuite/gas/bfin/load.d +++ b/gas/testsuite/gas/bfin/load.d @@ -31,84 +31,86 @@ Disassembly of section .text: 54: 36 e1 ff 7f M2=0x7fff \(X\); 58: 81 60 R1=0x10\(x\); 5a: 3c e1 00 00 L0=0x0 \(X\); - 5e: 27 e1 eb 00 R7=0xeb \(X\); + 5e: 27 e1 f3 00 R7=0xf3 \(X\); + 62: 00 e1 03 00 R0.L=0x3; + 66: 01 e1 0f 00 R1.L=0xf; -00000062 <load_pointer_register>: - 62: 7e 91 SP=\[FP\]; - 64: 47 90 FP=\[P0\+\+\]; - 66: f1 90 P1=\[SP--\]; - 68: 96 af SP=\[P2\+0x38\]; - 6a: 3b ac P3=\[FP\+0x0]; - 6c: 3c e5 ff 7f P4=\[FP\+0x1fffc\]; - 70: 3e e5 01 80 SP=\[FP\+-131068\]; - 74: 26 ac SP=\[P4\+0x0\]; - 76: 0d b8 P5=\[FP-128\]; +0000006a <load_pointer_register>: + 6a: 7e 91 SP=\[FP\]; + 6c: 47 90 FP=\[P0\+\+\]; + 6e: f1 90 P1=\[SP--\]; + 70: 96 af SP=\[P2\+0x38\]; + 72: 3b ac P3=\[FP\+0x0\]; + 74: 3c e5 ff 7f P4=\[FP\+0x1fffc\]; + 78: 3e e5 01 80 SP=\[FP\+-131068\]; + 7c: 26 ac SP=\[P4\+0x0\]; + 7e: 0d b8 P5=\[FP-128\]; -00000078 <load_data_register>: - 78: 07 91 R7=\[P0\]; - 7a: 2e 90 R6=\[P5\+\+\]; - 7c: a5 90 R5=\[P4--\]; - 7e: bc a2 R4=\[FP\+0x28\]; - 80: 33 e4 ff 7f R3=\[SP\+0x1fffc\]; - 84: 32 a0 R2=\[SP\+0x0\]; - 86: 39 e4 01 80 R1=\[FP\+-131068\]; - 8a: 06 80 R0=\[SP\+\+P0\]; - 8c: 05 b8 R5=\[FP-128\]; - 8e: 02 9d R2=\[I0\]; - 90: 09 9c R1=\[I1\+\+\]; - 92: 93 9c R3=\[I2--\]; - 94: 9c 9d R4=\[I3\+\+M0\]; +00000080 <load_data_register>: + 80: 07 91 R7=\[P0\]; + 82: 2e 90 R6=\[P5\+\+\]; + 84: a5 90 R5=\[P4--\]; + 86: bc a2 R4=\[FP\+0x28\]; + 88: 33 e4 ff 7f R3=\[SP\+0x1fffc\]; + 8c: 32 a0 R2=\[SP\+0x0\]; + 8e: 39 e4 01 80 R1=\[FP\+-131068\]; + 92: 06 80 R0=\[SP\+\+P0\]; + 94: 05 b8 R5=\[FP-128\]; + 96: 02 9d R2=\[I0\]; + 98: 09 9c R1=\[I1\+\+\]; + 9a: 93 9c R3=\[I2--\]; + 9c: 9c 9d R4=\[I3\+\+M0\]; -00000096 <load_half_word_zero_extend>: - 96: 37 95 R7=W\[SP\] \(Z\); - 98: 3e 94 R6=W\[FP\+\+\] \(Z\); - 9a: 85 94 R5=W\[P0--\] \(Z\); - 9c: cc a7 R4=W\[P1\+0x1e\] \(Z\); - 9e: 73 e4 fe 7f R3=W\[SP\+0xfffc\] \(Z\); - a2: 7a e4 02 80 R2=W\[FP\+-65532\] \(Z\); - a6: 28 86 R0=W\[P0\+\+P5\] \(Z\); +0000009e <load_half_word_zero_extend>: + 9e: 37 95 R7=W\[SP\] \(Z\); + a0: 3e 94 R6=W\[FP\+\+\] \(Z\); + a2: 85 94 R5=W\[P0--\] \(Z\); + a4: cc a7 R4=W\[P1\+0x1e\] \(Z\); + a6: 73 e4 fe 7f R3=W\[SP\+0xfffc\] \(Z\); + aa: 7a e4 02 80 R2=W\[FP\+-65532\] \(Z\); + ae: 28 86 R0=W\[P0\+\+P5\] \(Z\); -000000a8 <load_half_word_sign_extend>: - a8: 77 95 R7=W\[SP\]\(X\); - aa: 7e 94 R6=W\[FP\+\+\]\(X\); - ac: c5 94 R5=W\[P0--\]\(X\); - ae: 0d ab R5=W\[P1\+0x18\]\(X\); - b0: 73 e5 fe 7f R3=W\[SP\+0xfffc\]\(X\); - b4: 7f e5 02 80 R7=W\[FP\+-65532\]\(X\); - b8: 51 8e R1=W\[P1\+\+P2\]\(X\); +000000b0 <load_half_word_sign_extend>: + b0: 77 95 R7=W\[SP\]\(X\); + b2: 7e 94 R6=W\[FP\+\+\]\(X\); + b4: c5 94 R5=W\[P0--\]\(X\); + b6: 0d ab R5=W\[P1\+0x18\]\(X\); + b8: 73 e5 fe 7f R3=W\[SP\+0xfffc\]\(X\); + bc: 7f e5 02 80 R7=W\[FP\+-65532\]\(X\); + c0: 51 8e R1=W\[P1\+\+P2\]\(X\); -000000ba <load_high_data_register_half>: - ba: 40 9d R0.H=W\[I0\]; - bc: 49 9c R1.H=W\[I1\+\+\]; - be: d2 9c R2.H=W\[I2--\]; - c0: f6 84 R3.H=W\[SP\]; - c2: 07 85 R4.H=W\[FP\+\+P0\]; +000000c2 <load_high_data_register_half>: + c2: 40 9d R0.H=W\[I0\]; + c4: 49 9c R1.H=W\[I1\+\+\]; + c6: d2 9c R2.H=W\[I2--\]; + c8: f6 84 R3.H=W\[SP\]; + ca: 07 85 R4.H=W\[FP\+\+P0\]; -000000c4 <load_low_data_register_half>: - c4: 3f 9d R7.L=W\[I3\]; - c6: 36 9c R6.L=W\[I2\+\+\]; - c8: ad 9c R5.L=W\[I1--\]; - ca: 00 83 R4.L=W\[P0\]; - cc: da 82 R3.L=W\[P2\+\+P3\]; +000000cc <load_low_data_register_half>: + cc: 3f 9d R7.L=W\[I3\]; + ce: 36 9c R6.L=W\[I2\+\+\]; + d0: ad 9c R5.L=W\[I1--\]; + d2: 00 83 R4.L=W\[P0\]; + d4: da 82 R3.L=W\[P2\+\+P3\]; -000000ce <load_byte_zero_extend>: - ce: 05 99 R5=B\[P0\] \(Z\); - d0: 0c 98 R4=B\[P1\+\+\] \(Z\); - d2: 90 98 R0=B\[P2--\] \(Z\); - d4: b3 e4 ff 7f R3=B\[SP\+0x7fff\] \(Z\); - d8: b7 e4 01 80 R7=B\[SP\+-32767\] \(Z\); +000000d6 <load_byte_zero_extend>: + d6: 05 99 R5=B\[P0\] \(Z\); + d8: 0c 98 R4=B\[P1\+\+\] \(Z\); + da: 90 98 R0=B\[P2--\] \(Z\); + dc: b3 e4 ff 7f R3=B\[SP\+0x7fff\] \(Z\); + e0: b7 e4 01 80 R7=B\[SP\+-32767\] \(Z\); -000000dc <load_byte_sign_extend>: - dc: 45 99 R5=B\[P0\]\(X\); - de: 4a 98 R2=B\[P1\+\+\]\(X\); - e0: fb 98 R3=B\[FP--\]\(X\); - e2: b7 e5 00 00 R7=B\[SP\+0x0\]\(X\); - e6: be e5 01 80 R6=B\[FP\+-32767\]\(X\); +000000e4 <load_byte_sign_extend>: + e4: 45 99 R5=B\[P0\]\(X\); + e6: 4a 98 R2=B\[P1\+\+\]\(X\); + e8: fb 98 R3=B\[FP--\]\(X\); + ea: b7 e5 00 00 R7=B\[SP\+0x0\]\(X\); + ee: be e5 01 80 R6=B\[FP\+-32767\]\(X\); -000000ea <load_data1>: +000000f2 <load_data1>: ... -000000eb <load_data2>: - eb: 10 00 IF ! CC JUMP eb <load_data2>; - ed: 00 00 NOP; +000000f3 <load_data2>: + f3: 10 00 IF ! CC JUMP f3 <load_data2>; + f5: 00 00 NOP; ... diff --git a/gas/testsuite/gas/bfin/load.s b/gas/testsuite/gas/bfin/load.s index 07f4732a7e99..96ae1faad194 100644 --- a/gas/testsuite/gas/bfin/load.s +++ b/gas/testsuite/gas/bfin/load.s @@ -36,6 +36,10 @@ load_immediate: L0 = foo1; r7 = load_data2; + /* Test constant folding. */ + r0.l = (a + 5) - 2; + r1.l = (a + 5) + 10; + .text .global load_pointer_register load_pointer_register: diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d index 57f3a91e2fa3..1a6b88492e88 100644 --- a/gas/testsuite/gas/bfin/vector2.d +++ b/gas/testsuite/gas/bfin/vector2.d @@ -469,3 +469,6 @@ Disassembly of section .text: 734: 00 9e 32 9c 738: 8b c8 9a 2f R6 = \(a0 \+= R3.H \* R2.H\) \(FU\) \|\| I2-=M0 \|\| NOP; 73c: 72 9e 00 00 + 740: 14 c2 1a a0 R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L; + 744: 1c c2 b8 60 R3 = R7.L \* R0.H \(M\), R2 = R7.L \* R0.L; + 748: 1c c0 b8 60 R3 = \(a1 = R7.L \* R0.H\) \(M\), R2 = \(a0 = R7.L \* R0.L\);
\ No newline at end of file diff --git a/gas/testsuite/gas/bfin/vector2.s b/gas/testsuite/gas/bfin/vector2.s index 30cca43c1ebe..d9ea20131e73 100755 --- a/gas/testsuite/gas/bfin/vector2.s +++ b/gas/testsuite/gas/bfin/vector2.s @@ -666,3 +666,8 @@ Ireg. */ r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;
/* which the assembler expands into:
r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */
+
+/* Test for ensure (m) is not thown away. */
+r0.l=r3.l*r2.l, r0.h=r3.h*r2.l (m) ;
+R2 = R7.L * R0.L, R3 = R7.L * R0.H (m);
+R2 = (A0 = R7.L * R0.L), R3 = ( A1 = R7.L * R0.H) (m);
diff --git a/gas/testsuite/gas/cfi/cfi-common-5.d b/gas/testsuite/gas/cfi/cfi-common-5.d new file mode 100644 index 000000000000..fed50c55b4bb --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-common-5.d @@ -0,0 +1,24 @@ +#readelf: -wf +#name: CFI common 5 +The section .eh_frame contains: + +00000000 00000010 00000000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: .* + Data alignment factor: .* + Return address column: .* + Augmentation data: [01]b +#... +00000014 00000014 00000018 FDE cie=00000000 pc=.* + DW_CFA_advance_loc: 4 to .* + DW_CFA_remember_state + DW_CFA_advance_loc: 4 to .* + DW_CFA_restore_state +#... +0000002c 0000001[48] 00000030 FDE cie=00000000 pc=.* + DW_CFA_advance_loc: 4 to .* + DW_CFA_def_cfa: r0 ofs 16 + DW_CFA_advance_loc: 4 to .* + DW_CFA_def_cfa_offset: 0 +#pass diff --git a/gas/testsuite/gas/cfi/cfi-common-5.s b/gas/testsuite/gas/cfi/cfi-common-5.s new file mode 100644 index 000000000000..f59d97782348 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-common-5.s @@ -0,0 +1,24 @@ + .text + .cfi_startproc simple + + .subsection 3 + .cfi_startproc simple + .long 0 + .cfi_def_cfa 0, 16 + .previous + + .long 0 + .cfi_remember_state + + .subsection 3 + .long 0 + .cfi_adjust_cfa_offset -16 + .previous + + .long 0 + .cfi_restore_state + .cfi_endproc + + .subsection 3 + .cfi_endproc + .previous diff --git a/gas/testsuite/gas/cfi/cfi-common-6.d b/gas/testsuite/gas/cfi/cfi-common-6.d new file mode 100644 index 000000000000..dcc7b79b9697 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-common-6.d @@ -0,0 +1,73 @@ +#readelf: -wf +#name: CFI common 6 +The section .eh_frame contains: + +00000000 00000018 00000000 CIE + Version: 1 + Augmentation: "zPLR" + Code alignment factor: .* + Data alignment factor: .* + Return address column: .* + Augmentation data: 03 .. .. .. .. 0c 1b + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +0000001c 00000018 00000020 FDE cie=00000000 pc=00000000..00000004 + Augmentation data: (00 00 00 00 de ad be ef|ef be ad de 00 00 00 00) + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +00000038 00000010 00000000 CIE + Version: 1 + Augmentation: "zLR" + Code alignment factor: .* + Data alignment factor: .* + Return address column: .* + Augmentation data: 0c 1b + + DW_CFA_nop + +0000004c 00000018 00000018 FDE cie=00000038 pc=00000004..00000008 + Augmentation data: (00 00 00 00 de ad be ef|ef be ad de 00 00 00 00) + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +00000068 00000018 0000006c FDE cie=00000000 pc=00000008..0000000c + Augmentation data: (00 00 00 00 be ef de ad|ad de ef be 00 00 00 00) + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +00000084 00000018 00000000 CIE + Version: 1 + Augmentation: "zPLR" + Code alignment factor: .* + Data alignment factor: .* + Return address column: .* + Augmentation data: 1b .. .. .. .. 1b 1b + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +000000a0 00000014 00000020 FDE cie=00000084 pc=0000000c..00000010 + Augmentation data: .. .. .. .. + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +000000b8 00000014 00000038 FDE cie=00000084 pc=00000010..00000014 + Augmentation data: .. .. .. .. + + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + diff --git a/gas/testsuite/gas/cfi/cfi-common-6.s b/gas/testsuite/gas/cfi/cfi-common-6.s new file mode 100644 index 000000000000..2471bff68ebc --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-common-6.s @@ -0,0 +1,40 @@ + .text + .cfi_startproc simple + .cfi_personality 3, my_personality_v0 + .cfi_lsda 12, 0xdeadbeef + .long 0 + .cfi_endproc + + .cfi_startproc simple + .cfi_personality 3, my_personality_v0 + .cfi_lsda 12, 0xdeadbeef + .cfi_personality 0xff + .long 0 + .cfi_endproc + + .cfi_startproc simple + .cfi_personality 3, my_personality_v0 + .cfi_lsda 12, 0xbeefdead + .long 0 + .cfi_endproc + + .cfi_startproc simple + .cfi_personality (0x1b), my_personality_v1 + .cfi_lsda 27, 1f + .long 0 + .cfi_endproc + + .cfi_startproc simple + .cfi_personality (0x1b), my_personality_v1 + .cfi_lsda 27, 2f + .long 0 + .cfi_endproc + +my_personality_v0: + .long 0 +my_personality_v1: + .long 0 +1: + .long 0 +2: + .long 0 diff --git a/gas/testsuite/gas/cfi/cfi-hppa-1.d b/gas/testsuite/gas/cfi/cfi-hppa-1.d new file mode 100644 index 000000000000..7b06d55f327b --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-hppa-1.d @@ -0,0 +1,38 @@ +#readelf: -wf +#name: CFI on hppa +The section .eh_frame contains: + +00000000 00000010 00000000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 4 + Data alignment factor: -[48] + Return address column: 2 + Augmentation data: 1b + + DW_CFA_def_cfa: r30 ofs 0 + +00000014 00000018 00000018 FDE cie=00000000 pc=00000000..00000018 + DW_CFA_advance_loc: 8 to 00000008 + DW_CFA_def_cfa_reg: r3 + DW_CFA_advance_loc: 4 to 0000000c + DW_CFA_def_cfa_offset: 4660 + DW_CFA_advance_loc: 8 to 00000014 + DW_CFA_def_cfa_reg: r30 + DW_CFA_nop + +00000030 00000018 00000034 FDE cie=00000000 pc=00000018..00000040 + DW_CFA_advance_loc: 12 to 00000024 + DW_CFA_def_cfa_reg: r3 + DW_CFA_offset: r2 at cfa-24 + DW_CFA_advance_loc: 24 to 0000003c + DW_CFA_def_cfa_reg: r30 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +0000004c 00000010 00000050 FDE cie=00000000 pc=00000040..00000048 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + diff --git a/gas/testsuite/gas/cfi/cfi-hppa-1.s b/gas/testsuite/gas/cfi/cfi-hppa-1.s new file mode 100644 index 000000000000..923350ccb949 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-hppa-1.s @@ -0,0 +1,66 @@ +#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o + + .text + .align 4 + .level 1.1 + +.globl func_locvars + .type func_locvars, @function +func_locvars: + .PROC + .CALLINFO FRAME=0x1234,NO_CALLS,SAVE_SP,ENTRY_GR=3 + .ENTRY + .cfi_startproc + copy %r3,%r1 + copy %r30,%r3 + .cfi_def_cfa_register r3 + stwm %r1,0x1234(%r30) + .cfi_adjust_cfa_offset 0x1234 + ldo 64(%r3),%r30 + ldwm -64(%r30),%r3 + .cfi_def_cfa_register sp + bv,n %r0(%r2) + .cfi_endproc + .EXIT + .PROCEND + +.globl func_prologue + .type func_prologue, @function +func_prologue: + .PROC + .CALLINFO FRAME=64,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 + .ENTRY + .cfi_startproc +#; This is not ABI-compliant but helps the test to run on both +#; 32-bit and 64-bit targets + stw %r2,-24(%r30) + copy %r3,%r1 + copy %r30,%r3 + .cfi_def_cfa_register r3 + .cfi_offset r2, -24 + stwm %r1,64(%r30) + bl func_locvars,%r2 + nop + ldw -20(%r3),%r2 + ldo 64(%r3),%r30 + ldwm -64(%r30),%r3 + .cfi_def_cfa_register sp + bv,n %r0(%r2) + .cfi_endproc + .EXIT + .PROCEND + + .align 4 +.globl main + .type main, @function +main: + .PROC + .CALLINFO CALLS + .ENTRY + #; tail call - simple function that doesn't touch the stack + .cfi_startproc + b func_prologue + nop + .cfi_endproc + .EXIT + .PROCEND diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d index f34643545028..2f37a9cb6446 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.d +++ b/gas/testsuite/gas/cfi/cfi-x86_64.d @@ -35,7 +35,7 @@ The section .eh_frame contains: 00000050 00000014 00000054 FDE cie=00000000 pc=00000022..00000035 DW_CFA_advance_loc: 3 to 00000025 - DW_CFA_def_cfa_reg: r12 + DW_CFA_def_cfa_reg: r8 DW_CFA_advance_loc: 15 to 00000034 DW_CFA_def_cfa_reg: r7 DW_CFA_nop @@ -50,3 +50,40 @@ The section .eh_frame contains: DW_CFA_nop DW_CFA_nop +00000090 00000010 00000000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 1 + Data alignment factor: -8 + Return address column: 16 + Augmentation data: 1b + + DW_CFA_def_cfa: r7 ofs 8 + +000000a4 00000030 00000018 FDE cie=00000090 pc=0000004d..00000058 + DW_CFA_advance_loc: 1 to 0000004e + DW_CFA_def_cfa_offset: 16 + DW_CFA_advance_loc: 1 to 0000004f + DW_CFA_def_cfa_reg: r8 + DW_CFA_advance_loc: 1 to 00000050 + DW_CFA_def_cfa_offset: 4676 + DW_CFA_advance_loc: 1 to 00000051 + DW_CFA_offset_extended_sf: r4 at cfa\+16 + DW_CFA_advance_loc: 1 to 00000052 + DW_CFA_register: r8 in r9 + DW_CFA_advance_loc: 1 to 00000053 + DW_CFA_remember_state + DW_CFA_advance_loc: 1 to 00000054 + DW_CFA_restore: r6 + DW_CFA_advance_loc: 1 to 00000055 + DW_CFA_undefined: r16 + DW_CFA_advance_loc: 1 to 00000056 + DW_CFA_same_value: r3 + DW_CFA_advance_loc: 1 to 00000057 + DW_CFA_restore_state + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.s b/gas/testsuite/gas/cfi/cfi-x86_64.s index 10035ad7f8fd..c2e2464b3630 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.s +++ b/gas/testsuite/gas/cfi/cfi-x86_64.s @@ -35,9 +35,9 @@ func_prologue: #; each instruction. pushq %rbp .cfi_def_cfa_offset 16 - .cfi_offset rbp,-16 + .cfi_offset %rbp, -16 movq %rsp, %rbp - .cfi_def_cfa_register rbp + .cfi_def_cfa_register %rbp #; function body call func_locvars @@ -46,7 +46,7 @@ func_prologue: #; epilogue with valid CFI #; (we're better than gcc :-) leaveq - .cfi_def_cfa rsp,8 + .cfi_def_cfa %rsp, 8 ret .cfi_endproc @@ -59,21 +59,21 @@ func_prologue: func_otherreg: .cfi_startproc - #; save frame pointer to r12 - movq %rsp,%r12 - .cfi_def_cfa_register r12 + #; save frame pointer to r8 + movq %rsp,%r8 + .cfi_def_cfa_register r8 #; alocate space for local vars #; (no .cfi_{def,adjust}_cfa_offset here, - #; because CFA is computed from r12!) + #; because CFA is computed from r8!) sub $100,%rsp #; function body call func_prologue addl $2, %eax - #; restore frame pointer from r12 - movq %r12,%rsp + #; restore frame pointer from r8 + movq %r8,%rsp .cfi_def_cfa_register rsp ret .cfi_endproc @@ -105,3 +105,34 @@ _start: syscall hlt .cfi_endproc + +#; func_alldirectives +#; - test for all .cfi directives. +#; This function is never called and the CFI info doesn't make sense. + + .type func_alldirectives,@function +func_alldirectives: + .cfi_startproc simple + .cfi_def_cfa rsp,8 + nop + .cfi_def_cfa_offset 16 + nop + .cfi_def_cfa_register r8 + nop + .cfi_adjust_cfa_offset 0x1234 + nop + .cfi_offset %rsi, 0x10 + nop + .cfi_register %r8, %r9 + nop + .cfi_remember_state + nop + .cfi_restore %rbp + nop + .cfi_undefined %rip + nop + .cfi_same_value rbx + nop + .cfi_restore_state + ret + .cfi_endproc diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp index eeb551098291..b396f9e85235 100644 --- a/gas/testsuite/gas/cfi/cfi.exp +++ b/gas/testsuite/gas/cfi/cfi.exp @@ -1,17 +1,3 @@ -# ??? This probably shouldn't be replicated here... -proc run_list_test { name opts } { - global srcdir subdir - set testname "cfi $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if ![is_elf_format] then { return } @@ -61,6 +47,8 @@ if [istarget "x86_64-*"] then { } elseif { [istarget "mips*-*"] } then { run_dump_test "cfi-mips-1" +} elseif { [istarget "hppa*-linux*"] } then { + run_dump_test "cfi-hppa-1" } else { return } @@ -70,3 +58,9 @@ run_dump_test "cfi-common-1" run_dump_test "cfi-common-2" run_dump_test "cfi-common-3" run_dump_test "cfi-common-4" +run_dump_test "cfi-common-5" + +# MIPS doesn't support PC relative cfi directives +if { ![istarget "mips*-*"] } then { + run_dump_test "cfi-common-6" +} diff --git a/gas/testsuite/gas/cr16/add_test.d b/gas/testsuite/gas/cr16/add_test.d new file mode 100644 index 000000000000..c2a0fe0e3c8e --- /dev/null +++ b/gas/testsuite/gas/cr16/add_test.d @@ -0,0 +1,71 @@ +#as: +#objdump: -dr +#name: add_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 30 addb \$0xf:s,r1 + 2: b2 30 ff 00 addb \$0xff:m,r2 + 6: b1 30 ff 0f addb \$0xfff:m,r1 + a: b1 30 14 00 addb \$0x14:m,r1 + e: a2 30 addb \$0xa:s,r2 + 10: b2 30 0b 00 addb \$0xb:m,r2 + 14: 12 31 addb r1,r2 + 16: 23 31 addb r2,r3 + 18: 34 31 addb r3,r4 + 1a: 56 31 addb r5,r6 + 1c: 67 31 addb r6,r7 + 1e: 78 31 addb r7,r8 + 20: f1 34 addcb \$0xf:s,r1 + 22: b2 34 ff 00 addcb \$0xff:m,r2 + 26: b1 34 ff 0f addcb \$0xfff:m,r1 + 2a: b1 34 14 00 addcb \$0x14:m,r1 + 2e: a2 34 addcb \$0xa:s,r2 + 30: b2 34 0b 00 addcb \$0xb:m,r2 + 34: 12 35 addcb r1,r2 + 36: 23 35 addcb r2,r3 + 38: 34 35 addcb r3,r4 + 3a: 56 35 addcb r5,r6 + 3c: 67 35 addcb r6,r7 + 3e: 78 35 addcb r7,r8 + 40: f1 36 addcw \$0xf:s,r1 + 42: b2 36 ff 00 addcw \$0xff:m,r2 + 46: b1 36 ff 0f addcw \$0xfff:m,r1 + 4a: b1 36 14 00 addcw \$0x14:m,r1 + 4e: a2 36 addcw \$0xa:s,r2 + 50: b2 36 0b 00 addcw \$0xb:m,r2 + 54: 12 37 addcw r1,r2 + 56: 23 37 addcw r2,r3 + 58: 34 37 addcw r3,r4 + 5a: 56 37 addcw r5,r6 + 5c: 67 37 addcw r6,r7 + 5e: 78 37 addcw r7,r8 + 60: f1 32 addw \$0xf:s,r1 + 62: b2 32 ff 00 addw \$0xff:m,r2 + 66: b1 32 ff 0f addw \$0xfff:m,r1 + 6a: b1 32 14 00 addw \$0x14:m,r1 + 6e: a2 32 addw \$0xa:s,r2 + 70: 12 33 addw r1,r2 + 72: 23 33 addw r2,r3 + 74: 34 33 addw r3,r4 + 76: 56 33 addw r5,r6 + 78: 67 33 addw r6,r7 + 7a: 78 33 addw r7,r8 + 7c: f1 60 addd \$0xf:s,\(r2,r1\) + 7e: b1 60 0b 00 addd \$0xb:m,\(r2,r1\) + 82: b1 60 ff 00 addd \$0xff:m,\(r2,r1\) + 86: b1 60 ff 0f addd \$0xfff:m,\(r2,r1\) + 8a: 10 04 ff ff addd \$0xffff:m,\(r2,r1\) + 8e: 1f 04 ff ff addd \$0xfffff:m,\(r2,r1\) + 92: 21 00 ff 0f addd \$0xfffffff:l,\(r2,r1\) + 96: ff ff + 98: 91 60 addd \$-1:s,\(r2,r1\) + 9a: 31 61 addd \(r4,r3\),\(r2,r1\) + 9c: 31 61 addd \(r4,r3\),\(r2,r1\) + 9e: af 60 addd \$0xa:s,\(sp\) + a0: ef 60 addd \$0xe:s,\(sp\) + a2: bf 60 0b 00 addd \$0xb:m,\(sp\) + a6: 8f 60 addd \$0x8:s,\(sp\) diff --git a/gas/testsuite/gas/cr16/add_test.s b/gas/testsuite/gas/cr16/add_test.s new file mode 100644 index 000000000000..de5270db19c3 --- /dev/null +++ b/gas/testsuite/gas/cr16/add_test.s @@ -0,0 +1,98 @@ + .text + .global main +main: + ########### + # ADDB imm4/imm16, reg + ########### + addb $0xf,r1 + addb $0xff,r2 + addb $0xfff,r1 + #addb $0xffff,r2 // CHECK WITH CRASM 4.1 + addb $20,r1 + addb $10,r2 + addb $11,r2 + ########### + # ADDB reg, reg + ########### + addb r1,r2 + addb r2,r3 + addb r3,r4 + addb r5,r6 + addb r6,r7 + addb r7,r8 + ########### + # ADDCB imm4/imm16, reg + ########### + addcb $0xf,r1 + addcb $0xff,r2 + addcb $0xfff,r1 + #addcb $0xffff,r2 // CHECK WITH CRASM 4.1 + addcb $20,r1 + addcb $10,r2 + addcb $11,r2 + ########### + # ADDCB reg, reg + ########### + addcb r1,r2 + addcb r2,r3 + addcb r3,r4 + addcb r5,r6 + addcb r6,r7 + addcb r7,r8 + ########### + # ADDCW imm4/imm16, reg + ########### + addcw $0xf,r1 + addcw $0xff,r2 + addcw $0xfff,r1 + #addcw $0xffff,r2 # check with CRASM 4.1 + addcw $20,r1 + addcw $10,r2 + addcw $11,r2 + ########### + # ADDCW reg, reg + ########### + addcw r1,r2 + addcw r2,r3 + addcw r3,r4 + addcw r5,r6 + addcw r6,r7 + addcw r7,r8 + ########### + # ADDW imm4/imm16, reg + ########### + addw $0xf,r1 + addw $0xff,r2 + addw $0xfff,r1 + #addw $0xffff,r2 // CHECK WITH CRASM 4.1 + addw $20,r1 + addw $10,r2 + ########### + # ADDW reg, reg + ########### + addw r1,r2 + addw r2,r3 + addw r3,r4 + addw r5,r6 + addw r6,r7 + addw r7,r8 + ########### + # ADDD imm4/imm16/imm20/imm32, regp + ########### + addd $0xf,(r2,r1) + addd $0xB,(r2,r1) + addd $0xff,(r2,r1) + addd $0xfff,(r2,r1) + addd $0xffff,(r2,r1) + addd $0xfffff,(r2,r1) + addd $0xfffffff,(r2,r1) + addd $0xffffffff,(r2,r1) + ########### + # ADDD regp, regp + ########### + addd (r4,r3),(r2,r1) + addd (r4,r3),(r2,r1) + addd $10,(sp) + addd $14,(sp) + addd $11,(sp) + addd $8,(sp) diff --git a/gas/testsuite/gas/cr16/and_test.d b/gas/testsuite/gas/cr16/and_test.d new file mode 100644 index 000000000000..f8e1f27f57bf --- /dev/null +++ b/gas/testsuite/gas/cr16/and_test.d @@ -0,0 +1,55 @@ +#as: +#objdump: -dr +#name: and_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 20 andb \$0xf:s,r1 + 2: b2 20 ff 00 andb \$0xff:m,r2 + 6: b1 20 ff 0f andb \$0xfff:m,r1 + a: b2 20 ff ff andb \$0xffff:m,r2 + e: b1 20 14 00 andb \$0x14:m,r1 + 12: a2 20 andb \$0xa:s,r2 + 14: 12 21 andb r1,r2 + 16: 23 21 andb r2,r3 + 18: 34 21 andb r3,r4 + 1a: 56 21 andb r5,r6 + 1c: 67 21 andb r6,r7 + 1e: 78 21 andb r7,r8 + 20: f1 22 andw \$0xf:s,r1 + 22: b2 22 ff 00 andw \$0xff:m,r2 + 26: b1 22 ff 0f andw \$0xfff:m,r1 + 2a: b2 22 ff ff andw \$0xffff:m,r2 + 2e: b1 22 14 00 andw \$0x14:m,r1 + 32: a2 22 andw \$0xa:s,r2 + 34: 12 23 andw r1,r2 + 36: 23 23 andw r2,r3 + 38: 34 23 andw r3,r4 + 3a: 56 23 andw r5,r6 + 3c: 67 23 andw r6,r7 + 3e: 78 23 andw r7,r8 + 40: 41 00 00 00 andd \$0xf:l,\(r2,r1\) + 44: 0f 00 + 46: 41 00 00 00 andd \$0xff:l,\(r2,r1\) + 4a: ff 00 + 4c: 41 00 00 00 andd \$0xfff:l,\(r2,r1\) + 50: ff 0f + 52: 41 00 00 00 andd \$0xffff:l,\(r2,r1\) + 56: ff ff + 58: 41 00 0f 00 andd \$0xfffff:l,\(r2,r1\) + 5c: ff ff + 5e: 41 00 ff 0f andd \$0xfffffff:l,\(r2,r1\) + 62: ff ff + 64: 41 00 ff ff andd \$0xffffffff:l,\(r2,r1\) + 68: ff ff + 6a: 14 00 31 b0 andd \(r4,r3\),\(r2,r1\) + 6e: 14 00 31 b0 andd \(r4,r3\),\(r2,r1\) + 72: 4f 00 00 00 andd \$0xa:l,\(sp\) + 76: 0a 00 + 78: 4f 00 00 00 andd \$0xe:l,\(sp\) + 7c: 0e 00 + 7e: 4f 00 00 00 andd \$0x8:l,\(sp\) + 82: 08 00 diff --git a/gas/testsuite/gas/cr16/and_test.s b/gas/testsuite/gas/cr16/and_test.s new file mode 100644 index 000000000000..b21fdb7fec63 --- /dev/null +++ b/gas/testsuite/gas/cr16/and_test.s @@ -0,0 +1,57 @@ + .text + .global main +main: + ########### + # ANDB imm4/imm16, reg + ########### + andb $0xf,r1 + andb $0xff,r2 + andb $0xfff,r1 + andb $0xffff,r2 + andb $20,r1 + andb $10,r2 + ########### + # ANDB reg, reg + ########### + andb r1,r2 + andb r2,r3 + andb r3,r4 + andb r5,r6 + andb r6,r7 + andb r7,r8 + ########### + # ANDW imm4/imm16, reg + ########### + andw $0xf,r1 + andw $0xff,r2 + andw $0xfff,r1 + andw $0xffff,r2 + andw $20,r1 + andw $10,r2 + ########### + # ANDW reg, reg + ########### + andw r1,r2 + andw r2,r3 + andw r3,r4 + andw r5,r6 + andw r6,r7 + andw r7,r8 + ########### + # ANDD imm4/imm16/imm32, regp + ########### + andd $0xf,(r2,r1) + andd $0xff,(r2,r1) + andd $0xfff,(r2,r1) + andd $0xffff,(r2,r1) + andd $0xfffff,(r2,r1) + andd $0xfffffff,(r2,r1) + andd $0xffffffff,(r2,r1) + ########### + # ANDD regp, regp + ########### + andd (r4,r3),(r2,r1) + andd (r4,r3),(r2,r1) + andd $10,(sp) + andd $14,(sp) + andd $8,(sp) diff --git a/gas/testsuite/gas/cr16/ash_test.d b/gas/testsuite/gas/cr16/ash_test.d new file mode 100644 index 000000000000..2818012f7b13 --- /dev/null +++ b/gas/testsuite/gas/cr16/ash_test.d @@ -0,0 +1,47 @@ +#as: +#objdump: -dr +#name: ash_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 71 40 ashub \$7:s,r1 + 2: 91 40 ashub \$-7:s,r1 + 4: 41 40 ashub \$4:s,r1 + 6: c1 40 ashub \$-4:s,r1 + 8: 81 40 ashub \$-8:s,r1 + a: 31 40 ashub \$3:s,r1 + c: d1 40 ashub \$-3:s,r1 + e: 21 41 ashub r2,r1 + 10: 34 41 ashub r3,r4 + 12: 56 41 ashub r5,r6 + 14: 8a 41 ashub r8,r10 + 16: 71 42 ashuw \$7:s,r1 + 18: 91 43 ashuw \$-7:s,r1 + 1a: 41 42 ashuw \$4:s,r1 + 1c: c1 43 ashuw \$-4:s,r1 + 1e: 81 42 ashuw \$8:s,r1 + 20: 81 43 ashuw \$-8:s,r1 + 22: 31 42 ashuw \$3:s,r1 + 24: d1 43 ashuw \$-3:s,r1 + 26: 21 45 ashuw r2,r1 + 28: 34 45 ashuw r3,r4 + 2a: 56 45 ashuw r5,r6 + 2c: 8a 45 ashuw r8,r10 + 2e: 72 4c ashud \$7:s,\(r3,r2\) + 30: 92 4f ashud \$-7:s,\(r3,r2\) + 32: 82 4c ashud \$8:s,\(r3,r2\) + 34: 82 4f ashud \$-8:s,\(r3,r2\) + 36: 42 4c ashud \$4:s,\(r3,r2\) + 38: c2 4f ashud \$-4:s,\(r3,r2\) + 3a: c2 4c ashud \$12:s,\(r3,r2\) + 3c: 42 4f ashud \$-12:s,\(r3,r2\) + 3e: 31 4c ashud \$3:s,\(r2,r1\) + 40: d1 4f ashud \$-3:s,\(r2,r1\) + 42: 41 48 ashud r4,\(r2,r1\) + 44: 51 48 ashud r5,\(r2,r1\) + 46: 61 48 ashud r6,\(r2,r1\) + 48: 81 48 ashud r8,\(r2,r1\) + 4a: 11 48 ashud r1,\(r2,r1\) diff --git a/gas/testsuite/gas/cr16/ash_test.s b/gas/testsuite/gas/cr16/ash_test.s new file mode 100644 index 000000000000..dc3e794929ca --- /dev/null +++ b/gas/testsuite/gas/cr16/ash_test.s @@ -0,0 +1,59 @@ + .text + .global main +main: + ##################################### + # ASHUB cnt(left +)/cnt (right -), reg + ##################################### + ashub $7,r1 + ashub $-7,r1 + ashub $4,r1 + ashub $-4,r1 + ashub $-8,r1 + ashub $3,r1 + ashub $-3,r1 + ##################################### + # ASHUB reg, reg + ##################################### + ashub r2,r1 + ashub r3,r4 + ashub r5,r6 + ashub r8,r10 + ##################################### + # ASHUW cnt(left +)/cnt (right -), reg + ##################################### + ashuw $7,r1 + ashuw $-7,r1 + ashuw $4,r1 + ashuw $-4,r1 + ashuw $8,r1 + ashuw $-8,r1 + ashuw $3,r1 + ashuw $-3,r1 + ##################################### + # ASHUW reg, reg + ##################################### + ashuw r2,r1 + ashuw r3,r4 + ashuw r5,r6 + ashuw r8,r10 + ##################################### + # ASHUD cnt(left +)/cnt (right -), regp + ##################################### + ashud $7, (r3,r2) + ashud $-7, (r3,r2) + ashud $8, (r3,r2) + ashud $-8, (r3,r2) + ashud $4, (r3,r2) + ashud $-4, (r3,r2) + ashud $12,(r3,r2) + ashud $-12,(r3,r2) + ashud $3,(r2,r1) + ashud $-3,(r2,r1) + ##################################### + # ASHUD reg, regp + ##################################### + ashud r4,(r2,r1) + ashud r5,(r2,r1) + ashud r6,(r2,r1) + ashud r8,(r2,r1) + ashud r1,(r2,r1) diff --git a/gas/testsuite/gas/cr16/bal_test.d b/gas/testsuite/gas/cr16/bal_test.d new file mode 100644 index 000000000000..eb1558de9829 --- /dev/null +++ b/gas/testsuite/gas/cr16/bal_test.d @@ -0,0 +1,25 @@ +#as: +#objdump: -dr +#name: bal_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 0f c0 22 f1 bal \(ra\),\*\+0xff122 <main\+0xff122>:m + 4: ff c0 26 f1 bal \(ra\),\*\+0xfff12a <main\+0xfff12a>:m + 8: 00 c0 22 00 bal \(ra\),\*\+0x2a <main\+0x2a>:m + c: 00 c0 22 01 bal \(ra\),\*\+0x12e <main\+0x12e>:m + 10: 00 c0 22 f1 bal \(ra\),\*\+0xf132 <main\+0xf132>:m + 14: 00 c0 2a 81 bal \(ra\),\*\+0x813e <main\+0x813e>:m + 18: 10 00 00 20 bal \(r1,r0\),\*\+0x13a <main\+0x13a>:l + 1c: 22 01 + 1e: 10 00 ac 2f bal \(r11,r10\),\*\+0xcff140 <main\+0xcff140>:l + 22: 22 f1 + 24: 10 00 6a 2f bal \(r7,r6\),\*\+0xaff146 <main\+0xaff146>:l + 28: 22 f1 + 2a: 10 00 38 2f bal \(r4,r3\),\*\+0x8ff14c <main\+0x8ff14c>:l + 2e: 22 f1 + 30: 10 00 7f 2f bal \(r8,r7\),\*\+0xfff152 <main\+0xfff152>:l + 34: 22 f1 diff --git a/gas/testsuite/gas/cr16/bal_test.s b/gas/testsuite/gas/cr16/bal_test.s new file mode 100644 index 000000000000..b89f1f6baa65 --- /dev/null +++ b/gas/testsuite/gas/cr16/bal_test.s @@ -0,0 +1,14 @@ + .text
+ .global main
+main:
+bal (ra),*+0xff122
+bal (ra),*+0xfff126
+bal (ra),*+0x22
+bal (ra),*+0x122
+bal (ra),*+0xf122
+bal (ra),*+0x812a
+bal (r1,r0),*+0x122
+bal (r11,r10),*+0xcff122
+bal (r7,r6),*+0xaff122
+bal (r4,r3),*+0x8ff122
+bal (r8,r7),*+0xfff122
diff --git a/gas/testsuite/gas/cr16/bcc_test.d b/gas/testsuite/gas/cr16/bcc_test.d new file mode 100644 index 000000000000..4613edf92d4d --- /dev/null +++ b/gas/testsuite/gas/cr16/bcc_test.d @@ -0,0 +1,69 @@ +#as: +#objdump: -dr +#name: bcc_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 01 11 beq \*\+0x22 <main\+0x22>:s + 2: 19 11 bne \*\+0x34 <main\+0x34>:s + 4: 32 12 bcc \*\+0x48 <main\+0x48>:s + 6: 3a 12 bcc \*\+0x5a <main\+0x5a>:s + 8: 43 13 bhi \*\+0x6e <main\+0x6e>:s + a: cb 13 blt \*\+0x80 <main\+0x80>:s + c: 64 14 bgt \*\+0x94 <main\+0x94>:s + e: 8d 14 bfs \*\+0xa8 <main\+0xa8>:s + 10: 95 15 bfc \*\+0xba <main\+0xba>:s + 12: a0 18 bc 01 blo \*\+0x1ce <main\+0x1ce>:m + 16: 40 18 cc 01 bhi \*\+0x1e2 <main\+0x1e2>:m + 1a: c0 18 d6 01 blt \*\+0x1f0 <main\+0x1f0>:m + 1e: d0 18 e6 01 bge \*\+0x204 <main\+0x204>:m + 22: eb 17 br \*\+0x118 <main\+0x118>:s + 24: 00 18 12 01 beq \*\+0x136 <main\+0x136>:m + 28: 00 18 12 1f beq \*\+0x1f3a <main\+0x1f3a>:m + 2c: 00 18 22 0f beq \*\+0xf4e <main\+0xf4e>:m + 30: 10 18 34 0f bne \*\+0xf64 <main\+0xf64>:m + 34: 30 18 44 0f bcc \*\+0xf78 <main\+0xf78>:m + 38: 30 18 56 0f bcc \*\+0xf8e <main\+0xf8e>:m + 3c: 40 18 66 0f bhi \*\+0xfa2 <main\+0xfa2>:m + 40: c0 18 78 0f blt \*\+0xfb8 <main\+0xfb8>:m + 44: 60 18 88 0f bgt \*\+0xfcc <main\+0xfcc>:m + 48: 80 18 9a 0f bfs \*\+0xfe2 <main\+0xfe2>:m + 4c: 90 18 aa 0f bfc \*\+0xff6 <main\+0xff6>:m + 50: a0 18 bc 1f blo \*\+0x200c <main\+0x200c>:m + 54: 40 18 cc 1f bhi \*\+0x2020 <main\+0x2020>:m + 58: c0 18 da 1f blt \*\+0x2032 <main\+0x2032>:m + 5c: d0 18 ea 1f bge \*\+0x2046 <main\+0x2046>:m + 60: e0 18 fa ff br \*\+0x1005a <main\+0x1005a>:m + 64: 10 00 0f 0f beq \*\+0xff1f76 <main\+0xff1f76>:l + 68: 12 1f + 6a: 10 00 0a 0a beq \*\+0xaa0f8c <main\+0xaa0f8c>:l + 6e: 22 0f + 70: 10 00 1b 0b bne \*\+0xbb0fa4 <main\+0xbb0fa4>:l + 74: 34 0f + 76: 10 00 3c 0c bcc \*\+0xcc0fba <main\+0xcc0fba>:l + 7a: 44 0f + 7c: 10 00 3d 0d bcc \*\+0xdd0fd2 <main\+0xdd0fd2>:l + 80: 56 0f + 82: 10 00 49 09 bhi \*\+0x990fe8 <main\+0x990fe8>:l + 86: 66 0f + 88: 10 00 c8 08 blt \*\+0x881000 <main\+0x881000>:l + 8c: 78 0f + 8e: 10 00 67 07 bgt \*\+0x771016 <main\+0x771016>:l + 92: 88 0f + 94: 10 00 86 06 bfs \*\+0x66102e <main\+0x66102e>:l + 98: 9a 0f + 9a: 10 00 95 05 bfc \*\+0x551044 <main\+0x551044>:l + 9e: aa 0f + a0: 10 00 a4 04 blo \*\+0x44205c <main\+0x44205c>:l + a4: bc 1f + a6: 10 00 43 03 bhi \*\+0x332072 <main\+0x332072>:l + aa: cc 1f + ac: 10 00 c2 02 blt \*\+0x22208a <main\+0x22208a>:l + b0: de 1f + b2: 10 00 d1 01 bge \*\+0x1120a0 <main\+0x1120a0>:l + b6: ee 1f + b8: 10 00 e0 0f br \*\+0x1000b6 <main\+0x1000b6>:l + bc: fe ff diff --git a/gas/testsuite/gas/cr16/bcc_test.s b/gas/testsuite/gas/cr16/bcc_test.s new file mode 100644 index 000000000000..50f3fbe01d58 --- /dev/null +++ b/gas/testsuite/gas/cr16/bcc_test.s @@ -0,0 +1,59 @@ + .text
+ .global main
+main:
+ ###################
+ # bcc disp9/disp17/disp25
+ ###################
+ # bcc disp9
+ ###################
+ beq *+0x022
+ bne *+0x032
+ bcc *+0x044
+ bcc *+0x054
+ bhi *+0x066
+ blt *+0x076
+ bgt *+0x088
+ bfs *+0x09a
+ bfc *+0x0aa
+ blo *+0x1bc
+ bhi *+0x1cc
+ blt *+0x1d6
+ bge *+0x1e6
+ br *+0x0f6
+ ###################
+ # bcc disp17
+ ###################
+ beq *+0x112
+ beq *+0x1f12
+ beq *+0x0f22
+ bne *+0x0f34
+ bcc *+0x0f44
+ bcc *+0x0f56
+ bhi *+0x0f66
+ blt *+0x0f78
+ bgt *+0x0f88
+ bfs *+0x0f9a
+ bfc *+0x0faa
+ blo *+0x1fbc
+ bhi *+0x1fcc
+ blt *+0x1fda
+ bge *+0x1fea
+ br *+0xfffa
+ ###################
+ # bcc disp25
+ ###################
+ beq *+0xff1f12
+ beq *+0xaa0f22
+ bne *+0xbb0f34
+ bcc *+0xcc0f44
+ bcc *+0xdd0f56
+ bhi *+0x990f66
+ blt *+0x880f78
+ bgt *+0x770f88
+ bfs *+0x660f9a
+ bfc *+0x550faa
+ blo *+0x441fbc
+ bhi *+0x331fcc
+ blt *+0x221fde
+ bge *+0x111fee
+ br *+0x0ffffe
diff --git a/gas/testsuite/gas/cr16/beq0_test.d b/gas/testsuite/gas/cr16/beq0_test.d new file mode 100644 index 000000000000..82f923c01412 --- /dev/null +++ b/gas/testsuite/gas/cr16/beq0_test.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dr +#name: beq0_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 71 0c beq0b r1,\*\+0x10 <main\+0x10>:s + 2: b1 0c beq0b r1,\*\+0x18 <main\+0x18>:s + 4: e1 0c beq0b r1,\*\+0x1e <main\+0x1e>:s + 6: 71 0e beq0w r1,\*\+0x10 <main\+0x10>:s + 8: b1 0e beq0w r1,\*\+0x18 <main\+0x18>:s + a: e1 0e beq0w r1,\*\+0x1e <main\+0x1e>:s diff --git a/gas/testsuite/gas/cr16/beq0_test.s b/gas/testsuite/gas/cr16/beq0_test.s new file mode 100644 index 000000000000..70e9f6ab6ed5 --- /dev/null +++ b/gas/testsuite/gas/cr16/beq0_test.s @@ -0,0 +1,15 @@ + .text + .global main +main: + ################### + # beq0b reg, dispu5 + ################### + beq0b r1,*+16 + beq0b r1,*+24 + beq0b r1,*+30 + ################### + # beq0w reg, dispu5 + ################### + beq0w r1,*+16 + beq0w r1,*+24 + beq0w r1,*+30 diff --git a/gas/testsuite/gas/cr16/cbitb_test.d b/gas/testsuite/gas/cr16/cbitb_test.d new file mode 100644 index 000000000000..bbb382e503c0 --- /dev/null +++ b/gas/testsuite/gas/cr16/cbitb_test.d @@ -0,0 +1,82 @@ +#as: +#objdump: -dr +#name: cbitb_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: c0 6b cd 0b cbitb \$0x4,0xbcd <main\+0xbcd>:m + 4: da 6b cd ab cbitb \$0x5,0xaabcd <main\+0xaabcd>:m + 8: 10 00 3f 7a cbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: 50 68 14 00 cbitb \$0x5,\[r12\]0x14:m + 12: c0 68 fc ab cbitb \$0x4,\[r13\]0xabfc:m + 16: 30 68 34 12 cbitb \$0x3,\[r12\]0x1234:m + 1a: b0 68 34 12 cbitb \$0x3,\[r13\]0x1234:m + 1e: 30 68 34 00 cbitb \$0x3,\[r12\]0x34:m + 22: b0 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\) + 26: b1 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\) + 2a: b6 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\) + 2e: b2 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\) + 32: b7 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\) + 36: b3 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\) + 3a: b4 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\) + 3e: b5 6a 3a 4a cbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\) + 42: b8 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\) + 46: b9 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\) + 4a: be 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\) + 4e: ba 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\) + 52: bf 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\) + 56: bb 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\) + 5a: bc 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\) + 5e: bd 6a 3a 4a cbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\) + 62: be 6a 5a 4b cbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\) + 66: b7 6a 1a 41 cbitb \$0x1,\[r12\]0x17a:m\(r6,r5\) + 6a: bf 6a 14 01 cbitb \$0x1,\[r13\]0x134:m\(r6,r5\) + 6e: 10 00 36 6a cbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\) + 72: de bc + 74: 10 00 5e 60 cbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\) + 78: cd ab + 7a: 10 00 37 60 cbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\) + 7e: cd ab + 80: 10 00 3f 60 cbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\) + 84: de bc + 86: 10 00 52 40 cbitb \$0x5,0x0:l\(r2\) + 8a: 00 00 + 8c: 3c 6b 34 00 cbitb \$0x3,0x34:m\(r12\) + 90: 3d 6b ab 00 cbitb \$0x3,0xab:m\(r13\) + 94: 10 00 51 40 cbitb \$0x5,0xad:l\(r1\) + 98: ad 00 + 9a: 10 00 52 40 cbitb \$0x5,0xcd:l\(r2\) + 9e: cd 00 + a0: 10 00 50 40 cbitb \$0x5,0xfff:l\(r0\) + a4: ff 0f + a6: 10 00 34 40 cbitb \$0x3,0xbcd:l\(r4\) + aa: cd 0b + ac: 3c 6b ff 0f cbitb \$0x3,0xfff:m\(r12\) + b0: 3d 6b ff 0f cbitb \$0x3,0xfff:m\(r13\) + b4: 3d 6b ff ff cbitb \$0x3,0xffff:m\(r13\) + b8: 3c 6b 43 23 cbitb \$0x3,0x2343:m\(r12\) + bc: 10 00 32 41 cbitb \$0x3,0x2345:l\(r2\) + c0: 45 23 + c2: 10 00 38 44 cbitb \$0x3,0xabcd:l\(r8\) + c6: cd ab + c8: 10 00 3d 5f cbitb \$0x3,0xfabcd:l\(r13\) + cc: cd ab + ce: 10 00 38 4f cbitb \$0x3,0xabcd:l\(r8\) + d2: cd ab + d4: 10 00 39 4f cbitb \$0x3,0xabcd:l\(r9\) + d8: cd ab + da: 10 00 39 44 cbitb \$0x3,0xabcd:l\(r9\) + de: cd ab + e0: 31 6a cbitb \$0x3,0x0:s\(r2,r1\) + e2: 51 6b 01 00 cbitb \$0x5,0x1:m\(r2,r1\) + e6: 41 6b 34 12 cbitb \$0x4,0x1234:m\(r2,r1\) + ea: 31 6b 34 12 cbitb \$0x3,0x1234:m\(r2,r1\) + ee: 10 00 31 51 cbitb \$0x3,0x12345:l\(r2,r1\) + f2: 45 23 + f4: 31 6b 23 01 cbitb \$0x3,0x123:m\(r2,r1\) + f8: 10 00 31 51 cbitb \$0x3,0x12345:l\(r2,r1\) + fc: 45 23 diff --git a/gas/testsuite/gas/cr16/cbitb_test.s b/gas/testsuite/gas/cr16/cbitb_test.s new file mode 100644 index 000000000000..1e65ef304f2a --- /dev/null +++ b/gas/testsuite/gas/cr16/cbitb_test.s @@ -0,0 +1,62 @@ + .text + .global main +main: + cbitb $4,0xbcd + cbitb $5,0xaabcd + cbitb $3,0xfaabcd + + cbitb $5,[r12]0x14 + cbitb $4,[r13]0xabfc + cbitb $3,[r12]0x1234 + cbitb $3,[r13]0x1234 + cbitb $3,[r12]0x34 + + cbitb $3,[r12]0xa7a(r1,r0) + cbitb $3,[r12]0xa7a(r3,r2) + cbitb $3,[r12]0xa7a(r4,r3) + cbitb $3,[r12]0xa7a(r5,r4) + cbitb $3,[r12]0xa7a(r6,r5) + cbitb $3,[r12]0xa7a(r7,r6) + cbitb $3,[r12]0xa7a(r9,r8) + cbitb $3,[r12]0xa7a(r11,r10) + cbitb $3,[r13]0xa7a(r1,r0) + cbitb $3,[r13]0xa7a(r3,r2) + cbitb $3,[r13]0xa7a(r4,r3) + cbitb $3,[r13]0xa7a(r5,r4) + cbitb $3,[r13]0xa7a(r6,r5) + cbitb $3,[r13]0xa7a(r7,r6) + cbitb $3,[r13]0xa7a(r9,r8) + cbitb $3,[r13]0xa7a(r11,r10) + cbitb $5,[r13]0xb7a(r4,r3) + cbitb $1,[r12]0x17a(r6,r5) + cbitb $1,[r13]0x134(r6,r5) + cbitb $3,[r12]0xabcde(r4,r3) + cbitb $5,[r13]0xabcd(r4,r3) + cbitb $3,[r12]0xabcd(r6,r5) + cbitb $3,[r13]0xbcde(r6,r5) + + cbitb $5,0x0(r2) + cbitb $3,0x34(r12) + cbitb $3,0xab(r13) + cbitb $5,0xad(r1) + cbitb $5,0xcd(r2) + cbitb $5,0xfff(r0) + cbitb $3,0xbcd(r4) + cbitb $3,0xfff(r12) + cbitb $3,0xfff(r13) + cbitb $3,0xffff(r13) + cbitb $3,0x2343(r12) + cbitb $3,0x12345(r2) + cbitb $3,0x4abcd(r8) + cbitb $3,0xfabcd(r13) + cbitb $3,0xfabcd(r8) + cbitb $3,0xfabcd(r9) + cbitb $3,0x4abcd(r9) + + cbitb $3,0x0(r2,r1) + cbitb $5,0x1(r2,r1) + cbitb $4,0x1234(r2,r1) + cbitb $3,0x1234(r2,r1) + cbitb $3,0x12345(r2,r1) + cbitb $3,0x123(r2,r1) + cbitb $3,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/cbitw_test.d b/gas/testsuite/gas/cr16/cbitw_test.d new file mode 100644 index 000000000000..55e1543cd954 --- /dev/null +++ b/gas/testsuite/gas/cr16/cbitw_test.d @@ -0,0 +1,155 @@ +#as: +#objdump: -dr +#name: cbitw_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 40 6f cd 0b cbitw \$0x4:s,0xbcd <main\+0xbcd>:m + 4: 5a 6f cd ab cbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m + 8: 11 00 3f 7a cbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: a0 6f cd 0b cbitw \$0xa:s,0xbcd <main\+0xbcd>:m + 12: fa 6f cd ab cbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m + 16: 11 00 ef 7a cbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l + 1a: cd ab + 1c: 50 6c 14 00 cbitw \$0x5:s,\[r13\]0x14:m + 20: 40 6d fc ab cbitw \$0x4:s,\[r13\]0xabfc:m + 24: 30 6c 34 12 cbitw \$0x3:s,\[r12\]0x1234:m + 28: 30 6d 34 12 cbitw \$0x3:s,\[r12\]0x1234:m + 2c: 30 6c 34 00 cbitw \$0x3:s,\[r12\]0x34:m + 30: f0 6c 14 00 cbitw \$0xf:s,\[r13\]0x14:m + 34: e0 6d fc ab cbitw \$0xe:s,\[r13\]0xabfc:m + 38: d0 6c 34 12 cbitw \$0xd:s,\[r13\]0x1234:m + 3c: d0 6d 34 12 cbitw \$0xd:s,\[r13\]0x1234:m + 40: b0 6c 34 00 cbitw \$0xb:s,\[r12\]0x34:m + 44: f0 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\) + 48: f1 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\) + 4c: f6 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\) + 50: f2 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\) + 54: f7 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\) + 58: f3 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\) + 5c: f4 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\) + 60: f5 6a 3a 4a cbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\) + 64: f8 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\) + 68: f9 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\) + 6c: fe 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\) + 70: fa 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\) + 74: ff 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\) + 78: fb 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\) + 7c: fc 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\) + 80: fd 6a 3a 4a cbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\) + 84: fe 6a 5a 4b cbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\) + 88: f7 6a 1a 41 cbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\) + 8c: ff 6a 14 01 cbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\) + 90: 11 00 36 6a cbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\) + 94: de bc + 96: 11 00 5e 60 cbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\) + 9a: cd ab + 9c: 11 00 37 60 cbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\) + a0: cd ab + a2: 11 00 3f 60 cbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\) + a6: de bc + a8: f0 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\) + ac: f1 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\) + b0: f6 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\) + b4: f2 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\) + b8: f7 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\) + bc: f3 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\) + c0: f4 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\) + c4: f5 6a da 4a cbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\) + c8: f8 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\) + cc: f9 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\) + d0: fe 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\) + d4: fa 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\) + d8: ff 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\) + dc: fb 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\) + e0: fc 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\) + e4: fd 6a da 4a cbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\) + e8: fe 6a fa 4b cbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\) + ec: f7 6a ba 41 cbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\) + f0: ff 6a b4 01 cbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\) + f4: 11 00 d6 6a cbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\) + f8: de bc + fa: 11 00 fe 60 cbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\) + fe: cd ab + 100: 11 00 d7 60 cbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\) + 104: cd ab + 106: 11 00 df 60 cbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\) + 10a: de bc + 10c: 11 00 52 40 cbitw \$0x5:s,0x0:l\(r2\) + 110: 00 00 + 112: 3c 69 34 00 cbitw \$0x3:s,0x34:m\(r12\) + 116: 3d 69 ab 00 cbitw \$0x3:s,0xab:m\(r13\) + 11a: 11 00 51 40 cbitw \$0x5:s,0xad:l\(r1\) + 11e: ad 00 + 120: 11 00 52 40 cbitw \$0x5:s,0xcd:l\(r2\) + 124: cd 00 + 126: 11 00 50 40 cbitw \$0x5:s,0xfff:l\(r0\) + 12a: ff 0f + 12c: 11 00 34 40 cbitw \$0x3:s,0xbcd:l\(r4\) + 130: cd 0b + 132: 3c 69 ff 0f cbitw \$0x3:s,0xfff:m\(r12\) + 136: 3d 69 ff 0f cbitw \$0x3:s,0xfff:m\(r13\) + 13a: 3d 69 ff ff cbitw \$0x3:s,0xffff:m\(r13\) + 13e: 3c 69 43 23 cbitw \$0x3:s,0x2343:m\(r12\) + 142: 11 00 32 41 cbitw \$0x3:s,0x2345:l\(r2\) + 146: 45 23 + 148: 11 00 38 44 cbitw \$0x3:s,0xabcd:l\(r8\) + 14c: cd ab + 14e: 11 00 3d 5f cbitw \$0x3:s,0xfabcd:l\(r13\) + 152: cd ab + 154: 11 00 38 4f cbitw \$0x3:s,0xabcd:l\(r8\) + 158: cd ab + 15a: 11 00 39 4f cbitw \$0x3:s,0xabcd:l\(r9\) + 15e: cd ab + 160: 11 00 39 44 cbitw \$0x3:s,0xabcd:l\(r9\) + 164: cd ab + 166: 11 00 f2 40 cbitw \$0xf:s,0x0:l\(r2\) + 16a: 00 00 + 16c: dc 69 34 00 cbitw \$0xd:s,0x34:m\(r12\) + 170: dd 69 ab 00 cbitw \$0xd:s,0xab:m\(r13\) + 174: 11 00 f1 40 cbitw \$0xf:s,0xad:l\(r1\) + 178: ad 00 + 17a: 11 00 f2 40 cbitw \$0xf:s,0xcd:l\(r2\) + 17e: cd 00 + 180: 11 00 f0 40 cbitw \$0xf:s,0xfff:l\(r0\) + 184: ff 0f + 186: 11 00 d4 40 cbitw \$0xd:s,0xbcd:l\(r4\) + 18a: cd 0b + 18c: dc 69 ff 0f cbitw \$0xd:s,0xfff:m\(r12\) + 190: dd 69 ff 0f cbitw \$0xd:s,0xfff:m\(r13\) + 194: dd 69 ff ff cbitw \$0xd:s,0xffff:m\(r13\) + 198: dc 69 43 23 cbitw \$0xd:s,0x2343:m\(r12\) + 19c: 11 00 d2 41 cbitw \$0xd:s,0x2345:l\(r2\) + 1a0: 45 23 + 1a2: 11 00 d8 44 cbitw \$0xd:s,0xabcd:l\(r8\) + 1a6: cd ab + 1a8: 11 00 dd 5f cbitw \$0xd:s,0xfabcd:l\(r13\) + 1ac: cd ab + 1ae: 11 00 d8 4f cbitw \$0xd:s,0xabcd:l\(r8\) + 1b2: cd ab + 1b4: 11 00 d9 4f cbitw \$0xd:s,0xabcd:l\(r9\) + 1b8: cd ab + 1ba: 11 00 d9 44 cbitw \$0xd:s,0xabcd:l\(r9\) + 1be: cd ab + 1c0: 31 6e cbitw \$0x3:s,0x0:s\(r2,r1\) + 1c2: 51 69 01 00 cbitw \$0x5:s,0x1:m\(r2,r1\) + 1c6: 41 69 34 12 cbitw \$0x4:s,0x1234:m\(r2,r1\) + 1ca: 31 69 34 12 cbitw \$0x3:s,0x1234:m\(r2,r1\) + 1ce: 11 00 31 51 cbitw \$0x3:s,0x12345:l\(r2,r1\) + 1d2: 45 23 + 1d4: 31 69 23 01 cbitw \$0x3:s,0x123:m\(r2,r1\) + 1d8: 11 00 31 51 cbitw \$0x3:s,0x12345:l\(r2,r1\) + 1dc: 45 23 + 1de: d1 6e cbitw \$0xd:s,0x0:s\(r2,r1\) + 1e0: f1 69 01 00 cbitw \$0xf:s,0x1:m\(r2,r1\) + 1e4: e1 69 34 12 cbitw \$0xe:s,0x1234:m\(r2,r1\) + 1e8: d1 69 34 12 cbitw \$0xd:s,0x1234:m\(r2,r1\) + 1ec: 11 00 d1 51 cbitw \$0xd:s,0x12345:l\(r2,r1\) + 1f0: 45 23 + 1f2: d1 69 23 01 cbitw \$0xd:s,0x123:m\(r2,r1\) + 1f6: 11 00 d1 51 cbitw \$0xd:s,0x12345:l\(r2,r1\) + 1fa: 45 23 diff --git a/gas/testsuite/gas/cr16/cbitw_test.s b/gas/testsuite/gas/cr16/cbitw_test.s new file mode 100644 index 000000000000..61bda0874904 --- /dev/null +++ b/gas/testsuite/gas/cr16/cbitw_test.s @@ -0,0 +1,117 @@ + .text + .global main +main: + cbitw $4,0xbcd + cbitw $5,0xaabcd + cbitw $3,0xfaabcd + cbitw $10,0xbcd + cbitw $15,0xaabcd + cbitw $14,0xfaabcd + + cbitw $5,[r12]0x14 + cbitw $4,[r13]0xabfc + cbitw $3,[r12]0x1234 + cbitw $3,[r13]0x1234 + cbitw $3,[r12]0x34 + cbitw $15,[r12]0x14 + cbitw $14,[r13]0xabfc + cbitw $13,[r12]0x1234 + cbitw $13,[r13]0x1234 + cbitw $11,[r12]0x34 + + cbitw $3,[r12]0xa7a(r1,r0) + cbitw $3,[r12]0xa7a(r3,r2) + cbitw $3,[r12]0xa7a(r4,r3) + cbitw $3,[r12]0xa7a(r5,r4) + cbitw $3,[r12]0xa7a(r6,r5) + cbitw $3,[r12]0xa7a(r7,r6) + cbitw $3,[r12]0xa7a(r9,r8) + cbitw $3,[r12]0xa7a(r11,r10) + cbitw $3,[r13]0xa7a(r1,r0) + cbitw $3,[r13]0xa7a(r3,r2) + cbitw $3,[r13]0xa7a(r4,r3) + cbitw $3,[r13]0xa7a(r5,r4) + cbitw $3,[r13]0xa7a(r6,r5) + cbitw $3,[r13]0xa7a(r7,r6) + cbitw $3,[r13]0xa7a(r9,r8) + cbitw $3,[r13]0xa7a(r11,r10) + cbitw $5,[r13]0xb7a(r4,r3) + cbitw $1,[r12]0x17a(r6,r5) + cbitw $1,[r13]0x134(r6,r5) + cbitw $3,[r12]0xabcde(r4,r3) + cbitw $5,[r13]0xabcd(r4,r3) + cbitw $3,[r12]0xabcd(r6,r5) + cbitw $3,[r13]0xbcde(r6,r5) + cbitw $13,[r12]0xa7a(r1,r0) + cbitw $13,[r12]0xa7a(r3,r2) + cbitw $13,[r12]0xa7a(r4,r3) + cbitw $13,[r12]0xa7a(r5,r4) + cbitw $13,[r12]0xa7a(r6,r5) + cbitw $13,[r12]0xa7a(r7,r6) + cbitw $13,[r12]0xa7a(r9,r8) + cbitw $13,[r12]0xa7a(r11,r10) + cbitw $13,[r13]0xa7a(r1,r0) + cbitw $13,[r13]0xa7a(r3,r2) + cbitw $13,[r13]0xa7a(r4,r3) + cbitw $13,[r13]0xa7a(r5,r4) + cbitw $13,[r13]0xa7a(r6,r5) + cbitw $13,[r13]0xa7a(r7,r6) + cbitw $13,[r13]0xa7a(r9,r8) + cbitw $13,[r13]0xa7a(r11,r10) + cbitw $15,[r13]0xb7a(r4,r3) + cbitw $11,[r12]0x17a(r6,r5) + cbitw $11,[r13]0x134(r6,r5) + cbitw $13,[r12]0xabcde(r4,r3) + cbitw $15,[r13]0xabcd(r4,r3) + cbitw $13,[r12]0xabcd(r6,r5) + cbitw $13,[r13]0xbcde(r6,r5) + + cbitw $5,0x0(r2) + cbitw $3,0x34(r12) + cbitw $3,0xab(r13) + cbitw $5,0xad(r1) + cbitw $5,0xcd(r2) + cbitw $5,0xfff(r0) + cbitw $3,0xbcd(r4) + cbitw $3,0xfff(r12) + cbitw $3,0xfff(r13) + cbitw $3,0xffff(r13) + cbitw $3,0x2343(r12) + cbitw $3,0x12345(r2) + cbitw $3,0x4abcd(r8) + cbitw $3,0xfabcd(r13) + cbitw $3,0xfabcd(r8) + cbitw $3,0xfabcd(r9) + cbitw $3,0x4abcd(r9) + cbitw $15,0x0(r2) + cbitw $13,0x34(r12) + cbitw $13,0xab(r13) + cbitw $15,0xad(r1) + cbitw $15,0xcd(r2) + cbitw $15,0xfff(r0) + cbitw $13,0xbcd(r4) + cbitw $13,0xfff(r12) + cbitw $13,0xfff(r13) + cbitw $13,0xffff(r13) + cbitw $13,0x2343(r12) + cbitw $13,0x12345(r2) + cbitw $13,0x4abcd(r8) + cbitw $13,0xfabcd(r13) + cbitw $13,0xfabcd(r8) + cbitw $13,0xfabcd(r9) + cbitw $13,0x4abcd(r9) + + cbitw $3,0x0(r2,r1) + cbitw $5,0x1(r2,r1) + cbitw $4,0x1234(r2,r1) + cbitw $3,0x1234(r2,r1) + cbitw $3,0x12345(r2,r1) + cbitw $3,0x123(r2,r1) + cbitw $3,0x12345(r2,r1) + cbitw $13,0x0(r2,r1) + cbitw $15,0x1(r2,r1) + cbitw $14,0x1234(r2,r1) + cbitw $13,0x1234(r2,r1) + cbitw $13,0x12345(r2,r1) + cbitw $13,0x123(r2,r1) + cbitw $13,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/cinv_test.d b/gas/testsuite/gas/cr16/cinv_test.d new file mode 100644 index 000000000000..f1e2f253b5a3 --- /dev/null +++ b/gas/testsuite/gas/cr16/cinv_test.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dr +#name: cinv_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 0a 00 cinv \[i\] + 2: 0b 00 cinv \[i,u\] + 4: 0c 00 cinv \[d\] + 6: 0d 00 cinv \[d,u\] + 8: 0e 00 cinv \[d,i\] + a: 0f 00 cinv \[d,i,u\] diff --git a/gas/testsuite/gas/cr16/cinv_test.s b/gas/testsuite/gas/cr16/cinv_test.s new file mode 100644 index 000000000000..eda4b97bad23 --- /dev/null +++ b/gas/testsuite/gas/cr16/cinv_test.s @@ -0,0 +1,12 @@ + .text
+ .global main
+main:
+ ##############################
+ # cin [i/i,u/d/d,u/d,i/d,i,u]
+ ##############################
+ cinv [i]
+ cinv [i,u]
+ cinv [d]
+ cinv [d,u]
+ cinv [d,i]
+ cinv [d,i,u]
diff --git a/gas/testsuite/gas/cr16/cmp_test.d b/gas/testsuite/gas/cr16/cmp_test.d new file mode 100644 index 000000000000..6c3e101740be --- /dev/null +++ b/gas/testsuite/gas/cr16/cmp_test.d @@ -0,0 +1,51 @@ +#as: +#objdump: -dr +#name: cmp_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 50 cmpb \$0xf:s,r1 + 2: b2 50 ff 00 cmpb \$0xff:m,r2 + 6: b1 50 ff 0f cmpb \$0xfff:m,r1 + a: b1 50 14 00 cmpb \$0x14:m,r1 + e: a2 50 cmpb \$0xa:s,r2 + 10: b2 50 0b 00 cmpb \$0xb:m,r2 + 14: 12 51 cmpb r1,r2 + 16: 23 51 cmpb r2,r3 + 18: 34 51 cmpb r3,r4 + 1a: 56 51 cmpb r5,r6 + 1c: 67 51 cmpb r6,r7 + 1e: 78 51 cmpb r7,r8 + 20: f1 52 cmpw \$0xf:s,r1 + 22: b1 52 0b 00 cmpw \$0xb:m,r1 + 26: b2 52 ff 00 cmpw \$0xff:m,r2 + 2a: b1 52 ff 0f cmpw \$0xfff:m,r1 + 2e: b1 52 14 00 cmpw \$0x14:m,r1 + 32: a2 52 cmpw \$0xa:s,r2 + 34: b2 52 0b 00 cmpw \$0xb:m,r2 + 38: 12 53 cmpw r1,r2 + 3a: 23 53 cmpw r2,r3 + 3c: 34 53 cmpw r3,r4 + 3e: 56 53 cmpw r5,r6 + 40: 67 53 cmpw r6,r7 + 42: 78 53 cmpw r7,r8 + 44: f1 56 cmpd \$0xf:s,\(r2,r1\) + 46: b1 56 0b 00 cmpd \$0xb:m,\(r2,r1\) + 4a: b1 56 ff 00 cmpd \$0xff:m,\(r2,r1\) + 4e: b1 56 ff 0f cmpd \$0xfff:m,\(r2,r1\) + 52: 91 00 00 00 cmpd \$0xffff:l,\(r2,r1\) + 56: ff ff + 58: 91 00 0f 00 cmpd \$0xfffff:l,\(r2,r1\) + 5c: ff ff + 5e: 91 00 ff 0f cmpd \$0xfffffff:l,\(r2,r1\) + 62: ff ff + 64: 91 56 cmpd \$-1:s,\(r2,r1\) + 66: 31 57 cmpd \(r4,r3\),\(r2,r1\) + 68: 31 57 cmpd \(r4,r3\),\(r2,r1\) + 6a: af 56 cmpd \$0xa:s,\(sp\) + 6c: ef 56 cmpd \$0xe:s,\(sp\) + 6e: bf 56 0b 00 cmpd \$0xb:m,\(sp\) + 72: 8f 56 cmpd \$0x8:s,\(sp\) diff --git a/gas/testsuite/gas/cr16/cmp_test.s b/gas/testsuite/gas/cr16/cmp_test.s new file mode 100644 index 000000000000..2d0af3bce71d --- /dev/null +++ b/gas/testsuite/gas/cr16/cmp_test.s @@ -0,0 +1,62 @@ + .text + .global main +main: + ########### + # CMPB imm4/imm16, reg + ########### + cmpb $0xf,r1 + cmpb $0xff,r2 + cmpb $0xfff,r1 + #cmpb $0xffff,r2 // CHCEFK WITH CRASM 4.1 + cmpb $20,r1 + cmpb $10,r2 + cmpb $11,r2 + ########### + # CMPB reg, reg + ########### + cmpb r1,r2 + cmpb r2,r3 + cmpb r3,r4 + cmpb r5,r6 + cmpb r6,r7 + cmpb r7,r8 + ########### + # CMPW imm4/imm16, reg + ########### + cmpw $0xf,r1 + cmpw $0xB,r1 + cmpw $0xff,r2 + cmpw $0xfff,r1 + #cmpw $0xffff,r2 // CHECK WITH CRASM 4.1 + cmpw $20,r1 + cmpw $10,r2 + cmpw $11,r2 + ########### + # CMPW reg, reg + ########### + cmpw r1,r2 + cmpw r2,r3 + cmpw r3,r4 + cmpw r5,r6 + cmpw r6,r7 + cmpw r7,r8 + ########### + # CMPD imm4/imm16/imm32, regp + ########### + cmpd $0xf,(r2,r1) + cmpd $0xB,(r2,r1) + cmpd $0xff,(r2,r1) + cmpd $0xfff,(r2,r1) + cmpd $0xffff,(r2,r1) + cmpd $0xfffff,(r2,r1) + cmpd $0xfffffff,(r2,r1) + cmpd $0xffffffff,(r2,r1) + ########### + # CMPD regp, regp + ########### + cmpd (r4,r3),(r2,r1) + cmpd (r4,r3),(r2,r1) + cmpd $10,(sp) + cmpd $14,(sp) + cmpd $11,(sp) + cmpd $8,(sp) diff --git a/gas/testsuite/gas/cr16/cr16.exp b/gas/testsuite/gas/cr16/cr16.exp new file mode 100644 index 000000000000..6697c33d6aee --- /dev/null +++ b/gas/testsuite/gas/cr16/cr16.exp @@ -0,0 +1,27 @@ +# +# Driver for CR16 assembler testsuite +# + +proc run_list_test { name opts } { + global srcdir subdir + set testname "cr16 $name" + set file $srcdir/$subdir/$name + gas_run ${name}.s $opts ">&dump.out" + if {[regexp_diff "dump.out" "${file}.l"] } { + fail $testname + verbose "output is [file_contents "dump.out"]" 2 + return + } + pass $testname +} + +if ![istarget cr16-*-*] { + return +} + +set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +foreach test $test_list { + # We need to strip the ".d", but can leave the dirname. + verbose [file rootname $test] + run_dump_test [file rootname $test] +} diff --git a/gas/testsuite/gas/cr16/excp_test.d b/gas/testsuite/gas/cr16/excp_test.d new file mode 100644 index 000000000000..7c4053b8aa58 --- /dev/null +++ b/gas/testsuite/gas/cr16/excp_test.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dr +#name: excp_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: c5 00 excp svc + 2: c6 00 excp dvz + 4: c7 00 excp flg + 6: c8 00 excp bpt + 8: c9 00 excp trc + a: ca 00 excp und + c: cc 00 excp iad + e: ce 00 excp dbg + 10: cf 00 excp ise diff --git a/gas/testsuite/gas/cr16/excp_test.s b/gas/testsuite/gas/cr16/excp_test.s new file mode 100644 index 000000000000..4984a749ed20 --- /dev/null +++ b/gas/testsuite/gas/cr16/excp_test.s @@ -0,0 +1,15 @@ + .text + .global main +main: + ########################################## + # excp svc/dvz/flg/bpt/trc/und/iad/dbg/ise + ########################################## + excp svc + excp dvz + excp flg + excp bpt + excp trc + excp und + excp iad + excp dbg + excp ise diff --git a/gas/testsuite/gas/cr16/jal_test.d b/gas/testsuite/gas/cr16/jal_test.d new file mode 100644 index 000000000000..51a4e7637c6c --- /dev/null +++ b/gas/testsuite/gas/cr16/jal_test.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dr +#name: jal_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: d1 00 jal \(r2,r1\) + 2: 14 00 15 80 jal \(r6,r5\),\(r2,r1\) + 6: 14 00 32 80 jal \(r3,r2\),\(r4,r3\) + a: 14 00 30 80 jal \(r1,r0\),\(r4,r3\) + e: 14 00 72 80 jal \(r3,r2\),\(r8,r7\) diff --git a/gas/testsuite/gas/cr16/jal_test.s b/gas/testsuite/gas/cr16/jal_test.s new file mode 100644 index 000000000000..2a4715b98f4e --- /dev/null +++ b/gas/testsuite/gas/cr16/jal_test.s @@ -0,0 +1,11 @@ + .text + .global main +main: + ################ + # JAL regp regp + ################ + jal (r2,r1) + jal (r6,r5),(r2,r1) + jal (r3,r2),(r4,r3) + jal (r1,r0), (r4,r3) + jal (r3,r2), (r8,r7) diff --git a/gas/testsuite/gas/cr16/jcc_test.d b/gas/testsuite/gas/cr16/jcc_test.d new file mode 100644 index 000000000000..e192c9db0ac3 --- /dev/null +++ b/gas/testsuite/gas/cr16/jcc_test.d @@ -0,0 +1,24 @@ +#as: +#objdump: -dr +#name: jcc_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 0a jeq \(r1,r0\) + 2: 11 0a jne \(r2,r1\) + 4: 32 0a jcc \(r3,r2\) + 6: 33 0a jcc \(r4,r3\) + 8: 44 0a jhi \(r5,r4\) + a: c5 0a jlt \(r6,r5\) + c: 66 0a jgt \(r7,r6\) + e: 87 0a jfs \(r8,r7\) + 10: 98 0a jfc \(r9,r8\) + 12: a9 0a jlo \(r10,r9\) + 14: 4a 0a jhi \(r11,r10\) + 16: c0 0a jlt \(r1,r0\) + 18: d2 0a jge \(r3,r2\) + 1a: e5 0a jump \(r6,r5\) + 1c: f5 0a jusr \(r6,r5\) diff --git a/gas/testsuite/gas/cr16/jcc_test.s b/gas/testsuite/gas/cr16/jcc_test.s new file mode 100644 index 000000000000..c384e1a9daa2 --- /dev/null +++ b/gas/testsuite/gas/cr16/jcc_test.s @@ -0,0 +1,21 @@ + .text + .global main +main: + ########## + # JCond regp + ########## + jeq (r1,r0) + jne (r2,r1) + jcc (r3,r2) + jcc (r4,r3) + jhi (r5,r4) + jlt (r6,r5) + jgt (r7,r6) + jfs (r8,r7) + jfc (r9,r8) + jlo (r10,r9) + jhi (r11,r10) + jlt (r1,r0) + jge (r3,r2) + jump (r6,r5) + jusr (r6,r5) diff --git a/gas/testsuite/gas/cr16/loadb_test.d b/gas/testsuite/gas/cr16/loadb_test.d new file mode 100644 index 000000000000..0e22d5743b0f --- /dev/null +++ b/gas/testsuite/gas/cr16/loadb_test.d @@ -0,0 +1,79 @@ +#as: +#objdump: -dr +#name: loadd_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 88 00 00 loadb 0x0 <main>:m,r0 + 4: 10 88 ff 00 loadb 0xff <main\+0xff>:m,r1 + 8: 30 88 ff 0f loadb 0xfff <main\+0xfff>:m,r3 + c: 40 88 34 12 loadb 0x1234 <main\+0x1234>:m,r4 + 10: 50 88 34 12 loadb 0x1234 <main\+0x1234>:m,r5 + 14: 12 00 07 7a loadb 0x7a1234 <main\+0x7a1234>:l,r0 + 18: 34 12 + 1a: 12 00 1b 7a loadb 0xba1234 <main\+0xba1234>:l,r1 + 1e: 34 12 + 20: 2f 88 ff ff loadb 0xfffff <main\+0xfffff>:m,r2 + 24: 00 8a 00 00 loadb \[r12\]0x0:m,r0 + 28: 00 8b 00 00 loadb \[r12\]0x0:m,r0 + 2c: 10 8a ff 00 loadb \[r12\]0xff:m,r1 + 30: 10 8b ff 00 loadb \[r12\]0xff:m,r1 + 34: 30 8a ff 0f loadb \[r12\]0xfff:m,r3 + 38: 30 8b ff 0f loadb \[r12\]0xfff:m,r3 + 3c: 40 8a 34 12 loadb \[r13\]0x1234:m,r4 + 40: 40 8b 34 12 loadb \[r13\]0x1234:m,r4 + 44: 50 8a 34 12 loadb \[r13\]0x1234:m,r5 + 48: 50 8b 34 12 loadb \[r13\]0x1234:m,r5 + 4c: 20 8a 67 45 loadb \[r12\]0x4567:m,r2 + 50: 2a 8b 34 12 loadb \[r12\]0xa1234:m,r2 + 54: 10 b4 loadb 0x4:s\(r1,r0\),r1 + 56: 32 b4 loadb 0x4:s\(r3,r2\),r3 + 58: 40 bf 34 12 loadb 0x1234:m\(r1,r0\),r4 + 5c: 52 bf 34 12 loadb 0x1234:m\(r3,r2\),r5 + 60: 12 00 60 5a loadb 0xa1234:l\(r1,r0\),r6 + 64: 34 12 + 66: 18 00 10 5f loadb 0xffffc:l\(r1,r0\),r1 + 6a: fc ff + 6c: 18 00 32 5f loadb 0xffffc:l\(r3,r2\),r3 + 70: fc ff + 72: 18 00 40 5f loadb 0xfedcc:l\(r1,r0\),r4 + 76: cc ed + 78: 18 00 52 5f loadb 0xfedcc:l\(r3,r2\),r5 + 7c: cc ed + 7e: 18 00 60 55 loadb 0x5edcc:l\(r1,r0\),r6 + 82: cc ed + 84: 00 b0 loadb 0x0:s\(r1,r0\),r0 + 86: 10 b0 loadb 0x0:s\(r1,r0\),r1 + 88: 00 bf 0f 00 loadb 0xf:m\(r1,r0\),r0 + 8c: 10 bf 0f 00 loadb 0xf:m\(r1,r0\),r1 + 90: 20 bf 34 12 loadb 0x1234:m\(r1,r0\),r2 + 94: 32 bf cd ab loadb 0xabcd:m\(r3,r2\),r3 + 98: 43 bf ff af loadb 0xafff:m\(r4,r3\),r4 + 9c: 12 00 55 5a loadb 0xa1234:l\(r6,r5\),r5 + a0: 34 12 + a2: 18 00 00 5f loadb 0xffff1:l\(r1,r0\),r0 + a6: f1 ff + a8: 18 00 10 5f loadb 0xffff1:l\(r1,r0\),r1 + ac: f1 ff + ae: 18 00 20 5f loadb 0xfedcc:l\(r1,r0\),r2 + b2: cc ed + b4: 18 00 32 5f loadb 0xf5433:l\(r3,r2\),r3 + b8: 33 54 + ba: 18 00 43 5f loadb 0xf5001:l\(r4,r3\),r4 + be: 01 50 + c0: 18 00 55 55 loadb 0x5edcc:l\(r6,r5\),r5 + c4: cc ed + c6: 00 be loadb \[r12\]0x0:s\(r1,r0\),r0 + c8: 18 be loadb \[r13\]0x0:s\(r1,r0\),r1 + ca: 70 86 04 12 loadb \[r12\]0x234:m\(r1,r0\),r7 + ce: 12 00 38 61 loadb \[r13\]0x1abcd:l\(r1,r0\),r3 + d2: cd ab + d4: 12 00 40 6a loadb \[r12\]0xa1234:l\(r1,r0\),r4 + d8: 34 12 + da: 12 00 58 6b loadb \[r13\]0xb1234:l\(r1,r0\),r5 + de: 34 12 + e0: 12 00 68 6f loadb \[r13\]0xfffff:l\(r1,r0\),r6 + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadb_test.s b/gas/testsuite/gas/cr16/loadb_test.s new file mode 100644 index 000000000000..258e3b380048 --- /dev/null +++ b/gas/testsuite/gas/cr16/loadb_test.s @@ -0,0 +1,72 @@ + .text
+ .global main
+main:
+ ######################
+ # loadb abs20/24 reg
+ ######################
+ loadb 0x0,r0
+ loadb 0xff,r1
+ loadb 0xfff,r3
+ loadb 0x1234,r4
+ loadb 0x1234,r5
+ loadb 0x7A1234,r0
+ loadb 0xBA1234,r1
+ loadb 0xffffff,r2
+ ######################
+ # loadb abs20 rel reg
+ ######################
+ loadb [r12]0x0,r0
+ loadb [r13]0x0,r0
+ loadb [r12]0xff,r1
+ loadb [r13]0xff,r1
+ loadb [r12]0xfff,r3
+ loadb [r13]0xfff,r3
+ loadb [r12]0x1234,r4
+ loadb [r13]0x1234,r4
+ loadb [r12]0x1234,r5
+ loadb [r13]0x1234,r5
+ loadb [r12]0x4567,r2
+ loadb [r13]0xA1234,r2
+ ###################################
+ # loadb rbase(disp20/-disp20) reg
+ ###################################
+ loadb 0x4(r1,r0),r1
+ loadb 0x4(r3,r2),r3
+ loadb 0x1234(r1,r0),r4
+ loadb 0x1234(r3,r2),r5
+ loadb 0xA1234(r1,r0),r6
+ loadb -0x4(r1,r0),r1
+ loadb -0x4(r3,r2),r3
+ loadb -0x1234(r1,r0),r4
+ loadb -0x1234(r3,r2),r5
+ loadb -0xA1234(r1,r0),r6
+ #################################################
+ # loadb rpbase(disp4/disp16/disp20/-disp20) reg
+ #################################################
+ loadb 0x0(r1,r0),r0
+ loadb 0x0(r1,r0),r1
+ loadb 0xf(r1,r0),r0
+ loadb 0xf(r1,r0),r1
+ loadb 0x1234(r1,r0),r2
+ loadb 0xabcd(r3,r2),r3
+ loadb 0xAfff(r4,r3),r4
+ loadb 0xA1234(r6,r5),r5
+ loadb -0xf(r1,r0),r0
+ loadb -0xf(r1,r0),r1
+ loadb -0x1234(r1,r0),r2
+ loadb -0xabcd(r3,r2),r3
+ loadb -0xAfff(r4,r3),r4
+ loadb -0xA1234(r6,r5),r5
+ ####################################
+ # loadb rbase(disp0/disp14) rel reg
+ ####################################
+ loadb [r12]0x0(r1,r0),r0
+ loadb [r13]0x0(r1,r0),r1
+ loadb [r12]0x1234(r1,r0),r2
+ loadb [r13]0x1abcd(r1,r0),r3
+ #################################
+ # loadb rpbase(disp20) rel reg
+ #################################
+ loadb [r12]0xA1234(r1,r0),r4
+ loadb [r13]0xB1234(r1,r0),r5
+ loadb [r13]0xfffff(r1,r0),r6
diff --git a/gas/testsuite/gas/cr16/loadd_test.d b/gas/testsuite/gas/cr16/loadd_test.d new file mode 100644 index 000000000000..77ea45fc8b6d --- /dev/null +++ b/gas/testsuite/gas/cr16/loadd_test.d @@ -0,0 +1,79 @@ +#as: +#objdump: -dr +#name: loadd_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 87 00 00 loadd 0x0 <main>:m,\(r1,r0\) + 4: 00 87 ff 00 loadd 0xff <main\+0xff>:m,\(r1,r0\) + 8: 20 87 ff 0f loadd 0xfff <main\+0xfff>:m,\(r3,r2\) + c: 30 87 34 12 loadd 0x1234 <main\+0x1234>:m,\(r4,r3\) + 10: 40 87 34 12 loadd 0x1234 <main\+0x1234>:m,\(r5,r4\) + 14: 12 00 07 ba loadd 0x7a1234 <main\+0x7a1234>:l,\(r1,r0\) + 18: 34 12 + 1a: 12 00 0b ba loadd 0xba1234 <main\+0xba1234>:l,\(r1,r0\) + 1e: 34 12 + 20: 1f 87 ff ff loadd 0xfffff <main\+0xfffff>:m,\(r2,r1\) + 24: 00 8c 00 00 loadd \[r12\]0x0:m,\(r1,r0\) + 28: 00 8d 00 00 loadd \[r12\]0x0:m,\(r1,r0\) + 2c: 00 8c ff 00 loadd \[r12\]0xff:m,\(r1,r0\) + 30: 00 8d ff 00 loadd \[r12\]0xff:m,\(r1,r0\) + 34: 20 8c ff 0f loadd \[r12\]0xfff:m,\(r3,r2\) + 38: 20 8d ff 0f loadd \[r12\]0xfff:m,\(r3,r2\) + 3c: 30 8c 34 12 loadd \[r12\]0x1234:m,\(r4,r3\) + 40: 30 8d 34 12 loadd \[r12\]0x1234:m,\(r4,r3\) + 44: 40 8c 34 12 loadd \[r13\]0x1234:m,\(r5,r4\) + 48: 40 8d 34 12 loadd \[r13\]0x1234:m,\(r5,r4\) + 4c: 10 8c 67 45 loadd \[r12\]0x4567:m,\(r2,r1\) + 50: 1a 8d 34 12 loadd \[r12\]0xa1234:m,\(r2,r1\) + 54: 10 a2 loadd 0x4:s\(r1,r0\),\(r2,r1\) + 56: 22 a2 loadd 0x4:s\(r3,r2\),\(r3,r2\) + 58: 30 af 34 12 loadd 0x1234:m\(r1,r0\),\(r4,r3\) + 5c: 42 af 34 12 loadd 0x1234:m\(r3,r2\),\(r5,r4\) + 60: 12 00 50 9a loadd 0xa1234:l\(r1,r0\),\(r6,r5\) + 64: 34 12 + 66: 18 00 10 9f loadd 0xffffc:l\(r1,r0\),\(r2,r1\) + 6a: fc ff + 6c: 18 00 22 9f loadd 0xffffc:l\(r3,r2\),\(r3,r2\) + 70: fc ff + 72: 18 00 30 9f loadd 0xfedcc:l\(r1,r0\),\(r4,r3\) + 76: cc ed + 78: 18 00 42 9f loadd 0xfedcc:l\(r3,r2\),\(r5,r4\) + 7c: cc ed + 7e: 18 00 50 95 loadd 0x5edcc:l\(r1,r0\),\(r6,r5\) + 82: cc ed + 84: 00 a0 loadd 0x0:s\(r1,r0\),\(r1,r0\) + 86: 00 a0 loadd 0x0:s\(r1,r0\),\(r1,r0\) + 88: 00 af 0f 00 loadd 0xf:m\(r1,r0\),\(r1,r0\) + 8c: 00 af 0f 00 loadd 0xf:m\(r1,r0\),\(r1,r0\) + 90: 10 af 34 12 loadd 0x1234:m\(r1,r0\),\(r2,r1\) + 94: 22 af cd ab loadd 0xabcd:m\(r3,r2\),\(r3,r2\) + 98: 33 af ff af loadd 0xafff:m\(r4,r3\),\(r4,r3\) + 9c: 12 00 65 9a loadd 0xa1234:l\(r6,r5\),\(r7,r6\) + a0: 34 12 + a2: 18 00 00 9f loadd 0xffff1:l\(r1,r0\),\(r1,r0\) + a6: f1 ff + a8: 18 00 00 9f loadd 0xffff1:l\(r1,r0\),\(r1,r0\) + ac: f1 ff + ae: 18 00 10 9f loadd 0xfedcc:l\(r1,r0\),\(r2,r1\) + b2: cc ed + b4: 18 00 22 9f loadd 0xf5433:l\(r3,r2\),\(r3,r2\) + b8: 33 54 + ba: 18 00 43 9f loadd 0xf5001:l\(r4,r3\),\(r5,r4\) + be: 01 50 + c0: 18 00 45 95 loadd 0x5edcc:l\(r6,r5\),\(r5,r4\) + c4: cc ed + c6: 00 ae loadd \[r12\]0x0:s\(r1,r0\),\(r1,r0\) + c8: 08 ae loadd \[r13\]0x0:s\(r1,r0\),\(r1,r0\) + ca: b0 86 04 12 loadd \[r12\]0x234:m\(r1,r0\),\(r12,r11\) + ce: 12 00 28 a1 loadd \[r13\]0x1abcd:l\(r1,r0\),\(r3,r2\) + d2: cd ab + d4: 12 00 20 aa loadd \[r12\]0xa1234:l\(r1,r0\),\(r3,r2\) + d8: 34 12 + da: 12 00 38 ab loadd \[r13\]0xb1234:l\(r1,r0\),\(r4,r3\) + de: 34 12 + e0: 12 00 48 af loadd \[r13\]0xfffff:l\(r1,r0\),\(r5,r4\) + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadd_test.s b/gas/testsuite/gas/cr16/loadd_test.s new file mode 100644 index 000000000000..677752d7522d --- /dev/null +++ b/gas/testsuite/gas/cr16/loadd_test.s @@ -0,0 +1,72 @@ + .text
+ .global main
+main:
+ ######################
+ # loadd abs20/24 regp
+ ######################
+ loadd 0x0,(r1,r0)
+ loadd 0xff,(r1,r0)
+ loadd 0xfff,(r3,r2)
+ loadd 0x1234,(r4,r3)
+ loadd 0x1234,(r5,r4)
+ loadd 0x7A1234,(r1,r0)
+ loadd 0xBA1234,(r1,r0)
+ loadd 0xffffff,(r2,r1)
+ ######################
+ # loadd abs20 rel regp
+ ######################
+ loadd [r12]0x0,(r1,r0)
+ loadd [r13]0x0,(r1,r0)
+ loadd [r12]0xff,(r1,r0)
+ loadd [r13]0xff,(r1,r0)
+ loadd [r12]0xfff,(r3,r2)
+ loadd [r13]0xfff,(r3,r2)
+ loadd [r12]0x1234,(r4,r3)
+ loadd [r13]0x1234,(r4,r3)
+ loadd [r12]0x1234,(r5,r4)
+ loadd [r13]0x1234,(r5,r4)
+ loadd [r12]0x4567,(r2,r1)
+ loadd [r13]0xA1234,(r2,r1)
+ ###################################
+ # loadd rbase(disp20/-disp20) regp
+ ###################################
+ loadd 0x4(r1,r0),(r2,r1)
+ loadd 0x4(r3,r2),(r3,r2)
+ loadd 0x1234(r1,r0),(r4,r3)
+ loadd 0x1234(r3,r2),(r5,r4)
+ loadd 0xA1234(r1,r0),(r6,r5)
+ loadd -0x4(r1,r0),(r2,r1)
+ loadd -0x4(r3,r2),(r3,r2)
+ loadd -0x1234(r1,r0),(r4,r3)
+ loadd -0x1234(r3,r2),(r5,r4)
+ loadd -0xA1234(r1,r0),(r6,r5)
+ #################################################
+ # loadd rpbase(disp4/disp16/disp20/-disp20) reg
+ #################################################
+ loadd 0x0(r1,r0),(r1,r0)
+ loadd 0x0(r1,r0),(r1,r0)
+ loadd 0xf(r1,r0),(r1,r0)
+ loadd 0xf(r1,r0),(r1,r0)
+ loadd 0x1234(r1,r0),(r2,r1)
+ loadd 0xabcd(r3,r2),(r3,r2)
+ loadd 0xAfff(r4,r3),(r4,r3)
+ loadd 0xA1234(r6,r5),(r7,r6)
+ loadd -0xf(r1,r0),(r1,r0)
+ loadd -0xf(r1,r0),(r1,r0)
+ loadd -0x1234(r1,r0),(r2,r1)
+ loadd -0xabcd(r3,r2),(r3,r2)
+ loadd -0xAfff(r4,r3),(r5,r4)
+ loadd -0xA1234(r6,r5),(r5,r4)
+ ####################################
+ # loadd rbase(disp0/disp14) rel reg
+ ####################################
+ loadd [r12]0x0(r1,r0),(r1,r0)
+ loadd [r13]0x0(r1,r0),(r1,r0)
+ loadd [r12]0x1234(r1,r0),(r2,r1)
+ loadd [r13]0x1abcd(r1,r0),(r3,r2)
+ #################################
+ # loadd rpbase(disp20) rel reg
+ #################################
+ loadd [r12]0xA1234(r1,r0),(r3,r2)
+ loadd [r13]0xB1234(r1,r0),(r4,r3)
+ loadd [r13]0xfffff(r1,r0),(r5,r4)
diff --git a/gas/testsuite/gas/cr16/loadm_test.d b/gas/testsuite/gas/cr16/loadm_test.d new file mode 100644 index 000000000000..7d7ff3e99994 --- /dev/null +++ b/gas/testsuite/gas/cr16/loadm_test.d @@ -0,0 +1,25 @@ +#as: +#objdump: -dr +#name: loadm_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: a0 00 loadm \$0x1,r0 + 2: a1 00 loadm \$0x2,r0 + 4: a2 00 loadm \$0x3,r0 + 6: a3 00 loadm \$0x4,r0 + 8: a4 00 loadm \$0x5,r0 + a: a5 00 loadm \$0x6,r0 + c: a6 00 loadm \$0x7,r0 + e: a7 00 loadm \$0x8,r0 + 10: a8 00 loadmp \$0x1,r0 + 12: a9 00 loadmp \$0x2,r0 + 14: aa 00 loadmp \$0x3,r0 + 16: ab 00 loadmp \$0x4,r0 + 18: ac 00 loadmp \$0x5,r0 + 1a: ad 00 loadmp \$0x6,r0 + 1c: ae 00 loadmp \$0x7,r0 + 1e: af 00 loadmp \$0x8,r0 diff --git a/gas/testsuite/gas/cr16/loadm_test.s b/gas/testsuite/gas/cr16/loadm_test.s new file mode 100644 index 000000000000..3549e2049c2c --- /dev/null +++ b/gas/testsuite/gas/cr16/loadm_test.s @@ -0,0 +1,25 @@ + .text + .global main +main: + ############## + # loadm cnt + ############## + loadm $1 + loadm $2 + loadm $3 + loadm $4 + loadm $5 + loadm $6 + loadm $7 + loadm $8 + ############## + # loadmp cnt + ############## + loadmp $1 + loadmp $2 + loadmp $3 + loadmp $4 + loadmp $5 + loadmp $6 + loadmp $7 + loadmp $8 diff --git a/gas/testsuite/gas/cr16/loadw_test.d b/gas/testsuite/gas/cr16/loadw_test.d new file mode 100644 index 000000000000..cc4f311ae991 --- /dev/null +++ b/gas/testsuite/gas/cr16/loadw_test.d @@ -0,0 +1,79 @@ +#as: +#objdump: -dr +#name: loadw_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 89 00 00 loadw 0x0 <main>:m,r0 + 4: 10 89 ff 00 loadw 0xff <main\+0xff>:m,r1 + 8: 30 89 ff 0f loadw 0xfff <main\+0xfff>:m,r3 + c: 40 89 34 12 loadw 0x1234 <main\+0x1234>:m,r4 + 10: 50 89 34 12 loadw 0x1234 <main\+0x1234>:m,r5 + 14: 12 00 07 fa loadw 0x7a1234 <main\+0x7a1234>:l,r0 + 18: 34 12 + 1a: 12 00 1b fa loadw 0xba1234 <main\+0xba1234>:l,r1 + 1e: 34 12 + 20: 2f 89 ff ff loadw 0xfffff <main\+0xfffff>:m,r2 + 24: 00 8e 00 00 loadw \[r12\]0x0:m,r0 + 28: 00 8f 00 00 loadw \[r12\]0x0:m,r0 + 2c: 10 8e ff 00 loadw \[r12\]0xff:m,r1 + 30: 10 8f ff 00 loadw \[r12\]0xff:m,r1 + 34: 30 8e ff 0f loadw \[r12\]0xfff:m,r3 + 38: 30 8f ff 0f loadw \[r12\]0xfff:m,r3 + 3c: 40 8e 34 12 loadw \[r13\]0x1234:m,r4 + 40: 40 8f 34 12 loadw \[r13\]0x1234:m,r4 + 44: 50 8e 34 12 loadw \[r13\]0x1234:m,r5 + 48: 50 8f 34 12 loadw \[r13\]0x1234:m,r5 + 4c: 20 8e 67 45 loadw \[r12\]0x4567:m,r2 + 50: 2a 8f 34 12 loadw \[r12\]0xa1234:m,r2 + 54: 10 92 loadw 0x4:s\(r1,r0\),r1 + 56: 32 92 loadw 0x4:s\(r3,r2\),r3 + 58: 40 9f 34 12 loadw 0x1234:m\(r1,r0\),r4 + 5c: 52 9f 34 12 loadw 0x1234:m\(r3,r2\),r5 + 60: 12 00 60 da loadw 0xa1234:l\(r1,r0\),r6 + 64: 34 12 + 66: 18 00 10 df loadw 0xffffc:l\(r1,r0\),r1 + 6a: fc ff + 6c: 18 00 32 df loadw 0xffffc:l\(r3,r2\),r3 + 70: fc ff + 72: 18 00 40 df loadw 0xfedcc:l\(r1,r0\),r4 + 76: cc ed + 78: 18 00 52 df loadw 0xfedcc:l\(r3,r2\),r5 + 7c: cc ed + 7e: 18 00 60 d5 loadw 0x5edcc:l\(r1,r0\),r6 + 82: cc ed + 84: 00 90 loadw 0x0:s\(r1,r0\),r0 + 86: 10 90 loadw 0x0:s\(r1,r0\),r1 + 88: 00 9f 0f 00 loadw 0xf:m\(r1,r0\),r0 + 8c: 10 9f 0f 00 loadw 0xf:m\(r1,r0\),r1 + 90: 20 9f 34 12 loadw 0x1234:m\(r1,r0\),r2 + 94: 32 9f cd ab loadw 0xabcd:m\(r3,r2\),r3 + 98: 43 9f ff af loadw 0xafff:m\(r4,r3\),r4 + 9c: 12 00 55 da loadw 0xa1234:l\(r6,r5\),r5 + a0: 34 12 + a2: 18 00 00 df loadw 0xffff1:l\(r1,r0\),r0 + a6: f1 ff + a8: 18 00 10 df loadw 0xffff1:l\(r1,r0\),r1 + ac: f1 ff + ae: 18 00 20 df loadw 0xfedcc:l\(r1,r0\),r2 + b2: cc ed + b4: 18 00 32 df loadw 0xf5433:l\(r3,r2\),r3 + b8: 33 54 + ba: 18 00 43 df loadw 0xf5001:l\(r4,r3\),r4 + be: 01 50 + c0: 18 00 55 d5 loadw 0x5edcc:l\(r6,r5\),r5 + c4: cc ed + c6: 00 9e loadw \[r12\]0x0:s\(r1,r0\),r0 + c8: 18 9e loadw \[r13\]0x0:s\(r1,r0\),r1 + ca: f0 86 04 12 loadw \[r12\]0x234:m\(r1,r0\),r15 + ce: 12 00 38 e1 loadw \[r13\]0x1abcd:l\(r1,r0\),r3 + d2: cd ab + d4: 12 00 40 ea loadw \[r12\]0xa1234:l\(r1,r0\),r4 + d8: 34 12 + da: 12 00 58 eb loadw \[r13\]0xb1234:l\(r1,r0\),r5 + de: 34 12 + e0: 12 00 68 ef loadw \[r13\]0xfffff:l\(r1,r0\),r6 + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadw_test.s b/gas/testsuite/gas/cr16/loadw_test.s new file mode 100644 index 000000000000..bd9a2bb0ae90 --- /dev/null +++ b/gas/testsuite/gas/cr16/loadw_test.s @@ -0,0 +1,72 @@ + .text
+ .global main
+main:
+ ######################
+ # loadw abs20/24 reg
+ ######################
+ loadw 0x0,r0
+ loadw 0xff,r1
+ loadw 0xfff,r3
+ loadw 0x1234,r4
+ loadw 0x1234,r5
+ loadw 0x7A1234,r0
+ loadw 0xBA1234,r1
+ loadw 0xffffff,r2
+ ######################
+ # loadw abs20 rel reg
+ ######################
+ loadw [r12]0x0,r0
+ loadw [r13]0x0,r0
+ loadw [r12]0xff,r1
+ loadw [r13]0xff,r1
+ loadw [r12]0xfff,r3
+ loadw [r13]0xfff,r3
+ loadw [r12]0x1234,r4
+ loadw [r13]0x1234,r4
+ loadw [r12]0x1234,r5
+ loadw [r13]0x1234,r5
+ loadw [r12]0x4567,r2
+ loadw [r13]0xA1234,r2
+ ###################################
+ # loadw rbase(disp20/-disp20) reg
+ ###################################
+ loadw 0x4(r1,r0),r1
+ loadw 0x4(r3,r2),r3
+ loadw 0x1234(r1,r0),r4
+ loadw 0x1234(r3,r2),r5
+ loadw 0xA1234(r1,r0),r6
+ loadw -0x4(r1,r0),r1
+ loadw -0x4(r3,r2),r3
+ loadw -0x1234(r1,r0),r4
+ loadw -0x1234(r3,r2),r5
+ loadw -0xA1234(r1,r0),r6
+ #################################################
+ # loadw rpbase(disp4/disp16/disp20/-disp20) reg
+ #################################################
+ loadw 0x0(r1,r0),r0
+ loadw 0x0(r1,r0),r1
+ loadw 0xf(r1,r0),r0
+ loadw 0xf(r1,r0),r1
+ loadw 0x1234(r1,r0),r2
+ loadw 0xabcd(r3,r2),r3
+ loadw 0xAfff(r4,r3),r4
+ loadw 0xA1234(r6,r5),r5
+ loadw -0xf(r1,r0),r0
+ loadw -0xf(r1,r0),r1
+ loadw -0x1234(r1,r0),r2
+ loadw -0xabcd(r3,r2),r3
+ loadw -0xAfff(r4,r3),r4
+ loadw -0xA1234(r6,r5),r5
+ ####################################
+ # loadw rbase(disp0/disp14) rel reg
+ ####################################
+ loadw [r12]0x0(r1,r0),r0
+ loadw [r13]0x0(r1,r0),r1
+ loadw [r12]0x1234(r1,r0),r2
+ loadw [r13]0x1abcd(r1,r0),r3
+ #################################
+ # loadw rpbase(disp20) rel reg
+ #################################
+ loadw [r12]0xA1234(r1,r0),r4
+ loadw [r13]0xB1234(r1,r0),r5
+ loadw [r13]0xfffff(r1,r0),r6
diff --git a/gas/testsuite/gas/cr16/lpsp_test.d b/gas/testsuite/gas/cr16/lpsp_test.d new file mode 100644 index 000000000000..66ca8e25e39b --- /dev/null +++ b/gas/testsuite/gas/cr16/lpsp_test.d @@ -0,0 +1,57 @@ +#as: +#objdump: -dr +#name: lpsp_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 14 00 91 00 lpr r1,psr + 4: 14 00 82 00 lpr r2,cfg + 8: 14 00 a2 00 lpr r2,intbasel + c: 14 00 b3 00 lpr r3,intbaseh + 10: 14 00 c4 00 lpr r4,ispl + 14: 14 00 d5 00 lpr r5,isph + 18: 14 00 e6 00 lpr r6,uspl + 1c: 14 00 f7 00 lpr r7,usph + 20: 14 00 18 00 lpr r8,dsr + 24: 14 00 29 00 lpr r9,dcrl + 28: 14 00 3a 00 lpr r10,dcrh + 2c: 14 00 4b 00 lpr r11,car0l + 30: 14 00 50 00 lpr r0,car0h + 34: 14 00 61 00 lpr r1,car1l + 38: 14 00 73 00 lpr r3,car1h + 3c: 14 00 90 10 lprd \(r1,r0\),psr + 40: 14 00 81 10 lprd \(r2,r1\),cfg + 44: 14 00 a2 10 lprd \(r3,r2\),intbase + 48: 14 00 c3 10 lprd \(r4,r3\),isp + 4c: 14 00 e4 10 lprd \(r5,r4\),usp + 50: 14 00 15 10 lprd \(r6,r5\),dsr + 54: 14 00 26 10 lprd \(r7,r6\),dcr + 58: 14 00 47 10 lprd \(r8,r7\),car0 + 5c: 14 00 68 10 lprd \(r9,r8\),car1 + 60: 14 00 90 20 spr psr,r0 + 64: 14 00 81 20 spr cfg,r1 + 68: 14 00 a2 20 spr intbasel,r2 + 6c: 14 00 b3 20 spr intbaseh,r3 + 70: 14 00 c4 20 spr ispl,r4 + 74: 14 00 d5 20 spr isph,r5 + 78: 14 00 e6 20 spr uspl,r6 + 7c: 14 00 f7 20 spr usph,r7 + 80: 14 00 18 20 spr dsr,r8 + 84: 14 00 29 20 spr dcrl,r9 + 88: 14 00 3a 20 spr dcrh,r10 + 8c: 14 00 4b 20 spr car0l,r11 + 90: 14 00 50 20 spr car0h,r0 + 94: 14 00 61 20 spr car1l,r1 + 98: 14 00 72 20 spr car1h,r2 + 9c: 14 00 90 30 sprd psr,\(r1,r0\) + a0: 14 00 81 30 sprd cfg,\(r2,r1\) + a4: 14 00 a2 30 sprd intbase,\(r3,r2\) + a8: 14 00 c3 30 sprd isp,\(r4,r3\) + ac: 14 00 e4 30 sprd usp,\(r5,r4\) + b0: 14 00 15 30 sprd dsr,\(r6,r5\) + b4: 14 00 26 30 sprd dcr,\(r7,r6\) + b8: 14 00 47 30 sprd car0,\(r8,r7\) + bc: 14 00 68 30 sprd car1,\(r9,r8\) diff --git a/gas/testsuite/gas/cr16/lpsp_test.s b/gas/testsuite/gas/cr16/lpsp_test.s new file mode 100644 index 000000000000..8e9d45961bca --- /dev/null +++ b/gas/testsuite/gas/cr16/lpsp_test.s @@ -0,0 +1,63 @@ + .text
+ .global main
+main:
+ ################
+ # lpr reg, preg
+ ################
+ lpr r1,psr
+ lpr r2,cfg
+ lpr r2,intbasel
+ lpr r3,intbaseh
+ lpr r4,ispl
+ lpr r5,isph
+ lpr r6,uspl
+ lpr r7,usph
+ lpr r8,dsr
+ lpr r9,dcrl
+ lpr r10,dcrh
+ lpr r11,car0l
+ lpr r0,car0h
+ lpr r1,car1l
+ lpr r3,car1h
+ #################
+ # lprd regp, preg
+ #################
+ lprd (r1,r0),psr
+ lprd (r2,r1),cfg
+ lprd (r3,r2),intbase
+ lprd (r4,r3),isp
+ lprd (r5,r4),usp
+ lprd (r6,r5),dsr
+ lprd (r7,r6),dcr
+ lprd (r8,r7),car0
+ lprd (r9,r8),car1
+ #################
+ # spr preg, reg
+ #################
+ spr psr,r0
+ spr cfg,r1
+ spr intbasel,r2
+ spr intbaseh,r3
+ spr ispl,r4
+ spr isph,r5
+ spr uspl,r6
+ spr usph,r7
+ spr dsr,r8
+ spr dcrl,r9
+ spr dcrh,r10
+ spr car0l,r11
+ spr car0h,r0
+ spr car1l,r1
+ spr car1h,r2
+ #################
+ # sprd preg, regp
+ #################
+ sprd psr,(r1,r0)
+ sprd cfg,(r2,r1)
+ sprd intbase,(r3,r2)
+ sprd isp,(r4,r3)
+ sprd usp,(r5,r4)
+ sprd dsr,(r6,r5)
+ sprd dcr,(r7,r6)
+ sprd car0,(r8,r7)
+ sprd car1,(r9,r8)
diff --git a/gas/testsuite/gas/cr16/lsh_test.d b/gas/testsuite/gas/cr16/lsh_test.d new file mode 100644 index 000000000000..aba1cda98560 --- /dev/null +++ b/gas/testsuite/gas/cr16/lsh_test.d @@ -0,0 +1,47 @@ +#as: +#objdump: -dr +#name: lsh_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 71 40 ashub \$7:s,r1 + 2: 91 09 lshb \$-7:s,r1 + 4: 41 40 ashub \$4:s,r1 + 6: c1 09 lshb \$-4:s,r1 + 8: 81 09 lshb \$-8:s,r1 + a: 31 40 ashub \$3:s,r1 + c: d1 09 lshb \$-3:s,r1 + e: 21 44 lshb r2,r1 + 10: 34 44 lshb r3,r4 + 12: 56 44 lshb r5,r6 + 14: 8a 44 lshb r8,r10 + 16: 71 42 ashuw \$7:s,r1 + 18: 91 49 lshw \$-7:s,r1 + 1a: 41 42 ashuw \$4:s,r1 + 1c: c1 49 lshw \$-4:s,r1 + 1e: 81 42 ashuw \$8:s,r1 + 20: 81 49 lshw \$-8:s,r1 + 22: 31 42 ashuw \$3:s,r1 + 24: d1 49 lshw \$-3:s,r1 + 26: 21 46 lshw r2,r1 + 28: 34 46 lshw r3,r4 + 2a: 56 46 lshw r5,r6 + 2c: 8a 46 lshw r8,r10 + 2e: 72 4c ashud \$7:s,\(r3,r2\) + 30: 92 4b lshd \$-7:s,\(r3,r2\) + 32: 82 4c ashud \$8:s,\(r3,r2\) + 34: 82 4b lshd \$-8:s,\(r3,r2\) + 36: 42 4c ashud \$4:s,\(r3,r2\) + 38: c2 4b lshd \$-4:s,\(r3,r2\) + 3a: c2 4c ashud \$12:s,\(r3,r2\) + 3c: 42 4b lshd \$-12:s,\(r3,r2\) + 3e: 31 4c ashud \$3:s,\(r2,r1\) + 40: d1 4b lshd \$-3:s,\(r2,r1\) + 42: 41 47 lshd r4,\(r2,r1\) + 44: 51 47 lshd r5,\(r2,r1\) + 46: 61 47 lshd r6,\(r2,r1\) + 48: 81 47 lshd r8,\(r2,r1\) + 4a: 11 47 lshd r1,\(r2,r1\) diff --git a/gas/testsuite/gas/cr16/lsh_test.s b/gas/testsuite/gas/cr16/lsh_test.s new file mode 100644 index 000000000000..3236cbdda758 --- /dev/null +++ b/gas/testsuite/gas/cr16/lsh_test.s @@ -0,0 +1,59 @@ + .text + .global main +main: + ########################### + # LSHB cnt(right -), reg + ########################### + lshb $7,r1 + lshb $-7,r1 + lshb $4,r1 + lshb $-4,r1 + lshb $-8,r1 + lshb $3,r1 + lshb $-3,r1 + ########################### + # LSHB reg, reg + ########################### + lshb r2,r1 + lshb r3,r4 + lshb r5,r6 + lshb r8,r10 + ########################### + # LSHW cnt (right -), reg + ########################### + lshw $7,r1 + lshw $-7,r1 + lshw $4,r1 + lshw $-4,r1 + lshw $8,r1 + lshw $-8,r1 + lshw $3,r1 + lshw $-3,r1 + ########################## + # LSHW reg, reg + ########################## + lshw r2,r1 + lshw r3,r4 + lshw r5,r6 + lshw r8,r10 + ########################### + # LSHD cnt (right -), regp + ############################ + lshd $7, (r3,r2) + lshd $-7, (r3,r2) + lshd $8, (r3,r2) + lshd $-8, (r3,r2) + lshd $4, (r3,r2) + lshd $-4, (r3,r2) + lshd $12,(r3,r2) + lshd $-12,(r3,r2) + lshd $3,(r2,r1) + lshd $-3,(r2,r1) + ################# + # LSHD reg, regp + ################# + lshd r4,(r2,r1) + lshd r5,(r2,r1) + lshd r6,(r2,r1) + lshd r8,(r2,r1) + lshd r1,(r2,r1) diff --git a/gas/testsuite/gas/cr16/mov_test.d b/gas/testsuite/gas/cr16/mov_test.d new file mode 100644 index 000000000000..ce253e7fa7fc --- /dev/null +++ b/gas/testsuite/gas/cr16/mov_test.d @@ -0,0 +1,69 @@ +#as: +#objdump: -dr +#name: mov_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 58 movb \$0xf:s,r1 + 2: b2 58 ff 00 movb \$0xff:m,r2 + 6: b1 58 ff 0f movb \$0xfff:m,r1 + a: b1 58 14 00 movb \$0x14:m,r1 + e: a2 58 movb \$0xa:s,r2 + 10: b2 58 0b 00 movb \$0xb:m,r2 + 14: 12 59 movb r1,r2 + 16: 23 59 movb r2,r3 + 18: 34 59 movb r3,r4 + 1a: 56 59 movb r5,r6 + 1c: 67 59 movb r6,r7 + 1e: 78 59 movb r7,r8 + 20: f1 5a movw \$0xf:s,r1 + 22: b1 5a 0b 00 movw \$0xb:m,r1 + 26: b2 5a ff 00 movw \$0xff:m,r2 + 2a: b1 5a ff 0f movw \$0xfff:m,r1 + 2e: b1 5a 14 00 movw \$0x14:m,r1 + 32: a2 5a movw \$0xa:s,r2 + 34: b2 5a 0b 00 movw \$0xb:m,r2 + 38: 12 5b movw r1,r2 + 3a: 23 5b movw r2,r3 + 3c: 34 5b movw r3,r4 + 3e: 56 5b movw r5,r6 + 40: 67 5b movw r6,r7 + 42: 78 5b movw r7,r8 + 44: f1 54 movd \$0xf:s,\(r2,r1\) + 46: b1 54 0b 00 movd \$0xb:m,\(r2,r1\) + 4a: b1 54 ff 00 movd \$0xff:m,\(r2,r1\) + 4e: b1 54 ff 0f movd \$0xfff:m,\(r2,r1\) + 52: 10 05 ff ff movd \$0xffff:m,\(r2,r1\) + 56: 1f 05 ff ff movd \$0xfffff:m,\(r2,r1\) + 5a: 71 00 ff 0f movd \$0xfffffff:l,\(r2,r1\) + 5e: ff ff + 60: 91 54 movd \$-1:s,\(r2,r1\) + 62: 31 55 movd \(r4,r3\),\(r2,r1\) + 64: 31 55 movd \(r4,r3\),\(r2,r1\) + 66: af 54 movd \$0xa:s,\(sp\) + 68: ef 54 movd \$0xe:s,\(sp\) + 6a: bf 54 0b 00 movd \$0xb:m,\(sp\) + 6e: 8f 54 movd \$0x8:s,\(sp\) + 70: 12 5c movxb r1,r2 + 72: 34 5c movxb r3,r4 + 74: 56 5c movxb r5,r6 + 76: 78 5c movxb r7,r8 + 78: 9a 5c movxb r9,r10 + 7a: 12 5e movxw r1,\(r3,r2\) + 7c: 33 5e movxw r3,\(r4,r3\) + 7e: 55 5e movxw r5,\(r6,r5\) + 80: 77 5e movxw r7,\(r8,r7\) + 82: 98 5e movxw r9,\(r9,r8\) + 84: 12 5d movzb r1,r2 + 86: 34 5d movzb r3,r4 + 88: 56 5d movzb r5,r6 + 8a: 78 5d movzb r7,r8 + 8c: 9a 5d movzb r9,r10 + 8e: 12 5f movzw r1,\(r3,r2\) + 90: 33 5f movzw r3,\(r4,r3\) + 92: 55 5f movzw r5,\(r6,r5\) + 94: 77 5f movzw r7,\(r8,r7\) + 96: 98 5f movzw r9,\(r9,r8\) diff --git a/gas/testsuite/gas/cr16/mov_test.s b/gas/testsuite/gas/cr16/mov_test.s new file mode 100644 index 000000000000..20fdf4d5443b --- /dev/null +++ b/gas/testsuite/gas/cr16/mov_test.s @@ -0,0 +1,94 @@ + .text + .global main +main: + ########### + # MOVB imm4/imm16, reg + ########### + movb $0xf,r1 + movb $0xff,r2 + movb $0xfff,r1 + #movb $0xffff,r2 // CHECK WITH CRASM 4.1 + movb $20,r1 + movb $10,r2 + movb $11,r2 + ########### + # MOVB reg, reg + ########### + movb r1,r2 + movb r2,r3 + movb r3,r4 + movb r5,r6 + movb r6,r7 + movb r7,r8 + ########### + # MOVW imm4/imm16, reg + ########### + movw $0xf,r1 + movw $0xB,r1 + movw $0xff,r2 + movw $0xfff,r1 + #movw $0xffff,r2 // CHECK WITH CRASM 4.1 + movw $20,r1 + movw $10,r2 + movw $11,r2 + ########### + # MOVW reg, reg + ########### + movw r1,r2 + movw r2,r3 + movw r3,r4 + movw r5,r6 + movw r6,r7 + movw r7,r8 + ########### + # MOVD imm4/imm16/imm20/imm32, regp + ########### + movd $0xf,(r2,r1) + movd $0xB,(r2,r1) + movd $0xff,(r2,r1) + movd $0xfff,(r2,r1) + movd $0xffff,(r2,r1) + movd $0xfffff,(r2,r1) + movd $0xfffffff,(r2,r1) + movd $0xffffffff,(r2,r1) + ########### + # MOVD regp, regp + ########### + movd (r4,r3),(r2,r1) + movd (r4,r3),(r2,r1) + movd $10,(sp) + movd $14,(sp) + movd $11,(sp) + movd $8,(sp) + ########### + # MOVXB reg, reg + ########### + movxb r1,r2 + movxb r3,r4 + movxb r5,r6 + movxb r7,r8 + movxb r9,r10 + ########### + # MOVXW reg, regp + ########### + movxw r1,(r3,r2) + movxw r3,(r4,r3) + movxw r5,(r6,r5) + movxw r7,(r8,r7) + movxw r9,(r9,r8) + ########### + # MOVZB reg, reg + ########### + movzb r1,r2 + movzb r3,r4 + movzb r5,r6 + movzb r7,r8 + movzb r9,r10 + ########### + # MOVZW reg, regp + ########### + movzw r1,(r3,r2) + movzw r3,(r4,r3) + movzw r5,(r6,r5) + movzw r7,(r8,r7) + movzw r9,(r9,r8) diff --git a/gas/testsuite/gas/cr16/mul_test.d b/gas/testsuite/gas/cr16/mul_test.d new file mode 100644 index 000000000000..6e5755d33e12 --- /dev/null +++ b/gas/testsuite/gas/cr16/mul_test.d @@ -0,0 +1,47 @@ +#as: +#objdump: -dr +#name: mul_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 64 mulb \$0xf:s,r1 + 2: b2 64 ff 00 mulb \$0xff:m,r2 + 6: b1 64 ff 0f mulb \$0xfff:m,r1 + a: b1 64 14 00 mulb \$0x14:m,r1 + e: a2 64 mulb \$0xa:s,r2 + 10: 12 65 mulb r1,r2 + 12: 23 65 mulb r2,r3 + 14: 34 65 mulb r3,r4 + 16: 56 65 mulb r5,r6 + 18: 67 65 mulb r6,r7 + 1a: 78 65 mulb r7,r8 + 1c: f1 66 mulw \$0xf:s,r1 + 1e: b2 66 ff 00 mulw \$0xff:m,r2 + 22: b1 66 ff 0f mulw \$0xfff:m,r1 + 26: b1 66 14 00 mulw \$0x14:m,r1 + 2a: a2 66 mulw \$0xa:s,r2 + 2c: 12 67 mulw r1,r2 + 2e: 23 67 mulw r2,r3 + 30: 34 67 mulw r3,r4 + 32: 56 67 mulw r5,r6 + 34: 67 67 mulw r6,r7 + 36: 78 67 mulw r7,r8 + 38: 12 0b mulsb r1,r2 + 3a: 34 0b mulsb r3,r4 + 3c: 56 0b mulsb r5,r6 + 3e: 78 0b mulsb r7,r8 + 40: 9a 0b mulsb r9,r10 + 42: 12 62 mulsw r1,\(r3,r2\) + 44: 33 62 mulsw r3,\(r4,r3\) + 46: 55 62 mulsw r5,\(r6,r5\) + 48: 77 62 mulsw r7,\(r8,r7\) + 4a: 98 62 mulsw r9,\(r9,r8\) + 4c: 14 00 12 d2 macqw r1,r2,\(r3,r2\) + 50: 14 00 45 d4 macqw r4,r5,\(r5,r4\) + 54: 14 00 12 e2 macuw r1,r2,\(r3,r2\) + 58: 14 00 45 e7 macuw r4,r5,\(r8,r7\) + 5c: 14 00 12 f2 macsw r1,r2,\(r3,r2\) + 60: 14 00 45 f6 macsw r4,r5,\(r7,r6\) diff --git a/gas/testsuite/gas/cr16/mul_test.s b/gas/testsuite/gas/cr16/mul_test.s new file mode 100644 index 000000000000..c2b960c7f0fc --- /dev/null +++ b/gas/testsuite/gas/cr16/mul_test.s @@ -0,0 +1,64 @@ + .text + .global main +main: + ########### + # MULB imm4/imm16, reg + ########### + mulb $0xf,r1 + mulb $0xff,r2 + mulb $0xfff,r1 + #mulb $0xffff,r2 // CHCEK WITH CRASM 4.1 + mulb $20,r1 + mulb $10,r2 + ########### + # MULB reg, reg + ########### + mulb r1,r2 + mulb r2,r3 + mulb r3,r4 + mulb r5,r6 + mulb r6,r7 + mulb r7,r8 + ########### + # MULW imm4/imm16, reg + ########### + mulw $0xf,r1 + mulw $0xff,r2 + mulw $0xfff,r1 + #mulw $0xffff,r2 // CHCEK WITH CRASM 4.1 + mulw $20,r1 + mulw $10,r2 + ########### + # MULW reg, reg + ########### + mulw r1,r2 + mulw r2,r3 + mulw r3,r4 + mulw r5,r6 + mulw r6,r7 + mulw r7,r8 + ########### + # MULSB reg, reg + ########### + mulsb r1,r2 + mulsb r3,r4 + mulsb r5,r6 + mulsb r7,r8 + mulsb r9,r10 + ########### + # MULSW reg, regp + ########### + mulsw r1,(r3,r2) + mulsw r3,(r4,r3) + mulsw r5,(r6,r5) + mulsw r7,(r8,r7) + mulsw r9,(r9,r8) + ############################# + # MUC[q/u/s/]w reg, reg, regp + ############################# + macqw r1,r2,(r3,r2) + macqw r4,r5,(r5,r4) + macuw r1,r2,(r3,r2) + macuw r4,r5,(r8,r7) + macsw r1,r2,(r3,r2) + macsw r4,r5,(r7,r6) diff --git a/gas/testsuite/gas/cr16/or_test.d b/gas/testsuite/gas/cr16/or_test.d new file mode 100644 index 000000000000..73d95d0ca5d9 --- /dev/null +++ b/gas/testsuite/gas/cr16/or_test.d @@ -0,0 +1,49 @@ +#as: +#objdump: -dr +#name: or_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 24 orb \$0xf:s,r1 + 2: b2 24 ff 00 orb \$0xff:m,r2 + 6: b1 24 ff 0f orb \$0xfff:m,r1 + a: b2 24 ff ff orb \$0xffff:m,r2 + e: b1 24 14 00 orb \$0x14:m,r1 + 12: a2 24 orb \$0xa:s,r2 + 14: 12 25 orb r1,r2 + 16: 23 25 orb r2,r3 + 18: 34 25 orb r3,r4 + 1a: 56 25 orb r5,r6 + 1c: 67 25 orb r6,r7 + 1e: 78 25 orb r7,r8 + 20: f1 26 orw \$0xf:s,r1 + 22: b2 26 ff 00 orw \$0xff:m,r2 + 26: b1 26 ff 0f orw \$0xfff:m,r1 + 2a: b2 26 ff ff orw \$0xffff:m,r2 + 2e: b1 26 14 00 orw \$0x14:m,r1 + 32: a2 26 orw \$0xa:s,r2 + 34: 12 27 orw r1,r2 + 36: 23 27 orw r2,r3 + 38: 34 27 orw r3,r4 + 3a: 56 27 orw r5,r6 + 3c: 67 27 orw r6,r7 + 3e: 78 27 orw r7,r8 + 40: 51 00 00 00 ord \$0xf:l,\(r2,r1\) + 44: 0f 00 + 46: 51 00 00 00 ord \$0xff:l,\(r2,r1\) + 4a: ff 00 + 4c: 51 00 00 00 ord \$0xfff:l,\(r2,r1\) + 50: ff 0f + 52: 51 00 00 00 ord \$0xffff:l,\(r2,r1\) + 56: ff ff + 58: 51 00 0f 00 ord \$0xfffff:l,\(r2,r1\) + 5c: ff ff + 5e: 51 00 ff 0f ord \$0xfffffff:l,\(r2,r1\) + 62: ff ff + 64: 51 00 ff ff ord \$0xffffffff:l,\(r2,r1\) + 68: ff ff + 6a: 14 00 31 90 ord \(r4,r3\),\(r2,r1\) + 6e: 14 00 31 90 ord \(r4,r3\),\(r2,r1\) diff --git a/gas/testsuite/gas/cr16/or_test.s b/gas/testsuite/gas/cr16/or_test.s new file mode 100644 index 000000000000..df140c164865 --- /dev/null +++ b/gas/testsuite/gas/cr16/or_test.s @@ -0,0 +1,57 @@ + .text + .global main +main: + ########### + # ORB imm4/imm16, reg + ########### + orb $0xf,r1 + orb $0xff,r2 + orb $0xfff,r1 + orb $0xffff,r2 + orb $20,r1 + orb $10,r2 + ########### + # ORB reg, reg + ########### + orb r1,r2 + orb r2,r3 + orb r3,r4 + orb r5,r6 + orb r6,r7 + orb r7,r8 + ########### + # ORW imm4/imm16, reg + ########### + orw $0xf,r1 + orw $0xff,r2 + orw $0xfff,r1 + orw $0xffff,r2 + orw $20,r1 + orw $10,r2 + ########### + # ORW reg, reg + ########### + orw r1,r2 + orw r2,r3 + orw r3,r4 + orw r5,r6 + orw r6,r7 + orw r7,r8 + ########### + # ORD imm32, regp + ########### + ord $0xf,(r2,r1) + ord $0xff,(r2,r1) + ord $0xfff,(r2,r1) + ord $0xffff,(r2,r1) + ord $0xfffff,(r2,r1) + ord $0xfffffff,(r2,r1) + ord $0xffffffff,(r2,r1) + ########### + # ORD regp, regp + ########### + ord (r4,r3),(r2,r1) + ord (r4,r3),(r2,r1) + #ord $10,(sp) + #ord $14,(sp) + #ord $8,(sp) diff --git a/gas/testsuite/gas/cr16/pop_test.d b/gas/testsuite/gas/cr16/pop_test.d new file mode 100644 index 000000000000..1ed8c431b935 --- /dev/null +++ b/gas/testsuite/gas/cr16/pop_test.d @@ -0,0 +1,24 @@ +#as: +#objdump: -dr +#name: pop_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 87 02 pop \$0x1,r7,RA + 2: 96 02 pop \$0x2,r6,RA + 4: a5 02 pop \$0x3,r5,RA + 6: b4 02 pop \$0x4,r4,RA + 8: c3 02 pop \$0x5,r3,RA + a: d2 02 pop \$0x6,r2,RA + c: e1 02 pop \$0x7,r1,RA + e: 07 02 pop \$0x1,r7 + 10: 16 02 pop \$0x2,r6 + 12: 25 02 pop \$0x3,r5 + 14: 34 02 pop \$0x4,r4 + 16: 43 02 pop \$0x5,r3 + 18: 52 02 pop \$0x6,r2 + 1a: 61 02 pop \$0x7,r1 + 1c: 1e 02 pop RA diff --git a/gas/testsuite/gas/cr16/pop_test.s b/gas/testsuite/gas/cr16/pop_test.s new file mode 100644 index 000000000000..e88acff66112 --- /dev/null +++ b/gas/testsuite/gas/cr16/pop_test.s @@ -0,0 +1,27 @@ + .text + .global main +main: + #################### + # pop uimm3 regr RA + #################### + pop $1,r7,RA + pop $2,r6,RA + pop $3,r5,RA + pop $4,r4,RA + pop $5,r3,RA + pop $6,r2,RA + pop $7,r1,RA + ################# + # pop uimm3 regr + ################# + pop $1,r7 + pop $2,r6 + pop $3,r5 + pop $4,r4 + pop $5,r3 + pop $6,r2 + pop $7,r1 + ########## + # pop RA + ########## + pop RA diff --git a/gas/testsuite/gas/cr16/popret_test.d b/gas/testsuite/gas/cr16/popret_test.d new file mode 100644 index 000000000000..cbc8f85a874b --- /dev/null +++ b/gas/testsuite/gas/cr16/popret_test.d @@ -0,0 +1,24 @@ +#as: +#objdump: -dr +#name: popret_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 87 03 popret \$0x1,r7,RA + 2: 96 03 popret \$0x2,r6,RA + 4: a5 03 popret \$0x3,r5,RA + 6: b4 03 popret \$0x4,r4,RA + 8: c3 03 popret \$0x5,r3,RA + a: d2 03 popret \$0x6,r2,RA + c: e1 03 popret \$0x7,r1,RA + e: 07 03 popret \$0x1,r7 + 10: 16 03 popret \$0x2,r6 + 12: 25 03 popret \$0x3,r5 + 14: 34 03 popret \$0x4,r4 + 16: 43 03 popret \$0x5,r3 + 18: 52 03 popret \$0x6,r2 + 1a: 61 03 popret \$0x7,r1 + 1c: 1e 03 popret RA diff --git a/gas/testsuite/gas/cr16/popret_test.s b/gas/testsuite/gas/cr16/popret_test.s new file mode 100644 index 000000000000..f88bf2844d23 --- /dev/null +++ b/gas/testsuite/gas/cr16/popret_test.s @@ -0,0 +1,27 @@ + .text + .global main +main: + #################### + # popret uimm3 regr RA + #################### + popret $1,r7,RA + popret $2,r6,RA + popret $3,r5,RA + popret $4,r4,RA + popret $5,r3,RA + popret $6,r2,RA + popret $7,r1,RA + ################# + # popret uimm3 regr + ################# + popret $1,r7 + popret $2,r6 + popret $3,r5 + popret $4,r4 + popret $5,r3 + popret $6,r2 + popret $7,r1 + ########## + # popret RA + ########## + popret RA diff --git a/gas/testsuite/gas/cr16/push_test.d b/gas/testsuite/gas/cr16/push_test.d new file mode 100644 index 000000000000..0a8afab80a5b --- /dev/null +++ b/gas/testsuite/gas/cr16/push_test.d @@ -0,0 +1,26 @@ +#as: +#objdump: -dr +#name: push_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 87 01 push \$0x1,r7,RA + 2: 96 01 push \$0x2,r6,RA + 4: a5 01 push \$0x3,r5,RA + 6: b4 01 push \$0x4,r4,RA + 8: c3 01 push \$0x5,r3,RA + a: d2 01 push \$0x6,r2,RA + c: e1 01 push \$0x7,r1,RA + e: 07 01 push \$0x1,r7 + 10: 16 01 push \$0x2,r6 + 12: 25 01 push \$0x3,r5 + 14: 34 01 push \$0x4,r4 + 16: 43 01 push \$0x5,r3 + 18: 52 01 push \$0x6,r2 + 1a: 61 01 push \$0x7,r1 + 1c: 5c 01 push \$0x6,r12 + 1e: 1e 01 push RA + 20: 1e 01 push RA diff --git a/gas/testsuite/gas/cr16/push_test.s b/gas/testsuite/gas/cr16/push_test.s new file mode 100644 index 000000000000..804419cc548c --- /dev/null +++ b/gas/testsuite/gas/cr16/push_test.s @@ -0,0 +1,40 @@ + .text + .global main +main: + #################### + # push uimm3 regr RA + #################### + push $1,r7,RA + push $2,r6,RA + push $3,r5,RA + push $4,r4,RA + push $5,r3,RA + push $6,r2,RA + push $7,r1,RA +#push $6,r12,RA + #push $7,r13,RA + #push $7,r12,RA + #push $8,r12,RA + ################# + # push uimm3 regr + ################# + push $1,r7 + push $2,r6 + push $3,r5 + push $4,r4 + push $5,r3 + push $6,r2 + push $7,r1 + push $6,r12 + #push $7,r13 + #push $7,r12 + #push $8,r12 + #push $6,r13 + ########## + # push RA + ########## + #push r1 + #push r4 + #push r9 + push ra + push RA diff --git a/gas/testsuite/gas/cr16/sbitb_test.d b/gas/testsuite/gas/cr16/sbitb_test.d new file mode 100644 index 000000000000..e04dddeef342 --- /dev/null +++ b/gas/testsuite/gas/cr16/sbitb_test.d @@ -0,0 +1,82 @@ +#as: +#objdump: -dr +#name: sbitb_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: c0 73 cd 0b sbitb \$0x4,0xbcd <main\+0xbcd>:m + 4: da 73 cd ab sbitb \$0x5,0xaabcd <main\+0xaabcd>:m + 8: 10 00 3f ba sbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: 50 70 14 00 sbitb \$0x5,\[r12\]0x14:m + 12: c0 70 fc ab sbitb \$0x4,\[r13\]0xabfc:m + 16: 30 70 34 12 sbitb \$0x3,\[r12\]0x1234:m + 1a: b0 70 34 12 sbitb \$0x3,\[r13\]0x1234:m + 1e: 30 70 34 00 sbitb \$0x3,\[r12\]0x34:m + 22: b0 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\) + 26: b1 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\) + 2a: b6 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\) + 2e: b2 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\) + 32: b7 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\) + 36: b3 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\) + 3a: b4 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\) + 3e: b5 72 3a 4a sbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\) + 42: b8 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\) + 46: b9 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\) + 4a: be 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\) + 4e: ba 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\) + 52: bf 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\) + 56: bb 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\) + 5a: bc 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\) + 5e: bd 72 3a 4a sbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\) + 62: be 72 5a 4b sbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\) + 66: b7 72 1a 41 sbitb \$0x1,\[r12\]0x17a:m\(r6,r5\) + 6a: bf 72 14 01 sbitb \$0x1,\[r13\]0x134:m\(r6,r5\) + 6e: 10 00 36 aa sbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\) + 72: de bc + 74: 10 00 5e a0 sbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\) + 78: cd ab + 7a: 10 00 37 a0 sbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\) + 7e: cd ab + 80: 10 00 3f a0 sbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\) + 84: de bc + 86: 10 00 52 80 sbitb \$0x5,0x0:l\(r2\) + 8a: 00 00 + 8c: 3c 73 34 00 sbitb \$0x3,0x34:m\(r12\) + 90: 3d 73 ab 00 sbitb \$0x3,0xab:m\(r13\) + 94: 10 00 51 80 sbitb \$0x5,0xad:l\(r1\) + 98: ad 00 + 9a: 10 00 52 80 sbitb \$0x5,0xcd:l\(r2\) + 9e: cd 00 + a0: 10 00 50 80 sbitb \$0x5,0xfff:l\(r0\) + a4: ff 0f + a6: 10 00 34 80 sbitb \$0x3,0xbcd:l\(r4\) + aa: cd 0b + ac: 3c 73 ff 0f sbitb \$0x3,0xfff:m\(r12\) + b0: 3d 73 ff 0f sbitb \$0x3,0xfff:m\(r13\) + b4: 3d 73 ff ff sbitb \$0x3,0xffff:m\(r13\) + b8: 3c 73 43 23 sbitb \$0x3,0x2343:m\(r12\) + bc: 10 00 32 81 sbitb \$0x3,0x2345:l\(r2\) + c0: 45 23 + c2: 10 00 38 84 sbitb \$0x3,0xabcd:l\(r8\) + c6: cd ab + c8: 10 00 3d 9f sbitb \$0x3,0xfabcd:l\(r13\) + cc: cd ab + ce: 10 00 38 8f sbitb \$0x3,0xabcd:l\(r8\) + d2: cd ab + d4: 10 00 39 8f sbitb \$0x3,0xabcd:l\(r9\) + d8: cd ab + da: 10 00 39 84 sbitb \$0x3,0xabcd:l\(r9\) + de: cd ab + e0: 31 72 sbitb \$0x3,0x0:s\(r2,r1\) + e2: 51 73 01 00 sbitb \$0x5,0x1:m\(r2,r1\) + e6: 41 73 34 12 sbitb \$0x4,0x1234:m\(r2,r1\) + ea: 31 73 34 12 sbitb \$0x3,0x1234:m\(r2,r1\) + ee: 10 00 31 91 sbitb \$0x3,0x12345:l\(r2,r1\) + f2: 45 23 + f4: 31 73 23 01 sbitb \$0x3,0x123:m\(r2,r1\) + f8: 10 00 31 91 sbitb \$0x3,0x12345:l\(r2,r1\) + fc: 45 23 diff --git a/gas/testsuite/gas/cr16/sbitb_test.s b/gas/testsuite/gas/cr16/sbitb_test.s new file mode 100644 index 000000000000..937e6c622111 --- /dev/null +++ b/gas/testsuite/gas/cr16/sbitb_test.s @@ -0,0 +1,62 @@ + .text + .global main +main: + sbitb $4,0xbcd + sbitb $5,0xaabcd + sbitb $3,0xfaabcd + + sbitb $5,[r12]0x14 + sbitb $4,[r13]0xabfc + sbitb $3,[r12]0x1234 + sbitb $3,[r13]0x1234 + sbitb $3,[r12]0x34 + + sbitb $3,[r12]0xa7a(r1,r0) + sbitb $3,[r12]0xa7a(r3,r2) + sbitb $3,[r12]0xa7a(r4,r3) + sbitb $3,[r12]0xa7a(r5,r4) + sbitb $3,[r12]0xa7a(r6,r5) + sbitb $3,[r12]0xa7a(r7,r6) + sbitb $3,[r12]0xa7a(r9,r8) + sbitb $3,[r12]0xa7a(r11,r10) + sbitb $3,[r13]0xa7a(r1,r0) + sbitb $3,[r13]0xa7a(r3,r2) + sbitb $3,[r13]0xa7a(r4,r3) + sbitb $3,[r13]0xa7a(r5,r4) + sbitb $3,[r13]0xa7a(r6,r5) + sbitb $3,[r13]0xa7a(r7,r6) + sbitb $3,[r13]0xa7a(r9,r8) + sbitb $3,[r13]0xa7a(r11,r10) + sbitb $5,[r13]0xb7a(r4,r3) + sbitb $1,[r12]0x17a(r6,r5) + sbitb $1,[r13]0x134(r6,r5) + sbitb $3,[r12]0xabcde(r4,r3) + sbitb $5,[r13]0xabcd(r4,r3) + sbitb $3,[r12]0xabcd(r6,r5) + sbitb $3,[r13]0xbcde(r6,r5) + + sbitb $5,0x0(r2) + sbitb $3,0x34(r12) + sbitb $3,0xab(r13) + sbitb $5,0xad(r1) + sbitb $5,0xcd(r2) + sbitb $5,0xfff(r0) + sbitb $3,0xbcd(r4) + sbitb $3,0xfff(r12) + sbitb $3,0xfff(r13) + sbitb $3,0xffff(r13) + sbitb $3,0x2343(r12) + sbitb $3,0x12345(r2) + sbitb $3,0x4abcd(r8) + sbitb $3,0xfabcd(r13) + sbitb $3,0xfabcd(r8) + sbitb $3,0xfabcd(r9) + sbitb $3,0x4abcd(r9) + + sbitb $3,0x0(r2,r1) + sbitb $5,0x1(r2,r1) + sbitb $4,0x1234(r2,r1) + sbitb $3,0x1234(r2,r1) + sbitb $3,0x12345(r2,r1) + sbitb $3,0x123(r2,r1) + sbitb $3,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/sbitw_test.d b/gas/testsuite/gas/cr16/sbitw_test.d new file mode 100644 index 000000000000..afc75f4d5d94 --- /dev/null +++ b/gas/testsuite/gas/cr16/sbitw_test.d @@ -0,0 +1,155 @@ +#as: +#objdump: -dr +#name: sbitw_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 40 77 cd 0b sbitw \$0x4:s,0xbcd <main\+0xbcd>:m + 4: 5a 77 cd ab sbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m + 8: 11 00 3f ba sbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: a0 77 cd 0b sbitw \$0xa:s,0xbcd <main\+0xbcd>:m + 12: fa 77 cd ab sbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m + 16: 11 00 ef ba sbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l + 1a: cd ab + 1c: 50 74 14 00 sbitw \$0x5:s,\[r13\]0x14:m + 20: 40 75 fc ab sbitw \$0x4:s,\[r13\]0xabfc:m + 24: 30 74 34 12 sbitw \$0x3:s,\[r12\]0x1234:m + 28: 30 75 34 12 sbitw \$0x3:s,\[r12\]0x1234:m + 2c: 30 74 34 00 sbitw \$0x3:s,\[r12\]0x34:m + 30: f0 74 14 00 sbitw \$0xf:s,\[r13\]0x14:m + 34: e0 75 fc ab sbitw \$0xe:s,\[r13\]0xabfc:m + 38: d0 74 34 12 sbitw \$0xd:s,\[r13\]0x1234:m + 3c: d0 75 34 12 sbitw \$0xd:s,\[r13\]0x1234:m + 40: b0 74 34 00 sbitw \$0xb:s,\[r12\]0x34:m + 44: f0 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\) + 48: f1 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\) + 4c: f6 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\) + 50: f2 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\) + 54: f7 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\) + 58: f3 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\) + 5c: f4 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\) + 60: f5 72 3a 4a sbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\) + 64: f8 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\) + 68: f9 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\) + 6c: fe 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\) + 70: fa 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\) + 74: ff 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\) + 78: fb 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\) + 7c: fc 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\) + 80: fd 72 3a 4a sbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\) + 84: fe 72 5a 4b sbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\) + 88: f7 72 1a 41 sbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\) + 8c: ff 72 14 01 sbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\) + 90: 11 00 36 aa sbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\) + 94: de bc + 96: 11 00 5e a0 sbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\) + 9a: cd ab + 9c: 11 00 37 a0 sbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\) + a0: cd ab + a2: 11 00 3f a0 sbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\) + a6: de bc + a8: f0 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\) + ac: f1 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\) + b0: f6 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\) + b4: f2 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\) + b8: f7 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\) + bc: f3 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\) + c0: f4 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\) + c4: f5 72 da 4a sbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\) + c8: f8 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\) + cc: f9 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\) + d0: fe 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\) + d4: fa 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\) + d8: ff 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\) + dc: fb 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\) + e0: fc 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\) + e4: fd 72 da 4a sbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\) + e8: fe 72 fa 4b sbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\) + ec: f7 72 ba 41 sbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\) + f0: ff 72 b4 01 sbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\) + f4: 11 00 d6 aa sbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\) + f8: de bc + fa: 11 00 fe a0 sbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\) + fe: cd ab + 100: 11 00 d7 a0 sbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\) + 104: cd ab + 106: 11 00 df a0 sbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\) + 10a: de bc + 10c: 11 00 52 80 sbitw \$0x5:s,0x0:l\(r2\) + 110: 00 00 + 112: 3c 71 34 00 sbitw \$0x3:s,0x34:m\(r12\) + 116: 3d 71 ab 00 sbitw \$0x3:s,0xab:m\(r13\) + 11a: 11 00 51 80 sbitw \$0x5:s,0xad:l\(r1\) + 11e: ad 00 + 120: 11 00 52 80 sbitw \$0x5:s,0xcd:l\(r2\) + 124: cd 00 + 126: 11 00 50 80 sbitw \$0x5:s,0xfff:l\(r0\) + 12a: ff 0f + 12c: 11 00 34 80 sbitw \$0x3:s,0xbcd:l\(r4\) + 130: cd 0b + 132: 3c 71 ff 0f sbitw \$0x3:s,0xfff:m\(r12\) + 136: 3d 71 ff 0f sbitw \$0x3:s,0xfff:m\(r13\) + 13a: 3d 71 ff ff sbitw \$0x3:s,0xffff:m\(r13\) + 13e: 3c 71 43 23 sbitw \$0x3:s,0x2343:m\(r12\) + 142: 11 00 32 81 sbitw \$0x3:s,0x2345:l\(r2\) + 146: 45 23 + 148: 11 00 38 84 sbitw \$0x3:s,0xabcd:l\(r8\) + 14c: cd ab + 14e: 11 00 3d 9f sbitw \$0x3:s,0xfabcd:l\(r13\) + 152: cd ab + 154: 11 00 38 8f sbitw \$0x3:s,0xabcd:l\(r8\) + 158: cd ab + 15a: 11 00 39 8f sbitw \$0x3:s,0xabcd:l\(r9\) + 15e: cd ab + 160: 11 00 39 84 sbitw \$0x3:s,0xabcd:l\(r9\) + 164: cd ab + 166: 11 00 f2 80 sbitw \$0xf:s,0x0:l\(r2\) + 16a: 00 00 + 16c: dc 71 34 00 sbitw \$0xd:s,0x34:m\(r12\) + 170: dd 71 ab 00 sbitw \$0xd:s,0xab:m\(r13\) + 174: 11 00 f1 80 sbitw \$0xf:s,0xad:l\(r1\) + 178: ad 00 + 17a: 11 00 f2 80 sbitw \$0xf:s,0xcd:l\(r2\) + 17e: cd 00 + 180: 11 00 f0 80 sbitw \$0xf:s,0xfff:l\(r0\) + 184: ff 0f + 186: 11 00 d4 80 sbitw \$0xd:s,0xbcd:l\(r4\) + 18a: cd 0b + 18c: dc 71 ff 0f sbitw \$0xd:s,0xfff:m\(r12\) + 190: dd 71 ff 0f sbitw \$0xd:s,0xfff:m\(r13\) + 194: dd 71 ff ff sbitw \$0xd:s,0xffff:m\(r13\) + 198: dc 71 43 23 sbitw \$0xd:s,0x2343:m\(r12\) + 19c: 11 00 d2 81 sbitw \$0xd:s,0x2345:l\(r2\) + 1a0: 45 23 + 1a2: 11 00 d8 84 sbitw \$0xd:s,0xabcd:l\(r8\) + 1a6: cd ab + 1a8: 11 00 dd 9f sbitw \$0xd:s,0xfabcd:l\(r13\) + 1ac: cd ab + 1ae: 11 00 d8 8f sbitw \$0xd:s,0xabcd:l\(r8\) + 1b2: cd ab + 1b4: 11 00 d9 8f sbitw \$0xd:s,0xabcd:l\(r9\) + 1b8: cd ab + 1ba: 11 00 d9 84 sbitw \$0xd:s,0xabcd:l\(r9\) + 1be: cd ab + 1c0: 31 76 sbitw \$0x3:s,0x0:s\(r2,r1\) + 1c2: 51 71 01 00 sbitw \$0x5:s,0x1:m\(r2,r1\) + 1c6: 41 71 34 12 sbitw \$0x4:s,0x1234:m\(r2,r1\) + 1ca: 31 71 34 12 sbitw \$0x3:s,0x1234:m\(r2,r1\) + 1ce: 11 00 31 91 sbitw \$0x3:s,0x12345:l\(r2,r1\) + 1d2: 45 23 + 1d4: 31 71 23 01 sbitw \$0x3:s,0x123:m\(r2,r1\) + 1d8: 11 00 31 91 sbitw \$0x3:s,0x12345:l\(r2,r1\) + 1dc: 45 23 + 1de: d1 76 sbitw \$0xd:s,0x0:s\(r2,r1\) + 1e0: f1 71 01 00 sbitw \$0xf:s,0x1:m\(r2,r1\) + 1e4: e1 71 34 12 sbitw \$0xe:s,0x1234:m\(r2,r1\) + 1e8: d1 71 34 12 sbitw \$0xd:s,0x1234:m\(r2,r1\) + 1ec: 11 00 d1 91 sbitw \$0xd:s,0x12345:l\(r2,r1\) + 1f0: 45 23 + 1f2: d1 71 23 01 sbitw \$0xd:s,0x123:m\(r2,r1\) + 1f6: 11 00 d1 91 sbitw \$0xd:s,0x12345:l\(r2,r1\) + 1fa: 45 23 diff --git a/gas/testsuite/gas/cr16/sbitw_test.s b/gas/testsuite/gas/cr16/sbitw_test.s new file mode 100644 index 000000000000..334d033a44fa --- /dev/null +++ b/gas/testsuite/gas/cr16/sbitw_test.s @@ -0,0 +1,117 @@ + .text + .global main +main: + sbitw $4,0xbcd + sbitw $5,0xaabcd + sbitw $3,0xfaabcd + sbitw $10,0xbcd + sbitw $15,0xaabcd + sbitw $14,0xfaabcd + + sbitw $5,[r12]0x14 + sbitw $4,[r13]0xabfc + sbitw $3,[r12]0x1234 + sbitw $3,[r13]0x1234 + sbitw $3,[r12]0x34 + sbitw $15,[r12]0x14 + sbitw $14,[r13]0xabfc + sbitw $13,[r12]0x1234 + sbitw $13,[r13]0x1234 + sbitw $11,[r12]0x34 + + sbitw $3,[r12]0xa7a(r1,r0) + sbitw $3,[r12]0xa7a(r3,r2) + sbitw $3,[r12]0xa7a(r4,r3) + sbitw $3,[r12]0xa7a(r5,r4) + sbitw $3,[r12]0xa7a(r6,r5) + sbitw $3,[r12]0xa7a(r7,r6) + sbitw $3,[r12]0xa7a(r9,r8) + sbitw $3,[r12]0xa7a(r11,r10) + sbitw $3,[r13]0xa7a(r1,r0) + sbitw $3,[r13]0xa7a(r3,r2) + sbitw $3,[r13]0xa7a(r4,r3) + sbitw $3,[r13]0xa7a(r5,r4) + sbitw $3,[r13]0xa7a(r6,r5) + sbitw $3,[r13]0xa7a(r7,r6) + sbitw $3,[r13]0xa7a(r9,r8) + sbitw $3,[r13]0xa7a(r11,r10) + sbitw $5,[r13]0xb7a(r4,r3) + sbitw $1,[r12]0x17a(r6,r5) + sbitw $1,[r13]0x134(r6,r5) + sbitw $3,[r12]0xabcde(r4,r3) + sbitw $5,[r13]0xabcd(r4,r3) + sbitw $3,[r12]0xabcd(r6,r5) + sbitw $3,[r13]0xbcde(r6,r5) + sbitw $13,[r12]0xa7a(r1,r0) + sbitw $13,[r12]0xa7a(r3,r2) + sbitw $13,[r12]0xa7a(r4,r3) + sbitw $13,[r12]0xa7a(r5,r4) + sbitw $13,[r12]0xa7a(r6,r5) + sbitw $13,[r12]0xa7a(r7,r6) + sbitw $13,[r12]0xa7a(r9,r8) + sbitw $13,[r12]0xa7a(r11,r10) + sbitw $13,[r13]0xa7a(r1,r0) + sbitw $13,[r13]0xa7a(r3,r2) + sbitw $13,[r13]0xa7a(r4,r3) + sbitw $13,[r13]0xa7a(r5,r4) + sbitw $13,[r13]0xa7a(r6,r5) + sbitw $13,[r13]0xa7a(r7,r6) + sbitw $13,[r13]0xa7a(r9,r8) + sbitw $13,[r13]0xa7a(r11,r10) + sbitw $15,[r13]0xb7a(r4,r3) + sbitw $11,[r12]0x17a(r6,r5) + sbitw $11,[r13]0x134(r6,r5) + sbitw $13,[r12]0xabcde(r4,r3) + sbitw $15,[r13]0xabcd(r4,r3) + sbitw $13,[r12]0xabcd(r6,r5) + sbitw $13,[r13]0xbcde(r6,r5) + + sbitw $5,0x0(r2) + sbitw $3,0x34(r12) + sbitw $3,0xab(r13) + sbitw $5,0xad(r1) + sbitw $5,0xcd(r2) + sbitw $5,0xfff(r0) + sbitw $3,0xbcd(r4) + sbitw $3,0xfff(r12) + sbitw $3,0xfff(r13) + sbitw $3,0xffff(r13) + sbitw $3,0x2343(r12) + sbitw $3,0x12345(r2) + sbitw $3,0x4abcd(r8) + sbitw $3,0xfabcd(r13) + sbitw $3,0xfabcd(r8) + sbitw $3,0xfabcd(r9) + sbitw $3,0x4abcd(r9) + sbitw $15,0x0(r2) + sbitw $13,0x34(r12) + sbitw $13,0xab(r13) + sbitw $15,0xad(r1) + sbitw $15,0xcd(r2) + sbitw $15,0xfff(r0) + sbitw $13,0xbcd(r4) + sbitw $13,0xfff(r12) + sbitw $13,0xfff(r13) + sbitw $13,0xffff(r13) + sbitw $13,0x2343(r12) + sbitw $13,0x12345(r2) + sbitw $13,0x4abcd(r8) + sbitw $13,0xfabcd(r13) + sbitw $13,0xfabcd(r8) + sbitw $13,0xfabcd(r9) + sbitw $13,0x4abcd(r9) + + sbitw $3,0x0(r2,r1) + sbitw $5,0x1(r2,r1) + sbitw $4,0x1234(r2,r1) + sbitw $3,0x1234(r2,r1) + sbitw $3,0x12345(r2,r1) + sbitw $3,0x123(r2,r1) + sbitw $3,0x12345(r2,r1) + sbitw $13,0x0(r2,r1) + sbitw $15,0x1(r2,r1) + sbitw $14,0x1234(r2,r1) + sbitw $13,0x1234(r2,r1) + sbitw $13,0x12345(r2,r1) + sbitw $13,0x123(r2,r1) + sbitw $13,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/scc_test.d b/gas/testsuite/gas/cr16/scc_test.d new file mode 100644 index 000000000000..308e75518c8c --- /dev/null +++ b/gas/testsuite/gas/cr16/scc_test.d @@ -0,0 +1,22 @@ +#as: +#objdump: -dr +#name: scc_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 02 08 seq r2 + 2: 13 08 sne r3 + 4: 23 08 scs r3 + 6: 34 08 scc r4 + 8: 45 08 shi r5 + a: 56 08 sls r6 + c: 67 08 sgt r7 + e: 88 08 sfs r8 + 10: 99 08 sfc r9 + 12: aa 08 slo r10 + 14: b1 08 shs r1 + 16: cb 08 slt r11 + 18: d0 08 sge r0 diff --git a/gas/testsuite/gas/cr16/scc_test.s b/gas/testsuite/gas/cr16/scc_test.s new file mode 100644 index 000000000000..9b9d01c3059f --- /dev/null +++ b/gas/testsuite/gas/cr16/scc_test.s @@ -0,0 +1,19 @@ + .text + .global main +main: + ########## + # SCond reg + ########## + seq r2 + sne r3 + scs r3 + scc r4 + shi r5 + sls r6 + sgt r7 + sfs r8 + sfc r9 + slo r10 + shs r1 + slt r11 + sge r0 diff --git a/gas/testsuite/gas/cr16/storb_test.d b/gas/testsuite/gas/cr16/storb_test.d new file mode 100644 index 000000000000..dc2a9c260f09 --- /dev/null +++ b/gas/testsuite/gas/cr16/storb_test.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: storb_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 c8 00 00 storb r0,0x0 <main>:m + 4: 10 c8 ff 00 storb r1,0xff <main\+0xff>:m + 8: 30 c8 ff 0f storb r3,0xfff <main\+0xfff>:m + c: 40 c8 34 12 storb r4,0x1234 <main\+0x1234>:m + 10: 50 c8 34 12 storb r5,0x1234 <main\+0x1234>:m + 14: 13 00 07 7a storb r0,0x7a1234 <main\+0x7a1234>:l + 18: 34 12 + 1a: 13 00 1b 7a storb r1,0xba1234 <main\+0xba1234>:l + 1e: 34 12 + 20: 13 00 2f 7f storb r2,0xffffff <main\+0xffffff>:l + 24: ff ff + 26: 00 ca 00 00 storb r0,\[r12\]0x0:m + 2a: 00 cb 00 00 storb r0,\[r12\]0x0:m + 2e: 10 ca ff 00 storb r1,\[r12\]0xff:m + 32: 10 cb ff 00 storb r1,\[r12\]0xff:m + 36: 30 ca ff 0f storb r3,\[r12\]0xfff:m + 3a: 30 cb ff 0f storb r3,\[r12\]0xfff:m + 3e: 40 ca 34 12 storb r4,\[r13\]0x1234:m + 42: 40 cb 34 12 storb r4,\[r13\]0x1234:m + 46: 50 ca 34 12 storb r5,\[r13\]0x1234:m + 4a: 50 cb 34 12 storb r5,\[r13\]0x1234:m + 4e: 20 ca 67 45 storb r2,\[r12\]0x4567:m + 52: 2a cb 34 12 storb r2,\[r12\]0xa1234:m + 56: 10 f4 storb r1,0x4:s\(r1,r0\) + 58: 32 f4 storb r3,0x4:s\(r3,r2\) + 5a: 40 ff 34 12 storb r4,0x1234:m\(r1,r0\) + 5e: 52 ff 34 12 storb r5,0x1234:m\(r3,r2\) + 62: 13 00 60 5a storb r6,0xa1234:l\(r1,r0\) + 66: 34 12 + 68: 19 00 10 5f storb r1,0xffffc:l\(r1,r0\) + 6c: fc ff + 6e: 19 00 32 5f storb r3,0xffffc:l\(r3,r2\) + 72: fc ff + 74: 19 00 40 5f storb r4,0xfedcc:l\(r1,r0\) + 78: cc ed + 7a: 19 00 52 5f storb r5,0xfedcc:l\(r3,r2\) + 7e: cc ed + 80: 19 00 60 55 storb r6,0x5edcc:l\(r1,r0\) + 84: cc ed + 86: 00 f0 storb r0,0x0:s\(r1,r0\) + 88: 00 f0 storb r0,0x0:s\(r1,r0\) + 8a: 00 ff 0f 00 storb r0,0xf:m\(r1,r0\) + 8e: 10 ff 0f 00 storb r1,0xf:m\(r1,r0\) + 92: 20 ff 34 12 storb r2,0x1234:m\(r1,r0\) + 96: 32 ff cd ab storb r3,0xabcd:m\(r3,r2\) + 9a: 43 ff ff af storb r4,0xafff:m\(r4,r3\) + 9e: 13 00 55 5a storb r5,0xa1234:l\(r6,r5\) + a2: 34 12 + a4: 19 00 00 5f storb r0,0xffff1:l\(r1,r0\) + a8: f1 ff + aa: 19 00 10 5f storb r1,0xffff1:l\(r1,r0\) + ae: f1 ff + b0: 19 00 20 5f storb r2,0xfedcc:l\(r1,r0\) + b4: cc ed + b6: 19 00 32 5f storb r3,0xf5433:l\(r3,r2\) + ba: 33 54 + bc: 19 00 43 5f storb r4,0xf5001:l\(r4,r3\) + c0: 01 50 + c2: 19 00 55 55 storb r5,0x5edcc:l\(r6,r5\) + c6: cc ed + c8: 00 fe storb r0,\[r12\]0x0:s\(r1,r0\) + ca: 18 fe storb r1,\[r13\]0x0:s\(r1,r0\) + cc: 70 c6 04 12 storb r7,\[r12\]0x234:m\(r1,r0\) + d0: 13 00 38 61 storb r3,\[r13\]0x1abcd:l\(r1,r0\) + d4: cd ab + d6: 13 00 40 6a storb r4,\[r12\]0xa1234:l\(r1,r0\) + da: 34 12 + dc: 13 00 58 6b storb r5,\[r13\]0xb1234:l\(r1,r0\) + e0: 34 12 + e2: 13 00 68 6f storb r6,\[r13\]0xfffff:l\(r1,r0\) + e6: ff ff + e8: 40 81 cd 0b storb \$0x4:s,0xbcd <main\+0xbcd>:m + ec: 5a 81 cd ab storb \$0x5:s,0xaabcd <main\+0xaabcd>:m + f0: 12 00 3f 3a storb \$0x3:s,0xfaabcd <main\+0xfaabcd>:l + f4: cd ab + f6: 50 84 14 00 storb \$0x5:s,\[r13\]0x14:m + fa: 40 85 fc ab storb \$0x4:s,\[r13\]0xabfc:m + fe: 30 84 34 12 storb \$0x3:s,\[r12\]0x1234:m + 102: 30 85 34 12 storb \$0x3:s,\[r12\]0x1234:m + 106: 30 84 34 00 storb \$0x3:s,\[r12\]0x34:m + 10a: 30 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r1,r0\) + 10e: 31 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r3,r2\) + 112: 36 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r4,r3\) + 116: 32 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r5,r4\) + 11a: 37 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r6,r5\) + 11e: 33 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r7,r6\) + 122: 34 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r9,r8\) + 126: 35 86 3a 4a storb \$0x3:s,\[r12\]0xa7a:m\(r11,r10\) + 12a: 38 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r1,r0\) + 12e: 39 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r3,r2\) + 132: 3e 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r4,r3\) + 136: 3a 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r5,r4\) + 13a: 3f 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r6,r5\) + 13e: 3b 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r7,r6\) + 142: 3c 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r9,r8\) + 146: 3d 86 3a 4a storb \$0x3:s,\[r13\]0xa7a:m\(r11,r10\) + 14a: 3e 86 5a 4b storb \$0x5:s,\[r13\]0xb7a:m\(r4,r3\) + 14e: 37 86 1a 41 storb \$0x1:s,\[r12\]0x17a:m\(r6,r5\) + 152: 3f 86 14 01 storb \$0x1:s,\[r13\]0x134:m\(r6,r5\) + 156: 12 00 36 2a storb \$0x3:s,\[r12\]0xabcde:l\(r4,r3\) + 15a: de bc + 15c: 12 00 5e 20 storb \$0x5:s,\[r13\]0xabcd:l\(r4,r3\) + 160: cd ab + 162: 12 00 37 20 storb \$0x3:s,\[r12\]0xabcd:l\(r6,r5\) + 166: cd ab + 168: 12 00 3f 20 storb \$0x3:s,\[r13\]0xbcde:l\(r6,r5\) + 16c: de bc + 16e: 12 00 52 00 storb \$0x5:s,0x0:l\(r2\) + 172: 00 00 + 174: 3c 83 34 00 storb \$0x3:s,0x34:m\(r12\) + 178: 3d 83 ab 00 storb \$0x3:s,0xab:m\(r13\) + 17c: 12 00 51 00 storb \$0x5:s,0xad:l\(r1\) + 180: ad 00 + 182: 12 00 52 00 storb \$0x5:s,0xcd:l\(r2\) + 186: cd 00 + 188: 12 00 50 00 storb \$0x5:s,0xfff:l\(r0\) + 18c: ff 0f + 18e: 12 00 34 00 storb \$0x3:s,0xbcd:l\(r4\) + 192: cd 0b + 194: 3c 83 ff 0f storb \$0x3:s,0xfff:m\(r12\) + 198: 3d 83 ff 0f storb \$0x3:s,0xfff:m\(r13\) + 19c: 3d 83 ff ff storb \$0x3:s,0xffff:m\(r13\) + 1a0: 3c 83 43 23 storb \$0x3:s,0x2343:m\(r12\) + 1a4: 12 00 32 01 storb \$0x3:s,0x2345:l\(r2\) + 1a8: 45 23 + 1aa: 12 00 38 04 storb \$0x3:s,0xabcd:l\(r8\) + 1ae: cd ab + 1b0: 12 00 3d 1f storb \$0x3:s,0xfabcd:l\(r13\) + 1b4: cd ab + 1b6: 12 00 38 0f storb \$0x3:s,0xabcd:l\(r8\) + 1ba: cd ab + 1bc: 12 00 39 0f storb \$0x3:s,0xabcd:l\(r9\) + 1c0: cd ab + 1c2: 12 00 39 04 storb \$0x3:s,0xabcd:l\(r9\) + 1c6: cd ab + 1c8: 31 82 storb \$0x3:s,0x0:s\(r2,r1\) + 1ca: 51 83 01 00 storb \$0x5:s,0x1:m\(r2,r1\) + 1ce: 41 83 34 12 storb \$0x4:s,0x1234:m\(r2,r1\) + 1d2: 31 83 34 12 storb \$0x3:s,0x1234:m\(r2,r1\) + 1d6: 12 00 31 11 storb \$0x3:s,0x12345:l\(r2,r1\) + 1da: 45 23 + 1dc: 31 83 23 01 storb \$0x3:s,0x123:m\(r2,r1\) + 1e0: 12 00 31 11 storb \$0x3:s,0x12345:l\(r2,r1\) + 1e4: 45 23 diff --git a/gas/testsuite/gas/cr16/storb_test.s b/gas/testsuite/gas/cr16/storb_test.s new file mode 100644 index 000000000000..2cd2706ec07c --- /dev/null +++ b/gas/testsuite/gas/cr16/storb_test.s @@ -0,0 +1,143 @@ + .text
+ .global main
+main:
+ ######################
+ # storb reg abs20/24
+ ######################
+ storb r0,0x0
+ storb r1,0xff
+ storb r3,0xfff
+ storb r4,0x1234
+ storb r5,0x1234
+ storb r0,0x7A1234
+ storb r1,0xBA1234
+ storb r2,0xffffff
+ ######################
+ # storb abs20 rel reg
+ ######################
+ storb r0,[r12]0x0
+ storb r0,[r13]0x0
+ storb r1,[r12]0xff
+ storb r1,[r13]0xff
+ storb r3,[r12]0xfff
+ storb r3,[r13]0xfff
+ storb r4,[r12]0x1234
+ storb r4,[r13]0x1234
+ storb r5,[r12]0x1234
+ storb r5,[r13]0x1234
+ storb r2,[r12]0x4567
+ storb r2,[r13]0xA1234
+ ###################################
+ # storb reg rbase(disp20/-disp20)
+ ###################################
+ storb r1,0x4(r1,r0)
+ storb r3,0x4(r3,r2)
+ storb r4,0x1234(r1,r0)
+ storb r5,0x1234(r3,r2)
+ storb r6,0xA1234(r1,r0)
+ storb r1,-0x4(r1,r0)
+ storb r3,-0x4(r3,r2)
+ storb r4,-0x1234(r1,r0)
+ storb r5,-0x1234(r3,r2)
+ storb r6,-0xA1234(r1,r0)
+ #################################################
+ # storb reg rpbase(disp4/disp16/disp20/-disp20)
+ #################################################
+ storb r0,0x0(r1,r0)
+ storb r0,0x0(r1,r0)
+ storb r0,0xf(r1,r0)
+ storb r1,0xf(r1,r0)
+ storb r2,0x1234(r1,r0)
+ storb r3,0xabcd(r3,r2)
+ storb r4,0xAfff(r4,r3)
+ storb r5,0xA1234(r6,r5)
+ storb r0,-0xf(r1,r0)
+ storb r1,-0xf(r1,r0)
+ storb r2,-0x1234(r1,r0)
+ storb r3,-0xabcd(r3,r2)
+ storb r4,-0xAfff(r4,r3)
+ storb r5,-0xA1234(r6,r5)
+ ####################################
+ # storb rbase(disp0/disp14) rel reg
+ ####################################
+ storb r0,[r12]0x0(r1,r0)
+ storb r1,[r13]0x0(r1,r0)
+ storb r2,[r12]0x1234(r1,r0)
+ storb r3,[r13]0x1abcd(r1,r0)
+ #################################
+ # storb reg rpbase(disp20) rel
+ #################################
+ storb r4,[r12]0xA1234(r1,r0)
+ storb r5,[r13]0xB1234(r1,r0)
+ storb r6,[r13]0xfffff(r1,r0)
+ #######################
+ # storb reg, uimm16/20
+ ######################
+ storb $4,0xbcd
+ storb $5,0xaabcd
+ storb $3,0xfaabcd
+
+ #######################
+ # storb reg, uimm16/20
+ ######################
+ storb $5,[r12]0x14
+ storb $4,[r13]0xabfc
+ storb $3,[r12]0x1234
+ storb $3,[r13]0x1234
+ storb $3,[r12]0x34
+ #######################
+ # storb imm, index-rbase
+ ######################
+ storb $3,[r12]0xa7a(r1,r0)
+ storb $3,[r12]0xa7a(r3,r2)
+ storb $3,[r12]0xa7a(r4,r3)
+ storb $3,[r12]0xa7a(r5,r4)
+ storb $3,[r12]0xa7a(r6,r5)
+ storb $3,[r12]0xa7a(r7,r6)
+ storb $3,[r12]0xa7a(r9,r8)
+ storb $3,[r12]0xa7a(r11,r10)
+ storb $3,[r13]0xa7a(r1,r0)
+ storb $3,[r13]0xa7a(r3,r2)
+ storb $3,[r13]0xa7a(r4,r3)
+ storb $3,[r13]0xa7a(r5,r4)
+ storb $3,[r13]0xa7a(r6,r5)
+ storb $3,[r13]0xa7a(r7,r6)
+ storb $3,[r13]0xa7a(r9,r8)
+ storb $3,[r13]0xa7a(r11,r10)
+ storb $5,[r13]0xb7a(r4,r3)
+ storb $1,[r12]0x17a(r6,r5)
+ storb $1,[r13]0x134(r6,r5)
+ storb $3,[r12]0xabcde(r4,r3)
+ storb $5,[r13]0xabcd(r4,r3)
+ storb $3,[r12]0xabcd(r6,r5)
+ storb $3,[r13]0xbcde(r6,r5)
+ #######################
+ # storb imm4, rbase(disp)
+ ######################
+ storb $5,0x0(r2)
+ storb $3,0x34(r12)
+ storb $3,0xab(r13)
+ storb $5,0xad(r1)
+ storb $5,0xcd(r2)
+ storb $5,0xfff(r0)
+ storb $3,0xbcd(r4)
+ storb $3,0xfff(r12)
+ storb $3,0xfff(r13)
+ storb $3,0xffff(r13)
+ storb $3,0x2343(r12)
+ storb $3,0x12345(r2)
+ storb $3,0x4abcd(r8)
+ storb $3,0xfabcd(r13)
+ storb $3,0xfabcd(r8)
+ storb $3,0xfabcd(r9)
+ storb $3,0x4abcd(r9)
+ ##########################
+ # storb imm, disp20(rpbase)
+ #########################
+ storb $3,0x0(r2,r1)
+ storb $5,0x1(r2,r1)
+ storb $4,0x1234(r2,r1)
+ storb $3,0x1234(r2,r1)
+ storb $3,0x12345(r2,r1)
+ storb $3,0x123(r2,r1)
+ storb $3,0x12345(r2,r1)
diff --git a/gas/testsuite/gas/cr16/stord_test.d b/gas/testsuite/gas/cr16/stord_test.d new file mode 100644 index 000000000000..9e31b7a886e9 --- /dev/null +++ b/gas/testsuite/gas/cr16/stord_test.d @@ -0,0 +1,80 @@ +#as: +#objdump: -dr +#name: stord_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 c7 00 00 stord \(r1,r0\),0x0 <main>:m + 4: 00 c7 ff 00 stord \(r1,r0\),0xff <main\+0xff>:m + 8: 20 c7 ff 0f stord \(r3,r2\),0xfff <main\+0xfff>:m + c: 30 c7 34 12 stord \(r4,r3\),0x1234 <main\+0x1234>:m + 10: 40 c7 34 12 stord \(r5,r4\),0x1234 <main\+0x1234>:m + 14: 13 00 07 ba stord \(r1,r0\),0x7a1234 <main\+0x7a1234>:l + 18: 34 12 + 1a: 13 00 0b ba stord \(r1,r0\),0xba1234 <main\+0xba1234>:l + 1e: 34 12 + 20: 13 00 1f bf stord \(r2,r1\),0xffffff <main\+0xffffff>:l + 24: ff ff + 26: 00 cc 00 00 stord \(r1,r0\),\[r12\]0x0:m + 2a: 00 cd 00 00 stord \(r1,r0\),\[r12\]0x0:m + 2e: 00 cc ff 00 stord \(r1,r0\),\[r12\]0xff:m + 32: 00 cd ff 00 stord \(r1,r0\),\[r12\]0xff:m + 36: 20 cc ff 0f stord \(r3,r2\),\[r12\]0xfff:m + 3a: 20 cd ff 0f stord \(r3,r2\),\[r12\]0xfff:m + 3e: 30 cc 34 12 stord \(r4,r3\),\[r12\]0x1234:m + 42: 30 cd 34 12 stord \(r4,r3\),\[r12\]0x1234:m + 46: 40 cc 34 12 stord \(r5,r4\),\[r13\]0x1234:m + 4a: 40 cd 34 12 stord \(r5,r4\),\[r13\]0x1234:m + 4e: 10 cc 67 45 stord \(r2,r1\),\[r12\]0x4567:m + 52: 1a cd 34 12 stord \(r2,r1\),\[r12\]0xa1234:m + 56: 10 e2 stord \(r2,r1\),0x4:s\(r1,r0\) + 58: 22 e2 stord \(r3,r2\),0x4:s\(r3,r2\) + 5a: 30 ef 34 12 stord \(r4,r3\),0x1234:m\(r1,r0\) + 5e: 42 ef 34 12 stord \(r5,r4\),0x1234:m\(r3,r2\) + 62: 13 00 50 9a stord \(r6,r5\),0xa1234:l\(r1,r0\) + 66: 34 12 + 68: 19 00 10 9f stord \(r2,r1\),0xffffc:l\(r1,r0\) + 6c: fc ff + 6e: 19 00 22 9f stord \(r3,r2\),0xffffc:l\(r3,r2\) + 72: fc ff + 74: 19 00 30 9f stord \(r4,r3\),0xfedcc:l\(r1,r0\) + 78: cc ed + 7a: 19 00 42 9f stord \(r5,r4\),0xfedcc:l\(r3,r2\) + 7e: cc ed + 80: 19 00 50 95 stord \(r6,r5\),0x5edcc:l\(r1,r0\) + 84: cc ed + 86: 00 e0 stord \(r1,r0\),0x0:s\(r1,r0\) + 88: 00 e0 stord \(r1,r0\),0x0:s\(r1,r0\) + 8a: 00 ef 0f 00 stord \(r1,r0\),0xf:m\(r1,r0\) + 8e: 00 ef 0f 00 stord \(r1,r0\),0xf:m\(r1,r0\) + 92: 10 ef 34 12 stord \(r2,r1\),0x1234:m\(r1,r0\) + 96: 22 ef cd ab stord \(r3,r2\),0xabcd:m\(r3,r2\) + 9a: 33 ef ff af stord \(r4,r3\),0xafff:m\(r4,r3\) + 9e: 13 00 65 9a stord \(r7,r6\),0xa1234:l\(r6,r5\) + a2: 34 12 + a4: 19 00 00 9f stord \(r1,r0\),0xffff1:l\(r1,r0\) + a8: f1 ff + aa: 19 00 00 9f stord \(r1,r0\),0xffff1:l\(r1,r0\) + ae: f1 ff + b0: 19 00 10 9f stord \(r2,r1\),0xfedcc:l\(r1,r0\) + b4: cc ed + b6: 19 00 22 9f stord \(r3,r2\),0xf5433:l\(r3,r2\) + ba: 33 54 + bc: 19 00 43 9f stord \(r5,r4\),0xf5001:l\(r4,r3\) + c0: 01 50 + c2: 19 00 45 95 stord \(r5,r4\),0x5edcc:l\(r6,r5\) + c6: cc ed + c8: 00 ee stord \(r1,r0\),\[r12\]0x0:s\(r1,r0\) + ca: 08 ee stord \(r1,r0\),\[r13\]0x0:s\(r1,r0\) + cc: b0 c6 04 12 stord \(r12,r11\),\[r12\]0x234:m\(r1,r0\) + d0: 13 00 28 a1 stord \(r3,r2\),\[r13\]0x1abcd:l\(r1,r0\) + d4: cd ab + d6: 13 00 20 aa stord \(r3,r2\),\[r12\]0xa1234:l\(r1,r0\) + da: 34 12 + dc: 13 00 38 ab stord \(r4,r3\),\[r13\]0xb1234:l\(r1,r0\) + e0: 34 12 + e2: 13 00 48 af stord \(r5,r4\),\[r13\]0xfffff:l\(r1,r0\) + e6: ff ff diff --git a/gas/testsuite/gas/cr16/stord_test.s b/gas/testsuite/gas/cr16/stord_test.s new file mode 100644 index 000000000000..dcac741fc052 --- /dev/null +++ b/gas/testsuite/gas/cr16/stord_test.s @@ -0,0 +1,72 @@ + .text
+ .global main
+main:
+ ######################
+ # stord abs20/24 regp
+ ######################
+ stord (r1,r0),0x0
+ stord (r1,r0),0xff
+ stord (r3,r2),0xfff
+ stord (r4,r3),0x1234
+ stord (r5,r4),0x1234
+ stord (r1,r0),0x7A1234
+ stord (r1,r0),0xBA1234
+ stord (r2,r1),0xffffff
+ ######################
+ # stord abs20 rel regp
+ ######################
+ stord (r1,r0),[r12]0x0
+ stord (r1,r0),[r13]0x0
+ stord (r1,r0),[r12]0xff
+ stord (r1,r0),[r13]0xff
+ stord (r3,r2),[r12]0xfff
+ stord (r3,r2),[r13]0xfff
+ stord (r4,r3),[r12]0x1234
+ stord (r4,r3),[r13]0x1234
+ stord (r5,r4),[r12]0x1234
+ stord (r5,r4),[r13]0x1234
+ stord (r2,r1),[r12]0x4567
+ stord (r2,r1),[r13]0xA1234
+ ###################################
+ # stord regp rbase(disp20/-disp20)
+ ###################################
+ stord (r2,r1),0x4(r1,r0)
+ stord (r3,r2),0x4(r3,r2)
+ stord (r4,r3),0x1234(r1,r0)
+ stord (r5,r4),0x1234(r3,r2)
+ stord (r6,r5),0xA1234(r1,r0)
+ stord (r2,r1),-0x4(r1,r0)
+ stord (r3,r2),-0x4(r3,r2)
+ stord (r4,r3),-0x1234(r1,r0)
+ stord (r5,r4),-0x1234(r3,r2)
+ stord (r6,r5),-0xA1234(r1,r0)
+ #################################################
+ # stord regp rpbase(disp4/disp16/disp20/-disp20)
+ #################################################
+ stord (r1,r0),0x0(r1,r0)
+ stord (r1,r0),0x0(r1,r0)
+ stord (r1,r0),0xf(r1,r0)
+ stord (r1,r0),0xf(r1,r0)
+ stord (r2,r1),0x1234(r1,r0)
+ stord (r3,r2),0xabcd(r3,r2)
+ stord (r4,r3),0xAfff(r4,r3)
+ stord (r7,r6),0xA1234(r6,r5)
+ stord (r1,r0),-0xf(r1,r0)
+ stord (r1,r0),-0xf(r1,r0)
+ stord (r2,r1),-0x1234(r1,r0)
+ stord (r3,r2),-0xabcd(r3,r2)
+ stord (r5,r4),-0xAfff(r4,r3)
+ stord (r5,r4),-0xA1234(r6,r5)
+ ####################################
+ # stord rbase(disp0/disp14) rel reg
+ ####################################
+ stord (r1,r0),[r12]0x0(r1,r0)
+ stord (r1,r0),[r13]0x0(r1,r0)
+ stord (r2,r1),[r12]0x1234(r1,r0)
+ stord (r3,r2),[r13]0x1abcd(r1,r0)
+ #################################
+ # stord rpbase(disp20) rel reg
+ #################################
+ stord (r3,r2),[r12]0xA1234(r1,r0)
+ stord (r4,r3),[r13]0xB1234(r1,r0)
+ stord (r5,r4),[r13]0xfffff(r1,r0)
diff --git a/gas/testsuite/gas/cr16/storm_test.d b/gas/testsuite/gas/cr16/storm_test.d new file mode 100644 index 000000000000..8e103ba9d665 --- /dev/null +++ b/gas/testsuite/gas/cr16/storm_test.d @@ -0,0 +1,25 @@ +#as: +#objdump: -dr +#name: storm_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: b0 00 storm \$0x1,r0 + 2: b1 00 storm \$0x2,r0 + 4: b2 00 storm \$0x3,r0 + 6: b3 00 storm \$0x4,r0 + 8: b4 00 storm \$0x5,r0 + a: b5 00 storm \$0x6,r0 + c: b6 00 storm \$0x7,r0 + e: b7 00 storm \$0x8,r0 + 10: b8 00 stormp \$0x1,r0 + 12: b9 00 stormp \$0x2,r0 + 14: ba 00 stormp \$0x3,r0 + 16: bb 00 stormp \$0x4,r0 + 18: bc 00 stormp \$0x5,r0 + 1a: bd 00 stormp \$0x6,r0 + 1c: be 00 stormp \$0x7,r0 + 1e: bf 00 stormp \$0x8,r0 diff --git a/gas/testsuite/gas/cr16/storm_test.s b/gas/testsuite/gas/cr16/storm_test.s new file mode 100644 index 000000000000..ad5de6117e73 --- /dev/null +++ b/gas/testsuite/gas/cr16/storm_test.s @@ -0,0 +1,25 @@ + .text + .global main +main: + ############## + # storm cnt + ############## + storm $1 + storm $2 + storm $3 + storm $4 + storm $5 + storm $6 + storm $7 + storm $8 + ############## + # stormp cnt + ############## + stormp $1 + stormp $2 + stormp $3 + stormp $4 + stormp $5 + stormp $6 + stormp $7 + stormp $8 diff --git a/gas/testsuite/gas/cr16/storw_test.d b/gas/testsuite/gas/cr16/storw_test.d new file mode 100644 index 000000000000..02b1b6543aee --- /dev/null +++ b/gas/testsuite/gas/cr16/storw_test.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: storw_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 c9 00 00 storw r0,0x0 <main>:m + 4: 10 c9 ff 00 storw r1,0xff <main\+0xff>:m + 8: 30 c9 ff 0f storw r3,0xfff <main\+0xfff>:m + c: 40 c9 34 12 storw r4,0x1234 <main\+0x1234>:m + 10: 50 c9 34 12 storw r5,0x1234 <main\+0x1234>:m + 14: 13 00 07 fa storw r0,0x7a1234 <main\+0x7a1234>:l + 18: 34 12 + 1a: 13 00 1b fa storw r1,0xba1234 <main\+0xba1234>:l + 1e: 34 12 + 20: 13 00 2f ff storw r2,0xffffff <main\+0xffffff>:l + 24: ff ff + 26: 00 ce 00 00 storw r0,\[r12\]0x0:m + 2a: 00 cf 00 00 storw r0,\[r12\]0x0:m + 2e: 10 ce ff 00 storw r1,\[r12\]0xff:m + 32: 10 cf ff 00 storw r1,\[r12\]0xff:m + 36: 30 ce ff 0f storw r3,\[r12\]0xfff:m + 3a: 30 cf ff 0f storw r3,\[r12\]0xfff:m + 3e: 40 ce 34 12 storw r4,\[r13\]0x1234:m + 42: 40 cf 34 12 storw r4,\[r13\]0x1234:m + 46: 50 ce 34 12 storw r5,\[r13\]0x1234:m + 4a: 50 cf 34 12 storw r5,\[r13\]0x1234:m + 4e: 20 ce 67 45 storw r2,\[r12\]0x4567:m + 52: 2a cf 34 12 storw r2,\[r12\]0xa1234:m + 56: 10 d2 storw r1,0x4:s\(r1,r0\) + 58: 32 d2 storw r3,0x4:s\(r3,r2\) + 5a: 40 df 34 12 storw r4,0x1234:m\(r1,r0\) + 5e: 52 df 34 12 storw r5,0x1234:m\(r3,r2\) + 62: 13 00 60 da storw r6,0xa1234:l\(r1,r0\) + 66: 34 12 + 68: 19 00 10 df storw r1,0xffffc:l\(r1,r0\) + 6c: fc ff + 6e: 19 00 32 df storw r3,0xffffc:l\(r3,r2\) + 72: fc ff + 74: 19 00 40 df storw r4,0xfedcc:l\(r1,r0\) + 78: cc ed + 7a: 19 00 52 df storw r5,0xfedcc:l\(r3,r2\) + 7e: cc ed + 80: 19 00 60 d5 storw r6,0x5edcc:l\(r1,r0\) + 84: cc ed + 86: 00 d0 storw r0,0x0:s\(r1,r0\) + 88: 00 d0 storw r0,0x0:s\(r1,r0\) + 8a: 00 df 0f 00 storw r0,0xf:m\(r1,r0\) + 8e: 10 df 0f 00 storw r1,0xf:m\(r1,r0\) + 92: 20 df 34 12 storw r2,0x1234:m\(r1,r0\) + 96: 32 df cd ab storw r3,0xabcd:m\(r3,r2\) + 9a: 43 df ff af storw r4,0xafff:m\(r4,r3\) + 9e: 13 00 55 da storw r5,0xa1234:l\(r6,r5\) + a2: 34 12 + a4: 19 00 00 df storw r0,0xffff1:l\(r1,r0\) + a8: f1 ff + aa: 19 00 10 df storw r1,0xffff1:l\(r1,r0\) + ae: f1 ff + b0: 19 00 20 df storw r2,0xfedcc:l\(r1,r0\) + b4: cc ed + b6: 19 00 32 df storw r3,0xf5433:l\(r3,r2\) + ba: 33 54 + bc: 19 00 43 df storw r4,0xf5001:l\(r4,r3\) + c0: 01 50 + c2: 19 00 55 d5 storw r5,0x5edcc:l\(r6,r5\) + c6: cc ed + c8: 00 de storw r0,\[r12\]0x0:s\(r1,r0\) + ca: 18 de storw r1,\[r13\]0x0:s\(r1,r0\) + cc: f0 c6 04 12 storw r15,\[r12\]0x234:m\(r1,r0\) + d0: 13 00 38 e1 storw r3,\[r13\]0x1abcd:l\(r1,r0\) + d4: cd ab + d6: 13 00 40 ea storw r4,\[r12\]0xa1234:l\(r1,r0\) + da: 34 12 + dc: 13 00 58 eb storw r5,\[r13\]0xb1234:l\(r1,r0\) + e0: 34 12 + e2: 13 00 68 ef storw r6,\[r13\]0xfffff:l\(r1,r0\) + e6: ff ff + e8: 40 c1 cd 0b storw \$0x4:s,0xbcd <main\+0xbcd>:m + ec: 5a c1 cd ab storw \$0x5:s,0xaabcd <main\+0xaabcd>:m + f0: 13 00 3f 3a storw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l + f4: cd ab + f6: 50 c4 14 00 storw \$0x5:s,\[r13\]0x14:m + fa: 40 c5 fc ab storw \$0x4:s,\[r13\]0xabfc:m + fe: 30 c4 34 12 storw \$0x3:s,\[r12\]0x1234:m + 102: 30 c5 34 12 storw \$0x3:s,\[r12\]0x1234:m + 106: 30 c4 34 00 storw \$0x3:s,\[r12\]0x34:m + 10a: 30 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\) + 10e: 31 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\) + 112: 36 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\) + 116: 32 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\) + 11a: 37 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\) + 11e: 33 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\) + 122: 34 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\) + 126: 35 c6 3a 4a storw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\) + 12a: 38 c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\) + 12e: 39 c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\) + 132: 3e c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\) + 136: 3a c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\) + 13a: 3f c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\) + 13e: 3b c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\) + 142: 3c c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\) + 146: 3d c6 3a 4a storw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\) + 14a: 3e c6 5a 4b storw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\) + 14e: 37 c6 1a 41 storw \$0x1:s,\[r12\]0x17a:m\(r6,r5\) + 152: 3f c6 14 01 storw \$0x1:s,\[r13\]0x134:m\(r6,r5\) + 156: 13 00 36 2a storw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\) + 15a: de bc + 15c: 13 00 5e 20 storw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\) + 160: cd ab + 162: 13 00 37 20 storw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\) + 166: cd ab + 168: 13 00 3f 20 storw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\) + 16c: de bc + 16e: 13 00 52 00 storw \$0x5:s,0x0:l\(r2\) + 172: 00 00 + 174: 3c c3 34 00 storw \$0x3:s,0x34:m\(r12\) + 178: 3d c3 ab 00 storw \$0x3:s,0xab:m\(r13\) + 17c: 13 00 51 00 storw \$0x5:s,0xad:l\(r1\) + 180: ad 00 + 182: 13 00 52 00 storw \$0x5:s,0xcd:l\(r2\) + 186: cd 00 + 188: 13 00 50 00 storw \$0x5:s,0xfff:l\(r0\) + 18c: ff 0f + 18e: 13 00 34 00 storw \$0x3:s,0xbcd:l\(r4\) + 192: cd 0b + 194: 3c c3 ff 0f storw \$0x3:s,0xfff:m\(r12\) + 198: 3d c3 ff 0f storw \$0x3:s,0xfff:m\(r13\) + 19c: 3d c3 ff ff storw \$0x3:s,0xffff:m\(r13\) + 1a0: 3c c3 43 23 storw \$0x3:s,0x2343:m\(r12\) + 1a4: 13 00 32 01 storw \$0x3:s,0x2345:l\(r2\) + 1a8: 45 23 + 1aa: 13 00 38 04 storw \$0x3:s,0xabcd:l\(r8\) + 1ae: cd ab + 1b0: 13 00 3d 1f storw \$0x3:s,0xfabcd:l\(r13\) + 1b4: cd ab + 1b6: 13 00 38 0f storw \$0x3:s,0xabcd:l\(r8\) + 1ba: cd ab + 1bc: 13 00 39 0f storw \$0x3:s,0xabcd:l\(r9\) + 1c0: cd ab + 1c2: 13 00 39 04 storw \$0x3:s,0xabcd:l\(r9\) + 1c6: cd ab + 1c8: 31 c2 storw \$0x3:s,0x0:s\(r2,r1\) + 1ca: 51 c3 01 00 storw \$0x5:s,0x1:m\(r2,r1\) + 1ce: 41 c3 34 12 storw \$0x4:s,0x1234:m\(r2,r1\) + 1d2: 31 c3 34 12 storw \$0x3:s,0x1234:m\(r2,r1\) + 1d6: 13 00 31 11 storw \$0x3:s,0x12345:l\(r2,r1\) + 1da: 45 23 + 1dc: 31 c3 23 01 storw \$0x3:s,0x123:m\(r2,r1\) + 1e0: 13 00 31 11 storw \$0x3:s,0x12345:l\(r2,r1\) + 1e4: 45 23 diff --git a/gas/testsuite/gas/cr16/storw_test.s b/gas/testsuite/gas/cr16/storw_test.s new file mode 100644 index 000000000000..6adee5cee1ff --- /dev/null +++ b/gas/testsuite/gas/cr16/storw_test.s @@ -0,0 +1,144 @@ + .text
+ .global main
+main:
+ ######################
+ # storw reg abs20/24
+ ######################
+ storw r0,0x0
+ storw r1,0xff
+ storw r3,0xfff
+ storw r4,0x1234
+ storw r5,0x1234
+ storw r0,0x7A1234
+ storw r1,0xBA1234
+ storw r2,0xffffff
+ ######################
+ # storw abs20 rel reg
+ ######################
+ storw r0,[r12]0x0
+ storw r0,[r13]0x0
+ storw r1,[r12]0xff
+ storw r1,[r13]0xff
+ storw r3,[r12]0xfff
+ storw r3,[r13]0xfff
+ storw r4,[r12]0x1234
+ storw r4,[r13]0x1234
+ storw r5,[r12]0x1234
+ storw r5,[r13]0x1234
+ storw r2,[r12]0x4567
+ storw r2,[r13]0xA1234
+ ###################################
+ # storw reg rbase(disp20/-disp20)
+ ###################################
+ storw r1,0x4(r1,r0)
+ storw r3,0x4(r3,r2)
+ storw r4,0x1234(r1,r0)
+ storw r5,0x1234(r3,r2)
+ storw r6,0xA1234(r1,r0)
+ storw r1,-0x4(r1,r0)
+ storw r3,-0x4(r3,r2)
+ storw r4,-0x1234(r1,r0)
+ storw r5,-0x1234(r3,r2)
+ storw r6,-0xA1234(r1,r0)
+ #################################################
+ # storw reg rpbase(disp4/disp16/disp20/-disp20)
+ #################################################
+ storw r0,0x0(r1,r0)
+ storw r0,0x0(r1,r0)
+ storw r0,0xf(r1,r0)
+ storw r1,0xf(r1,r0)
+ storw r2,0x1234(r1,r0)
+ storw r3,0xabcd(r3,r2)
+ storw r4,0xAfff(r4,r3)
+ storw r5,0xA1234(r6,r5)
+ storw r0,-0xf(r1,r0)
+ storw r1,-0xf(r1,r0)
+ storw r2,-0x1234(r1,r0)
+ storw r3,-0xabcd(r3,r2)
+ storw r4,-0xAfff(r4,r3)
+ storw r5,-0xA1234(r6,r5)
+ ####################################
+ # storw rbase(disp0/disp14) rel reg
+ ####################################
+ storw r0,[r12]0x0(r1,r0)
+ storw r1,[r13]0x0(r1,r0)
+ storw r2,[r12]0x1234(r1,r0)
+ storw r3,[r13]0x1abcd(r1,r0)
+ #################################
+ # storw reg rpbase(disp20) rel
+ #################################
+ storw r4,[r12]0xA1234(r1,r0)
+ storw r5,[r13]0xB1234(r1,r0)
+ storw r6,[r13]0xfffff(r1,r0)
+ #######################
+ # storw reg, uimm16/20
+ ######################
+ storw $4,0xbcd
+ storw $5,0xaabcd
+ storw $3,0xfaabcd
+
+ #######################
+ # storw reg, uimm16/20
+ ######################
+ storw $5,[r12]0x14
+ storw $4,[r13]0xabfc
+ storw $3,[r12]0x1234
+ storw $3,[r13]0x1234
+ storw $3,[r12]0x34
+ #######################
+ # storw imm, index-rbase
+ ######################
+ storw $3,[r12]0xa7a(r1,r0)
+ storw $3,[r12]0xa7a(r3,r2)
+ storw $3,[r12]0xa7a(r4,r3)
+ storw $3,[r12]0xa7a(r5,r4)
+ storw $3,[r12]0xa7a(r6,r5)
+ storw $3,[r12]0xa7a(r7,r6)
+ storw $3,[r12]0xa7a(r9,r8)
+ storw $3,[r12]0xa7a(r11,r10)
+ storw $3,[r13]0xa7a(r1,r0)
+ storw $3,[r13]0xa7a(r3,r2)
+ storw $3,[r13]0xa7a(r4,r3)
+ storw $3,[r13]0xa7a(r5,r4)
+ storw $3,[r13]0xa7a(r6,r5)
+ storw $3,[r13]0xa7a(r7,r6)
+ storw $3,[r13]0xa7a(r9,r8)
+ storw $3,[r13]0xa7a(r11,r10)
+ storw $5,[r13]0xb7a(r4,r3)
+ storw $1,[r12]0x17a(r6,r5)
+ storw $1,[r13]0x134(r6,r5)
+ storw $3,[r12]0xabcde(r4,r3)
+ storw $5,[r13]0xabcd(r4,r3)
+ storw $3,[r12]0xabcd(r6,r5)
+ storw $3,[r13]0xbcde(r6,r5)
+ #######################
+ # storw imm4, rbase(disp)
+ ######################
+ storw $5,0x0(r2)
+ storw $3,0x34(r12)
+ storw $3,0xab(r13)
+ storw $5,0xad(r1)
+ storw $5,0xcd(r2)
+ storw $5,0xfff(r0)
+ storw $3,0xbcd(r4)
+ storw $3,0xfff(r12)
+ storw $3,0xfff(r13)
+ storw $3,0xffff(r13)
+ storw $3,0x2343(r12)
+ storw $3,0x12345(r2)
+ storw $3,0x4abcd(r8)
+ storw $3,0xfabcd(r13)
+ storw $3,0xfabcd(r8)
+ storw $3,0xfabcd(r9)
+ storw $3,0x4abcd(r9)
+ ##########################
+ # storw imm, disp20(rpbase)
+ #########################
+ storw $3,0x0(r2,r1)
+ storw $5,0x1(r2,r1)
+ storw $4,0x1234(r2,r1)
+ storw $3,0x1234(r2,r1)
+ storw $3,0x12345(r2,r1)
+ storw $3,0x123(r2,r1)
+ storw $3,0x12345(r2,r1)
+
diff --git a/gas/testsuite/gas/cr16/sub_test.d b/gas/testsuite/gas/cr16/sub_test.d new file mode 100644 index 000000000000..1744836588d1 --- /dev/null +++ b/gas/testsuite/gas/cr16/sub_test.d @@ -0,0 +1,69 @@ +#as: +#objdump: -dr +#name: sub_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 38 subb \$0xf:s,r1 + 2: b2 38 ff 00 subb \$0xff:m,r2 + 6: b1 38 ff 0f subb \$0xfff:m,r1 + a: b1 38 14 00 subb \$0x14:m,r1 + e: a2 38 subb \$0xa:s,r2 + 10: 12 39 subb r1,r2 + 12: 23 39 subb r2,r3 + 14: 34 39 subb r3,r4 + 16: 56 39 subb r5,r6 + 18: 67 39 subb r6,r7 + 1a: 78 39 subb r7,r8 + 1c: f1 3c subcb \$0xf:s,r1 + 1e: b2 3c ff 00 subcb \$0xff:m,r2 + 22: b1 3c ff 0f subcb \$0xfff:m,r1 + 26: b1 3c 14 00 subcb \$0x14:m,r1 + 2a: a2 3c subcb \$0xa:s,r2 + 2c: 12 3d subcb r1,r2 + 2e: 23 3d subcb r2,r3 + 30: 34 3d subcb r3,r4 + 32: 56 3d subcb r5,r6 + 34: 67 3d subcb r6,r7 + 36: 78 3d subcb r7,r8 + 38: f1 3e subcw \$0xf:s,r1 + 3a: b2 3e ff 00 subcw \$0xff:m,r2 + 3e: b1 3e ff 0f subcw \$0xfff:m,r1 + 42: b1 3e 14 00 subcw \$0x14:m,r1 + 46: a2 3e subcw \$0xa:s,r2 + 48: 12 3f subcw r1,r2 + 4a: 23 3f subcw r2,r3 + 4c: 34 3f subcw r3,r4 + 4e: 56 3f subcw r5,r6 + 50: 67 3f subcw r6,r7 + 52: 78 3f subcw r7,r8 + 54: f1 3a subw \$0xf:s,r1 + 56: b2 3a ff 00 subw \$0xff:m,r2 + 5a: b1 3a ff 0f subw \$0xfff:m,r1 + 5e: b1 3a 14 00 subw \$0x14:m,r1 + 62: a2 3a subw \$0xa:s,r2 + 64: 12 3b subw r1,r2 + 66: 23 3b subw r2,r3 + 68: 34 3b subw r3,r4 + 6a: 56 3b subw r5,r6 + 6c: 67 3b subw r6,r7 + 6e: 78 3b subw r7,r8 + 70: 31 00 00 00 subd \$0xf:l,\(r2,r1\) + 74: 0f 00 + 76: 31 00 00 00 subd \$0xff:l,\(r2,r1\) + 7a: ff 00 + 7c: 31 00 00 00 subd \$0xfff:l,\(r2,r1\) + 80: ff 0f + 82: 31 00 00 00 subd \$0xffff:l,\(r2,r1\) + 86: ff ff + 88: 31 00 0f 00 subd \$0xfffff:l,\(r2,r1\) + 8c: ff ff + 8e: 31 00 ff 0f subd \$0xfffffff:l,\(r2,r1\) + 92: ff ff + 94: 31 00 ff ff subd \$0xffffffff:l,\(r2,r1\) + 98: ff ff + 9a: 14 00 31 c0 subd \(r4,r3\),\(r2,r1\) + 9e: 14 00 31 c0 subd \(r4,r3\),\(r2,r1\) diff --git a/gas/testsuite/gas/cr16/sub_test.s b/gas/testsuite/gas/cr16/sub_test.s new file mode 100644 index 000000000000..ad0ac07a6ef8 --- /dev/null +++ b/gas/testsuite/gas/cr16/sub_test.s @@ -0,0 +1,93 @@ + .text + .global main +main: + ########### + # SUBB imm4/imm16, reg + ########### + subb $0xf,r1 + subb $0xff,r2 + subb $0xfff,r1 + #subb $0xffff,r2 // CHECK WITH CRASM 4.1 + subb $20,r1 + subb $10,r2 + ########### + # SUBB reg, reg + ########### + subb r1,r2 + subb r2,r3 + subb r3,r4 + subb r5,r6 + subb r6,r7 + subb r7,r8 + ########### + # SUBCB imm4/imm16, reg + ########### + subcb $0xf,r1 + subcb $0xff,r2 + subcb $0xfff,r1 + #subcb $0xffff,r2 // CHECK WITH CRASM 4.1 + subcb $20,r1 + subcb $10,r2 + ########### + # SUBCB reg, reg + ########### + subcb r1,r2 + subcb r2,r3 + subcb r3,r4 + subcb r5,r6 + subcb r6,r7 + subcb r7,r8 + ########### + # SUBCW imm4/imm16, reg + ########### + subcw $0xf,r1 + subcw $0xff,r2 + subcw $0xfff,r1 + #subcw $0xffff,r2 // CHECK WITH CRASM 4.1 + subcw $20,r1 + subcw $10,r2 + ########### + # SUBCW reg, reg + ########### + subcw r1,r2 + subcw r2,r3 + subcw r3,r4 + subcw r5,r6 + subcw r6,r7 + subcw r7,r8 + ########### + # SUBW imm4/imm16, reg + ########### + subw $0xf,r1 + subw $0xff,r2 + subw $0xfff,r1 + #subw $0xffff,r2 // CHECK WITH CRASM 4.1 + subw $20,r1 + subw $10,r2 + ########### + # SUBW reg, reg + ########### + subw r1,r2 + subw r2,r3 + subw r3,r4 + subw r5,r6 + subw r6,r7 + subw r7,r8 + ########### + # SUBD imm4/imm16/imm32, regp + ########### + subd $0xf,(r2,r1) + subd $0xff,(r2,r1) + subd $0xfff,(r2,r1) + subd $0xffff,(r2,r1) + subd $0xfffff,(r2,r1) + subd $0xfffffff,(r2,r1) + subd $0xffffffff,(r2,r1) + ########### + # SUBD regp, regp + ########### + subd (r4,r3),(r2,r1) + subd (r4,r3),(r2,r1) + #subd $10,(sp) + #subd $14,(sp) + #subd $8,(sp) diff --git a/gas/testsuite/gas/cr16/tbit_test.d b/gas/testsuite/gas/cr16/tbit_test.d new file mode 100644 index 000000000000..cf5b4993b942 --- /dev/null +++ b/gas/testsuite/gas/cr16/tbit_test.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dr +#name: tbit_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 00 06 tbit \$0x0:s,r0 + 2: 11 06 tbit \$0x1:s,r1 + 4: 22 06 tbit \$0x2:s,r2 + 6: 33 06 tbit \$0x3:s,r3 + 8: 44 06 tbit \$0x4:s,r4 + a: 55 06 tbit \$0x5:s,r5 + c: 66 06 tbit \$0x6:s,r6 + e: 77 06 tbit \$0x7:s,r7 + 10: 88 06 tbit \$0x8:s,r8 + 12: 99 06 tbit \$0x9:s,r9 + 14: aa 06 tbit \$0xa:s,r10 + 16: bb 06 tbit \$0xb:s,r11 + 18: cc 06 tbit \$0xc:s,r12 + 1a: dd 06 tbit \$0xd:s,r13 + 1c: 00 07 tbit r0,r0 + 1e: 11 07 tbit r1,r1 + 20: 22 07 tbit r2,r2 + 22: 33 07 tbit r3,r3 + 24: 44 07 tbit r4,r4 + 26: 55 07 tbit r5,r5 + 28: 66 07 tbit r6,r6 + 2a: 77 07 tbit r7,r7 + 2c: 88 07 tbit r8,r8 + 2e: 99 07 tbit r9,r9 + 30: aa 07 tbit r10,r10 + 32: bb 07 tbit r11,r11 + 34: cc 07 tbit r12,r12 + 36: dd 07 tbit r13,r13 diff --git a/gas/testsuite/gas/cr16/tbit_test.s b/gas/testsuite/gas/cr16/tbit_test.s new file mode 100644 index 000000000000..aec79232e4e4 --- /dev/null +++ b/gas/testsuite/gas/cr16/tbit_test.s @@ -0,0 +1,41 @@ + .text + .global main +main: + ################## + # tbit uimm4, reg + ################# + tbit $0,r0 + tbit $1,r1 + tbit $2,r2 + tbit $3,r3 + tbit $4,r4 + tbit $5,r5 + tbit $6,r6 + tbit $7,r7 + tbit $8,r8 + tbit $9,r9 + tbit $10,r10 + tbit $11,r11 + tbit $12,r12 + tbit $13,r13 +# tbit $14,r14 // Add error check for these INST +# tbit $15,r15 // Add error check for these INST + ################## + # tbit reg, reg + ################# + tbit r0,r0 + tbit r1,r1 + tbit r2,r2 + tbit r3,r3 + tbit r4,r4 + tbit r5,r5 + tbit r6,r6 + tbit r7,r7 + tbit r8,r8 + tbit r9,r9 + tbit r10,r10 + tbit r11,r11 + tbit r12,r12 + tbit r13,r13 +# tbit r14,r14 // Add error check for these INST +# tbit r15,r15 // Add error check for these INST diff --git a/gas/testsuite/gas/cr16/tbitb_test.d b/gas/testsuite/gas/cr16/tbitb_test.d new file mode 100644 index 000000000000..9965fac585cc --- /dev/null +++ b/gas/testsuite/gas/cr16/tbitb_test.d @@ -0,0 +1,82 @@ +#as: +#objdump: -dr +#name: tbitb_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: c0 7b cd 0b tbitb \$0x4,0xbcd <main\+0xbcd>:m + 4: da 7b cd ab tbitb \$0x5,0xaabcd <main\+0xaabcd>:m + 8: 10 00 3f fa tbitb \$0x3,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: 50 78 14 00 tbitb \$0x5,\[r12\]0x14:m + 12: c0 78 fc ab tbitb \$0x4,\[r13\]0xabfc:m + 16: 30 78 34 12 tbitb \$0x3,\[r12\]0x1234:m + 1a: b0 78 34 12 tbitb \$0x3,\[r13\]0x1234:m + 1e: 30 78 34 00 tbitb \$0x3,\[r12\]0x34:m + 22: b0 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r1,r0\) + 26: b1 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r3,r2\) + 2a: b6 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r4,r3\) + 2e: b2 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r5,r4\) + 32: b7 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r6,r5\) + 36: b3 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r7,r6\) + 3a: b4 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r9,r8\) + 3e: b5 7a 3a 4a tbitb \$0x3,\[r12\]0xa7a:m\(r11,r10\) + 42: b8 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r1,r0\) + 46: b9 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r3,r2\) + 4a: be 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r4,r3\) + 4e: ba 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r5,r4\) + 52: bf 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r6,r5\) + 56: bb 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r7,r6\) + 5a: bc 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r9,r8\) + 5e: bd 7a 3a 4a tbitb \$0x3,\[r13\]0xa7a:m\(r11,r10\) + 62: be 7a 5a 4b tbitb \$0x5,\[r13\]0xb7a:m\(r4,r3\) + 66: b7 7a 1a 41 tbitb \$0x1,\[r12\]0x17a:m\(r6,r5\) + 6a: bf 7a 14 01 tbitb \$0x1,\[r13\]0x134:m\(r6,r5\) + 6e: 10 00 36 ea tbitb \$0x3,\[r12\]0xabcde:l\(r4,r3\) + 72: de bc + 74: 10 00 5e e0 tbitb \$0x5,\[r13\]0xabcd:l\(r4,r3\) + 78: cd ab + 7a: 10 00 37 e0 tbitb \$0x3,\[r12\]0xabcd:l\(r6,r5\) + 7e: cd ab + 80: 10 00 3f e0 tbitb \$0x3,\[r13\]0xbcde:l\(r6,r5\) + 84: de bc + 86: 10 00 52 c0 tbitb \$0x5,0x0:l\(r2\) + 8a: 00 00 + 8c: 3c 7b 34 00 tbitb \$0x3,0x34:m\(r12\) + 90: 3d 7b ab 00 tbitb \$0x3,0xab:m\(r13\) + 94: 10 00 51 c0 tbitb \$0x5,0xad:l\(r1\) + 98: ad 00 + 9a: 10 00 52 c0 tbitb \$0x5,0xcd:l\(r2\) + 9e: cd 00 + a0: 10 00 50 c0 tbitb \$0x5,0xfff:l\(r0\) + a4: ff 0f + a6: 10 00 34 c0 tbitb \$0x3,0xbcd:l\(r4\) + aa: cd 0b + ac: 3c 7b ff 0f tbitb \$0x3,0xfff:m\(r12\) + b0: 3d 7b ff 0f tbitb \$0x3,0xfff:m\(r13\) + b4: 3d 7b ff ff tbitb \$0x3,0xffff:m\(r13\) + b8: 3c 7b 43 23 tbitb \$0x3,0x2343:m\(r12\) + bc: 10 00 32 c1 tbitb \$0x3,0x2345:l\(r2\) + c0: 45 23 + c2: 10 00 38 c4 tbitb \$0x3,0xabcd:l\(r8\) + c6: cd ab + c8: 10 00 3d df tbitb \$0x3,0xfabcd:l\(r13\) + cc: cd ab + ce: 10 00 38 cf tbitb \$0x3,0xabcd:l\(r8\) + d2: cd ab + d4: 10 00 39 cf tbitb \$0x3,0xabcd:l\(r9\) + d8: cd ab + da: 10 00 39 c4 tbitb \$0x3,0xabcd:l\(r9\) + de: cd ab + e0: 31 7a tbitb \$0x3,0x0:s\(r2,r1\) + e2: 51 7b 01 00 tbitb \$0x5,0x1:m\(r2,r1\) + e6: 41 7b 34 12 tbitb \$0x4,0x1234:m\(r2,r1\) + ea: 31 7b 34 12 tbitb \$0x3,0x1234:m\(r2,r1\) + ee: 10 00 31 d1 tbitb \$0x3,0x12345:l\(r2,r1\) + f2: 45 23 + f4: 31 7b 23 01 tbitb \$0x3,0x123:m\(r2,r1\) + f8: 10 00 31 d1 tbitb \$0x3,0x12345:l\(r2,r1\) + fc: 45 23 diff --git a/gas/testsuite/gas/cr16/tbitb_test.s b/gas/testsuite/gas/cr16/tbitb_test.s new file mode 100644 index 000000000000..7fe427ee02af --- /dev/null +++ b/gas/testsuite/gas/cr16/tbitb_test.s @@ -0,0 +1,62 @@ + .text + .global main +main: + tbitb $4,0xbcd + tbitb $5,0xaabcd + tbitb $3,0xfaabcd + + tbitb $5,[r12]0x14 + tbitb $4,[r13]0xabfc + tbitb $3,[r12]0x1234 + tbitb $3,[r13]0x1234 + tbitb $3,[r12]0x34 + + tbitb $3,[r12]0xa7a(r1,r0) + tbitb $3,[r12]0xa7a(r3,r2) + tbitb $3,[r12]0xa7a(r4,r3) + tbitb $3,[r12]0xa7a(r5,r4) + tbitb $3,[r12]0xa7a(r6,r5) + tbitb $3,[r12]0xa7a(r7,r6) + tbitb $3,[r12]0xa7a(r9,r8) + tbitb $3,[r12]0xa7a(r11,r10) + tbitb $3,[r13]0xa7a(r1,r0) + tbitb $3,[r13]0xa7a(r3,r2) + tbitb $3,[r13]0xa7a(r4,r3) + tbitb $3,[r13]0xa7a(r5,r4) + tbitb $3,[r13]0xa7a(r6,r5) + tbitb $3,[r13]0xa7a(r7,r6) + tbitb $3,[r13]0xa7a(r9,r8) + tbitb $3,[r13]0xa7a(r11,r10) + tbitb $5,[r13]0xb7a(r4,r3) + tbitb $1,[r12]0x17a(r6,r5) + tbitb $1,[r13]0x134(r6,r5) + tbitb $3,[r12]0xabcde(r4,r3) + tbitb $5,[r13]0xabcd(r4,r3) + tbitb $3,[r12]0xabcd(r6,r5) + tbitb $3,[r13]0xbcde(r6,r5) + + tbitb $5,0x0(r2) + tbitb $3,0x34(r12) + tbitb $3,0xab(r13) + tbitb $5,0xad(r1) + tbitb $5,0xcd(r2) + tbitb $5,0xfff(r0) + tbitb $3,0xbcd(r4) + tbitb $3,0xfff(r12) + tbitb $3,0xfff(r13) + tbitb $3,0xffff(r13) + tbitb $3,0x2343(r12) + tbitb $3,0x12345(r2) + tbitb $3,0x4abcd(r8) + tbitb $3,0xfabcd(r13) + tbitb $3,0xfabcd(r8) + tbitb $3,0xfabcd(r9) + tbitb $3,0x4abcd(r9) + + tbitb $3,0x0(r2,r1) + tbitb $5,0x1(r2,r1) + tbitb $4,0x1234(r2,r1) + tbitb $3,0x1234(r2,r1) + tbitb $3,0x12345(r2,r1) + tbitb $3,0x123(r2,r1) + tbitb $3,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/tbitw_test.d b/gas/testsuite/gas/cr16/tbitw_test.d new file mode 100644 index 000000000000..81022b1a8cec --- /dev/null +++ b/gas/testsuite/gas/cr16/tbitw_test.d @@ -0,0 +1,155 @@ +#as: +#objdump: -dr +#name: tbitw_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: 40 7f cd 0b tbitw \$0x4:s,0xbcd <main\+0xbcd>:m + 4: 5a 7f cd ab tbitw \$0x5:s,0xaabcd <main\+0xaabcd>:m + 8: 11 00 3f fa tbitw \$0x3:s,0xfaabcd <main\+0xfaabcd>:l + c: cd ab + e: a0 7f cd 0b tbitw \$0xa:s,0xbcd <main\+0xbcd>:m + 12: fa 7f cd ab tbitw \$0xf:s,0xaabcd <main\+0xaabcd>:m + 16: 11 00 ef fa tbitw \$0xe:s,0xfaabcd <main\+0xfaabcd>:l + 1a: cd ab + 1c: 50 7c 14 00 tbitw \$0x5:s,\[r13\]0x14:m + 20: 40 7d fc ab tbitw \$0x4:s,\[r13\]0xabfc:m + 24: 30 7c 34 12 tbitw \$0x3:s,\[r12\]0x1234:m + 28: 30 7d 34 12 tbitw \$0x3:s,\[r12\]0x1234:m + 2c: 30 7c 34 00 tbitw \$0x3:s,\[r12\]0x34:m + 30: f0 7c 14 00 tbitw \$0xf:s,\[r13\]0x14:m + 34: e0 7d fc ab tbitw \$0xe:s,\[r13\]0xabfc:m + 38: d0 7c 34 12 tbitw \$0xd:s,\[r13\]0x1234:m + 3c: d0 7d 34 12 tbitw \$0xd:s,\[r13\]0x1234:m + 40: b0 7c 34 00 tbitw \$0xb:s,\[r12\]0x34:m + 44: f0 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r1,r0\) + 48: f1 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r3,r2\) + 4c: f6 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r4,r3\) + 50: f2 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r5,r4\) + 54: f7 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r6,r5\) + 58: f3 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r7,r6\) + 5c: f4 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r9,r8\) + 60: f5 7a 3a 4a tbitw \$0x3:s,\[r12\]0xa7a:m\(r11,r10\) + 64: f8 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r1,r0\) + 68: f9 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r3,r2\) + 6c: fe 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r4,r3\) + 70: fa 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r5,r4\) + 74: ff 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r6,r5\) + 78: fb 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r7,r6\) + 7c: fc 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r9,r8\) + 80: fd 7a 3a 4a tbitw \$0x3:s,\[r13\]0xa7a:m\(r11,r10\) + 84: fe 7a 5a 4b tbitw \$0x5:s,\[r13\]0xb7a:m\(r4,r3\) + 88: f7 7a 1a 41 tbitw \$0x1:s,\[r12\]0x17a:m\(r6,r5\) + 8c: ff 7a 14 01 tbitw \$0x1:s,\[r13\]0x134:m\(r6,r5\) + 90: 11 00 36 ea tbitw \$0x3:s,\[r12\]0xabcde:l\(r4,r3\) + 94: de bc + 96: 11 00 5e e0 tbitw \$0x5:s,\[r13\]0xabcd:l\(r4,r3\) + 9a: cd ab + 9c: 11 00 37 e0 tbitw \$0x3:s,\[r12\]0xabcd:l\(r6,r5\) + a0: cd ab + a2: 11 00 3f e0 tbitw \$0x3:s,\[r13\]0xbcde:l\(r6,r5\) + a6: de bc + a8: f0 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r1,r0\) + ac: f1 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r3,r2\) + b0: f6 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r4,r3\) + b4: f2 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r5,r4\) + b8: f7 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r6,r5\) + bc: f3 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r7,r6\) + c0: f4 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r9,r8\) + c4: f5 7a da 4a tbitw \$0xd:s,\[r12\]0xafa:m\(r11,r10\) + c8: f8 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r1,r0\) + cc: f9 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r3,r2\) + d0: fe 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r4,r3\) + d4: fa 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r5,r4\) + d8: ff 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r6,r5\) + dc: fb 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r7,r6\) + e0: fc 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r9,r8\) + e4: fd 7a da 4a tbitw \$0xd:s,\[r13\]0xafa:m\(r11,r10\) + e8: fe 7a fa 4b tbitw \$0xf:s,\[r13\]0xbfa:m\(r4,r3\) + ec: f7 7a ba 41 tbitw \$0xb:s,\[r12\]0x1fa:m\(r6,r5\) + f0: ff 7a b4 01 tbitw \$0xb:s,\[r13\]0x1b4:m\(r6,r5\) + f4: 11 00 d6 ea tbitw \$0xd:s,\[r12\]0xabcde:l\(r4,r3\) + f8: de bc + fa: 11 00 fe e0 tbitw \$0xf:s,\[r13\]0xabcd:l\(r4,r3\) + fe: cd ab + 100: 11 00 d7 e0 tbitw \$0xd:s,\[r12\]0xabcd:l\(r6,r5\) + 104: cd ab + 106: 11 00 df e0 tbitw \$0xd:s,\[r13\]0xbcde:l\(r6,r5\) + 10a: de bc + 10c: 11 00 52 c0 tbitw \$0x5:s,0x0:l\(r2\) + 110: 00 00 + 112: 3c 79 34 00 tbitw \$0x3:s,0x34:m\(r12\) + 116: 3d 79 ab 00 tbitw \$0x3:s,0xab:m\(r13\) + 11a: 11 00 51 c0 tbitw \$0x5:s,0xad:l\(r1\) + 11e: ad 00 + 120: 11 00 52 c0 tbitw \$0x5:s,0xcd:l\(r2\) + 124: cd 00 + 126: 11 00 50 c0 tbitw \$0x5:s,0xfff:l\(r0\) + 12a: ff 0f + 12c: 11 00 34 c0 tbitw \$0x3:s,0xbcd:l\(r4\) + 130: cd 0b + 132: 3c 79 ff 0f tbitw \$0x3:s,0xfff:m\(r12\) + 136: 3d 79 ff 0f tbitw \$0x3:s,0xfff:m\(r13\) + 13a: 3d 79 ff ff tbitw \$0x3:s,0xffff:m\(r13\) + 13e: 3c 79 43 23 tbitw \$0x3:s,0x2343:m\(r12\) + 142: 11 00 32 c1 tbitw \$0x3:s,0x2345:l\(r2\) + 146: 45 23 + 148: 11 00 38 c4 tbitw \$0x3:s,0xabcd:l\(r8\) + 14c: cd ab + 14e: 11 00 3d df tbitw \$0x3:s,0xfabcd:l\(r13\) + 152: cd ab + 154: 11 00 38 cf tbitw \$0x3:s,0xabcd:l\(r8\) + 158: cd ab + 15a: 11 00 39 cf tbitw \$0x3:s,0xabcd:l\(r9\) + 15e: cd ab + 160: 11 00 39 c4 tbitw \$0x3:s,0xabcd:l\(r9\) + 164: cd ab + 166: 11 00 f2 c0 tbitw \$0xf:s,0x0:l\(r2\) + 16a: 00 00 + 16c: dc 79 34 00 tbitw \$0xd:s,0x34:m\(r12\) + 170: dd 79 ab 00 tbitw \$0xd:s,0xab:m\(r13\) + 174: 11 00 f1 c0 tbitw \$0xf:s,0xad:l\(r1\) + 178: ad 00 + 17a: 11 00 f2 c0 tbitw \$0xf:s,0xcd:l\(r2\) + 17e: cd 00 + 180: 11 00 f0 c0 tbitw \$0xf:s,0xfff:l\(r0\) + 184: ff 0f + 186: 11 00 d4 c0 tbitw \$0xd:s,0xbcd:l\(r4\) + 18a: cd 0b + 18c: dc 79 ff 0f tbitw \$0xd:s,0xfff:m\(r12\) + 190: dd 79 ff 0f tbitw \$0xd:s,0xfff:m\(r13\) + 194: dd 79 ff ff tbitw \$0xd:s,0xffff:m\(r13\) + 198: dc 79 43 23 tbitw \$0xd:s,0x2343:m\(r12\) + 19c: 11 00 d2 c1 tbitw \$0xd:s,0x2345:l\(r2\) + 1a0: 45 23 + 1a2: 11 00 d8 c4 tbitw \$0xd:s,0xabcd:l\(r8\) + 1a6: cd ab + 1a8: 11 00 dd df tbitw \$0xd:s,0xfabcd:l\(r13\) + 1ac: cd ab + 1ae: 11 00 d8 cf tbitw \$0xd:s,0xabcd:l\(r8\) + 1b2: cd ab + 1b4: 11 00 d9 cf tbitw \$0xd:s,0xabcd:l\(r9\) + 1b8: cd ab + 1ba: 11 00 d9 c4 tbitw \$0xd:s,0xabcd:l\(r9\) + 1be: cd ab + 1c0: 31 7e tbitw \$0x3:s,0x0:s\(r2,r1\) + 1c2: 51 79 01 00 tbitw \$0x5:s,0x1:m\(r2,r1\) + 1c6: 41 79 34 12 tbitw \$0x4:s,0x1234:m\(r2,r1\) + 1ca: 31 79 34 12 tbitw \$0x3:s,0x1234:m\(r2,r1\) + 1ce: 11 00 31 d1 tbitw \$0x3:s,0x12345:l\(r2,r1\) + 1d2: 45 23 + 1d4: 31 79 23 01 tbitw \$0x3:s,0x123:m\(r2,r1\) + 1d8: 11 00 31 d1 tbitw \$0x3:s,0x12345:l\(r2,r1\) + 1dc: 45 23 + 1de: d1 7e tbitw \$0xd:s,0x0:s\(r2,r1\) + 1e0: f1 79 01 00 tbitw \$0xf:s,0x1:m\(r2,r1\) + 1e4: e1 79 34 12 tbitw \$0xe:s,0x1234:m\(r2,r1\) + 1e8: d1 79 34 12 tbitw \$0xd:s,0x1234:m\(r2,r1\) + 1ec: 11 00 d1 d1 tbitw \$0xd:s,0x12345:l\(r2,r1\) + 1f0: 45 23 + 1f2: d1 79 23 01 tbitw \$0xd:s,0x123:m\(r2,r1\) + 1f6: 11 00 d1 d1 tbitw \$0xd:s,0x12345:l\(r2,r1\) + 1fa: 45 23 diff --git a/gas/testsuite/gas/cr16/tbitw_test.s b/gas/testsuite/gas/cr16/tbitw_test.s new file mode 100644 index 000000000000..939804cd0094 --- /dev/null +++ b/gas/testsuite/gas/cr16/tbitw_test.s @@ -0,0 +1,117 @@ + .text + .global main +main: + tbitw $4,0xbcd + tbitw $5,0xaabcd + tbitw $3,0xfaabcd + tbitw $10,0xbcd + tbitw $15,0xaabcd + tbitw $14,0xfaabcd + + tbitw $5,[r12]0x14 + tbitw $4,[r13]0xabfc + tbitw $3,[r12]0x1234 + tbitw $3,[r13]0x1234 + tbitw $3,[r12]0x34 + tbitw $15,[r12]0x14 + tbitw $14,[r13]0xabfc + tbitw $13,[r12]0x1234 + tbitw $13,[r13]0x1234 + tbitw $11,[r12]0x34 + + tbitw $3,[r12]0xa7a(r1,r0) + tbitw $3,[r12]0xa7a(r3,r2) + tbitw $3,[r12]0xa7a(r4,r3) + tbitw $3,[r12]0xa7a(r5,r4) + tbitw $3,[r12]0xa7a(r6,r5) + tbitw $3,[r12]0xa7a(r7,r6) + tbitw $3,[r12]0xa7a(r9,r8) + tbitw $3,[r12]0xa7a(r11,r10) + tbitw $3,[r13]0xa7a(r1,r0) + tbitw $3,[r13]0xa7a(r3,r2) + tbitw $3,[r13]0xa7a(r4,r3) + tbitw $3,[r13]0xa7a(r5,r4) + tbitw $3,[r13]0xa7a(r6,r5) + tbitw $3,[r13]0xa7a(r7,r6) + tbitw $3,[r13]0xa7a(r9,r8) + tbitw $3,[r13]0xa7a(r11,r10) + tbitw $5,[r13]0xb7a(r4,r3) + tbitw $1,[r12]0x17a(r6,r5) + tbitw $1,[r13]0x134(r6,r5) + tbitw $3,[r12]0xabcde(r4,r3) + tbitw $5,[r13]0xabcd(r4,r3) + tbitw $3,[r12]0xabcd(r6,r5) + tbitw $3,[r13]0xbcde(r6,r5) + tbitw $13,[r12]0xa7a(r1,r0) + tbitw $13,[r12]0xa7a(r3,r2) + tbitw $13,[r12]0xa7a(r4,r3) + tbitw $13,[r12]0xa7a(r5,r4) + tbitw $13,[r12]0xa7a(r6,r5) + tbitw $13,[r12]0xa7a(r7,r6) + tbitw $13,[r12]0xa7a(r9,r8) + tbitw $13,[r12]0xa7a(r11,r10) + tbitw $13,[r13]0xa7a(r1,r0) + tbitw $13,[r13]0xa7a(r3,r2) + tbitw $13,[r13]0xa7a(r4,r3) + tbitw $13,[r13]0xa7a(r5,r4) + tbitw $13,[r13]0xa7a(r6,r5) + tbitw $13,[r13]0xa7a(r7,r6) + tbitw $13,[r13]0xa7a(r9,r8) + tbitw $13,[r13]0xa7a(r11,r10) + tbitw $15,[r13]0xb7a(r4,r3) + tbitw $11,[r12]0x17a(r6,r5) + tbitw $11,[r13]0x134(r6,r5) + tbitw $13,[r12]0xabcde(r4,r3) + tbitw $15,[r13]0xabcd(r4,r3) + tbitw $13,[r12]0xabcd(r6,r5) + tbitw $13,[r13]0xbcde(r6,r5) + + tbitw $5,0x0(r2) + tbitw $3,0x34(r12) + tbitw $3,0xab(r13) + tbitw $5,0xad(r1) + tbitw $5,0xcd(r2) + tbitw $5,0xfff(r0) + tbitw $3,0xbcd(r4) + tbitw $3,0xfff(r12) + tbitw $3,0xfff(r13) + tbitw $3,0xffff(r13) + tbitw $3,0x2343(r12) + tbitw $3,0x12345(r2) + tbitw $3,0x4abcd(r8) + tbitw $3,0xfabcd(r13) + tbitw $3,0xfabcd(r8) + tbitw $3,0xfabcd(r9) + tbitw $3,0x4abcd(r9) + tbitw $15,0x0(r2) + tbitw $13,0x34(r12) + tbitw $13,0xab(r13) + tbitw $15,0xad(r1) + tbitw $15,0xcd(r2) + tbitw $15,0xfff(r0) + tbitw $13,0xbcd(r4) + tbitw $13,0xfff(r12) + tbitw $13,0xfff(r13) + tbitw $13,0xffff(r13) + tbitw $13,0x2343(r12) + tbitw $13,0x12345(r2) + tbitw $13,0x4abcd(r8) + tbitw $13,0xfabcd(r13) + tbitw $13,0xfabcd(r8) + tbitw $13,0xfabcd(r9) + tbitw $13,0x4abcd(r9) + + tbitw $3,0x0(r2,r1) + tbitw $5,0x1(r2,r1) + tbitw $4,0x1234(r2,r1) + tbitw $3,0x1234(r2,r1) + tbitw $3,0x12345(r2,r1) + tbitw $3,0x123(r2,r1) + tbitw $3,0x12345(r2,r1) + tbitw $13,0x0(r2,r1) + tbitw $15,0x1(r2,r1) + tbitw $14,0x1234(r2,r1) + tbitw $13,0x1234(r2,r1) + tbitw $13,0x12345(r2,r1) + tbitw $13,0x123(r2,r1) + tbitw $13,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/xor_test.d b/gas/testsuite/gas/cr16/xor_test.d new file mode 100644 index 000000000000..57f7e23676e0 --- /dev/null +++ b/gas/testsuite/gas/cr16/xor_test.d @@ -0,0 +1,49 @@ +#as: +#objdump: -dr +#name: xor_test + +.*: +file format .* + +Disassembly of section .text: + +00000000 <main>: + 0: f1 28 xorb \$0xf:s,r1 + 2: b2 28 ff 00 xorb \$0xff:m,r2 + 6: b1 28 ff 0f xorb \$0xfff:m,r1 + a: b2 28 ff ff xorb \$0xffff:m,r2 + e: b1 28 14 00 xorb \$0x14:m,r1 + 12: a2 28 xorb \$0xa:s,r2 + 14: 12 29 xorb r1,r2 + 16: 23 29 xorb r2,r3 + 18: 34 29 xorb r3,r4 + 1a: 56 29 xorb r5,r6 + 1c: 67 29 xorb r6,r7 + 1e: 78 29 xorb r7,r8 + 20: f1 2a xorw \$0xf:s,r1 + 22: b2 2a ff 00 xorw \$0xff:m,r2 + 26: b1 2a ff 0f xorw \$0xfff:m,r1 + 2a: b2 2a ff ff xorw \$0xffff:m,r2 + 2e: b1 2a 14 00 xorw \$0x14:m,r1 + 32: a2 2a xorw \$0xa:s,r2 + 34: 12 2b xorw r1,r2 + 36: 23 2b xorw r2,r3 + 38: 34 2b xorw r3,r4 + 3a: 56 2b xorw r5,r6 + 3c: 67 2b xorw r6,r7 + 3e: 78 2b xorw r7,r8 + 40: 61 00 00 00 xord \$0xf:l,\(r2,r1\) + 44: 0f 00 + 46: 61 00 00 00 xord \$0xff:l,\(r2,r1\) + 4a: ff 00 + 4c: 61 00 00 00 xord \$0xfff:l,\(r2,r1\) + 50: ff 0f + 52: 61 00 00 00 xord \$0xffff:l,\(r2,r1\) + 56: ff ff + 58: 61 00 0f 00 xord \$0xfffff:l,\(r2,r1\) + 5c: ff ff + 5e: 61 00 ff 0f xord \$0xfffffff:l,\(r2,r1\) + 62: ff ff + 64: 61 00 ff ff xord \$0xffffffff:l,\(r2,r1\) + 68: ff ff + 6a: 14 00 31 a0 xord \(r4,r3\),\(r2,r1\) + 6e: 14 00 31 a0 xord \(r4,r3\),\(r2,r1\) diff --git a/gas/testsuite/gas/cr16/xor_test.s b/gas/testsuite/gas/cr16/xor_test.s new file mode 100644 index 000000000000..b99d103c3b34 --- /dev/null +++ b/gas/testsuite/gas/cr16/xor_test.s @@ -0,0 +1,57 @@ + .text + .global main +main: + ########### + # XORB imm4/imm16, reg + ########### + xorb $0xf,r1 + xorb $0xff,r2 + xorb $0xfff,r1 + xorb $0xffff,r2 + xorb $20,r1 + xorb $10,r2 + ########### + # XORB reg, reg + ########### + xorb r1,r2 + xorb r2,r3 + xorb r3,r4 + xorb r5,r6 + xorb r6,r7 + xorb r7,r8 + ########### + # XORW imm4/imm16, reg + ########### + xorw $0xf,r1 + xorw $0xff,r2 + xorw $0xfff,r1 + xorw $0xffff,r2 + xorw $20,r1 + xorw $10,r2 + ########### + # XORW reg, reg + ########### + xorw r1,r2 + xorw r2,r3 + xorw r3,r4 + xorw r5,r6 + xorw r6,r7 + xorw r7,r8 + ########### + # XORD imm32, regp + ########### + xord $0xf,(r2,r1) + xord $0xff,(r2,r1) + xord $0xfff,(r2,r1) + xord $0xffff,(r2,r1) + xord $0xfffff,(r2,r1) + xord $0xfffffff,(r2,r1) + xord $0xffffffff,(r2,r1) + ########### + # XORD regp, regp + ########### + xord (r4,r3),(r2,r1) + xord (r4,r3),(r2,r1) + #xord $10,(sp) + #xord $14,(sp) + #xord $8,(sp) diff --git a/gas/testsuite/gas/crx/allinsn.exp b/gas/testsuite/gas/crx/allinsn.exp index f3f8ae80a58e..2a52f701b5c1 100644 --- a/gas/testsuite/gas/crx/allinsn.exp +++ b/gas/testsuite/gas/crx/allinsn.exp @@ -2,19 +2,6 @@ # Driver for CRX assembler testsuite # -proc run_list_test { name opts } { - global srcdir subdir - set testname "CRX $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if {[regexp_diff "dump.out" "${file}.l"] } { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if ![istarget crx-*-*] { return } diff --git a/gas/testsuite/gas/d10v/address-002.l b/gas/testsuite/gas/d10v/address-002.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-002.l +++ b/gas/testsuite/gas/d10v/address-002.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-003.l b/gas/testsuite/gas/d10v/address-003.l index 2f8c4f596b8e..36068de50a8f 100644 --- a/gas/testsuite/gas/d10v/address-003.l +++ b/gas/testsuite/gas/d10v/address-003.l @@ -1,3 +1,4 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 + diff --git a/gas/testsuite/gas/d10v/address-004.l b/gas/testsuite/gas/d10v/address-004.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-004.l +++ b/gas/testsuite/gas/d10v/address-004.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-005.l b/gas/testsuite/gas/d10v/address-005.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-005.l +++ b/gas/testsuite/gas/d10v/address-005.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-006.l b/gas/testsuite/gas/d10v/address-006.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-006.l +++ b/gas/testsuite/gas/d10v/address-006.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-007.l b/gas/testsuite/gas/d10v/address-007.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-007.l +++ b/gas/testsuite/gas/d10v/address-007.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-008.l b/gas/testsuite/gas/d10v/address-008.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-008.l +++ b/gas/testsuite/gas/d10v/address-008.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-009.l b/gas/testsuite/gas/d10v/address-009.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-009.l +++ b/gas/testsuite/gas/d10v/address-009.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-010.l b/gas/testsuite/gas/d10v/address-010.l index 2f8c4f596b8e..2847fa9b9ee5 100644 --- a/gas/testsuite/gas/d10v/address-010.l +++ b/gas/testsuite/gas/d10v/address-010.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld r0 diff --git a/gas/testsuite/gas/d10v/address-011.l b/gas/testsuite/gas/d10v/address-011.l index 2f8c4f596b8e..688385e4d196 100644 --- a/gas/testsuite/gas/d10v/address-011.l +++ b/gas/testsuite/gas/d10v/address-011.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld2w r0 diff --git a/gas/testsuite/gas/d10v/address-012.l b/gas/testsuite/gas/d10v/address-012.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-012.l +++ b/gas/testsuite/gas/d10v/address-012.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-013.l b/gas/testsuite/gas/d10v/address-013.l index 2f8c4f596b8e..edf420d15df6 100644 --- a/gas/testsuite/gas/d10v/address-013.l +++ b/gas/testsuite/gas/d10v/address-013.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st r0 diff --git a/gas/testsuite/gas/d10v/address-014.l b/gas/testsuite/gas/d10v/address-014.l index 2f8c4f596b8e..49f87bbc3ec2 100644 --- a/gas/testsuite/gas/d10v/address-014.l +++ b/gas/testsuite/gas/d10v/address-014.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st2w r0 diff --git a/gas/testsuite/gas/d10v/address-015.l b/gas/testsuite/gas/d10v/address-015.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-015.l +++ b/gas/testsuite/gas/d10v/address-015.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-016.l b/gas/testsuite/gas/d10v/address-016.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-016.l +++ b/gas/testsuite/gas/d10v/address-016.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-017.l b/gas/testsuite/gas/d10v/address-017.l index 2f8c4f596b8e..2847fa9b9ee5 100644 --- a/gas/testsuite/gas/d10v/address-017.l +++ b/gas/testsuite/gas/d10v/address-017.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld r0 diff --git a/gas/testsuite/gas/d10v/address-018.l b/gas/testsuite/gas/d10v/address-018.l index 2f8c4f596b8e..688385e4d196 100644 --- a/gas/testsuite/gas/d10v/address-018.l +++ b/gas/testsuite/gas/d10v/address-018.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld2w r0 diff --git a/gas/testsuite/gas/d10v/address-019.l b/gas/testsuite/gas/d10v/address-019.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-019.l +++ b/gas/testsuite/gas/d10v/address-019.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-020.l b/gas/testsuite/gas/d10v/address-020.l index 2f8c4f596b8e..edf420d15df6 100644 --- a/gas/testsuite/gas/d10v/address-020.l +++ b/gas/testsuite/gas/d10v/address-020.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st r0 diff --git a/gas/testsuite/gas/d10v/address-021.l b/gas/testsuite/gas/d10v/address-021.l index 2f8c4f596b8e..49f87bbc3ec2 100644 --- a/gas/testsuite/gas/d10v/address-021.l +++ b/gas/testsuite/gas/d10v/address-021.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st2w r0 diff --git a/gas/testsuite/gas/d10v/address-022.l b/gas/testsuite/gas/d10v/address-022.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-022.l +++ b/gas/testsuite/gas/d10v/address-022.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-023.l b/gas/testsuite/gas/d10v/address-023.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-023.l +++ b/gas/testsuite/gas/d10v/address-023.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-024.l b/gas/testsuite/gas/d10v/address-024.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-024.l +++ b/gas/testsuite/gas/d10v/address-024.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-025.l b/gas/testsuite/gas/d10v/address-025.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-025.l +++ b/gas/testsuite/gas/d10v/address-025.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-026.l b/gas/testsuite/gas/d10v/address-026.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-026.l +++ b/gas/testsuite/gas/d10v/address-026.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-027.l b/gas/testsuite/gas/d10v/address-027.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-027.l +++ b/gas/testsuite/gas/d10v/address-027.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-030.l b/gas/testsuite/gas/d10v/address-030.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-030.l +++ b/gas/testsuite/gas/d10v/address-030.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-031.l b/gas/testsuite/gas/d10v/address-031.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-031.l +++ b/gas/testsuite/gas/d10v/address-031.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-032.l b/gas/testsuite/gas/d10v/address-032.l index 2f8c4f596b8e..2847fa9b9ee5 100644 --- a/gas/testsuite/gas/d10v/address-032.l +++ b/gas/testsuite/gas/d10v/address-032.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld r0 diff --git a/gas/testsuite/gas/d10v/address-033.l b/gas/testsuite/gas/d10v/address-033.l index 2f8c4f596b8e..688385e4d196 100644 --- a/gas/testsuite/gas/d10v/address-033.l +++ b/gas/testsuite/gas/d10v/address-033.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld2w r0 diff --git a/gas/testsuite/gas/d10v/address-034.l b/gas/testsuite/gas/d10v/address-034.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-034.l +++ b/gas/testsuite/gas/d10v/address-034.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/address-035.l b/gas/testsuite/gas/d10v/address-035.l index 2f8c4f596b8e..edf420d15df6 100644 --- a/gas/testsuite/gas/d10v/address-035.l +++ b/gas/testsuite/gas/d10v/address-035.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st r0 diff --git a/gas/testsuite/gas/d10v/address-036.l b/gas/testsuite/gas/d10v/address-036.l index 2f8c4f596b8e..49f87bbc3ec2 100644 --- a/gas/testsuite/gas/d10v/address-036.l +++ b/gas/testsuite/gas/d10v/address-036.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: st2w r0 diff --git a/gas/testsuite/gas/d10v/address-037.l b/gas/testsuite/gas/d10v/address-037.l index 2f8c4f596b8e..1ad93db858b5 100644 --- a/gas/testsuite/gas/d10v/address-037.l +++ b/gas/testsuite/gas/d10v/address-037.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldb r0 diff --git a/gas/testsuite/gas/d10v/address-038.l b/gas/testsuite/gas/d10v/address-038.l index 2f8c4f596b8e..72cff1d71ff1 100644 --- a/gas/testsuite/gas/d10v/address-038.l +++ b/gas/testsuite/gas/d10v/address-038.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ldub r0 diff --git a/gas/testsuite/gas/d10v/address-039.l b/gas/testsuite/gas/d10v/address-039.l index 2f8c4f596b8e..2847fa9b9ee5 100644 --- a/gas/testsuite/gas/d10v/address-039.l +++ b/gas/testsuite/gas/d10v/address-039.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld r0 diff --git a/gas/testsuite/gas/d10v/address-040.l b/gas/testsuite/gas/d10v/address-040.l index 2f8c4f596b8e..688385e4d196 100644 --- a/gas/testsuite/gas/d10v/address-040.l +++ b/gas/testsuite/gas/d10v/address-040.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: ld2w r0 diff --git a/gas/testsuite/gas/d10v/address-041.l b/gas/testsuite/gas/d10v/address-041.l index 2f8c4f596b8e..a41162138632 100644 --- a/gas/testsuite/gas/d10v/address-041.l +++ b/gas/testsuite/gas/d10v/address-041.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: bad opcode or operands -.*:6: Fatal error: can't find opcode +.*:6: Error: could not assemble: stb r0 diff --git a/gas/testsuite/gas/d10v/d10v.exp b/gas/testsuite/gas/d10v/d10v.exp index 6169ecf1aa63..0b152b016a15 100644 --- a/gas/testsuite/gas/d10v/d10v.exp +++ b/gas/testsuite/gas/d10v/d10v.exp @@ -1,19 +1,6 @@ # # Driver for D10V assembler testsuite # -proc run_list_test { name opts } { - global srcdir subdir - set testname "D10V $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if {[regexp_diff "dump.out" "${file}.l"] } { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if {[istarget d10v-*-*]} { run_dump_test "inst" run_dump_test "address-001" diff --git a/gas/testsuite/gas/d30v/d30.exp b/gas/testsuite/gas/d30v/d30.exp index 275b0e06df1d..d06f6066c636 100644 --- a/gas/testsuite/gas/d30v/d30.exp +++ b/gas/testsuite/gas/d30v/d30.exp @@ -2,19 +2,6 @@ # D30V assembler tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "D30V $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if {[regexp_diff "dump.out" "${file}.l"] } { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if {[istarget d30v-*-*]} { run_dump_test "inst" run_dump_test "align" diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index 43265d0d2fae..227b77ef472e 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -2,7 +2,7 @@ # elf tests # -proc run_list_test { name suffix opts readelf_opts readelf_pipe } { +proc run_elf_list_test { name suffix opts readelf_opts readelf_pipe } { global READELF global srcdir subdir set testname "elf $name list" @@ -50,11 +50,21 @@ if { ([istarget "*-*-*elf*"] if {[istarget m32r*-*-*]} then { set target_machine -m32r } + if {[istarget "score-*-*"]} then { + set target_machine -score + } + if {[istarget "xtensa-*-*"]} then { + set target_machine -xtensa + } if { ([istarget "*arm*-*-*"] - || [istarget "xscale*-*-*"]) - && ([istarget "*-*-*eabi"] - || [istarget "*-*-symbianelf"])} then { - set target_machine -armeabi + || [istarget "xscale*-*-*"]) } { + + if { ([istarget "*-*-*eabi"] + || [istarget "*-*-symbianelf"])} then { + set target_machine -armeabi + } else { + set target_machine -armelf + } } run_dump_test "ehopt0" run_dump_test "group0a" @@ -68,16 +78,22 @@ if { ([istarget "*-*-*elf*"] { mips*-*-* } { } { *c54x*-*-* } { } default { + # The next test can fail if the target does not convert fixups + # against ordinary symbols into relocations against section symbols. + # This is usually revealed by the error message: + # symbol `sym' required but not present + setup_xfail "h8300-*-*" "mn10300-*-*" run_dump_test redef + run_dump_test equ-reloc } } run_dump_test "section0" run_dump_test "section1" - run_list_test "section2" "$target_machine" "-al" "-s" "" + run_elf_list_test "section2" "$target_machine" "-al" "-s" "" run_dump_test "section3" run_dump_test "section4" - run_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\"" + run_elf_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\"" run_dump_test "struct" run_dump_test "symver" - run_list_test "type" "" "" "-s" "| grep \"1 \\\[FONT\\\]\"" + run_elf_list_test "type" "" "" "-s" "| grep \"1 \\\[FONT\\\]\"" } diff --git a/gas/testsuite/gas/elf/equ-reloc.d b/gas/testsuite/gas/elf/equ-reloc.d new file mode 100644 index 000000000000..e4e7d47f47a9 --- /dev/null +++ b/gas/testsuite/gas/elf/equ-reloc.d @@ -0,0 +1,13 @@ +#objdump: -rsj .data +#name: elf equate relocs + +.*: +file format .* + +RELOCATION RECORDS FOR \[.*\]: +OFFSET *TYPE *VALUE +0*0 [^ ]+ +(\.bss(\+0x0*4)?|y1) +0*4 [^ ]+ +(\.bss(\+0x0*8)?|y2) +#... +Contents of section .data: + 0000 0[04]00000[04] 0[08]00000[08].* +#pass diff --git a/gas/testsuite/gas/elf/equ-reloc.s b/gas/testsuite/gas/elf/equ-reloc.s new file mode 100644 index 000000000000..efdd0e1b8ab5 --- /dev/null +++ b/gas/testsuite/gas/elf/equ-reloc.s @@ -0,0 +1,16 @@ + .data + .long x1, x2 + + .global x1, x2, z2 + + .set x1, y1 + .set x2, y2 + .set x2, z2 + + .section .bss, "aw", %nobits +x1: + .zero 4 +y1: + .zero 4 +y2: + .zero 4 diff --git a/gas/testsuite/gas/elf/section2.e-armeabi b/gas/testsuite/gas/elf/section2.e-armeabi index 84463b1f8b2b..44ecffc37768 100644 --- a/gas/testsuite/gas/elf/section2.e-armeabi +++ b/gas/testsuite/gas/elf/section2.e-armeabi @@ -1,9 +1,10 @@ -Symbol table '.symtab' contains 6 entries: +Symbol table '.symtab' contains 7 entries: Num: Value[ ]* Size Type Bind Vis Ndx Name 0: 0+0 0 NOTYPE LOCAL DEFAULT UND 1: 0+0 0 SECTION LOCAL DEFAULT 1 2: 0+0 0 SECTION LOCAL DEFAULT 2 3: 0+0 0 SECTION LOCAL DEFAULT 3 4: 0+0 0 SECTION LOCAL DEFAULT 4 - 5: 0+0 0 SECTION LOCAL DEFAULT 5 + 5: 0+0 0 NOTYPE LOCAL DEFAULT 4 \$d + 6: 0+0 0 SECTION LOCAL DEFAULT 5 diff --git a/gas/testsuite/gas/elf/section2.e-armelf b/gas/testsuite/gas/elf/section2.e-armelf new file mode 100644 index 000000000000..8d2e4ff6a758 --- /dev/null +++ b/gas/testsuite/gas/elf/section2.e-armelf @@ -0,0 +1,9 @@ + +Symbol table '.symtab' contains 6 entries: + Num: Value[ ]* Size Type Bind Vis Ndx Name + 0: 0+0 0 NOTYPE LOCAL DEFAULT UND + 1: 0+0 0 SECTION LOCAL DEFAULT 1 + 2: 0+0 0 SECTION LOCAL DEFAULT 2 + 3: 0+0 0 SECTION LOCAL DEFAULT 3 + 4: 0+0 0 SECTION LOCAL DEFAULT 4 + 5: 0+0 0 NOTYPE LOCAL DEFAULT 4 \$d diff --git a/gas/testsuite/gas/elf/section2.e-score b/gas/testsuite/gas/elf/section2.e-score new file mode 100644 index 000000000000..6f30cbaa16e4 --- /dev/null +++ b/gas/testsuite/gas/elf/section2.e-score @@ -0,0 +1,9 @@ + +Symbol table '.symtab' contains 6 entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND + 1: 00000000 0 SECTION LOCAL DEFAULT 1 + 2: 00000000 0 SECTION LOCAL DEFAULT 2 + 3: 00000000 0 SECTION LOCAL DEFAULT 3 + 4: 00000000 0 SECTION LOCAL DEFAULT 5 + 5: 00000000 0 SECTION LOCAL DEFAULT 4 diff --git a/gas/testsuite/gas/elf/section2.e-xtensa b/gas/testsuite/gas/elf/section2.e-xtensa new file mode 100644 index 000000000000..84463b1f8b2b --- /dev/null +++ b/gas/testsuite/gas/elf/section2.e-xtensa @@ -0,0 +1,9 @@ + +Symbol table '.symtab' contains 6 entries: + Num: Value[ ]* Size Type Bind Vis Ndx Name + 0: 0+0 0 NOTYPE LOCAL DEFAULT UND + 1: 0+0 0 SECTION LOCAL DEFAULT 1 + 2: 0+0 0 SECTION LOCAL DEFAULT 2 + 3: 0+0 0 SECTION LOCAL DEFAULT 3 + 4: 0+0 0 SECTION LOCAL DEFAULT 4 + 5: 0+0 0 SECTION LOCAL DEFAULT 5 diff --git a/gas/testsuite/gas/frv/allinsn.exp b/gas/testsuite/gas/frv/allinsn.exp index ed29d20893b3..b6950aeb614c 100644 --- a/gas/testsuite/gas/frv/allinsn.exp +++ b/gas/testsuite/gas/frv/allinsn.exp @@ -1,31 +1,19 @@ # FRV assembler testsuite. -proc run_list_test { name opts } { - global srcdir subdir - set testname "$name error test ($opts)" - gas_run $name.s $opts >&dump.out - if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} { - fail $testname - verbose "output is [file_contents dump.out]" 2 - return - } - pass $testname -} - if [istarget frv*-*-*] { run_dump_test "allinsn" run_dump_test "fdpic" run_dump_test "reloc1" run_dump_test "fr405-insn" - run_list_test "fr405-insn" "-mcpu=fr400" - run_list_test "fr405-insn" "-mcpu=fr500" + run_list_test "fr405-insn" "-mcpu=fr400" "fr405-insn -mcpu=fr400" + run_list_test "fr405-insn" "-mcpu=fr500" "fr405-insn -mcpu=fr500" run_dump_test "fr450-spr" run_dump_test "fr450-insn" - run_list_test "fr450-insn" "-mcpu=fr405" - run_list_test "fr450-insn" "-mcpu=fr400" - run_list_test "fr450-insn" "-mcpu=fr500" + run_list_test "fr450-insn" "-mcpu=fr405" "fr450-insn -mcpu=fr405" + run_list_test "fr450-insn" "-mcpu=fr400" "fr450-insn -mcpu=fr400" + run_list_test "fr450-insn" "-mcpu=fr500" "fr450-insn -mcpu=fr500" run_list_test "fr450-media-issue" "-mcpu=fr450" run_dump_test "fr550-pack1" diff --git a/gas/testsuite/gas/i386/addr16.d b/gas/testsuite/gas/i386/addr16.d new file mode 100644 index 000000000000..910d72570fcf --- /dev/null +++ b/gas/testsuite/gas/i386/addr16.d @@ -0,0 +1,15 @@ +#objdump: -drw +#name: i386 16-bit addressing in 32-bit mode. + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+67 a0 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%al +[ ]*4:[ ]+67 66 a1 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%ax +[ ]*9:[ ]+67 a1 98 08 [ ]+addr16[ ]+mov[ ]+0x898,%eax +[ ]*d:[ ]+67 a2 98 08 [ ]+addr16[ ]+mov[ ]+%al,0x898 +[ ]*11:[ ]+67 66 a3 98 08 [ ]+addr16[ ]+mov[ ]+%ax,0x898 +[ ]*16:[ ]+67 a3 98 08[ ]+addr16[ ]+mov[ ]+%eax,0x898 +#pass diff --git a/gas/testsuite/gas/i386/addr16.s b/gas/testsuite/gas/i386/addr16.s new file mode 100644 index 000000000000..b1510e798510 --- /dev/null +++ b/gas/testsuite/gas/i386/addr16.s @@ -0,0 +1,7 @@ + .text + addr16 mov 0x0898,%al + addr16 mov 0x0898,%ax + addr16 mov 0x0898,%eax + addr16 mov %al,0x0898 + addr16 mov %ax,0x0898 + addr16 mov %eax,0x0898 diff --git a/gas/testsuite/gas/i386/addr32.d b/gas/testsuite/gas/i386/addr32.d new file mode 100644 index 000000000000..5866a30c7927 --- /dev/null +++ b/gas/testsuite/gas/i386/addr32.d @@ -0,0 +1,15 @@ +#objdump: -drw -mi8086 +#name: i386 32-bit addressing in 16-bit mode. + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%al +[ ]*6:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%ax +[ ]*c:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%eax +[ ]*13:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+%al,0x600898 +[ ]*19:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898 +[ ]*1f:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898 +#pass diff --git a/gas/testsuite/gas/i386/addr32.s b/gas/testsuite/gas/i386/addr32.s new file mode 100644 index 000000000000..3dab339dc256 --- /dev/null +++ b/gas/testsuite/gas/i386/addr32.s @@ -0,0 +1,8 @@ + .text + .code16 + addr32 mov 0x600898,%al + addr32 mov 0x600898,%ax + addr32 mov 0x600898,%eax + addr32 mov %al,0x600898 + addr32 mov %ax,0x600898 + addr32 mov %eax,0x600898 diff --git a/gas/testsuite/gas/i386/amd.d b/gas/testsuite/gas/i386/amd.d index 1ff16792f19f..8009260e50a1 100644 --- a/gas/testsuite/gas/i386/amd.d +++ b/gas/testsuite/gas/i386/amd.d @@ -17,7 +17,7 @@ Disassembly of section .text: 27: 0f 0f ae 90 90 00 00 90 [ ]*pfcmpge 0x9090\(%esi\),%mm5 2f: 0f 0f 74 75 00 a0 [ ]*pfcmpgt 0x0\(%ebp,%esi,2\),%mm6 35: 0f 0f 7c 75 02 a4 [ ]*pfmax 0x2\(%ebp,%esi,2\),%mm7 - 3b: 0f 0f 84 75 90 90 90 90 94 [ ]*pfmin 0x90909090\(%ebp,%esi,2\),%mm0 + 3b: 0f 0f 84 75 90 90 90 90 94 [ ]*pfmin -0x6f6f6f70\(%ebp,%esi,2\),%mm0 44: 0f 0f 0d 04 00 00 00 b4 [ ]*pfmul 0x4,%mm1 4c: 2e 0f 0f 54 c3 07 96 [ ]*pfrcp %cs:0x7\(%ebx,%eax,8\),%mm2 53: 0f 0f d8 a6 [ ]*pfrcpit1 %mm0,%mm3 @@ -27,7 +27,7 @@ Disassembly of section .text: 63: 0f 0f fc 9a [ ]*pfsub %mm4,%mm7 67: 0f 0f c5 aa [ ]*pfsubr %mm5,%mm0 6b: 0f 0f ce 0d [ ]*pi2fd %mm6,%mm1 - 6f: 0f 0f d7 b7 [ ]*pfmulhrw %mm7,%mm2 + 6f: 0f 0f d7 b7 [ ]*pmulhrw %mm7,%mm2 73: 2e 0f [ ]*\(bad\) 75: 0f 54 c3 [ ]*andps %xmm3,%xmm0 78: 07 [ ]*pop %es diff --git a/gas/testsuite/gas/i386/amdfam10.d b/gas/testsuite/gas/i386/amdfam10.d new file mode 100644 index 000000000000..ba63e49bfd1b --- /dev/null +++ b/gas/testsuite/gas/i386/amdfam10.d @@ -0,0 +1,23 @@ +#objdump: -dw +#name: i386 amdfam10 + +.*: +file format .* + +Disassembly of section .text: + +0+000 <foo>: + 0: f3 0f bd 19[ ]+lzcnt \(%ecx\),%ebx + 4: 66 f3 0f bd 19[ ]+lzcnt \(%ecx\),%bx + 9: f3 0f bd d9[ ]+lzcnt %ecx,%ebx + d: 66 f3 0f bd d9[ ]+lzcnt %cx,%bx + 12: f3 0f b8 19[ ]+popcnt \(%ecx\),%ebx + 16: 66 f3 0f b8 19[ ]+popcnt \(%ecx\),%bx + 1b: f3 0f b8 d9[ ]+popcnt %ecx,%ebx + 1f: 66 f3 0f b8 d9[ ]+popcnt %cx,%bx + 24: 66 0f 79 ca[ ]+extrq %xmm2,%xmm1 + 28: 66 0f 78 c1 02 04[ ]*extrq \$0x4,\$0x2,%xmm1 + 2e: f2 0f 79 ca[ ]+insertq %xmm2,%xmm1 + 32: f2 0f 78 ca 02 04[ ]*insertq \$0x4,\$0x2,%xmm2,%xmm1 + 38: f2 0f 2b 09[ ]+movntsd %xmm1,\(%ecx\) + 3c: f3 0f 2b 09[ ]+movntss %xmm1,\(%ecx\) + diff --git a/gas/testsuite/gas/i386/amdfam10.s b/gas/testsuite/gas/i386/amdfam10.s new file mode 100644 index 000000000000..bef51fee2f38 --- /dev/null +++ b/gas/testsuite/gas/i386/amdfam10.s @@ -0,0 +1,21 @@ +#AMDFAM10 New Instructions + + .text +foo: + lzcnt (%ecx),%ebx + lzcnt (%ecx),%bx + lzcnt %ecx,%ebx + lzcnt %cx,%bx + popcnt (%ecx),%ebx + popcnt (%ecx),%bx + popcnt %ecx,%ebx + popcnt %cx,%bx + extrq %xmm2,%xmm1 + extrq $4,$2,%xmm1 + insertq %xmm2,%xmm1 + insertq $4,$2,%xmm2,%xmm1 + movntsd %xmm1,(%ecx) + movntss %xmm1,(%ecx) + + # Force a good alignment. + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/crc32-intel.d b/gas/testsuite/gas/i386/crc32-intel.d new file mode 100644 index 000000000000..705f6b809838 --- /dev/null +++ b/gas/testsuite/gas/i386/crc32-intel.d @@ -0,0 +1,25 @@ +#objdump: -dwMintel +#name: i386 crc32 (Intel disassembly) +#source: crc32.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32 eax,BYTE PTR \[esi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32 eax,WORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32 eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32 eax,BYTE PTR \[esi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32 eax,WORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32 eax,DWORD PTR \[esi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +#pass diff --git a/gas/testsuite/gas/i386/crc32.d b/gas/testsuite/gas/i386/crc32.d new file mode 100644 index 000000000000..a398a75f9a69 --- /dev/null +++ b/gas/testsuite/gas/i386/crc32.d @@ -0,0 +1,24 @@ +#objdump: -dw +#name: i386 crc32 + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%esi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%esi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +#pass diff --git a/gas/testsuite/gas/i386/crc32.s b/gas/testsuite/gas/i386/crc32.s new file mode 100644 index 000000000000..edcfe1c4c0c8 --- /dev/null +++ b/gas/testsuite/gas/i386/crc32.s @@ -0,0 +1,24 @@ +# Check crc32 in SSE4.2 + + .text +foo: + +crc32b (%esi), %eax +crc32w (%esi), %eax +crc32l (%esi), %eax +crc32 %al, %eax +crc32b %al, %eax +crc32 %ax, %eax +crc32w %ax, %eax +crc32 %eax, %eax +crc32l %eax, %eax + +.intel_syntax noprefix +crc32 eax,byte ptr [esi] +crc32 eax, word ptr [esi] +crc32 eax,dword ptr [esi] +crc32 eax,al +crc32 eax, ax +crc32 eax,eax + +.p2align 4,0 diff --git a/gas/testsuite/gas/i386/fp.d b/gas/testsuite/gas/i386/fp.d new file mode 100644 index 000000000000..21838e262bc2 --- /dev/null +++ b/gas/testsuite/gas/i386/fp.d @@ -0,0 +1,8 @@ +#objdump: -s -j .data +#name: i386 fp + +.*: file format .* + +Contents of section .data: + 0000 00881bcd 4b789ad4 004071a3 79094f93 ....Kx...@q.y.O. + 0010 0a40789a 5440789a 54400000 00000000 .@x.T@x.T@...... diff --git a/gas/testsuite/gas/i386/fp.s b/gas/testsuite/gas/i386/fp.s new file mode 100644 index 000000000000..4187d4e55c31 --- /dev/null +++ b/gas/testsuite/gas/i386/fp.s @@ -0,0 +1,13 @@ + .data +# .tfloat is 80-bit floating point format. + .tfloat 3.32192809488736218171e0 +# .byte 0x0, 0x88, 0x1b, 0xcd, 0x4b, 0x78, 0x9a, 0xd4, 0x0, 0x40 +# .double is 64-bit floating point format. + .double 3.32192809488736218171e0 +# .byte 0x71, 0xa3, 0x79, 0x09, 0x4f, 0x93, 0x0a, 0x40 +# The next two are 32-bit floating point format. + .float 3.32192809488736218171e0 +# .byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0 + .single 3.32192809488736218171e0 +# .byte 0x78, 0x9a, 0x54, 0x40, 0, 0, 0, 0 + .byte 0, 0, 0, 0, 0, 0 diff --git a/gas/testsuite/gas/i386/gotpc.d b/gas/testsuite/gas/i386/gotpc.d index 499e831c1b45..ef79cbd78322 100644 --- a/gas/testsuite/gas/i386/gotpc.d +++ b/gas/testsuite/gas/i386/gotpc.d @@ -49,4 +49,6 @@ Disassembly of section .text: e0: e0 00 [ ]*loopne e2 <test\+0xe2> e0: (R_386_)?GOTPC _GLOBAL_OFFSET_TABLE_ e2: 00 00 [ ]*add %al,\(%eax\) e4: 00 00 [ ]*add %al,\(%eax\) e4: (R_386_)?GOTOFF _GLOBAL_OFFSET_TABLE_ - ... + e6: 00 00 [ ]*add %al,\(%eax\) + e8: 8b 83 00 00 00 00 [ ]*mov 0x0\(%ebx\),%eax ea: (R_386_)?GOTOFF _GLOBAL_OFFSET_TABLE_ +#pass diff --git a/gas/testsuite/gas/i386/gotpc.s b/gas/testsuite/gas/i386/gotpc.s index 5787b8e8f88c..fc771f6cff55 100644 --- a/gas/testsuite/gas/i386/gotpc.s +++ b/gas/testsuite/gas/i386/gotpc.s @@ -38,3 +38,4 @@ test: movl _GLOBAL_OFFSET_TABLE_@GOTOFF(%ebx), %ebx .long _GLOBAL_OFFSET_TABLE_+[.-test] .long _GLOBAL_OFFSET_TABLE_@GOTOFF + movl _GLOBAL_OFFSET_TABLE_@GOTOFF (%ebx), %eax diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index a12bc91fb210..8f0437c47381 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -1,19 +1,6 @@ # # i386 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "i386 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - proc gas_64_check { } { global NM global NMFLAGS @@ -46,6 +33,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_list_test "modrm" "-al --listing-lhs-width=2" run_dump_test "naked" run_dump_test "opcode" + run_dump_test "opcode-intel" + run_dump_test "opcode-suffix" run_dump_test "intel" run_dump_test "intel16" run_list_test "intelbad" "" @@ -68,9 +57,29 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "crx" run_list_test "cr-err" "" run_dump_test "svme" + run_dump_test "amdfam10" run_dump_test "merom" run_dump_test "rep" run_dump_test "rep-suffix" + run_dump_test "fp" + run_dump_test "nops" + run_dump_test "nops-1" + run_dump_test "nops-1-i386" + run_dump_test "nops-1-i686" + run_dump_test "nops-1-merom" + run_dump_test "nops-2" + run_dump_test "nops-2-i386" + run_dump_test "nops-2-merom" + run_dump_test "nops-3" + run_dump_test "addr16" + run_dump_test "addr32" + run_dump_test "sse4_1" + run_dump_test "sse4_2" + run_dump_test "crc32" + run_dump_test "crc32-intel" + run_list_test "inval-crc32" "-al" + run_dump_test "simd" + run_dump_test "simd-intel" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -121,9 +130,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86_64" run_dump_test "x86-64-addr32" + run_dump_test "x86-64-addr32-intel" run_dump_test "x86-64-opcode" run_dump_test "x86-64-pcrel" run_dump_test "x86-64-rip" + run_dump_test "x86-64-rip-intel" run_dump_test "x86-64-stack" run_dump_test "x86-64-stack-intel" run_dump_test "x86-64-stack-suffix" @@ -132,6 +143,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_list_test "x86-64-inval-seg" "-al" run_dump_test "x86-64-branch" run_dump_test "svme64" + run_dump_test "x86-64-amdfam10" run_dump_test "x86-64-vmx" run_dump_test "immed64" run_dump_test "x86-64-prescott" @@ -142,6 +154,26 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-merom" run_dump_test "x86-64-rep" run_dump_test "x86-64-rep-suffix" + run_dump_test "x86-64-cbw" + run_dump_test "x86-64-cbw-intel" + run_dump_test "x86-64-io" + run_dump_test "x86-64-io-intel" + run_dump_test "x86-64-io-suffix" + run_dump_test "x86-64-gidt" + run_dump_test "x86-64-nops" + if ![istarget "x86_64-*-mingw*"] then { + run_dump_test "x86-64-nops-1" + } + run_dump_test "x86-64-nops-1-k8" + run_dump_test "x86-64-nops-1-nocona" + run_dump_test "x86-64-nops-1-merom" + run_dump_test "x86-64-sse4_1" + run_dump_test "x86-64-sse4_2" + run_dump_test "x86-64-crc32" + run_dump_test "x86-64-crc32-intel" + run_list_test "x86-64-inval-crc32" "-al" + run_dump_test "x86-64-simd" + run_dump_test "x86-64-simd-intel" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/immed32.d b/gas/testsuite/gas/i386/immed32.d index 3d308a833b4a..d22538fb4fb5 100644 --- a/gas/testsuite/gas/i386/immed32.d +++ b/gas/testsuite/gas/i386/immed32.d @@ -9,9 +9,9 @@ Disassembly of section \.text: [ ]*[0-9a-fA-F]+:[ ]+ff 50 04[ ]+calll? +\*0x4\(%eax\) [ ]*[0-9a-fA-F]+:[ ]+ff 90 08 00 00 00[ ]+calll? +\*0x8\(%eax\) [ ]*[0-9a-fA-F]+:[ ]+ff 90 00 00 00 00[ ]+calll? +\*0x0\(%eax\) -[ ]*[0-9a-fA-F]+:[ ]+67 ff 57 04[ ]+(addr16 )?calll? +\*4\(%bx\) -[ ]*[0-9a-fA-F]+:[ ]+67 ff 97 08 00[ ]+(addr16 )?calll? +\*8\(%bx\) -[ ]*[0-9a-fA-F]+:[ ]+67 ff 97 00 00[ ]+(addr16 )?calll? +\*0\(%bx\) +[ ]*[0-9a-fA-F]+:[ ]+67 ff 57 04[ ]+(addr16 )?calll? +\*0x4\(%bx\) +[ ]*[0-9a-fA-F]+:[ ]+67 ff 97 08 00[ ]+(addr16 )?calll? +\*0x8\(%bx\) +[ ]*[0-9a-fA-F]+:[ ]+67 ff 97 00 00[ ]+(addr16 )?calll? +\*0x0\(%bx\) [ ]*[0-9a-fA-F]+:[ ]+b0 04[ ]+movb? +\$0x4,%al [ ]*[0-9a-fA-F]+:[ ]+b0 08[ ]+movb? +\$0x8,%al [ ]*[0-9a-fA-F]+:[ ]+b0 00[ ]+movb? +\$0x0,%al diff --git a/gas/testsuite/gas/i386/immed64.d b/gas/testsuite/gas/i386/immed64.d index c2ab3248b7d6..667680675a58 100644 --- a/gas/testsuite/gas/i386/immed64.d +++ b/gas/testsuite/gas/i386/immed64.d @@ -57,3 +57,4 @@ Disassembly of section \.text: [ ]*[0-9a-fA-F]+:[ ]+e5 04[ ]+inl? +\$0x4,%eax [ ]*[0-9a-fA-F]+:[ ]+e5 08[ ]+inl? +\$0x8,%eax [ ]*[0-9a-fA-F]+:[ ]+e5 00[ ]+inl? +\$0x0,%eax +#pass diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d index 02b1a0a197f5..f8a96dfd7327 100644 --- a/gas/testsuite/gas/i386/intel.d +++ b/gas/testsuite/gas/i386/intel.d @@ -8,62 +8,62 @@ Disassembly of section .text: 0+000 <foo>: - 0: 00 90 90 90 90 90 [ ]*add %dl,0x90909090\(%eax\) - 6: 01 90 90 90 90 90 [ ]*add %edx,0x90909090\(%eax\) - c: 02 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%dl - 12: 03 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%edx + 0: 00 90 90 90 90 90 [ ]*add %dl,-0x6f6f6f70\(%eax\) + 6: 01 90 90 90 90 90 [ ]*add %edx,-0x6f6f6f70\(%eax\) + c: 02 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%dl + 12: 03 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%edx 18: 04 90 [ ]*add \$0x90,%al 1a: 05 90 90 90 90 [ ]*add \$0x90909090,%eax 1f: 06 [ ]*push %es 20: 07 [ ]*pop %es - 21: 08 90 90 90 90 90 [ ]*or %dl,0x90909090\(%eax\) - 27: 09 90 90 90 90 90 [ ]*or %edx,0x90909090\(%eax\) - 2d: 0a 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%dl - 33: 0b 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%edx + 21: 08 90 90 90 90 90 [ ]*or %dl,-0x6f6f6f70\(%eax\) + 27: 09 90 90 90 90 90 [ ]*or %edx,-0x6f6f6f70\(%eax\) + 2d: 0a 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%dl + 33: 0b 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%edx 39: 0c 90 [ ]*or \$0x90,%al 3b: 0d 90 90 90 90 [ ]*or \$0x90909090,%eax 40: 0e [ ]*push %cs - 41: 10 90 90 90 90 90 [ ]*adc %dl,0x90909090\(%eax\) - 47: 11 90 90 90 90 90 [ ]*adc %edx,0x90909090\(%eax\) - 4d: 12 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%dl - 53: 13 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%edx + 41: 10 90 90 90 90 90 [ ]*adc %dl,-0x6f6f6f70\(%eax\) + 47: 11 90 90 90 90 90 [ ]*adc %edx,-0x6f6f6f70\(%eax\) + 4d: 12 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%dl + 53: 13 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%edx 59: 14 90 [ ]*adc \$0x90,%al 5b: 15 90 90 90 90 [ ]*adc \$0x90909090,%eax 60: 16 [ ]*push %ss 61: 17 [ ]*pop %ss - 62: 18 90 90 90 90 90 [ ]*sbb %dl,0x90909090\(%eax\) - 68: 19 90 90 90 90 90 [ ]*sbb %edx,0x90909090\(%eax\) - 6e: 1a 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%dl - 74: 1b 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%edx + 62: 18 90 90 90 90 90 [ ]*sbb %dl,-0x6f6f6f70\(%eax\) + 68: 19 90 90 90 90 90 [ ]*sbb %edx,-0x6f6f6f70\(%eax\) + 6e: 1a 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%dl + 74: 1b 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%edx 7a: 1c 90 [ ]*sbb \$0x90,%al 7c: 1d 90 90 90 90 [ ]*sbb \$0x90909090,%eax 81: 1e [ ]*push %ds 82: 1f [ ]*pop %ds - 83: 20 90 90 90 90 90 [ ]*and %dl,0x90909090\(%eax\) - 89: 21 90 90 90 90 90 [ ]*and %edx,0x90909090\(%eax\) - 8f: 22 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%dl - 95: 23 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%edx + 83: 20 90 90 90 90 90 [ ]*and %dl,-0x6f6f6f70\(%eax\) + 89: 21 90 90 90 90 90 [ ]*and %edx,-0x6f6f6f70\(%eax\) + 8f: 22 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%dl + 95: 23 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%edx 9b: 24 90 [ ]*and \$0x90,%al 9d: 25 90 90 90 90 [ ]*and \$0x90909090,%eax a2: 27 [ ]*daa - a3: 28 90 90 90 90 90 [ ]*sub %dl,0x90909090\(%eax\) - a9: 29 90 90 90 90 90 [ ]*sub %edx,0x90909090\(%eax\) - af: 2a 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%dl - b5: 2b 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%edx + a3: 28 90 90 90 90 90 [ ]*sub %dl,-0x6f6f6f70\(%eax\) + a9: 29 90 90 90 90 90 [ ]*sub %edx,-0x6f6f6f70\(%eax\) + af: 2a 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%dl + b5: 2b 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%edx bb: 2c 90 [ ]*sub \$0x90,%al bd: 2d 90 90 90 90 [ ]*sub \$0x90909090,%eax c2: 2f [ ]*das - c3: 30 90 90 90 90 90 [ ]*xor %dl,0x90909090\(%eax\) - c9: 31 90 90 90 90 90 [ ]*xor %edx,0x90909090\(%eax\) - cf: 32 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%dl - d5: 33 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%edx + c3: 30 90 90 90 90 90 [ ]*xor %dl,-0x6f6f6f70\(%eax\) + c9: 31 90 90 90 90 90 [ ]*xor %edx,-0x6f6f6f70\(%eax\) + cf: 32 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%dl + d5: 33 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%edx db: 34 90 [ ]*xor \$0x90,%al dd: 35 90 90 90 90 [ ]*xor \$0x90909090,%eax e2: 37 [ ]*aaa - e3: 38 90 90 90 90 90 [ ]*cmp %dl,0x90909090\(%eax\) - e9: 39 90 90 90 90 90 [ ]*cmp %edx,0x90909090\(%eax\) - ef: 3a 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%dl - f5: 3b 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%edx + e3: 38 90 90 90 90 90 [ ]*cmp %dl,-0x6f6f6f70\(%eax\) + e9: 39 90 90 90 90 90 [ ]*cmp %edx,-0x6f6f6f70\(%eax\) + ef: 3a 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%dl + f5: 3b 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%edx fb: 3c 90 [ ]*cmp \$0x90,%al fd: 3d 90 90 90 90 [ ]*cmp \$0x90909090,%eax 102: 3f [ ]*aas @@ -101,12 +101,12 @@ Disassembly of section .text: 122: 5f [ ]*pop %edi 123: 60 [ ]*pusha 124: 61 [ ]*popa - 125: 62 90 90 90 90 90 [ ]*bound %edx,0x90909090\(%eax\) - 12b: 63 90 90 90 90 90 [ ]*arpl %dx,0x90909090\(%eax\) + 125: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\) + 12b: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\) 131: 68 90 90 90 90 [ ]*push \$0x90909090 - 136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,0x90909090\(%eax\),%edx + 136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx 140: 6a 90 [ ]*push \$0xffffff90 - 142: 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,0x90909090\(%eax\),%edx + 142: 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,-0x6f6f6f70\(%eax\),%edx 149: 6c [ ]*insb \(%dx\),%es:\(%edi\) 14a: 6d [ ]*insl \(%dx\),%es:\(%edi\) 14b: 6e [ ]*outsb %ds:\(%esi\),\(%dx\) @@ -127,21 +127,21 @@ Disassembly of section .text: 167: 7d 90 [ ]*jge (0x)?f9.* 169: 7e 90 [ ]*jle (0x)?fb.* 16b: 7f 90 [ ]*jg (0x)?fd.* - 16d: 80 90 90 90 90 90 90 [ ]*adcb \$0x90,0x90909090\(%eax\) - 174: 81 90 90 90 90 90 90 90 90 90 [ ]*adcl \$0x90909090,0x90909090\(%eax\) - 17e: 83 90 90 90 90 90 90 [ ]*adcl \$0xffffff90,0x90909090\(%eax\) - 185: 84 90 90 90 90 90 [ ]*test %dl,0x90909090\(%eax\) - 18b: 85 90 90 90 90 90 [ ]*test %edx,0x90909090\(%eax\) - 191: 86 90 90 90 90 90 [ ]*xchg %dl,0x90909090\(%eax\) - 197: 87 90 90 90 90 90 [ ]*xchg %edx,0x90909090\(%eax\) - 19d: 88 90 90 90 90 90 [ ]*mov %dl,0x90909090\(%eax\) - 1a3: 89 90 90 90 90 90 [ ]*mov %edx,0x90909090\(%eax\) - 1a9: 8a 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%dl - 1af: 8b 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%edx - 1b5: 8c 90 90 90 90 90 [ ]*movw %ss,0x90909090\(%eax\) - 1bb: 8d 90 90 90 90 90 [ ]*lea 0x90909090\(%eax\),%edx - 1c1: 8e 90 90 90 90 90 [ ]*movw 0x90909090\(%eax\),%ss - 1c7: 8f 80 90 90 90 90 [ ]*popl 0x90909090\(%eax\) + 16d: 80 90 90 90 90 90 90 [ ]*adcb \$0x90,-0x6f6f6f70\(%eax\) + 174: 81 90 90 90 90 90 90 90 90 90 [ ]*adcl \$0x90909090,-0x6f6f6f70\(%eax\) + 17e: 83 90 90 90 90 90 90 [ ]*adcl \$0xffffff90,-0x6f6f6f70\(%eax\) + 185: 84 90 90 90 90 90 [ ]*test %dl,-0x6f6f6f70\(%eax\) + 18b: 85 90 90 90 90 90 [ ]*test %edx,-0x6f6f6f70\(%eax\) + 191: 86 90 90 90 90 90 [ ]*xchg %dl,-0x6f6f6f70\(%eax\) + 197: 87 90 90 90 90 90 [ ]*xchg %edx,-0x6f6f6f70\(%eax\) + 19d: 88 90 90 90 90 90 [ ]*mov %dl,-0x6f6f6f70\(%eax\) + 1a3: 89 90 90 90 90 90 [ ]*mov %edx,-0x6f6f6f70\(%eax\) + 1a9: 8a 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%dl + 1af: 8b 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%edx + 1b5: 8c 90 90 90 90 90 [ ]*mov %ss,-0x6f6f6f70\(%eax\) + 1bb: 8d 90 90 90 90 90 [ ]*lea -0x6f6f6f70\(%eax\),%edx + 1c1: 8e 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%ss + 1c7: 8f 80 90 90 90 90 [ ]*popl -0x6f6f6f70\(%eax\) 1cd: 90 [ ]*nop 1ce: 91 [ ]*xchg %eax,%ecx 1cf: 92 [ ]*xchg %eax,%edx @@ -190,14 +190,14 @@ Disassembly of section .text: 231: bd 90 90 90 90 [ ]*mov \$0x90909090,%ebp 236: be 90 90 90 90 [ ]*mov \$0x90909090,%esi 23b: bf 90 90 90 90 [ ]*mov \$0x90909090,%edi - 240: c0 90 90 90 90 90 90 [ ]*rclb \$0x90,0x90909090\(%eax\) - 247: c1 90 90 90 90 90 90 [ ]*rcll \$0x90,0x90909090\(%eax\) + 240: c0 90 90 90 90 90 90 [ ]*rclb \$0x90,-0x6f6f6f70\(%eax\) + 247: c1 90 90 90 90 90 90 [ ]*rcll \$0x90,-0x6f6f6f70\(%eax\) 24e: c2 90 90 [ ]*ret \$0x9090 251: c3 [ ]*ret - 252: c4 90 90 90 90 90 [ ]*les 0x90909090\(%eax\),%edx - 258: c5 90 90 90 90 90 [ ]*lds 0x90909090\(%eax\),%edx - 25e: c6 80 90 90 90 90 90 [ ]*movb \$0x90,0x90909090\(%eax\) - 265: c7 80 90 90 90 90 90 90 90 90 [ ]*movl \$0x90909090,0x90909090\(%eax\) + 252: c4 90 90 90 90 90 [ ]*les -0x6f6f6f70\(%eax\),%edx + 258: c5 90 90 90 90 90 [ ]*lds -0x6f6f6f70\(%eax\),%edx + 25e: c6 80 90 90 90 90 90 [ ]*movb \$0x90,-0x6f6f6f70\(%eax\) + 265: c7 80 90 90 90 90 90 90 90 90 [ ]*movl \$0x90909090,-0x6f6f6f70\(%eax\) 26f: c8 90 90 90 [ ]*enter \$0x9090,\$0x90 273: c9 [ ]*leave 274: ca 90 90 [ ]*lret \$0x9090 @@ -206,21 +206,21 @@ Disassembly of section .text: 279: cd 90 [ ]*int \$0x90 27b: ce [ ]*into 27c: cf [ ]*iret - 27d: d0 90 90 90 90 90 [ ]*rclb 0x90909090\(%eax\) - 283: d1 90 90 90 90 90 [ ]*rcll 0x90909090\(%eax\) - 289: d2 90 90 90 90 90 [ ]*rclb %cl,0x90909090\(%eax\) - 28f: d3 90 90 90 90 90 [ ]*rcll %cl,0x90909090\(%eax\) + 27d: d0 90 90 90 90 90 [ ]*rclb -0x6f6f6f70\(%eax\) + 283: d1 90 90 90 90 90 [ ]*rcll -0x6f6f6f70\(%eax\) + 289: d2 90 90 90 90 90 [ ]*rclb %cl,-0x6f6f6f70\(%eax\) + 28f: d3 90 90 90 90 90 [ ]*rcll %cl,-0x6f6f6f70\(%eax\) 295: d4 90 [ ]*aam \$0xffffff90 297: d5 90 [ ]*aad \$0xffffff90 299: d7 [ ]*xlat %ds:\(%ebx\) - 29a: d8 90 90 90 90 90 [ ]*fcoms 0x90909090\(%eax\) - 2a0: d9 90 90 90 90 90 [ ]*fsts 0x90909090\(%eax\) - 2a6: da 90 90 90 90 90 [ ]*ficoml 0x90909090\(%eax\) - 2ac: db 90 90 90 90 90 [ ]*fistl 0x90909090\(%eax\) - 2b2: dc 90 90 90 90 90 [ ]*fcoml 0x90909090\(%eax\) - 2b8: dd 90 90 90 90 90 [ ]*fstl 0x90909090\(%eax\) - 2be: de 90 90 90 90 90 [ ]*ficom 0x90909090\(%eax\) - 2c4: df 90 90 90 90 90 [ ]*fist 0x90909090\(%eax\) + 29a: d8 90 90 90 90 90 [ ]*fcoms -0x6f6f6f70\(%eax\) + 2a0: d9 90 90 90 90 90 [ ]*fsts -0x6f6f6f70\(%eax\) + 2a6: da 90 90 90 90 90 [ ]*ficoml -0x6f6f6f70\(%eax\) + 2ac: db 90 90 90 90 90 [ ]*fistl -0x6f6f6f70\(%eax\) + 2b2: dc 90 90 90 90 90 [ ]*fcoml -0x6f6f6f70\(%eax\) + 2b8: dd 90 90 90 90 90 [ ]*fstl -0x6f6f6f70\(%eax\) + 2be: de 90 90 90 90 90 [ ]*ficom -0x6f6f6f70\(%eax\) + 2c4: df 90 90 90 90 90 [ ]*fist -0x6f6f6f70\(%eax\) 2ca: e0 90 [ ]*loopne (0x)?25c.* 2cc: e1 90 [ ]*loope (0x)?25e.* 2ce: e2 90 [ ]*loop (0x)?260.* @@ -239,19 +239,19 @@ Disassembly of section .text: 2f0: ef [ ]*out %eax,\(%dx\) 2f1: f4 [ ]*hlt 2f2: f5 [ ]*cmc - 2f3: f6 90 90 90 90 90 [ ]*notb 0x90909090\(%eax\) - 2f9: f7 90 90 90 90 90 [ ]*notl 0x90909090\(%eax\) + 2f3: f6 90 90 90 90 90 [ ]*notb -0x6f6f6f70\(%eax\) + 2f9: f7 90 90 90 90 90 [ ]*notl -0x6f6f6f70\(%eax\) 2ff: f8 [ ]*clc 300: f9 [ ]*stc 301: fa [ ]*cli 302: fb [ ]*sti 303: fc [ ]*cld 304: fd [ ]*std - 305: ff 90 90 90 90 90 [ ]*call \*0x90909090\(%eax\) - 30b: 0f 00 90 90 90 90 90 [ ]*lldt 0x90909090\(%eax\) - 312: 0f 01 90 90 90 90 90 [ ]*lgdtl 0x90909090\(%eax\) - 319: 0f 02 90 90 90 90 90 [ ]*lar 0x90909090\(%eax\),%edx - 320: 0f 03 90 90 90 90 90 [ ]*lsl 0x90909090\(%eax\),%edx + 305: ff 90 90 90 90 90 [ ]*call \*-0x6f6f6f70\(%eax\) + 30b: 0f 00 90 90 90 90 90 [ ]*lldt -0x6f6f6f70\(%eax\) + 312: 0f 01 90 90 90 90 90 [ ]*lgdtl -0x6f6f6f70\(%eax\) + 319: 0f 02 90 90 90 90 90 [ ]*lar -0x6f6f6f70\(%eax\),%edx + 320: 0f 03 90 90 90 90 90 [ ]*lsl -0x6f6f6f70\(%eax\),%edx 327: 0f 06 [ ]*clts 329: 0f 08 [ ]*invd 32b: 0f 09 [ ]*wbinvd @@ -266,45 +266,45 @@ Disassembly of section .text: 343: 0f 31 [ ]*rdtsc 345: 0f 32 [ ]*rdmsr 347: 0f 33 [ ]*rdpmc - 349: 0f 40 90 90 90 90 90 [ ]*cmovo 0x90909090\(%eax\),%edx - 350: 0f 41 90 90 90 90 90 [ ]*cmovno 0x90909090\(%eax\),%edx - 357: 0f 42 90 90 90 90 90 [ ]*cmovb 0x90909090\(%eax\),%edx - 35e: 0f 43 90 90 90 90 90 [ ]*cmovae 0x90909090\(%eax\),%edx - 365: 0f 44 90 90 90 90 90 [ ]*cmove 0x90909090\(%eax\),%edx - 36c: 0f 45 90 90 90 90 90 [ ]*cmovne 0x90909090\(%eax\),%edx - 373: 0f 46 90 90 90 90 90 [ ]*cmovbe 0x90909090\(%eax\),%edx - 37a: 0f 47 90 90 90 90 90 [ ]*cmova 0x90909090\(%eax\),%edx - 381: 0f 48 90 90 90 90 90 [ ]*cmovs 0x90909090\(%eax\),%edx - 388: 0f 49 90 90 90 90 90 [ ]*cmovns 0x90909090\(%eax\),%edx - 38f: 0f 4a 90 90 90 90 90 [ ]*cmovp 0x90909090\(%eax\),%edx - 396: 0f 4b 90 90 90 90 90 [ ]*cmovnp 0x90909090\(%eax\),%edx - 39d: 0f 4c 90 90 90 90 90 [ ]*cmovl 0x90909090\(%eax\),%edx - 3a4: 0f 4d 90 90 90 90 90 [ ]*cmovge 0x90909090\(%eax\),%edx - 3ab: 0f 4e 90 90 90 90 90 [ ]*cmovle 0x90909090\(%eax\),%edx - 3b2: 0f 4f 90 90 90 90 90 [ ]*cmovg 0x90909090\(%eax\),%edx - 3b9: 0f 60 90 90 90 90 90 [ ]*punpcklbw 0x90909090\(%eax\),%mm2 - 3c0: 0f 61 90 90 90 90 90 [ ]*punpcklwd 0x90909090\(%eax\),%mm2 - 3c7: 0f 62 90 90 90 90 90 [ ]*punpckldq 0x90909090\(%eax\),%mm2 - 3ce: 0f 63 90 90 90 90 90 [ ]*packsswb 0x90909090\(%eax\),%mm2 - 3d5: 0f 64 90 90 90 90 90 [ ]*pcmpgtb 0x90909090\(%eax\),%mm2 - 3dc: 0f 65 90 90 90 90 90 [ ]*pcmpgtw 0x90909090\(%eax\),%mm2 - 3e3: 0f 66 90 90 90 90 90 [ ]*pcmpgtd 0x90909090\(%eax\),%mm2 - 3ea: 0f 67 90 90 90 90 90 [ ]*packuswb 0x90909090\(%eax\),%mm2 - 3f1: 0f 68 90 90 90 90 90 [ ]*punpckhbw 0x90909090\(%eax\),%mm2 - 3f8: 0f 69 90 90 90 90 90 [ ]*punpckhwd 0x90909090\(%eax\),%mm2 - 3ff: 0f 6a 90 90 90 90 90 [ ]*punpckhdq 0x90909090\(%eax\),%mm2 - 406: 0f 6b 90 90 90 90 90 [ ]*packssdw 0x90909090\(%eax\),%mm2 - 40d: 0f 6e 90 90 90 90 90 [ ]*movd 0x90909090\(%eax\),%mm2 - 414: 0f 6f 90 90 90 90 90 [ ]*movq 0x90909090\(%eax\),%mm2 + 349: 0f 40 90 90 90 90 90 [ ]*cmovo -0x6f6f6f70\(%eax\),%edx + 350: 0f 41 90 90 90 90 90 [ ]*cmovno -0x6f6f6f70\(%eax\),%edx + 357: 0f 42 90 90 90 90 90 [ ]*cmovb -0x6f6f6f70\(%eax\),%edx + 35e: 0f 43 90 90 90 90 90 [ ]*cmovae -0x6f6f6f70\(%eax\),%edx + 365: 0f 44 90 90 90 90 90 [ ]*cmove -0x6f6f6f70\(%eax\),%edx + 36c: 0f 45 90 90 90 90 90 [ ]*cmovne -0x6f6f6f70\(%eax\),%edx + 373: 0f 46 90 90 90 90 90 [ ]*cmovbe -0x6f6f6f70\(%eax\),%edx + 37a: 0f 47 90 90 90 90 90 [ ]*cmova -0x6f6f6f70\(%eax\),%edx + 381: 0f 48 90 90 90 90 90 [ ]*cmovs -0x6f6f6f70\(%eax\),%edx + 388: 0f 49 90 90 90 90 90 [ ]*cmovns -0x6f6f6f70\(%eax\),%edx + 38f: 0f 4a 90 90 90 90 90 [ ]*cmovp -0x6f6f6f70\(%eax\),%edx + 396: 0f 4b 90 90 90 90 90 [ ]*cmovnp -0x6f6f6f70\(%eax\),%edx + 39d: 0f 4c 90 90 90 90 90 [ ]*cmovl -0x6f6f6f70\(%eax\),%edx + 3a4: 0f 4d 90 90 90 90 90 [ ]*cmovge -0x6f6f6f70\(%eax\),%edx + 3ab: 0f 4e 90 90 90 90 90 [ ]*cmovle -0x6f6f6f70\(%eax\),%edx + 3b2: 0f 4f 90 90 90 90 90 [ ]*cmovg -0x6f6f6f70\(%eax\),%edx + 3b9: 0f 60 90 90 90 90 90 [ ]*punpcklbw -0x6f6f6f70\(%eax\),%mm2 + 3c0: 0f 61 90 90 90 90 90 [ ]*punpcklwd -0x6f6f6f70\(%eax\),%mm2 + 3c7: 0f 62 90 90 90 90 90 [ ]*punpckldq -0x6f6f6f70\(%eax\),%mm2 + 3ce: 0f 63 90 90 90 90 90 [ ]*packsswb -0x6f6f6f70\(%eax\),%mm2 + 3d5: 0f 64 90 90 90 90 90 [ ]*pcmpgtb -0x6f6f6f70\(%eax\),%mm2 + 3dc: 0f 65 90 90 90 90 90 [ ]*pcmpgtw -0x6f6f6f70\(%eax\),%mm2 + 3e3: 0f 66 90 90 90 90 90 [ ]*pcmpgtd -0x6f6f6f70\(%eax\),%mm2 + 3ea: 0f 67 90 90 90 90 90 [ ]*packuswb -0x6f6f6f70\(%eax\),%mm2 + 3f1: 0f 68 90 90 90 90 90 [ ]*punpckhbw -0x6f6f6f70\(%eax\),%mm2 + 3f8: 0f 69 90 90 90 90 90 [ ]*punpckhwd -0x6f6f6f70\(%eax\),%mm2 + 3ff: 0f 6a 90 90 90 90 90 [ ]*punpckhdq -0x6f6f6f70\(%eax\),%mm2 + 406: 0f 6b 90 90 90 90 90 [ ]*packssdw -0x6f6f6f70\(%eax\),%mm2 + 40d: 0f 6e 90 90 90 90 90 [ ]*movd -0x6f6f6f70\(%eax\),%mm2 + 414: 0f 6f 90 90 90 90 90 [ ]*movq -0x6f6f6f70\(%eax\),%mm2 41b: 0f 71 d0 90 [ ]*psrlw \$0x90,%mm0 41f: 0f 72 d0 90 [ ]*psrld \$0x90,%mm0 423: 0f 73 d0 90 [ ]*psrlq \$0x90,%mm0 - 427: 0f 74 90 90 90 90 90 [ ]*pcmpeqb 0x90909090\(%eax\),%mm2 - 42e: 0f 75 90 90 90 90 90 [ ]*pcmpeqw 0x90909090\(%eax\),%mm2 - 435: 0f 76 90 90 90 90 90 [ ]*pcmpeqd 0x90909090\(%eax\),%mm2 + 427: 0f 74 90 90 90 90 90 [ ]*pcmpeqb -0x6f6f6f70\(%eax\),%mm2 + 42e: 0f 75 90 90 90 90 90 [ ]*pcmpeqw -0x6f6f6f70\(%eax\),%mm2 + 435: 0f 76 90 90 90 90 90 [ ]*pcmpeqd -0x6f6f6f70\(%eax\),%mm2 43c: 0f 77 [ ]*emms - 43e: 0f 7e 90 90 90 90 90 [ ]*movd %mm2,0x90909090\(%eax\) - 445: 0f 7f 90 90 90 90 90 [ ]*movq %mm2,0x90909090\(%eax\) + 43e: 0f 7e 90 90 90 90 90 [ ]*movd %mm2,-0x6f6f6f70\(%eax\) + 445: 0f 7f 90 90 90 90 90 [ ]*movq %mm2,-0x6f6f6f70\(%eax\) 44c: 0f 80 90 90 90 90 [ ]*jo (0x)?909094e2.* 452: 0f 81 90 90 90 90 [ ]*jno (0x)?909094e8.* 458: 0f 82 90 90 90 90 [ ]*jb (0x)?909094ee.* @@ -321,51 +321,51 @@ Disassembly of section .text: 49a: 0f 8d 90 90 90 90 [ ]*jge (0x)?90909530.* 4a0: 0f 8e 90 90 90 90 [ ]*jle (0x)?90909536.* 4a6: 0f 8f 90 90 90 90 [ ]*jg (0x)?9090953c.* - 4ac: 0f 90 80 90 90 90 90 [ ]*seto 0x90909090\(%eax\) - 4b3: 0f 91 80 90 90 90 90 [ ]*setno 0x90909090\(%eax\) - 4ba: 0f 92 80 90 90 90 90 [ ]*setb 0x90909090\(%eax\) - 4c1: 0f 93 80 90 90 90 90 [ ]*setae 0x90909090\(%eax\) - 4c8: 0f 94 80 90 90 90 90 [ ]*sete 0x90909090\(%eax\) - 4cf: 0f 95 80 90 90 90 90 [ ]*setne 0x90909090\(%eax\) - 4d6: 0f 96 80 90 90 90 90 [ ]*setbe 0x90909090\(%eax\) - 4dd: 0f 97 80 90 90 90 90 [ ]*seta 0x90909090\(%eax\) - 4e4: 0f 98 80 90 90 90 90 [ ]*sets 0x90909090\(%eax\) - 4eb: 0f 99 80 90 90 90 90 [ ]*setns 0x90909090\(%eax\) - 4f2: 0f 9a 80 90 90 90 90 [ ]*setp 0x90909090\(%eax\) - 4f9: 0f 9b 80 90 90 90 90 [ ]*setnp 0x90909090\(%eax\) - 500: 0f 9c 80 90 90 90 90 [ ]*setl 0x90909090\(%eax\) - 507: 0f 9d 80 90 90 90 90 [ ]*setge 0x90909090\(%eax\) - 50e: 0f 9e 80 90 90 90 90 [ ]*setle 0x90909090\(%eax\) - 515: 0f 9f 80 90 90 90 90 [ ]*setg 0x90909090\(%eax\) + 4ac: 0f 90 80 90 90 90 90 [ ]*seto -0x6f6f6f70\(%eax\) + 4b3: 0f 91 80 90 90 90 90 [ ]*setno -0x6f6f6f70\(%eax\) + 4ba: 0f 92 80 90 90 90 90 [ ]*setb -0x6f6f6f70\(%eax\) + 4c1: 0f 93 80 90 90 90 90 [ ]*setae -0x6f6f6f70\(%eax\) + 4c8: 0f 94 80 90 90 90 90 [ ]*sete -0x6f6f6f70\(%eax\) + 4cf: 0f 95 80 90 90 90 90 [ ]*setne -0x6f6f6f70\(%eax\) + 4d6: 0f 96 80 90 90 90 90 [ ]*setbe -0x6f6f6f70\(%eax\) + 4dd: 0f 97 80 90 90 90 90 [ ]*seta -0x6f6f6f70\(%eax\) + 4e4: 0f 98 80 90 90 90 90 [ ]*sets -0x6f6f6f70\(%eax\) + 4eb: 0f 99 80 90 90 90 90 [ ]*setns -0x6f6f6f70\(%eax\) + 4f2: 0f 9a 80 90 90 90 90 [ ]*setp -0x6f6f6f70\(%eax\) + 4f9: 0f 9b 80 90 90 90 90 [ ]*setnp -0x6f6f6f70\(%eax\) + 500: 0f 9c 80 90 90 90 90 [ ]*setl -0x6f6f6f70\(%eax\) + 507: 0f 9d 80 90 90 90 90 [ ]*setge -0x6f6f6f70\(%eax\) + 50e: 0f 9e 80 90 90 90 90 [ ]*setle -0x6f6f6f70\(%eax\) + 515: 0f 9f 80 90 90 90 90 [ ]*setg -0x6f6f6f70\(%eax\) 51c: 0f a0 [ ]*push %fs 51e: 0f a1 [ ]*pop %fs 520: 0f a2 [ ]*cpuid - 522: 0f a3 90 90 90 90 90 [ ]*bt %edx,0x90909090\(%eax\) - 529: 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%edx,0x90909090\(%eax\) - 531: 0f a5 90 90 90 90 90 [ ]*shld %cl,%edx,0x90909090\(%eax\) + 522: 0f a3 90 90 90 90 90 [ ]*bt %edx,-0x6f6f6f70\(%eax\) + 529: 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%edx,-0x6f6f6f70\(%eax\) + 531: 0f a5 90 90 90 90 90 [ ]*shld %cl,%edx,-0x6f6f6f70\(%eax\) 538: 0f a8 [ ]*push %gs 53a: 0f a9 [ ]*pop %gs 53c: 0f aa [ ]*rsm - 53e: 0f ab 90 90 90 90 90 [ ]*bts %edx,0x90909090\(%eax\) - 545: 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%edx,0x90909090\(%eax\) - 54d: 0f ad 90 90 90 90 90 [ ]*shrd %cl,%edx,0x90909090\(%eax\) - 554: 0f af 90 90 90 90 90 [ ]*imul 0x90909090\(%eax\),%edx - 55b: 0f b0 90 90 90 90 90 [ ]*cmpxchg %dl,0x90909090\(%eax\) - 562: 0f b1 90 90 90 90 90 [ ]*cmpxchg %edx,0x90909090\(%eax\) - 569: 0f b2 90 90 90 90 90 [ ]*lss 0x90909090\(%eax\),%edx - 570: 0f b3 90 90 90 90 90 [ ]*btr %edx,0x90909090\(%eax\) - 577: 0f b4 90 90 90 90 90 [ ]*lfs 0x90909090\(%eax\),%edx - 57e: 0f b5 90 90 90 90 90 [ ]*lgs 0x90909090\(%eax\),%edx - 585: 0f b6 90 90 90 90 90 [ ]*movzbl 0x90909090\(%eax\),%edx - 58c: 0f b7 90 90 90 90 90 [ ]*movzwl 0x90909090\(%eax\),%edx + 53e: 0f ab 90 90 90 90 90 [ ]*bts %edx,-0x6f6f6f70\(%eax\) + 545: 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%edx,-0x6f6f6f70\(%eax\) + 54d: 0f ad 90 90 90 90 90 [ ]*shrd %cl,%edx,-0x6f6f6f70\(%eax\) + 554: 0f af 90 90 90 90 90 [ ]*imul -0x6f6f6f70\(%eax\),%edx + 55b: 0f b0 90 90 90 90 90 [ ]*cmpxchg %dl,-0x6f6f6f70\(%eax\) + 562: 0f b1 90 90 90 90 90 [ ]*cmpxchg %edx,-0x6f6f6f70\(%eax\) + 569: 0f b2 90 90 90 90 90 [ ]*lss -0x6f6f6f70\(%eax\),%edx + 570: 0f b3 90 90 90 90 90 [ ]*btr %edx,-0x6f6f6f70\(%eax\) + 577: 0f b4 90 90 90 90 90 [ ]*lfs -0x6f6f6f70\(%eax\),%edx + 57e: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx + 585: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx + 58c: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx 593: 0f b9 [ ]*ud2b - 595: 0f bb 90 90 90 90 90 [ ]*btc %edx,0x90909090\(%eax\) - 59c: 0f bc 90 90 90 90 90 [ ]*bsf 0x90909090\(%eax\),%edx - 5a3: 0f bd 90 90 90 90 90 [ ]*bsr 0x90909090\(%eax\),%edx - 5aa: 0f be 90 90 90 90 90 [ ]*movsbl 0x90909090\(%eax\),%edx - 5b1: 0f bf 90 90 90 90 90 [ ]*movswl 0x90909090\(%eax\),%edx - 5b8: 0f c0 90 90 90 90 90 [ ]*xadd %dl,0x90909090\(%eax\) - 5bf: 0f c1 90 90 90 90 90 [ ]*xadd %edx,0x90909090\(%eax\) + 595: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\) + 59c: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx + 5a3: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx + 5aa: 0f be 90 90 90 90 90 [ ]*movsbl -0x6f6f6f70\(%eax\),%edx + 5b1: 0f bf 90 90 90 90 90 [ ]*movswl -0x6f6f6f70\(%eax\),%edx + 5b8: 0f c0 90 90 90 90 90 [ ]*xadd %dl,-0x6f6f6f70\(%eax\) + 5bf: 0f c1 90 90 90 90 90 [ ]*xadd %edx,-0x6f6f6f70\(%eax\) 5c6: 0f c8 [ ]*bswap %eax 5c8: 0f c9 [ ]*bswap %ecx 5ca: 0f ca [ ]*bswap %edx @@ -374,65 +374,65 @@ Disassembly of section .text: 5d0: 0f cd [ ]*bswap %ebp 5d2: 0f ce [ ]*bswap %esi 5d4: 0f cf [ ]*bswap %edi - 5d6: 0f d1 90 90 90 90 90 [ ]*psrlw 0x90909090\(%eax\),%mm2 - 5dd: 0f d2 90 90 90 90 90 [ ]*psrld 0x90909090\(%eax\),%mm2 - 5e4: 0f d3 90 90 90 90 90 [ ]*psrlq 0x90909090\(%eax\),%mm2 - 5eb: 0f d5 90 90 90 90 90 [ ]*pmullw 0x90909090\(%eax\),%mm2 - 5f2: 0f d8 90 90 90 90 90 [ ]*psubusb 0x90909090\(%eax\),%mm2 - 5f9: 0f d9 90 90 90 90 90 [ ]*psubusw 0x90909090\(%eax\),%mm2 - 600: 0f db 90 90 90 90 90 [ ]*pand 0x90909090\(%eax\),%mm2 - 607: 0f dc 90 90 90 90 90 [ ]*paddusb 0x90909090\(%eax\),%mm2 - 60e: 0f dd 90 90 90 90 90 [ ]*paddusw 0x90909090\(%eax\),%mm2 - 615: 0f df 90 90 90 90 90 [ ]*pandn 0x90909090\(%eax\),%mm2 - 61c: 0f e1 90 90 90 90 90 [ ]*psraw 0x90909090\(%eax\),%mm2 - 623: 0f e2 90 90 90 90 90 [ ]*psrad 0x90909090\(%eax\),%mm2 - 62a: 0f e5 90 90 90 90 90 [ ]*pmulhw 0x90909090\(%eax\),%mm2 - 631: 0f e8 90 90 90 90 90 [ ]*psubsb 0x90909090\(%eax\),%mm2 - 638: 0f e9 90 90 90 90 90 [ ]*psubsw 0x90909090\(%eax\),%mm2 - 63f: 0f eb 90 90 90 90 90 [ ]*por 0x90909090\(%eax\),%mm2 - 646: 0f ec 90 90 90 90 90 [ ]*paddsb 0x90909090\(%eax\),%mm2 - 64d: 0f ed 90 90 90 90 90 [ ]*paddsw 0x90909090\(%eax\),%mm2 - 654: 0f ef 90 90 90 90 90 [ ]*pxor 0x90909090\(%eax\),%mm2 - 65b: 0f f1 90 90 90 90 90 [ ]*psllw 0x90909090\(%eax\),%mm2 - 662: 0f f2 90 90 90 90 90 [ ]*pslld 0x90909090\(%eax\),%mm2 - 669: 0f f3 90 90 90 90 90 [ ]*psllq 0x90909090\(%eax\),%mm2 - 670: 0f f5 90 90 90 90 90 [ ]*pmaddwd 0x90909090\(%eax\),%mm2 - 677: 0f f8 90 90 90 90 90 [ ]*psubb 0x90909090\(%eax\),%mm2 - 67e: 0f f9 90 90 90 90 90 [ ]*psubw 0x90909090\(%eax\),%mm2 - 685: 0f fa 90 90 90 90 90 [ ]*psubd 0x90909090\(%eax\),%mm2 - 68c: 0f fc 90 90 90 90 90 [ ]*paddb 0x90909090\(%eax\),%mm2 - 693: 0f fd 90 90 90 90 90 [ ]*paddw 0x90909090\(%eax\),%mm2 - 69a: 0f fe 90 90 90 90 90 [ ]*paddd 0x90909090\(%eax\),%mm2 - 6a1: 66 01 90 90 90 90 90 [ ]*add %dx,0x90909090\(%eax\) - 6a8: 66 03 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%dx + 5d6: 0f d1 90 90 90 90 90 [ ]*psrlw -0x6f6f6f70\(%eax\),%mm2 + 5dd: 0f d2 90 90 90 90 90 [ ]*psrld -0x6f6f6f70\(%eax\),%mm2 + 5e4: 0f d3 90 90 90 90 90 [ ]*psrlq -0x6f6f6f70\(%eax\),%mm2 + 5eb: 0f d5 90 90 90 90 90 [ ]*pmullw -0x6f6f6f70\(%eax\),%mm2 + 5f2: 0f d8 90 90 90 90 90 [ ]*psubusb -0x6f6f6f70\(%eax\),%mm2 + 5f9: 0f d9 90 90 90 90 90 [ ]*psubusw -0x6f6f6f70\(%eax\),%mm2 + 600: 0f db 90 90 90 90 90 [ ]*pand -0x6f6f6f70\(%eax\),%mm2 + 607: 0f dc 90 90 90 90 90 [ ]*paddusb -0x6f6f6f70\(%eax\),%mm2 + 60e: 0f dd 90 90 90 90 90 [ ]*paddusw -0x6f6f6f70\(%eax\),%mm2 + 615: 0f df 90 90 90 90 90 [ ]*pandn -0x6f6f6f70\(%eax\),%mm2 + 61c: 0f e1 90 90 90 90 90 [ ]*psraw -0x6f6f6f70\(%eax\),%mm2 + 623: 0f e2 90 90 90 90 90 [ ]*psrad -0x6f6f6f70\(%eax\),%mm2 + 62a: 0f e5 90 90 90 90 90 [ ]*pmulhw -0x6f6f6f70\(%eax\),%mm2 + 631: 0f e8 90 90 90 90 90 [ ]*psubsb -0x6f6f6f70\(%eax\),%mm2 + 638: 0f e9 90 90 90 90 90 [ ]*psubsw -0x6f6f6f70\(%eax\),%mm2 + 63f: 0f eb 90 90 90 90 90 [ ]*por -0x6f6f6f70\(%eax\),%mm2 + 646: 0f ec 90 90 90 90 90 [ ]*paddsb -0x6f6f6f70\(%eax\),%mm2 + 64d: 0f ed 90 90 90 90 90 [ ]*paddsw -0x6f6f6f70\(%eax\),%mm2 + 654: 0f ef 90 90 90 90 90 [ ]*pxor -0x6f6f6f70\(%eax\),%mm2 + 65b: 0f f1 90 90 90 90 90 [ ]*psllw -0x6f6f6f70\(%eax\),%mm2 + 662: 0f f2 90 90 90 90 90 [ ]*pslld -0x6f6f6f70\(%eax\),%mm2 + 669: 0f f3 90 90 90 90 90 [ ]*psllq -0x6f6f6f70\(%eax\),%mm2 + 670: 0f f5 90 90 90 90 90 [ ]*pmaddwd -0x6f6f6f70\(%eax\),%mm2 + 677: 0f f8 90 90 90 90 90 [ ]*psubb -0x6f6f6f70\(%eax\),%mm2 + 67e: 0f f9 90 90 90 90 90 [ ]*psubw -0x6f6f6f70\(%eax\),%mm2 + 685: 0f fa 90 90 90 90 90 [ ]*psubd -0x6f6f6f70\(%eax\),%mm2 + 68c: 0f fc 90 90 90 90 90 [ ]*paddb -0x6f6f6f70\(%eax\),%mm2 + 693: 0f fd 90 90 90 90 90 [ ]*paddw -0x6f6f6f70\(%eax\),%mm2 + 69a: 0f fe 90 90 90 90 90 [ ]*paddd -0x6f6f6f70\(%eax\),%mm2 + 6a1: 66 01 90 90 90 90 90 [ ]*add %dx,-0x6f6f6f70\(%eax\) + 6a8: 66 03 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%dx 6af: 66 05 90 90 [ ]*add \$0x9090,%ax 6b3: 66 06 [ ]*pushw %es 6b5: 66 07 [ ]*popw %es - 6b7: 66 09 90 90 90 90 90 [ ]*or %dx,0x90909090\(%eax\) - 6be: 66 0b 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%dx + 6b7: 66 09 90 90 90 90 90 [ ]*or %dx,-0x6f6f6f70\(%eax\) + 6be: 66 0b 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%dx 6c5: 66 0d 90 90 [ ]*or \$0x9090,%ax 6c9: 66 0e [ ]*pushw %cs - 6cb: 66 11 90 90 90 90 90 [ ]*adc %dx,0x90909090\(%eax\) - 6d2: 66 13 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%dx + 6cb: 66 11 90 90 90 90 90 [ ]*adc %dx,-0x6f6f6f70\(%eax\) + 6d2: 66 13 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%dx 6d9: 66 15 90 90 [ ]*adc \$0x9090,%ax 6dd: 66 16 [ ]*pushw %ss 6df: 66 17 [ ]*popw %ss - 6e1: 66 19 90 90 90 90 90 [ ]*sbb %dx,0x90909090\(%eax\) - 6e8: 66 1b 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%dx + 6e1: 66 19 90 90 90 90 90 [ ]*sbb %dx,-0x6f6f6f70\(%eax\) + 6e8: 66 1b 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%dx 6ef: 66 1d 90 90 [ ]*sbb \$0x9090,%ax 6f3: 66 1e [ ]*pushw %ds 6f5: 66 1f [ ]*popw %ds - 6f7: 66 21 90 90 90 90 90 [ ]*and %dx,0x90909090\(%eax\) - 6fe: 66 23 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%dx + 6f7: 66 21 90 90 90 90 90 [ ]*and %dx,-0x6f6f6f70\(%eax\) + 6fe: 66 23 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%dx 705: 66 25 90 90 [ ]*and \$0x9090,%ax - 709: 66 29 90 90 90 90 90 [ ]*sub %dx,0x90909090\(%eax\) - 710: 66 2b 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%dx + 709: 66 29 90 90 90 90 90 [ ]*sub %dx,-0x6f6f6f70\(%eax\) + 710: 66 2b 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%dx 717: 66 2d 90 90 [ ]*sub \$0x9090,%ax - 71b: 66 31 90 90 90 90 90 [ ]*xor %dx,0x90909090\(%eax\) - 722: 66 33 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%dx + 71b: 66 31 90 90 90 90 90 [ ]*xor %dx,-0x6f6f6f70\(%eax\) + 722: 66 33 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%dx 729: 66 35 90 90 [ ]*xor \$0x9090,%ax - 72d: 66 39 90 90 90 90 90 [ ]*cmp %dx,0x90909090\(%eax\) - 734: 66 3b 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%dx + 72d: 66 39 90 90 90 90 90 [ ]*cmp %dx,-0x6f6f6f70\(%eax\) + 734: 66 3b 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%dx 73b: 66 3d 90 90 [ ]*cmp \$0x9090,%ax 73f: 66 40 [ ]*inc %ax 741: 66 41 [ ]*inc %cx @@ -468,22 +468,22 @@ Disassembly of section .text: 77d: 66 5f [ ]*pop %di 77f: 66 60 [ ]*pushaw 781: 66 61 [ ]*popaw - 783: 66 62 90 90 90 90 90 [ ]*bound %dx,0x90909090\(%eax\) + 783: 66 62 90 90 90 90 90 [ ]*bound %dx,-0x6f6f6f70\(%eax\) 78a: 66 68 90 90 [ ]*pushw \$0x9090 - 78e: 66 69 90 90 90 90 90 90 90 [ ]*imul \$0x9090,0x90909090\(%eax\),%dx + 78e: 66 69 90 90 90 90 90 90 90 [ ]*imul \$0x9090,-0x6f6f6f70\(%eax\),%dx 797: 66 6a 90 [ ]*pushw \$0xffffff90 - 79a: 66 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,0x90909090\(%eax\),%dx + 79a: 66 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,-0x6f6f6f70\(%eax\),%dx 7a2: 66 6d [ ]*insw \(%dx\),%es:\(%edi\) 7a4: 66 6f [ ]*outsw %ds:\(%esi\),\(%dx\) - 7a6: 66 81 90 90 90 90 90 90 90 [ ]*adcw \$0x9090,0x90909090\(%eax\) - 7af: 66 83 90 90 90 90 90 90 [ ]*adcw \$0xffffff90,0x90909090\(%eax\) - 7b7: 66 85 90 90 90 90 90 [ ]*test %dx,0x90909090\(%eax\) - 7be: 66 87 90 90 90 90 90 [ ]*xchg %dx,0x90909090\(%eax\) - 7c5: 66 89 90 90 90 90 90 [ ]*mov %dx,0x90909090\(%eax\) - 7cc: 66 8b 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%dx - 7d3: 8c 90 90 90 90 90 [ ]*mov[w ] %ss,0x90909090\(%eax\) - 7d9: 66 8d 90 90 90 90 90 [ ]*lea 0x90909090\(%eax\),%dx - 7e0: 66 8f 80 90 90 90 90 [ ]*popw 0x90909090\(%eax\) + 7a6: 66 81 90 90 90 90 90 90 90 [ ]*adcw \$0x9090,-0x6f6f6f70\(%eax\) + 7af: 66 83 90 90 90 90 90 90 [ ]*adcw \$0xffffff90,-0x6f6f6f70\(%eax\) + 7b7: 66 85 90 90 90 90 90 [ ]*test %dx,-0x6f6f6f70\(%eax\) + 7be: 66 87 90 90 90 90 90 [ ]*xchg %dx,-0x6f6f6f70\(%eax\) + 7c5: 66 89 90 90 90 90 90 [ ]*mov %dx,-0x6f6f6f70\(%eax\) + 7cc: 66 8b 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%dx + 7d3: 8c 90 90 90 90 90 [ ]*mov[w ] %ss,-0x6f6f6f70\(%eax\) + 7d9: 66 8d 90 90 90 90 90 [ ]*lea -0x6f6f6f70\(%eax\),%dx + 7e0: 66 8f 80 90 90 90 90 [ ]*popw -0x6f6f6f70\(%eax\) 7e7: 66 91 [ ]*xchg %ax,%cx 7e9: 66 92 [ ]*xchg %ax,%dx 7eb: 66 93 [ ]*xchg %ax,%bx @@ -512,67 +512,67 @@ Disassembly of section .text: 831: 66 bd 90 90 [ ]*mov \$0x9090,%bp 835: 66 be 90 90 [ ]*mov \$0x9090,%si 839: 66 bf 90 90 [ ]*mov \$0x9090,%di - 83d: 66 c1 90 90 90 90 90 90 [ ]*rclw \$0x90,0x90909090\(%eax\) + 83d: 66 c1 90 90 90 90 90 90 [ ]*rclw \$0x90,-0x6f6f6f70\(%eax\) 845: 66 c2 90 90 [ ]*retw \$0x9090 849: 66 c3 [ ]*retw - 84b: 66 c4 90 90 90 90 90 [ ]*les 0x90909090\(%eax\),%dx - 852: 66 c5 90 90 90 90 90 [ ]*lds 0x90909090\(%eax\),%dx - 859: 66 c7 80 90 90 90 90 90 90 [ ]*movw \$0x9090,0x90909090\(%eax\) + 84b: 66 c4 90 90 90 90 90 [ ]*les -0x6f6f6f70\(%eax\),%dx + 852: 66 c5 90 90 90 90 90 [ ]*lds -0x6f6f6f70\(%eax\),%dx + 859: 66 c7 80 90 90 90 90 90 90 [ ]*movw \$0x9090,-0x6f6f6f70\(%eax\) 862: 66 c8 90 90 90 [ ]*enterw \$0x9090,\$0x90 867: 66 c9 [ ]*leavew 869: 66 ca 90 90 [ ]*lretw \$0x9090 86d: 66 cb [ ]*lretw 86f: 66 cf [ ]*iretw - 871: 66 d1 90 90 90 90 90 [ ]*rclw 0x90909090\(%eax\) - 878: 66 d3 90 90 90 90 90 [ ]*rclw %cl,0x90909090\(%eax\) + 871: 66 d1 90 90 90 90 90 [ ]*rclw -0x6f6f6f70\(%eax\) + 878: 66 d3 90 90 90 90 90 [ ]*rclw %cl,-0x6f6f6f70\(%eax\) 87f: 66 e5 90 [ ]*in \$0x90,%ax 882: 66 e7 90 [ ]*out %ax,\$0x90 885: 66 e8 8f 90 [ ]*callw (0x)?9918.* 889: 66 ea 90 90 90 90 [ ]*ljmpw \$0x9090,\$0x9090 88f: 66 ed [ ]*in \(%dx\),%ax 891: 66 ef [ ]*out %ax,\(%dx\) - 893: 66 f7 90 90 90 90 90 [ ]*notw 0x90909090\(%eax\) - 89a: 66 ff 90 90 90 90 90 [ ]*callw \*0x90909090\(%eax\) - 8a1: 66 0f 02 90 90 90 90 90 [ ]*lar 0x90909090\(%eax\),%dx - 8a9: 66 0f 03 90 90 90 90 90 [ ]*lsl 0x90909090\(%eax\),%dx - 8b1: 66 0f 40 90 90 90 90 90 [ ]*cmovo 0x90909090\(%eax\),%dx - 8b9: 66 0f 41 90 90 90 90 90 [ ]*cmovno 0x90909090\(%eax\),%dx - 8c1: 66 0f 42 90 90 90 90 90 [ ]*cmovb 0x90909090\(%eax\),%dx - 8c9: 66 0f 43 90 90 90 90 90 [ ]*cmovae 0x90909090\(%eax\),%dx - 8d1: 66 0f 44 90 90 90 90 90 [ ]*cmove 0x90909090\(%eax\),%dx - 8d9: 66 0f 45 90 90 90 90 90 [ ]*cmovne 0x90909090\(%eax\),%dx - 8e1: 66 0f 46 90 90 90 90 90 [ ]*cmovbe 0x90909090\(%eax\),%dx - 8e9: 66 0f 47 90 90 90 90 90 [ ]*cmova 0x90909090\(%eax\),%dx - 8f1: 66 0f 48 90 90 90 90 90 [ ]*cmovs 0x90909090\(%eax\),%dx - 8f9: 66 0f 49 90 90 90 90 90 [ ]*cmovns 0x90909090\(%eax\),%dx - 901: 66 0f 4a 90 90 90 90 90 [ ]*cmovp 0x90909090\(%eax\),%dx - 909: 66 0f 4b 90 90 90 90 90 [ ]*cmovnp 0x90909090\(%eax\),%dx - 911: 66 0f 4c 90 90 90 90 90 [ ]*cmovl 0x90909090\(%eax\),%dx - 919: 66 0f 4d 90 90 90 90 90 [ ]*cmovge 0x90909090\(%eax\),%dx - 921: 66 0f 4e 90 90 90 90 90 [ ]*cmovle 0x90909090\(%eax\),%dx - 929: 66 0f 4f 90 90 90 90 90 [ ]*cmovg 0x90909090\(%eax\),%dx + 893: 66 f7 90 90 90 90 90 [ ]*notw -0x6f6f6f70\(%eax\) + 89a: 66 ff 90 90 90 90 90 [ ]*callw \*-0x6f6f6f70\(%eax\) + 8a1: 66 0f 02 90 90 90 90 90 [ ]*lar -0x6f6f6f70\(%eax\),%dx + 8a9: 66 0f 03 90 90 90 90 90 [ ]*lsl -0x6f6f6f70\(%eax\),%dx + 8b1: 66 0f 40 90 90 90 90 90 [ ]*cmovo -0x6f6f6f70\(%eax\),%dx + 8b9: 66 0f 41 90 90 90 90 90 [ ]*cmovno -0x6f6f6f70\(%eax\),%dx + 8c1: 66 0f 42 90 90 90 90 90 [ ]*cmovb -0x6f6f6f70\(%eax\),%dx + 8c9: 66 0f 43 90 90 90 90 90 [ ]*cmovae -0x6f6f6f70\(%eax\),%dx + 8d1: 66 0f 44 90 90 90 90 90 [ ]*cmove -0x6f6f6f70\(%eax\),%dx + 8d9: 66 0f 45 90 90 90 90 90 [ ]*cmovne -0x6f6f6f70\(%eax\),%dx + 8e1: 66 0f 46 90 90 90 90 90 [ ]*cmovbe -0x6f6f6f70\(%eax\),%dx + 8e9: 66 0f 47 90 90 90 90 90 [ ]*cmova -0x6f6f6f70\(%eax\),%dx + 8f1: 66 0f 48 90 90 90 90 90 [ ]*cmovs -0x6f6f6f70\(%eax\),%dx + 8f9: 66 0f 49 90 90 90 90 90 [ ]*cmovns -0x6f6f6f70\(%eax\),%dx + 901: 66 0f 4a 90 90 90 90 90 [ ]*cmovp -0x6f6f6f70\(%eax\),%dx + 909: 66 0f 4b 90 90 90 90 90 [ ]*cmovnp -0x6f6f6f70\(%eax\),%dx + 911: 66 0f 4c 90 90 90 90 90 [ ]*cmovl -0x6f6f6f70\(%eax\),%dx + 919: 66 0f 4d 90 90 90 90 90 [ ]*cmovge -0x6f6f6f70\(%eax\),%dx + 921: 66 0f 4e 90 90 90 90 90 [ ]*cmovle -0x6f6f6f70\(%eax\),%dx + 929: 66 0f 4f 90 90 90 90 90 [ ]*cmovg -0x6f6f6f70\(%eax\),%dx 931: 66 0f a0 [ ]*pushw %fs 934: 66 0f a1 [ ]*popw %fs - 937: 66 0f a3 90 90 90 90 90 [ ]*bt %dx,0x90909090\(%eax\) - 93f: 66 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%dx,0x90909090\(%eax\) - 948: 66 0f a5 90 90 90 90 90 [ ]*shld %cl,%dx,0x90909090\(%eax\) + 937: 66 0f a3 90 90 90 90 90 [ ]*bt %dx,-0x6f6f6f70\(%eax\) + 93f: 66 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%dx,-0x6f6f6f70\(%eax\) + 948: 66 0f a5 90 90 90 90 90 [ ]*shld %cl,%dx,-0x6f6f6f70\(%eax\) 950: 66 0f a8 [ ]*pushw %gs 953: 66 0f a9 [ ]*popw %gs - 956: 66 0f ab 90 90 90 90 90 [ ]*bts %dx,0x90909090\(%eax\) - 95e: 66 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%dx,0x90909090\(%eax\) - 967: 66 0f ad 90 90 90 90 90 [ ]*shrd %cl,%dx,0x90909090\(%eax\) - 96f: 66 0f af 90 90 90 90 90 [ ]*imul 0x90909090\(%eax\),%dx - 977: 66 0f b1 90 90 90 90 90 [ ]*cmpxchg %dx,0x90909090\(%eax\) - 97f: 66 0f b2 90 90 90 90 90 [ ]*lss 0x90909090\(%eax\),%dx - 987: 66 0f b3 90 90 90 90 90 [ ]*btr %dx,0x90909090\(%eax\) - 98f: 66 0f b4 90 90 90 90 90 [ ]*lfs 0x90909090\(%eax\),%dx - 997: 66 0f b5 90 90 90 90 90 [ ]*lgs 0x90909090\(%eax\),%dx - 99f: 66 0f b6 90 90 90 90 90 [ ]*movzbw 0x90909090\(%eax\),%dx - 9a7: 66 0f bb 90 90 90 90 90 [ ]*btc %dx,0x90909090\(%eax\) - 9af: 66 0f bc 90 90 90 90 90 [ ]*bsf 0x90909090\(%eax\),%dx - 9b7: 66 0f bd 90 90 90 90 90 [ ]*bsr 0x90909090\(%eax\),%dx - 9bf: 66 0f be 90 90 90 90 90 [ ]*movsbw 0x90909090\(%eax\),%dx - 9c7: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,0x90909090\(%eax\) + 956: 66 0f ab 90 90 90 90 90 [ ]*bts %dx,-0x6f6f6f70\(%eax\) + 95e: 66 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%dx,-0x6f6f6f70\(%eax\) + 967: 66 0f ad 90 90 90 90 90 [ ]*shrd %cl,%dx,-0x6f6f6f70\(%eax\) + 96f: 66 0f af 90 90 90 90 90 [ ]*imul -0x6f6f6f70\(%eax\),%dx + 977: 66 0f b1 90 90 90 90 90 [ ]*cmpxchg %dx,-0x6f6f6f70\(%eax\) + 97f: 66 0f b2 90 90 90 90 90 [ ]*lss -0x6f6f6f70\(%eax\),%dx + 987: 66 0f b3 90 90 90 90 90 [ ]*btr %dx,-0x6f6f6f70\(%eax\) + 98f: 66 0f b4 90 90 90 90 90 [ ]*lfs -0x6f6f6f70\(%eax\),%dx + 997: 66 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%dx + 99f: 66 0f b6 90 90 90 90 90 [ ]*movzbw -0x6f6f6f70\(%eax\),%dx + 9a7: 66 0f bb 90 90 90 90 90 [ ]*btc %dx,-0x6f6f6f70\(%eax\) + 9af: 66 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%dx + 9b7: 66 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%dx + 9bf: 66 0f be 90 90 90 90 90 [ ]*movsbw -0x6f6f6f70\(%eax\),%dx + 9c7: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,-0x6f6f6f70\(%eax\) 0+9cf <gs_foo>: 9cf: c3 [ ]*ret @@ -591,7 +591,7 @@ Disassembly of section .text: 9ec: 88 04 56 [ ]*mov %al,\(%esi,%edx,2\) 9ef: eb 0c [ ]*jmp 9fd <rot5> 9f1: 6c [ ]*insb \(%dx\),%es:\(%edi\) - 9f2: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,0x90909090\(%eax\) + 9f2: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,-0x6f6f6f70\(%eax\) 9fa: 83 e0 f8 [ ]*and \$0xfffffff8,%eax 0+9fd <rot5>: @@ -601,7 +601,7 @@ Disassembly of section .text: a04: 0d 90 90 90 90 [ ]*or \$0x90909090,%eax a09: 0e [ ]*push %cs a0a: 8b 04 5d 00 00 00 00 [ ]*mov 0x0\(,%ebx,2\),%eax - a11: 10 14 85 90 90 90 90 [ ]*adc %dl,0x90909090\(,%eax,4\) + a11: 10 14 85 90 90 90 90 [ ]*adc %dl,-0x6f6f6f70\(,%eax,4\) a18: 2f [ ]*das a19: ea 90 90 90 90 90 90 [ ]*ljmp \$0x9090,\$0x90909090 a20: 66 a5 [ ]*movsw %ds:\(%esi\),%es:\(%edi\) @@ -628,5 +628,6 @@ Disassembly of section .text: a87: b0 11 [ ]*mov \$0x11,%al a89: b3 47 [ ]*mov \$0x47,%bl a8b: b3 47 [ ]*mov \$0x47,%bl - a8d: 00 00 .* + a8d: 0f ad d0 [ ]*shrd %cl,%edx,%eax + a90: 0f a5 d0 [ ]*shld %cl,%edx,%eax [ ]*... diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s index 464f4b6d411b..ef65aa9c30f0 100644 --- a/gas/testsuite/gas/i386/intel.s +++ b/gas/testsuite/gas/i386/intel.s @@ -484,8 +484,8 @@ foo: xchg bp, ax xchg si, ax xchg di, ax - cbtw - cwtd + cbw + cwd callw 0x9090,0x9090 pushfw popfw @@ -624,5 +624,8 @@ rot5: mov %al, 0x11 mov %bl, ((( 0x4711 ) >> 8) & 0xff) mov %bl, 0x47 - + + shrd eax, edx, cl + shld eax, edx, cl + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/intel16.d b/gas/testsuite/gas/i386/intel16.d index 495fe14f211b..e6d0ee28f83a 100644 --- a/gas/testsuite/gas/i386/intel16.d +++ b/gas/testsuite/gas/i386/intel16.d @@ -7,12 +7,12 @@ Disassembly of section .text: 0+000 <.text>: - 0: 66 0f bf 06 00 00 [ ]*movswl 0,%eax - 6: 66 0f be 06 00 00 [ ]*movsbl 0,%eax - c: 0f be 06 00 00 [ ]*movsbw 0,%ax - 11: 66 0f b7 06 00 00 [ ]*movzwl 0,%eax - 17: 66 0f b6 06 00 00 [ ]*movzbl 0,%eax - 1d: 0f b6 06 00 00 [ ]*movzbw 0,%ax + 0: 66 0f bf 06 00 00 [ ]*movswl 0x0,%eax + 6: 66 0f be 06 00 00 [ ]*movsbl 0x0,%eax + c: 0f be 06 00 00 [ ]*movsbw 0x0,%ax + 11: 66 0f b7 06 00 00 [ ]*movzwl 0x0,%eax + 17: 66 0f b6 06 00 00 [ ]*movzbl 0x0,%eax + 1d: 0f b6 06 00 00 [ ]*movzbw 0x0,%ax 22: 8d 00 [ ]*lea \(%bx,%si\),%ax 24: 8d 02 [ ]*lea \(%bp,%si\),%ax 26: 8d 01 [ ]*lea \(%bx,%di\),%ax diff --git a/gas/testsuite/gas/i386/intelok.d b/gas/testsuite/gas/i386/intelok.d index 8e7fdbf75447..878b712cf117 100644 --- a/gas/testsuite/gas/i386/intelok.d +++ b/gas/testsuite/gas/i386/intelok.d @@ -94,35 +94,35 @@ Disassembly of section .text: [ ]*[0-9a-f]+: d7[ ]+xlat(b|[ ]+(BYTE PTR )?(ds:)?\[ebx\]) [ ]*[0-9a-f]+: d7[ ]+xlat(b|[ ]+(BYTE PTR )?(ds:)?\[ebx\]) [ ]*[0-9a-f]+: d7[ ]+xlat(b|[ ]+(BYTE PTR )?(ds:)?\[ebx\]) -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\] -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\] -[ ]*[0-9a-f]+: 8b 40 04[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+4\] -[ ]*[0-9a-f]+: 8b 40 04[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+4\] -[ ]*[0-9a-f]+: 8b 40 06[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+6\] -[ ]*[0-9a-f]+: 8b 40 06[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+6\] -[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+12\] -[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+12\] -[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\] -[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+18\] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 40 04[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?4\] +[ ]*[0-9a-f]+: 8b 40 04[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?4\] +[ ]*[0-9a-f]+: 8b 40 06[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?6\] +[ ]*[0-9a-f]+: 8b 40 06[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?6\] +[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0xc\] +[ ]*[0-9a-f]+: 8b 40 0c[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0xc\] +[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0x12\] +[ ]*[0-9a-f]+: 8b 40 12[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0x12\] [ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\] [ ]*[0-9a-f]+: 8b 04 85 02 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\] -[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\] -[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\] -[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\] -[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\] -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\] -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\] -[ ]*[0-9a-f]+: 8b 44 08 fb[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\-5\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] -[ ]*[0-9a-f]+: 8b 44 08 0f[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+15\] -[ ]*[0-9a-f]+: 8b 40 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+16\] -[ ]*[0-9a-f]+: 8b 40 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+16\] -[ ]*[0-9a-f]+: 8b 44 08 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+16\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] -[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+1\] +[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\+(0x)?0] +[ ]*[0-9a-f]+: 8b 04 45 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\*2\+(0x)?0] +[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\+(0x)?0] +[ ]*[0-9a-f]+: 8b 04 8d 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[ecx\*4\+(0x)?0] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 fb[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\-(0x)?5\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 0f[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+0xf\] +[ ]*[0-9a-f]+: 8b 40 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0x10\] +[ ]*[0-9a-f]+: 8b 40 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+0x10\] +[ ]*[0-9a-f]+: 8b 44 08 10[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+0x10\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] +[ ]*[0-9a-f]+: 8b 44 08 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\+(0x)?1\] [ ]*[0-9a-f]+: 8b 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\] [ ]*[0-9a-f]+: 8b 04 08[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\] [ ]*[0-9a-f]+: 8b 04 08[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+ecx\] @@ -153,12 +153,12 @@ Disassembly of section .text: [ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,0x0 [ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,0x0 [ ]*[0-9a-f]+: b8 00 00 00 00[ ]+mov[ ]+eax,0x0 -[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\] -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1] -[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\] +[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?0\] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1] +[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?0\] [ ]*[0-9a-f]+: 8b 80 01 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] -[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\] -[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+1\] +[ ]*[0-9a-f]+: 8b 80 00 00 00 00[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?0\] +[ ]*[0-9a-f]+: 8b 40 01[ ]+mov[ ]+eax,(DWORD PTR )?\[eax\+(0x)?1\] [ ]*[0-9a-f]+: a1 01 00 00 00[ ]+mov[ ]+eax,ds:0x1 [ ]*[0-9a-f]+: a1 ff ff ff ff[ ]+mov[ ]+eax,ds:0xffffffff [ ]*[0-9a-f]+: 26 a1 02 00 00 00[ ]+mov[ ]+eax,es:0x2 diff --git a/gas/testsuite/gas/i386/inval-crc32.l b/gas/testsuite/gas/i386/inval-crc32.l new file mode 100644 index 000000000000..14f908d1b9fc --- /dev/null +++ b/gas/testsuite/gas/i386/inval-crc32.l @@ -0,0 +1,43 @@ +.*: Assembler messages: +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* +.*:23: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Check illegal crc32 in SSE4\.2 +[ ]*2[ ]+ +[ ]*3[ ]+\.text +[ ]*4[ ]+foo: +[ ]*5[ ]+ +[ ]*6[ ]+crc32b \(%esi\), %al +[ ]*7[ ]+crc32w \(%esi\), %ax +[ ]*8[ ]+crc32 \(%esi\), %al +[ ]*9[ ]+crc32 \(%esi\), %ax +[ ]*10[ ]+crc32 \(%esi\), %eax +[ ]*11[ ]+crc32 %al, %al +[ ]*12[ ]+crc32b %al, %al +[ ]*13[ ]+crc32 %ax, %ax +[ ]*14[ ]+crc32w %ax, %ax +[ ]*15[ ]+ +[ ]*16[ ]+\.intel_syntax noprefix +[ ]*17[ ]+crc32 al,byte ptr \[esi\] +[ ]*18[ ]+crc32 ax, word ptr \[esi\] +[ ]*19[ ]+crc32 al, \[esi\] +[ ]*20[ ]+crc32 ax, \[esi\] +[ ]*21[ ]+crc32 eax, \[esi\] +[ ]*22[ ]+crc32 al,al +[ ]*23[ ]+crc32 ax, ax diff --git a/gas/testsuite/gas/i386/inval-crc32.s b/gas/testsuite/gas/i386/inval-crc32.s new file mode 100644 index 000000000000..5232fb0ae98e --- /dev/null +++ b/gas/testsuite/gas/i386/inval-crc32.s @@ -0,0 +1,23 @@ +# Check illegal crc32 in SSE4.2 + + .text +foo: + +crc32b (%esi), %al +crc32w (%esi), %ax +crc32 (%esi), %al +crc32 (%esi), %ax +crc32 (%esi), %eax +crc32 %al, %al +crc32b %al, %al +crc32 %ax, %ax +crc32w %ax, %ax + +.intel_syntax noprefix +crc32 al,byte ptr [esi] +crc32 ax, word ptr [esi] +crc32 al, [esi] +crc32 ax, [esi] +crc32 eax, [esi] +crc32 al,al +crc32 ax, ax diff --git a/gas/testsuite/gas/i386/inval.l b/gas/testsuite/gas/i386/inval.l index e78949918531..8abcbde95a73 100644 --- a/gas/testsuite/gas/i386/inval.l +++ b/gas/testsuite/gas/i386/inval.l @@ -45,6 +45,8 @@ .*:46: Error: .* .*:47: Error: .* .*:48: Error: .* +.*:49: Error: .* +.*:50: Error: .* GAS LISTING .* @@ -96,3 +98,5 @@ GAS LISTING .* 46 [ ]* fstb %st\(0\) 47 [ ]* fcompll 28\(%ebp\) 48 [ ]* fldlw \(%eax\) + 49 [ ]* movl \$%ebx,%eax + 50 [ ]* insertq \$4,\$2,%xmm2,%ebx diff --git a/gas/testsuite/gas/i386/inval.s b/gas/testsuite/gas/i386/inval.s index e37a18eac60d..5b440ed0b55f 100644 --- a/gas/testsuite/gas/i386/inval.s +++ b/gas/testsuite/gas/i386/inval.s @@ -46,3 +46,5 @@ foo: jaw foo fstb %st(0) fcompll 28(%ebp) fldlw (%eax) + movl $%ebx,%eax + insertq $4,$2,%xmm2,%ebx diff --git a/gas/testsuite/gas/i386/jump16.d b/gas/testsuite/gas/i386/jump16.d index 3d5d6bbb42f2..87951effa576 100644 --- a/gas/testsuite/gas/i386/jump16.d +++ b/gas/testsuite/gas/i386/jump16.d @@ -8,33 +8,33 @@ Disassembly of section .text: 0+000 <.text>: 0: eb fe [ ]*jmp (0x0|0 <.text>) 2: e9 (fe|fb) ff [ ]*jmp (0x3|0x0|0 <.text>) 3: (R_386_PC)?(DISP)?16 xxx - 5: ff 26 00 00 [ ]*jmp \*0 7: (R_386_)?(dir)?16 xxx + 5: ff 26 00 00 [ ]*jmp \*0x0 7: (R_386_)?(dir)?16 xxx 9: 66 ff e7 [ ]*jmpl \*%edi c: 67 ff 27 [ ]*addr32 jmp \*\(%edi\) f: 67 ff af 00 00 00 00 [ ]*addr32 ljmp \*0x0\(%edi\) 12: (R_386_)?(dir)?32 xxx - 16: ff 2e 00 00 [ ]*ljmp \*0 18: (R_386_)?(dir)?16 xxx + 16: ff 2e 00 00 [ ]*ljmp \*0x0 18: (R_386_)?(dir)?16 xxx 1a: ea 00 00 34 12 [ ]*ljmp \$0x1234,\$0x0 1b: (R_386_)?(dir)?16 xxx 1f: 66 e8 db ff ff ff [ ]*calll (0x0|0 <.text>) 25: 66 e8 (fc|d5) ff ff ff [ ]*calll (0x27|0x0|0 <.text>) 27: (R_386_PC)?(DISP)?32 xxx - 2b: 66 ff 16 00 00 [ ]*calll \*0 2e: (R_386_)?(dir)?16 xxx + 2b: 66 ff 16 00 00 [ ]*calll \*0x0 2e: (R_386_)?(dir)?16 xxx 30: 66 ff d7 [ ]*calll \*%edi 33: 67 66 ff 17 [ ]*addr32 calll \*\(%edi\) 37: 67 66 ff 9f 00 00 00 00 [ ]*addr32 lcalll \*0x0\(%edi\) 3b: (R_386_)?(dir)?32 xxx - 3f: 66 ff 1e 00 00 [ ]*lcalll \*0 42: (R_386_)?(dir)?16 xxx + 3f: 66 ff 1e 00 00 [ ]*lcalll \*0x0 42: (R_386_)?(dir)?16 xxx 44: 66 9a 00 00 00 00 34 12 [ ]*lcalll \$0x1234,\$0x0 46: (R_386_)?(dir)?32 xxx 4c: eb b2 [ ]*jmp (0x0|0 <.text>) - 4e: ff 26 00 00 [ ]*jmp \*0 50: (R_386_)?(dir)?16 xxx + 4e: ff 26 00 00 [ ]*jmp \*0x0 50: (R_386_)?(dir)?16 xxx 52: ff e7 [ ]*jmp \*%di 54: ff 25 [ ]*jmp \*\(%di\) - 56: ff ad 00 00 [ ]*ljmp \*0\(%di\) 58: (R_386_)?(dir)?16 xxx - 5a: ff 2e 00 00 [ ]*ljmp \*0 5c: (R_386_)?(dir)?16 xxx + 56: ff ad 00 00 [ ]*ljmp \*0x0\(%di\) 58: (R_386_)?(dir)?16 xxx + 5a: ff 2e 00 00 [ ]*ljmp \*0x0 5c: (R_386_)?(dir)?16 xxx 5e: ea 00 00 34 12 [ ]*ljmp \$0x1234,\$0x0 5f: (R_386_)?(dir)?16 xxx 63: e8 9a ff [ ]*call (0x0|0 <.text>) 66: e8 (fe|97) ff [ ]*call (0x67|0x0|0 <.text>) 67: (R_386_PC)?(DISP)?16 xxx - 69: ff 16 00 00 [ ]*call \*0 6b: (R_386_)?(dir)?16 xxx + 69: ff 16 00 00 [ ]*call \*0x0 6b: (R_386_)?(dir)?16 xxx 6d: ff d7 [ ]*call \*%di 6f: ff 15 [ ]*call \*\(%di\) - 71: ff 9d 00 00 [ ]*lcall \*0\(%di\) 73: (R_386_)?(dir)?16 xxx - 75: ff 1e 00 00 [ ]*lcall \*0 77: (R_386_)?(dir)?16 xxx + 71: ff 9d 00 00 [ ]*lcall \*0x0\(%di\) 73: (R_386_)?(dir)?16 xxx + 75: ff 1e 00 00 [ ]*lcall \*0x0 77: (R_386_)?(dir)?16 xxx 79: 9a 00 00 34 12 [ ]*lcall \$0x1234,\$0x0 7a: (R_386_)?(dir)?16 xxx ... diff --git a/gas/testsuite/gas/i386/merom.d b/gas/testsuite/gas/i386/merom.d index a09721c85eca..9baa234e45fe 100644 --- a/gas/testsuite/gas/i386/merom.d +++ b/gas/testsuite/gas/i386/merom.d @@ -70,4 +70,4 @@ Disassembly of section .text: 116: 0f 38 1e c1[ ]+pabsd %mm1,%mm0 11a: 66 0f 38 1e 01[ ]+pabsd \(%ecx\),%xmm0 11f: 66 0f 38 1e c1[ ]+pabsd %xmm1,%xmm0 - ... +#pass diff --git a/gas/testsuite/gas/i386/naked.d b/gas/testsuite/gas/i386/naked.d index 66214d58addf..27c1c052e501 100644 --- a/gas/testsuite/gas/i386/naked.d +++ b/gas/testsuite/gas/i386/naked.d @@ -6,16 +6,16 @@ Disassembly of section .text: 0+000 <foo>: - 0: 66 26 ff 23 [ ]*jmpw \*%es:\(%ebx\) + 0: 26 66 ff 23 [ ]*jmpw \*%es:\(%ebx\) 4: 8a 25 50 00 00 00 [ ]*mov 0x50,%ah a: b2 20 [ ]*mov \$0x20,%dl c: bb 00 00 00 00 [ ]*mov \$0x0,%ebx d: (R_386_)?(dir)?32 .text 11: d9 c9 [ ]*fxch %st\(1\) - 13: 36 8c a4 81 d2 04 00 00 [ ]*movw %fs,%ss:0x4d2\(%ecx,%eax,4\) - 1b: 8c 2c ed 00 00 00 00 [ ]*movw %gs,0x0\(,%ebp,8\) + 13: 36 8c a4 81 d2 04 00 00 [ ]*mov %fs,%ss:0x4d2\(%ecx,%eax,4\) + 1b: 8c 2c ed 00 00 00 00 [ ]*mov %gs,0x0\(,%ebp,8\) 22: 26 88 25 00 00 00 00 [ ]*mov %ah,%es:0x0 - 29: 2e 8b 74 14 80 [ ]*mov %cs:0xffffff80\(%esp,%edx,1\),%esi - 2e: f3 65 a5 [ ]*rep movsl %gs:\(%esi\),%es:\(%edi\) + 29: 2e 8b 74 14 80 [ ]*mov %cs:-0x80\(%esp,%edx,1\),%esi + 2e: 65 f3 a5 [ ]*rep movsl %gs:\(%esi\),%es:\(%edi\) 31: ec [ ]*in \(%dx\),%al 32: 66 ef [ ]*out %ax,\(%dx\) 34: 67 d2 14 [ ]*addr16 rclb %cl,\(%si\) diff --git a/gas/testsuite/gas/i386/nops-1-i386.d b/gas/testsuite/gas/i386/nops-1-i386.d new file mode 100644 index 000000000000..6d1582aa3752 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-i386.d @@ -0,0 +1,177 @@ +#as: -mtune=i686 -march=i386 +#source: nops-1.s +#objdump: -drw +#name: i386 -mtune=i686 -march=i386 nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+eb 0d[ ]+jmp[ ]+10[ ]+<nop14> +[ ]*3:[ ]+90[ ]+nop[ ]* +[ ]*4:[ ]+90[ ]+nop[ ]* +[ ]*5:[ ]+90[ ]+nop[ ]* +[ ]*6:[ ]+90[ ]+nop[ ]* +[ ]*7:[ ]+90[ ]+nop[ ]* +[ ]*8:[ ]+90[ ]+nop[ ]* +[ ]*9:[ ]+90[ ]+nop[ ]* +[ ]*a:[ ]+90[ ]+nop[ ]* +[ ]*b:[ ]+90[ ]+nop[ ]* +[ ]*c:[ ]+90[ ]+nop[ ]* +[ ]*d:[ ]+90[ ]+nop[ ]* +[ ]*e:[ ]+90[ ]+nop[ ]* +[ ]*f:[ ]+90[ ]+nop[ ]* + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*3a:[ ]+8d bf 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+89 f6[ ]+mov[ ]+%esi,%esi +[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+90[ ]+nop[ ]* +[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+90[ ]+nop[ ]* +[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-1-i686.d b/gas/testsuite/gas/i386/nops-1-i686.d new file mode 100644 index 000000000000..b3ee23bb24b8 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-i686.d @@ -0,0 +1,161 @@ +#as: -mtune=i686 +#source: nops-1.s +#objdump: -drw +#name: i386 -mtune=i686 nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) +[ ]*8:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) +[ ]*19:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) +[ ]*29:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) +[ ]*3a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) +[ ]*4a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%eax\) + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\) + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-1-merom.d b/gas/testsuite/gas/i386/nops-1-merom.d new file mode 100644 index 000000000000..90668e56f07b --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-merom.d @@ -0,0 +1,156 @@ +#as: -mtune=merom +#source: nops-1.s +#objdump: -drw +#name: i386 -mtune=merom nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%eax\) + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\) + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-1.d b/gas/testsuite/gas/i386/nops-1.d new file mode 100644 index 000000000000..4e81e9554585 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1.d @@ -0,0 +1,176 @@ +#source: nops-1.s +#objdump: -drw +#name: i386 nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+eb 0d[ ]+jmp[ ]+10[ ]+<nop14> +[ ]*3:[ ]+90[ ]+nop[ ]* +[ ]*4:[ ]+90[ ]+nop[ ]* +[ ]*5:[ ]+90[ ]+nop[ ]* +[ ]*6:[ ]+90[ ]+nop[ ]* +[ ]*7:[ ]+90[ ]+nop[ ]* +[ ]*8:[ ]+90[ ]+nop[ ]* +[ ]*9:[ ]+90[ ]+nop[ ]* +[ ]*a:[ ]+90[ ]+nop[ ]* +[ ]*b:[ ]+90[ ]+nop[ ]* +[ ]*c:[ ]+90[ ]+nop[ ]* +[ ]*d:[ ]+90[ ]+nop[ ]* +[ ]*e:[ ]+90[ ]+nop[ ]* +[ ]*f:[ ]+90[ ]+nop[ ]* + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*19:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*3a:[ ]+8d bf 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*49:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+89 f6[ ]+mov[ ]+%esi,%esi +[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+90[ ]+nop[ ]* +[ ]*79:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+90[ ]+nop[ ]* +[ ]*ac:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-1.s b/gas/testsuite/gas/i386/nops-1.s new file mode 100644 index 000000000000..a4fd7694de76 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1.s @@ -0,0 +1,147 @@ + .text +nop15: + nop + .p2align 4 + +nop14: + nop + nop + .p2align 4 + +nop13: + nop + nop + nop + .p2align 4 + +nop12: + nop + nop + nop + nop + .p2align 4 + +nop11: + nop + nop + nop + nop + nop + .p2align 4 + +nop10: + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop9: + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop8: + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop7: + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop6: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop5: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop4: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop3: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop2: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 diff --git a/gas/testsuite/gas/i386/nops-2-i386.d b/gas/testsuite/gas/i386/nops-2-i386.d new file mode 100644 index 000000000000..c7dffabe70be --- /dev/null +++ b/gas/testsuite/gas/i386/nops-2-i386.d @@ -0,0 +1,182 @@ +#as: -march=i386 +#source: nops-2.s +#objdump: -drw +#name: i386 -march=i386 nops 2 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop>: +[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+10 <nop15>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+eb 0d[ ]+jmp[ ]+20[ ]+<nop14> +[ ]*13:[ ]+90[ ]+nop[ ]* +[ ]*14:[ ]+90[ ]+nop[ ]* +[ ]*15:[ ]+90[ ]+nop[ ]* +[ ]*16:[ ]+90[ ]+nop[ ]* +[ ]*17:[ ]+90[ ]+nop[ ]* +[ ]*18:[ ]+90[ ]+nop[ ]* +[ ]*19:[ ]+90[ ]+nop[ ]* +[ ]*1a:[ ]+90[ ]+nop[ ]* +[ ]*1b:[ ]+90[ ]+nop[ ]* +[ ]*1c:[ ]+90[ ]+nop[ ]* +[ ]*1d:[ ]+90[ ]+nop[ ]* +[ ]*1e:[ ]+90[ ]+nop[ ]* +[ ]*1f:[ ]+90[ ]+nop[ ]* + +0+20 <nop14>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+30 <nop13>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+40 <nop12>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*4a:[ ]+8d bf 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+50 <nop11>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+60 <nop10>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+70 <nop9>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi +[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+80 <nop8>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+90 <nop7>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+a0 <nop6>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+b0 <nop5>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+c0 <nop4>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+d0 <nop3>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+e0 <nop2>: +[ ]*e0:[ ]+90[ ]+nop[ ]* +[ ]*e1:[ ]+90[ ]+nop[ ]* +[ ]*e2:[ ]+90[ ]+nop[ ]* +[ ]*e3:[ ]+90[ ]+nop[ ]* +[ ]*e4:[ ]+90[ ]+nop[ ]* +[ ]*e5:[ ]+90[ ]+nop[ ]* +[ ]*e6:[ ]+90[ ]+nop[ ]* +[ ]*e7:[ ]+90[ ]+nop[ ]* +[ ]*e8:[ ]+90[ ]+nop[ ]* +[ ]*e9:[ ]+90[ ]+nop[ ]* +[ ]*ea:[ ]+90[ ]+nop[ ]* +[ ]*eb:[ ]+90[ ]+nop[ ]* +[ ]*ec:[ ]+90[ ]+nop[ ]* +[ ]*ed:[ ]+90[ ]+nop[ ]* +[ ]*ee:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-2-merom.d b/gas/testsuite/gas/i386/nops-2-merom.d new file mode 100644 index 000000000000..c6ea559761e0 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-2-merom.d @@ -0,0 +1,182 @@ +#as: -march=i386 -mtune=merom +#source: nops-2.s +#objdump: -drw +#name: i386 -march=i386 -mtune=merom nops 2 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop>: +[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+10 <nop15>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+eb 0d[ ]+jmp[ ]+20[ ]+<nop14> +[ ]*13:[ ]+90[ ]+nop[ ]* +[ ]*14:[ ]+90[ ]+nop[ ]* +[ ]*15:[ ]+90[ ]+nop[ ]* +[ ]*16:[ ]+90[ ]+nop[ ]* +[ ]*17:[ ]+90[ ]+nop[ ]* +[ ]*18:[ ]+90[ ]+nop[ ]* +[ ]*19:[ ]+90[ ]+nop[ ]* +[ ]*1a:[ ]+90[ ]+nop[ ]* +[ ]*1b:[ ]+90[ ]+nop[ ]* +[ ]*1c:[ ]+90[ ]+nop[ ]* +[ ]*1d:[ ]+90[ ]+nop[ ]* +[ ]*1e:[ ]+90[ ]+nop[ ]* +[ ]*1f:[ ]+90[ ]+nop[ ]* + +0+20 <nop14>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+30 <nop13>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+40 <nop12>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*4a:[ ]+8d bf 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+50 <nop11>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+60 <nop10>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+70 <nop9>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi +[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+80 <nop8>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+90 <nop7>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+a0 <nop6>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+b0 <nop5>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+c0 <nop4>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+d0 <nop3>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+e0 <nop2>: +[ ]*e0:[ ]+90[ ]+nop[ ]* +[ ]*e1:[ ]+90[ ]+nop[ ]* +[ ]*e2:[ ]+90[ ]+nop[ ]* +[ ]*e3:[ ]+90[ ]+nop[ ]* +[ ]*e4:[ ]+90[ ]+nop[ ]* +[ ]*e5:[ ]+90[ ]+nop[ ]* +[ ]*e6:[ ]+90[ ]+nop[ ]* +[ ]*e7:[ ]+90[ ]+nop[ ]* +[ ]*e8:[ ]+90[ ]+nop[ ]* +[ ]*e9:[ ]+90[ ]+nop[ ]* +[ ]*ea:[ ]+90[ ]+nop[ ]* +[ ]*eb:[ ]+90[ ]+nop[ ]* +[ ]*ec:[ ]+90[ ]+nop[ ]* +[ ]*ed:[ ]+90[ ]+nop[ ]* +[ ]*ee:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-2.d b/gas/testsuite/gas/i386/nops-2.d new file mode 100644 index 000000000000..6382f7e3772a --- /dev/null +++ b/gas/testsuite/gas/i386/nops-2.d @@ -0,0 +1,181 @@ +#source: nops-2.s +#objdump: -drw +#name: i386 nops 2 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop>: +[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+10 <nop15>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+eb 0d[ ]+jmp[ ]+20[ ]+<nop14> +[ ]*13:[ ]+90[ ]+nop[ ]* +[ ]*14:[ ]+90[ ]+nop[ ]* +[ ]*15:[ ]+90[ ]+nop[ ]* +[ ]*16:[ ]+90[ ]+nop[ ]* +[ ]*17:[ ]+90[ ]+nop[ ]* +[ ]*18:[ ]+90[ ]+nop[ ]* +[ ]*19:[ ]+90[ ]+nop[ ]* +[ ]*1a:[ ]+90[ ]+nop[ ]* +[ ]*1b:[ ]+90[ ]+nop[ ]* +[ ]*1c:[ ]+90[ ]+nop[ ]* +[ ]*1d:[ ]+90[ ]+nop[ ]* +[ ]*1e:[ ]+90[ ]+nop[ ]* +[ ]*1f:[ ]+90[ ]+nop[ ]* + +0+20 <nop14>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*29:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+30 <nop13>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*39:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+40 <nop12>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*4a:[ ]+8d bf 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+50 <nop11>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*59:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+60 <nop10>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi +[ ]*69:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+70 <nop9>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+89 f6[ ]+mov[ ]+%esi,%esi +[ ]*79:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi\),%edi + +0+80 <nop8>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+90 <nop7>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+8d b4 26 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+a0 <nop6>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+b0 <nop5>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+c0 <nop4>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+8d 74 26 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+d0 <nop3>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+8d 76 00[ ]+lea[ ]+0x0\(%esi\),%esi + +0+e0 <nop2>: +[ ]*e0:[ ]+90[ ]+nop[ ]* +[ ]*e1:[ ]+90[ ]+nop[ ]* +[ ]*e2:[ ]+90[ ]+nop[ ]* +[ ]*e3:[ ]+90[ ]+nop[ ]* +[ ]*e4:[ ]+90[ ]+nop[ ]* +[ ]*e5:[ ]+90[ ]+nop[ ]* +[ ]*e6:[ ]+90[ ]+nop[ ]* +[ ]*e7:[ ]+90[ ]+nop[ ]* +[ ]*e8:[ ]+90[ ]+nop[ ]* +[ ]*e9:[ ]+90[ ]+nop[ ]* +[ ]*ea:[ ]+90[ ]+nop[ ]* +[ ]*eb:[ ]+90[ ]+nop[ ]* +[ ]*ec:[ ]+90[ ]+nop[ ]* +[ ]*ed:[ ]+90[ ]+nop[ ]* +[ ]*ee:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/nops-2.s b/gas/testsuite/gas/i386/nops-2.s new file mode 100644 index 000000000000..afbb87e09488 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-2.s @@ -0,0 +1,151 @@ + .text +nop: + cmove %eax,%eax + .p2align 4 + +nop15: + nop + .p2align 4 + +nop14: + nop + nop + .p2align 4 + +nop13: + nop + nop + nop + .p2align 4 + +nop12: + nop + nop + nop + nop + .p2align 4 + +nop11: + nop + nop + nop + nop + nop + .p2align 4 + +nop10: + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop9: + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop8: + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop7: + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop6: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop5: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop4: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop3: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop2: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 diff --git a/gas/testsuite/gas/i386/nops-3.d b/gas/testsuite/gas/i386/nops-3.d new file mode 100644 index 000000000000..10cc95c3fc98 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-3.d @@ -0,0 +1,43 @@ +#source: nops-3.s +#objdump: -drw +#name: i386 nops 3 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+90[ ]+nop[ ]* +[ ]*2:[ ]+90[ ]+nop[ ]* +[ ]*3:[ ]+90[ ]+nop[ ]* +[ ]*4:[ ]+90[ ]+nop[ ]* +[ ]*5:[ ]+90[ ]+nop[ ]* +[ ]*6:[ ]+90[ ]+nop[ ]* +[ ]*7:[ ]+90[ ]+nop[ ]* +[ ]*8:[ ]+90[ ]+nop[ ]* +[ ]*9:[ ]+90[ ]+nop[ ]* +[ ]*a:[ ]+90[ ]+nop[ ]* +[ ]*b:[ ]+90[ ]+nop[ ]* +[ ]*c:[ ]+90[ ]+nop[ ]* +[ ]*d:[ ]+90[ ]+nop[ ]* +[ ]*e:[ ]+90[ ]+nop[ ]* +[ ]*f:[ ]+90[ ]+nop[ ]* +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+90[ ]+nop[ ]* +[ ]*13:[ ]+90[ ]+nop[ ]* +[ ]*14:[ ]+90[ ]+nop[ ]* +[ ]*15:[ ]+90[ ]+nop[ ]* +[ ]*16:[ ]+90[ ]+nop[ ]* +[ ]*17:[ ]+90[ ]+nop[ ]* +[ ]*18:[ ]+90[ ]+nop[ ]* +[ ]*19:[ ]+90[ ]+nop[ ]* +[ ]*1a:[ ]+90[ ]+nop[ ]* +[ ]*1b:[ ]+90[ ]+nop[ ]* +[ ]*1c:[ ]+90[ ]+nop[ ]* +[ ]*1d:[ ]+90[ ]+nop[ ]* +[ ]*1e:[ ]+90[ ]+nop[ ]* +[ ]*1f:[ ]+90[ ]+nop[ ]* +[ ]*20:[ ]+89 c3[ ]+mov[ ]+%eax,%ebx[ ]* +#pass diff --git a/gas/testsuite/gas/i386/nops-3.s b/gas/testsuite/gas/i386/nops-3.s new file mode 100644 index 000000000000..c42b354788b9 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-3.s @@ -0,0 +1,6 @@ + .text +nop: + nop + .p2align 5 + mov %eax,%ebx + .p2align 4 diff --git a/gas/testsuite/gas/i386/nops.d b/gas/testsuite/gas/i386/nops.d new file mode 100644 index 000000000000..dc01585a69d9 --- /dev/null +++ b/gas/testsuite/gas/i386/nops.d @@ -0,0 +1,24 @@ +#objdump: -drw +#name: i386 nops + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\) +[ ]*3:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%eax\) +[ ]*7:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) +[ ]*c:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) +[ ]*12:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%eax\) +[ ]*19:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\) +[ ]*21:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\) +[ ]*2a:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\) +[ ]*34:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\) +[ ]*37:[ ]+0f 1f c0[ ]+nop[ ]+%eax +[ ]*3a:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax +[ ]*3e:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\) +[ ]*41:[ ]+66 0f 1f 00[ ]+nopw[ ]+\(%eax\) +[ ]*45:[ ]+0f 1f c0[ ]+nop[ ]+%eax +[ ]*48:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax +#pass diff --git a/gas/testsuite/gas/i386/nops.s b/gas/testsuite/gas/i386/nops.s new file mode 100644 index 000000000000..9dddb42b9ea1 --- /dev/null +++ b/gas/testsuite/gas/i386/nops.s @@ -0,0 +1,20 @@ + .text + + .byte 0x0f, 0x1f, 0x0 + .byte 0x0f, 0x1f, 0x40, 0x0 + .byte 0x0f, 0x1f, 0x44, 0x0, 0x0 + .byte 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0 + .byte 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0 + .byte 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + .byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + .byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + + nop (%eax) + nop %eax + nop %ax + nopl (%eax) + nopw (%eax) + nopl %eax + nopw %ax + + .p2align 4 diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d new file mode 100644 index 000000000000..2b728e113277 --- /dev/null +++ b/gas/testsuite/gas/i386/opcode-intel.d @@ -0,0 +1,615 @@ +#source: opcode.s +#as: -J +#objdump: -dwMintel +#name: i386 opcodes (Intel disassembly) + +.*: +file format .* + +Disassembly of section .text: + +0+000 <foo>: + *[0-9a-f]+: 00 90 90 90 90 90[ ]+add[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 01 90 90 90 90 90[ ]+add[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 02 90 90 90 90 90[ ]+add[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 03 90 90 90 90 90[ ]+add[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 04 90[ ]+add[ ]+al,0x90 + *[0-9a-f]+: 05 90 90 90 90[ ]+add[ ]+eax,0x90909090 + *[0-9a-f]+: 06[ ]+push[ ]+es + *[0-9a-f]+: 07[ ]+pop[ ]+es + *[0-9a-f]+: 08 90 90 90 90 90[ ]+or[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 09 90 90 90 90 90[ ]+or[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0a 90 90 90 90 90[ ]+or[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0b 90 90 90 90 90[ ]+or[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0c 90[ ]+or[ ]+al,0x90 + *[0-9a-f]+: 0d 90 90 90 90[ ]+or[ ]+eax,0x90909090 + *[0-9a-f]+: 0e[ ]+push[ ]+cs + *[0-9a-f]+: 10 90 90 90 90 90[ ]+adc[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 11 90 90 90 90 90[ ]+adc[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 12 90 90 90 90 90[ ]+adc[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 13 90 90 90 90 90[ ]+adc[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 14 90[ ]+adc[ ]+al,0x90 + *[0-9a-f]+: 15 90 90 90 90[ ]+adc[ ]+eax,0x90909090 + *[0-9a-f]+: 16[ ]+push[ ]+ss + *[0-9a-f]+: 17[ ]+pop[ ]+ss + *[0-9a-f]+: 18 90 90 90 90 90[ ]+sbb[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 19 90 90 90 90 90[ ]+sbb[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 1a 90 90 90 90 90[ ]+sbb[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 1b 90 90 90 90 90[ ]+sbb[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 1c 90[ ]+sbb[ ]+al,0x90 + *[0-9a-f]+: 1d 90 90 90 90[ ]+sbb[ ]+eax,0x90909090 + *[0-9a-f]+: 1e[ ]+push[ ]+ds + *[0-9a-f]+: 1f[ ]+pop[ ]+ds + *[0-9a-f]+: 20 90 90 90 90 90[ ]+and[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 21 90 90 90 90 90[ ]+and[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 22 90 90 90 90 90[ ]+and[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 23 90 90 90 90 90[ ]+and[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 24 90[ ]+and[ ]+al,0x90 + *[0-9a-f]+: 25 90 90 90 90[ ]+and[ ]+eax,0x90909090 + *[0-9a-f]+: 27[ ]+daa[ ]* + *[0-9a-f]+: 28 90 90 90 90 90[ ]+sub[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 29 90 90 90 90 90[ ]+sub[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 2a 90 90 90 90 90[ ]+sub[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 2b 90 90 90 90 90[ ]+sub[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 2c 90[ ]+sub[ ]+al,0x90 + *[0-9a-f]+: 2d 90 90 90 90[ ]+sub[ ]+eax,0x90909090 + *[0-9a-f]+: 2f[ ]+das[ ]* + *[0-9a-f]+: 30 90 90 90 90 90[ ]+xor[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 31 90 90 90 90 90[ ]+xor[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 32 90 90 90 90 90[ ]+xor[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 33 90 90 90 90 90[ ]+xor[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 34 90[ ]+xor[ ]+al,0x90 + *[0-9a-f]+: 35 90 90 90 90[ ]+xor[ ]+eax,0x90909090 + *[0-9a-f]+: 37[ ]+aaa[ ]* + *[0-9a-f]+: 38 90 90 90 90 90[ ]+cmp[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 39 90 90 90 90 90[ ]+cmp[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 3a 90 90 90 90 90[ ]+cmp[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 3b 90 90 90 90 90[ ]+cmp[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 3c 90[ ]+cmp[ ]+al,0x90 + *[0-9a-f]+: 3d 90 90 90 90[ ]+cmp[ ]+eax,0x90909090 + *[0-9a-f]+: 3f[ ]+aas[ ]* + *[0-9a-f]+: 40[ ]+inc[ ]+eax + *[0-9a-f]+: 41[ ]+inc[ ]+ecx + *[0-9a-f]+: 42[ ]+inc[ ]+edx + *[0-9a-f]+: 43[ ]+inc[ ]+ebx + *[0-9a-f]+: 44[ ]+inc[ ]+esp + *[0-9a-f]+: 45[ ]+inc[ ]+ebp + *[0-9a-f]+: 46[ ]+inc[ ]+esi + *[0-9a-f]+: 47[ ]+inc[ ]+edi + *[0-9a-f]+: 48[ ]+dec[ ]+eax + *[0-9a-f]+: 49[ ]+dec[ ]+ecx + *[0-9a-f]+: 4a[ ]+dec[ ]+edx + *[0-9a-f]+: 4b[ ]+dec[ ]+ebx + *[0-9a-f]+: 4c[ ]+dec[ ]+esp + *[0-9a-f]+: 4d[ ]+dec[ ]+ebp + *[0-9a-f]+: 4e[ ]+dec[ ]+esi + *[0-9a-f]+: 4f[ ]+dec[ ]+edi + *[0-9a-f]+: 50[ ]+push[ ]+eax + *[0-9a-f]+: 51[ ]+push[ ]+ecx + *[0-9a-f]+: 52[ ]+push[ ]+edx + *[0-9a-f]+: 53[ ]+push[ ]+ebx + *[0-9a-f]+: 54[ ]+push[ ]+esp + *[0-9a-f]+: 55[ ]+push[ ]+ebp + *[0-9a-f]+: 56[ ]+push[ ]+esi + *[0-9a-f]+: 57[ ]+push[ ]+edi + *[0-9a-f]+: 58[ ]+pop[ ]+eax + *[0-9a-f]+: 59[ ]+pop[ ]+ecx + *[0-9a-f]+: 5a[ ]+pop[ ]+edx + *[0-9a-f]+: 5b[ ]+pop[ ]+ebx + *[0-9a-f]+: 5c[ ]+pop[ ]+esp + *[0-9a-f]+: 5d[ ]+pop[ ]+ebp + *[0-9a-f]+: 5e[ ]+pop[ ]+esi + *[0-9a-f]+: 5f[ ]+pop[ ]+edi + *[0-9a-f]+: 60[ ]+pusha[ ]* + *[0-9a-f]+: 61[ ]+popa[ ]* + *[0-9a-f]+: 62 90 90 90 90 90[ ]+bound[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 68 90 90 90 90[ ]+push[ ]+0x90909090 + *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imul[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0x90909090 + *[0-9a-f]+: 6a 90[ ]+push[ ]+0xffffff90 + *[0-9a-f]+: 6b 90 90 90 90 90 90[ ]+imul[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\],0xffffff90 + *[0-9a-f]+: 6c[ ]+ins[ ]+BYTE PTR es:\[edi\],dx + *[0-9a-f]+: 6d[ ]+ins[ ]+DWORD PTR es:\[edi\],dx + *[0-9a-f]+: 6e[ ]+outs[ ]+dx,BYTE PTR ds:\[esi\] + *[0-9a-f]+: 6f[ ]+outs[ ]+dx,DWORD PTR ds:\[esi\] + *[0-9a-f]+: 70 90[ ]+jo[ ]+(0x)?df.* + *[0-9a-f]+: 71 90[ ]+jno[ ]+(0x)?e1.* + *[0-9a-f]+: 72 90[ ]+jb[ ]+(0x)?e3.* + *[0-9a-f]+: 73 90[ ]+jae[ ]+(0x)?e5.* + *[0-9a-f]+: 74 90[ ]+je[ ]+(0x)?e7.* + *[0-9a-f]+: 75 90[ ]+jne[ ]+(0x)?e9.* + *[0-9a-f]+: 76 90[ ]+jbe[ ]+(0x)?eb.* + *[0-9a-f]+: 77 90[ ]+ja[ ]+(0x)?ed.* + *[0-9a-f]+: 78 90[ ]+js[ ]+(0x)?ef.* + *[0-9a-f]+: 79 90[ ]+jns[ ]+(0x)?f1.* + *[0-9a-f]+: 7a 90[ ]+jp[ ]+(0x)?f3.* + *[0-9a-f]+: 7b 90[ ]+jnp[ ]+(0x)?f5.* + *[0-9a-f]+: 7c 90[ ]+jl[ ]+(0x)?f7.* + *[0-9a-f]+: 7d 90[ ]+jge[ ]+(0x)?f9.* + *[0-9a-f]+: 7e 90[ ]+jle[ ]+(0x)?fb.* + *[0-9a-f]+: 7f 90[ ]+jg[ ]+(0x)?fd.* + *[0-9a-f]+: 80 90 90 90 90 90 90[ ]+adc[ ]+BYTE PTR \[eax-0x6f6f6f70\],0x90 + *[0-9a-f]+: 81 90 90 90 90 90 90 90 90 90[ ]+adc[ ]+DWORD PTR \[eax-0x6f6f6f70\],0x90909090 + *[0-9a-f]+: 83 90 90 90 90 90 90[ ]+adc[ ]+DWORD PTR \[eax-0x6f6f6f70\],0xffffff90 + *[0-9a-f]+: 84 90 90 90 90 90[ ]+test[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 85 90 90 90 90 90[ ]+test[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 86 90 90 90 90 90[ ]+xchg[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 87 90 90 90 90 90[ ]+xchg[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 88 90 90 90 90 90[ ]+mov[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 89 90 90 90 90 90[ ]+mov[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 8a 90 90 90 90 90[ ]+mov[ ]+dl,(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 8b 90 90 90 90 90[ ]+mov[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 8c 90 90 90 90 90[ ]+mov[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],ss + *[0-9a-f]+: 8d 90 90 90 90 90[ ]+lea[ ]+edx,\[eax-0x6f6f6f70\] + *[0-9a-f]+: 8e 90 90 90 90 90[ ]+mov[ ]+ss,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 8f 80 90 90 90 90[ ]+pop[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 90[ ]+nop[ ]* + *[0-9a-f]+: 91[ ]+xchg[ ]+ecx,eax + *[0-9a-f]+: 92[ ]+xchg[ ]+edx,eax + *[0-9a-f]+: 93[ ]+xchg[ ]+ebx,eax + *[0-9a-f]+: 94[ ]+xchg[ ]+esp,eax + *[0-9a-f]+: 95[ ]+xchg[ ]+ebp,eax + *[0-9a-f]+: 96[ ]+xchg[ ]+esi,eax + *[0-9a-f]+: 97[ ]+xchg[ ]+edi,eax + *[0-9a-f]+: 98[ ]+cwde[ ]* + *[0-9a-f]+: 99[ ]+cdq[ ]* + *[0-9a-f]+: 9a 90 90 90 90 90 90[ ]+call[ ]+0x9090:0x90909090 + *[0-9a-f]+: 9b[ ]+fwait + *[0-9a-f]+: 9c[ ]+pushf[ ]* + *[0-9a-f]+: 9d[ ]+popf[ ]* + *[0-9a-f]+: 9e[ ]+sahf[ ]* + *[0-9a-f]+: 9f[ ]+lahf[ ]* + *[0-9a-f]+: a0 90 90 90 90[ ]+mov[ ]+al,ds:0x90909090 + *[0-9a-f]+: a1 90 90 90 90[ ]+mov[ ]+eax,ds:0x90909090 + *[0-9a-f]+: a2 90 90 90 90[ ]+mov[ ]+ds:0x90909090,al + *[0-9a-f]+: a3 90 90 90 90[ ]+mov[ ]+ds:0x90909090,eax + *[0-9a-f]+: a4[ ]+movs[ ]+BYTE PTR es:\[edi\],(BYTE PTR )?ds:\[esi\] + *[0-9a-f]+: a5[ ]+movs[ ]+DWORD PTR es:\[edi\],(DWORD PTR )?ds:\[esi\] + *[0-9a-f]+: a6[ ]+cmps[ ]+BYTE PTR ds:\[esi\],(BYTE PTR )?es:\[edi\] + *[0-9a-f]+: a7[ ]+cmps[ ]+DWORD PTR ds:\[esi\],(DWORD PTR )?es:\[edi\] + *[0-9a-f]+: a8 90[ ]+test[ ]+al,0x90 + *[0-9a-f]+: a9 90 90 90 90[ ]+test[ ]+eax,0x90909090 + *[0-9a-f]+: aa[ ]+stos[ ]+BYTE PTR es:\[edi\](,al)? + *[0-9a-f]+: ab[ ]+stos[ ]+DWORD PTR es:\[edi\](,eax)? + *[0-9a-f]+: ac[ ]+lods[ ]+(al,)?BYTE PTR ds:\[esi\] + *[0-9a-f]+: ad[ ]+lods[ ]+(eax,)?DWORD PTR ds:\[esi\] + *[0-9a-f]+: ae[ ]+scas[ ]+(al,)?BYTE PTR es:\[edi\] + *[0-9a-f]+: af[ ]+scas[ ]+(eax,)?DWORD PTR es:\[edi\] + *[0-9a-f]+: b0 90[ ]+mov[ ]+al,0x90 + *[0-9a-f]+: b1 90[ ]+mov[ ]+cl,0x90 + *[0-9a-f]+: b2 90[ ]+mov[ ]+dl,0x90 + *[0-9a-f]+: b3 90[ ]+mov[ ]+bl,0x90 + *[0-9a-f]+: b4 90[ ]+mov[ ]+ah,0x90 + *[0-9a-f]+: b5 90[ ]+mov[ ]+ch,0x90 + *[0-9a-f]+: b6 90[ ]+mov[ ]+dh,0x90 + *[0-9a-f]+: b7 90[ ]+mov[ ]+bh,0x90 + *[0-9a-f]+: b8 90 90 90 90[ ]+mov[ ]+eax,0x90909090 + *[0-9a-f]+: b9 90 90 90 90[ ]+mov[ ]+ecx,0x90909090 + *[0-9a-f]+: ba 90 90 90 90[ ]+mov[ ]+edx,0x90909090 + *[0-9a-f]+: bb 90 90 90 90[ ]+mov[ ]+ebx,0x90909090 + *[0-9a-f]+: bc 90 90 90 90[ ]+mov[ ]+esp,0x90909090 + *[0-9a-f]+: bd 90 90 90 90[ ]+mov[ ]+ebp,0x90909090 + *[0-9a-f]+: be 90 90 90 90[ ]+mov[ ]+esi,0x90909090 + *[0-9a-f]+: bf 90 90 90 90[ ]+mov[ ]+edi,0x90909090 + *[0-9a-f]+: c0 90 90 90 90 90 90[ ]+rcl[ ]+BYTE PTR \[eax-0x6f6f6f70\],0x90 + *[0-9a-f]+: c1 90 90 90 90 90 90[ ]+rcl[ ]+DWORD PTR \[eax-0x6f6f6f70\],0x90 + *[0-9a-f]+: c2 90 90[ ]+ret[ ]+0x9090 + *[0-9a-f]+: c3[ ]+ret[ ]* + *[0-9a-f]+: c4 90 90 90 90 90[ ]+les[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: c5 90 90 90 90 90[ ]+lds[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: c6 80 90 90 90 90 90[ ]+mov[ ]+BYTE PTR \[eax-0x6f6f6f70\],0x90 + *[0-9a-f]+: c7 80 90 90 90 90 90 90 90 90[ ]+mov[ ]+DWORD PTR \[eax-0x6f6f6f70\],0x90909090 + *[0-9a-f]+: c8 90 90 90[ ]+enter[ ]+0x9090,0x90 + *[0-9a-f]+: c9[ ]+leave[ ]* + *[0-9a-f]+: ca 90 90[ ]+lret[ ]+0x9090 + *[0-9a-f]+: cb[ ]+lret[ ]* + *[0-9a-f]+: cc[ ]+int3[ ]* + *[0-9a-f]+: cd 90[ ]+int[ ]+0x90 + *[0-9a-f]+: ce[ ]+into[ ]* + *[0-9a-f]+: cf[ ]+iret[ ]* + *[0-9a-f]+: d0 90 90 90 90 90[ ]+rcl[ ]+BYTE PTR \[eax-0x6f6f6f70\],1 + *[0-9a-f]+: d1 90 90 90 90 90[ ]+rcl[ ]+DWORD PTR \[eax-0x6f6f6f70\],1 + *[0-9a-f]+: d2 90 90 90 90 90[ ]+rcl[ ]+BYTE PTR \[eax-0x6f6f6f70\],cl + *[0-9a-f]+: d3 90 90 90 90 90[ ]+rcl[ ]+DWORD PTR \[eax-0x6f6f6f70\],cl + *[0-9a-f]+: d4 90[ ]+aam[ ]+0xffffff90 + *[0-9a-f]+: d5 90[ ]+aad[ ]+0xffffff90 + *[0-9a-f]+: d7[ ]+xlat[ ]+(BYTE PTR )?(ds:)?\[ebx\] + *[0-9a-f]+: d8 90 90 90 90 90[ ]+fcom[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: d9 90 90 90 90 90[ ]+fst[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: da 90 90 90 90 90[ ]+ficom[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: db 90 90 90 90 90[ ]+fist[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: dc 90 90 90 90 90[ ]+fcom[ ]+QWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: dd 90 90 90 90 90[ ]+fst[ ]+QWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: de 90 90 90 90 90[ ]+ficom[ ]+WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: df 90 90 90 90 90[ ]+fist[ ]+WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: e0 90[ ]+loopne[ ]+(0x)?25c.* + *[0-9a-f]+: e1 90[ ]+loope[ ]+(0x)?25e.* + *[0-9a-f]+: e2 90[ ]+loop[ ]+(0x)?260.* + *[0-9a-f]+: e3 90[ ]+jecxz[ ]+(0x)?262.* + *[0-9a-f]+: e4 90[ ]+in[ ]+al,0x90 + *[0-9a-f]+: e5 90[ ]+in[ ]+eax,0x90 + *[0-9a-f]+: e6 90[ ]+out[ ]+0x90,al + *[0-9a-f]+: e7 90[ ]+out[ ]+0x90,eax + *[0-9a-f]+: e8 90 90 90 90[ ]+call[ ]+(0x)?9090936f.* + *[0-9a-f]+: e9 90 90 90 90[ ]+jmp[ ]+(0x)?90909374.* + *[0-9a-f]+: ea 90 90 90 90 90 90[ ]+jmp[ ]+0x9090:0x90909090 + *[0-9a-f]+: eb 90[ ]+jmp[ ]+(0x)?27d.* + *[0-9a-f]+: ec[ ]+in[ ]+al,dx + *[0-9a-f]+: ed[ ]+in[ ]+eax,dx + *[0-9a-f]+: ee[ ]+out[ ]+dx,al + *[0-9a-f]+: ef[ ]+out[ ]+dx,eax + *[0-9a-f]+: f4[ ]+hlt[ ]* + *[0-9a-f]+: f5[ ]+cmc[ ]* + *[0-9a-f]+: f6 90 90 90 90 90[ ]+not[ ]+BYTE PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: f7 90 90 90 90 90[ ]+not[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: f8[ ]+clc[ ]* + *[0-9a-f]+: f9[ ]+stc[ ]* + *[0-9a-f]+: fa[ ]+cli[ ]* + *[0-9a-f]+: fb[ ]+sti[ ]* + *[0-9a-f]+: fc[ ]+cld[ ]* + *[0-9a-f]+: fd[ ]+std[ ]* + *[0-9a-f]+: ff 90 90 90 90 90[ ]+call[ ]+DWORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtd[ ]+\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+lar[ ]+edx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsl[ ]+edx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 06[ ]+clts[ ]* + *[0-9a-f]+: 0f 08[ ]+invd[ ]* + *[0-9a-f]+: 0f 09[ ]+wbinvd[ ]* + *[0-9a-f]+: 0f 0b[ ]+ud2a[ ]* + *[0-9a-f]+: 0f 20 d0[ ]+mov[ ]+eax,cr2 + *[0-9a-f]+: 0f 21 d0[ ]+mov[ ]+eax,db2 + *[0-9a-f]+: 0f 22 d0[ ]+mov[ ]+cr2,eax + *[0-9a-f]+: 0f 23 d0[ ]+mov[ ]+db2,eax + *[0-9a-f]+: 0f 24 d0[ ]+mov[ ]+eax,tr2 + *[0-9a-f]+: 0f 26 d0[ ]+mov[ ]+tr2,eax + *[0-9a-f]+: 0f 30[ ]+wrmsr[ ]* + *[0-9a-f]+: 0f 31[ ]+rdtsc[ ]* + *[0-9a-f]+: 0f 32[ ]+rdmsr[ ]* + *[0-9a-f]+: 0f 33[ ]+rdpmc[ ]* + *[0-9a-f]+: 0f 40 90 90 90 90 90[ ]+cmovo[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 41 90 90 90 90 90[ ]+cmovno[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 42 90 90 90 90 90[ ]+cmovb[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 43 90 90 90 90 90[ ]+cmovae[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 44 90 90 90 90 90[ ]+cmove[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 45 90 90 90 90 90[ ]+cmovne[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 46 90 90 90 90 90[ ]+cmovbe[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 47 90 90 90 90 90[ ]+cmova[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 48 90 90 90 90 90[ ]+cmovs[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 49 90 90 90 90 90[ ]+cmovns[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4a 90 90 90 90 90[ ]+cmovp[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4b 90 90 90 90 90[ ]+cmovnp[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4c 90 90 90 90 90[ ]+cmovl[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4d 90 90 90 90 90[ ]+cmovge[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4e 90 90 90 90 90[ ]+cmovle[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 4f 90 90 90 90 90[ ]+cmovg[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 60 90 90 90 90 90[ ]+punpcklbw[ ]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 61 90 90 90 90 90[ ]+punpcklwd[ ]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 62 90 90 90 90 90[ ]+punpckldq[ ]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 63 90 90 90 90 90[ ]+packsswb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 64 90 90 90 90 90[ ]+pcmpgtb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 65 90 90 90 90 90[ ]+pcmpgtw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 66 90 90 90 90 90[ ]+pcmpgtd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 67 90 90 90 90 90[ ]+packuswb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 68 90 90 90 90 90[ ]+punpckhbw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 69 90 90 90 90 90[ ]+punpckhwd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 6a 90 90 90 90 90[ ]+punpckhdq[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 6b 90 90 90 90 90[ ]+packssdw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 6e 90 90 90 90 90[ ]+movd[ ]+mm2,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 6f 90 90 90 90 90[ ]+movq[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 71 d0 90[ ]+psrlw[ ]+mm0,0x90 + *[0-9a-f]+: 0f 72 d0 90[ ]+psrld[ ]+mm0,0x90 + *[0-9a-f]+: 0f 73 d0 90[ ]+psrlq[ ]+mm0,0x90 + *[0-9a-f]+: 0f 74 90 90 90 90 90[ ]+pcmpeqb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 75 90 90 90 90 90[ ]+pcmpeqw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 76 90 90 90 90 90[ ]+pcmpeqd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 77[ ]+emms[ ]* + *[0-9a-f]+: 0f 7e 90 90 90 90 90[ ]+movd[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],mm2 + *[0-9a-f]+: 0f 7f 90 90 90 90 90[ ]+movq[ ]+(QWORD PTR )?\[eax-0x6f6f6f70\],mm2 + *[0-9a-f]+: 0f 80 90 90 90 90[ ]+jo[ ]+909094e2 <foo\+0x909094e2> + *[0-9a-f]+: 0f 81 90 90 90 90[ ]+jno[ ]+909094e8 <foo\+0x909094e8> + *[0-9a-f]+: 0f 82 90 90 90 90[ ]+jb[ ]+909094ee <foo\+0x909094ee> + *[0-9a-f]+: 0f 83 90 90 90 90[ ]+jae[ ]+909094f4 <foo\+0x909094f4> + *[0-9a-f]+: 0f 84 90 90 90 90[ ]+je[ ]+909094fa <foo\+0x909094fa> + *[0-9a-f]+: 0f 85 90 90 90 90[ ]+jne[ ]+90909500 <foo\+0x90909500> + *[0-9a-f]+: 0f 86 90 90 90 90[ ]+jbe[ ]+90909506 <foo\+0x90909506> + *[0-9a-f]+: 0f 87 90 90 90 90[ ]+ja[ ]+9090950c <foo\+0x9090950c> + *[0-9a-f]+: 0f 88 90 90 90 90[ ]+js[ ]+90909512 <foo\+0x90909512> + *[0-9a-f]+: 0f 89 90 90 90 90[ ]+jns[ ]+90909518 <foo\+0x90909518> + *[0-9a-f]+: 0f 8a 90 90 90 90[ ]+jp[ ]+9090951e <foo\+0x9090951e> + *[0-9a-f]+: 0f 8b 90 90 90 90[ ]+jnp[ ]+90909524 <foo\+0x90909524> + *[0-9a-f]+: 0f 8c 90 90 90 90[ ]+jl[ ]+9090952a <foo\+0x9090952a> + *[0-9a-f]+: 0f 8d 90 90 90 90[ ]+jge[ ]+90909530 <foo\+0x90909530> + *[0-9a-f]+: 0f 8e 90 90 90 90[ ]+jle[ ]+90909536 <foo\+0x90909536> + *[0-9a-f]+: 0f 8f 90 90 90 90[ ]+jg[ ]+9090953c <foo\+0x9090953c> + *[0-9a-f]+: 0f 90 80 90 90 90 90[ ]+seto[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 91 80 90 90 90 90[ ]+setno[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 92 80 90 90 90 90[ ]+setb[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 93 80 90 90 90 90[ ]+setae[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 94 80 90 90 90 90[ ]+sete[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 95 80 90 90 90 90[ ]+setne[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 96 80 90 90 90 90[ ]+setbe[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 97 80 90 90 90 90[ ]+seta[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 98 80 90 90 90 90[ ]+sets[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 99 80 90 90 90 90[ ]+setns[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9a 80 90 90 90 90[ ]+setp[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9b 80 90 90 90 90[ ]+setnp[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9c 80 90 90 90 90[ ]+setl[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9d 80 90 90 90 90[ ]+setge[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9e 80 90 90 90 90[ ]+setle[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f 9f 80 90 90 90 90[ ]+setg[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f a0[ ]+push[ ]+fs + *[0-9a-f]+: 0f a1[ ]+pop[ ]+fs + *[0-9a-f]+: 0f a2[ ]+cpuid[ ]* + *[0-9a-f]+: 0f a3 90 90 90 90 90[ ]+bt[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f a4 90 90 90 90 90 90[ ]+shld[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,0x90 + *[0-9a-f]+: 0f a5 90 90 90 90 90[ ]+shld[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,cl + *[0-9a-f]+: 0f a8[ ]+push[ ]+gs + *[0-9a-f]+: 0f a9[ ]+pop[ ]+gs + *[0-9a-f]+: 0f aa[ ]+rsm[ ]* + *[0-9a-f]+: 0f ab 90 90 90 90 90[ ]+bts[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f ac 90 90 90 90 90 90[ ]+shrd[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,0x90 + *[0-9a-f]+: 0f ad 90 90 90 90 90[ ]+shrd[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx,cl + *[0-9a-f]+: 0f af 90 90 90 90 90[ ]+imul[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b0 90 90 90 90 90[ ]+cmpxchg (BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 0f b1 90 90 90 90 90[ ]+cmpxchg (DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f b2 90 90 90 90 90[ ]+lss[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b3 90 90 90 90 90[ ]+btr[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f b4 90 90 90 90 90[ ]+lfs[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgs[ ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzx[ ]+edx,BYTE PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzx[ ]+edx,WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f b9[ ]+ud2b[ ]* + *[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btc[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsf[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsr[ ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f be 90 90 90 90 90[ ]+movsx[ ]+edx,BYTE PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f bf 90 90 90 90 90[ ]+movsx[ ]+edx,WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f c0 90 90 90 90 90[ ]+xadd[ ]+(BYTE PTR )?\[eax-0x6f6f6f70\],dl + *[0-9a-f]+: 0f c1 90 90 90 90 90[ ]+xadd[ ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx + *[0-9a-f]+: 0f c8[ ]+bswap[ ]+eax + *[0-9a-f]+: 0f c9[ ]+bswap[ ]+ecx + *[0-9a-f]+: 0f ca[ ]+bswap[ ]+edx + *[0-9a-f]+: 0f cb[ ]+bswap[ ]+ebx + *[0-9a-f]+: 0f cc[ ]+bswap[ ]+esp + *[0-9a-f]+: 0f cd[ ]+bswap[ ]+ebp + *[0-9a-f]+: 0f ce[ ]+bswap[ ]+esi + *[0-9a-f]+: 0f cf[ ]+bswap[ ]+edi + *[0-9a-f]+: 0f d1 90 90 90 90 90[ ]+psrlw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f d2 90 90 90 90 90[ ]+psrld[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f d3 90 90 90 90 90[ ]+psrlq[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f d5 90 90 90 90 90[ ]+pmullw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f d8 90 90 90 90 90[ ]+psubusb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f d9 90 90 90 90 90[ ]+psubusw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f db 90 90 90 90 90[ ]+pand[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f dc 90 90 90 90 90[ ]+paddusb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f dd 90 90 90 90 90[ ]+paddusw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f df 90 90 90 90 90[ ]+pandn[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f e1 90 90 90 90 90[ ]+psraw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f e2 90 90 90 90 90[ ]+psrad[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f e5 90 90 90 90 90[ ]+pmulhw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f e8 90 90 90 90 90[ ]+psubsb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f e9 90 90 90 90 90[ ]+psubsw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f eb 90 90 90 90 90[ ]+por[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f ec 90 90 90 90 90[ ]+paddsb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f ed 90 90 90 90 90[ ]+paddsw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f ef 90 90 90 90 90[ ]+pxor[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f1 90 90 90 90 90[ ]+psllw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f2 90 90 90 90 90[ ]+pslld[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f3 90 90 90 90 90[ ]+psllq[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f5 90 90 90 90 90[ ]+pmaddwd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f8 90 90 90 90 90[ ]+psubb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f f9 90 90 90 90 90[ ]+psubw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f fa 90 90 90 90 90[ ]+psubd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f fc 90 90 90 90 90[ ]+paddb[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f fd 90 90 90 90 90[ ]+paddw[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 0f fe 90 90 90 90 90[ ]+paddd[ ]+mm2,(QWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 01 90 90 90 90 90[ ]+add[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 03 90 90 90 90 90[ ]+add[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 05 90 90[ ]+add[ ]+ax,0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 06[ ]+push[ ]+es + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 07[ ]+pop[ ]+es + *[0-9a-f]+: 66 09 90 90 90 90 90[ ]+or[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0b 90 90 90 90 90[ ]+or[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0d 90 90[ ]+or[ ]+ax,0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 0e[ ]+push[ ]+cs + *[0-9a-f]+: 66 11 90 90 90 90 90[ ]+adc[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 13 90 90 90 90 90[ ]+adc[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 15 90 90[ ]+adc[ ]+ax,0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 16[ ]+push[ ]+ss + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 17[ ]+pop[ ]+ss + *[0-9a-f]+: 66 19 90 90 90 90 90[ ]+sbb[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 1b 90 90 90 90 90[ ]+sbb[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 1d 90 90[ ]+sbb[ ]+ax,0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 1e[ ]+push[ ]+ds + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 1f[ ]+pop[ ]+ds + *[0-9a-f]+: 66 21 90 90 90 90 90[ ]+and[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 23 90 90 90 90 90[ ]+and[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 25 90 90[ ]+and[ ]+ax,0x9090 + *[0-9a-f]+: 66 29 90 90 90 90 90[ ]+sub[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 2b 90 90 90 90 90[ ]+sub[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 2d 90 90[ ]+sub[ ]+ax,0x9090 + *[0-9a-f]+: 66 31 90 90 90 90 90[ ]+xor[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 33 90 90 90 90 90[ ]+xor[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 35 90 90[ ]+xor[ ]+ax,0x9090 + *[0-9a-f]+: 66 39 90 90 90 90 90[ ]+cmp[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 3b 90 90 90 90 90[ ]+cmp[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 3d 90 90[ ]+cmp[ ]+ax,0x9090 + *[0-9a-f]+: 66 40[ ]+inc[ ]+ax + *[0-9a-f]+: 66 41[ ]+inc[ ]+cx + *[0-9a-f]+: 66 42[ ]+inc[ ]+dx + *[0-9a-f]+: 66 43[ ]+inc[ ]+bx + *[0-9a-f]+: 66 44[ ]+inc[ ]+sp + *[0-9a-f]+: 66 45[ ]+inc[ ]+bp + *[0-9a-f]+: 66 46[ ]+inc[ ]+si + *[0-9a-f]+: 66 47[ ]+inc[ ]+di + *[0-9a-f]+: 66 48[ ]+dec[ ]+ax + *[0-9a-f]+: 66 49[ ]+dec[ ]+cx + *[0-9a-f]+: 66 4a[ ]+dec[ ]+dx + *[0-9a-f]+: 66 4b[ ]+dec[ ]+bx + *[0-9a-f]+: 66 4c[ ]+dec[ ]+sp + *[0-9a-f]+: 66 4d[ ]+dec[ ]+bp + *[0-9a-f]+: 66 4e[ ]+dec[ ]+si + *[0-9a-f]+: 66 4f[ ]+dec[ ]+di + *[0-9a-f]+: 66 50[ ]+push[ ]+ax + *[0-9a-f]+: 66 51[ ]+push[ ]+cx + *[0-9a-f]+: 66 52[ ]+push[ ]+dx + *[0-9a-f]+: 66 53[ ]+push[ ]+bx + *[0-9a-f]+: 66 54[ ]+push[ ]+sp + *[0-9a-f]+: 66 55[ ]+push[ ]+bp + *[0-9a-f]+: 66 56[ ]+push[ ]+si + *[0-9a-f]+: 66 57[ ]+push[ ]+di + *[0-9a-f]+: 66 58[ ]+pop[ ]+ax + *[0-9a-f]+: 66 59[ ]+pop[ ]+cx + *[0-9a-f]+: 66 5a[ ]+pop[ ]+dx + *[0-9a-f]+: 66 5b[ ]+pop[ ]+bx + *[0-9a-f]+: 66 5c[ ]+pop[ ]+sp + *[0-9a-f]+: 66 5d[ ]+pop[ ]+bp + *[0-9a-f]+: 66 5e[ ]+pop[ ]+si + *[0-9a-f]+: 66 5f[ ]+pop[ ]+di + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 60[ ]+pusha[ ]* + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 61[ ]+popa[ ]* + *[0-9a-f]+: 66 62 90 90 90 90 90[ ]+bound[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 68 90 90[ ]+push[ ]+0x9090 + *[0-9a-f]+: 66 69 90 90 90 90 90 90 90[ ]+imul[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\],0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 6a 90[ ]+push[ ]+0xffffff90 + *[0-9a-f]+: 66 6b 90 90 90 90 90 90[ ]+imul[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\],0xffffff90 + *[0-9a-f]+: 66 6d[ ]+ins[ ]+WORD PTR es:\[edi\],dx + *[0-9a-f]+: 66 6f[ ]+outs[ ]+dx,WORD PTR ds:\[esi\] + *[0-9a-f]+: 66 81 90 90 90 90 90 90 90[ ]+adc[ ]+WORD PTR \[eax-0x6f6f6f70\],0x9090 + *[0-9a-f]+: 66 83 90 90 90 90 90 90[ ]+adc[ ]+WORD PTR \[eax-0x6f6f6f70\],0xffffff90 + *[0-9a-f]+: 66 85 90 90 90 90 90[ ]+test[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 87 90 90 90 90 90[ ]+xchg[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 89 90 90 90 90 90[ ]+mov[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 8b 90 90 90 90 90[ ]+mov[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 8c 90 90 90 90 90[ ]+mov[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],ss + *[0-9a-f]+: 66 8d 90 90 90 90 90[ ]+lea[ ]+dx,\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 8f 80 90 90 90 90[ ]+pop[ ]+WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 91[ ]+xchg[ ]+cx,ax + *[0-9a-f]+: 66 92[ ]+xchg[ ]+dx,ax + *[0-9a-f]+: 66 93[ ]+xchg[ ]+bx,ax + *[0-9a-f]+: 66 94[ ]+xchg[ ]+sp,ax + *[0-9a-f]+: 66 95[ ]+xchg[ ]+bp,ax + *[0-9a-f]+: 66 96[ ]+xchg[ ]+si,ax + *[0-9a-f]+: 66 97[ ]+xchg[ ]+di,ax + *[0-9a-f]+: 66 98[ ]+cbw[ ]* + *[0-9a-f]+: 66 99[ ]+cwd[ ]* + *[0-9a-f]+: 66 9a 90 90 90 90[ ]+call[ ]+0x9090:0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 9c[ ]+pushf[ ]* + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 9d[ ]+popf[ ]* + *[0-9a-f]+: 66 a1 90 90 90 90[ ]+mov[ ]+ax,ds:0x90909090 + *[0-9a-f]+: 66 a3 90 90 90 90[ ]+mov[ ]+ds:0x90909090,ax + *[0-9a-f]+: 66 a5[ ]+movs[ ]+WORD PTR es:\[edi\],(WORD PTR )?ds:\[esi\] + *[0-9a-f]+: 66 a7[ ]+cmps[ ]+WORD PTR ds:\[esi\],(WORD PTR )?es:\[edi\] + *[0-9a-f]+: 66 a9 90 90[ ]+test[ ]+ax,0x9090 + *[0-9a-f]+: 66 ab[ ]+stos[ ]+WORD PTR es:\[edi\](,ax)? + *[0-9a-f]+: 66 ad[ ]+lods[ ]+(ax,)?WORD PTR ds:\[esi\] + *[0-9a-f]+: 66 af[ ]+scas[ ]+(ax,)?WORD PTR es:\[edi\] + *[0-9a-f]+: 66 b8 90 90[ ]+mov[ ]+ax,0x9090 + *[0-9a-f]+: 66 b9 90 90[ ]+mov[ ]+cx,0x9090 + *[0-9a-f]+: 66 ba 90 90[ ]+mov[ ]+dx,0x9090 + *[0-9a-f]+: 66 bb 90 90[ ]+mov[ ]+bx,0x9090 + *[0-9a-f]+: 66 bc 90 90[ ]+mov[ ]+sp,0x9090 + *[0-9a-f]+: 66 bd 90 90[ ]+mov[ ]+bp,0x9090 + *[0-9a-f]+: 66 be 90 90[ ]+mov[ ]+si,0x9090 + *[0-9a-f]+: 66 bf 90 90[ ]+mov[ ]+di,0x9090 + *[0-9a-f]+: 66 c1 90 90 90 90 90 90[ ]+rcl[ ]+WORD PTR \[eax-0x6f6f6f70\],0x90 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: c2 90 90[ ]+ret[ ]+0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: c3[ ]+ret[ ]* + *[0-9a-f]+: 66 c4 90 90 90 90 90[ ]+les[ ]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 c5 90 90 90 90 90[ ]+lds[ ]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 c7 80 90 90 90 90 90 90[ ]+mov[ ]+WORD PTR \[eax-0x6f6f6f70\],0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: c8 90 90 90[ ]+enter[ ]+0x9090,0x90 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: c9[ ]+leave[ ]* + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: ca 90 90[ ]+lret[ ]+0x9090 + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: cb[ ]+lret[ ]* + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: cf[ ]+iret[ ]* + *[0-9a-f]+: 66 d1 90 90 90 90 90[ ]+rcl[ ]+WORD PTR \[eax-0x6f6f6f70\],1 + *[0-9a-f]+: 66 d3 90 90 90 90 90[ ]+rcl[ ]+WORD PTR \[eax-0x6f6f6f70\],cl + *[0-9a-f]+: 66 e5 90[ ]+in[ ]+ax,0x90 + *[0-9a-f]+: 66 e7 90[ ]+out[ ]+0x90,ax + *[0-9a-f]+: 66 e8 8f 90[ ]+call[ ]+(0x)?9918.* + *[0-9a-f]+: 66 ea 90 90 90 90[ ]+jmp[ ]+0x9090:0x9090 + *[0-9a-f]+: 66 ed[ ]+in[ ]+ax,dx + *[0-9a-f]+: 66 ef[ ]+out[ ]+dx,ax + *[0-9a-f]+: 66 f7 90 90 90 90 90[ ]+not[ ]+WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 ff 90 90 90 90 90[ ]+call[ ]+WORD PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 02 90 90 90 90 90[ ]+lar[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 03 90 90 90 90 90[ ]+lsl[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 40 90 90 90 90 90[ ]+cmovo[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 41 90 90 90 90 90[ ]+cmovno[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 42 90 90 90 90 90[ ]+cmovb[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 43 90 90 90 90 90[ ]+cmovae[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 44 90 90 90 90 90[ ]+cmove[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 45 90 90 90 90 90[ ]+cmovne[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 46 90 90 90 90 90[ ]+cmovbe[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 47 90 90 90 90 90[ ]+cmova[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 48 90 90 90 90 90[ ]+cmovs[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 49 90 90 90 90 90[ ]+cmovns[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4a 90 90 90 90 90[ ]+cmovp[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4b 90 90 90 90 90[ ]+cmovnp[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4c 90 90 90 90 90[ ]+cmovl[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4d 90 90 90 90 90[ ]+cmovge[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4e 90 90 90 90 90[ ]+cmovle[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f 4f 90 90 90 90 90[ ]+cmovg[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 0f a0[ ]+push[ ]+fs + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 0f a1[ ]+pop[ ]+fs + *[0-9a-f]+: 66 0f a3 90 90 90 90 90[ ]+bt[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0f a4 90 90 90 90 90 90[ ]+shld[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,0x90 + *[0-9a-f]+: 66 0f a5 90 90 90 90 90[ ]+shld[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,cl + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 0f a8[ ]+push[ ]+gs + *[0-9a-f]+: 66[ ]+data16 + *[0-9a-f]+: 0f a9[ ]+pop[ ]+gs + *[0-9a-f]+: 66 0f ab 90 90 90 90 90[ ]+bts[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0f ac 90 90 90 90 90 90[ ]+shrd[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,0x90 + *[0-9a-f]+: 66 0f ad 90 90 90 90 90[ ]+shrd[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx,cl + *[0-9a-f]+: 66 0f af 90 90 90 90 90[ ]+imul[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f b1 90 90 90 90 90[ ]+cmpxchg (WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0f b2 90 90 90 90 90[ ]+lss[ ]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f b3 90 90 90 90 90[ ]+btr[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0f b4 90 90 90 90 90[ ]+lfs[ ]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f b5 90 90 90 90 90[ ]+lgs[ ]+dx,(DWORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f b6 90 90 90 90 90[ ]+movzx[ ]+dx,BYTE PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f bb 90 90 90 90 90[ ]+btc[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 0f bc 90 90 90 90 90[ ]+bsf[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f bd 90 90 90 90 90[ ]+bsr[ ]+dx,(WORD PTR )?\[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f be 90 90 90 90 90[ ]+movsx[ ]+dx,BYTE PTR \[eax-0x6f6f6f70\] + *[0-9a-f]+: 66 0f c1 90 90 90 90 90[ ]+xadd[ ]+(WORD PTR )?\[eax-0x6f6f6f70\],dx + *[0-9a-f]+: 66 90[ ]+xchg[ ]+ax,ax + *[0-9a-f]+: 0f 00 c0[ ]+sldt[ ]+eax + *[0-9a-f]+: 66 0f 00 c0[ ]+sldt[ ]+ax + *[0-9a-f]+: 0f 00 00[ ]+sldt[ ]+(WORD PTR )?\[eax\] + *[0-9a-f]+: 0f 01 e0[ ]+smsw[ ]+eax + *[0-9a-f]+: 66 0f 01 e0[ ]+smsw[ ]+ax + *[0-9a-f]+: 0f 01 20[ ]+smsw[ ]+(WORD PTR )?\[eax\] + *[0-9a-f]+: 0f 00 c8[ ]+str[ ]+eax + *[0-9a-f]+: 66 0f 00 c8[ ]+str[ ]+ax + *[0-9a-f]+: 0f 00 08[ ]+str[ ]+(WORD PTR )?\[eax\] + *[0-9a-f]+: 0f ad d0 [ ]*shrd[ ]+eax,edx,cl + *[0-9a-f]+: 0f a5 d0 [ ]*shld[ ]+eax,edx,cl + *[0-9a-f]+: 85 c3 [ ]*test[ ]+ebx,eax + *[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx + *[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx +#pass + \.\.\. diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d new file mode 100644 index 000000000000..9db7e671135d --- /dev/null +++ b/gas/testsuite/gas/i386/opcode-suffix.d @@ -0,0 +1,591 @@ +#source: opcode.s +#as: -J +#objdump: -dwMsuffix +#name: i386 opcodes (w/ suffix) + +.*: +file format .* + +Disassembly of section .text: + +0+000 <foo>: + *[0-9a-f]+: 00 90 90 90 90 90[ ]+addb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 01 90 90 90 90 90[ ]+addl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 02 90 90 90 90 90[ ]+addb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 03 90 90 90 90 90[ ]+addl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 04 90[ ]+addb[ ]+\$0x90,%al + *[0-9a-f]+: 05 90 90 90 90[ ]+addl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 06[ ]+pushl[ ]+%es + *[0-9a-f]+: 07[ ]+popl[ ]+%es + *[0-9a-f]+: 08 90 90 90 90 90[ ]+orb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 09 90 90 90 90 90[ ]+orl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0a 90 90 90 90 90[ ]+orb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 0b 90 90 90 90 90[ ]+orl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0c 90[ ]+orb[ ]+\$0x90,%al + *[0-9a-f]+: 0d 90 90 90 90[ ]+orl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 0e[ ]+pushl[ ]+%cs + *[0-9a-f]+: 10 90 90 90 90 90[ ]+adcb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 11 90 90 90 90 90[ ]+adcl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 12 90 90 90 90 90[ ]+adcb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 13 90 90 90 90 90[ ]+adcl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 14 90[ ]+adcb[ ]+\$0x90,%al + *[0-9a-f]+: 15 90 90 90 90[ ]+adcl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 16[ ]+pushl[ ]+%ss + *[0-9a-f]+: 17[ ]+popl[ ]+%ss + *[0-9a-f]+: 18 90 90 90 90 90[ ]+sbbb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 19 90 90 90 90 90[ ]+sbbl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 1a 90 90 90 90 90[ ]+sbbb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 1b 90 90 90 90 90[ ]+sbbl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 1c 90[ ]+sbbb[ ]+\$0x90,%al + *[0-9a-f]+: 1d 90 90 90 90[ ]+sbbl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 1e[ ]+pushl[ ]+%ds + *[0-9a-f]+: 1f[ ]+popl[ ]+%ds + *[0-9a-f]+: 20 90 90 90 90 90[ ]+andb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 21 90 90 90 90 90[ ]+andl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 22 90 90 90 90 90[ ]+andb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 23 90 90 90 90 90[ ]+andl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 24 90[ ]+andb[ ]+\$0x90,%al + *[0-9a-f]+: 25 90 90 90 90[ ]+andl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 27[ ]+daa[ ]+ + *[0-9a-f]+: 28 90 90 90 90 90[ ]+subb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 29 90 90 90 90 90[ ]+subl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 2a 90 90 90 90 90[ ]+subb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 2b 90 90 90 90 90[ ]+subl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 2c 90[ ]+subb[ ]+\$0x90,%al + *[0-9a-f]+: 2d 90 90 90 90[ ]+subl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 2f[ ]+das[ ]+ + *[0-9a-f]+: 30 90 90 90 90 90[ ]+xorb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 31 90 90 90 90 90[ ]+xorl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 32 90 90 90 90 90[ ]+xorb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 33 90 90 90 90 90[ ]+xorl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 34 90[ ]+xorb[ ]+\$0x90,%al + *[0-9a-f]+: 35 90 90 90 90[ ]+xorl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 37[ ]+aaa[ ]+ + *[0-9a-f]+: 38 90 90 90 90 90[ ]+cmpb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 39 90 90 90 90 90[ ]+cmpl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 3a 90 90 90 90 90[ ]+cmpb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 3b 90 90 90 90 90[ ]+cmpl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 3c 90[ ]+cmpb[ ]+\$0x90,%al + *[0-9a-f]+: 3d 90 90 90 90[ ]+cmpl[ ]+\$0x90909090,%eax + *[0-9a-f]+: 3f[ ]+aas[ ]+ + *[0-9a-f]+: 40[ ]+incl[ ]+%eax + *[0-9a-f]+: 41[ ]+incl[ ]+%ecx + *[0-9a-f]+: 42[ ]+incl[ ]+%edx + *[0-9a-f]+: 43[ ]+incl[ ]+%ebx + *[0-9a-f]+: 44[ ]+incl[ ]+%esp + *[0-9a-f]+: 45[ ]+incl[ ]+%ebp + *[0-9a-f]+: 46[ ]+incl[ ]+%esi + *[0-9a-f]+: 47[ ]+incl[ ]+%edi + *[0-9a-f]+: 48[ ]+decl[ ]+%eax + *[0-9a-f]+: 49[ ]+decl[ ]+%ecx + *[0-9a-f]+: 4a[ ]+decl[ ]+%edx + *[0-9a-f]+: 4b[ ]+decl[ ]+%ebx + *[0-9a-f]+: 4c[ ]+decl[ ]+%esp + *[0-9a-f]+: 4d[ ]+decl[ ]+%ebp + *[0-9a-f]+: 4e[ ]+decl[ ]+%esi + *[0-9a-f]+: 4f[ ]+decl[ ]+%edi + *[0-9a-f]+: 50[ ]+pushl[ ]+%eax + *[0-9a-f]+: 51[ ]+pushl[ ]+%ecx + *[0-9a-f]+: 52[ ]+pushl[ ]+%edx + *[0-9a-f]+: 53[ ]+pushl[ ]+%ebx + *[0-9a-f]+: 54[ ]+pushl[ ]+%esp + *[0-9a-f]+: 55[ ]+pushl[ ]+%ebp + *[0-9a-f]+: 56[ ]+pushl[ ]+%esi + *[0-9a-f]+: 57[ ]+pushl[ ]+%edi + *[0-9a-f]+: 58[ ]+popl[ ]+%eax + *[0-9a-f]+: 59[ ]+popl[ ]+%ecx + *[0-9a-f]+: 5a[ ]+popl[ ]+%edx + *[0-9a-f]+: 5b[ ]+popl[ ]+%ebx + *[0-9a-f]+: 5c[ ]+popl[ ]+%esp + *[0-9a-f]+: 5d[ ]+popl[ ]+%ebp + *[0-9a-f]+: 5e[ ]+popl[ ]+%esi + *[0-9a-f]+: 5f[ ]+popl[ ]+%edi + *[0-9a-f]+: 60[ ]+pushal + *[0-9a-f]+: 61[ ]+popal[ ]+ + *[0-9a-f]+: 62 90 90 90 90 90[ ]+boundl %edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 63 90 90 90 90 90[ ]+arpl[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 68 90 90 90 90[ ]+pushl[ ]+\$0x90909090 + *[0-9a-f]+: 69 90 90 90 90 90 90 90 90 90[ ]+imull[ ]+\$0x90909090,-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 6a 90[ ]+pushl[ ]+\$0xffffff90 + *[0-9a-f]+: 6b 90 90 90 90 90 90[ ]+imull[ ]+\$0xffffff90,-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 6c[ ]+insb[ ]+\(%dx\),%es:\(%edi\) + *[0-9a-f]+: 6d[ ]+insl[ ]+\(%dx\),%es:\(%edi\) + *[0-9a-f]+: 6e[ ]+outsb[ ]+%ds:\(%esi\),\(%dx\) + *[0-9a-f]+: 6f[ ]+outsl[ ]+%ds:\(%esi\),\(%dx\) + *[0-9a-f]+: 70 90[ ]+jo[ ]+(0x)?df.* + *[0-9a-f]+: 71 90[ ]+jno[ ]+(0x)?e1.* + *[0-9a-f]+: 72 90[ ]+jb[ ]+(0x)?e3.* + *[0-9a-f]+: 73 90[ ]+jae[ ]+(0x)?e5.* + *[0-9a-f]+: 74 90[ ]+je[ ]+(0x)?e7.* + *[0-9a-f]+: 75 90[ ]+jne[ ]+(0x)?e9.* + *[0-9a-f]+: 76 90[ ]+jbe[ ]+(0x)?eb.* + *[0-9a-f]+: 77 90[ ]+ja[ ]+(0x)?ed.* + *[0-9a-f]+: 78 90[ ]+js[ ]+(0x)?ef.* + *[0-9a-f]+: 79 90[ ]+jns[ ]+(0x)?f1.* + *[0-9a-f]+: 7a 90[ ]+jp[ ]+(0x)?f3.* + *[0-9a-f]+: 7b 90[ ]+jnp[ ]+(0x)?f5.* + *[0-9a-f]+: 7c 90[ ]+jl[ ]+(0x)?f7.* + *[0-9a-f]+: 7d 90[ ]+jge[ ]+(0x)?f9.* + *[0-9a-f]+: 7e 90[ ]+jle[ ]+(0x)?fb.* + *[0-9a-f]+: 7f 90[ ]+jg[ ]+(0x)?fd.* + *[0-9a-f]+: 80 90 90 90 90 90 90[ ]+adcb[ ]+\$0x90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 81 90 90 90 90 90 90 90 90 90[ ]+adcl[ ]+\$0x90909090,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 83 90 90 90 90 90 90[ ]+adcl[ ]+\$0xffffff90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 84 90 90 90 90 90[ ]+testb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 85 90 90 90 90 90[ ]+testl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 86 90 90 90 90 90[ ]+xchgb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 87 90 90 90 90 90[ ]+xchgl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 88 90 90 90 90 90[ ]+movb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 89 90 90 90 90 90[ ]+movl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 8a 90 90 90 90 90[ ]+movb[ ]+-0x6f6f6f70\(%eax\),%dl + *[0-9a-f]+: 8b 90 90 90 90 90[ ]+movl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 8c 90 90 90 90 90[ ]+movw[ ]+%ss,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 8d 90 90 90 90 90[ ]+leal[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 8e 90 90 90 90 90[ ]+movw[ ]+-0x6f6f6f70\(%eax\),%ss + *[0-9a-f]+: 8f 80 90 90 90 90[ ]+popl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 90[ ]+nop[ ]+ + *[0-9a-f]+: 91[ ]+xchgl[ ]+%eax,%ecx + *[0-9a-f]+: 92[ ]+xchgl[ ]+%eax,%edx + *[0-9a-f]+: 93[ ]+xchgl[ ]+%eax,%ebx + *[0-9a-f]+: 94[ ]+xchgl[ ]+%eax,%esp + *[0-9a-f]+: 95[ ]+xchgl[ ]+%eax,%ebp + *[0-9a-f]+: 96[ ]+xchgl[ ]+%eax,%esi + *[0-9a-f]+: 97[ ]+xchgl[ ]+%eax,%edi + *[0-9a-f]+: 98[ ]+cwtl[ ]+ + *[0-9a-f]+: 99[ ]+cltd[ ]+ + *[0-9a-f]+: 9a 90 90 90 90 90 90[ ]+lcalll \$0x9090,\$0x90909090 + *[0-9a-f]+: 9b[ ]+fwait + *[0-9a-f]+: 9c[ ]+pushfl + *[0-9a-f]+: 9d[ ]+popfl[ ]+ + *[0-9a-f]+: 9e[ ]+sahf[ ]+ + *[0-9a-f]+: 9f[ ]+lahf[ ]+ + *[0-9a-f]+: a0 90 90 90 90[ ]+movb[ ]+0x90909090,%al + *[0-9a-f]+: a1 90 90 90 90[ ]+movl[ ]+0x90909090,%eax + *[0-9a-f]+: a2 90 90 90 90[ ]+movb[ ]+%al,0x90909090 + *[0-9a-f]+: a3 90 90 90 90[ ]+movl[ ]+%eax,0x90909090 + *[0-9a-f]+: a4[ ]+movsb[ ]+%ds:\(%esi\),%es:\(%edi\) + *[0-9a-f]+: a5[ ]+movsl[ ]+%ds:\(%esi\),%es:\(%edi\) + *[0-9a-f]+: a6[ ]+cmpsb[ ]+%es:\(%edi\),%ds:\(%esi\) + *[0-9a-f]+: a7[ ]+cmpsl[ ]+%es:\(%edi\),%ds:\(%esi\) + *[0-9a-f]+: a8 90[ ]+testb[ ]+\$0x90,%al + *[0-9a-f]+: a9 90 90 90 90[ ]+testl[ ]+\$0x90909090,%eax + *[0-9a-f]+: aa[ ]+stosb[ ]+%al,%es:\(%edi\) + *[0-9a-f]+: ab[ ]+stosl[ ]+%eax,%es:\(%edi\) + *[0-9a-f]+: ac[ ]+lodsb[ ]+%ds:\(%esi\),%al + *[0-9a-f]+: ad[ ]+lodsl[ ]+%ds:\(%esi\),%eax + *[0-9a-f]+: ae[ ]+scasb[ ]+%es:\(%edi\),%al + *[0-9a-f]+: af[ ]+scasl[ ]+%es:\(%edi\),%eax + *[0-9a-f]+: b0 90[ ]+movb[ ]+\$0x90,%al + *[0-9a-f]+: b1 90[ ]+movb[ ]+\$0x90,%cl + *[0-9a-f]+: b2 90[ ]+movb[ ]+\$0x90,%dl + *[0-9a-f]+: b3 90[ ]+movb[ ]+\$0x90,%bl + *[0-9a-f]+: b4 90[ ]+movb[ ]+\$0x90,%ah + *[0-9a-f]+: b5 90[ ]+movb[ ]+\$0x90,%ch + *[0-9a-f]+: b6 90[ ]+movb[ ]+\$0x90,%dh + *[0-9a-f]+: b7 90[ ]+movb[ ]+\$0x90,%bh + *[0-9a-f]+: b8 90 90 90 90[ ]+movl[ ]+\$0x90909090,%eax + *[0-9a-f]+: b9 90 90 90 90[ ]+movl[ ]+\$0x90909090,%ecx + *[0-9a-f]+: ba 90 90 90 90[ ]+movl[ ]+\$0x90909090,%edx + *[0-9a-f]+: bb 90 90 90 90[ ]+movl[ ]+\$0x90909090,%ebx + *[0-9a-f]+: bc 90 90 90 90[ ]+movl[ ]+\$0x90909090,%esp + *[0-9a-f]+: bd 90 90 90 90[ ]+movl[ ]+\$0x90909090,%ebp + *[0-9a-f]+: be 90 90 90 90[ ]+movl[ ]+\$0x90909090,%esi + *[0-9a-f]+: bf 90 90 90 90[ ]+movl[ ]+\$0x90909090,%edi + *[0-9a-f]+: c0 90 90 90 90 90 90[ ]+rclb[ ]+\$0x90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: c1 90 90 90 90 90 90[ ]+rcll[ ]+\$0x90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: c2 90 90[ ]+retl[ ]+\$0x9090 + *[0-9a-f]+: c3[ ]+retl[ ]+ + *[0-9a-f]+: c4 90 90 90 90 90[ ]+lesl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: c5 90 90 90 90 90[ ]+ldsl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: c6 80 90 90 90 90 90[ ]+movb[ ]+\$0x90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: c7 80 90 90 90 90 90 90 90 90[ ]+movl[ ]+\$0x90909090,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: c8 90 90 90[ ]+enterl \$0x9090,\$0x90 + *[0-9a-f]+: c9[ ]+leavel + *[0-9a-f]+: ca 90 90[ ]+lretl[ ]+\$0x9090 + *[0-9a-f]+: cb[ ]+lretl[ ]+ + *[0-9a-f]+: cc[ ]+int3[ ]+ + *[0-9a-f]+: cd 90[ ]+int[ ]+\$0x90 + *[0-9a-f]+: ce[ ]+into[ ]+ + *[0-9a-f]+: cf[ ]+iretl[ ]+ + *[0-9a-f]+: d0 90 90 90 90 90[ ]+rclb[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: d1 90 90 90 90 90[ ]+rcll[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: d2 90 90 90 90 90[ ]+rclb[ ]+%cl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: d3 90 90 90 90 90[ ]+rcll[ ]+%cl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: d4 90[ ]+aam[ ]+\$0xffffff90 + *[0-9a-f]+: d5 90[ ]+aad[ ]+\$0xffffff90 + *[0-9a-f]+: d7[ ]+xlat[ ]+%ds:\(%ebx\) + *[0-9a-f]+: d8 90 90 90 90 90[ ]+fcoms[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: d9 90 90 90 90 90[ ]+fsts[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: da 90 90 90 90 90[ ]+ficoml -0x6f6f6f70\(%eax\) + *[0-9a-f]+: db 90 90 90 90 90[ ]+fistl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: dc 90 90 90 90 90[ ]+fcoml[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: dd 90 90 90 90 90[ ]+fstl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: de 90 90 90 90 90[ ]+ficom[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: df 90 90 90 90 90[ ]+fist[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: e0 90[ ]+loopnel (0x)?25c.* + *[0-9a-f]+: e1 90[ ]+loopel (0x)?25e.* + *[0-9a-f]+: e2 90[ ]+loopl[ ]+(0x)?260.* + *[0-9a-f]+: e3 90[ ]+jecxz[ ]+(0x)?262.* + *[0-9a-f]+: e4 90[ ]+inb[ ]+\$0x90,%al + *[0-9a-f]+: e5 90[ ]+inl[ ]+\$0x90,%eax + *[0-9a-f]+: e6 90[ ]+outb[ ]+%al,\$0x90 + *[0-9a-f]+: e7 90[ ]+outl[ ]+%eax,\$0x90 + *[0-9a-f]+: e8 90 90 90 90[ ]+calll[ ]+(0x)?9090936f.* + *[0-9a-f]+: e9 90 90 90 90[ ]+jmpl[ ]+(0x)?90909374.* + *[0-9a-f]+: ea 90 90 90 90 90 90[ ]+ljmpl[ ]+\$0x9090,\$0x90909090 + *[0-9a-f]+: eb 90[ ]+jmp[ ]+(0x)?27d.* + *[0-9a-f]+: ec[ ]+inb[ ]+\(%dx\),%al + *[0-9a-f]+: ed[ ]+inl[ ]+\(%dx\),%eax + *[0-9a-f]+: ee[ ]+outb[ ]+%al,\(%dx\) + *[0-9a-f]+: ef[ ]+outl[ ]+%eax,\(%dx\) + *[0-9a-f]+: f4[ ]+hlt[ ]+ + *[0-9a-f]+: f5[ ]+cmc[ ]+ + *[0-9a-f]+: f6 90 90 90 90 90[ ]+notb[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: f7 90 90 90 90 90[ ]+notl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: f8[ ]+clc[ ]+ + *[0-9a-f]+: f9[ ]+stc[ ]+ + *[0-9a-f]+: fa[ ]+cli[ ]+ + *[0-9a-f]+: fb[ ]+sti[ ]+ + *[0-9a-f]+: fc[ ]+cld[ ]+ + *[0-9a-f]+: fd[ ]+std[ ]+ + *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 06[ ]+clts[ ]+ + *[0-9a-f]+: 0f 08[ ]+invd[ ]+ + *[0-9a-f]+: 0f 09[ ]+wbinvd + *[0-9a-f]+: 0f 0b[ ]+ud2a[ ]+ + *[0-9a-f]+: 0f 20 d0[ ]+movl[ ]+%cr2,%eax + *[0-9a-f]+: 0f 21 d0[ ]+movl[ ]+%db2,%eax + *[0-9a-f]+: 0f 22 d0[ ]+movl[ ]+%eax,%cr2 + *[0-9a-f]+: 0f 23 d0[ ]+movl[ ]+%eax,%db2 + *[0-9a-f]+: 0f 24 d0[ ]+movl[ ]+%tr2,%eax + *[0-9a-f]+: 0f 26 d0[ ]+movl[ ]+%eax,%tr2 + *[0-9a-f]+: 0f 30[ ]+wrmsr[ ]+ + *[0-9a-f]+: 0f 31[ ]+rdtsc[ ]+ + *[0-9a-f]+: 0f 32[ ]+rdmsr[ ]+ + *[0-9a-f]+: 0f 33[ ]+rdpmc[ ]+ + *[0-9a-f]+: 0f 40 90 90 90 90 90[ ]+cmovo[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 41 90 90 90 90 90[ ]+cmovno -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 42 90 90 90 90 90[ ]+cmovb[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 43 90 90 90 90 90[ ]+cmovae -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 44 90 90 90 90 90[ ]+cmove[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 45 90 90 90 90 90[ ]+cmovne -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 46 90 90 90 90 90[ ]+cmovbe -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 47 90 90 90 90 90[ ]+cmova[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 48 90 90 90 90 90[ ]+cmovs[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 49 90 90 90 90 90[ ]+cmovns -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4a 90 90 90 90 90[ ]+cmovp[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4b 90 90 90 90 90[ ]+cmovnp -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4c 90 90 90 90 90[ ]+cmovl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4d 90 90 90 90 90[ ]+cmovge -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4e 90 90 90 90 90[ ]+cmovle -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 4f 90 90 90 90 90[ ]+cmovg[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f 60 90 90 90 90 90[ ]+punpcklbw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 61 90 90 90 90 90[ ]+punpcklwd -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 62 90 90 90 90 90[ ]+punpckldq -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 63 90 90 90 90 90[ ]+packsswb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 64 90 90 90 90 90[ ]+pcmpgtb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 65 90 90 90 90 90[ ]+pcmpgtw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 66 90 90 90 90 90[ ]+pcmpgtd -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 67 90 90 90 90 90[ ]+packuswb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 68 90 90 90 90 90[ ]+punpckhbw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 69 90 90 90 90 90[ ]+punpckhwd -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 6a 90 90 90 90 90[ ]+punpckhdq -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 6b 90 90 90 90 90[ ]+packssdw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 6e 90 90 90 90 90[ ]+movd[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 6f 90 90 90 90 90[ ]+movq[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 71 d0 90[ ]+psrlw[ ]+\$0x90,%mm0 + *[0-9a-f]+: 0f 72 d0 90[ ]+psrld[ ]+\$0x90,%mm0 + *[0-9a-f]+: 0f 73 d0 90[ ]+psrlq[ ]+\$0x90,%mm0 + *[0-9a-f]+: 0f 74 90 90 90 90 90[ ]+pcmpeqb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 75 90 90 90 90 90[ ]+pcmpeqw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 76 90 90 90 90 90[ ]+pcmpeqd -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f 77[ ]+emms[ ]+ + *[0-9a-f]+: 0f 7e 90 90 90 90 90[ ]+movd[ ]+%mm2,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 7f 90 90 90 90 90[ ]+movq[ ]+%mm2,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 80 90 90 90 90[ ]+jo[ ]+909094e2 <foo\+0x909094e2> + *[0-9a-f]+: 0f 81 90 90 90 90[ ]+jno[ ]+909094e8 <foo\+0x909094e8> + *[0-9a-f]+: 0f 82 90 90 90 90[ ]+jb[ ]+909094ee <foo\+0x909094ee> + *[0-9a-f]+: 0f 83 90 90 90 90[ ]+jae[ ]+909094f4 <foo\+0x909094f4> + *[0-9a-f]+: 0f 84 90 90 90 90[ ]+je[ ]+909094fa <foo\+0x909094fa> + *[0-9a-f]+: 0f 85 90 90 90 90[ ]+jne[ ]+90909500 <foo\+0x90909500> + *[0-9a-f]+: 0f 86 90 90 90 90[ ]+jbe[ ]+90909506 <foo\+0x90909506> + *[0-9a-f]+: 0f 87 90 90 90 90[ ]+ja[ ]+9090950c <foo\+0x9090950c> + *[0-9a-f]+: 0f 88 90 90 90 90[ ]+js[ ]+90909512 <foo\+0x90909512> + *[0-9a-f]+: 0f 89 90 90 90 90[ ]+jns[ ]+90909518 <foo\+0x90909518> + *[0-9a-f]+: 0f 8a 90 90 90 90[ ]+jp[ ]+9090951e <foo\+0x9090951e> + *[0-9a-f]+: 0f 8b 90 90 90 90[ ]+jnp[ ]+90909524 <foo\+0x90909524> + *[0-9a-f]+: 0f 8c 90 90 90 90[ ]+jl[ ]+9090952a <foo\+0x9090952a> + *[0-9a-f]+: 0f 8d 90 90 90 90[ ]+jge[ ]+90909530 <foo\+0x90909530> + *[0-9a-f]+: 0f 8e 90 90 90 90[ ]+jle[ ]+90909536 <foo\+0x90909536> + *[0-9a-f]+: 0f 8f 90 90 90 90[ ]+jg[ ]+9090953c <foo\+0x9090953c> + *[0-9a-f]+: 0f 90 80 90 90 90 90[ ]+seto[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 91 80 90 90 90 90[ ]+setno[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 92 80 90 90 90 90[ ]+setb[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 93 80 90 90 90 90[ ]+setae[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 94 80 90 90 90 90[ ]+sete[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 95 80 90 90 90 90[ ]+setne[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 96 80 90 90 90 90[ ]+setbe[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 97 80 90 90 90 90[ ]+seta[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 98 80 90 90 90 90[ ]+sets[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 99 80 90 90 90 90[ ]+setns[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9a 80 90 90 90 90[ ]+setp[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9b 80 90 90 90 90[ ]+setnp[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9c 80 90 90 90 90[ ]+setl[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9d 80 90 90 90 90[ ]+setge[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9e 80 90 90 90 90[ ]+setle[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f 9f 80 90 90 90 90[ ]+setg[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f a0[ ]+pushl[ ]+%fs + *[0-9a-f]+: 0f a1[ ]+popl[ ]+%fs + *[0-9a-f]+: 0f a2[ ]+cpuid[ ]+ + *[0-9a-f]+: 0f a3 90 90 90 90 90[ ]+btl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f a4 90 90 90 90 90 90[ ]+shldl[ ]+\$0x90,%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f a5 90 90 90 90 90[ ]+shldl[ ]+%cl,%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f a8[ ]+pushl[ ]+%gs + *[0-9a-f]+: 0f a9[ ]+popl[ ]+%gs + *[0-9a-f]+: 0f aa[ ]+rsm[ ]+ + *[0-9a-f]+: 0f ab 90 90 90 90 90[ ]+btsl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f ac 90 90 90 90 90 90[ ]+shrdl[ ]+\$0x90,%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f ad 90 90 90 90 90[ ]+shrdl[ ]+%cl,%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f af 90 90 90 90 90[ ]+imull[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b0 90 90 90 90 90[ ]+cmpxchgb %dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f b1 90 90 90 90 90[ ]+cmpxchgl %edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f b2 90 90 90 90 90[ ]+lssl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b3 90 90 90 90 90[ ]+btrl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f b4 90 90 90 90 90[ ]+lfsl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b5 90 90 90 90 90[ ]+lgsl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b6 90 90 90 90 90[ ]+movzbl -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b7 90 90 90 90 90[ ]+movzwl -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f b9[ ]+ud2b[ ]+ + *[0-9a-f]+: 0f bb 90 90 90 90 90[ ]+btcl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f bc 90 90 90 90 90[ ]+bsfl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f bd 90 90 90 90 90[ ]+bsrl[ ]+-0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f be 90 90 90 90 90[ ]+movsbl -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f bf 90 90 90 90 90[ ]+movswl -0x6f6f6f70\(%eax\),%edx + *[0-9a-f]+: 0f c0 90 90 90 90 90[ ]+xaddb[ ]+%dl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f c1 90 90 90 90 90[ ]+xaddl[ ]+%edx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 0f c8[ ]+bswap[ ]+%eax + *[0-9a-f]+: 0f c9[ ]+bswap[ ]+%ecx + *[0-9a-f]+: 0f ca[ ]+bswap[ ]+%edx + *[0-9a-f]+: 0f cb[ ]+bswap[ ]+%ebx + *[0-9a-f]+: 0f cc[ ]+bswap[ ]+%esp + *[0-9a-f]+: 0f cd[ ]+bswap[ ]+%ebp + *[0-9a-f]+: 0f ce[ ]+bswap[ ]+%esi + *[0-9a-f]+: 0f cf[ ]+bswap[ ]+%edi + *[0-9a-f]+: 0f d1 90 90 90 90 90[ ]+psrlw[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f d2 90 90 90 90 90[ ]+psrld[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f d3 90 90 90 90 90[ ]+psrlq[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f d5 90 90 90 90 90[ ]+pmullw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f d8 90 90 90 90 90[ ]+psubusb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f d9 90 90 90 90 90[ ]+psubusw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f db 90 90 90 90 90[ ]+pand[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f dc 90 90 90 90 90[ ]+paddusb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f dd 90 90 90 90 90[ ]+paddusw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f df 90 90 90 90 90[ ]+pandn[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f e1 90 90 90 90 90[ ]+psraw[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f e2 90 90 90 90 90[ ]+psrad[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f e5 90 90 90 90 90[ ]+pmulhw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f e8 90 90 90 90 90[ ]+psubsb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f e9 90 90 90 90 90[ ]+psubsw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f eb 90 90 90 90 90[ ]+por[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f ec 90 90 90 90 90[ ]+paddsb -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f ed 90 90 90 90 90[ ]+paddsw -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f ef 90 90 90 90 90[ ]+pxor[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f1 90 90 90 90 90[ ]+psllw[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f2 90 90 90 90 90[ ]+pslld[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f3 90 90 90 90 90[ ]+psllq[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f5 90 90 90 90 90[ ]+pmaddwd -0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f8 90 90 90 90 90[ ]+psubb[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f f9 90 90 90 90 90[ ]+psubw[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f fa 90 90 90 90 90[ ]+psubd[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f fc 90 90 90 90 90[ ]+paddb[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f fd 90 90 90 90 90[ ]+paddw[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 0f fe 90 90 90 90 90[ ]+paddd[ ]+-0x6f6f6f70\(%eax\),%mm2 + *[0-9a-f]+: 66 01 90 90 90 90 90[ ]+addw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 03 90 90 90 90 90[ ]+addw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 05 90 90[ ]+addw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 06[ ]+pushw[ ]+%es + *[0-9a-f]+: 66 07[ ]+popw[ ]+%es + *[0-9a-f]+: 66 09 90 90 90 90 90[ ]+orw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0b 90 90 90 90 90[ ]+orw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0d 90 90[ ]+orw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 0e[ ]+pushw[ ]+%cs + *[0-9a-f]+: 66 11 90 90 90 90 90[ ]+adcw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 13 90 90 90 90 90[ ]+adcw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 15 90 90[ ]+adcw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 16[ ]+pushw[ ]+%ss + *[0-9a-f]+: 66 17[ ]+popw[ ]+%ss + *[0-9a-f]+: 66 19 90 90 90 90 90[ ]+sbbw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 1b 90 90 90 90 90[ ]+sbbw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 1d 90 90[ ]+sbbw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 1e[ ]+pushw[ ]+%ds + *[0-9a-f]+: 66 1f[ ]+popw[ ]+%ds + *[0-9a-f]+: 66 21 90 90 90 90 90[ ]+andw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 23 90 90 90 90 90[ ]+andw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 25 90 90[ ]+andw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 29 90 90 90 90 90[ ]+subw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 2b 90 90 90 90 90[ ]+subw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 2d 90 90[ ]+subw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 31 90 90 90 90 90[ ]+xorw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 33 90 90 90 90 90[ ]+xorw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 35 90 90[ ]+xorw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 39 90 90 90 90 90[ ]+cmpw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 3b 90 90 90 90 90[ ]+cmpw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 3d 90 90[ ]+cmpw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 40[ ]+incw[ ]+%ax + *[0-9a-f]+: 66 41[ ]+incw[ ]+%cx + *[0-9a-f]+: 66 42[ ]+incw[ ]+%dx + *[0-9a-f]+: 66 43[ ]+incw[ ]+%bx + *[0-9a-f]+: 66 44[ ]+incw[ ]+%sp + *[0-9a-f]+: 66 45[ ]+incw[ ]+%bp + *[0-9a-f]+: 66 46[ ]+incw[ ]+%si + *[0-9a-f]+: 66 47[ ]+incw[ ]+%di + *[0-9a-f]+: 66 48[ ]+decw[ ]+%ax + *[0-9a-f]+: 66 49[ ]+decw[ ]+%cx + *[0-9a-f]+: 66 4a[ ]+decw[ ]+%dx + *[0-9a-f]+: 66 4b[ ]+decw[ ]+%bx + *[0-9a-f]+: 66 4c[ ]+decw[ ]+%sp + *[0-9a-f]+: 66 4d[ ]+decw[ ]+%bp + *[0-9a-f]+: 66 4e[ ]+decw[ ]+%si + *[0-9a-f]+: 66 4f[ ]+decw[ ]+%di + *[0-9a-f]+: 66 50[ ]+pushw[ ]+%ax + *[0-9a-f]+: 66 51[ ]+pushw[ ]+%cx + *[0-9a-f]+: 66 52[ ]+pushw[ ]+%dx + *[0-9a-f]+: 66 53[ ]+pushw[ ]+%bx + *[0-9a-f]+: 66 54[ ]+pushw[ ]+%sp + *[0-9a-f]+: 66 55[ ]+pushw[ ]+%bp + *[0-9a-f]+: 66 56[ ]+pushw[ ]+%si + *[0-9a-f]+: 66 57[ ]+pushw[ ]+%di + *[0-9a-f]+: 66 58[ ]+popw[ ]+%ax + *[0-9a-f]+: 66 59[ ]+popw[ ]+%cx + *[0-9a-f]+: 66 5a[ ]+popw[ ]+%dx + *[0-9a-f]+: 66 5b[ ]+popw[ ]+%bx + *[0-9a-f]+: 66 5c[ ]+popw[ ]+%sp + *[0-9a-f]+: 66 5d[ ]+popw[ ]+%bp + *[0-9a-f]+: 66 5e[ ]+popw[ ]+%si + *[0-9a-f]+: 66 5f[ ]+popw[ ]+%di + *[0-9a-f]+: 66 60[ ]+pushaw + *[0-9a-f]+: 66 61[ ]+popaw[ ]+ + *[0-9a-f]+: 66 62 90 90 90 90 90[ ]+boundw %dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 68 90 90[ ]+pushw[ ]+\$0x9090 + *[0-9a-f]+: 66 69 90 90 90 90 90 90 90[ ]+imulw[ ]+\$0x9090,-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 6a 90[ ]+pushw[ ]+\$0xffffff90 + *[0-9a-f]+: 66 6b 90 90 90 90 90 90[ ]+imulw[ ]+\$0xffffff90,-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 6d[ ]+insw[ ]+\(%dx\),%es:\(%edi\) + *[0-9a-f]+: 66 6f[ ]+outsw[ ]+%ds:\(%esi\),\(%dx\) + *[0-9a-f]+: 66 81 90 90 90 90 90 90 90[ ]+adcw[ ]+\$0x9090,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 83 90 90 90 90 90 90[ ]+adcw[ ]+\$0xffffff90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 85 90 90 90 90 90[ ]+testw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 87 90 90 90 90 90[ ]+xchgw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 89 90 90 90 90 90[ ]+movw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 8b 90 90 90 90 90[ ]+movw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 8c 90 90 90 90 90[ ]+movw[ ]+%ss,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 8d 90 90 90 90 90[ ]+leaw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 8f 80 90 90 90 90[ ]+popw[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 91[ ]+xchgw[ ]+%ax,%cx + *[0-9a-f]+: 66 92[ ]+xchgw[ ]+%ax,%dx + *[0-9a-f]+: 66 93[ ]+xchgw[ ]+%ax,%bx + *[0-9a-f]+: 66 94[ ]+xchgw[ ]+%ax,%sp + *[0-9a-f]+: 66 95[ ]+xchgw[ ]+%ax,%bp + *[0-9a-f]+: 66 96[ ]+xchgw[ ]+%ax,%si + *[0-9a-f]+: 66 97[ ]+xchgw[ ]+%ax,%di + *[0-9a-f]+: 66 98[ ]+cbtw[ ]+ + *[0-9a-f]+: 66 99[ ]+cwtd[ ]+ + *[0-9a-f]+: 66 9a 90 90 90 90[ ]+lcallw \$0x9090,\$0x9090 + *[0-9a-f]+: 66 9c[ ]+pushfw + *[0-9a-f]+: 66 9d[ ]+popfw[ ]+ + *[0-9a-f]+: 66 a1 90 90 90 90[ ]+movw[ ]+0x90909090,%ax + *[0-9a-f]+: 66 a3 90 90 90 90[ ]+movw[ ]+%ax,0x90909090 + *[0-9a-f]+: 66 a5[ ]+movsw[ ]+%ds:\(%esi\),%es:\(%edi\) + *[0-9a-f]+: 66 a7[ ]+cmpsw[ ]+%es:\(%edi\),%ds:\(%esi\) + *[0-9a-f]+: 66 a9 90 90[ ]+testw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 ab[ ]+stosw[ ]+%ax,%es:\(%edi\) + *[0-9a-f]+: 66 ad[ ]+lodsw[ ]+%ds:\(%esi\),%ax + *[0-9a-f]+: 66 af[ ]+scasw[ ]+%es:\(%edi\),%ax + *[0-9a-f]+: 66 b8 90 90[ ]+movw[ ]+\$0x9090,%ax + *[0-9a-f]+: 66 b9 90 90[ ]+movw[ ]+\$0x9090,%cx + *[0-9a-f]+: 66 ba 90 90[ ]+movw[ ]+\$0x9090,%dx + *[0-9a-f]+: 66 bb 90 90[ ]+movw[ ]+\$0x9090,%bx + *[0-9a-f]+: 66 bc 90 90[ ]+movw[ ]+\$0x9090,%sp + *[0-9a-f]+: 66 bd 90 90[ ]+movw[ ]+\$0x9090,%bp + *[0-9a-f]+: 66 be 90 90[ ]+movw[ ]+\$0x9090,%si + *[0-9a-f]+: 66 bf 90 90[ ]+movw[ ]+\$0x9090,%di + *[0-9a-f]+: 66 c1 90 90 90 90 90 90[ ]+rclw[ ]+\$0x90,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 c2 90 90[ ]+retw[ ]+\$0x9090 + *[0-9a-f]+: 66 c3[ ]+retw[ ]+ + *[0-9a-f]+: 66 c4 90 90 90 90 90[ ]+lesw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 c5 90 90 90 90 90[ ]+ldsw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 c7 80 90 90 90 90 90 90[ ]+movw[ ]+\$0x9090,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 c8 90 90 90[ ]+enterw \$0x9090,\$0x90 + *[0-9a-f]+: 66 c9[ ]+leavew + *[0-9a-f]+: 66 ca 90 90[ ]+lretw[ ]+\$0x9090 + *[0-9a-f]+: 66 cb[ ]+lretw[ ]+ + *[0-9a-f]+: 66 cf[ ]+iretw[ ]+ + *[0-9a-f]+: 66 d1 90 90 90 90 90[ ]+rclw[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 d3 90 90 90 90 90[ ]+rclw[ ]+%cl,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 e5 90[ ]+inw[ ]+\$0x90,%ax + *[0-9a-f]+: 66 e7 90[ ]+outw[ ]+%ax,\$0x90 + *[0-9a-f]+: 66 e8 8f 90[ ]+callw[ ]+(0x)?9918.* + *[0-9a-f]+: 66 ea 90 90 90 90[ ]+ljmpw[ ]+\$0x9090,\$0x9090 + *[0-9a-f]+: 66 ed[ ]+inw[ ]+\(%dx\),%ax + *[0-9a-f]+: 66 ef[ ]+outw[ ]+%ax,\(%dx\) + *[0-9a-f]+: 66 f7 90 90 90 90 90[ ]+notw[ ]+-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 ff 90 90 90 90 90[ ]+callw[ ]+\*-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f 02 90 90 90 90 90[ ]+larw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 03 90 90 90 90 90[ ]+lslw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 40 90 90 90 90 90[ ]+cmovo[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 41 90 90 90 90 90[ ]+cmovno -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 42 90 90 90 90 90[ ]+cmovb[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 43 90 90 90 90 90[ ]+cmovae -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 44 90 90 90 90 90[ ]+cmove[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 45 90 90 90 90 90[ ]+cmovne -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 46 90 90 90 90 90[ ]+cmovbe -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 47 90 90 90 90 90[ ]+cmova[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 48 90 90 90 90 90[ ]+cmovs[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 49 90 90 90 90 90[ ]+cmovns -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4a 90 90 90 90 90[ ]+cmovp[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4b 90 90 90 90 90[ ]+cmovnp -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4c 90 90 90 90 90[ ]+cmovl[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4d 90 90 90 90 90[ ]+cmovge -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4e 90 90 90 90 90[ ]+cmovle -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f 4f 90 90 90 90 90[ ]+cmovg[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f a0[ ]+pushw[ ]+%fs + *[0-9a-f]+: 66 0f a1[ ]+popw[ ]+%fs + *[0-9a-f]+: 66 0f a3 90 90 90 90 90[ ]+btw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f a4 90 90 90 90 90 90[ ]+shldw[ ]+\$0x90,%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f a5 90 90 90 90 90[ ]+shldw[ ]+%cl,%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f a8[ ]+pushw[ ]+%gs + *[0-9a-f]+: 66 0f a9[ ]+popw[ ]+%gs + *[0-9a-f]+: 66 0f ab 90 90 90 90 90[ ]+btsw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f ac 90 90 90 90 90 90[ ]+shrdw[ ]+\$0x90,%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f ad 90 90 90 90 90[ ]+shrdw[ ]+%cl,%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f af 90 90 90 90 90[ ]+imulw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f b1 90 90 90 90 90[ ]+cmpxchgw %dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f b2 90 90 90 90 90[ ]+lssw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f b3 90 90 90 90 90[ ]+btrw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f b4 90 90 90 90 90[ ]+lfsw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f b5 90 90 90 90 90[ ]+lgsw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f b6 90 90 90 90 90[ ]+movzbw -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f bb 90 90 90 90 90[ ]+btcw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 0f bc 90 90 90 90 90[ ]+bsfw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f bd 90 90 90 90 90[ ]+bsrw[ ]+-0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f be 90 90 90 90 90[ ]+movsbw -0x6f6f6f70\(%eax\),%dx + *[0-9a-f]+: 66 0f c1 90 90 90 90 90[ ]+xaddw[ ]+%dx,-0x6f6f6f70\(%eax\) + *[0-9a-f]+: 66 90[ ]+xchgw[ ]+%ax,%ax + *[0-9a-f]+: 0f 00 c0[ ]+sldtl[ ]+%eax + *[0-9a-f]+: 66 0f 00 c0[ ]+sldtw[ ]+%ax + *[0-9a-f]+: 0f 00 00[ ]+sldtw[ ]+\(%eax\) + *[0-9a-f]+: 0f 01 e0[ ]+smswl[ ]+%eax + *[0-9a-f]+: 66 0f 01 e0[ ]+smsww[ ]+%ax + *[0-9a-f]+: 0f 01 20[ ]+smsww[ ]+\(%eax\) + *[0-9a-f]+: 0f 00 c8[ ]+strl[ ]+%eax + *[0-9a-f]+: 66 0f 00 c8[ ]+strw[ ]+%ax + *[0-9a-f]+: 0f 00 08[ ]+strw[ ]+\(%eax\) + *[0-9a-f]+: 0f ad d0 [ ]*shrdl[ ]+%cl,%edx,%eax + *[0-9a-f]+: 0f a5 d0 [ ]*shldl[ ]+%cl,%edx,%eax + *[0-9a-f]+: 85 c3 [ ]*testl[ ]+%eax,%ebx + *[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax + *[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\) +#pass diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d index 808ddc5371a4..5683895d0dc3 100644 --- a/gas/testsuite/gas/i386/opcode.d +++ b/gas/testsuite/gas/i386/opcode.d @@ -1,68 +1,68 @@ #as: -J #objdump: -dw -#name: i386 intel +#name: i386 opcodes .*: +file format .* Disassembly of section .text: 0+000 <foo>: - 0: 00 90 90 90 90 90 [ ]*add %dl,0x90909090\(%eax\) - 6: 01 90 90 90 90 90 [ ]*add %edx,0x90909090\(%eax\) - c: 02 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%dl - 12: 03 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%edx + 0: 00 90 90 90 90 90 [ ]*add %dl,-0x6f6f6f70\(%eax\) + 6: 01 90 90 90 90 90 [ ]*add %edx,-0x6f6f6f70\(%eax\) + c: 02 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%dl + 12: 03 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%edx 18: 04 90 [ ]*add \$0x90,%al 1a: 05 90 90 90 90 [ ]*add \$0x90909090,%eax 1f: 06 [ ]*push %es 20: 07 [ ]*pop %es - 21: 08 90 90 90 90 90 [ ]*or %dl,0x90909090\(%eax\) - 27: 09 90 90 90 90 90 [ ]*or %edx,0x90909090\(%eax\) - 2d: 0a 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%dl - 33: 0b 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%edx + 21: 08 90 90 90 90 90 [ ]*or %dl,-0x6f6f6f70\(%eax\) + 27: 09 90 90 90 90 90 [ ]*or %edx,-0x6f6f6f70\(%eax\) + 2d: 0a 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%dl + 33: 0b 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%edx 39: 0c 90 [ ]*or \$0x90,%al 3b: 0d 90 90 90 90 [ ]*or \$0x90909090,%eax 40: 0e [ ]*push %cs - 41: 10 90 90 90 90 90 [ ]*adc %dl,0x90909090\(%eax\) - 47: 11 90 90 90 90 90 [ ]*adc %edx,0x90909090\(%eax\) - 4d: 12 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%dl - 53: 13 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%edx + 41: 10 90 90 90 90 90 [ ]*adc %dl,-0x6f6f6f70\(%eax\) + 47: 11 90 90 90 90 90 [ ]*adc %edx,-0x6f6f6f70\(%eax\) + 4d: 12 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%dl + 53: 13 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%edx 59: 14 90 [ ]*adc \$0x90,%al 5b: 15 90 90 90 90 [ ]*adc \$0x90909090,%eax 60: 16 [ ]*push %ss 61: 17 [ ]*pop %ss - 62: 18 90 90 90 90 90 [ ]*sbb %dl,0x90909090\(%eax\) - 68: 19 90 90 90 90 90 [ ]*sbb %edx,0x90909090\(%eax\) - 6e: 1a 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%dl - 74: 1b 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%edx + 62: 18 90 90 90 90 90 [ ]*sbb %dl,-0x6f6f6f70\(%eax\) + 68: 19 90 90 90 90 90 [ ]*sbb %edx,-0x6f6f6f70\(%eax\) + 6e: 1a 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%dl + 74: 1b 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%edx 7a: 1c 90 [ ]*sbb \$0x90,%al 7c: 1d 90 90 90 90 [ ]*sbb \$0x90909090,%eax 81: 1e [ ]*push %ds 82: 1f [ ]*pop %ds - 83: 20 90 90 90 90 90 [ ]*and %dl,0x90909090\(%eax\) - 89: 21 90 90 90 90 90 [ ]*and %edx,0x90909090\(%eax\) - 8f: 22 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%dl - 95: 23 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%edx + 83: 20 90 90 90 90 90 [ ]*and %dl,-0x6f6f6f70\(%eax\) + 89: 21 90 90 90 90 90 [ ]*and %edx,-0x6f6f6f70\(%eax\) + 8f: 22 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%dl + 95: 23 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%edx 9b: 24 90 [ ]*and \$0x90,%al 9d: 25 90 90 90 90 [ ]*and \$0x90909090,%eax a2: 27 [ ]*daa - a3: 28 90 90 90 90 90 [ ]*sub %dl,0x90909090\(%eax\) - a9: 29 90 90 90 90 90 [ ]*sub %edx,0x90909090\(%eax\) - af: 2a 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%dl - b5: 2b 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%edx + a3: 28 90 90 90 90 90 [ ]*sub %dl,-0x6f6f6f70\(%eax\) + a9: 29 90 90 90 90 90 [ ]*sub %edx,-0x6f6f6f70\(%eax\) + af: 2a 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%dl + b5: 2b 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%edx bb: 2c 90 [ ]*sub \$0x90,%al bd: 2d 90 90 90 90 [ ]*sub \$0x90909090,%eax c2: 2f [ ]*das - c3: 30 90 90 90 90 90 [ ]*xor %dl,0x90909090\(%eax\) - c9: 31 90 90 90 90 90 [ ]*xor %edx,0x90909090\(%eax\) - cf: 32 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%dl - d5: 33 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%edx + c3: 30 90 90 90 90 90 [ ]*xor %dl,-0x6f6f6f70\(%eax\) + c9: 31 90 90 90 90 90 [ ]*xor %edx,-0x6f6f6f70\(%eax\) + cf: 32 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%dl + d5: 33 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%edx db: 34 90 [ ]*xor \$0x90,%al dd: 35 90 90 90 90 [ ]*xor \$0x90909090,%eax e2: 37 [ ]*aaa - e3: 38 90 90 90 90 90 [ ]*cmp %dl,0x90909090\(%eax\) - e9: 39 90 90 90 90 90 [ ]*cmp %edx,0x90909090\(%eax\) - ef: 3a 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%dl - f5: 3b 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%edx + e3: 38 90 90 90 90 90 [ ]*cmp %dl,-0x6f6f6f70\(%eax\) + e9: 39 90 90 90 90 90 [ ]*cmp %edx,-0x6f6f6f70\(%eax\) + ef: 3a 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%dl + f5: 3b 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%edx fb: 3c 90 [ ]*cmp \$0x90,%al fd: 3d 90 90 90 90 [ ]*cmp \$0x90909090,%eax 102: 3f [ ]*aas @@ -100,12 +100,12 @@ Disassembly of section .text: 122: 5f [ ]*pop %edi 123: 60 [ ]*pusha 124: 61 [ ]*popa - 125: 62 90 90 90 90 90 [ ]*bound %edx,0x90909090\(%eax\) - 12b: 63 90 90 90 90 90 [ ]*arpl %dx,0x90909090\(%eax\) + 125: 62 90 90 90 90 90 [ ]*bound %edx,-0x6f6f6f70\(%eax\) + 12b: 63 90 90 90 90 90 [ ]*arpl %dx,-0x6f6f6f70\(%eax\) 131: 68 90 90 90 90 [ ]*push \$0x90909090 - 136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,0x90909090\(%eax\),%edx + 136: 69 90 90 90 90 90 90 90 90 90 [ ]*imul \$0x90909090,-0x6f6f6f70\(%eax\),%edx 140: 6a 90 [ ]*push \$0xffffff90 - 142: 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,0x90909090\(%eax\),%edx + 142: 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,-0x6f6f6f70\(%eax\),%edx 149: 6c [ ]*insb \(%dx\),%es:\(%edi\) 14a: 6d [ ]*insl \(%dx\),%es:\(%edi\) 14b: 6e [ ]*outsb %ds:\(%esi\),\(%dx\) @@ -126,21 +126,21 @@ Disassembly of section .text: 167: 7d 90 [ ]*jge (0x)?f9.* 169: 7e 90 [ ]*jle (0x)?fb.* 16b: 7f 90 [ ]*jg (0x)?fd.* - 16d: 80 90 90 90 90 90 90 [ ]*adcb \$0x90,0x90909090\(%eax\) - 174: 81 90 90 90 90 90 90 90 90 90 [ ]*adcl \$0x90909090,0x90909090\(%eax\) - 17e: 83 90 90 90 90 90 90 [ ]*adcl \$0xffffff90,0x90909090\(%eax\) - 185: 84 90 90 90 90 90 [ ]*test %dl,0x90909090\(%eax\) - 18b: 85 90 90 90 90 90 [ ]*test %edx,0x90909090\(%eax\) - 191: 86 90 90 90 90 90 [ ]*xchg %dl,0x90909090\(%eax\) - 197: 87 90 90 90 90 90 [ ]*xchg %edx,0x90909090\(%eax\) - 19d: 88 90 90 90 90 90 [ ]*mov %dl,0x90909090\(%eax\) - 1a3: 89 90 90 90 90 90 [ ]*mov %edx,0x90909090\(%eax\) - 1a9: 8a 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%dl - 1af: 8b 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%edx - 1b5: 8c 90 90 90 90 90 [ ]*movw %ss,0x90909090\(%eax\) - 1bb: 8d 90 90 90 90 90 [ ]*lea 0x90909090\(%eax\),%edx - 1c1: 8e 90 90 90 90 90 [ ]*movw 0x90909090\(%eax\),%ss - 1c7: 8f 80 90 90 90 90 [ ]*popl 0x90909090\(%eax\) + 16d: 80 90 90 90 90 90 90 [ ]*adcb \$0x90,-0x6f6f6f70\(%eax\) + 174: 81 90 90 90 90 90 90 90 90 90 [ ]*adcl \$0x90909090,-0x6f6f6f70\(%eax\) + 17e: 83 90 90 90 90 90 90 [ ]*adcl \$0xffffff90,-0x6f6f6f70\(%eax\) + 185: 84 90 90 90 90 90 [ ]*test %dl,-0x6f6f6f70\(%eax\) + 18b: 85 90 90 90 90 90 [ ]*test %edx,-0x6f6f6f70\(%eax\) + 191: 86 90 90 90 90 90 [ ]*xchg %dl,-0x6f6f6f70\(%eax\) + 197: 87 90 90 90 90 90 [ ]*xchg %edx,-0x6f6f6f70\(%eax\) + 19d: 88 90 90 90 90 90 [ ]*mov %dl,-0x6f6f6f70\(%eax\) + 1a3: 89 90 90 90 90 90 [ ]*mov %edx,-0x6f6f6f70\(%eax\) + 1a9: 8a 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%dl + 1af: 8b 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%edx + 1b5: 8c 90 90 90 90 90 [ ]*mov %ss,-0x6f6f6f70\(%eax\) + 1bb: 8d 90 90 90 90 90 [ ]*lea -0x6f6f6f70\(%eax\),%edx + 1c1: 8e 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%ss + 1c7: 8f 80 90 90 90 90 [ ]*popl -0x6f6f6f70\(%eax\) 1cd: 90 [ ]*nop 1ce: 91 [ ]*xchg %eax,%ecx 1cf: 92 [ ]*xchg %eax,%edx @@ -189,14 +189,14 @@ Disassembly of section .text: 231: bd 90 90 90 90 [ ]*mov \$0x90909090,%ebp 236: be 90 90 90 90 [ ]*mov \$0x90909090,%esi 23b: bf 90 90 90 90 [ ]*mov \$0x90909090,%edi - 240: c0 90 90 90 90 90 90 [ ]*rclb \$0x90,0x90909090\(%eax\) - 247: c1 90 90 90 90 90 90 [ ]*rcll \$0x90,0x90909090\(%eax\) + 240: c0 90 90 90 90 90 90 [ ]*rclb \$0x90,-0x6f6f6f70\(%eax\) + 247: c1 90 90 90 90 90 90 [ ]*rcll \$0x90,-0x6f6f6f70\(%eax\) 24e: c2 90 90 [ ]*ret \$0x9090 251: c3 [ ]*ret - 252: c4 90 90 90 90 90 [ ]*les 0x90909090\(%eax\),%edx - 258: c5 90 90 90 90 90 [ ]*lds 0x90909090\(%eax\),%edx - 25e: c6 80 90 90 90 90 90 [ ]*movb \$0x90,0x90909090\(%eax\) - 265: c7 80 90 90 90 90 90 90 90 90 [ ]*movl \$0x90909090,0x90909090\(%eax\) + 252: c4 90 90 90 90 90 [ ]*les -0x6f6f6f70\(%eax\),%edx + 258: c5 90 90 90 90 90 [ ]*lds -0x6f6f6f70\(%eax\),%edx + 25e: c6 80 90 90 90 90 90 [ ]*movb \$0x90,-0x6f6f6f70\(%eax\) + 265: c7 80 90 90 90 90 90 90 90 90 [ ]*movl \$0x90909090,-0x6f6f6f70\(%eax\) 26f: c8 90 90 90 [ ]*enter \$0x9090,\$0x90 273: c9 [ ]*leave 274: ca 90 90 [ ]*lret \$0x9090 @@ -205,21 +205,21 @@ Disassembly of section .text: 279: cd 90 [ ]*int \$0x90 27b: ce [ ]*into 27c: cf [ ]*iret - 27d: d0 90 90 90 90 90 [ ]*rclb 0x90909090\(%eax\) - 283: d1 90 90 90 90 90 [ ]*rcll 0x90909090\(%eax\) - 289: d2 90 90 90 90 90 [ ]*rclb %cl,0x90909090\(%eax\) - 28f: d3 90 90 90 90 90 [ ]*rcll %cl,0x90909090\(%eax\) + 27d: d0 90 90 90 90 90 [ ]*rclb -0x6f6f6f70\(%eax\) + 283: d1 90 90 90 90 90 [ ]*rcll -0x6f6f6f70\(%eax\) + 289: d2 90 90 90 90 90 [ ]*rclb %cl,-0x6f6f6f70\(%eax\) + 28f: d3 90 90 90 90 90 [ ]*rcll %cl,-0x6f6f6f70\(%eax\) 295: d4 90 [ ]*aam \$0xffffff90 297: d5 90 [ ]*aad \$0xffffff90 299: d7 [ ]*xlat %ds:\(%ebx\) - 29a: d8 90 90 90 90 90 [ ]*fcoms 0x90909090\(%eax\) - 2a0: d9 90 90 90 90 90 [ ]*fsts 0x90909090\(%eax\) - 2a6: da 90 90 90 90 90 [ ]*ficoml 0x90909090\(%eax\) - 2ac: db 90 90 90 90 90 [ ]*fistl 0x90909090\(%eax\) - 2b2: dc 90 90 90 90 90 [ ]*fcoml 0x90909090\(%eax\) - 2b8: dd 90 90 90 90 90 [ ]*fstl 0x90909090\(%eax\) - 2be: de 90 90 90 90 90 [ ]*ficom 0x90909090\(%eax\) - 2c4: df 90 90 90 90 90 [ ]*fist 0x90909090\(%eax\) + 29a: d8 90 90 90 90 90 [ ]*fcoms -0x6f6f6f70\(%eax\) + 2a0: d9 90 90 90 90 90 [ ]*fsts -0x6f6f6f70\(%eax\) + 2a6: da 90 90 90 90 90 [ ]*ficoml -0x6f6f6f70\(%eax\) + 2ac: db 90 90 90 90 90 [ ]*fistl -0x6f6f6f70\(%eax\) + 2b2: dc 90 90 90 90 90 [ ]*fcoml -0x6f6f6f70\(%eax\) + 2b8: dd 90 90 90 90 90 [ ]*fstl -0x6f6f6f70\(%eax\) + 2be: de 90 90 90 90 90 [ ]*ficom -0x6f6f6f70\(%eax\) + 2c4: df 90 90 90 90 90 [ ]*fist -0x6f6f6f70\(%eax\) 2ca: e0 90 [ ]*loopne (0x)?25c.* 2cc: e1 90 [ ]*loope (0x)?25e.* 2ce: e2 90 [ ]*loop (0x)?260.* @@ -238,19 +238,19 @@ Disassembly of section .text: 2f0: ef [ ]*out %eax,\(%dx\) 2f1: f4 [ ]*hlt 2f2: f5 [ ]*cmc - 2f3: f6 90 90 90 90 90 [ ]*notb 0x90909090\(%eax\) - 2f9: f7 90 90 90 90 90 [ ]*notl 0x90909090\(%eax\) + 2f3: f6 90 90 90 90 90 [ ]*notb -0x6f6f6f70\(%eax\) + 2f9: f7 90 90 90 90 90 [ ]*notl -0x6f6f6f70\(%eax\) 2ff: f8 [ ]*clc 300: f9 [ ]*stc 301: fa [ ]*cli 302: fb [ ]*sti 303: fc [ ]*cld 304: fd [ ]*std - 305: ff 90 90 90 90 90 [ ]*call \*0x90909090\(%eax\) - 30b: 0f 00 90 90 90 90 90 [ ]*lldt 0x90909090\(%eax\) - 312: 0f 01 90 90 90 90 90 [ ]*lgdtl 0x90909090\(%eax\) - 319: 0f 02 90 90 90 90 90 [ ]*lar 0x90909090\(%eax\),%edx - 320: 0f 03 90 90 90 90 90 [ ]*lsl 0x90909090\(%eax\),%edx + 305: ff 90 90 90 90 90 [ ]*call \*-0x6f6f6f70\(%eax\) + 30b: 0f 00 90 90 90 90 90 [ ]*lldt -0x6f6f6f70\(%eax\) + 312: 0f 01 90 90 90 90 90 [ ]*lgdtl -0x6f6f6f70\(%eax\) + 319: 0f 02 90 90 90 90 90 [ ]*lar -0x6f6f6f70\(%eax\),%edx + 320: 0f 03 90 90 90 90 90 [ ]*lsl -0x6f6f6f70\(%eax\),%edx 327: 0f 06 [ ]*clts 329: 0f 08 [ ]*invd 32b: 0f 09 [ ]*wbinvd @@ -265,45 +265,45 @@ Disassembly of section .text: 343: 0f 31 [ ]*rdtsc 345: 0f 32 [ ]*rdmsr 347: 0f 33 [ ]*rdpmc - 349: 0f 40 90 90 90 90 90 [ ]*cmovo 0x90909090\(%eax\),%edx - 350: 0f 41 90 90 90 90 90 [ ]*cmovno 0x90909090\(%eax\),%edx - 357: 0f 42 90 90 90 90 90 [ ]*cmovb 0x90909090\(%eax\),%edx - 35e: 0f 43 90 90 90 90 90 [ ]*cmovae 0x90909090\(%eax\),%edx - 365: 0f 44 90 90 90 90 90 [ ]*cmove 0x90909090\(%eax\),%edx - 36c: 0f 45 90 90 90 90 90 [ ]*cmovne 0x90909090\(%eax\),%edx - 373: 0f 46 90 90 90 90 90 [ ]*cmovbe 0x90909090\(%eax\),%edx - 37a: 0f 47 90 90 90 90 90 [ ]*cmova 0x90909090\(%eax\),%edx - 381: 0f 48 90 90 90 90 90 [ ]*cmovs 0x90909090\(%eax\),%edx - 388: 0f 49 90 90 90 90 90 [ ]*cmovns 0x90909090\(%eax\),%edx - 38f: 0f 4a 90 90 90 90 90 [ ]*cmovp 0x90909090\(%eax\),%edx - 396: 0f 4b 90 90 90 90 90 [ ]*cmovnp 0x90909090\(%eax\),%edx - 39d: 0f 4c 90 90 90 90 90 [ ]*cmovl 0x90909090\(%eax\),%edx - 3a4: 0f 4d 90 90 90 90 90 [ ]*cmovge 0x90909090\(%eax\),%edx - 3ab: 0f 4e 90 90 90 90 90 [ ]*cmovle 0x90909090\(%eax\),%edx - 3b2: 0f 4f 90 90 90 90 90 [ ]*cmovg 0x90909090\(%eax\),%edx - 3b9: 0f 60 90 90 90 90 90 [ ]*punpcklbw 0x90909090\(%eax\),%mm2 - 3c0: 0f 61 90 90 90 90 90 [ ]*punpcklwd 0x90909090\(%eax\),%mm2 - 3c7: 0f 62 90 90 90 90 90 [ ]*punpckldq 0x90909090\(%eax\),%mm2 - 3ce: 0f 63 90 90 90 90 90 [ ]*packsswb 0x90909090\(%eax\),%mm2 - 3d5: 0f 64 90 90 90 90 90 [ ]*pcmpgtb 0x90909090\(%eax\),%mm2 - 3dc: 0f 65 90 90 90 90 90 [ ]*pcmpgtw 0x90909090\(%eax\),%mm2 - 3e3: 0f 66 90 90 90 90 90 [ ]*pcmpgtd 0x90909090\(%eax\),%mm2 - 3ea: 0f 67 90 90 90 90 90 [ ]*packuswb 0x90909090\(%eax\),%mm2 - 3f1: 0f 68 90 90 90 90 90 [ ]*punpckhbw 0x90909090\(%eax\),%mm2 - 3f8: 0f 69 90 90 90 90 90 [ ]*punpckhwd 0x90909090\(%eax\),%mm2 - 3ff: 0f 6a 90 90 90 90 90 [ ]*punpckhdq 0x90909090\(%eax\),%mm2 - 406: 0f 6b 90 90 90 90 90 [ ]*packssdw 0x90909090\(%eax\),%mm2 - 40d: 0f 6e 90 90 90 90 90 [ ]*movd 0x90909090\(%eax\),%mm2 - 414: 0f 6f 90 90 90 90 90 [ ]*movq 0x90909090\(%eax\),%mm2 + 349: 0f 40 90 90 90 90 90 [ ]*cmovo -0x6f6f6f70\(%eax\),%edx + 350: 0f 41 90 90 90 90 90 [ ]*cmovno -0x6f6f6f70\(%eax\),%edx + 357: 0f 42 90 90 90 90 90 [ ]*cmovb -0x6f6f6f70\(%eax\),%edx + 35e: 0f 43 90 90 90 90 90 [ ]*cmovae -0x6f6f6f70\(%eax\),%edx + 365: 0f 44 90 90 90 90 90 [ ]*cmove -0x6f6f6f70\(%eax\),%edx + 36c: 0f 45 90 90 90 90 90 [ ]*cmovne -0x6f6f6f70\(%eax\),%edx + 373: 0f 46 90 90 90 90 90 [ ]*cmovbe -0x6f6f6f70\(%eax\),%edx + 37a: 0f 47 90 90 90 90 90 [ ]*cmova -0x6f6f6f70\(%eax\),%edx + 381: 0f 48 90 90 90 90 90 [ ]*cmovs -0x6f6f6f70\(%eax\),%edx + 388: 0f 49 90 90 90 90 90 [ ]*cmovns -0x6f6f6f70\(%eax\),%edx + 38f: 0f 4a 90 90 90 90 90 [ ]*cmovp -0x6f6f6f70\(%eax\),%edx + 396: 0f 4b 90 90 90 90 90 [ ]*cmovnp -0x6f6f6f70\(%eax\),%edx + 39d: 0f 4c 90 90 90 90 90 [ ]*cmovl -0x6f6f6f70\(%eax\),%edx + 3a4: 0f 4d 90 90 90 90 90 [ ]*cmovge -0x6f6f6f70\(%eax\),%edx + 3ab: 0f 4e 90 90 90 90 90 [ ]*cmovle -0x6f6f6f70\(%eax\),%edx + 3b2: 0f 4f 90 90 90 90 90 [ ]*cmovg -0x6f6f6f70\(%eax\),%edx + 3b9: 0f 60 90 90 90 90 90 [ ]*punpcklbw -0x6f6f6f70\(%eax\),%mm2 + 3c0: 0f 61 90 90 90 90 90 [ ]*punpcklwd -0x6f6f6f70\(%eax\),%mm2 + 3c7: 0f 62 90 90 90 90 90 [ ]*punpckldq -0x6f6f6f70\(%eax\),%mm2 + 3ce: 0f 63 90 90 90 90 90 [ ]*packsswb -0x6f6f6f70\(%eax\),%mm2 + 3d5: 0f 64 90 90 90 90 90 [ ]*pcmpgtb -0x6f6f6f70\(%eax\),%mm2 + 3dc: 0f 65 90 90 90 90 90 [ ]*pcmpgtw -0x6f6f6f70\(%eax\),%mm2 + 3e3: 0f 66 90 90 90 90 90 [ ]*pcmpgtd -0x6f6f6f70\(%eax\),%mm2 + 3ea: 0f 67 90 90 90 90 90 [ ]*packuswb -0x6f6f6f70\(%eax\),%mm2 + 3f1: 0f 68 90 90 90 90 90 [ ]*punpckhbw -0x6f6f6f70\(%eax\),%mm2 + 3f8: 0f 69 90 90 90 90 90 [ ]*punpckhwd -0x6f6f6f70\(%eax\),%mm2 + 3ff: 0f 6a 90 90 90 90 90 [ ]*punpckhdq -0x6f6f6f70\(%eax\),%mm2 + 406: 0f 6b 90 90 90 90 90 [ ]*packssdw -0x6f6f6f70\(%eax\),%mm2 + 40d: 0f 6e 90 90 90 90 90 [ ]*movd -0x6f6f6f70\(%eax\),%mm2 + 414: 0f 6f 90 90 90 90 90 [ ]*movq -0x6f6f6f70\(%eax\),%mm2 41b: 0f 71 d0 90 [ ]*psrlw \$0x90,%mm0 41f: 0f 72 d0 90 [ ]*psrld \$0x90,%mm0 423: 0f 73 d0 90 [ ]*psrlq \$0x90,%mm0 - 427: 0f 74 90 90 90 90 90 [ ]*pcmpeqb 0x90909090\(%eax\),%mm2 - 42e: 0f 75 90 90 90 90 90 [ ]*pcmpeqw 0x90909090\(%eax\),%mm2 - 435: 0f 76 90 90 90 90 90 [ ]*pcmpeqd 0x90909090\(%eax\),%mm2 + 427: 0f 74 90 90 90 90 90 [ ]*pcmpeqb -0x6f6f6f70\(%eax\),%mm2 + 42e: 0f 75 90 90 90 90 90 [ ]*pcmpeqw -0x6f6f6f70\(%eax\),%mm2 + 435: 0f 76 90 90 90 90 90 [ ]*pcmpeqd -0x6f6f6f70\(%eax\),%mm2 43c: 0f 77 [ ]*emms - 43e: 0f 7e 90 90 90 90 90 [ ]*movd %mm2,0x90909090\(%eax\) - 445: 0f 7f 90 90 90 90 90 [ ]*movq %mm2,0x90909090\(%eax\) + 43e: 0f 7e 90 90 90 90 90 [ ]*movd %mm2,-0x6f6f6f70\(%eax\) + 445: 0f 7f 90 90 90 90 90 [ ]*movq %mm2,-0x6f6f6f70\(%eax\) 44c: 0f 80 90 90 90 90 [ ]*jo (0x)?909094e2.* 452: 0f 81 90 90 90 90 [ ]*jno (0x)?909094e8.* 458: 0f 82 90 90 90 90 [ ]*jb (0x)?909094ee.* @@ -320,51 +320,51 @@ Disassembly of section .text: 49a: 0f 8d 90 90 90 90 [ ]*jge (0x)?90909530.* 4a0: 0f 8e 90 90 90 90 [ ]*jle (0x)?90909536.* 4a6: 0f 8f 90 90 90 90 [ ]*jg (0x)?9090953c.* - 4ac: 0f 90 80 90 90 90 90 [ ]*seto 0x90909090\(%eax\) - 4b3: 0f 91 80 90 90 90 90 [ ]*setno 0x90909090\(%eax\) - 4ba: 0f 92 80 90 90 90 90 [ ]*setb 0x90909090\(%eax\) - 4c1: 0f 93 80 90 90 90 90 [ ]*setae 0x90909090\(%eax\) - 4c8: 0f 94 80 90 90 90 90 [ ]*sete 0x90909090\(%eax\) - 4cf: 0f 95 80 90 90 90 90 [ ]*setne 0x90909090\(%eax\) - 4d6: 0f 96 80 90 90 90 90 [ ]*setbe 0x90909090\(%eax\) - 4dd: 0f 97 80 90 90 90 90 [ ]*seta 0x90909090\(%eax\) - 4e4: 0f 98 80 90 90 90 90 [ ]*sets 0x90909090\(%eax\) - 4eb: 0f 99 80 90 90 90 90 [ ]*setns 0x90909090\(%eax\) - 4f2: 0f 9a 80 90 90 90 90 [ ]*setp 0x90909090\(%eax\) - 4f9: 0f 9b 80 90 90 90 90 [ ]*setnp 0x90909090\(%eax\) - 500: 0f 9c 80 90 90 90 90 [ ]*setl 0x90909090\(%eax\) - 507: 0f 9d 80 90 90 90 90 [ ]*setge 0x90909090\(%eax\) - 50e: 0f 9e 80 90 90 90 90 [ ]*setle 0x90909090\(%eax\) - 515: 0f 9f 80 90 90 90 90 [ ]*setg 0x90909090\(%eax\) + 4ac: 0f 90 80 90 90 90 90 [ ]*seto -0x6f6f6f70\(%eax\) + 4b3: 0f 91 80 90 90 90 90 [ ]*setno -0x6f6f6f70\(%eax\) + 4ba: 0f 92 80 90 90 90 90 [ ]*setb -0x6f6f6f70\(%eax\) + 4c1: 0f 93 80 90 90 90 90 [ ]*setae -0x6f6f6f70\(%eax\) + 4c8: 0f 94 80 90 90 90 90 [ ]*sete -0x6f6f6f70\(%eax\) + 4cf: 0f 95 80 90 90 90 90 [ ]*setne -0x6f6f6f70\(%eax\) + 4d6: 0f 96 80 90 90 90 90 [ ]*setbe -0x6f6f6f70\(%eax\) + 4dd: 0f 97 80 90 90 90 90 [ ]*seta -0x6f6f6f70\(%eax\) + 4e4: 0f 98 80 90 90 90 90 [ ]*sets -0x6f6f6f70\(%eax\) + 4eb: 0f 99 80 90 90 90 90 [ ]*setns -0x6f6f6f70\(%eax\) + 4f2: 0f 9a 80 90 90 90 90 [ ]*setp -0x6f6f6f70\(%eax\) + 4f9: 0f 9b 80 90 90 90 90 [ ]*setnp -0x6f6f6f70\(%eax\) + 500: 0f 9c 80 90 90 90 90 [ ]*setl -0x6f6f6f70\(%eax\) + 507: 0f 9d 80 90 90 90 90 [ ]*setge -0x6f6f6f70\(%eax\) + 50e: 0f 9e 80 90 90 90 90 [ ]*setle -0x6f6f6f70\(%eax\) + 515: 0f 9f 80 90 90 90 90 [ ]*setg -0x6f6f6f70\(%eax\) 51c: 0f a0 [ ]*push %fs 51e: 0f a1 [ ]*pop %fs 520: 0f a2 [ ]*cpuid - 522: 0f a3 90 90 90 90 90 [ ]*bt %edx,0x90909090\(%eax\) - 529: 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%edx,0x90909090\(%eax\) - 531: 0f a5 90 90 90 90 90 [ ]*shld %cl,%edx,0x90909090\(%eax\) + 522: 0f a3 90 90 90 90 90 [ ]*bt %edx,-0x6f6f6f70\(%eax\) + 529: 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%edx,-0x6f6f6f70\(%eax\) + 531: 0f a5 90 90 90 90 90 [ ]*shld %cl,%edx,-0x6f6f6f70\(%eax\) 538: 0f a8 [ ]*push %gs 53a: 0f a9 [ ]*pop %gs 53c: 0f aa [ ]*rsm - 53e: 0f ab 90 90 90 90 90 [ ]*bts %edx,0x90909090\(%eax\) - 545: 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%edx,0x90909090\(%eax\) - 54d: 0f ad 90 90 90 90 90 [ ]*shrd %cl,%edx,0x90909090\(%eax\) - 554: 0f af 90 90 90 90 90 [ ]*imul 0x90909090\(%eax\),%edx - 55b: 0f b0 90 90 90 90 90 [ ]*cmpxchg %dl,0x90909090\(%eax\) - 562: 0f b1 90 90 90 90 90 [ ]*cmpxchg %edx,0x90909090\(%eax\) - 569: 0f b2 90 90 90 90 90 [ ]*lss 0x90909090\(%eax\),%edx - 570: 0f b3 90 90 90 90 90 [ ]*btr %edx,0x90909090\(%eax\) - 577: 0f b4 90 90 90 90 90 [ ]*lfs 0x90909090\(%eax\),%edx - 57e: 0f b5 90 90 90 90 90 [ ]*lgs 0x90909090\(%eax\),%edx - 585: 0f b6 90 90 90 90 90 [ ]*movzbl 0x90909090\(%eax\),%edx - 58c: 0f b7 90 90 90 90 90 [ ]*movzwl 0x90909090\(%eax\),%edx + 53e: 0f ab 90 90 90 90 90 [ ]*bts %edx,-0x6f6f6f70\(%eax\) + 545: 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%edx,-0x6f6f6f70\(%eax\) + 54d: 0f ad 90 90 90 90 90 [ ]*shrd %cl,%edx,-0x6f6f6f70\(%eax\) + 554: 0f af 90 90 90 90 90 [ ]*imul -0x6f6f6f70\(%eax\),%edx + 55b: 0f b0 90 90 90 90 90 [ ]*cmpxchg %dl,-0x6f6f6f70\(%eax\) + 562: 0f b1 90 90 90 90 90 [ ]*cmpxchg %edx,-0x6f6f6f70\(%eax\) + 569: 0f b2 90 90 90 90 90 [ ]*lss -0x6f6f6f70\(%eax\),%edx + 570: 0f b3 90 90 90 90 90 [ ]*btr %edx,-0x6f6f6f70\(%eax\) + 577: 0f b4 90 90 90 90 90 [ ]*lfs -0x6f6f6f70\(%eax\),%edx + 57e: 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%edx + 585: 0f b6 90 90 90 90 90 [ ]*movzbl -0x6f6f6f70\(%eax\),%edx + 58c: 0f b7 90 90 90 90 90 [ ]*movzwl -0x6f6f6f70\(%eax\),%edx 593: 0f b9 [ ]*ud2b - 595: 0f bb 90 90 90 90 90 [ ]*btc %edx,0x90909090\(%eax\) - 59c: 0f bc 90 90 90 90 90 [ ]*bsf 0x90909090\(%eax\),%edx - 5a3: 0f bd 90 90 90 90 90 [ ]*bsr 0x90909090\(%eax\),%edx - 5aa: 0f be 90 90 90 90 90 [ ]*movsbl 0x90909090\(%eax\),%edx - 5b1: 0f bf 90 90 90 90 90 [ ]*movswl 0x90909090\(%eax\),%edx - 5b8: 0f c0 90 90 90 90 90 [ ]*xadd %dl,0x90909090\(%eax\) - 5bf: 0f c1 90 90 90 90 90 [ ]*xadd %edx,0x90909090\(%eax\) + 595: 0f bb 90 90 90 90 90 [ ]*btc %edx,-0x6f6f6f70\(%eax\) + 59c: 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%edx + 5a3: 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%edx + 5aa: 0f be 90 90 90 90 90 [ ]*movsbl -0x6f6f6f70\(%eax\),%edx + 5b1: 0f bf 90 90 90 90 90 [ ]*movswl -0x6f6f6f70\(%eax\),%edx + 5b8: 0f c0 90 90 90 90 90 [ ]*xadd %dl,-0x6f6f6f70\(%eax\) + 5bf: 0f c1 90 90 90 90 90 [ ]*xadd %edx,-0x6f6f6f70\(%eax\) 5c6: 0f c8 [ ]*bswap %eax 5c8: 0f c9 [ ]*bswap %ecx 5ca: 0f ca [ ]*bswap %edx @@ -373,65 +373,65 @@ Disassembly of section .text: 5d0: 0f cd [ ]*bswap %ebp 5d2: 0f ce [ ]*bswap %esi 5d4: 0f cf [ ]*bswap %edi - 5d6: 0f d1 90 90 90 90 90 [ ]*psrlw 0x90909090\(%eax\),%mm2 - 5dd: 0f d2 90 90 90 90 90 [ ]*psrld 0x90909090\(%eax\),%mm2 - 5e4: 0f d3 90 90 90 90 90 [ ]*psrlq 0x90909090\(%eax\),%mm2 - 5eb: 0f d5 90 90 90 90 90 [ ]*pmullw 0x90909090\(%eax\),%mm2 - 5f2: 0f d8 90 90 90 90 90 [ ]*psubusb 0x90909090\(%eax\),%mm2 - 5f9: 0f d9 90 90 90 90 90 [ ]*psubusw 0x90909090\(%eax\),%mm2 - 600: 0f db 90 90 90 90 90 [ ]*pand 0x90909090\(%eax\),%mm2 - 607: 0f dc 90 90 90 90 90 [ ]*paddusb 0x90909090\(%eax\),%mm2 - 60e: 0f dd 90 90 90 90 90 [ ]*paddusw 0x90909090\(%eax\),%mm2 - 615: 0f df 90 90 90 90 90 [ ]*pandn 0x90909090\(%eax\),%mm2 - 61c: 0f e1 90 90 90 90 90 [ ]*psraw 0x90909090\(%eax\),%mm2 - 623: 0f e2 90 90 90 90 90 [ ]*psrad 0x90909090\(%eax\),%mm2 - 62a: 0f e5 90 90 90 90 90 [ ]*pmulhw 0x90909090\(%eax\),%mm2 - 631: 0f e8 90 90 90 90 90 [ ]*psubsb 0x90909090\(%eax\),%mm2 - 638: 0f e9 90 90 90 90 90 [ ]*psubsw 0x90909090\(%eax\),%mm2 - 63f: 0f eb 90 90 90 90 90 [ ]*por 0x90909090\(%eax\),%mm2 - 646: 0f ec 90 90 90 90 90 [ ]*paddsb 0x90909090\(%eax\),%mm2 - 64d: 0f ed 90 90 90 90 90 [ ]*paddsw 0x90909090\(%eax\),%mm2 - 654: 0f ef 90 90 90 90 90 [ ]*pxor 0x90909090\(%eax\),%mm2 - 65b: 0f f1 90 90 90 90 90 [ ]*psllw 0x90909090\(%eax\),%mm2 - 662: 0f f2 90 90 90 90 90 [ ]*pslld 0x90909090\(%eax\),%mm2 - 669: 0f f3 90 90 90 90 90 [ ]*psllq 0x90909090\(%eax\),%mm2 - 670: 0f f5 90 90 90 90 90 [ ]*pmaddwd 0x90909090\(%eax\),%mm2 - 677: 0f f8 90 90 90 90 90 [ ]*psubb 0x90909090\(%eax\),%mm2 - 67e: 0f f9 90 90 90 90 90 [ ]*psubw 0x90909090\(%eax\),%mm2 - 685: 0f fa 90 90 90 90 90 [ ]*psubd 0x90909090\(%eax\),%mm2 - 68c: 0f fc 90 90 90 90 90 [ ]*paddb 0x90909090\(%eax\),%mm2 - 693: 0f fd 90 90 90 90 90 [ ]*paddw 0x90909090\(%eax\),%mm2 - 69a: 0f fe 90 90 90 90 90 [ ]*paddd 0x90909090\(%eax\),%mm2 - 6a1: 66 01 90 90 90 90 90 [ ]*add %dx,0x90909090\(%eax\) - 6a8: 66 03 90 90 90 90 90 [ ]*add 0x90909090\(%eax\),%dx + 5d6: 0f d1 90 90 90 90 90 [ ]*psrlw -0x6f6f6f70\(%eax\),%mm2 + 5dd: 0f d2 90 90 90 90 90 [ ]*psrld -0x6f6f6f70\(%eax\),%mm2 + 5e4: 0f d3 90 90 90 90 90 [ ]*psrlq -0x6f6f6f70\(%eax\),%mm2 + 5eb: 0f d5 90 90 90 90 90 [ ]*pmullw -0x6f6f6f70\(%eax\),%mm2 + 5f2: 0f d8 90 90 90 90 90 [ ]*psubusb -0x6f6f6f70\(%eax\),%mm2 + 5f9: 0f d9 90 90 90 90 90 [ ]*psubusw -0x6f6f6f70\(%eax\),%mm2 + 600: 0f db 90 90 90 90 90 [ ]*pand -0x6f6f6f70\(%eax\),%mm2 + 607: 0f dc 90 90 90 90 90 [ ]*paddusb -0x6f6f6f70\(%eax\),%mm2 + 60e: 0f dd 90 90 90 90 90 [ ]*paddusw -0x6f6f6f70\(%eax\),%mm2 + 615: 0f df 90 90 90 90 90 [ ]*pandn -0x6f6f6f70\(%eax\),%mm2 + 61c: 0f e1 90 90 90 90 90 [ ]*psraw -0x6f6f6f70\(%eax\),%mm2 + 623: 0f e2 90 90 90 90 90 [ ]*psrad -0x6f6f6f70\(%eax\),%mm2 + 62a: 0f e5 90 90 90 90 90 [ ]*pmulhw -0x6f6f6f70\(%eax\),%mm2 + 631: 0f e8 90 90 90 90 90 [ ]*psubsb -0x6f6f6f70\(%eax\),%mm2 + 638: 0f e9 90 90 90 90 90 [ ]*psubsw -0x6f6f6f70\(%eax\),%mm2 + 63f: 0f eb 90 90 90 90 90 [ ]*por -0x6f6f6f70\(%eax\),%mm2 + 646: 0f ec 90 90 90 90 90 [ ]*paddsb -0x6f6f6f70\(%eax\),%mm2 + 64d: 0f ed 90 90 90 90 90 [ ]*paddsw -0x6f6f6f70\(%eax\),%mm2 + 654: 0f ef 90 90 90 90 90 [ ]*pxor -0x6f6f6f70\(%eax\),%mm2 + 65b: 0f f1 90 90 90 90 90 [ ]*psllw -0x6f6f6f70\(%eax\),%mm2 + 662: 0f f2 90 90 90 90 90 [ ]*pslld -0x6f6f6f70\(%eax\),%mm2 + 669: 0f f3 90 90 90 90 90 [ ]*psllq -0x6f6f6f70\(%eax\),%mm2 + 670: 0f f5 90 90 90 90 90 [ ]*pmaddwd -0x6f6f6f70\(%eax\),%mm2 + 677: 0f f8 90 90 90 90 90 [ ]*psubb -0x6f6f6f70\(%eax\),%mm2 + 67e: 0f f9 90 90 90 90 90 [ ]*psubw -0x6f6f6f70\(%eax\),%mm2 + 685: 0f fa 90 90 90 90 90 [ ]*psubd -0x6f6f6f70\(%eax\),%mm2 + 68c: 0f fc 90 90 90 90 90 [ ]*paddb -0x6f6f6f70\(%eax\),%mm2 + 693: 0f fd 90 90 90 90 90 [ ]*paddw -0x6f6f6f70\(%eax\),%mm2 + 69a: 0f fe 90 90 90 90 90 [ ]*paddd -0x6f6f6f70\(%eax\),%mm2 + 6a1: 66 01 90 90 90 90 90 [ ]*add %dx,-0x6f6f6f70\(%eax\) + 6a8: 66 03 90 90 90 90 90 [ ]*add -0x6f6f6f70\(%eax\),%dx 6af: 66 05 90 90 [ ]*add \$0x9090,%ax 6b3: 66 06 [ ]*pushw %es 6b5: 66 07 [ ]*popw %es - 6b7: 66 09 90 90 90 90 90 [ ]*or %dx,0x90909090\(%eax\) - 6be: 66 0b 90 90 90 90 90 [ ]*or 0x90909090\(%eax\),%dx + 6b7: 66 09 90 90 90 90 90 [ ]*or %dx,-0x6f6f6f70\(%eax\) + 6be: 66 0b 90 90 90 90 90 [ ]*or -0x6f6f6f70\(%eax\),%dx 6c5: 66 0d 90 90 [ ]*or \$0x9090,%ax 6c9: 66 0e [ ]*pushw %cs - 6cb: 66 11 90 90 90 90 90 [ ]*adc %dx,0x90909090\(%eax\) - 6d2: 66 13 90 90 90 90 90 [ ]*adc 0x90909090\(%eax\),%dx + 6cb: 66 11 90 90 90 90 90 [ ]*adc %dx,-0x6f6f6f70\(%eax\) + 6d2: 66 13 90 90 90 90 90 [ ]*adc -0x6f6f6f70\(%eax\),%dx 6d9: 66 15 90 90 [ ]*adc \$0x9090,%ax 6dd: 66 16 [ ]*pushw %ss 6df: 66 17 [ ]*popw %ss - 6e1: 66 19 90 90 90 90 90 [ ]*sbb %dx,0x90909090\(%eax\) - 6e8: 66 1b 90 90 90 90 90 [ ]*sbb 0x90909090\(%eax\),%dx + 6e1: 66 19 90 90 90 90 90 [ ]*sbb %dx,-0x6f6f6f70\(%eax\) + 6e8: 66 1b 90 90 90 90 90 [ ]*sbb -0x6f6f6f70\(%eax\),%dx 6ef: 66 1d 90 90 [ ]*sbb \$0x9090,%ax 6f3: 66 1e [ ]*pushw %ds 6f5: 66 1f [ ]*popw %ds - 6f7: 66 21 90 90 90 90 90 [ ]*and %dx,0x90909090\(%eax\) - 6fe: 66 23 90 90 90 90 90 [ ]*and 0x90909090\(%eax\),%dx + 6f7: 66 21 90 90 90 90 90 [ ]*and %dx,-0x6f6f6f70\(%eax\) + 6fe: 66 23 90 90 90 90 90 [ ]*and -0x6f6f6f70\(%eax\),%dx 705: 66 25 90 90 [ ]*and \$0x9090,%ax - 709: 66 29 90 90 90 90 90 [ ]*sub %dx,0x90909090\(%eax\) - 710: 66 2b 90 90 90 90 90 [ ]*sub 0x90909090\(%eax\),%dx + 709: 66 29 90 90 90 90 90 [ ]*sub %dx,-0x6f6f6f70\(%eax\) + 710: 66 2b 90 90 90 90 90 [ ]*sub -0x6f6f6f70\(%eax\),%dx 717: 66 2d 90 90 [ ]*sub \$0x9090,%ax - 71b: 66 31 90 90 90 90 90 [ ]*xor %dx,0x90909090\(%eax\) - 722: 66 33 90 90 90 90 90 [ ]*xor 0x90909090\(%eax\),%dx + 71b: 66 31 90 90 90 90 90 [ ]*xor %dx,-0x6f6f6f70\(%eax\) + 722: 66 33 90 90 90 90 90 [ ]*xor -0x6f6f6f70\(%eax\),%dx 729: 66 35 90 90 [ ]*xor \$0x9090,%ax - 72d: 66 39 90 90 90 90 90 [ ]*cmp %dx,0x90909090\(%eax\) - 734: 66 3b 90 90 90 90 90 [ ]*cmp 0x90909090\(%eax\),%dx + 72d: 66 39 90 90 90 90 90 [ ]*cmp %dx,-0x6f6f6f70\(%eax\) + 734: 66 3b 90 90 90 90 90 [ ]*cmp -0x6f6f6f70\(%eax\),%dx 73b: 66 3d 90 90 [ ]*cmp \$0x9090,%ax 73f: 66 40 [ ]*inc %ax 741: 66 41 [ ]*inc %cx @@ -467,22 +467,22 @@ Disassembly of section .text: 77d: 66 5f [ ]*pop %di 77f: 66 60 [ ]*pushaw 781: 66 61 [ ]*popaw - 783: 66 62 90 90 90 90 90 [ ]*bound %dx,0x90909090\(%eax\) + 783: 66 62 90 90 90 90 90 [ ]*bound %dx,-0x6f6f6f70\(%eax\) 78a: 66 68 90 90 [ ]*pushw \$0x9090 - 78e: 66 69 90 90 90 90 90 90 90 [ ]*imul \$0x9090,0x90909090\(%eax\),%dx + 78e: 66 69 90 90 90 90 90 90 90 [ ]*imul \$0x9090,-0x6f6f6f70\(%eax\),%dx 797: 66 6a 90 [ ]*pushw \$0xffffff90 - 79a: 66 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,0x90909090\(%eax\),%dx + 79a: 66 6b 90 90 90 90 90 90 [ ]*imul \$0xffffff90,-0x6f6f6f70\(%eax\),%dx 7a2: 66 6d [ ]*insw \(%dx\),%es:\(%edi\) 7a4: 66 6f [ ]*outsw %ds:\(%esi\),\(%dx\) - 7a6: 66 81 90 90 90 90 90 90 90 [ ]*adcw \$0x9090,0x90909090\(%eax\) - 7af: 66 83 90 90 90 90 90 90 [ ]*adcw \$0xffffff90,0x90909090\(%eax\) - 7b7: 66 85 90 90 90 90 90 [ ]*test %dx,0x90909090\(%eax\) - 7be: 66 87 90 90 90 90 90 [ ]*xchg %dx,0x90909090\(%eax\) - 7c5: 66 89 90 90 90 90 90 [ ]*mov %dx,0x90909090\(%eax\) - 7cc: 66 8b 90 90 90 90 90 [ ]*mov 0x90909090\(%eax\),%dx - 7d3: 8c 90 90 90 90 90 [ ]*mov[w ] %ss,0x90909090\(%eax\) - 7d9: 66 8d 90 90 90 90 90 [ ]*lea 0x90909090\(%eax\),%dx - 7e0: 66 8f 80 90 90 90 90 [ ]*popw 0x90909090\(%eax\) + 7a6: 66 81 90 90 90 90 90 90 90 [ ]*adcw \$0x9090,-0x6f6f6f70\(%eax\) + 7af: 66 83 90 90 90 90 90 90 [ ]*adcw \$0xffffff90,-0x6f6f6f70\(%eax\) + 7b7: 66 85 90 90 90 90 90 [ ]*test %dx,-0x6f6f6f70\(%eax\) + 7be: 66 87 90 90 90 90 90 [ ]*xchg %dx,-0x6f6f6f70\(%eax\) + 7c5: 66 89 90 90 90 90 90 [ ]*mov %dx,-0x6f6f6f70\(%eax\) + 7cc: 66 8b 90 90 90 90 90 [ ]*mov -0x6f6f6f70\(%eax\),%dx + 7d3: 8c 90 90 90 90 90 [ ]*mov[w ] %ss,-0x6f6f6f70\(%eax\) + 7d9: 66 8d 90 90 90 90 90 [ ]*lea -0x6f6f6f70\(%eax\),%dx + 7e0: 66 8f 80 90 90 90 90 [ ]*popw -0x6f6f6f70\(%eax\) 7e7: 66 91 [ ]*xchg %ax,%cx 7e9: 66 92 [ ]*xchg %ax,%dx 7eb: 66 93 [ ]*xchg %ax,%bx @@ -511,65 +511,80 @@ Disassembly of section .text: 831: 66 bd 90 90 [ ]*mov \$0x9090,%bp 835: 66 be 90 90 [ ]*mov \$0x9090,%si 839: 66 bf 90 90 [ ]*mov \$0x9090,%di - 83d: 66 c1 90 90 90 90 90 90 [ ]*rclw \$0x90,0x90909090\(%eax\) + 83d: 66 c1 90 90 90 90 90 90 [ ]*rclw \$0x90,-0x6f6f6f70\(%eax\) 845: 66 c2 90 90 [ ]*retw \$0x9090 849: 66 c3 [ ]*retw - 84b: 66 c4 90 90 90 90 90 [ ]*les 0x90909090\(%eax\),%dx - 852: 66 c5 90 90 90 90 90 [ ]*lds 0x90909090\(%eax\),%dx - 859: 66 c7 80 90 90 90 90 90 90 [ ]*movw \$0x9090,0x90909090\(%eax\) + 84b: 66 c4 90 90 90 90 90 [ ]*les -0x6f6f6f70\(%eax\),%dx + 852: 66 c5 90 90 90 90 90 [ ]*lds -0x6f6f6f70\(%eax\),%dx + 859: 66 c7 80 90 90 90 90 90 90 [ ]*movw \$0x9090,-0x6f6f6f70\(%eax\) 862: 66 c8 90 90 90 [ ]*enterw \$0x9090,\$0x90 867: 66 c9 [ ]*leavew 869: 66 ca 90 90 [ ]*lretw \$0x9090 86d: 66 cb [ ]*lretw 86f: 66 cf [ ]*iretw - 871: 66 d1 90 90 90 90 90 [ ]*rclw 0x90909090\(%eax\) - 878: 66 d3 90 90 90 90 90 [ ]*rclw %cl,0x90909090\(%eax\) + 871: 66 d1 90 90 90 90 90 [ ]*rclw -0x6f6f6f70\(%eax\) + 878: 66 d3 90 90 90 90 90 [ ]*rclw %cl,-0x6f6f6f70\(%eax\) 87f: 66 e5 90 [ ]*in \$0x90,%ax 882: 66 e7 90 [ ]*out %ax,\$0x90 885: 66 e8 8f 90 [ ]*callw (0x)?9918.* 889: 66 ea 90 90 90 90 [ ]*ljmpw \$0x9090,\$0x9090 88f: 66 ed [ ]*in \(%dx\),%ax 891: 66 ef [ ]*out %ax,\(%dx\) - 893: 66 f7 90 90 90 90 90 [ ]*notw 0x90909090\(%eax\) - 89a: 66 ff 90 90 90 90 90 [ ]*callw \*0x90909090\(%eax\) - 8a1: 66 0f 02 90 90 90 90 90 [ ]*lar 0x90909090\(%eax\),%dx - 8a9: 66 0f 03 90 90 90 90 90 [ ]*lsl 0x90909090\(%eax\),%dx - 8b1: 66 0f 40 90 90 90 90 90 [ ]*cmovo 0x90909090\(%eax\),%dx - 8b9: 66 0f 41 90 90 90 90 90 [ ]*cmovno 0x90909090\(%eax\),%dx - 8c1: 66 0f 42 90 90 90 90 90 [ ]*cmovb 0x90909090\(%eax\),%dx - 8c9: 66 0f 43 90 90 90 90 90 [ ]*cmovae 0x90909090\(%eax\),%dx - 8d1: 66 0f 44 90 90 90 90 90 [ ]*cmove 0x90909090\(%eax\),%dx - 8d9: 66 0f 45 90 90 90 90 90 [ ]*cmovne 0x90909090\(%eax\),%dx - 8e1: 66 0f 46 90 90 90 90 90 [ ]*cmovbe 0x90909090\(%eax\),%dx - 8e9: 66 0f 47 90 90 90 90 90 [ ]*cmova 0x90909090\(%eax\),%dx - 8f1: 66 0f 48 90 90 90 90 90 [ ]*cmovs 0x90909090\(%eax\),%dx - 8f9: 66 0f 49 90 90 90 90 90 [ ]*cmovns 0x90909090\(%eax\),%dx - 901: 66 0f 4a 90 90 90 90 90 [ ]*cmovp 0x90909090\(%eax\),%dx - 909: 66 0f 4b 90 90 90 90 90 [ ]*cmovnp 0x90909090\(%eax\),%dx - 911: 66 0f 4c 90 90 90 90 90 [ ]*cmovl 0x90909090\(%eax\),%dx - 919: 66 0f 4d 90 90 90 90 90 [ ]*cmovge 0x90909090\(%eax\),%dx - 921: 66 0f 4e 90 90 90 90 90 [ ]*cmovle 0x90909090\(%eax\),%dx - 929: 66 0f 4f 90 90 90 90 90 [ ]*cmovg 0x90909090\(%eax\),%dx + 893: 66 f7 90 90 90 90 90 [ ]*notw -0x6f6f6f70\(%eax\) + 89a: 66 ff 90 90 90 90 90 [ ]*callw \*-0x6f6f6f70\(%eax\) + 8a1: 66 0f 02 90 90 90 90 90 [ ]*lar -0x6f6f6f70\(%eax\),%dx + 8a9: 66 0f 03 90 90 90 90 90 [ ]*lsl -0x6f6f6f70\(%eax\),%dx + 8b1: 66 0f 40 90 90 90 90 90 [ ]*cmovo -0x6f6f6f70\(%eax\),%dx + 8b9: 66 0f 41 90 90 90 90 90 [ ]*cmovno -0x6f6f6f70\(%eax\),%dx + 8c1: 66 0f 42 90 90 90 90 90 [ ]*cmovb -0x6f6f6f70\(%eax\),%dx + 8c9: 66 0f 43 90 90 90 90 90 [ ]*cmovae -0x6f6f6f70\(%eax\),%dx + 8d1: 66 0f 44 90 90 90 90 90 [ ]*cmove -0x6f6f6f70\(%eax\),%dx + 8d9: 66 0f 45 90 90 90 90 90 [ ]*cmovne -0x6f6f6f70\(%eax\),%dx + 8e1: 66 0f 46 90 90 90 90 90 [ ]*cmovbe -0x6f6f6f70\(%eax\),%dx + 8e9: 66 0f 47 90 90 90 90 90 [ ]*cmova -0x6f6f6f70\(%eax\),%dx + 8f1: 66 0f 48 90 90 90 90 90 [ ]*cmovs -0x6f6f6f70\(%eax\),%dx + 8f9: 66 0f 49 90 90 90 90 90 [ ]*cmovns -0x6f6f6f70\(%eax\),%dx + 901: 66 0f 4a 90 90 90 90 90 [ ]*cmovp -0x6f6f6f70\(%eax\),%dx + 909: 66 0f 4b 90 90 90 90 90 [ ]*cmovnp -0x6f6f6f70\(%eax\),%dx + 911: 66 0f 4c 90 90 90 90 90 [ ]*cmovl -0x6f6f6f70\(%eax\),%dx + 919: 66 0f 4d 90 90 90 90 90 [ ]*cmovge -0x6f6f6f70\(%eax\),%dx + 921: 66 0f 4e 90 90 90 90 90 [ ]*cmovle -0x6f6f6f70\(%eax\),%dx + 929: 66 0f 4f 90 90 90 90 90 [ ]*cmovg -0x6f6f6f70\(%eax\),%dx 931: 66 0f a0 [ ]*pushw %fs 934: 66 0f a1 [ ]*popw %fs - 937: 66 0f a3 90 90 90 90 90 [ ]*bt %dx,0x90909090\(%eax\) - 93f: 66 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%dx,0x90909090\(%eax\) - 948: 66 0f a5 90 90 90 90 90 [ ]*shld %cl,%dx,0x90909090\(%eax\) + 937: 66 0f a3 90 90 90 90 90 [ ]*bt %dx,-0x6f6f6f70\(%eax\) + 93f: 66 0f a4 90 90 90 90 90 90 [ ]*shld \$0x90,%dx,-0x6f6f6f70\(%eax\) + 948: 66 0f a5 90 90 90 90 90 [ ]*shld %cl,%dx,-0x6f6f6f70\(%eax\) 950: 66 0f a8 [ ]*pushw %gs 953: 66 0f a9 [ ]*popw %gs - 956: 66 0f ab 90 90 90 90 90 [ ]*bts %dx,0x90909090\(%eax\) - 95e: 66 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%dx,0x90909090\(%eax\) - 967: 66 0f ad 90 90 90 90 90 [ ]*shrd %cl,%dx,0x90909090\(%eax\) - 96f: 66 0f af 90 90 90 90 90 [ ]*imul 0x90909090\(%eax\),%dx - 977: 66 0f b1 90 90 90 90 90 [ ]*cmpxchg %dx,0x90909090\(%eax\) - 97f: 66 0f b2 90 90 90 90 90 [ ]*lss 0x90909090\(%eax\),%dx - 987: 66 0f b3 90 90 90 90 90 [ ]*btr %dx,0x90909090\(%eax\) - 98f: 66 0f b4 90 90 90 90 90 [ ]*lfs 0x90909090\(%eax\),%dx - 997: 66 0f b5 90 90 90 90 90 [ ]*lgs 0x90909090\(%eax\),%dx - 99f: 66 0f b6 90 90 90 90 90 [ ]*movzbw 0x90909090\(%eax\),%dx - 9a7: 66 0f bb 90 90 90 90 90 [ ]*btc %dx,0x90909090\(%eax\) - 9af: 66 0f bc 90 90 90 90 90 [ ]*bsf 0x90909090\(%eax\),%dx - 9b7: 66 0f bd 90 90 90 90 90 [ ]*bsr 0x90909090\(%eax\),%dx - 9bf: 66 0f be 90 90 90 90 90 [ ]*movsbw 0x90909090\(%eax\),%dx - 9c7: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,0x90909090\(%eax\) - \.\.\. + 956: 66 0f ab 90 90 90 90 90 [ ]*bts %dx,-0x6f6f6f70\(%eax\) + 95e: 66 0f ac 90 90 90 90 90 90 [ ]*shrd \$0x90,%dx,-0x6f6f6f70\(%eax\) + 967: 66 0f ad 90 90 90 90 90 [ ]*shrd %cl,%dx,-0x6f6f6f70\(%eax\) + 96f: 66 0f af 90 90 90 90 90 [ ]*imul -0x6f6f6f70\(%eax\),%dx + 977: 66 0f b1 90 90 90 90 90 [ ]*cmpxchg %dx,-0x6f6f6f70\(%eax\) + 97f: 66 0f b2 90 90 90 90 90 [ ]*lss -0x6f6f6f70\(%eax\),%dx + 987: 66 0f b3 90 90 90 90 90 [ ]*btr %dx,-0x6f6f6f70\(%eax\) + 98f: 66 0f b4 90 90 90 90 90 [ ]*lfs -0x6f6f6f70\(%eax\),%dx + 997: 66 0f b5 90 90 90 90 90 [ ]*lgs -0x6f6f6f70\(%eax\),%dx + 99f: 66 0f b6 90 90 90 90 90 [ ]*movzbw -0x6f6f6f70\(%eax\),%dx + 9a7: 66 0f bb 90 90 90 90 90 [ ]*btc %dx,-0x6f6f6f70\(%eax\) + 9af: 66 0f bc 90 90 90 90 90 [ ]*bsf -0x6f6f6f70\(%eax\),%dx + 9b7: 66 0f bd 90 90 90 90 90 [ ]*bsr -0x6f6f6f70\(%eax\),%dx + 9bf: 66 0f be 90 90 90 90 90 [ ]*movsbw -0x6f6f6f70\(%eax\),%dx + 9c7: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,-0x6f6f6f70\(%eax\) + 9cf: 66 90 [ ]*xchg %ax,%ax + 9d1: 0f 00 c0 [ ]*sldt %eax + 9d4: 66 0f 00 c0 [ ]*sldt %ax + 9d8: 0f 00 00 [ ]*sldt \(%eax\) + 9db: 0f 01 e0 [ ]*smsw %eax + 9de: 66 0f 01 e0 [ ]*smsw %ax + 9e2: 0f 01 20 [ ]*smsw \(%eax\) + 9e5: 0f 00 c8 [ ]*str %eax + 9e8: 66 0f 00 c8 [ ]*str %ax + 9ec: 0f 00 08 [ ]*str \(%eax\) + 9ef: 0f ad d0 [ ]*shrd %cl,%edx,%eax + 9f2: 0f a5 d0 [ ]*shld %cl,%edx,%eax + 9f5: 85 c3 [ ]*test %eax,%ebx + 9f7: 85 d8 [ ]*test %ebx,%eax + 9f9: 85 18 [ ]*test %ebx,\(%eax\) +#pass diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s index 8d7cd050f165..b54b9fcf89bd 100644 --- a/gas/testsuite/gas/i386/opcode.s +++ b/gas/testsuite/gas/i386/opcode.s @@ -566,5 +566,24 @@ foo: movsbw 0x90909090(%eax),%dx xadd %dx,0x90909090(%eax) + xchg %ax,%ax + + sldt %eax + sldt %ax + sldt (%eax) + smsw %eax + smsw %ax + smsw (%eax) + str %eax + str %ax + str (%eax) + + shrd %cl,%edx,%eax + shld %cl,%edx,%eax + + test %eax,%ebx + test %ebx,%eax + test (%eax),%ebx + # Force a good alignment. .p2align 4,0 diff --git a/gas/testsuite/gas/i386/prefix.d b/gas/testsuite/gas/i386/prefix.d index 229a2a766a30..9021f09e250b 100644 --- a/gas/testsuite/gas/i386/prefix.d +++ b/gas/testsuite/gas/i386/prefix.d @@ -6,10 +6,10 @@ Disassembly of section .text: 0+000 <foo>: - 0: 9b 67 26 d9 3c [ ]*addr16 fstcw %es:\(%si\) + 0: 9b 26 67 d9 3c [ ]*addr16 fstcw %es:\(%si\) 5: 9b df e0 [ ]*fstsw %ax 8: 9b df e0 [ ]*fstsw %ax b: 9b df e0 [ ]*fstsw %ax e: 9b 67 df e0 [ ]*addr16 fstsw %ax - 12: f3 67 66 36 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\) + 12: 36 67 66 f3 a7 [ ]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\) #pass diff --git a/gas/testsuite/gas/i386/prescott.d b/gas/testsuite/gas/i386/prescott.d index 1e66065433ac..9b701c007d4b 100644 --- a/gas/testsuite/gas/i386/prescott.d +++ b/gas/testsuite/gas/i386/prescott.d @@ -10,9 +10,9 @@ Disassembly of section .text: 4: 66 0f d0 ca [ ]*addsubpd %xmm2,%xmm1 8: f2 0f d0 13 [ ]*addsubps \(%ebx\),%xmm2 c: f2 0f d0 dc [ ]*addsubps %xmm4,%xmm3 - 10: df 88 90 90 90 90 [ ]*fisttp 0x90909090\(%eax\) - 16: db 88 90 90 90 90 [ ]*fisttpl 0x90909090\(%eax\) - 1c: dd 88 90 90 90 90 [ ]*fisttpll 0x90909090\(%eax\) + 10: df 88 90 90 90 90 [ ]*fisttp -0x6f6f6f70\(%eax\) + 16: db 88 90 90 90 90 [ ]*fisttpl -0x6f6f6f70\(%eax\) + 1c: dd 88 90 90 90 90 [ ]*fisttpll -0x6f6f6f70\(%eax\) 22: 66 0f 7c 65 00 [ ]*haddpd 0x0\(%ebp\),%xmm4 27: 66 0f 7c ee [ ]*haddpd %xmm6,%xmm5 2b: f2 0f 7c 37 [ ]*haddps \(%edi\),%xmm6 diff --git a/gas/testsuite/gas/i386/reloc64.d b/gas/testsuite/gas/i386/reloc64.d index 11dfdb4fedd2..333deaa3a614 100644 --- a/gas/testsuite/gas/i386/reloc64.d +++ b/gas/testsuite/gas/i386/reloc64.d @@ -47,6 +47,7 @@ Disassembly of section \.text: .*[ ]+R_X86_64_TPOFF64[ ]+xtrn .*[ ]+R_X86_64_TPOFF32[ ]+xtrn .*[ ]+R_X86_64_TPOFF32[ ]+xtrn +.*[ ]+R_X86_64_TPOFF32[ ]+xtrn Disassembly of section \.data: #... .*[ ]+R_X86_64_64[ ]+xtrn diff --git a/gas/testsuite/gas/i386/reloc64.s b/gas/testsuite/gas/i386/reloc64.s index 47ebfa8dc0ad..7fd741af8395 100644 --- a/gas/testsuite/gas/i386/reloc64.s +++ b/gas/testsuite/gas/i386/reloc64.s @@ -195,3 +195,6 @@ bad .byte xtrn@gottpoff bad .byte xtrn@tlsld bad .byte xtrn@dtpoff bad .byte xtrn@tpoff + + .text + mov xtrn@tpoff (%rbx), %eax diff --git a/gas/testsuite/gas/i386/rep-suffix.d b/gas/testsuite/gas/i386/rep-suffix.d index 9eaaf3dd5d98..ac4e606be0a5 100644 --- a/gas/testsuite/gas/i386/rep-suffix.d +++ b/gas/testsuite/gas/i386/rep-suffix.d @@ -8,8 +8,8 @@ Disassembly of section .text: 0+000 <_start>: 0: f3 ac[ ]+rep lodsb %ds:\(%esi\),%al 2: f3 aa[ ]+rep stosb %al,%es:\(%edi\) - 4: f3 66 ad[ ]+rep lodsw %ds:\(%esi\),%ax - 7: f3 66 ab[ ]+rep stosw %ax,%es:\(%edi\) + 4: 66 f3 ad[ ]+rep lodsw %ds:\(%esi\),%ax + 7: 66 f3 ab[ ]+rep stosw %ax,%es:\(%edi\) a: f3 ad[ ]+rep lodsl %ds:\(%esi\),%eax c: f3 ab[ ]+rep stosl %eax,%es:\(%edi\) #pass diff --git a/gas/testsuite/gas/i386/rep.d b/gas/testsuite/gas/i386/rep.d index f43cc5feb6cf..279924863940 100644 --- a/gas/testsuite/gas/i386/rep.d +++ b/gas/testsuite/gas/i386/rep.d @@ -13,13 +13,13 @@ Disassembly of section .text: 8: f3 aa[ ]+rep stos %al,%es:\(%edi\) a: f3 a6[ ]+repz cmpsb %es:\(%edi\),%ds:\(%esi\) c: f3 ae[ ]+repz scas %es:\(%edi\),%al - e: f3 66 6d[ ]+rep insw \(%dx\),%es:\(%edi\) - 11: f3 66 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\) - 14: f3 66 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\) - 17: f3 66 ad[ ]+rep lods %ds:\(%esi\),%ax - 1a: f3 66 ab[ ]+rep stos %ax,%es:\(%edi\) - 1d: f3 66 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\) - 20: f3 66 af[ ]+repz scas %es:\(%edi\),%ax + e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%edi\) + 11: 66 f3 6f[ ]+rep outsw %ds:\(%esi\),\(%dx\) + 14: 66 f3 a5[ ]+rep movsw %ds:\(%esi\),%es:\(%edi\) + 17: 66 f3 ad[ ]+rep lods %ds:\(%esi\),%ax + 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%edi\) + 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%edi\),%ds:\(%esi\) + 20: 66 f3 af[ ]+repz scas %es:\(%edi\),%ax 23: f3 6d[ ]+rep insl \(%dx\),%es:\(%edi\) 25: f3 6f[ ]+rep outsl %ds:\(%esi\),\(%dx\) 27: f3 a5[ ]+rep movsl %ds:\(%esi\),%es:\(%edi\) @@ -27,25 +27,25 @@ Disassembly of section .text: 2b: f3 ab[ ]+rep stos %eax,%es:\(%edi\) 2d: f3 a7[ ]+repz cmpsl %es:\(%edi\),%ds:\(%esi\) 2f: f3 af[ ]+repz scas %es:\(%edi\),%eax - 31: f3 67 6c[ ]+rep addr16 insb \(%dx\),%es:\(%di\) - 34: f3 67 6e[ ]+rep addr16 outsb %ds:\(%si\),\(%dx\) - 37: f3 67 a4[ ]+rep addr16 movsb %ds:\(%si\),%es:\(%di\) - 3a: f3 67 ac[ ]+rep addr16 lods %ds:\(%si\),%al - 3d: f3 67 aa[ ]+rep addr16 stos %al,%es:\(%di\) - 40: f3 67 a6[ ]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\) - 43: f3 67 ae[ ]+repz addr16 scas %es:\(%di\),%al - 46: f3 67 66 6d[ ]+rep addr16 insw \(%dx\),%es:\(%di\) - 4a: f3 67 66 6f[ ]+rep addr16 outsw %ds:\(%si\),\(%dx\) - 4e: f3 67 66 a5[ ]+rep addr16 movsw %ds:\(%si\),%es:\(%di\) - 52: f3 67 66 ad[ ]+rep addr16 lods %ds:\(%si\),%ax - 56: f3 67 66 ab[ ]+rep addr16 stos %ax,%es:\(%di\) - 5a: f3 67 66 a7[ ]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\) - 5e: f3 67 66 af[ ]+repz addr16 scas %es:\(%di\),%ax - 62: f3 67 6d[ ]+rep addr16 insl \(%dx\),%es:\(%di\) - 65: f3 67 6f[ ]+rep addr16 outsl %ds:\(%si\),\(%dx\) - 68: f3 67 a5[ ]+rep addr16 movsl %ds:\(%si\),%es:\(%di\) - 6b: f3 67 ad[ ]+rep addr16 lods %ds:\(%si\),%eax - 6e: f3 67 ab[ ]+rep addr16 stos %eax,%es:\(%di\) - 71: f3 67 a7[ ]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\) - 74: f3 67 af[ ]+repz addr16 scas %es:\(%di\),%eax + 31: 67 f3 6c[ ]+rep addr16 insb \(%dx\),%es:\(%di\) + 34: 67 f3 6e[ ]+rep addr16 outsb %ds:\(%si\),\(%dx\) + 37: 67 f3 a4[ ]+rep addr16 movsb %ds:\(%si\),%es:\(%di\) + 3a: 67 f3 ac[ ]+rep addr16 lods %ds:\(%si\),%al + 3d: 67 f3 aa[ ]+rep addr16 stos %al,%es:\(%di\) + 40: 67 f3 a6[ ]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\) + 43: 67 f3 ae[ ]+repz addr16 scas %es:\(%di\),%al + 46: 67 66 f3 6d[ ]+rep addr16 insw \(%dx\),%es:\(%di\) + 4a: 67 66 f3 6f[ ]+rep addr16 outsw %ds:\(%si\),\(%dx\) + 4e: 67 66 f3 a5[ ]+rep addr16 movsw %ds:\(%si\),%es:\(%di\) + 52: 67 66 f3 ad[ ]+rep addr16 lods %ds:\(%si\),%ax + 56: 67 66 f3 ab[ ]+rep addr16 stos %ax,%es:\(%di\) + 5a: 67 66 f3 a7[ ]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\) + 5e: 67 66 f3 af[ ]+repz addr16 scas %es:\(%di\),%ax + 62: 67 f3 6d[ ]+rep addr16 insl \(%dx\),%es:\(%di\) + 65: 67 f3 6f[ ]+rep addr16 outsl %ds:\(%si\),\(%dx\) + 68: 67 f3 a5[ ]+rep addr16 movsl %ds:\(%si\),%es:\(%di\) + 6b: 67 f3 ad[ ]+rep addr16 lods %ds:\(%si\),%eax + 6e: 67 f3 ab[ ]+rep addr16 stos %eax,%es:\(%di\) + 71: 67 f3 a7[ ]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\) + 74: 67 f3 af[ ]+repz addr16 scas %es:\(%di\),%eax ... diff --git a/gas/testsuite/gas/i386/rex.d b/gas/testsuite/gas/i386/rex.d index dab6b12580d1..9023b49ace4b 100644 --- a/gas/testsuite/gas/i386/rex.d +++ b/gas/testsuite/gas/i386/rex.d @@ -1,17 +1,33 @@ #objdump: -dw #name: x86-64 manual rex prefix use -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: 0+ <_start>: [ ]*[0-9a-f]+:[ ]+40 0f ae 00[ ]+rex fxsavel?[ ]+\(%rax\) -[ ]*[0-9a-f]+:[ ]+48 0f ae 00[ ]+(rex64 )?fxsaveq?[ ]+\(%rax\) +[ ]*[0-9a-f]+:[ ]+48 0f ae 00[ ]+(rex.W )?fxsaveq?[ ]+\(%rax\) [ ]*[0-9a-f]+:[ ]+41 0f ae 00[ ]+fxsavel?[ ]+\(%r8\) -[ ]*[0-9a-f]+:[ ]+49 0f ae 00[ ]+(rex64Z? )?fxsaveq?[ ]+\(%r8\) +[ ]*[0-9a-f]+:[ ]+49 0f ae 00[ ]+(rex.WB? )?fxsaveq?[ ]+\(%r8\) [ ]*[0-9a-f]+:[ ]+42 0f ae 04 05 00 00 00 00[ ]+fxsavel?[ ]+(0x0)?\(,%r8(,1)?\) -[ ]*[0-9a-f]+:[ ]+4a 0f ae 04 05 00 00 00 00[ ]+(rex64Y? )?fxsaveq?[ ]+(0x0)?\(,%r8(,1)?\) +[ ]*[0-9a-f]+:[ ]+4a 0f ae 04 05 00 00 00 00[ ]+(rex.WX? )?fxsaveq?[ ]+(0x0)?\(,%r8(,1)?\) [ ]*[0-9a-f]+:[ ]+43 0f ae 04 00[ ]+fxsavel?[ ]+\(%r8,%r8(,1)?\) -[ ]*[0-9a-f]+:[ ]+4b 0f ae 04 00[ ]+(rex64(YZ)? )?fxsaveq?[ ]+\(%r8,%r8(,1)?\) +[ ]*[0-9a-f]+:[ ]+4b 0f ae 04 00[ ]+(rex.W(XB)? )?fxsaveq?[ ]+\(%r8,%r8(,1)?\) +[ ]*[0-9a-f]+:[ ]+40[ ]+rex +[ ]*[0-9a-f]+:[ ]+41[ ]+rex.B +[ ]*[0-9a-f]+:[ ]+42[ ]+rex.X +[ ]*[0-9a-f]+:[ ]+43[ ]+rex.XB +[ ]*[0-9a-f]+:[ ]+44[ ]+rex.R +[ ]*[0-9a-f]+:[ ]+45[ ]+rex.RB +[ ]*[0-9a-f]+:[ ]+46[ ]+rex.RX +[ ]*[0-9a-f]+:[ ]+47[ ]+rex.RXB +[ ]*[0-9a-f]+:[ ]+48[ ]+rex.W +[ ]*[0-9a-f]+:[ ]+49[ ]+rex.WB +[ ]*[0-9a-f]+:[ ]+4a[ ]+rex.WX +[ ]*[0-9a-f]+:[ ]+4b[ ]+rex.WXB +[ ]*[0-9a-f]+:[ ]+4c[ ]+rex.WR +[ ]*[0-9a-f]+:[ ]+4d[ ]+rex.WRB +[ ]*[0-9a-f]+:[ ]+4e[ ]+rex.WRX +[ ]*[0-9a-f]+:[ ]+4f[ ]+rex.WRXB #pass diff --git a/gas/testsuite/gas/i386/rex.s b/gas/testsuite/gas/i386/rex.s index a142312a2c6b..6f1e38a47038 100644 --- a/gas/testsuite/gas/i386/rex.s +++ b/gas/testsuite/gas/i386/rex.s @@ -9,3 +9,21 @@ _start: rex64/fxsave (,%r8) rex/fxsave (%r8,%r8) rex64/fxsave (%r8,%r8) + +# Test prefixes family. + rex + rex.B + rex.X + rex.XB + rex.R + rex.RB + rex.RX + rex.RXB + rex.W + rex.WB + rex.WX + rex.WXB + rex.WR + rex.WRB + rex.WRX + rex.WRXB diff --git a/gas/testsuite/gas/i386/secrel.d b/gas/testsuite/gas/i386/secrel.d index 6a3b915fd77d..58967cb51414 100644 --- a/gas/testsuite/gas/i386/secrel.d +++ b/gas/testsuite/gas/i386/secrel.d @@ -4,23 +4,23 @@ .*: +file format pe-i386
RELOCATION RECORDS FOR \[\.data\]:
-OFFSET TYPE VALUE
-00000024 secrel32 \.text
-00000029 secrel32 \.text
-0000002e secrel32 \.text
-00000033 secrel32 \.text
-00000044 secrel32 \.data
-00000049 secrel32 \.data
-0000004e secrel32 \.data
-00000053 secrel32 \.data
-00000064 secrel32 \.rdata
-00000069 secrel32 \.rdata
-0000006e secrel32 \.rdata
-00000073 secrel32 \.rdata
-00000084 secrel32 ext24
-00000089 secrel32 ext2d
-0000008e secrel32 ext36
-00000093 secrel32 ext3f
+OFFSET[ ]+TYPE[ ]+VALUE
+0+24 secrel32 \.text
+0+29 secrel32 \.text
+0+2e secrel32 \.text
+0+33 secrel32 \.text
+0+44 secrel32 \.data
+0+49 secrel32 \.data
+0+4e secrel32 \.data
+0+53 secrel32 \.data
+0+64 secrel32 \.rdata
+0+69 secrel32 \.rdata
+0+6e secrel32 \.rdata
+0+73 secrel32 \.rdata
+0+84 secrel32 ext24
+0+89 secrel32 ext2d
+0+8e secrel32 ext36
+0+93 secrel32 ext3f
Contents of section \.text:
diff --git a/gas/testsuite/gas/i386/simd-intel.d b/gas/testsuite/gas/i386/simd-intel.d new file mode 100644 index 000000000000..7f4cc102b5c4 --- /dev/null +++ b/gas/testsuite/gas/i386/simd-intel.d @@ -0,0 +1,37 @@ +#source: simd.s +#as: -J +#objdump: -dw -Mintel +#name: i386 SIMD (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: f2 0f d0 0d 78 56 34 12 addsubps xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 66 0f 2f 0d 78 56 34 12 comisd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 2f 0d 78 56 34 12 comiss xmm1,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f e6 0d 78 56 34 12 cvtdq2pd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f2 0f e6 0d 78 56 34 12 cvtpd2dq xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 5a 0d 78 56 34 12 cvtps2pd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f 7f 0d 78 56 34 12 movdqu XMMWORD PTR ds:0x12345678,xmm1 +[ ]*[a-f0-9]+: f3 0f 6f 0d 78 56 34 12 movdqu xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 66 0f 17 0d 78 56 34 12 movhpd QWORD PTR ds:0x12345678,xmm1 +[ ]*[a-f0-9]+: 66 0f 16 0d 78 56 34 12 movhpd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 17 0d 78 56 34 12 movhps QWORD PTR ds:0x12345678,xmm1 +[ ]*[a-f0-9]+: 0f 16 0d 78 56 34 12 movhps xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 66 0f 13 0d 78 56 34 12 movlpd QWORD PTR ds:0x12345678,xmm1 +[ ]*[a-f0-9]+: 66 0f 12 0d 78 56 34 12 movlpd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps QWORD PTR ds:0x12345678,xmm1 +[ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f 16 0d 78 56 34 12 movshdup xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f 12 0d 78 56 34 12 movsldup xmm1,XMMWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: f3 0f 70 0d 78 56 34 12 90 pshufhw xmm1,XMMWORD PTR ds:0x12345678,0x90 +[ ]*[a-f0-9]+: f2 0f 70 0d 78 56 34 12 90 pshuflw xmm1,XMMWORD PTR ds:0x12345678,0x90 +[ ]*[a-f0-9]+: 0f 60 0d 78 56 34 12 punpcklbw mm1,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 62 0d 78 56 34 12 punpckldq mm1,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 61 0d 78 56 34 12 punpcklwd mm1,DWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 66 0f 2e 0d 78 56 34 12 ucomisd xmm1,QWORD PTR ds:0x12345678 +[ ]*[a-f0-9]+: 0f 2e 0d 78 56 34 12 ucomiss xmm1,DWORD PTR ds:0x12345678 diff --git a/gas/testsuite/gas/i386/simd.d b/gas/testsuite/gas/i386/simd.d new file mode 100644 index 000000000000..38a296af15d2 --- /dev/null +++ b/gas/testsuite/gas/i386/simd.d @@ -0,0 +1,36 @@ +#as: -J +#objdump: -dw +#name: i386 SIMD + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: f2 0f d0 0d 78 56 34 12 addsubps 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 66 0f 2f 0d 78 56 34 12 comisd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 2f 0d 78 56 34 12 comiss 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f e6 0d 78 56 34 12 cvtdq2pd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f2 0f e6 0d 78 56 34 12 cvtpd2dq 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 5a 0d 78 56 34 12 cvtps2pd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f 7f 0d 78 56 34 12 movdqu %xmm1,0x12345678 +[ ]*[a-f0-9]+: f3 0f 6f 0d 78 56 34 12 movdqu 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 66 0f 17 0d 78 56 34 12 movhpd %xmm1,0x12345678 +[ ]*[a-f0-9]+: 66 0f 16 0d 78 56 34 12 movhpd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 17 0d 78 56 34 12 movhps %xmm1,0x12345678 +[ ]*[a-f0-9]+: 0f 16 0d 78 56 34 12 movhps 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 66 0f 13 0d 78 56 34 12 movlpd %xmm1,0x12345678 +[ ]*[a-f0-9]+: 66 0f 12 0d 78 56 34 12 movlpd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678 +[ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f 16 0d 78 56 34 12 movshdup 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f 12 0d 78 56 34 12 movsldup 0x12345678,%xmm1 +[ ]*[a-f0-9]+: f3 0f 70 0d 78 56 34 12 90 pshufhw \$0x90,0x12345678,%xmm1 +[ ]*[a-f0-9]+: f2 0f 70 0d 78 56 34 12 90 pshuflw \$0x90,0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 60 0d 78 56 34 12 punpcklbw 0x12345678,%mm1 +[ ]*[a-f0-9]+: 0f 62 0d 78 56 34 12 punpckldq 0x12345678,%mm1 +[ ]*[a-f0-9]+: 0f 61 0d 78 56 34 12 punpcklwd 0x12345678,%mm1 +[ ]*[a-f0-9]+: 66 0f 2e 0d 78 56 34 12 ucomisd 0x12345678,%xmm1 +[ ]*[a-f0-9]+: 0f 2e 0d 78 56 34 12 ucomiss 0x12345678,%xmm1 diff --git a/gas/testsuite/gas/i386/simd.s b/gas/testsuite/gas/i386/simd.s new file mode 100644 index 000000000000..cd0cf93cb266 --- /dev/null +++ b/gas/testsuite/gas/i386/simd.s @@ -0,0 +1,29 @@ + .text +_start: + addsubps 0x12345678,%xmm1 + comisd 0x12345678,%xmm1 + comiss 0x12345678,%xmm1 + cvtdq2pd 0x12345678,%xmm1 + cvtpd2dq 0x12345678,%xmm1 + cvtps2pd 0x12345678,%xmm1 + cvttps2dq 0x12345678,%xmm1 + haddps 0x12345678,%xmm1 + movdqu %xmm1,0x12345678 + movdqu 0x12345678,%xmm1 + movhpd %xmm1,0x12345678 + movhpd 0x12345678,%xmm1 + movhps %xmm1,0x12345678 + movhps 0x12345678,%xmm1 + movlpd %xmm1,0x12345678 + movlpd 0x12345678,%xmm1 + movlps %xmm1,0x12345678 + movlps 0x12345678,%xmm1 + movshdup 0x12345678,%xmm1 + movsldup 0x12345678,%xmm1 + pshufhw $0x90,0x12345678,%xmm1 + pshuflw $0x90,0x12345678,%xmm1 + punpcklbw 0x12345678,%mm1 + punpckldq 0x12345678,%mm1 + punpcklwd 0x12345678,%mm1 + ucomisd 0x12345678,%xmm1 + ucomiss 0x12345678,%xmm1 diff --git a/gas/testsuite/gas/i386/sse2.d b/gas/testsuite/gas/i386/sse2.d index eb6a161cbf98..8b067f568d7e 100644 --- a/gas/testsuite/gas/i386/sse2.d +++ b/gas/testsuite/gas/i386/sse2.d @@ -61,16 +61,16 @@ Disassembly of section .text: [ ]+f5: f2 0f c2 f8 07[ ]+cmpordsd %xmm0,%xmm7 [ ]+fa: 66 0f 2f c1[ ]+comisd %xmm1,%xmm0 [ ]+fe: 66 0f 2f 0a[ ]+comisd \(%edx\),%xmm1 - 102: 66 0f 2a d3[ ]+cvtpi2pd %xmm3,%xmm2 + 102: 66 0f 2a d3[ ]+cvtpi2pd %mm3,%xmm2 106: 66 0f 2a 1c 24[ ]+cvtpi2pd \(%esp\),%xmm3 10b: f2 0f 2a e5[ ]+cvtsi2sd %ebp,%xmm4 10f: f2 0f 2a 2e[ ]+cvtsi2sd \(%esi\),%xmm5 - 113: 66 0f 2d f7[ ]+cvtpd2pi %xmm7,%xmm6 - 117: 66 0f 2d 38[ ]+cvtpd2pi \(%eax\),%xmm7 + 113: 66 0f 2d f7[ ]+cvtpd2pi %xmm7,%mm6 + 117: 66 0f 2d 38[ ]+cvtpd2pi \(%eax\),%mm7 11b: f2 0f 2d 01[ ]+cvtsd2si \(%ecx\),%eax 11f: f2 0f 2d ca[ ]+cvtsd2si %xmm2,%ecx - 123: 66 0f 2c 13[ ]+cvttpd2pi \(%ebx\),%xmm2 - 127: 66 0f 2c dc[ ]+cvttpd2pi %xmm4,%xmm3 + 123: 66 0f 2c 13[ ]+cvttpd2pi \(%ebx\),%mm2 + 127: 66 0f 2c dc[ ]+cvttpd2pi %xmm4,%mm3 12b: f2 0f 2c 65 00[ ]+cvttsd2si 0x0\(%ebp\),%esp 130: f2 0f 2c ee[ ]+cvttsd2si %xmm6,%ebp 134: 66 0f 5e c1[ ]+divpd[ ]+%xmm1,%xmm0 @@ -140,9 +140,9 @@ Disassembly of section .text: 239: f3 0f 5b c8[ ]+cvttps2dq %xmm0,%xmm1 23d: 66 0f f7 c8[ ]+maskmovdqu %xmm0,%xmm1 241: 66 0f 6f c8[ ]+movdqa %xmm0,%xmm1 - 245: 66 0f 6f c8[ ]+movdqa %xmm0,%xmm1 + 245: 66 0f 7f 06[ ]+movdqa %xmm0,\(%esi\) 249: f3 0f 6f c8[ ]+movdqu %xmm0,%xmm1 - 24d: f3 0f 6f c8[ ]+movdqu %xmm0,%xmm1 + 24d: f3 0f 7f 06[ ]+movdqu %xmm0,\(%esi\) 251: f2 0f d6 c8[ ]+movdq2q %xmm0,%mm1 255: f3 0f d6 c8[ ]+movq2dq %mm0,%xmm1 259: 66 0f f4 c8[ ]+pmuludq %xmm0,%xmm1 @@ -153,4 +153,4 @@ Disassembly of section .text: 270: 66 0f 73 f8 01[ ]+pslldq \$0x1,%xmm0 275: 66 0f 73 d8 01[ ]+psrldq \$0x1,%xmm0 27a: 66 0f 6d c8[ ]+punpckhqdq %xmm0,%xmm1 - 27e: 89 f6[ ]+mov[ ]+%esi,%esi + 27e: 66 90[ ]+xchg[ ]+%ax,%ax diff --git a/gas/testsuite/gas/i386/sse2.s b/gas/testsuite/gas/i386/sse2.s index ba5ae8d7b474..edb79fcba353 100644 --- a/gas/testsuite/gas/i386/sse2.s +++ b/gas/testsuite/gas/i386/sse2.s @@ -132,9 +132,9 @@ foo: cvttps2dq %xmm0, %xmm1 maskmovdqu %xmm0, %xmm1 movdqa %xmm0, %xmm1 - movdqa %xmm0, %xmm1 - movdqu %xmm0, %xmm1 + movdqa %xmm0, (%esi) movdqu %xmm0, %xmm1 + movdqu %xmm0, (%esi) movdq2q %xmm0, %mm1 movq2dq %mm0, %xmm1 pmuludq %xmm0, %xmm1 diff --git a/gas/testsuite/gas/i386/sse4_1.d b/gas/testsuite/gas/i386/sse4_1.d new file mode 100644 index 000000000000..6797228a5299 --- /dev/null +++ b/gas/testsuite/gas/i386/sse4_1.d @@ -0,0 +1,102 @@ +#objdump: -dw +#name: i386 SSE4.1 + +.*: file format .* + +Disassembly of section .text: + +0+000 <foo>: +[ ]*[0-9a-f]+: 66 0f 3a 0d 01 00 blendpd \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0d c1 00 blendpd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0c 01 00 blendps \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0c c1 00 blendps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd %xmm0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps %xmm0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 41 01 00 dppd \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 41 c1 00 dppd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 40 01 00 dpps \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 40 c1 00 dpps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 17 c1 00 extractps \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 17 01 00 extractps \$0x0,%xmm0,\(%ecx\) +[ ]*[0-9a-f]+: 66 0f 3a 21 c1 00 insertps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 21 01 00 insertps \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2a 01 movntdqa \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 42 01 00 mpsadbw \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 42 c1 00 mpsadbw \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2b 01 packusdw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2b c1 packusdw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb %xmm0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0e 01 00 pblendw \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0e c1 00 pblendw \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 29 c1 pcmpeqq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 29 01 pcmpeqq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 14 c1 00 pextrb \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 14 01 00 pextrb \$0x0,%xmm0,\(%ecx\) +[ ]*[0-9a-f]+: 66 0f 3a 16 c1 00 pextrd \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 16 01 00 pextrd \$0x0,%xmm0,\(%ecx\) +[ ]*[0-9a-f]+: 66 0f c5 c8 00 pextrw \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 15 01 00 pextrw \$0x0,%xmm0,\(%ecx\) +[ ]*[0-9a-f]+: 66 0f 38 41 c1 phminposuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 41 01 phminposuw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 20 01 00 pinsrb \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 20 c1 00 pinsrb \$0x0,%ecx,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 22 01 00 pinsrd \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 22 c1 00 pinsrd \$0x0,%ecx,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3c c1 pmaxsb %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3c 01 pmaxsb \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3d c1 pmaxsd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3d 01 pmaxsd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3f c1 pmaxud %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3f 01 pmaxud \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3e c1 pmaxuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3e 01 pmaxuw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 38 c1 pminsb %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 38 01 pminsb \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 39 c1 pminsd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 39 01 pminsd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3b c1 pminud %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3b 01 pminud \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3a c1 pminuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3a 01 pminuw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 20 c1 pmovsxbw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 20 01 pmovsxbw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 21 c1 pmovsxbd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 21 01 pmovsxbd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 22 c1 pmovsxbq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 22 01 pmovsxbq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 23 c1 pmovsxwd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 23 01 pmovsxwd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 24 c1 pmovsxwq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 24 01 pmovsxwq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 25 c1 pmovsxdq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 25 01 pmovsxdq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 30 c1 pmovzxbw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 30 01 pmovzxbw \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 31 c1 pmovzxbd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 31 01 pmovzxbd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 32 c1 pmovzxbq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 32 01 pmovzxbq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 33 c1 pmovzxwd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 33 01 pmovzxwd \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 34 c1 pmovzxwq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 34 01 pmovzxwq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 35 c1 pmovzxdq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 35 01 pmovzxdq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 28 c1 pmuldq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 28 01 pmuldq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 40 c1 pmulld %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 40 01 pmulld \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 17 c1 ptest %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 17 01 ptest \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 09 01 00 roundpd \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 09 c1 00 roundpd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 08 01 00 roundps \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 08 c1 00 roundps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0b 01 00 roundsd \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0b c1 00 roundsd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0a 01 00 roundss \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0a c1 00 roundss \$0x0,%xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/sse4_1.s b/gas/testsuite/gas/i386/sse4_1.s new file mode 100644 index 000000000000..258dde8a4b9e --- /dev/null +++ b/gas/testsuite/gas/i386/sse4_1.s @@ -0,0 +1,99 @@ +# Streaming SIMD extensions 4.1 Instructions + + .text +foo: + blendpd $0,(%ecx),%xmm0 + blendpd $0,%xmm1,%xmm0 + blendps $0,(%ecx),%xmm0 + blendps $0,%xmm1,%xmm0 + blendvpd %xmm0,(%ecx),%xmm0 + blendvpd %xmm0,%xmm1,%xmm0 + blendvps %xmm0,(%ecx),%xmm0 + blendvps %xmm0,%xmm1,%xmm0 + dppd $0,(%ecx),%xmm0 + dppd $0,%xmm1,%xmm0 + dpps $0,(%ecx),%xmm0 + dpps $0,%xmm1,%xmm0 + extractps $0,%xmm0,%ecx + extractps $0,%xmm0,(%ecx) + insertps $0,%xmm1,%xmm0 + insertps $0,(%ecx),%xmm0 + movntdqa (%ecx),%xmm0 + mpsadbw $0,(%ecx),%xmm0 + mpsadbw $0,%xmm1,%xmm0 + packusdw (%ecx),%xmm0 + packusdw %xmm1,%xmm0 + pblendvb %xmm0,(%ecx),%xmm0 + pblendvb %xmm0,%xmm1,%xmm0 + pblendw $0,(%ecx),%xmm0 + pblendw $0,%xmm1,%xmm0 + pcmpeqq %xmm1,%xmm0 + pcmpeqq (%ecx),%xmm0 + pextrb $0,%xmm0,%ecx + pextrb $0,%xmm0,(%ecx) + pextrd $0,%xmm0,%ecx + pextrd $0,%xmm0,(%ecx) + pextrw $0,%xmm0,%ecx + pextrw $0,%xmm0,(%ecx) + phminposuw %xmm1,%xmm0 + phminposuw (%ecx),%xmm0 + pinsrb $0,(%ecx),%xmm0 + pinsrb $0,%ecx,%xmm0 + pinsrd $0,(%ecx),%xmm0 + pinsrd $0,%ecx,%xmm0 + pmaxsb %xmm1,%xmm0 + pmaxsb (%ecx),%xmm0 + pmaxsd %xmm1,%xmm0 + pmaxsd (%ecx),%xmm0 + pmaxud %xmm1,%xmm0 + pmaxud (%ecx),%xmm0 + pmaxuw %xmm1,%xmm0 + pmaxuw (%ecx),%xmm0 + pminsb %xmm1,%xmm0 + pminsb (%ecx),%xmm0 + pminsd %xmm1,%xmm0 + pminsd (%ecx),%xmm0 + pminud %xmm1,%xmm0 + pminud (%ecx),%xmm0 + pminuw %xmm1,%xmm0 + pminuw (%ecx),%xmm0 + pmovsxbw %xmm1,%xmm0 + pmovsxbw (%ecx),%xmm0 + pmovsxbd %xmm1,%xmm0 + pmovsxbd (%ecx),%xmm0 + pmovsxbq %xmm1,%xmm0 + pmovsxbq (%ecx),%xmm0 + pmovsxwd %xmm1,%xmm0 + pmovsxwd (%ecx),%xmm0 + pmovsxwq %xmm1,%xmm0 + pmovsxwq (%ecx),%xmm0 + pmovsxdq %xmm1,%xmm0 + pmovsxdq (%ecx),%xmm0 + pmovzxbw %xmm1,%xmm0 + pmovzxbw (%ecx),%xmm0 + pmovzxbd %xmm1,%xmm0 + pmovzxbd (%ecx),%xmm0 + pmovzxbq %xmm1,%xmm0 + pmovzxbq (%ecx),%xmm0 + pmovzxwd %xmm1,%xmm0 + pmovzxwd (%ecx),%xmm0 + pmovzxwq %xmm1,%xmm0 + pmovzxwq (%ecx),%xmm0 + pmovzxdq %xmm1,%xmm0 + pmovzxdq (%ecx),%xmm0 + pmuldq %xmm1,%xmm0 + pmuldq (%ecx),%xmm0 + pmulld %xmm1,%xmm0 + pmulld (%ecx),%xmm0 + ptest %xmm1,%xmm0 + ptest (%ecx),%xmm0 + roundpd $0,(%ecx),%xmm0 + roundpd $0,%xmm1,%xmm0 + roundps $0,(%ecx),%xmm0 + roundps $0,%xmm1,%xmm0 + roundsd $0,(%ecx),%xmm0 + roundsd $0,%xmm1,%xmm0 + roundss $0,(%ecx),%xmm0 + roundss $0,%xmm1,%xmm0 + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/sse4_2.d b/gas/testsuite/gas/i386/sse4_2.d new file mode 100644 index 000000000000..b889769ac4c7 --- /dev/null +++ b/gas/testsuite/gas/i386/sse4_2.d @@ -0,0 +1,36 @@ +#objdump: -dw +#name: i386 SSE4.2 + +.*: file format .* + +Disassembly of section .text: + +0+000 <foo>: +[ ]*[0-9a-f]+: f2 0f 38 f0 d9 crc32b %cl,%ebx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 d9 crc32w %cx,%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[0-9a-f]+: f2 0f 38 f0 19 crc32b \(%ecx\),%ebx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 19 crc32w \(%ecx\),%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 19 crc32l \(%ecx\),%ebx +[ ]*[0-9a-f]+: f2 0f 38 f0 d9 crc32b %cl,%ebx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 d9 crc32w %cx,%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[0-9a-f]+: 66 0f 38 37 01 pcmpgtq \(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 37 c1 pcmpgtq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 61 01 00 pcmpestri \$0x0,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 61 c1 00 pcmpestri \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 60 01 01 pcmpestrm \$0x1,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 60 c1 01 pcmpestrm \$0x1,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 63 01 02 pcmpistri \$0x2,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 63 c1 02 pcmpistri \$0x2,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 62 01 03 pcmpistrm \$0x3,\(%ecx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 62 c1 03 pcmpistrm \$0x3,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 f3 0f b8 19 popcnt \(%ecx\),%bx +[ ]*[0-9a-f]+: f3 0f b8 19 popcnt \(%ecx\),%ebx +[ ]*[0-9a-f]+: 66 f3 0f b8 19 popcnt \(%ecx\),%bx +[ ]*[0-9a-f]+: f3 0f b8 19 popcnt \(%ecx\),%ebx +[ ]*[0-9a-f]+: 66 f3 0f b8 d9 popcnt %cx,%bx +[ ]*[0-9a-f]+: f3 0f b8 d9 popcnt %ecx,%ebx +[ ]*[0-9a-f]+: 66 f3 0f b8 d9 popcnt %cx,%bx +[ ]*[0-9a-f]+: f3 0f b8 d9 popcnt %ecx,%ebx +#pass diff --git a/gas/testsuite/gas/i386/sse4_2.s b/gas/testsuite/gas/i386/sse4_2.s new file mode 100644 index 000000000000..a6c2e4610ee1 --- /dev/null +++ b/gas/testsuite/gas/i386/sse4_2.s @@ -0,0 +1,33 @@ +# Streaming SIMD extensions 4.2 Instructions + + .text +foo: + crc32 %cl,%ebx + crc32 %cx,%ebx + crc32 %ecx,%ebx + crc32b (%ecx),%ebx + crc32w (%ecx),%ebx + crc32l (%ecx),%ebx + crc32b %cl,%ebx + crc32w %cx,%ebx + crc32l %ecx,%ebx + pcmpgtq (%ecx),%xmm0 + pcmpgtq %xmm1,%xmm0 + pcmpestri $0x0,(%ecx),%xmm0 + pcmpestri $0x0,%xmm1,%xmm0 + pcmpestrm $0x1,(%ecx),%xmm0 + pcmpestrm $0x1,%xmm1,%xmm0 + pcmpistri $0x2,(%ecx),%xmm0 + pcmpistri $0x2,%xmm1,%xmm0 + pcmpistrm $0x3,(%ecx),%xmm0 + pcmpistrm $0x3,%xmm1,%xmm0 + popcnt (%ecx),%bx + popcnt (%ecx),%ebx + popcntw (%ecx),%bx + popcntl (%ecx),%ebx + popcnt %cx,%bx + popcnt %ecx,%ebx + popcntw %cx,%bx + popcntl %ecx,%ebx + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/ssemmx2.d b/gas/testsuite/gas/i386/ssemmx2.d index 04ccbafe457b..f25bc5f80b65 100644 --- a/gas/testsuite/gas/i386/ssemmx2.d +++ b/gas/testsuite/gas/i386/ssemmx2.d @@ -34,55 +34,55 @@ Disassembly of section .text: [ ]+6b: f2 0f 70 da 01[ ]+pshuflw \$0x1,%xmm2,%xmm3 [ ]+70: f2 0f 70 75 00 04[ ]+pshuflw \$0x4,0x0\(%ebp\),%xmm6 [ ]+76: 66 0f e7 10[ ]+movntdq %xmm2,\(%eax\) -[ ]+7a: 66 0f 60 90 90 90 90 90 punpcklbw 0x90909090\(%eax\),%xmm2 -[ ]+82: 66 0f 61 90 90 90 90 90 punpcklwd 0x90909090\(%eax\),%xmm2 -[ ]+8a: 66 0f 62 90 90 90 90 90 punpckldq 0x90909090\(%eax\),%xmm2 -[ ]+92: 66 0f 63 90 90 90 90 90 packsswb 0x90909090\(%eax\),%xmm2 -[ ]+9a: 66 0f 64 90 90 90 90 90 pcmpgtb 0x90909090\(%eax\),%xmm2 -[ ]+a2: 66 0f 65 90 90 90 90 90 pcmpgtw 0x90909090\(%eax\),%xmm2 -[ ]+aa: 66 0f 66 90 90 90 90 90 pcmpgtd 0x90909090\(%eax\),%xmm2 -[ ]+b2: 66 0f 67 90 90 90 90 90 packuswb 0x90909090\(%eax\),%xmm2 -[ ]+ba: 66 0f 68 90 90 90 90 90 punpckhbw 0x90909090\(%eax\),%xmm2 -[ ]+c2: 66 0f 69 90 90 90 90 90 punpckhwd 0x90909090\(%eax\),%xmm2 -[ ]+ca: 66 0f 6a 90 90 90 90 90 punpckhdq 0x90909090\(%eax\),%xmm2 -[ ]+d2: 66 0f 6b 90 90 90 90 90 packssdw 0x90909090\(%eax\),%xmm2 -[ ]+da: 66 0f 6e 90 90 90 90 90 movd[ ]+0x90909090\(%eax\),%xmm2 -[ ]+e2: f3 0f 7e 90 90 90 90 90 movq[ ]+0x90909090\(%eax\),%xmm2 +[ ]+7a: 66 0f 60 90 90 90 90 90 punpcklbw -0x6f6f6f70\(%eax\),%xmm2 +[ ]+82: 66 0f 61 90 90 90 90 90 punpcklwd -0x6f6f6f70\(%eax\),%xmm2 +[ ]+8a: 66 0f 62 90 90 90 90 90 punpckldq -0x6f6f6f70\(%eax\),%xmm2 +[ ]+92: 66 0f 63 90 90 90 90 90 packsswb -0x6f6f6f70\(%eax\),%xmm2 +[ ]+9a: 66 0f 64 90 90 90 90 90 pcmpgtb -0x6f6f6f70\(%eax\),%xmm2 +[ ]+a2: 66 0f 65 90 90 90 90 90 pcmpgtw -0x6f6f6f70\(%eax\),%xmm2 +[ ]+aa: 66 0f 66 90 90 90 90 90 pcmpgtd -0x6f6f6f70\(%eax\),%xmm2 +[ ]+b2: 66 0f 67 90 90 90 90 90 packuswb -0x6f6f6f70\(%eax\),%xmm2 +[ ]+ba: 66 0f 68 90 90 90 90 90 punpckhbw -0x6f6f6f70\(%eax\),%xmm2 +[ ]+c2: 66 0f 69 90 90 90 90 90 punpckhwd -0x6f6f6f70\(%eax\),%xmm2 +[ ]+ca: 66 0f 6a 90 90 90 90 90 punpckhdq -0x6f6f6f70\(%eax\),%xmm2 +[ ]+d2: 66 0f 6b 90 90 90 90 90 packssdw -0x6f6f6f70\(%eax\),%xmm2 +[ ]+da: 66 0f 6e 90 90 90 90 90 movd[ ]+-0x6f6f6f70\(%eax\),%xmm2 +[ ]+e2: f3 0f 7e 90 90 90 90 90 movq[ ]+-0x6f6f6f70\(%eax\),%xmm2 [ ]+ea: 66 0f 71 d0 90[ ]+psrlw[ ]+\$0x90,%xmm0 [ ]+ef: 66 0f 72 d0 90[ ]+psrld[ ]+\$0x90,%xmm0 [ ]+f4: 66 0f 73 d0 90[ ]+psrlq[ ]+\$0x90,%xmm0 -[ ]+f9: 66 0f 74 90 90 90 90 90 pcmpeqb 0x90909090\(%eax\),%xmm2 - 101: 66 0f 75 90 90 90 90 90 pcmpeqw 0x90909090\(%eax\),%xmm2 - 109: 66 0f 76 90 90 90 90 90 pcmpeqd 0x90909090\(%eax\),%xmm2 - 111: 66 0f 7e 90 90 90 90 90 movd[ ]+%xmm2,0x90909090\(%eax\) - 119: 66 0f d6 90 90 90 90 90 movq[ ]+%xmm2,0x90909090\(%eax\) - 121: 66 0f d1 90 90 90 90 90 psrlw[ ]+0x90909090\(%eax\),%xmm2 - 129: 66 0f d2 90 90 90 90 90 psrld[ ]+0x90909090\(%eax\),%xmm2 - 131: 66 0f d3 90 90 90 90 90 psrlq[ ]+0x90909090\(%eax\),%xmm2 - 139: 66 0f d5 90 90 90 90 90 pmullw 0x90909090\(%eax\),%xmm2 - 141: 66 0f d8 90 90 90 90 90 psubusb 0x90909090\(%eax\),%xmm2 - 149: 66 0f d9 90 90 90 90 90 psubusw 0x90909090\(%eax\),%xmm2 - 151: 66 0f db 90 90 90 90 90 pand[ ]+0x90909090\(%eax\),%xmm2 - 159: 66 0f dc 90 90 90 90 90 paddusb 0x90909090\(%eax\),%xmm2 - 161: 66 0f dd 90 90 90 90 90 paddusw 0x90909090\(%eax\),%xmm2 - 169: 66 0f df 90 90 90 90 90 pandn[ ]+0x90909090\(%eax\),%xmm2 - 171: 66 0f e1 90 90 90 90 90 psraw[ ]+0x90909090\(%eax\),%xmm2 - 179: 66 0f e2 90 90 90 90 90 psrad[ ]+0x90909090\(%eax\),%xmm2 - 181: 66 0f e5 90 90 90 90 90 pmulhw 0x90909090\(%eax\),%xmm2 - 189: 66 0f e8 90 90 90 90 90 psubsb 0x90909090\(%eax\),%xmm2 - 191: 66 0f e9 90 90 90 90 90 psubsw 0x90909090\(%eax\),%xmm2 - 199: 66 0f eb 90 90 90 90 90 por[ ]+0x90909090\(%eax\),%xmm2 - 1a1: 66 0f ec 90 90 90 90 90 paddsb 0x90909090\(%eax\),%xmm2 - 1a9: 66 0f ed 90 90 90 90 90 paddsw 0x90909090\(%eax\),%xmm2 - 1b1: 66 0f ef 90 90 90 90 90 pxor[ ]+0x90909090\(%eax\),%xmm2 - 1b9: 66 0f f1 90 90 90 90 90 psllw[ ]+0x90909090\(%eax\),%xmm2 - 1c1: 66 0f f2 90 90 90 90 90 pslld[ ]+0x90909090\(%eax\),%xmm2 - 1c9: 66 0f f3 90 90 90 90 90 psllq[ ]+0x90909090\(%eax\),%xmm2 - 1d1: 66 0f f5 90 90 90 90 90 pmaddwd 0x90909090\(%eax\),%xmm2 - 1d9: 66 0f f8 90 90 90 90 90 psubb[ ]+0x90909090\(%eax\),%xmm2 - 1e1: 66 0f f9 90 90 90 90 90 psubw[ ]+0x90909090\(%eax\),%xmm2 - 1e9: 66 0f fa 90 90 90 90 90 psubd[ ]+0x90909090\(%eax\),%xmm2 - 1f1: 66 0f fc 90 90 90 90 90 paddb[ ]+0x90909090\(%eax\),%xmm2 - 1f9: 66 0f fd 90 90 90 90 90 paddw[ ]+0x90909090\(%eax\),%xmm2 - 201: 66 0f fe 90 90 90 90 90 paddd[ ]+0x90909090\(%eax\),%xmm2 +[ ]+f9: 66 0f 74 90 90 90 90 90 pcmpeqb -0x6f6f6f70\(%eax\),%xmm2 + 101: 66 0f 75 90 90 90 90 90 pcmpeqw -0x6f6f6f70\(%eax\),%xmm2 + 109: 66 0f 76 90 90 90 90 90 pcmpeqd -0x6f6f6f70\(%eax\),%xmm2 + 111: 66 0f 7e 90 90 90 90 90 movd[ ]+%xmm2,-0x6f6f6f70\(%eax\) + 119: 66 0f d6 90 90 90 90 90 movq[ ]+%xmm2,-0x6f6f6f70\(%eax\) + 121: 66 0f d1 90 90 90 90 90 psrlw[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 129: 66 0f d2 90 90 90 90 90 psrld[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 131: 66 0f d3 90 90 90 90 90 psrlq[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 139: 66 0f d5 90 90 90 90 90 pmullw -0x6f6f6f70\(%eax\),%xmm2 + 141: 66 0f d8 90 90 90 90 90 psubusb -0x6f6f6f70\(%eax\),%xmm2 + 149: 66 0f d9 90 90 90 90 90 psubusw -0x6f6f6f70\(%eax\),%xmm2 + 151: 66 0f db 90 90 90 90 90 pand[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 159: 66 0f dc 90 90 90 90 90 paddusb -0x6f6f6f70\(%eax\),%xmm2 + 161: 66 0f dd 90 90 90 90 90 paddusw -0x6f6f6f70\(%eax\),%xmm2 + 169: 66 0f df 90 90 90 90 90 pandn[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 171: 66 0f e1 90 90 90 90 90 psraw[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 179: 66 0f e2 90 90 90 90 90 psrad[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 181: 66 0f e5 90 90 90 90 90 pmulhw -0x6f6f6f70\(%eax\),%xmm2 + 189: 66 0f e8 90 90 90 90 90 psubsb -0x6f6f6f70\(%eax\),%xmm2 + 191: 66 0f e9 90 90 90 90 90 psubsw -0x6f6f6f70\(%eax\),%xmm2 + 199: 66 0f eb 90 90 90 90 90 por[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1a1: 66 0f ec 90 90 90 90 90 paddsb -0x6f6f6f70\(%eax\),%xmm2 + 1a9: 66 0f ed 90 90 90 90 90 paddsw -0x6f6f6f70\(%eax\),%xmm2 + 1b1: 66 0f ef 90 90 90 90 90 pxor[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1b9: 66 0f f1 90 90 90 90 90 psllw[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1c1: 66 0f f2 90 90 90 90 90 pslld[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1c9: 66 0f f3 90 90 90 90 90 psllq[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1d1: 66 0f f5 90 90 90 90 90 pmaddwd -0x6f6f6f70\(%eax\),%xmm2 + 1d9: 66 0f f8 90 90 90 90 90 psubb[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1e1: 66 0f f9 90 90 90 90 90 psubw[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1e9: 66 0f fa 90 90 90 90 90 psubd[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1f1: 66 0f fc 90 90 90 90 90 paddb[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 1f9: 66 0f fd 90 90 90 90 90 paddw[ ]+-0x6f6f6f70\(%eax\),%xmm2 + 201: 66 0f fe 90 90 90 90 90 paddd[ ]+-0x6f6f6f70\(%eax\),%xmm2 209: 8d b4 26 00 00 00 00 lea[ ]+0x0\(%esi\),%esi diff --git a/gas/testsuite/gas/i386/tlsd.d b/gas/testsuite/gas/i386/tlsd.d index bbf6fd49cfa9..620a0d944081 100644 --- a/gas/testsuite/gas/i386/tlsd.d +++ b/gas/testsuite/gas/i386/tlsd.d @@ -28,6 +28,6 @@ Disassembly of section .text: 31: 83 c6 00 [ ]*add \$0x0,%esi 34: 8d 88 00 00 00 00 [ ]*lea 0x0\(%eax\),%ecx [ ]+36: R_386_TLS_LDO_32 baz - 3a: 8b 5d fc [ ]*mov 0xfffffffc\(%ebp\),%ebx + 3a: 8b 5d fc [ ]*mov -0x4\(%ebp\),%ebx 3d: c9 [ ]*leave[ ]* 3e: c3 [ ]*ret[ ]* diff --git a/gas/testsuite/gas/i386/tlspic.d b/gas/testsuite/gas/i386/tlspic.d index bd5dbb7bace9..ccb292c3e685 100644 --- a/gas/testsuite/gas/i386/tlspic.d +++ b/gas/testsuite/gas/i386/tlspic.d @@ -25,6 +25,6 @@ Disassembly of section .text: 2c: 65 8b 0d 00 00 00 00 [ ]*mov %gs:0x0,%ecx 33: 03 8b 00 00 00 00 [ ]*add 0x0\(%ebx\),%ecx [ ]+35: R_386_TLS_GOTIE foo - 39: 8b 5d fc [ ]*mov 0xfffffffc\(%ebp\),%ebx + 39: 8b 5d fc [ ]*mov -0x4\(%ebp\),%ebx 3c: c9 [ ]*leave[ ]* 3d: c3 [ ]*ret[ ]* diff --git a/gas/testsuite/gas/i386/white.l b/gas/testsuite/gas/i386/white.l index c2d9157a2248..876c9d525f42 100644 --- a/gas/testsuite/gas/i386/white.l +++ b/gas/testsuite/gas/i386/white.l @@ -8,7 +8,7 @@ GAS LISTING .* 5 0003 C705D711 00007B00 0000 mOvl \$ 123 , 4567 6 000d 678A787B ADDr16 mov 123 \( % bx , % si , 1 \) , % bh 7 0011 FFE0 jmp \* % eax - 8 0013 6626FF23 foo: jmpw % es : \* \( % ebx \) + 8 0013 2666FF23 foo: jmpw % es : \* \( % ebx \) 9 10 0017 A0500000 00 mov \( 0x8 \* 0Xa \) , % al 11 001c B020 mov \$ \( 8 \* 4 \) , % al diff --git a/gas/testsuite/gas/i386/x86-64-addr32-intel.d b/gas/testsuite/gas/i386/x86-64-addr32-intel.d new file mode 100644 index 000000000000..90858dcc08fe --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-addr32-intel.d @@ -0,0 +1,23 @@ +#as: -J +#objdump: -drwMintel +#name: x86-64 32-bit addressing (Intel mode) +#source: x86-64-addr32.s + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+67 48 8d 80 00 00 00 00[ ]+addr32[ ]+lea[ ]+rax,\[[re]ax\+(0x)?0\].* +[ ]*8:[ ]+67 49 8d 80 00 00 00 00[ ]+addr32[ ]+lea[ ]+rax,\[r8d?\+(0x)?0\].* +[ ]*10:[ ]+67 48 8d 05 00 00 00 00[ ]+addr32[ ]+lea[ ]+rax,\[[re]ip\+(0x)?0\].* +[ ]*18:[ ]+67 48 8d 04 25 00 00 00 00[ ]+addr32[ ]+lea[ ]+rax,ds:0x0.* +[ ]*21:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+al,ds:0x600898 +[ ]*27:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+ax,ds:0x600898 +[ ]*2e:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+eax,ds:0x600898 +[ ]*34:[ ]+67 48 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+rax,ds:0x600898 +[ ]*3b:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+ds:0x600898,al +[ ]*41:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+ds:0x600898,ax +[ ]*48:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+ds:0x600898,eax +[ ]*4e:[ ]+67 48 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+ds:0x600898,rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-addr32.d b/gas/testsuite/gas/i386/x86-64-addr32.d index c892fb1ba1d5..c08f382553ba 100644 --- a/gas/testsuite/gas/i386/x86-64-addr32.d +++ b/gas/testsuite/gas/i386/x86-64-addr32.d @@ -2,12 +2,21 @@ #objdump: -drw #name: x86-64 32-bit addressing -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: 0+000 <.text>: [ ]*0:[ ]+67 48 8d 80 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0\(%[re]ax\),%rax.* [ ]*8:[ ]+67 49 8d 80 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0\(%r8d?\),%rax.* -[ ]*10:[ ]+67 48 8d 05 00 00 00 00[ ]+addr32[ ]+lea[ ]+0\(%[re]ip\),%rax.* +[ ]*10:[ ]+67 48 8d 05 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0\(%[re]ip\),%rax.* [ ]*18:[ ]+67 48 8d 04 25 00 00 00 00[ ]+addr32[ ]+lea[ ]+0x0,%rax.* +[ ]*21:[ ]+67 a0 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%al +[ ]*27:[ ]+67 66 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%ax +[ ]*2e:[ ]+67 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%eax +[ ]*34:[ ]+67 48 a1 98 08 60 00[ ]+addr32[ ]+mov[ ]+0x600898,%rax +[ ]*3b:[ ]+67 a2 98 08 60 00[ ]+addr32[ ]+mov[ ]+%al,0x600898 +[ ]*41:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898 +[ ]*48:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898 +[ ]*4e:[ ]+67 48 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%rax,0x600898 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-addr32.s b/gas/testsuite/gas/i386/x86-64-addr32.s index d18cbb91bcfc..c32525ffa1fe 100644 --- a/gas/testsuite/gas/i386/x86-64-addr32.s +++ b/gas/testsuite/gas/i386/x86-64-addr32.s @@ -3,3 +3,11 @@ lea symbol(%r8d), %rax addr32 lea symbol(%rip), %rax addr32 lea symbol, %rax + addr32 mov 0x600898,%al + addr32 mov 0x600898,%ax + addr32 mov 0x600898,%eax + addr32 mov 0x600898,%rax + addr32 mov %al,0x600898 + addr32 mov %ax,0x600898 + addr32 mov %eax,0x600898 + addr32 mov %rax,0x600898 diff --git a/gas/testsuite/gas/i386/x86-64-amdfam10.d b/gas/testsuite/gas/i386/x86-64-amdfam10.d new file mode 100644 index 000000000000..ed142b1d95eb --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amdfam10.d @@ -0,0 +1,27 @@ +#objdump: -dw +#name: x86-64 amdfam10 + +.*: +file format .* + +Disassembly of section .text: + +0+000 <foo>: + 0: f3 48 0f bd 19[ ]+lzcnt \(%rcx\),%rbx + 5: f3 0f bd 19[ ]+lzcnt \(%rcx\),%ebx + 9: 66 f3 0f bd 19[ ]+lzcnt \(%rcx\),%bx + e: f3 48 0f bd d9[ ]+lzcnt %rcx,%rbx + 13: f3 0f bd d9[ ]+lzcnt %ecx,%ebx + 17: 66 f3 0f bd d9[ ]+lzcnt %cx,%bx + 1c: f3 48 0f b8 19[ ]+popcnt \(%rcx\),%rbx + 21: f3 0f b8 19[ ]+popcnt \(%rcx\),%ebx + 25: 66 f3 0f b8 19[ ]+popcnt \(%rcx\),%bx + 2a: f3 48 0f b8 d9[ ]+popcnt %rcx,%rbx + 2f: f3 0f b8 d9[ ]+popcnt %ecx,%ebx + 33: 66 f3 0f b8 d9[ ]+popcnt %cx,%bx + 38: 66 0f 79 ca[ ]+extrq %xmm2,%xmm1 + 3c: 66 0f 78 c1 02 04[ ]+extrq \$0x4,\$0x2,%xmm1 + 42: f2 0f 79 ca[ ]+insertq %xmm2,%xmm1 + 46: f2 0f 78 ca 02 04[ ]+insertq \$0x4,\$0x2,%xmm2,%xmm1 + 4c: f2 0f 2b 09[ ]+movntsd %xmm1,\(%rcx\) + 50: f3 0f 2b 09[ ]+movntss %xmm1,\(%rcx\) + ... diff --git a/gas/testsuite/gas/i386/x86-64-amdfam10.s b/gas/testsuite/gas/i386/x86-64-amdfam10.s new file mode 100644 index 000000000000..df0416443b09 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-amdfam10.s @@ -0,0 +1,25 @@ +#AMDFAM10 New Instructions + + .text +foo: + lzcnt (%rcx),%rbx + lzcnt (%rcx),%ebx + lzcnt (%rcx),%bx + lzcnt %rcx,%rbx + lzcnt %ecx,%ebx + lzcnt %cx,%bx + popcnt (%rcx),%rbx + popcnt (%rcx),%ebx + popcnt (%rcx),%bx + popcnt %rcx,%rbx + popcnt %ecx,%ebx + popcnt %cx,%bx + extrq %xmm2,%xmm1 + extrq $4,$2,%xmm1 + insertq %xmm2,%xmm1 + insertq $4,$2,%xmm2,%xmm1 + movntsd %xmm1,(%rcx) + movntss %xmm1,(%rcx) + + # Force a good alignment. + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d index 7ddd6fe17778..17c46a752b1c 100644 --- a/gas/testsuite/gas/i386/x86-64-branch.d +++ b/gas/testsuite/gas/i386/x86-64-branch.d @@ -2,7 +2,7 @@ #objdump: -drw #name: x86-64 indirect branch -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: @@ -11,3 +11,4 @@ Disassembly of section .text: [ ]*2:[ ]+ff d0[ ]+callq[ ]+\*%rax [ ]*4:[ ]+ff e0[ ]+jmpq[ ]+\*%rax [ ]*6:[ ]+ff e0[ ]+jmpq[ ]+\*%rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-cbw-intel.d b/gas/testsuite/gas/i386/x86-64-cbw-intel.d new file mode 100644 index 000000000000..616ffad9f259 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cbw-intel.d @@ -0,0 +1,26 @@ +#source: x86-64-cbw.s +#objdump: -dwMintel +#name: x86-64 CBW/CWD & Co (Intel disassembly) + +.*: +file format .* + +Disassembly of section .text: + +0+000 <_cbw>: + 0: 66 98 cbw + 2: 98 cwde + 3: 48 98 cdqe + 5: 66 40 98 rex cbw + 8: 40 98 rex cwde + a: 66 data16 + b: 48 98 cdqe + +0+00d <_cwd>: + d: 66 99 cwd + f: 99 cdq + 10: 48 99 cqo + 12: 66 40 99 rex cwd + 15: 40 99 rex cdq + 17: 66 data16 + 18: 48 99 cqo +#pass diff --git a/gas/testsuite/gas/i386/x86-64-cbw.d b/gas/testsuite/gas/i386/x86-64-cbw.d new file mode 100644 index 000000000000..5474ce2859ba --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cbw.d @@ -0,0 +1,25 @@ +#objdump: -dw +#name: x86-64 CBW/CWD & Co + +.*: +file format .* + +Disassembly of section .text: + +0+000 <_cbw>: + 0: 66 98 cbtw + 2: 98 cwtl + 3: 48 98 cltq + 5: 66 40 98 rex cbtw + 8: 40 98 rex cwtl + a: 66 data16 + b: 48 98 cltq + +0+00d <_cwd>: + d: 66 99 cwtd + f: 99 cltd + 10: 48 99 cqto + 12: 66 40 99 rex cwtd + 15: 40 99 rex cltd + 17: 66 data16 + 18: 48 99 cqto +#pass diff --git a/gas/testsuite/gas/i386/x86-64-cbw.s b/gas/testsuite/gas/i386/x86-64-cbw.s new file mode 100644 index 000000000000..085c2797348e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cbw.s @@ -0,0 +1,18 @@ + .intel_syntax noprefix + .text +_cbw: + cbw + cwde + cdqe + rex cbw + rex cwde + rex64 cbw +_cwd: + cwd + cdq + cqo + rex cwd + rex cdq + rex64 cwd + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-crc32-intel.d b/gas/testsuite/gas/i386/x86-64-crc32-intel.d new file mode 100644 index 000000000000..24bd66dd001e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32-intel.d @@ -0,0 +1,35 @@ +#objdump: -drwMintel +#name: x86-64 crc32 (Intel mode) +#source: x86-64-crc32.s + +.*: +file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32 eax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32 rax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32 eax,WORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32 eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32 rax,QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32 rax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32 rax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32 rax,rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32 rax,rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32 rax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32 eax,BYTE PTR \[rsi\] +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32 eax,WORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32 eax,DWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32 rax,QWORD PTR \[rsi\] +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32 eax,al +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32 rax,al +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32 eax,ax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32 eax,eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32 rax,rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-crc32.d b/gas/testsuite/gas/i386/x86-64-crc32.d new file mode 100644 index 000000000000..1a33fac02d85 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32.d @@ -0,0 +1,34 @@ +#objdump: -dw +#name: x86-64 crc32 + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 06 crc32b \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f0 06 crc32b \(%rsi\),%eax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 06 crc32w \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 06 crc32l \(%rsi\),%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 06 crc32q \(%rsi\),%rax +[ ]*[a-f0-9]+: f2 0f 38 f0 c0 crc32b %al,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f0 c0 crc32b %al,%rax +[ ]*[a-f0-9]+: 66 f2 0f 38 f1 c0 crc32w %ax,%eax +[ ]*[a-f0-9]+: f2 0f 38 f1 c0 crc32l %eax,%eax +[ ]*[a-f0-9]+: f2 48 0f 38 f1 c0 crc32q %rax,%rax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-crc32.s b/gas/testsuite/gas/i386/x86-64-crc32.s new file mode 100644 index 000000000000..7ebe894e3413 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-crc32.s @@ -0,0 +1,34 @@ +# Check 64bit crc32 in SSE4.2 + + .text +foo: + +crc32b (%rsi), %eax +crc32b (%rsi), %rax +crc32w (%rsi), %eax +crc32l (%rsi), %eax +crc32q (%rsi), %rax +crc32 %al, %eax +crc32b %al, %eax +crc32 %al, %rax +crc32b %al, %rax +crc32 %ax, %eax +crc32w %ax, %eax +crc32 %eax, %eax +crc32l %eax, %eax +crc32 %rax, %rax +crc32q %rax, %rax + +.intel_syntax noprefix +crc32 rax,byte ptr [rsi] +crc32 eax,byte ptr [rsi] +crc32 eax, word ptr [rsi] +crc32 eax,dword ptr [rsi] +crc32 rax,qword ptr [rsi] +crc32 eax,al +crc32 rax,al +crc32 eax, ax +crc32 eax,eax +crc32 rax,rax + +.p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-crx-suffix.d b/gas/testsuite/gas/i386/x86-64-crx-suffix.d index 1dc3584219ed..6dfd47cdef65 100644 --- a/gas/testsuite/gas/i386/x86-64-crx-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-crx-suffix.d @@ -2,7 +2,7 @@ #name: x86-64 control register related opcodes (with suffixes) #source: x86-64-crx.s -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-crx.d b/gas/testsuite/gas/i386/x86-64-crx.d index 8c1333f53693..62abe70301a5 100644 --- a/gas/testsuite/gas/i386/x86-64-crx.d +++ b/gas/testsuite/gas/i386/x86-64-crx.d @@ -2,7 +2,7 @@ #name: x86-64 control register related opcodes #source: x86-64-crx.s -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-drx-suffix.d b/gas/testsuite/gas/i386/x86-64-drx-suffix.d index 1f76b8b163b8..254e24defc4d 100644 --- a/gas/testsuite/gas/i386/x86-64-drx-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-drx-suffix.d @@ -2,7 +2,7 @@ #name: x86-64 debug register related opcodes (with suffixes) #source: x86-64-drx.s -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-drx.d b/gas/testsuite/gas/i386/x86-64-drx.d index 879ce50a5ef8..18b328f9b30c 100644 --- a/gas/testsuite/gas/i386/x86-64-drx.d +++ b/gas/testsuite/gas/i386/x86-64-drx.d @@ -1,7 +1,7 @@ #objdump: -dw #name: x86-64 debug register related opcodes -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-gidt.d b/gas/testsuite/gas/i386/x86-64-gidt.d new file mode 100644 index 000000000000..d8b0a0671a26 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-gidt.d @@ -0,0 +1,17 @@ +#objdump: -dw +#name: 64bit load/store global/interrupt description table register. + +.*: +file format .* + +Disassembly of section .text: + +0+000 <foo>: + 0: 0f 01 08 [ ]*sidt \(%rax\) + 3: 0f 01 18 [ ]*lidt \(%rax\) + 6: 0f 01 00 [ ]*sgdt \(%rax\) + 9: 0f 01 10 [ ]*lgdt \(%rax\) + c: 0f 01 08 [ ]*sidt \(%rax\) + f: 0f 01 18 [ ]*lidt \(%rax\) + 12: 0f 01 00 [ ]*sgdt \(%rax\) + 15: 0f 01 10 [ ]*lgdt \(%rax\) + ... diff --git a/gas/testsuite/gas/i386/x86-64-gidt.s b/gas/testsuite/gas/i386/x86-64-gidt.s new file mode 100644 index 000000000000..dd2028910b92 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-gidt.s @@ -0,0 +1,14 @@ +# Instructions to load/store global/interrupt description table +# register. + + .text +foo: + sidt (%rax) + lidt (%rax) + sgdt (%rax) + lgdt (%rax) + sidtq (%rax) + lidtq (%rax) + sgdtq (%rax) + lgdtq (%rax) + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.l b/gas/testsuite/gas/i386/x86-64-inval-crc32.l new file mode 100644 index 000000000000..b4a8eaabcf67 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.l @@ -0,0 +1,65 @@ +.*: Assembler messages: +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* +.*:10: Error: .* +.*:11: Error: .* +.*:12: Error: .* +.*:13: Error: .* +.*:14: Error: .* +.*:15: Error: .* +.*:16: Error: .* +.*:17: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:24: Error: .* +.*:25: Error: .* +.*:26: Error: .* +.*:27: Error: .* +.*:28: Error: .* +.*:29: Error: .* +.*:30: Error: .* +.*:31: Error: .* +.*:32: Error: .* +.*:33: Error: .* +.*:34: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\# Check illegal 64bit crc32 in SSE4\.2 +[ ]*2[ ]+ +[ ]*3[ ]+\.text +[ ]*4[ ]+foo: +[ ]*5[ ]+ +[ ]*6[ ]+crc32b \(%rsi\), %al +[ ]*7[ ]+crc32w \(%rsi\), %ax +[ ]*8[ ]+crc32 \(%rsi\), %al +[ ]*9[ ]+crc32 \(%rsi\), %ax +[ ]*10[ ]+crc32 \(%rsi\), %eax +[ ]*11[ ]+crc32 \(%rsi\), %rax +[ ]*12[ ]+crc32 %al, %al +[ ]*13[ ]+crc32b %al, %al +[ ]*14[ ]+crc32 %ax, %ax +[ ]*15[ ]+crc32w %ax, %ax +[ ]*16[ ]+crc32 %rax, %eax +[ ]*17[ ]+crc32 %eax, %rax +[ ]*18[ ]+crc32l %rax, %eax +[ ]*19[ ]+crc32l %eax, %rax +[ ]*20[ ]+crc32q %eax, %rax +[ ]*21[ ]+crc32q %rax, %eax +[ ]*22[ ]+ +[ ]*23[ ]+\.intel_syntax noprefix +[ ]*24[ ]+crc32 al,byte ptr \[rsi\] +[ ]*25[ ]+crc32 ax, word ptr \[rsi\] +[ ]*26[ ]+crc32 rax,word ptr \[rsi\] +[ ]*27[ ]+crc32 rax,dword ptr \[rsi\] +[ ]*28[ ]+crc32 al,\[rsi\] +[ ]*29[ ]+crc32 ax,\[rsi\] +[ ]*30[ ]+crc32 eax,\[rsi\] +[ ]*31[ ]+crc32 rax,\[rsi\] +[ ]*32[ ]+crc32 al,al +[ ]*33[ ]+crc32 ax, ax +[ ]*34[ ]+crc32 rax,eax diff --git a/gas/testsuite/gas/i386/x86-64-inval-crc32.s b/gas/testsuite/gas/i386/x86-64-inval-crc32.s new file mode 100644 index 000000000000..77408118ba77 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-crc32.s @@ -0,0 +1,34 @@ +# Check illegal 64bit crc32 in SSE4.2 + + .text +foo: + +crc32b (%rsi), %al +crc32w (%rsi), %ax +crc32 (%rsi), %al +crc32 (%rsi), %ax +crc32 (%rsi), %eax +crc32 (%rsi), %rax +crc32 %al, %al +crc32b %al, %al +crc32 %ax, %ax +crc32w %ax, %ax +crc32 %rax, %eax +crc32 %eax, %rax +crc32l %rax, %eax +crc32l %eax, %rax +crc32q %eax, %rax +crc32q %rax, %eax + +.intel_syntax noprefix +crc32 al,byte ptr [rsi] +crc32 ax, word ptr [rsi] +crc32 rax,word ptr [rsi] +crc32 rax,dword ptr [rsi] +crc32 al,[rsi] +crc32 ax,[rsi] +crc32 eax,[rsi] +crc32 rax,[rsi] +crc32 al,al +crc32 ax, ax +crc32 rax,eax diff --git a/gas/testsuite/gas/i386/x86-64-inval.l b/gas/testsuite/gas/i386/x86-64-inval.l index aa080cba46a6..87503e5bbde0 100644 --- a/gas/testsuite/gas/i386/x86-64-inval.l +++ b/gas/testsuite/gas/i386/x86-64-inval.l @@ -48,6 +48,8 @@ .*:49: Error: .* .*:50: Error: .* .*:51: Error: .* +.*:52: Error: .* +.*:54: Error: .* GAS LISTING .* @@ -102,3 +104,6 @@ GAS LISTING .* 49 [ ]*pushfl # can't have 32-bit stack operands 50 [ ]*popfl # can't have 32-bit stack operands 51 [ ]*retl # can't have 32-bit stack operands + 52 [ ]*insertq \$4,\$2,%xmm2,%ebx # The last operand must be XMM register. + 53 [ ]*.intel_syntax noprefix + 54 [ ]*cmpxchg16b dword ptr \[rax\] # Must be oword diff --git a/gas/testsuite/gas/i386/x86-64-inval.s b/gas/testsuite/gas/i386/x86-64-inval.s index b069a282e5c5..f7a4379ad407 100644 --- a/gas/testsuite/gas/i386/x86-64-inval.s +++ b/gas/testsuite/gas/i386/x86-64-inval.s @@ -49,3 +49,6 @@ foo: jcxz foo # No prefix exists to select CX as a counter pushfl # can't have 32-bit stack operands popfl # can't have 32-bit stack operands retl # can't have 32-bit stack operands + insertq $4,$2,%xmm2,%ebx # The last operand must be XMM register. + .intel_syntax noprefix + cmpxchg16b dword ptr [rax] # Must be oword diff --git a/gas/testsuite/gas/i386/x86-64-io-intel.d b/gas/testsuite/gas/i386/x86-64-io-intel.d new file mode 100644 index 000000000000..c6df6e68c3f0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io-intel.d @@ -0,0 +1,28 @@ +#source: x86-64-io.s +#objdump: -dwMintel +#name: x86-64 rex.W in/out (Intel disassembly) + +.*: +file format .* + +Disassembly of section .text: + +0+000 <_in>: + 0: 48 ed rex.W in eax,dx + 2: 66 data16 + 3: 48 ed rex.W in eax,dx + +0+005 <_out>: + 5: 48 ef rex.W out dx,eax + 7: 66 data16 + 8: 48 ef rex.W out dx,eax + +0+00a <_ins>: + a: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx + c: 66 data16 + d: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx + +0+00f <_outs>: + f: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] + 11: 66 data16 + 12: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io-suffix.d b/gas/testsuite/gas/i386/x86-64-io-suffix.d new file mode 100644 index 000000000000..a0ee9d0289c7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io-suffix.d @@ -0,0 +1,28 @@ +#source: x86-64-io.s +#objdump: -dwMsuffix +#name: x86-64 rex.W in/out w/ suffix + +.*: +file format .* + +Disassembly of section .text: + +0+000 <_in>: + 0: 48 ed rex.W inl \(%dx\),%eax + 2: 66 data16 + 3: 48 ed rex.W inl \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W outl %eax,\(%dx\) + 7: 66 data16 + 8: 48 ef rex.W outl %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) + c: 66 data16 + d: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) + 11: 66 data16 + 12: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io.d b/gas/testsuite/gas/i386/x86-64-io.d new file mode 100644 index 000000000000..3e3b7e7bad24 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io.d @@ -0,0 +1,27 @@ +#objdump: -dw +#name: x86-64 rex.W in/out + +.*: +file format .* + +Disassembly of section .text: + +0+000 <_in>: + 0: 48 ed rex.W in \(%dx\),%eax + 2: 66 data16 + 3: 48 ed rex.W in \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W out %eax,\(%dx\) + 7: 66 data16 + 8: 48 ef rex.W out %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) + c: 66 data16 + d: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) + 11: 66 data16 + 12: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io.s b/gas/testsuite/gas/i386/x86-64-io.s new file mode 100644 index 000000000000..58200c825b80 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io.s @@ -0,0 +1,16 @@ + .intel_syntax noprefix + .text +_in: + rex64 in eax,dx + rex64 in ax,dx +_out: + rex64 out dx,eax + rex64 out dx,ax +_ins: + rex64 insd + rex64 insw +_outs: + rex64 outsd + rex64 outsw + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-merom.d b/gas/testsuite/gas/i386/x86-64-merom.d index f15a6e466abc..4593e526ef25 100644 --- a/gas/testsuite/gas/i386/x86-64-merom.d +++ b/gas/testsuite/gas/i386/x86-64-merom.d @@ -70,4 +70,4 @@ Disassembly of section .text: 116: 0f 38 1e c1[ ]+pabsd %mm1,%mm0 11a: 66 0f 38 1e 01[ ]+pabsd \(%rcx\),%xmm0 11f: 66 0f 38 1e c1[ ]+pabsd %xmm1,%xmm0 - ... +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-k8.d b/gas/testsuite/gas/i386/x86-64-nops-1-k8.d new file mode 100644 index 000000000000..6785fbb065f9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-k8.d @@ -0,0 +1,177 @@ +#as: -mtune=k8 +#source: x86-64-nops-1.s +#objdump: -drw +#name: x86-64 -mtune=k8 nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*5:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*9:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*16:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*1a:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*1d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*27:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*2a:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*2d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*38:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*3c:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*49:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*4d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*5a:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*5d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*6a:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*6d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*7c:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*8d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*9d:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax +[ ]*ae:[ ]+66 90[ ]+xchg[ ]+%ax,%ax + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+66 66 66 90[ ]+xchg[ ]+%ax,%ax + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+66 66 90[ ]+xchg[ ]+%ax,%ax + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-merom.d b/gas/testsuite/gas/i386/x86-64-nops-1-merom.d new file mode 100644 index 000000000000..2aa49aeeec62 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-merom.d @@ -0,0 +1,156 @@ +#as: -mtune=merom +#source: x86-64-nops-1.s +#objdump: -drw +#name: x86-64 -mtune=merom nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+66 66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%rax\) + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d new file mode 100644 index 000000000000..c1886b605a71 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d @@ -0,0 +1,161 @@ +#as: -mtune=nocona +#source: x86-64-nops-1.s +#objdump: -drw +#name: x86-64 -mtune=nocona nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*8:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*19:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*29:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*3a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) +[ ]*4a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%rax\) + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1.d b/gas/testsuite/gas/i386/x86-64-nops-1.d new file mode 100644 index 000000000000..a6d8188754ac --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1.d @@ -0,0 +1,160 @@ +#source: x86-64-nops-1.s +#objdump: -drw +#name: x86-64 nops 1 + +.*: +file format .* + +Disassembly of section .text: + +0+ <nop15>: +[ ]*0:[ ]+90[ ]+nop[ ]* +[ ]*1:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*8:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+10 <nop14>: +[ ]*10:[ ]+90[ ]+nop[ ]* +[ ]*11:[ ]+90[ ]+nop[ ]* +[ ]*12:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*19:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+20 <nop13>: +[ ]*20:[ ]+90[ ]+nop[ ]* +[ ]*21:[ ]+90[ ]+nop[ ]* +[ ]*22:[ ]+90[ ]+nop[ ]* +[ ]*23:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*29:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+30 <nop12>: +[ ]*30:[ ]+90[ ]+nop[ ]* +[ ]*31:[ ]+90[ ]+nop[ ]* +[ ]*32:[ ]+90[ ]+nop[ ]* +[ ]*33:[ ]+90[ ]+nop[ ]* +[ ]*34:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*3a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+40 <nop11>: +[ ]*40:[ ]+90[ ]+nop[ ]* +[ ]*41:[ ]+90[ ]+nop[ ]* +[ ]*42:[ ]+90[ ]+nop[ ]* +[ ]*43:[ ]+90[ ]+nop[ ]* +[ ]*44:[ ]+90[ ]+nop[ ]* +[ ]*45:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) +[ ]*4a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+50 <nop10>: +[ ]*50:[ ]+90[ ]+nop[ ]* +[ ]*51:[ ]+90[ ]+nop[ ]* +[ ]*52:[ ]+90[ ]+nop[ ]* +[ ]*53:[ ]+90[ ]+nop[ ]* +[ ]*54:[ ]+90[ ]+nop[ ]* +[ ]*55:[ ]+90[ ]+nop[ ]* +[ ]*56:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) + +0+60 <nop9>: +[ ]*60:[ ]+90[ ]+nop[ ]* +[ ]*61:[ ]+90[ ]+nop[ ]* +[ ]*62:[ ]+90[ ]+nop[ ]* +[ ]*63:[ ]+90[ ]+nop[ ]* +[ ]*64:[ ]+90[ ]+nop[ ]* +[ ]*65:[ ]+90[ ]+nop[ ]* +[ ]*66:[ ]+90[ ]+nop[ ]* +[ ]*67:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+70 <nop8>: +[ ]*70:[ ]+90[ ]+nop[ ]* +[ ]*71:[ ]+90[ ]+nop[ ]* +[ ]*72:[ ]+90[ ]+nop[ ]* +[ ]*73:[ ]+90[ ]+nop[ ]* +[ ]*74:[ ]+90[ ]+nop[ ]* +[ ]*75:[ ]+90[ ]+nop[ ]* +[ ]*76:[ ]+90[ ]+nop[ ]* +[ ]*77:[ ]+90[ ]+nop[ ]* +[ ]*78:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+80 <nop7>: +[ ]*80:[ ]+90[ ]+nop[ ]* +[ ]*81:[ ]+90[ ]+nop[ ]* +[ ]*82:[ ]+90[ ]+nop[ ]* +[ ]*83:[ ]+90[ ]+nop[ ]* +[ ]*84:[ ]+90[ ]+nop[ ]* +[ ]*85:[ ]+90[ ]+nop[ ]* +[ ]*86:[ ]+90[ ]+nop[ ]* +[ ]*87:[ ]+90[ ]+nop[ ]* +[ ]*88:[ ]+90[ ]+nop[ ]* +[ ]*89:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) + +0+90 <nop6>: +[ ]*90:[ ]+90[ ]+nop[ ]* +[ ]*91:[ ]+90[ ]+nop[ ]* +[ ]*92:[ ]+90[ ]+nop[ ]* +[ ]*93:[ ]+90[ ]+nop[ ]* +[ ]*94:[ ]+90[ ]+nop[ ]* +[ ]*95:[ ]+90[ ]+nop[ ]* +[ ]*96:[ ]+90[ ]+nop[ ]* +[ ]*97:[ ]+90[ ]+nop[ ]* +[ ]*98:[ ]+90[ ]+nop[ ]* +[ ]*99:[ ]+90[ ]+nop[ ]* +[ ]*9a:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) + +0+a0 <nop5>: +[ ]*a0:[ ]+90[ ]+nop[ ]* +[ ]*a1:[ ]+90[ ]+nop[ ]* +[ ]*a2:[ ]+90[ ]+nop[ ]* +[ ]*a3:[ ]+90[ ]+nop[ ]* +[ ]*a4:[ ]+90[ ]+nop[ ]* +[ ]*a5:[ ]+90[ ]+nop[ ]* +[ ]*a6:[ ]+90[ ]+nop[ ]* +[ ]*a7:[ ]+90[ ]+nop[ ]* +[ ]*a8:[ ]+90[ ]+nop[ ]* +[ ]*a9:[ ]+90[ ]+nop[ ]* +[ ]*aa:[ ]+90[ ]+nop[ ]* +[ ]*ab:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) + +0+b0 <nop4>: +[ ]*b0:[ ]+90[ ]+nop[ ]* +[ ]*b1:[ ]+90[ ]+nop[ ]* +[ ]*b2:[ ]+90[ ]+nop[ ]* +[ ]*b3:[ ]+90[ ]+nop[ ]* +[ ]*b4:[ ]+90[ ]+nop[ ]* +[ ]*b5:[ ]+90[ ]+nop[ ]* +[ ]*b6:[ ]+90[ ]+nop[ ]* +[ ]*b7:[ ]+90[ ]+nop[ ]* +[ ]*b8:[ ]+90[ ]+nop[ ]* +[ ]*b9:[ ]+90[ ]+nop[ ]* +[ ]*ba:[ ]+90[ ]+nop[ ]* +[ ]*bb:[ ]+90[ ]+nop[ ]* +[ ]*bc:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%rax\) + +0+c0 <nop3>: +[ ]*c0:[ ]+90[ ]+nop[ ]* +[ ]*c1:[ ]+90[ ]+nop[ ]* +[ ]*c2:[ ]+90[ ]+nop[ ]* +[ ]*c3:[ ]+90[ ]+nop[ ]* +[ ]*c4:[ ]+90[ ]+nop[ ]* +[ ]*c5:[ ]+90[ ]+nop[ ]* +[ ]*c6:[ ]+90[ ]+nop[ ]* +[ ]*c7:[ ]+90[ ]+nop[ ]* +[ ]*c8:[ ]+90[ ]+nop[ ]* +[ ]*c9:[ ]+90[ ]+nop[ ]* +[ ]*ca:[ ]+90[ ]+nop[ ]* +[ ]*cb:[ ]+90[ ]+nop[ ]* +[ ]*cc:[ ]+90[ ]+nop[ ]* +[ ]*cd:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) + +0+d0 <nop2>: +[ ]*d0:[ ]+90[ ]+nop[ ]* +[ ]*d1:[ ]+90[ ]+nop[ ]* +[ ]*d2:[ ]+90[ ]+nop[ ]* +[ ]*d3:[ ]+90[ ]+nop[ ]* +[ ]*d4:[ ]+90[ ]+nop[ ]* +[ ]*d5:[ ]+90[ ]+nop[ ]* +[ ]*d6:[ ]+90[ ]+nop[ ]* +[ ]*d7:[ ]+90[ ]+nop[ ]* +[ ]*d8:[ ]+90[ ]+nop[ ]* +[ ]*d9:[ ]+90[ ]+nop[ ]* +[ ]*da:[ ]+90[ ]+nop[ ]* +[ ]*db:[ ]+90[ ]+nop[ ]* +[ ]*dc:[ ]+90[ ]+nop[ ]* +[ ]*dd:[ ]+90[ ]+nop[ ]* +[ ]*de:[ ]+66 90[ ]+xchg[ ]+%ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1.s b/gas/testsuite/gas/i386/x86-64-nops-1.s new file mode 100644 index 000000000000..a4fd7694de76 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1.s @@ -0,0 +1,147 @@ + .text +nop15: + nop + .p2align 4 + +nop14: + nop + nop + .p2align 4 + +nop13: + nop + nop + nop + .p2align 4 + +nop12: + nop + nop + nop + nop + .p2align 4 + +nop11: + nop + nop + nop + nop + nop + .p2align 4 + +nop10: + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop9: + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop8: + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop7: + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop6: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop5: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop4: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop3: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 + +nop2: + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + .p2align 4 diff --git a/gas/testsuite/gas/i386/x86-64-nops.d b/gas/testsuite/gas/i386/x86-64-nops.d new file mode 100644 index 000000000000..916361925359 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops.d @@ -0,0 +1,37 @@ +#objdump: -drw +#name: x86-64 nops + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) +[ ]*3:[ ]+0f 1f 40 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*7:[ ]+0f 1f 44 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) +[ ]*c:[ ]+66 0f 1f 44 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*12:[ ]+0f 1f 80 00 00 00 00[ ]+nopl[ ]+0x0\(%rax\) +[ ]*19:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\) +[ ]*21:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\) +[ ]*2a:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\) +[ ]*34:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) +[ ]*37:[ ]+48 0f 1f c0[ ]+nop[ ]+%rax +[ ]*3b:[ ]+0f 1f c0[ ]+nop[ ]+%eax +[ ]*3e:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax +[ ]*42:[ ]+48 0f 1f 00[ ]+nopq[ ]+\(%rax\) +[ ]*46:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\) +[ ]*49:[ ]+66 0f 1f 00[ ]+nopw[ ]+\(%rax\) +[ ]*4d:[ ]+48 0f 1f c0[ ]+nop[ ]+%rax +[ ]*51:[ ]+0f 1f c0[ ]+nop[ ]+%eax +[ ]*54:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax +[ ]*58:[ ]+41 0f 1f 02[ ]+nopl[ ]+\(%r10\) +[ ]*5c:[ ]+49 0f 1f c2[ ]+nop[ ]+%r10 +[ ]*60:[ ]+41 0f 1f c2[ ]+nop[ ]+%r10d +[ ]*64:[ ]+66 41 0f 1f c2[ ]+nop[ ]+%r10w +[ ]*69:[ ]+49 0f 1f 02[ ]+nopq[ ]+\(%r10\) +[ ]*6d:[ ]+41 0f 1f 02[ ]+nopl[ ]+\(%r10\) +[ ]*71:[ ]+66 41 0f 1f 02[ ]+nopw[ ]+\(%r10\) +[ ]*76:[ ]+49 0f 1f c2[ ]+nop[ ]+%r10 +[ ]*7a:[ ]+41 0f 1f c2[ ]+nop[ ]+%r10d +[ ]*7e:[ ]+66 41 0f 1f c2[ ]+nop[ ]+%r10w +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops.s b/gas/testsuite/gas/i386/x86-64-nops.s new file mode 100644 index 000000000000..2268e7f57699 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops.s @@ -0,0 +1,33 @@ + .text + + .byte 0x0f, 0x1f, 0x0 + .byte 0x0f, 0x1f, 0x40, 0x0 + .byte 0x0f, 0x1f, 0x44, 0x0, 0x0 + .byte 0x66, 0x0f, 0x1f, 0x44, 0x0, 0x0 + .byte 0x0f, 0x1f, 0x80, 0x0, 0x0, 0x0, 0x0 + .byte 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + .byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + .byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0 + + nop (%rax) + nop %rax + nop %eax + nop %ax + nopq (%rax) + nopl (%rax) + nopw (%rax) + nopq %rax + nopl %eax + nopw %ax + nop (%r10) + nop %r10 + nop %r10d + nop %r10w + nopq (%r10) + nopl (%r10) + nopw (%r10) + nopq %r10 + nopl %r10d + nopw %r10w + + .p2align 4 diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d index 13d58be1bdb8..912075e3bee9 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.d +++ b/gas/testsuite/gas/i386/x86-64-opcode.d @@ -2,7 +2,7 @@ #objdump: -drw #name: x86-64 opcode -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: @@ -263,9 +263,33 @@ Disassembly of section .text: [ ]*[0-9a-f]+:[ ]+41 0f 01 38[ ]+invlpg[ ]+\(%r8\)[ ]*(#.*)* [ ]*[0-9a-f]+:[ ]+0f 01 38[ ]+invlpg[ ]+\(%rax\)[ ]*(#.*)* [ ]*[0-9a-f]+:[ ]+0f 00 c0[ ]+sldt[ ]+%eax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+48 0f 00 c0[ ]+sldt[ ]+%rax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 0f 00 c0[ ]+sldt[ ]+%ax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+0f 00 00[ ]+sldt[ ]+\(%rax\)[ ]*(#.*)* [ ]*[0-9a-f]+:[ ]+e6 00[ ]+out[ ]+%al,\$0[x0]*[ ]*(#.*)* [ ]*[0-9a-f]+:[ ]+66 e7 00[ ]+out[ ]+%ax,\$0[x0]*[ ]*(#.*)* [ ]*[0-9a-f]+:[ ]+e7 00[ ]+out[ ]+%eax,\$0[x0]*[ ]*(#.*)* -[ ]*[0-9a-f]+:[ ]+00 00[ ]+.* -[ ]*[0-9a-f]+:[ ]+00 00[ ]+.* -[ *]... +[ ]*[0-9a-f]+:[ ]+66 90[ ]+xchg[ ]+%ax,%ax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+87 c0[ ]+xchg[ ]+%eax,%eax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+90[ ]+nop[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+48 90[ ]+rex.W nop[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+49 90[ ]+xchg[ ]+%rax,%r8[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+41 90[ ]+xchg[ ]+%eax,%r8d[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+41 90[ ]+xchg[ ]+%eax,%r8d[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+41 91[ ]+xchg[ ]+%eax,%r9d[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+41 91[ ]+xchg[ ]+%eax,%r9d[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+93[ ]+xchg[ ]+%eax,%ebx[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+93[ ]+xchg[ ]+%eax,%ebx[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 41 90[ ]+xchg[ ]+%ax,%r8w[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 41 90[ ]+xchg[ ]+%ax,%r8w[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 41 91[ ]+xchg[ ]+%ax,%r9w[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 41 91[ ]+xchg[ ]+%ax,%r9w[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+48 0f 01 e0[ ]+smsw[ ]+%rax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+0f 01 e0[ ]+smsw[ ]+%eax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 0f 01 e0[ ]+smsw[ ]+%ax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+0f 01 20[ ]+smsw[ ]+\(%rax\)[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+48 0f 00 c8[ ]+str[ ]+%rax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+0f 00 c8[ ]+str[ ]+%eax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+66 0f 00 c8[ ]+str[ ]+%ax[ ]*(#.*)* +[ ]*[0-9a-f]+:[ ]+0f 00 08[ ]+str[ ]+\(%rax\)[ ]*(#.*)* +#pass diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s index 8b132b390468..dd373427dde1 100644 --- a/gas/testsuite/gas/i386/x86-64-opcode.s +++ b/gas/testsuite/gas/i386/x86-64-opcode.s @@ -373,6 +373,9 @@ # SLDT # SLDT (%eax) # -- 67 -- -- 0F 00 00 ; A32 override: (Addr64) = ZEXT(Addr32 ) SLDT %eax # -- -- -- -- 0F 00 C0 + SLDT %rax # -- -- -- 48 0F 00 C0 + SLDT %ax # 66 -- -- -- 0F 00 C0 + SLDT (%rax) # -- -- -- -- 0F 00 00 # SWAPGS @@ -387,4 +390,32 @@ # IN + + + xchg %ax,%ax # 66 -- -- -- 90 + xchg %eax,%eax # -- -- -- -- 87 C0 + xchg %rax,%rax # -- -- -- -- 90 + rex64 xchg %rax,%rax # -- -- -- 48 90 + xchg %rax,%r8 # -- -- -- 49 90 + xchg %eax,%r8d # -- -- -- 41 90 + xchg %r8d,%eax # -- -- -- 41 90 + xchg %eax,%r9d # -- -- -- 41 91 + xchg %r9d,%eax # -- -- -- 41 91 + xchg %ebx,%eax # -- -- -- 93 + xchg %eax,%ebx # -- -- -- 93 + xchg %ax,%r8w # -- -- -- 66 41 90 + xchg %r8w,%ax # -- -- -- 66 41 90 + xchg %ax,%r9w # -- -- -- 66 41 91 + xchg %r9w,%ax # -- -- -- 66 41 91 + + smsw %rax # -- -- -- 48 0F 01 e0 + smsw %eax # -- -- -- -- 0F 01 e0 + smsw %ax # 66 -- -- -- 0F 01 e0 + smsw (%rax) # -- -- -- -- 0F 01 20 + + str %rax # -- -- -- 48 0F 00 c8 + str %eax # -- -- -- -- 0F 00 c8 + str %ax # 66 -- -- -- 0F 00 c8 + str (%rax) # -- -- -- -- 0F 00 08 + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-pcrel.d b/gas/testsuite/gas/i386/x86-64-pcrel.d index 3be86c7c3405..818ea2e6f734 100644 --- a/gas/testsuite/gas/i386/x86-64-pcrel.d +++ b/gas/testsuite/gas/i386/x86-64-pcrel.d @@ -1,7 +1,7 @@ #objdump: -drw #name: x86-64 pcrel -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-prescott.d b/gas/testsuite/gas/i386/x86-64-prescott.d index 43a2d2802027..26b9e6ec95f6 100644 --- a/gas/testsuite/gas/i386/x86-64-prescott.d +++ b/gas/testsuite/gas/i386/x86-64-prescott.d @@ -10,9 +10,9 @@ Disassembly of section .text: 4: 66 0f d0 ca [ ]*addsubpd %xmm2,%xmm1 8: f2 0f d0 13 [ ]*addsubps \(%rbx\),%xmm2 c: f2 0f d0 dc [ ]*addsubps %xmm4,%xmm3 - 10: df 88 90 90 90 90 [ ]*fisttp 0xffffffff90909090\(%rax\) - 16: db 88 90 90 90 90 [ ]*fisttpl 0xffffffff90909090\(%rax\) - 1c: dd 88 90 90 90 90 [ ]*fisttpll 0xffffffff90909090\(%rax\) + 10: df 88 90 90 90 90 [ ]*fisttp -0x6f6f6f70\(%rax\) + 16: db 88 90 90 90 90 [ ]*fisttpl -0x6f6f6f70\(%rax\) + 1c: dd 88 90 90 90 90 [ ]*fisttpll -0x6f6f6f70\(%rax\) 22: 66 0f 7c 65 00 [ ]*haddpd 0x0\(%rbp\),%xmm4 27: 66 0f 7c ee [ ]*haddpd %xmm6,%xmm5 2b: f2 0f 7c 37 [ ]*haddps \(%rdi\),%xmm6 diff --git a/gas/testsuite/gas/i386/x86-64-rep-suffix.d b/gas/testsuite/gas/i386/x86-64-rep-suffix.d index a85b4a941779..68a90d9d6be4 100644 --- a/gas/testsuite/gas/i386/x86-64-rep-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-rep-suffix.d @@ -8,8 +8,8 @@ Disassembly of section .text: 0+000 <_start>: 0: f3 ac[ ]+rep lodsb %ds:\(%rsi\),%al 2: f3 aa[ ]+rep stosb %al,%es:\(%rdi\) - 4: f3 66 ad[ ]+rep lodsw %ds:\(%rsi\),%ax - 7: f3 66 ab[ ]+rep stosw %ax,%es:\(%rdi\) + 4: 66 f3 ad[ ]+rep lodsw %ds:\(%rsi\),%ax + 7: 66 f3 ab[ ]+rep stosw %ax,%es:\(%rdi\) a: f3 ad[ ]+rep lodsl %ds:\(%rsi\),%eax c: f3 ab[ ]+rep stosl %eax,%es:\(%rdi\) e: f3 48 ad[ ]+rep lodsq %ds:\(%rsi\),%rax diff --git a/gas/testsuite/gas/i386/x86-64-rep.d b/gas/testsuite/gas/i386/x86-64-rep.d index 631b7113d8e7..66fc03636c58 100644 --- a/gas/testsuite/gas/i386/x86-64-rep.d +++ b/gas/testsuite/gas/i386/x86-64-rep.d @@ -13,13 +13,13 @@ Disassembly of section .text: 8: f3 aa[ ]+rep stos %al,%es:\(%rdi\) a: f3 a6[ ]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\) c: f3 ae[ ]+repz scas %es:\(%rdi\),%al - e: f3 66 6d[ ]+rep insw \(%dx\),%es:\(%rdi\) - 11: f3 66 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\) - 14: f3 66 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) - 17: f3 66 ad[ ]+rep lods %ds:\(%rsi\),%ax - 1a: f3 66 ab[ ]+rep stos %ax,%es:\(%rdi\) - 1d: f3 66 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\) - 20: f3 66 af[ ]+repz scas %es:\(%rdi\),%ax + e: 66 f3 6d[ ]+rep insw \(%dx\),%es:\(%rdi\) + 11: 66 f3 6f[ ]+rep outsw %ds:\(%rsi\),\(%dx\) + 14: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) + 17: 66 f3 ad[ ]+rep lods %ds:\(%rsi\),%ax + 1a: 66 f3 ab[ ]+rep stos %ax,%es:\(%rdi\) + 1d: 66 f3 a7[ ]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\) + 20: 66 f3 af[ ]+repz scas %es:\(%rdi\),%ax 23: f3 6d[ ]+rep insl \(%dx\),%es:\(%rdi\) 25: f3 6f[ ]+rep outsl %ds:\(%rsi\),\(%dx\) 27: f3 a5[ ]+rep movsl %ds:\(%rsi\),%es:\(%rdi\) @@ -32,30 +32,30 @@ Disassembly of section .text: 37: f3 48 ab[ ]+rep stos %rax,%es:\(%rdi\) 3a: f3 48 a7[ ]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\) 3d: f3 48 af[ ]+repz scas %es:\(%rdi\),%rax - 40: f3 67 6c[ ]+rep addr32 insb \(%dx\),%es:\(%edi\) - 43: f3 67 6e[ ]+rep addr32 outsb %ds:\(%esi\),\(%dx\) - 46: f3 67 a4[ ]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\) - 49: f3 67 ac[ ]+rep addr32 lods %ds:\(%esi\),%al - 4c: f3 67 aa[ ]+rep addr32 stos %al,%es:\(%edi\) - 4f: f3 67 a6[ ]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\) - 52: f3 67 ae[ ]+repz addr32 scas %es:\(%edi\),%al - 55: f3 67 66 6d[ ]+rep addr32 insw \(%dx\),%es:\(%edi\) - 59: f3 67 66 6f[ ]+rep addr32 outsw %ds:\(%esi\),\(%dx\) - 5d: f3 67 66 a5[ ]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\) - 61: f3 67 66 ad[ ]+rep addr32 lods %ds:\(%esi\),%ax - 65: f3 67 66 ab[ ]+rep addr32 stos %ax,%es:\(%edi\) - 69: f3 67 66 a7[ ]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\) - 6d: f3 67 66 af[ ]+repz addr32 scas %es:\(%edi\),%ax - 71: f3 67 6d[ ]+rep addr32 insl \(%dx\),%es:\(%edi\) - 74: f3 67 6f[ ]+rep addr32 outsl %ds:\(%esi\),\(%dx\) - 77: f3 67 a5[ ]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\) - 7a: f3 67 ad[ ]+rep addr32 lods %ds:\(%esi\),%eax - 7d: f3 67 ab[ ]+rep addr32 stos %eax,%es:\(%edi\) - 80: f3 67 a7[ ]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\) - 83: f3 67 af[ ]+repz addr32 scas %es:\(%edi\),%eax - 86: f3 67 48 a5[ ]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\) - 8a: f3 67 48 ad[ ]+rep addr32 lods %ds:\(%esi\),%rax - 8e: f3 67 48 ab[ ]+rep addr32 stos %rax,%es:\(%edi\) - 92: f3 67 48 a7[ ]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\) - 96: f3 67 48 af[ ]+repz addr32 scas %es:\(%edi\),%rax + 40: 67 f3 6c[ ]+rep addr32 insb \(%dx\),%es:\(%edi\) + 43: 67 f3 6e[ ]+rep addr32 outsb %ds:\(%esi\),\(%dx\) + 46: 67 f3 a4[ ]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\) + 49: 67 f3 ac[ ]+rep addr32 lods %ds:\(%esi\),%al + 4c: 67 f3 aa[ ]+rep addr32 stos %al,%es:\(%edi\) + 4f: 67 f3 a6[ ]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\) + 52: 67 f3 ae[ ]+repz addr32 scas %es:\(%edi\),%al + 55: 67 66 f3 6d[ ]+rep addr32 insw \(%dx\),%es:\(%edi\) + 59: 67 66 f3 6f[ ]+rep addr32 outsw %ds:\(%esi\),\(%dx\) + 5d: 67 66 f3 a5[ ]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\) + 61: 67 66 f3 ad[ ]+rep addr32 lods %ds:\(%esi\),%ax + 65: 67 66 f3 ab[ ]+rep addr32 stos %ax,%es:\(%edi\) + 69: 67 66 f3 a7[ ]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\) + 6d: 67 66 f3 af[ ]+repz addr32 scas %es:\(%edi\),%ax + 71: 67 f3 6d[ ]+rep addr32 insl \(%dx\),%es:\(%edi\) + 74: 67 f3 6f[ ]+rep addr32 outsl %ds:\(%esi\),\(%dx\) + 77: 67 f3 a5[ ]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\) + 7a: 67 f3 ad[ ]+rep addr32 lods %ds:\(%esi\),%eax + 7d: 67 f3 ab[ ]+rep addr32 stos %eax,%es:\(%edi\) + 80: 67 f3 a7[ ]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\) + 83: 67 f3 af[ ]+repz addr32 scas %es:\(%edi\),%eax + 86: 67 f3 48 a5[ ]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\) + 8a: 67 f3 48 ad[ ]+rep addr32 lods %ds:\(%esi\),%rax + 8e: 67 f3 48 ab[ ]+rep addr32 stos %rax,%es:\(%edi\) + 92: 67 f3 48 a7[ ]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\) + 96: 67 f3 48 af[ ]+repz addr32 scas %es:\(%edi\),%rax #pass diff --git a/gas/testsuite/gas/i386/x86-64-rip-intel.d b/gas/testsuite/gas/i386/x86-64-rip-intel.d new file mode 100644 index 000000000000..162f654c556d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-rip-intel.d @@ -0,0 +1,15 @@ +#as: -J +#objdump: -drwMintel +#name: x86-64 rip addressing (Intel mode) +#source: x86-64-rip.s + +.*: +file format .* + +Disassembly of section .text: + +0+000 <.text>: +[ ]*0:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+eax,\[rip\+0x0\][ ]*(#.*)? +[ ]*6:[ ]+8d 05 11 11 11 11[ ]+lea[ ]+eax,\[rip\+0x11111111\][ ]*(#.*)? +[ ]*c:[ ]+8d 05 01 00 00 00[ ]+lea[ ]+eax,\[rip\+0x1\][ ]*(#.*)? +[ ]*12:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+eax,\[rip\+0x0\][ ]*(#.*)? +#pass diff --git a/gas/testsuite/gas/i386/x86-64-rip.d b/gas/testsuite/gas/i386/x86-64-rip.d index 1b1d6c8a31c5..66fe771b9608 100644 --- a/gas/testsuite/gas/i386/x86-64-rip.d +++ b/gas/testsuite/gas/i386/x86-64-rip.d @@ -2,12 +2,13 @@ #objdump: -drw #name: x86-64 rip addressing -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: 0+000 <.text>: -[ ]*0:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0\(%rip\),%eax[ ]*(#.*)? -[ ]*6:[ ]+8d 05 11 11 11 11[ ]+lea[ ]+286331153\(%rip\),%eax[ ]*(#.*)? -[ ]*c:[ ]+8d 05 01 00 00 00[ ]+lea[ ]+1\(%rip\),%eax[ ]*(#.*)? -[ ]*12:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0\(%rip\),%eax[ ]*(#.*)? +[ ]*0:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%rip\),%eax[ ]*(#.*)? +[ ]*6:[ ]+8d 05 11 11 11 11[ ]+lea[ ]+0x11111111\(%rip\),%eax[ ]*(#.*)? +[ ]*c:[ ]+8d 05 01 00 00 00[ ]+lea[ ]+0x1\(%rip\),%eax[ ]*(#.*)? +[ ]*12:[ ]+8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%rip\),%eax[ ]*(#.*)? +#pass diff --git a/gas/testsuite/gas/i386/x86-64-simd-intel.d b/gas/testsuite/gas/i386/x86-64-simd-intel.d new file mode 100644 index 000000000000..799a9b314cf0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d @@ -0,0 +1,37 @@ +#source: x86-64-simd.s +#as: -J +#objdump: -dw -Mintel +#name: x86-64 SIMD (Intel mode) + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: f2 0f d0 0d 78 56 34 12 addsubps xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 2f 0d 78 56 34 12 comisd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 2f 0d 78 56 34 12 comiss xmm1,DWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f e6 0d 78 56 34 12 cvtdq2pd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f e6 0d 78 56 34 12 cvtpd2dq xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 5a 0d 78 56 34 12 cvtps2pd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 7f 0d 78 56 34 12 movdqu XMMWORD PTR \[rip\+0x12345678\],xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 6f 0d 78 56 34 12 movdqu xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 17 0d 78 56 34 12 movhpd QWORD PTR \[rip\+0x12345678\],xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 16 0d 78 56 34 12 movhpd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 17 0d 78 56 34 12 movhps QWORD PTR \[rip\+0x12345678\],xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 16 0d 78 56 34 12 movhps xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 13 0d 78 56 34 12 movlpd QWORD PTR \[rip\+0x12345678\],xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 12 0d 78 56 34 12 movlpd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps QWORD PTR \[rip\+0x12345678\],xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 16 0d 78 56 34 12 movshdup xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 12 0d 78 56 34 12 movsldup xmm1,XMMWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 70 0d 78 56 34 12 90 pshufhw xmm1,XMMWORD PTR \[rip\+0x12345678\],0x90[ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f 70 0d 78 56 34 12 90 pshuflw xmm1,XMMWORD PTR \[rip\+0x12345678\],0x90[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 60 0d 78 56 34 12 punpcklbw mm1,DWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 62 0d 78 56 34 12 punpckldq mm1,DWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 61 0d 78 56 34 12 punpcklwd mm1,DWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 2e 0d 78 56 34 12 ucomisd xmm1,QWORD PTR \[rip\+0x12345678\][ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 2e 0d 78 56 34 12 ucomiss xmm1,DWORD PTR \[rip\+0x12345678\][ ]*(#.*)? diff --git a/gas/testsuite/gas/i386/x86-64-simd.d b/gas/testsuite/gas/i386/x86-64-simd.d new file mode 100644 index 000000000000..f00b2c15ed80 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-simd.d @@ -0,0 +1,36 @@ +#as: -J +#objdump: -dw +#name: x86-64 SIMD + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: f2 0f d0 0d 78 56 34 12 addsubps 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 2f 0d 78 56 34 12 comisd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 2f 0d 78 56 34 12 comiss 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f e6 0d 78 56 34 12 cvtdq2pd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f e6 0d 78 56 34 12 cvtpd2dq 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 5a 0d 78 56 34 12 cvtps2pd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 7f 0d 78 56 34 12 movdqu %xmm1,0x12345678\(%rip\)[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 6f 0d 78 56 34 12 movdqu 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 17 0d 78 56 34 12 movhpd %xmm1,0x12345678\(%rip\)[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 16 0d 78 56 34 12 movhpd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 17 0d 78 56 34 12 movhps %xmm1,0x12345678\(%rip\)[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 16 0d 78 56 34 12 movhps 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 13 0d 78 56 34 12 movlpd %xmm1,0x12345678\(%rip\)[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 12 0d 78 56 34 12 movlpd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 13 0d 78 56 34 12 movlps %xmm1,0x12345678\(%rip\)[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 12 0d 78 56 34 12 movlps 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 16 0d 78 56 34 12 movshdup 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 12 0d 78 56 34 12 movsldup 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f3 0f 70 0d 78 56 34 12 90 pshufhw \$0x90,0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: f2 0f 70 0d 78 56 34 12 90 pshuflw \$0x90,0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 60 0d 78 56 34 12 punpcklbw 0x12345678\(%rip\),%mm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 62 0d 78 56 34 12 punpckldq 0x12345678\(%rip\),%mm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 61 0d 78 56 34 12 punpcklwd 0x12345678\(%rip\),%mm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 66 0f 2e 0d 78 56 34 12 ucomisd 0x12345678\(%rip\),%xmm1[ ]*(#.*)? +[ ]*[a-f0-9]+: 0f 2e 0d 78 56 34 12 ucomiss 0x12345678\(%rip\),%xmm1[ ]*(#.*)? diff --git a/gas/testsuite/gas/i386/x86-64-simd.s b/gas/testsuite/gas/i386/x86-64-simd.s new file mode 100644 index 000000000000..579c1ecbeda5 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-simd.s @@ -0,0 +1,29 @@ + .text +_start: + addsubps 0x12345678(%rip),%xmm1 + comisd 0x12345678(%rip),%xmm1 + comiss 0x12345678(%rip),%xmm1 + cvtdq2pd 0x12345678(%rip),%xmm1 + cvtpd2dq 0x12345678(%rip),%xmm1 + cvtps2pd 0x12345678(%rip),%xmm1 + cvttps2dq 0x12345678(%rip),%xmm1 + haddps 0x12345678(%rip),%xmm1 + movdqu %xmm1,0x12345678(%rip) + movdqu 0x12345678(%rip),%xmm1 + movhpd %xmm1,0x12345678(%rip) + movhpd 0x12345678(%rip),%xmm1 + movhps %xmm1,0x12345678(%rip) + movhps 0x12345678(%rip),%xmm1 + movlpd %xmm1,0x12345678(%rip) + movlpd 0x12345678(%rip),%xmm1 + movlps %xmm1,0x12345678(%rip) + movlps 0x12345678(%rip),%xmm1 + movshdup 0x12345678(%rip),%xmm1 + movsldup 0x12345678(%rip),%xmm1 + pshufhw $0x90,0x12345678(%rip),%xmm1 + pshuflw $0x90,0x12345678(%rip),%xmm1 + punpcklbw 0x12345678(%rip),%mm1 + punpckldq 0x12345678(%rip),%mm1 + punpcklwd 0x12345678(%rip),%mm1 + ucomisd 0x12345678(%rip),%xmm1 + ucomiss 0x12345678(%rip),%xmm1 diff --git a/gas/testsuite/gas/i386/x86-64-sse4_1.d b/gas/testsuite/gas/i386/x86-64-sse4_1.d new file mode 100644 index 000000000000..6ed99e28378a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse4_1.d @@ -0,0 +1,110 @@ +#objdump: -dw +#name: x86-64 SSE4.1 + +.*: file format .* + +Disassembly of section .text: + +0+000 <foo>: +[ ]*[0-9a-f]+: 66 0f 3a 0d 01 00 blendpd \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0d c1 00 blendpd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0c 01 00 blendps \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0c c1 00 blendps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 15 01 blendvpd %xmm0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 15 c1 blendvpd %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 14 01 blendvps %xmm0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 14 c1 blendvps %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 41 01 00 dppd \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 41 c1 00 dppd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 40 01 00 dpps \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 40 c1 00 dpps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 48 0f 3a 17 c1 00 extractps \$0x0,%xmm0,%rcx +[ ]*[0-9a-f]+: 66 0f 3a 17 c1 00 extractps \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 17 01 00 extractps \$0x0,%xmm0,\(%rcx\) +[ ]*[0-9a-f]+: 66 0f 3a 21 c1 00 insertps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 21 01 00 insertps \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2a 01 movntdqa \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 42 01 00 mpsadbw \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 42 c1 00 mpsadbw \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2b 01 packusdw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 2b c1 packusdw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 10 01 pblendvb %xmm0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 10 c1 pblendvb %xmm0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0e 01 00 pblendw \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0e c1 00 pblendw \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 29 c1 pcmpeqq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 29 01 pcmpeqq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 48 0f 3a 14 c1 00 pextrb \$0x0,%xmm0,%rcx +[ ]*[0-9a-f]+: 66 0f 3a 14 c1 00 pextrb \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 14 01 00 pextrb \$0x0,%xmm0,\(%rcx\) +[ ]*[0-9a-f]+: 66 0f 3a 16 c1 00 pextrd \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 16 01 00 pextrd \$0x0,%xmm0,\(%rcx\) +[ ]*[0-9a-f]+: 66 48 0f 3a 16 c1 00 pextrq \$0x0,%xmm0,%rcx +[ ]*[0-9a-f]+: 66 48 0f 3a 16 01 00 pextrq \$0x0,%xmm0,\(%rcx\) +[ ]*[0-9a-f]+: 66 48 0f c5 c8 00 pextrw \$0x0,%xmm0,%rcx +[ ]*[0-9a-f]+: 66 0f c5 c8 00 pextrw \$0x0,%xmm0,%ecx +[ ]*[0-9a-f]+: 66 0f 3a 15 01 00 pextrw \$0x0,%xmm0,\(%rcx\) +[ ]*[0-9a-f]+: 66 0f 38 41 c1 phminposuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 41 01 phminposuw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 20 01 00 pinsrb \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 20 c1 00 pinsrb \$0x0,%ecx,%xmm0 +[ ]*[0-9a-f]+: 66 48 0f 3a 20 c1 00 pinsrb \$0x0,%rcx,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 22 01 00 pinsrd \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 22 c1 00 pinsrd \$0x0,%ecx,%xmm0 +[ ]*[0-9a-f]+: 66 48 0f 3a 22 01 00 pinsrq \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 48 0f 3a 22 c1 00 pinsrq \$0x0,%rcx,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3c c1 pmaxsb %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3c 01 pmaxsb \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3d c1 pmaxsd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3d 01 pmaxsd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3f c1 pmaxud %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3f 01 pmaxud \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3e c1 pmaxuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3e 01 pmaxuw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 38 c1 pminsb %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 38 01 pminsb \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 39 c1 pminsd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 39 01 pminsd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3b c1 pminud %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3b 01 pminud \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3a c1 pminuw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 3a 01 pminuw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 20 c1 pmovsxbw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 20 01 pmovsxbw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 21 c1 pmovsxbd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 21 01 pmovsxbd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 22 c1 pmovsxbq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 22 01 pmovsxbq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 23 c1 pmovsxwd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 23 01 pmovsxwd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 24 c1 pmovsxwq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 24 01 pmovsxwq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 25 c1 pmovsxdq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 25 01 pmovsxdq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 30 c1 pmovzxbw %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 30 01 pmovzxbw \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 31 c1 pmovzxbd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 31 01 pmovzxbd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 32 c1 pmovzxbq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 32 01 pmovzxbq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 33 c1 pmovzxwd %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 33 01 pmovzxwd \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 34 c1 pmovzxwq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 34 01 pmovzxwq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 35 c1 pmovzxdq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 35 01 pmovzxdq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 28 c1 pmuldq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 28 01 pmuldq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 40 c1 pmulld %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 40 01 pmulld \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 17 c1 ptest %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 17 01 ptest \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 09 01 00 roundpd \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 09 c1 00 roundpd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 08 01 00 roundps \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 08 c1 00 roundps \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0b 01 00 roundsd \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0b c1 00 roundsd \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0a 01 00 roundss \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 0a c1 00 roundss \$0x0,%xmm1,%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-sse4_1.s b/gas/testsuite/gas/i386/x86-64-sse4_1.s new file mode 100644 index 000000000000..70c2394833a1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse4_1.s @@ -0,0 +1,107 @@ +# Streaming SIMD extensions 4.1 Instructions + + .text +foo: + blendpd $0x0,(%rcx),%xmm0 + blendpd $0x0,%xmm1,%xmm0 + blendps $0x0,(%rcx),%xmm0 + blendps $0x0,%xmm1,%xmm0 + blendvpd %xmm0,(%rcx),%xmm0 + blendvpd %xmm0,%xmm1,%xmm0 + blendvps %xmm0,(%rcx),%xmm0 + blendvps %xmm0,%xmm1,%xmm0 + dppd $0x0,(%rcx),%xmm0 + dppd $0x0,%xmm1,%xmm0 + dpps $0x0,(%rcx),%xmm0 + dpps $0x0,%xmm1,%xmm0 + extractps $0x0,%xmm0,%rcx + extractps $0x0,%xmm0,%ecx + extractps $0x0,%xmm0,(%rcx) + insertps $0x0,%xmm1,%xmm0 + insertps $0x0,(%rcx),%xmm0 + movntdqa (%rcx),%xmm0 + mpsadbw $0x0,(%rcx),%xmm0 + mpsadbw $0x0,%xmm1,%xmm0 + packusdw (%rcx),%xmm0 + packusdw %xmm1,%xmm0 + pblendvb %xmm0,(%rcx),%xmm0 + pblendvb %xmm0,%xmm1,%xmm0 + pblendw $0x0,(%rcx),%xmm0 + pblendw $0x0,%xmm1,%xmm0 + pcmpeqq %xmm1,%xmm0 + pcmpeqq (%rcx),%xmm0 + pextrb $0x0,%xmm0,%rcx + pextrb $0x0,%xmm0,%ecx + pextrb $0x0,%xmm0,(%rcx) + pextrd $0x0,%xmm0,%ecx + pextrd $0x0,%xmm0,(%rcx) + pextrq $0x0,%xmm0,%rcx + pextrq $0x0,%xmm0,(%rcx) + pextrw $0x0,%xmm0,%rcx + pextrw $0x0,%xmm0,%ecx + pextrw $0x0,%xmm0,(%rcx) + phminposuw %xmm1,%xmm0 + phminposuw (%rcx),%xmm0 + pinsrb $0x0,(%rcx),%xmm0 + pinsrb $0x0,%ecx,%xmm0 + pinsrb $0x0,%rcx,%xmm0 + pinsrd $0x0,(%rcx),%xmm0 + pinsrd $0x0,%ecx,%xmm0 + pinsrq $0x0,(%rcx),%xmm0 + pinsrq $0x0,%rcx,%xmm0 + pmaxsb %xmm1,%xmm0 + pmaxsb (%rcx),%xmm0 + pmaxsd %xmm1,%xmm0 + pmaxsd (%rcx),%xmm0 + pmaxud %xmm1,%xmm0 + pmaxud (%rcx),%xmm0 + pmaxuw %xmm1,%xmm0 + pmaxuw (%rcx),%xmm0 + pminsb %xmm1,%xmm0 + pminsb (%rcx),%xmm0 + pminsd %xmm1,%xmm0 + pminsd (%rcx),%xmm0 + pminud %xmm1,%xmm0 + pminud (%rcx),%xmm0 + pminuw %xmm1,%xmm0 + pminuw (%rcx),%xmm0 + pmovsxbw %xmm1,%xmm0 + pmovsxbw (%rcx),%xmm0 + pmovsxbd %xmm1,%xmm0 + pmovsxbd (%rcx),%xmm0 + pmovsxbq %xmm1,%xmm0 + pmovsxbq (%rcx),%xmm0 + pmovsxwd %xmm1,%xmm0 + pmovsxwd (%rcx),%xmm0 + pmovsxwq %xmm1,%xmm0 + pmovsxwq (%rcx),%xmm0 + pmovsxdq %xmm1,%xmm0 + pmovsxdq (%rcx),%xmm0 + pmovzxbw %xmm1,%xmm0 + pmovzxbw (%rcx),%xmm0 + pmovzxbd %xmm1,%xmm0 + pmovzxbd (%rcx),%xmm0 + pmovzxbq %xmm1,%xmm0 + pmovzxbq (%rcx),%xmm0 + pmovzxwd %xmm1,%xmm0 + pmovzxwd (%rcx),%xmm0 + pmovzxwq %xmm1,%xmm0 + pmovzxwq (%rcx),%xmm0 + pmovzxdq %xmm1,%xmm0 + pmovzxdq (%rcx),%xmm0 + pmuldq %xmm1,%xmm0 + pmuldq (%rcx),%xmm0 + pmulld %xmm1,%xmm0 + pmulld (%rcx),%xmm0 + ptest %xmm1,%xmm0 + ptest (%rcx),%xmm0 + roundpd $0x0,(%rcx),%xmm0 + roundpd $0x0,%xmm1,%xmm0 + roundps $0x0,(%rcx),%xmm0 + roundps $0x0,%xmm1,%xmm0 + roundsd $0x0,(%rcx),%xmm0 + roundsd $0x0,%xmm1,%xmm0 + roundss $0x0,(%rcx),%xmm0 + roundss $0x0,%xmm1,%xmm0 + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.d b/gas/testsuite/gas/i386/x86-64-sse4_2.d new file mode 100644 index 000000000000..379dbb54a1a9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse4_2.d @@ -0,0 +1,45 @@ +#objdump: -dw +#name: x86-64 SSE4.2 + +.*: file format .* + +Disassembly of section .text: + +0+000 <foo>: +[ ]*[0-9a-f]+: f2 0f 38 f0 d9 crc32b %cl,%ebx +[ ]*[0-9a-f]+: f2 48 0f 38 f0 d9 crc32b %cl,%rbx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 d9 crc32w %cx,%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[0-9a-f]+: f2 48 0f 38 f1 d9 crc32q %rcx,%rbx +[ ]*[0-9a-f]+: f2 0f 38 f0 19 crc32b \(%rcx\),%ebx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 19 crc32w \(%rcx\),%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 19 crc32l \(%rcx\),%ebx +[ ]*[0-9a-f]+: f2 48 0f 38 f1 19 crc32q \(%rcx\),%rbx +[ ]*[0-9a-f]+: f2 0f 38 f0 d9 crc32b %cl,%ebx +[ ]*[0-9a-f]+: f2 48 0f 38 f0 d9 crc32b %cl,%rbx +[ ]*[0-9a-f]+: 66 f2 0f 38 f1 d9 crc32w %cx,%ebx +[ ]*[0-9a-f]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[0-9a-f]+: f2 48 0f 38 f1 d9 crc32q %rcx,%rbx +[ ]*[0-9a-f]+: 66 0f 38 37 01 pcmpgtq \(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 38 37 c1 pcmpgtq %xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 61 01 00 pcmpestri \$0x0,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 61 c1 00 pcmpestri \$0x0,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 60 01 01 pcmpestrm \$0x1,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 60 c1 01 pcmpestrm \$0x1,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 63 01 02 pcmpistri \$0x2,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 63 c1 02 pcmpistri \$0x2,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 62 01 03 pcmpistrm \$0x3,\(%rcx\),%xmm0 +[ ]*[0-9a-f]+: 66 0f 3a 62 c1 03 pcmpistrm \$0x3,%xmm1,%xmm0 +[ ]*[0-9a-f]+: 66 f3 0f b8 19 popcnt \(%rcx\),%bx +[ ]*[0-9a-f]+: f3 0f b8 19 popcnt \(%rcx\),%ebx +[ ]*[0-9a-f]+: f3 48 0f b8 19 popcnt \(%rcx\),%rbx +[ ]*[0-9a-f]+: 66 f3 0f b8 19 popcnt \(%rcx\),%bx +[ ]*[0-9a-f]+: f3 0f b8 19 popcnt \(%rcx\),%ebx +[ ]*[0-9a-f]+: f3 48 0f b8 19 popcnt \(%rcx\),%rbx +[ ]*[0-9a-f]+: 66 f3 0f b8 d9 popcnt %cx,%bx +[ ]*[0-9a-f]+: f3 0f b8 d9 popcnt %ecx,%ebx +[ ]*[0-9a-f]+: f3 48 0f b8 d9 popcnt %rcx,%rbx +[ ]*[0-9a-f]+: 66 f3 0f b8 d9 popcnt %cx,%bx +[ ]*[0-9a-f]+: f3 0f b8 d9 popcnt %ecx,%ebx +[ ]*[0-9a-f]+: f3 48 0f b8 d9 popcnt %rcx,%rbx +#pass diff --git a/gas/testsuite/gas/i386/x86-64-sse4_2.s b/gas/testsuite/gas/i386/x86-64-sse4_2.s new file mode 100644 index 000000000000..9d59b10aab8e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse4_2.s @@ -0,0 +1,42 @@ +# Streaming SIMD extensions 4.2 Instructions + + .text +foo: + crc32 %cl,%ebx + crc32 %cl,%rbx + crc32 %cx,%ebx + crc32 %ecx,%ebx + crc32 %rcx,%rbx + crc32b (%rcx),%ebx + crc32w (%rcx),%ebx + crc32l (%rcx),%ebx + crc32q (%rcx),%rbx + crc32b %cl,%ebx + crc32b %cl,%rbx + crc32w %cx,%ebx + crc32l %ecx,%ebx + crc32q %rcx,%rbx + pcmpgtq (%rcx),%xmm0 + pcmpgtq %xmm1,%xmm0 + pcmpestri $0x0,(%rcx),%xmm0 + pcmpestri $0x0,%xmm1,%xmm0 + pcmpestrm $0x1,(%rcx),%xmm0 + pcmpestrm $0x1,%xmm1,%xmm0 + pcmpistri $0x2,(%rcx),%xmm0 + pcmpistri $0x2,%xmm1,%xmm0 + pcmpistrm $0x3,(%rcx),%xmm0 + pcmpistrm $0x3,%xmm1,%xmm0 + popcnt (%rcx),%bx + popcnt (%rcx),%ebx + popcnt (%rcx),%rbx + popcntw (%rcx),%bx + popcntl (%rcx),%ebx + popcntq (%rcx),%rbx + popcnt %cx,%bx + popcnt %ecx,%ebx + popcnt %rcx,%rbx + popcntw %cx,%bx + popcntl %ecx,%ebx + popcntq %rcx,%rbx + + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-stack-intel.d b/gas/testsuite/gas/i386/x86-64-stack-intel.d index 0dfab4d3fbe8..aaeff2ffcb39 100644 --- a/gas/testsuite/gas/i386/x86-64-stack-intel.d +++ b/gas/testsuite/gas/i386/x86-64-stack-intel.d @@ -2,7 +2,7 @@ #name: x86-64 stack-related opcodes (Intel mode) #source: x86-64-stack.s -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/x86-64-stack-suffix.d index c5d789d8a71d..75fd900feae1 100644 --- a/gas/testsuite/gas/i386/x86-64-stack-suffix.d +++ b/gas/testsuite/gas/i386/x86-64-stack-suffix.d @@ -2,7 +2,7 @@ #name: x86-64 stack-related opcodes (with suffixes) #source: x86-64-stack.s -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86-64-stack.d b/gas/testsuite/gas/i386/x86-64-stack.d index fa010a981a12..f686a04fee88 100644 --- a/gas/testsuite/gas/i386/x86-64-stack.d +++ b/gas/testsuite/gas/i386/x86-64-stack.d @@ -1,7 +1,7 @@ #objdump: -dw #name: x86-64 stack-related opcodes -.*: +file format elf64-x86-64 +.*: +file format .* Disassembly of section .text: diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d index 60452a512735..a5bf0fdacc51 100644 --- a/gas/testsuite/gas/i386/x86_64.d +++ b/gas/testsuite/gas/i386/x86_64.d @@ -6,7 +6,7 @@ Disassembly of section .text: -0+ <bar-0x1a7>: +0+ <.*>: [ ]+0: 01 ca[ ]+add[ ]+%ecx,%edx [ ]+2: 44 01 ca[ ]+add[ ]+%r9d,%edx [ ]+5: 41 01 ca[ ]+add[ ]+%ecx,%r10d @@ -38,7 +38,7 @@ Disassembly of section .text: [ ]+5a: 44 0f 20 c0[ ]+mov[ ]+%cr8,%rax [ ]+5e: 44 0f 22 c0[ ]+mov[ ]+%rax,%cr8 [ ]+62: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\) -[ ]+65: f3 66 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) +[ ]+65: 66 f3 a5[ ]+rep movsw %ds:\(%rsi\),%es:\(%rdi\) [ ]+68: f3 48 a5[ ]+rep movsq %ds:\(%rsi\),%es:\(%rdi\) [ ]+6b: b0 11[ ]+mov[ ]+\$0x11,%al [ ]+6d: b4 11[ ]+mov[ ]+\$0x11,%ah @@ -52,7 +52,7 @@ Disassembly of section .text: [ ]+96: 41 03 00[ ]+add[ ]+\(%r8\),%eax [ ]+99: 45 03 00[ ]+add[ ]+\(%r8\),%r8d [ ]+9c: 49 03 00[ ]+add[ ]+\(%r8\),%rax -[ ]+9f: 03 05 22 22 22 22[ ]+add[ ]+572662306\(%rip\),%eax.* +[ ]+9f: 03 05 22 22 22 22[ ]+add[ ]+0x22222222\(%rip\),%eax.* [ ]+a5: 03 45 00[ ]+add[ ]+0x0\(%rbp\),%eax [ ]+a8: 03 04 25 22 22 22 22 add[ ]+0x22222222,%eax [ ]+af: 41 03 45 00[ ]+add[ ]+0x0\(%r13\),%eax @@ -84,10 +84,10 @@ Disassembly of section .text: 10b: 83 04 81 11[ ]+addl[ ]+\$0x11,\(%rcx,%rax,4\) 10f: 41 83 04 81 11[ ]+addl[ ]+\$0x11,\(%r9,%rax,4\) 114: 42 83 04 81 11[ ]+addl[ ]+\$0x11,\(%rcx,%r8,4\) - 119: 83 05 22 22 22 22 33 addl[ ]+\$0x33,572662306\(%rip\).* - 120: 48 83 05 22 22 22 22 33 addq[ ]+\$0x33,572662306\(%rip\).* - 128: 81 05 22 22 22 22 33 33 33 33 addl[ ]+\$0x33333333,572662306\(%rip\).* - 132: 48 81 05 22 22 22 22 33 33 33 33 addq[ ]+\$0x33333333,572662306\(%rip\).* + 119: 83 05 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rip\).* + 120: 48 83 05 22 22 22 22 33 addq[ ]+\$0x33,0x22222222\(%rip\).* + 128: 81 05 22 22 22 22 33 33 33 33 addl[ ]+\$0x33333333,0x22222222\(%rip\).* + 132: 48 81 05 22 22 22 22 33 33 33 33 addq[ ]+\$0x33333333,0x22222222\(%rip\).* 13d: 83 04 c5 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(,%rax,8\) 145: 83 80 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rax\) 14c: 83 80 22 22 22 22 33 addl[ ]+\$0x33,0x22222222\(%rax\) @@ -113,7 +113,7 @@ Disassembly of section .text: 1b9: a1 00 00 00 00 00 00 00 00 mov[ ]+0x0,%eax 1c2: 8b 04 25 00 00 00 00 mov[ ]+0x0,%eax 1c9: 8b 80 00 00 00 00[ ]+mov[ ]+0x0\(%rax\),%eax - 1cf: 8b 05 00 00 00 00[ ]+mov[ ]+0\(%rip\),%eax.* + 1cf: 8b 05 00 00 00 00[ ]+mov[ ]+0x0\(%rip\),%eax.* 1d5: b0 00[ ]+mov[ ]+\$0x0,%al 1d7: 66 b8 00 00[ ]+mov[ ]+\$0x0,%ax 1db: b8 00 00 00 00[ ]+mov[ ]+\$0x0,%eax @@ -121,7 +121,7 @@ Disassembly of section .text: 1e7: a1 00 00 00 00 00 00 00 00 mov[ ]+0x0,%eax 1f0: 8b 04 25 00 00 00 00 mov[ ]+0x0,%eax 1f7: 8b 80 00 00 00 00[ ]+mov[ ]+0x0\(%rax\),%eax - 1fd: 8b 05 00 00 00 00[ ]+mov[ ]+0\(%rip\),%eax.* + 1fd: 8b 05 00 00 00 00[ ]+mov[ ]+0x0\(%rip\),%eax.* 0+203 <foo>: 203: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al @@ -156,4 +156,6 @@ Disassembly of section .text: 2fc: 66 89 04 25 11 22 33 ff mov[ ]+%ax,0xffffffffff332211 304: 89 04 25 11 22 33 ff mov[ ]+%eax,0xffffffffff332211 30b: 48 89 04 25 11 22 33 ff mov[ ]+%rax,0xffffffffff332211 + 313: 48 0f c7 08[ ]+cmpxchg16b \(%rax\) + 317: 48 0f c7 08[ ]+cmpxchg16b \(%rax\) #pass diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s index 3e5532ab297b..aad9b2737754 100644 --- a/gas/testsuite/gas/i386/x86_64.s +++ b/gas/testsuite/gas/i386/x86_64.s @@ -188,5 +188,10 @@ movw %ax,0xffffffffff332211 movl %eax,0xffffffffff332211 movq %rax,0xffffffffff332211 +cmpxchg16b (%rax) + +.intel_syntax noprefix +cmpxchg16b oword ptr [rax] + # Get a good alignment. .p2align 4,0 diff --git a/gas/testsuite/gas/i860/i860.exp b/gas/testsuite/gas/i860/i860.exp index 041d859cc92a..39e40af26fd8 100644 --- a/gas/testsuite/gas/i860/i860.exp +++ b/gas/testsuite/gas/i860/i860.exp @@ -1,18 +1,5 @@ # i860 assembler testsuite. -proc run_list_test { name opts } { - global srcdir subdir - set testname "i860 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if [istarget i860-*-*] { run_dump_test "bitwise" run_dump_test "branch" diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp index f68c107f528b..3dfd10b8c343 100644 --- a/gas/testsuite/gas/ia64/ia64.exp +++ b/gas/testsuite/gas/ia64/ia64.exp @@ -1,19 +1,6 @@ # # ia64 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "ia64 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if [istarget "ia64-*"] then { run_dump_test "regs" diff --git a/gas/testsuite/gas/lns/lns-common-1-alt.d b/gas/testsuite/gas/lns/lns-common-1-alt.d new file mode 100644 index 000000000000..f76e8528ce35 --- /dev/null +++ b/gas/testsuite/gas/lns/lns-common-1-alt.d @@ -0,0 +1,39 @@ +#source: lns-common-1.s +#readelf: -wl +#name: lns-common-1 +Dump of debug contents of section \.debug_line: +#... + Initial value of 'is_stmt': 1 +#... + Line Number Statements: + Extended opcode 2: set Address to .* + Copy + Set column to 3 + Advance Line by 1 to 2 + Advance PC by fixed size amount .* to .* + Copy + Set prologue_end to true + Advance Line by 1 to 3 + Advance PC by fixed size amount .* to .* + Copy + Set column to 0 + Set epilogue_begin to true + Advance Line by 1 to 4 + Advance PC by fixed size amount .* to .* + Copy + Set ISA to 1 + Set basic block + Advance Line by 1 to 5 + Advance PC by fixed size amount .* to .* + Copy + Set is_stmt to 0 + Advance Line by 1 to 6 + Advance PC by fixed size amount .* to .* + Copy + Set is_stmt to 1 + Advance Line by 1 to 7 + Advance PC by fixed size amount .* to .* + Copy + Advance PC by fixed size amount .* to .* + Extended opcode 1: End of Sequence +#... diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp index 1bc95990e3ea..2373290e8425 100644 --- a/gas/testsuite/gas/lns/lns.exp +++ b/gas/testsuite/gas/lns/lns.exp @@ -1,17 +1,3 @@ -# ??? This probably shouldn't be replicated here... -proc run_list_test { name opts } { - global srcdir subdir - set testname "lns $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if ![is_elf_format] then { return } @@ -21,7 +7,21 @@ run_list_test "lns-diag-1" "" # ??? Won't work on targets that don't have a bare "nop" insn. # Perhaps we could arrange for an include file or something that # defined a macro... -if { ![istarget ia64*-*-*] && ![istarget i370-*-*] && ![istarget i960-*-*] - && ![istarget or32-*-*] && ![istarget s390*-*-*] } { - run_dump_test "lns-common-1" +# Nor does it work on targets that do not generate line number +# information (d10v). +if { + ![istarget d10v-*-*] + && ![istarget ia64*-*-*] + && ![istarget i370-*-*] + && ![istarget i960-*-*] + && ![istarget mcore-*-*] + && ![istarget or32-*-*] + && ![istarget s390*-*-*] +} { + # Use alternate file for targets using DW_LNS_fixed_advance_pc opcodes. + if { [istarget xtensa-*-*] } { + run_dump_test "lns-common-1-alt" + } else { + run_dump_test "lns-common-1" + } } diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp index 9516b1ab1dfc..ae9f993b7e41 100644 --- a/gas/testsuite/gas/m68k/all.exp +++ b/gas/testsuite/gas/m68k/all.exp @@ -13,7 +13,7 @@ if [istarget "m6811-*-*"] then { if [istarget "m6812-*-*"] then { return } -if [istarget m68*-*-*] then { +if { [istarget m68*-*-*] || [istarget fido*-*-*] } then { gas_test "t2.s" "" "" "cross-section branch" if [istarget m68*-motorola-sysv] then { run_dump_test t2 @@ -29,17 +29,48 @@ if [istarget m68*-*-*] then { setup_xfail "*-*" clear_xfail "*-*-*elf*" "*-*-sysv4*" "*-*-rtems" "*-*-*gnu*" "*-*-psos*" run_dump_test pcrel - run_dump_test operands - run_dump_test cas - run_dump_test bitfield + + # Since fido is basically CPU32, it does not support those + # instructions beyond CPU32. Disable those tests that test them. + if ![istarget fido-*-*] then { + run_dump_test operands + run_dump_test cas + run_dump_test bitfield + } else { + # Test fido-specific instructions. + run_dump_test fido + } + run_dump_test link - run_dump_test fmoveml + + # fido does not have a floating point unit. + if ![istarget fido-*-*] then { + run_dump_test fmoveml + } + run_dump_test mcf-mov3q run_dump_test mode5 run_dump_test mcf-mac run_dump_test mcf-emac + run_dump_test mcf-coproc run_dump_test mcf-fpu - run_dump_test arch-cpu-1 + run_dump_test mcf-trap + run_dump_test mcf-wdebug + if { [istarget *-*-elf] || [istarget *-*-linux*] } then { + run_dump_test arch-cpu-1 + } + run_dump_test cpu32 + + run_dump_test br-isaa + run_dump_test br-isab + run_dump_test br-isac + + run_dump_test ctrl-1 + run_dump_test ctrl-2 + + if { [istarget *-*-netbsd] } then { + run_dump_test p3041 + } set testname "68000 operands" gas_run "operands.s" "-m68000" "2>err.out" diff --git a/gas/testsuite/gas/m68k/br-isaa.d b/gas/testsuite/gas/m68k/br-isaa.d new file mode 100644 index 000000000000..0b49dc2ea237 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isaa.d @@ -0,0 +1,15 @@ +#name: br-isaa.d +#objdump: -d +#as: -march=isaa -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: + 0: 4e71 nop + 2: 60fc bras 0 <foo> + 4: 6000 0000 braw 6 <foo\+0x6> + 8: 61f6 bsrs 0 <foo> + a: 6100 0000 bsrw c <foo\+0xc> + e: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isaa.s b/gas/testsuite/gas/m68k/br-isaa.s new file mode 100644 index 000000000000..d405338c9a24 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isaa.s @@ -0,0 +1,6 @@ +foo: nop + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/gas/testsuite/gas/m68k/br-isab.d b/gas/testsuite/gas/m68k/br-isab.d new file mode 100644 index 000000000000..20e093f734d3 --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isab.d @@ -0,0 +1,16 @@ +#name: br-isab.d +#objdump: -d +#as: -march=isab -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: + 0: 4e71 nop + 2: 61ff ffff fffc bsrl 0 <foo> + 8: 60f6 bras 0 <foo> + a: 60ff 0000 0000 bral c <foo\+0xc> + 10: 61ee bsrs 0 <foo> + 12: 61ff 0000 0000 bsrl 14 <foo\+0x14> + 18: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isab.s b/gas/testsuite/gas/m68k/br-isab.s new file mode 100644 index 000000000000..5db3c076ee5f --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isab.s @@ -0,0 +1,7 @@ +foo: nop + bsr.l foo + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/gas/testsuite/gas/m68k/br-isac.d b/gas/testsuite/gas/m68k/br-isac.d new file mode 100644 index 000000000000..126ff464bb8b --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isac.d @@ -0,0 +1,16 @@ +#name: br-isac.d +#objdump: -d +#as: -march=isac -pcrel + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: + 0: 4e71 nop + 2: 61ff ffff fffc bsrl 0 <foo> + 8: 60f6 bras 0 <foo> + a: 6000 0000 braw c <foo\+0xc> + e: 61f0 bsrs 0 <foo> + 10: 61ff 0000 0000 bsrl 12 <foo\+0x12> + 16: 4e71 nop diff --git a/gas/testsuite/gas/m68k/br-isac.s b/gas/testsuite/gas/m68k/br-isac.s new file mode 100644 index 000000000000..5db3c076ee5f --- /dev/null +++ b/gas/testsuite/gas/m68k/br-isac.s @@ -0,0 +1,7 @@ +foo: nop + bsr.l foo + jbra foo + jbra bar + jbsr foo + jbsr bar + nop diff --git a/gas/testsuite/gas/m68k/cpu32.d b/gas/testsuite/gas/m68k/cpu32.d new file mode 100644 index 000000000000..e7054a394733 --- /dev/null +++ b/gas/testsuite/gas/m68k/cpu32.d @@ -0,0 +1,35 @@ +#name: cpu32 +#objdump: -d +#as: -mcpu32 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ 0-9a-f]+: 4afa bgnd +[ 0-9a-f]+: f800 2001 tblub %d0,%d1,%d2 +[ 0-9a-f]+: f800 2041 tbluw %d0,%d1,%d2 +[ 0-9a-f]+: f800 2081 tblul %d0,%d1,%d2 +[ 0-9a-f]+: f800 2401 tblunb %d0,%d1,%d2 +[ 0-9a-f]+: f800 2441 tblunw %d0,%d1,%d2 +[ 0-9a-f]+: f800 2481 tblunl %d0,%d1,%d2 +[ 0-9a-f]+: f800 2801 tblsb %d0,%d1,%d2 +[ 0-9a-f]+: f800 2841 tblsw %d0,%d1,%d2 +[ 0-9a-f]+: f800 2881 tblsl %d0,%d1,%d2 +[ 0-9a-f]+: f800 2c01 tblsnb %d0,%d1,%d2 +[ 0-9a-f]+: f800 2c41 tblsnw %d0,%d1,%d2 +[ 0-9a-f]+: f800 2c81 tblsnl %d0,%d1,%d2 +[ 0-9a-f]+: f810 1100 tblub %a0@,%d1 +[ 0-9a-f]+: f810 1140 tbluw %a0@,%d1 +[ 0-9a-f]+: f810 1180 tblul %a0@,%d1 +[ 0-9a-f]+: f810 1500 tblunb %a0@,%d1 +[ 0-9a-f]+: f810 1540 tblunw %a0@,%d1 +[ 0-9a-f]+: f810 1580 tblunl %a0@,%d1 +[ 0-9a-f]+: f810 1900 tblsb %a0@,%d1 +[ 0-9a-f]+: f810 1940 tblsw %a0@,%d1 +[ 0-9a-f]+: f810 1980 tblsl %a0@,%d1 +[ 0-9a-f]+: f810 1d00 tblsnb %a0@,%d1 +[ 0-9a-f]+: f810 1d40 tblsnw %a0@,%d1 +[ 0-9a-f]+: f810 1d80 tblsnl %a0@,%d1 +#... diff --git a/gas/testsuite/gas/m68k/cpu32.s b/gas/testsuite/gas/m68k/cpu32.s new file mode 100644 index 000000000000..589e7e305672 --- /dev/null +++ b/gas/testsuite/gas/m68k/cpu32.s @@ -0,0 +1,26 @@ + # cpu32 specific insns + bgnd + tblub %d0,%d1,%d2 + tbluw %d0,%d1,%d2 + tblul %d0,%d1,%d2 + tblunb %d0,%d1,%d2 + tblunw %d0,%d1,%d2 + tblunl %d0,%d1,%d2 + tblsb %d0,%d1,%d2 + tblsw %d0,%d1,%d2 + tblsl %d0,%d1,%d2 + tblsnb %d0,%d1,%d2 + tblsnw %d0,%d1,%d2 + tblsnl %d0,%d1,%d2 + tblub (%a0),%d1 + tbluw (%a0),%d1 + tblul (%a0),%d1 + tblunb (%a0),%d1 + tblunw (%a0),%d1 + tblunl (%a0),%d1 + tblsb (%a0),%d1 + tblsw (%a0),%d1 + tblsl (%a0),%d1 + tblsnb (%a0),%d1 + tblsnw (%a0),%d1 + tblsnl (%a0),%d1 diff --git a/gas/testsuite/gas/m68k/ctrl-1.d b/gas/testsuite/gas/m68k/ctrl-1.d new file mode 100644 index 000000000000..d4347281b4bf --- /dev/null +++ b/gas/testsuite/gas/m68k/ctrl-1.d @@ -0,0 +1,12 @@ +#name: ctrl-1.d +#objdump: -d +#as: -mcpu=5307 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: + 0: 4e7b 0c04 movec %d0,%rambar0 + 4: 4e7b 0c04 movec %d0,%rambar0 + diff --git a/gas/testsuite/gas/m68k/ctrl-1.s b/gas/testsuite/gas/m68k/ctrl-1.s new file mode 100644 index 000000000000..cac82d93cb42 --- /dev/null +++ b/gas/testsuite/gas/m68k/ctrl-1.s @@ -0,0 +1,2 @@ + movec %d0,%rambar + movec %d0,%rambar0 diff --git a/gas/testsuite/gas/m68k/ctrl-2.d b/gas/testsuite/gas/m68k/ctrl-2.d new file mode 100644 index 000000000000..00b8aa3b7f8e --- /dev/null +++ b/gas/testsuite/gas/m68k/ctrl-2.d @@ -0,0 +1,11 @@ +#name: ctrl-2.d +#objdump: -d +#as: -mcpu=5208 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: + 0: 4e7b 0c05 movec %d0,%rambar1 + 4: 4e7b 0c05 movec %d0,%rambar1 diff --git a/gas/testsuite/gas/m68k/ctrl-2.s b/gas/testsuite/gas/m68k/ctrl-2.s new file mode 100644 index 000000000000..3a36db0bb89c --- /dev/null +++ b/gas/testsuite/gas/m68k/ctrl-2.s @@ -0,0 +1,2 @@ + movec %d0,%rambar + movec %d0,%rambar1 diff --git a/gas/testsuite/gas/m68k/fido.d b/gas/testsuite/gas/m68k/fido.d new file mode 100644 index 000000000000..fff5abbef38a --- /dev/null +++ b/gas/testsuite/gas/m68k/fido.d @@ -0,0 +1,41 @@ +#objdump: -d --prefix-addresses +#name: fido + +# Test parsing of the operands of the fido-specific instructions. + +.*: +file format .* + +Disassembly of section .text: +0+000 <foo> sleep +0+002 <foo\+(0x|)2> trapx #0 +0+004 <foo\+(0x|)4> trapx #1 +0+006 <foo\+(0x|)6> trapx #2 +0+008 <foo\+(0x|)8> trapx #3 +0+00a <foo\+(0x|)a> trapx #4 +0+00c <foo\+(0x|)c> trapx #5 +0+00e <foo\+(0x|)e> trapx #6 +0+010 <foo\+(0x|)10> trapx #7 +0+012 <foo\+(0x|)12> trapx #8 +0+014 <foo\+(0x|)14> trapx #9 +0+016 <foo\+(0x|)16> trapx #10 +0+018 <foo\+(0x|)18> trapx #11 +0+01a <foo\+(0x|)1a> trapx #12 +0+01c <foo\+(0x|)1c> trapx #13 +0+01e <foo\+(0x|)1e> trapx #14 +0+020 <foo\+(0x|)20> trapx #15 +0+022 <foo\+(0x|)22> movec %cac,%d0 +0+026 <foo\+(0x|)26> movec %cac,%a0 +0+02a <foo\+(0x|)2a> movec %mbb,%d1 +0+02e <foo\+(0x|)2e> movec %mbb,%a1 +0+032 <foo\+(0x|)32> movec %d2,%cac +0+036 <foo\+(0x|)36> movec %a2,%cac +0+03a <foo\+(0x|)3a> movec %d3,%mbb +0+03e <foo\+(0x|)3e> movec %a3,%mbb +0+042 <foo\+(0x|)42> movec %cac,%d4 +0+046 <foo\+(0x|)46> movec %cac,%a4 +0+04a <foo\+(0x|)4a> movec %mbb,%d5 +0+04e <foo\+(0x|)4e> movec %mbb,%a5 +0+052 <foo\+(0x|)52> movec %d6,%cac +0+056 <foo\+(0x|)56> movec %fp,%cac +0+05a <foo\+(0x|)5a> movec %d7,%mbb +0+05e <foo\+(0x|)5e> movec %sp,%mbb diff --git a/gas/testsuite/gas/m68k/fido.s b/gas/testsuite/gas/m68k/fido.s new file mode 100644 index 000000000000..8aaac7c54736 --- /dev/null +++ b/gas/testsuite/gas/m68k/fido.s @@ -0,0 +1,37 @@ +# Test parsing of the operands of the fido-specific instructions. + .text + .globl foo +foo: + sleep + trapx #0 + trapx #1 + trapx #2 + trapx #3 + trapx #4 + trapx #5 + trapx #6 + trapx #7 + trapx #8 + trapx #9 + trapx #10 + trapx #11 + trapx #12 + trapx #13 + trapx #14 + trapx #15 + movec #0xffe,%d0 + movec #0xffe,%a0 + movec #0xfff,%d1 + movec #0xfff,%a1 + movec %d2,#0xffe + movec %a2,#0xffe + movec %d3,#0xfff + movec %a3,#0xfff + movec %cac,%d4 + movec %cac,%a4 + movec %mbb,%d5 + movec %mbb,%a5 + movec %d6,%cac + movec %a6,%cac + movec %d7,%mbb + movec %a7,%mbb diff --git a/gas/testsuite/gas/m68k/mcf-coproc.d b/gas/testsuite/gas/m68k/mcf-coproc.d new file mode 100644 index 000000000000..86401cbbcbda --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-coproc.d @@ -0,0 +1,50 @@ +#objdump: -d +#as: -mcpu=5475 + +.*: file format .* + +Disassembly of section .text: + +0+ <start>: +[ 0-9a-f]+: fcc0 0050 cp0bcbusy [0-9a-f]+ <zero> +[ 0-9a-f]+: fc80 2123 cp0ldl %d0,%d2,#1,#291 +[ 0-9a-f]+: fc88 a201 cp0ldl %a0,%a2,#2,#1 +[ 0-9a-f]+: fc50 a401 cp0ldw %a0@,%a2,#3,#1 +[ 0-9a-f]+: fc18 aa01 cp0ldb %a0@\+,%a2,#6,#1 +[ 0-9a-f]+: fca0 ac01 cp0ldl %a0@-,%a2,#7,#1 +[ 0-9a-f]+: fca8 ae01 0010 cp0ldl %a0@\(16\),%a2,#8,#1 +[ 0-9a-f]+: fd80 2123 cp0stl %d2,%d0,#1,#291 +[ 0-9a-f]+: fd88 a201 cp0stl %a2,%a0,#2,#1 +[ 0-9a-f]+: fd50 a401 cp0stw %a2,%a0@,#3,#1 +[ 0-9a-f]+: fd18 aa01 cp0stb %a2,%a0@\+,#6,#1 +[ 0-9a-f]+: fda0 ac01 cp0stl %a2,%a0@-,#7,#1 +[ 0-9a-f]+: fda8 ae01 0010 cp0stl %a2,%a0@\(16\),#8,#1 +[ 0-9a-f]+: fc00 0e00 cp0nop #8 +[ 0-9a-f]+: fc80 0400 cp0nop #3 +[ 0-9a-f]+: fc80 1400 cp0ldl %d0,%d1,#3,#0 +[ 0-9a-f]+: fc88 0400 cp0ldl %a0,%d0,#3,#0 +[ 0-9a-f]+: fc90 0400 cp0ldl %a0@,%d0,#3,#0 +[ 0-9a-f]+: fca8 0400 0010 cp0ldl %a0@\(16\),%d0,#3,#0 +[ 0-9a-f]+ <zero>: +[ 0-9a-f]+: 4e71 nop +[ 0-9a-f]+: fec0 0050 cp1bcbusy [0-9a-f]+ <one> +[ 0-9a-f]+: fe80 2123 cp1ldl %d0,%d2,#1,#291 +[ 0-9a-f]+: fe88 a201 cp1ldl %a0,%a2,#2,#1 +[ 0-9a-f]+: fe50 a401 cp1ldw %a0@,%a2,#3,#1 +[ 0-9a-f]+: fe18 aa01 cp1ldb %a0@\+,%a2,#6,#1 +[ 0-9a-f]+: fea0 ac01 cp1ldl %a0@-,%a2,#7,#1 +[ 0-9a-f]+: fea8 ae01 0010 cp1ldl %a0@\(16\),%a2,#8,#1 +[ 0-9a-f]+: ff80 2123 cp1stl %d2,%d0,#1,#291 +[ 0-9a-f]+: ff88 a201 cp1stl %a2,%a0,#2,#1 +[ 0-9a-f]+: ff50 a401 cp1stw %a2,%a0@,#3,#1 +[ 0-9a-f]+: ff18 aa01 cp1stb %a2,%a0@\+,#6,#1 +[ 0-9a-f]+: ffa0 ac01 cp1stl %a2,%a0@-,#7,#1 +[ 0-9a-f]+: ffa8 ae01 0010 cp1stl %a2,%a0@\(16\),#8,#1 +[ 0-9a-f]+: fe00 0e00 cp1nop #8 +[ 0-9a-f]+: fe80 0400 cp1nop #3 +[ 0-9a-f]+: fe80 1400 cp1ldl %d0,%d1,#3,#0 +[ 0-9a-f]+: fe88 0400 cp1ldl %a0,%d0,#3,#0 +[ 0-9a-f]+: fe90 0400 cp1ldl %a0@,%d0,#3,#0 +[ 0-9a-f]+: fea8 0400 0010 cp1ldl %a0@\(16\),%d0,#3,#0 +[ 0-9a-f]+ <one>: +[ 0-9a-f]+: 4e71 nop diff --git a/gas/testsuite/gas/m68k/mcf-coproc.s b/gas/testsuite/gas/m68k/mcf-coproc.s new file mode 100644 index 000000000000..6173d6ac847f --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-coproc.s @@ -0,0 +1,47 @@ + +start: + cp0bcbusy zero + cp0ld %d0,%d2,#1,#0x123 + cp0ldl %a0,%a2,#2,#0x1 + cp0ldw (%a0),%a2,#3,#0x1 + cp0ldb (%a0)+,%a2,#6,#0x1 + cp0ldl -(%a0),%a2,#7,#0x1 + cp0ldl 16(%a0),%a2,#8,#0x1 + + cp0st %d2,%d0,#1,#0x123 + cp0stl %a2,%a0,#2,#0x1 + cp0stw %a2,(%a0),#3,#0x1 + cp0stb %a2,(%a0)+,#6,#0x1 + cp0stl %a2,-(%a0),#7,#0x1 + cp0stl %a2,16(%a0),#8,#0x1 + + cp0nop #8 + cp0ld %d0,%d0,#3,#0 + cp0ld %d0,%d1,#3,#0 + cp0ld %a0,%d0,#3,#0 + cp0ld (%a0),%d0,#3,#0 + cp0ld 16(%a0),%d0,#3,#0 +zero: nop + + cp1bcbusy one + cp1ld %d0,%d2,#1,#0x123 + cp1ldl %a0,%a2,#2,#0x1 + cp1ldw (%a0),%a2,#3,#0x1 + cp1ldb (%a0)+,%a2,#6,#0x1 + cp1ldl -(%a0),%a2,#7,#0x1 + cp1ldl 16(%a0),%a2,#8,#0x1 + + cp1st %d2,%d0,#1,#0x123 + cp1stl %a2,%a0,#2,#0x1 + cp1stw %a2,(%a0),#3,#0x1 + cp1stb %a2,(%a0)+,#6,#0x1 + cp1stl %a2,-(%a0),#7,#0x1 + cp1stl %a2,16(%a0),#8,#0x1 + + cp1nop #8 + cp1ld %d0,%d0,#3,#0 + cp1ld %d0,%d1,#3,#0 + cp1ld %a0,%d0,#3,#0 + cp1ld (%a0),%d0,#3,#0 + cp1ld 16(%a0),%d0,#3,#0 +one: nop diff --git a/gas/testsuite/gas/m68k/mcf-fpu.d b/gas/testsuite/gas/m68k/mcf-fpu.d index 5167b08dff0d..f285fd235166 100644 --- a/gas/testsuite/gas/m68k/mcf-fpu.d +++ b/gas/testsuite/gas/m68k/mcf-fpu.d @@ -7,167 +7,815 @@ Disassembly of section .text: 0+ <.text>: [ 0-9a-f]+: f200 0004 fsqrtd %fp0,%fp0 +[ 0-9a-f]+: f205 4004 fsqrtl %d5,%fp0 +[ 0-9a-f]+: f214 4004 fsqrtl %a4@,%fp0 +[ 0-9a-f]+: f21b 4004 fsqrtl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4004 fsqrtl %a2@-,%fp0 [ 0-9a-f]+: f22e 4004 0008 fsqrtl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4004 1234 fsqrtl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4404 fsqrts %d5,%fp0 +[ 0-9a-f]+: f214 4404 fsqrts %a4@,%fp0 +[ 0-9a-f]+: f21b 4404 fsqrts %a3@\+,%fp0 +[ 0-9a-f]+: f222 4404 fsqrts %a2@-,%fp0 [ 0-9a-f]+: f22e 4404 0008 fsqrts %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4404 1234 fsqrts %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5004 fsqrtw %d5,%fp0 +[ 0-9a-f]+: f214 5004 fsqrtw %a4@,%fp0 +[ 0-9a-f]+: f21b 5004 fsqrtw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5004 fsqrtw %a2@-,%fp0 [ 0-9a-f]+: f22e 5004 0008 fsqrtw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5004 1234 fsqrtw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5404 fsqrtd %a4@,%fp0 +[ 0-9a-f]+: f21b 5404 fsqrtd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5404 fsqrtd %a2@-,%fp0 [ 0-9a-f]+: f22e 5404 0008 fsqrtd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5404 1234 fsqrtd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5804 fsqrtb %d5,%fp0 +[ 0-9a-f]+: f214 5804 fsqrtb %a4@,%fp0 +[ 0-9a-f]+: f21b 5804 fsqrtb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5804 fsqrtb %a2@-,%fp0 [ 0-9a-f]+: f22e 5804 0008 fsqrtb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5804 1234 fsqrtb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0041 fssqrtd %fp0,%fp0 +[ 0-9a-f]+: f205 4041 fssqrtl %d5,%fp0 +[ 0-9a-f]+: f214 4041 fssqrtl %a4@,%fp0 +[ 0-9a-f]+: f21b 4041 fssqrtl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4041 fssqrtl %a2@-,%fp0 [ 0-9a-f]+: f22e 4041 0008 fssqrtl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4041 1234 fssqrtl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4441 fssqrts %d5,%fp0 +[ 0-9a-f]+: f214 4441 fssqrts %a4@,%fp0 +[ 0-9a-f]+: f21b 4441 fssqrts %a3@\+,%fp0 +[ 0-9a-f]+: f222 4441 fssqrts %a2@-,%fp0 [ 0-9a-f]+: f22e 4441 0008 fssqrts %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4441 1234 fssqrts %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5041 fssqrtw %d5,%fp0 +[ 0-9a-f]+: f214 5041 fssqrtw %a4@,%fp0 +[ 0-9a-f]+: f21b 5041 fssqrtw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5041 fssqrtw %a2@-,%fp0 [ 0-9a-f]+: f22e 5041 0008 fssqrtw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5041 1234 fssqrtw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5441 fssqrtd %a4@,%fp0 +[ 0-9a-f]+: f21b 5441 fssqrtd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5441 fssqrtd %a2@-,%fp0 [ 0-9a-f]+: f22e 5441 0008 fssqrtd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5441 1234 fssqrtd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5841 fssqrtb %d5,%fp0 +[ 0-9a-f]+: f214 5841 fssqrtb %a4@,%fp0 +[ 0-9a-f]+: f21b 5841 fssqrtb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5841 fssqrtb %a2@-,%fp0 [ 0-9a-f]+: f22e 5841 0008 fssqrtb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5841 1234 fssqrtb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0045 fdsqrtd %fp0,%fp0 +[ 0-9a-f]+: f205 4045 fdsqrtl %d5,%fp0 +[ 0-9a-f]+: f214 4045 fdsqrtl %a4@,%fp0 +[ 0-9a-f]+: f21b 4045 fdsqrtl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4045 fdsqrtl %a2@-,%fp0 [ 0-9a-f]+: f22e 4045 0008 fdsqrtl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4045 1234 fdsqrtl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4445 fdsqrts %d5,%fp0 +[ 0-9a-f]+: f214 4445 fdsqrts %a4@,%fp0 +[ 0-9a-f]+: f21b 4445 fdsqrts %a3@\+,%fp0 +[ 0-9a-f]+: f222 4445 fdsqrts %a2@-,%fp0 [ 0-9a-f]+: f22e 4445 0008 fdsqrts %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4445 1234 fdsqrts %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5045 fdsqrtw %d5,%fp0 +[ 0-9a-f]+: f214 5045 fdsqrtw %a4@,%fp0 +[ 0-9a-f]+: f21b 5045 fdsqrtw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5045 fdsqrtw %a2@-,%fp0 [ 0-9a-f]+: f22e 5045 0008 fdsqrtw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5045 1234 fdsqrtw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5445 fdsqrtd %a4@,%fp0 +[ 0-9a-f]+: f21b 5445 fdsqrtd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5445 fdsqrtd %a2@-,%fp0 [ 0-9a-f]+: f22e 5445 0008 fdsqrtd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5445 1234 fdsqrtd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5845 fdsqrtb %d5,%fp0 +[ 0-9a-f]+: f214 5845 fdsqrtb %a4@,%fp0 +[ 0-9a-f]+: f21b 5845 fdsqrtb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5845 fdsqrtb %a2@-,%fp0 [ 0-9a-f]+: f22e 5845 0008 fdsqrtb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5845 1234 fdsqrtb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0018 fabsd %fp0,%fp0 +[ 0-9a-f]+: f205 4018 fabsl %d5,%fp0 +[ 0-9a-f]+: f214 4018 fabsl %a4@,%fp0 +[ 0-9a-f]+: f21b 4018 fabsl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4018 fabsl %a2@-,%fp0 [ 0-9a-f]+: f22e 4018 0008 fabsl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4018 1234 fabsl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4418 fabss %d5,%fp0 +[ 0-9a-f]+: f214 4418 fabss %a4@,%fp0 +[ 0-9a-f]+: f21b 4418 fabss %a3@\+,%fp0 +[ 0-9a-f]+: f222 4418 fabss %a2@-,%fp0 [ 0-9a-f]+: f22e 4418 0008 fabss %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4418 1234 fabss %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5018 fabsw %d5,%fp0 +[ 0-9a-f]+: f214 5018 fabsw %a4@,%fp0 +[ 0-9a-f]+: f21b 5018 fabsw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5018 fabsw %a2@-,%fp0 [ 0-9a-f]+: f22e 5018 0008 fabsw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5018 1234 fabsw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5418 fabsd %a4@,%fp0 +[ 0-9a-f]+: f21b 5418 fabsd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5418 fabsd %a2@-,%fp0 [ 0-9a-f]+: f22e 5418 0008 fabsd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5418 1234 fabsd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5818 fabsb %d5,%fp0 +[ 0-9a-f]+: f214 5818 fabsb %a4@,%fp0 +[ 0-9a-f]+: f21b 5818 fabsb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5818 fabsb %a2@-,%fp0 [ 0-9a-f]+: f22e 5818 0008 fabsb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5818 1234 fabsb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0058 fsabsd %fp0,%fp0 +[ 0-9a-f]+: f205 4058 fsabsl %d5,%fp0 +[ 0-9a-f]+: f214 4058 fsabsl %a4@,%fp0 +[ 0-9a-f]+: f21b 4058 fsabsl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4058 fsabsl %a2@-,%fp0 [ 0-9a-f]+: f22e 4058 0008 fsabsl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4058 1234 fsabsl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4458 fsabss %d5,%fp0 +[ 0-9a-f]+: f214 4458 fsabss %a4@,%fp0 +[ 0-9a-f]+: f21b 4458 fsabss %a3@\+,%fp0 +[ 0-9a-f]+: f222 4458 fsabss %a2@-,%fp0 [ 0-9a-f]+: f22e 4458 0008 fsabss %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4458 1234 fsabss %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5058 fsabsw %d5,%fp0 +[ 0-9a-f]+: f214 5058 fsabsw %a4@,%fp0 +[ 0-9a-f]+: f21b 5058 fsabsw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5058 fsabsw %a2@-,%fp0 [ 0-9a-f]+: f22e 5058 0008 fsabsw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5058 1234 fsabsw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5458 fsabsd %a4@,%fp0 +[ 0-9a-f]+: f21b 5458 fsabsd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5458 fsabsd %a2@-,%fp0 [ 0-9a-f]+: f22e 5458 0008 fsabsd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5458 1234 fsabsd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5858 fsabsb %d5,%fp0 +[ 0-9a-f]+: f214 5858 fsabsb %a4@,%fp0 +[ 0-9a-f]+: f21b 5858 fsabsb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5858 fsabsb %a2@-,%fp0 [ 0-9a-f]+: f22e 5858 0008 fsabsb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5858 1234 fsabsb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 005c fdabsd %fp0,%fp0 +[ 0-9a-f]+: f205 405c fdabsl %d5,%fp0 +[ 0-9a-f]+: f214 405c fdabsl %a4@,%fp0 +[ 0-9a-f]+: f21b 405c fdabsl %a3@\+,%fp0 +[ 0-9a-f]+: f222 405c fdabsl %a2@-,%fp0 [ 0-9a-f]+: f22e 405c 0008 fdabsl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 405c 1234 fdabsl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 445c fdabss %d5,%fp0 +[ 0-9a-f]+: f214 445c fdabss %a4@,%fp0 +[ 0-9a-f]+: f21b 445c fdabss %a3@\+,%fp0 +[ 0-9a-f]+: f222 445c fdabss %a2@-,%fp0 [ 0-9a-f]+: f22e 445c 0008 fdabss %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 445c 1234 fdabss %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 505c fdabsw %d5,%fp0 +[ 0-9a-f]+: f214 505c fdabsw %a4@,%fp0 +[ 0-9a-f]+: f21b 505c fdabsw %a3@\+,%fp0 +[ 0-9a-f]+: f222 505c fdabsw %a2@-,%fp0 [ 0-9a-f]+: f22e 505c 0008 fdabsw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 505c 1234 fdabsw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 545c fdabsd %a4@,%fp0 +[ 0-9a-f]+: f21b 545c fdabsd %a3@\+,%fp0 +[ 0-9a-f]+: f222 545c fdabsd %a2@-,%fp0 [ 0-9a-f]+: f22e 545c 0008 fdabsd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 545c 1234 fdabsd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 585c fdabsb %d5,%fp0 +[ 0-9a-f]+: f214 585c fdabsb %a4@,%fp0 +[ 0-9a-f]+: f21b 585c fdabsb %a3@\+,%fp0 +[ 0-9a-f]+: f222 585c fdabsb %a2@-,%fp0 [ 0-9a-f]+: f22e 585c 0008 fdabsb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 585c 1234 fdabsb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 001a fnegd %fp0,%fp0 +[ 0-9a-f]+: f205 401a fnegl %d5,%fp0 +[ 0-9a-f]+: f214 401a fnegl %a4@,%fp0 +[ 0-9a-f]+: f21b 401a fnegl %a3@\+,%fp0 +[ 0-9a-f]+: f222 401a fnegl %a2@-,%fp0 [ 0-9a-f]+: f22e 401a 0008 fnegl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 401a 1234 fnegl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 441a fnegs %d5,%fp0 +[ 0-9a-f]+: f214 441a fnegs %a4@,%fp0 +[ 0-9a-f]+: f21b 441a fnegs %a3@\+,%fp0 +[ 0-9a-f]+: f222 441a fnegs %a2@-,%fp0 [ 0-9a-f]+: f22e 441a 0008 fnegs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 441a 1234 fnegs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 501a fnegw %d5,%fp0 +[ 0-9a-f]+: f214 501a fnegw %a4@,%fp0 +[ 0-9a-f]+: f21b 501a fnegw %a3@\+,%fp0 +[ 0-9a-f]+: f222 501a fnegw %a2@-,%fp0 [ 0-9a-f]+: f22e 501a 0008 fnegw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 501a 1234 fnegw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 541a fnegd %a4@,%fp0 +[ 0-9a-f]+: f21b 541a fnegd %a3@\+,%fp0 +[ 0-9a-f]+: f222 541a fnegd %a2@-,%fp0 [ 0-9a-f]+: f22e 541a 0008 fnegd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 541a 1234 fnegd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 581a fnegb %d5,%fp0 +[ 0-9a-f]+: f214 581a fnegb %a4@,%fp0 +[ 0-9a-f]+: f21b 581a fnegb %a3@\+,%fp0 +[ 0-9a-f]+: f222 581a fnegb %a2@-,%fp0 [ 0-9a-f]+: f22e 581a 0008 fnegb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 581a 1234 fnegb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 005a fsnegd %fp0,%fp0 +[ 0-9a-f]+: f205 405a fsnegl %d5,%fp0 +[ 0-9a-f]+: f214 405a fsnegl %a4@,%fp0 +[ 0-9a-f]+: f21b 405a fsnegl %a3@\+,%fp0 +[ 0-9a-f]+: f222 405a fsnegl %a2@-,%fp0 [ 0-9a-f]+: f22e 405a 0008 fsnegl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 405a 1234 fsnegl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 445a fsnegs %d5,%fp0 +[ 0-9a-f]+: f214 445a fsnegs %a4@,%fp0 +[ 0-9a-f]+: f21b 445a fsnegs %a3@\+,%fp0 +[ 0-9a-f]+: f222 445a fsnegs %a2@-,%fp0 [ 0-9a-f]+: f22e 445a 0008 fsnegs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 445a 1234 fsnegs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 505a fsnegw %d5,%fp0 +[ 0-9a-f]+: f214 505a fsnegw %a4@,%fp0 +[ 0-9a-f]+: f21b 505a fsnegw %a3@\+,%fp0 +[ 0-9a-f]+: f222 505a fsnegw %a2@-,%fp0 [ 0-9a-f]+: f22e 505a 0008 fsnegw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 505a 1234 fsnegw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 545a fsnegd %a4@,%fp0 +[ 0-9a-f]+: f21b 545a fsnegd %a3@\+,%fp0 +[ 0-9a-f]+: f222 545a fsnegd %a2@-,%fp0 [ 0-9a-f]+: f22e 545a 0008 fsnegd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 545a 1234 fsnegd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 585a fsnegb %d5,%fp0 +[ 0-9a-f]+: f214 585a fsnegb %a4@,%fp0 +[ 0-9a-f]+: f21b 585a fsnegb %a3@\+,%fp0 +[ 0-9a-f]+: f222 585a fsnegb %a2@-,%fp0 [ 0-9a-f]+: f22e 585a 0008 fsnegb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 585a 1234 fsnegb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 005e fdnegd %fp0,%fp0 +[ 0-9a-f]+: f205 405e fdnegl %d5,%fp0 +[ 0-9a-f]+: f214 405e fdnegl %a4@,%fp0 +[ 0-9a-f]+: f21b 405e fdnegl %a3@\+,%fp0 +[ 0-9a-f]+: f222 405e fdnegl %a2@-,%fp0 [ 0-9a-f]+: f22e 405e 0008 fdnegl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 405e 1234 fdnegl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 445e fdnegs %d5,%fp0 +[ 0-9a-f]+: f214 445e fdnegs %a4@,%fp0 +[ 0-9a-f]+: f21b 445e fdnegs %a3@\+,%fp0 +[ 0-9a-f]+: f222 445e fdnegs %a2@-,%fp0 [ 0-9a-f]+: f22e 445e 0008 fdnegs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 445e 1234 fdnegs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 505e fdnegw %d5,%fp0 +[ 0-9a-f]+: f214 505e fdnegw %a4@,%fp0 +[ 0-9a-f]+: f21b 505e fdnegw %a3@\+,%fp0 +[ 0-9a-f]+: f222 505e fdnegw %a2@-,%fp0 [ 0-9a-f]+: f22e 505e 0008 fdnegw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 505e 1234 fdnegw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 545e fdnegd %a4@,%fp0 +[ 0-9a-f]+: f21b 545e fdnegd %a3@\+,%fp0 +[ 0-9a-f]+: f222 545e fdnegd %a2@-,%fp0 [ 0-9a-f]+: f22e 545e 0008 fdnegd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 545e 1234 fdnegd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 585e fdnegb %d5,%fp0 +[ 0-9a-f]+: f214 585e fdnegb %a4@,%fp0 +[ 0-9a-f]+: f21b 585e fdnegb %a3@\+,%fp0 +[ 0-9a-f]+: f222 585e fdnegb %a2@-,%fp0 [ 0-9a-f]+: f22e 585e 0008 fdnegb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 585e 1234 fdnegb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0020 fdivd %fp0,%fp0 +[ 0-9a-f]+: f205 4020 fdivl %d5,%fp0 +[ 0-9a-f]+: f214 4020 fdivl %a4@,%fp0 +[ 0-9a-f]+: f21b 4020 fdivl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4020 fdivl %a2@-,%fp0 [ 0-9a-f]+: f22e 4020 0008 fdivl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4020 1234 fdivl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4420 fdivs %d5,%fp0 +[ 0-9a-f]+: f214 4420 fdivs %a4@,%fp0 +[ 0-9a-f]+: f21b 4420 fdivs %a3@\+,%fp0 +[ 0-9a-f]+: f222 4420 fdivs %a2@-,%fp0 [ 0-9a-f]+: f22e 4420 0008 fdivs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4420 1234 fdivs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5020 fdivw %d5,%fp0 +[ 0-9a-f]+: f214 5020 fdivw %a4@,%fp0 +[ 0-9a-f]+: f21b 5020 fdivw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5020 fdivw %a2@-,%fp0 [ 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0-9a-f]+: f222 4460 fsdivs %a2@-,%fp0 [ 0-9a-f]+: f22e 4460 0008 fsdivs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4460 1234 fsdivs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5060 fsdivw %d5,%fp0 +[ 0-9a-f]+: f214 5060 fsdivw %a4@,%fp0 +[ 0-9a-f]+: f21b 5060 fsdivw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5060 fsdivw %a2@-,%fp0 [ 0-9a-f]+: f22e 5060 0008 fsdivw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5060 1234 fsdivw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5460 fsdivd %a4@,%fp0 +[ 0-9a-f]+: f21b 5460 fsdivd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5460 fsdivd %a2@-,%fp0 [ 0-9a-f]+: f22e 5460 0008 fsdivd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5460 1234 fsdivd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5860 fsdivb %d5,%fp0 +[ 0-9a-f]+: f214 5860 fsdivb %a4@,%fp0 +[ 0-9a-f]+: f21b 5860 fsdivb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5860 fsdivb %a2@-,%fp0 [ 0-9a-f]+: f22e 5860 0008 fsdivb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5860 1234 fsdivb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0064 fddivd %fp0,%fp0 +[ 0-9a-f]+: f205 4064 fddivl %d5,%fp0 +[ 0-9a-f]+: f214 4064 fddivl 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5864 fddivb %a4@,%fp0 +[ 0-9a-f]+: f21b 5864 fddivb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5864 fddivb %a2@-,%fp0 [ 0-9a-f]+: f22e 5864 0008 fddivb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5864 1234 fddivb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0022 faddd %fp0,%fp0 +[ 0-9a-f]+: f205 4022 faddl %d5,%fp0 +[ 0-9a-f]+: f214 4022 faddl %a4@,%fp0 +[ 0-9a-f]+: f21b 4022 faddl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4022 faddl %a2@-,%fp0 [ 0-9a-f]+: f22e 4022 0008 faddl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4022 1234 faddl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4422 fadds %d5,%fp0 +[ 0-9a-f]+: f214 4422 fadds %a4@,%fp0 +[ 0-9a-f]+: f21b 4422 fadds %a3@\+,%fp0 +[ 0-9a-f]+: f222 4422 fadds %a2@-,%fp0 [ 0-9a-f]+: f22e 4422 0008 fadds %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4422 1234 fadds %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5022 faddw %d5,%fp0 +[ 0-9a-f]+: f214 5022 faddw %a4@,%fp0 +[ 0-9a-f]+: f21b 5022 faddw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5022 faddw %a2@-,%fp0 [ 0-9a-f]+: f22e 5022 0008 faddw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5022 1234 faddw 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f222 5866 fdaddb %a2@-,%fp0 [ 0-9a-f]+: f22e 5866 0008 fdaddb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5866 1234 fdaddb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0023 fmuld %fp0,%fp0 +[ 0-9a-f]+: f205 4023 fmull %d5,%fp0 +[ 0-9a-f]+: f214 4023 fmull %a4@,%fp0 +[ 0-9a-f]+: f21b 4023 fmull %a3@\+,%fp0 +[ 0-9a-f]+: f222 4023 fmull %a2@-,%fp0 [ 0-9a-f]+: f22e 4023 0008 fmull %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4023 1234 fmull %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4423 fmuls %d5,%fp0 +[ 0-9a-f]+: f214 4423 fmuls %a4@,%fp0 +[ 0-9a-f]+: f21b 4423 fmuls %a3@\+,%fp0 +[ 0-9a-f]+: f222 4423 fmuls %a2@-,%fp0 [ 0-9a-f]+: f22e 4423 0008 fmuls %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4423 1234 fmuls %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5023 fmulw %d5,%fp0 +[ 0-9a-f]+: f214 5023 fmulw %a4@,%fp0 +[ 0-9a-f]+: f21b 5023 fmulw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5023 fmulw %a2@-,%fp0 [ 0-9a-f]+: f22e 5023 0008 fmulw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5023 1234 fmulw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5423 fmuld %a4@,%fp0 +[ 0-9a-f]+: f21b 5423 fmuld %a3@\+,%fp0 +[ 0-9a-f]+: f222 5423 fmuld %a2@-,%fp0 [ 0-9a-f]+: f22e 5423 0008 fmuld %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5423 1234 fmuld %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5823 fmulb %d5,%fp0 +[ 0-9a-f]+: f214 5823 fmulb %a4@,%fp0 +[ 0-9a-f]+: f21b 5823 fmulb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5823 fmulb %a2@-,%fp0 [ 0-9a-f]+: f22e 5823 0008 fmulb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5823 1234 fmulb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0063 fsmuld %fp0,%fp0 +[ 0-9a-f]+: f205 4063 fsmull %d5,%fp0 +[ 0-9a-f]+: f214 4063 fsmull %a4@,%fp0 +[ 0-9a-f]+: f21b 4063 fsmull %a3@\+,%fp0 +[ 0-9a-f]+: f222 4063 fsmull %a2@-,%fp0 [ 0-9a-f]+: f22e 4063 0008 fsmull %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4063 1234 fsmull %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4463 fsmuls %d5,%fp0 +[ 0-9a-f]+: f214 4463 fsmuls %a4@,%fp0 +[ 0-9a-f]+: f21b 4463 fsmuls %a3@\+,%fp0 +[ 0-9a-f]+: f222 4463 fsmuls %a2@-,%fp0 [ 0-9a-f]+: f22e 4463 0008 fsmuls %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4463 1234 fsmuls %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5063 fsmulw %d5,%fp0 +[ 0-9a-f]+: f214 5063 fsmulw %a4@,%fp0 +[ 0-9a-f]+: f21b 5063 fsmulw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5063 fsmulw %a2@-,%fp0 [ 0-9a-f]+: f22e 5063 0008 fsmulw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5063 1234 fsmulw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5463 fsmuld %a4@,%fp0 +[ 0-9a-f]+: f21b 5463 fsmuld %a3@\+,%fp0 +[ 0-9a-f]+: f222 5463 fsmuld %a2@-,%fp0 [ 0-9a-f]+: f22e 5463 0008 fsmuld %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5463 1234 fsmuld %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5863 fsmulb %d5,%fp0 +[ 0-9a-f]+: f214 5863 fsmulb %a4@,%fp0 +[ 0-9a-f]+: f21b 5863 fsmulb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5863 fsmulb %a2@-,%fp0 [ 0-9a-f]+: f22e 5863 0008 fsmulb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5863 1234 fsmulb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0067 fdmuld %fp0,%fp0 +[ 0-9a-f]+: f205 4067 fdmull %d5,%fp0 +[ 0-9a-f]+: f214 4067 fdmull %a4@,%fp0 +[ 0-9a-f]+: f21b 4067 fdmull %a3@\+,%fp0 +[ 0-9a-f]+: f222 4067 fdmull %a2@-,%fp0 [ 0-9a-f]+: f22e 4067 0008 fdmull %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4067 1234 fdmull %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4467 fdmuls %d5,%fp0 +[ 0-9a-f]+: f214 4467 fdmuls %a4@,%fp0 +[ 0-9a-f]+: f21b 4467 fdmuls %a3@\+,%fp0 +[ 0-9a-f]+: f222 4467 fdmuls %a2@-,%fp0 [ 0-9a-f]+: f22e 4467 0008 fdmuls %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4467 1234 fdmuls %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5067 fdmulw %d5,%fp0 +[ 0-9a-f]+: f214 5067 fdmulw %a4@,%fp0 +[ 0-9a-f]+: f21b 5067 fdmulw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5067 fdmulw %a2@-,%fp0 [ 0-9a-f]+: f22e 5067 0008 fdmulw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5067 1234 fdmulw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5467 fdmuld %a4@,%fp0 +[ 0-9a-f]+: f21b 5467 fdmuld %a3@\+,%fp0 +[ 0-9a-f]+: f222 5467 fdmuld %a2@-,%fp0 [ 0-9a-f]+: f22e 5467 0008 fdmuld %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5467 1234 fdmuld %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5867 fdmulb %d5,%fp0 +[ 0-9a-f]+: f214 5867 fdmulb %a4@,%fp0 +[ 0-9a-f]+: f21b 5867 fdmulb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5867 fdmulb %a2@-,%fp0 [ 0-9a-f]+: f22e 5867 0008 fdmulb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5867 1234 fdmulb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0028 fsubd %fp0,%fp0 +[ 0-9a-f]+: f205 4028 fsubl %d5,%fp0 +[ 0-9a-f]+: f214 4028 fsubl %a4@,%fp0 +[ 0-9a-f]+: f21b 4028 fsubl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4028 fsubl %a2@-,%fp0 [ 0-9a-f]+: f22e 4028 0008 fsubl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4028 1234 fsubl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4428 fsubs %d5,%fp0 +[ 0-9a-f]+: f214 4428 fsubs %a4@,%fp0 +[ 0-9a-f]+: f21b 4428 fsubs %a3@\+,%fp0 +[ 0-9a-f]+: f222 4428 fsubs %a2@-,%fp0 [ 0-9a-f]+: f22e 4428 0008 fsubs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4428 1234 fsubs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5028 fsubw %d5,%fp0 +[ 0-9a-f]+: f214 5028 fsubw %a4@,%fp0 +[ 0-9a-f]+: f21b 5028 fsubw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5028 fsubw %a2@-,%fp0 [ 0-9a-f]+: f22e 5028 0008 fsubw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5028 1234 fsubw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5428 fsubd %a4@,%fp0 +[ 0-9a-f]+: f21b 5428 fsubd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5428 fsubd %a2@-,%fp0 [ 0-9a-f]+: f22e 5428 0008 fsubd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5428 1234 fsubd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5828 fsubb %d5,%fp0 +[ 0-9a-f]+: f214 5828 fsubb %a4@,%fp0 +[ 0-9a-f]+: f21b 5828 fsubb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5828 fsubb %a2@-,%fp0 [ 0-9a-f]+: f22e 5828 0008 fsubb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5828 1234 fsubb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0068 fssubd %fp0,%fp0 +[ 0-9a-f]+: f205 4068 fssubl %d5,%fp0 +[ 0-9a-f]+: f214 4068 fssubl %a4@,%fp0 +[ 0-9a-f]+: f21b 4068 fssubl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4068 fssubl %a2@-,%fp0 [ 0-9a-f]+: f22e 4068 0008 fssubl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4068 1234 fssubl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4468 fssubs %d5,%fp0 +[ 0-9a-f]+: f214 4468 fssubs %a4@,%fp0 +[ 0-9a-f]+: f21b 4468 fssubs %a3@\+,%fp0 +[ 0-9a-f]+: f222 4468 fssubs %a2@-,%fp0 [ 0-9a-f]+: f22e 4468 0008 fssubs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4468 1234 fssubs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5068 fssubw %d5,%fp0 +[ 0-9a-f]+: f214 5068 fssubw %a4@,%fp0 +[ 0-9a-f]+: f21b 5068 fssubw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5068 fssubw %a2@-,%fp0 [ 0-9a-f]+: f22e 5068 0008 fssubw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5068 1234 fssubw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5468 fssubd %a4@,%fp0 +[ 0-9a-f]+: f21b 5468 fssubd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5468 fssubd %a2@-,%fp0 [ 0-9a-f]+: f22e 5468 0008 fssubd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5468 1234 fssubd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5868 fssubb %d5,%fp0 +[ 0-9a-f]+: f214 5868 fssubb %a4@,%fp0 +[ 0-9a-f]+: f21b 5868 fssubb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5868 fssubb %a2@-,%fp0 [ 0-9a-f]+: f22e 5868 0008 fssubb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5868 1234 fssubb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 006c fdsubd %fp0,%fp0 +[ 0-9a-f]+: f205 406c fdsubl %d5,%fp0 +[ 0-9a-f]+: f214 406c fdsubl %a4@,%fp0 +[ 0-9a-f]+: f21b 406c fdsubl %a3@\+,%fp0 +[ 0-9a-f]+: f222 406c fdsubl %a2@-,%fp0 [ 0-9a-f]+: f22e 406c 0008 fdsubl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 406c 1234 fdsubl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 446c fdsubs %d5,%fp0 +[ 0-9a-f]+: f214 446c fdsubs %a4@,%fp0 +[ 0-9a-f]+: f21b 446c fdsubs %a3@\+,%fp0 +[ 0-9a-f]+: f222 446c fdsubs %a2@-,%fp0 [ 0-9a-f]+: f22e 446c 0008 fdsubs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 446c 1234 fdsubs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 506c fdsubw %d5,%fp0 +[ 0-9a-f]+: f214 506c fdsubw %a4@,%fp0 +[ 0-9a-f]+: f21b 506c fdsubw %a3@\+,%fp0 +[ 0-9a-f]+: f222 506c fdsubw %a2@-,%fp0 [ 0-9a-f]+: f22e 506c 0008 fdsubw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 506c 1234 fdsubw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 546c fdsubd %a4@,%fp0 +[ 0-9a-f]+: f21b 546c fdsubd %a3@\+,%fp0 +[ 0-9a-f]+: f222 546c fdsubd %a2@-,%fp0 [ 0-9a-f]+: f22e 546c 0008 fdsubd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 546c 1234 fdsubd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 586c fdsubb %d5,%fp0 +[ 0-9a-f]+: f214 586c fdsubb %a4@,%fp0 +[ 0-9a-f]+: f21b 586c fdsubb %a3@\+,%fp0 +[ 0-9a-f]+: f222 586c fdsubb %a2@-,%fp0 [ 0-9a-f]+: f22e 586c 0008 fdsubb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 586c 1234 fdsubb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0000 fmoved %fp0,%fp0 +[ 0-9a-f]+: f205 4000 fmovel %d5,%fp0 +[ 0-9a-f]+: f214 4000 fmovel %a4@,%fp0 +[ 0-9a-f]+: f21b 4000 fmovel %a3@\+,%fp0 +[ 0-9a-f]+: f222 4000 fmovel %a2@-,%fp0 [ 0-9a-f]+: f22e 4000 0008 fmovel %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4000 1234 fmovel %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4400 fmoves %d5,%fp0 +[ 0-9a-f]+: f214 4400 fmoves %a4@,%fp0 +[ 0-9a-f]+: f21b 4400 fmoves %a3@\+,%fp0 +[ 0-9a-f]+: f222 4400 fmoves %a2@-,%fp0 [ 0-9a-f]+: f22e 4400 0008 fmoves %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4400 1234 fmoves %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5000 fmovew %d5,%fp0 +[ 0-9a-f]+: f214 5000 fmovew %a4@,%fp0 +[ 0-9a-f]+: f21b 5000 fmovew %a3@\+,%fp0 +[ 0-9a-f]+: f222 5000 fmovew %a2@-,%fp0 [ 0-9a-f]+: f22e 5000 0008 fmovew %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5000 1234 fmovew %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5400 fmoved %a4@,%fp0 +[ 0-9a-f]+: f21b 5400 fmoved %a3@\+,%fp0 +[ 0-9a-f]+: f222 5400 fmoved %a2@-,%fp0 [ 0-9a-f]+: f22e 5400 0008 fmoved %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5400 1234 fmoved %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5800 fmoveb %d5,%fp0 +[ 0-9a-f]+: f214 5800 fmoveb %a4@,%fp0 +[ 0-9a-f]+: f21b 5800 fmoveb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5800 fmoveb %a2@-,%fp0 [ 0-9a-f]+: f22e 5800 0008 fmoveb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5800 1234 fmoveb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0040 fsmoved %fp0,%fp0 +[ 0-9a-f]+: f205 4040 fsmovel %d5,%fp0 +[ 0-9a-f]+: f214 4040 fsmovel %a4@,%fp0 +[ 0-9a-f]+: f21b 4040 fsmovel %a3@\+,%fp0 +[ 0-9a-f]+: f222 4040 fsmovel %a2@-,%fp0 [ 0-9a-f]+: f22e 4040 0008 fsmovel %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4040 1234 fsmovel %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4440 fsmoves %d5,%fp0 +[ 0-9a-f]+: f214 4440 fsmoves %a4@,%fp0 +[ 0-9a-f]+: f21b 4440 fsmoves %a3@\+,%fp0 +[ 0-9a-f]+: f222 4440 fsmoves %a2@-,%fp0 [ 0-9a-f]+: f22e 4440 0008 fsmoves %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4440 1234 fsmoves %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5040 fsmovew %d5,%fp0 +[ 0-9a-f]+: f214 5040 fsmovew %a4@,%fp0 +[ 0-9a-f]+: f21b 5040 fsmovew %a3@\+,%fp0 +[ 0-9a-f]+: f222 5040 fsmovew %a2@-,%fp0 [ 0-9a-f]+: f22e 5040 0008 fsmovew %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5040 1234 fsmovew %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5440 fsmoved %a4@,%fp0 +[ 0-9a-f]+: f21b 5440 fsmoved %a3@\+,%fp0 +[ 0-9a-f]+: f222 5440 fsmoved %a2@-,%fp0 [ 0-9a-f]+: f22e 5440 0008 fsmoved %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5440 1234 fsmoved %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5840 fsmoveb %d5,%fp0 +[ 0-9a-f]+: f214 5840 fsmoveb %a4@,%fp0 +[ 0-9a-f]+: f21b 5840 fsmoveb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5840 fsmoveb %a2@-,%fp0 [ 0-9a-f]+: f22e 5840 0008 fsmoveb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5840 1234 fsmoveb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0044 fdmoved %fp0,%fp0 +[ 0-9a-f]+: f205 4044 fdmovel %d5,%fp0 +[ 0-9a-f]+: f214 4044 fdmovel %a4@,%fp0 +[ 0-9a-f]+: f21b 4044 fdmovel %a3@\+,%fp0 +[ 0-9a-f]+: f222 4044 fdmovel %a2@-,%fp0 [ 0-9a-f]+: f22e 4044 0008 fdmovel %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4044 1234 fdmovel %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4444 fdmoves %d5,%fp0 +[ 0-9a-f]+: f214 4444 fdmoves %a4@,%fp0 +[ 0-9a-f]+: f21b 4444 fdmoves %a3@\+,%fp0 +[ 0-9a-f]+: f222 4444 fdmoves %a2@-,%fp0 [ 0-9a-f]+: f22e 4444 0008 fdmoves %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4444 1234 fdmoves %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5044 fdmovew %d5,%fp0 +[ 0-9a-f]+: f214 5044 fdmovew %a4@,%fp0 +[ 0-9a-f]+: f21b 5044 fdmovew %a3@\+,%fp0 +[ 0-9a-f]+: f222 5044 fdmovew %a2@-,%fp0 [ 0-9a-f]+: f22e 5044 0008 fdmovew %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5044 1234 fdmovew %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5444 fdmoved %a4@,%fp0 +[ 0-9a-f]+: f21b 5444 fdmoved %a3@\+,%fp0 +[ 0-9a-f]+: f222 5444 fdmoved %a2@-,%fp0 [ 0-9a-f]+: f22e 5444 0008 fdmoved %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5444 1234 fdmoved %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5844 fdmoveb %d5,%fp0 +[ 0-9a-f]+: f214 5844 fdmoveb %a4@,%fp0 +[ 0-9a-f]+: f21b 5844 fdmoveb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5844 fdmoveb %a2@-,%fp0 [ 0-9a-f]+: f22e 5844 0008 fdmoveb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5844 1234 fdmoveb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0001 fintd %fp0,%fp0 +[ 0-9a-f]+: f205 4001 fintl %d5,%fp0 +[ 0-9a-f]+: f214 4001 fintl %a4@,%fp0 +[ 0-9a-f]+: f21b 4001 fintl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4001 fintl %a2@-,%fp0 [ 0-9a-f]+: f22e 4001 0008 fintl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4001 1234 fintl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4401 fints %d5,%fp0 +[ 0-9a-f]+: f214 4401 fints %a4@,%fp0 +[ 0-9a-f]+: f21b 4401 fints %a3@\+,%fp0 +[ 0-9a-f]+: f222 4401 fints %a2@-,%fp0 [ 0-9a-f]+: f22e 4401 0008 fints %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4401 1234 fints %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5001 fintw %d5,%fp0 +[ 0-9a-f]+: f214 5001 fintw %a4@,%fp0 +[ 0-9a-f]+: f21b 5001 fintw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5001 fintw %a2@-,%fp0 [ 0-9a-f]+: f22e 5001 0008 fintw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5001 1234 fintw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5401 fintd %a4@,%fp0 +[ 0-9a-f]+: f21b 5401 fintd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5401 fintd %a2@-,%fp0 [ 0-9a-f]+: f22e 5401 0008 fintd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5401 1234 fintd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5801 fintb %d5,%fp0 +[ 0-9a-f]+: f214 5801 fintb %a4@,%fp0 +[ 0-9a-f]+: f21b 5801 fintb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5801 fintb %a2@-,%fp0 [ 0-9a-f]+: f22e 5801 0008 fintb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5801 1234 fintb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0003 fintrzd %fp0,%fp0 +[ 0-9a-f]+: f205 4003 fintrzl %d5,%fp0 +[ 0-9a-f]+: f214 4003 fintrzl %a4@,%fp0 +[ 0-9a-f]+: f21b 4003 fintrzl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4003 fintrzl %a2@-,%fp0 [ 0-9a-f]+: f22e 4003 0008 fintrzl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4003 1234 fintrzl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4403 fintrzs %d5,%fp0 +[ 0-9a-f]+: f214 4403 fintrzs %a4@,%fp0 +[ 0-9a-f]+: f21b 4403 fintrzs %a3@\+,%fp0 +[ 0-9a-f]+: f222 4403 fintrzs %a2@-,%fp0 [ 0-9a-f]+: f22e 4403 0008 fintrzs %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4403 1234 fintrzs %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5003 fintrzw %d5,%fp0 +[ 0-9a-f]+: f214 5003 fintrzw %a4@,%fp0 +[ 0-9a-f]+: f21b 5003 fintrzw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5003 fintrzw %a2@-,%fp0 [ 0-9a-f]+: f22e 5003 0008 fintrzw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5003 1234 fintrzw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5403 fintrzd %a4@,%fp0 +[ 0-9a-f]+: f21b 5403 fintrzd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5403 fintrzd %a2@-,%fp0 [ 0-9a-f]+: f22e 5403 0008 fintrzd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5403 1234 fintrzd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5803 fintrzb %d5,%fp0 +[ 0-9a-f]+: f214 5803 fintrzb %a4@,%fp0 +[ 0-9a-f]+: f21b 5803 fintrzb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5803 fintrzb %a2@-,%fp0 [ 0-9a-f]+: f22e 5803 0008 fintrzb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5803 1234 fintrzb %pc@\(.*\),%fp0 [ 0-9a-f]+: f200 0038 fcmpd %fp0,%fp0 +[ 0-9a-f]+: f205 4038 fcmpl %d5,%fp0 +[ 0-9a-f]+: f214 4038 fcmpl %a4@,%fp0 +[ 0-9a-f]+: f21b 4038 fcmpl %a3@\+,%fp0 +[ 0-9a-f]+: f222 4038 fcmpl %a2@-,%fp0 [ 0-9a-f]+: f22e 4038 0008 fcmpl %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4038 1234 fcmpl %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 4438 fcmps %d5,%fp0 +[ 0-9a-f]+: f214 4438 fcmps %a4@,%fp0 +[ 0-9a-f]+: f21b 4438 fcmps %a3@\+,%fp0 +[ 0-9a-f]+: f222 4438 fcmps %a2@-,%fp0 [ 0-9a-f]+: f22e 4438 0008 fcmps %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 4438 1234 fcmps %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5038 fcmpw %d5,%fp0 +[ 0-9a-f]+: f214 5038 fcmpw %a4@,%fp0 +[ 0-9a-f]+: f21b 5038 fcmpw %a3@\+,%fp0 +[ 0-9a-f]+: f222 5038 fcmpw %a2@-,%fp0 [ 0-9a-f]+: f22e 5038 0008 fcmpw %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5038 1234 fcmpw %pc@\(.*\),%fp0 +[ 0-9a-f]+: f214 5438 fcmpd %a4@,%fp0 +[ 0-9a-f]+: f21b 5438 fcmpd %a3@\+,%fp0 +[ 0-9a-f]+: f222 5438 fcmpd %a2@-,%fp0 [ 0-9a-f]+: f22e 5438 0008 fcmpd %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5438 1234 fcmpd %pc@\(.*\),%fp0 +[ 0-9a-f]+: f205 5838 fcmpb %d5,%fp0 +[ 0-9a-f]+: f214 5838 fcmpb %a4@,%fp0 +[ 0-9a-f]+: f21b 5838 fcmpb %a3@\+,%fp0 +[ 0-9a-f]+: f222 5838 fcmpb %a2@-,%fp0 [ 0-9a-f]+: f22e 5838 0008 fcmpb %fp@\(8\),%fp0 +[ 0-9a-f]+: f23a 5838 1234 fcmpb %pc@\(.*\),%fp0 [ 0-9a-f]+: f22e f0f2 0008 fmovemd %fp0-%fp3/%fp6,%fp@\(8\) [ 0-9a-f]+: f22e d02c 0008 fmovemd %fp@\(8\),%fp2/%fp4-%fp5 [ 0-9a-f]+: f22e f027 0008 fmovemd %fp2/%fp5-%fp7,%fp@\(8\) diff --git a/gas/testsuite/gas/m68k/mcf-fpu.s b/gas/testsuite/gas/m68k/mcf-fpu.s index 99231a74e31f..fd2a15621c52 100644 --- a/gas/testsuite/gas/m68k/mcf-fpu.s +++ b/gas/testsuite/gas/m68k/mcf-fpu.s @@ -2,167 +2,815 @@ .text fsqrtd %fp0,%fp0 + fsqrtl %d5,%fp0 + fsqrtl %a4@,%fp0 + fsqrtl %a3@+,%fp0 + fsqrtl %a2@-,%fp0 fsqrtl %fp@(8),%fp0 + fsqrtl %pc@(.+0x1238),%fp0 + fsqrts %d5,%fp0 + fsqrts %a4@,%fp0 + fsqrts %a3@+,%fp0 + fsqrts %a2@-,%fp0 fsqrts %fp@(8),%fp0 + fsqrts %pc@(.+0x1238),%fp0 + fsqrtw %d5,%fp0 + fsqrtw %a4@,%fp0 + fsqrtw %a3@+,%fp0 + fsqrtw %a2@-,%fp0 fsqrtw %fp@(8),%fp0 + fsqrtw %pc@(.+0x1238),%fp0 + fsqrtd %a4@,%fp0 + fsqrtd %a3@+,%fp0 + fsqrtd %a2@-,%fp0 fsqrtd %fp@(8),%fp0 + fsqrtd %pc@(.+0x1238),%fp0 + fsqrtb %d5,%fp0 + fsqrtb %a4@,%fp0 + fsqrtb %a3@+,%fp0 + fsqrtb %a2@-,%fp0 fsqrtb %fp@(8),%fp0 + fsqrtb %pc@(.+0x1238),%fp0 fssqrtd %fp0,%fp0 + fssqrtl %d5,%fp0 + fssqrtl %a4@,%fp0 + fssqrtl %a3@+,%fp0 + fssqrtl %a2@-,%fp0 fssqrtl %fp@(8),%fp0 + fssqrtl %pc@(.+0x1238),%fp0 + fssqrts %d5,%fp0 + fssqrts %a4@,%fp0 + fssqrts %a3@+,%fp0 + fssqrts %a2@-,%fp0 fssqrts %fp@(8),%fp0 + fssqrts %pc@(.+0x1238),%fp0 + fssqrtw %d5,%fp0 + fssqrtw %a4@,%fp0 + fssqrtw %a3@+,%fp0 + fssqrtw %a2@-,%fp0 fssqrtw %fp@(8),%fp0 + fssqrtw %pc@(.+0x1238),%fp0 + fssqrtd %a4@,%fp0 + fssqrtd %a3@+,%fp0 + fssqrtd %a2@-,%fp0 fssqrtd %fp@(8),%fp0 + fssqrtd %pc@(.+0x1238),%fp0 + fssqrtb %d5,%fp0 + fssqrtb %a4@,%fp0 + fssqrtb %a3@+,%fp0 + fssqrtb %a2@-,%fp0 fssqrtb %fp@(8),%fp0 + fssqrtb %pc@(.+0x1238),%fp0 fdsqrtd %fp0,%fp0 + fdsqrtl %d5,%fp0 + fdsqrtl %a4@,%fp0 + fdsqrtl %a3@+,%fp0 + fdsqrtl %a2@-,%fp0 fdsqrtl %fp@(8),%fp0 + fdsqrtl %pc@(.+0x1238),%fp0 + fdsqrts %d5,%fp0 + fdsqrts %a4@,%fp0 + fdsqrts %a3@+,%fp0 + fdsqrts %a2@-,%fp0 fdsqrts %fp@(8),%fp0 + fdsqrts %pc@(.+0x1238),%fp0 + fdsqrtw %d5,%fp0 + fdsqrtw %a4@,%fp0 + fdsqrtw %a3@+,%fp0 + fdsqrtw %a2@-,%fp0 fdsqrtw %fp@(8),%fp0 + fdsqrtw %pc@(.+0x1238),%fp0 + fdsqrtd %a4@,%fp0 + fdsqrtd %a3@+,%fp0 + fdsqrtd %a2@-,%fp0 fdsqrtd %fp@(8),%fp0 + fdsqrtd %pc@(.+0x1238),%fp0 + fdsqrtb %d5,%fp0 + fdsqrtb %a4@,%fp0 + fdsqrtb %a3@+,%fp0 + fdsqrtb %a2@-,%fp0 fdsqrtb %fp@(8),%fp0 + fdsqrtb %pc@(.+0x1238),%fp0 fabsd %fp0,%fp0 + fabsl %d5,%fp0 + fabsl %a4@,%fp0 + fabsl %a3@+,%fp0 + fabsl %a2@-,%fp0 fabsl %fp@(8),%fp0 + fabsl %pc@(.+0x1238),%fp0 + fabss %d5,%fp0 + fabss %a4@,%fp0 + fabss %a3@+,%fp0 + fabss %a2@-,%fp0 fabss %fp@(8),%fp0 + fabss %pc@(.+0x1238),%fp0 + fabsw %d5,%fp0 + fabsw %a4@,%fp0 + fabsw %a3@+,%fp0 + fabsw %a2@-,%fp0 fabsw %fp@(8),%fp0 + fabsw %pc@(.+0x1238),%fp0 + fabsd %a4@,%fp0 + fabsd %a3@+,%fp0 + fabsd %a2@-,%fp0 fabsd %fp@(8),%fp0 + fabsd %pc@(.+0x1238),%fp0 + fabsb %d5,%fp0 + fabsb %a4@,%fp0 + fabsb %a3@+,%fp0 + fabsb %a2@-,%fp0 fabsb %fp@(8),%fp0 + fabsb %pc@(.+0x1238),%fp0 fsabsd %fp0,%fp0 + fsabsl %d5,%fp0 + fsabsl %a4@,%fp0 + fsabsl %a3@+,%fp0 + fsabsl %a2@-,%fp0 fsabsl %fp@(8),%fp0 + fsabsl %pc@(.+0x1238),%fp0 + fsabss %d5,%fp0 + fsabss %a4@,%fp0 + fsabss %a3@+,%fp0 + fsabss %a2@-,%fp0 fsabss %fp@(8),%fp0 + fsabss %pc@(.+0x1238),%fp0 + fsabsw %d5,%fp0 + fsabsw %a4@,%fp0 + fsabsw %a3@+,%fp0 + fsabsw %a2@-,%fp0 fsabsw %fp@(8),%fp0 + fsabsw %pc@(.+0x1238),%fp0 + fsabsd %a4@,%fp0 + fsabsd %a3@+,%fp0 + fsabsd %a2@-,%fp0 fsabsd %fp@(8),%fp0 + fsabsd %pc@(.+0x1238),%fp0 + fsabsb %d5,%fp0 + fsabsb %a4@,%fp0 + fsabsb %a3@+,%fp0 + fsabsb %a2@-,%fp0 fsabsb %fp@(8),%fp0 + fsabsb %pc@(.+0x1238),%fp0 fdabsd %fp0,%fp0 + fdabsl %d5,%fp0 + fdabsl %a4@,%fp0 + fdabsl %a3@+,%fp0 + fdabsl %a2@-,%fp0 fdabsl %fp@(8),%fp0 + fdabsl %pc@(.+0x1238),%fp0 + fdabss %d5,%fp0 + fdabss %a4@,%fp0 + fdabss %a3@+,%fp0 + fdabss %a2@-,%fp0 fdabss %fp@(8),%fp0 + fdabss %pc@(.+0x1238),%fp0 + fdabsw %d5,%fp0 + fdabsw %a4@,%fp0 + fdabsw %a3@+,%fp0 + fdabsw %a2@-,%fp0 fdabsw %fp@(8),%fp0 + fdabsw %pc@(.+0x1238),%fp0 + fdabsd %a4@,%fp0 + fdabsd %a3@+,%fp0 + fdabsd %a2@-,%fp0 fdabsd %fp@(8),%fp0 + fdabsd %pc@(.+0x1238),%fp0 + fdabsb %d5,%fp0 + fdabsb %a4@,%fp0 + fdabsb %a3@+,%fp0 + fdabsb %a2@-,%fp0 fdabsb %fp@(8),%fp0 + fdabsb %pc@(.+0x1238),%fp0 fnegd %fp0,%fp0 + fnegl %d5,%fp0 + fnegl %a4@,%fp0 + fnegl %a3@+,%fp0 + fnegl %a2@-,%fp0 fnegl %fp@(8),%fp0 + fnegl %pc@(.+0x1238),%fp0 + fnegs %d5,%fp0 + fnegs %a4@,%fp0 + fnegs %a3@+,%fp0 + fnegs %a2@-,%fp0 fnegs %fp@(8),%fp0 + fnegs %pc@(.+0x1238),%fp0 + fnegw %d5,%fp0 + fnegw %a4@,%fp0 + fnegw %a3@+,%fp0 + fnegw %a2@-,%fp0 fnegw %fp@(8),%fp0 + fnegw %pc@(.+0x1238),%fp0 + fnegd %a4@,%fp0 + fnegd %a3@+,%fp0 + fnegd %a2@-,%fp0 fnegd %fp@(8),%fp0 + fnegd %pc@(.+0x1238),%fp0 + fnegb %d5,%fp0 + fnegb %a4@,%fp0 + fnegb %a3@+,%fp0 + fnegb %a2@-,%fp0 fnegb %fp@(8),%fp0 + fnegb %pc@(.+0x1238),%fp0 fsnegd %fp0,%fp0 + fsnegl %d5,%fp0 + fsnegl %a4@,%fp0 + fsnegl %a3@+,%fp0 + fsnegl %a2@-,%fp0 fsnegl %fp@(8),%fp0 + fsnegl %pc@(.+0x1238),%fp0 + fsnegs %d5,%fp0 + fsnegs %a4@,%fp0 + fsnegs %a3@+,%fp0 + fsnegs %a2@-,%fp0 fsnegs %fp@(8),%fp0 + fsnegs %pc@(.+0x1238),%fp0 + fsnegw %d5,%fp0 + fsnegw %a4@,%fp0 + fsnegw %a3@+,%fp0 + fsnegw %a2@-,%fp0 fsnegw %fp@(8),%fp0 + fsnegw %pc@(.+0x1238),%fp0 + fsnegd %a4@,%fp0 + fsnegd %a3@+,%fp0 + fsnegd %a2@-,%fp0 fsnegd %fp@(8),%fp0 + fsnegd %pc@(.+0x1238),%fp0 + fsnegb %d5,%fp0 + fsnegb %a4@,%fp0 + fsnegb %a3@+,%fp0 + fsnegb %a2@-,%fp0 fsnegb %fp@(8),%fp0 + fsnegb %pc@(.+0x1238),%fp0 fdnegd %fp0,%fp0 + fdnegl %d5,%fp0 + fdnegl %a4@,%fp0 + fdnegl %a3@+,%fp0 + fdnegl %a2@-,%fp0 fdnegl %fp@(8),%fp0 + fdnegl %pc@(.+0x1238),%fp0 + fdnegs %d5,%fp0 + fdnegs %a4@,%fp0 + fdnegs %a3@+,%fp0 + fdnegs %a2@-,%fp0 fdnegs %fp@(8),%fp0 + fdnegs %pc@(.+0x1238),%fp0 + fdnegw %d5,%fp0 + fdnegw %a4@,%fp0 + fdnegw %a3@+,%fp0 + fdnegw %a2@-,%fp0 fdnegw %fp@(8),%fp0 + fdnegw %pc@(.+0x1238),%fp0 + fdnegd %a4@,%fp0 + fdnegd %a3@+,%fp0 + fdnegd %a2@-,%fp0 fdnegd %fp@(8),%fp0 + fdnegd %pc@(.+0x1238),%fp0 + fdnegb %d5,%fp0 + fdnegb %a4@,%fp0 + fdnegb %a3@+,%fp0 + fdnegb %a2@-,%fp0 fdnegb %fp@(8),%fp0 + fdnegb %pc@(.+0x1238),%fp0 fdivd %fp0,%fp0 + fdivl %d5,%fp0 + fdivl %a4@,%fp0 + fdivl %a3@+,%fp0 + fdivl %a2@-,%fp0 fdivl %fp@(8),%fp0 + fdivl %pc@(.+0x1238),%fp0 + fdivs %d5,%fp0 + fdivs %a4@,%fp0 + fdivs %a3@+,%fp0 + fdivs %a2@-,%fp0 fdivs %fp@(8),%fp0 + fdivs %pc@(.+0x1238),%fp0 + fdivw %d5,%fp0 + fdivw %a4@,%fp0 + fdivw %a3@+,%fp0 + fdivw %a2@-,%fp0 fdivw %fp@(8),%fp0 + fdivw %pc@(.+0x1238),%fp0 + fdivd %a4@,%fp0 + fdivd %a3@+,%fp0 + fdivd %a2@-,%fp0 fdivd %fp@(8),%fp0 + fdivd %pc@(.+0x1238),%fp0 + fdivb %d5,%fp0 + fdivb %a4@,%fp0 + fdivb %a3@+,%fp0 + fdivb %a2@-,%fp0 fdivb %fp@(8),%fp0 + fdivb %pc@(.+0x1238),%fp0 fsdivd %fp0,%fp0 + fsdivl %d5,%fp0 + fsdivl %a4@,%fp0 + fsdivl %a3@+,%fp0 + fsdivl %a2@-,%fp0 fsdivl %fp@(8),%fp0 + fsdivl %pc@(.+0x1238),%fp0 + fsdivs %d5,%fp0 + fsdivs %a4@,%fp0 + fsdivs %a3@+,%fp0 + fsdivs %a2@-,%fp0 fsdivs %fp@(8),%fp0 + fsdivs %pc@(.+0x1238),%fp0 + fsdivw %d5,%fp0 + fsdivw %a4@,%fp0 + fsdivw %a3@+,%fp0 + fsdivw %a2@-,%fp0 fsdivw %fp@(8),%fp0 + fsdivw %pc@(.+0x1238),%fp0 + fsdivd %a4@,%fp0 + fsdivd %a3@+,%fp0 + fsdivd %a2@-,%fp0 fsdivd %fp@(8),%fp0 + fsdivd %pc@(.+0x1238),%fp0 + fsdivb %d5,%fp0 + fsdivb %a4@,%fp0 + fsdivb %a3@+,%fp0 + fsdivb %a2@-,%fp0 fsdivb %fp@(8),%fp0 + fsdivb %pc@(.+0x1238),%fp0 fddivd %fp0,%fp0 + fddivl %d5,%fp0 + fddivl %a4@,%fp0 + fddivl %a3@+,%fp0 + fddivl %a2@-,%fp0 fddivl %fp@(8),%fp0 + fddivl %pc@(.+0x1238),%fp0 + fddivs %d5,%fp0 + fddivs %a4@,%fp0 + fddivs %a3@+,%fp0 + fddivs %a2@-,%fp0 fddivs %fp@(8),%fp0 + fddivs %pc@(.+0x1238),%fp0 + fddivw %d5,%fp0 + fddivw %a4@,%fp0 + fddivw %a3@+,%fp0 + fddivw %a2@-,%fp0 fddivw %fp@(8),%fp0 + fddivw %pc@(.+0x1238),%fp0 + fddivd %a4@,%fp0 + fddivd %a3@+,%fp0 + fddivd %a2@-,%fp0 fddivd %fp@(8),%fp0 + fddivd %pc@(.+0x1238),%fp0 + fddivb %d5,%fp0 + fddivb %a4@,%fp0 + fddivb %a3@+,%fp0 + fddivb %a2@-,%fp0 fddivb %fp@(8),%fp0 + fddivb %pc@(.+0x1238),%fp0 faddd %fp0,%fp0 + faddl %d5,%fp0 + faddl %a4@,%fp0 + faddl %a3@+,%fp0 + faddl %a2@-,%fp0 faddl %fp@(8),%fp0 + faddl %pc@(.+0x1238),%fp0 + fadds %d5,%fp0 + fadds %a4@,%fp0 + fadds %a3@+,%fp0 + fadds %a2@-,%fp0 fadds %fp@(8),%fp0 + fadds %pc@(.+0x1238),%fp0 + faddw %d5,%fp0 + faddw %a4@,%fp0 + faddw %a3@+,%fp0 + faddw %a2@-,%fp0 faddw %fp@(8),%fp0 + faddw %pc@(.+0x1238),%fp0 + faddd %a4@,%fp0 + faddd %a3@+,%fp0 + faddd %a2@-,%fp0 faddd %fp@(8),%fp0 + faddd %pc@(.+0x1238),%fp0 + faddb %d5,%fp0 + faddb %a4@,%fp0 + faddb %a3@+,%fp0 + faddb %a2@-,%fp0 faddb %fp@(8),%fp0 + faddb %pc@(.+0x1238),%fp0 fsaddd %fp0,%fp0 + fsaddl %d5,%fp0 + fsaddl %a4@,%fp0 + fsaddl %a3@+,%fp0 + fsaddl %a2@-,%fp0 fsaddl %fp@(8),%fp0 + fsaddl %pc@(.+0x1238),%fp0 + fsadds %d5,%fp0 + fsadds %a4@,%fp0 + fsadds %a3@+,%fp0 + fsadds %a2@-,%fp0 fsadds %fp@(8),%fp0 + fsadds %pc@(.+0x1238),%fp0 + fsaddw %d5,%fp0 + fsaddw %a4@,%fp0 + fsaddw %a3@+,%fp0 + fsaddw %a2@-,%fp0 fsaddw %fp@(8),%fp0 + fsaddw %pc@(.+0x1238),%fp0 + fsaddd %a4@,%fp0 + fsaddd %a3@+,%fp0 + fsaddd %a2@-,%fp0 fsaddd %fp@(8),%fp0 + fsaddd %pc@(.+0x1238),%fp0 + fsaddb %d5,%fp0 + fsaddb %a4@,%fp0 + fsaddb %a3@+,%fp0 + fsaddb %a2@-,%fp0 fsaddb %fp@(8),%fp0 + fsaddb %pc@(.+0x1238),%fp0 fdaddd %fp0,%fp0 + fdaddl %d5,%fp0 + fdaddl %a4@,%fp0 + fdaddl %a3@+,%fp0 + fdaddl %a2@-,%fp0 fdaddl %fp@(8),%fp0 + fdaddl %pc@(.+0x1238),%fp0 + fdadds %d5,%fp0 + fdadds %a4@,%fp0 + fdadds %a3@+,%fp0 + fdadds %a2@-,%fp0 fdadds %fp@(8),%fp0 + fdadds %pc@(.+0x1238),%fp0 + fdaddw %d5,%fp0 + fdaddw %a4@,%fp0 + fdaddw %a3@+,%fp0 + fdaddw %a2@-,%fp0 fdaddw %fp@(8),%fp0 + fdaddw %pc@(.+0x1238),%fp0 + fdaddd %a4@,%fp0 + fdaddd %a3@+,%fp0 + fdaddd %a2@-,%fp0 fdaddd %fp@(8),%fp0 + fdaddd %pc@(.+0x1238),%fp0 + fdaddb %d5,%fp0 + fdaddb %a4@,%fp0 + fdaddb %a3@+,%fp0 + fdaddb %a2@-,%fp0 fdaddb %fp@(8),%fp0 + fdaddb %pc@(.+0x1238),%fp0 fmuld %fp0,%fp0 + fmull %d5,%fp0 + fmull %a4@,%fp0 + fmull %a3@+,%fp0 + fmull %a2@-,%fp0 fmull %fp@(8),%fp0 + fmull %pc@(.+0x1238),%fp0 + fmuls %d5,%fp0 + fmuls %a4@,%fp0 + fmuls %a3@+,%fp0 + fmuls %a2@-,%fp0 fmuls %fp@(8),%fp0 + fmuls %pc@(.+0x1238),%fp0 + fmulw %d5,%fp0 + fmulw %a4@,%fp0 + fmulw %a3@+,%fp0 + fmulw %a2@-,%fp0 fmulw %fp@(8),%fp0 + fmulw %pc@(.+0x1238),%fp0 + fmuld %a4@,%fp0 + fmuld %a3@+,%fp0 + fmuld %a2@-,%fp0 fmuld %fp@(8),%fp0 + fmuld %pc@(.+0x1238),%fp0 + fmulb %d5,%fp0 + fmulb %a4@,%fp0 + fmulb %a3@+,%fp0 + fmulb %a2@-,%fp0 fmulb %fp@(8),%fp0 + fmulb %pc@(.+0x1238),%fp0 fsmuld %fp0,%fp0 + fsmull %d5,%fp0 + fsmull %a4@,%fp0 + fsmull %a3@+,%fp0 + fsmull %a2@-,%fp0 fsmull %fp@(8),%fp0 + fsmull %pc@(.+0x1238),%fp0 + fsmuls %d5,%fp0 + fsmuls %a4@,%fp0 + fsmuls %a3@+,%fp0 + fsmuls %a2@-,%fp0 fsmuls %fp@(8),%fp0 + fsmuls %pc@(.+0x1238),%fp0 + fsmulw %d5,%fp0 + fsmulw %a4@,%fp0 + fsmulw %a3@+,%fp0 + fsmulw %a2@-,%fp0 fsmulw %fp@(8),%fp0 + fsmulw %pc@(.+0x1238),%fp0 + fsmuld %a4@,%fp0 + fsmuld %a3@+,%fp0 + fsmuld %a2@-,%fp0 fsmuld %fp@(8),%fp0 + fsmuld %pc@(.+0x1238),%fp0 + fsmulb %d5,%fp0 + fsmulb %a4@,%fp0 + fsmulb %a3@+,%fp0 + fsmulb %a2@-,%fp0 fsmulb %fp@(8),%fp0 + fsmulb %pc@(.+0x1238),%fp0 fdmuld %fp0,%fp0 + fdmull %d5,%fp0 + fdmull %a4@,%fp0 + fdmull %a3@+,%fp0 + fdmull %a2@-,%fp0 fdmull %fp@(8),%fp0 + fdmull %pc@(.+0x1238),%fp0 + fdmuls %d5,%fp0 + fdmuls %a4@,%fp0 + fdmuls %a3@+,%fp0 + fdmuls %a2@-,%fp0 fdmuls %fp@(8),%fp0 + fdmuls %pc@(.+0x1238),%fp0 + fdmulw %d5,%fp0 + fdmulw %a4@,%fp0 + fdmulw %a3@+,%fp0 + fdmulw %a2@-,%fp0 fdmulw %fp@(8),%fp0 + fdmulw %pc@(.+0x1238),%fp0 + fdmuld %a4@,%fp0 + fdmuld %a3@+,%fp0 + fdmuld %a2@-,%fp0 fdmuld %fp@(8),%fp0 + fdmuld %pc@(.+0x1238),%fp0 + fdmulb %d5,%fp0 + fdmulb %a4@,%fp0 + fdmulb %a3@+,%fp0 + fdmulb %a2@-,%fp0 fdmulb %fp@(8),%fp0 + fdmulb %pc@(.+0x1238),%fp0 fsubd %fp0,%fp0 + fsubl %d5,%fp0 + fsubl %a4@,%fp0 + fsubl %a3@+,%fp0 + fsubl %a2@-,%fp0 fsubl %fp@(8),%fp0 + fsubl %pc@(.+0x1238),%fp0 + fsubs %d5,%fp0 + fsubs %a4@,%fp0 + fsubs %a3@+,%fp0 + fsubs %a2@-,%fp0 fsubs %fp@(8),%fp0 + fsubs %pc@(.+0x1238),%fp0 + fsubw %d5,%fp0 + fsubw %a4@,%fp0 + fsubw %a3@+,%fp0 + fsubw %a2@-,%fp0 fsubw %fp@(8),%fp0 + fsubw %pc@(.+0x1238),%fp0 + fsubd %a4@,%fp0 + fsubd %a3@+,%fp0 + fsubd %a2@-,%fp0 fsubd %fp@(8),%fp0 + fsubd %pc@(.+0x1238),%fp0 + fsubb %d5,%fp0 + fsubb %a4@,%fp0 + fsubb %a3@+,%fp0 + fsubb %a2@-,%fp0 fsubb %fp@(8),%fp0 + fsubb %pc@(.+0x1238),%fp0 fssubd %fp0,%fp0 + fssubl %d5,%fp0 + fssubl %a4@,%fp0 + fssubl %a3@+,%fp0 + fssubl %a2@-,%fp0 fssubl %fp@(8),%fp0 + fssubl %pc@(.+0x1238),%fp0 + fssubs %d5,%fp0 + fssubs %a4@,%fp0 + fssubs %a3@+,%fp0 + fssubs %a2@-,%fp0 fssubs %fp@(8),%fp0 + fssubs %pc@(.+0x1238),%fp0 + fssubw %d5,%fp0 + fssubw %a4@,%fp0 + fssubw %a3@+,%fp0 + fssubw %a2@-,%fp0 fssubw %fp@(8),%fp0 + fssubw %pc@(.+0x1238),%fp0 + fssubd %a4@,%fp0 + fssubd %a3@+,%fp0 + fssubd %a2@-,%fp0 fssubd %fp@(8),%fp0 + fssubd %pc@(.+0x1238),%fp0 + fssubb %d5,%fp0 + fssubb %a4@,%fp0 + fssubb %a3@+,%fp0 + fssubb %a2@-,%fp0 fssubb %fp@(8),%fp0 + fssubb %pc@(.+0x1238),%fp0 fdsubd %fp0,%fp0 + fdsubl %d5,%fp0 + fdsubl %a4@,%fp0 + fdsubl %a3@+,%fp0 + fdsubl %a2@-,%fp0 fdsubl %fp@(8),%fp0 + fdsubl %pc@(.+0x1238),%fp0 + fdsubs %d5,%fp0 + fdsubs %a4@,%fp0 + fdsubs %a3@+,%fp0 + fdsubs %a2@-,%fp0 fdsubs %fp@(8),%fp0 + fdsubs %pc@(.+0x1238),%fp0 + fdsubw %d5,%fp0 + fdsubw %a4@,%fp0 + fdsubw %a3@+,%fp0 + fdsubw %a2@-,%fp0 fdsubw %fp@(8),%fp0 + fdsubw %pc@(.+0x1238),%fp0 + fdsubd %a4@,%fp0 + fdsubd %a3@+,%fp0 + fdsubd %a2@-,%fp0 fdsubd %fp@(8),%fp0 + fdsubd %pc@(.+0x1238),%fp0 + fdsubb %d5,%fp0 + fdsubb %a4@,%fp0 + fdsubb %a3@+,%fp0 + fdsubb %a2@-,%fp0 fdsubb %fp@(8),%fp0 + fdsubb %pc@(.+0x1238),%fp0 fmoved %fp0,%fp0 + fmovel %d5,%fp0 + fmovel %a4@,%fp0 + fmovel %a3@+,%fp0 + fmovel %a2@-,%fp0 fmovel %fp@(8),%fp0 + fmovel %pc@(.+0x1238),%fp0 + fmoves %d5,%fp0 + fmoves %a4@,%fp0 + fmoves %a3@+,%fp0 + fmoves %a2@-,%fp0 fmoves %fp@(8),%fp0 + fmoves %pc@(.+0x1238),%fp0 + fmovew %d5,%fp0 + fmovew %a4@,%fp0 + fmovew %a3@+,%fp0 + fmovew %a2@-,%fp0 fmovew %fp@(8),%fp0 + fmovew %pc@(.+0x1238),%fp0 + fmoved %a4@,%fp0 + fmoved %a3@+,%fp0 + fmoved %a2@-,%fp0 fmoved %fp@(8),%fp0 + fmoved %pc@(.+0x1238),%fp0 + fmoveb %d5,%fp0 + fmoveb %a4@,%fp0 + fmoveb %a3@+,%fp0 + fmoveb %a2@-,%fp0 fmoveb %fp@(8),%fp0 + fmoveb %pc@(.+0x1238),%fp0 fsmoved %fp0,%fp0 + fsmovel %d5,%fp0 + fsmovel %a4@,%fp0 + fsmovel %a3@+,%fp0 + fsmovel %a2@-,%fp0 fsmovel %fp@(8),%fp0 + fsmovel %pc@(.+0x1238),%fp0 + fsmoves %d5,%fp0 + fsmoves %a4@,%fp0 + fsmoves %a3@+,%fp0 + fsmoves %a2@-,%fp0 fsmoves %fp@(8),%fp0 + fsmoves %pc@(.+0x1238),%fp0 + fsmovew %d5,%fp0 + fsmovew %a4@,%fp0 + fsmovew %a3@+,%fp0 + fsmovew %a2@-,%fp0 fsmovew %fp@(8),%fp0 + fsmovew %pc@(.+0x1238),%fp0 + fsmoved %a4@,%fp0 + fsmoved %a3@+,%fp0 + fsmoved %a2@-,%fp0 fsmoved %fp@(8),%fp0 + fsmoved %pc@(.+0x1238),%fp0 + fsmoveb %d5,%fp0 + fsmoveb %a4@,%fp0 + fsmoveb %a3@+,%fp0 + fsmoveb %a2@-,%fp0 fsmoveb %fp@(8),%fp0 + fsmoveb %pc@(.+0x1238),%fp0 fdmoved %fp0,%fp0 + fdmovel %d5,%fp0 + fdmovel %a4@,%fp0 + fdmovel %a3@+,%fp0 + fdmovel %a2@-,%fp0 fdmovel %fp@(8),%fp0 + fdmovel %pc@(.+0x1238),%fp0 + fdmoves %d5,%fp0 + fdmoves %a4@,%fp0 + fdmoves %a3@+,%fp0 + fdmoves %a2@-,%fp0 fdmoves %fp@(8),%fp0 + fdmoves %pc@(.+0x1238),%fp0 + fdmovew %d5,%fp0 + fdmovew %a4@,%fp0 + fdmovew %a3@+,%fp0 + fdmovew %a2@-,%fp0 fdmovew %fp@(8),%fp0 + fdmovew %pc@(.+0x1238),%fp0 + fdmoved %a4@,%fp0 + fdmoved %a3@+,%fp0 + fdmoved %a2@-,%fp0 fdmoved %fp@(8),%fp0 + fdmoved %pc@(.+0x1238),%fp0 + fdmoveb %d5,%fp0 + fdmoveb %a4@,%fp0 + fdmoveb %a3@+,%fp0 + fdmoveb %a2@-,%fp0 fdmoveb %fp@(8),%fp0 + fdmoveb %pc@(.+0x1238),%fp0 fintd %fp0,%fp0 + fintl %d5,%fp0 + fintl %a4@,%fp0 + fintl %a3@+,%fp0 + fintl %a2@-,%fp0 fintl %fp@(8),%fp0 + fintl %pc@(.+0x1238),%fp0 + fints %d5,%fp0 + fints %a4@,%fp0 + fints %a3@+,%fp0 + fints %a2@-,%fp0 fints %fp@(8),%fp0 + fints %pc@(.+0x1238),%fp0 + fintw %d5,%fp0 + fintw %a4@,%fp0 + fintw %a3@+,%fp0 + fintw %a2@-,%fp0 fintw %fp@(8),%fp0 + fintw %pc@(.+0x1238),%fp0 + fintd %a4@,%fp0 + fintd %a3@+,%fp0 + fintd %a2@-,%fp0 fintd %fp@(8),%fp0 + fintd %pc@(.+0x1238),%fp0 + fintb %d5,%fp0 + fintb %a4@,%fp0 + fintb %a3@+,%fp0 + fintb %a2@-,%fp0 fintb %fp@(8),%fp0 + fintb %pc@(.+0x1238),%fp0 fintrzd %fp0,%fp0 + fintrzl %d5,%fp0 + fintrzl %a4@,%fp0 + fintrzl %a3@+,%fp0 + fintrzl %a2@-,%fp0 fintrzl %fp@(8),%fp0 + fintrzl %pc@(.+0x1238),%fp0 + fintrzs %d5,%fp0 + fintrzs %a4@,%fp0 + fintrzs %a3@+,%fp0 + fintrzs %a2@-,%fp0 fintrzs %fp@(8),%fp0 + fintrzs %pc@(.+0x1238),%fp0 + fintrzw %d5,%fp0 + fintrzw %a4@,%fp0 + fintrzw %a3@+,%fp0 + fintrzw %a2@-,%fp0 fintrzw %fp@(8),%fp0 + fintrzw %pc@(.+0x1238),%fp0 + fintrzd %a4@,%fp0 + fintrzd %a3@+,%fp0 + fintrzd %a2@-,%fp0 fintrzd %fp@(8),%fp0 + fintrzd %pc@(.+0x1238),%fp0 + fintrzb %d5,%fp0 + fintrzb %a4@,%fp0 + fintrzb %a3@+,%fp0 + fintrzb %a2@-,%fp0 fintrzb %fp@(8),%fp0 + fintrzb %pc@(.+0x1238),%fp0 fcmpd %fp0,%fp0 + fcmpl %d5,%fp0 + fcmpl %a4@,%fp0 + fcmpl %a3@+,%fp0 + fcmpl %a2@-,%fp0 fcmpl %fp@(8),%fp0 + fcmpl %pc@(.+0x1238),%fp0 + fcmps %d5,%fp0 + fcmps %a4@,%fp0 + fcmps %a3@+,%fp0 + fcmps %a2@-,%fp0 fcmps %fp@(8),%fp0 + fcmps %pc@(.+0x1238),%fp0 + fcmpw %d5,%fp0 + fcmpw %a4@,%fp0 + fcmpw %a3@+,%fp0 + fcmpw %a2@-,%fp0 fcmpw %fp@(8),%fp0 + fcmpw %pc@(.+0x1238),%fp0 + fcmpd %a4@,%fp0 + fcmpd %a3@+,%fp0 + fcmpd %a2@-,%fp0 fcmpd %fp@(8),%fp0 + fcmpd %pc@(.+0x1238),%fp0 + fcmpb %d5,%fp0 + fcmpb %a4@,%fp0 + fcmpb %a3@+,%fp0 + fcmpb %a2@-,%fp0 fcmpb %fp@(8),%fp0 + fcmpb %pc@(.+0x1238),%fp0 fmovemd %fp0-%fp3/%fp6,%fp@(8) fmovemd %fp@(8),%fp5/%fp4/%fp2 fmovemd #0x27,%fp@(8) diff --git a/gas/testsuite/gas/m68k/mcf-trap.d b/gas/testsuite/gas/m68k/mcf-trap.d new file mode 100644 index 000000000000..63d18fd7bfd4 --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-trap.d @@ -0,0 +1,15 @@ +#name: mcf-trap +#objdump: -d +#as: -m5208 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ 0-9a-f]+: 51fc t[rap]*f +[ 0-9a-f]+: 51fa 1234 t[rap]*fw #4660 +[ 0-9a-f]+: 51fb 1234 5678 t[rap]*fl #305419896 +[ 0-9a-f]+: 51fc t[rap]*f +[ 0-9a-f]+: 51fa 1234 t[rap]*fw #4660 +[ 0-9a-f]+: 51fb 1234 5678 t[rap]*fl #305419896 diff --git a/gas/testsuite/gas/m68k/mcf-trap.s b/gas/testsuite/gas/m68k/mcf-trap.s new file mode 100644 index 000000000000..a5d6acc7db86 --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-trap.s @@ -0,0 +1,9 @@ + # the m68k compatible names + trapf + trapf.w #0x1234 + trapf.l #0x12345678 + + # the coldfire specific names + tpf + tpf.w #0x1234 + tpf.l #0x12345678 diff --git a/gas/testsuite/gas/m68k/mcf-wdebug.d b/gas/testsuite/gas/m68k/mcf-wdebug.d new file mode 100644 index 000000000000..257d1e386031 --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-wdebug.d @@ -0,0 +1,11 @@ +#name: mcf-wdebug +#objdump: -d +#as: -m5208 + +.*: file format .* + +Disassembly of section .text: + +0+ <foo>: + 0: fbd0 0003 wdebugl %a0@ + 4: fbd0 0003 wdebugl %a0@ diff --git a/gas/testsuite/gas/m68k/mcf-wdebug.s b/gas/testsuite/gas/m68k/mcf-wdebug.s new file mode 100644 index 000000000000..36b9f27df9d9 --- /dev/null +++ b/gas/testsuite/gas/m68k/mcf-wdebug.s @@ -0,0 +1,6 @@ +# Check that gas recognizes both wdebug and wdebug.l. + .text + .globl foo +foo: + wdebug (%a0) + wdebug.l (%a0) diff --git a/gas/testsuite/gas/m68k/p3041.d b/gas/testsuite/gas/m68k/p3041.d new file mode 100644 index 000000000000..b4a41c4a01ee --- /dev/null +++ b/gas/testsuite/gas/m68k/p3041.d @@ -0,0 +1,15 @@ +#name: PR 3041 +#objdump: -dr + +.*: file format .* + +Disassembly of section .text: + +0+ <.*>: + 0: 4ef9 0000 0002 [ ]+jmp 2 <mylabel-0x6> + 2: .* mylabel + 6: 4e71 [ ]+nop + +0+8 <mylabel>: + 8: 4e71 [ ]+nop + a: 4e71 [ ]+nop diff --git a/gas/testsuite/gas/m68k/p3041.s b/gas/testsuite/gas/m68k/p3041.s new file mode 100644 index 000000000000..96a8910b104c --- /dev/null +++ b/gas/testsuite/gas/m68k/p3041.s @@ -0,0 +1,6 @@ + jmp mylabel+2 + nop + .weak mylabel +mylabel: + nop + nop diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp index e175ad9a53ec..62392ec3b48c 100644 --- a/gas/testsuite/gas/macros/macros.exp +++ b/gas/testsuite/gas/macros/macros.exp @@ -1,18 +1,5 @@ # Run some tests of gas macros. -proc run_list_test { name opts } { - global srcdir subdir - set testname "macros $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } { run_dump_test test1 } @@ -69,6 +56,7 @@ run_dump_test app3 run_dump_test app4 run_list_test badarg "" + case $target_triplet in { { *c54x*-*-* } { } { *c4x*-*-* } { } diff --git a/gas/testsuite/gas/maxq10/maxq10.exp b/gas/testsuite/gas/maxq10/maxq10.exp index 482bd4ca2c23..8887b53494eb 100644 --- a/gas/testsuite/gas/maxq10/maxq10.exp +++ b/gas/testsuite/gas/maxq10/maxq10.exp @@ -1,19 +1,6 @@ # # MAXQ10 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "maxq10 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - proc gas_64_check { } { global NM global NMFLAGS diff --git a/gas/testsuite/gas/maxq20/maxq20.exp b/gas/testsuite/gas/maxq20/maxq20.exp index d2857f617b96..6d952e9e3ed5 100644 --- a/gas/testsuite/gas/maxq20/maxq20.exp +++ b/gas/testsuite/gas/maxq20/maxq20.exp @@ -1,19 +1,6 @@ # # MAXQ20 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "maxq20 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - proc gas_64_check { } { global NM global NMFLAGS diff --git a/gas/testsuite/gas/mcore/allinsn.d b/gas/testsuite/gas/mcore/allinsn.d index 1565ea5d5fe3..a53805bae2f5 100644 --- a/gas/testsuite/gas/mcore/allinsn.d +++ b/gas/testsuite/gas/mcore/allinsn.d @@ -40,7 +40,7 @@ Disassembly of section \.text: 14: 300f bclri r15, 0 0+016 <bf>: - 16: eff4 bf 0x0 + 16: eff4 bf 0x.*0 0+018 <bgeni>: 18: 3270 bgeni r0, 7 @@ -64,7 +64,7 @@ Disassembly of section \.text: 24: 2df3 bmaski r3, 31 0+026 <br>: - 26: f7ff br 0x26 + 26: f7ff br 0x.*26 0+028 <brev>: 28: 00f4 brev r4 @@ -73,10 +73,10 @@ Disassembly of section \.text: 2a: 35e5 bseti r5, 30 0+02c <bsr>: - 2c: ffe9 bsr 0x0 + 2c: ffe9 bsr 0x.*0.* 0+02e <bt>: - 2e: e7e8 bt 0x0 + 2e: e7e8 bt 0x.*0 0+030 <btsti>: 30: 37b6 btsti r6, 27 @@ -148,7 +148,7 @@ Disassembly of section \.text: 5c: 150f ixw r15, r0 0+05e <jbf>: - 5e: efd0 bf 0x0 + 5e: efd0 bf 0x.*0 0+060 <jbr>: 60: f00e br 0x7e @@ -202,10 +202,10 @@ Disassembly of section \.text: 80: 048e loopt r8, 0x64 0+082 <LRW>: - 82: 7903 lrw r9, (0x86|0x0 // from address pool at 0x90) + 82: 7901 lrw r9, 0x3C0C1BBA 0+084 <lrw>: - 84: 7904 lrw r9, 0x4321 + 84: 7903 lrw r9, 0x4321 0+086 <foolit>: 86: 1234 mov r4, r3 @@ -218,184 +218,181 @@ Disassembly of section \.text: 8c: 0000 bkpt 8c: ADDR32 \.text 8e: 0000 bkpt - 90: (0000 bkpt|0086 dect r6) - 90: ADDR32 \.text(\+0x86)? + 90: 4321 \.short 0x4321 92: 0000 bkpt - 94: 4321 \.short 0x4321 - 96: 0000 bkpt -0+098 <lsli>: - 98: 3dfd lsli r13, 31 +0+094 <lsli>: + 94: 3dfd lsli r13, 31 -0+09a <lsr>: - 9a: 0bfe lsr r14, r15 +0+096 <lsr>: + 96: 0bfe lsr r14, r15 -0+09c <lsrc>: - 9c: 3e00 lsrc r0 +0+098 <lsrc>: + 98: 3e00 lsrc r0 -0+09e <lsri>: - 9e: 3e11 lsri r1, 1 +0+09a <lsri>: + 9a: 3e11 lsri r1, 1 -0+0a0 <mclri>: - a0: 3064 bclri r4, 6 +0+09c <mclri>: + 9c: 3064 bclri r4, 6 -0+0a2 <mfcr>: - a2: 1002 mfcr r2, psr +0+09e <mfcr>: + 9e: 1002 mfcr r2, psr -0+0a4 <mov>: - a4: 1243 mov r3, r4 +0+0a0 <mov>: + a0: 1243 mov r3, r4 -0+0a6 <movf>: - a6: 0a65 movf r5, r6 +0+0a2 <movf>: + a2: 0a65 movf r5, r6 -0+0a8 <movi>: - a8: 67f7 movi r7, 127 +0+0a4 <movi>: + a4: 67f7 movi r7, 127 -0+0aa <movt>: - aa: 0298 movt r8, r9 +0+0a6 <movt>: + a6: 0298 movt r8, r9 -0+0ac <mtcr>: - ac: 180a mtcr r10, psr +0+0a8 <mtcr>: + a8: 180a mtcr r10, psr -0+0ae <mult>: - ae: 03cb mult r11, r12 +0+0aa <mult>: + aa: 03cb mult r11, r12 -0+0b0 <mvc>: - b0: 002d mvc r13 +0+0ac <mvc>: + ac: 002d mvc r13 -0+0b2 <mvcv>: - b2: 003e mvcv r14 +0+0ae <mvcv>: + ae: 003e mvcv r14 -0+0b4 <neg>: - b4: 2802 rsubi r2, 0 +0+0b0 <neg>: + b0: 2802 rsubi r2, 0 -0+0b6 <not>: - b6: 01ff not r15 +0+0b2 <not>: + b2: 01ff not r15 -0+0b8 <or>: - b8: 1e10 or r0, r1 +0+0b4 <or>: + b4: 1e10 or r0, r1 -0+0ba <rfi>: - ba: 0003 rfi +0+0b6 <rfi>: + b6: 0003 rfi -0+0bc <rolc>: - bc: 0666 addc r6, r6 +0+0b8 <rolc>: + b8: 0666 addc r6, r6 -0+0be <rori>: - be: 39a9 rotli r9, 26 +0+0ba <rori>: + ba: 39a9 rotli r9, 26 -0+0c0 <rotlc>: - c0: 0666 addc r6, r6 +0+0bc <rotlc>: + bc: 0666 addc r6, r6 -0+0c2 <rotli>: - c2: 38a2 rotli r2, 10 +0+0be <rotli>: + be: 38a2 rotli r2, 10 -0+0c4 <rotri>: - c4: 39a9 rotli r9, 26 +0+0c0 <rotri>: + c0: 39a9 rotli r9, 26 -0+0c6 <rsub>: - c6: 1443 rsub r3, r4 +0+0c2 <rsub>: + c2: 1443 rsub r3, r4 -0+0c8 <rsubi>: - c8: 2805 rsubi r5, 0 +0+0c4 <rsubi>: + c4: 2805 rsubi r5, 0 -0+0ca <rte>: - ca: 0002 rte +0+0c6 <rte>: + c6: 0002 rte -0+0cc <rts>: - cc: 00cf jmp r15 +0+0c8 <rts>: + c8: 00cf jmp r15 -0+0ce <setc>: - ce: 0c00 cmphs r0, r0 +0+0ca <setc>: + ca: 0c00 cmphs r0, r0 -0+0d0 <sextb>: - d0: 0156 sextb r6 +0+0cc <sextb>: + cc: 0156 sextb r6 -0+0d2 <sexth>: - d2: 0177 sexth r7 +0+0ce <sexth>: + ce: 0177 sexth r7 -0+0d4 <st\.b>: - d4: b809 stb r8, \(r9, 0\) +0+0d0 <st\.b>: + d0: b809 stb r8, \(r9, 0\) -0+0d6 <st\.h>: - d6: da1b sth r10, \(r11, 2\) +0+0d2 <st\.h>: + d2: da1b sth r10, \(r11, 2\) -0+0d8 <st\.w>: - d8: 9c1d st r12, \(r13, 4\) +0+0d4 <st\.w>: + d4: 9c1d st r12, \(r13, 4\) -0+0da <stb>: - da: beff stb r14, \(r15, 15\) +0+0d6 <stb>: + d6: beff stb r14, \(r15, 15\) -0+0dc <sth>: - dc: d0f1 sth r0, \(r1, 30\) +0+0d8 <sth>: + d8: d0f1 sth r0, \(r1, 30\) -0+0de <stw>: - de: 92f3 st r2, \(r3, 60\) +0+0da <stw>: + da: 92f3 st r2, \(r3, 60\) -0+0e0 <st>: - e0: 9405 st r4, \(r5, 0\) +0+0dc <st>: + dc: 9405 st r4, \(r5, 0\) -0+0e2 <stm>: - e2: 007e stm r14-r15, \(r0\) +0+0de <stm>: + de: 007e stm r14-r15, \(r0\) -0+0e4 <stop>: - e4: 0004 stop +0+0e0 <stop>: + e0: 0004 stop -0+0e6 <stq>: - e6: 0051 stq r4-r7, \(r1\) +0+0e2 <stq>: + e2: 0051 stq r4-r7, \(r1\) -0+0e8 <subc>: - e8: 07d7 subc r7, r13 +0+0e4 <subc>: + e4: 07d7 subc r7, r13 -0+0ea <subi>: - ea: 25fe subi r14, 32 +0+0e6 <subi>: + e6: 25fe subi r14, 32 -0+0ec <subu>: - ec: 0539 subu r9, r3 +0+0e8 <subu>: + e8: 0539 subu r9, r3 -0+0ee <sync>: - ee: 0001 sync +0+0ea <sync>: + ea: 0001 sync -0+0f0 <tstlt>: - f0: 37f5 btsti r5, 31 +0+0ec <tstlt>: + ec: 37f5 btsti r5, 31 -0+0f2 <tstne>: - f2: 2a07 cmpnei r7, 0 +0+0ee <tstne>: + ee: 2a07 cmpnei r7, 0 -0+0f4 <trap>: - f4: 000a trap 2 +0+0f0 <trap>: + f0: 000a trap 2 -0+0f6 <tst>: - f6: 0eee tst r14, r14 +0+0f2 <tst>: + f2: 0eee tst r14, r14 -0+0f8 <tstnbz>: - f8: 0192 tstnbz r2 +0+0f4 <tstnbz>: + f4: 0192 tstnbz r2 -0+0fa <wait>: - fa: 0005 wait +0+0f6 <wait>: + f6: 0005 wait -0+0fc <xor>: - fc: 170f xor r15, r0 +0+0f8 <xor>: + f8: 170f xor r15, r0 -0+0fe <xsr>: - fe: 380b xsr r11 +0+0fa <xsr>: + fa: 380b xsr r11 -0+0100 <xtrb0>: - 100: 0131 xtrb0 r1, r1 +0+0fc <xtrb0>: + fc: 0131 xtrb0 r1, r1 -0+0102 <xtrb1>: - 102: 0122 xtrb1 r1, r2 +0+0fe <xtrb1>: + fe: 0122 xtrb1 r1, r2 -0+0104 <xtrb2>: - 104: 0110 xtrb2 r1, r0 +0+0100 <xtrb2>: + 100: 0110 xtrb2 r1, r0 -0+0106 <xtrb3>: - 106: 010d xtrb3 r1, r13 +0+0102 <xtrb3>: + 102: 010d xtrb3 r1, r13 -0+0108 <zextb>: - 108: 0148 zextb r8 +0+0104 <zextb>: + 104: 0148 zextb r8 -0+010a <zexth>: - 10a: 0164 zexth r4 - 10c: 0f00 cmpne r0, r0 - 10e: 0f00 cmpne r0, r0 +0+0106 <zexth>: + 106: 0164 zexth r4 + 108: 0f00 cmpne r0, r0 + 10a: 0f00 cmpne r0, r0 diff --git a/gas/testsuite/gas/mcore/allinsn.s b/gas/testsuite/gas/mcore/allinsn.s index 84068404e74a..e9196e750754 100644 --- a/gas/testsuite/gas/mcore/allinsn.s +++ b/gas/testsuite/gas/mcore/allinsn.s @@ -13,11 +13,11 @@ footext: test addc "r1,r2" // A double forward slash starts a line comment test addi "r3, 1" # So does a hash test addu "r4, r5" // White space between operands should be ignored - test and "r6,r7" ; test andi "r8,#2" // A semicolon seperates statements + test and "r6,r7" ; test andi "r8,2" // A semicolon seperates statements test andn "r9, r10" test asr "r11, R12" // Uppercase R is allowed as a register prefix test asrc "r13" - test asri "r14,#0x1f" + test asri "r14,0x1f" test bclri "r15,0" test bf footext test bgeni "sp, 7" // r0 can also be refered to as 'sp' @@ -25,7 +25,7 @@ footext: test BGENi "r0, 31" // mnemonics should not be allowed, but we relax this... test bgenr "r1, r2" test bkpt - test bmaski "r3,#8" + test bmaski "r3,8" test BMASKI "r3,0x1f" test br . // Dot means the current address test brev r4 @@ -64,9 +64,9 @@ footext: test jsr r2 test jsri footext test ld.b "r3,(r4,0)" - test ld.h "r5 , ( r6, #2)" + test ld.h "r5 , ( r6, 2)" test ld.w "r7, (r8, 0x4)" - test ldb "r9,(r10,#0xf)" + test ldb "r9,(r10,0xf)" test ldh "r11, (r12, 30)" test ld "r13, (r14, 20)" test ldw "r13, (r14, 60)" @@ -104,7 +104,7 @@ foolit: test rolc "r6, 1" test rori "r9, 6" test rotlc "r6, 1" - test rotli "r2, #10" + test rotli "r2, 10" test rotri "r9, 6" test rsub "r3, r4" test rsubi "r5, 0x0" diff --git a/gas/testsuite/gas/mep/allinsn.d b/gas/testsuite/gas/mep/allinsn.d new file mode 100644 index 000000000000..3a1f62c30609 --- /dev/null +++ b/gas/testsuite/gas/mep/allinsn.d @@ -0,0 +1,1345 @@ +#as: +#objdump: -dr +#name: allinsn + +.*: +file format .* + +Disassembly of section .text: + +00000000 <sb>: + 0: 07 88 sb \$7,\(\$8\) + 2: 05 98 sb \$5,\(\$9\) + 4: 07 e8 sb \$7,\(\$gp\) + 6: 0e 88 sb \$gp,\(\$8\) + 8: 0f e8 sb \$sp,\(\$gp\) + +0000000a <sh>: + a: 03 89 sh \$3,\(\$8\) + c: 0c 19 sh \$12,\(\$1\) + e: 0d 29 sh \$tp,\(\$2\) + 10: 02 89 sh \$2,\(\$8\) + 12: 0c a9 sh \$12,\(\$10\) + +00000014 <sw>: + 14: 0b 0a sw \$11,\(\$0\) + 16: 03 7a sw \$3,\(\$7\) + 18: 0d ea sw \$tp,\(\$gp\) + 1a: 08 9a sw \$8,\(\$9\) + 1c: 0e 8a sw \$gp,\(\$8\) + +0000001e <lb>: + 1e: 0c bc lb \$12,\(\$11\) + 20: 09 2c lb \$9,\(\$2\) + 22: 08 bc lb \$8,\(\$11\) + 24: 0e 2c lb \$gp,\(\$2\) + 26: 02 cc lb \$2,\(\$12\) + +00000028 <lh>: + 28: 0f 8d lh \$sp,\(\$8\) + 2a: 03 ad lh \$3,\(\$10\) + 2c: 09 fd lh \$9,\(\$sp\) + 2e: 06 fd lh \$6,\(\$sp\) + 30: 0f bd lh \$sp,\(\$11\) + +00000032 <lw>: + 32: 0c ae lw \$12,\(\$10\) + 34: 09 de lw \$9,\(\$tp\) + 36: 0c ee lw \$12,\(\$gp\) + 38: 0c be lw \$12,\(\$11\) + 3a: 0d ae lw \$tp,\(\$10\) + +0000003c <lbu>: + 3c: 0e eb lbu \$gp,\(\$gp\) + 3e: 0c 8b lbu \$12,\(\$8\) + 40: 0e 1b lbu \$gp,\(\$1\) + 42: 08 cb lbu \$8,\(\$12\) + 44: 0c 1b lbu \$12,\(\$1\) + +00000046 <lhu>: + 46: 0f 4f lhu \$sp,\(\$4\) + 48: 0e 4f lhu \$gp,\(\$4\) + 4a: 05 4f lhu \$5,\(\$4\) + 4c: 0f df lhu \$sp,\(\$tp\) + 4e: 04 ff lhu \$4,\(\$sp\) + +00000050 <sw_sp>: + 50: c9 8a 00 03 sw \$9,3\(\$8\) + 54: ca 5a 00 04 sw \$10,4\(\$5\) + 58: c0 ea 00 03 sw \$0,3\(\$gp\) + 5c: c0 8a 00 02 sw \$0,2\(\$8\) + 60: cf 8a 00 01 sw \$sp,1\(\$8\) + +00000064 <lw_sp>: + 64: cd 5e 00 01 lw \$tp,1\(\$5\) + 68: cf 0e 00 01 lw \$sp,1\(\$0\) + 6c: c0 ce 00 04 lw \$0,4\(\$12\) + 70: cb de 00 01 lw \$11,1\(\$tp\) + 74: c9 4e 00 03 lw \$9,3\(\$4\) + +00000078 <sb_tp>: + 78: c5 18 00 01 sb \$5,1\(\$1\) + 7c: ca 98 00 01 sb \$10,1\(\$9\) + 80: c5 38 00 03 sb \$5,3\(\$3\) + 84: c5 38 00 01 sb \$5,1\(\$3\) + 88: ca 48 00 04 sb \$10,4\(\$4\) + +0000008c <sh_tp>: + 8c: c3 09 00 01 sh \$3,1\(\$0\) + 90: cd 99 00 01 sh \$tp,1\(\$9\) + 94: c9 a9 00 04 sh \$9,4\(\$10\) + 98: cf e9 00 03 sh \$sp,3\(\$gp\) + 9c: ce 99 00 04 sh \$gp,4\(\$9\) + +000000a0 <sw_tp>: + a0: c6 da 00 02 sw \$6,2\(\$tp\) + a4: c6 fa 00 01 sw \$6,1\(\$sp\) + a8: c2 3a 00 02 sw \$2,2\(\$3\) + ac: c6 ca 00 02 sw \$6,2\(\$12\) + b0: c3 ba 00 01 sw \$3,1\(\$11\) + +000000b4 <lb_tp>: + b4: cd bc 00 04 lb \$tp,4\(\$11\) + b8: cd 8c 00 04 lb \$tp,4\(\$8\) + bc: c5 5c 00 04 lb \$5,4\(\$5\) + c0: cf ec 00 02 lb \$sp,2\(\$gp\) + c4: c3 3c 00 02 lb \$3,2\(\$3\) + +000000c8 <lh_tp>: + c8: c7 8d 00 02 lh \$7,2\(\$8\) + cc: c4 8d 00 03 lh \$4,3\(\$8\) + d0: ce fd 00 01 lh \$gp,1\(\$sp\) + d4: c9 0d 00 01 lh \$9,1\(\$0\) + d8: cd 0d 00 02 lh \$tp,2\(\$0\) + +000000dc <lw_tp>: + dc: 48 07 lw \$8,0x4\(\$sp\) + de: cb 9e 00 04 lw \$11,4\(\$9\) + e2: ce 2e 00 01 lw \$gp,1\(\$2\) + e6: c9 ee 00 02 lw \$9,2\(\$gp\) + ea: c8 ce 00 01 lw \$8,1\(\$12\) + +000000ee <lbu_tp>: + ee: cc 9b 00 01 lbu \$12,1\(\$9\) + f2: cb 9b 00 01 lbu \$11,1\(\$9\) + f6: ce 8b 00 03 lbu \$gp,3\(\$8\) + fa: c0 fb 00 02 lbu \$0,2\(\$sp\) + fe: cd bb 00 01 lbu \$tp,1\(\$11\) + +00000102 <lhu_tp>: + 102: ce af 00 02 lhu \$gp,2\(\$10\) + 106: cb 8f 00 01 lhu \$11,1\(\$8\) + 10a: c1 0f 00 01 lhu \$1,1\(\$0\) + 10e: c7 ff 00 02 lhu \$7,2\(\$sp\) + 112: 8b 83 lhu \$3,0x2\(\$tp\) + +00000114 <sb16>: + 114: c7 b8 ff ff sb \$7,-1\(\$11\) + 118: cd e8 00 01 sb \$tp,1\(\$gp\) + 11c: c3 e8 00 01 sb \$3,1\(\$gp\) + 120: ce 68 00 02 sb \$gp,2\(\$6\) + 124: ce 78 00 01 sb \$gp,1\(\$7\) + +00000128 <sh16>: + 128: cc 49 ff ff sh \$12,-1\(\$4\) + 12c: cf 19 00 01 sh \$sp,1\(\$1\) + 130: c2 c9 ff fe sh \$2,-2\(\$12\) + 134: c9 b9 00 02 sh \$9,2\(\$11\) + 138: c9 c9 ff fe sh \$9,-2\(\$12\) + +0000013c <sw16>: + 13c: cb ea ff ff sw \$11,-1\(\$gp\) + 140: 44 06 sw \$4,0x4\(\$sp\) + 142: c2 3a ff fe sw \$2,-2\(\$3\) + 146: c6 2a ff ff sw \$6,-1\(\$2\) + 14a: c8 da ff fe sw \$8,-2\(\$tp\) + +0000014e <lb16>: + 14e: ca 2c ff fe lb \$10,-2\(\$2\) + 152: c3 bc ff fe lb \$3,-2\(\$11\) + 156: cc 5c 00 01 lb \$12,1\(\$5\) + 15a: c5 5c 00 01 lb \$5,1\(\$5\) + 15e: cb dc 00 02 lb \$11,2\(\$tp\) + +00000162 <lh16>: + 162: cf bd ff ff lh \$sp,-1\(\$11\) + 166: cd bd ff fe lh \$tp,-2\(\$11\) + 16a: c2 ad 00 01 lh \$2,1\(\$10\) + 16e: c8 7d ff ff lh \$8,-1\(\$7\) + 172: ce bd ff ff lh \$gp,-1\(\$11\) + +00000176 <lw16>: + 176: c0 5e ff ff lw \$0,-1\(\$5\) + 17a: cc 7e ff fe lw \$12,-2\(\$7\) + 17e: c1 3e ff fe lw \$1,-2\(\$3\) + 182: c1 7e 00 02 lw \$1,2\(\$7\) + 186: c4 8e 00 01 lw \$4,1\(\$8\) + +0000018a <lbu16>: + 18a: cc 4b ff ff lbu \$12,-1\(\$4\) + 18e: ce bb 00 01 lbu \$gp,1\(\$11\) + 192: c1 db ff ff lbu \$1,-1\(\$tp\) + 196: c9 db ff ff lbu \$9,-1\(\$tp\) + 19a: c8 fb 00 01 lbu \$8,1\(\$sp\) + +0000019e <lhu16>: + 19e: cd ff ff ff lhu \$tp,-1\(\$sp\) + 1a2: ce 8f 00 02 lhu \$gp,2\(\$8\) + 1a6: cf cf ff ff lhu \$sp,-1\(\$12\) + 1aa: c3 0f ff ff lhu \$3,-1\(\$0\) + 1ae: c3 cf ff fe lhu \$3,-2\(\$12\) + +000001b2 <sw24>: + 1b2: eb 06 00 00 sw \$11,\(0x4\) + 1b6: ef 06 00 00 sw \$sp,\(0x4\) + 1ba: e7 0a 00 00 sw \$7,\(0x8\) + 1be: ea 12 00 00 sw \$10,\(0x10\) + 1c2: e8 a2 00 00 sw \$8,\(0xa0\) + +000001c6 <lw24>: + 1c6: e4 07 00 00 lw \$4,\(0x4\) + 1ca: ef 07 00 00 lw \$sp,\(0x4\) + 1ce: e4 13 00 00 lw \$4,\(0x10\) + 1d2: e8 03 00 00 lw \$8,\(0x0\) + 1d6: ed 0b 00 00 lw \$tp,\(0x8\) + +000001da <extb>: + 1da: 1d 0d extb \$tp + 1dc: 1d 0d extb \$tp + 1de: 16 0d extb \$6 + 1e0: 1e 0d extb \$gp + 1e2: 1a 0d extb \$10 + +000001e4 <exth>: + 1e4: 1f 2d exth \$sp + 1e6: 12 2d exth \$2 + 1e8: 15 2d exth \$5 + 1ea: 1a 2d exth \$10 + 1ec: 14 2d exth \$4 + +000001ee <extub>: + 1ee: 12 8d extub \$2 + 1f0: 1d 8d extub \$tp + 1f2: 13 8d extub \$3 + 1f4: 19 8d extub \$9 + 1f6: 1e 8d extub \$gp + +000001f8 <extuh>: + 1f8: 18 ad extuh \$8 + 1fa: 18 ad extuh \$8 + 1fc: 14 ad extuh \$4 + 1fe: 10 ad extuh \$0 + 200: 10 ad extuh \$0 + +00000202 <ssarb>: + 202: 12 8c ssarb 2\(\$8\) + 204: 12 dc ssarb 2\(\$tp\) + 206: 11 dc ssarb 1\(\$tp\) + 208: 12 5c ssarb 2\(\$5\) + 20a: 10 9c ssarb 0\(\$9\) + +0000020c <mov>: + 20c: 02 30 mov \$2,\$3 + 20e: 03 b0 mov \$3,\$11 + 210: 0f a0 mov \$sp,\$10 + 212: 0f 00 mov \$sp,\$0 + 214: 03 d0 mov \$3,\$tp + +00000216 <movi8>: + 216: 5b ff mov \$11,-1 + 218: 56 02 mov \$6,2 + 21a: 5f ff mov \$sp,-1 + 21c: 5f 01 mov \$sp,1 + 21e: 5e ff mov \$gp,-1 + +00000220 <movi16>: + 220: 5f 00 mov \$sp,0 + 222: 50 02 mov \$0,2 + 224: 58 ff mov \$8,-1 + 226: 5c 01 mov \$12,1 + 228: 57 ff mov \$7,-1 + +0000022a <movu24>: + 22a: d2 01 00 00 movu \$2,0x1 + 22e: ca 11 00 04 movu \$10,0x4 + 232: c9 11 00 00 movu \$9,0x0 + 236: d4 03 00 00 movu \$4,0x3 + 23a: ce 11 00 01 movu \$gp,0x1 + +0000023e <movu16>: + 23e: cf 11 00 01 movu \$sp,0x1 + 242: d6 03 00 00 movu \$6,0x3 + 246: d0 03 00 00 movu \$0,0x3 + 24a: ce 11 00 03 movu \$gp,0x3 + 24e: ca 11 00 02 movu \$10,0x2 + +00000252 <movh>: + 252: c8 21 00 02 movh \$8,0x2 + 256: cd 21 00 01 movh \$tp,0x1 + 25a: ce 21 00 02 movh \$gp,0x2 + 25e: cc 21 00 00 movh \$12,0x0 + 262: cb 21 00 02 movh \$11,0x2 + +00000266 <add3>: + 266: 9b 36 add3 \$6,\$11,\$3 + 268: 9d 5e add3 \$gp,\$tp,\$5 + 26a: 9b 73 add3 \$3,\$11,\$7 + 26c: 9e dd add3 \$tp,\$gp,\$tp + 26e: 9e 80 add3 \$0,\$gp,\$8 + +00000270 <add>: + 270: 6c 08 add \$12,2 + 272: 6c fc add \$12,-1 + 274: 64 04 add \$4,1 + 276: 66 04 add \$6,1 + 278: 66 08 add \$6,2 + +0000027a <add3i>: + 27a: 4b 04 add3 \$11,\$sp,0x4 + 27c: c4 f0 00 01 add3 \$4,\$sp,1 + 280: 40 00 add3 \$0,\$sp,0x0 + 282: cd f0 00 03 add3 \$tp,\$sp,3 + 286: 4b 00 add3 \$11,\$sp,0x0 + +00000288 <advck3>: + 288: 0e a7 advck3 \$0,\$gp,\$10 + 28a: 0d 07 advck3 \$0,\$tp,\$0 + 28c: 0e d7 advck3 \$0,\$gp,\$tp + 28e: 07 87 advck3 \$0,\$7,\$8 + 290: 01 27 advck3 \$0,\$1,\$2 + +00000292 <sub>: + 292: 08 e4 sub \$8,\$gp + 294: 01 94 sub \$1,\$9 + 296: 0d 74 sub \$tp,\$7 + 298: 0f 34 sub \$sp,\$3 + 29a: 02 74 sub \$2,\$7 + +0000029c <sbvck3>: + 29c: 03 e5 sbvck3 \$0,\$3,\$gp + 29e: 03 75 sbvck3 \$0,\$3,\$7 + 2a0: 0a a5 sbvck3 \$0,\$10,\$10 + 2a2: 04 d5 sbvck3 \$0,\$4,\$tp + 2a4: 0a f5 sbvck3 \$0,\$10,\$sp + +000002a6 <neg>: + 2a6: 0e 71 neg \$gp,\$7 + 2a8: 01 71 neg \$1,\$7 + 2aa: 02 b1 neg \$2,\$11 + 2ac: 0d 81 neg \$tp,\$8 + 2ae: 0e d1 neg \$gp,\$tp + +000002b0 <slt3>: + 2b0: 0e 82 slt3 \$0,\$gp,\$8 + 2b2: 04 d2 slt3 \$0,\$4,\$tp + 2b4: 0a e2 slt3 \$0,\$10,\$gp + 2b6: 0e 52 slt3 \$0,\$gp,\$5 + 2b8: 03 c2 slt3 \$0,\$3,\$12 + +000002ba <sltu3>: + 2ba: 02 83 sltu3 \$0,\$2,\$8 + 2bc: 0e b3 sltu3 \$0,\$gp,\$11 + 2be: 02 d3 sltu3 \$0,\$2,\$tp + 2c0: 09 83 sltu3 \$0,\$9,\$8 + 2c2: 06 93 sltu3 \$0,\$6,\$9 + +000002c4 <slt3i>: + 2c4: 66 11 slt3 \$0,\$6,0x2 + 2c6: 6b 09 slt3 \$0,\$11,0x1 + 2c8: 6f 01 slt3 \$0,\$sp,0x0 + 2ca: 63 01 slt3 \$0,\$3,0x0 + 2cc: 6d 01 slt3 \$0,\$tp,0x0 + +000002ce <sltu3i>: + 2ce: 6e 25 sltu3 \$0,\$gp,0x4 + 2d0: 6d 1d sltu3 \$0,\$tp,0x3 + 2d2: 63 0d sltu3 \$0,\$3,0x1 + 2d4: 6c 05 sltu3 \$0,\$12,0x0 + 2d6: 61 1d sltu3 \$0,\$1,0x3 + +000002d8 <sl1ad3>: + 2d8: 28 e6 sl1ad3 \$0,\$8,\$gp + 2da: 24 26 sl1ad3 \$0,\$4,\$2 + 2dc: 2f c6 sl1ad3 \$0,\$sp,\$12 + 2de: 29 16 sl1ad3 \$0,\$9,\$1 + 2e0: 28 26 sl1ad3 \$0,\$8,\$2 + +000002e2 <sl2ad3>: + 2e2: 28 d7 sl2ad3 \$0,\$8,\$tp + 2e4: 22 37 sl2ad3 \$0,\$2,\$3 + 2e6: 28 97 sl2ad3 \$0,\$8,\$9 + 2e8: 27 c7 sl2ad3 \$0,\$7,\$12 + 2ea: 24 c7 sl2ad3 \$0,\$4,\$12 + +000002ec <add3x>: + 2ec: cd b0 00 01 add3 \$tp,\$11,1 + 2f0: cd 40 ff ff add3 \$tp,\$4,-1 + 2f4: c2 d0 00 01 add3 \$2,\$tp,1 + 2f8: c3 e0 00 01 add3 \$3,\$gp,1 + 2fc: ca f0 00 02 add3 \$10,\$sp,2 + +00000300 <slt3x>: + 300: c8 12 ff ff slt3 \$8,\$1,-1 + 304: c0 32 ff fe slt3 \$0,\$3,-2 + 308: c9 f2 ff ff slt3 \$9,\$sp,-1 + 30c: c3 82 00 02 slt3 \$3,\$8,2 + 310: cd e2 00 00 slt3 \$tp,\$gp,0 + +00000314 <sltu3x>: + 314: cf b3 00 02 sltu3 \$sp,\$11,0x2 + 318: c6 03 00 01 sltu3 \$6,\$0,0x1 + 31c: c9 b3 00 03 sltu3 \$9,\$11,0x3 + 320: 64 05 sltu3 \$0,\$4,0x0 + 322: cd e3 00 04 sltu3 \$tp,\$gp,0x4 + +00000326 <or>: + 326: 1f e0 or \$sp,\$gp + 328: 18 30 or \$8,\$3 + 32a: 10 f0 or \$0,\$sp + 32c: 1d 00 or \$tp,\$0 + 32e: 18 60 or \$8,\$6 + +00000330 <and>: + 330: 1f f1 and \$sp,\$sp + 332: 16 e1 and \$6,\$gp + 334: 14 21 and \$4,\$2 + 336: 15 81 and \$5,\$8 + 338: 17 e1 and \$7,\$gp + +0000033a <xor>: + 33a: 11 c2 xor \$1,\$12 + 33c: 1c d2 xor \$12,\$tp + 33e: 1a 82 xor \$10,\$8 + 340: 1f b2 xor \$sp,\$11 + 342: 1c 82 xor \$12,\$8 + +00000344 <nor>: + 344: 19 53 nor \$9,\$5 + 346: 18 23 nor \$8,\$2 + 348: 1f 93 nor \$sp,\$9 + 34a: 15 f3 nor \$5,\$sp + 34c: 1f e3 nor \$sp,\$gp + +0000034e <or3>: + 34e: cd f4 00 02 or3 \$tp,\$sp,0x2 + 352: cf d4 00 03 or3 \$sp,\$tp,0x3 + 356: c0 a4 00 04 or3 \$0,\$10,0x4 + 35a: c9 f4 00 03 or3 \$9,\$sp,0x3 + 35e: c9 f4 00 00 or3 \$9,\$sp,0x0 + +00000362 <and3>: + 362: c5 85 00 01 and3 \$5,\$8,0x1 + 366: cb e5 00 03 and3 \$11,\$gp,0x3 + 36a: c6 05 00 00 and3 \$6,\$0,0x0 + 36e: cf f5 00 00 and3 \$sp,\$sp,0x0 + 372: c1 a5 00 03 and3 \$1,\$10,0x3 + +00000376 <xor3>: + 376: c0 06 00 02 xor3 \$0,\$0,0x2 + 37a: cf 66 00 00 xor3 \$sp,\$6,0x0 + 37e: cd 56 00 00 xor3 \$tp,\$5,0x0 + 382: cf 76 00 00 xor3 \$sp,\$7,0x0 + 386: cf f6 00 02 xor3 \$sp,\$sp,0x2 + +0000038a <sra>: + 38a: 24 1d sra \$4,\$1 + 38c: 28 fd sra \$8,\$sp + 38e: 21 1d sra \$1,\$1 + 390: 20 5d sra \$0,\$5 + 392: 29 1d sra \$9,\$1 + +00000394 <srl>: + 394: 22 bc srl \$2,\$11 + 396: 2f 7c srl \$sp,\$7 + 398: 21 7c srl \$1,\$7 + 39a: 23 dc srl \$3,\$tp + 39c: 2e 1c srl \$gp,\$1 + +0000039e <sll>: + 39e: 2b 0e sll \$11,\$0 + 3a0: 2d 8e sll \$tp,\$8 + 3a2: 28 9e sll \$8,\$9 + 3a4: 2d fe sll \$tp,\$sp + 3a6: 2f fe sll \$sp,\$sp + +000003a8 <srai>: + 3a8: 61 13 sra \$1,0x2 + 3aa: 6f 1b sra \$sp,0x3 + 3ac: 6f 1b sra \$sp,0x3 + 3ae: 66 23 sra \$6,0x4 + 3b0: 6f 1b sra \$sp,0x3 + +000003b2 <srli>: + 3b2: 6a 02 srl \$10,0x0 + 3b4: 69 1a srl \$9,0x3 + 3b6: 66 22 srl \$6,0x4 + 3b8: 6a 12 srl \$10,0x2 + 3ba: 68 1a srl \$8,0x3 + +000003bc <slli>: + 3bc: 60 06 sll \$0,0x0 + 3be: 64 06 sll \$4,0x0 + 3c0: 6d 16 sll \$tp,0x2 + 3c2: 6b 16 sll \$11,0x2 + 3c4: 66 06 sll \$6,0x0 + +000003c6 <sll3>: + 3c6: 6d 27 sll3 \$0,\$tp,0x4 + 3c8: 6e 07 sll3 \$0,\$gp,0x0 + 3ca: 68 17 sll3 \$0,\$8,0x2 + 3cc: 63 17 sll3 \$0,\$3,0x2 + 3ce: 68 07 sll3 \$0,\$8,0x0 + +000003d0 <fsft>: + 3d0: 2e af fsft \$gp,\$10 + 3d2: 2e 9f fsft \$gp,\$9 + 3d4: 2f df fsft \$sp,\$tp + 3d6: 2b 3f fsft \$11,\$3 + 3d8: 25 3f fsft \$5,\$3 + +000003da <bra>: + 3da: b0 02 bra 3dc <bra\+0x2> + 3dc: bf fe bra 3da <bra> + 3de: b0 02 bra 3e0 <bra\+0x6> + 3e0: b0 00 bra 3e0 <bra\+0x6> + 3e2: b0 02 bra 3e4 <beqz> + +000003e4 <beqz>: + 3e4: a1 fe beqz \$1,3e2 <bra\+0x8> + 3e6: af 02 beqz \$sp,3e8 <beqz\+0x4> + 3e8: a4 04 beqz \$4,3ec <beqz\+0x8> + 3ea: a4 00 beqz \$4,3ea <beqz\+0x6> + 3ec: a9 fe beqz \$9,3ea <beqz\+0x6> + +000003ee <bnez>: + 3ee: a8 03 bnez \$8,3f0 <bnez\+0x2> + 3f0: ad 03 bnez \$tp,3f2 <bnez\+0x4> + 3f2: ae 01 bnez \$gp,3f2 <bnez\+0x4> + 3f4: a6 03 bnez \$6,3f6 <bnez\+0x8> + 3f6: a8 fd bnez \$8,3f2 <bnez\+0x4> + +000003f8 <beqi>: + 3f8: ed 30 00 00 beqi \$tp,0x3,3f8 <beqi> + 3fc: e0 40 ff ff beqi \$0,0x4,3fa <beqi\+0x2> + 400: ef 40 ff ff beqi \$sp,0x4,3fe <beqi\+0x6> + 404: ed 20 00 00 beqi \$tp,0x2,404 <beqi\+0xc> + 408: e4 20 ff fc beqi \$4,0x2,400 <beqi\+0x8> + +0000040c <bnei>: + 40c: e8 14 00 00 bnei \$8,0x1,40c <bnei> + 410: e5 14 00 01 bnei \$5,0x1,412 <bnei\+0x6> + 414: e5 04 00 04 bnei \$5,0x0,41c <bnei\+0x10> + 418: e9 44 ff ff bnei \$9,0x4,416 <bnei\+0xa> + 41c: e0 44 ff fc bnei \$0,0x4,414 <bnei\+0x8> + +00000420 <blti>: + 420: e7 3c 00 00 blti \$7,0x3,420 <blti> + 424: e1 1c 00 00 blti \$1,0x1,424 <blti\+0x4> + 428: e8 2c 00 01 blti \$8,0x2,42a <blti\+0xa> + 42c: eb 2c 00 01 blti \$11,0x2,42e <blti\+0xe> + 430: ef 3c ff ff blti \$sp,0x3,42e <blti\+0xe> + +00000434 <bgei>: + 434: e4 38 ff fc bgei \$4,0x3,42c <blti\+0xc> + 438: e7 08 00 01 bgei \$7,0x0,43a <bgei\+0x6> + 43c: ed 18 00 00 bgei \$tp,0x1,43c <bgei\+0x8> + 440: e5 28 ff ff bgei \$5,0x2,43e <bgei\+0xa> + 444: ec 48 ff fc bgei \$12,0x4,43c <bgei\+0x8> + +00000448 <beq>: + 448: e7 21 ff ff beq \$7,\$2,446 <bgei\+0x12> + 44c: e1 31 ff fc beq \$1,\$3,444 <bgei\+0x10> + 450: e2 01 00 01 beq \$2,\$0,452 <beq\+0xa> + 454: ef 81 00 01 beq \$sp,\$8,456 <beq\+0xe> + 458: e3 01 00 00 beq \$3,\$0,458 <beq\+0x10> + +0000045c <bne>: + 45c: e6 35 00 00 bne \$6,\$3,45c <bne> + 460: ef 35 ff fc bne \$sp,\$3,458 <beq\+0x10> + 464: e8 05 00 01 bne \$8,\$0,466 <bne\+0xa> + 468: ee f5 00 04 bne \$gp,\$sp,470 <bsr12> + 46c: ef 45 00 01 bne \$sp,\$4,46e <bne\+0x12> + +00000470 <bsr12>: + 470: b0 03 bsr 472 <bsr12\+0x2> + 472: bf f9 bsr 46a <bne\+0xe> + 474: bf f1 bsr 464 <bne\+0x8> + 476: bf ff bsr 474 <bsr12\+0x4> + 478: bf f9 bsr 470 <bsr12> + +0000047a <bsr24>: + 47a: b0 05 bsr 47e <bsr24\+0x4> + 47c: bf ff bsr 47a <bsr24> + 47e: bf fd bsr 47a <bsr24> + 480: b0 01 bsr 480 <bsr24\+0x6> + 482: b0 03 bsr 484 <jmp> + +00000484 <jmp>: + 484: 10 2e jmp \$2 + 486: 10 de jmp \$tp + 488: 10 5e jmp \$5 + 48a: 10 fe jmp \$sp + 48c: 10 8e jmp \$8 + +0000048e <jmp24>: + 48e: d8 28 00 00 jmp 4 <sb\+0x4> + 492: d8 18 00 00 jmp 2 <sb\+0x2> + 496: d8 08 00 00 jmp 0 <sb> + 49a: d8 18 00 00 jmp 2 <sb\+0x2> + 49e: d8 28 00 00 jmp 4 <sb\+0x4> + +000004a2 <jsr>: + 4a2: 10 ff jsr \$sp + 4a4: 10 df jsr \$tp + 4a6: 10 df jsr \$tp + 4a8: 10 6f jsr \$6 + 4aa: 10 6f jsr \$6 + +000004ac <ret>: + 4ac: 70 02 ret + +000004ae <repeat>: + 4ae: e4 09 00 01 repeat \$4,4b0 <repeat\+0x2> + 4b2: e8 09 00 02 repeat \$8,4b6 <repeat\+0x8> + 4b6: e0 09 00 04 repeat \$0,4be <repeat\+0x10> + 4ba: e6 09 00 01 repeat \$6,4bc <repeat\+0xe> + 4be: e4 09 00 01 repeat \$4,4c0 <repeat\+0x12> + +000004c2 <erepeat>: + 4c2: e0 19 00 01 erepeat 4c4 <erepeat\+0x2> + 4c6: e0 19 00 00 erepeat 4c6 <erepeat\+0x4> + 4ca: e0 19 00 01 erepeat 4cc <erepeat\+0xa> + 4ce: e0 19 ff ff erepeat 4cc <erepeat\+0xa> + 4d2: e0 19 00 00 erepeat 4d2 <erepeat\+0x10> + +000004d6 <stc>: + 4d6: 7d e8 stc \$tp,\$mb1 + 4d8: 7d c9 stc \$tp,\$ccfg + 4da: 7b 89 stc \$11,\$dbg + 4dc: 7a c9 stc \$10,\$ccfg + 4de: 79 39 stc \$9,\$epc + +000004e0 <ldc>: + 4e0: 7d 8a ldc \$tp,\$lo + 4e2: 78 7b ldc \$8,\$npc + 4e4: 79 ca ldc \$9,\$mb0 + 4e6: 7f 2a ldc \$sp,\$sar + 4e8: 79 cb ldc \$9,\$ccfg + +000004ea <di>: + 4ea: 70 00 di + +000004ec <ei>: + 4ec: 70 10 ei + +000004ee <reti>: + 4ee: 70 12 reti + +000004f0 <halt>: + 4f0: 70 22 halt + +000004f2 <swi>: + 4f2: 70 26 swi 0x2 + 4f4: 70 06 swi 0x0 + 4f6: 70 26 swi 0x2 + 4f8: 70 36 swi 0x3 + 4fa: 70 16 swi 0x1 + +000004fc <break>: + 4fc: 70 32 break + +000004fe <syncm>: + 4fe: 70 11 syncm + +00000500 <stcb>: + 500: f5 04 00 04 stcb \$5,0x4 + 504: f5 04 00 01 stcb \$5,0x1 + 508: fe 04 00 00 stcb \$gp,0x0 + 50c: ff 04 00 04 stcb \$sp,0x4 + 510: fb 04 00 02 stcb \$11,0x2 + +00000514 <ldcb>: + 514: f2 14 00 03 ldcb \$2,0x3 + 518: f2 14 00 04 ldcb \$2,0x4 + 51c: f9 14 00 01 ldcb \$9,0x1 + 520: fa 14 00 04 ldcb \$10,0x4 + 524: f1 14 00 04 ldcb \$1,0x4 + +00000528 <bsetm>: + 528: 20 a0 bsetm \(\$10\),0x0 + 52a: 20 f0 bsetm \(\$sp\),0x0 + 52c: 22 10 bsetm \(\$1\),0x2 + 52e: 24 f0 bsetm \(\$sp\),0x4 + 530: 24 80 bsetm \(\$8\),0x4 + +00000532 <bclrm>: + 532: 20 51 bclrm \(\$5\),0x0 + 534: 22 51 bclrm \(\$5\),0x2 + 536: 20 81 bclrm \(\$8\),0x0 + 538: 22 91 bclrm \(\$9\),0x2 + 53a: 23 51 bclrm \(\$5\),0x3 + +0000053c <bnotm>: + 53c: 24 e2 bnotm \(\$gp\),0x4 + 53e: 24 b2 bnotm \(\$11\),0x4 + 540: 20 a2 bnotm \(\$10\),0x0 + 542: 24 d2 bnotm \(\$tp\),0x4 + 544: 20 82 bnotm \(\$8\),0x0 + +00000546 <btstm>: + 546: 20 e3 btstm \$0,\(\$gp\),0x0 + 548: 21 e3 btstm \$0,\(\$gp\),0x1 + 54a: 20 b3 btstm \$0,\(\$11\),0x0 + 54c: 23 e3 btstm \$0,\(\$gp\),0x3 + 54e: 22 83 btstm \$0,\(\$8\),0x2 + +00000550 <tas>: + 550: 27 d4 tas \$7,\(\$tp\) + 552: 27 c4 tas \$7,\(\$12\) + 554: 23 84 tas \$3,\(\$8\) + 556: 22 54 tas \$2,\(\$5\) + 558: 26 a4 tas \$6,\(\$10\) + +0000055a <cache>: + 55a: 71 d4 cache 0x1,\(\$tp\) + 55c: 73 c4 cache 0x3,\(\$12\) + 55e: 73 94 cache 0x3,\(\$9\) + 560: 74 24 cache 0x4,\(\$2\) + 562: 74 74 cache 0x4,\(\$7\) + +00000564 <mul>: + 564: 18 e4 mul \$8,\$gp + 566: 12 94 mul \$2,\$9 + 568: 1e f4 mul \$gp,\$sp + 56a: 19 74 mul \$9,\$7 + 56c: 17 b4 mul \$7,\$11 + +0000056e <mulu>: + 56e: 12 55 mulu \$2,\$5 + 570: 16 e5 mulu \$6,\$gp + 572: 1e f5 mulu \$gp,\$sp + 574: 1b e5 mulu \$11,\$gp + 576: 13 95 mulu \$3,\$9 + +00000578 <mulr>: + 578: 1c 66 mulr \$12,\$6 + 57a: 1d 86 mulr \$tp,\$8 + 57c: 17 a6 mulr \$7,\$10 + 57e: 1e 16 mulr \$gp,\$1 + 580: 10 f6 mulr \$0,\$sp + +00000582 <mulru>: + 582: 14 27 mulru \$4,\$2 + 584: 1e 17 mulru \$gp,\$1 + 586: 1f 47 mulru \$sp,\$4 + 588: 1a 67 mulru \$10,\$6 + 58a: 10 e7 mulru \$0,\$gp + +0000058c <madd>: + 58c: f4 b1 30 04 madd \$4,\$11 + 590: ff e1 30 04 madd \$sp,\$gp + 594: fe f1 30 04 madd \$gp,\$sp + 598: f4 d1 30 04 madd \$4,\$tp + 59c: f1 e1 30 04 madd \$1,\$gp + +000005a0 <maddu>: + 5a0: f0 11 30 05 maddu \$0,\$1 + 5a4: f7 61 30 05 maddu \$7,\$6 + 5a8: f9 51 30 05 maddu \$9,\$5 + 5ac: fe f1 30 05 maddu \$gp,\$sp + 5b0: f7 d1 30 05 maddu \$7,\$tp + +000005b4 <maddr>: + 5b4: f6 81 30 06 maddr \$6,\$8 + 5b8: f9 e1 30 06 maddr \$9,\$gp + 5bc: f8 e1 30 06 maddr \$8,\$gp + 5c0: f3 21 30 06 maddr \$3,\$2 + 5c4: f1 b1 30 06 maddr \$1,\$11 + +000005c8 <maddru>: + 5c8: fa 31 30 07 maddru \$10,\$3 + 5cc: ff c1 30 07 maddru \$sp,\$12 + 5d0: f8 81 30 07 maddru \$8,\$8 + 5d4: fe 31 30 07 maddru \$gp,\$3 + 5d8: f8 f1 30 07 maddru \$8,\$sp + +000005dc <div>: + 5dc: 19 38 div \$9,\$3 + 5de: 14 e8 div \$4,\$gp + 5e0: 12 c8 div \$2,\$12 + 5e2: 18 d8 div \$8,\$tp + 5e4: 1d 68 div \$tp,\$6 + +000005e6 <divu>: + 5e6: 19 59 divu \$9,\$5 + 5e8: 18 d9 divu \$8,\$tp + 5ea: 10 e9 divu \$0,\$gp + 5ec: 19 59 divu \$9,\$5 + 5ee: 10 59 divu \$0,\$5 + +000005f0 <dret>: + 5f0: 70 13 dret + +000005f2 <dbreak>: + 5f2: 70 33 dbreak + +000005f4 <ldz>: + 5f4: fe 41 00 00 ldz \$gp,\$4 + 5f8: fa b1 00 00 ldz \$10,\$11 + 5fc: f9 91 00 00 ldz \$9,\$9 + 600: ff d1 00 00 ldz \$sp,\$tp + 604: fe 31 00 00 ldz \$gp,\$3 + +00000608 <abs>: + 608: ff 91 00 03 abs \$sp,\$9 + 60c: f5 41 00 03 abs \$5,\$4 + 610: fd d1 00 03 abs \$tp,\$tp + 614: f0 31 00 03 abs \$0,\$3 + 618: f3 e1 00 03 abs \$3,\$gp + +0000061c <ave>: + 61c: fb a1 00 02 ave \$11,\$10 + 620: f8 a1 00 02 ave \$8,\$10 + 624: fe 21 00 02 ave \$gp,\$2 + 628: fa c1 00 02 ave \$10,\$12 + 62c: ff 81 00 02 ave \$sp,\$8 + +00000630 <min>: + 630: f8 31 00 04 min \$8,\$3 + 634: f7 01 00 04 min \$7,\$0 + 638: f2 21 00 04 min \$2,\$2 + 63c: f5 61 00 04 min \$5,\$6 + 640: fb 51 00 04 min \$11,\$5 + +00000644 <max>: + 644: fb f1 00 05 max \$11,\$sp + 648: fe 01 00 05 max \$gp,\$0 + 64c: fc f1 00 05 max \$12,\$sp + 650: fe 21 00 05 max \$gp,\$2 + 654: fe f1 00 05 max \$gp,\$sp + +00000658 <minu>: + 658: fb 81 00 06 minu \$11,\$8 + 65c: f7 51 00 06 minu \$7,\$5 + 660: f8 e1 00 06 minu \$8,\$gp + 664: fb 41 00 06 minu \$11,\$4 + 668: f2 f1 00 06 minu \$2,\$sp + +0000066c <maxu>: + 66c: f3 31 00 07 maxu \$3,\$3 + 670: fd 01 00 07 maxu \$tp,\$0 + 674: f4 81 00 07 maxu \$4,\$8 + 678: fe 21 00 07 maxu \$gp,\$2 + 67c: fc 81 00 07 maxu \$12,\$8 + +00000680 <clip>: + 680: fa 01 10 08 clip \$10,0x1 + 684: ff 01 10 20 clip \$sp,0x4 + 688: f4 01 10 18 clip \$4,0x3 + 68c: ff 01 10 18 clip \$sp,0x3 + 690: f1 01 10 00 clip \$1,0x0 + +00000694 <clipu>: + 694: fa 01 10 21 clipu \$10,0x4 + 698: fd 01 10 09 clipu \$tp,0x1 + 69c: f5 01 10 21 clipu \$5,0x4 + 6a0: fe 01 10 01 clipu \$gp,0x0 + 6a4: f5 01 10 09 clipu \$5,0x1 + +000006a8 <sadd>: + 6a8: f5 01 00 08 sadd \$5,\$0 + 6ac: ff 31 00 08 sadd \$sp,\$3 + 6b0: f0 a1 00 08 sadd \$0,\$10 + 6b4: ff c1 00 08 sadd \$sp,\$12 + 6b8: f4 21 00 08 sadd \$4,\$2 + +000006bc <ssub>: + 6bc: f1 a1 00 0a ssub \$1,\$10 + 6c0: f4 71 00 0a ssub \$4,\$7 + 6c4: f8 31 00 0a ssub \$8,\$3 + 6c8: f7 e1 00 0a ssub \$7,\$gp + 6cc: fd 41 00 0a ssub \$tp,\$4 + +000006d0 <saddu>: + 6d0: f9 e1 00 09 saddu \$9,\$gp + 6d4: f0 a1 00 09 saddu \$0,\$10 + 6d8: f7 c1 00 09 saddu \$7,\$12 + 6dc: f5 f1 00 09 saddu \$5,\$sp + 6e0: fd 31 00 09 saddu \$tp,\$3 + +000006e4 <ssubu>: + 6e4: ff e1 00 0b ssubu \$sp,\$gp + 6e8: f0 f1 00 0b ssubu \$0,\$sp + 6ec: f3 a1 00 0b ssubu \$3,\$10 + 6f0: ff d1 00 0b ssubu \$sp,\$tp + 6f4: f2 91 00 0b ssubu \$2,\$9 + +000006f8 <swcp>: + 6f8: 33 d8 swcp \$c3,\(\$tp\) + 6fa: 3f d8 swcp \$c15,\(\$tp\) + 6fc: 3d 08 swcp \$c13,\(\$0\) + 6fe: 3c c8 swcp \$c12,\(\$12\) + 700: 39 e8 swcp \$c9,\(\$gp\) + +00000702 <lwcp>: + 702: 37 39 lwcp \$c7,\(\$3\) + 704: 36 39 lwcp \$c6,\(\$3\) + 706: 30 29 lwcp \$c0,\(\$2\) + 708: 38 89 lwcp \$c8,\(\$8\) + 70a: 3b d9 lwcp \$c11,\(\$tp\) + +0000070c <smcp>: + 70c: 3e 9a smcp \$c14,\(\$9\) + 70e: 32 8a smcp \$c2,\(\$8\) + 710: 3e fa smcp \$c14,\(\$sp\) + 712: 3a 8a smcp \$c10,\(\$8\) + 714: 32 8a smcp \$c2,\(\$8\) + +00000716 <lmcp>: + 716: 3b 1b lmcp \$c11,\(\$1\) + 718: 38 8b lmcp \$c8,\(\$8\) + 71a: 3b db lmcp \$c11,\(\$tp\) + 71c: 38 0b lmcp \$c8,\(\$0\) + 71e: 38 eb lmcp \$c8,\(\$gp\) + +00000720 <swcpi>: + 720: 37 00 swcpi \$c7,\(\$0\+\) + 722: 36 e0 swcpi \$c6,\(\$gp\+\) + 724: 3c 80 swcpi \$c12,\(\$8\+\) + 726: 3e f0 swcpi \$c14,\(\$sp\+\) + 728: 36 00 swcpi \$c6,\(\$0\+\) + +0000072a <lwcpi>: + 72a: 38 21 lwcpi \$c8,\(\$2\+\) + 72c: 39 01 lwcpi \$c9,\(\$0\+\) + 72e: 33 e1 lwcpi \$c3,\(\$gp\+\) + 730: 3d 51 lwcpi \$c13,\(\$5\+\) + 732: 3b e1 lwcpi \$c11,\(\$gp\+\) + +00000734 <smcpi>: + 734: 38 22 smcpi \$c8,\(\$2\+\) + 736: 3b 92 smcpi \$c11,\(\$9\+\) + 738: 34 32 smcpi \$c4,\(\$3\+\) + 73a: 3e 22 smcpi \$c14,\(\$2\+\) + 73c: 39 32 smcpi \$c9,\(\$3\+\) + +0000073e <lmcpi>: + 73e: 36 e3 lmcpi \$c6,\(\$gp\+\) + 740: 39 53 lmcpi \$c9,\(\$5\+\) + 742: 3a 63 lmcpi \$c10,\(\$6\+\) + 744: 31 63 lmcpi \$c1,\(\$6\+\) + 746: 32 83 lmcpi \$c2,\(\$8\+\) + +00000748 <swcp16>: + 748: f0 2c ff ff swcp \$c0,-1\(\$2\) + 74c: f5 ac 00 01 swcp \$c5,1\(\$10\) + 750: f8 cc 00 02 swcp \$c8,2\(\$12\) + 754: fe 1c ff ff swcp \$c14,-1\(\$1\) + 758: fc 3c 00 02 swcp \$c12,2\(\$3\) + +0000075c <lwcp16>: + 75c: f8 5d ff ff lwcp \$c8,-1\(\$5\) + 760: fc fd 00 01 lwcp \$c12,1\(\$sp\) + 764: f1 0d 00 02 lwcp \$c1,2\(\$0\) + 768: f4 dd 00 01 lwcp \$c4,1\(\$tp\) + 76c: f6 bd 00 02 lwcp \$c6,2\(\$11\) + +00000770 <smcp16>: + 770: f9 ae ff ff smcp \$c9,-1\(\$10\) + 774: fe ee 00 01 smcp \$c14,1\(\$gp\) + 778: f3 fe 00 02 smcp \$c3,2\(\$sp\) + 77c: ff 8e ff fe smcp \$c15,-2\(\$8\) + 780: fd de 00 01 smcp \$c13,1\(\$tp\) + +00000784 <lmcp16>: + 784: f0 ff 00 01 lmcp \$c0,1\(\$sp\) + 788: ff 8f 00 01 lmcp \$c15,1\(\$8\) + 78c: f2 8f ff ff lmcp \$c2,-1\(\$8\) + 790: fe 8f 00 01 lmcp \$c14,1\(\$8\) + 794: f1 af ff ff lmcp \$c1,-1\(\$10\) + +00000798 <sbcpa>: + 798: fe f5 00 02 sbcpa \$c14,\(\$sp\+\),2 + 79c: f2 45 00 fe sbcpa \$c2,\(\$4\+\),-2 + 7a0: f8 15 00 00 sbcpa \$c8,\(\$1\+\),0 + 7a4: fb 35 00 00 sbcpa \$c11,\(\$3\+\),0 + 7a8: f9 e5 00 fe sbcpa \$c9,\(\$gp\+\),-2 + +000007ac <lbcpa>: + 7ac: f7 25 40 fe lbcpa \$c7,\(\$2\+\),-2 + 7b0: fc f5 40 02 lbcpa \$c12,\(\$sp\+\),2 + 7b4: f5 45 40 fe lbcpa \$c5,\(\$4\+\),-2 + 7b8: f7 45 40 fe lbcpa \$c7,\(\$4\+\),-2 + 7bc: f8 f5 40 00 lbcpa \$c8,\(\$sp\+\),0 + +000007c0 <shcpa>: + 7c0: f0 e5 10 00 shcpa \$c0,\(\$gp\+\),0 + 7c4: fc f5 10 10 shcpa \$c12,\(\$sp\+\),16 + 7c8: f1 45 10 04 shcpa \$c1,\(\$4\+\),4 + 7cc: f5 45 10 e0 shcpa \$c5,\(\$4\+\),-32 + 7d0: f1 f5 10 00 shcpa \$c1,\(\$sp\+\),0 + +000007d4 <lhcpa>: + 7d4: f4 45 50 00 lhcpa \$c4,\(\$4\+\),0 + 7d8: f6 55 50 30 lhcpa \$c6,\(\$5\+\),48 + 7dc: f3 65 50 cc lhcpa \$c3,\(\$6\+\),-52 + 7e0: f8 65 50 e8 lhcpa \$c8,\(\$6\+\),-24 + 7e4: f0 95 50 00 lhcpa \$c0,\(\$9\+\),0 + +000007e8 <swcpa>: + 7e8: f1 95 20 10 swcpa \$c1,\(\$9\+\),16 + 7ec: f7 f5 20 20 swcpa \$c7,\(\$sp\+\),32 + 7f0: f3 c5 20 30 swcpa \$c3,\(\$12\+\),48 + 7f4: fa 95 20 08 swcpa \$c10,\(\$9\+\),8 + 7f8: fe 85 20 04 swcpa \$c14,\(\$8\+\),4 + +000007fc <lwcpa>: + 7fc: f6 e5 60 f8 lwcpa \$c6,\(\$gp\+\),-8 + 800: f4 75 60 04 lwcpa \$c4,\(\$7\+\),4 + 804: fb e5 60 f0 lwcpa \$c11,\(\$gp\+\),-16 + 808: fa f5 60 e0 lwcpa \$c10,\(\$sp\+\),-32 + 80c: f2 25 60 08 lwcpa \$c2,\(\$2\+\),8 + +00000810 <smcpa>: + 810: fd f5 30 f8 smcpa \$c13,\(\$sp\+\),-8 + 814: f6 75 30 f8 smcpa \$c6,\(\$7\+\),-8 + 818: f5 35 30 10 smcpa \$c5,\(\$3\+\),16 + 81c: fd f5 30 10 smcpa \$c13,\(\$sp\+\),16 + 820: f3 c5 30 30 smcpa \$c3,\(\$12\+\),48 + +00000824 <lmcpa>: + 824: f9 45 70 00 lmcpa \$c9,\(\$4\+\),0 + 828: f3 f5 70 f0 lmcpa \$c3,\(\$sp\+\),-16 + 82c: ff d5 70 08 lmcpa \$c15,\(\$tp\+\),8 + 830: f8 85 70 f8 lmcpa \$c8,\(\$8\+\),-8 + 834: fa 95 70 00 lmcpa \$c10,\(\$9\+\),0 + +00000838 <sbcpm0>: + 838: fa d5 08 08 sbcpm0 \$c10,\(\$tp\+\),8 + 83c: fd 55 08 f8 sbcpm0 \$c13,\(\$5\+\),-8 + 840: f4 55 08 f8 sbcpm0 \$c4,\(\$5\+\),-8 + 844: fa d5 08 10 sbcpm0 \$c10,\(\$tp\+\),16 + 848: f4 55 08 e8 sbcpm0 \$c4,\(\$5\+\),-24 + +0000084c <lbcpm0>: + 84c: f0 45 48 00 lbcpm0 \$c0,\(\$4\+\),0 + 850: f9 75 48 f8 lbcpm0 \$c9,\(\$7\+\),-8 + 854: fc 85 48 18 lbcpm0 \$c12,\(\$8\+\),24 + 858: f8 c5 48 10 lbcpm0 \$c8,\(\$12\+\),16 + 85c: f7 85 48 10 lbcpm0 \$c7,\(\$8\+\),16 + +00000860 <shcpm0>: + 860: f2 d5 18 02 shcpm0 \$c2,\(\$tp\+\),2 + 864: f7 f5 18 fe shcpm0 \$c7,\(\$sp\+\),-2 + 868: f8 25 18 02 shcpm0 \$c8,\(\$2\+\),2 + 86c: fd 55 18 00 shcpm0 \$c13,\(\$5\+\),0 + 870: f3 e5 18 08 shcpm0 \$c3,\(\$gp\+\),8 + +00000874 <lhcpm0>: + 874: f7 45 58 08 lhcpm0 \$c7,\(\$4\+\),8 + 878: f3 35 58 fe lhcpm0 \$c3,\(\$3\+\),-2 + 87c: f3 15 58 00 lhcpm0 \$c3,\(\$1\+\),0 + 880: f2 e5 58 00 lhcpm0 \$c2,\(\$gp\+\),0 + 884: fc 65 58 02 lhcpm0 \$c12,\(\$6\+\),2 + +00000888 <swcpm0>: + 888: f8 85 28 20 swcpm0 \$c8,\(\$8\+\),32 + 88c: f9 f5 28 00 swcpm0 \$c9,\(\$sp\+\),0 + 890: f9 25 28 f0 swcpm0 \$c9,\(\$2\+\),-16 + 894: f0 e5 28 30 swcpm0 \$c0,\(\$gp\+\),48 + 898: ff 15 28 08 swcpm0 \$c15,\(\$1\+\),8 + +0000089c <lwcpm0>: + 89c: fe a5 68 fc lwcpm0 \$c14,\(\$10\+\),-4 + 8a0: fb f5 68 fc lwcpm0 \$c11,\(\$sp\+\),-4 + 8a4: f5 75 68 f8 lwcpm0 \$c5,\(\$7\+\),-8 + 8a8: f2 c5 68 20 lwcpm0 \$c2,\(\$12\+\),32 + 8ac: f2 e5 68 10 lwcpm0 \$c2,\(\$gp\+\),16 + +000008b0 <smcpm0>: + 8b0: f1 c5 38 08 smcpm0 \$c1,\(\$12\+\),8 + 8b4: f8 45 38 f0 smcpm0 \$c8,\(\$4\+\),-16 + 8b8: fa b5 38 00 smcpm0 \$c10,\(\$11\+\),0 + 8bc: f1 35 38 f0 smcpm0 \$c1,\(\$3\+\),-16 + 8c0: fb f5 38 f8 smcpm0 \$c11,\(\$sp\+\),-8 + +000008c4 <lmcpm0>: + 8c4: fe a5 78 00 lmcpm0 \$c14,\(\$10\+\),0 + 8c8: f6 f5 78 f0 lmcpm0 \$c6,\(\$sp\+\),-16 + 8cc: fd 15 78 08 lmcpm0 \$c13,\(\$1\+\),8 + 8d0: fa d5 78 e8 lmcpm0 \$c10,\(\$tp\+\),-24 + 8d4: f7 e5 78 e8 lmcpm0 \$c7,\(\$gp\+\),-24 + +000008d8 <sbcpm1>: + 8d8: f9 85 0c 00 sbcpm1 \$c9,\(\$8\+\),0 + 8dc: f7 c5 0c e8 sbcpm1 \$c7,\(\$12\+\),-24 + 8e0: ff 55 0c e8 sbcpm1 \$c15,\(\$5\+\),-24 + 8e4: f5 d5 0c 10 sbcpm1 \$c5,\(\$tp\+\),16 + 8e8: f6 15 0c 80 sbcpm1 \$c6,\(\$1\+\),-128 + +000008ec <lbcpm1>: + 8ec: f6 e5 4c 02 lbcpm1 \$c6,\(\$gp\+\),2 + 8f0: f7 d5 4c fe lbcpm1 \$c7,\(\$tp\+\),-2 + 8f4: f4 d5 4c 01 lbcpm1 \$c4,\(\$tp\+\),1 + 8f8: fc 25 4c fe lbcpm1 \$c12,\(\$2\+\),-2 + 8fc: fb 75 4c 01 lbcpm1 \$c11,\(\$7\+\),1 + +00000900 <shcpm1>: + 900: f4 85 1c 18 shcpm1 \$c4,\(\$8\+\),24 + 904: fb 65 1c f0 shcpm1 \$c11,\(\$6\+\),-16 + 908: f7 85 1c 08 shcpm1 \$c7,\(\$8\+\),8 + 90c: f5 c5 1c 10 shcpm1 \$c5,\(\$12\+\),16 + 910: f0 85 1c e0 shcpm1 \$c0,\(\$8\+\),-32 + +00000914 <lhcpm1>: + 914: fb 05 5c 00 lhcpm1 \$c11,\(\$0\+\),0 + 918: f7 d5 5c fe lhcpm1 \$c7,\(\$tp\+\),-2 + 91c: fa 85 5c 08 lhcpm1 \$c10,\(\$8\+\),8 + 920: f3 d5 5c 00 lhcpm1 \$c3,\(\$tp\+\),0 + 924: f9 65 5c 02 lhcpm1 \$c9,\(\$6\+\),2 + +00000928 <swcpm1>: + 928: f9 85 2c 18 swcpm1 \$c9,\(\$8\+\),24 + 92c: f9 e5 2c 00 swcpm1 \$c9,\(\$gp\+\),0 + 930: f9 85 2c 10 swcpm1 \$c9,\(\$8\+\),16 + 934: fe 15 2c 00 swcpm1 \$c14,\(\$1\+\),0 + 938: f2 f5 2c 08 swcpm1 \$c2,\(\$sp\+\),8 + +0000093c <lwcpm1>: + 93c: f8 85 6c 00 lwcpm1 \$c8,\(\$8\+\),0 + 940: f3 e5 6c f0 lwcpm1 \$c3,\(\$gp\+\),-16 + 944: f7 65 6c f8 lwcpm1 \$c7,\(\$6\+\),-8 + 948: fe 85 6c e8 lwcpm1 \$c14,\(\$8\+\),-24 + 94c: f3 85 6c 18 lwcpm1 \$c3,\(\$8\+\),24 + +00000950 <smcpm1>: + 950: fa 45 3c 00 smcpm1 \$c10,\(\$4\+\),0 + 954: f6 f5 3c f0 smcpm1 \$c6,\(\$sp\+\),-16 + 958: fd 75 3c e8 smcpm1 \$c13,\(\$7\+\),-24 + 95c: f3 e5 3c f8 smcpm1 \$c3,\(\$gp\+\),-8 + 960: f0 25 3c 08 smcpm1 \$c0,\(\$2\+\),8 + +00000964 <lmcpm1>: + 964: fc 15 7c 00 lmcpm1 \$c12,\(\$1\+\),0 + 968: f0 65 7c 08 lmcpm1 \$c0,\(\$6\+\),8 + 96c: f6 25 7c f8 lmcpm1 \$c6,\(\$2\+\),-8 + 970: fc e5 7c f0 lmcpm1 \$c12,\(\$gp\+\),-16 + 974: fe f5 7c 30 lmcpm1 \$c14,\(\$sp\+\),48 + +00000... <bcpeq>: + ...: d8 44 00 00 bcpeq 0x4,... <bcpeq> + ...: d8 04 ff ff bcpeq 0x0,... <bcpeq\+0x2> + ...: d8 44 ff ff bcpeq 0x4,... <bcpeq\+0x6> + ...: d8 14 00 01 bcpeq 0x1,... <bcpeq\+0xe> + ...: d8 24 00 01 bcpeq 0x2,... <bcpeq\+0x12> + +00000... <bcpne>: + ...: d8 25 00 00 bcpne 0x2,... <bcpne> + ...: d8 45 00 00 bcpne 0x4,... <bcpne\+0x4> + ...: d8 15 00 00 bcpne 0x1,... <bcpne\+0x8> + ...: d8 45 00 00 bcpne 0x4,... <bcpne\+0xc> + ...: d8 15 00 01 bcpne 0x1,... <bcpne\+0x12> + +00000... <bcpat>: + ...: d8 16 ff ff bcpat 0x1,... <bcpne\+0x12> + ...: d8 06 00 01 bcpat 0x0,... <bcpat\+0x6> + ...: d8 06 ff ff bcpat 0x0,... <bcpat\+0x6> + ...: d8 26 00 00 bcpat 0x2,... <bcpat\+0xc> + ...: d8 16 ff ff bcpat 0x1,... <bcpat\+0xe> + +00000... <bcpaf>: + ...: d8 47 00 00 bcpaf 0x4,... <bcpaf> + ...: d8 37 00 00 bcpaf 0x3,... <bcpaf\+0x4> + ...: d8 47 00 00 bcpaf 0x4,... <bcpaf\+0x8> + ...: d8 17 00 01 bcpaf 0x1,... <bcpaf\+0xe> + ...: d8 47 00 01 bcpaf 0x4,... <bcpaf\+0x12> + +00000... <synccp>: + ...: 70 21 synccp + +00000... <jsrv>: + ...: 18 bf jsrv \$11 + ...: 18 5f jsrv \$5 + ...: 18 af jsrv \$10 + ...: 18 cf jsrv \$12 + ...: 18 af jsrv \$10 + +00000... <bsrv>: + ...: df fb ff ff bsrv ... <jsrv\+0x8> + ...: df fb ff ff bsrv ... <bsrv\+0x2> + ...: df fb ff ff bsrv ... <bsrv\+0x6> + ...: d8 1b 00 00 bsrv ... <bsrv\+0xe> + ...: d8 0b 00 00 bsrv ... <bsrv\+0x10> + +00000... <case106341>: + ...: 7a 78 stc \$10,\$hi + ...: 70 8a ldc \$0,\$lo + +00000... <case106821>: + ...: 00 08 sb \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 08 sb \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 09 sh \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0a sw \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0c lb \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0d lh \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0e lw \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0b lbu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: 00 0f lhu \$0,\(\$0\) + ...: c0 08 00 01 sb \$0,1\(\$0\) + ...: c0 08 00 01 sb \$0,1\(\$0\) + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: c0 08 00 01 sb \$0,1\(\$0\) + ...: c0 08 00 01 sb \$0,1\(\$0\) + ...: c0 09 00 01 sh \$0,1\(\$0\) + ...: c0 09 00 01 sh \$0,1\(\$0\) + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: c0 09 00 01 sh \$0,1\(\$0\) + ...: c0 09 00 01 sh \$0,1\(\$0\) + ...: c0 0a 00 01 sw \$0,1\(\$0\) + ...: c0 0a 00 01 sw \$0,1\(\$0\) + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: c0 0a 00 01 sw \$0,1\(\$0\) + ...: c0 0a 00 01 sw \$0,1\(\$0\) + ...: c0 0c 00 01 lb \$0,1\(\$0\) + ...: c0 0c 00 01 lb \$0,1\(\$0\) + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: c0 0c 00 01 lb \$0,1\(\$0\) + ...: c0 0c 00 01 lb \$0,1\(\$0\) + ...: c0 0d 00 01 lh \$0,1\(\$0\) + ...: c0 0d 00 01 lh \$0,1\(\$0\) + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: c0 0d 00 01 lh \$0,1\(\$0\) + ...: c0 0d 00 01 lh \$0,1\(\$0\) + ...: c0 0e 00 01 lw \$0,1\(\$0\) + ...: c0 0e 00 01 lw \$0,1\(\$0\) + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: c0 0e 00 01 lw \$0,1\(\$0\) + ...: c0 0e 00 01 lw \$0,1\(\$0\) + ...: c0 0b 00 01 lbu \$0,1\(\$0\) + ...: c0 0b 00 01 lbu \$0,1\(\$0\) + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: c0 0b 00 01 lbu \$0,1\(\$0\) + ...: c0 0b 00 01 lbu \$0,1\(\$0\) + ...: c0 0f 00 01 lhu \$0,1\(\$0\) + ...: c0 0f 00 01 lhu \$0,1\(\$0\) + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: c0 0f 00 01 lhu \$0,1\(\$0\) + ...: c0 0f 00 01 lhu \$0,1\(\$0\) + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 08 00 00 sb \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 09 00 00 sh \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0a 00 00 sw \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0c 00 00 lb \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0d 00 00 lh \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0e 00 00 lw \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0b 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: c0 0f 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... diff --git a/gas/testsuite/gas/mep/allinsn.exp b/gas/testsuite/gas/mep/allinsn.exp new file mode 100644 index 000000000000..259ed10b1a14 --- /dev/null +++ b/gas/testsuite/gas/mep/allinsn.exp @@ -0,0 +1,9 @@ +# MEP assembler testsuite. -*- Tcl -*- + +if [istarget mep*-*-*] { + foreach test {allinsn dj1 dj2} { + run_dump_test $test + run_dump_test $test.le + } + run_dump_test branch1 +} diff --git a/gas/testsuite/gas/mep/allinsn.le.d b/gas/testsuite/gas/mep/allinsn.le.d new file mode 100644 index 000000000000..2d9c50bad6e0 --- /dev/null +++ b/gas/testsuite/gas/mep/allinsn.le.d @@ -0,0 +1,1346 @@ +#as: -EL +#objdump: -dr +#source: allinsn.s +#name: allinsn.le + +.*: +file format .* + +Disassembly of section .text: + +00000000 <sb>: + 0: 88 07 sb \$7,\(\$8\) + 2: 98 05 sb \$5,\(\$9\) + 4: e8 07 sb \$7,\(\$gp\) + 6: 88 0e sb \$gp,\(\$8\) + 8: e8 0f sb \$sp,\(\$gp\) + +0000000a <sh>: + a: 89 03 sh \$3,\(\$8\) + c: 19 0c sh \$12,\(\$1\) + e: 29 0d sh \$tp,\(\$2\) + 10: 89 02 sh \$2,\(\$8\) + 12: a9 0c sh \$12,\(\$10\) + +00000014 <sw>: + 14: 0a 0b sw \$11,\(\$0\) + 16: 7a 03 sw \$3,\(\$7\) + 18: ea 0d sw \$tp,\(\$gp\) + 1a: 9a 08 sw \$8,\(\$9\) + 1c: 8a 0e sw \$gp,\(\$8\) + +0000001e <lb>: + 1e: bc 0c lb \$12,\(\$11\) + 20: 2c 09 lb \$9,\(\$2\) + 22: bc 08 lb \$8,\(\$11\) + 24: 2c 0e lb \$gp,\(\$2\) + 26: cc 02 lb \$2,\(\$12\) + +00000028 <lh>: + 28: 8d 0f lh \$sp,\(\$8\) + 2a: ad 03 lh \$3,\(\$10\) + 2c: fd 09 lh \$9,\(\$sp\) + 2e: fd 06 lh \$6,\(\$sp\) + 30: bd 0f lh \$sp,\(\$11\) + +00000032 <lw>: + 32: ae 0c lw \$12,\(\$10\) + 34: de 09 lw \$9,\(\$tp\) + 36: ee 0c lw \$12,\(\$gp\) + 38: be 0c lw \$12,\(\$11\) + 3a: ae 0d lw \$tp,\(\$10\) + +0000003c <lbu>: + 3c: eb 0e lbu \$gp,\(\$gp\) + 3e: 8b 0c lbu \$12,\(\$8\) + 40: 1b 0e lbu \$gp,\(\$1\) + 42: cb 08 lbu \$8,\(\$12\) + 44: 1b 0c lbu \$12,\(\$1\) + +00000046 <lhu>: + 46: 4f 0f lhu \$sp,\(\$4\) + 48: 4f 0e lhu \$gp,\(\$4\) + 4a: 4f 05 lhu \$5,\(\$4\) + 4c: df 0f lhu \$sp,\(\$tp\) + 4e: ff 04 lhu \$4,\(\$sp\) + +00000050 <sw_sp>: + 50: 8a c9 03 00 sw \$9,3\(\$8\) + 54: 5a ca 04 00 sw \$10,4\(\$5\) + 58: ea c0 03 00 sw \$0,3\(\$gp\) + 5c: 8a c0 02 00 sw \$0,2\(\$8\) + 60: 8a cf 01 00 sw \$sp,1\(\$8\) + +00000064 <lw_sp>: + 64: 5e cd 01 00 lw \$tp,1\(\$5\) + 68: 0e cf 01 00 lw \$sp,1\(\$0\) + 6c: ce c0 04 00 lw \$0,4\(\$12\) + 70: de cb 01 00 lw \$11,1\(\$tp\) + 74: 4e c9 03 00 lw \$9,3\(\$4\) + +00000078 <sb_tp>: + 78: 18 c5 01 00 sb \$5,1\(\$1\) + 7c: 98 ca 01 00 sb \$10,1\(\$9\) + 80: 38 c5 03 00 sb \$5,3\(\$3\) + 84: 38 c5 01 00 sb \$5,1\(\$3\) + 88: 48 ca 04 00 sb \$10,4\(\$4\) + +0000008c <sh_tp>: + 8c: 09 c3 01 00 sh \$3,1\(\$0\) + 90: 99 cd 01 00 sh \$tp,1\(\$9\) + 94: a9 c9 04 00 sh \$9,4\(\$10\) + 98: e9 cf 03 00 sh \$sp,3\(\$gp\) + 9c: 99 ce 04 00 sh \$gp,4\(\$9\) + +000000a0 <sw_tp>: + a0: da c6 02 00 sw \$6,2\(\$tp\) + a4: fa c6 01 00 sw \$6,1\(\$sp\) + a8: 3a c2 02 00 sw \$2,2\(\$3\) + ac: ca c6 02 00 sw \$6,2\(\$12\) + b0: ba c3 01 00 sw \$3,1\(\$11\) + +000000b4 <lb_tp>: + b4: bc cd 04 00 lb \$tp,4\(\$11\) + b8: 8c cd 04 00 lb \$tp,4\(\$8\) + bc: 5c c5 04 00 lb \$5,4\(\$5\) + c0: ec cf 02 00 lb \$sp,2\(\$gp\) + c4: 3c c3 02 00 lb \$3,2\(\$3\) + +000000c8 <lh_tp>: + c8: 8d c7 02 00 lh \$7,2\(\$8\) + cc: 8d c4 03 00 lh \$4,3\(\$8\) + d0: fd ce 01 00 lh \$gp,1\(\$sp\) + d4: 0d c9 01 00 lh \$9,1\(\$0\) + d8: 0d cd 02 00 lh \$tp,2\(\$0\) + +000000dc <lw_tp>: + dc: 07 48 lw \$8,0x4\(\$sp\) + de: 9e cb 04 00 lw \$11,4\(\$9\) + e2: 2e ce 01 00 lw \$gp,1\(\$2\) + e6: ee c9 02 00 lw \$9,2\(\$gp\) + ea: ce c8 01 00 lw \$8,1\(\$12\) + +000000ee <lbu_tp>: + ee: 9b cc 01 00 lbu \$12,1\(\$9\) + f2: 9b cb 01 00 lbu \$11,1\(\$9\) + f6: 8b ce 03 00 lbu \$gp,3\(\$8\) + fa: fb c0 02 00 lbu \$0,2\(\$sp\) + fe: bb cd 01 00 lbu \$tp,1\(\$11\) + +00000102 <lhu_tp>: + 102: af ce 02 00 lhu \$gp,2\(\$10\) + 106: 8f cb 01 00 lhu \$11,1\(\$8\) + 10a: 0f c1 01 00 lhu \$1,1\(\$0\) + 10e: ff c7 02 00 lhu \$7,2\(\$sp\) + 112: 83 8b lhu \$3,0x2\(\$tp\) + +00000114 <sb16>: + 114: b8 c7 ff ff sb \$7,-1\(\$11\) + 118: e8 cd 01 00 sb \$tp,1\(\$gp\) + 11c: e8 c3 01 00 sb \$3,1\(\$gp\) + 120: 68 ce 02 00 sb \$gp,2\(\$6\) + 124: 78 ce 01 00 sb \$gp,1\(\$7\) + +00000128 <sh16>: + 128: 49 cc ff ff sh \$12,-1\(\$4\) + 12c: 19 cf 01 00 sh \$sp,1\(\$1\) + 130: c9 c2 fe ff sh \$2,-2\(\$12\) + 134: b9 c9 02 00 sh \$9,2\(\$11\) + 138: c9 c9 fe ff sh \$9,-2\(\$12\) + +0000013c <sw16>: + 13c: ea cb ff ff sw \$11,-1\(\$gp\) + 140: 06 44 sw \$4,0x4\(\$sp\) + 142: 3a c2 fe ff sw \$2,-2\(\$3\) + 146: 2a c6 ff ff sw \$6,-1\(\$2\) + 14a: da c8 fe ff sw \$8,-2\(\$tp\) + +0000014e <lb16>: + 14e: 2c ca fe ff lb \$10,-2\(\$2\) + 152: bc c3 fe ff lb \$3,-2\(\$11\) + 156: 5c cc 01 00 lb \$12,1\(\$5\) + 15a: 5c c5 01 00 lb \$5,1\(\$5\) + 15e: dc cb 02 00 lb \$11,2\(\$tp\) + +00000162 <lh16>: + 162: bd cf ff ff lh \$sp,-1\(\$11\) + 166: bd cd fe ff lh \$tp,-2\(\$11\) + 16a: ad c2 01 00 lh \$2,1\(\$10\) + 16e: 7d c8 ff ff lh \$8,-1\(\$7\) + 172: bd ce ff ff lh \$gp,-1\(\$11\) + +00000176 <lw16>: + 176: 5e c0 ff ff lw \$0,-1\(\$5\) + 17a: 7e cc fe ff lw \$12,-2\(\$7\) + 17e: 3e c1 fe ff lw \$1,-2\(\$3\) + 182: 7e c1 02 00 lw \$1,2\(\$7\) + 186: 8e c4 01 00 lw \$4,1\(\$8\) + +0000018a <lbu16>: + 18a: 4b cc ff ff lbu \$12,-1\(\$4\) + 18e: bb ce 01 00 lbu \$gp,1\(\$11\) + 192: db c1 ff ff lbu \$1,-1\(\$tp\) + 196: db c9 ff ff lbu \$9,-1\(\$tp\) + 19a: fb c8 01 00 lbu \$8,1\(\$sp\) + +0000019e <lhu16>: + 19e: ff cd ff ff lhu \$tp,-1\(\$sp\) + 1a2: 8f ce 02 00 lhu \$gp,2\(\$8\) + 1a6: cf cf ff ff lhu \$sp,-1\(\$12\) + 1aa: 0f c3 ff ff lhu \$3,-1\(\$0\) + 1ae: cf c3 fe ff lhu \$3,-2\(\$12\) + +000001b2 <sw24>: + 1b2: 06 eb 00 00 sw \$11,\(0x4\) + 1b6: 06 ef 00 00 sw \$sp,\(0x4\) + 1ba: 0a e7 00 00 sw \$7,\(0x8\) + 1be: 12 ea 00 00 sw \$10,\(0x10\) + 1c2: a2 e8 00 00 sw \$8,\(0xa0\) + +000001c6 <lw24>: + 1c6: 07 e4 00 00 lw \$4,\(0x4\) + 1ca: 07 ef 00 00 lw \$sp,\(0x4\) + 1ce: 13 e4 00 00 lw \$4,\(0x10\) + 1d2: 03 e8 00 00 lw \$8,\(0x0\) + 1d6: 0b ed 00 00 lw \$tp,\(0x8\) + +000001da <extb>: + 1da: 0d 1d extb \$tp + 1dc: 0d 1d extb \$tp + 1de: 0d 16 extb \$6 + 1e0: 0d 1e extb \$gp + 1e2: 0d 1a extb \$10 + +000001e4 <exth>: + 1e4: 2d 1f exth \$sp + 1e6: 2d 12 exth \$2 + 1e8: 2d 15 exth \$5 + 1ea: 2d 1a exth \$10 + 1ec: 2d 14 exth \$4 + +000001ee <extub>: + 1ee: 8d 12 extub \$2 + 1f0: 8d 1d extub \$tp + 1f2: 8d 13 extub \$3 + 1f4: 8d 19 extub \$9 + 1f6: 8d 1e extub \$gp + +000001f8 <extuh>: + 1f8: ad 18 extuh \$8 + 1fa: ad 18 extuh \$8 + 1fc: ad 14 extuh \$4 + 1fe: ad 10 extuh \$0 + 200: ad 10 extuh \$0 + +00000202 <ssarb>: + 202: 8c 12 ssarb 2\(\$8\) + 204: dc 12 ssarb 2\(\$tp\) + 206: dc 11 ssarb 1\(\$tp\) + 208: 5c 12 ssarb 2\(\$5\) + 20a: 9c 10 ssarb 0\(\$9\) + +0000020c <mov>: + 20c: 30 02 mov \$2,\$3 + 20e: b0 03 mov \$3,\$11 + 210: a0 0f mov \$sp,\$10 + 212: 00 0f mov \$sp,\$0 + 214: d0 03 mov \$3,\$tp + +00000216 <movi8>: + 216: ff 5b mov \$11,-1 + 218: 02 56 mov \$6,2 + 21a: ff 5f mov \$sp,-1 + 21c: 01 5f mov \$sp,1 + 21e: ff 5e mov \$gp,-1 + +00000220 <movi16>: + 220: 00 5f mov \$sp,0 + 222: 02 50 mov \$0,2 + 224: ff 58 mov \$8,-1 + 226: 01 5c mov \$12,1 + 228: ff 57 mov \$7,-1 + +0000022a <movu24>: + 22a: 01 d2 00 00 movu \$2,0x1 + 22e: 11 ca 04 00 movu \$10,0x4 + 232: 11 c9 00 00 movu \$9,0x0 + 236: 03 d4 00 00 movu \$4,0x3 + 23a: 11 ce 01 00 movu \$gp,0x1 + +0000023e <movu16>: + 23e: 11 cf 01 00 movu \$sp,0x1 + 242: 03 d6 00 00 movu \$6,0x3 + 246: 03 d0 00 00 movu \$0,0x3 + 24a: 11 ce 03 00 movu \$gp,0x3 + 24e: 11 ca 02 00 movu \$10,0x2 + +00000252 <movh>: + 252: 21 c8 02 00 movh \$8,0x2 + 256: 21 cd 01 00 movh \$tp,0x1 + 25a: 21 ce 02 00 movh \$gp,0x2 + 25e: 21 cc 00 00 movh \$12,0x0 + 262: 21 cb 02 00 movh \$11,0x2 + +00000266 <add3>: + 266: 36 9b add3 \$6,\$11,\$3 + 268: 5e 9d add3 \$gp,\$tp,\$5 + 26a: 73 9b add3 \$3,\$11,\$7 + 26c: dd 9e add3 \$tp,\$gp,\$tp + 26e: 80 9e add3 \$0,\$gp,\$8 + +00000270 <add>: + 270: 08 6c add \$12,2 + 272: fc 6c add \$12,-1 + 274: 04 64 add \$4,1 + 276: 04 66 add \$6,1 + 278: 08 66 add \$6,2 + +0000027a <add3i>: + 27a: 04 4b add3 \$11,\$sp,0x4 + 27c: f0 c4 01 00 add3 \$4,\$sp,1 + 280: 00 40 add3 \$0,\$sp,0x0 + 282: f0 cd 03 00 add3 \$tp,\$sp,3 + 286: 00 4b add3 \$11,\$sp,0x0 + +00000288 <advck3>: + 288: a7 0e advck3 \$0,\$gp,\$10 + 28a: 07 0d advck3 \$0,\$tp,\$0 + 28c: d7 0e advck3 \$0,\$gp,\$tp + 28e: 87 07 advck3 \$0,\$7,\$8 + 290: 27 01 advck3 \$0,\$1,\$2 + +00000292 <sub>: + 292: e4 08 sub \$8,\$gp + 294: 94 01 sub \$1,\$9 + 296: 74 0d sub \$tp,\$7 + 298: 34 0f sub \$sp,\$3 + 29a: 74 02 sub \$2,\$7 + +0000029c <sbvck3>: + 29c: e5 03 sbvck3 \$0,\$3,\$gp + 29e: 75 03 sbvck3 \$0,\$3,\$7 + 2a0: a5 0a sbvck3 \$0,\$10,\$10 + 2a2: d5 04 sbvck3 \$0,\$4,\$tp + 2a4: f5 0a sbvck3 \$0,\$10,\$sp + +000002a6 <neg>: + 2a6: 71 0e neg \$gp,\$7 + 2a8: 71 01 neg \$1,\$7 + 2aa: b1 02 neg \$2,\$11 + 2ac: 81 0d neg \$tp,\$8 + 2ae: d1 0e neg \$gp,\$tp + +000002b0 <slt3>: + 2b0: 82 0e slt3 \$0,\$gp,\$8 + 2b2: d2 04 slt3 \$0,\$4,\$tp + 2b4: e2 0a slt3 \$0,\$10,\$gp + 2b6: 52 0e slt3 \$0,\$gp,\$5 + 2b8: c2 03 slt3 \$0,\$3,\$12 + +000002ba <sltu3>: + 2ba: 83 02 sltu3 \$0,\$2,\$8 + 2bc: b3 0e sltu3 \$0,\$gp,\$11 + 2be: d3 02 sltu3 \$0,\$2,\$tp + 2c0: 83 09 sltu3 \$0,\$9,\$8 + 2c2: 93 06 sltu3 \$0,\$6,\$9 + +000002c4 <slt3i>: + 2c4: 11 66 slt3 \$0,\$6,0x2 + 2c6: 09 6b slt3 \$0,\$11,0x1 + 2c8: 01 6f slt3 \$0,\$sp,0x0 + 2ca: 01 63 slt3 \$0,\$3,0x0 + 2cc: 01 6d slt3 \$0,\$tp,0x0 + +000002ce <sltu3i>: + 2ce: 25 6e sltu3 \$0,\$gp,0x4 + 2d0: 1d 6d sltu3 \$0,\$tp,0x3 + 2d2: 0d 63 sltu3 \$0,\$3,0x1 + 2d4: 05 6c sltu3 \$0,\$12,0x0 + 2d6: 1d 61 sltu3 \$0,\$1,0x3 + +000002d8 <sl1ad3>: + 2d8: e6 28 sl1ad3 \$0,\$8,\$gp + 2da: 26 24 sl1ad3 \$0,\$4,\$2 + 2dc: c6 2f sl1ad3 \$0,\$sp,\$12 + 2de: 16 29 sl1ad3 \$0,\$9,\$1 + 2e0: 26 28 sl1ad3 \$0,\$8,\$2 + +000002e2 <sl2ad3>: + 2e2: d7 28 sl2ad3 \$0,\$8,\$tp + 2e4: 37 22 sl2ad3 \$0,\$2,\$3 + 2e6: 97 28 sl2ad3 \$0,\$8,\$9 + 2e8: c7 27 sl2ad3 \$0,\$7,\$12 + 2ea: c7 24 sl2ad3 \$0,\$4,\$12 + +000002ec <add3x>: + 2ec: b0 cd 01 00 add3 \$tp,\$11,1 + 2f0: 40 cd ff ff add3 \$tp,\$4,-1 + 2f4: d0 c2 01 00 add3 \$2,\$tp,1 + 2f8: e0 c3 01 00 add3 \$3,\$gp,1 + 2fc: f0 ca 02 00 add3 \$10,\$sp,2 + +00000300 <slt3x>: + 300: 12 c8 ff ff slt3 \$8,\$1,-1 + 304: 32 c0 fe ff slt3 \$0,\$3,-2 + 308: f2 c9 ff ff slt3 \$9,\$sp,-1 + 30c: 82 c3 02 00 slt3 \$3,\$8,2 + 310: e2 cd 00 00 slt3 \$tp,\$gp,0 + +00000314 <sltu3x>: + 314: b3 cf 02 00 sltu3 \$sp,\$11,0x2 + 318: 03 c6 01 00 sltu3 \$6,\$0,0x1 + 31c: b3 c9 03 00 sltu3 \$9,\$11,0x3 + 320: 05 64 sltu3 \$0,\$4,0x0 + 322: e3 cd 04 00 sltu3 \$tp,\$gp,0x4 + +00000326 <or>: + 326: e0 1f or \$sp,\$gp + 328: 30 18 or \$8,\$3 + 32a: f0 10 or \$0,\$sp + 32c: 00 1d or \$tp,\$0 + 32e: 60 18 or \$8,\$6 + +00000330 <and>: + 330: f1 1f and \$sp,\$sp + 332: e1 16 and \$6,\$gp + 334: 21 14 and \$4,\$2 + 336: 81 15 and \$5,\$8 + 338: e1 17 and \$7,\$gp + +0000033a <xor>: + 33a: c2 11 xor \$1,\$12 + 33c: d2 1c xor \$12,\$tp + 33e: 82 1a xor \$10,\$8 + 340: b2 1f xor \$sp,\$11 + 342: 82 1c xor \$12,\$8 + +00000344 <nor>: + 344: 53 19 nor \$9,\$5 + 346: 23 18 nor \$8,\$2 + 348: 93 1f nor \$sp,\$9 + 34a: f3 15 nor \$5,\$sp + 34c: e3 1f nor \$sp,\$gp + +0000034e <or3>: + 34e: f4 cd 02 00 or3 \$tp,\$sp,0x2 + 352: d4 cf 03 00 or3 \$sp,\$tp,0x3 + 356: a4 c0 04 00 or3 \$0,\$10,0x4 + 35a: f4 c9 03 00 or3 \$9,\$sp,0x3 + 35e: f4 c9 00 00 or3 \$9,\$sp,0x0 + +00000362 <and3>: + 362: 85 c5 01 00 and3 \$5,\$8,0x1 + 366: e5 cb 03 00 and3 \$11,\$gp,0x3 + 36a: 05 c6 00 00 and3 \$6,\$0,0x0 + 36e: f5 cf 00 00 and3 \$sp,\$sp,0x0 + 372: a5 c1 03 00 and3 \$1,\$10,0x3 + +00000376 <xor3>: + 376: 06 c0 02 00 xor3 \$0,\$0,0x2 + 37a: 66 cf 00 00 xor3 \$sp,\$6,0x0 + 37e: 56 cd 00 00 xor3 \$tp,\$5,0x0 + 382: 76 cf 00 00 xor3 \$sp,\$7,0x0 + 386: f6 cf 02 00 xor3 \$sp,\$sp,0x2 + +0000038a <sra>: + 38a: 1d 24 sra \$4,\$1 + 38c: fd 28 sra \$8,\$sp + 38e: 1d 21 sra \$1,\$1 + 390: 5d 20 sra \$0,\$5 + 392: 1d 29 sra \$9,\$1 + +00000394 <srl>: + 394: bc 22 srl \$2,\$11 + 396: 7c 2f srl \$sp,\$7 + 398: 7c 21 srl \$1,\$7 + 39a: dc 23 srl \$3,\$tp + 39c: 1c 2e srl \$gp,\$1 + +0000039e <sll>: + 39e: 0e 2b sll \$11,\$0 + 3a0: 8e 2d sll \$tp,\$8 + 3a2: 9e 28 sll \$8,\$9 + 3a4: fe 2d sll \$tp,\$sp + 3a6: fe 2f sll \$sp,\$sp + +000003a8 <srai>: + 3a8: 13 61 sra \$1,0x2 + 3aa: 1b 6f sra \$sp,0x3 + 3ac: 1b 6f sra \$sp,0x3 + 3ae: 23 66 sra \$6,0x4 + 3b0: 1b 6f sra \$sp,0x3 + +000003b2 <srli>: + 3b2: 02 6a srl \$10,0x0 + 3b4: 1a 69 srl \$9,0x3 + 3b6: 22 66 srl \$6,0x4 + 3b8: 12 6a srl \$10,0x2 + 3ba: 1a 68 srl \$8,0x3 + +000003bc <slli>: + 3bc: 06 60 sll \$0,0x0 + 3be: 06 64 sll \$4,0x0 + 3c0: 16 6d sll \$tp,0x2 + 3c2: 16 6b sll \$11,0x2 + 3c4: 06 66 sll \$6,0x0 + +000003c6 <sll3>: + 3c6: 27 6d sll3 \$0,\$tp,0x4 + 3c8: 07 6e sll3 \$0,\$gp,0x0 + 3ca: 17 68 sll3 \$0,\$8,0x2 + 3cc: 17 63 sll3 \$0,\$3,0x2 + 3ce: 07 68 sll3 \$0,\$8,0x0 + +000003d0 <fsft>: + 3d0: af 2e fsft \$gp,\$10 + 3d2: 9f 2e fsft \$gp,\$9 + 3d4: df 2f fsft \$sp,\$tp + 3d6: 3f 2b fsft \$11,\$3 + 3d8: 3f 25 fsft \$5,\$3 + +000003da <bra>: + 3da: 02 b0 bra 3dc <bra\+0x2> + 3dc: fe bf bra 3da <bra> + 3de: 02 b0 bra 3e0 <bra\+0x6> + 3e0: 00 b0 bra 3e0 <bra\+0x6> + 3e2: 02 b0 bra 3e4 <beqz> + +000003e4 <beqz>: + 3e4: fe a1 beqz \$1,3e2 <bra\+0x8> + 3e6: 02 af beqz \$sp,3e8 <beqz\+0x4> + 3e8: 04 a4 beqz \$4,3ec <beqz\+0x8> + 3ea: 00 a4 beqz \$4,3ea <beqz\+0x6> + 3ec: fe a9 beqz \$9,3ea <beqz\+0x6> + +000003ee <bnez>: + 3ee: 03 a8 bnez \$8,3f0 <bnez\+0x2> + 3f0: 03 ad bnez \$tp,3f2 <bnez\+0x4> + 3f2: 01 ae bnez \$gp,3f2 <bnez\+0x4> + 3f4: 03 a6 bnez \$6,3f6 <bnez\+0x8> + 3f6: fd a8 bnez \$8,3f2 <bnez\+0x4> + +000003f8 <beqi>: + 3f8: 30 ed 00 00 beqi \$tp,0x3,3f8 <beqi> + 3fc: 40 e0 ff ff beqi \$0,0x4,3fa <beqi\+0x2> + 400: 40 ef ff ff beqi \$sp,0x4,3fe <beqi\+0x6> + 404: 20 ed 00 00 beqi \$tp,0x2,404 <beqi\+0xc> + 408: 20 e4 fc ff beqi \$4,0x2,400 <beqi\+0x8> + +0000040c <bnei>: + 40c: 14 e8 00 00 bnei \$8,0x1,40c <bnei> + 410: 14 e5 01 00 bnei \$5,0x1,412 <bnei\+0x6> + 414: 04 e5 04 00 bnei \$5,0x0,41c <bnei\+0x10> + 418: 44 e9 ff ff bnei \$9,0x4,416 <bnei\+0xa> + 41c: 44 e0 fc ff bnei \$0,0x4,414 <bnei\+0x8> + +00000420 <blti>: + 420: 3c e7 00 00 blti \$7,0x3,420 <blti> + 424: 1c e1 00 00 blti \$1,0x1,424 <blti\+0x4> + 428: 2c e8 01 00 blti \$8,0x2,42a <blti\+0xa> + 42c: 2c eb 01 00 blti \$11,0x2,42e <blti\+0xe> + 430: 3c ef ff ff blti \$sp,0x3,42e <blti\+0xe> + +00000434 <bgei>: + 434: 38 e4 fc ff bgei \$4,0x3,42c <blti\+0xc> + 438: 08 e7 01 00 bgei \$7,0x0,43a <bgei\+0x6> + 43c: 18 ed 00 00 bgei \$tp,0x1,43c <bgei\+0x8> + 440: 28 e5 ff ff bgei \$5,0x2,43e <bgei\+0xa> + 444: 48 ec fc ff bgei \$12,0x4,43c <bgei\+0x8> + +00000448 <beq>: + 448: 21 e7 ff ff beq \$7,\$2,446 <bgei\+0x12> + 44c: 31 e1 fc ff beq \$1,\$3,444 <bgei\+0x10> + 450: 01 e2 01 00 beq \$2,\$0,452 <beq\+0xa> + 454: 81 ef 01 00 beq \$sp,\$8,456 <beq\+0xe> + 458: 01 e3 00 00 beq \$3,\$0,458 <beq\+0x10> + +0000045c <bne>: + 45c: 35 e6 00 00 bne \$6,\$3,45c <bne> + 460: 35 ef fc ff bne \$sp,\$3,458 <beq\+0x10> + 464: 05 e8 01 00 bne \$8,\$0,466 <bne\+0xa> + 468: f5 ee 04 00 bne \$gp,\$sp,470 <bsr12> + 46c: 45 ef 01 00 bne \$sp,\$4,46e <bne\+0x12> + +00000470 <bsr12>: + 470: 03 b0 bsr 472 <bsr12\+0x2> + 472: f9 bf bsr 46a <bne\+0xe> + 474: f1 bf bsr 464 <bne\+0x8> + 476: ff bf bsr 474 <bsr12\+0x4> + 478: f9 bf bsr 470 <bsr12> + +0000047a <bsr24>: + 47a: 05 b0 bsr 47e <bsr24\+0x4> + 47c: ff bf bsr 47a <bsr24> + 47e: fd bf bsr 47a <bsr24> + 480: 01 b0 bsr 480 <bsr24\+0x6> + 482: 03 b0 bsr 484 <jmp> + +00000484 <jmp>: + 484: 2e 10 jmp \$2 + 486: de 10 jmp \$tp + 488: 5e 10 jmp \$5 + 48a: fe 10 jmp \$sp + 48c: 8e 10 jmp \$8 + +0000048e <jmp24>: + 48e: 28 d8 00 00 jmp 4 <sb\+0x4> + 492: 18 d8 00 00 jmp 2 <sb\+0x2> + 496: 08 d8 00 00 jmp 0 <sb> + 49a: 18 d8 00 00 jmp 2 <sb\+0x2> + 49e: 28 d8 00 00 jmp 4 <sb\+0x4> + +000004a2 <jsr>: + 4a2: ff 10 jsr \$sp + 4a4: df 10 jsr \$tp + 4a6: df 10 jsr \$tp + 4a8: 6f 10 jsr \$6 + 4aa: 6f 10 jsr \$6 + +000004ac <ret>: + 4ac: 02 70 ret + +000004ae <repeat>: + 4ae: 09 e4 01 00 repeat \$4,4b0 <repeat\+0x2> + 4b2: 09 e8 02 00 repeat \$8,4b6 <repeat\+0x8> + 4b6: 09 e0 04 00 repeat \$0,4be <repeat\+0x10> + 4ba: 09 e6 01 00 repeat \$6,4bc <repeat\+0xe> + 4be: 09 e4 01 00 repeat \$4,4c0 <repeat\+0x12> + +000004c2 <erepeat>: + 4c2: 19 e0 01 00 erepeat 4c4 <erepeat\+0x2> + 4c6: 19 e0 00 00 erepeat 4c6 <erepeat\+0x4> + 4ca: 19 e0 01 00 erepeat 4cc <erepeat\+0xa> + 4ce: 19 e0 ff ff erepeat 4cc <erepeat\+0xa> + 4d2: 19 e0 00 00 erepeat 4d2 <erepeat\+0x10> + +000004d6 <stc>: + 4d6: e8 7d stc \$tp,\$mb1 + 4d8: c9 7d stc \$tp,\$ccfg + 4da: 89 7b stc \$11,\$dbg + 4dc: c9 7a stc \$10,\$ccfg + 4de: 39 79 stc \$9,\$epc + +000004e0 <ldc>: + 4e0: 8a 7d ldc \$tp,\$lo + 4e2: 7b 78 ldc \$8,\$npc + 4e4: ca 79 ldc \$9,\$mb0 + 4e6: 2a 7f ldc \$sp,\$sar + 4e8: cb 79 ldc \$9,\$ccfg + +000004ea <di>: + 4ea: 00 70 di + +000004ec <ei>: + 4ec: 10 70 ei + +000004ee <reti>: + 4ee: 12 70 reti + +000004f0 <halt>: + 4f0: 22 70 halt + +000004f2 <swi>: + 4f2: 26 70 swi 0x2 + 4f4: 06 70 swi 0x0 + 4f6: 26 70 swi 0x2 + 4f8: 36 70 swi 0x3 + 4fa: 16 70 swi 0x1 + +000004fc <break>: + 4fc: 32 70 break + +000004fe <syncm>: + 4fe: 11 70 syncm + +00000500 <stcb>: + 500: 04 f5 04 00 stcb \$5,0x4 + 504: 04 f5 01 00 stcb \$5,0x1 + 508: 04 fe 00 00 stcb \$gp,0x0 + 50c: 04 ff 04 00 stcb \$sp,0x4 + 510: 04 fb 02 00 stcb \$11,0x2 + +00000514 <ldcb>: + 514: 14 f2 03 00 ldcb \$2,0x3 + 518: 14 f2 04 00 ldcb \$2,0x4 + 51c: 14 f9 01 00 ldcb \$9,0x1 + 520: 14 fa 04 00 ldcb \$10,0x4 + 524: 14 f1 04 00 ldcb \$1,0x4 + +00000528 <bsetm>: + 528: a0 20 bsetm \(\$10\),0x0 + 52a: f0 20 bsetm \(\$sp\),0x0 + 52c: 10 22 bsetm \(\$1\),0x2 + 52e: f0 24 bsetm \(\$sp\),0x4 + 530: 80 24 bsetm \(\$8\),0x4 + +00000532 <bclrm>: + 532: 51 20 bclrm \(\$5\),0x0 + 534: 51 22 bclrm \(\$5\),0x2 + 536: 81 20 bclrm \(\$8\),0x0 + 538: 91 22 bclrm \(\$9\),0x2 + 53a: 51 23 bclrm \(\$5\),0x3 + +0000053c <bnotm>: + 53c: e2 24 bnotm \(\$gp\),0x4 + 53e: b2 24 bnotm \(\$11\),0x4 + 540: a2 20 bnotm \(\$10\),0x0 + 542: d2 24 bnotm \(\$tp\),0x4 + 544: 82 20 bnotm \(\$8\),0x0 + +00000546 <btstm>: + 546: e3 20 btstm \$0,\(\$gp\),0x0 + 548: e3 21 btstm \$0,\(\$gp\),0x1 + 54a: b3 20 btstm \$0,\(\$11\),0x0 + 54c: e3 23 btstm \$0,\(\$gp\),0x3 + 54e: 83 22 btstm \$0,\(\$8\),0x2 + +00000550 <tas>: + 550: d4 27 tas \$7,\(\$tp\) + 552: c4 27 tas \$7,\(\$12\) + 554: 84 23 tas \$3,\(\$8\) + 556: 54 22 tas \$2,\(\$5\) + 558: a4 26 tas \$6,\(\$10\) + +0000055a <cache>: + 55a: d4 71 cache 0x1,\(\$tp\) + 55c: c4 73 cache 0x3,\(\$12\) + 55e: 94 73 cache 0x3,\(\$9\) + 560: 24 74 cache 0x4,\(\$2\) + 562: 74 74 cache 0x4,\(\$7\) + +00000564 <mul>: + 564: e4 18 mul \$8,\$gp + 566: 94 12 mul \$2,\$9 + 568: f4 1e mul \$gp,\$sp + 56a: 74 19 mul \$9,\$7 + 56c: b4 17 mul \$7,\$11 + +0000056e <mulu>: + 56e: 55 12 mulu \$2,\$5 + 570: e5 16 mulu \$6,\$gp + 572: f5 1e mulu \$gp,\$sp + 574: e5 1b mulu \$11,\$gp + 576: 95 13 mulu \$3,\$9 + +00000578 <mulr>: + 578: 66 1c mulr \$12,\$6 + 57a: 86 1d mulr \$tp,\$8 + 57c: a6 17 mulr \$7,\$10 + 57e: 16 1e mulr \$gp,\$1 + 580: f6 10 mulr \$0,\$sp + +00000582 <mulru>: + 582: 27 14 mulru \$4,\$2 + 584: 17 1e mulru \$gp,\$1 + 586: 47 1f mulru \$sp,\$4 + 588: 67 1a mulru \$10,\$6 + 58a: e7 10 mulru \$0,\$gp + +0000058c <madd>: + 58c: b1 f4 04 30 madd \$4,\$11 + 590: e1 ff 04 30 madd \$sp,\$gp + 594: f1 fe 04 30 madd \$gp,\$sp + 598: d1 f4 04 30 madd \$4,\$tp + 59c: e1 f1 04 30 madd \$1,\$gp + +000005a0 <maddu>: + 5a0: 11 f0 05 30 maddu \$0,\$1 + 5a4: 61 f7 05 30 maddu \$7,\$6 + 5a8: 51 f9 05 30 maddu \$9,\$5 + 5ac: f1 fe 05 30 maddu \$gp,\$sp + 5b0: d1 f7 05 30 maddu \$7,\$tp + +000005b4 <maddr>: + 5b4: 81 f6 06 30 maddr \$6,\$8 + 5b8: e1 f9 06 30 maddr \$9,\$gp + 5bc: e1 f8 06 30 maddr \$8,\$gp + 5c0: 21 f3 06 30 maddr \$3,\$2 + 5c4: b1 f1 06 30 maddr \$1,\$11 + +000005c8 <maddru>: + 5c8: 31 fa 07 30 maddru \$10,\$3 + 5cc: c1 ff 07 30 maddru \$sp,\$12 + 5d0: 81 f8 07 30 maddru \$8,\$8 + 5d4: 31 fe 07 30 maddru \$gp,\$3 + 5d8: f1 f8 07 30 maddru \$8,\$sp + +000005dc <div>: + 5dc: 38 19 div \$9,\$3 + 5de: e8 14 div \$4,\$gp + 5e0: c8 12 div \$2,\$12 + 5e2: d8 18 div \$8,\$tp + 5e4: 68 1d div \$tp,\$6 + +000005e6 <divu>: + 5e6: 59 19 divu \$9,\$5 + 5e8: d9 18 divu \$8,\$tp + 5ea: e9 10 divu \$0,\$gp + 5ec: 59 19 divu \$9,\$5 + 5ee: 59 10 divu \$0,\$5 + +000005f0 <dret>: + 5f0: 13 70 dret + +000005f2 <dbreak>: + 5f2: 33 70 dbreak + +000005f4 <ldz>: + 5f4: 41 fe 00 00 ldz \$gp,\$4 + 5f8: b1 fa 00 00 ldz \$10,\$11 + 5fc: 91 f9 00 00 ldz \$9,\$9 + 600: d1 ff 00 00 ldz \$sp,\$tp + 604: 31 fe 00 00 ldz \$gp,\$3 + +00000608 <abs>: + 608: 91 ff 03 00 abs \$sp,\$9 + 60c: 41 f5 03 00 abs \$5,\$4 + 610: d1 fd 03 00 abs \$tp,\$tp + 614: 31 f0 03 00 abs \$0,\$3 + 618: e1 f3 03 00 abs \$3,\$gp + +0000061c <ave>: + 61c: a1 fb 02 00 ave \$11,\$10 + 620: a1 f8 02 00 ave \$8,\$10 + 624: 21 fe 02 00 ave \$gp,\$2 + 628: c1 fa 02 00 ave \$10,\$12 + 62c: 81 ff 02 00 ave \$sp,\$8 + +00000630 <min>: + 630: 31 f8 04 00 min \$8,\$3 + 634: 01 f7 04 00 min \$7,\$0 + 638: 21 f2 04 00 min \$2,\$2 + 63c: 61 f5 04 00 min \$5,\$6 + 640: 51 fb 04 00 min \$11,\$5 + +00000644 <max>: + 644: f1 fb 05 00 max \$11,\$sp + 648: 01 fe 05 00 max \$gp,\$0 + 64c: f1 fc 05 00 max \$12,\$sp + 650: 21 fe 05 00 max \$gp,\$2 + 654: f1 fe 05 00 max \$gp,\$sp + +00000658 <minu>: + 658: 81 fb 06 00 minu \$11,\$8 + 65c: 51 f7 06 00 minu \$7,\$5 + 660: e1 f8 06 00 minu \$8,\$gp + 664: 41 fb 06 00 minu \$11,\$4 + 668: f1 f2 06 00 minu \$2,\$sp + +0000066c <maxu>: + 66c: 31 f3 07 00 maxu \$3,\$3 + 670: 01 fd 07 00 maxu \$tp,\$0 + 674: 81 f4 07 00 maxu \$4,\$8 + 678: 21 fe 07 00 maxu \$gp,\$2 + 67c: 81 fc 07 00 maxu \$12,\$8 + +00000680 <clip>: + 680: 01 fa 08 10 clip \$10,0x1 + 684: 01 ff 20 10 clip \$sp,0x4 + 688: 01 f4 18 10 clip \$4,0x3 + 68c: 01 ff 18 10 clip \$sp,0x3 + 690: 01 f1 00 10 clip \$1,0x0 + +00000694 <clipu>: + 694: 01 fa 21 10 clipu \$10,0x4 + 698: 01 fd 09 10 clipu \$tp,0x1 + 69c: 01 f5 21 10 clipu \$5,0x4 + 6a0: 01 fe 01 10 clipu \$gp,0x0 + 6a4: 01 f5 09 10 clipu \$5,0x1 + +000006a8 <sadd>: + 6a8: 01 f5 08 00 sadd \$5,\$0 + 6ac: 31 ff 08 00 sadd \$sp,\$3 + 6b0: a1 f0 08 00 sadd \$0,\$10 + 6b4: c1 ff 08 00 sadd \$sp,\$12 + 6b8: 21 f4 08 00 sadd \$4,\$2 + +000006bc <ssub>: + 6bc: a1 f1 0a 00 ssub \$1,\$10 + 6c0: 71 f4 0a 00 ssub \$4,\$7 + 6c4: 31 f8 0a 00 ssub \$8,\$3 + 6c8: e1 f7 0a 00 ssub \$7,\$gp + 6cc: 41 fd 0a 00 ssub \$tp,\$4 + +000006d0 <saddu>: + 6d0: e1 f9 09 00 saddu \$9,\$gp + 6d4: a1 f0 09 00 saddu \$0,\$10 + 6d8: c1 f7 09 00 saddu \$7,\$12 + 6dc: f1 f5 09 00 saddu \$5,\$sp + 6e0: 31 fd 09 00 saddu \$tp,\$3 + +000006e4 <ssubu>: + 6e4: e1 ff 0b 00 ssubu \$sp,\$gp + 6e8: f1 f0 0b 00 ssubu \$0,\$sp + 6ec: a1 f3 0b 00 ssubu \$3,\$10 + 6f0: d1 ff 0b 00 ssubu \$sp,\$tp + 6f4: 91 f2 0b 00 ssubu \$2,\$9 + +000006f8 <swcp>: + 6f8: d8 33 swcp \$c3,\(\$tp\) + 6fa: d8 3f swcp \$c15,\(\$tp\) + 6fc: 08 3d swcp \$c13,\(\$0\) + 6fe: c8 3c swcp \$c12,\(\$12\) + 700: e8 39 swcp \$c9,\(\$gp\) + +00000702 <lwcp>: + 702: 39 37 lwcp \$c7,\(\$3\) + 704: 39 36 lwcp \$c6,\(\$3\) + 706: 29 30 lwcp \$c0,\(\$2\) + 708: 89 38 lwcp \$c8,\(\$8\) + 70a: d9 3b lwcp \$c11,\(\$tp\) + +0000070c <smcp>: + 70c: 9a 3e smcp \$c14,\(\$9\) + 70e: 8a 32 smcp \$c2,\(\$8\) + 710: fa 3e smcp \$c14,\(\$sp\) + 712: 8a 3a smcp \$c10,\(\$8\) + 714: 8a 32 smcp \$c2,\(\$8\) + +00000716 <lmcp>: + 716: 1b 3b lmcp \$c11,\(\$1\) + 718: 8b 38 lmcp \$c8,\(\$8\) + 71a: db 3b lmcp \$c11,\(\$tp\) + 71c: 0b 38 lmcp \$c8,\(\$0\) + 71e: eb 38 lmcp \$c8,\(\$gp\) + +00000720 <swcpi>: + 720: 00 37 swcpi \$c7,\(\$0\+\) + 722: e0 36 swcpi \$c6,\(\$gp\+\) + 724: 80 3c swcpi \$c12,\(\$8\+\) + 726: f0 3e swcpi \$c14,\(\$sp\+\) + 728: 00 36 swcpi \$c6,\(\$0\+\) + +0000072a <lwcpi>: + 72a: 21 38 lwcpi \$c8,\(\$2\+\) + 72c: 01 39 lwcpi \$c9,\(\$0\+\) + 72e: e1 33 lwcpi \$c3,\(\$gp\+\) + 730: 51 3d lwcpi \$c13,\(\$5\+\) + 732: e1 3b lwcpi \$c11,\(\$gp\+\) + +00000734 <smcpi>: + 734: 22 38 smcpi \$c8,\(\$2\+\) + 736: 92 3b smcpi \$c11,\(\$9\+\) + 738: 32 34 smcpi \$c4,\(\$3\+\) + 73a: 22 3e smcpi \$c14,\(\$2\+\) + 73c: 32 39 smcpi \$c9,\(\$3\+\) + +0000073e <lmcpi>: + 73e: e3 36 lmcpi \$c6,\(\$gp\+\) + 740: 53 39 lmcpi \$c9,\(\$5\+\) + 742: 63 3a lmcpi \$c10,\(\$6\+\) + 744: 63 31 lmcpi \$c1,\(\$6\+\) + 746: 83 32 lmcpi \$c2,\(\$8\+\) + +00000748 <swcp16>: + 748: 2c f0 ff ff swcp \$c0,-1\(\$2\) + 74c: ac f5 01 00 swcp \$c5,1\(\$10\) + 750: cc f8 02 00 swcp \$c8,2\(\$12\) + 754: 1c fe ff ff swcp \$c14,-1\(\$1\) + 758: 3c fc 02 00 swcp \$c12,2\(\$3\) + +0000075c <lwcp16>: + 75c: 5d f8 ff ff lwcp \$c8,-1\(\$5\) + 760: fd fc 01 00 lwcp \$c12,1\(\$sp\) + 764: 0d f1 02 00 lwcp \$c1,2\(\$0\) + 768: dd f4 01 00 lwcp \$c4,1\(\$tp\) + 76c: bd f6 02 00 lwcp \$c6,2\(\$11\) + +00000770 <smcp16>: + 770: ae f9 ff ff smcp \$c9,-1\(\$10\) + 774: ee fe 01 00 smcp \$c14,1\(\$gp\) + 778: fe f3 02 00 smcp \$c3,2\(\$sp\) + 77c: 8e ff fe ff smcp \$c15,-2\(\$8\) + 780: de fd 01 00 smcp \$c13,1\(\$tp\) + +00000784 <lmcp16>: + 784: ff f0 01 00 lmcp \$c0,1\(\$sp\) + 788: 8f ff 01 00 lmcp \$c15,1\(\$8\) + 78c: 8f f2 ff ff lmcp \$c2,-1\(\$8\) + 790: 8f fe 01 00 lmcp \$c14,1\(\$8\) + 794: af f1 ff ff lmcp \$c1,-1\(\$10\) + +00000798 <sbcpa>: + 798: f5 fe 02 00 sbcpa \$c14,\(\$sp\+\),2 + 79c: 45 f2 fe 00 sbcpa \$c2,\(\$4\+\),-2 + 7a0: 15 f8 00 00 sbcpa \$c8,\(\$1\+\),0 + 7a4: 35 fb 00 00 sbcpa \$c11,\(\$3\+\),0 + 7a8: e5 f9 fe 00 sbcpa \$c9,\(\$gp\+\),-2 + +000007ac <lbcpa>: + 7ac: 25 f7 fe 40 lbcpa \$c7,\(\$2\+\),-2 + 7b0: f5 fc 02 40 lbcpa \$c12,\(\$sp\+\),2 + 7b4: 45 f5 fe 40 lbcpa \$c5,\(\$4\+\),-2 + 7b8: 45 f7 fe 40 lbcpa \$c7,\(\$4\+\),-2 + 7bc: f5 f8 00 40 lbcpa \$c8,\(\$sp\+\),0 + +000007c0 <shcpa>: + 7c0: e5 f0 00 10 shcpa \$c0,\(\$gp\+\),0 + 7c4: f5 fc 10 10 shcpa \$c12,\(\$sp\+\),16 + 7c8: 45 f1 04 10 shcpa \$c1,\(\$4\+\),4 + 7cc: 45 f5 e0 10 shcpa \$c5,\(\$4\+\),-32 + 7d0: f5 f1 00 10 shcpa \$c1,\(\$sp\+\),0 + +000007d4 <lhcpa>: + 7d4: 45 f4 00 50 lhcpa \$c4,\(\$4\+\),0 + 7d8: 55 f6 30 50 lhcpa \$c6,\(\$5\+\),48 + 7dc: 65 f3 cc 50 lhcpa \$c3,\(\$6\+\),-52 + 7e0: 65 f8 e8 50 lhcpa \$c8,\(\$6\+\),-24 + 7e4: 95 f0 00 50 lhcpa \$c0,\(\$9\+\),0 + +000007e8 <swcpa>: + 7e8: 95 f1 10 20 swcpa \$c1,\(\$9\+\),16 + 7ec: f5 f7 20 20 swcpa \$c7,\(\$sp\+\),32 + 7f0: c5 f3 30 20 swcpa \$c3,\(\$12\+\),48 + 7f4: 95 fa 08 20 swcpa \$c10,\(\$9\+\),8 + 7f8: 85 fe 04 20 swcpa \$c14,\(\$8\+\),4 + +000007fc <lwcpa>: + 7fc: e5 f6 f8 60 lwcpa \$c6,\(\$gp\+\),-8 + 800: 75 f4 04 60 lwcpa \$c4,\(\$7\+\),4 + 804: e5 fb f0 60 lwcpa \$c11,\(\$gp\+\),-16 + 808: f5 fa e0 60 lwcpa \$c10,\(\$sp\+\),-32 + 80c: 25 f2 08 60 lwcpa \$c2,\(\$2\+\),8 + +00000810 <smcpa>: + 810: f5 fd f8 30 smcpa \$c13,\(\$sp\+\),-8 + 814: 75 f6 f8 30 smcpa \$c6,\(\$7\+\),-8 + 818: 35 f5 10 30 smcpa \$c5,\(\$3\+\),16 + 81c: f5 fd 10 30 smcpa \$c13,\(\$sp\+\),16 + 820: c5 f3 30 30 smcpa \$c3,\(\$12\+\),48 + +00000824 <lmcpa>: + 824: 45 f9 00 70 lmcpa \$c9,\(\$4\+\),0 + 828: f5 f3 f0 70 lmcpa \$c3,\(\$sp\+\),-16 + 82c: d5 ff 08 70 lmcpa \$c15,\(\$tp\+\),8 + 830: 85 f8 f8 70 lmcpa \$c8,\(\$8\+\),-8 + 834: 95 fa 00 70 lmcpa \$c10,\(\$9\+\),0 + +00000838 <sbcpm0>: + 838: d5 fa 08 08 sbcpm0 \$c10,\(\$tp\+\),8 + 83c: 55 fd f8 08 sbcpm0 \$c13,\(\$5\+\),-8 + 840: 55 f4 f8 08 sbcpm0 \$c4,\(\$5\+\),-8 + 844: d5 fa 10 08 sbcpm0 \$c10,\(\$tp\+\),16 + 848: 55 f4 e8 08 sbcpm0 \$c4,\(\$5\+\),-24 + +0000084c <lbcpm0>: + 84c: 45 f0 00 48 lbcpm0 \$c0,\(\$4\+\),0 + 850: 75 f9 f8 48 lbcpm0 \$c9,\(\$7\+\),-8 + 854: 85 fc 18 48 lbcpm0 \$c12,\(\$8\+\),24 + 858: c5 f8 10 48 lbcpm0 \$c8,\(\$12\+\),16 + 85c: 85 f7 10 48 lbcpm0 \$c7,\(\$8\+\),16 + +00000860 <shcpm0>: + 860: d5 f2 02 18 shcpm0 \$c2,\(\$tp\+\),2 + 864: f5 f7 fe 18 shcpm0 \$c7,\(\$sp\+\),-2 + 868: 25 f8 02 18 shcpm0 \$c8,\(\$2\+\),2 + 86c: 55 fd 00 18 shcpm0 \$c13,\(\$5\+\),0 + 870: e5 f3 08 18 shcpm0 \$c3,\(\$gp\+\),8 + +00000874 <lhcpm0>: + 874: 45 f7 08 58 lhcpm0 \$c7,\(\$4\+\),8 + 878: 35 f3 fe 58 lhcpm0 \$c3,\(\$3\+\),-2 + 87c: 15 f3 00 58 lhcpm0 \$c3,\(\$1\+\),0 + 880: e5 f2 00 58 lhcpm0 \$c2,\(\$gp\+\),0 + 884: 65 fc 02 58 lhcpm0 \$c12,\(\$6\+\),2 + +00000888 <swcpm0>: + 888: 85 f8 20 28 swcpm0 \$c8,\(\$8\+\),32 + 88c: f5 f9 00 28 swcpm0 \$c9,\(\$sp\+\),0 + 890: 25 f9 f0 28 swcpm0 \$c9,\(\$2\+\),-16 + 894: e5 f0 30 28 swcpm0 \$c0,\(\$gp\+\),48 + 898: 15 ff 08 28 swcpm0 \$c15,\(\$1\+\),8 + +0000089c <lwcpm0>: + 89c: a5 fe fc 68 lwcpm0 \$c14,\(\$10\+\),-4 + 8a0: f5 fb fc 68 lwcpm0 \$c11,\(\$sp\+\),-4 + 8a4: 75 f5 f8 68 lwcpm0 \$c5,\(\$7\+\),-8 + 8a8: c5 f2 20 68 lwcpm0 \$c2,\(\$12\+\),32 + 8ac: e5 f2 10 68 lwcpm0 \$c2,\(\$gp\+\),16 + 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<shcpm1>: + 900: 85 f4 18 1c shcpm1 \$c4,\(\$8\+\),24 + 904: 65 fb f0 1c shcpm1 \$c11,\(\$6\+\),-16 + 908: 85 f7 08 1c shcpm1 \$c7,\(\$8\+\),8 + 90c: c5 f5 10 1c shcpm1 \$c5,\(\$12\+\),16 + 910: 85 f0 e0 1c shcpm1 \$c0,\(\$8\+\),-32 + +00000914 <lhcpm1>: + 914: 05 fb 00 5c lhcpm1 \$c11,\(\$0\+\),0 + 918: d5 f7 fe 5c lhcpm1 \$c7,\(\$tp\+\),-2 + 91c: 85 fa 08 5c lhcpm1 \$c10,\(\$8\+\),8 + 920: d5 f3 00 5c lhcpm1 \$c3,\(\$tp\+\),0 + 924: 65 f9 02 5c lhcpm1 \$c9,\(\$6\+\),2 + +00000928 <swcpm1>: + 928: 85 f9 18 2c swcpm1 \$c9,\(\$8\+\),24 + 92c: e5 f9 00 2c swcpm1 \$c9,\(\$gp\+\),0 + 930: 85 f9 10 2c swcpm1 \$c9,\(\$8\+\),16 + 934: 15 fe 00 2c swcpm1 \$c14,\(\$1\+\),0 + 938: f5 f2 08 2c swcpm1 \$c2,\(\$sp\+\),8 + +0000093c <lwcpm1>: + 93c: 85 f8 00 6c lwcpm1 \$c8,\(\$8\+\),0 + 940: e5 f3 f0 6c lwcpm1 \$c3,\(\$gp\+\),-16 + 944: 65 f7 f8 6c lwcpm1 \$c7,\(\$6\+\),-8 + 948: 85 fe e8 6c lwcpm1 \$c14,\(\$8\+\),-24 + 94c: 85 f3 18 6c lwcpm1 \$c3,\(\$8\+\),24 + +00000950 <smcpm1>: + 950: 45 fa 00 3c smcpm1 \$c10,\(\$4\+\),0 + 954: f5 f6 f0 3c smcpm1 \$c6,\(\$sp\+\),-16 + 958: 75 fd e8 3c smcpm1 \$c13,\(\$7\+\),-24 + 95c: e5 f3 f8 3c smcpm1 \$c3,\(\$gp\+\),-8 + 960: 25 f0 08 3c smcpm1 \$c0,\(\$2\+\),8 + +00000964 <lmcpm1>: + 964: 15 fc 00 7c lmcpm1 \$c12,\(\$1\+\),0 + 968: 65 f0 08 7c lmcpm1 \$c0,\(\$6\+\),8 + 96c: 25 f6 f8 7c lmcpm1 \$c6,\(\$2\+\),-8 + 970: e5 fc f0 7c lmcpm1 \$c12,\(\$gp\+\),-16 + 974: f5 fe 30 7c lmcpm1 \$c14,\(\$sp\+\),48 + +00000... <bcpeq>: + ...: 44 d8 00 00 bcpeq 0x4,... <bcpeq> + ...: 04 d8 ff ff bcpeq 0x0,... <bcpeq\+0x2> + ...: 44 d8 ff ff bcpeq 0x4,... <bcpeq\+0x6> + ...: 14 d8 01 00 bcpeq 0x1,... <bcpeq\+0xe> + ...: 24 d8 01 00 bcpeq 0x2,... <bcpeq\+0x12> + +00000... <bcpne>: + ...: 25 d8 00 00 bcpne 0x2,... <bcpne> + ...: 45 d8 00 00 bcpne 0x4,... <bcpne\+0x4> + ...: 15 d8 00 00 bcpne 0x1,... <bcpne\+0x8> + ...: 45 d8 00 00 bcpne 0x4,... <bcpne\+0xc> + ...: 15 d8 01 00 bcpne 0x1,... <bcpne\+0x12> + +00000... <bcpat>: + ...: 16 d8 ff ff bcpat 0x1,... <bcpne\+0x12> + ...: 06 d8 01 00 bcpat 0x0,... <bcpat\+0x6> + ...: 06 d8 ff ff bcpat 0x0,... <bcpat\+0x6> + ...: 26 d8 00 00 bcpat 0x2,... <bcpat\+0xc> + ...: 16 d8 ff ff bcpat 0x1,... <bcpat\+0xe> + +00000... <bcpaf>: + ...: 47 d8 00 00 bcpaf 0x4,... <bcpaf> + ...: 37 d8 00 00 bcpaf 0x3,... <bcpaf\+0x4> + ...: 47 d8 00 00 bcpaf 0x4,... <bcpaf\+0x8> + ...: 17 d8 01 00 bcpaf 0x1,... <bcpaf\+0xe> + ...: 47 d8 01 00 bcpaf 0x4,... <bcpaf\+0x12> + +00000... <synccp>: + ...: 21 70 synccp + +00000... <jsrv>: + ...: bf 18 jsrv \$11 + ...: 5f 18 jsrv \$5 + ...: af 18 jsrv \$10 + ...: cf 18 jsrv \$12 + ...: af 18 jsrv \$10 + +00000... <bsrv>: + ...: fb df ff ff bsrv ... <jsrv\+0x8> + ...: fb df ff ff bsrv ... <bsrv\+0x2> + ...: fb df ff ff bsrv ... <bsrv\+0x6> + ...: 1b d8 00 00 bsrv ... <bsrv\+0xe> + ...: 0b d8 00 00 bsrv ... <bsrv\+0x10> + +00000... <case106341>: + ...: 78 7a stc \$10,\$hi + ...: 8a 70 ldc \$0,\$lo + +00000... <case106821>: + ...: 08 00 sb \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 08 00 sb \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 09 00 sh \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0a 00 sw \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0c 00 lb \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0d 00 lh \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0e 00 lw \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0b 00 lbu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 0f 00 lhu \$0,\(\$0\) + ...: 08 c0 01 00 sb \$0,1\(\$0\) + ...: 08 c0 01 00 sb \$0,1\(\$0\) + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: 08 c0 01 00 sb \$0,1\(\$0\) + ...: 08 c0 01 00 sb \$0,1\(\$0\) + ...: 09 c0 01 00 sh \$0,1\(\$0\) + ...: 09 c0 01 00 sh \$0,1\(\$0\) + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: 09 c0 01 00 sh \$0,1\(\$0\) + ...: 09 c0 01 00 sh \$0,1\(\$0\) + ...: 0a c0 01 00 sw \$0,1\(\$0\) + ...: 0a c0 01 00 sw \$0,1\(\$0\) + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: 0a c0 01 00 sw \$0,1\(\$0\) + ...: 0a c0 01 00 sw \$0,1\(\$0\) + ...: 0c c0 01 00 lb \$0,1\(\$0\) + ...: 0c c0 01 00 lb \$0,1\(\$0\) + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: 0c c0 01 00 lb \$0,1\(\$0\) + ...: 0c c0 01 00 lb \$0,1\(\$0\) + ...: 0d c0 01 00 lh \$0,1\(\$0\) + ...: 0d c0 01 00 lh \$0,1\(\$0\) + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: 0d c0 01 00 lh \$0,1\(\$0\) + ...: 0d c0 01 00 lh \$0,1\(\$0\) + ...: 0e c0 01 00 lw \$0,1\(\$0\) + ...: 0e c0 01 00 lw \$0,1\(\$0\) + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: 0e c0 01 00 lw \$0,1\(\$0\) + ...: 0e c0 01 00 lw \$0,1\(\$0\) + ...: 0b c0 01 00 lbu \$0,1\(\$0\) + ...: 0b c0 01 00 lbu \$0,1\(\$0\) + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: 0b c0 01 00 lbu \$0,1\(\$0\) + ...: 0b c0 01 00 lbu \$0,1\(\$0\) + ...: 0f c0 01 00 lhu \$0,1\(\$0\) + ...: 0f c0 01 00 lhu \$0,1\(\$0\) + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: 0f c0 01 00 lhu \$0,1\(\$0\) + ...: 0f c0 01 00 lhu \$0,1\(\$0\) + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 08 c0 00 00 sb \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 09 c0 00 00 sh \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0a c0 00 00 sw \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0c c0 00 00 lb \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0d c0 00 00 lh \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0e c0 00 00 lw \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0b c0 00 00 lbu \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_16 .text\+0x... + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_LOW16 .text\+0x... + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_HI16S .text\+0x... + ...: 0f c0 00 00 lhu \$0,0\(\$0\) + ...: R_MEP_HI16U .text\+0x... diff --git a/gas/testsuite/gas/mep/allinsn.s b/gas/testsuite/gas/mep/allinsn.s new file mode 100644 index 000000000000..784337c865d3 --- /dev/null +++ b/gas/testsuite/gas/mep/allinsn.s @@ -0,0 +1,1536 @@ + .data +foodata: .word 42 + .text +footext: + .text + .global sb +sb: + sb $7,($fp) + sb $5,($9) + sb $7,($14) + sb $14,($fp) + sb $15,($14) + .text + .global sh +sh: + sh $3,($fp) + sh $12,($1) + sh $13,($2) + sh $2,($8) + sh $12,($10) + .text + .global sw +sw: + sw $11,($0) + sw $3,($7) + sw $13,($14) + sw $8,($9) + sw $gp,($fp) + .text + .global lb +lb: + lb $12,($11) + lb $9,($2) + lb $fp,($11) + lb $gp,($2) + lb $2,($12) + .text + .global lh +lh: + lh $15,($8) + lh $3,($10) + lh $9,($sp) + lh $6,($sp) + lh $15,($11) + .text + .global lw +lw: + lw $12,($10) + lw $9,($13) + lw $12,($gp) + lw $12,($11) + lw $13,($10) + .text + .global lbu +lbu: + lbu $14,($14) + lbu $12,($fp) + lbu $gp,($1) + lbu $fp,($12) + lbu $12,($1) + .text + .global lhu +lhu: + lhu $15,($4) + lhu $14,($4) + lhu $5,($4) + lhu $sp,($tp) + lhu $4,($15) + .text + .global sw_sp +sw_sp: + sw $9,3($8) + sw $10,4($5) + sw $0,3($gp) + sw $0,2($8) + sw $15,1($8) + .text + .global lw_sp +lw_sp: + lw $tp,1($5) + lw $15,1($0) + lw $0,4($12) + lw $11,1($tp) + lw $9,3($4) + .text + .global sb_tp +sb_tp: + sb $5,1($1) + sb $10,1($9) + sb $5,3($3) + sb $5,1($3) + sb $10,4($4) + .text + .global sh_tp +sh_tp: + sh $3,1($0) + sh $tp,1($9) + sh $9,4($10) + sh $15,3($14) + sh $14,4($9) + .text + .global sw_tp +sw_tp: + sw $6,2($13) + sw $6,1($15) + sw $2,2($3) + sw $6,2($12) + sw $3,1($11) + .text + .global lb_tp +lb_tp: + lb $tp,4($11) + lb $13,4($8) + lb $5,4($5) + lb $sp,2($gp) + lb $3,2($3) + .text + .global lh_tp +lh_tp: + lh $7,2($fp) + lh $4,3($8) + lh $14,1($sp) + lh $9,1($0) + lh $13,2($0) + .text + .global lw_tp +lw_tp: + lw $8,4($15) + lw $11,4($9) + lw $gp,1($2) + lw $9,2($14) + lw $8,1($12) + .text + .global lbu_tp +lbu_tp: + lbu $12,1($9) + lbu $11,1($9) + lbu $14,3($8) + lbu $0,2($sp) + lbu $13,1($11) + .text + .global lhu_tp +lhu_tp: + lhu $14,2($10) + lhu $11,1($8) + lhu $1,1($0) + lhu $7,2($15) + lhu $3,2($tp) + .text + .global sb16 +sb16: + sb $7,-1($11) + sb $tp,1($gp) + sb $3,1($gp) + sb $14,2($6) + sb $14,1($7) + .text + .global sh16 +sh16: + sh $12,-1($4) + sh $sp,1($1) + sh $2,-2($12) + sh $9,2($11) + sh $9,-2($12) + .text + .global sw16 +sw16: + sw $11,-1($gp) + sw $4,4($15) + sw $2,-2($3) + sw $6,-1($2) + sw $fp,-2($tp) + .text + .global lb16 +lb16: + lb $10,-2($2) + lb $3,-2($11) + lb $12,1($5) + lb $5,1($5) + lb $11,2($13) + .text + .global lh16 +lh16: + lh $sp,-1($11) + lh $tp,-2($11) + lh $2,1($10) + lh $8,-1($7) + lh $14,-1($11) + .text + .global lw16 +lw16: + lw $0,-1($5) + lw $12,-2($7) + lw $1,-2($3) + lw $1,2($7) + lw $4,1($fp) + .text + .global lbu16 +lbu16: + lbu $12,-1($4) + lbu $14,1($11) + lbu $1,-1($13) + lbu $9,-1($tp) + lbu $8,1($15) + .text + .global lhu16 +lhu16: + lhu $tp,-1($15) + lhu $gp,2($fp) + lhu $15,-1($12) + lhu $3,-1($0) + lhu $3,-2($12) + .text + .global sw24 +sw24: + sw $11,(4) + sw $sp,(4) + sw $7,(8) + sw $10,(16) + sw $8,(160) + .text + .global lw24 +lw24: + lw $4,(4) + lw $sp,(4) + lw $4,(16) + lw $fp,(0) + lw $tp,(8) + .text + .global extb +extb: + extb $13 + extb $tp + extb $6 + extb $14 + extb $10 + .text + .global exth +exth: + exth $15 + exth $2 + exth $5 + exth $10 + exth $4 + .text + .global extub +extub: + extub $2 + extub $tp + extub $3 + extub $9 + extub $gp + .text + .global extuh +extuh: + extuh $8 + extuh $8 + extuh $4 + extuh $0 + extuh $0 + .text + .global ssarb +ssarb: + ssarb 2($fp) + ssarb 2($13) + ssarb 1($13) + ssarb 2($5) + ssarb 0($9) + .text + .global mov +mov: + mov $2,$3 + mov $3,$11 + mov $15,$10 + mov $15,$0 + mov $3,$tp + .text + .global movi8 +movi8: + mov $11,-1 + mov $6,2 + mov $sp,-1 + mov $sp,1 + mov $gp,-1 + .text + .global movi16 +movi16: + mov $15,0 + mov $0,2 + mov $8,-1 + mov $12,1 + mov $7,-1 + .text + .global movu24 +movu24: + movu $2,1 + movu $10,4 + movu $9,0 + movu $4,3 + movu $14,1 + .text + .global movu16 +movu16: + movu $sp,1 + movu $6,3 + movu $0,3 + movu $gp,3 + movu $10,2 + .text + .global movh +movh: + movh $8,2 + movh $13,1 + movh $gp,2 + movh $12,0 + movh $11,2 + .text + .global add3 +add3: + add3 $6,$11,$3 + add3 $14,$13,$5 + add3 $3,$11,$7 + add3 $13,$14,$13 + add3 $0,$14,$8 + .text + .global add +add: + add $12,2 + add $12,-1 + add $4,1 + add $6,1 + add $6,2 + .text + .global add3i +add3i: + add3 $11,$sp,4 + add3 $4,$sp,1 + add3 $0,$sp,0 + add3 $13,$sp,3 + add3 $11,$sp,0 + .text + .global advck3 +advck3: + advck3 $0,$gp,$10 + advck3 $0,$tp,$0 + advck3 $0,$gp,$13 + advck3 $0,$7,$fp + advck3 $0,$1,$2 + .text + .global sub +sub: + sub $8,$14 + sub $1,$9 + sub $13,$7 + sub $15,$3 + sub $2,$7 + .text + .global sbvck3 +sbvck3: + sbvck3 $0,$3,$gp + sbvck3 $0,$3,$7 + sbvck3 $0,$10,$10 + sbvck3 $0,$4,$tp + sbvck3 $0,$10,$15 + .text + .global neg +neg: + neg $14,$7 + neg $1,$7 + neg $2,$11 + neg $13,$fp + neg $14,$13 + .text + .global slt3 +slt3: + slt3 $0,$14,$8 + slt3 $0,$4,$13 + slt3 $0,$10,$14 + slt3 $0,$14,$5 + slt3 $0,$3,$12 + .text + .global sltu3 +sltu3: + sltu3 $0,$2,$8 + sltu3 $0,$gp,$11 + sltu3 $0,$2,$tp + sltu3 $0,$9,$fp + sltu3 $0,$6,$9 + .text + .global slt3i +slt3i: + slt3 $0,$6,2 + slt3 $0,$11,1 + slt3 $0,$15,0 + slt3 $0,$3,0 + slt3 $0,$tp,0 + .text + .global sltu3i +sltu3i: + sltu3 $0,$14,4 + sltu3 $0,$tp,3 + sltu3 $0,$3,1 + sltu3 $0,$12,0 + sltu3 $0,$1,3 + .text + .global sl1ad3 +sl1ad3: + sl1ad3 $0,$fp,$gp + sl1ad3 $0,$4,$2 + sl1ad3 $0,$sp,$12 + sl1ad3 $0,$9,$1 + sl1ad3 $0,$fp,$2 + .text + .global sl2ad3 +sl2ad3: + sl2ad3 $0,$8,$13 + sl2ad3 $0,$2,$3 + sl2ad3 $0,$8,$9 + sl2ad3 $0,$7,$12 + sl2ad3 $0,$4,$12 + .text + .global add3x +add3x: + add3 $tp,$11,1 + add3 $tp,$4,-1 + add3 $2,$13,1 + add3 $3,$gp,1 + add3 $10,$15,2 + .text + .global slt3x +slt3x: + slt3 $fp,$1,-1 + slt3 $0,$3,-2 + slt3 $9,$15,-1 + slt3 $3,$fp,2 + slt3 $tp,$14,0 + .text + .global sltu3x +sltu3x: + sltu3 $15,$11,2 + sltu3 $6,$0,1 + sltu3 $9,$11,3 + sltu3 $0,$4,0 + sltu3 $13,$gp,4 + .text + .global or +or: + or $sp,$gp + or $fp,$3 + or $0,$sp + or $tp,$0 + or $8,$6 + .text + .global and +and: + and $15,$sp + and $6,$14 + and $4,$2 + and $5,$fp + and $7,$14 + .text + .global xor +xor: + xor $1,$12 + xor $12,$tp + xor $10,$8 + xor $sp,$11 + xor $12,$8 + .text + .global nor +nor: + nor $9,$5 + nor $8,$2 + nor $15,$9 + nor $5,$sp + nor $sp,$14 + .text + .global or3 +or3: + or3 $13,$sp,2 + or3 $sp,$tp,3 + or3 $0,$10,4 + or3 $9,$15,3 + or3 $9,$sp,0 + .text + .global and3 +and3: + and3 $5,$8,1 + and3 $11,$gp,3 + and3 $6,$0,0 + and3 $sp,$sp,0 + and3 $1,$10,3 + .text + .global xor3 +xor3: + xor3 $0,$0,2 + xor3 $15,$6,0 + xor3 $13,$5,0 + xor3 $15,$7,0 + xor3 $15,$sp,2 + .text + .global sra +sra: + sra $4,$1 + sra $fp,$15 + sra $1,$1 + sra $0,$5 + sra $9,$1 + .text + .global srl +srl: + srl $2,$11 + srl $15,$7 + srl $1,$7 + srl $3,$13 + srl $14,$1 + .text + .global sll +sll: + sll $11,$0 + sll $tp,$fp + sll $8,$9 + sll $13,$15 + sll $sp,$sp + .text + .global srai +srai: + sra $1,2 + sra $15,3 + sra $sp,3 + sra $6,4 + sra $sp,3 + .text + .global srli +srli: + srl $10,0 + srl $9,3 + srl $6,4 + srl $10,2 + srl $8,3 + .text + .global slli +slli: + sll $0,0 + sll $4,0 + sll $13,2 + sll $11,2 + sll $6,0 + .text + .global sll3 +sll3: + sll3 $0,$tp,4 + sll3 $0,$14,0 + sll3 $0,$8,2 + sll3 $0,$3,2 + sll3 $0,$fp,0 + .text + .global fsft +fsft: + fsft $gp,$10 + fsft $gp,$9 + fsft $15,$13 + fsft $11,$3 + fsft $5,$3 + .text + .global bra +bra: + bra 2 + bra -2 + bra 2 + bra 0 + bra 2 + .text + .global beqz +beqz: + beqz $1,-2 + beqz $sp,2 + beqz $4,4 + beqz $4,0 + beqz $9,-2 + .text + .global bnez +bnez: + bnez $8,2 + bnez $13,2 + bnez $gp,0 + bnez $6,2 + bnez $8,-4 + .text + .global beqi +beqi: + beqi $tp,3,0 + beqi $0,4,-2 + beqi $sp,4,-2 + beqi $13,2,0 + beqi $4,2,-8 + .text + .global bnei +bnei: + bnei $8,1,0 + bnei $5,1,2 + bnei $5,0,8 + bnei $9,4,-2 + bnei $0,4,-8 + .text + .global blti +blti: + blti $7,3,0 + blti $1,1,0 + blti $8,2,2 + blti $11,2,2 + blti $15,3,-2 + .text + .global bgei +bgei: + bgei $4,3,-8 + bgei $7,0,2 + bgei $13,1,0 + bgei $5,2,-2 + bgei $12,4,-8 + .text + .global beq +beq: + beq $7,$2,-2 + beq $1,$3,-8 + beq $2,$0,2 + beq $sp,$fp,2 + beq $3,$0,0 + .text + .global bne +bne: + bne $6,$3,0 + bne $sp,$3,-8 + bne $8,$0,2 + bne $gp,$sp,8 + bne $sp,$4,2 + .text + .global bsr12 +bsr12: + bsr 2 + bsr -8 + bsr -16 + bsr -2 + bsr -8 + .text + .global bsr24 +bsr24: + bsr 4 + bsr -2 + bsr -4 + bsr 0 + bsr 2 + .text + .global jmp +jmp: + jmp $2 + jmp $tp + jmp $5 + jmp $sp + jmp $fp + .text + .global jmp24 +jmp24: + jmp 4 + jmp 2 + jmp 0 + jmp 2 + jmp 4 + .text + .global jsr +jsr: + jsr $15 + jsr $13 + jsr $13 + jsr $6 + jsr $6 + .text + .global ret +ret: + ret + .text + .global repeat +repeat: + repeat $4,2 + repeat $fp,4 + repeat $0,8 + repeat $6,2 + repeat $4,2 + .text + .global erepeat +erepeat: + erepeat 2 + erepeat 0 + erepeat 2 + erepeat -2 + erepeat 0 + .text + .global stc +stc: + stc $13,$mb1 + stc $tp,$ccfg + stc $11,$dbg + stc $10,$ccfg + stc $9,$epc + .text + .global ldc +ldc: + ldc $tp,$lo + ldc $8,$npc + ldc $9,$mb0 + ldc $15,$sar + ldc $9,$ccfg + .text + .global di +di: + di + .text + .global ei +ei: + ei + .text + .global reti +reti: + reti + .text + .global halt +halt: + halt + .text + .global swi +swi: + swi 2 + swi 0 + swi 2 + swi 3 + swi 1 + .text + .global break +break: + break + .text + .global sycnm +syncm: + syncm + .text + .global stcb +stcb: + stcb $5,4 + stcb $5,1 + stcb $gp,0 + stcb $15,4 + stcb $11,2 + .text + .global ldcb +ldcb: + ldcb $2,3 + ldcb $2,4 + ldcb $9,1 + ldcb $10,4 + ldcb $1,4 + .text + .global bsetm +bsetm: + bsetm ($10),0 + bsetm ($sp),0 + bsetm ($1),2 + bsetm ($sp),4 + bsetm ($8),4 + .text + .global bclrm +bclrm: + bclrm ($5),0 + bclrm ($5),2 + bclrm ($8),0 + bclrm ($9),2 + bclrm ($5),3 + .text + .global bnotm +bnotm: + bnotm ($14),4 + bnotm ($11),4 + bnotm ($10),0 + bnotm ($tp),4 + bnotm ($fp),0 + .text + .global btstm +btstm: + btstm $0,($14),0 + btstm $0,($14),1 + btstm $0,($11),0 + btstm $0,($14),3 + btstm $0,($fp),2 + .text + .global tas +tas: + tas $7,($tp) + tas $7,($12) + tas $3,($fp) + tas $2,($5) + tas $6,($10) + .text + .global cache +cache: + cache 1,($13) + cache 3,($12) + cache 3,($9) + cache 4,($2) + cache 4,($7) + .text + .global mul +mul: + mul $8,$14 + mul $2,$9 + mul $14,$15 + mul $9,$7 + mul $7,$11 + .text + .global mulu +mulu: + mulu $2,$5 + mulu $6,$gp + mulu $gp,$sp + mulu $11,$14 + mulu $3,$9 + .text + .global mulr +mulr: + mulr $12,$6 + mulr $13,$8 + mulr $7,$10 + mulr $gp,$1 + mulr $0,$15 + .text + .global mulru +mulru: + mulru $4,$2 + mulru $14,$1 + mulru $15,$4 + mulru $10,$6 + mulru $0,$gp + .text + .global madd +madd: + madd $4,$11 + madd $15,$14 + madd $14,$sp + madd $4,$tp + madd $1,$gp + .text + .global maddu +maddu: + maddu $0,$1 + maddu $7,$6 + maddu $9,$5 + maddu $gp,$15 + maddu $7,$13 + .text + .global maddr +maddr: + maddr $6,$fp + maddr $9,$14 + maddr $8,$gp + maddr $3,$2 + maddr $1,$11 + .text + .global maddru +maddru: + maddru $10,$3 + maddru $15,$12 + maddru $8,$fp + maddru $14,$3 + maddru $fp,$15 + .text + .global div +div: + div $9,$3 + div $4,$14 + div $2,$12 + div $fp,$tp + div $tp,$6 + .text + .global divu +divu: + divu $9,$5 + divu $8,$13 + divu $0,$14 + divu $9,$5 + divu $0,$5 + .text + .global dret +dret: + dret + .text + .global dbreak +dbreak: + dbreak + .text + .global ldz +ldz: + ldz $gp,$4 + ldz $10,$11 + ldz $9,$9 + ldz $15,$tp + ldz $gp,$3 + .text + .global abs +abs: + abs $sp,$9 + abs $5,$4 + abs $tp,$13 + abs $0,$3 + abs $3,$14 + .text + .global ave +ave: + ave $11,$10 + ave $fp,$10 + ave $14,$2 + ave $10,$12 + ave $15,$8 + .text + .global min +min: + min $8,$3 + min $7,$0 + min $2,$2 + min $5,$6 + min $11,$5 + .text + .global max +max: + max $11,$sp + max $gp,$0 + max $12,$sp + max $gp,$2 + max $14,$sp + .text + .global minu +minu: + minu $11,$8 + minu $7,$5 + minu $fp,$14 + minu $11,$4 + minu $2,$sp + .text + .global maxu +maxu: + maxu $3,$3 + maxu $13,$0 + maxu $4,$fp + maxu $gp,$2 + maxu $12,$fp + .text + .global clip +clip: + clip $10,1 + clip $15,4 + clip $4,3 + clip $15,3 + clip $1,0 + .text + .global clipu +clipu: + clipu $10,4 + clipu $13,1 + clipu $5,4 + clipu $14,0 + clipu $5,1 + .text + .global sadd +sadd: + sadd $5,$0 + sadd $15,$3 + sadd $0,$10 + sadd $sp,$12 + sadd $4,$2 + .text + .global ssub +ssub: + ssub $1,$10 + ssub $4,$7 + ssub $fp,$3 + ssub $7,$gp + ssub $13,$4 + .text + .global saddu +saddu: + saddu $9,$14 + saddu $0,$10 + saddu $7,$12 + saddu $5,$15 + saddu $13,$3 + .text + .global ssubu +ssubu: + ssubu $15,$gp + ssubu $0,$15 + ssubu $3,$10 + ssubu $sp,$13 + ssubu $2,$9 + .text + .global swcp +swcp: + swcp $c3,($13) + swcp $c15,($13) + swcp $c13,($0) + swcp $c12,($12) + swcp $c9,($gp) + .text + .global lwcp +lwcp: + lwcp $c7,($3) + lwcp $c6,($3) + lwcp $c0,($2) + lwcp $c8,($fp) + lwcp $c11,($13) + .text + .global smcp +smcp: + smcp $c14,($9) + smcp $c2,($fp) + smcp $c14,($15) + smcp $c10,($8) + smcp $c2,($8) + .text + .global lmcp +lmcp: + lmcp $c11,($1) + lmcp $c8,($8) + lmcp $c11,($13) + lmcp $c8,($0) + lmcp $c8,($14) + .text + .global swcpi +swcpi: + swcpi $c7,($0+) + swcpi $c6,($gp+) + swcpi $c12,($8+) + swcpi $c14,($15+) + swcpi $c6,($0+) + .text + .global lwcpi +lwcpi: + lwcpi $c8,($2+) + lwcpi $c9,($0+) + lwcpi $c3,($14+) + lwcpi $c13,($5+) + lwcpi $c11,($gp+) + .text + .global smcpi +smcpi: + smcpi $c8,($2+) + smcpi $c11,($9+) + smcpi $c4,($3+) + smcpi $c14,($2+) + smcpi $c9,($3+) + .text + .global lmcpi +lmcpi: + lmcpi $c6,($14+) + lmcpi $c9,($5+) + lmcpi $c10,($6+) + lmcpi $c1,($6+) + lmcpi $c2,($8+) + .text + .global swcp16 +swcp16: + swcp $c0,-1($2) + swcp $c5,1($10) + swcp $c8,2($12) + swcp $c14,-1($1) + swcp $c12,2($3) + .text + .global lwcp16 +lwcp16: + lwcp $c8,-1($5) + lwcp $c12,1($15) + lwcp $c1,2($0) + lwcp $c4,1($13) + lwcp $c6,2($11) + .text + .global smcp16 +smcp16: + smcp $c9,-1($10) + smcp $c14,1($gp) + smcp $c3,2($sp) + smcp $c15,-2($8) + smcp $c13,1($13) + .text + .global lmcp16 +lmcp16: + lmcp $c0,1($15) + lmcp $c15,1($fp) + lmcp $c2,-1($8) + lmcp $c14,1($fp) + lmcp $c1,-1($10) + .text + .global sbcpa +sbcpa: + sbcpa $c14,($sp+),2 + sbcpa $c2,($4+),-2 + sbcpa $c8,($1+),0 + sbcpa $c11,($3+),0 + sbcpa $c9,($14+),-2 + .text + .global lbcpa +lbcpa: + lbcpa $c7,($2+),-2 + lbcpa $c12,($sp+),2 + lbcpa $c5,($4+),-2 + lbcpa $c7,($4+),-2 + lbcpa $c8,($15+),0 + .text + .global shcpa +shcpa: + shcpa $c0,($14+),0 + shcpa $c12,($sp+),16 + shcpa $c1,($4+),4 + shcpa $c5,($4+),-32 + shcpa $c1,($15+),0 + .text + .global lhcpa +lhcpa: + lhcpa $c4,($4+),0 + lhcpa $c6,($5+),48 + lhcpa $c3,($6+),-52 + lhcpa $c8,($6+),-24 + lhcpa $c0,($9+),0 + .text + .global swcpa +swcpa: + swcpa $c1,($9+),16 + swcpa $c7,($sp+),32 + swcpa $c3,($12+),48 + swcpa $c10,($9+),8 + swcpa $c14,($8+),4 + .text + .global lwcpa +lwcpa: + lwcpa $c6,($gp+),-8 + lwcpa $c4,($7+),4 + lwcpa $c11,($gp+),-16 + lwcpa $c10,($sp+),-32 + lwcpa $c2,($2+),8 + .text + .global smcpa +smcpa: + smcpa $c13,($15+),-8 + smcpa $c6,($7+),-8 + smcpa $c5,($3+),16 + smcpa $c13,($15+),16 + smcpa $c3,($12+),48 + .text + .global lmcpa +lmcpa: + lmcpa $c9,($4+),0 + lmcpa $c3,($sp+),-16 + lmcpa $c15,($13+),8 + lmcpa $c8,($8+),-8 + lmcpa $c10,($9+),0 + .text + .global sbcpm0 +sbcpm0: + sbcpm0 $c10,($13+),8 + sbcpm0 $c13,($5+),-8 + sbcpm0 $c4,($5+),-8 + sbcpm0 $c10,($tp+),16 + sbcpm0 $c4,($5+),-24 + .text + .global lbcpm0 +lbcpm0: + lbcpm0 $c0,($4+),0 + lbcpm0 $c9,($7+),-8 + lbcpm0 $c12,($fp+),24 + lbcpm0 $c8,($12+),16 + lbcpm0 $c7,($fp+),16 + .text + .global shcpm0 +shcpm0: + shcpm0 $c2,($13+),2 + shcpm0 $c7,($15+),-2 + shcpm0 $c8,($2+),2 + shcpm0 $c13,($5+),0 + shcpm0 $c3,($14+),8 + .text + .global lhcpm0 +lhcpm0: + lhcpm0 $c7,($4+),8 + lhcpm0 $c3,($3+),-2 + lhcpm0 $c3,($1+),0 + lhcpm0 $c2,($gp+),0 + lhcpm0 $c12,($6+),2 + .text + .global swcpm0 +swcpm0: + swcpm0 $c8,($fp+),32 + swcpm0 $c9,($sp+),0 + swcpm0 $c9,($2+),-16 + swcpm0 $c0,($14+),48 + swcpm0 $c15,($1+),8 + .text + .global lwcpm0 +lwcpm0: + lwcpm0 $c14,($10+),-4 + lwcpm0 $c11,($sp+),-4 + lwcpm0 $c5,($7+),-8 + lwcpm0 $c2,($12+),32 + lwcpm0 $c2,($gp+),16 + .text + .global smcpm0 +smcpm0: + smcpm0 $c1,($12+),8 + smcpm0 $c8,($4+),-16 + smcpm0 $c10,($11+),0 + smcpm0 $c1,($3+),-16 + smcpm0 $c11,($sp+),-8 + .text + .global lmcpm0 +lmcpm0: + lmcpm0 $c14,($10+),0 + lmcpm0 $c6,($15+),-16 + lmcpm0 $c13,($1+),8 + lmcpm0 $c10,($tp+),-24 + lmcpm0 $c7,($14+),-24 + .text + .global sbcpm1 +sbcpm1: + sbcpm1 $c9,($fp+),0 + sbcpm1 $c7,($12+),-24 + sbcpm1 $c15,($5+),-24 + sbcpm1 $c5,($tp+),16 + sbcpm1 $c6,($1+),-128 + .text + .global lbcpm1 +lbcpm1: + lbcpm1 $c6,($gp+),2 + lbcpm1 $c7,($tp+),-2 + lbcpm1 $c4,($13+),1 + lbcpm1 $c12,($2+),-2 + lbcpm1 $c11,($7+),1 + .text + .global shcpm1 +shcpm1: + shcpm1 $c4,($fp+),24 + shcpm1 $c11,($6+),-16 + shcpm1 $c7,($8+),8 + shcpm1 $c5,($12+),16 + shcpm1 $c0,($8+),-32 + .text + .global lhcpm1 +lhcpm1: + lhcpm1 $c11,($0+),0 + lhcpm1 $c7,($tp+),-2 + lhcpm1 $c10,($8+),8 + lhcpm1 $c3,($tp+),0 + lhcpm1 $c9,($6+),2 + .text + .global swcpm1 +swcpm1: + swcpm1 $c9,($8+),24 + swcpm1 $c9,($14+),0 + swcpm1 $c9,($fp+),16 + swcpm1 $c14,($1+),0 + swcpm1 $c2,($sp+),8 + .text + .global lwcpm1 +lwcpm1: + lwcpm1 $c8,($fp+),0 + lwcpm1 $c3,($14+),-16 + lwcpm1 $c7,($6+),-8 + lwcpm1 $c14,($fp+),-24 + lwcpm1 $c3,($fp+),24 + .text + .global smcpm1 +smcpm1: + smcpm1 $c10,($4+),0 + smcpm1 $c6,($sp+),-16 + smcpm1 $c13,($7+),-24 + smcpm1 $c3,($gp+),-8 + smcpm1 $c0,($2+),8 + .text + .global lmcpm1 +lmcpm1: + lmcpm1 $c12,($1+),0 + lmcpm1 $c0,($6+),8 + lmcpm1 $c6,($2+),-8 + lmcpm1 $c12,($gp+),-16 + lmcpm1 $c14,($15+),48 +/* + .text + .global cmov1 +cmov1: + cmov $c11,$10 + cmov $c14,$3 + cmov $c3,$15 + cmov $c6,$5 + cmov $c6,$10 + .text + .global cmov2 +cmov2: + cmov $11,$c2 + cmov $10,$c2 + cmov $tp,$c10 + cmov $12,$c9 + cmov $15,$c3 + .text + .global cmovc1 +cmovc1: + cmovc $ccr9,$sp + cmovc $ccr12,$fp + cmovc $ccr1,$4 + cmovc $ccr11,$sp + cmovc $ccr14,$7 + .text + .global cmovc2 +cmovc2: + cmovc $fp,$ccr6 + cmovc $fp,$ccr6 + cmovc $7,$ccr8 + cmovc $sp,$ccr12 + cmovc $sp,$ccr5 + .text + .global cmovh1 +cmovh1: + cmovh $c8,$1 + cmovh $c12,$sp + cmovh $c11,$5 + cmovh $c4,$4 + cmovh $c3,$gp + .text + .global cmovh2 +cmovh2: + cmovh $4,$c7 + cmovh $gp,$c8 + cmovh $6,$c10 + cmovh $2,$c8 + cmovh $10,$c4 +*/ + .text + .global bcpeq +bcpeq: + bcpeq 4,0 + bcpeq 0,-2 + bcpeq 4,-2 + bcpeq 1,2 + bcpeq 2,2 + .text + .global bcpne +bcpne: + bcpne 2,0 + bcpne 4,0 + bcpne 1,0 + bcpne 4,0 + bcpne 1,2 + .text + .global bcpat +bcpat: + bcpat 1,-2 + bcpat 0,2 + bcpat 0,-2 + bcpat 2,0 + bcpat 1,-2 + .text + .global bcpaf +bcpaf: + bcpaf 4,0 + bcpaf 3,0 + bcpaf 4,0 + bcpaf 1,2 + bcpaf 4,2 + .text + .global synccp +synccp: + synccp + .text + .global jsrv +jsrv: + jsrv $11 + jsrv $5 + jsrv $10 + jsrv $12 + jsrv $10 + .text + .global bsrv +bsrv: + bsrv -2 + bsrv -2 + bsrv -2 + bsrv 2 + bsrv 0 + .text + .global case106341 +case106341: + stc $10,7 + ldc $0, (4 + 4) +case106821: + /* Actual 16 bit form */ + sb $0,($0) + sh $0,($0) + sw $0,($0) + lb $0,($0) + lh $0,($0) + lw $0,($0) + lbu $0,($0) + lhu $0,($0) + /* Should use 16 bit form */ + sb $0,0($0) + sb $0,%lo(0)($0) + sb $0,%hi(0)($0) + sb $0,%uhi(0)($0) + sb $0,%sdaoff(0)($0) + sb $0,%tpoff(0)($0) + sh $0,0($0) + sh $0,%lo(0)($0) + sh $0,%hi(0)($0) + sh $0,%uhi(0)($0) + sh $0,%sdaoff(0)($0) + sh $0,%tpoff(0)($0) + sw $0,0($0) + sw $0,%lo(0)($0) + sw $0,%hi(0)($0) + sw $0,%uhi(0)($0) + sw $0,%sdaoff(0)($0) + sw $0,%tpoff(0)($0) + lb $0,0($0) + lb $0,%lo(0)($0) + lb $0,%hi(0)($0) + lb $0,%uhi(0)($0) + lb $0,%sdaoff(0)($0) + lb $0,%tpoff(0)($0) + lh $0,0($0) + lh $0,%lo(0)($0) + lh $0,%hi(0)($0) + lh $0,%uhi(0)($0) + lh $0,%sdaoff(0)($0) + lh $0,%tpoff(0)($0) + lw $0,0($0) + lw $0,%lo(0)($0) + lw $0,%hi(0)($0) + lw $0,%uhi(0)($0) + lw $0,%sdaoff(0)($0) + lw $0,%tpoff(0)($0) + lbu $0,0($0) + lbu $0,%lo(0)($0) + lbu $0,%hi(0)($0) + lbu $0,%uhi(0)($0) + lbu $0,%sdaoff(0)($0) + lbu $0,%tpoff(0)($0) + lhu $0,0($0) + lhu $0,%lo(0)($0) + lhu $0,%hi(0)($0) + lhu $0,%uhi(0)($0) + lhu $0,%sdaoff(0)($0) + lhu $0,%tpoff(0)($0) + /* Should use 32 bit form */ + sb $0,1($0) + sb $0,%lo(1)($0) + sb $0,%hi(1)($0) + sb $0,%uhi(1)($0) + sb $0,%sdaoff(1)($0) + sb $0,%tpoff(1)($0) + sh $0,1($0) + sh $0,%lo(1)($0) + sh $0,%hi(1)($0) + sh $0,%uhi(1)($0) + sh $0,%sdaoff(1)($0) + sh $0,%tpoff(1)($0) + sw $0,1($0) + sw $0,%lo(1)($0) + sw $0,%hi(1)($0) + sw $0,%uhi(1)($0) + sw $0,%sdaoff(1)($0) + sw $0,%tpoff(1)($0) + lb $0,1($0) + lb $0,%lo(1)($0) + lb $0,%hi(1)($0) + lb $0,%uhi(1)($0) + lb $0,%sdaoff(1)($0) + lb $0,%tpoff(1)($0) + lh $0,1($0) + lh $0,%lo(1)($0) + lh $0,%hi(1)($0) + lh $0,%uhi(1)($0) + lh $0,%sdaoff(1)($0) + lh $0,%tpoff(1)($0) + lw $0,1($0) + lw $0,%lo(1)($0) + lw $0,%hi(1)($0) + lw $0,%uhi(1)($0) + lw $0,%sdaoff(1)($0) + lw $0,%tpoff(1)($0) + lbu $0,1($0) + lbu $0,%lo(1)($0) + lbu $0,%hi(1)($0) + lbu $0,%uhi(1)($0) + lbu $0,%sdaoff(1)($0) + lbu $0,%tpoff(1)($0) + lhu $0,1($0) + lhu $0,%lo(1)($0) + lhu $0,%hi(1)($0) + lhu $0,%uhi(1)($0) + lhu $0,%sdaoff(1)($0) + lhu $0,%tpoff(1)($0) + /* Should use 32 bit form */ + sb $0,case106821($0) + sb $0,%lo(case106821)($0) + sb $0,%hi(case106821)($0) + sb $0,%uhi(case106821)($0) + sh $0,case106821($0) + sh $0,%lo(case106821)($0) + sh $0,%hi(case106821)($0) + sh $0,%uhi(case106821)($0) + sw $0,case106821($0) + sw $0,%lo(case106821)($0) + sw $0,%hi(case106821)($0) + sw $0,%uhi(case106821)($0) + lb $0,case106821($0) + lb $0,%lo(case106821)($0) + lb $0,%hi(case106821)($0) + lb $0,%uhi(case106821)($0) + lh $0,case106821($0) + lh $0,%lo(case106821)($0) + lh $0,%hi(case106821)($0) + lh $0,%uhi(case106821)($0) + lw $0,case106821($0) + lw $0,%lo(case106821)($0) + lw $0,%hi(case106821)($0) + lw $0,%uhi(case106821)($0) + lbu $0,case106821($0) + lbu $0,%lo(case106821)($0) + lbu $0,%hi(case106821)($0) + lbu $0,%uhi(case106821)($0) + lhu $0,case106821($0) + lhu $0,%lo(case106821)($0) + lhu $0,%hi(case106821)($0) + lhu $0,%uhi(case106821)($0) diff --git a/gas/testsuite/gas/mep/branch1.d b/gas/testsuite/gas/mep/branch1.d new file mode 100644 index 000000000000..271b9184a548 --- /dev/null +++ b/gas/testsuite/gas/mep/branch1.d @@ -0,0 +1,14 @@ +#objdump: -dzr + +.*: *file format elf32-mep + +Disassembly of section \.text: + +.* <.*>: + .*: 00 00 * nop + .*: e4 51 00 04 * beq \$4,\$5,.* <foo> + .*: 00 00 * nop + .*: 00 00 * nop + +.* <foo>: + .*: 00 00 * nop diff --git a/gas/testsuite/gas/mep/branch1.s b/gas/testsuite/gas/mep/branch1.s new file mode 100644 index 000000000000..7c69985d7e50 --- /dev/null +++ b/gas/testsuite/gas/mep/branch1.s @@ -0,0 +1,7 @@ + .globl foo + nop + beq $4,$5,foo + nop + nop +foo: + nop diff --git a/gas/testsuite/gas/mep/complex-relocs.exp b/gas/testsuite/gas/mep/complex-relocs.exp new file mode 100644 index 000000000000..ed8a72a413bf --- /dev/null +++ b/gas/testsuite/gas/mep/complex-relocs.exp @@ -0,0 +1,42 @@ +# complex relocations testsuite + +proc ld_test { objects ldflags dest test } { + set ld_output [target_link $objects $dest $ldflags] + if [string match "" $ld_output] then { pass $test } else { fail $test } +} + +proc ld_test_error { objects ldflags dest test } { + set ld_output [target_link $objects $dest $ldflags] + if [string match "" $ld_output] then { fail $test } else { pass $test } +} + +proc objdump_test { exec flags dest test } { + set objdump [find_binutils_prog objdump] + verbose -log "$objdump $flags $exec > $dest" + catch "exec $objdump $flags $exec > $dest" objdump_output + if [string match "" $objdump_output] then { pass $test } else { fail $test } +} + +proc regexp_test { file1 file2 test } { + if [regexp_diff $file1 $file2] then { fail $test } else { pass $test } +} + + +global srcdir subdir +if [istarget mep*-*-*] { + + # test that complex relocs between files work, generally + gas_test relocs-junk1.s {-mconfig=fmax -o relocs-junk1.o} {} {assembling relocs-junk1} + gas_test relocs-syms.s {-mconfig=fmax -o relocs-syms.o} {} {assembling relocs-syms} + gas_test relocs-junk2.s {-mconfig=fmax -o relocs-junk2.o} {} {assembling relocs-junk2} + gas_test relocs-refs.s {-mconfig=fmax -o relocs-refs.o} {} {assembling relocs-refs} + ld_test {relocs-junk1.o relocs-syms.o relocs-junk2.o relocs-refs.o} {--defsym __stack=0x1ffff0 --defsym __sbss_end=0x1000 -e 1233} {relocs.x} {linking relocs.x} + objdump_test {relocs.x} {-dzs} {relocs.dump} {disassembling relocs.x} + regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly for relocs.x} + + foreach test {3} { + # perform specific negative boundary tests + gas_test "relocs-bad$test.s" [list -mconfig=fmax -o "relocs-bad$test.o"] {} [list assembling "relocs-bad$test"] + ld_test_error "relocs-bad$test.o" {-e 1233} "relocs-bad$test.x" [list linking "relocs-bad$test"] + } +} diff --git a/gas/testsuite/gas/mep/dj1.d b/gas/testsuite/gas/mep/dj1.d new file mode 100644 index 000000000000..c314d724ce68 --- /dev/null +++ b/gas/testsuite/gas/mep/dj1.d @@ -0,0 +1,1393 @@ +#as: +#objdump: -dr +#name: dj1 + +dump.o: file format elf32-mep + +Disassembly of section .text: + +00000000 <.text>: + 0: 00 00 nop + 2: 01 00 mov \$1,\$0 + 4: 02 00 mov \$2,\$0 + 6: 03 00 mov \$3,\$0 + 8: 04 00 mov \$4,\$0 + a: 05 00 mov \$5,\$0 + c: 06 00 mov \$6,\$0 + e: 07 00 mov \$7,\$0 + 10: 08 00 mov \$8,\$0 + 12: 09 00 mov \$9,\$0 + 14: 0a 00 mov \$10,\$0 + 16: 0b 00 mov \$11,\$0 + 18: 0c 00 mov \$12,\$0 + 1a: 0d 00 mov \$tp,\$0 + 1c: 0e 00 mov \$gp,\$0 + 1e: 0f 00 mov \$sp,\$0 + 20: 08 00 mov \$8,\$0 + 22: 0d 00 mov \$tp,\$0 + 24: 0e 00 mov \$gp,\$0 + 26: 0f 00 mov \$sp,\$0 + 28: 00 08 sb \$0,\(\$0\) + 2a: 00 09 sh \$0,\(\$0\) + 2c: 00 0a sw \$0,\(\$0\) + 2e: 00 0c lb \$0,\(\$0\) + 30: 00 0d lh \$0,\(\$0\) + 32: 00 0e lw \$0,\(\$0\) + 34: 00 0b lbu \$0,\(\$0\) + 36: 00 0f lhu \$0,\(\$0\) + 38: 0f 08 sb \$sp,\(\$0\) + 3a: 0f 09 sh \$sp,\(\$0\) + 3c: 0f 0a sw \$sp,\(\$0\) + 3e: 0f 0c lb \$sp,\(\$0\) + 40: 0f 0d lh \$sp,\(\$0\) + 42: 0f 0e lw \$sp,\(\$0\) + 44: 0f 0b lbu \$sp,\(\$0\) + 46: 0f 0f lhu \$sp,\(\$0\) + 48: 00 f8 sb \$0,\(\$sp\) + 4a: 00 f9 sh \$0,\(\$sp\) + 4c: 00 fa sw \$0,\(\$sp\) + 4e: 00 fc lb \$0,\(\$sp\) + 50: 00 fd lh \$0,\(\$sp\) + 52: 00 fe lw \$0,\(\$sp\) + 54: 00 fb lbu \$0,\(\$sp\) + 56: 00 ff lhu \$0,\(\$sp\) + 58: 0f f8 sb \$sp,\(\$sp\) + 5a: 0f f9 sh \$sp,\(\$sp\) + 5c: 0f fa sw \$sp,\(\$sp\) + 5e: 0f fc lb \$sp,\(\$sp\) + 60: 0f fd lh \$sp,\(\$sp\) + 62: 0f fe lw \$sp,\(\$sp\) + 64: 0f fb lbu \$sp,\(\$sp\) + 66: 0f ff lhu \$sp,\(\$sp\) + 68: 00 fa sw \$0,\(\$sp\) + 6a: 00 fe lw \$0,\(\$sp\) + 6c: 0f fa sw \$sp,\(\$sp\) + 6e: 0f fe lw \$sp,\(\$sp\) + 70: 40 7e sw \$0,0x7c\(\$sp\) + 72: 40 7f lw \$0,0x7c\(\$sp\) + 74: 4f 7e sw \$sp,0x7c\(\$sp\) + 76: 4f 7f lw \$sp,0x7c\(\$sp\) + 78: 00 fa sw \$0,\(\$sp\) + 7a: 00 fe lw \$0,\(\$sp\) + 7c: 0f fa sw \$sp,\(\$sp\) + 7e: 0f fe lw \$sp,\(\$sp\) + 80: 40 7e sw \$0,0x7c\(\$sp\) + 82: 40 7f lw \$0,0x7c\(\$sp\) + 84: 4f 7e sw \$sp,0x7c\(\$sp\) + 86: 4f 7f lw \$sp,0x7c\(\$sp\) + 88: 00 d8 sb \$0,\(\$tp\) + 8a: 00 dc lb \$0,\(\$tp\) + 8c: 00 db lbu \$0,\(\$tp\) + 8e: 07 d8 sb \$7,\(\$tp\) + 90: 07 dc lb \$7,\(\$tp\) + 92: 07 db lbu \$7,\(\$tp\) + 94: 80 7f sb \$0,0x7f\(\$tp\) + 96: 88 7f lb \$0,0x7f\(\$tp\) + 98: 48 ff lbu \$0,0x7f\(\$tp\) + 9a: 87 7f sb \$7,0x7f\(\$tp\) + 9c: 8f 7f lb \$7,0x7f\(\$tp\) + 9e: 4f ff lbu \$7,0x7f\(\$tp\) + a0: 80 00 sb \$0,0x0\(\$tp\) + a0: R_MEP_TPREL7 symbol + a2: 88 00 lb \$0,0x0\(\$tp\) + a2: R_MEP_TPREL7 symbol + a4: 48 80 lbu \$0,0x0\(\$tp\) + a4: R_MEP_TPREL7 symbol + a6: 87 00 sb \$7,0x0\(\$tp\) + a6: R_MEP_TPREL7 symbol + a8: 8f 00 lb \$7,0x0\(\$tp\) + a8: R_MEP_TPREL7 symbol + aa: 4f 80 lbu \$7,0x0\(\$tp\) + aa: R_MEP_TPREL7 symbol + ac: 00 d8 sb \$0,\(\$tp\) + ae: 00 dc lb \$0,\(\$tp\) + b0: 00 db lbu \$0,\(\$tp\) + b2: 07 d8 sb \$7,\(\$tp\) + b4: 07 dc lb \$7,\(\$tp\) + b6: 07 db lbu \$7,\(\$tp\) + b8: 80 7f sb \$0,0x7f\(\$tp\) + ba: 88 7f lb \$0,0x7f\(\$tp\) + bc: 48 ff lbu \$0,0x7f\(\$tp\) + be: 87 7f sb \$7,0x7f\(\$tp\) + c0: 8f 7f lb \$7,0x7f\(\$tp\) + c2: 4f ff lbu \$7,0x7f\(\$tp\) + c4: 80 00 sb \$0,0x0\(\$tp\) + c4: R_MEP_TPREL7 symbol + c6: 88 00 lb \$0,0x0\(\$tp\) + c6: R_MEP_TPREL7 symbol + c8: 48 80 lbu \$0,0x0\(\$tp\) + c8: R_MEP_TPREL7 symbol + ca: 87 00 sb \$7,0x0\(\$tp\) + ca: R_MEP_TPREL7 symbol + cc: 8f 00 lb \$7,0x0\(\$tp\) + cc: R_MEP_TPREL7 symbol + ce: 4f 80 lbu \$7,0x0\(\$tp\) + ce: R_MEP_TPREL7 symbol + d0: 00 d9 sh \$0,\(\$tp\) + d2: 00 dd lh \$0,\(\$tp\) + d4: 00 df lhu \$0,\(\$tp\) + d6: 07 d9 sh \$7,\(\$tp\) + d8: 07 dd lh \$7,\(\$tp\) + da: 07 df lhu \$7,\(\$tp\) + dc: 80 fe sh \$0,0x7e\(\$tp\) + de: 88 fe lh \$0,0x7e\(\$tp\) + e0: 88 ff lhu \$0,0x7e\(\$tp\) + e2: 87 fe sh \$7,0x7e\(\$tp\) + e4: 8f fe lh \$7,0x7e\(\$tp\) + e6: 8f ff lhu \$7,0x7e\(\$tp\) + e8: 80 80 sh \$0,0x0\(\$tp\) + e8: R_MEP_TPREL7A2 symbol + ea: 88 80 lh \$0,0x0\(\$tp\) + ea: R_MEP_TPREL7A2 symbol + ec: 88 81 lhu \$0,0x0\(\$tp\) + ec: R_MEP_TPREL7A2 symbol + ee: 87 80 sh \$7,0x0\(\$tp\) + ee: R_MEP_TPREL7A2 symbol + f0: 8f 80 lh \$7,0x0\(\$tp\) + f0: R_MEP_TPREL7A2 symbol + f2: 8f 81 lhu \$7,0x0\(\$tp\) + f2: R_MEP_TPREL7A2 symbol + f4: 00 d9 sh \$0,\(\$tp\) + f6: 00 dd lh \$0,\(\$tp\) + f8: 00 df lhu \$0,\(\$tp\) + fa: 07 d9 sh \$7,\(\$tp\) + fc: 07 dd lh \$7,\(\$tp\) + fe: 07 df lhu \$7,\(\$tp\) + 100: 80 fe sh \$0,0x7e\(\$tp\) + 102: 88 fe lh \$0,0x7e\(\$tp\) + 104: 88 ff lhu \$0,0x7e\(\$tp\) + 106: 87 fe sh \$7,0x7e\(\$tp\) + 108: 8f fe lh \$7,0x7e\(\$tp\) + 10a: 8f ff lhu \$7,0x7e\(\$tp\) + 10c: 80 80 sh \$0,0x0\(\$tp\) + 10c: R_MEP_TPREL7A2 symbol + 10e: 88 80 lh \$0,0x0\(\$tp\) + 10e: R_MEP_TPREL7A2 symbol + 110: 88 81 lhu \$0,0x0\(\$tp\) + 110: R_MEP_TPREL7A2 symbol + 112: 87 80 sh \$7,0x0\(\$tp\) + 112: R_MEP_TPREL7A2 symbol + 114: 8f 80 lh \$7,0x0\(\$tp\) + 114: R_MEP_TPREL7A2 symbol + 116: 8f 81 lhu \$7,0x0\(\$tp\) + 116: R_MEP_TPREL7A2 symbol + 118: 00 da sw \$0,\(\$tp\) + 11a: 00 de lw \$0,\(\$tp\) + 11c: 07 da sw \$7,\(\$tp\) + 11e: 07 de lw \$7,\(\$tp\) + 120: 40 fe sw \$0,0x7c\(\$tp\) + 122: 40 ff lw \$0,0x7c\(\$tp\) + 124: 47 fe sw \$7,0x7c\(\$tp\) + 126: 47 ff lw \$7,0x7c\(\$tp\) + 128: 40 82 sw \$0,0x0\(\$tp\) + 128: R_MEP_TPREL7A4 symbol + 12a: 40 83 lw \$0,0x0\(\$tp\) + 12a: R_MEP_TPREL7A4 symbol + 12c: 47 82 sw \$7,0x0\(\$tp\) + 12c: R_MEP_TPREL7A4 symbol + 12e: 47 83 lw \$7,0x0\(\$tp\) + 12e: R_MEP_TPREL7A4 symbol + 130: 00 da sw \$0,\(\$tp\) + 132: 00 de lw \$0,\(\$tp\) + 134: 07 da sw \$7,\(\$tp\) + 136: 07 de lw \$7,\(\$tp\) + 138: 40 fe sw \$0,0x7c\(\$tp\) + 13a: 40 ff lw \$0,0x7c\(\$tp\) + 13c: 47 fe sw \$7,0x7c\(\$tp\) + 13e: 47 ff lw \$7,0x7c\(\$tp\) + 140: 40 82 sw \$0,0x0\(\$tp\) + 140: R_MEP_TPREL7A4 symbol + 142: 40 83 lw \$0,0x0\(\$tp\) + 142: R_MEP_TPREL7A4 symbol + 144: 47 82 sw \$7,0x0\(\$tp\) + 144: R_MEP_TPREL7A4 symbol + 146: 47 83 lw \$7,0x0\(\$tp\) + 146: R_MEP_TPREL7A4 symbol + 148: c0 08 80 00 sb \$0,-32768\(\$0\) + 14c: c0 09 80 00 sh \$0,-32768\(\$0\) + 150: c0 0a 80 00 sw \$0,-32768\(\$0\) + 154: c0 0c 80 00 lb \$0,-32768\(\$0\) + 158: c0 0d 80 00 lh \$0,-32768\(\$0\) + 15c: c0 0e 80 00 lw \$0,-32768\(\$0\) + 160: c0 0b 80 00 lbu \$0,-32768\(\$0\) + 164: c0 0f 80 00 lhu \$0,-32768\(\$0\) + 168: cf 08 80 00 sb \$sp,-32768\(\$0\) + 16c: cf 09 80 00 sh \$sp,-32768\(\$0\) + 170: cf 0a 80 00 sw \$sp,-32768\(\$0\) + 174: cf 0c 80 00 lb \$sp,-32768\(\$0\) + 178: cf 0d 80 00 lh \$sp,-32768\(\$0\) + 17c: cf 0e 80 00 lw \$sp,-32768\(\$0\) + 180: cf 0b 80 00 lbu \$sp,-32768\(\$0\) + 184: cf 0f 80 00 lhu \$sp,-32768\(\$0\) + 188: c0 08 7f ff sb \$0,32767\(\$0\) + 18c: c0 09 7f ff sh \$0,32767\(\$0\) + 190: c0 0a 7f ff sw \$0,32767\(\$0\) + 194: c0 0c 7f ff lb \$0,32767\(\$0\) + 198: c0 0d 7f ff lh \$0,32767\(\$0\) + 19c: c0 0e 7f ff lw \$0,32767\(\$0\) + 1a0: c0 0b 7f ff lbu \$0,32767\(\$0\) + 1a4: c0 0f 7f ff lhu \$0,32767\(\$0\) + 1a8: cf 08 7f ff sb \$sp,32767\(\$0\) + 1ac: cf 09 7f ff sh \$sp,32767\(\$0\) + 1b0: cf 0a 7f ff sw \$sp,32767\(\$0\) + 1b4: cf 0c 7f ff lb \$sp,32767\(\$0\) + 1b8: cf 0d 7f ff lh \$sp,32767\(\$0\) + 1bc: cf 0e 7f ff lw \$sp,32767\(\$0\) + 1c0: cf 0b 7f ff lbu \$sp,32767\(\$0\) + 1c4: cf 0f 7f ff lhu \$sp,32767\(\$0\) + 1c8: c0 08 00 00 sb \$0,0\(\$0\) + 1c8: R_MEP_GPREL symbol + 1cc: c0 09 00 00 sh \$0,0\(\$0\) + 1cc: R_MEP_GPREL symbol + 1d0: c0 0a 00 00 sw \$0,0\(\$0\) + 1d0: R_MEP_GPREL symbol + 1d4: c0 0c 00 00 lb \$0,0\(\$0\) + 1d4: R_MEP_GPREL symbol + 1d8: c0 0d 00 00 lh \$0,0\(\$0\) + 1d8: R_MEP_GPREL symbol + 1dc: c0 0e 00 00 lw \$0,0\(\$0\) + 1dc: R_MEP_GPREL symbol + 1e0: c0 0b 00 00 lbu \$0,0\(\$0\) + 1e0: R_MEP_GPREL symbol + 1e4: c0 0f 00 00 lhu \$0,0\(\$0\) + 1e4: R_MEP_GPREL symbol + 1e8: cf 08 00 00 sb \$sp,0\(\$0\) + 1e8: R_MEP_GPREL symbol + 1ec: cf 09 00 00 sh \$sp,0\(\$0\) + 1ec: R_MEP_GPREL symbol + 1f0: cf 0a 00 00 sw \$sp,0\(\$0\) + 1f0: R_MEP_GPREL symbol + 1f4: cf 0c 00 00 lb \$sp,0\(\$0\) + 1f4: R_MEP_GPREL symbol + 1f8: cf 0d 00 00 lh \$sp,0\(\$0\) + 1f8: R_MEP_GPREL symbol + 1fc: cf 0e 00 00 lw \$sp,0\(\$0\) + 1fc: R_MEP_GPREL symbol + 200: cf 0b 00 00 lbu \$sp,0\(\$0\) + 200: R_MEP_GPREL symbol + 204: cf 0f 00 00 lhu \$sp,0\(\$0\) + 204: R_MEP_GPREL symbol + 208: c0 08 80 00 sb \$0,-32768\(\$0\) + 20c: c0 09 80 00 sh \$0,-32768\(\$0\) + 210: c0 0a 80 00 sw \$0,-32768\(\$0\) + 214: c0 0c 80 00 lb \$0,-32768\(\$0\) + 218: c0 0d 80 00 lh \$0,-32768\(\$0\) + 21c: c0 0e 80 00 lw \$0,-32768\(\$0\) + 220: c0 0b 80 00 lbu \$0,-32768\(\$0\) + 224: c0 0f 80 00 lhu \$0,-32768\(\$0\) + 228: cf 08 80 00 sb \$sp,-32768\(\$0\) + 22c: cf 09 80 00 sh \$sp,-32768\(\$0\) + 230: cf 0a 80 00 sw \$sp,-32768\(\$0\) + 234: cf 0c 80 00 lb \$sp,-32768\(\$0\) + 238: cf 0d 80 00 lh \$sp,-32768\(\$0\) + 23c: cf 0e 80 00 lw \$sp,-32768\(\$0\) + 240: cf 0b 80 00 lbu \$sp,-32768\(\$0\) + 244: cf 0f 80 00 lhu \$sp,-32768\(\$0\) + 248: c0 08 7f ff sb \$0,32767\(\$0\) + 24c: c0 09 7f ff sh \$0,32767\(\$0\) + 250: c0 0a 7f ff sw \$0,32767\(\$0\) + 254: c0 0c 7f ff lb \$0,32767\(\$0\) + 258: c0 0d 7f ff lh \$0,32767\(\$0\) + 25c: c0 0e 7f ff lw \$0,32767\(\$0\) + 260: c0 0b 7f ff lbu \$0,32767\(\$0\) + 264: c0 0f 7f ff lhu \$0,32767\(\$0\) + 268: cf 08 7f ff sb \$sp,32767\(\$0\) + 26c: cf 09 7f ff sh \$sp,32767\(\$0\) + 270: cf 0a 7f ff sw \$sp,32767\(\$0\) + 274: cf 0c 7f ff lb \$sp,32767\(\$0\) + 278: cf 0d 7f ff lh \$sp,32767\(\$0\) + 27c: cf 0e 7f ff lw \$sp,32767\(\$0\) + 280: cf 0b 7f ff lbu \$sp,32767\(\$0\) + 284: cf 0f 7f ff lhu \$sp,32767\(\$0\) + 288: c0 08 00 00 sb \$0,0\(\$0\) + 288: R_MEP_TPREL symbol + 28c: c0 09 00 00 sh \$0,0\(\$0\) + 28c: R_MEP_TPREL symbol + 290: c0 0a 00 00 sw \$0,0\(\$0\) + 290: R_MEP_TPREL symbol + 294: c0 0c 00 00 lb \$0,0\(\$0\) + 294: R_MEP_TPREL symbol + 298: c0 0d 00 00 lh \$0,0\(\$0\) + 298: R_MEP_TPREL symbol + 29c: c0 0e 00 00 lw \$0,0\(\$0\) + 29c: R_MEP_TPREL symbol + 2a0: c0 0b 00 00 lbu \$0,0\(\$0\) + 2a0: R_MEP_TPREL symbol + 2a4: c0 0f 00 00 lhu \$0,0\(\$0\) + 2a4: R_MEP_TPREL symbol + 2a8: cf 08 00 00 sb \$sp,0\(\$0\) + 2a8: R_MEP_TPREL symbol + 2ac: cf 09 00 00 sh \$sp,0\(\$0\) + 2ac: R_MEP_TPREL symbol + 2b0: cf 0a 00 00 sw \$sp,0\(\$0\) + 2b0: R_MEP_TPREL symbol + 2b4: cf 0c 00 00 lb \$sp,0\(\$0\) + 2b4: R_MEP_TPREL symbol + 2b8: cf 0d 00 00 lh \$sp,0\(\$0\) + 2b8: R_MEP_TPREL symbol + 2bc: cf 0e 00 00 lw \$sp,0\(\$0\) + 2bc: R_MEP_TPREL symbol + 2c0: cf 0b 00 00 lbu \$sp,0\(\$0\) + 2c0: R_MEP_TPREL symbol + 2c4: cf 0f 00 00 lhu \$sp,0\(\$0\) + 2c4: R_MEP_TPREL symbol + 2c8: c0 f8 80 00 sb \$0,-32768\(\$sp\) + 2cc: c0 f9 80 00 sh \$0,-32768\(\$sp\) + 2d0: c0 fa 80 00 sw \$0,-32768\(\$sp\) + 2d4: c0 fc 80 00 lb \$0,-32768\(\$sp\) + 2d8: c0 fd 80 00 lh \$0,-32768\(\$sp\) + 2dc: c0 fe 80 00 lw \$0,-32768\(\$sp\) + 2e0: c0 fb 80 00 lbu \$0,-32768\(\$sp\) + 2e4: c0 ff 80 00 lhu \$0,-32768\(\$sp\) + 2e8: cf f8 80 00 sb \$sp,-32768\(\$sp\) + 2ec: cf f9 80 00 sh \$sp,-32768\(\$sp\) + 2f0: cf fa 80 00 sw \$sp,-32768\(\$sp\) + 2f4: cf fc 80 00 lb \$sp,-32768\(\$sp\) + 2f8: cf fd 80 00 lh \$sp,-32768\(\$sp\) + 2fc: cf fe 80 00 lw \$sp,-32768\(\$sp\) + 300: cf fb 80 00 lbu \$sp,-32768\(\$sp\) + 304: cf ff 80 00 lhu \$sp,-32768\(\$sp\) + 308: c0 f8 7f ff sb \$0,32767\(\$sp\) + 30c: c0 f9 7f ff sh \$0,32767\(\$sp\) + 310: c0 fa 7f ff sw \$0,32767\(\$sp\) + 314: c0 fc 7f ff lb \$0,32767\(\$sp\) + 318: c0 fd 7f ff lh \$0,32767\(\$sp\) + 31c: c0 fe 7f ff lw \$0,32767\(\$sp\) + 320: c0 fb 7f ff lbu \$0,32767\(\$sp\) + 324: c0 ff 7f ff lhu \$0,32767\(\$sp\) + 328: cf f8 7f ff sb \$sp,32767\(\$sp\) + 32c: cf f9 7f ff sh \$sp,32767\(\$sp\) + 330: cf fa 7f ff sw \$sp,32767\(\$sp\) + 334: cf fc 7f ff lb \$sp,32767\(\$sp\) + 338: cf fd 7f ff lh \$sp,32767\(\$sp\) + 33c: cf fe 7f ff lw \$sp,32767\(\$sp\) + 340: cf fb 7f ff lbu \$sp,32767\(\$sp\) + 344: cf ff 7f ff lhu \$sp,32767\(\$sp\) + 348: c0 f8 00 00 sb \$0,0\(\$sp\) + 348: R_MEP_GPREL symbol + 34c: c0 f9 00 00 sh \$0,0\(\$sp\) + 34c: R_MEP_GPREL symbol + 350: c0 fa 00 00 sw \$0,0\(\$sp\) + 350: R_MEP_GPREL symbol + 354: c0 fc 00 00 lb \$0,0\(\$sp\) + 354: R_MEP_GPREL symbol + 358: c0 fd 00 00 lh \$0,0\(\$sp\) + 358: R_MEP_GPREL symbol + 35c: c0 fe 00 00 lw \$0,0\(\$sp\) + 35c: R_MEP_GPREL symbol + 360: c0 fb 00 00 lbu \$0,0\(\$sp\) + 360: R_MEP_GPREL symbol + 364: c0 ff 00 00 lhu \$0,0\(\$sp\) + 364: R_MEP_GPREL symbol + 368: cf f8 00 00 sb \$sp,0\(\$sp\) + 368: R_MEP_GPREL symbol + 36c: cf f9 00 00 sh \$sp,0\(\$sp\) + 36c: R_MEP_GPREL symbol + 370: cf fa 00 00 sw \$sp,0\(\$sp\) + 370: R_MEP_GPREL symbol + 374: cf fc 00 00 lb \$sp,0\(\$sp\) + 374: R_MEP_GPREL symbol + 378: cf fd 00 00 lh \$sp,0\(\$sp\) + 378: R_MEP_GPREL symbol + 37c: cf fe 00 00 lw \$sp,0\(\$sp\) + 37c: R_MEP_GPREL symbol + 380: cf fb 00 00 lbu \$sp,0\(\$sp\) + 380: R_MEP_GPREL symbol + 384: cf ff 00 00 lhu \$sp,0\(\$sp\) + 384: R_MEP_GPREL symbol + 388: c0 f8 80 00 sb \$0,-32768\(\$sp\) + 38c: c0 f9 80 00 sh \$0,-32768\(\$sp\) + 390: c0 fa 80 00 sw \$0,-32768\(\$sp\) + 394: c0 fc 80 00 lb \$0,-32768\(\$sp\) + 398: c0 fd 80 00 lh \$0,-32768\(\$sp\) + 39c: c0 fe 80 00 lw \$0,-32768\(\$sp\) + 3a0: c0 fb 80 00 lbu \$0,-32768\(\$sp\) + 3a4: c0 ff 80 00 lhu \$0,-32768\(\$sp\) + 3a8: cf f8 80 00 sb \$sp,-32768\(\$sp\) + 3ac: cf f9 80 00 sh \$sp,-32768\(\$sp\) + 3b0: cf fa 80 00 sw \$sp,-32768\(\$sp\) + 3b4: cf fc 80 00 lb \$sp,-32768\(\$sp\) + 3b8: cf fd 80 00 lh \$sp,-32768\(\$sp\) + 3bc: cf fe 80 00 lw \$sp,-32768\(\$sp\) + 3c0: cf fb 80 00 lbu \$sp,-32768\(\$sp\) + 3c4: cf ff 80 00 lhu \$sp,-32768\(\$sp\) + 3c8: c0 f8 7f ff sb \$0,32767\(\$sp\) + 3cc: c0 f9 7f ff sh \$0,32767\(\$sp\) + 3d0: c0 fa 7f ff sw \$0,32767\(\$sp\) + 3d4: c0 fc 7f ff lb \$0,32767\(\$sp\) + 3d8: c0 fd 7f ff lh \$0,32767\(\$sp\) + 3dc: c0 fe 7f ff lw \$0,32767\(\$sp\) + 3e0: c0 fb 7f ff lbu \$0,32767\(\$sp\) + 3e4: c0 ff 7f ff lhu \$0,32767\(\$sp\) + 3e8: cf f8 7f ff sb \$sp,32767\(\$sp\) + 3ec: cf f9 7f ff sh \$sp,32767\(\$sp\) + 3f0: cf fa 7f ff sw \$sp,32767\(\$sp\) + 3f4: cf fc 7f ff lb \$sp,32767\(\$sp\) + 3f8: cf fd 7f ff lh \$sp,32767\(\$sp\) + 3fc: cf fe 7f ff lw \$sp,32767\(\$sp\) + 400: cf fb 7f ff lbu \$sp,32767\(\$sp\) + 404: cf ff 7f ff lhu \$sp,32767\(\$sp\) + 408: c0 f8 00 00 sb \$0,0\(\$sp\) + 408: R_MEP_TPREL symbol + 40c: c0 f9 00 00 sh \$0,0\(\$sp\) + 40c: R_MEP_TPREL symbol + 410: 40 02 sw \$0,0x0\(\$sp\) + 410: R_MEP_TPREL7A4 symbol + 412: c0 fc 00 00 lb \$0,0\(\$sp\) + 412: R_MEP_TPREL symbol + 416: c0 fd 00 00 lh \$0,0\(\$sp\) + 416: R_MEP_TPREL symbol + 41a: 40 03 lw \$0,0x0\(\$sp\) + 41a: R_MEP_TPREL7A4 symbol + 41c: c0 fb 00 00 lbu \$0,0\(\$sp\) + 41c: R_MEP_TPREL symbol + 420: c0 ff 00 00 lhu \$0,0\(\$sp\) + 420: R_MEP_TPREL symbol + 424: cf f8 00 00 sb \$sp,0\(\$sp\) + 424: R_MEP_TPREL symbol + 428: cf f9 00 00 sh \$sp,0\(\$sp\) + 428: R_MEP_TPREL symbol + 42c: 4f 02 sw \$sp,0x0\(\$sp\) + 42c: R_MEP_TPREL7A4 symbol + 42e: cf fc 00 00 lb \$sp,0\(\$sp\) + 42e: R_MEP_TPREL symbol + 432: cf fd 00 00 lh \$sp,0\(\$sp\) + 432: R_MEP_TPREL symbol + 436: 4f 03 lw \$sp,0x0\(\$sp\) + 436: R_MEP_TPREL7A4 symbol + 438: cf fb 00 00 lbu \$sp,0\(\$sp\) + 438: R_MEP_TPREL symbol + 43c: cf ff 00 00 lhu \$sp,0\(\$sp\) + 43c: R_MEP_TPREL symbol + 440: e0 02 00 00 sw \$0,\(0x0\) + 444: e0 03 00 00 lw \$0,\(0x0\) + 448: ef 02 00 00 sw \$sp,\(0x0\) + 44c: ef 03 00 00 lw \$sp,\(0x0\) + 450: e0 fe ff ff sw \$0,\(0xfffffc\) + 454: e0 ff ff ff lw \$0,\(0xfffffc\) + 458: ef fe ff ff sw \$sp,\(0xfffffc\) + 45c: ef ff ff ff lw \$sp,\(0xfffffc\) + 460: e0 02 00 00 sw \$0,\(0x0\) + 460: R_MEP_ADDR24A4 symbol + 464: e0 03 00 00 lw \$0,\(0x0\) + 464: R_MEP_ADDR24A4 symbol + 468: ef 02 00 00 sw \$sp,\(0x0\) + 468: R_MEP_ADDR24A4 symbol + 46c: ef 03 00 00 lw \$sp,\(0x0\) + 46c: R_MEP_ADDR24A4 symbol + 470: 10 0d extb \$0 + 472: 10 8d extub \$0 + 474: 10 2d exth \$0 + 476: 10 ad extuh \$0 + 478: 1f 0d extb \$sp + 47a: 1f 8d extub \$sp + 47c: 1f 2d exth \$sp + 47e: 1f ad extuh \$sp + 480: 10 0c ssarb 0\(\$0\) + 482: 13 0c ssarb 3\(\$0\) + 484: 10 fc ssarb 0\(\$sp\) + 486: 13 fc ssarb 3\(\$sp\) + 488: 00 00 nop + 48a: 0f 00 mov \$sp,\$0 + 48c: 00 f0 mov \$0,\$sp + 48e: 0f f0 mov \$sp,\$sp + 490: c0 01 80 00 mov \$0,-32768 + 494: cf 01 80 00 mov \$sp,-32768 + 498: 50 80 mov \$0,-128 + 49a: 5f 80 mov \$sp,-128 + 49c: 50 00 mov \$0,0 + 49e: 5f 00 mov \$sp,0 + 4a0: 50 7f mov \$0,127 + 4a2: 5f 7f mov \$sp,127 + 4a4: c0 01 7f ff mov \$0,32767 + 4a8: cf 01 7f ff mov \$sp,32767 + 4ac: c0 01 00 00 mov \$0,0 + 4ac: R_MEP_LOW16 symbol + 4b0: c0 01 00 00 mov \$0,0 + 4b0: R_MEP_HI16S symbol + 4b4: c0 01 00 00 mov \$0,0 + 4b4: R_MEP_HI16U symbol + 4b8: c0 01 00 00 mov \$0,0 + 4b8: R_MEP_GPREL symbol + 4bc: c0 01 00 00 mov \$0,0 + 4bc: R_MEP_TPREL symbol + 4c0: d0 00 00 00 movu \$0,0x0 + 4c4: d7 00 00 00 movu \$7,0x0 + 4c8: d0 ff ff ff movu \$0,0xffffff + 4cc: d7 ff ff ff movu \$7,0xffffff + 4d0: c0 11 00 00 movu \$0,0x0 + 4d0: R_MEP_LOW16 symbol + 4d4: c7 11 00 00 movu \$7,0x0 + 4d4: R_MEP_LOW16 symbol + 4d8: d0 00 00 00 movu \$0,0x0 + 4d8: R_MEP_UIMM24 symbol + 4dc: d7 00 00 00 movu \$7,0x0 + 4dc: R_MEP_UIMM24 symbol + 4e0: d0 00 00 00 movu \$0,0x0 + 4e4: c0 21 00 00 movh \$0,0x0 + 4e8: cf 11 00 00 movu \$sp,0x0 + 4ec: cf 21 00 00 movh \$sp,0x0 + 4f0: d0 ff 00 ff movu \$0,0xffff + 4f4: c0 21 ff ff movh \$0,0xffff + 4f8: cf 11 ff ff movu \$sp,0xffff + 4fc: cf 21 ff ff movh \$sp,0xffff + 500: c0 11 00 00 movu \$0,0x0 + 500: R_MEP_LOW16 symbol + 504: c0 21 00 00 movh \$0,0x0 + 504: R_MEP_LOW16 symbol + 508: cf 11 00 00 movu \$sp,0x0 + 508: R_MEP_LOW16 symbol + 50c: cf 21 00 00 movh \$sp,0x0 + 50c: R_MEP_LOW16 symbol + 510: c0 11 00 00 movu \$0,0x0 + 510: R_MEP_HI16S symbol + 514: c0 21 00 00 movh \$0,0x0 + 514: R_MEP_HI16S symbol + 518: cf 11 00 00 movu \$sp,0x0 + 518: R_MEP_HI16S symbol + 51c: cf 21 00 00 movh \$sp,0x0 + 51c: R_MEP_HI16S symbol + 520: c0 11 00 00 movu \$0,0x0 + 520: R_MEP_HI16U symbol + 524: c0 21 00 00 movh \$0,0x0 + 524: R_MEP_HI16U symbol + 528: cf 11 00 00 movu \$sp,0x0 + 528: R_MEP_HI16U symbol + 52c: cf 21 00 00 movh \$sp,0x0 + 52c: R_MEP_HI16U symbol + 530: c0 11 56 78 movu \$0,0x5678 + 534: c0 21 56 78 movh \$0,0x5678 + 538: cf 11 56 78 movu \$sp,0x5678 + 53c: cf 21 56 78 movh \$sp,0x5678 + 540: c0 11 12 34 movu \$0,0x1234 + 544: c0 21 12 34 movh \$0,0x1234 + 548: cf 11 12 34 movu \$sp,0x1234 + 54c: cf 21 12 34 movh \$sp,0x1234 + 550: c0 11 12 34 movu \$0,0x1234 + 554: c0 21 12 34 movh \$0,0x1234 + 558: cf 11 12 34 movu \$sp,0x1234 + 55c: cf 21 12 34 movh \$sp,0x1234 + 560: 90 00 add3 \$0,\$0,\$0 + 562: 90 0f add3 \$sp,\$0,\$0 + 564: 9f 00 add3 \$0,\$sp,\$0 + 566: 9f 0f add3 \$sp,\$sp,\$0 + 568: 90 f0 add3 \$0,\$0,\$sp + 56a: 90 ff add3 \$sp,\$0,\$sp + 56c: 9f f0 add3 \$0,\$sp,\$sp + 56e: 9f ff add3 \$sp,\$sp,\$sp + 570: 60 c0 add \$0,-16 + 572: 6f c0 add \$sp,-16 + 574: 60 00 add \$0,0 + 576: 6f 00 add \$sp,0 + 578: 60 3c add \$0,15 + 57a: 6f 3c add \$sp,15 + 57c: 40 00 add3 \$0,\$sp,0x0 + 57e: 4f 00 add3 \$sp,\$sp,0x0 + 580: 40 7c add3 \$0,\$sp,0x7c + 582: 4f 7c add3 \$sp,\$sp,0x7c + 584: c0 f0 00 01 add3 \$0,\$sp,1 + 588: cf f0 00 01 add3 \$sp,\$sp,1 + 58c: 00 07 advck3 \$0,\$0,\$0 + 58e: 00 05 sbvck3 \$0,\$0,\$0 + 590: 0f 07 advck3 \$0,\$sp,\$0 + 592: 0f 05 sbvck3 \$0,\$sp,\$0 + 594: 00 f7 advck3 \$0,\$0,\$sp + 596: 00 f5 sbvck3 \$0,\$0,\$sp + 598: 0f f7 advck3 \$0,\$sp,\$sp + 59a: 0f f5 sbvck3 \$0,\$sp,\$sp + 59c: 00 04 sub \$0,\$0 + 59e: 00 01 neg \$0,\$0 + 5a0: 0f 04 sub \$sp,\$0 + 5a2: 0f 01 neg \$sp,\$0 + 5a4: 00 f4 sub \$0,\$sp + 5a6: 00 f1 neg \$0,\$sp + 5a8: 0f f4 sub \$sp,\$sp + 5aa: 0f f1 neg \$sp,\$sp + 5ac: 00 02 slt3 \$0,\$0,\$0 + 5ae: 00 03 sltu3 \$0,\$0,\$0 + 5b0: 20 06 sl1ad3 \$0,\$0,\$0 + 5b2: 20 07 sl2ad3 \$0,\$0,\$0 + 5b4: 0f 02 slt3 \$0,\$sp,\$0 + 5b6: 0f 03 sltu3 \$0,\$sp,\$0 + 5b8: 2f 06 sl1ad3 \$0,\$sp,\$0 + 5ba: 2f 07 sl2ad3 \$0,\$sp,\$0 + 5bc: 00 f2 slt3 \$0,\$0,\$sp + 5be: 00 f3 sltu3 \$0,\$0,\$sp + 5c0: 20 f6 sl1ad3 \$0,\$0,\$sp + 5c2: 20 f7 sl2ad3 \$0,\$0,\$sp + 5c4: 0f f2 slt3 \$0,\$sp,\$sp + 5c6: 0f f3 sltu3 \$0,\$sp,\$sp + 5c8: 2f f6 sl1ad3 \$0,\$sp,\$sp + 5ca: 2f f7 sl2ad3 \$0,\$sp,\$sp + 5cc: c0 00 80 00 add3 \$0,\$0,-32768 + 5d0: cf 00 80 00 add3 \$sp,\$0,-32768 + 5d4: c0 f0 80 00 add3 \$0,\$sp,-32768 + 5d8: cf f0 80 00 add3 \$sp,\$sp,-32768 + 5dc: c0 00 7f ff add3 \$0,\$0,32767 + 5e0: cf 00 7f ff add3 \$sp,\$0,32767 + 5e4: c0 f0 7f ff add3 \$0,\$sp,32767 + 5e8: cf f0 7f ff add3 \$sp,\$sp,32767 + 5ec: c0 00 00 00 add3 \$0,\$0,0 + 5ec: R_MEP_LOW16 symbol + 5f0: cf 00 00 00 add3 \$sp,\$0,0 + 5f0: R_MEP_LOW16 symbol + 5f4: c0 f0 00 00 add3 \$0,\$sp,0 + 5f4: R_MEP_LOW16 symbol + 5f8: cf f0 00 00 add3 \$sp,\$sp,0 + 5f8: R_MEP_LOW16 symbol + 5fc: 60 01 slt3 \$0,\$0,0x0 + 5fe: 60 05 sltu3 \$0,\$0,0x0 + 600: 6f 01 slt3 \$0,\$sp,0x0 + 602: 6f 05 sltu3 \$0,\$sp,0x0 + 604: 60 f9 slt3 \$0,\$0,0x1f + 606: 60 fd sltu3 \$0,\$0,0x1f + 608: 6f f9 slt3 \$0,\$sp,0x1f + 60a: 6f fd sltu3 \$0,\$sp,0x1f + 60c: 10 00 or \$0,\$0 + 60e: 10 01 and \$0,\$0 + 610: 10 02 xor \$0,\$0 + 612: 10 03 nor \$0,\$0 + 614: 1f 00 or \$sp,\$0 + 616: 1f 01 and \$sp,\$0 + 618: 1f 02 xor \$sp,\$0 + 61a: 1f 03 nor \$sp,\$0 + 61c: 10 f0 or \$0,\$sp + 61e: 10 f1 and \$0,\$sp + 620: 10 f2 xor \$0,\$sp + 622: 10 f3 nor \$0,\$sp + 624: 1f f0 or \$sp,\$sp + 626: 1f f1 and \$sp,\$sp + 628: 1f f2 xor \$sp,\$sp + 62a: 1f f3 nor \$sp,\$sp + 62c: c0 04 00 00 or3 \$0,\$0,0x0 + 630: c0 05 00 00 and3 \$0,\$0,0x0 + 634: c0 06 00 00 xor3 \$0,\$0,0x0 + 638: cf 04 00 00 or3 \$sp,\$0,0x0 + 63c: cf 05 00 00 and3 \$sp,\$0,0x0 + 640: cf 06 00 00 xor3 \$sp,\$0,0x0 + 644: c0 f4 00 00 or3 \$0,\$sp,0x0 + 648: c0 f5 00 00 and3 \$0,\$sp,0x0 + 64c: c0 f6 00 00 xor3 \$0,\$sp,0x0 + 650: cf f4 00 00 or3 \$sp,\$sp,0x0 + 654: cf f5 00 00 and3 \$sp,\$sp,0x0 + 658: cf f6 00 00 xor3 \$sp,\$sp,0x0 + 65c: c0 04 ff ff or3 \$0,\$0,0xffff + 660: c0 05 ff ff and3 \$0,\$0,0xffff + 664: c0 06 ff ff xor3 \$0,\$0,0xffff + 668: cf 04 ff ff or3 \$sp,\$0,0xffff + 66c: cf 05 ff ff and3 \$sp,\$0,0xffff + 670: cf 06 ff ff xor3 \$sp,\$0,0xffff + 674: c0 f4 ff ff or3 \$0,\$sp,0xffff + 678: c0 f5 ff ff and3 \$0,\$sp,0xffff + 67c: c0 f6 ff ff xor3 \$0,\$sp,0xffff + 680: cf f4 ff ff or3 \$sp,\$sp,0xffff + 684: cf f5 ff ff and3 \$sp,\$sp,0xffff + 688: cf f6 ff ff xor3 \$sp,\$sp,0xffff + 68c: c0 04 00 00 or3 \$0,\$0,0x0 + 68c: R_MEP_LOW16 symbol + 690: c0 05 00 00 and3 \$0,\$0,0x0 + 690: R_MEP_LOW16 symbol + 694: c0 06 00 00 xor3 \$0,\$0,0x0 + 694: R_MEP_LOW16 symbol + 698: cf 04 00 00 or3 \$sp,\$0,0x0 + 698: R_MEP_LOW16 symbol + 69c: cf 05 00 00 and3 \$sp,\$0,0x0 + 69c: R_MEP_LOW16 symbol + 6a0: cf 06 00 00 xor3 \$sp,\$0,0x0 + 6a0: R_MEP_LOW16 symbol + 6a4: c0 f4 00 00 or3 \$0,\$sp,0x0 + 6a4: R_MEP_LOW16 symbol + 6a8: c0 f5 00 00 and3 \$0,\$sp,0x0 + 6a8: R_MEP_LOW16 symbol + 6ac: c0 f6 00 00 xor3 \$0,\$sp,0x0 + 6ac: R_MEP_LOW16 symbol + 6b0: cf f4 00 00 or3 \$sp,\$sp,0x0 + 6b0: R_MEP_LOW16 symbol + 6b4: cf f5 00 00 and3 \$sp,\$sp,0x0 + 6b4: R_MEP_LOW16 symbol + 6b8: cf f6 00 00 xor3 \$sp,\$sp,0x0 + 6b8: R_MEP_LOW16 symbol + 6bc: 20 0d sra \$0,\$0 + 6be: 20 0c srl \$0,\$0 + 6c0: 20 0e sll \$0,\$0 + 6c2: 20 0f fsft \$0,\$0 + 6c4: 2f 0d sra \$sp,\$0 + 6c6: 2f 0c srl \$sp,\$0 + 6c8: 2f 0e sll \$sp,\$0 + 6ca: 2f 0f fsft \$sp,\$0 + 6cc: 20 fd sra \$0,\$sp + 6ce: 20 fc srl \$0,\$sp + 6d0: 20 fe sll \$0,\$sp + 6d2: 20 ff fsft \$0,\$sp + 6d4: 2f fd sra \$sp,\$sp + 6d6: 2f fc srl \$sp,\$sp + 6d8: 2f fe sll \$sp,\$sp + 6da: 2f ff fsft \$sp,\$sp + 6dc: 60 03 sra \$0,0x0 + 6de: 60 02 srl \$0,0x0 + 6e0: 60 06 sll \$0,0x0 + 6e2: 6f 03 sra \$sp,0x0 + 6e4: 6f 02 srl \$sp,0x0 + 6e6: 6f 06 sll \$sp,0x0 + 6e8: 60 fb sra \$0,0x1f + 6ea: 60 fa srl \$0,0x1f + 6ec: 60 fe sll \$0,0x1f + 6ee: 6f fb sra \$sp,0x1f + 6f0: 6f fa srl \$sp,0x1f + 6f2: 6f fe sll \$sp,0x1f + 6f4: 60 07 sll3 \$0,\$0,0x0 + 6f6: 6f 07 sll3 \$0,\$sp,0x0 + 6f8: 60 ff sll3 \$0,\$0,0x1f + 6fa: 6f ff sll3 \$0,\$sp,0x1f + 6fc: b8 02 bra 0xfffffefe + 6fe: e0 01 04 00 beq \$0,\$0,0xefe + 702: b0 00 bra 0x702 + 702: R_MEP_PCREL12A2 symbol + 704: a0 82 beqz \$0,0x686 + 706: a0 83 bnez \$0,0x688 + 708: af 82 beqz \$sp,0x68a + 70a: af 83 bnez \$sp,0x68c + 70c: e0 00 00 40 beqi \$0,0x0,0x78c + 710: e0 04 00 40 bnei \$0,0x0,0x790 + 714: ef 00 00 40 beqi \$sp,0x0,0x794 + 718: ef 04 00 40 bnei \$sp,0x0,0x798 + 71c: a0 00 beqz \$0,0x71c + 71c: R_MEP_PCREL8A2 symbol + 71e: a0 01 bnez \$0,0x71e + 71e: R_MEP_PCREL8A2 symbol + 720: af 00 beqz \$sp,0x720 + 720: R_MEP_PCREL8A2 symbol + 722: af 01 bnez \$sp,0x722 + 722: R_MEP_PCREL8A2 symbol + 724: e0 00 80 02 beqi \$0,0x0,0xffff0728 + 728: e0 04 80 02 bnei \$0,0x0,0xffff072c + 72c: e0 0c 80 02 blti \$0,0x0,0xffff0730 + 730: e0 08 80 02 bgei \$0,0x0,0xffff0734 + 734: ef 00 80 02 beqi \$sp,0x0,0xffff0738 + 738: ef 04 80 02 bnei \$sp,0x0,0xffff073c + 73c: ef 0c 80 02 blti \$sp,0x0,0xffff0740 + 740: ef 08 80 02 bgei \$sp,0x0,0xffff0744 + 744: e0 f0 80 02 beqi \$0,0xf,0xffff0748 + 748: e0 f4 80 02 bnei \$0,0xf,0xffff074c + 74c: e0 fc 80 02 blti \$0,0xf,0xffff0750 + 750: e0 f8 80 02 bgei \$0,0xf,0xffff0754 + 754: ef f0 80 02 beqi \$sp,0xf,0xffff0758 + 758: ef f4 80 02 bnei \$sp,0xf,0xffff075c + 75c: ef fc 80 02 blti \$sp,0xf,0xffff0760 + 760: ef f8 80 02 bgei \$sp,0xf,0xffff0764 + 764: e0 00 3f ff beqi \$0,0x0,0x8762 + 768: e0 04 3f ff bnei \$0,0x0,0x8766 + 76c: e0 0c 3f ff blti \$0,0x0,0x876a + 770: e0 08 3f ff bgei \$0,0x0,0x876e + 774: ef 00 3f ff beqi \$sp,0x0,0x8772 + 778: ef 04 3f ff bnei \$sp,0x0,0x8776 + 77c: ef 0c 3f ff blti \$sp,0x0,0x877a + 780: ef 08 3f ff bgei \$sp,0x0,0x877e + 784: e0 f0 3f ff beqi \$0,0xf,0x8782 + 788: e0 f4 3f ff bnei \$0,0xf,0x8786 + 78c: e0 fc 3f ff blti \$0,0xf,0x878a + 790: e0 f8 3f ff bgei \$0,0xf,0x878e + 794: ef f0 3f ff beqi \$sp,0xf,0x8792 + 798: ef f4 3f ff bnei \$sp,0xf,0x8796 + 79c: ef fc 3f ff blti \$sp,0xf,0x879a + 7a0: ef f8 3f ff bgei \$sp,0xf,0x879e + 7a4: e0 00 00 00 beqi \$0,0x0,0x7a4 + 7a4: R_MEP_PCREL17A2 symbol + 7a8: e0 04 00 00 bnei \$0,0x0,0x7a8 + 7a8: R_MEP_PCREL17A2 symbol + 7ac: e0 0c 00 00 blti \$0,0x0,0x7ac + 7ac: R_MEP_PCREL17A2 symbol + 7b0: e0 08 00 00 bgei \$0,0x0,0x7b0 + 7b0: R_MEP_PCREL17A2 symbol + 7b4: ef 00 00 00 beqi \$sp,0x0,0x7b4 + 7b4: R_MEP_PCREL17A2 symbol + 7b8: ef 04 00 00 bnei \$sp,0x0,0x7b8 + 7b8: R_MEP_PCREL17A2 symbol + 7bc: ef 0c 00 00 blti \$sp,0x0,0x7bc + 7bc: R_MEP_PCREL17A2 symbol + 7c0: ef 08 00 00 bgei \$sp,0x0,0x7c0 + 7c0: R_MEP_PCREL17A2 symbol + 7c4: e0 f0 00 00 beqi \$0,0xf,0x7c4 + 7c4: R_MEP_PCREL17A2 symbol + 7c8: e0 f4 00 00 bnei \$0,0xf,0x7c8 + 7c8: R_MEP_PCREL17A2 symbol + 7cc: e0 fc 00 00 blti \$0,0xf,0x7cc + 7cc: R_MEP_PCREL17A2 symbol + 7d0: e0 f8 00 00 bgei \$0,0xf,0x7d0 + 7d0: R_MEP_PCREL17A2 symbol + 7d4: ef f0 00 00 beqi \$sp,0xf,0x7d4 + 7d4: R_MEP_PCREL17A2 symbol + 7d8: ef f4 00 00 bnei \$sp,0xf,0x7d8 + 7d8: R_MEP_PCREL17A2 symbol + 7dc: ef fc 00 00 blti \$sp,0xf,0x7dc + 7dc: R_MEP_PCREL17A2 symbol + 7e0: ef f8 00 00 bgei \$sp,0xf,0x7e0 + 7e0: R_MEP_PCREL17A2 symbol + 7e4: e0 01 80 02 beq \$0,\$0,0xffff07e8 + 7e8: e0 05 80 02 bne \$0,\$0,0xffff07ec + 7ec: ef 01 80 02 beq \$sp,\$0,0xffff07f0 + 7f0: ef 05 80 02 bne \$sp,\$0,0xffff07f4 + 7f4: e0 f1 80 02 beq \$0,\$sp,0xffff07f8 + 7f8: e0 f5 80 02 bne \$0,\$sp,0xffff07fc + 7fc: ef f1 80 02 beq \$sp,\$sp,0xffff0800 + 800: ef f5 80 02 bne \$sp,\$sp,0xffff0804 + 804: e0 01 3f ff beq \$0,\$0,0x8802 + 808: e0 05 3f ff bne \$0,\$0,0x8806 + 80c: ef 01 3f ff beq \$sp,\$0,0x880a + 810: ef 05 3f ff bne \$sp,\$0,0x880e + 814: e0 f1 3f ff beq \$0,\$sp,0x8812 + 818: e0 f5 3f ff bne \$0,\$sp,0x8816 + 81c: ef f1 3f ff beq \$sp,\$sp,0x881a + 820: ef f5 3f ff bne \$sp,\$sp,0x881e + 824: e0 01 00 00 beq \$0,\$0,0x824 + 824: R_MEP_PCREL17A2 symbol + 828: e0 05 00 00 bne \$0,\$0,0x828 + 828: R_MEP_PCREL17A2 symbol + 82c: ef 01 00 00 beq \$sp,\$0,0x82c + 82c: R_MEP_PCREL17A2 symbol + 830: ef 05 00 00 bne \$sp,\$0,0x830 + 830: R_MEP_PCREL17A2 symbol + 834: e0 f1 00 00 beq \$0,\$sp,0x834 + 834: R_MEP_PCREL17A2 symbol + 838: e0 f5 00 00 bne \$0,\$sp,0x838 + 838: R_MEP_PCREL17A2 symbol + 83c: ef f1 00 00 beq \$sp,\$sp,0x83c + 83c: R_MEP_PCREL17A2 symbol + 840: ef f5 00 00 bne \$sp,\$sp,0x840 + 840: R_MEP_PCREL17A2 symbol + 844: d8 29 80 00 bsr 0xff800848 + 848: b8 03 bsr 0x4a + 84a: d8 09 00 08 bsr 0x104a + 84e: d8 19 80 00 bsr 0xff800850 + 852: d8 09 00 00 bsr 0x852 + 852: R_MEP_PCREL24A2 symbol + 856: 10 0e jmp \$0 + 858: 10 fe jmp \$sp + 85a: d8 08 00 00 jmp 0x0 + 85e: df f8 ff ff jmp 0xfffffe + 862: d8 08 00 00 jmp 0x0 + 862: R_MEP_PCABS24A2 symbol + 866: 10 0f jsr \$0 + 868: 10 ff jsr \$sp + 86a: 70 02 ret + 86c: e0 09 80 02 repeat \$0,0xffff0870 + 870: ef 09 80 02 repeat \$sp,0xffff0874 + 874: e0 09 3f ff repeat \$0,0x8872 + 878: ef 09 3f ff repeat \$sp,0x8876 + 87c: e0 09 00 00 repeat \$0,0x87c + 87c: R_MEP_PCREL17A2 symbol + 880: ef 09 00 00 repeat \$sp,0x880 + 880: R_MEP_PCREL17A2 symbol + 884: e0 19 80 02 erepeat 0xffff0888 + 888: e0 19 3f ff erepeat 0x8886 + 88c: e0 19 00 00 erepeat 0x88c + 88c: R_MEP_PCREL17A2 symbol + 890: 70 08 stc \$0,\$pc + 892: 70 0a ldc \$0,\$pc + 894: 7f 08 stc \$sp,\$pc + 896: 7f 0a ldc \$sp,\$pc + 898: 70 18 stc \$0,\$lp + 89a: 70 1a ldc \$0,\$lp + 89c: 7f 18 stc \$sp,\$lp + 89e: 7f 1a ldc \$sp,\$lp + 8a0: 70 28 stc \$0,\$sar + 8a2: 70 2a ldc \$0,\$sar + 8a4: 7f 28 stc \$sp,\$sar + 8a6: 7f 2a ldc \$sp,\$sar + 8a8: 70 48 stc \$0,\$rpb + 8aa: 70 4a ldc \$0,\$rpb + 8ac: 7f 48 stc \$sp,\$rpb + 8ae: 7f 4a ldc \$sp,\$rpb + 8b0: 70 58 stc \$0,\$rpe + 8b2: 70 5a ldc \$0,\$rpe + 8b4: 7f 58 stc \$sp,\$rpe + 8b6: 7f 5a ldc \$sp,\$rpe + 8b8: 70 68 stc \$0,\$rpc + 8ba: 70 6a ldc \$0,\$rpc + 8bc: 7f 68 stc \$sp,\$rpc + 8be: 7f 6a ldc \$sp,\$rpc + 8c0: 70 78 stc \$0,\$hi + 8c2: 70 7a ldc \$0,\$hi + 8c4: 7f 78 stc \$sp,\$hi + 8c6: 7f 7a ldc \$sp,\$hi + 8c8: 70 88 stc \$0,\$lo + 8ca: 70 8a ldc \$0,\$lo + 8cc: 7f 88 stc \$sp,\$lo + 8ce: 7f 8a ldc \$sp,\$lo + 8d0: 70 c8 stc \$0,\$mb0 + 8d2: 70 ca ldc \$0,\$mb0 + 8d4: 7f c8 stc \$sp,\$mb0 + 8d6: 7f ca ldc \$sp,\$mb0 + 8d8: 70 d8 stc \$0,\$me0 + 8da: 70 da ldc \$0,\$me0 + 8dc: 7f d8 stc \$sp,\$me0 + 8de: 7f da ldc \$sp,\$me0 + 8e0: 70 e8 stc \$0,\$mb1 + 8e2: 70 ea ldc \$0,\$mb1 + 8e4: 7f e8 stc \$sp,\$mb1 + 8e6: 7f ea ldc \$sp,\$mb1 + 8e8: 70 f8 stc \$0,\$me1 + 8ea: 70 fa ldc \$0,\$me1 + 8ec: 7f f8 stc \$sp,\$me1 + 8ee: 7f fa ldc \$sp,\$me1 + 8f0: 70 09 stc \$0,\$psw + 8f2: 70 0b ldc \$0,\$psw + 8f4: 7f 09 stc \$sp,\$psw + 8f6: 7f 0b ldc \$sp,\$psw + 8f8: 70 19 stc \$0,\$id + 8fa: 70 1b ldc \$0,\$id + 8fc: 7f 19 stc \$sp,\$id + 8fe: 7f 1b ldc \$sp,\$id + 900: 70 29 stc \$0,\$tmp + 902: 70 2b ldc \$0,\$tmp + 904: 7f 29 stc \$sp,\$tmp + 906: 7f 2b ldc \$sp,\$tmp + 908: 70 39 stc \$0,\$epc + 90a: 70 3b ldc \$0,\$epc + 90c: 7f 39 stc \$sp,\$epc + 90e: 7f 3b ldc \$sp,\$epc + 910: 70 49 stc \$0,\$exc + 912: 70 4b ldc \$0,\$exc + 914: 7f 49 stc \$sp,\$exc + 916: 7f 4b ldc \$sp,\$exc + 918: 70 59 stc \$0,\$cfg + 91a: 70 5b ldc \$0,\$cfg + 91c: 7f 59 stc \$sp,\$cfg + 91e: 7f 5b ldc \$sp,\$cfg + 920: 70 79 stc \$0,\$npc + 922: 70 7b ldc \$0,\$npc + 924: 7f 79 stc \$sp,\$npc + 926: 7f 7b ldc \$sp,\$npc + 928: 70 89 stc \$0,\$dbg + 92a: 70 8b ldc \$0,\$dbg + 92c: 7f 89 stc \$sp,\$dbg + 92e: 7f 8b ldc \$sp,\$dbg + 930: 70 99 stc \$0,\$depc + 932: 70 9b ldc \$0,\$depc + 934: 7f 99 stc \$sp,\$depc + 936: 7f 9b ldc \$sp,\$depc + 938: 70 a9 stc \$0,\$opt + 93a: 70 ab ldc \$0,\$opt + 93c: 7f a9 stc \$sp,\$opt + 93e: 7f ab ldc \$sp,\$opt + 940: 70 b9 stc \$0,\$rcfg + 942: 70 bb ldc \$0,\$rcfg + 944: 7f b9 stc \$sp,\$rcfg + 946: 7f bb ldc \$sp,\$rcfg + 948: 70 c9 stc \$0,\$ccfg + 94a: 70 cb ldc \$0,\$ccfg + 94c: 7f c9 stc \$sp,\$ccfg + 94e: 7f cb ldc \$sp,\$ccfg + 950: 70 00 di + 952: 70 10 ei + 954: 70 12 reti + 956: 70 22 halt + 958: 70 32 break + 95a: 70 11 syncm + 95c: 70 06 swi 0x0 + 95e: 70 36 swi 0x3 + 960: f0 04 00 00 stcb \$0,0x0 + 964: f0 14 00 00 ldcb \$0,0x0 + 968: ff 04 00 00 stcb \$sp,0x0 + 96c: ff 14 00 00 ldcb \$sp,0x0 + 970: f0 04 ff ff stcb \$0,0xffff + 974: f0 14 ff ff ldcb \$0,0xffff + 978: ff 04 ff ff stcb \$sp,0xffff + 97c: ff 14 ff ff ldcb \$sp,0xffff + 980: f0 04 00 00 stcb \$0,0x0 + 982: R_MEP_16 symbol + 984: f0 14 00 00 ldcb \$0,0x0 + 986: R_MEP_16 symbol + 988: ff 04 00 00 stcb \$sp,0x0 + 98a: R_MEP_16 symbol + 98c: ff 14 00 00 ldcb \$sp,0x0 + 98e: R_MEP_16 symbol + 990: 20 00 bsetm \(\$0\),0x0 + 992: 20 01 bclrm \(\$0\),0x0 + 994: 20 02 bnotm \(\$0\),0x0 + 996: 20 f0 bsetm \(\$sp\),0x0 + 998: 20 f1 bclrm \(\$sp\),0x0 + 99a: 20 f2 bnotm \(\$sp\),0x0 + 99c: 27 00 bsetm \(\$0\),0x7 + 99e: 27 01 bclrm \(\$0\),0x7 + 9a0: 27 02 bnotm \(\$0\),0x7 + 9a2: 27 f0 bsetm \(\$sp\),0x7 + 9a4: 27 f1 bclrm \(\$sp\),0x7 + 9a6: 27 f2 bnotm \(\$sp\),0x7 + 9a8: 20 03 btstm \$0,\(\$0\),0x0 + 9aa: 20 f3 btstm \$0,\(\$sp\),0x0 + 9ac: 27 03 btstm \$0,\(\$0\),0x7 + 9ae: 27 f3 btstm \$0,\(\$sp\),0x7 + 9b0: 20 04 tas \$0,\(\$0\) + 9b2: 2f 04 tas \$sp,\(\$0\) + 9b4: 20 f4 tas \$0,\(\$sp\) + 9b6: 2f f4 tas \$sp,\(\$sp\) + 9b8: 70 04 cache 0x0,\(\$0\) + 9ba: 73 04 cache 0x3,\(\$0\) + 9bc: 70 f4 cache 0x0,\(\$sp\) + 9be: 73 f4 cache 0x3,\(\$sp\) + 9c0: 10 04 mul \$0,\$0 + 9c2: f0 01 30 04 madd \$0,\$0 + 9c6: 10 06 mulr \$0,\$0 + 9c8: f0 01 30 06 maddr \$0,\$0 + 9cc: 10 05 mulu \$0,\$0 + 9ce: f0 01 30 05 maddu \$0,\$0 + 9d2: 10 07 mulru \$0,\$0 + 9d4: f0 01 30 07 maddru \$0,\$0 + 9d8: 1f 04 mul \$sp,\$0 + 9da: ff 01 30 04 madd \$sp,\$0 + 9de: 1f 06 mulr \$sp,\$0 + 9e0: ff 01 30 06 maddr \$sp,\$0 + 9e4: 1f 05 mulu \$sp,\$0 + 9e6: ff 01 30 05 maddu \$sp,\$0 + 9ea: 1f 07 mulru \$sp,\$0 + 9ec: ff 01 30 07 maddru \$sp,\$0 + 9f0: 10 f4 mul \$0,\$sp + 9f2: f0 f1 30 04 madd \$0,\$sp + 9f6: 10 f6 mulr \$0,\$sp + 9f8: f0 f1 30 06 maddr \$0,\$sp + 9fc: 10 f5 mulu \$0,\$sp + 9fe: f0 f1 30 05 maddu \$0,\$sp + a02: 10 f7 mulru \$0,\$sp + a04: f0 f1 30 07 maddru \$0,\$sp + a08: 1f f4 mul \$sp,\$sp + a0a: ff f1 30 04 madd \$sp,\$sp + a0e: 1f f6 mulr \$sp,\$sp + a10: ff f1 30 06 maddr \$sp,\$sp + a14: 1f f5 mulu \$sp,\$sp + a16: ff f1 30 05 maddu \$sp,\$sp + a1a: 1f f7 mulru \$sp,\$sp + a1c: ff f1 30 07 maddru \$sp,\$sp + a20: 10 08 div \$0,\$0 + a22: 10 09 divu \$0,\$0 + a24: 1f 08 div \$sp,\$0 + a26: 1f 09 divu \$sp,\$0 + a28: 10 f8 div \$0,\$sp + a2a: 10 f9 divu \$0,\$sp + a2c: 1f f8 div \$sp,\$sp + a2e: 1f f9 divu \$sp,\$sp + a30: 70 13 dret + a32: 70 33 dbreak + a34: f0 01 00 00 ldz \$0,\$0 + a38: f0 01 00 03 abs \$0,\$0 + a3c: f0 01 00 02 ave \$0,\$0 + a40: ff 01 00 00 ldz \$sp,\$0 + a44: ff 01 00 03 abs \$sp,\$0 + a48: ff 01 00 02 ave \$sp,\$0 + a4c: f0 f1 00 00 ldz \$0,\$sp + a50: f0 f1 00 03 abs \$0,\$sp + a54: f0 f1 00 02 ave \$0,\$sp + a58: ff f1 00 00 ldz \$sp,\$sp + a5c: ff f1 00 03 abs \$sp,\$sp + a60: ff f1 00 02 ave \$sp,\$sp + a64: f0 01 00 04 min \$0,\$0 + a68: f0 01 00 05 max \$0,\$0 + a6c: f0 01 00 06 minu \$0,\$0 + a70: f0 01 00 07 maxu \$0,\$0 + a74: ff 01 00 04 min \$sp,\$0 + a78: ff 01 00 05 max \$sp,\$0 + a7c: ff 01 00 06 minu \$sp,\$0 + a80: ff 01 00 07 maxu \$sp,\$0 + a84: f0 f1 00 04 min \$0,\$sp + a88: f0 f1 00 05 max \$0,\$sp + a8c: f0 f1 00 06 minu \$0,\$sp + a90: f0 f1 00 07 maxu \$0,\$sp + a94: ff f1 00 04 min \$sp,\$sp + a98: ff f1 00 05 max \$sp,\$sp + a9c: ff f1 00 06 minu \$sp,\$sp + aa0: ff f1 00 07 maxu \$sp,\$sp + aa4: f0 01 10 00 clip \$0,0x0 + aa8: f0 01 10 01 clipu \$0,0x0 + aac: ff 01 10 00 clip \$sp,0x0 + ab0: ff 01 10 01 clipu \$sp,0x0 + ab4: f0 01 10 f8 clip \$0,0x1f + ab8: f0 01 10 f9 clipu \$0,0x1f + abc: ff 01 10 f8 clip \$sp,0x1f + ac0: ff 01 10 f9 clipu \$sp,0x1f + ac4: f0 01 00 08 sadd \$0,\$0 + ac8: f0 01 00 0a ssub \$0,\$0 + acc: f0 01 00 09 saddu \$0,\$0 + ad0: f0 01 00 0b ssubu \$0,\$0 + ad4: ff 01 00 08 sadd \$sp,\$0 + ad8: ff 01 00 0a ssub \$sp,\$0 + adc: ff 01 00 09 saddu \$sp,\$0 + ae0: ff 01 00 0b ssubu \$sp,\$0 + ae4: f0 f1 00 08 sadd \$0,\$sp + ae8: f0 f1 00 0a ssub \$0,\$sp + aec: f0 f1 00 09 saddu \$0,\$sp + af0: f0 f1 00 0b ssubu \$0,\$sp + af4: ff f1 00 08 sadd \$sp,\$sp + af8: ff f1 00 0a ssub \$sp,\$sp + afc: ff f1 00 09 saddu \$sp,\$sp + b00: ff f1 00 0b ssubu \$sp,\$sp + b04: 30 08 swcp \$c0,\(\$0\) + b06: 30 09 lwcp \$c0,\(\$0\) + b08: 30 0a smcp \$c0,\(\$0\) + b0a: 30 0b lmcp \$c0,\(\$0\) + b0c: 3f 08 swcp \$c15,\(\$0\) + b0e: 3f 09 lwcp \$c15,\(\$0\) + b10: 3f 0a smcp \$c15,\(\$0\) + b12: 3f 0b lmcp \$c15,\(\$0\) + b14: 30 f8 swcp \$c0,\(\$sp\) + b16: 30 f9 lwcp \$c0,\(\$sp\) + b18: 30 fa smcp \$c0,\(\$sp\) + b1a: 30 fb lmcp \$c0,\(\$sp\) + b1c: 3f f8 swcp \$c15,\(\$sp\) + b1e: 3f f9 lwcp \$c15,\(\$sp\) + b20: 3f fa smcp \$c15,\(\$sp\) + b22: 3f fb lmcp \$c15,\(\$sp\) + b24: 30 00 swcpi \$c0,\(\$0\+\) + b26: 30 01 lwcpi \$c0,\(\$0\+\) + b28: 30 02 smcpi \$c0,\(\$0\+\) + b2a: 30 03 lmcpi \$c0,\(\$0\+\) + b2c: 3f 00 swcpi \$c15,\(\$0\+\) + b2e: 3f 01 lwcpi \$c15,\(\$0\+\) + b30: 3f 02 smcpi \$c15,\(\$0\+\) + b32: 3f 03 lmcpi \$c15,\(\$0\+\) + b34: 30 f0 swcpi \$c0,\(\$sp\+\) + b36: 30 f1 lwcpi \$c0,\(\$sp\+\) + b38: 30 f2 smcpi \$c0,\(\$sp\+\) + b3a: 30 f3 lmcpi \$c0,\(\$sp\+\) + b3c: 3f f0 swcpi \$c15,\(\$sp\+\) + b3e: 3f f1 lwcpi \$c15,\(\$sp\+\) + b40: 3f f2 smcpi \$c15,\(\$sp\+\) + b42: 3f f3 lmcpi \$c15,\(\$sp\+\) + b44: f0 05 00 80 sbcpa \$c0,\(\$0\+\),-128 + b48: f0 05 40 80 lbcpa \$c0,\(\$0\+\),-128 + b4c: f0 05 08 80 sbcpm0 \$c0,\(\$0\+\),-128 + b50: f0 05 48 80 lbcpm0 \$c0,\(\$0\+\),-128 + b54: f0 05 0c 80 sbcpm1 \$c0,\(\$0\+\),-128 + b58: f0 05 4c 80 lbcpm1 \$c0,\(\$0\+\),-128 + b5c: ff 05 00 80 sbcpa \$c15,\(\$0\+\),-128 + b60: ff 05 40 80 lbcpa \$c15,\(\$0\+\),-128 + b64: ff 05 08 80 sbcpm0 \$c15,\(\$0\+\),-128 + b68: ff 05 48 80 lbcpm0 \$c15,\(\$0\+\),-128 + b6c: ff 05 0c 80 sbcpm1 \$c15,\(\$0\+\),-128 + b70: ff 05 4c 80 lbcpm1 \$c15,\(\$0\+\),-128 + b74: f0 f5 00 80 sbcpa \$c0,\(\$sp\+\),-128 + b78: f0 f5 40 80 lbcpa \$c0,\(\$sp\+\),-128 + b7c: f0 f5 08 80 sbcpm0 \$c0,\(\$sp\+\),-128 + b80: f0 f5 48 80 lbcpm0 \$c0,\(\$sp\+\),-128 + b84: f0 f5 0c 80 sbcpm1 \$c0,\(\$sp\+\),-128 + b88: f0 f5 4c 80 lbcpm1 \$c0,\(\$sp\+\),-128 + b8c: ff f5 00 80 sbcpa \$c15,\(\$sp\+\),-128 + b90: ff f5 40 80 lbcpa \$c15,\(\$sp\+\),-128 + b94: ff f5 08 80 sbcpm0 \$c15,\(\$sp\+\),-128 + b98: ff f5 48 80 lbcpm0 \$c15,\(\$sp\+\),-128 + b9c: ff f5 0c 80 sbcpm1 \$c15,\(\$sp\+\),-128 + ba0: ff f5 4c 80 lbcpm1 \$c15,\(\$sp\+\),-128 + ba4: f0 05 00 7f sbcpa \$c0,\(\$0\+\),127 + ba8: f0 05 40 7f lbcpa \$c0,\(\$0\+\),127 + bac: f0 05 08 7f sbcpm0 \$c0,\(\$0\+\),127 + bb0: f0 05 48 7f lbcpm0 \$c0,\(\$0\+\),127 + bb4: f0 05 0c 7f sbcpm1 \$c0,\(\$0\+\),127 + bb8: f0 05 4c 7f lbcpm1 \$c0,\(\$0\+\),127 + bbc: ff 05 00 7f sbcpa \$c15,\(\$0\+\),127 + bc0: ff 05 40 7f lbcpa \$c15,\(\$0\+\),127 + bc4: ff 05 08 7f sbcpm0 \$c15,\(\$0\+\),127 + bc8: ff 05 48 7f lbcpm0 \$c15,\(\$0\+\),127 + bcc: ff 05 0c 7f sbcpm1 \$c15,\(\$0\+\),127 + bd0: ff 05 4c 7f lbcpm1 \$c15,\(\$0\+\),127 + bd4: f0 f5 00 7f sbcpa \$c0,\(\$sp\+\),127 + bd8: f0 f5 40 7f lbcpa \$c0,\(\$sp\+\),127 + bdc: f0 f5 08 7f sbcpm0 \$c0,\(\$sp\+\),127 + be0: f0 f5 48 7f lbcpm0 \$c0,\(\$sp\+\),127 + be4: f0 f5 0c 7f sbcpm1 \$c0,\(\$sp\+\),127 + be8: f0 f5 4c 7f lbcpm1 \$c0,\(\$sp\+\),127 + bec: ff f5 00 7f sbcpa \$c15,\(\$sp\+\),127 + bf0: ff f5 40 7f lbcpa \$c15,\(\$sp\+\),127 + bf4: ff f5 08 7f sbcpm0 \$c15,\(\$sp\+\),127 + bf8: ff f5 48 7f lbcpm0 \$c15,\(\$sp\+\),127 + bfc: ff f5 0c 7f sbcpm1 \$c15,\(\$sp\+\),127 + c00: ff f5 4c 7f lbcpm1 \$c15,\(\$sp\+\),127 + c04: f0 05 10 80 shcpa \$c0,\(\$0\+\),-128 + c08: f0 05 50 80 lhcpa \$c0,\(\$0\+\),-128 + c0c: f0 05 18 80 shcpm0 \$c0,\(\$0\+\),-128 + c10: f0 05 58 80 lhcpm0 \$c0,\(\$0\+\),-128 + c14: f0 05 1c 80 shcpm1 \$c0,\(\$0\+\),-128 + c18: f0 05 5c 80 lhcpm1 \$c0,\(\$0\+\),-128 + c1c: ff 05 10 80 shcpa \$c15,\(\$0\+\),-128 + c20: ff 05 50 80 lhcpa \$c15,\(\$0\+\),-128 + c24: ff 05 18 80 shcpm0 \$c15,\(\$0\+\),-128 + c28: ff 05 58 80 lhcpm0 \$c15,\(\$0\+\),-128 + c2c: ff 05 1c 80 shcpm1 \$c15,\(\$0\+\),-128 + c30: ff 05 5c 80 lhcpm1 \$c15,\(\$0\+\),-128 + c34: f0 f5 10 80 shcpa \$c0,\(\$sp\+\),-128 + c38: f0 f5 50 80 lhcpa \$c0,\(\$sp\+\),-128 + c3c: f0 f5 18 80 shcpm0 \$c0,\(\$sp\+\),-128 + c40: f0 f5 58 80 lhcpm0 \$c0,\(\$sp\+\),-128 + c44: f0 f5 1c 80 shcpm1 \$c0,\(\$sp\+\),-128 + c48: f0 f5 5c 80 lhcpm1 \$c0,\(\$sp\+\),-128 + c4c: ff f5 10 80 shcpa \$c15,\(\$sp\+\),-128 + c50: ff f5 50 80 lhcpa \$c15,\(\$sp\+\),-128 + c54: ff f5 18 80 shcpm0 \$c15,\(\$sp\+\),-128 + c58: ff f5 58 80 lhcpm0 \$c15,\(\$sp\+\),-128 + c5c: ff f5 1c 80 shcpm1 \$c15,\(\$sp\+\),-128 + c60: ff f5 5c 80 lhcpm1 \$c15,\(\$sp\+\),-128 + c64: f0 05 10 7e shcpa \$c0,\(\$0\+\),126 + c68: f0 05 50 7e lhcpa \$c0,\(\$0\+\),126 + c6c: f0 05 18 7e shcpm0 \$c0,\(\$0\+\),126 + c70: f0 05 58 7e lhcpm0 \$c0,\(\$0\+\),126 + c74: f0 05 1c 7e shcpm1 \$c0,\(\$0\+\),126 + c78: f0 05 5c 7e lhcpm1 \$c0,\(\$0\+\),126 + c7c: ff 05 10 7e shcpa \$c15,\(\$0\+\),126 + c80: ff 05 50 7e lhcpa \$c15,\(\$0\+\),126 + c84: ff 05 18 7e shcpm0 \$c15,\(\$0\+\),126 + c88: ff 05 58 7e lhcpm0 \$c15,\(\$0\+\),126 + c8c: ff 05 1c 7e shcpm1 \$c15,\(\$0\+\),126 + c90: ff 05 5c 7e lhcpm1 \$c15,\(\$0\+\),126 + c94: f0 f5 10 7e shcpa \$c0,\(\$sp\+\),126 + c98: f0 f5 50 7e lhcpa \$c0,\(\$sp\+\),126 + c9c: f0 f5 18 7e shcpm0 \$c0,\(\$sp\+\),126 + ca0: f0 f5 58 7e lhcpm0 \$c0,\(\$sp\+\),126 + ca4: f0 f5 1c 7e shcpm1 \$c0,\(\$sp\+\),126 + ca8: f0 f5 5c 7e lhcpm1 \$c0,\(\$sp\+\),126 + cac: ff f5 10 7e shcpa \$c15,\(\$sp\+\),126 + cb0: ff f5 50 7e lhcpa \$c15,\(\$sp\+\),126 + cb4: ff f5 18 7e shcpm0 \$c15,\(\$sp\+\),126 + cb8: ff f5 58 7e lhcpm0 \$c15,\(\$sp\+\),126 + cbc: ff f5 1c 7e shcpm1 \$c15,\(\$sp\+\),126 + cc0: ff f5 5c 7e lhcpm1 \$c15,\(\$sp\+\),126 + cc4: f0 05 20 80 swcpa \$c0,\(\$0\+\),-128 + cc8: f0 05 60 80 lwcpa \$c0,\(\$0\+\),-128 + ccc: f0 05 28 80 swcpm0 \$c0,\(\$0\+\),-128 + cd0: f0 05 68 80 lwcpm0 \$c0,\(\$0\+\),-128 + cd4: f0 05 2c 80 swcpm1 \$c0,\(\$0\+\),-128 + cd8: f0 05 6c 80 lwcpm1 \$c0,\(\$0\+\),-128 + cdc: ff 05 20 80 swcpa \$c15,\(\$0\+\),-128 + ce0: ff 05 60 80 lwcpa \$c15,\(\$0\+\),-128 + ce4: ff 05 28 80 swcpm0 \$c15,\(\$0\+\),-128 + ce8: ff 05 68 80 lwcpm0 \$c15,\(\$0\+\),-128 + cec: ff 05 2c 80 swcpm1 \$c15,\(\$0\+\),-128 + cf0: ff 05 6c 80 lwcpm1 \$c15,\(\$0\+\),-128 + cf4: f0 f5 20 80 swcpa \$c0,\(\$sp\+\),-128 + cf8: f0 f5 60 80 lwcpa \$c0,\(\$sp\+\),-128 + cfc: f0 f5 28 80 swcpm0 \$c0,\(\$sp\+\),-128 + d00: f0 f5 68 80 lwcpm0 \$c0,\(\$sp\+\),-128 + d04: f0 f5 2c 80 swcpm1 \$c0,\(\$sp\+\),-128 + d08: f0 f5 6c 80 lwcpm1 \$c0,\(\$sp\+\),-128 + d0c: ff f5 20 80 swcpa \$c15,\(\$sp\+\),-128 + d10: ff f5 60 80 lwcpa \$c15,\(\$sp\+\),-128 + d14: ff f5 28 80 swcpm0 \$c15,\(\$sp\+\),-128 + d18: ff f5 68 80 lwcpm0 \$c15,\(\$sp\+\),-128 + d1c: ff f5 2c 80 swcpm1 \$c15,\(\$sp\+\),-128 + d20: ff f5 6c 80 lwcpm1 \$c15,\(\$sp\+\),-128 + d24: f0 05 20 7c swcpa \$c0,\(\$0\+\),124 + d28: f0 05 60 7c lwcpa \$c0,\(\$0\+\),124 + d2c: f0 05 28 7c swcpm0 \$c0,\(\$0\+\),124 + d30: f0 05 68 7c lwcpm0 \$c0,\(\$0\+\),124 + d34: f0 05 2c 7c swcpm1 \$c0,\(\$0\+\),124 + d38: f0 05 6c 7c lwcpm1 \$c0,\(\$0\+\),124 + d3c: ff 05 20 7c swcpa \$c15,\(\$0\+\),124 + d40: ff 05 60 7c lwcpa \$c15,\(\$0\+\),124 + d44: ff 05 28 7c swcpm0 \$c15,\(\$0\+\),124 + d48: ff 05 68 7c lwcpm0 \$c15,\(\$0\+\),124 + d4c: ff 05 2c 7c swcpm1 \$c15,\(\$0\+\),124 + d50: ff 05 6c 7c lwcpm1 \$c15,\(\$0\+\),124 + d54: f0 f5 20 7c swcpa \$c0,\(\$sp\+\),124 + d58: f0 f5 60 7c lwcpa \$c0,\(\$sp\+\),124 + d5c: f0 f5 28 7c swcpm0 \$c0,\(\$sp\+\),124 + d60: f0 f5 68 7c lwcpm0 \$c0,\(\$sp\+\),124 + d64: f0 f5 2c 7c swcpm1 \$c0,\(\$sp\+\),124 + d68: f0 f5 6c 7c lwcpm1 \$c0,\(\$sp\+\),124 + d6c: ff f5 20 7c swcpa \$c15,\(\$sp\+\),124 + d70: ff f5 60 7c lwcpa \$c15,\(\$sp\+\),124 + d74: ff f5 28 7c swcpm0 \$c15,\(\$sp\+\),124 + d78: ff f5 68 7c lwcpm0 \$c15,\(\$sp\+\),124 + d7c: ff f5 2c 7c swcpm1 \$c15,\(\$sp\+\),124 + d80: ff f5 6c 7c lwcpm1 \$c15,\(\$sp\+\),124 + d84: f0 05 30 80 smcpa \$c0,\(\$0\+\),-128 + d88: f0 05 70 80 lmcpa \$c0,\(\$0\+\),-128 + d8c: f0 05 38 80 smcpm0 \$c0,\(\$0\+\),-128 + d90: f0 05 78 80 lmcpm0 \$c0,\(\$0\+\),-128 + d94: f0 05 3c 80 smcpm1 \$c0,\(\$0\+\),-128 + d98: f0 05 7c 80 lmcpm1 \$c0,\(\$0\+\),-128 + d9c: ff 05 30 80 smcpa \$c15,\(\$0\+\),-128 + da0: ff 05 70 80 lmcpa \$c15,\(\$0\+\),-128 + da4: ff 05 38 80 smcpm0 \$c15,\(\$0\+\),-128 + da8: ff 05 78 80 lmcpm0 \$c15,\(\$0\+\),-128 + dac: ff 05 3c 80 smcpm1 \$c15,\(\$0\+\),-128 + db0: ff 05 7c 80 lmcpm1 \$c15,\(\$0\+\),-128 + db4: f0 f5 30 80 smcpa \$c0,\(\$sp\+\),-128 + db8: f0 f5 70 80 lmcpa \$c0,\(\$sp\+\),-128 + dbc: f0 f5 38 80 smcpm0 \$c0,\(\$sp\+\),-128 + dc0: f0 f5 78 80 lmcpm0 \$c0,\(\$sp\+\),-128 + dc4: f0 f5 3c 80 smcpm1 \$c0,\(\$sp\+\),-128 + dc8: f0 f5 7c 80 lmcpm1 \$c0,\(\$sp\+\),-128 + dcc: ff f5 30 80 smcpa \$c15,\(\$sp\+\),-128 + dd0: ff f5 70 80 lmcpa \$c15,\(\$sp\+\),-128 + dd4: ff f5 38 80 smcpm0 \$c15,\(\$sp\+\),-128 + dd8: ff f5 78 80 lmcpm0 \$c15,\(\$sp\+\),-128 + ddc: ff f5 3c 80 smcpm1 \$c15,\(\$sp\+\),-128 + de0: ff f5 7c 80 lmcpm1 \$c15,\(\$sp\+\),-128 + de4: f0 05 30 78 smcpa \$c0,\(\$0\+\),120 + de8: f0 05 70 78 lmcpa \$c0,\(\$0\+\),120 + dec: f0 05 38 78 smcpm0 \$c0,\(\$0\+\),120 + df0: f0 05 78 78 lmcpm0 \$c0,\(\$0\+\),120 + df4: f0 05 3c 78 smcpm1 \$c0,\(\$0\+\),120 + df8: f0 05 7c 78 lmcpm1 \$c0,\(\$0\+\),120 + dfc: ff 05 30 78 smcpa \$c15,\(\$0\+\),120 + e00: ff 05 70 78 lmcpa \$c15,\(\$0\+\),120 + e04: ff 05 38 78 smcpm0 \$c15,\(\$0\+\),120 + e08: ff 05 78 78 lmcpm0 \$c15,\(\$0\+\),120 + e0c: ff 05 3c 78 smcpm1 \$c15,\(\$0\+\),120 + e10: ff 05 7c 78 lmcpm1 \$c15,\(\$0\+\),120 + e14: f0 f5 30 78 smcpa \$c0,\(\$sp\+\),120 + e18: f0 f5 70 78 lmcpa \$c0,\(\$sp\+\),120 + e1c: f0 f5 38 78 smcpm0 \$c0,\(\$sp\+\),120 + e20: f0 f5 78 78 lmcpm0 \$c0,\(\$sp\+\),120 + e24: f0 f5 3c 78 smcpm1 \$c0,\(\$sp\+\),120 + e28: f0 f5 7c 78 lmcpm1 \$c0,\(\$sp\+\),120 + e2c: ff f5 30 78 smcpa \$c15,\(\$sp\+\),120 + e30: ff f5 70 78 lmcpa \$c15,\(\$sp\+\),120 + e34: ff f5 38 78 smcpm0 \$c15,\(\$sp\+\),120 + e38: ff f5 78 78 lmcpm0 \$c15,\(\$sp\+\),120 + e3c: ff f5 3c 78 smcpm1 \$c15,\(\$sp\+\),120 + e40: ff f5 7c 78 lmcpm1 \$c15,\(\$sp\+\),120 + e44: d8 04 80 02 bcpeq 0x0,0xffff0e48 + e48: d8 05 80 02 bcpne 0x0,0xffff0e4c + e4c: d8 06 80 02 bcpat 0x0,0xffff0e50 + e50: d8 07 80 02 bcpaf 0x0,0xffff0e54 + e54: d8 f4 80 02 bcpeq 0xf,0xffff0e58 + e58: d8 f5 80 02 bcpne 0xf,0xffff0e5c + e5c: d8 f6 80 02 bcpat 0xf,0xffff0e60 + e60: d8 f7 80 02 bcpaf 0xf,0xffff0e64 + e64: d8 04 3f ff bcpeq 0x0,0x8e62 + e68: d8 05 3f ff bcpne 0x0,0x8e66 + e6c: d8 06 3f ff bcpat 0x0,0x8e6a + e70: d8 07 3f ff bcpaf 0x0,0x8e6e + e74: d8 f4 3f ff bcpeq 0xf,0x8e72 + e78: d8 f5 3f ff bcpne 0xf,0x8e76 + e7c: d8 f6 3f ff bcpat 0xf,0x8e7a + e80: d8 f7 3f ff bcpaf 0xf,0x8e7e + e84: d8 04 00 00 bcpeq 0x0,0xe84 + e84: R_MEP_PCREL17A2 symbol + e88: d8 05 00 00 bcpne 0x0,0xe88 + e88: R_MEP_PCREL17A2 symbol + e8c: d8 06 00 00 bcpat 0x0,0xe8c + e8c: R_MEP_PCREL17A2 symbol + e90: d8 07 00 00 bcpaf 0x0,0xe90 + e90: R_MEP_PCREL17A2 symbol + e94: d8 f4 00 00 bcpeq 0xf,0xe94 + e94: R_MEP_PCREL17A2 symbol + e98: d8 f5 00 00 bcpne 0xf,0xe98 + e98: R_MEP_PCREL17A2 symbol + e9c: d8 f6 00 00 bcpat 0xf,0xe9c + e9c: R_MEP_PCREL17A2 symbol + ea0: d8 f7 00 00 bcpaf 0xf,0xea0 + ea0: R_MEP_PCREL17A2 symbol + ea4: 70 21 synccp + ea6: 18 0f jsrv \$0 + ea8: 18 ff jsrv \$sp + eaa: d8 2b 80 00 bsrv 0xff800eae + eae: df fb 7f ff bsrv 0x800eac + eb2: d8 0b 00 00 bsrv 0xeb2 + eb2: R_MEP_PCREL24A2 symbol + eb6: 00 00 nop + eb6: R_MEP_8 symbol + eb7: R_MEP_16 symbol + eb8: 00 00 nop + eb9: R_MEP_32 symbol + eba: 00 00 nop +.* + diff --git a/gas/testsuite/gas/mep/dj1.le.d b/gas/testsuite/gas/mep/dj1.le.d new file mode 100644 index 000000000000..c860c5be0fa0 --- /dev/null +++ b/gas/testsuite/gas/mep/dj1.le.d @@ -0,0 +1,1393 @@ +#as: -EL +#objdump: -dr +#source: dj1.s +#name: dj1.le + +dump.o: file format elf32-mep-little + +Disassembly of section .text: + +00000000 <.text>: + 0: 00 00 nop + 2: 00 01 mov \$1,\$0 + 4: 00 02 mov \$2,\$0 + 6: 00 03 mov \$3,\$0 + 8: 00 04 mov \$4,\$0 + a: 00 05 mov \$5,\$0 + c: 00 06 mov \$6,\$0 + e: 00 07 mov \$7,\$0 + 10: 00 08 mov \$8,\$0 + 12: 00 09 mov \$9,\$0 + 14: 00 0a mov \$10,\$0 + 16: 00 0b mov \$11,\$0 + 18: 00 0c mov \$12,\$0 + 1a: 00 0d mov \$tp,\$0 + 1c: 00 0e mov \$gp,\$0 + 1e: 00 0f mov \$sp,\$0 + 20: 00 08 mov \$8,\$0 + 22: 00 0d mov \$tp,\$0 + 24: 00 0e mov \$gp,\$0 + 26: 00 0f mov \$sp,\$0 + 28: 08 00 sb \$0,\(\$0\) + 2a: 09 00 sh \$0,\(\$0\) + 2c: 0a 00 sw \$0,\(\$0\) + 2e: 0c 00 lb \$0,\(\$0\) + 30: 0d 00 lh \$0,\(\$0\) + 32: 0e 00 lw \$0,\(\$0\) + 34: 0b 00 lbu \$0,\(\$0\) + 36: 0f 00 lhu \$0,\(\$0\) + 38: 08 0f sb \$sp,\(\$0\) + 3a: 09 0f sh \$sp,\(\$0\) + 3c: 0a 0f sw \$sp,\(\$0\) + 3e: 0c 0f lb \$sp,\(\$0\) + 40: 0d 0f lh \$sp,\(\$0\) + 42: 0e 0f lw \$sp,\(\$0\) + 44: 0b 0f lbu \$sp,\(\$0\) + 46: 0f 0f lhu \$sp,\(\$0\) + 48: f8 00 sb \$0,\(\$sp\) + 4a: f9 00 sh \$0,\(\$sp\) + 4c: fa 00 sw \$0,\(\$sp\) + 4e: fc 00 lb \$0,\(\$sp\) + 50: fd 00 lh \$0,\(\$sp\) + 52: fe 00 lw \$0,\(\$sp\) + 54: fb 00 lbu \$0,\(\$sp\) + 56: ff 00 lhu \$0,\(\$sp\) + 58: f8 0f sb \$sp,\(\$sp\) + 5a: f9 0f sh \$sp,\(\$sp\) + 5c: fa 0f sw \$sp,\(\$sp\) + 5e: fc 0f lb \$sp,\(\$sp\) + 60: fd 0f lh \$sp,\(\$sp\) + 62: fe 0f lw \$sp,\(\$sp\) + 64: fb 0f lbu \$sp,\(\$sp\) + 66: ff 0f lhu \$sp,\(\$sp\) + 68: fa 00 sw \$0,\(\$sp\) + 6a: fe 00 lw \$0,\(\$sp\) + 6c: fa 0f sw \$sp,\(\$sp\) + 6e: fe 0f lw \$sp,\(\$sp\) + 70: 7e 40 sw \$0,0x7c\(\$sp\) + 72: 7f 40 lw \$0,0x7c\(\$sp\) + 74: 7e 4f sw \$sp,0x7c\(\$sp\) + 76: 7f 4f lw \$sp,0x7c\(\$sp\) + 78: fa 00 sw \$0,\(\$sp\) + 7a: fe 00 lw \$0,\(\$sp\) + 7c: fa 0f sw \$sp,\(\$sp\) + 7e: fe 0f lw \$sp,\(\$sp\) + 80: 7e 40 sw \$0,0x7c\(\$sp\) + 82: 7f 40 lw \$0,0x7c\(\$sp\) + 84: 7e 4f sw \$sp,0x7c\(\$sp\) + 86: 7f 4f lw \$sp,0x7c\(\$sp\) + 88: d8 00 sb \$0,\(\$tp\) + 8a: dc 00 lb \$0,\(\$tp\) + 8c: db 00 lbu \$0,\(\$tp\) + 8e: d8 07 sb \$7,\(\$tp\) + 90: dc 07 lb \$7,\(\$tp\) + 92: db 07 lbu \$7,\(\$tp\) + 94: 7f 80 sb \$0,0x7f\(\$tp\) + 96: 7f 88 lb \$0,0x7f\(\$tp\) + 98: ff 48 lbu \$0,0x7f\(\$tp\) + 9a: 7f 87 sb \$7,0x7f\(\$tp\) + 9c: 7f 8f lb \$7,0x7f\(\$tp\) + 9e: ff 4f lbu \$7,0x7f\(\$tp\) + a0: 00 80 sb \$0,0x0\(\$tp\) + a0: R_MEP_TPREL7 symbol + a2: 00 88 lb \$0,0x0\(\$tp\) + a2: R_MEP_TPREL7 symbol + a4: 80 48 lbu \$0,0x0\(\$tp\) + a4: R_MEP_TPREL7 symbol + a6: 00 87 sb \$7,0x0\(\$tp\) + a6: R_MEP_TPREL7 symbol + a8: 00 8f lb \$7,0x0\(\$tp\) + a8: R_MEP_TPREL7 symbol + aa: 80 4f lbu \$7,0x0\(\$tp\) + aa: R_MEP_TPREL7 symbol + ac: d8 00 sb \$0,\(\$tp\) + ae: dc 00 lb \$0,\(\$tp\) + b0: db 00 lbu \$0,\(\$tp\) + b2: d8 07 sb \$7,\(\$tp\) + b4: dc 07 lb \$7,\(\$tp\) + b6: db 07 lbu \$7,\(\$tp\) + b8: 7f 80 sb \$0,0x7f\(\$tp\) + ba: 7f 88 lb \$0,0x7f\(\$tp\) + bc: ff 48 lbu \$0,0x7f\(\$tp\) + be: 7f 87 sb \$7,0x7f\(\$tp\) + c0: 7f 8f lb \$7,0x7f\(\$tp\) + c2: ff 4f lbu \$7,0x7f\(\$tp\) + c4: 00 80 sb \$0,0x0\(\$tp\) + c4: R_MEP_TPREL7 symbol + c6: 00 88 lb \$0,0x0\(\$tp\) + c6: R_MEP_TPREL7 symbol + c8: 80 48 lbu \$0,0x0\(\$tp\) + c8: R_MEP_TPREL7 symbol + ca: 00 87 sb \$7,0x0\(\$tp\) + ca: R_MEP_TPREL7 symbol + cc: 00 8f lb \$7,0x0\(\$tp\) + cc: R_MEP_TPREL7 symbol + ce: 80 4f lbu \$7,0x0\(\$tp\) + ce: R_MEP_TPREL7 symbol + d0: d9 00 sh \$0,\(\$tp\) + d2: dd 00 lh \$0,\(\$tp\) + d4: df 00 lhu \$0,\(\$tp\) + d6: d9 07 sh \$7,\(\$tp\) + d8: dd 07 lh \$7,\(\$tp\) + da: df 07 lhu \$7,\(\$tp\) + dc: fe 80 sh \$0,0x7e\(\$tp\) + de: fe 88 lh \$0,0x7e\(\$tp\) + e0: ff 88 lhu \$0,0x7e\(\$tp\) + e2: fe 87 sh \$7,0x7e\(\$tp\) + e4: fe 8f lh \$7,0x7e\(\$tp\) + e6: ff 8f lhu \$7,0x7e\(\$tp\) + e8: 80 80 sh \$0,0x0\(\$tp\) + e8: R_MEP_TPREL7A2 symbol + ea: 80 88 lh \$0,0x0\(\$tp\) + ea: R_MEP_TPREL7A2 symbol + ec: 81 88 lhu \$0,0x0\(\$tp\) + ec: R_MEP_TPREL7A2 symbol + ee: 80 87 sh \$7,0x0\(\$tp\) + ee: R_MEP_TPREL7A2 symbol + f0: 80 8f lh \$7,0x0\(\$tp\) + f0: R_MEP_TPREL7A2 symbol + f2: 81 8f lhu \$7,0x0\(\$tp\) + f2: R_MEP_TPREL7A2 symbol + f4: d9 00 sh \$0,\(\$tp\) + f6: dd 00 lh \$0,\(\$tp\) + f8: df 00 lhu \$0,\(\$tp\) + fa: d9 07 sh \$7,\(\$tp\) + fc: dd 07 lh \$7,\(\$tp\) + fe: df 07 lhu \$7,\(\$tp\) + 100: fe 80 sh \$0,0x7e\(\$tp\) + 102: fe 88 lh \$0,0x7e\(\$tp\) + 104: ff 88 lhu \$0,0x7e\(\$tp\) + 106: fe 87 sh \$7,0x7e\(\$tp\) + 108: fe 8f lh \$7,0x7e\(\$tp\) + 10a: ff 8f lhu \$7,0x7e\(\$tp\) + 10c: 80 80 sh \$0,0x0\(\$tp\) + 10c: R_MEP_TPREL7A2 symbol + 10e: 80 88 lh \$0,0x0\(\$tp\) + 10e: R_MEP_TPREL7A2 symbol + 110: 81 88 lhu \$0,0x0\(\$tp\) + 110: R_MEP_TPREL7A2 symbol + 112: 80 87 sh \$7,0x0\(\$tp\) + 112: R_MEP_TPREL7A2 symbol + 114: 80 8f lh \$7,0x0\(\$tp\) + 114: R_MEP_TPREL7A2 symbol + 116: 81 8f lhu \$7,0x0\(\$tp\) + 116: R_MEP_TPREL7A2 symbol + 118: da 00 sw \$0,\(\$tp\) + 11a: de 00 lw \$0,\(\$tp\) + 11c: da 07 sw \$7,\(\$tp\) + 11e: de 07 lw \$7,\(\$tp\) + 120: fe 40 sw \$0,0x7c\(\$tp\) + 122: ff 40 lw \$0,0x7c\(\$tp\) + 124: fe 47 sw \$7,0x7c\(\$tp\) + 126: ff 47 lw \$7,0x7c\(\$tp\) + 128: 82 40 sw \$0,0x0\(\$tp\) + 128: R_MEP_TPREL7A4 symbol + 12a: 83 40 lw \$0,0x0\(\$tp\) + 12a: R_MEP_TPREL7A4 symbol + 12c: 82 47 sw \$7,0x0\(\$tp\) + 12c: R_MEP_TPREL7A4 symbol + 12e: 83 47 lw \$7,0x0\(\$tp\) + 12e: R_MEP_TPREL7A4 symbol + 130: da 00 sw \$0,\(\$tp\) + 132: de 00 lw \$0,\(\$tp\) + 134: da 07 sw \$7,\(\$tp\) + 136: de 07 lw \$7,\(\$tp\) + 138: fe 40 sw \$0,0x7c\(\$tp\) + 13a: ff 40 lw \$0,0x7c\(\$tp\) + 13c: fe 47 sw \$7,0x7c\(\$tp\) + 13e: ff 47 lw \$7,0x7c\(\$tp\) + 140: 82 40 sw \$0,0x0\(\$tp\) + 140: R_MEP_TPREL7A4 symbol + 142: 83 40 lw \$0,0x0\(\$tp\) + 142: R_MEP_TPREL7A4 symbol + 144: 82 47 sw \$7,0x0\(\$tp\) + 144: R_MEP_TPREL7A4 symbol + 146: 83 47 lw \$7,0x0\(\$tp\) + 146: R_MEP_TPREL7A4 symbol + 148: 08 c0 00 80 sb \$0,-32768\(\$0\) + 14c: 09 c0 00 80 sh \$0,-32768\(\$0\) + 150: 0a c0 00 80 sw \$0,-32768\(\$0\) + 154: 0c c0 00 80 lb \$0,-32768\(\$0\) + 158: 0d c0 00 80 lh \$0,-32768\(\$0\) + 15c: 0e c0 00 80 lw \$0,-32768\(\$0\) + 160: 0b c0 00 80 lbu \$0,-32768\(\$0\) + 164: 0f c0 00 80 lhu \$0,-32768\(\$0\) + 168: 08 cf 00 80 sb \$sp,-32768\(\$0\) + 16c: 09 cf 00 80 sh \$sp,-32768\(\$0\) + 170: 0a cf 00 80 sw \$sp,-32768\(\$0\) + 174: 0c cf 00 80 lb \$sp,-32768\(\$0\) + 178: 0d cf 00 80 lh \$sp,-32768\(\$0\) + 17c: 0e cf 00 80 lw \$sp,-32768\(\$0\) + 180: 0b cf 00 80 lbu \$sp,-32768\(\$0\) + 184: 0f cf 00 80 lhu \$sp,-32768\(\$0\) + 188: 08 c0 ff 7f sb \$0,32767\(\$0\) + 18c: 09 c0 ff 7f sh \$0,32767\(\$0\) + 190: 0a c0 ff 7f sw \$0,32767\(\$0\) + 194: 0c c0 ff 7f lb \$0,32767\(\$0\) + 198: 0d c0 ff 7f lh \$0,32767\(\$0\) + 19c: 0e c0 ff 7f lw \$0,32767\(\$0\) + 1a0: 0b c0 ff 7f lbu \$0,32767\(\$0\) + 1a4: 0f c0 ff 7f lhu \$0,32767\(\$0\) + 1a8: 08 cf ff 7f sb \$sp,32767\(\$0\) + 1ac: 09 cf ff 7f sh \$sp,32767\(\$0\) + 1b0: 0a cf ff 7f sw \$sp,32767\(\$0\) + 1b4: 0c cf ff 7f lb \$sp,32767\(\$0\) + 1b8: 0d cf ff 7f lh \$sp,32767\(\$0\) + 1bc: 0e cf ff 7f lw \$sp,32767\(\$0\) + 1c0: 0b cf ff 7f lbu \$sp,32767\(\$0\) + 1c4: 0f cf ff 7f lhu \$sp,32767\(\$0\) + 1c8: 08 c0 00 00 sb \$0,0\(\$0\) + 1c8: R_MEP_GPREL symbol + 1cc: 09 c0 00 00 sh \$0,0\(\$0\) + 1cc: R_MEP_GPREL symbol + 1d0: 0a c0 00 00 sw \$0,0\(\$0\) + 1d0: R_MEP_GPREL symbol + 1d4: 0c c0 00 00 lb \$0,0\(\$0\) + 1d4: R_MEP_GPREL symbol + 1d8: 0d c0 00 00 lh \$0,0\(\$0\) + 1d8: R_MEP_GPREL symbol + 1dc: 0e c0 00 00 lw \$0,0\(\$0\) + 1dc: R_MEP_GPREL symbol + 1e0: 0b c0 00 00 lbu \$0,0\(\$0\) + 1e0: R_MEP_GPREL symbol + 1e4: 0f c0 00 00 lhu \$0,0\(\$0\) + 1e4: R_MEP_GPREL symbol + 1e8: 08 cf 00 00 sb \$sp,0\(\$0\) + 1e8: R_MEP_GPREL symbol + 1ec: 09 cf 00 00 sh \$sp,0\(\$0\) + 1ec: R_MEP_GPREL symbol + 1f0: 0a cf 00 00 sw \$sp,0\(\$0\) + 1f0: R_MEP_GPREL symbol + 1f4: 0c cf 00 00 lb \$sp,0\(\$0\) + 1f4: R_MEP_GPREL symbol + 1f8: 0d cf 00 00 lh \$sp,0\(\$0\) + 1f8: R_MEP_GPREL symbol + 1fc: 0e cf 00 00 lw \$sp,0\(\$0\) + 1fc: R_MEP_GPREL symbol + 200: 0b cf 00 00 lbu \$sp,0\(\$0\) + 200: R_MEP_GPREL symbol + 204: 0f cf 00 00 lhu \$sp,0\(\$0\) + 204: R_MEP_GPREL symbol + 208: 08 c0 00 80 sb \$0,-32768\(\$0\) + 20c: 09 c0 00 80 sh \$0,-32768\(\$0\) + 210: 0a c0 00 80 sw \$0,-32768\(\$0\) + 214: 0c c0 00 80 lb \$0,-32768\(\$0\) + 218: 0d c0 00 80 lh \$0,-32768\(\$0\) + 21c: 0e c0 00 80 lw \$0,-32768\(\$0\) + 220: 0b c0 00 80 lbu \$0,-32768\(\$0\) + 224: 0f c0 00 80 lhu \$0,-32768\(\$0\) + 228: 08 cf 00 80 sb \$sp,-32768\(\$0\) + 22c: 09 cf 00 80 sh \$sp,-32768\(\$0\) + 230: 0a cf 00 80 sw \$sp,-32768\(\$0\) + 234: 0c cf 00 80 lb \$sp,-32768\(\$0\) + 238: 0d cf 00 80 lh \$sp,-32768\(\$0\) + 23c: 0e cf 00 80 lw \$sp,-32768\(\$0\) + 240: 0b cf 00 80 lbu \$sp,-32768\(\$0\) + 244: 0f cf 00 80 lhu \$sp,-32768\(\$0\) + 248: 08 c0 ff 7f sb \$0,32767\(\$0\) + 24c: 09 c0 ff 7f sh \$0,32767\(\$0\) + 250: 0a c0 ff 7f sw \$0,32767\(\$0\) + 254: 0c c0 ff 7f lb \$0,32767\(\$0\) + 258: 0d c0 ff 7f lh \$0,32767\(\$0\) + 25c: 0e c0 ff 7f lw \$0,32767\(\$0\) + 260: 0b c0 ff 7f lbu \$0,32767\(\$0\) + 264: 0f c0 ff 7f lhu \$0,32767\(\$0\) + 268: 08 cf ff 7f sb \$sp,32767\(\$0\) + 26c: 09 cf ff 7f sh \$sp,32767\(\$0\) + 270: 0a cf ff 7f sw \$sp,32767\(\$0\) + 274: 0c cf ff 7f lb \$sp,32767\(\$0\) + 278: 0d cf ff 7f lh \$sp,32767\(\$0\) + 27c: 0e cf ff 7f lw \$sp,32767\(\$0\) + 280: 0b cf ff 7f lbu \$sp,32767\(\$0\) + 284: 0f cf ff 7f lhu \$sp,32767\(\$0\) + 288: 08 c0 00 00 sb \$0,0\(\$0\) + 288: R_MEP_TPREL symbol + 28c: 09 c0 00 00 sh \$0,0\(\$0\) + 28c: R_MEP_TPREL symbol + 290: 0a c0 00 00 sw \$0,0\(\$0\) + 290: R_MEP_TPREL symbol + 294: 0c c0 00 00 lb \$0,0\(\$0\) + 294: R_MEP_TPREL symbol + 298: 0d c0 00 00 lh \$0,0\(\$0\) + 298: R_MEP_TPREL symbol + 29c: 0e c0 00 00 lw \$0,0\(\$0\) + 29c: R_MEP_TPREL symbol + 2a0: 0b c0 00 00 lbu \$0,0\(\$0\) + 2a0: R_MEP_TPREL symbol + 2a4: 0f c0 00 00 lhu \$0,0\(\$0\) + 2a4: R_MEP_TPREL symbol + 2a8: 08 cf 00 00 sb \$sp,0\(\$0\) + 2a8: R_MEP_TPREL symbol + 2ac: 09 cf 00 00 sh \$sp,0\(\$0\) + 2ac: R_MEP_TPREL symbol + 2b0: 0a cf 00 00 sw \$sp,0\(\$0\) + 2b0: R_MEP_TPREL symbol + 2b4: 0c cf 00 00 lb \$sp,0\(\$0\) + 2b4: R_MEP_TPREL symbol + 2b8: 0d cf 00 00 lh \$sp,0\(\$0\) + 2b8: R_MEP_TPREL symbol + 2bc: 0e cf 00 00 lw \$sp,0\(\$0\) + 2bc: R_MEP_TPREL symbol + 2c0: 0b cf 00 00 lbu \$sp,0\(\$0\) + 2c0: R_MEP_TPREL symbol + 2c4: 0f cf 00 00 lhu \$sp,0\(\$0\) + 2c4: R_MEP_TPREL symbol + 2c8: f8 c0 00 80 sb \$0,-32768\(\$sp\) + 2cc: f9 c0 00 80 sh \$0,-32768\(\$sp\) + 2d0: fa c0 00 80 sw \$0,-32768\(\$sp\) + 2d4: fc c0 00 80 lb \$0,-32768\(\$sp\) + 2d8: fd c0 00 80 lh \$0,-32768\(\$sp\) + 2dc: fe c0 00 80 lw \$0,-32768\(\$sp\) + 2e0: fb c0 00 80 lbu \$0,-32768\(\$sp\) + 2e4: ff c0 00 80 lhu \$0,-32768\(\$sp\) + 2e8: f8 cf 00 80 sb \$sp,-32768\(\$sp\) + 2ec: f9 cf 00 80 sh \$sp,-32768\(\$sp\) + 2f0: fa cf 00 80 sw \$sp,-32768\(\$sp\) + 2f4: fc cf 00 80 lb \$sp,-32768\(\$sp\) + 2f8: fd cf 00 80 lh \$sp,-32768\(\$sp\) + 2fc: fe cf 00 80 lw \$sp,-32768\(\$sp\) + 300: fb cf 00 80 lbu \$sp,-32768\(\$sp\) + 304: ff cf 00 80 lhu \$sp,-32768\(\$sp\) + 308: f8 c0 ff 7f sb \$0,32767\(\$sp\) + 30c: f9 c0 ff 7f sh \$0,32767\(\$sp\) + 310: fa c0 ff 7f sw \$0,32767\(\$sp\) + 314: fc c0 ff 7f lb \$0,32767\(\$sp\) + 318: fd c0 ff 7f lh \$0,32767\(\$sp\) + 31c: fe c0 ff 7f lw \$0,32767\(\$sp\) + 320: fb c0 ff 7f lbu \$0,32767\(\$sp\) + 324: ff c0 ff 7f lhu \$0,32767\(\$sp\) + 328: f8 cf ff 7f sb \$sp,32767\(\$sp\) + 32c: f9 cf ff 7f sh \$sp,32767\(\$sp\) + 330: fa cf ff 7f sw \$sp,32767\(\$sp\) + 334: fc cf ff 7f lb \$sp,32767\(\$sp\) + 338: fd cf ff 7f lh \$sp,32767\(\$sp\) + 33c: fe cf ff 7f lw \$sp,32767\(\$sp\) + 340: fb cf ff 7f lbu \$sp,32767\(\$sp\) + 344: ff cf ff 7f lhu \$sp,32767\(\$sp\) + 348: f8 c0 00 00 sb \$0,0\(\$sp\) + 348: R_MEP_GPREL symbol + 34c: f9 c0 00 00 sh \$0,0\(\$sp\) + 34c: R_MEP_GPREL symbol + 350: fa c0 00 00 sw \$0,0\(\$sp\) + 350: R_MEP_GPREL symbol + 354: fc c0 00 00 lb \$0,0\(\$sp\) + 354: R_MEP_GPREL symbol + 358: fd c0 00 00 lh \$0,0\(\$sp\) + 358: R_MEP_GPREL symbol + 35c: fe c0 00 00 lw \$0,0\(\$sp\) + 35c: R_MEP_GPREL symbol + 360: fb c0 00 00 lbu \$0,0\(\$sp\) + 360: R_MEP_GPREL symbol + 364: ff c0 00 00 lhu \$0,0\(\$sp\) + 364: R_MEP_GPREL symbol + 368: f8 cf 00 00 sb \$sp,0\(\$sp\) + 368: R_MEP_GPREL symbol + 36c: f9 cf 00 00 sh \$sp,0\(\$sp\) + 36c: R_MEP_GPREL symbol + 370: fa cf 00 00 sw \$sp,0\(\$sp\) + 370: R_MEP_GPREL symbol + 374: fc cf 00 00 lb \$sp,0\(\$sp\) + 374: R_MEP_GPREL symbol + 378: fd cf 00 00 lh \$sp,0\(\$sp\) + 378: R_MEP_GPREL symbol + 37c: fe cf 00 00 lw \$sp,0\(\$sp\) + 37c: R_MEP_GPREL symbol + 380: fb cf 00 00 lbu \$sp,0\(\$sp\) + 380: R_MEP_GPREL symbol + 384: ff cf 00 00 lhu \$sp,0\(\$sp\) + 384: R_MEP_GPREL symbol + 388: f8 c0 00 80 sb \$0,-32768\(\$sp\) + 38c: f9 c0 00 80 sh \$0,-32768\(\$sp\) + 390: fa c0 00 80 sw \$0,-32768\(\$sp\) + 394: fc c0 00 80 lb \$0,-32768\(\$sp\) + 398: fd c0 00 80 lh \$0,-32768\(\$sp\) + 39c: fe c0 00 80 lw \$0,-32768\(\$sp\) + 3a0: fb c0 00 80 lbu \$0,-32768\(\$sp\) + 3a4: ff c0 00 80 lhu \$0,-32768\(\$sp\) + 3a8: f8 cf 00 80 sb \$sp,-32768\(\$sp\) + 3ac: f9 cf 00 80 sh \$sp,-32768\(\$sp\) + 3b0: fa cf 00 80 sw \$sp,-32768\(\$sp\) + 3b4: fc cf 00 80 lb \$sp,-32768\(\$sp\) + 3b8: fd cf 00 80 lh \$sp,-32768\(\$sp\) + 3bc: fe cf 00 80 lw \$sp,-32768\(\$sp\) + 3c0: fb cf 00 80 lbu \$sp,-32768\(\$sp\) + 3c4: ff cf 00 80 lhu \$sp,-32768\(\$sp\) + 3c8: f8 c0 ff 7f sb \$0,32767\(\$sp\) + 3cc: f9 c0 ff 7f sh \$0,32767\(\$sp\) + 3d0: fa c0 ff 7f sw \$0,32767\(\$sp\) + 3d4: fc c0 ff 7f lb \$0,32767\(\$sp\) + 3d8: fd c0 ff 7f lh \$0,32767\(\$sp\) + 3dc: fe c0 ff 7f lw \$0,32767\(\$sp\) + 3e0: fb c0 ff 7f lbu \$0,32767\(\$sp\) + 3e4: ff c0 ff 7f lhu \$0,32767\(\$sp\) + 3e8: f8 cf ff 7f sb \$sp,32767\(\$sp\) + 3ec: f9 cf ff 7f sh \$sp,32767\(\$sp\) + 3f0: fa cf ff 7f sw \$sp,32767\(\$sp\) + 3f4: fc cf ff 7f lb \$sp,32767\(\$sp\) + 3f8: fd cf ff 7f lh \$sp,32767\(\$sp\) + 3fc: fe cf ff 7f lw \$sp,32767\(\$sp\) + 400: fb cf ff 7f lbu \$sp,32767\(\$sp\) + 404: ff cf ff 7f lhu \$sp,32767\(\$sp\) + 408: f8 c0 00 00 sb \$0,0\(\$sp\) + 408: R_MEP_TPREL symbol + 40c: f9 c0 00 00 sh \$0,0\(\$sp\) + 40c: R_MEP_TPREL symbol + 410: 02 40 sw \$0,0x0\(\$sp\) + 410: R_MEP_TPREL7A4 symbol + 412: fc c0 00 00 lb \$0,0\(\$sp\) + 412: R_MEP_TPREL symbol + 416: fd c0 00 00 lh \$0,0\(\$sp\) + 416: R_MEP_TPREL symbol + 41a: 03 40 lw \$0,0x0\(\$sp\) + 41a: R_MEP_TPREL7A4 symbol + 41c: fb c0 00 00 lbu \$0,0\(\$sp\) + 41c: R_MEP_TPREL symbol + 420: ff c0 00 00 lhu \$0,0\(\$sp\) + 420: R_MEP_TPREL symbol + 424: f8 cf 00 00 sb \$sp,0\(\$sp\) + 424: R_MEP_TPREL symbol + 428: f9 cf 00 00 sh \$sp,0\(\$sp\) + 428: R_MEP_TPREL symbol + 42c: 02 4f sw \$sp,0x0\(\$sp\) + 42c: R_MEP_TPREL7A4 symbol + 42e: fc cf 00 00 lb \$sp,0\(\$sp\) + 42e: R_MEP_TPREL symbol + 432: fd cf 00 00 lh \$sp,0\(\$sp\) + 432: R_MEP_TPREL symbol + 436: 03 4f lw \$sp,0x0\(\$sp\) + 436: R_MEP_TPREL7A4 symbol + 438: fb cf 00 00 lbu \$sp,0\(\$sp\) + 438: R_MEP_TPREL symbol + 43c: ff cf 00 00 lhu \$sp,0\(\$sp\) + 43c: R_MEP_TPREL symbol + 440: 02 e0 00 00 sw \$0,\(0x0\) + 444: 03 e0 00 00 lw \$0,\(0x0\) + 448: 02 ef 00 00 sw \$sp,\(0x0\) + 44c: 03 ef 00 00 lw \$sp,\(0x0\) + 450: fe e0 ff ff sw \$0,\(0xfffffc\) + 454: ff e0 ff ff lw \$0,\(0xfffffc\) + 458: fe ef ff ff sw \$sp,\(0xfffffc\) + 45c: ff ef ff ff lw \$sp,\(0xfffffc\) + 460: 02 e0 00 00 sw \$0,\(0x0\) + 460: R_MEP_ADDR24A4 symbol + 464: 03 e0 00 00 lw \$0,\(0x0\) + 464: R_MEP_ADDR24A4 symbol + 468: 02 ef 00 00 sw \$sp,\(0x0\) + 468: R_MEP_ADDR24A4 symbol + 46c: 03 ef 00 00 lw \$sp,\(0x0\) + 46c: R_MEP_ADDR24A4 symbol + 470: 0d 10 extb \$0 + 472: 8d 10 extub \$0 + 474: 2d 10 exth \$0 + 476: ad 10 extuh \$0 + 478: 0d 1f extb \$sp + 47a: 8d 1f extub \$sp + 47c: 2d 1f exth \$sp + 47e: ad 1f extuh \$sp + 480: 0c 10 ssarb 0\(\$0\) + 482: 0c 13 ssarb 3\(\$0\) + 484: fc 10 ssarb 0\(\$sp\) + 486: fc 13 ssarb 3\(\$sp\) + 488: 00 00 nop + 48a: 00 0f mov \$sp,\$0 + 48c: f0 00 mov \$0,\$sp + 48e: f0 0f mov \$sp,\$sp + 490: 01 c0 00 80 mov \$0,-32768 + 494: 01 cf 00 80 mov \$sp,-32768 + 498: 80 50 mov \$0,-128 + 49a: 80 5f mov \$sp,-128 + 49c: 00 50 mov \$0,0 + 49e: 00 5f mov \$sp,0 + 4a0: 7f 50 mov \$0,127 + 4a2: 7f 5f mov \$sp,127 + 4a4: 01 c0 ff 7f mov \$0,32767 + 4a8: 01 cf ff 7f mov \$sp,32767 + 4ac: 01 c0 00 00 mov \$0,0 + 4ac: R_MEP_LOW16 symbol + 4b0: 01 c0 00 00 mov \$0,0 + 4b0: R_MEP_HI16S symbol + 4b4: 01 c0 00 00 mov \$0,0 + 4b4: R_MEP_HI16U symbol + 4b8: 01 c0 00 00 mov \$0,0 + 4b8: R_MEP_GPREL symbol + 4bc: 01 c0 00 00 mov \$0,0 + 4bc: R_MEP_TPREL symbol + 4c0: 00 d0 00 00 movu \$0,0x0 + 4c4: 00 d7 00 00 movu \$7,0x0 + 4c8: ff d0 ff ff movu \$0,0xffffff + 4cc: ff d7 ff ff movu \$7,0xffffff + 4d0: 11 c0 00 00 movu \$0,0x0 + 4d0: R_MEP_LOW16 symbol + 4d4: 11 c7 00 00 movu \$7,0x0 + 4d4: R_MEP_LOW16 symbol + 4d8: 00 d0 00 00 movu \$0,0x0 + 4d8: R_MEP_UIMM24 symbol + 4dc: 00 d7 00 00 movu \$7,0x0 + 4dc: R_MEP_UIMM24 symbol + 4e0: 00 d0 00 00 movu \$0,0x0 + 4e4: 21 c0 00 00 movh \$0,0x0 + 4e8: 11 cf 00 00 movu \$sp,0x0 + 4ec: 21 cf 00 00 movh \$sp,0x0 + 4f0: ff d0 ff 00 movu \$0,0xffff + 4f4: 21 c0 ff ff movh \$0,0xffff + 4f8: 11 cf ff ff movu \$sp,0xffff + 4fc: 21 cf ff ff movh \$sp,0xffff + 500: 11 c0 00 00 movu \$0,0x0 + 500: R_MEP_LOW16 symbol + 504: 21 c0 00 00 movh \$0,0x0 + 504: R_MEP_LOW16 symbol + 508: 11 cf 00 00 movu \$sp,0x0 + 508: R_MEP_LOW16 symbol + 50c: 21 cf 00 00 movh \$sp,0x0 + 50c: R_MEP_LOW16 symbol + 510: 11 c0 00 00 movu \$0,0x0 + 510: R_MEP_HI16S symbol + 514: 21 c0 00 00 movh \$0,0x0 + 514: R_MEP_HI16S symbol + 518: 11 cf 00 00 movu \$sp,0x0 + 518: R_MEP_HI16S symbol + 51c: 21 cf 00 00 movh \$sp,0x0 + 51c: R_MEP_HI16S symbol + 520: 11 c0 00 00 movu \$0,0x0 + 520: R_MEP_HI16U symbol + 524: 21 c0 00 00 movh \$0,0x0 + 524: R_MEP_HI16U symbol + 528: 11 cf 00 00 movu \$sp,0x0 + 528: R_MEP_HI16U symbol + 52c: 21 cf 00 00 movh \$sp,0x0 + 52c: R_MEP_HI16U symbol + 530: 11 c0 78 56 movu \$0,0x5678 + 534: 21 c0 78 56 movh \$0,0x5678 + 538: 11 cf 78 56 movu \$sp,0x5678 + 53c: 21 cf 78 56 movh \$sp,0x5678 + 540: 11 c0 34 12 movu \$0,0x1234 + 544: 21 c0 34 12 movh \$0,0x1234 + 548: 11 cf 34 12 movu \$sp,0x1234 + 54c: 21 cf 34 12 movh \$sp,0x1234 + 550: 11 c0 34 12 movu \$0,0x1234 + 554: 21 c0 34 12 movh \$0,0x1234 + 558: 11 cf 34 12 movu \$sp,0x1234 + 55c: 21 cf 34 12 movh \$sp,0x1234 + 560: 00 90 add3 \$0,\$0,\$0 + 562: 0f 90 add3 \$sp,\$0,\$0 + 564: 00 9f add3 \$0,\$sp,\$0 + 566: 0f 9f add3 \$sp,\$sp,\$0 + 568: f0 90 add3 \$0,\$0,\$sp + 56a: ff 90 add3 \$sp,\$0,\$sp + 56c: f0 9f add3 \$0,\$sp,\$sp + 56e: ff 9f add3 \$sp,\$sp,\$sp + 570: c0 60 add \$0,-16 + 572: c0 6f add \$sp,-16 + 574: 00 60 add \$0,0 + 576: 00 6f add \$sp,0 + 578: 3c 60 add \$0,15 + 57a: 3c 6f add \$sp,15 + 57c: 00 40 add3 \$0,\$sp,0x0 + 57e: 00 4f add3 \$sp,\$sp,0x0 + 580: 7c 40 add3 \$0,\$sp,0x7c + 582: 7c 4f add3 \$sp,\$sp,0x7c + 584: f0 c0 01 00 add3 \$0,\$sp,1 + 588: f0 cf 01 00 add3 \$sp,\$sp,1 + 58c: 07 00 advck3 \$0,\$0,\$0 + 58e: 05 00 sbvck3 \$0,\$0,\$0 + 590: 07 0f advck3 \$0,\$sp,\$0 + 592: 05 0f sbvck3 \$0,\$sp,\$0 + 594: f7 00 advck3 \$0,\$0,\$sp + 596: f5 00 sbvck3 \$0,\$0,\$sp + 598: f7 0f advck3 \$0,\$sp,\$sp + 59a: f5 0f sbvck3 \$0,\$sp,\$sp + 59c: 04 00 sub \$0,\$0 + 59e: 01 00 neg \$0,\$0 + 5a0: 04 0f sub \$sp,\$0 + 5a2: 01 0f neg \$sp,\$0 + 5a4: f4 00 sub \$0,\$sp + 5a6: f1 00 neg \$0,\$sp + 5a8: f4 0f sub \$sp,\$sp + 5aa: f1 0f neg \$sp,\$sp + 5ac: 02 00 slt3 \$0,\$0,\$0 + 5ae: 03 00 sltu3 \$0,\$0,\$0 + 5b0: 06 20 sl1ad3 \$0,\$0,\$0 + 5b2: 07 20 sl2ad3 \$0,\$0,\$0 + 5b4: 02 0f slt3 \$0,\$sp,\$0 + 5b6: 03 0f sltu3 \$0,\$sp,\$0 + 5b8: 06 2f sl1ad3 \$0,\$sp,\$0 + 5ba: 07 2f sl2ad3 \$0,\$sp,\$0 + 5bc: f2 00 slt3 \$0,\$0,\$sp + 5be: f3 00 sltu3 \$0,\$0,\$sp + 5c0: f6 20 sl1ad3 \$0,\$0,\$sp + 5c2: f7 20 sl2ad3 \$0,\$0,\$sp + 5c4: f2 0f slt3 \$0,\$sp,\$sp + 5c6: f3 0f sltu3 \$0,\$sp,\$sp + 5c8: f6 2f sl1ad3 \$0,\$sp,\$sp + 5ca: f7 2f sl2ad3 \$0,\$sp,\$sp + 5cc: 00 c0 00 80 add3 \$0,\$0,-32768 + 5d0: 00 cf 00 80 add3 \$sp,\$0,-32768 + 5d4: f0 c0 00 80 add3 \$0,\$sp,-32768 + 5d8: f0 cf 00 80 add3 \$sp,\$sp,-32768 + 5dc: 00 c0 ff 7f add3 \$0,\$0,32767 + 5e0: 00 cf ff 7f add3 \$sp,\$0,32767 + 5e4: f0 c0 ff 7f add3 \$0,\$sp,32767 + 5e8: f0 cf ff 7f add3 \$sp,\$sp,32767 + 5ec: 00 c0 00 00 add3 \$0,\$0,0 + 5ec: R_MEP_LOW16 symbol + 5f0: 00 cf 00 00 add3 \$sp,\$0,0 + 5f0: R_MEP_LOW16 symbol + 5f4: f0 c0 00 00 add3 \$0,\$sp,0 + 5f4: R_MEP_LOW16 symbol + 5f8: f0 cf 00 00 add3 \$sp,\$sp,0 + 5f8: R_MEP_LOW16 symbol + 5fc: 01 60 slt3 \$0,\$0,0x0 + 5fe: 05 60 sltu3 \$0,\$0,0x0 + 600: 01 6f slt3 \$0,\$sp,0x0 + 602: 05 6f sltu3 \$0,\$sp,0x0 + 604: f9 60 slt3 \$0,\$0,0x1f + 606: fd 60 sltu3 \$0,\$0,0x1f + 608: f9 6f slt3 \$0,\$sp,0x1f + 60a: fd 6f sltu3 \$0,\$sp,0x1f + 60c: 00 10 or \$0,\$0 + 60e: 01 10 and \$0,\$0 + 610: 02 10 xor \$0,\$0 + 612: 03 10 nor \$0,\$0 + 614: 00 1f or \$sp,\$0 + 616: 01 1f and \$sp,\$0 + 618: 02 1f xor \$sp,\$0 + 61a: 03 1f nor \$sp,\$0 + 61c: f0 10 or \$0,\$sp + 61e: f1 10 and \$0,\$sp + 620: f2 10 xor \$0,\$sp + 622: f3 10 nor \$0,\$sp + 624: f0 1f or \$sp,\$sp + 626: f1 1f and \$sp,\$sp + 628: f2 1f xor \$sp,\$sp + 62a: f3 1f nor \$sp,\$sp + 62c: 04 c0 00 00 or3 \$0,\$0,0x0 + 630: 05 c0 00 00 and3 \$0,\$0,0x0 + 634: 06 c0 00 00 xor3 \$0,\$0,0x0 + 638: 04 cf 00 00 or3 \$sp,\$0,0x0 + 63c: 05 cf 00 00 and3 \$sp,\$0,0x0 + 640: 06 cf 00 00 xor3 \$sp,\$0,0x0 + 644: f4 c0 00 00 or3 \$0,\$sp,0x0 + 648: f5 c0 00 00 and3 \$0,\$sp,0x0 + 64c: f6 c0 00 00 xor3 \$0,\$sp,0x0 + 650: f4 cf 00 00 or3 \$sp,\$sp,0x0 + 654: f5 cf 00 00 and3 \$sp,\$sp,0x0 + 658: f6 cf 00 00 xor3 \$sp,\$sp,0x0 + 65c: 04 c0 ff ff or3 \$0,\$0,0xffff + 660: 05 c0 ff ff and3 \$0,\$0,0xffff + 664: 06 c0 ff ff xor3 \$0,\$0,0xffff + 668: 04 cf ff ff or3 \$sp,\$0,0xffff + 66c: 05 cf ff ff and3 \$sp,\$0,0xffff + 670: 06 cf ff ff xor3 \$sp,\$0,0xffff + 674: f4 c0 ff ff or3 \$0,\$sp,0xffff + 678: f5 c0 ff ff and3 \$0,\$sp,0xffff + 67c: f6 c0 ff ff xor3 \$0,\$sp,0xffff + 680: f4 cf ff ff or3 \$sp,\$sp,0xffff + 684: f5 cf ff ff and3 \$sp,\$sp,0xffff + 688: f6 cf ff ff xor3 \$sp,\$sp,0xffff + 68c: 04 c0 00 00 or3 \$0,\$0,0x0 + 68c: R_MEP_LOW16 symbol + 690: 05 c0 00 00 and3 \$0,\$0,0x0 + 690: R_MEP_LOW16 symbol + 694: 06 c0 00 00 xor3 \$0,\$0,0x0 + 694: R_MEP_LOW16 symbol + 698: 04 cf 00 00 or3 \$sp,\$0,0x0 + 698: R_MEP_LOW16 symbol + 69c: 05 cf 00 00 and3 \$sp,\$0,0x0 + 69c: R_MEP_LOW16 symbol + 6a0: 06 cf 00 00 xor3 \$sp,\$0,0x0 + 6a0: R_MEP_LOW16 symbol + 6a4: f4 c0 00 00 or3 \$0,\$sp,0x0 + 6a4: R_MEP_LOW16 symbol + 6a8: f5 c0 00 00 and3 \$0,\$sp,0x0 + 6a8: R_MEP_LOW16 symbol + 6ac: f6 c0 00 00 xor3 \$0,\$sp,0x0 + 6ac: R_MEP_LOW16 symbol + 6b0: f4 cf 00 00 or3 \$sp,\$sp,0x0 + 6b0: R_MEP_LOW16 symbol + 6b4: f5 cf 00 00 and3 \$sp,\$sp,0x0 + 6b4: R_MEP_LOW16 symbol + 6b8: f6 cf 00 00 xor3 \$sp,\$sp,0x0 + 6b8: R_MEP_LOW16 symbol + 6bc: 0d 20 sra \$0,\$0 + 6be: 0c 20 srl \$0,\$0 + 6c0: 0e 20 sll \$0,\$0 + 6c2: 0f 20 fsft \$0,\$0 + 6c4: 0d 2f sra \$sp,\$0 + 6c6: 0c 2f srl \$sp,\$0 + 6c8: 0e 2f sll \$sp,\$0 + 6ca: 0f 2f fsft \$sp,\$0 + 6cc: fd 20 sra \$0,\$sp + 6ce: fc 20 srl \$0,\$sp + 6d0: fe 20 sll \$0,\$sp + 6d2: ff 20 fsft \$0,\$sp + 6d4: fd 2f sra \$sp,\$sp + 6d6: fc 2f srl \$sp,\$sp + 6d8: fe 2f sll \$sp,\$sp + 6da: ff 2f fsft \$sp,\$sp + 6dc: 03 60 sra \$0,0x0 + 6de: 02 60 srl \$0,0x0 + 6e0: 06 60 sll \$0,0x0 + 6e2: 03 6f sra \$sp,0x0 + 6e4: 02 6f srl \$sp,0x0 + 6e6: 06 6f sll \$sp,0x0 + 6e8: fb 60 sra \$0,0x1f + 6ea: fa 60 srl \$0,0x1f + 6ec: fe 60 sll \$0,0x1f + 6ee: fb 6f sra \$sp,0x1f + 6f0: fa 6f srl \$sp,0x1f + 6f2: fe 6f sll \$sp,0x1f + 6f4: 07 60 sll3 \$0,\$0,0x0 + 6f6: 07 6f sll3 \$0,\$sp,0x0 + 6f8: ff 60 sll3 \$0,\$0,0x1f + 6fa: ff 6f sll3 \$0,\$sp,0x1f + 6fc: 02 b8 bra 0xfffffefe + 6fe: 01 e0 00 04 beq \$0,\$0,0xefe + 702: 00 b0 bra 0x702 + 702: R_MEP_PCREL12A2 symbol + 704: 82 a0 beqz \$0,0x686 + 706: 83 a0 bnez \$0,0x688 + 708: 82 af beqz \$sp,0x68a + 70a: 83 af bnez \$sp,0x68c + 70c: 00 e0 40 00 beqi \$0,0x0,0x78c + 710: 04 e0 40 00 bnei \$0,0x0,0x790 + 714: 00 ef 40 00 beqi \$sp,0x0,0x794 + 718: 04 ef 40 00 bnei \$sp,0x0,0x798 + 71c: 00 a0 beqz \$0,0x71c + 71c: R_MEP_PCREL8A2 symbol + 71e: 01 a0 bnez \$0,0x71e + 71e: R_MEP_PCREL8A2 symbol + 720: 00 af beqz \$sp,0x720 + 720: R_MEP_PCREL8A2 symbol + 722: 01 af bnez \$sp,0x722 + 722: R_MEP_PCREL8A2 symbol + 724: 00 e0 02 80 beqi \$0,0x0,0xffff0728 + 728: 04 e0 02 80 bnei \$0,0x0,0xffff072c + 72c: 0c e0 02 80 blti \$0,0x0,0xffff0730 + 730: 08 e0 02 80 bgei \$0,0x0,0xffff0734 + 734: 00 ef 02 80 beqi \$sp,0x0,0xffff0738 + 738: 04 ef 02 80 bnei \$sp,0x0,0xffff073c + 73c: 0c ef 02 80 blti \$sp,0x0,0xffff0740 + 740: 08 ef 02 80 bgei \$sp,0x0,0xffff0744 + 744: f0 e0 02 80 beqi \$0,0xf,0xffff0748 + 748: f4 e0 02 80 bnei \$0,0xf,0xffff074c + 74c: fc e0 02 80 blti \$0,0xf,0xffff0750 + 750: f8 e0 02 80 bgei \$0,0xf,0xffff0754 + 754: f0 ef 02 80 beqi \$sp,0xf,0xffff0758 + 758: f4 ef 02 80 bnei \$sp,0xf,0xffff075c + 75c: fc ef 02 80 blti \$sp,0xf,0xffff0760 + 760: f8 ef 02 80 bgei \$sp,0xf,0xffff0764 + 764: 00 e0 ff 3f beqi \$0,0x0,0x8762 + 768: 04 e0 ff 3f bnei \$0,0x0,0x8766 + 76c: 0c e0 ff 3f blti \$0,0x0,0x876a + 770: 08 e0 ff 3f bgei \$0,0x0,0x876e + 774: 00 ef ff 3f beqi \$sp,0x0,0x8772 + 778: 04 ef ff 3f bnei \$sp,0x0,0x8776 + 77c: 0c ef ff 3f blti \$sp,0x0,0x877a + 780: 08 ef ff 3f bgei \$sp,0x0,0x877e + 784: f0 e0 ff 3f beqi \$0,0xf,0x8782 + 788: f4 e0 ff 3f bnei \$0,0xf,0x8786 + 78c: fc e0 ff 3f blti \$0,0xf,0x878a + 790: f8 e0 ff 3f bgei \$0,0xf,0x878e + 794: f0 ef ff 3f beqi \$sp,0xf,0x8792 + 798: f4 ef ff 3f bnei \$sp,0xf,0x8796 + 79c: fc ef ff 3f blti \$sp,0xf,0x879a + 7a0: f8 ef ff 3f bgei \$sp,0xf,0x879e + 7a4: 00 e0 00 00 beqi \$0,0x0,0x7a4 + 7a4: R_MEP_PCREL17A2 symbol + 7a8: 04 e0 00 00 bnei \$0,0x0,0x7a8 + 7a8: R_MEP_PCREL17A2 symbol + 7ac: 0c e0 00 00 blti \$0,0x0,0x7ac + 7ac: R_MEP_PCREL17A2 symbol + 7b0: 08 e0 00 00 bgei \$0,0x0,0x7b0 + 7b0: R_MEP_PCREL17A2 symbol + 7b4: 00 ef 00 00 beqi \$sp,0x0,0x7b4 + 7b4: R_MEP_PCREL17A2 symbol + 7b8: 04 ef 00 00 bnei \$sp,0x0,0x7b8 + 7b8: R_MEP_PCREL17A2 symbol + 7bc: 0c ef 00 00 blti \$sp,0x0,0x7bc + 7bc: R_MEP_PCREL17A2 symbol + 7c0: 08 ef 00 00 bgei \$sp,0x0,0x7c0 + 7c0: R_MEP_PCREL17A2 symbol + 7c4: f0 e0 00 00 beqi \$0,0xf,0x7c4 + 7c4: R_MEP_PCREL17A2 symbol + 7c8: f4 e0 00 00 bnei \$0,0xf,0x7c8 + 7c8: R_MEP_PCREL17A2 symbol + 7cc: fc e0 00 00 blti \$0,0xf,0x7cc + 7cc: R_MEP_PCREL17A2 symbol + 7d0: f8 e0 00 00 bgei \$0,0xf,0x7d0 + 7d0: R_MEP_PCREL17A2 symbol + 7d4: f0 ef 00 00 beqi \$sp,0xf,0x7d4 + 7d4: R_MEP_PCREL17A2 symbol + 7d8: f4 ef 00 00 bnei \$sp,0xf,0x7d8 + 7d8: R_MEP_PCREL17A2 symbol + 7dc: fc ef 00 00 blti \$sp,0xf,0x7dc + 7dc: R_MEP_PCREL17A2 symbol + 7e0: f8 ef 00 00 bgei \$sp,0xf,0x7e0 + 7e0: R_MEP_PCREL17A2 symbol + 7e4: 01 e0 02 80 beq \$0,\$0,0xffff07e8 + 7e8: 05 e0 02 80 bne \$0,\$0,0xffff07ec + 7ec: 01 ef 02 80 beq \$sp,\$0,0xffff07f0 + 7f0: 05 ef 02 80 bne \$sp,\$0,0xffff07f4 + 7f4: f1 e0 02 80 beq \$0,\$sp,0xffff07f8 + 7f8: f5 e0 02 80 bne \$0,\$sp,0xffff07fc + 7fc: f1 ef 02 80 beq \$sp,\$sp,0xffff0800 + 800: f5 ef 02 80 bne \$sp,\$sp,0xffff0804 + 804: 01 e0 ff 3f beq \$0,\$0,0x8802 + 808: 05 e0 ff 3f bne \$0,\$0,0x8806 + 80c: 01 ef ff 3f beq \$sp,\$0,0x880a + 810: 05 ef ff 3f bne \$sp,\$0,0x880e + 814: f1 e0 ff 3f beq \$0,\$sp,0x8812 + 818: f5 e0 ff 3f bne \$0,\$sp,0x8816 + 81c: f1 ef ff 3f beq \$sp,\$sp,0x881a + 820: f5 ef ff 3f bne \$sp,\$sp,0x881e + 824: 01 e0 00 00 beq \$0,\$0,0x824 + 824: R_MEP_PCREL17A2 symbol + 828: 05 e0 00 00 bne \$0,\$0,0x828 + 828: R_MEP_PCREL17A2 symbol + 82c: 01 ef 00 00 beq \$sp,\$0,0x82c + 82c: R_MEP_PCREL17A2 symbol + 830: 05 ef 00 00 bne \$sp,\$0,0x830 + 830: R_MEP_PCREL17A2 symbol + 834: f1 e0 00 00 beq \$0,\$sp,0x834 + 834: R_MEP_PCREL17A2 symbol + 838: f5 e0 00 00 bne \$0,\$sp,0x838 + 838: R_MEP_PCREL17A2 symbol + 83c: f1 ef 00 00 beq \$sp,\$sp,0x83c + 83c: R_MEP_PCREL17A2 symbol + 840: f5 ef 00 00 bne \$sp,\$sp,0x840 + 840: R_MEP_PCREL17A2 symbol + 844: 29 d8 00 80 bsr 0xff800848 + 848: 03 b8 bsr 0x4a + 84a: 09 d8 08 00 bsr 0x104a + 84e: 19 d8 00 80 bsr 0xff800850 + 852: 09 d8 00 00 bsr 0x852 + 852: R_MEP_PCREL24A2 symbol + 856: 0e 10 jmp \$0 + 858: fe 10 jmp \$sp + 85a: 08 d8 00 00 jmp 0x0 + 85e: f8 df ff ff jmp 0xfffffe + 862: 08 d8 00 00 jmp 0x0 + 862: R_MEP_PCABS24A2 symbol + 866: 0f 10 jsr \$0 + 868: ff 10 jsr \$sp + 86a: 02 70 ret + 86c: 09 e0 02 80 repeat \$0,0xffff0870 + 870: 09 ef 02 80 repeat \$sp,0xffff0874 + 874: 09 e0 ff 3f repeat \$0,0x8872 + 878: 09 ef ff 3f repeat \$sp,0x8876 + 87c: 09 e0 00 00 repeat \$0,0x87c + 87c: R_MEP_PCREL17A2 symbol + 880: 09 ef 00 00 repeat \$sp,0x880 + 880: R_MEP_PCREL17A2 symbol + 884: 19 e0 02 80 erepeat 0xffff0888 + 888: 19 e0 ff 3f erepeat 0x8886 + 88c: 19 e0 00 00 erepeat 0x88c + 88c: R_MEP_PCREL17A2 symbol + 890: 08 70 stc \$0,\$pc + 892: 0a 70 ldc \$0,\$pc + 894: 08 7f stc \$sp,\$pc + 896: 0a 7f ldc \$sp,\$pc + 898: 18 70 stc \$0,\$lp + 89a: 1a 70 ldc \$0,\$lp + 89c: 18 7f stc \$sp,\$lp + 89e: 1a 7f ldc \$sp,\$lp + 8a0: 28 70 stc \$0,\$sar + 8a2: 2a 70 ldc \$0,\$sar + 8a4: 28 7f stc \$sp,\$sar + 8a6: 2a 7f ldc \$sp,\$sar + 8a8: 48 70 stc \$0,\$rpb + 8aa: 4a 70 ldc \$0,\$rpb + 8ac: 48 7f stc \$sp,\$rpb + 8ae: 4a 7f ldc \$sp,\$rpb + 8b0: 58 70 stc \$0,\$rpe + 8b2: 5a 70 ldc \$0,\$rpe + 8b4: 58 7f stc \$sp,\$rpe + 8b6: 5a 7f ldc \$sp,\$rpe + 8b8: 68 70 stc \$0,\$rpc + 8ba: 6a 70 ldc \$0,\$rpc + 8bc: 68 7f stc \$sp,\$rpc + 8be: 6a 7f ldc \$sp,\$rpc + 8c0: 78 70 stc \$0,\$hi + 8c2: 7a 70 ldc \$0,\$hi + 8c4: 78 7f stc \$sp,\$hi + 8c6: 7a 7f ldc \$sp,\$hi + 8c8: 88 70 stc \$0,\$lo + 8ca: 8a 70 ldc \$0,\$lo + 8cc: 88 7f stc \$sp,\$lo + 8ce: 8a 7f ldc \$sp,\$lo + 8d0: c8 70 stc \$0,\$mb0 + 8d2: ca 70 ldc \$0,\$mb0 + 8d4: c8 7f stc \$sp,\$mb0 + 8d6: ca 7f ldc \$sp,\$mb0 + 8d8: d8 70 stc \$0,\$me0 + 8da: da 70 ldc \$0,\$me0 + 8dc: d8 7f stc \$sp,\$me0 + 8de: da 7f ldc \$sp,\$me0 + 8e0: e8 70 stc \$0,\$mb1 + 8e2: ea 70 ldc \$0,\$mb1 + 8e4: e8 7f stc \$sp,\$mb1 + 8e6: ea 7f ldc \$sp,\$mb1 + 8e8: f8 70 stc \$0,\$me1 + 8ea: fa 70 ldc \$0,\$me1 + 8ec: f8 7f stc \$sp,\$me1 + 8ee: fa 7f ldc \$sp,\$me1 + 8f0: 09 70 stc \$0,\$psw + 8f2: 0b 70 ldc \$0,\$psw + 8f4: 09 7f stc \$sp,\$psw + 8f6: 0b 7f ldc \$sp,\$psw + 8f8: 19 70 stc \$0,\$id + 8fa: 1b 70 ldc \$0,\$id + 8fc: 19 7f stc \$sp,\$id + 8fe: 1b 7f ldc \$sp,\$id + 900: 29 70 stc \$0,\$tmp + 902: 2b 70 ldc \$0,\$tmp + 904: 29 7f stc \$sp,\$tmp + 906: 2b 7f ldc \$sp,\$tmp + 908: 39 70 stc \$0,\$epc + 90a: 3b 70 ldc \$0,\$epc + 90c: 39 7f stc \$sp,\$epc + 90e: 3b 7f ldc \$sp,\$epc + 910: 49 70 stc \$0,\$exc + 912: 4b 70 ldc \$0,\$exc + 914: 49 7f stc \$sp,\$exc + 916: 4b 7f ldc \$sp,\$exc + 918: 59 70 stc \$0,\$cfg + 91a: 5b 70 ldc \$0,\$cfg + 91c: 59 7f stc \$sp,\$cfg + 91e: 5b 7f ldc \$sp,\$cfg + 920: 79 70 stc \$0,\$npc + 922: 7b 70 ldc \$0,\$npc + 924: 79 7f stc \$sp,\$npc + 926: 7b 7f ldc \$sp,\$npc + 928: 89 70 stc \$0,\$dbg + 92a: 8b 70 ldc \$0,\$dbg + 92c: 89 7f stc \$sp,\$dbg + 92e: 8b 7f ldc \$sp,\$dbg + 930: 99 70 stc \$0,\$depc + 932: 9b 70 ldc \$0,\$depc + 934: 99 7f stc \$sp,\$depc + 936: 9b 7f ldc \$sp,\$depc + 938: a9 70 stc \$0,\$opt + 93a: ab 70 ldc \$0,\$opt + 93c: a9 7f stc \$sp,\$opt + 93e: ab 7f ldc \$sp,\$opt + 940: b9 70 stc \$0,\$rcfg + 942: bb 70 ldc \$0,\$rcfg + 944: b9 7f stc \$sp,\$rcfg + 946: bb 7f ldc \$sp,\$rcfg + 948: c9 70 stc \$0,\$ccfg + 94a: cb 70 ldc \$0,\$ccfg + 94c: c9 7f stc \$sp,\$ccfg + 94e: cb 7f ldc \$sp,\$ccfg + 950: 00 70 di + 952: 10 70 ei + 954: 12 70 reti + 956: 22 70 halt + 958: 32 70 break + 95a: 11 70 syncm + 95c: 06 70 swi 0x0 + 95e: 36 70 swi 0x3 + 960: 04 f0 00 00 stcb \$0,0x0 + 964: 14 f0 00 00 ldcb \$0,0x0 + 968: 04 ff 00 00 stcb \$sp,0x0 + 96c: 14 ff 00 00 ldcb \$sp,0x0 + 970: 04 f0 ff ff stcb \$0,0xffff + 974: 14 f0 ff ff ldcb \$0,0xffff + 978: 04 ff ff ff stcb \$sp,0xffff + 97c: 14 ff ff ff ldcb \$sp,0xffff + 980: 04 f0 00 00 stcb \$0,0x0 + 982: R_MEP_16 symbol + 984: 14 f0 00 00 ldcb \$0,0x0 + 986: R_MEP_16 symbol + 988: 04 ff 00 00 stcb \$sp,0x0 + 98a: R_MEP_16 symbol + 98c: 14 ff 00 00 ldcb \$sp,0x0 + 98e: R_MEP_16 symbol + 990: 00 20 bsetm \(\$0\),0x0 + 992: 01 20 bclrm \(\$0\),0x0 + 994: 02 20 bnotm \(\$0\),0x0 + 996: f0 20 bsetm \(\$sp\),0x0 + 998: f1 20 bclrm \(\$sp\),0x0 + 99a: f2 20 bnotm \(\$sp\),0x0 + 99c: 00 27 bsetm \(\$0\),0x7 + 99e: 01 27 bclrm \(\$0\),0x7 + 9a0: 02 27 bnotm \(\$0\),0x7 + 9a2: f0 27 bsetm \(\$sp\),0x7 + 9a4: f1 27 bclrm \(\$sp\),0x7 + 9a6: f2 27 bnotm \(\$sp\),0x7 + 9a8: 03 20 btstm \$0,\(\$0\),0x0 + 9aa: f3 20 btstm \$0,\(\$sp\),0x0 + 9ac: 03 27 btstm \$0,\(\$0\),0x7 + 9ae: f3 27 btstm \$0,\(\$sp\),0x7 + 9b0: 04 20 tas \$0,\(\$0\) + 9b2: 04 2f tas \$sp,\(\$0\) + 9b4: f4 20 tas \$0,\(\$sp\) + 9b6: f4 2f tas \$sp,\(\$sp\) + 9b8: 04 70 cache 0x0,\(\$0\) + 9ba: 04 73 cache 0x3,\(\$0\) + 9bc: f4 70 cache 0x0,\(\$sp\) + 9be: f4 73 cache 0x3,\(\$sp\) + 9c0: 04 10 mul \$0,\$0 + 9c2: 01 f0 04 30 madd \$0,\$0 + 9c6: 06 10 mulr \$0,\$0 + 9c8: 01 f0 06 30 maddr \$0,\$0 + 9cc: 05 10 mulu \$0,\$0 + 9ce: 01 f0 05 30 maddu \$0,\$0 + 9d2: 07 10 mulru \$0,\$0 + 9d4: 01 f0 07 30 maddru \$0,\$0 + 9d8: 04 1f mul \$sp,\$0 + 9da: 01 ff 04 30 madd \$sp,\$0 + 9de: 06 1f mulr \$sp,\$0 + 9e0: 01 ff 06 30 maddr \$sp,\$0 + 9e4: 05 1f mulu \$sp,\$0 + 9e6: 01 ff 05 30 maddu \$sp,\$0 + 9ea: 07 1f mulru \$sp,\$0 + 9ec: 01 ff 07 30 maddru \$sp,\$0 + 9f0: f4 10 mul \$0,\$sp + 9f2: f1 f0 04 30 madd \$0,\$sp + 9f6: f6 10 mulr \$0,\$sp + 9f8: f1 f0 06 30 maddr \$0,\$sp + 9fc: f5 10 mulu \$0,\$sp + 9fe: f1 f0 05 30 maddu \$0,\$sp + a02: f7 10 mulru \$0,\$sp + a04: f1 f0 07 30 maddru \$0,\$sp + a08: f4 1f mul \$sp,\$sp + a0a: f1 ff 04 30 madd \$sp,\$sp + a0e: f6 1f mulr \$sp,\$sp + a10: f1 ff 06 30 maddr \$sp,\$sp + a14: f5 1f mulu \$sp,\$sp + a16: f1 ff 05 30 maddu \$sp,\$sp + a1a: f7 1f mulru \$sp,\$sp + a1c: f1 ff 07 30 maddru \$sp,\$sp + a20: 08 10 div \$0,\$0 + a22: 09 10 divu \$0,\$0 + a24: 08 1f div \$sp,\$0 + a26: 09 1f divu \$sp,\$0 + a28: f8 10 div \$0,\$sp + a2a: f9 10 divu \$0,\$sp + a2c: f8 1f div \$sp,\$sp + a2e: f9 1f divu \$sp,\$sp + a30: 13 70 dret + a32: 33 70 dbreak + a34: 01 f0 00 00 ldz \$0,\$0 + a38: 01 f0 03 00 abs \$0,\$0 + a3c: 01 f0 02 00 ave \$0,\$0 + a40: 01 ff 00 00 ldz \$sp,\$0 + a44: 01 ff 03 00 abs \$sp,\$0 + a48: 01 ff 02 00 ave \$sp,\$0 + a4c: f1 f0 00 00 ldz \$0,\$sp + a50: f1 f0 03 00 abs \$0,\$sp + a54: f1 f0 02 00 ave \$0,\$sp + a58: f1 ff 00 00 ldz \$sp,\$sp + a5c: f1 ff 03 00 abs \$sp,\$sp + a60: f1 ff 02 00 ave \$sp,\$sp + a64: 01 f0 04 00 min \$0,\$0 + a68: 01 f0 05 00 max \$0,\$0 + a6c: 01 f0 06 00 minu \$0,\$0 + a70: 01 f0 07 00 maxu \$0,\$0 + a74: 01 ff 04 00 min \$sp,\$0 + a78: 01 ff 05 00 max \$sp,\$0 + a7c: 01 ff 06 00 minu \$sp,\$0 + a80: 01 ff 07 00 maxu \$sp,\$0 + a84: f1 f0 04 00 min \$0,\$sp + a88: f1 f0 05 00 max \$0,\$sp + a8c: f1 f0 06 00 minu \$0,\$sp + a90: f1 f0 07 00 maxu \$0,\$sp + a94: f1 ff 04 00 min \$sp,\$sp + a98: f1 ff 05 00 max \$sp,\$sp + a9c: f1 ff 06 00 minu \$sp,\$sp + aa0: f1 ff 07 00 maxu \$sp,\$sp + aa4: 01 f0 00 10 clip \$0,0x0 + aa8: 01 f0 01 10 clipu \$0,0x0 + aac: 01 ff 00 10 clip \$sp,0x0 + ab0: 01 ff 01 10 clipu \$sp,0x0 + ab4: 01 f0 f8 10 clip \$0,0x1f + ab8: 01 f0 f9 10 clipu \$0,0x1f + abc: 01 ff f8 10 clip \$sp,0x1f + ac0: 01 ff f9 10 clipu \$sp,0x1f + ac4: 01 f0 08 00 sadd \$0,\$0 + ac8: 01 f0 0a 00 ssub \$0,\$0 + acc: 01 f0 09 00 saddu \$0,\$0 + ad0: 01 f0 0b 00 ssubu \$0,\$0 + ad4: 01 ff 08 00 sadd \$sp,\$0 + ad8: 01 ff 0a 00 ssub \$sp,\$0 + adc: 01 ff 09 00 saddu \$sp,\$0 + ae0: 01 ff 0b 00 ssubu \$sp,\$0 + ae4: f1 f0 08 00 sadd \$0,\$sp + ae8: f1 f0 0a 00 ssub \$0,\$sp + aec: f1 f0 09 00 saddu \$0,\$sp + af0: f1 f0 0b 00 ssubu \$0,\$sp + af4: f1 ff 08 00 sadd \$sp,\$sp + af8: f1 ff 0a 00 ssub \$sp,\$sp + afc: f1 ff 09 00 saddu \$sp,\$sp + b00: f1 ff 0b 00 ssubu \$sp,\$sp + b04: 08 30 swcp \$c0,\(\$0\) + b06: 09 30 lwcp \$c0,\(\$0\) + b08: 0a 30 smcp \$c0,\(\$0\) + b0a: 0b 30 lmcp \$c0,\(\$0\) + b0c: 08 3f swcp \$c15,\(\$0\) + b0e: 09 3f lwcp \$c15,\(\$0\) + b10: 0a 3f smcp \$c15,\(\$0\) + b12: 0b 3f lmcp \$c15,\(\$0\) + b14: f8 30 swcp \$c0,\(\$sp\) + b16: f9 30 lwcp \$c0,\(\$sp\) + b18: fa 30 smcp \$c0,\(\$sp\) + b1a: fb 30 lmcp \$c0,\(\$sp\) + b1c: f8 3f swcp \$c15,\(\$sp\) + b1e: f9 3f lwcp \$c15,\(\$sp\) + b20: fa 3f smcp \$c15,\(\$sp\) + b22: fb 3f lmcp \$c15,\(\$sp\) + b24: 00 30 swcpi \$c0,\(\$0\+\) + b26: 01 30 lwcpi \$c0,\(\$0\+\) + b28: 02 30 smcpi \$c0,\(\$0\+\) + b2a: 03 30 lmcpi \$c0,\(\$0\+\) + b2c: 00 3f swcpi \$c15,\(\$0\+\) + b2e: 01 3f lwcpi \$c15,\(\$0\+\) + b30: 02 3f smcpi \$c15,\(\$0\+\) + b32: 03 3f lmcpi \$c15,\(\$0\+\) + b34: f0 30 swcpi \$c0,\(\$sp\+\) + b36: f1 30 lwcpi \$c0,\(\$sp\+\) + b38: f2 30 smcpi \$c0,\(\$sp\+\) + b3a: f3 30 lmcpi \$c0,\(\$sp\+\) + b3c: f0 3f swcpi \$c15,\(\$sp\+\) + b3e: f1 3f lwcpi \$c15,\(\$sp\+\) + b40: f2 3f smcpi \$c15,\(\$sp\+\) + b42: f3 3f lmcpi \$c15,\(\$sp\+\) + b44: 05 f0 80 00 sbcpa \$c0,\(\$0\+\),-128 + b48: 05 f0 80 40 lbcpa \$c0,\(\$0\+\),-128 + b4c: 05 f0 80 08 sbcpm0 \$c0,\(\$0\+\),-128 + b50: 05 f0 80 48 lbcpm0 \$c0,\(\$0\+\),-128 + b54: 05 f0 80 0c sbcpm1 \$c0,\(\$0\+\),-128 + b58: 05 f0 80 4c lbcpm1 \$c0,\(\$0\+\),-128 + b5c: 05 ff 80 00 sbcpa \$c15,\(\$0\+\),-128 + b60: 05 ff 80 40 lbcpa \$c15,\(\$0\+\),-128 + b64: 05 ff 80 08 sbcpm0 \$c15,\(\$0\+\),-128 + b68: 05 ff 80 48 lbcpm0 \$c15,\(\$0\+\),-128 + b6c: 05 ff 80 0c sbcpm1 \$c15,\(\$0\+\),-128 + b70: 05 ff 80 4c lbcpm1 \$c15,\(\$0\+\),-128 + b74: f5 f0 80 00 sbcpa \$c0,\(\$sp\+\),-128 + b78: f5 f0 80 40 lbcpa \$c0,\(\$sp\+\),-128 + b7c: f5 f0 80 08 sbcpm0 \$c0,\(\$sp\+\),-128 + b80: f5 f0 80 48 lbcpm0 \$c0,\(\$sp\+\),-128 + b84: f5 f0 80 0c sbcpm1 \$c0,\(\$sp\+\),-128 + b88: f5 f0 80 4c lbcpm1 \$c0,\(\$sp\+\),-128 + b8c: f5 ff 80 00 sbcpa \$c15,\(\$sp\+\),-128 + b90: f5 ff 80 40 lbcpa \$c15,\(\$sp\+\),-128 + b94: f5 ff 80 08 sbcpm0 \$c15,\(\$sp\+\),-128 + b98: f5 ff 80 48 lbcpm0 \$c15,\(\$sp\+\),-128 + b9c: f5 ff 80 0c sbcpm1 \$c15,\(\$sp\+\),-128 + ba0: f5 ff 80 4c lbcpm1 \$c15,\(\$sp\+\),-128 + ba4: 05 f0 7f 00 sbcpa \$c0,\(\$0\+\),127 + ba8: 05 f0 7f 40 lbcpa \$c0,\(\$0\+\),127 + bac: 05 f0 7f 08 sbcpm0 \$c0,\(\$0\+\),127 + bb0: 05 f0 7f 48 lbcpm0 \$c0,\(\$0\+\),127 + bb4: 05 f0 7f 0c sbcpm1 \$c0,\(\$0\+\),127 + bb8: 05 f0 7f 4c lbcpm1 \$c0,\(\$0\+\),127 + bbc: 05 ff 7f 00 sbcpa \$c15,\(\$0\+\),127 + bc0: 05 ff 7f 40 lbcpa \$c15,\(\$0\+\),127 + bc4: 05 ff 7f 08 sbcpm0 \$c15,\(\$0\+\),127 + bc8: 05 ff 7f 48 lbcpm0 \$c15,\(\$0\+\),127 + bcc: 05 ff 7f 0c sbcpm1 \$c15,\(\$0\+\),127 + bd0: 05 ff 7f 4c lbcpm1 \$c15,\(\$0\+\),127 + bd4: f5 f0 7f 00 sbcpa \$c0,\(\$sp\+\),127 + bd8: f5 f0 7f 40 lbcpa \$c0,\(\$sp\+\),127 + bdc: f5 f0 7f 08 sbcpm0 \$c0,\(\$sp\+\),127 + be0: f5 f0 7f 48 lbcpm0 \$c0,\(\$sp\+\),127 + be4: f5 f0 7f 0c sbcpm1 \$c0,\(\$sp\+\),127 + be8: f5 f0 7f 4c lbcpm1 \$c0,\(\$sp\+\),127 + bec: f5 ff 7f 00 sbcpa \$c15,\(\$sp\+\),127 + bf0: f5 ff 7f 40 lbcpa \$c15,\(\$sp\+\),127 + bf4: f5 ff 7f 08 sbcpm0 \$c15,\(\$sp\+\),127 + bf8: f5 ff 7f 48 lbcpm0 \$c15,\(\$sp\+\),127 + bfc: f5 ff 7f 0c sbcpm1 \$c15,\(\$sp\+\),127 + c00: f5 ff 7f 4c lbcpm1 \$c15,\(\$sp\+\),127 + c04: 05 f0 80 10 shcpa \$c0,\(\$0\+\),-128 + c08: 05 f0 80 50 lhcpa \$c0,\(\$0\+\),-128 + c0c: 05 f0 80 18 shcpm0 \$c0,\(\$0\+\),-128 + c10: 05 f0 80 58 lhcpm0 \$c0,\(\$0\+\),-128 + c14: 05 f0 80 1c shcpm1 \$c0,\(\$0\+\),-128 + c18: 05 f0 80 5c lhcpm1 \$c0,\(\$0\+\),-128 + c1c: 05 ff 80 10 shcpa \$c15,\(\$0\+\),-128 + c20: 05 ff 80 50 lhcpa \$c15,\(\$0\+\),-128 + c24: 05 ff 80 18 shcpm0 \$c15,\(\$0\+\),-128 + c28: 05 ff 80 58 lhcpm0 \$c15,\(\$0\+\),-128 + c2c: 05 ff 80 1c shcpm1 \$c15,\(\$0\+\),-128 + c30: 05 ff 80 5c lhcpm1 \$c15,\(\$0\+\),-128 + c34: f5 f0 80 10 shcpa \$c0,\(\$sp\+\),-128 + c38: f5 f0 80 50 lhcpa \$c0,\(\$sp\+\),-128 + c3c: f5 f0 80 18 shcpm0 \$c0,\(\$sp\+\),-128 + c40: f5 f0 80 58 lhcpm0 \$c0,\(\$sp\+\),-128 + c44: f5 f0 80 1c shcpm1 \$c0,\(\$sp\+\),-128 + c48: f5 f0 80 5c lhcpm1 \$c0,\(\$sp\+\),-128 + c4c: f5 ff 80 10 shcpa \$c15,\(\$sp\+\),-128 + c50: f5 ff 80 50 lhcpa \$c15,\(\$sp\+\),-128 + c54: f5 ff 80 18 shcpm0 \$c15,\(\$sp\+\),-128 + c58: f5 ff 80 58 lhcpm0 \$c15,\(\$sp\+\),-128 + c5c: f5 ff 80 1c shcpm1 \$c15,\(\$sp\+\),-128 + c60: f5 ff 80 5c lhcpm1 \$c15,\(\$sp\+\),-128 + c64: 05 f0 7e 10 shcpa \$c0,\(\$0\+\),126 + c68: 05 f0 7e 50 lhcpa \$c0,\(\$0\+\),126 + c6c: 05 f0 7e 18 shcpm0 \$c0,\(\$0\+\),126 + c70: 05 f0 7e 58 lhcpm0 \$c0,\(\$0\+\),126 + c74: 05 f0 7e 1c shcpm1 \$c0,\(\$0\+\),126 + c78: 05 f0 7e 5c lhcpm1 \$c0,\(\$0\+\),126 + c7c: 05 ff 7e 10 shcpa \$c15,\(\$0\+\),126 + c80: 05 ff 7e 50 lhcpa \$c15,\(\$0\+\),126 + c84: 05 ff 7e 18 shcpm0 \$c15,\(\$0\+\),126 + c88: 05 ff 7e 58 lhcpm0 \$c15,\(\$0\+\),126 + c8c: 05 ff 7e 1c shcpm1 \$c15,\(\$0\+\),126 + c90: 05 ff 7e 5c lhcpm1 \$c15,\(\$0\+\),126 + c94: f5 f0 7e 10 shcpa \$c0,\(\$sp\+\),126 + c98: f5 f0 7e 50 lhcpa \$c0,\(\$sp\+\),126 + c9c: f5 f0 7e 18 shcpm0 \$c0,\(\$sp\+\),126 + ca0: f5 f0 7e 58 lhcpm0 \$c0,\(\$sp\+\),126 + ca4: f5 f0 7e 1c shcpm1 \$c0,\(\$sp\+\),126 + ca8: f5 f0 7e 5c lhcpm1 \$c0,\(\$sp\+\),126 + cac: f5 ff 7e 10 shcpa \$c15,\(\$sp\+\),126 + cb0: f5 ff 7e 50 lhcpa \$c15,\(\$sp\+\),126 + cb4: f5 ff 7e 18 shcpm0 \$c15,\(\$sp\+\),126 + cb8: f5 ff 7e 58 lhcpm0 \$c15,\(\$sp\+\),126 + cbc: f5 ff 7e 1c shcpm1 \$c15,\(\$sp\+\),126 + cc0: f5 ff 7e 5c lhcpm1 \$c15,\(\$sp\+\),126 + cc4: 05 f0 80 20 swcpa \$c0,\(\$0\+\),-128 + cc8: 05 f0 80 60 lwcpa \$c0,\(\$0\+\),-128 + ccc: 05 f0 80 28 swcpm0 \$c0,\(\$0\+\),-128 + cd0: 05 f0 80 68 lwcpm0 \$c0,\(\$0\+\),-128 + cd4: 05 f0 80 2c swcpm1 \$c0,\(\$0\+\),-128 + cd8: 05 f0 80 6c lwcpm1 \$c0,\(\$0\+\),-128 + cdc: 05 ff 80 20 swcpa \$c15,\(\$0\+\),-128 + ce0: 05 ff 80 60 lwcpa \$c15,\(\$0\+\),-128 + ce4: 05 ff 80 28 swcpm0 \$c15,\(\$0\+\),-128 + ce8: 05 ff 80 68 lwcpm0 \$c15,\(\$0\+\),-128 + cec: 05 ff 80 2c swcpm1 \$c15,\(\$0\+\),-128 + cf0: 05 ff 80 6c lwcpm1 \$c15,\(\$0\+\),-128 + cf4: f5 f0 80 20 swcpa \$c0,\(\$sp\+\),-128 + cf8: f5 f0 80 60 lwcpa \$c0,\(\$sp\+\),-128 + cfc: f5 f0 80 28 swcpm0 \$c0,\(\$sp\+\),-128 + d00: f5 f0 80 68 lwcpm0 \$c0,\(\$sp\+\),-128 + d04: f5 f0 80 2c swcpm1 \$c0,\(\$sp\+\),-128 + d08: f5 f0 80 6c lwcpm1 \$c0,\(\$sp\+\),-128 + d0c: f5 ff 80 20 swcpa \$c15,\(\$sp\+\),-128 + d10: f5 ff 80 60 lwcpa \$c15,\(\$sp\+\),-128 + d14: f5 ff 80 28 swcpm0 \$c15,\(\$sp\+\),-128 + d18: f5 ff 80 68 lwcpm0 \$c15,\(\$sp\+\),-128 + d1c: f5 ff 80 2c swcpm1 \$c15,\(\$sp\+\),-128 + d20: f5 ff 80 6c lwcpm1 \$c15,\(\$sp\+\),-128 + d24: 05 f0 7c 20 swcpa \$c0,\(\$0\+\),124 + d28: 05 f0 7c 60 lwcpa \$c0,\(\$0\+\),124 + d2c: 05 f0 7c 28 swcpm0 \$c0,\(\$0\+\),124 + d30: 05 f0 7c 68 lwcpm0 \$c0,\(\$0\+\),124 + d34: 05 f0 7c 2c swcpm1 \$c0,\(\$0\+\),124 + d38: 05 f0 7c 6c lwcpm1 \$c0,\(\$0\+\),124 + d3c: 05 ff 7c 20 swcpa \$c15,\(\$0\+\),124 + d40: 05 ff 7c 60 lwcpa \$c15,\(\$0\+\),124 + d44: 05 ff 7c 28 swcpm0 \$c15,\(\$0\+\),124 + d48: 05 ff 7c 68 lwcpm0 \$c15,\(\$0\+\),124 + d4c: 05 ff 7c 2c swcpm1 \$c15,\(\$0\+\),124 + d50: 05 ff 7c 6c lwcpm1 \$c15,\(\$0\+\),124 + d54: f5 f0 7c 20 swcpa \$c0,\(\$sp\+\),124 + d58: f5 f0 7c 60 lwcpa \$c0,\(\$sp\+\),124 + d5c: f5 f0 7c 28 swcpm0 \$c0,\(\$sp\+\),124 + d60: f5 f0 7c 68 lwcpm0 \$c0,\(\$sp\+\),124 + d64: f5 f0 7c 2c swcpm1 \$c0,\(\$sp\+\),124 + d68: f5 f0 7c 6c lwcpm1 \$c0,\(\$sp\+\),124 + d6c: f5 ff 7c 20 swcpa \$c15,\(\$sp\+\),124 + d70: f5 ff 7c 60 lwcpa \$c15,\(\$sp\+\),124 + d74: f5 ff 7c 28 swcpm0 \$c15,\(\$sp\+\),124 + d78: f5 ff 7c 68 lwcpm0 \$c15,\(\$sp\+\),124 + d7c: f5 ff 7c 2c swcpm1 \$c15,\(\$sp\+\),124 + d80: f5 ff 7c 6c lwcpm1 \$c15,\(\$sp\+\),124 + d84: 05 f0 80 30 smcpa \$c0,\(\$0\+\),-128 + d88: 05 f0 80 70 lmcpa \$c0,\(\$0\+\),-128 + d8c: 05 f0 80 38 smcpm0 \$c0,\(\$0\+\),-128 + d90: 05 f0 80 78 lmcpm0 \$c0,\(\$0\+\),-128 + d94: 05 f0 80 3c smcpm1 \$c0,\(\$0\+\),-128 + d98: 05 f0 80 7c lmcpm1 \$c0,\(\$0\+\),-128 + d9c: 05 ff 80 30 smcpa \$c15,\(\$0\+\),-128 + da0: 05 ff 80 70 lmcpa \$c15,\(\$0\+\),-128 + da4: 05 ff 80 38 smcpm0 \$c15,\(\$0\+\),-128 + da8: 05 ff 80 78 lmcpm0 \$c15,\(\$0\+\),-128 + dac: 05 ff 80 3c smcpm1 \$c15,\(\$0\+\),-128 + db0: 05 ff 80 7c lmcpm1 \$c15,\(\$0\+\),-128 + db4: f5 f0 80 30 smcpa \$c0,\(\$sp\+\),-128 + db8: f5 f0 80 70 lmcpa \$c0,\(\$sp\+\),-128 + dbc: f5 f0 80 38 smcpm0 \$c0,\(\$sp\+\),-128 + dc0: f5 f0 80 78 lmcpm0 \$c0,\(\$sp\+\),-128 + dc4: f5 f0 80 3c smcpm1 \$c0,\(\$sp\+\),-128 + dc8: f5 f0 80 7c lmcpm1 \$c0,\(\$sp\+\),-128 + dcc: f5 ff 80 30 smcpa \$c15,\(\$sp\+\),-128 + dd0: f5 ff 80 70 lmcpa \$c15,\(\$sp\+\),-128 + dd4: f5 ff 80 38 smcpm0 \$c15,\(\$sp\+\),-128 + dd8: f5 ff 80 78 lmcpm0 \$c15,\(\$sp\+\),-128 + ddc: f5 ff 80 3c smcpm1 \$c15,\(\$sp\+\),-128 + de0: f5 ff 80 7c lmcpm1 \$c15,\(\$sp\+\),-128 + de4: 05 f0 78 30 smcpa \$c0,\(\$0\+\),120 + de8: 05 f0 78 70 lmcpa \$c0,\(\$0\+\),120 + dec: 05 f0 78 38 smcpm0 \$c0,\(\$0\+\),120 + df0: 05 f0 78 78 lmcpm0 \$c0,\(\$0\+\),120 + df4: 05 f0 78 3c smcpm1 \$c0,\(\$0\+\),120 + df8: 05 f0 78 7c lmcpm1 \$c0,\(\$0\+\),120 + dfc: 05 ff 78 30 smcpa \$c15,\(\$0\+\),120 + e00: 05 ff 78 70 lmcpa \$c15,\(\$0\+\),120 + e04: 05 ff 78 38 smcpm0 \$c15,\(\$0\+\),120 + e08: 05 ff 78 78 lmcpm0 \$c15,\(\$0\+\),120 + e0c: 05 ff 78 3c smcpm1 \$c15,\(\$0\+\),120 + e10: 05 ff 78 7c lmcpm1 \$c15,\(\$0\+\),120 + e14: f5 f0 78 30 smcpa \$c0,\(\$sp\+\),120 + e18: f5 f0 78 70 lmcpa \$c0,\(\$sp\+\),120 + e1c: f5 f0 78 38 smcpm0 \$c0,\(\$sp\+\),120 + e20: f5 f0 78 78 lmcpm0 \$c0,\(\$sp\+\),120 + e24: f5 f0 78 3c smcpm1 \$c0,\(\$sp\+\),120 + e28: f5 f0 78 7c lmcpm1 \$c0,\(\$sp\+\),120 + e2c: f5 ff 78 30 smcpa \$c15,\(\$sp\+\),120 + e30: f5 ff 78 70 lmcpa \$c15,\(\$sp\+\),120 + e34: f5 ff 78 38 smcpm0 \$c15,\(\$sp\+\),120 + e38: f5 ff 78 78 lmcpm0 \$c15,\(\$sp\+\),120 + e3c: f5 ff 78 3c smcpm1 \$c15,\(\$sp\+\),120 + e40: f5 ff 78 7c lmcpm1 \$c15,\(\$sp\+\),120 + e44: 04 d8 02 80 bcpeq 0x0,0xffff0e48 + e48: 05 d8 02 80 bcpne 0x0,0xffff0e4c + e4c: 06 d8 02 80 bcpat 0x0,0xffff0e50 + e50: 07 d8 02 80 bcpaf 0x0,0xffff0e54 + e54: f4 d8 02 80 bcpeq 0xf,0xffff0e58 + e58: f5 d8 02 80 bcpne 0xf,0xffff0e5c + e5c: f6 d8 02 80 bcpat 0xf,0xffff0e60 + e60: f7 d8 02 80 bcpaf 0xf,0xffff0e64 + e64: 04 d8 ff 3f bcpeq 0x0,0x8e62 + e68: 05 d8 ff 3f bcpne 0x0,0x8e66 + e6c: 06 d8 ff 3f bcpat 0x0,0x8e6a + e70: 07 d8 ff 3f bcpaf 0x0,0x8e6e + e74: f4 d8 ff 3f bcpeq 0xf,0x8e72 + e78: f5 d8 ff 3f bcpne 0xf,0x8e76 + e7c: f6 d8 ff 3f bcpat 0xf,0x8e7a + e80: f7 d8 ff 3f bcpaf 0xf,0x8e7e + e84: 04 d8 00 00 bcpeq 0x0,0xe84 + e84: R_MEP_PCREL17A2 symbol + e88: 05 d8 00 00 bcpne 0x0,0xe88 + e88: R_MEP_PCREL17A2 symbol + e8c: 06 d8 00 00 bcpat 0x0,0xe8c + e8c: R_MEP_PCREL17A2 symbol + e90: 07 d8 00 00 bcpaf 0x0,0xe90 + e90: R_MEP_PCREL17A2 symbol + e94: f4 d8 00 00 bcpeq 0xf,0xe94 + e94: R_MEP_PCREL17A2 symbol + e98: f5 d8 00 00 bcpne 0xf,0xe98 + e98: R_MEP_PCREL17A2 symbol + e9c: f6 d8 00 00 bcpat 0xf,0xe9c + e9c: R_MEP_PCREL17A2 symbol + ea0: f7 d8 00 00 bcpaf 0xf,0xea0 + ea0: R_MEP_PCREL17A2 symbol + ea4: 21 70 synccp + ea6: 0f 18 jsrv \$0 + ea8: ff 18 jsrv \$sp + eaa: 2b d8 00 80 bsrv 0xff800eae + eae: fb df ff 7f bsrv 0x800eac + eb2: 0b d8 00 00 bsrv 0xeb2 + eb2: R_MEP_PCREL24A2 symbol + eb6: 00 00 nop + eb6: R_MEP_8 symbol + eb7: R_MEP_16 symbol + eb8: 00 00 nop + eb9: R_MEP_32 symbol + eba: 00 00 nop +.* diff --git a/gas/testsuite/gas/mep/dj1.s b/gas/testsuite/gas/mep/dj1.s new file mode 100644 index 000000000000..e281cb8fa9b1 --- /dev/null +++ b/gas/testsuite/gas/mep/dj1.s @@ -0,0 +1,1306 @@ + + mov $0,$0 + mov $1,$0 + mov $2,$0 + mov $3,$0 + mov $4,$0 + mov $5,$0 + mov $6,$0 + mov $7,$0 + mov $8,$0 + mov $9,$0 + mov $10,$0 + mov $11,$0 + mov $12,$0 + mov $13,$0 + mov $14,$0 + mov $15,$0 + + mov $fp,$0 + mov $tp,$0 + mov $gp,$0 + mov $sp,$0 + + + sb $0,($0) + sh $0,($0) + sw $0,($0) + lb $0,($0) + lh $0,($0) + lw $0,($0) + lbu $0,($0) + lhu $0,($0) + sb $15,($0) + sh $15,($0) + sw $15,($0) + lb $15,($0) + lh $15,($0) + lw $15,($0) + lbu $15,($0) + lhu $15,($0) + sb $0,($15) + sh $0,($15) + sw $0,($15) + lb $0,($15) + lh $0,($15) + lw $0,($15) + lbu $0,($15) + lhu $0,($15) + sb $15,($15) + sh $15,($15) + sw $15,($15) + lb $15,($15) + lh $15,($15) + lw $15,($15) + lbu $15,($15) + lhu $15,($15) + + sw $0,0($sp) + lw $0,0($sp) + sw $15,0($sp) + lw $15,0($sp) + sw $0,124($sp) + lw $0,124($sp) + sw $15,124($sp) + lw $15,124($sp) + sw $0,0($15) + lw $0,0($15) + sw $15,0($15) + lw $15,0($15) + sw $0,124($15) + lw $0,124($15) + sw $15,124($15) + lw $15,124($15) + + sb $0,0($tp) + lb $0,0($tp) + lbu $0,0($tp) + sb $7,0($tp) + lb $7,0($tp) + lbu $7,0($tp) + sb $0,127($tp) + lb $0,127($tp) + lbu $0,127($tp) + sb $7,127($tp) + lb $7,127($tp) + lbu $7,127($tp) + sb $0,%tpoff(symbol)($tp) + lb $0,%tpoff(symbol)($tp) + lbu $0,%tpoff(symbol)($tp) + sb $7,%tpoff(symbol)($tp) + lb $7,%tpoff(symbol)($tp) + lbu $7,%tpoff(symbol)($tp) + sb $0,0($13) + lb $0,0($13) + lbu $0,0($13) + sb $7,0($13) + lb $7,0($13) + lbu $7,0($13) + sb $0,127($13) + lb $0,127($13) + lbu $0,127($13) + sb $7,127($13) + lb $7,127($13) + lbu $7,127($13) + sb $0,%tpoff(symbol)($13) + lb $0,%tpoff(symbol)($13) + lbu $0,%tpoff(symbol)($13) + sb $7,%tpoff(symbol)($13) + lb $7,%tpoff(symbol)($13) + lbu $7,%tpoff(symbol)($13) + + sh $0,0($tp) + lh $0,0($tp) + lhu $0,0($tp) + sh $7,0($tp) + lh $7,0($tp) + lhu $7,0($tp) + sh $0,126($tp) + lh $0,126($tp) + lhu $0,126($tp) + sh $7,126($tp) + lh $7,126($tp) + lhu $7,126($tp) + sh $0,%tpoff(symbol)($tp) + lh $0,%tpoff(symbol)($tp) + lhu $0,%tpoff(symbol)($tp) + sh $7,%tpoff(symbol)($tp) + lh $7,%tpoff(symbol)($tp) + lhu $7,%tpoff(symbol)($tp) + sh $0,0($13) + lh $0,0($13) + lhu $0,0($13) + sh $7,0($13) + lh $7,0($13) + lhu $7,0($13) + sh $0,126($13) + lh $0,126($13) + lhu $0,126($13) + sh $7,126($13) + lh $7,126($13) + lhu $7,126($13) + sh $0,%tpoff(symbol)($13) + lh $0,%tpoff(symbol)($13) + lhu $0,%tpoff(symbol)($13) + sh $7,%tpoff(symbol)($13) + lh $7,%tpoff(symbol)($13) + lhu $7,%tpoff(symbol)($13) + + sw $0,0($tp) + lw $0,0($tp) + sw $7,0($tp) + lw $7,0($tp) + sw $0,124($tp) + lw $0,124($tp) + sw $7,124($tp) + lw $7,124($tp) + sw $0,%tpoff(symbol)($tp) + lw $0,%tpoff(symbol)($tp) + sw $7,%tpoff(symbol)($tp) + lw $7,%tpoff(symbol)($tp) + sw $0,0($13) + lw $0,0($13) + sw $7,0($13) + lw $7,0($13) + sw $0,124($13) + lw $0,124($13) + sw $7,124($13) + lw $7,124($13) + sw $0,%tpoff(symbol)($13) + lw $0,%tpoff(symbol)($13) + sw $7,%tpoff(symbol)($13) + lw $7,%tpoff(symbol)($13) + + sb $0,-32768($0) + sh $0,-32768($0) + sw $0,-32768($0) + lb $0,-32768($0) + lh $0,-32768($0) + lw $0,-32768($0) + lbu $0,-32768($0) + lhu $0,-32768($0) + sb $15,-32768($0) + sh $15,-32768($0) + sw $15,-32768($0) + lb $15,-32768($0) + lh $15,-32768($0) + lw $15,-32768($0) + lbu $15,-32768($0) + lhu $15,-32768($0) + sb $0,32767($0) + sh $0,32767($0) + sw $0,32767($0) + lb $0,32767($0) + lh $0,32767($0) + lw $0,32767($0) + lbu $0,32767($0) + lhu $0,32767($0) + sb $15,32767($0) + sh $15,32767($0) + sw $15,32767($0) + lb $15,32767($0) + lh $15,32767($0) + lw $15,32767($0) + lbu $15,32767($0) + lhu $15,32767($0) + sb $0,%sdaoff(symbol)($0) + sh $0,%sdaoff(symbol)($0) + sw $0,%sdaoff(symbol)($0) + lb $0,%sdaoff(symbol)($0) + lh $0,%sdaoff(symbol)($0) + lw $0,%sdaoff(symbol)($0) + lbu $0,%sdaoff(symbol)($0) + lhu $0,%sdaoff(symbol)($0) + sb $15,%sdaoff(symbol)($0) + sh $15,%sdaoff(symbol)($0) + sw $15,%sdaoff(symbol)($0) + lb $15,%sdaoff(symbol)($0) + lh $15,%sdaoff(symbol)($0) + lw $15,%sdaoff(symbol)($0) + lbu $15,%sdaoff(symbol)($0) + lhu $15,%sdaoff(symbol)($0) + sb $0,-32768($0) + sh $0,-32768($0) + sw $0,-32768($0) + lb $0,-32768($0) + lh $0,-32768($0) + lw $0,-32768($0) + lbu $0,-32768($0) + lhu $0,-32768($0) + sb $15,-32768($0) + sh $15,-32768($0) + sw $15,-32768($0) + lb $15,-32768($0) + lh $15,-32768($0) + lw $15,-32768($0) + lbu $15,-32768($0) + lhu $15,-32768($0) + sb $0,32767($0) + sh $0,32767($0) + sw $0,32767($0) + lb $0,32767($0) + lh $0,32767($0) + lw $0,32767($0) + lbu $0,32767($0) + lhu $0,32767($0) + sb $15,32767($0) + sh $15,32767($0) + sw $15,32767($0) + lb $15,32767($0) + lh $15,32767($0) + lw $15,32767($0) + lbu $15,32767($0) + lhu $15,32767($0) + sb $0,%tpoff(symbol)($0) + sh $0,%tpoff(symbol)($0) + sw $0,%tpoff(symbol)($0) + lb $0,%tpoff(symbol)($0) + lh $0,%tpoff(symbol)($0) + lw $0,%tpoff(symbol)($0) + lbu $0,%tpoff(symbol)($0) + lhu $0,%tpoff(symbol)($0) + sb $15,%tpoff(symbol)($0) + sh $15,%tpoff(symbol)($0) + sw $15,%tpoff(symbol)($0) + lb $15,%tpoff(symbol)($0) + lh $15,%tpoff(symbol)($0) + lw $15,%tpoff(symbol)($0) + lbu $15,%tpoff(symbol)($0) + lhu $15,%tpoff(symbol)($0) + sb $0,-32768($15) + sh $0,-32768($15) + sw $0,-32768($15) + lb $0,-32768($15) + lh $0,-32768($15) + lw $0,-32768($15) + lbu $0,-32768($15) + lhu $0,-32768($15) + sb $15,-32768($15) + sh $15,-32768($15) + sw $15,-32768($15) + lb $15,-32768($15) + lh $15,-32768($15) + lw $15,-32768($15) + lbu $15,-32768($15) + lhu $15,-32768($15) + sb $0,32767($15) + sh $0,32767($15) + sw $0,32767($15) + lb $0,32767($15) + lh $0,32767($15) + lw $0,32767($15) + lbu $0,32767($15) + lhu $0,32767($15) + sb $15,32767($15) + sh $15,32767($15) + sw $15,32767($15) + lb $15,32767($15) + lh $15,32767($15) + lw $15,32767($15) + lbu $15,32767($15) + lhu $15,32767($15) + sb $0,%sdaoff(symbol)($15) + sh $0,%sdaoff(symbol)($15) + sw $0,%sdaoff(symbol)($15) + lb $0,%sdaoff(symbol)($15) + lh $0,%sdaoff(symbol)($15) + lw $0,%sdaoff(symbol)($15) + lbu $0,%sdaoff(symbol)($15) + lhu $0,%sdaoff(symbol)($15) + sb $15,%sdaoff(symbol)($15) + sh $15,%sdaoff(symbol)($15) + sw $15,%sdaoff(symbol)($15) + lb $15,%sdaoff(symbol)($15) + lh $15,%sdaoff(symbol)($15) + lw $15,%sdaoff(symbol)($15) + lbu $15,%sdaoff(symbol)($15) + lhu $15,%sdaoff(symbol)($15) + sb $0,-32768($15) + sh $0,-32768($15) + sw $0,-32768($15) + lb $0,-32768($15) + lh $0,-32768($15) + lw $0,-32768($15) + lbu $0,-32768($15) + lhu $0,-32768($15) + sb $15,-32768($15) + sh $15,-32768($15) + sw $15,-32768($15) + lb $15,-32768($15) + lh $15,-32768($15) + lw $15,-32768($15) + lbu $15,-32768($15) + lhu $15,-32768($15) + sb $0,32767($15) + sh $0,32767($15) + sw $0,32767($15) + lb $0,32767($15) + lh $0,32767($15) + lw $0,32767($15) + lbu $0,32767($15) + lhu $0,32767($15) + sb $15,32767($15) + sh $15,32767($15) + sw $15,32767($15) + lb $15,32767($15) + lh $15,32767($15) + lw $15,32767($15) + lbu $15,32767($15) + lhu $15,32767($15) + sb $0,%tpoff(symbol)($15) + sh $0,%tpoff(symbol)($15) + sw $0,%tpoff(symbol)($15) + lb $0,%tpoff(symbol)($15) + lh $0,%tpoff(symbol)($15) + lw $0,%tpoff(symbol)($15) + lbu $0,%tpoff(symbol)($15) + lhu $0,%tpoff(symbol)($15) + sb $15,%tpoff(symbol)($15) + sh $15,%tpoff(symbol)($15) + sw $15,%tpoff(symbol)($15) + lb $15,%tpoff(symbol)($15) + lh $15,%tpoff(symbol)($15) + lw $15,%tpoff(symbol)($15) + lbu $15,%tpoff(symbol)($15) + lhu $15,%tpoff(symbol)($15) + + sw $0,(0) + lw $0,(0) + sw $15,(0) + lw $15,(0) + sw $0,(0xfffffc) + lw $0,(0xfffffc) + sw $15,(0xfffffc) + lw $15,(0xfffffc) + sw $0,(symbol) + lw $0,(symbol) + sw $15,(symbol) + lw $15,(symbol) + + + extb $0 + extub $0 + exth $0 + extuh $0 + extb $15 + extub $15 + exth $15 + extuh $15 + + + ssarb 0($0) + ssarb 3($0) + ssarb 0($15) + ssarb 3($15) + + + mov $0,$0 + mov $15,$0 + mov $0,$15 + mov $15,$15 + mov $0,-32768 + mov $15,-32768 + mov $0,-128 + mov $15,-128 + mov $0,0 + mov $15,0 + mov $0,127 + mov $15,127 + mov $0,32767 + mov $15,32767 + + mov $0,%lo(symbol) + mov $0,%hi(symbol) + mov $0,%uhi(symbol) + mov $0,%sdaoff(symbol) + mov $0,%tpoff(symbol) + + movu $0,0 + movu $7,0 + movu $0,0xffffff + movu $7,0xffffff + movu $0,%lo(symbol) + movu $7,%lo(symbol) + movu $0,symbol + movu $7,symbol + + movu $0,0 + movh $0,0 + movu $15,0 + movh $15,0 + movu $0,0xffff + movh $0,0xffff + movu $15,0xffff + movh $15,0xffff + + movu $0,%lo(symbol) + movh $0,%lo(symbol) + movu $15,%lo(symbol) + movh $15,%lo(symbol) + movu $0,%hi(symbol) + movh $0,%hi(symbol) + movu $15,%hi(symbol) + movh $15,%hi(symbol) + movu $0,%uhi(symbol) + movh $0,%uhi(symbol) + movu $15,%uhi(symbol) + movh $15,%uhi(symbol) + movu $0,%lo(0x12345678) + movh $0,%lo(0x12345678) + movu $15,%lo(0x12345678) + movh $15,%lo(0x12345678) + movu $0,%hi(0x12345678) + movh $0,%hi(0x12345678) + movu $15,%hi(0x12345678) + movh $15,%hi(0x12345678) + movu $0,%uhi(0x12345678) + movh $0,%uhi(0x12345678) + movu $15,%uhi(0x12345678) + movh $15,%uhi(0x12345678) + + + add3 $0,$0,$0 + add3 $15,$0,$0 + add3 $0,$15,$0 + add3 $15,$15,$0 + add3 $0,$0,$15 + add3 $15,$0,$15 + add3 $0,$15,$15 + add3 $15,$15,$15 + + add $0,-16 + add $15,-16 + add $0,0 + add $15,0 + add $0,15 + add $15,15 + + add3 $0,$sp,0 + add3 $15,$sp,0 + add3 $0,$sp,124 + add3 $15,$sp,124 + add3 $0,$sp,1 + add3 $15,$sp,1 + + advck3 $0,$0,$0 + sbvck3 $0,$0,$0 + advck3 $0,$15,$0 + sbvck3 $0,$15,$0 + advck3 $0,$0,$15 + sbvck3 $0,$0,$15 + advck3 $0,$15,$15 + sbvck3 $0,$15,$15 + + sub $0,$0 + neg $0,$0 + sub $15,$0 + neg $15,$0 + sub $0,$15 + neg $0,$15 + sub $15,$15 + neg $15,$15 + + slt3 $0,$0,$0 + sltu3 $0,$0,$0 + sl1ad3 $0,$0,$0 + sl2ad3 $0,$0,$0 + slt3 $0,$15,$0 + sltu3 $0,$15,$0 + sl1ad3 $0,$15,$0 + sl2ad3 $0,$15,$0 + slt3 $0,$0,$15 + sltu3 $0,$0,$15 + sl1ad3 $0,$0,$15 + sl2ad3 $0,$0,$15 + slt3 $0,$15,$15 + sltu3 $0,$15,$15 + sl1ad3 $0,$15,$15 + sl2ad3 $0,$15,$15 + + add3 $0,$0,-32768 + add3 $15,$0,-32768 + add3 $0,$15,-32768 + add3 $15,$15,-32768 + add3 $0,$0,32767 + add3 $15,$0,32767 + add3 $0,$15,32767 + add3 $15,$15,32767 + add3 $0,$0,%lo(symbol) + add3 $15,$0,%lo(symbol) + add3 $0,$15,%lo(symbol) + add3 $15,$15,%lo(symbol) + + slt3 $0,$0,0 + sltu3 $0,$0,0 + slt3 $0,$15,0 + sltu3 $0,$15,0 + slt3 $0,$0,31 + sltu3 $0,$0,31 + slt3 $0,$15,31 + sltu3 $0,$15,31 + + + or $0,$0 + and $0,$0 + xor $0,$0 + nor $0,$0 + or $15,$0 + and $15,$0 + xor $15,$0 + nor $15,$0 + or $0,$15 + and $0,$15 + xor $0,$15 + nor $0,$15 + or $15,$15 + and $15,$15 + xor $15,$15 + nor $15,$15 + + or3 $0,$0,0 + and3 $0,$0,0 + xor3 $0,$0,0 + or3 $15,$0,0 + and3 $15,$0,0 + xor3 $15,$0,0 + or3 $0,$15,0 + and3 $0,$15,0 + xor3 $0,$15,0 + or3 $15,$15,0 + and3 $15,$15,0 + xor3 $15,$15,0 + or3 $0,$0,65535 + and3 $0,$0,65535 + xor3 $0,$0,65535 + or3 $15,$0,65535 + and3 $15,$0,65535 + xor3 $15,$0,65535 + or3 $0,$15,65535 + and3 $0,$15,65535 + xor3 $0,$15,65535 + or3 $15,$15,65535 + and3 $15,$15,65535 + xor3 $15,$15,65535 + or3 $0,$0,%lo(symbol) + and3 $0,$0,%lo(symbol) + xor3 $0,$0,%lo(symbol) + or3 $15,$0,%lo(symbol) + and3 $15,$0,%lo(symbol) + xor3 $15,$0,%lo(symbol) + or3 $0,$15,%lo(symbol) + and3 $0,$15,%lo(symbol) + xor3 $0,$15,%lo(symbol) + or3 $15,$15,%lo(symbol) + and3 $15,$15,%lo(symbol) + xor3 $15,$15,%lo(symbol) + + + sra $0,$0 + srl $0,$0 + sll $0,$0 + fsft $0,$0 + sra $15,$0 + srl $15,$0 + sll $15,$0 + fsft $15,$0 + sra $0,$15 + srl $0,$15 + sll $0,$15 + fsft $0,$15 + sra $15,$15 + srl $15,$15 + sll $15,$15 + fsft $15,$15 + + sra $0,0 + srl $0,0 + sll $0,0 + sra $15,0 + srl $15,0 + sll $15,0 + sra $0,31 + srl $0,31 + sll $0,31 + sra $15,31 + srl $15,31 + sll $15,31 + + sll3 $0,$0,0 + sll3 $0,$15,0 + sll3 $0,$0,31 + sll3 $0,$15,31 + + + bra .-2048+2 + bra .+2046+2 + bra symbol + + beqz $0,.-128+2 + bnez $0,.-128+2 + beqz $15,.-128+2 + bnez $15,.-128+2 + beqz $0,.+126+2 + bnez $0,.+126+2 + beqz $15,.+126+2 + bnez $15,.+126+2 + beqz $0,symbol + bnez $0,symbol + beqz $15,symbol + bnez $15,symbol + + beqi $0,0,.-65536+4 + bnei $0,0,.-65536+4 + blti $0,0,.-65536+4 + bgei $0,0,.-65536+4 + beqi $15,0,.-65536+4 + bnei $15,0,.-65536+4 + blti $15,0,.-65536+4 + bgei $15,0,.-65536+4 + beqi $0,15,.-65536+4 + bnei $0,15,.-65536+4 + blti $0,15,.-65536+4 + bgei $0,15,.-65536+4 + beqi $15,15,.-65536+4 + bnei $15,15,.-65536+4 + blti $15,15,.-65536+4 + bgei $15,15,.-65536+4 + beqi $0,0,.+32763+4 + bnei $0,0,.+32763+4 + blti $0,0,.+32763+4 + bgei $0,0,.+32763+4 + beqi $15,0,.+32763+4 + bnei $15,0,.+32763+4 + blti $15,0,.+32763+4 + bgei $15,0,.+32763+4 + beqi $0,15,.+32763+4 + bnei $0,15,.+32763+4 + blti $0,15,.+32763+4 + bgei $0,15,.+32763+4 + beqi $15,15,.+32763+4 + bnei $15,15,.+32763+4 + blti $15,15,.+32763+4 + bgei $15,15,.+32763+4 + beqi $0,0,symbol + bnei $0,0,symbol + blti $0,0,symbol + bgei $0,0,symbol + beqi $15,0,symbol + bnei $15,0,symbol + blti $15,0,symbol + bgei $15,0,symbol + beqi $0,15,symbol + bnei $0,15,symbol + blti $0,15,symbol + bgei $0,15,symbol + beqi $15,15,symbol + bnei $15,15,symbol + blti $15,15,symbol + bgei $15,15,symbol + + beq $0,$0,.-65536+4 + bne $0,$0,.-65536+4 + beq $15,$0,.-65536+4 + bne $15,$0,.-65536+4 + beq $0,$15,.-65536+4 + bne $0,$15,.-65536+4 + beq $15,$15,.-65536+4 + bne $15,$15,.-65536+4 + beq $0,$0,.+32763+4 + bne $0,$0,.+32763+4 + beq $15,$0,.+32763+4 + bne $15,$0,.+32763+4 + beq $0,$15,.+32763+4 + bne $0,$15,.+32763+4 + beq $15,$15,.+32763+4 + bne $15,$15,.+32763+4 + beq $0,$0,symbol + bne $0,$0,symbol + beq $15,$0,symbol + bne $15,$0,symbol + beq $0,$15,symbol + bne $0,$15,symbol + beq $15,$15,symbol + bne $15,$15,symbol + + bsr .-0x800000+4 + bsr .-2048+2 + bsr .+2046+2 + bsr .+0x7ffffe+4 + bsr symbol + + jmp $0 + jmp $15 + jmp 0 + jmp 0xfffffe + jmp symbol + + jsr $0 + jsr $15 + + ret + + repeat $0,.-65536+4 + repeat $15,.-65536+4 + repeat $0,.+32763+4 + repeat $15,.+32763+4 + repeat $0,symbol + repeat $15,symbol + + erepeat .-65536+4 + erepeat .+32763+4 + erepeat symbol + + + stc $0,$pc + ldc $0,$pc + stc $15,$pc + ldc $15,$pc + stc $0,$lp + ldc $0,$lp + stc $15,$lp + ldc $15,$lp + stc $0,$sar + ldc $0,$sar + stc $15,$sar + ldc $15,$sar + stc $0,$rpb + ldc $0,$rpb + stc $15,$rpb + ldc $15,$rpb + stc $0,$rpe + ldc $0,$rpe + stc $15,$rpe + ldc $15,$rpe + stc $0,$rpc + ldc $0,$rpc + stc $15,$rpc + ldc $15,$rpc + stc $0,$hi + ldc $0,$hi + stc $15,$hi + ldc $15,$hi + stc $0,$lo + ldc $0,$lo + stc $15,$lo + ldc $15,$lo + stc $0,$mb0 + ldc $0,$mb0 + stc $15,$mb0 + ldc $15,$mb0 + stc $0,$me0 + ldc $0,$me0 + stc $15,$me0 + ldc $15,$me0 + stc $0,$mb1 + ldc $0,$mb1 + stc $15,$mb1 + ldc $15,$mb1 + stc $0,$me1 + ldc $0,$me1 + stc $15,$me1 + ldc $15,$me1 + + stc $0,$psw + ldc $0,$psw + stc $15,$psw + ldc $15,$psw + stc $0,$id + ldc $0,$id + stc $15,$id + ldc $15,$id + stc $0,$tmp + ldc $0,$tmp + stc $15,$tmp + ldc $15,$tmp + stc $0,$epc + ldc $0,$epc + stc $15,$epc + ldc $15,$epc + stc $0,$exc + ldc $0,$exc + stc $15,$exc + ldc $15,$exc + stc $0,$cfg + ldc $0,$cfg + stc $15,$cfg + ldc $15,$cfg + stc $0,$npc + ldc $0,$npc + stc $15,$npc + ldc $15,$npc + stc $0,$dbg + ldc $0,$dbg + stc $15,$dbg + ldc $15,$dbg + stc $0,$depc + ldc $0,$depc + stc $15,$depc + ldc $15,$depc + stc $0,$opt + ldc $0,$opt + stc $15,$opt + ldc $15,$opt + stc $0,$rcfg + ldc $0,$rcfg + stc $15,$rcfg + ldc $15,$rcfg + stc $0,$ccfg + ldc $0,$ccfg + stc $15,$ccfg + ldc $15,$ccfg + + di + ei + reti + halt + break + syncm + + swi 0 + swi 3 + + stcb $0,0 + ldcb $0,0 + stcb $15,0 + ldcb $15,0 + stcb $0,65535 + ldcb $0,65535 + stcb $15,65535 + ldcb $15,65535 + stcb $0,symbol + ldcb $0,symbol + stcb $15,symbol + ldcb $15,symbol + + + bsetm ($0),0 + bclrm ($0),0 + bnotm ($0),0 + bsetm ($15),0 + bclrm ($15),0 + bnotm ($15),0 + bsetm ($0),7 + bclrm ($0),7 + bnotm ($0),7 + bsetm ($15),7 + bclrm ($15),7 + bnotm ($15),7 + + btstm $0,($0),0 + btstm $0,($15),0 + btstm $0,($0),7 + btstm $0,($15),7 + + tas $0,($0) + tas $15,($0) + tas $0,($15) + tas $15,($15) + + + cache 0,($0) + cache 3,($0) + cache 0,($15) + cache 3,($15) + + mul $0,$0 + madd $0,$0 + mulr $0,$0 + maddr $0,$0 + mulu $0,$0 + maddu $0,$0 + mulru $0,$0 + maddru $0,$0 + mul $15,$0 + madd $15,$0 + mulr $15,$0 + maddr $15,$0 + mulu $15,$0 + maddu $15,$0 + mulru $15,$0 + maddru $15,$0 + mul $0,$15 + madd $0,$15 + mulr $0,$15 + maddr $0,$15 + mulu $0,$15 + maddu $0,$15 + mulru $0,$15 + maddru $0,$15 + mul $15,$15 + madd $15,$15 + mulr $15,$15 + maddr $15,$15 + mulu $15,$15 + maddu $15,$15 + mulru $15,$15 + maddru $15,$15 + + div $0,$0 + divu $0,$0 + div $15,$0 + divu $15,$0 + div $0,$15 + divu $0,$15 + div $15,$15 + divu $15,$15 + + dret + dbreak + + ldz $0,$0 + abs $0,$0 + ave $0,$0 + ldz $15,$0 + abs $15,$0 + ave $15,$0 + ldz $0,$15 + abs $0,$15 + ave $0,$15 + ldz $15,$15 + abs $15,$15 + ave $15,$15 + + min $0,$0 + max $0,$0 + minu $0,$0 + maxu $0,$0 + min $15,$0 + max $15,$0 + minu $15,$0 + maxu $15,$0 + min $0,$15 + max $0,$15 + minu $0,$15 + maxu $0,$15 + min $15,$15 + max $15,$15 + minu $15,$15 + maxu $15,$15 + + clip $0,0 + clipu $0,0 + clip $15,0 + clipu $15,0 + clip $0,31 + clipu $0,31 + clip $15,31 + clipu $15,31 + + sadd $0,$0 + ssub $0,$0 + saddu $0,$0 + ssubu $0,$0 + sadd $15,$0 + ssub $15,$0 + saddu $15,$0 + ssubu $15,$0 + sadd $0,$15 + ssub $0,$15 + saddu $0,$15 + ssubu $0,$15 + sadd $15,$15 + ssub $15,$15 + saddu $15,$15 + ssubu $15,$15 + + swcp $c0,($0) + lwcp $c0,($0) + smcp $c0,($0) + lmcp $c0,($0) + swcp $c15,($0) + lwcp $c15,($0) + smcp $c15,($0) + lmcp $c15,($0) + swcp $c0,($15) + lwcp $c0,($15) + smcp $c0,($15) + lmcp $c0,($15) + swcp $c15,($15) + lwcp $c15,($15) + smcp $c15,($15) + lmcp $c15,($15) + + swcpi $c0,($0+) + lwcpi $c0,($0+) + smcpi $c0,($0+) + lmcpi $c0,($0+) + swcpi $c15,($0+) + lwcpi $c15,($0+) + smcpi $c15,($0+) + lmcpi $c15,($0+) + swcpi $c0,($15+) + lwcpi $c0,($15+) + smcpi $c0,($15+) + lmcpi $c0,($15+) + swcpi $c15,($15+) + lwcpi $c15,($15+) + smcpi $c15,($15+) + lmcpi $c15,($15+) + + sbcpa $c0,($0+),-128 + lbcpa $c0,($0+),-128 + sbcpm0 $c0,($0+),-128 + lbcpm0 $c0,($0+),-128 + sbcpm1 $c0,($0+),-128 + lbcpm1 $c0,($0+),-128 + sbcpa $c15,($0+),-128 + lbcpa $c15,($0+),-128 + sbcpm0 $c15,($0+),-128 + lbcpm0 $c15,($0+),-128 + sbcpm1 $c15,($0+),-128 + lbcpm1 $c15,($0+),-128 + sbcpa $c0,($15+),-128 + lbcpa $c0,($15+),-128 + sbcpm0 $c0,($15+),-128 + lbcpm0 $c0,($15+),-128 + sbcpm1 $c0,($15+),-128 + lbcpm1 $c0,($15+),-128 + sbcpa $c15,($15+),-128 + lbcpa $c15,($15+),-128 + sbcpm0 $c15,($15+),-128 + lbcpm0 $c15,($15+),-128 + sbcpm1 $c15,($15+),-128 + lbcpm1 $c15,($15+),-128 + sbcpa $c0,($0+),127 + lbcpa $c0,($0+),127 + sbcpm0 $c0,($0+),127 + lbcpm0 $c0,($0+),127 + sbcpm1 $c0,($0+),127 + lbcpm1 $c0,($0+),127 + sbcpa $c15,($0+),127 + lbcpa $c15,($0+),127 + sbcpm0 $c15,($0+),127 + lbcpm0 $c15,($0+),127 + sbcpm1 $c15,($0+),127 + lbcpm1 $c15,($0+),127 + sbcpa $c0,($15+),127 + lbcpa $c0,($15+),127 + sbcpm0 $c0,($15+),127 + lbcpm0 $c0,($15+),127 + sbcpm1 $c0,($15+),127 + lbcpm1 $c0,($15+),127 + sbcpa $c15,($15+),127 + lbcpa $c15,($15+),127 + sbcpm0 $c15,($15+),127 + lbcpm0 $c15,($15+),127 + sbcpm1 $c15,($15+),127 + lbcpm1 $c15,($15+),127 + + shcpa $c0,($0+),-128 + lhcpa $c0,($0+),-128 + shcpm0 $c0,($0+),-128 + lhcpm0 $c0,($0+),-128 + shcpm1 $c0,($0+),-128 + lhcpm1 $c0,($0+),-128 + shcpa $c15,($0+),-128 + lhcpa $c15,($0+),-128 + shcpm0 $c15,($0+),-128 + lhcpm0 $c15,($0+),-128 + shcpm1 $c15,($0+),-128 + lhcpm1 $c15,($0+),-128 + shcpa $c0,($15+),-128 + lhcpa $c0,($15+),-128 + shcpm0 $c0,($15+),-128 + lhcpm0 $c0,($15+),-128 + shcpm1 $c0,($15+),-128 + lhcpm1 $c0,($15+),-128 + shcpa $c15,($15+),-128 + lhcpa $c15,($15+),-128 + shcpm0 $c15,($15+),-128 + lhcpm0 $c15,($15+),-128 + shcpm1 $c15,($15+),-128 + lhcpm1 $c15,($15+),-128 + shcpa $c0,($0+),126 + lhcpa $c0,($0+),126 + shcpm0 $c0,($0+),126 + lhcpm0 $c0,($0+),126 + shcpm1 $c0,($0+),126 + lhcpm1 $c0,($0+),126 + shcpa $c15,($0+),126 + lhcpa $c15,($0+),126 + shcpm0 $c15,($0+),126 + lhcpm0 $c15,($0+),126 + shcpm1 $c15,($0+),126 + lhcpm1 $c15,($0+),126 + shcpa $c0,($15+),126 + lhcpa $c0,($15+),126 + shcpm0 $c0,($15+),126 + lhcpm0 $c0,($15+),126 + shcpm1 $c0,($15+),126 + lhcpm1 $c0,($15+),126 + shcpa $c15,($15+),126 + lhcpa $c15,($15+),126 + shcpm0 $c15,($15+),126 + lhcpm0 $c15,($15+),126 + shcpm1 $c15,($15+),126 + lhcpm1 $c15,($15+),126 + + swcpa $c0,($0+),-128 + lwcpa $c0,($0+),-128 + swcpm0 $c0,($0+),-128 + lwcpm0 $c0,($0+),-128 + swcpm1 $c0,($0+),-128 + lwcpm1 $c0,($0+),-128 + swcpa $c15,($0+),-128 + lwcpa $c15,($0+),-128 + swcpm0 $c15,($0+),-128 + lwcpm0 $c15,($0+),-128 + swcpm1 $c15,($0+),-128 + lwcpm1 $c15,($0+),-128 + swcpa $c0,($15+),-128 + lwcpa $c0,($15+),-128 + swcpm0 $c0,($15+),-128 + lwcpm0 $c0,($15+),-128 + swcpm1 $c0,($15+),-128 + lwcpm1 $c0,($15+),-128 + swcpa $c15,($15+),-128 + lwcpa $c15,($15+),-128 + swcpm0 $c15,($15+),-128 + lwcpm0 $c15,($15+),-128 + swcpm1 $c15,($15+),-128 + lwcpm1 $c15,($15+),-128 + swcpa $c0,($0+),124 + lwcpa $c0,($0+),124 + swcpm0 $c0,($0+),124 + lwcpm0 $c0,($0+),124 + swcpm1 $c0,($0+),124 + lwcpm1 $c0,($0+),124 + swcpa $c15,($0+),124 + lwcpa $c15,($0+),124 + swcpm0 $c15,($0+),124 + lwcpm0 $c15,($0+),124 + swcpm1 $c15,($0+),124 + lwcpm1 $c15,($0+),124 + swcpa $c0,($15+),124 + lwcpa $c0,($15+),124 + swcpm0 $c0,($15+),124 + lwcpm0 $c0,($15+),124 + swcpm1 $c0,($15+),124 + lwcpm1 $c0,($15+),124 + swcpa $c15,($15+),124 + lwcpa $c15,($15+),124 + swcpm0 $c15,($15+),124 + lwcpm0 $c15,($15+),124 + swcpm1 $c15,($15+),124 + lwcpm1 $c15,($15+),124 + + smcpa $c0,($0+),-128 + lmcpa $c0,($0+),-128 + smcpm0 $c0,($0+),-128 + lmcpm0 $c0,($0+),-128 + smcpm1 $c0,($0+),-128 + lmcpm1 $c0,($0+),-128 + smcpa $c15,($0+),-128 + lmcpa $c15,($0+),-128 + smcpm0 $c15,($0+),-128 + lmcpm0 $c15,($0+),-128 + smcpm1 $c15,($0+),-128 + lmcpm1 $c15,($0+),-128 + smcpa $c0,($15+),-128 + lmcpa $c0,($15+),-128 + smcpm0 $c0,($15+),-128 + lmcpm0 $c0,($15+),-128 + smcpm1 $c0,($15+),-128 + lmcpm1 $c0,($15+),-128 + smcpa $c15,($15+),-128 + lmcpa $c15,($15+),-128 + smcpm0 $c15,($15+),-128 + lmcpm0 $c15,($15+),-128 + smcpm1 $c15,($15+),-128 + lmcpm1 $c15,($15+),-128 + smcpa $c0,($0+),120 + lmcpa $c0,($0+),120 + smcpm0 $c0,($0+),120 + lmcpm0 $c0,($0+),120 + smcpm1 $c0,($0+),120 + lmcpm1 $c0,($0+),120 + smcpa $c15,($0+),120 + lmcpa $c15,($0+),120 + smcpm0 $c15,($0+),120 + lmcpm0 $c15,($0+),120 + smcpm1 $c15,($0+),120 + lmcpm1 $c15,($0+),120 + smcpa $c0,($15+),120 + lmcpa $c0,($15+),120 + smcpm0 $c0,($15+),120 + lmcpm0 $c0,($15+),120 + smcpm1 $c0,($15+),120 + lmcpm1 $c0,($15+),120 + smcpa $c15,($15+),120 + lmcpa $c15,($15+),120 + smcpm0 $c15,($15+),120 + lmcpm0 $c15,($15+),120 + smcpm1 $c15,($15+),120 + lmcpm1 $c15,($15+),120 + +/* + cmov $c0,$0 + cmov $c15,$0 + cmov $c0,$15 + cmov $c15,$15 + + cmov $0,$c0 + cmov $15,$c0 + cmov $0,$c15 + cmov $15,$c15 + + cmovc $ccr0,$0 + cmovc $ccr15,$0 + cmovc $ccr0,$15 + cmovc $ccr15,$15 + + cmovc $0,$ccr0 + cmovc $15,$ccr0 + cmovc $0,$ccr15 + cmovc $15,$ccr15 + + cmovh $c0,$0 + cmovh $c15,$0 + cmovh $c0,$15 + cmovh $c15,$15 + + cmovh $0,$c0 + cmovh $15,$c0 + cmovh $0,$c15 + cmovh $15,$c15 +*/ + bcpeq 0,.-65536+4 + bcpne 0,.-65536+4 + bcpat 0,.-65536+4 + bcpaf 0,.-65536+4 + bcpeq 15,.-65536+4 + bcpne 15,.-65536+4 + bcpat 15,.-65536+4 + bcpaf 15,.-65536+4 + bcpeq 0,.+32763+4 + bcpne 0,.+32763+4 + bcpat 0,.+32763+4 + bcpaf 0,.+32763+4 + bcpeq 15,.+32763+4 + bcpne 15,.+32763+4 + bcpat 15,.+32763+4 + bcpaf 15,.+32763+4 + bcpeq 0,symbol + bcpne 0,symbol + bcpat 0,symbol + bcpaf 0,symbol + bcpeq 15,symbol + bcpne 15,symbol + bcpat 15,symbol + bcpaf 15,symbol + + synccp + + jsrv $0 + jsrv $15 + + bsrv .+4-0x800000 + bsrv .+4+0x7ffffb + bsrv symbol + + + .byte symbol + .short symbol + .long symbol + + diff --git a/gas/testsuite/gas/mep/dj2.d b/gas/testsuite/gas/mep/dj2.d new file mode 100644 index 000000000000..9634cf4c4327 --- /dev/null +++ b/gas/testsuite/gas/mep/dj2.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr +#name: dj2 + +.*: +file format .* + +Disassembly of section .text: + +00000000 <.text>: + 0: 07 88 sb \$7,\(\$8\) + 2: 05 98 sb \$5,\(\$9\) diff --git a/gas/testsuite/gas/mep/dj2.le.d b/gas/testsuite/gas/mep/dj2.le.d new file mode 100644 index 000000000000..1c1053c51a9e --- /dev/null +++ b/gas/testsuite/gas/mep/dj2.le.d @@ -0,0 +1,12 @@ +#as: -EL +#objdump: -dr +#source: dj2.s +#name: dj2.le + +.*: +file format .* + +Disassembly of section .text: + +00000000 <.text>: + 0: 88 07 sb \$7,\(\$8\) + 2: 98 05 sb \$5,\(\$9\) diff --git a/gas/testsuite/gas/mep/dj2.s b/gas/testsuite/gas/mep/dj2.s new file mode 100644 index 000000000000..4eabf82b0f08 --- /dev/null +++ b/gas/testsuite/gas/mep/dj2.s @@ -0,0 +1,5 @@ + + .text + sb $7,($fp) + sb $5,($9) + diff --git a/gas/testsuite/gas/mep/relocs-bad3.s b/gas/testsuite/gas/mep/relocs-bad3.s new file mode 100644 index 000000000000..1e80a6b0dda3 --- /dev/null +++ b/gas/testsuite/gas/mep/relocs-bad3.s @@ -0,0 +1,15 @@ + .global main + +test: + mov $0,0 + +# negative test from case 106708 + +L1: + mov $1,1 + mov $1,((L1 & 0x00007fff) | 0x00008000) + ret + mov $0,0 +main: + mov $0,0 + ret diff --git a/gas/testsuite/gas/mep/relocs-junk1.s b/gas/testsuite/gas/mep/relocs-junk1.s new file mode 100644 index 000000000000..6e9c6c2be09b --- /dev/null +++ b/gas/testsuite/gas/mep/relocs-junk1.s @@ -0,0 +1,8 @@ +junk1: + nop + nop + nop + nop + nop + .data +foodata: .word 42 diff --git a/gas/testsuite/gas/mep/relocs-junk2.s b/gas/testsuite/gas/mep/relocs-junk2.s new file mode 100644 index 000000000000..361ad6ec7cf7 --- /dev/null +++ b/gas/testsuite/gas/mep/relocs-junk2.s @@ -0,0 +1,7 @@ +junk2: + nop + nop + nop + nop + nop +
\ No newline at end of file diff --git a/gas/testsuite/gas/mep/relocs-refs.s b/gas/testsuite/gas/mep/relocs-refs.s new file mode 100644 index 000000000000..43dc77ee64b9 --- /dev/null +++ b/gas/testsuite/gas/mep/relocs-refs.s @@ -0,0 +1,55 @@ + + .global main + .global foo + .global bar +main: + nop + nop + lb $5, foo($3) + bsr foo + repeat $5, foo + + nop + nop + lb $5, (-foo & 0xffff)($3) + bsr -foo + repeat $5, -foo + + nop + nop + lb $5, (foo + bar)($3) + bsr (foo + bar) + repeat $5, (foo + bar) + + jmp (foo << 3) + jmp (foo >> 3) + jmp (foo - bar) & 0x7fffff + jmp (foo - main) & 0x7fffff + jmp (.text - foo) & 0x7fffff + jmp (.data - foo) & 0x7fffff + jmp (foo - %sizeof(.text)) + jmp (foo * 7) + jmp (foo / 7) + jmp (foo % 7) + jmp (foo ^ bar) + jmp (foo | bar) + jmp (foo & bar) + jmp (foo == bar) << 5 + jmp (foo < bar) << 5 + jmp (foo <= bar) << 5 + jmp (foo > bar) << 5 + jmp (foo >= bar) << 5 + # jmp (foo != bar) # FIXME this appears to not work atm. + jmp (foo && bar) << 5 + jmp (foo || bar) << 5 + + nop + nop + nop + nop + + jmp %sizeof(.data) >> (((main ^ (bar + 0xf)) - ((foo | .text) << 2)) / 3) + + nop + nop + nop diff --git a/gas/testsuite/gas/mep/relocs-syms.s b/gas/testsuite/gas/mep/relocs-syms.s new file mode 100644 index 000000000000..508efaf10327 --- /dev/null +++ b/gas/testsuite/gas/mep/relocs-syms.s @@ -0,0 +1,18 @@ + .global foo + .global bar + nop + nop + nop + nop +foo: + nop + nop + nop + nop +bar: + nop + nop + nop + nop + nop +
\ No newline at end of file diff --git a/gas/testsuite/gas/mep/relocs.d b/gas/testsuite/gas/mep/relocs.d new file mode 100644 index 000000000000..602545a316e5 --- /dev/null +++ b/gas/testsuite/gas/mep/relocs.d @@ -0,0 +1,98 @@ + +relocs.x: file format elf32-mep + +Contents of section .text: + 1000 00000000 00000000 00000000 00000000 ................ + 1010 00000000 00000000 00000000 00000000 ................ + 1020 00000000 00000000 00000000 00000000 ................ + 1030 0000c53c 1012dee9 ffffe509 ffec0000 ...<............ + 1040 0000c53c efeedd49 ffdfe509 efd20000 ...<...I........ + 1050 0000c53c 202cdeb9 000fe509 07e9dc88 ...< ,.......... + 1060 0080d818 0002dfc8 7fffdf28 7fffdf78 ...........\(...x + 1070 7fffdd98 0001da98 000fdbf8 0070da58 .............p.X + 1080 0002d828 0000d848 0000d8d8 0010d898 ...\(...H........ + 1090 0010d808 0000d908 0000d908 0000d808 ................ + 10a0 0000d808 0000d908 0000d908 00000000 ................ + 10b0 00000000 0000d808 00000000 00000000 ................ +Contents of section .rostacktab: + 10c0 001ffff0 .... +Contents of section .data: + 11c4 0000002a ...* +Disassembly of section .text: + +00001000 <junk1>: + 1000: 00 00 nop + 1002: 00 00 nop + 1004: 00 00 nop + 1006: 00 00 nop + 1008: 00 00 nop + 100a: 00 00 nop + 100c: 00 00 nop + 100e: 00 00 nop + 1010: 00 00 nop + +00001012 <foo>: + 1012: 00 00 nop + 1014: 00 00 nop + 1016: 00 00 nop + 1018: 00 00 nop + +0000101a <bar>: + 101a: 00 00 nop + 101c: 00 00 nop + 101e: 00 00 nop + 1020: 00 00 nop + 1022: 00 00 nop + +00001024 <junk2>: + 1024: 00 00 nop + 1026: 00 00 nop + 1028: 00 00 nop + 102a: 00 00 nop + 102c: 00 00 nop + +0000102e <main>: + 102e: 00 00 nop + 1030: 00 00 nop + 1032: c5 3c 10 12 lb \$5,4114\(\$3\) + 1036: de e9 ff ff bsr 1012 <&:s3:foo:s3:bar> + 103a: e5 09 ff ec repeat \$5,1012 <&:s3:foo:s3:bar> + 103e: 00 00 nop + 1040: 00 00 nop + 1042: c5 3c ef ee lb \$5,-4114\(\$3\) + 1046: dd 49 ff df bsr ffffefee <0-:s3:foo> + 104a: e5 09 ef d2 repeat \$5,ffffefee <0-:s3:foo> + 104e: 00 00 nop + 1050: 00 00 nop + 1052: c5 3c 20 2c lb \$5,8236\(\$3\) + 1056: de b9 00 0f bsr 202c <\+:s3:foo:s3:bar> + 105a: e5 09 07 e9 repeat \$5,202c <\+:s3:foo:s3:bar> + 105e: dc 88 00 80 jmp 8090 <<<:s3:foo:#00000003> + 1062: d8 18 00 02 jmp 202 <>>:s3:foo:#00000003> + 1066: df c8 7f ff jmp 7ffff8 <&:-:s3:foo:s3:bar:#007fffff> + 106a: df 28 7f ff jmp 7fffe4 <&:-:s3:foo:s4:main:#007fffff> + 106e: df 78 7f ff jmp 7fffee <&:-:S5:.text:s3:foo:#007fffff> + 1072: dd 98 00 01 jmp 1b2 <&:-:S5:.data:s3:foo:#007fffff> + 1076: da 98 00 0f jmp f52 <-:s3:foo:\+:s9:.text.end:0-:S5:.text> + 107a: db f8 00 70 jmp 707e <\*:s3:foo:#00000007> + 107e: da 58 00 02 jmp 24a <>>:s3:foo:#00000003\+0x48> + 1082: d8 28 00 00 jmp 4 <__assert_based_size\+0x3> + 1086: d8 48 00 00 jmp 8 <\^:s3:foo:s3:bar> + 108a: d8 d8 00 10 jmp 101a <|:s3:foo:s3:bar> + 108e: d8 98 00 10 jmp 1012 <&:s3:foo:s3:bar> + 1092: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005> + 1096: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005> + 109a: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005> + 109e: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005> + 10a2: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005> + 10a6: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005> + 10aa: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005> + 10ae: 00 00 nop + 10b0: 00 00 nop + 10b2: 00 00 nop + 10b4: 00 00 nop + 10b6: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005> + 10ba: 00 00 nop + 10bc: 00 00 nop + 10be: 00 00 nop +#pass diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d index 6f3660d4ca76..aa4c8a5e3d9c 100644 --- a/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d +++ b/gas/testsuite/gas/mips/cp0sel-names-mips32r2.d @@ -8,27 +8,27 @@ .*: +file format .*mips.* Disassembly of section .text: -0+0000 <[^>]*> 40800001 mtc0 \$0,\$0,1 -0+0004 <[^>]*> 40800002 mtc0 \$0,\$0,2 -0+0008 <[^>]*> 40800003 mtc0 \$0,\$0,3 +0+0000 <[^>]*> 40800001 mtc0 \$0,c0_mvpcontrol +0+0004 <[^>]*> 40800002 mtc0 \$0,c0_mvpconf0 +0+0008 <[^>]*> 40800003 mtc0 \$0,c0_mvpconf1 0+000c <[^>]*> 40800004 mtc0 \$0,\$0,4 0+0010 <[^>]*> 40800005 mtc0 \$0,\$0,5 0+0014 <[^>]*> 40800006 mtc0 \$0,\$0,6 0+0018 <[^>]*> 40800007 mtc0 \$0,\$0,7 -0+001c <[^>]*> 40800801 mtc0 \$0,\$1,1 -0+0020 <[^>]*> 40800802 mtc0 \$0,\$1,2 -0+0024 <[^>]*> 40800803 mtc0 \$0,\$1,3 -0+0028 <[^>]*> 40800804 mtc0 \$0,\$1,4 -0+002c <[^>]*> 40800805 mtc0 \$0,\$1,5 -0+0030 <[^>]*> 40800806 mtc0 \$0,\$1,6 +0+001c <[^>]*> 40800801 mtc0 \$0,c0_vpecontrol +0+0020 <[^>]*> 40800802 mtc0 \$0,c0_vpeconf0 +0+0024 <[^>]*> 40800803 mtc0 \$0,c0_vpeconf1 +0+0028 <[^>]*> 40800804 mtc0 \$0,c0_yqmask +0+002c <[^>]*> 40800805 mtc0 \$0,c0_vpeschedule +0+0030 <[^>]*> 40800806 mtc0 \$0,c0_vpeschefback 0+0034 <[^>]*> 40800807 mtc0 \$0,\$1,7 -0+0038 <[^>]*> 40801001 mtc0 \$0,\$2,1 -0+003c <[^>]*> 40801002 mtc0 \$0,\$2,2 -0+0040 <[^>]*> 40801003 mtc0 \$0,\$2,3 -0+0044 <[^>]*> 40801004 mtc0 \$0,\$2,4 -0+0048 <[^>]*> 40801005 mtc0 \$0,\$2,5 -0+004c <[^>]*> 40801006 mtc0 \$0,\$2,6 -0+0050 <[^>]*> 40801007 mtc0 \$0,\$2,7 +0+0038 <[^>]*> 40801001 mtc0 \$0,c0_tcstatus +0+003c <[^>]*> 40801002 mtc0 \$0,c0_tcbind +0+0040 <[^>]*> 40801003 mtc0 \$0,c0_tcrestart +0+0044 <[^>]*> 40801004 mtc0 \$0,c0_tchalt +0+0048 <[^>]*> 40801005 mtc0 \$0,c0_tccontext +0+004c <[^>]*> 40801006 mtc0 \$0,c0_tcschedule +0+0050 <[^>]*> 40801007 mtc0 \$0,c0_tcschefback 0+0054 <[^>]*> 40801801 mtc0 \$0,\$3,1 0+0058 <[^>]*> 40801802 mtc0 \$0,\$3,2 0+005c <[^>]*> 40801803 mtc0 \$0,\$3,3 @@ -50,11 +50,11 @@ Disassembly of section .text: 0+009c <[^>]*> 40802805 mtc0 \$0,\$5,5 0+00a0 <[^>]*> 40802806 mtc0 \$0,\$5,6 0+00a4 <[^>]*> 40802807 mtc0 \$0,\$5,7 -0+00a8 <[^>]*> 40803001 mtc0 \$0,\$6,1 -0+00ac <[^>]*> 40803002 mtc0 \$0,\$6,2 -0+00b0 <[^>]*> 40803003 mtc0 \$0,\$6,3 -0+00b4 <[^>]*> 40803004 mtc0 \$0,\$6,4 -0+00b8 <[^>]*> 40803005 mtc0 \$0,\$6,5 +0+00a8 <[^>]*> 40803001 mtc0 \$0,c0_srsconf0 +0+00ac <[^>]*> 40803002 mtc0 \$0,c0_srsconf1 +0+00b0 <[^>]*> 40803003 mtc0 \$0,c0_srsconf2 +0+00b4 <[^>]*> 40803004 mtc0 \$0,c0_srsconf3 +0+00b8 <[^>]*> 40803005 mtc0 \$0,c0_srsconf4 0+00bc <[^>]*> 40803006 mtc0 \$0,\$6,6 0+00c0 <[^>]*> 40803007 mtc0 \$0,\$6,7 0+00c4 <[^>]*> 40803801 mtc0 \$0,\$7,1 diff --git a/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d index 9222800a67be..22aa180ee235 100644 --- a/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d +++ b/gas/testsuite/gas/mips/cp0sel-names-mips64r2.d @@ -8,27 +8,27 @@ .*: +file format .*mips.* Disassembly of section .text: -0+0000 <[^>]*> 40800001 mtc0 \$0,\$0,1 -0+0004 <[^>]*> 40800002 mtc0 \$0,\$0,2 -0+0008 <[^>]*> 40800003 mtc0 \$0,\$0,3 +0+0000 <[^>]*> 40800001 mtc0 \$0,c0_mvpcontrol +0+0004 <[^>]*> 40800002 mtc0 \$0,c0_mvpconf0 +0+0008 <[^>]*> 40800003 mtc0 \$0,c0_mvpconf1 0+000c <[^>]*> 40800004 mtc0 \$0,\$0,4 0+0010 <[^>]*> 40800005 mtc0 \$0,\$0,5 0+0014 <[^>]*> 40800006 mtc0 \$0,\$0,6 0+0018 <[^>]*> 40800007 mtc0 \$0,\$0,7 -0+001c <[^>]*> 40800801 mtc0 \$0,\$1,1 -0+0020 <[^>]*> 40800802 mtc0 \$0,\$1,2 -0+0024 <[^>]*> 40800803 mtc0 \$0,\$1,3 -0+0028 <[^>]*> 40800804 mtc0 \$0,\$1,4 -0+002c <[^>]*> 40800805 mtc0 \$0,\$1,5 -0+0030 <[^>]*> 40800806 mtc0 \$0,\$1,6 +0+001c <[^>]*> 40800801 mtc0 \$0,c0_vpecontrol +0+0020 <[^>]*> 40800802 mtc0 \$0,c0_vpeconf0 +0+0024 <[^>]*> 40800803 mtc0 \$0,c0_vpeconf1 +0+0028 <[^>]*> 40800804 mtc0 \$0,c0_yqmask +0+002c <[^>]*> 40800805 mtc0 \$0,c0_vpeschedule +0+0030 <[^>]*> 40800806 mtc0 \$0,c0_vpeschefback 0+0034 <[^>]*> 40800807 mtc0 \$0,\$1,7 -0+0038 <[^>]*> 40801001 mtc0 \$0,\$2,1 -0+003c <[^>]*> 40801002 mtc0 \$0,\$2,2 -0+0040 <[^>]*> 40801003 mtc0 \$0,\$2,3 -0+0044 <[^>]*> 40801004 mtc0 \$0,\$2,4 -0+0048 <[^>]*> 40801005 mtc0 \$0,\$2,5 -0+004c <[^>]*> 40801006 mtc0 \$0,\$2,6 -0+0050 <[^>]*> 40801007 mtc0 \$0,\$2,7 +0+0038 <[^>]*> 40801001 mtc0 \$0,c0_tcstatus +0+003c <[^>]*> 40801002 mtc0 \$0,c0_tcbind +0+0040 <[^>]*> 40801003 mtc0 \$0,c0_tcrestart +0+0044 <[^>]*> 40801004 mtc0 \$0,c0_tchalt +0+0048 <[^>]*> 40801005 mtc0 \$0,c0_tccontext +0+004c <[^>]*> 40801006 mtc0 \$0,c0_tcschedule +0+0050 <[^>]*> 40801007 mtc0 \$0,c0_tcschefback 0+0054 <[^>]*> 40801801 mtc0 \$0,\$3,1 0+0058 <[^>]*> 40801802 mtc0 \$0,\$3,2 0+005c <[^>]*> 40801803 mtc0 \$0,\$3,3 @@ -50,11 +50,11 @@ Disassembly of section .text: 0+009c <[^>]*> 40802805 mtc0 \$0,\$5,5 0+00a0 <[^>]*> 40802806 mtc0 \$0,\$5,6 0+00a4 <[^>]*> 40802807 mtc0 \$0,\$5,7 -0+00a8 <[^>]*> 40803001 mtc0 \$0,\$6,1 -0+00ac <[^>]*> 40803002 mtc0 \$0,\$6,2 -0+00b0 <[^>]*> 40803003 mtc0 \$0,\$6,3 -0+00b4 <[^>]*> 40803004 mtc0 \$0,\$6,4 -0+00b8 <[^>]*> 40803005 mtc0 \$0,\$6,5 +0+00a8 <[^>]*> 40803001 mtc0 \$0,c0_srsconf0 +0+00ac <[^>]*> 40803002 mtc0 \$0,c0_srsconf1 +0+00b0 <[^>]*> 40803003 mtc0 \$0,c0_srsconf2 +0+00b4 <[^>]*> 40803004 mtc0 \$0,c0_srsconf3 +0+00b8 <[^>]*> 40803005 mtc0 \$0,c0_srsconf4 0+00bc <[^>]*> 40803006 mtc0 \$0,\$6,6 0+00c0 <[^>]*> 40803007 mtc0 \$0,\$6,7 0+00c4 <[^>]*> 40803801 mtc0 \$0,\$7,1 diff --git a/gas/testsuite/gas/mips/e32-rel2.d b/gas/testsuite/gas/mips/e32-rel2.d index 3983c7fd6f91..a43fd33059a5 100644 --- a/gas/testsuite/gas/mips/e32-rel2.d +++ b/gas/testsuite/gas/mips/e32-rel2.d @@ -1,5 +1,6 @@ #objdump: -sr -j .text #name: MIPS ELF reloc 2 (32-bit) +#as: -mabi=32 #source: elf-rel2.s # Test the GPREL and LITERAL generation. diff --git a/gas/testsuite/gas/mips/e32-rel4.d b/gas/testsuite/gas/mips/e32-rel4.d index 81ae4e7fc1b2..35deea45efca 100644 --- a/gas/testsuite/gas/mips/e32-rel4.d +++ b/gas/testsuite/gas/mips/e32-rel4.d @@ -1,5 +1,6 @@ #objdump: --prefix-addresses -dr -#name: MIPS ELF reloc 4 +#name: MIPS ELF reloc 4 (32-bit) +#as: -mabi=32 #source: elf-rel4.s .*: +file format.* diff --git a/gas/testsuite/gas/mips/elf-rel26.d b/gas/testsuite/gas/mips/elf-rel26.d new file mode 100644 index 000000000000..d176acbf52c2 --- /dev/null +++ b/gas/testsuite/gas/mips/elf-rel26.d @@ -0,0 +1,22 @@ +#as: -mips32 -EL -KPIC +#readelf: --relocs +#name: MIPS ELF reloc 26 + +Relocation section '\.rel\.pdr' .* + *Offset.* +00.* + +Relocation section '\.rel\.text\.foo' at offset .* contains 11 entries: + *Offset * Info * Type * Sym\.Value * Sym\. Name +0+000 * .+ * R_MIPS_HI16 * 0+0 * _gp_disp +0+004 * .+ * R_MIPS_LO16 * 0+0 * _gp_disp +0+014 * .+ * R_MIPS_GOT16 * 0+0 * \$LC28 +0+01c * .+ * R_MIPS_LO16 * 0+0 * \$LC28 +0+020 * .+ * R_MIPS_CALL16 * 0+0 * bar +0+030 * .+ * R_MIPS_PC16 * 0+0 * \$L846 +0+034 * .+ * R_MIPS_GOT16 * 0+0 * \$LC27 +0+038 * .+ * R_MIPS_PC16 * 0+0 * \$L848 +0+048 * .+ * R_MIPS_PC16 * 0+0 * \$L925 +0+010 * .+ * R_MIPS_GOT16 * 0+0 * \.rodata\.foo +0+05c * .+ * R_MIPS_LO16 * 0+0 * \.rodata\.foo +#pass diff --git a/gas/testsuite/gas/mips/elf-rel26.s b/gas/testsuite/gas/mips/elf-rel26.s new file mode 100644 index 000000000000..ed6984a169e0 --- /dev/null +++ b/gas/testsuite/gas/mips/elf-rel26.s @@ -0,0 +1,62 @@ + .section .text.foo,"axG",@progbits,foo,comdat + .align 2 + .weak foo + .ent foo + .type foo, @function +foo: +$LFB308: + .frame $fp,136,$31 # vars= 72, regs= 10/0, args= 16, gp= 8 + .mask 0xc0ff0000,-4 + .fmask 0x00000000,0 + .set noreorder + .cpload $25 + + .set nomacro + bne $3,$0,$L924 + lw $25,%got($L874)($28) + .set macro + .set reorder + lw $5,%got($LC28)($28) + lw $4,136($fp) + addiu $5,$5,%lo($LC28) + lw $25,%call16(bar)($28) + .set noreorder + .set nomacro + jalr $25 + li $6,-1 # 0xffffffffffffffff + .set macro + .set reorder + lw $25,64($fp) + .set noreorder + .set nomacro + bne $25,$0,$L846 + lw $5,%got($LC27)($28) + b $L848 + sw $0,68($fp) + .set macro + .set reorder +$L920: + lb $3,0($18) + li $2,59 # 0x3b + .set noreorder + .set nomacro + beq $3,$2,$L925 + lw $25,76($fp) + b $L920 + addiu $18,$18,1 + .set macro + .set reorder + +$L924: + sll $2,$2,2 + addiu $25,$25,%lo($L874) + addu $2,$2,$25 + lw $3,0($2) + addu $3,$3,$28 + j $3 + .end foo + .section .rodata.foo,"aG",@progbits,foo,comdat + .align 2 + .align 2 +$L874: + .gpword $L924 diff --git a/gas/testsuite/gas/mips/elf-rel6-n32.d b/gas/testsuite/gas/mips/elf-rel6-n32.d new file mode 100644 index 000000000000..258fcf656b67 --- /dev/null +++ b/gas/testsuite/gas/mips/elf-rel6-n32.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses +#name: MIPS ELF reloc 6 n32 +#as: -mabi=n32 -march=mips64 +#source: elf-rel6.s + +.*: +file format elf.*mips.* + +Disassembly of section \.text: +0+00 <.*> lb v0,0\(v1\) + 0: R_MIPS16_GPREL bar +0+04 <.*> lb v0,0\(v1\) + 4: R_MIPS16_GPREL bar\+0x1 +0+08 <.*> lb v0,0\(v1\) + 8: R_MIPS16_GPREL bar\+0x1234 +0+0c <[^>]*> nop +0+0e <[^>]*> nop diff --git a/gas/testsuite/gas/mips/elf-rel6-n64.d b/gas/testsuite/gas/mips/elf-rel6-n64.d new file mode 100644 index 000000000000..d65b10ab3133 --- /dev/null +++ b/gas/testsuite/gas/mips/elf-rel6-n64.d @@ -0,0 +1,22 @@ +#objdump: -dr --prefix-addresses +#name: MIPS ELF reloc 6 n64 +#as: -mabi=64 -march=mips64 +#source: elf-rel6.s + +.*: +file format elf.*mips.* + +Disassembly of section \.text: +0+00 <.*> lb v0,0\(v1\) + 0: R_MIPS16_GPREL bar + 0: R_MIPS_NONE \*ABS\* + 0: R_MIPS_NONE \*ABS\* +0+04 <.*> lb v0,0\(v1\) + 4: R_MIPS16_GPREL bar\+0x1 + 4: R_MIPS_NONE \*ABS\*\+0x1 + 4: R_MIPS_NONE \*ABS\*\+0x1 +0+08 <.*> lb v0,0\(v1\) + 8: R_MIPS16_GPREL bar\+0x1234 + 8: R_MIPS_NONE \*ABS\*\+0x1234 + 8: R_MIPS_NONE \*ABS\*\+0x1234 +0+0c <[^>]*> nop +0+0e <[^>]*> nop diff --git a/gas/testsuite/gas/mips/elf-rel6.d b/gas/testsuite/gas/mips/elf-rel6.d index 85efe9d0aed0..cea8d7fd81b9 100644 --- a/gas/testsuite/gas/mips/elf-rel6.d +++ b/gas/testsuite/gas/mips/elf-rel6.d @@ -9,7 +9,7 @@ Disassembly of section \.text: 0: R_MIPS16_GPREL bar 0+04 <.*> lb v0,1\(v1\) 4: R_MIPS16_GPREL bar -0+08 <[^>]*> nop -0+0a <[^>]*> nop +0+08 <.*> lb v0,4660\(v1\) + 8: R_MIPS16_GPREL bar 0+0c <[^>]*> nop 0+0e <[^>]*> nop diff --git a/gas/testsuite/gas/mips/elf-rel6.s b/gas/testsuite/gas/mips/elf-rel6.s index 6735d7555fad..34c3a84b6ff8 100644 --- a/gas/testsuite/gas/mips/elf-rel6.s +++ b/gas/testsuite/gas/mips/elf-rel6.s @@ -13,6 +13,7 @@ bar: .byte 3 f: lb $2,%gprel(bar)($3) lb $2,%gprel(bar+1)($3) + lb $2,%gprel(bar+0x1234)($3) .end f # align section end to 16-byte boundary for easier testing on multiple targets diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d index 52c1701bd411..3ebbe3f4cf4c 100644 --- a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d +++ b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d @@ -1,6 +1,7 @@ #objdump: -d -mmips:8000 #as: -32 -march=8000 -EB -mgp32 -mfp64 -KPIC #name: MIPS -mgp32 -mfp64 (SVR4 PIC) +#stderr: mips-gp32-fp64.l .*: +file format.* diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.d b/gas/testsuite/gas/mips/mips-gp32-fp64.d index b266f702f6d4..8fcd56380fa8 100644 --- a/gas/testsuite/gas/mips/mips-gp32-fp64.d +++ b/gas/testsuite/gas/mips/mips-gp32-fp64.d @@ -1,6 +1,7 @@ #objdump: -d -mmips:8000 #as: -32 -march=8000 -EB -mgp32 -mfp64 #name: MIPS -mgp32 -mfp64 +#stderr: mips-gp32-fp64.l .*: +file format.* diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.l b/gas/testsuite/gas/mips/mips-gp32-fp64.l new file mode 100644 index 000000000000..de3f3b06ce28 --- /dev/null +++ b/gas/testsuite/gas/mips/mips-gp32-fp64.l @@ -0,0 +1,2 @@ +Assembler messages: +Warning: -mfp64 used with a 32-bit ABI diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d index f5a8e8963942..52fe8afd013a 100644 --- a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d +++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d @@ -1,6 +1,7 @@ #objdump: -d -mmips:8000 #as: -mabi=o64 -march=8000 -EB -mfp32 -KPIC #name: MIPS -mgp64 -mfp32 (SVR4 PIC) +#stderr: mips-gp64-fp32-pic.l .*: +file format.* diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l new file mode 100644 index 000000000000..2d3730301237 --- /dev/null +++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l @@ -0,0 +1,2 @@ +Assembler messages: +Warning: -mfp32 used with a 64-bit ABI diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32.l b/gas/testsuite/gas/mips/mips-gp64-fp32.l index 4f26b42dce1a..3668a25e3b20 100644 --- a/gas/testsuite/gas/mips/mips-gp64-fp32.l +++ b/gas/testsuite/gas/mips/mips-gp64-fp32.l @@ -1,4 +1,5 @@ -.*: Assembler messages: +Assembler messages: +Warning: -mfp32 used with a 64-bit ABI .*:92: Warning: Macro instruction expanded into multiple instructions in a branch delay slot .*:96: Warning: Macro instruction expanded into multiple instructions in a branch delay slot .*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot diff --git a/gas/testsuite/gas/mips/mips-gp64-fp64.d b/gas/testsuite/gas/mips/mips-gp64-fp64.d index bf3e44f84f0e..3e1bfd5d5b8e 100644 --- a/gas/testsuite/gas/mips/mips-gp64-fp64.d +++ b/gas/testsuite/gas/mips/mips-gp64-fp64.d @@ -1,7 +1,7 @@ #objdump: -d -mmips:8000 #as: -mabi=o64 -march=8000 -EB #name: MIPS -mgp64 -mfp64 -#stderr: mips-gp64-fp32.l +#stderr: mips-gp64-fp64.l .*: +file format.* diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 7843f2a9742b..523a7738242a 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -292,27 +292,6 @@ proc run_dump_test_arches { name arch_list } { } } -# run_list_test NAME OPTS (optional): TESTNAME -# -# Assemble the file "NAME.d" and compare the assembler standard error -# output against the regular expressions given in the file "NAME.l". -# The assembler is passed the flags given in OPTS. If TESTNAME is -# provided, it will be used as the name of the test. -proc run_list_test { name opts {testname {}} } { - global srcdir subdir - if { [string length $testname] == 0 } then { - set testname "MIPS $name" - } - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - # run_list_test_arch NAME OPTS ARCH # # Invoke "run_list_test" for test NAME with options OPTS, with extra @@ -390,6 +369,8 @@ mips_arch_create sb1 64 mips64 { mips3d } \ if { [istarget mips*-*-vxworks*] } { run_dump_test "vxworks1" run_dump_test "vxworks1-xgot" + run_dump_test "vxworks1-el" + run_dump_test "vxworks1-xgot-el" } elseif { [istarget mips*-*-*] } { set no_mips16 0 set elf [expr [istarget *-*-elf*] || [istarget *-*-irix5*] || [istarget *-*-irix6* ] || [istarget *-*-linux*] || [istarget *-*-netbsd*] ] @@ -400,7 +381,7 @@ if { [istarget mips*-*-vxworks*] } { set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*]] set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]] - if { [istarget "mips*-*-*linux*"] } then { + if { [istarget "mips*-*-*linux*"] || [istarget "mips*-sde-elf*"] } then { set tmips "t" } else { set tmips "" @@ -531,6 +512,8 @@ if { [istarget mips*-*-vxworks*] } { if { $elf && !$no_mips16 } { run_dump_test "mips16" run_dump_test "mips16-64" + # Check MIPS16e extensions + run_dump_test_arches "mips16e" [mips_arch_list_matching mips32] # Check jalx handling run_dump_test "mips16-jalx" run_dump_test "mips-jalx" @@ -559,6 +542,8 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "mips32" [mips_arch_list_matching mips32] + run_dump_test_arches "mips32-sf32" [mips_arch_list_matching mips32] + run_dump_test_arches "mips32r2" [mips_arch_list_matching mips32r2] run_list_test_arches "mips32r2-ill" "-32" \ [mips_arch_list_matching mips32r2 gpr32] @@ -633,20 +618,17 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "mips-abi32-pic2" run_dump_test "elf${el}-rel" - if {[istarget mips64*-*-*] || [istarget mipsisa32*-*-*] - || [istarget mipsisa64*-*-*]} { - run_dump_test "elf${el}-rel2" - } else { - run_dump_test "e32${el}-rel2" - } + run_dump_test_arches "elf${el}-rel2" [mips_arch_list_matching gpr64] + run_dump_test "e32${el}-rel2" run_dump_test "elf${el}-rel3" - if {[istarget mips64*-*-*]} { - run_dump_test "elf-rel4" - } else { - run_dump_test "e32-rel4" - } + run_dump_test_arches "elf-rel4" [mips_arch_list_matching gpr64] + run_dump_test "e32-rel4" run_dump_test "elf-rel5" run_dump_test "elf-rel6" + if $has_newabi { + run_dump_test "elf-rel6-n32" + run_dump_test "elf-rel6-n64" + } run_dump_test "elf-rel7" run_dump_test "elf-rel8" run_dump_test "elf-rel9" @@ -684,6 +666,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "elf-rel25" run_dump_test "elf-rel25a" + run_dump_test "elf-rel26" if { !$no_mips16 } { run_dump_test "${tmips}mips${el}16-e" @@ -766,7 +749,10 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "noat-6" "" run_list_test "noat-7" "" - run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32 !sb1] + run_dump_test_arches "smartmips" [mips_arch_list_matching mips32 !gpr64] + run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2] + run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2] + run_dump_test_arches "mips64-dsp" [mips_arch_list_matching mips64r2] run_dump_test_arches "mips32-mt" [mips_arch_list_matching mips32r2 !gpr64] if { $elf && !$no_mips16 } { @@ -778,7 +764,14 @@ if { [istarget mips*-*-vxworks*] } { if { !$no_mips16 } { run_dump_test "mips16e-jrc" run_dump_test "mips16e-save" + run_dump_test "mips16e-64" + run_list_test "mips16e-64" "-march=mips32 -32" + run_dump_test "mips16-intermix" } run_dump_test "vxworks1" run_dump_test "vxworks1-xgot" + run_dump_test "vxworks1-el" + run_dump_test "vxworks1-xgot-el" + + run_dump_test "noreorder" } diff --git a/gas/testsuite/gas/mips/mips16-intermix.d b/gas/testsuite/gas/mips/mips16-intermix.d new file mode 100644 index 000000000000..9b541eefebcf --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-intermix.d @@ -0,0 +1,164 @@ +#objdump: -t +#as: -mips32r2 +#name: MIPS16 intermix + +.*: +file format .*mips.* + +SYMBOL TABLE: +#... +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_l +0+[0-9a-f]+ l d .mips16.fn.m16_d 0+[0-9a-f]+ .mips16.fn.m16_d +0+[0-9a-f]+ l F .mips16.fn.m16_d 0+[0-9a-f]+ __fn_stub_m16_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d +0+[0-9a-f]+ l d .mips16.fn.m16_static_d 0+[0-9a-f]+ .mips16.fn.m16_static_d +0+[0-9a-f]+ l F .mips16.fn.m16_static_d 0+[0-9a-f]+ __fn_stub_m16_static_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d +0+[0-9a-f]+ l d .mips16.fn.m16_static1_d 0+[0-9a-f]+ .mips16.fn.m16_static1_d +0+[0-9a-f]+ l F .mips16.fn.m16_static1_d 0+[0-9a-f]+ __fn_stub_m16_static1_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d +0+[0-9a-f]+ l d .mips16.fn.m16_static32_d 0+[0-9a-f]+ .mips16.fn.m16_static32_d +0+[0-9a-f]+ l F .mips16.fn.m16_static32_d 0+[0-9a-f]+ __fn_stub_m16_static32_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d +0+[0-9a-f]+ l d .mips16.fn.m16_static16_d 0+[0-9a-f]+ .mips16.fn.m16_static16_d +0+[0-9a-f]+ l F .mips16.fn.m16_static16_d 0+[0-9a-f]+ __fn_stub_m16_static16_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_ld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_ld +0+[0-9a-f]+ l d .mips16.fn.m16_dl 0+[0-9a-f]+ .mips16.fn.m16_dl +0+[0-9a-f]+ l F .mips16.fn.m16_dl 0+[0-9a-f]+ __fn_stub_m16_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_dl +0+[0-9a-f]+ l d .mips16.fn.m16_static_dl 0+[0-9a-f]+ .mips16.fn.m16_static_dl +0+[0-9a-f]+ l F .mips16.fn.m16_static_dl 0+[0-9a-f]+ __fn_stub_m16_static_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dl +0+[0-9a-f]+ l d .mips16.fn.m16_static1_dl 0+[0-9a-f]+ .mips16.fn.m16_static1_dl +0+[0-9a-f]+ l F .mips16.fn.m16_static1_dl 0+[0-9a-f]+ __fn_stub_m16_static1_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dl +0+[0-9a-f]+ l d .mips16.fn.m16_static32_dl 0+[0-9a-f]+ .mips16.fn.m16_static32_dl +0+[0-9a-f]+ l F .mips16.fn.m16_static32_dl 0+[0-9a-f]+ __fn_stub_m16_static32_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_dl +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dl +0+[0-9a-f]+ l d .mips16.fn.m16_static16_dl 0+[0-9a-f]+ .mips16.fn.m16_static16_dl +0+[0-9a-f]+ l F .mips16.fn.m16_static16_dl 0+[0-9a-f]+ __fn_stub_m16_static16_dl +0+[0-9a-f]+ l d .mips16.fn.m16_dlld 0+[0-9a-f]+ .mips16.fn.m16_dlld +0+[0-9a-f]+ l F .mips16.fn.m16_dlld 0+[0-9a-f]+ __fn_stub_m16_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_dlld +0+[0-9a-f]+ l d .mips16.fn.m16_static_dlld 0+[0-9a-f]+ .mips16.fn.m16_static_dlld +0+[0-9a-f]+ l F .mips16.fn.m16_static_dlld 0+[0-9a-f]+ __fn_stub_m16_static_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_dlld +0+[0-9a-f]+ l d .mips16.fn.m16_static1_dlld 0+[0-9a-f]+ .mips16.fn.m16_static1_dlld +0+[0-9a-f]+ l F .mips16.fn.m16_static1_dlld 0+[0-9a-f]+ __fn_stub_m16_static1_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_dlld +0+[0-9a-f]+ l d .mips16.fn.m16_static32_dlld 0+[0-9a-f]+ .mips16.fn.m16_static32_dlld +0+[0-9a-f]+ l F .mips16.fn.m16_static32_dlld 0+[0-9a-f]+ __fn_stub_m16_static32_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_dlld +0+[0-9a-f]+ l d .mips16.fn.m16_static16_dlld 0+[0-9a-f]+ .mips16.fn.m16_static16_dlld +0+[0-9a-f]+ l F .mips16.fn.m16_static16_dlld 0+[0-9a-f]+ __fn_stub_m16_static16_dlld +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d_l +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_l +0+[0-9a-f]+ l d .mips16.fn.m16_d_d 0+[0-9a-f]+ .mips16.fn.m16_d_d +0+[0-9a-f]+ l F .mips16.fn.m16_d_d 0+[0-9a-f]+ __fn_stub_m16_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static_d_d +0+[0-9a-f]+ l d .mips16.fn.m16_static_d_d 0+[0-9a-f]+ .mips16.fn.m16_static_d_d +0+[0-9a-f]+ l F .mips16.fn.m16_static_d_d 0+[0-9a-f]+ __fn_stub_m16_static_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static1_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static1_d_d +0+[0-9a-f]+ l d .mips16.fn.m16_static1_d_d 0+[0-9a-f]+ .mips16.fn.m16_static1_d_d +0+[0-9a-f]+ l F .mips16.fn.m16_static1_d_d 0+[0-9a-f]+ __fn_stub_m16_static1_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static32_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static32_d_d +0+[0-9a-f]+ l d .mips16.fn.m16_static32_d_d 0+[0-9a-f]+ .mips16.fn.m16_static32_d_d +0+[0-9a-f]+ l F .mips16.fn.m16_static32_d_d 0+[0-9a-f]+ __fn_stub_m16_static32_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ m32_static16_d_d +0+[0-9a-f]+ l F .text 0+[0-9a-f]+ 0xf0 m16_static16_d_d +0+[0-9a-f]+ l d .mips16.fn.m16_static16_d_d 0+[0-9a-f]+ .mips16.fn.m16_static16_d_d +0+[0-9a-f]+ l F .mips16.fn.m16_static16_d_d 0+[0-9a-f]+ __fn_stub_m16_static16_d_d +0+[0-9a-f]+ l d .mips16.call.m32_static1_d 0+[0-9a-f]+ .mips16.call.m32_static1_d +0+[0-9a-f]+ l F .mips16.call.m32_static1_d 0+[0-9a-f]+ __call_stub_m32_static1_d +0+[0-9a-f]+ l d .mips16.call.m16_static1_d 0+[0-9a-f]+ .mips16.call.m16_static1_d +0+[0-9a-f]+ l F .mips16.call.m16_static1_d 0+[0-9a-f]+ __call_stub_m16_static1_d +0+[0-9a-f]+ l d .mips16.call.m32_static1_dl 0+[0-9a-f]+ .mips16.call.m32_static1_dl +0+[0-9a-f]+ l F .mips16.call.m32_static1_dl 0+[0-9a-f]+ __call_stub_m32_static1_dl +0+[0-9a-f]+ l d .mips16.call.m16_static1_dl 0+[0-9a-f]+ .mips16.call.m16_static1_dl +0+[0-9a-f]+ l F .mips16.call.m16_static1_dl 0+[0-9a-f]+ __call_stub_m16_static1_dl +0+[0-9a-f]+ l d .mips16.call.m32_static1_dlld 0+[0-9a-f]+ .mips16.call.m32_static1_dlld +0+[0-9a-f]+ l F .mips16.call.m32_static1_dlld 0+[0-9a-f]+ __call_stub_m32_static1_dlld +0+[0-9a-f]+ l d .mips16.call.m16_static1_dlld 0+[0-9a-f]+ .mips16.call.m16_static1_dlld +0+[0-9a-f]+ l F .mips16.call.m16_static1_dlld 0+[0-9a-f]+ __call_stub_m16_static1_dlld +0+[0-9a-f]+ l d .mips16.call.fp.m32_static1_d_l 0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_l +0+[0-9a-f]+ l F .mips16.call.fp.m32_static1_d_l 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l +0+[0-9a-f]+ l d .mips16.call.fp.m16_static1_d_l 0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_l +0+[0-9a-f]+ l F .mips16.call.fp.m16_static1_d_l 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l +0+[0-9a-f]+ l d .mips16.call.fp.m32_static1_d_d 0+[0-9a-f]+ .mips16.call.fp.m32_static1_d_d +0+[0-9a-f]+ l F .mips16.call.fp.m32_static1_d_d 0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d +0+[0-9a-f]+ l d .mips16.call.fp.m16_static1_d_d 0+[0-9a-f]+ .mips16.call.fp.m16_static1_d_d +0+[0-9a-f]+ l F .mips16.call.fp.m16_static1_d_d 0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d +0+[0-9a-f]+ l d .mips16.call.m32_static16_d 0+[0-9a-f]+ .mips16.call.m32_static16_d +0+[0-9a-f]+ l F .mips16.call.m32_static16_d 0+[0-9a-f]+ __call_stub_m32_static16_d +0+[0-9a-f]+ l d .mips16.call.m16_static16_d 0+[0-9a-f]+ .mips16.call.m16_static16_d +0+[0-9a-f]+ l F .mips16.call.m16_static16_d 0+[0-9a-f]+ __call_stub_m16_static16_d +0+[0-9a-f]+ l d .mips16.call.m32_static16_dl 0+[0-9a-f]+ .mips16.call.m32_static16_dl +0+[0-9a-f]+ l F .mips16.call.m32_static16_dl 0+[0-9a-f]+ __call_stub_m32_static16_dl +0+[0-9a-f]+ l d .mips16.call.m16_static16_dl 0+[0-9a-f]+ .mips16.call.m16_static16_dl +0+[0-9a-f]+ l F .mips16.call.m16_static16_dl 0+[0-9a-f]+ __call_stub_m16_static16_dl +0+[0-9a-f]+ l d .mips16.call.m32_static16_dlld 0+[0-9a-f]+ .mips16.call.m32_static16_dlld +0+[0-9a-f]+ l F .mips16.call.m32_static16_dlld 0+[0-9a-f]+ __call_stub_m32_static16_dlld +0+[0-9a-f]+ l d .mips16.call.m16_static16_dlld 0+[0-9a-f]+ .mips16.call.m16_static16_dlld +0+[0-9a-f]+ l F .mips16.call.m16_static16_dlld 0+[0-9a-f]+ __call_stub_m16_static16_dlld +0+[0-9a-f]+ l d .mips16.call.fp.m32_static16_d_l 0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_l +0+[0-9a-f]+ l F .mips16.call.fp.m32_static16_d_l 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l +0+[0-9a-f]+ l d .mips16.call.fp.m16_static16_d_l 0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_l +0+[0-9a-f]+ l F .mips16.call.fp.m16_static16_d_l 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l +0+[0-9a-f]+ l d .mips16.call.fp.m32_static16_d_d 0+[0-9a-f]+ .mips16.call.fp.m32_static16_d_d +0+[0-9a-f]+ l F .mips16.call.fp.m32_static16_d_d 0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d +0+[0-9a-f]+ l d .mips16.call.fp.m16_static16_d_d 0+[0-9a-f]+ .mips16.call.fp.m16_static16_d_d +0+[0-9a-f]+ l F .mips16.call.fp.m16_static16_d_d 0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d +#... +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_l +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_l +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d +#... +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_ld +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_ld +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_dl +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_dl +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_dlld +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_dlld +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d_l +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d_l +#... +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ m32_d_d +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 m16_d_d +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ f32 +0+[0-9a-f]+ g F .text 0+[0-9a-f]+ 0xf0 f16 +#pass diff --git a/gas/testsuite/gas/mips/mips16-intermix.s b/gas/testsuite/gas/mips/mips16-intermix.s new file mode 100644 index 000000000000..49b0cc97668e --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-intermix.s @@ -0,0 +1,2631 @@ + .text + .align 2 + .globl m32_l + .set nomips16 + .ent m32_l +m32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_l + + .align 2 + .globl m16_l + .set mips16 + .ent m16_l +m16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_l + + .align 2 + .set nomips16 + .ent m32_static_l +m32_static_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static_l + + .align 2 + .set mips16 + .ent m16_static_l +m16_static_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static_l + + .align 2 + .set nomips16 + .ent m32_static1_l +m32_static1_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static1_l + + .align 2 + .set mips16 + .ent m16_static1_l +m16_static1_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static1_l + + .align 2 + .set nomips16 + .ent m32_static32_l +m32_static32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static32_l + + .align 2 + .set mips16 + .ent m16_static32_l +m16_static32_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static32_l + + .align 2 + .set nomips16 + .ent m32_static16_l +m32_static16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + move $2,$4 + + .set macro + .set reorder + .end m32_static16_l + + .align 2 + .set mips16 + .ent m16_static16_l +m16_static16_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + j $31 + move $2,$4 + .set macro + .set reorder + + .end m16_static16_l + + .align 2 + .globl m32_d + .set nomips16 + .ent m32_d +m32_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_d + + .align 2 + .globl m16_d + .set mips16 + .ent m16_d +m16_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_d + # Stub function for m16_d (double) + .set nomips16 + .section .mips16.fn.m16_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_d +__fn_stub_m16_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_d + .previous + + .align 2 + .set nomips16 + .ent m32_static_d +m32_static_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static_d + + .align 2 + .set mips16 + .ent m16_static_d +m16_static_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static_d + # Stub function for m16_static_d (double) + .set nomips16 + .section .mips16.fn.m16_static_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_d +__fn_stub_m16_static_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_d + .previous + + .align 2 + .set nomips16 + .ent m32_static1_d +m32_static1_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static1_d + + .align 2 + .set mips16 + .ent m16_static1_d +m16_static1_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static1_d + # Stub function for m16_static1_d (double) + .set nomips16 + .section .mips16.fn.m16_static1_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_d +__fn_stub_m16_static1_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_d + .previous + + .align 2 + .set nomips16 + .ent m32_static32_d +m32_static32_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static32_d + + .align 2 + .set mips16 + .ent m16_static32_d +m16_static32_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static32_d + # Stub function for m16_static32_d (double) + .set nomips16 + .section .mips16.fn.m16_static32_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_d +__fn_stub_m16_static32_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_d + .previous + + .align 2 + .set nomips16 + .ent m32_static16_d +m32_static16_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f12,$f12 + j $31 + mfc1 $2,$f12 + + .set macro + .set reorder + .end m32_static16_d + + .align 2 + .set mips16 + .ent m16_static16_d +m16_static16_d: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_fixdfsi + restore 24,$31 + j $31 + .end m16_static16_d + # Stub function for m16_static16_d (double) + .set nomips16 + .section .mips16.fn.m16_static16_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_d +__fn_stub_m16_static16_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_d + .previous + + .align 2 + .globl m32_ld + .set nomips16 + .ent m32_ld +m32_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_ld + + .align 2 + .globl m16_ld + .set mips16 + .ent m16_ld +m16_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_ld + + .align 2 + .set nomips16 + .ent m32_static_ld +m32_static_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static_ld + + .align 2 + .set mips16 + .ent m16_static_ld +m16_static_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static_ld + + .align 2 + .set nomips16 + .ent m32_static1_ld +m32_static1_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static1_ld + + .align 2 + .set mips16 + .ent m16_static1_ld +m16_static1_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static1_ld + + .align 2 + .set nomips16 + .ent m32_static32_ld +m32_static32_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static32_ld + + .align 2 + .set mips16 + .ent m16_static32_ld +m16_static32_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static32_ld + + .align 2 + .set nomips16 + .ent m32_static16_ld +m32_static16_ld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $7,$f2 + mtc1 $6,$f3 + trunc.w.d $f0,$f2 + mfc1 $24,$f0 + j $31 + addu $2,$24,$4 + + .set macro + .set reorder + .end m32_static16_ld + + .align 2 + .set mips16 + .ent m16_static16_ld +m16_static16_ld: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + move $16,$4 + move $5,$7 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $4,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static16_ld + + .align 2 + .globl m32_dl + .set nomips16 + .ent m32_dl +m32_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_dl + + .align 2 + .globl m16_dl + .set mips16 + .ent m16_dl +m16_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_dl + # Stub function for m16_dl (double) + .set nomips16 + .section .mips16.fn.m16_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_dl +__fn_stub_m16_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static_dl +m32_static_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static_dl + + .align 2 + .set mips16 + .ent m16_static_dl +m16_static_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static_dl + # Stub function for m16_static_dl (double) + .set nomips16 + .section .mips16.fn.m16_static_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_dl +__fn_stub_m16_static_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static1_dl +m32_static1_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static1_dl + + .align 2 + .set mips16 + .ent m16_static1_dl +m16_static1_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static1_dl + # Stub function for m16_static1_dl (double) + .set nomips16 + .section .mips16.fn.m16_static1_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_dl +__fn_stub_m16_static1_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static32_dl +m32_static32_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static32_dl + + .align 2 + .set mips16 + .ent m16_static32_dl +m16_static32_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static32_dl + # Stub function for m16_static32_dl (double) + .set nomips16 + .section .mips16.fn.m16_static32_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_dl +__fn_stub_m16_static32_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_dl + .previous + + .align 2 + .set nomips16 + .ent m32_static16_dl +m32_static16_dl: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f0,$f12 + mfc1 $24,$f0 + j $31 + addu $2,$24,$6 + + .set macro + .set reorder + .end m32_static16_dl + + .align 2 + .set mips16 + .ent m16_static16_dl +m16_static16_dl: + .frame $sp,24,$31 # vars= 0, regs= 2/0, args= 16, gp= 0 + .mask 0x80010000,-4 + .fmask 0x00000000,0 + save 24,$16,$31 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $16,$6 + .set macro + .set reorder + + addu $2,$16 + restore 24,$16,$31 + j $31 + .end m16_static16_dl + # Stub function for m16_static16_dl (double) + .set nomips16 + .section .mips16.fn.m16_static16_dl,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_dl +__fn_stub_m16_static16_dl: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_dl + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_dl + .previous + + .align 2 + .globl m32_dlld + .set nomips16 + .ent m32_dlld +m32_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_dlld + + .align 2 + .globl m16_dlld + .set mips16 + .ent m16_dlld +m16_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_dlld + # Stub function for m16_dlld (double) + .set nomips16 + .section .mips16.fn.m16_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_dlld +__fn_stub_m16_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static_dlld +m32_static_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static_dlld + + .align 2 + .set mips16 + .ent m16_static_dlld +m16_static_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static_dlld + # Stub function for m16_static_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_dlld +__fn_stub_m16_static_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static1_dlld +m32_static1_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static1_dlld + + .align 2 + .set mips16 + .ent m16_static1_dlld +m16_static1_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static1_dlld + # Stub function for m16_static1_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static1_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_dlld +__fn_stub_m16_static1_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static32_dlld +m32_static32_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static32_dlld + + .align 2 + .set mips16 + .ent m16_static32_dlld +m16_static32_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static32_dlld + # Stub function for m16_static32_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static32_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_dlld +__fn_stub_m16_static32_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_dlld + .previous + + .align 2 + .set nomips16 + .ent m32_static16_dlld +m32_static16_dlld: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + trunc.w.d $f1,$f12 + mfc1 $4,$f1 + addu $3,$4,$6 + addu $2,$3,$7 + ldc1 $f0,16($sp) + trunc.w.d $f2,$f0 + mfc1 $24,$f2 + j $31 + addu $2,$2,$24 + + .set macro + .set reorder + .end m32_static16_dlld + + .align 2 + .set mips16 + .ent m16_static16_dlld +m16_static16_dlld: + .frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0 + .mask 0x80030000,-4 + .fmask 0x00000000,0 + save 32,$16,$17,$31 + move $16,$6 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + move $17,$7 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + addu $16,$2,$16 + .set noreorder + .set nomacro + jal __mips16_fixdfsi + addu $16,$17 + .set macro + .set reorder + + addu $2,$16,$2 + restore 32,$16,$17,$31 + j $31 + .end m16_static16_dlld + # Stub function for m16_static16_dlld (double) + .set nomips16 + .section .mips16.fn.m16_static16_dlld,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_dlld +__fn_stub_m16_static16_dlld: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_dlld + .previous + + .align 2 + .globl m32_d_l + .set nomips16 + .ent m32_d_l +m32_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_d_l + + .align 2 + .globl m16_d_l + .set mips16 + .ent m16_d_l +m16_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_floatsidf + jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_d_l + + .align 2 + .set nomips16 + .ent m32_static_d_l +m32_static_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static_d_l + + .align 2 + .set mips16 + .ent m16_static_d_l +m16_static_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_floatsidf + jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static_d_l + + .align 2 + .set nomips16 + .ent m32_static1_d_l +m32_static1_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static1_d_l + + .align 2 + .set mips16 + .ent m16_static1_d_l +m16_static1_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_floatsidf + jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static1_d_l + + .align 2 + .set nomips16 + .ent m32_static32_d_l +m32_static32_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static32_d_l + + .align 2 + .set mips16 + .ent m16_static32_d_l +m16_static32_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_floatsidf + jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static32_d_l + + .align 2 + .set nomips16 + .ent m32_static16_d_l +m32_static16_d_l: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + mtc1 $4,$f2 + j $31 + cvt.d.w $f0,$f2 + + .set macro + .set reorder + .end m32_static16_d_l + + .align 2 + .set mips16 + .ent m16_static16_d_l +m16_static16_d_l: + .frame $sp,24,$31 # vars= 0, regs= 1/0, args= 16, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 24,$31 + jal __mips16_floatsidf + jal __mips16_ret_df + restore 24,$31 + j $31 + .end m16_static16_d_l + + .align 2 + .globl m32_d_d + .set nomips16 + .ent m32_d_d +m32_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_d_d + + .align 2 + .globl m16_d_d + .set mips16 + .ent m16_d_d +m16_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_d_d + # Stub function for m16_d_d (double) + .set nomips16 + .section .mips16.fn.m16_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_d_d +__fn_stub_m16_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static_d_d +m32_static_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static_d_d + + .align 2 + .set mips16 + .ent m16_static_d_d +m16_static_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static_d_d + # Stub function for m16_static_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static_d_d +__fn_stub_m16_static_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static1_d_d +m32_static1_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static1_d_d + + .align 2 + .set mips16 + .ent m16_static1_d_d +m16_static1_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static1_d_d + # Stub function for m16_static1_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static1_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static1_d_d +__fn_stub_m16_static1_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static1_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static1_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static32_d_d +m32_static32_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static32_d_d + + .align 2 + .set mips16 + .ent m16_static32_d_d +m16_static32_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static32_d_d + # Stub function for m16_static32_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static32_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static32_d_d +__fn_stub_m16_static32_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static32_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static32_d_d + .previous + + .align 2 + .set nomips16 + .ent m32_static16_d_d +m32_static16_d_d: + .frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0 + .mask 0x00000000,0 + .fmask 0x00000000,0 + .set noreorder + .set nomacro + + j $31 + mov.d $f0,$f12 + + .set macro + .set reorder + .end m32_static16_d_d + + .align 2 + .set mips16 + .ent m16_static16_d_d +m16_static16_d_d: + .frame $sp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0 + .mask 0x80000000,-4 + .fmask 0x00000000,0 + save 8,$31 + move $3,$5 + .set noreorder + .set nomacro + jal __mips16_ret_df + move $2,$4 + .set macro + .set reorder + + restore 8,$31 + j $31 + .end m16_static16_d_d + # Stub function for m16_static16_d_d (double) + .set nomips16 + .section .mips16.fn.m16_static16_d_d,"ax",@progbits + .align 2 + .ent __fn_stub_m16_static16_d_d +__fn_stub_m16_static16_d_d: + .set noreorder + mfc1 $4,$f13 + mfc1 $5,$f12 + .set noat + la $1,m16_static16_d_d + jr $1 + .set at + nop + .set reorder + .end __fn_stub_m16_static16_d_d + .previous + + .align 2 + .globl f32 + .set nomips16 + .ent f32 +f32: + .frame $sp,64,$31 # vars= 0, regs= 3/3, args= 24, gp= 0 + .mask 0x80030000,-32 + .fmask 0x03f00000,-8 + .set noreorder + .set nomacro + + addiu $sp,$sp,-64 + sw $17,28($sp) + move $17,$4 + sw $31,32($sp) + sdc1 $f24,56($sp) + sw $16,24($sp) + sdc1 $f22,48($sp) + sdc1 $f20,40($sp) + mtc1 $7,$f22 + jal m32_static1_l + mtc1 $6,$f23 + + move $4,$17 + jal m16_static1_l + move $16,$2 + + addu $16,$16,$2 + jal m32_static1_d + mov.d $f12,$f22 + + addu $16,$16,$2 + jal m16_static1_d + mov.d $f12,$f22 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m32_static1_ld + addu $16,$16,$2 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m16_static1_ld + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m32_static1_dl + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m16_static1_dl + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + sdc1 $f22,16($sp) + mov.d $f12,$f22 + jal m32_static1_dlld + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + mov.d $f12,$f22 + sdc1 $f22,16($sp) + jal m16_static1_dlld + addu $16,$16,$2 + + move $4,$17 + jal m32_static1_d_l + addu $16,$16,$2 + + move $4,$17 + jal m16_static1_d_l + mov.d $f20,$f0 + + add.d $f20,$f20,$f0 + jal m32_static1_d_d + mov.d $f12,$f22 + + add.d $f20,$f20,$f0 + jal m16_static1_d_d + mov.d $f12,$f22 + + move $4,$17 + jal m32_static32_l + add.d $f20,$f20,$f0 + + move $4,$17 + jal m16_static32_l + addu $16,$16,$2 + + addu $16,$16,$2 + jal m32_static32_d + mov.d $f12,$f22 + + addu $16,$16,$2 + jal m16_static32_d + mov.d $f12,$f22 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m32_static32_ld + addu $16,$16,$2 + + move $4,$17 + mfc1 $7,$f22 + mfc1 $6,$f23 + jal m16_static32_ld + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m32_static32_dl + addu $16,$16,$2 + + move $6,$17 + mov.d $f12,$f22 + jal m16_static32_dl + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + sdc1 $f22,16($sp) + mov.d $f12,$f22 + jal m32_static32_dlld + addu $16,$16,$2 + + move $6,$17 + move $7,$17 + mov.d $f12,$f22 + sdc1 $f22,16($sp) + jal m16_static32_dlld + addu $16,$16,$2 + + move $4,$17 + jal m32_static32_d_l + addu $16,$16,$2 + + move $4,$17 + jal m16_static32_d_l + add.d $f20,$f20,$f0 + + add.d $f20,$f20,$f0 + jal m32_static32_d_d + mov.d $f12,$f22 + + mtc1 $16,$f24 + add.d $f20,$f20,$f0 + jal m16_static32_d_d + mov.d $f12,$f22 + + lw $31,32($sp) + lw $17,28($sp) + lw $16,24($sp) + add.d $f20,$f20,$f0 + ldc1 $f22,48($sp) + cvt.d.w $f0,$f24 + ldc1 $f24,56($sp) + add.d $f0,$f0,$f20 + ldc1 $f20,40($sp) + j $31 + addiu $sp,$sp,64 + + .set macro + .set reorder + .end f32 + + # Stub function to call m32_static1_d (double) + .set nomips16 + .section .mips16.call.m32_static1_d,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_d +__call_stub_m32_static1_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_d + .previous + + # Stub function to call m16_static1_d (double) + .set nomips16 + .section .mips16.call.m16_static1_d,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_d +__call_stub_m16_static1_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_d + .previous + + # Stub function to call m32_static1_dl (double) + .set nomips16 + .section .mips16.call.m32_static1_dl,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_dl +__call_stub_m32_static1_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_dl + .previous + + # Stub function to call m16_static1_dl (double) + .set nomips16 + .section .mips16.call.m16_static1_dl,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_dl +__call_stub_m16_static1_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_dl + .previous + + # Stub function to call m32_static1_dlld (double) + .set nomips16 + .section .mips16.call.m32_static1_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m32_static1_dlld +__call_stub_m32_static1_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static1_dlld + .previous + + # Stub function to call m16_static1_dlld (double) + .set nomips16 + .section .mips16.call.m16_static1_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m16_static1_dlld +__call_stub_m16_static1_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static1_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static1_dlld + .previous + + # Stub function to call double m32_static1_d_l () + .set nomips16 + .section .mips16.call.fp.m32_static1_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static1_d_l +__call_stub_fp_m32_static1_d_l: + .set noreorder + move $18,$31 + jal m32_static1_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static1_d_l + .previous + + # Stub function to call double m16_static1_d_l () + .set nomips16 + .section .mips16.call.fp.m16_static1_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static1_d_l +__call_stub_fp_m16_static1_d_l: + .set noreorder + move $18,$31 + jal m16_static1_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static1_d_l + .previous + + # Stub function to call double m32_static1_d_d (double) + .set nomips16 + .section .mips16.call.fp.m32_static1_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static1_d_d +__call_stub_fp_m32_static1_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m32_static1_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static1_d_d + .previous + + # Stub function to call double m16_static1_d_d (double) + .set nomips16 + .section .mips16.call.fp.m16_static1_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static1_d_d +__call_stub_fp_m16_static1_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m16_static1_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static1_d_d + .previous + + # Stub function to call m32_static16_d (double) + .set nomips16 + .section .mips16.call.m32_static16_d,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_d +__call_stub_m32_static16_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_d + .previous + + # Stub function to call m16_static16_d (double) + .set nomips16 + .section .mips16.call.m16_static16_d,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_d +__call_stub_m16_static16_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_d + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_d + .previous + + # Stub function to call m32_static16_dl (double) + .set nomips16 + .section .mips16.call.m32_static16_dl,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_dl +__call_stub_m32_static16_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_dl + .previous + + # Stub function to call m16_static16_dl (double) + .set nomips16 + .section .mips16.call.m16_static16_dl,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_dl +__call_stub_m16_static16_dl: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_dl + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_dl + .previous + + # Stub function to call m32_static16_dlld (double) + .set nomips16 + .section .mips16.call.m32_static16_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m32_static16_dlld +__call_stub_m32_static16_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m32_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m32_static16_dlld + .previous + + # Stub function to call m16_static16_dlld (double) + .set nomips16 + .section .mips16.call.m16_static16_dlld,"ax",@progbits + .align 2 + .ent __call_stub_m16_static16_dlld +__call_stub_m16_static16_dlld: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + .set noat + la $1,m16_static16_dlld + jr $1 + .set at + nop + .set reorder + .end __call_stub_m16_static16_dlld + .previous + + # Stub function to call double m32_static16_d_l () + .set nomips16 + .section .mips16.call.fp.m32_static16_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static16_d_l +__call_stub_fp_m32_static16_d_l: + .set noreorder + move $18,$31 + jal m32_static16_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static16_d_l + .previous + + # Stub function to call double m16_static16_d_l () + .set nomips16 + .section .mips16.call.fp.m16_static16_d_l,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static16_d_l +__call_stub_fp_m16_static16_d_l: + .set noreorder + move $18,$31 + jal m16_static16_d_l + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static16_d_l + .previous + + # Stub function to call double m32_static16_d_d (double) + .set nomips16 + .section .mips16.call.fp.m32_static16_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m32_static16_d_d +__call_stub_fp_m32_static16_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m32_static16_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m32_static16_d_d + .previous + + # Stub function to call double m16_static16_d_d (double) + .set nomips16 + .section .mips16.call.fp.m16_static16_d_d,"ax",@progbits + .align 2 + .ent __call_stub_fp_m16_static16_d_d +__call_stub_fp_m16_static16_d_d: + .set noreorder + mtc1 $4,$f13 + mtc1 $5,$f12 + move $18,$31 + jal m16_static16_d_d + nop + mfc1 $2,$f1 + mfc1 $3,$f0 + j $18 + nop + .set reorder + .end __call_stub_fp_m16_static16_d_d + .previous + + .align 2 + .globl f16 + .set mips16 + .ent f16 +f16: + .frame $sp,104,$31 # vars= 64, regs= 4/0, args= 24, gp= 0 + .mask 0x80070000,-4 + .fmask 0x00000000,0 + save 104,$16,$17,$18,$31 + move $17,$4 + sw $7,116($sp) + .set noreorder + .set nomacro + jal m32_static1_l + sw $6,112($sp) + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m16_static1_l + move $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m32_static1_d + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m16_static1_d + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m32_static1_ld + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m16_static1_ld + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m32_static1_dl + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m16_static1_dl + addu $16,$2 + .set macro + .set reorder + + lw $3,116($sp) + lw $6,112($sp) + sw $3,20($sp) + move $5,$3 + sw $6,16($sp) + move $4,$6 + move $7,$17 + move $6,$17 + .set noreorder + .set nomacro + jal m32_static1_dlld + addu $16,$2 + .set macro + .set reorder + + addu $16,$2 + lw $7,112($sp) + lw $2,116($sp) + move $6,$17 + move $5,$2 + sw $7,16($sp) + move $4,$7 + sw $2,20($sp) + .set noreorder + .set nomacro + jal m16_static1_dlld + move $7,$17 + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m32_static1_d_l + addu $16,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,28($sp) + .set noreorder + .set nomacro + jal m16_static1_d_l + sw $2,24($sp) + .set macro + .set reorder + + lw $5,28($sp) + lw $4,24($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,36($sp) + .set noreorder + .set nomacro + jal m32_static1_d_d + sw $2,32($sp) + .set macro + .set reorder + + lw $5,36($sp) + lw $4,32($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,44($sp) + .set noreorder + .set nomacro + jal m16_static1_d_d + sw $2,40($sp) + .set macro + .set reorder + + lw $5,44($sp) + lw $4,40($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,52($sp) + .set noreorder + .set nomacro + jal m32_static16_l + sw $2,48($sp) + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m16_static16_l + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m32_static16_d + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + .set noreorder + .set nomacro + jal m16_static16_d + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m32_static16_ld + addu $16,$2 + .set macro + .set reorder + + lw $7,116($sp) + lw $6,112($sp) + move $4,$17 + .set noreorder + .set nomacro + jal m16_static16_ld + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m32_static16_dl + addu $16,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + move $6,$17 + .set noreorder + .set nomacro + jal m16_static16_dl + addu $16,$2 + .set macro + .set reorder + + lw $4,116($sp) + lw $6,112($sp) + sw $4,20($sp) + sw $6,16($sp) + move $5,$4 + move $7,$17 + move $4,$6 + move $6,$17 + .set noreorder + .set nomacro + jal m32_static16_dlld + addu $16,$2 + .set macro + .set reorder + + addu $16,$2 + lw $3,116($sp) + lw $2,112($sp) + move $6,$17 + move $7,$17 + sw $3,20($sp) + move $5,$3 + sw $2,16($sp) + .set noreorder + .set nomacro + jal m16_static16_dlld + move $4,$2 + .set macro + .set reorder + + move $4,$17 + .set noreorder + .set nomacro + jal m32_static16_d_l + addu $16,$2 + .set macro + .set reorder + + lw $5,52($sp) + lw $4,48($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$17 + sw $3,60($sp) + .set noreorder + .set nomacro + jal m16_static16_d_l + sw $2,56($sp) + .set macro + .set reorder + + lw $5,60($sp) + lw $4,56($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,68($sp) + .set noreorder + .set nomacro + jal m32_static16_d_d + sw $2,64($sp) + .set macro + .set reorder + + lw $5,68($sp) + lw $4,64($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + lw $5,116($sp) + lw $4,112($sp) + sw $3,76($sp) + .set noreorder + .set nomacro + jal m16_static16_d_d + sw $2,72($sp) + .set macro + .set reorder + + lw $5,76($sp) + lw $4,72($sp) + move $7,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $6,$2 + .set macro + .set reorder + + move $4,$16 + sw $3,84($sp) + .set noreorder + .set nomacro + jal __mips16_floatsidf + sw $2,80($sp) + .set macro + .set reorder + + lw $7,84($sp) + lw $6,80($sp) + move $5,$3 + .set noreorder + .set nomacro + jal __mips16_adddf3 + move $4,$2 + .set macro + .set reorder + + jal __mips16_ret_df + restore 104,$16,$17,$18,$31 + j $31 + .end f16 diff --git a/gas/testsuite/gas/mips/mips16e-64.d b/gas/testsuite/gas/mips/mips16e-64.d new file mode 100644 index 000000000000..9eb098f60a2f --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-64.d @@ -0,0 +1,19 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric -mmips:16 +#as: -march=mips64 +#name: MIPS16e-64 +#source: mips16e-64.s + +# Test the 64bit instructions of mips16e. + +.*: +file format .*mips.* + +Disassembly of section .text: + +0x00000000 ecd1 sew \$4 +0x00000002 ec51 zew \$4 +0x00000004 6500 nop +0x00000006 6500 nop +0x00000008 6500 nop +0x0000000a 6500 nop +0x0000000c 6500 nop +0x0000000e 6500 nop diff --git a/gas/testsuite/gas/mips/mips16e-64.l b/gas/testsuite/gas/mips/mips16e-64.l new file mode 100644 index 000000000000..8df0c0575a51 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-64.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: opcode not supported on this processor: .* (.*) `sew' +.*: Error: opcode not supported on this processor: .* (.*) `zew' diff --git a/gas/testsuite/gas/mips/mips16e-64.s b/gas/testsuite/gas/mips/mips16e-64.s new file mode 100644 index 000000000000..39b359731442 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e-64.s @@ -0,0 +1,9 @@ +# Test the 64bit instructions of mips16e. + + .text + .set mips16 + + sew $4 + zew $4 + + .p2align 4 diff --git a/gas/testsuite/gas/mips/mips16e-save.d b/gas/testsuite/gas/mips/mips16e-save.d index 6e18d8c32060..5f836866b9bc 100644 --- a/gas/testsuite/gas/mips/mips16e-save.d +++ b/gas/testsuite/gas/mips/mips16e-save.d @@ -39,5 +39,5 @@ Disassembly of section .text: 60:[ ]+6470[ ]+restore[ ]+128,ra,s0-s1 62:[ ]+f010 6441[ ]+restore[ ]+136,ra 66:[ ]+f100 6408[ ]+restore[ ]+64,s2 - 6a:[ ]+f71b 6470[ ]+restore[ ]+128,ra,s0-s8,a0-a3 + 6a:[ ]+f71a 6470[ ]+restore[ ]+a0-a1,128,ra,s0-s8,a2-a3 6e:[ ]+6500[ ]+nop diff --git a/gas/testsuite/gas/mips/mips16e.d b/gas/testsuite/gas/mips/mips16e.d new file mode 100644 index 000000000000..53aa0d32aad6 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e.d @@ -0,0 +1,50 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS16e +#as: -32 + + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> eac0 jalrc \$2 +0+0002 <[^>]*> eac0 jalrc \$2 +0+0004 <[^>]*> e8a0 jrc \$31 +0+0006 <[^>]*> ea80 jrc \$2 +0+0008 <[^>]*> eac0 jalrc \$2 +0+000a <[^>]*> eac0 jalrc \$2 +0+000c <[^>]*> eac0 jalrc \$2 +0+000e <[^>]*> eac0 jalrc \$2 +0+0010 <[^>]*> e8a0 jrc \$31 +0+0012 <[^>]*> ea80 jrc \$2 +0+0014 <[^>]*> e8a0 jrc \$31 +0+0016 <[^>]*> ea80 jrc \$2 +0+0018 <[^>]*> eac0 jalrc \$2 +0+001a <[^>]*> 1800 0000 jal 00000000 <[^>]*> + 1a: R_MIPS16_26 foo +0+001e <[^>]*> 4281 addiu \$4,\$2,1 +0+0020 <[^>]*> eac0 jalrc \$2 +0+0022 <[^>]*> 1800 0000 jal 00000000 <[^>]*> + 22: R_MIPS16_26 foo +0+0026 <[^>]*> 6500 nop +0+0028 <[^>]*> 6782 move \$4,\$2 +0+002a <[^>]*> eac0 jalrc \$2 +0+002c <[^>]*> 6782 move \$4,\$2 +0+002e <[^>]*> ea80 jrc \$2 +0+0030 <[^>]*> 6782 move \$4,\$2 +0+0032 <[^>]*> e8a0 jrc \$31 +0+0034 <[^>]*> ec91 seb \$4 +0+0036 <[^>]*> ecb1 seh \$4 +0+0038 <[^>]*> ec11 zeb \$4 +0+003a <[^>]*> ec31 zeh \$4 +0+003c <[^>]*> 64c1 save 8,\$31 +0+003e <[^>]*> 64c0 save 128,\$31 +0+0040 <[^>]*> 64e2 save 16,\$31,\$16 +0+0042 <[^>]*> 64f2 save 16,\$31,\$16-\$17 +0+0044 <[^>]*> 64df save 120,\$31,\$17 +0+0046 <[^>]*> f010 64e1 save 136,\$31,\$16 +0+004a <[^>]*> f004 64f2 save \$4,16,\$31,\$16-\$17 +0+004e <[^>]*> f308 64e2 save \$4-\$5,16,\$31,\$16,\$18-\$20 +0+0052 <[^>]*> f30c 64f2 save \$4-\$6,16,\$31,\$16-\$20 +0+0056 <[^>]*> f70e 64d2 save \$4-\$7,16,\$31,\$17-\$30 +0+005a <[^>]*> f30a 64e2 save \$4-\$5,16,\$31,\$16,\$18-\$20,\$6-\$7 +0+005e <[^>]*> 6500 nop diff --git a/gas/testsuite/gas/mips/mips16e.s b/gas/testsuite/gas/mips/mips16e.s new file mode 100644 index 000000000000..72e2d0928fb1 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16e.s @@ -0,0 +1,58 @@ +# Test the mips16e instruction set. + + .set mips16 + .text +stuff: + # explicit compact jumps + jalrc $2 + jalrc $31,$2 + jrc $31 + jrc $2 + + # these jumps should all be converted to compact versions + jalr $2 + jalr $31,$2 + jal $2 + jal $31,$2 + jr $31 + jr $2 + j $31 + j $2 + + # make sure unconditional jumps don't swap with compact jumps + # and vice versa. + jalr $2 + .set noreorder + jal foo # mustn't swap with previous jalr + addu $4,$2,1 + .set reorder + jalr $2 + jal foo + + move $4,$2 +1: jal $2 # can't swap with move + + move $4,$2 +1: jr $2 # can't swap with move + + move $4,$2 +1: jr $31 # can't swap with move + + seb $4 + seh $4 + zeb $4 + zeh $4 + + save $31,8 + save $31,128 + save $31,$16,16 + save $31,$16-$17,16 + save $31,$17,120 + save $31,$16,136 + save $4,$31,$16-$17,16 + save $4-$5,$31,$16,$18,$19,$20,16 + save $4-$6,$31,$16-$20,16 + save $4-$7,$31,$17,$18-$30,16 + save $4-$5,$31,$16,$18,$19,$20,16,$6-$7 + + .p2align 4 diff --git a/gas/testsuite/gas/mips/mips32-dsp.d b/gas/testsuite/gas/mips/mips32-dsp.d index 486f630ac942..d538abd5abe4 100644 --- a/gas/testsuite/gas/mips/mips32-dsp.d +++ b/gas/testsuite/gas/mips/mips32-dsp.d @@ -1,7 +1,6 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: MIPS DSP ASE for MIPS32 #as: -mdsp -32 -#stderr: mips32-dsp.l # Check MIPS DSP ASE for MIPS32 Instruction Assembly @@ -38,141 +37,103 @@ Disassembly of section .text: 0+006c <[^>]*> 7c1cdf52 preceu\.ph\.qbr k1,gp 0+0070 <[^>]*> 7c1de792 preceu\.ph\.qbla gp,sp 0+0074 <[^>]*> 7c1eefd2 preceu\.ph\.qbra sp,s8 -0+0078 <[^>]*> 7cfff013 shll\.qb s8,ra,0x7 -0+007c <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0 -0+0080 <[^>]*> 7cfff013 shll\.qb s8,ra,0x7 -0+0084 <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0 -0+0088 <[^>]*> 7c20f893 shllv\.qb ra,zero,at -0+008c <[^>]*> 7de10213 shll\.ph zero,at,0xf -0+0090 <[^>]*> 7c010213 shll\.ph zero,at,0x0 -0+0094 <[^>]*> 7de10213 shll\.ph zero,at,0xf -0+0098 <[^>]*> 7c010213 shll\.ph zero,at,0x0 -0+009c <[^>]*> 7c620a93 shllv\.ph at,v0,v1 -0+00a0 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf -0+00a4 <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0 -0+00a8 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf -0+00ac <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0 -0+00b0 <[^>]*> 7ca41b93 shllv_s\.ph v1,a0,a1 -0+00b4 <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f -0+00b8 <[^>]*> 7c052513 shll_s\.w a0,a1,0x0 -0+00bc <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f -0+00c0 <[^>]*> 7c052513 shll_s\.w a0,a1,0x0 -0+00c4 <[^>]*> 7ce62d93 shllv_s\.w a1,a2,a3 -0+00c8 <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7 -0+00cc <[^>]*> 7c073053 shrl\.qb a2,a3,0x0 -0+00d0 <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7 -0+00d4 <[^>]*> 7c073053 shrl\.qb a2,a3,0x0 -0+00d8 <[^>]*> 7d2838d3 shrlv\.qb a3,t0,t1 -0+00dc <[^>]*> 7de94253 shra\.ph t0,t1,0xf -0+00e0 <[^>]*> 7c094253 shra\.ph t0,t1,0x0 -0+00e4 <[^>]*> 7de94253 shra\.ph t0,t1,0xf -0+00e8 <[^>]*> 7c094253 shra\.ph t0,t1,0x0 -0+00ec <[^>]*> 7d6a4ad3 shrav\.ph t1,t2,t3 -0+00f0 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf -0+00f4 <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0 -0+00f8 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf -0+00fc <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0 -0+0100 <[^>]*> 7dac5bd3 shrav_r\.ph t3,t4,t5 -0+0104 <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f -0+0108 <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0 -0+010c <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f -0+0110 <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0 -0+0114 <[^>]*> 7dee6dd3 shrav_r\.w t5,t6,t7 -0+0118 <[^>]*> 7df07190 muleu_s\.ph\.qbl t6,t7,s0 -0+011c <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1 -0+0120 <[^>]*> 7e3287d0 mulq_rs\.ph s0,s1,s2 -0+0124 <[^>]*> 7e538f10 muleq_s\.w\.phl s1,s2,s3 -0+0128 <[^>]*> 7e749750 muleq_s\.w\.phr s2,s3,s4 -0+012c <[^>]*> 7e7400f0 dpau\.h\.qbl \$ac0,s3,s4 -0+0130 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5 -0+0134 <[^>]*> 7eb612f0 dpsu\.h\.qbl \$ac2,s5,s6 -0+0138 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7 -0+013c <[^>]*> 7ef80130 dpaq_s\.w\.ph \$ac0,s7,t8 -0+0140 <[^>]*> 7f190970 dpsq_s\.w\.ph \$ac1,t8,t9 -0+0144 <[^>]*> 7f3a11b0 mulsaq_s\.w\.ph \$ac2,t9,k0 -0+0148 <[^>]*> 7f5b1b30 dpaq_sa\.l\.w \$ac3,k0,k1 -0+014c <[^>]*> 7f7c0370 dpsq_sa\.l\.w \$ac0,k1,gp -0+0150 <[^>]*> 7f9d0d30 maq_s\.w\.phl \$ac1,gp,sp -0+0154 <[^>]*> 7fbe15b0 maq_s\.w\.phr \$ac2,sp,s8 -0+0158 <[^>]*> 7fdf1c30 maq_sa\.w\.phl \$ac3,s8,ra -0+015c <[^>]*> 7fe004b0 maq_sa\.w\.phr \$ac0,ra,zero -0+0160 <[^>]*> 7c0106d2 bitrev zero,at -0+0164 <[^>]*> 7c41000c insv at,v0 -0+0168 <[^>]*> 7cff1092 repl\.qb v0,0xff -0+016c <[^>]*> 7c001092 repl\.qb v0,0x0 -0+0170 <[^>]*> 7cff1092 repl\.qb v0,0xff -0+0174 <[^>]*> 7c001092 repl\.qb v0,0x0 -0+0178 <[^>]*> 7c0418d2 replv\.qb v1,a0 -0+017c <[^>]*> 7dff2292 repl\.ph a0,511 -0+0180 <[^>]*> 7e002292 repl\.ph a0,-512 -0+0184 <[^>]*> 7dff2292 repl\.ph a0,511 -0+0188 <[^>]*> 7e002292 repl\.ph a0,-512 -0+018c <[^>]*> 7c062ad2 replv\.ph a1,a2 -0+0190 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3 -0+0194 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0 -0+0198 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1 -0+019c <[^>]*> 7d4b4911 cmpgu\.eq\.qb t1,t2,t3 -0+01a0 <[^>]*> 7d6c5151 cmpgu\.lt\.qb t2,t3,t4 -0+01a4 <[^>]*> 7d8d5991 cmpgu\.le\.qb t3,t4,t5 -0+01a8 <[^>]*> 7d8d0211 cmp\.eq\.ph t4,t5 -0+01ac <[^>]*> 7dae0251 cmp\.lt\.ph t5,t6 -0+01b0 <[^>]*> 7dcf0291 cmp\.le\.ph t6,t7 -0+01b4 <[^>]*> 7e1178d1 pick\.qb t7,s0,s1 -0+01b8 <[^>]*> 7e3282d1 pick\.ph s0,s1,s2 -0+01bc <[^>]*> 7e538b91 packrl\.ph s1,s2,s3 -0+01c0 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f -0+01c4 <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0 -0+01c8 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f -0+01cc <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0 -0+01d0 <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f -0+01d4 <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0 -0+01d8 <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f -0+01dc <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0 -0+01e0 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f -0+01e4 <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0 -0+01e8 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f -0+01ec <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0 -0+01f0 <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f -0+01f4 <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0 -0+01f8 <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f -0+01fc <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0 -0+0200 <[^>]*> 7ef60bf8 extrv_s\.h s6,\$ac1,s7 -0+0204 <[^>]*> 7f171078 extrv\.w s7,\$ac2,t8 -0+0208 <[^>]*> 7f381978 extrv_r\.w t8,\$ac3,t9 -0+020c <[^>]*> 7f5901f8 extrv_rs\.w t9,\$ac0,k0 -0+0210 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f -0+0214 <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0 -0+0218 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f -0+021c <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0 -0+0220 <[^>]*> 7f9b10f8 extpv k1,\$ac2,gp -0+0224 <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f -0+0228 <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0 -0+022c <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f -0+0230 <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0 -0+0234 <[^>]*> 7fdd02f8 extpdpv sp,\$ac0,s8 -0+0238 <[^>]*> 7df00eb8 shilo \$ac1,31 -0+023c <[^>]*> 7e000eb8 shilo \$ac1,-32 -0+0240 <[^>]*> 7df00eb8 shilo \$ac1,31 -0+0244 <[^>]*> 7e000eb8 shilo \$ac1,-32 -0+0248 <[^>]*> 7fc016f8 shilov \$ac2,s8 -0+024c <[^>]*> 7fe01ff8 mthlip ra,\$ac3 -0+0250 <[^>]*> 00000010 mfhi zero -0+0254 <[^>]*> 00200812 mflo at,\$ac1 -0+0258 <[^>]*> 00401011 mthi v0,\$ac2 -0+025c <[^>]*> 00601813 mtlo v1,\$ac3 -0+0260 <[^>]*> 7c81fcf8 wrdsp a0,0x3f -0+0264 <[^>]*> 7c8004f8 wrdsp a0,0x0 -0+0268 <[^>]*> 7c81fcf8 wrdsp a0,0x3f -0+026c <[^>]*> 7c8004f8 wrdsp a0,0x0 -0+0270 <[^>]*> 7cbffcf8 wrdsp a1 -0+0274 <[^>]*> 7c3f34b8 rddsp a2,0x3f -0+0278 <[^>]*> 7c0034b8 rddsp a2,0x0 -0+027c <[^>]*> 7c3f34b8 rddsp a2,0x3f -0+0280 <[^>]*> 7c0034b8 rddsp a2,0x0 -0+0284 <[^>]*> 7fff3cb8 rddsp a3 -0+0288 <[^>]*> 7d49418a lbux t0,t1\(t2\) -0+028c <[^>]*> 7d6a490a lhx t1,t2\(t3\) -0+0290 <[^>]*> 7d8b500a lwx t2,t3\(t4\) -0+0294 <[^>]*> 041cff5a bposge32 0+0000 <text_label> -0+0298 <[^>]*> 00000000 nop - ... +0+0078 <[^>]*> 7c1ff013 shll\.qb s8,ra,0x0 +0+007c <[^>]*> 7cfff013 shll\.qb s8,ra,0x7 +0+0080 <[^>]*> 7c20f893 shllv\.qb ra,zero,at +0+0084 <[^>]*> 7c010213 shll\.ph zero,at,0x0 +0+0088 <[^>]*> 7de10213 shll\.ph zero,at,0xf +0+008c <[^>]*> 7c620a93 shllv\.ph at,v0,v1 +0+0090 <[^>]*> 7c031313 shll_s\.ph v0,v1,0x0 +0+0094 <[^>]*> 7de31313 shll_s\.ph v0,v1,0xf +0+0098 <[^>]*> 7ca41b93 shllv_s\.ph v1,a0,a1 +0+009c <[^>]*> 7c052513 shll_s\.w a0,a1,0x0 +0+00a0 <[^>]*> 7fe52513 shll_s\.w a0,a1,0x1f +0+00a4 <[^>]*> 7ce62d93 shllv_s\.w a1,a2,a3 +0+00a8 <[^>]*> 7c073053 shrl\.qb a2,a3,0x0 +0+00ac <[^>]*> 7ce73053 shrl\.qb a2,a3,0x7 +0+00b0 <[^>]*> 7d2838d3 shrlv\.qb a3,t0,t1 +0+00b4 <[^>]*> 7c094253 shra\.ph t0,t1,0x0 +0+00b8 <[^>]*> 7de94253 shra\.ph t0,t1,0xf +0+00bc <[^>]*> 7d6a4ad3 shrav\.ph t1,t2,t3 +0+00c0 <[^>]*> 7c0b5353 shra_r\.ph t2,t3,0x0 +0+00c4 <[^>]*> 7deb5353 shra_r\.ph t2,t3,0xf +0+00c8 <[^>]*> 7dac5bd3 shrav_r\.ph t3,t4,t5 +0+00cc <[^>]*> 7c0d6553 shra_r\.w t4,t5,0x0 +0+00d0 <[^>]*> 7fed6553 shra_r\.w t4,t5,0x1f +0+00d4 <[^>]*> 7dee6dd3 shrav_r\.w t5,t6,t7 +0+00d8 <[^>]*> 7df07190 muleu_s\.ph\.qbl t6,t7,s0 +0+00dc <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1 +0+00e0 <[^>]*> 7e3287d0 mulq_rs\.ph s0,s1,s2 +0+00e4 <[^>]*> 7e538f10 muleq_s\.w\.phl s1,s2,s3 +0+00e8 <[^>]*> 7e749750 muleq_s\.w\.phr s2,s3,s4 +0+00ec <[^>]*> 7e7400f0 dpau\.h\.qbl \$ac0,s3,s4 +0+00f0 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5 +0+00f4 <[^>]*> 7eb612f0 dpsu\.h\.qbl \$ac2,s5,s6 +0+00f8 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7 +0+00fc <[^>]*> 7ef80130 dpaq_s\.w\.ph \$ac0,s7,t8 +0+0100 <[^>]*> 7f190970 dpsq_s\.w\.ph \$ac1,t8,t9 +0+0104 <[^>]*> 7f3a11b0 mulsaq_s\.w\.ph \$ac2,t9,k0 +0+0108 <[^>]*> 7f5b1b30 dpaq_sa\.l\.w \$ac3,k0,k1 +0+010c <[^>]*> 7f7c0370 dpsq_sa\.l\.w \$ac0,k1,gp +0+0110 <[^>]*> 7f9d0d30 maq_s\.w\.phl \$ac1,gp,sp +0+0114 <[^>]*> 7fbe15b0 maq_s\.w\.phr \$ac2,sp,s8 +0+0118 <[^>]*> 7fdf1c30 maq_sa\.w\.phl \$ac3,s8,ra +0+011c <[^>]*> 7fe004b0 maq_sa\.w\.phr \$ac0,ra,zero +0+0120 <[^>]*> 7c0106d2 bitrev zero,at +0+0124 <[^>]*> 7c41000c insv at,v0 +0+0128 <[^>]*> 7c001092 repl\.qb v0,0x0 +0+012c <[^>]*> 7cff1092 repl\.qb v0,0xff +0+0130 <[^>]*> 7c0418d2 replv\.qb v1,a0 +0+0134 <[^>]*> 7e002292 repl\.ph a0,-512 +0+0138 <[^>]*> 7dff2292 repl\.ph a0,511 +0+013c <[^>]*> 7c062ad2 replv\.ph a1,a2 +0+0140 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3 +0+0144 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0 +0+0148 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1 +0+014c <[^>]*> 7d4b4911 cmpgu\.eq\.qb t1,t2,t3 +0+0150 <[^>]*> 7d6c5151 cmpgu\.lt\.qb t2,t3,t4 +0+0154 <[^>]*> 7d8d5991 cmpgu\.le\.qb t3,t4,t5 +0+0158 <[^>]*> 7d8d0211 cmp\.eq\.ph t4,t5 +0+015c <[^>]*> 7dae0251 cmp\.lt\.ph t5,t6 +0+0160 <[^>]*> 7dcf0291 cmp\.le\.ph t6,t7 +0+0164 <[^>]*> 7e1178d1 pick\.qb t7,s0,s1 +0+0168 <[^>]*> 7e3282d1 pick\.ph s0,s1,s2 +0+016c <[^>]*> 7e538b91 packrl\.ph s1,s2,s3 +0+0170 <[^>]*> 7c120838 extr\.w s2,\$ac1,0x0 +0+0174 <[^>]*> 7ff20838 extr\.w s2,\$ac1,0x1f +0+0178 <[^>]*> 7c131138 extr_r\.w s3,\$ac2,0x0 +0+017c <[^>]*> 7ff31138 extr_r\.w s3,\$ac2,0x1f +0+0180 <[^>]*> 7c1419b8 extr_rs\.w s4,\$ac3,0x0 +0+0184 <[^>]*> 7ff419b8 extr_rs\.w s4,\$ac3,0x1f +0+0188 <[^>]*> 7c1503b8 extr_s\.h s5,\$ac0,0x0 +0+018c <[^>]*> 7ff503b8 extr_s\.h s5,\$ac0,0x1f +0+0190 <[^>]*> 7ef60bf8 extrv_s\.h s6,\$ac1,s7 +0+0194 <[^>]*> 7f171078 extrv\.w s7,\$ac2,t8 +0+0198 <[^>]*> 7f381978 extrv_r\.w t8,\$ac3,t9 +0+019c <[^>]*> 7f5901f8 extrv_rs\.w t9,\$ac0,k0 +0+01a0 <[^>]*> 7c1a08b8 extp k0,\$ac1,0x0 +0+01a4 <[^>]*> 7ffa08b8 extp k0,\$ac1,0x1f +0+01a8 <[^>]*> 7f9b10f8 extpv k1,\$ac2,gp +0+01ac <[^>]*> 7c1c1ab8 extpdp gp,\$ac3,0x0 +0+01b0 <[^>]*> 7ffc1ab8 extpdp gp,\$ac3,0x1f +0+01b4 <[^>]*> 7fdd02f8 extpdpv sp,\$ac0,s8 +0+01b8 <[^>]*> 7e000eb8 shilo \$ac1,-32 +0+01bc <[^>]*> 7df00eb8 shilo \$ac1,31 +0+01c0 <[^>]*> 7fc016f8 shilov \$ac2,s8 +0+01c4 <[^>]*> 7fe01ff8 mthlip ra,\$ac3 +0+01c8 <[^>]*> 00000010 mfhi zero +0+01cc <[^>]*> 00200812 mflo at,\$ac1 +0+01d0 <[^>]*> 00401011 mthi v0,\$ac2 +0+01d4 <[^>]*> 00601813 mtlo v1,\$ac3 +0+01d8 <[^>]*> 7c8004f8 wrdsp a0,0x0 +0+01dc <[^>]*> 7c81fcf8 wrdsp a0,0x3f +0+01e0 <[^>]*> 7cbffcf8 wrdsp a1 +0+01e4 <[^>]*> 7c0034b8 rddsp a2,0x0 +0+01e8 <[^>]*> 7c3f34b8 rddsp a2,0x3f +0+01ec <[^>]*> 7fff3cb8 rddsp a3 +0+01f0 <[^>]*> 7d49418a lbux t0,t1\(t2\) +0+01f4 <[^>]*> 7d6a490a lhx t1,t2\(t3\) +0+01f8 <[^>]*> 7d8b500a lwx t2,t3\(t4\) +0+01fc <[^>]*> 041cff80 bposge32 00000000 <text_label> +0+0200 <[^>]*> 00000000 nop + \.\.\. diff --git a/gas/testsuite/gas/mips/mips32-dsp.l b/gas/testsuite/gas/mips/mips32-dsp.l deleted file mode 100644 index c7d3e7a14cfe..000000000000 --- a/gas/testsuite/gas/mips/mips32-dsp.l +++ /dev/null @@ -1,39 +0,0 @@ -.*: Assembler messages: -.*:39: Warning: DSP immediate not in range 0..7 \([0-9]*\) -.*:42: Warning: DSP immediate not in range 0..7 \(8\) -.*:44: Warning: DSP immediate not in range 0..15 \([0-9]*\) -.*:47: Warning: DSP immediate not in range 0..15 \(16\) -.*:49: Warning: DSP immediate not in range 0..15 \([0-9]*\) -.*:52: Warning: DSP immediate not in range 0..15 \(16\) -.*:54: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:57: Warning: DSP immediate not in range 0..31 \(32\) -.*:59: Warning: DSP immediate not in range 0..7 \([0-9]*\) -.*:62: Warning: DSP immediate not in range 0..7 \(8\) -.*:64: Warning: DSP immediate not in range 0..15 \([0-9]*\) -.*:67: Warning: DSP immediate not in range 0..15 \(16\) -.*:69: Warning: DSP immediate not in range 0..15 \([0-9]*\) -.*:72: Warning: DSP immediate not in range 0..15 \(16\) -.*:74: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:77: Warning: DSP immediate not in range 0..31 \(32\) -.*:99: Warning: DSP immediate not in range 0..255 \([0-9]*\) -.*:102: Warning: DSP immediate not in range 0..255 \(256\) -.*:104: Warning: DSP immediate not in range -512..511 \(-513\) -.*:107: Warning: DSP immediate not in range -512..511 \(512\) -.*:121: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:124: Warning: DSP immediate not in range 0..31 \(32\) -.*:125: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:128: Warning: DSP immediate not in range 0..31 \(32\) -.*:129: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:132: Warning: DSP immediate not in range 0..31 \(32\) -.*:133: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:136: Warning: DSP immediate not in range 0..31 \(32\) -.*:141: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:144: Warning: DSP immediate not in range 0..31 \(32\) -.*:146: Warning: DSP immediate not in range 0..31 \([0-9]*\) -.*:149: Warning: DSP immediate not in range 0..31 \(32\) -.*:151: Warning: DSP immediate not in range -32..31 \(-33\) -.*:154: Warning: DSP immediate not in range -32..31 \(32\) -.*:161: Warning: DSP immediate not in range 0..63 \([0-9]*\) -.*:164: Warning: DSP immediate not in range 0..63 \(64\) -.*:166: Warning: DSP immediate not in range 0..63 \([0-9]*\) -.*:169: Warning: DSP immediate not in range 0..63 \(64\) diff --git a/gas/testsuite/gas/mips/mips32-dsp.s b/gas/testsuite/gas/mips/mips32-dsp.s index aa818ce85138..8c5d46cad0e9 100644 --- a/gas/testsuite/gas/mips/mips32-dsp.s +++ b/gas/testsuite/gas/mips/mips32-dsp.s @@ -1,6 +1,7 @@ # source file to test assembly of MIPS DSP ASE for MIPS32 instructions .set noreorder + .set nomacro .set noat .text @@ -36,45 +37,29 @@ text_label: preceu.ph.qbr $27,$28 preceu.ph.qbla $28,$29 preceu.ph.qbra $29,$30 - shll.qb $30,$31,-1 shll.qb $30,$31,0 shll.qb $30,$31,7 - shll.qb $30,$31,8 shllv.qb $31,$0,$1 - shll.ph $0,$1,-1 shll.ph $0,$1,0 shll.ph $0,$1,15 - shll.ph $0,$1,16 shllv.ph $1,$2,$3 - shll_s.ph $2,$3,-1 shll_s.ph $2,$3,0 shll_s.ph $2,$3,15 - shll_s.ph $2,$3,16 shllv_s.ph $3,$4,$5 - shll_s.w $4,$5,-1 shll_s.w $4,$5,0 shll_s.w $4,$5,31 - shll_s.w $4,$5,32 shllv_s.w $5,$6,$7 - shrl.qb $6,$7,-1 shrl.qb $6,$7,0 shrl.qb $6,$7,7 - shrl.qb $6,$7,8 shrlv.qb $7,$8,$9 - shra.ph $8,$9,-1 shra.ph $8,$9,0 shra.ph $8,$9,15 - shra.ph $8,$9,16 shrav.ph $9,$10,$11 - shra_r.ph $10,$11,-1 shra_r.ph $10,$11,0 shra_r.ph $10,$11,15 - shra_r.ph $10,$11,16 shrav_r.ph $11,$12,$13 - shra_r.w $12,$13,-1 shra_r.w $12,$13,0 shra_r.w $12,$13,31 - shra_r.w $12,$13,32 shrav_r.w $13,$14,$15 muleu_s.ph.qbl $14,$15,$16 muleu_s.ph.qbr $15,$16,$17 @@ -96,15 +81,11 @@ text_label: maq_sa.w.phr $ac0,$31,$0 bitrev $0,$1 insv $1,$2 - repl.qb $2,-1 repl.qb $2,0 repl.qb $2,255 - repl.qb $2,256 replv.qb $3,$4 - repl.ph $4,-513 repl.ph $4,-512 repl.ph $4,511 - repl.ph $4,512 replv.ph $5,$6 cmpu.eq.qb $6,$7 cmpu.lt.qb $7,$8 @@ -118,55 +99,37 @@ text_label: pick.qb $15,$16,$17 pick.ph $16,$17,$18 packrl.ph $17,$18,$19 - extr.w $18,$ac1,-1 extr.w $18,$ac1,0 extr.w $18,$ac1,31 - extr.w $18,$ac1,32 - extr_r.w $19,$ac2,-1 extr_r.w $19,$ac2,0 extr_r.w $19,$ac2,31 - extr_r.w $19,$ac2,32 - extr_rs.w $20,$ac3,-1 extr_rs.w $20,$ac3,0 extr_rs.w $20,$ac3,31 - extr_rs.w $20,$ac3,32 - extr_s.h $21,$ac0,-1 extr_s.h $21,$ac0,0 extr_s.h $21,$ac0,31 - extr_s.h $21,$ac0,32 extrv_s.h $22,$ac1,$23 extrv.w $23,$ac2,$24 extrv_r.w $24,$ac3,$25 extrv_rs.w $25,$ac0,$26 - extp $26,$ac1,-1 extp $26,$ac1,0 extp $26,$ac1,31 - extp $26,$ac1,32 extpv $27,$ac2,$28 - extpdp $28,$ac3,-1 extpdp $28,$ac3,0 extpdp $28,$ac3,31 - extpdp $28,$ac3,32 extpdpv $29,$ac0,$30 - shilo $ac1,-33 shilo $ac1,-32 shilo $ac1,31 - shilo $ac1,32 shilov $ac2,$30 mthlip $31,$ac3 mfhi $0,$ac0 mflo $1,$ac1 mthi $2,$ac2 mtlo $3,$ac3 - wrdsp $4,-1 wrdsp $4,0 wrdsp $4,63 - wrdsp $4,64 wrdsp $5 - rddsp $6,-1 rddsp $6,0 rddsp $6,63 - rddsp $6,64 rddsp $7 lbux $8,$9($10) lhx $9,$10($11) diff --git a/gas/testsuite/gas/mips/mips32-dspr2.d b/gas/testsuite/gas/mips/mips32-dspr2.d new file mode 100644 index 000000000000..90c20ef711c3 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32-dspr2.d @@ -0,0 +1,72 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS DSP ASE Rev2 for MIPS32 +#as: -mdspr2 -32 + +# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 7c010052 absq_s\.qb zero,at +0+0004 <[^>]*> 7c430a10 addu\.ph at,v0,v1 +0+0008 <[^>]*> 7c641310 addu_s\.ph v0,v1,a0 +0+000c <[^>]*> 7c851818 adduh\.qb v1,a0,a1 +0+0010 <[^>]*> 7ca62098 adduh_r\.qb a0,a1,a2 +0+0014 <[^>]*> 7cc50031 append a1,a2,0x0 +0+0018 <[^>]*> 7cc5f831 append a1,a2,0x1f +0+001c <[^>]*> 00000000 nop +0+0020 <[^>]*> 7ce60c31 balign a2,a3,0x1 +0+0024 <[^>]*> 7cc73391 packrl.ph a2,a2,a3 +0+0028 <[^>]*> 7ce61c31 balign a2,a3,0x3 +0+002c <[^>]*> 7ce83611 cmpgdu\.eq\.qb a2,a3,t0 +0+0030 <[^>]*> 7d093e51 cmpgdu\.lt\.qb a3,t0,t1 +0+0034 <[^>]*> 7d2a4691 cmpgdu\.le\.qb t0,t1,t2 +0+0038 <[^>]*> 7d2a0030 dpa\.w\.ph \$ac0,t1,t2 +0+003c <[^>]*> 7d4b0870 dps\.w\.ph \$ac1,t2,t3 +0+0040 <[^>]*> 716c1000 madd \$ac2,t3,t4 +0+0044 <[^>]*> 718d1801 maddu \$ac3,t4,t5 +0+0048 <[^>]*> 71ae0004 msub t5,t6 +0+004c <[^>]*> 71cf0805 msubu \$ac1,t6,t7 +0+0050 <[^>]*> 7e117b18 mul\.ph t7,s0,s1 +0+0054 <[^>]*> 7e328398 mul_s\.ph s0,s1,s2 +0+0058 <[^>]*> 7e538dd8 mulq_rs\.w s1,s2,s3 +0+005c <[^>]*> 7e749790 mulq_s\.ph s2,s3,s4 +0+0060 <[^>]*> 7e959d98 mulq_s\.w s3,s4,s5 +0+0064 <[^>]*> 7e9510b0 mulsa\.w\.ph \$ac2,s4,s5 +0+0068 <[^>]*> 02b61818 mult \$ac3,s5,s6 +0+006c <[^>]*> 02d70019 multu s6,s7 +0+0070 <[^>]*> 7f19bb51 precr\.qb\.ph s7,t8,t9 +0+0074 <[^>]*> 7f380791 precr_sra\.ph\.w t8,t9,0x0 +0+0078 <[^>]*> 7f38ff91 precr_sra\.ph\.w t8,t9,0x1f +0+007c <[^>]*> 7f5907d1 precr_sra_r\.ph\.w t9,k0,0x0 +0+0080 <[^>]*> 7f59ffd1 precr_sra_r\.ph\.w t9,k0,0x1f +0+0084 <[^>]*> 7f7a0071 prepend k0,k1,0x0 +0+0088 <[^>]*> 7f7af871 prepend k0,k1,0x1f +0+008c <[^>]*> 7c1cd913 shra\.qb k1,gp,0x0 +0+0090 <[^>]*> 7cfcd913 shra\.qb k1,gp,0x7 +0+0094 <[^>]*> 7c1de153 shra_r\.qb gp,sp,0x0 +0+0098 <[^>]*> 7cfde153 shra_r\.qb gp,sp,0x7 +0+009c <[^>]*> 7ffee993 shrav\.qb sp,s8,ra +0+00a0 <[^>]*> 7c1ff1d3 shrav_r\.qb s8,ra,zero +0+00a4 <[^>]*> 7c00fe53 shrl\.ph ra,zero,0x0 +0+00a8 <[^>]*> 7de0fe53 shrl\.ph ra,zero,0xf +0+00ac <[^>]*> 7c4106d3 shrlv\.ph zero,at,v0 +0+00b0 <[^>]*> 7c430a50 subu\.ph at,v0,v1 +0+00b4 <[^>]*> 7c641350 subu_s\.ph v0,v1,a0 +0+00b8 <[^>]*> 7c851858 subuh\.qb v1,a0,a1 +0+00bc <[^>]*> 7ca620d8 subuh_r\.qb a0,a1,a2 +0+00c0 <[^>]*> 7cc72a18 addqh\.ph a1,a2,a3 +0+00c4 <[^>]*> 7ce83298 addqh_r\.ph a2,a3,t0 +0+00c8 <[^>]*> 7d093c18 addqh\.w a3,t0,t1 +0+00cc <[^>]*> 7d2a4498 addqh_r\.w t0,t1,t2 +0+00d0 <[^>]*> 7d4b4a58 subqh\.ph t1,t2,t3 +0+00d4 <[^>]*> 7d6c52d8 subqh_r\.ph t2,t3,t4 +0+00d8 <[^>]*> 7d8d5c58 subqh\.w t3,t4,t5 +0+00dc <[^>]*> 7dae64d8 subqh_r\.w t4,t5,t6 +0+00e0 <[^>]*> 7dae0a30 dpax\.w\.ph \$ac1,t5,t6 +0+00e4 <[^>]*> 7dcf1270 dpsx\.w\.ph \$ac2,t6,t7 +0+00e8 <[^>]*> 7df01e30 dpaqx_s\.w\.ph \$ac3,t7,s0 +0+00ec <[^>]*> 7e1106b0 dpaqx_sa\.w\.ph \$ac0,s0,s1 +0+00f0 <[^>]*> 7e320e70 dpsqx_s\.w\.ph \$ac1,s1,s2 +0+00f4 <[^>]*> 7e5316f0 dpsqx_sa\.w\.ph \$ac2,s2,s3 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips32-dspr2.s b/gas/testsuite/gas/mips/mips32-dspr2.s new file mode 100644 index 000000000000..e22d79807292 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32-dspr2.s @@ -0,0 +1,73 @@ +# source file to test assembly of MIPS DSP ASE Rev2 for MIPS32 instructions + + .set noreorder + .set noat + + .text +text_label: + + absq_s.qb $0,$1 + addu.ph $1,$2,$3 + addu_s.ph $2,$3,$4 + adduh.qb $3,$4,$5 + adduh_r.qb $4,$5,$6 + append $5,$6,0 + append $5,$6,31 + balign $6,$7,0 + balign $6,$7,1 + balign $6,$7,2 + balign $6,$7,3 + cmpgdu.eq.qb $6,$7,$8 + cmpgdu.lt.qb $7,$8,$9 + cmpgdu.le.qb $8,$9,$10 + dpa.w.ph $ac0,$9,$10 + dps.w.ph $ac1,$10,$11 + madd $ac2,$11,$12 + maddu $ac3,$12,$13 + msub $ac0,$13,$14 + msubu $ac1,$14,$15 + mul.ph $15,$16,$17 + mul_s.ph $16,$17,$18 + mulq_rs.w $17,$18,$19 + mulq_s.ph $18,$19,$20 + mulq_s.w $19,$20,$21 + mulsa.w.ph $ac2,$20,$21 + mult $ac3,$21,$22 + multu $ac0,$22,$23 + precr.qb.ph $23,$24,$25 + precr_sra.ph.w $24,$25,0 + precr_sra.ph.w $24,$25,31 + precr_sra_r.ph.w $25,$26,0 + precr_sra_r.ph.w $25,$26,31 + prepend $26,$27,0 + prepend $26,$27,31 + shra.qb $27,$28,0 + shra.qb $27,$28,7 + shra_r.qb $28,$29,0 + shra_r.qb $28,$29,7 + shrav.qb $29,$30,$31 + shrav_r.qb $30,$31,$0 + shrl.ph $31,$0,0 + shrl.ph $31,$0,15 + shrlv.ph $0,$1,$2 + subu.ph $1,$2,$3 + subu_s.ph $2,$3,$4 + subuh.qb $3,$4,$5 + subuh_r.qb $4,$5,$6 + addqh.ph $5,$6,$7 + addqh_r.ph $6,$7,$8 + addqh.w $7,$8,$9 + addqh_r.w $8,$9,$10 + subqh.ph $9,$10,$11 + subqh_r.ph $10,$11,$12 + subqh.w $11,$12,$13 + subqh_r.w $12,$13,$14 + dpax.w.ph $ac1,$13,$14 + dpsx.w.ph $ac2,$14,$15 + dpaqx_s.w.ph $ac3,$15,$16 + dpaqx_sa.w.ph $ac0,$16,$17 + dpsqx_s.w.ph $ac1,$17,$18 + dpsqx_sa.w.ph $ac2,$18,$19 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/mips32-mt.d b/gas/testsuite/gas/mips/mips32-mt.d index ffb3e975362e..c64073271b33 100644 --- a/gas/testsuite/gas/mips/mips32-mt.d +++ b/gas/testsuite/gas/mips/mips32-mt.d @@ -567,260 +567,68 @@ Disassembly of section .text: 0+08b0 <[^>]*> 418a5824 mttc2 t2,\$11 0+08b4 <[^>]*> 418b6034 mtthc2 t3,\$12 0+08b8 <[^>]*> 418c6825 cttc2 t4,\$13 -0+08bc <[^>]*> 410e6830 mftr t5,t6,1,0,1 -0+08c0 <[^>]*> 410e6831 mftr t5,t6,1,1,1 -0+08c4 <[^>]*> 410e6832 mfthc1 t5,\$f14 -0+08c8 <[^>]*> 410e6833 mftr t5,t6,1,3,1 -0+08cc <[^>]*> 410e6834 mfthc2 t5,\$14 -0+08d0 <[^>]*> 410e6835 mftr t5,t6,1,5,1 -0+08d4 <[^>]*> 410e6836 mftr t5,t6,1,6,1 -0+08d8 <[^>]*> 410e6837 mftr t5,t6,1,7,1 -0+08dc <[^>]*> 410e6820 mftgpr t5,t6 -0+08e0 <[^>]*> 410e6821 mftacx t5,\$ac3 -0+08e4 <[^>]*> 410e6822 mftc1 t5,\$f14 -0+08e8 <[^>]*> 410e6823 cftc1 t5,\$14 -0+08ec <[^>]*> 410e6824 mftc2 t5,\$14 -0+08f0 <[^>]*> 410e6825 cftc2 t5,\$14 -0+08f4 <[^>]*> 410e6826 mftr t5,t6,1,6,0 -0+08f8 <[^>]*> 410e6827 mftr t5,t6,1,7,0 -0+08fc <[^>]*> 410e6830 mftr t5,t6,1,0,1 -0+0900 <[^>]*> 410e6831 mftr t5,t6,1,1,1 -0+0904 <[^>]*> 410e6832 mfthc1 t5,\$f14 -0+0908 <[^>]*> 410e6833 mftr t5,t6,1,3,1 -0+090c <[^>]*> 410e6834 mfthc2 t5,\$14 -0+0910 <[^>]*> 410e6835 mftr t5,t6,1,5,1 -0+0914 <[^>]*> 410e6836 mftr t5,t6,1,6,1 -0+0918 <[^>]*> 410e6837 mftr t5,t6,1,7,1 -0+091c <[^>]*> 410e6820 mftgpr t5,t6 -0+0920 <[^>]*> 410e6821 mftacx t5,\$ac3 -0+0924 <[^>]*> 410e6822 mftc1 t5,\$f14 -0+0928 <[^>]*> 410e6823 cftc1 t5,\$14 -0+092c <[^>]*> 410e6824 mftc2 t5,\$14 -0+0930 <[^>]*> 410e6825 cftc2 t5,\$14 -0+0934 <[^>]*> 410e6826 mftr t5,t6,1,6,0 -0+0938 <[^>]*> 410e6827 mftr t5,t6,1,7,0 -0+093c <[^>]*> 410e6810 mftr t5,t6,0,0,1 -0+0940 <[^>]*> 410e6811 mftr t5,t6,0,1,1 -0+0944 <[^>]*> 410e6812 mftr t5,t6,0,2,1 -0+0948 <[^>]*> 410e6813 mftr t5,t6,0,3,1 -0+094c <[^>]*> 410e6814 mftr t5,t6,0,4,1 -0+0950 <[^>]*> 410e6815 mftr t5,t6,0,5,1 -0+0954 <[^>]*> 410e6816 mftr t5,t6,0,6,1 -0+0958 <[^>]*> 410e6817 mftr t5,t6,0,7,1 -0+095c <[^>]*> 410e6800 mftc0 t5,c0_epc -0+0960 <[^>]*> 410e6801 mftc0 t5,\$14,1 -0+0964 <[^>]*> 410e6802 mftc0 t5,\$14,2 -0+0968 <[^>]*> 410e6803 mftc0 t5,\$14,3 -0+096c <[^>]*> 410e6804 mftc0 t5,\$14,4 -0+0970 <[^>]*> 410e6805 mftc0 t5,\$14,5 -0+0974 <[^>]*> 410e6806 mftc0 t5,\$14,6 -0+0978 <[^>]*> 410e6807 mftc0 t5,\$14,7 -0+097c <[^>]*> 410e6810 mftr t5,t6,0,0,1 -0+0980 <[^>]*> 410e6811 mftr t5,t6,0,1,1 -0+0984 <[^>]*> 410e6812 mftr t5,t6,0,2,1 -0+0988 <[^>]*> 410e6813 mftr t5,t6,0,3,1 -0+098c <[^>]*> 410e6814 mftr t5,t6,0,4,1 -0+0990 <[^>]*> 410e6815 mftr t5,t6,0,5,1 -0+0994 <[^>]*> 410e6816 mftr t5,t6,0,6,1 -0+0998 <[^>]*> 410e6817 mftr t5,t6,0,7,1 -0+099c <[^>]*> 410e6800 mftc0 t5,c0_epc -0+09a0 <[^>]*> 410e6801 mftc0 t5,\$14,1 -0+09a4 <[^>]*> 410e6802 mftc0 t5,\$14,2 -0+09a8 <[^>]*> 410e6803 mftc0 t5,\$14,3 -0+09ac <[^>]*> 410e6804 mftc0 t5,\$14,4 -0+09b0 <[^>]*> 410e6805 mftc0 t5,\$14,5 -0+09b4 <[^>]*> 410e6806 mftc0 t5,\$14,6 -0+09b8 <[^>]*> 410e6807 mftc0 t5,\$14,7 -0+09bc <[^>]*> 410e6830 mftr t5,t6,1,0,1 -0+09c0 <[^>]*> 410e6831 mftr t5,t6,1,1,1 -0+09c4 <[^>]*> 410e6832 mfthc1 t5,\$f14 -0+09c8 <[^>]*> 410e6833 mftr t5,t6,1,3,1 -0+09cc <[^>]*> 410e6834 mfthc2 t5,\$14 -0+09d0 <[^>]*> 410e6835 mftr t5,t6,1,5,1 -0+09d4 <[^>]*> 410e6836 mftr t5,t6,1,6,1 -0+09d8 <[^>]*> 410e6837 mftr t5,t6,1,7,1 -0+09dc <[^>]*> 410e6820 mftgpr t5,t6 -0+09e0 <[^>]*> 410e6821 mftacx t5,\$ac3 -0+09e4 <[^>]*> 410e6822 mftc1 t5,\$f14 -0+09e8 <[^>]*> 410e6823 cftc1 t5,\$14 -0+09ec <[^>]*> 410e6824 mftc2 t5,\$14 -0+09f0 <[^>]*> 410e6825 cftc2 t5,\$14 -0+09f4 <[^>]*> 410e6826 mftr t5,t6,1,6,0 -0+09f8 <[^>]*> 410e6827 mftr t5,t6,1,7,0 -0+09fc <[^>]*> 410e6830 mftr t5,t6,1,0,1 -0+0a00 <[^>]*> 410e6831 mftr t5,t6,1,1,1 -0+0a04 <[^>]*> 410e6832 mfthc1 t5,\$f14 -0+0a08 <[^>]*> 410e6833 mftr t5,t6,1,3,1 -0+0a0c <[^>]*> 410e6834 mfthc2 t5,\$14 -0+0a10 <[^>]*> 410e6835 mftr t5,t6,1,5,1 -0+0a14 <[^>]*> 410e6836 mftr t5,t6,1,6,1 -0+0a18 <[^>]*> 410e6837 mftr t5,t6,1,7,1 -0+0a1c <[^>]*> 410e6820 mftgpr t5,t6 -0+0a20 <[^>]*> 410e6821 mftacx t5,\$ac3 -0+0a24 <[^>]*> 410e6822 mftc1 t5,\$f14 -0+0a28 <[^>]*> 410e6823 cftc1 t5,\$14 -0+0a2c <[^>]*> 410e6824 mftc2 t5,\$14 -0+0a30 <[^>]*> 410e6825 cftc2 t5,\$14 -0+0a34 <[^>]*> 410e6826 mftr t5,t6,1,6,0 -0+0a38 <[^>]*> 410e6827 mftr t5,t6,1,7,0 -0+0a3c <[^>]*> 410e6810 mftr t5,t6,0,0,1 -0+0a40 <[^>]*> 410e6811 mftr t5,t6,0,1,1 -0+0a44 <[^>]*> 410e6812 mftr t5,t6,0,2,1 -0+0a48 <[^>]*> 410e6813 mftr t5,t6,0,3,1 -0+0a4c <[^>]*> 410e6814 mftr t5,t6,0,4,1 -0+0a50 <[^>]*> 410e6815 mftr t5,t6,0,5,1 -0+0a54 <[^>]*> 410e6816 mftr t5,t6,0,6,1 -0+0a58 <[^>]*> 410e6817 mftr t5,t6,0,7,1 -0+0a5c <[^>]*> 410e6800 mftc0 t5,c0_epc -0+0a60 <[^>]*> 410e6801 mftc0 t5,\$14,1 -0+0a64 <[^>]*> 410e6802 mftc0 t5,\$14,2 -0+0a68 <[^>]*> 410e6803 mftc0 t5,\$14,3 -0+0a6c <[^>]*> 410e6804 mftc0 t5,\$14,4 -0+0a70 <[^>]*> 410e6805 mftc0 t5,\$14,5 -0+0a74 <[^>]*> 410e6806 mftc0 t5,\$14,6 -0+0a78 <[^>]*> 410e6807 mftc0 t5,\$14,7 -0+0a7c <[^>]*> 410e6810 mftr t5,t6,0,0,1 -0+0a80 <[^>]*> 410e6811 mftr t5,t6,0,1,1 -0+0a84 <[^>]*> 410e6812 mftr t5,t6,0,2,1 -0+0a88 <[^>]*> 410e6813 mftr t5,t6,0,3,1 -0+0a8c <[^>]*> 410e6814 mftr t5,t6,0,4,1 -0+0a90 <[^>]*> 410e6815 mftr t5,t6,0,5,1 -0+0a94 <[^>]*> 410e6816 mftr t5,t6,0,6,1 -0+0a98 <[^>]*> 410e6817 mftr t5,t6,0,7,1 -0+0a9c <[^>]*> 410e6800 mftc0 t5,c0_epc -0+0aa0 <[^>]*> 410e6801 mftc0 t5,\$14,1 -0+0aa4 <[^>]*> 410e6802 mftc0 t5,\$14,2 -0+0aa8 <[^>]*> 410e6803 mftc0 t5,\$14,3 -0+0aac <[^>]*> 410e6804 mftc0 t5,\$14,4 -0+0ab0 <[^>]*> 410e6805 mftc0 t5,\$14,5 -0+0ab4 <[^>]*> 410e6806 mftc0 t5,\$14,6 -0+0ab8 <[^>]*> 410e6807 mftc0 t5,\$14,7 -0+0abc <[^>]*> 418d7030 mttr t5,t6,1,0,1 -0+0ac0 <[^>]*> 418d7031 mttr t5,t6,1,1,1 -0+0ac4 <[^>]*> 418d7032 mtthc1 t5,\$f14 -0+0ac8 <[^>]*> 418d7033 mttr t5,t6,1,3,1 -0+0acc <[^>]*> 418d7034 mtthc2 t5,\$14 -0+0ad0 <[^>]*> 418d7035 mttr t5,t6,1,5,1 -0+0ad4 <[^>]*> 418d7036 mttr t5,t6,1,6,1 -0+0ad8 <[^>]*> 418d7037 mttr t5,t6,1,7,1 -0+0adc <[^>]*> 418d7020 mttgpr t5,t6 -0+0ae0 <[^>]*> 418d7021 mttacx t5,\$ac3 -0+0ae4 <[^>]*> 418d7022 mttc1 t5,\$f14 -0+0ae8 <[^>]*> 418d7023 cttc1 t5,\$14 -0+0aec <[^>]*> 418d7024 mttc2 t5,\$14 -0+0af0 <[^>]*> 418d7025 cttc2 t5,\$14 -0+0af4 <[^>]*> 418d7026 mttr t5,t6,1,6,0 -0+0af8 <[^>]*> 418d7027 mttr t5,t6,1,7,0 -0+0afc <[^>]*> 418d7030 mttr t5,t6,1,0,1 -0+0b00 <[^>]*> 418d7031 mttr t5,t6,1,1,1 -0+0b04 <[^>]*> 418d7032 mtthc1 t5,\$f14 -0+0b08 <[^>]*> 418d7033 mttr t5,t6,1,3,1 -0+0b0c <[^>]*> 418d7034 mtthc2 t5,\$14 -0+0b10 <[^>]*> 418d7035 mttr t5,t6,1,5,1 -0+0b14 <[^>]*> 418d7036 mttr t5,t6,1,6,1 -0+0b18 <[^>]*> 418d7037 mttr t5,t6,1,7,1 -0+0b1c <[^>]*> 418d7020 mttgpr t5,t6 -0+0b20 <[^>]*> 418d7021 mttacx t5,\$ac3 -0+0b24 <[^>]*> 418d7022 mttc1 t5,\$f14 -0+0b28 <[^>]*> 418d7023 cttc1 t5,\$14 -0+0b2c <[^>]*> 418d7024 mttc2 t5,\$14 -0+0b30 <[^>]*> 418d7025 cttc2 t5,\$14 -0+0b34 <[^>]*> 418d7026 mttr t5,t6,1,6,0 -0+0b38 <[^>]*> 418d7027 mttr t5,t6,1,7,0 -0+0b3c <[^>]*> 418d7010 mttr t5,t6,0,0,1 -0+0b40 <[^>]*> 418d7011 mttr t5,t6,0,1,1 -0+0b44 <[^>]*> 418d7012 mttr t5,t6,0,2,1 -0+0b48 <[^>]*> 418d7013 mttr t5,t6,0,3,1 -0+0b4c <[^>]*> 418d7014 mttr t5,t6,0,4,1 -0+0b50 <[^>]*> 418d7015 mttr t5,t6,0,5,1 -0+0b54 <[^>]*> 418d7016 mttr t5,t6,0,6,1 -0+0b58 <[^>]*> 418d7017 mttr t5,t6,0,7,1 -0+0b5c <[^>]*> 418d7000 mttc0 t5,c0_epc -0+0b60 <[^>]*> 418d7001 mttc0 t5,\$14,1 -0+0b64 <[^>]*> 418d7002 mttc0 t5,\$14,2 -0+0b68 <[^>]*> 418d7003 mttc0 t5,\$14,3 -0+0b6c <[^>]*> 418d7004 mttc0 t5,\$14,4 -0+0b70 <[^>]*> 418d7005 mttc0 t5,\$14,5 -0+0b74 <[^>]*> 418d7006 mttc0 t5,\$14,6 -0+0b78 <[^>]*> 418d7007 mttc0 t5,\$14,7 -0+0b7c <[^>]*> 418d7010 mttr t5,t6,0,0,1 -0+0b80 <[^>]*> 418d7011 mttr t5,t6,0,1,1 -0+0b84 <[^>]*> 418d7012 mttr t5,t6,0,2,1 -0+0b88 <[^>]*> 418d7013 mttr t5,t6,0,3,1 -0+0b8c <[^>]*> 418d7014 mttr t5,t6,0,4,1 -0+0b90 <[^>]*> 418d7015 mttr t5,t6,0,5,1 -0+0b94 <[^>]*> 418d7016 mttr t5,t6,0,6,1 -0+0b98 <[^>]*> 418d7017 mttr t5,t6,0,7,1 -0+0b9c <[^>]*> 418d7000 mttc0 t5,c0_epc -0+0ba0 <[^>]*> 418d7001 mttc0 t5,\$14,1 -0+0ba4 <[^>]*> 418d7002 mttc0 t5,\$14,2 -0+0ba8 <[^>]*> 418d7003 mttc0 t5,\$14,3 -0+0bac <[^>]*> 418d7004 mttc0 t5,\$14,4 -0+0bb0 <[^>]*> 418d7005 mttc0 t5,\$14,5 -0+0bb4 <[^>]*> 418d7006 mttc0 t5,\$14,6 -0+0bb8 <[^>]*> 418d7007 mttc0 t5,\$14,7 -0+0bbc <[^>]*> 418d7030 mttr t5,t6,1,0,1 -0+0bc0 <[^>]*> 418d7031 mttr t5,t6,1,1,1 -0+0bc4 <[^>]*> 418d7032 mtthc1 t5,\$f14 -0+0bc8 <[^>]*> 418d7033 mttr t5,t6,1,3,1 -0+0bcc <[^>]*> 418d7034 mtthc2 t5,\$14 -0+0bd0 <[^>]*> 418d7035 mttr t5,t6,1,5,1 -0+0bd4 <[^>]*> 418d7036 mttr t5,t6,1,6,1 -0+0bd8 <[^>]*> 418d7037 mttr t5,t6,1,7,1 -0+0bdc <[^>]*> 418d7020 mttgpr t5,t6 -0+0be0 <[^>]*> 418d7021 mttacx t5,\$ac3 -0+0be4 <[^>]*> 418d7022 mttc1 t5,\$f14 -0+0be8 <[^>]*> 418d7023 cttc1 t5,\$14 -0+0bec <[^>]*> 418d7024 mttc2 t5,\$14 -0+0bf0 <[^>]*> 418d7025 cttc2 t5,\$14 -0+0bf4 <[^>]*> 418d7026 mttr t5,t6,1,6,0 -0+0bf8 <[^>]*> 418d7027 mttr t5,t6,1,7,0 -0+0bfc <[^>]*> 418d7030 mttr t5,t6,1,0,1 -0+0c00 <[^>]*> 418d7031 mttr t5,t6,1,1,1 -0+0c04 <[^>]*> 418d7032 mtthc1 t5,\$f14 -0+0c08 <[^>]*> 418d7033 mttr t5,t6,1,3,1 -0+0c0c <[^>]*> 418d7034 mtthc2 t5,\$14 -0+0c10 <[^>]*> 418d7035 mttr t5,t6,1,5,1 -0+0c14 <[^>]*> 418d7036 mttr t5,t6,1,6,1 -0+0c18 <[^>]*> 418d7037 mttr t5,t6,1,7,1 -0+0c1c <[^>]*> 418d7020 mttgpr t5,t6 -0+0c20 <[^>]*> 418d7021 mttacx t5,\$ac3 -0+0c24 <[^>]*> 418d7022 mttc1 t5,\$f14 -0+0c28 <[^>]*> 418d7023 cttc1 t5,\$14 -0+0c2c <[^>]*> 418d7024 mttc2 t5,\$14 -0+0c30 <[^>]*> 418d7025 cttc2 t5,\$14 -0+0c34 <[^>]*> 418d7026 mttr t5,t6,1,6,0 -0+0c38 <[^>]*> 418d7027 mttr t5,t6,1,7,0 -0+0c3c <[^>]*> 418d7010 mttr t5,t6,0,0,1 -0+0c40 <[^>]*> 418d7011 mttr t5,t6,0,1,1 -0+0c44 <[^>]*> 418d7012 mttr t5,t6,0,2,1 -0+0c48 <[^>]*> 418d7013 mttr t5,t6,0,3,1 -0+0c4c <[^>]*> 418d7014 mttr t5,t6,0,4,1 -0+0c50 <[^>]*> 418d7015 mttr t5,t6,0,5,1 -0+0c54 <[^>]*> 418d7016 mttr t5,t6,0,6,1 -0+0c58 <[^>]*> 418d7017 mttr t5,t6,0,7,1 -0+0c5c <[^>]*> 418d7000 mttc0 t5,c0_epc -0+0c60 <[^>]*> 418d7001 mttc0 t5,\$14,1 -0+0c64 <[^>]*> 418d7002 mttc0 t5,\$14,2 -0+0c68 <[^>]*> 418d7003 mttc0 t5,\$14,3 -0+0c6c <[^>]*> 418d7004 mttc0 t5,\$14,4 -0+0c70 <[^>]*> 418d7005 mttc0 t5,\$14,5 -0+0c74 <[^>]*> 418d7006 mttc0 t5,\$14,6 -0+0c78 <[^>]*> 418d7007 mttc0 t5,\$14,7 -0+0c7c <[^>]*> 418d7010 mttr t5,t6,0,0,1 -0+0c80 <[^>]*> 418d7011 mttr t5,t6,0,1,1 -0+0c84 <[^>]*> 418d7012 mttr t5,t6,0,2,1 -0+0c88 <[^>]*> 418d7013 mttr t5,t6,0,3,1 -0+0c8c <[^>]*> 418d7014 mttr t5,t6,0,4,1 -0+0c90 <[^>]*> 418d7015 mttr t5,t6,0,5,1 -0+0c94 <[^>]*> 418d7016 mttr t5,t6,0,6,1 -0+0c98 <[^>]*> 418d7017 mttr t5,t6,0,7,1 -0+0c9c <[^>]*> 418d7000 mttc0 t5,c0_epc -0+0ca0 <[^>]*> 418d7001 mttc0 t5,\$14,1 -0+0ca4 <[^>]*> 418d7002 mttc0 t5,\$14,2 -0+0ca8 <[^>]*> 418d7003 mttc0 t5,\$14,3 -0+0cac <[^>]*> 418d7004 mttc0 t5,\$14,4 -0+0cb0 <[^>]*> 418d7005 mttc0 t5,\$14,5 -0+0cb4 <[^>]*> 418d7006 mttc0 t5,\$14,6 -0+0cb8 <[^>]*> 418d7007 mttc0 t5,\$14,7 +0+08bc <[^>]*> 410e6800 mftc0 t5,c0_epc +0+08c0 <[^>]*> 410e6801 mftc0 t5,\$14,1 +0+08c4 <[^>]*> 410e6802 mftc0 t5,\$14,2 +0+08c8 <[^>]*> 410e6803 mftc0 t5,\$14,3 +0+08cc <[^>]*> 410e6804 mftc0 t5,\$14,4 +0+08d0 <[^>]*> 410e6805 mftc0 t5,\$14,5 +0+08d4 <[^>]*> 410e6806 mftc0 t5,\$14,6 +0+08d8 <[^>]*> 410e6807 mftc0 t5,\$14,7 +0+08dc <[^>]*> 410e6810 mftr t5,t6,0,0,1 +0+08e0 <[^>]*> 410e6811 mftr t5,t6,0,1,1 +0+08e4 <[^>]*> 410e6812 mftr t5,t6,0,2,1 +0+08e8 <[^>]*> 410e6813 mftr t5,t6,0,3,1 +0+08ec <[^>]*> 410e6814 mftr t5,t6,0,4,1 +0+08f0 <[^>]*> 410e6815 mftr t5,t6,0,5,1 +0+08f4 <[^>]*> 410e6816 mftr t5,t6,0,6,1 +0+08f8 <[^>]*> 410e6817 mftr t5,t6,0,7,1 +0+08fc <[^>]*> 410e6820 mftgpr t5,t6 +0+0900 <[^>]*> 410e6821 mftacx t5,\$ac3 +0+0904 <[^>]*> 410e6822 mftc1 t5,\$f14 +0+0908 <[^>]*> 410e6823 cftc1 t5,\$14 +0+090c <[^>]*> 410e6824 mftc2 t5,\$14 +0+0910 <[^>]*> 410e6825 cftc2 t5,\$14 +0+0914 <[^>]*> 410e6826 mftr t5,t6,1,6,0 +0+0918 <[^>]*> 410e6827 mftr t5,t6,1,7,0 +0+091c <[^>]*> 410e6830 mftr t5,t6,1,0,1 +0+0920 <[^>]*> 410e6831 mftr t5,t6,1,1,1 +0+0924 <[^>]*> 410e6832 mfthc1 t5,\$f14 +0+0928 <[^>]*> 410e6833 mftr t5,t6,1,3,1 +0+092c <[^>]*> 410e6834 mfthc2 t5,\$14 +0+0930 <[^>]*> 410e6835 mftr t5,t6,1,5,1 +0+0934 <[^>]*> 410e6836 mftr t5,t6,1,6,1 +0+0938 <[^>]*> 410e6837 mftr t5,t6,1,7,1 +0+093c <[^>]*> 418d7000 mttc0 t5,c0_epc +0+0940 <[^>]*> 418d7001 mttc0 t5,\$14,1 +0+0944 <[^>]*> 418d7002 mttc0 t5,\$14,2 +0+0948 <[^>]*> 418d7003 mttc0 t5,\$14,3 +0+094c <[^>]*> 418d7004 mttc0 t5,\$14,4 +0+0950 <[^>]*> 418d7005 mttc0 t5,\$14,5 +0+0954 <[^>]*> 418d7006 mttc0 t5,\$14,6 +0+0958 <[^>]*> 418d7007 mttc0 t5,\$14,7 +0+095c <[^>]*> 418d7010 mttr t5,t6,0,0,1 +0+0960 <[^>]*> 418d7011 mttr t5,t6,0,1,1 +0+0964 <[^>]*> 418d7012 mttr t5,t6,0,2,1 +0+0968 <[^>]*> 418d7013 mttr t5,t6,0,3,1 +0+096c <[^>]*> 418d7014 mttr t5,t6,0,4,1 +0+0970 <[^>]*> 418d7015 mttr t5,t6,0,5,1 +0+0974 <[^>]*> 418d7016 mttr t5,t6,0,6,1 +0+0978 <[^>]*> 418d7017 mttr t5,t6,0,7,1 +0+097c <[^>]*> 418d7020 mttgpr t5,t6 +0+0980 <[^>]*> 418d7021 mttacx t5,\$ac3 +0+0984 <[^>]*> 418d7022 mttc1 t5,\$f14 +0+0988 <[^>]*> 418d7023 cttc1 t5,\$14 +0+098c <[^>]*> 418d7024 mttc2 t5,\$14 +0+0990 <[^>]*> 418d7025 cttc2 t5,\$14 +0+0994 <[^>]*> 418d7026 mttr t5,t6,1,6,0 +0+0998 <[^>]*> 418d7027 mttr t5,t6,1,7,0 +0+099c <[^>]*> 418d7030 mttr t5,t6,1,0,1 +0+09a0 <[^>]*> 418d7031 mttr t5,t6,1,1,1 +0+09a4 <[^>]*> 418d7032 mtthc1 t5,\$f14 +0+09a8 <[^>]*> 418d7033 mttr t5,t6,1,3,1 +0+09ac <[^>]*> 418d7034 mtthc2 t5,\$14 +0+09b0 <[^>]*> 418d7035 mttr t5,t6,1,5,1 +0+09b4 <[^>]*> 418d7036 mttr t5,t6,1,6,1 +0+09b8 <[^>]*> 418d7037 mttr t5,t6,1,7,1 \.\.\. diff --git a/gas/testsuite/gas/mips/mips32-mt.l b/gas/testsuite/gas/mips/mips32-mt.l deleted file mode 100644 index a3f32f27de12..000000000000 --- a/gas/testsuite/gas/mips/mips32-mt.l +++ /dev/null @@ -1,257 +0,0 @@ -.*: Assembler messages: -.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:576: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:577: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:578: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:579: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:580: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:581: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:582: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:583: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:584: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:585: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:586: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:587: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:588: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:589: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:590: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:591: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:592: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:592: Warning: MT immediate not in range 0..1 \(2\) -.*:593: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:593: Warning: MT immediate not in range 0..1 \(2\) -.*:594: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:594: Warning: MT immediate not in range 0..1 \(2\) -.*:595: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:595: Warning: MT immediate not in range 0..1 \(2\) -.*:596: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:596: Warning: MT immediate not in range 0..1 \(2\) -.*:597: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:597: Warning: MT immediate not in range 0..1 \(2\) -.*:598: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:598: Warning: MT immediate not in range 0..1 \(2\) -.*:599: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:599: Warning: MT immediate not in range 0..1 \(2\) -.*:600: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:601: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:602: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:603: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:604: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:605: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:606: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:607: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:624: Warning: MT immediate not in range 0..1 \(2\) -.*:625: Warning: MT immediate not in range 0..1 \(2\) -.*:626: Warning: MT immediate not in range 0..1 \(2\) -.*:627: Warning: MT immediate not in range 0..1 \(2\) -.*:628: Warning: MT immediate not in range 0..1 \(2\) -.*:629: Warning: MT immediate not in range 0..1 \(2\) -.*:630: Warning: MT immediate not in range 0..1 \(2\) -.*:631: Warning: MT immediate not in range 0..1 \(2\) -.*:632: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:633: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:634: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:635: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:636: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:637: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:638: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:639: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:656: Warning: MT immediate not in range 0..1 \(2\) -.*:657: Warning: MT immediate not in range 0..1 \(2\) -.*:658: Warning: MT immediate not in range 0..1 \(2\) -.*:659: Warning: MT immediate not in range 0..1 \(2\) -.*:660: Warning: MT immediate not in range 0..1 \(2\) -.*:661: Warning: MT immediate not in range 0..1 \(2\) -.*:662: Warning: MT immediate not in range 0..1 \(2\) -.*:663: Warning: MT immediate not in range 0..1 \(2\) -.*:664: Warning: MT immediate not in range 0..1 \(2\) -.*:664: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:665: Warning: MT immediate not in range 0..1 \(2\) -.*:665: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:666: Warning: MT immediate not in range 0..1 \(2\) -.*:666: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:667: Warning: MT immediate not in range 0..1 \(2\) -.*:667: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:668: Warning: MT immediate not in range 0..1 \(2\) -.*:668: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:669: Warning: MT immediate not in range 0..1 \(2\) -.*:669: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:670: Warning: MT immediate not in range 0..1 \(2\) -.*:670: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:671: Warning: MT immediate not in range 0..1 \(2\) -.*:671: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:672: Warning: MT immediate not in range 0..1 \(2\) -.*:673: Warning: MT immediate not in range 0..1 \(2\) -.*:674: Warning: MT immediate not in range 0..1 \(2\) -.*:675: Warning: MT immediate not in range 0..1 \(2\) -.*:676: Warning: MT immediate not in range 0..1 \(2\) -.*:677: Warning: MT immediate not in range 0..1 \(2\) -.*:678: Warning: MT immediate not in range 0..1 \(2\) -.*:679: Warning: MT immediate not in range 0..1 \(2\) -.*:680: Warning: MT immediate not in range 0..1 \(2\) -.*:681: Warning: MT immediate not in range 0..1 \(2\) -.*:682: Warning: MT immediate not in range 0..1 \(2\) -.*:683: Warning: MT immediate not in range 0..1 \(2\) -.*:684: Warning: MT immediate not in range 0..1 \(2\) -.*:685: Warning: MT immediate not in range 0..1 \(2\) -.*:686: Warning: MT immediate not in range 0..1 \(2\) -.*:687: Warning: MT immediate not in range 0..1 \(2\) -.*:688: Warning: MT immediate not in range 0..1 \(2\) -.*:688: Warning: MT immediate not in range 0..1 \(2\) -.*:689: Warning: MT immediate not in range 0..1 \(2\) -.*:689: Warning: MT immediate not in range 0..1 \(2\) -.*:690: Warning: MT immediate not in range 0..1 \(2\) -.*:690: Warning: MT immediate not in range 0..1 \(2\) -.*:691: Warning: MT immediate not in range 0..1 \(2\) -.*:691: Warning: MT immediate not in range 0..1 \(2\) -.*:692: Warning: MT immediate not in range 0..1 \(2\) -.*:692: Warning: MT immediate not in range 0..1 \(2\) -.*:693: Warning: MT immediate not in range 0..1 \(2\) -.*:693: Warning: MT immediate not in range 0..1 \(2\) -.*:694: Warning: MT immediate not in range 0..1 \(2\) -.*:694: Warning: MT immediate not in range 0..1 \(2\) -.*:695: Warning: MT immediate not in range 0..1 \(2\) -.*:695: Warning: MT immediate not in range 0..1 \(2\) -.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:704: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:705: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:706: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:707: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:708: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:709: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:710: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:711: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:712: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:713: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:714: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:715: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:716: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:717: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:718: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:719: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:720: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:720: Warning: MT immediate not in range 0..1 \(2\) -.*:721: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:721: Warning: MT immediate not in range 0..1 \(2\) -.*:722: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:722: Warning: MT immediate not in range 0..1 \(2\) -.*:723: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:723: Warning: MT immediate not in range 0..1 \(2\) -.*:724: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:724: Warning: MT immediate not in range 0..1 \(2\) -.*:725: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:725: Warning: MT immediate not in range 0..1 \(2\) -.*:726: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:726: Warning: MT immediate not in range 0..1 \(2\) -.*:727: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:727: Warning: MT immediate not in range 0..1 \(2\) -.*:728: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:729: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:730: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:731: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:732: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:733: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:734: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:735: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:752: Warning: MT immediate not in range 0..1 \(2\) -.*:753: Warning: MT immediate not in range 0..1 \(2\) -.*:754: Warning: MT immediate not in range 0..1 \(2\) -.*:755: Warning: MT immediate not in range 0..1 \(2\) -.*:756: Warning: MT immediate not in range 0..1 \(2\) -.*:757: Warning: MT immediate not in range 0..1 \(2\) -.*:758: Warning: MT immediate not in range 0..1 \(2\) -.*:759: Warning: MT immediate not in range 0..1 \(2\) -.*:760: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:761: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:762: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:763: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:764: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:765: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:766: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:767: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:784: Warning: MT immediate not in range 0..1 \(2\) -.*:785: Warning: MT immediate not in range 0..1 \(2\) -.*:786: Warning: MT immediate not in range 0..1 \(2\) -.*:787: Warning: MT immediate not in range 0..1 \(2\) -.*:788: Warning: MT immediate not in range 0..1 \(2\) -.*:789: Warning: MT immediate not in range 0..1 \(2\) -.*:790: Warning: MT immediate not in range 0..1 \(2\) -.*:791: Warning: MT immediate not in range 0..1 \(2\) -.*:792: Warning: MT immediate not in range 0..1 \(2\) -.*:792: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:793: Warning: MT immediate not in range 0..1 \(2\) -.*:793: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:794: Warning: MT immediate not in range 0..1 \(2\) -.*:794: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:795: Warning: MT immediate not in range 0..1 \(2\) -.*:795: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:796: Warning: MT immediate not in range 0..1 \(2\) -.*:796: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:797: Warning: MT immediate not in range 0..1 \(2\) -.*:797: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:798: Warning: MT immediate not in range 0..1 \(2\) -.*:798: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:799: Warning: MT immediate not in range 0..1 \(2\) -.*:799: Warning: MT immediate not in range 0..1 \([0-9]*\) -.*:800: Warning: MT immediate not in range 0..1 \(2\) -.*:801: Warning: MT immediate not in range 0..1 \(2\) -.*:802: Warning: MT immediate not in range 0..1 \(2\) -.*:803: Warning: MT immediate not in range 0..1 \(2\) -.*:804: Warning: MT immediate not in range 0..1 \(2\) -.*:805: Warning: MT immediate not in range 0..1 \(2\) -.*:806: Warning: MT immediate not in range 0..1 \(2\) -.*:807: Warning: MT immediate not in range 0..1 \(2\) -.*:808: Warning: MT immediate not in range 0..1 \(2\) -.*:809: Warning: MT immediate not in range 0..1 \(2\) -.*:810: Warning: MT immediate not in range 0..1 \(2\) -.*:811: Warning: MT immediate not in range 0..1 \(2\) -.*:812: Warning: MT immediate not in range 0..1 \(2\) -.*:813: Warning: MT immediate not in range 0..1 \(2\) -.*:814: Warning: MT immediate not in range 0..1 \(2\) -.*:815: Warning: MT immediate not in range 0..1 \(2\) -.*:816: Warning: MT immediate not in range 0..1 \(2\) -.*:816: Warning: MT immediate not in range 0..1 \(2\) -.*:817: Warning: MT immediate not in range 0..1 \(2\) -.*:817: Warning: MT immediate not in range 0..1 \(2\) -.*:818: Warning: MT immediate not in range 0..1 \(2\) -.*:818: Warning: MT immediate not in range 0..1 \(2\) -.*:819: Warning: MT immediate not in range 0..1 \(2\) -.*:819: Warning: MT immediate not in range 0..1 \(2\) -.*:820: Warning: MT immediate not in range 0..1 \(2\) -.*:820: Warning: MT immediate not in range 0..1 \(2\) -.*:821: Warning: MT immediate not in range 0..1 \(2\) -.*:821: Warning: MT immediate not in range 0..1 \(2\) -.*:822: Warning: MT immediate not in range 0..1 \(2\) -.*:822: Warning: MT immediate not in range 0..1 \(2\) -.*:823: Warning: MT immediate not in range 0..1 \(2\) -.*:823: Warning: MT immediate not in range 0..1 \(2\) diff --git a/gas/testsuite/gas/mips/mips32-mt.s b/gas/testsuite/gas/mips/mips32-mt.s index a3d8eeda0de3..8363256c6834 100644 --- a/gas/testsuite/gas/mips/mips32-mt.s +++ b/gas/testsuite/gas/mips/mips32-mt.s @@ -565,46 +565,6 @@ text_label: mttc2 $10,$11 mtthc2 $11,$12 cttc2 $12,$13 - mftr $13,$14,-1,0,-1 - mftr $13,$14,-1,1,-1 - mftr $13,$14,-1,2,-1 - mftr $13,$14,-1,3,-1 - mftr $13,$14,-1,4,-1 - mftr $13,$14,-1,5,-1 - mftr $13,$14,-1,6,-1 - mftr $13,$14,-1,7,-1 - mftr $13,$14,-1,0,0 - mftr $13,$14,-1,1,0 - mftr $13,$14,-1,2,0 - mftr $13,$14,-1,3,0 - mftr $13,$14,-1,4,0 - mftr $13,$14,-1,5,0 - mftr $13,$14,-1,6,0 - mftr $13,$14,-1,7,0 - mftr $13,$14,-1,0,1 - mftr $13,$14,-1,1,1 - mftr $13,$14,-1,2,1 - mftr $13,$14,-1,3,1 - mftr $13,$14,-1,4,1 - mftr $13,$14,-1,5,1 - mftr $13,$14,-1,6,1 - mftr $13,$14,-1,7,1 - mftr $13,$14,-1,0,2 - mftr $13,$14,-1,1,2 - mftr $13,$14,-1,2,2 - mftr $13,$14,-1,3,2 - mftr $13,$14,-1,4,2 - mftr $13,$14,-1,5,2 - mftr $13,$14,-1,6,2 - mftr $13,$14,-1,7,2 - mftr $13,$14,0,0,-1 - mftr $13,$14,0,1,-1 - mftr $13,$14,0,2,-1 - mftr $13,$14,0,3,-1 - mftr $13,$14,0,4,-1 - mftr $13,$14,0,5,-1 - mftr $13,$14,0,6,-1 - mftr $13,$14,0,7,-1 mftr $13,$14,0,0,0 mftr $13,$14,0,1,0 mftr $13,$14,0,2,0 @@ -621,22 +581,6 @@ text_label: mftr $13,$14,0,5,1 mftr $13,$14,0,6,1 mftr $13,$14,0,7,1 - mftr $13,$14,0,0,2 - mftr $13,$14,0,1,2 - mftr $13,$14,0,2,2 - mftr $13,$14,0,3,2 - mftr $13,$14,0,4,2 - mftr $13,$14,0,5,2 - mftr $13,$14,0,6,2 - mftr $13,$14,0,7,2 - mftr $13,$14,1,0,-1 - mftr $13,$14,1,1,-1 - mftr $13,$14,1,2,-1 - mftr $13,$14,1,3,-1 - mftr $13,$14,1,4,-1 - mftr $13,$14,1,5,-1 - mftr $13,$14,1,6,-1 - mftr $13,$14,1,7,-1 mftr $13,$14,1,0,0 mftr $13,$14,1,1,0 mftr $13,$14,1,2,0 @@ -653,86 +597,6 @@ text_label: mftr $13,$14,1,5,1 mftr $13,$14,1,6,1 mftr $13,$14,1,7,1 - mftr $13,$14,1,0,2 - mftr $13,$14,1,1,2 - mftr $13,$14,1,2,2 - mftr $13,$14,1,3,2 - mftr $13,$14,1,4,2 - mftr $13,$14,1,5,2 - mftr $13,$14,1,6,2 - mftr $13,$14,1,7,2 - mftr $13,$14,2,0,-1 - mftr $13,$14,2,1,-1 - mftr $13,$14,2,2,-1 - mftr $13,$14,2,3,-1 - mftr $13,$14,2,4,-1 - mftr $13,$14,2,5,-1 - mftr $13,$14,2,6,-1 - mftr $13,$14,2,7,-1 - mftr $13,$14,2,0,0 - mftr $13,$14,2,1,0 - mftr $13,$14,2,2,0 - mftr $13,$14,2,3,0 - mftr $13,$14,2,4,0 - mftr $13,$14,2,5,0 - mftr $13,$14,2,6,0 - mftr $13,$14,2,7,0 - mftr $13,$14,2,0,1 - mftr $13,$14,2,1,1 - mftr $13,$14,2,2,1 - mftr $13,$14,2,3,1 - mftr $13,$14,2,4,1 - mftr $13,$14,2,5,1 - mftr $13,$14,2,6,1 - mftr $13,$14,2,7,1 - mftr $13,$14,2,0,2 - mftr $13,$14,2,1,2 - mftr $13,$14,2,2,2 - mftr $13,$14,2,3,2 - mftr $13,$14,2,4,2 - mftr $13,$14,2,5,2 - mftr $13,$14,2,6,2 - mftr $13,$14,2,7,2 - mttr $13,$14,-1,0,-1 - mttr $13,$14,-1,1,-1 - mttr $13,$14,-1,2,-1 - mttr $13,$14,-1,3,-1 - mttr $13,$14,-1,4,-1 - mttr $13,$14,-1,5,-1 - mttr $13,$14,-1,6,-1 - mttr $13,$14,-1,7,-1 - mttr $13,$14,-1,0,0 - mttr $13,$14,-1,1,0 - mttr $13,$14,-1,2,0 - mttr $13,$14,-1,3,0 - mttr $13,$14,-1,4,0 - mttr $13,$14,-1,5,0 - mttr $13,$14,-1,6,0 - mttr $13,$14,-1,7,0 - mttr $13,$14,-1,0,1 - mttr $13,$14,-1,1,1 - mttr $13,$14,-1,2,1 - mttr $13,$14,-1,3,1 - mttr $13,$14,-1,4,1 - mttr $13,$14,-1,5,1 - mttr $13,$14,-1,6,1 - mttr $13,$14,-1,7,1 - mttr $13,$14,-1,0,2 - mttr $13,$14,-1,1,2 - mttr $13,$14,-1,2,2 - mttr $13,$14,-1,3,2 - mttr $13,$14,-1,4,2 - mttr $13,$14,-1,5,2 - mttr $13,$14,-1,6,2 - mttr $13,$14,-1,7,2 - mttr $13,$14,0,0,-1 - mttr $13,$14,0,1,-1 - mttr $13,$14,0,2,-1 - mttr $13,$14,0,3,-1 - mttr $13,$14,0,4,-1 - mttr $13,$14,0,5,-1 - mttr $13,$14,0,6,-1 - mttr $13,$14,0,7,-1 mttr $13,$14,0,0,0 mttr $13,$14,0,1,0 mttr $13,$14,0,2,0 @@ -749,22 +613,6 @@ text_label: mttr $13,$14,0,5,1 mttr $13,$14,0,6,1 mttr $13,$14,0,7,1 - mttr $13,$14,0,0,2 - mttr $13,$14,0,1,2 - mttr $13,$14,0,2,2 - mttr $13,$14,0,3,2 - mttr $13,$14,0,4,2 - mttr $13,$14,0,5,2 - mttr $13,$14,0,6,2 - mttr $13,$14,0,7,2 - mttr $13,$14,1,0,-1 - mttr $13,$14,1,1,-1 - mttr $13,$14,1,2,-1 - mttr $13,$14,1,3,-1 - mttr $13,$14,1,4,-1 - mttr $13,$14,1,5,-1 - mttr $13,$14,1,6,-1 - mttr $13,$14,1,7,-1 mttr $13,$14,1,0,0 mttr $13,$14,1,1,0 mttr $13,$14,1,2,0 @@ -781,46 +629,6 @@ text_label: mttr $13,$14,1,5,1 mttr $13,$14,1,6,1 mttr $13,$14,1,7,1 - mttr $13,$14,1,0,2 - mttr $13,$14,1,1,2 - mttr $13,$14,1,2,2 - mttr $13,$14,1,3,2 - mttr $13,$14,1,4,2 - mttr $13,$14,1,5,2 - mttr $13,$14,1,6,2 - mttr $13,$14,1,7,2 - mttr $13,$14,2,0,-1 - mttr $13,$14,2,1,-1 - mttr $13,$14,2,2,-1 - mttr $13,$14,2,3,-1 - mttr $13,$14,2,4,-1 - mttr $13,$14,2,5,-1 - mttr $13,$14,2,6,-1 - mttr $13,$14,2,7,-1 - mttr $13,$14,2,0,0 - mttr $13,$14,2,1,0 - mttr $13,$14,2,2,0 - mttr $13,$14,2,3,0 - mttr $13,$14,2,4,0 - mttr $13,$14,2,5,0 - mttr $13,$14,2,6,0 - mttr $13,$14,2,7,0 - mttr $13,$14,2,0,1 - mttr $13,$14,2,1,1 - mttr $13,$14,2,2,1 - mttr $13,$14,2,3,1 - mttr $13,$14,2,4,1 - mttr $13,$14,2,5,1 - mttr $13,$14,2,6,1 - mttr $13,$14,2,7,1 - mttr $13,$14,2,0,2 - mttr $13,$14,2,1,2 - mttr $13,$14,2,2,2 - mttr $13,$14,2,3,2 - mttr $13,$14,2,4,2 - mttr $13,$14,2,5,2 - mttr $13,$14,2,6,2 - mttr $13,$14,2,7,2 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .space 8 diff --git a/gas/testsuite/gas/mips/mips32-sf32.d b/gas/testsuite/gas/mips/mips32-sf32.d new file mode 100644 index 000000000000..4de9844d2615 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32-sf32.d @@ -0,0 +1,19 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS32 odd single-precision float registers +#as: -32 + +# Check MIPS32 instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 3c013f80 lui \$1,0x3f80 +0+0004 <[^>]*> 44810800 mtc1 \$1,\$f1 +0+0008 <[^>]*> c783c000 lwc1 \$f3,-16384\(\$28\) + 8: R_MIPS_LITERAL \.lit4\+0x4000 +0+000c <[^>]*> 46030940 add.s \$f5,\$f1,\$f3 +0+0010 <[^>]*> 46003a21 cvt.d.s \$f8,\$f7 +0+0014 <[^>]*> 46803a21 cvt.d.w \$f8,\$f7 +0+0018 <[^>]*> 462041e0 cvt.s.d \$f7,\$f8 +0+001c <[^>]*> 462041cd trunc.w.d \$f7,\$f8 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips32-sf32.s b/gas/testsuite/gas/mips/mips32-sf32.s new file mode 100644 index 000000000000..68b7e4ea7603 --- /dev/null +++ b/gas/testsuite/gas/mips/mips32-sf32.s @@ -0,0 +1,14 @@ + + .text +func: + .set noreorder + li.s $f1, 1.0 + li.s $f3, 1.9 + add.s $f5, $f1, $f3 + cvt.d.s $f8,$f7 + cvt.d.w $f8,$f7 + cvt.s.d $f7,$f8 + trunc.w.d $f7,$f8 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/mips32.d b/gas/testsuite/gas/mips/mips32.d index cb226d8f43b0..14693fc84ecc 100644 --- a/gas/testsuite/gas/mips/mips32.d +++ b/gas/testsuite/gas/mips/mips32.d @@ -38,19 +38,37 @@ Disassembly of section .text: 0+0070 <[^>]*> bc250000 cache 0x5,0\(at\) 0+0074 <[^>]*> bc457fff cache 0x5,32767\(v0\) 0+0078 <[^>]*> bc658000 cache 0x5,-32768\(v1\) -0+007c <[^>]*> 42000018 eret -0+0080 <[^>]*> 42000008 tlbp -0+0084 <[^>]*> 42000001 tlbr -0+0088 <[^>]*> 42000002 tlbwi -0+008c <[^>]*> 42000006 tlbwr -0+0090 <[^>]*> 42000020 wait -0+0094 <[^>]*> 42000020 wait -0+0098 <[^>]*> 4359e260 wait 0x56789 -0+009c <[^>]*> 0000000d break -0+00a0 <[^>]*> 0000000d break -0+00a4 <[^>]*> 0345000d break 0x345 -0+00a8 <[^>]*> 0048d14d break 0x48,0x345 -0+00ac <[^>]*> 7000003f sdbbp -0+00b0 <[^>]*> 7000003f sdbbp -0+00b4 <[^>]*> 7159e27f sdbbp 0x56789 - ... +0+007c <[^>]*> 3c010001 lui at,0x1 +0+0080 <[^>]*> 00240821 addu at,at,a0 +0+0084 <[^>]*> bc258000 cache 0x5,-32768\(at\) +0+0088 <[^>]*> 3c01ffff lui at,0xffff +0+008c <[^>]*> 00250821 addu at,at,a1 +0+0090 <[^>]*> bc257fff cache 0x5,32767\(at\) +0+0094 <[^>]*> 3c010001 lui at,0x1 +0+0098 <[^>]*> bc258000 cache 0x5,-32768\(at\) +0+009c <[^>]*> 3c01ffff lui at,0xffff +0+00a0 <[^>]*> bc257fff cache 0x5,32767\(at\) +0+00a4 <[^>]*> 42000018 eret +0+00a8 <[^>]*> 42000008 tlbp +0+00ac <[^>]*> 42000001 tlbr +0+00b0 <[^>]*> 42000002 tlbwi +0+00b4 <[^>]*> 42000006 tlbwr +0+00b8 <[^>]*> 42000020 wait +0+00bc <[^>]*> 42000020 wait +0+00c0 <[^>]*> 4359e260 wait 0x56789 +0+00c4 <[^>]*> 0000000d break +0+00c8 <[^>]*> 0000000d break +0+00cc <[^>]*> 0345000d break 0x345 +0+00d0 <[^>]*> 0048d14d break 0x48,0x345 +0+00d4 <[^>]*> 7000003f sdbbp +0+00d8 <[^>]*> 7000003f sdbbp +0+00dc <[^>]*> 7159e27f sdbbp 0x56789 +0+00e0 <[^>]*> 4900ffc7 bc2f 0+0000 <text_label> +0+00e4 <[^>]*> 00000000 nop +0+00e8 <[^>]*> 4906ffc5 bc2fl \$cc1,0+0000 <text_label> +0+00ec <[^>]*> 00000000 nop +0+00f0 <[^>]*> 4919ffc3 bc2t \$cc6,0+0000 <text_label> +0+00f4 <[^>]*> 00000000 nop +0+00f8 <[^>]*> 491fffc1 bc2tl \$cc7,0+0000 <text_label> +0+00fc <[^>]*> 00000000 nop + \.\.\. diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s index b3fb6fe13bf6..f54265805439 100644 --- a/gas/testsuite/gas/mips/mips32.s +++ b/gas/testsuite/gas/mips/mips32.s @@ -49,6 +49,12 @@ text_label: cache 5, ($1) cache 5, 32767($2) cache 5, -32768($3) + .set at + cache 5, 32768($4) + cache 5, -32769($5) + cache 5, 32768 + cache 5, -32769 + .set noat eret tlbp tlbr @@ -73,5 +79,15 @@ text_label: sdbbp 0 # disassembles without code sdbbp 0x56789 + # Cop2 branches with cond code number, like bc1t/f + bc2f $cc0,text_label + nop + bc2fl $cc1,text_label + nop + bc2t $cc6,text_label + nop + bc2tl $cc7,text_label + nop + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .space 8 diff --git a/gas/testsuite/gas/mips/mips4.d b/gas/testsuite/gas/mips/mips4.d index bc3e924948d3..1dfcb3983d1a 100644 --- a/gas/testsuite/gas/mips/mips4.d +++ b/gas/testsuite/gas/mips/mips4.d @@ -21,7 +21,7 @@ Disassembly of section .text: 0+0030 <[^>]*> ldxc1 \$f2,a0\(a1\) 0+0034 <[^>]*> lwxc1 \$f2,a0\(a1\) 0+0038 <[^>]*> madd.d \$f0,\$f2,\$f4,\$f6 -0+003c <[^>]*> madd.s \$f0,\$f2,\$f4,\$f6 +0+003c <[^>]*> madd.s \$f10,\$f8,\$f2,\$f0 0+0040 <[^>]*> movf a0,a1,\$fcc4 0+0044 <[^>]*> movf.d \$f4,\$f6,\$fcc0 0+0048 <[^>]*> movf.s \$f4,\$f6,\$fcc0 @@ -40,11 +40,12 @@ Disassembly of section .text: 0+007c <[^>]*> nmadd.s \$f0,\$f2,\$f4,\$f6 0+0080 <[^>]*> nmsub.d \$f0,\$f2,\$f4,\$f6 0+0084 <[^>]*> nmsub.s \$f0,\$f2,\$f4,\$f6 -0+0088 <[^>]*> prefx 0x4,a0\(a1\) -0+008c <[^>]*> recip.d \$f4,\$f6 -0+0090 <[^>]*> recip.s \$f4,\$f6 -0+0094 <[^>]*> rsqrt.d \$f4,\$f6 -0+0098 <[^>]*> rsqrt.s \$f4,\$f6 -0+009c <[^>]*> sdxc1 \$f4,a0\(a1\) -0+00a0 <[^>]*> swxc1 \$f4,a0\(a1\) +0+0088 <[^>]*> pref 0x4,0\(a0\) +0+008c <[^>]*> prefx 0x4,a0\(a1\) +0+0090 <[^>]*> recip.d \$f4,\$f6 +0+0094 <[^>]*> recip.s \$f4,\$f6 +0+0098 <[^>]*> rsqrt.d \$f4,\$f6 +0+009c <[^>]*> rsqrt.s \$f4,\$f6 +0+00a0 <[^>]*> sdxc1 \$f4,a0\(a1\) +0+00a4 <[^>]*> swxc1 \$f4,a0\(a1\) ... diff --git a/gas/testsuite/gas/mips/mips4.s b/gas/testsuite/gas/mips/mips4.s index 591292bb6b34..d346c2af2b9f 100644 --- a/gas/testsuite/gas/mips/mips4.s +++ b/gas/testsuite/gas/mips/mips4.s @@ -11,7 +11,8 @@ text_label: ldxc1 $f2,$4($5) lwxc1 $f2,$4($5) madd.d $f0,$f2,$f4,$f6 - madd.s $f0,$f2,$f4,$f6 + # This choice of arguments is so that it matches bc3f on pre-mips4. + madd.s $f10,$f8,$f2,$f0 movf $4,$5,$fcc4 movf.d $f4,$f6,$fcc0 movf.s $f4,$f6,$fcc0 @@ -30,14 +31,8 @@ text_label: nmadd.s $f0,$f2,$f4,$f6 nmsub.d $f0,$f2,$f4,$f6 nmsub.s $f0,$f2,$f4,$f6 - - # We don't test pref because currently the disassembler will - # disassemble it as lwc3. lwc3 is correct for mips1 to mips3, - # while pref is correct for mips4. Unfortunately, the - # disassembler does not know which architecture it is - # disassembling for. - # pref 4,0($4) - + # It used to be disabled due to a clash with lwc3. + pref 4,0($4) prefx 4,$4($5) recip.d $f4,$f6 recip.s $f4,$f6 diff --git a/gas/testsuite/gas/mips/mips64-dsp.d b/gas/testsuite/gas/mips/mips64-dsp.d new file mode 100644 index 000000000000..11009a012c52 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64-dsp.d @@ -0,0 +1,172 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=32 +#name: MIPS DSP ASE for MIPS64 +#as: -mdsp + +# Check MIPS DSP ASE for MIPS64 Instruction Assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 7c010456 absq_s\.pw zero,at +0+0004 <[^>]*> 7c1ff256 absq_s\.qh s8,ra +0+0008 <[^>]*> 7cc72c94 addq\.pw a1,a2,a3 +0+000c <[^>]*> 7ce83594 addq_s\.pw a2,a3,t0 +0+0010 <[^>]*> 7c641294 addq\.qh v0,v1,a0 +0+0014 <[^>]*> 7c851b94 addq_s\.qh v1,a0,a1 +0+0018 <[^>]*> 7d4b4814 addu\.ob t1,t2,t3 +0+001c <[^>]*> 7d6c5114 addu_s\.ob t2,t3,t4 +0+0020 <[^>]*> 041dfff7 bposge64 00000000 <text_label> +0+0024 <[^>]*> 00000000 nop +0+0028 <[^>]*> 7e950415 cmp\.eq\.pw s4,s5 +0+002c <[^>]*> 7eb60455 cmp\.lt\.pw s5,s6 +0+0030 <[^>]*> 7ed70495 cmp\.le\.pw s6,s7 +0+0034 <[^>]*> 7e320215 cmp\.eq\.qh s1,s2 +0+0038 <[^>]*> 7e530255 cmp\.lt\.qh s2,s3 +0+003c <[^>]*> 7e740295 cmp\.le\.qh s3,s4 +0+0040 <[^>]*> 7dcf0015 cmpu\.eq\.ob t6,t7 +0+0044 <[^>]*> 7df00055 cmpu\.lt\.ob t7,s0 +0+0048 <[^>]*> 7e110095 cmpu\.le\.ob s0,s1 +0+004c <[^>]*> 7d2a4115 cmpgu\.eq\.ob t0,t1,t2 +0+0050 <[^>]*> 7d4b4955 cmpgu\.lt\.ob t1,t2,t3 +0+0054 <[^>]*> 7d6c5195 cmpgu\.le\.ob t2,t3,t4 +0+0058 <[^>]*> 7c1f1abc dextpdp ra,\$ac3,0x0 +0+005c <[^>]*> 7c3f1abc dextpdp ra,\$ac3,0x1 +0+0060 <[^>]*> 7fff1abc dextpdp ra,\$ac3,0x1f +0+0064 <[^>]*> 7c2002fc dextpdpv zero,\$ac0,at +0+0068 <[^>]*> 7c1d08bc dextp sp,\$ac1,0x0 +0+006c <[^>]*> 7c3d08bc dextp sp,\$ac1,0x1 +0+0070 <[^>]*> 7ffd08bc dextp sp,\$ac1,0x1f +0+0074 <[^>]*> 7ffe10fc dextpv s8,\$ac2,ra +0+0078 <[^>]*> 7c031c3c dextr\.l v1,\$ac3,0x0 +0+007c <[^>]*> 7c231c3c dextr\.l v1,\$ac3,0x1 +0+0080 <[^>]*> 7fe31c3c dextr\.l v1,\$ac3,0x1f +0+0084 <[^>]*> 7c04053c dextr_r\.l a0,\$ac0,0x0 +0+0088 <[^>]*> 7c24053c dextr_r\.l a0,\$ac0,0x1 +0+008c <[^>]*> 7fe4053c dextr_r\.l a0,\$ac0,0x1f +0+0090 <[^>]*> 7c050dbc dextr_rs\.l a1,\$ac1,0x0 +0+0094 <[^>]*> 7c250dbc dextr_rs\.l a1,\$ac1,0x1 +0+0098 <[^>]*> 7fe50dbc dextr_rs\.l a1,\$ac1,0x1f +0+009c <[^>]*> 7c01093c dextr_r\.w at,\$ac1,0x0 +0+00a0 <[^>]*> 7c21093c dextr_r\.w at,\$ac1,0x1 +0+00a4 <[^>]*> 7fe1093c dextr_r\.w at,\$ac1,0x1f +0+00a8 <[^>]*> 7c0211bc dextr_rs\.w v0,\$ac2,0x0 +0+00ac <[^>]*> 7c2211bc dextr_rs\.w v0,\$ac2,0x1 +0+00b0 <[^>]*> 7fe211bc dextr_rs\.w v0,\$ac2,0x1f +0+00b4 <[^>]*> 7c0213bc dextr_s\.h v0,\$ac2,0x0 +0+00b8 <[^>]*> 7c2213bc dextr_s\.h v0,\$ac2,0x1 +0+00bc <[^>]*> 7fe213bc dextr_s\.h v0,\$ac2,0x1f +0+00c0 <[^>]*> 7c00003c dextr\.w zero,\$ac0,0x0 +0+00c4 <[^>]*> 7c20003c dextr\.w zero,\$ac0,0x1 +0+00c8 <[^>]*> 7fe0003c dextr\.w zero,\$ac0,0x1f +0+00cc <[^>]*> 7d8b187c dextrv\.w t3,\$ac3,t4 +0+00d0 <[^>]*> 7dac017c dextrv_r\.w t4,\$ac0,t5 +0+00d4 <[^>]*> 7dcd09fc dextrv_rs\.w t5,\$ac1,t6 +0+00d8 <[^>]*> 7dee147c dextrv\.l t6,\$ac2,t7 +0+00dc <[^>]*> 7e0f1d7c dextrv_r\.l t7,\$ac3,s0 +0+00e0 <[^>]*> 7e3005fc dextrv_rs\.l s0,\$ac0,s1 +0+00e4 <[^>]*> 7f7a000d dinsv k0,k1 +0+00e8 <[^>]*> 7e950e74 dmadd \$ac1,s4,s5 +0+00ec <[^>]*> 7eb61774 dmaddu \$ac2,s5,s6 +0+00f0 <[^>]*> 7ed71ef4 dmsub \$ac3,s6,s7 +0+00f4 <[^>]*> 7ef807f4 dmsubu \$ac0,s7,t8 +0+00f8 <[^>]*> 7c8017fc dmthlip a0,\$ac2 +0+00fc <[^>]*> 7c010b34 dpaq_sa\.l\.pw \$ac1,zero,at +0+0100 <[^>]*> 7eb61134 dpaq_s\.w\.qh \$ac2,s5,s6 +0+0104 <[^>]*> 7df000f4 dpau\.h\.obl \$ac0,t7,s0 +0+0108 <[^>]*> 7e1109f4 dpau\.h\.obr \$ac1,s0,s1 +0+010c <[^>]*> 7c640374 dpsq_sa\.l\.pw \$ac0,v1,a0 +0+0110 <[^>]*> 7f190974 dpsq_s\.w\.qh \$ac1,t8,t9 +0+0114 <[^>]*> 7e3212f4 dpsu\.h\.obl \$ac2,s1,s2 +0+0118 <[^>]*> 7e531bf4 dpsu\.h\.obr \$ac3,s2,s3 +0+011c <[^>]*> 7e001ebc dshilo \$ac3,-64 +0+0120 <[^>]*> 7df81ebc dshilo \$ac3,63 +0+0124 <[^>]*> 7c4006fc dshilov \$ac0,v0 +0+0128 <[^>]*> 7e51820a ldx s0,s1\(s2\) +0+012c <[^>]*> 7d4b1c34 maq_sa\.w\.qhll \$ac3,t2,t3 +0+0130 <[^>]*> 7d6c0474 maq_sa\.w\.qhlr \$ac0,t3,t4 +0+0134 <[^>]*> 7d8d0cb4 maq_sa\.w\.qhrl \$ac1,t4,t5 +0+0138 <[^>]*> 7dae14f4 maq_sa\.w\.qhrr \$ac2,t5,t6 +0+013c <[^>]*> 7e110f34 maq_s\.l\.pwl \$ac1,s0,s1 +0+0140 <[^>]*> 7e3217b4 maq_s\.l\.pwr \$ac2,s1,s2 +0+0144 <[^>]*> 7d4b1d34 maq_s\.w\.qhll \$ac3,t2,t3 +0+0148 <[^>]*> 7d6c0574 maq_s\.w\.qhlr \$ac0,t3,t4 +0+014c <[^>]*> 7d8d0db4 maq_s\.w\.qhrl \$ac1,t4,t5 +0+0150 <[^>]*> 7dae15f4 maq_s\.w\.qhrr \$ac2,t5,t6 +0+0154 <[^>]*> 7d8d5f14 muleq_s\.pw\.qhl t3,t4,t5 +0+0158 <[^>]*> 7dae6754 muleq_s\.pw\.qhr t4,t5,t6 +0+015c <[^>]*> 7ca62194 muleu_s\.qh\.obl a0,a1,a2 +0+0160 <[^>]*> 7cc729d4 muleu_s\.qh\.obr a1,a2,a3 +0+0164 <[^>]*> 7ce837d0 mulq_rs\.ph a2,a3,t0 +0+0168 <[^>]*> 7d2a47d4 mulq_rs\.qh t0,t1,t2 +0+016c <[^>]*> 7f7c01b4 mulsaq_s\.w\.qh \$ac0,k1,gp +0+0170 <[^>]*> 7fbe13b4 mulsaq_s\.l\.pw \$ac2,sp,s8 +0+0174 <[^>]*> 7fbee395 packrl\.pw gp,sp,s8 +0+0178 <[^>]*> 7f5bc8d5 pick\.ob t9,k0,k1 +0+017c <[^>]*> 7f7cd2d5 pick\.qh k0,k1,gp +0+0180 <[^>]*> 7f9ddcd5 pick\.pw k1,gp,sp +0+0184 <[^>]*> 7c0f7316 preceq\.pw\.qhl t6,t7 +0+0188 <[^>]*> 7c107b56 preceq\.pw\.qhr t7,s0 +0+018c <[^>]*> 7c118396 preceq\.pw\.qhla s0,s1 +0+0190 <[^>]*> 7c128bd6 preceq\.pw\.qhra s1,s2 +0+0194 <[^>]*> 7c139516 preceq\.s\.l\.pwl s2,s3 +0+0198 <[^>]*> 7c149d56 preceq\.s\.l\.pwr s3,s4 +0+019c <[^>]*> 7c19c116 precequ\.pw\.qhl t8,t9 +0+01a0 <[^>]*> 7c1ac956 precequ\.pw\.qhr t9,k0 +0+01a4 <[^>]*> 7c1bd196 precequ\.pw\.qhla k0,k1 +0+01a8 <[^>]*> 7c1cd9d6 precequ\.pw\.qhra k1,gp +0+01ac <[^>]*> 7c1de716 preceu\.qh\.obl gp,sp +0+01b0 <[^>]*> 7c1eef56 preceu\.qh\.obr sp,s8 +0+01b4 <[^>]*> 7c1ff796 preceu\.qh\.obla s8,ra +0+01b8 <[^>]*> 7c00ffd6 preceu\.qh\.obra ra,zero +0+01bc <[^>]*> 7ca62315 precrq\.ob\.qh a0,a1,a2 +0+01c0 <[^>]*> 7d093f15 precrq\.pw\.l a3,t0,t1 +0+01c4 <[^>]*> 7cc72d15 precrq\.qh\.pw a1,a2,a3 +0+01c8 <[^>]*> 7ce83555 precrq_rs\.qh\.pw a2,a3,t0 +0+01cc <[^>]*> 7d4b4bd5 precrqu_s\.ob\.qh t1,t2,t3 +0+01d0 <[^>]*> 7f60d514 raddu\.l\.ob k0,k1 +0+01d4 <[^>]*> 7c00e896 repl\.ob sp,0x0 +0+01d8 <[^>]*> 7cffe896 repl\.ob sp,0xff +0+01dc <[^>]*> 7c1ff0d6 replv\.ob s8,ra +0+01e0 <[^>]*> 7e000a96 repl\.qh at,-512 +0+01e4 <[^>]*> 7dff0a96 repl\.qh at,511 +0+01e8 <[^>]*> 7c0312d6 replv\.qh v0,v1 +0+01ec <[^>]*> 7e001c96 repl\.pw v1,-512 +0+01f0 <[^>]*> 7dff1c96 repl\.pw v1,511 +0+01f4 <[^>]*> 7c0524d6 replv\.pw a0,a1 +0+01f8 <[^>]*> 7c031017 shll\.ob v0,v1,0x0 +0+01fc <[^>]*> 7ce31017 shll\.ob v0,v1,0x7 +0+0200 <[^>]*> 7ca41897 shllv\.ob v1,a0,a1 +0+0204 <[^>]*> 7c094217 shll\.qh t0,t1,0x0 +0+0208 <[^>]*> 7de94217 shll\.qh t0,t1,0xf +0+020c <[^>]*> 7d6a4a97 shllv\.qh t1,t2,t3 +0+0210 <[^>]*> 7c0b5317 shll_s\.qh t2,t3,0x0 +0+0214 <[^>]*> 7deb5317 shll_s\.qh t2,t3,0xf +0+0218 <[^>]*> 7dac5b97 shllv_s\.qh t3,t4,t5 +0+021c <[^>]*> 7c0f7417 shll\.pw t6,t7,0x0 +0+0220 <[^>]*> 7fef7417 shll\.pw t6,t7,0x1f +0+0224 <[^>]*> 7e307c97 shllv\.pw t7,s0,s1 +0+0228 <[^>]*> 7c118517 shll_s\.pw s0,s1,0x0 +0+022c <[^>]*> 7ff18517 shll_s\.pw s0,s1,0x1f +0+0230 <[^>]*> 7e728d97 shllv_s\.pw s1,s2,s3 +0+0234 <[^>]*> 7c1de257 shra\.qh gp,sp,0x0 +0+0238 <[^>]*> 7dfde257 shra\.qh gp,sp,0xf +0+023c <[^>]*> 7ffeead7 shrav\.qh sp,s8,ra +0+0240 <[^>]*> 7c1ff357 shra_r\.qh s8,ra,0x0 +0+0244 <[^>]*> 7dfff357 shra_r\.qh s8,ra,0xf +0+0248 <[^>]*> 7c20fbd7 shrav_r\.qh ra,zero,at +0+024c <[^>]*> 7c010457 shra\.pw zero,at,0x0 +0+0250 <[^>]*> 7fe10457 shra\.pw zero,at,0x1f +0+0254 <[^>]*> 7c620cd7 shrav\.pw at,v0,v1 +0+0258 <[^>]*> 7c031557 shra_r\.pw v0,v1,0x0 +0+025c <[^>]*> 7fe31557 shra_r\.pw v0,v1,0x1f +0+0260 <[^>]*> 7ca41dd7 shrav_r\.pw v1,a0,a1 +0+0264 <[^>]*> 7c15a057 shrl\.ob s4,s5,0x0 +0+0268 <[^>]*> 7cf5a057 shrl\.ob s4,s5,0x7 +0+026c <[^>]*> 7ef6a8d7 shrlv\.ob s5,s6,s7 +0+0270 <[^>]*> 7e3282d4 subq\.qh s0,s1,s2 +0+0274 <[^>]*> 7e538bd4 subq_s\.qh s1,s2,s3 +0+0278 <[^>]*> 7e7494d4 subq\.pw s2,s3,s4 +0+027c <[^>]*> 7e959dd4 subq_s\.pw s3,s4,s5 +0+0280 <[^>]*> 7eb6a054 subu\.ob s4,s5,s6 +0+0284 <[^>]*> 7ed7a954 subu_s\.ob s5,s6,s7 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips64-dsp.s b/gas/testsuite/gas/mips/mips64-dsp.s new file mode 100644 index 000000000000..b372e651bbc8 --- /dev/null +++ b/gas/testsuite/gas/mips/mips64-dsp.s @@ -0,0 +1,174 @@ +# source file to test assembly of MIPS DSP ASE for MIPS64 instructions + + .set noreorder + .set nomacro + .set noat + + .text +text_label: + + absq_s.pw $0,$1 + absq_s.qh $30,$31 + addq.pw $5,$6,$7 + addq_s.pw $6,$7,$8 + addq.qh $2,$3,$4 + addq_s.qh $3,$4,$5 + addu.ob $9,$10,$11 + addu_s.ob $10,$11,$12 + bposge64 text_label + nop + cmp.eq.pw $20,$21 + cmp.lt.pw $21,$22 + cmp.le.pw $22,$23 + cmp.eq.qh $17,$18 + cmp.lt.qh $18,$19 + cmp.le.qh $19,$20 + cmpu.eq.ob $14,$15 + cmpu.lt.ob $15,$16 + cmpu.le.ob $16,$17 + cmpgu.eq.ob $8,$9,$10 + cmpgu.lt.ob $9,$10,$11 + cmpgu.le.ob $10,$11,$12 + dextpdp $31,$ac3,0 + dextpdp $31,$ac3,1 + dextpdp $31,$ac3,31 + dextpdpv $0,$ac0,$1 + dextp $29,$ac1,0 + dextp $29,$ac1,1 + dextp $29,$ac1,31 + dextpv $30,$ac2,$31 + dextr.l $3,$ac3,0 + dextr.l $3,$ac3,1 + dextr.l $3,$ac3,31 + dextr_r.l $4,$ac0,0 + dextr_r.l $4,$ac0,1 + dextr_r.l $4,$ac0,31 + dextr_rs.l $5,$ac1,0 + dextr_rs.l $5,$ac1,1 + dextr_rs.l $5,$ac1,31 + dextr_r.w $1,$ac1,0 + dextr_r.w $1,$ac1,1 + dextr_r.w $1,$ac1,31 + dextr_rs.w $2,$ac2,0 + dextr_rs.w $2,$ac2,1 + dextr_rs.w $2,$ac2,31 + dextr_s.h $2,$ac2,0 + dextr_s.h $2,$ac2,1 + dextr_s.h $2,$ac2,31 + dextr.w $0,$ac0,0 + dextr.w $0,$ac0,1 + dextr.w $0,$ac0,31 + dextrv.w $11,$ac3,$12 + dextrv_r.w $12,$ac0,$13 + dextrv_rs.w $13,$ac1,$14 + dextrv.l $14,$ac2,$15 + dextrv_r.l $15,$ac3,$16 + dextrv_rs.l $16,$ac0,$17 + dinsv $26,$27 + dmadd $ac1,$20,$21 + dmaddu $ac2,$21,$22 + dmsub $ac3,$22,$23 + dmsubu $ac0,$23,$24 + dmthlip $4,$ac2 + dpaq_sa.l.pw $ac1,$0,$1 + dpaq_s.w.qh $ac2,$21,$22 + dpau.h.obl $ac0,$15,$16 + dpau.h.obr $ac1,$16,$17 + dpsq_sa.l.pw $ac0,$3,$4 + dpsq_s.w.qh $ac1,$24,$25 + dpsu.h.obl $ac2,$17,$18 + dpsu.h.obr $ac3,$18,$19 + dshilo $ac3,-64 + dshilo $ac3,63 + dshilov $ac0,$2 + ldx $16,$17($18) + maq_sa.w.qhll $ac3,$10,$11 + maq_sa.w.qhlr $ac0,$11,$12 + maq_sa.w.qhrl $ac1,$12,$13 + maq_sa.w.qhrr $ac2,$13,$14 + maq_s.l.pwl $ac1,$16,$17 + maq_s.l.pwr $ac2,$17,$18 + maq_s.w.qhll $ac3,$10,$11 + maq_s.w.qhlr $ac0,$11,$12 + maq_s.w.qhrl $ac1,$12,$13 + maq_s.w.qhrr $ac2,$13,$14 + muleq_s.pw.qhl $11,$12,$13 + muleq_s.pw.qhr $12,$13,$14 + muleu_s.qh.obl $4,$5,$6 + muleu_s.qh.obr $5,$6,$7 + mulq_rs.ph $6,$7,$8 + mulq_rs.qh $8,$9,$10 + mulsaq_s.w.qh $ac0,$27,$28 + mulsaq_s.l.pw $ac2,$29,$30 + packrl.pw $28,$29,$30 + pick.ob $25,$26,$27 + pick.qh $26,$27,$28 + pick.pw $27,$28,$29 + preceq.pw.qhl $14,$15 + preceq.pw.qhr $15,$16 + preceq.pw.qhla $16,$17 + preceq.pw.qhra $17,$18 + preceq.s.l.pwl $18,$19 + preceq.s.l.pwr $19,$20 + precequ.pw.qhl $24,$25 + precequ.pw.qhr $25,$26 + precequ.pw.qhla $26,$27 + precequ.pw.qhra $27,$28 + preceu.qh.obl $28,$29 + preceu.qh.obr $29,$30 + preceu.qh.obla $30,$31 + preceu.qh.obra $31,$0 + precrq.ob.qh $4,$5,$6 + precrq.pw.l $7,$8,$9 + precrq.qh.pw $5,$6,$7 + precrq_rs.qh.pw $6,$7,$8 + precrqu_s.ob.qh $9,$10,$11 + raddu.l.ob $26,$27 + repl.ob $29,0 + repl.ob $29,255 + replv.ob $30,$31 + repl.qh $1,-512 + repl.qh $1,511 + replv.qh $2,$3 + repl.pw $3,-512 + repl.pw $3,511 + replv.pw $4,$5 + shll.ob $2,$3,0 + shll.ob $2,$3,7 + shllv.ob $3,$4,$5 + shll.qh $8,$9,0 + shll.qh $8,$9,15 + shllv.qh $9,$10,$11 + shll_s.qh $10,$11,0 + shll_s.qh $10,$11,15 + shllv_s.qh $11,$12,$13 + shll.pw $14,$15,0 + shll.pw $14,$15,31 + shllv.pw $15,$16,$17 + shll_s.pw $16,$17,0 + shll_s.pw $16,$17,31 + shllv_s.pw $17,$18,$19 + shra.qh $28,$29,0 + shra.qh $28,$29,15 + shrav.qh $29,$30,$31 + shra_r.qh $30,$31,0 + shra_r.qh $30,$31,15 + shrav_r.qh $31,$0,$1 + shra.pw $0,$1,0 + shra.pw $0,$1,31 + shrav.pw $1,$2,$3 + shra_r.pw $2,$3,0 + shra_r.pw $2,$3,31 + shrav_r.pw $3,$4,$5 + shrl.ob $20,$21,0 + shrl.ob $20,$21,7 + shrlv.ob $21,$22,$23 + subq.qh $16,$17,$18 + subq_s.qh $17,$18,$19 + subq.pw $18,$19,$20 + subq_s.pw $19,$20,$21 + subu.ob $20,$21,$22 + subu_s.ob $21,$22,$23 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/mips/noreorder.d b/gas/testsuite/gas/mips/noreorder.d new file mode 100644 index 000000000000..0866ca018314 --- /dev/null +++ b/gas/testsuite/gas/mips/noreorder.d @@ -0,0 +1,23 @@ +#objdump: -dr --disassemble-zeroes +#as: -march=mips2 -mabi=32 +#name: noreorder test + +.*: +file format .*mips.* + +Disassembly of section .text: + +00000000 <per_cpu_trap_init>: + 0: 00000000 nop + 4: 00000000 nop + 8: 0c000000 jal 0 <per_cpu_trap_init> + 8: R_MIPS_26 cpu_cache_init + c: 00000000 nop + 10: 8fbf0010 lw ra,16\(sp\) + 14: 08000000 j 0 <per_cpu_trap_init> + 14: R_MIPS_26 tlb_init + 18: 27bd0018 addiu sp,sp,24 + 1c: 00000000 nop + 20: 00000000 nop + 24: 1000fff6 b 0 <per_cpu_trap_init> + 28: 00000000 nop + 2c: 00000000 nop diff --git a/gas/testsuite/gas/mips/noreorder.s b/gas/testsuite/gas/mips/noreorder.s new file mode 100644 index 000000000000..71e92efacf21 --- /dev/null +++ b/gas/testsuite/gas/mips/noreorder.s @@ -0,0 +1,25 @@ + .text + .globl per_cpu_trap_init + .ent per_cpu_trap_init + .type per_cpu_trap_init, @function +per_cpu_trap_init: +$L807: + nop + nop + # Removing this .align make the code assemble correctly + .align 3 + jal cpu_cache_init + lw $31,16($sp) + .set noreorder + j tlb_init + addiu $sp,$sp,24 + # Replacing this .word with a nop causes the code to be assembled corrrectly + .word 0 + # Removing this nop causes the code to be compiled correctly + nop + .set reorder + + b $L807 + .end per_cpu_trap_init + + .p2align 4 diff --git a/gas/testsuite/gas/mips/set-arch.d b/gas/testsuite/gas/mips/set-arch.d index 66e52654b9e0..7639adb2822f 100644 --- a/gas/testsuite/gas/mips/set-arch.d +++ b/gas/testsuite/gas/mips/set-arch.d @@ -168,9 +168,9 @@ Disassembly of section \.text: 00000280 <[^>]*> 000000c0 sll zero,zero,0x3 00000284 <[^>]*> 7ca43980 0x7ca43980 00000288 <[^>]*> 7ca46984 0x7ca46984 -0000028c <[^>]*> 0100fc09 0x100fc09 -00000290 <[^>]*> 0120a409 0x120a409 -00000294 <[^>]*> 01000408 0x1000408 +0000028c <[^>]*> 0100fc09 jalr.hb t0 +00000290 <[^>]*> 0120a409 jalr.hb s4,t1 +00000294 <[^>]*> 01000408 jr.hb t0 00000298 <[^>]*> 7c0a003b 0x7c0a003b 0000029c <[^>]*> 7c0b083b 0x7c0b083b 000002a0 <[^>]*> 7c0c103b 0x7c0c103b @@ -334,7 +334,7 @@ Disassembly of section \.text: 00000518 <[^>]*> 48a41018 0x48a41018 0000051c <[^>]*> 4984101f 0x4984101f 00000520 <[^>]*> 49c4101f 0x49c4101f -00000524 <[^>]*> 4904101f 0x4904101f +00000524 <[^>]*> 4904101f bc2f \$cc1,000045a4 <[^>]*> 00000528 <[^>]*> 4944101f 0x4944101f 0000052c <[^>]*> 48c62090 0x48c62090 00000530 <[^>]*> 4bce3110 c2 0x1ce3110 diff --git a/gas/testsuite/gas/mips/smartmips.d b/gas/testsuite/gas/mips/smartmips.d new file mode 100644 index 000000000000..8bff68285d49 --- /dev/null +++ b/gas/testsuite/gas/mips/smartmips.d @@ -0,0 +1,29 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: SmartMIPS +#as: -msmartmips -32 + + +.*: +file format .*mips.* + +Disassembly of section \.text: + +0+0000 <[^>]*> 00c52046 rorv \$4,\$5,\$6 +0+0004 <[^>]*> 00c52046 rorv \$4,\$5,\$6 +0+0008 <[^>]*> 00c52046 rorv \$4,\$5,\$6 +0+000c <[^>]*> 00c52046 rorv \$4,\$5,\$6 +0+0010 <[^>]*> 002527c2 ror \$4,\$5,0x1f +0+0014 <[^>]*> 00252202 ror \$4,\$5,0x8 +0+0018 <[^>]*> 00252042 ror \$4,\$5,0x1 +0+001c <[^>]*> 00252002 ror \$4,\$5,0x0 +0+0020 <[^>]*> 002527c2 ror \$4,\$5,0x1f +0+0024 <[^>]*> 00252042 ror \$4,\$5,0x1 +0+0028 <[^>]*> 00252602 ror \$4,\$5,0x18 +0+002c <[^>]*> 002527c2 ror \$4,\$5,0x1f +0+0030 <[^>]*> 00252002 ror \$4,\$5,0x0 +0+0034 <[^>]*> 70a41088 lwxs \$2,\$4\(\$5\) +0+0038 <[^>]*> 72110441 maddp \$16,\$17 +0+003c <[^>]*> 016c0459 multp \$11,\$12 +0+0040 <[^>]*> 00004052 mflhxu \$8 +0+0044 <[^>]*> 00800053 mtlhx \$4 +0+0048 <[^>]*> 70d80481 pperm \$6,\$24 +0+004c <[^>]*> 00000000 nop diff --git a/gas/testsuite/gas/mips/smartmips.s b/gas/testsuite/gas/mips/smartmips.s new file mode 100644 index 000000000000..00e9895bd013 --- /dev/null +++ b/gas/testsuite/gas/mips/smartmips.s @@ -0,0 +1,31 @@ +# Source file used to test SmartMIPS instruction set + + .text +stuff: + ror $4,$5,$6 + rorv $4,$5,$6 + rotr $4,$5,$6 + rotrv $4,$5,$6 + + ror $4,$5,31 + ror $4,$5,8 + ror $4,$5,1 + ror $4,$5,0 + rotr $4,$5,31 + + rol $4,$5,31 + rol $4,$5,8 + rol $4,$5,1 + rol $4,$5,0 + + lwxs $2,$4($5) + + maddp $16,$17 + multp $11,$12 + + mflhxu $8 + mtlhx $4 + + pperm $6,$24 + + .p2align 4 diff --git a/gas/testsuite/gas/mmix/bspec-1.d b/gas/testsuite/gas/mmix/bspec-1.d index 2b15a4c443d0..c648a02f676d 100644 --- a/gas/testsuite/gas/mmix/bspec-1.d +++ b/gas/testsuite/gas/mmix/bspec-1.d @@ -23,4 +23,5 @@ Hex dump of section '\.text': 0x0+ fd010203 .* Hex dump of section '\.MMIX\.spec_data\.2': + NOTE: This section has relocations against it, but these have NOT been applied to this dump. 0x0+ 00000000 .* diff --git a/gas/testsuite/gas/mmix/bspec-2.d b/gas/testsuite/gas/mmix/bspec-2.d index 04fdbdd5e5ff..73cf96c8b972 100644 --- a/gas/testsuite/gas/mmix/bspec-2.d +++ b/gas/testsuite/gas/mmix/bspec-2.d @@ -23,4 +23,5 @@ Hex dump of section '\.text': 0x0+ fd010203 .* Hex dump of section '\.MMIX\.spec_data\.2': + NOTE: This section has relocations against it, but these have NOT been applied to this dump. 0x0+ 00000000 0000002a 00000000 00000000 .* diff --git a/gas/testsuite/gas/mmix/comment-1.d b/gas/testsuite/gas/mmix/comment-1.d index 142dca78fe8a..22ffdf5160a4 100644 --- a/gas/testsuite/gas/mmix/comment-1.d +++ b/gas/testsuite/gas/mmix/comment-1.d @@ -31,6 +31,7 @@ Symbol table '\.symtab' contains 12 entries: 11: 0+ 0 NOTYPE GLOBAL DEFAULT UND target3 Hex dump of section '\.text': + NOTE: This section has relocations against it, but these have NOT been applied to this dump. 0x0+ 0000007b 00010017 00010203 01030201 .* 0x0+10 09050006 09070208 0509000a 050b030c .* 0x0+20 230f1011 23121300 23141516 34170018 .* diff --git a/gas/testsuite/gas/mmix/mmix-list.exp b/gas/testsuite/gas/mmix/mmix-list.exp index 8d2a294f7c5b..e4a98d0cd80b 100644 --- a/gas/testsuite/gas/mmix/mmix-list.exp +++ b/gas/testsuite/gas/mmix/mmix-list.exp @@ -1,4 +1,4 @@ -# Copyright (C) 2001 Free Software Foundation, Inc. +# Copyright (C) 2001, 2007 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,24 +18,6 @@ if { ! [istarget "mmix-*"] } { return } -proc run_list_test { name opts } { - global srcdir subdir runtests - - if ![runtest_file_p $runtests $name] then { - return - } - - set testname "mmix list $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - proc run_mmix_list_tests { } { global srcdir subdir runtests foreach test_name [lsort [find ${srcdir}/${subdir} *.l]] { diff --git a/gas/testsuite/gas/mn10300/basic.exp b/gas/testsuite/gas/mn10300/basic.exp index b80e006cd215..37c1972738ff 100644 --- a/gas/testsuite/gas/mn10300/basic.exp +++ b/gas/testsuite/gas/mn10300/basic.exp @@ -1,4 +1,4 @@ -# Copyright (C) 1996, 2000, 2002, 2004 Free Software Foundation, Inc. +# Copyright (C) 1996, 2000, 2002, 2004, 2007 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -1768,20 +1768,6 @@ proc do_am33_8 {} { if [expr $x==67] then { pass $testname } else { fail $testname } } -proc run_list_test { name opts } { - global srcdir subdir - set testname "mn10300 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - return - } - pass $testname -} - - if [istarget mn10300*-*-*] then { # Test the basic instruction parser. do_add diff --git a/gas/testsuite/gas/msp430/msp430.exp b/gas/testsuite/gas/msp430/msp430.exp index a45ae4b630b5..c5e8052e0422 100644 --- a/gas/testsuite/gas/msp430/msp430.exp +++ b/gas/testsuite/gas/msp430/msp430.exp @@ -1,19 +1,6 @@ # # msp430 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "msp430 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - exit - return - } - pass $testname -} if [expr [istarget "msp430-*-*"]] then { run_dump_test "opcode" diff --git a/gas/testsuite/gas/pdp11/pdp11.exp b/gas/testsuite/gas/pdp11/pdp11.exp index 9ee6435df12a..91ccddbb2ef2 100644 --- a/gas/testsuite/gas/pdp11/pdp11.exp +++ b/gas/testsuite/gas/pdp11/pdp11.exp @@ -1,19 +1,6 @@ # # pdp11/pdp11 tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "pdp11 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - exit - return - } - pass $testname -} if [expr [istarget "pdp11-*-*"]] then { diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d index 56c7d5e3ae45..b07033f675e5 100644 --- a/gas/testsuite/gas/ppc/booke.d +++ b/gas/testsuite/gas/ppc/booke.d @@ -142,11 +142,15 @@ Disassembly of section \.text: 1c0: 7c 00 06 ac mbar 1c4: 7c 00 06 ac mbar 1c8: 7c 20 06 ac mbar 1 - 1cc: 7c 12 42 a6 mfsprg r0,2 - 1d0: 7c 12 42 a6 mfsprg r0,2 - 1d4: 7c 12 43 a6 mtsprg 2,r0 - 1d8: 7c 12 43 a6 mtsprg 2,r0 - 1dc: 7c 07 42 a6 mfsprg r0,7 - 1e0: 7c 07 42 a6 mfsprg r0,7 - 1e4: 7c 17 43 a6 mtsprg 7,r0 - 1e8: 7c 17 43 a6 mtsprg 7,r0 + 1cc: 7d 8d 77 24 tlbsx r12,r13,r14 + 1d0: 7d 8d 77 25 tlbsx\. r12,r13,r14 + 1d4: 7d 8d 77 26 tlbsxe r12,r13,r14 + 1d8: 7d 8d 77 27 tlbsxe\. r12,r13,r14 + 1dc: 7c 12 42 a6 mfsprg r0,2 + 1e0: 7c 12 42 a6 mfsprg r0,2 + 1e4: 7c 12 43 a6 mtsprg 2,r0 + 1e8: 7c 12 43 a6 mtsprg 2,r0 + 1ec: 7c 07 42 a6 mfsprg r0,7 + 1f0: 7c 07 42 a6 mfsprg r0,7 + 1f4: 7c 17 43 a6 mtsprg 7,r0 + 1f8: 7c 17 43 a6 mtsprg 7,r0 diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s index 0c6cf88f66a4..fa53c019b674 100644 --- a/gas/testsuite/gas/ppc/booke.s +++ b/gas/testsuite/gas/ppc/booke.s @@ -135,6 +135,11 @@ branch_target_8: mbar 0 mbar 1 + tlbsx 12, 13, 14 + tlbsx. 12, 13, 14 + tlbsxe 12, 13, 14 + tlbsxe. 12, 13, 14 + mfsprg 0, 2 mfsprg2 0 mtsprg 2, 0 diff --git a/gas/testsuite/gas/ppc/cell.d b/gas/testsuite/gas/ppc/cell.d new file mode 100644 index 000000000000..799a8e09aba8 --- /dev/null +++ b/gas/testsuite/gas/ppc/cell.d @@ -0,0 +1,31 @@ +#as: -mcell +#objdump: -dr -Mcell +#name: Cell tests + + +.*: +file format elf(32)?(64)?-powerpc.* + + +Disassembly of section \.text: + +0000000000000000 <.text>: + 0: 7c 01 14 0e lvlx v0,r1,r2 + 4: 7c 00 14 0e lvlx v0,0,r2 + 8: 7c 01 16 0e lvlxl v0,r1,r2 + c: 7c 00 16 0e lvlxl v0,0,r2 + 10: 7c 01 14 4e lvrx v0,r1,r2 + 14: 7c 00 14 4e lvrx v0,0,r2 + 18: 7c 01 16 4e lvrxl v0,r1,r2 + 1c: 7c 00 16 4e lvrxl v0,0,r2 + 20: 7c 01 15 0e stvlx v0,r1,r2 + 24: 7c 00 15 0e stvlx v0,0,r2 + 28: 7c 01 17 0e stvlxl v0,r1,r2 + 2c: 7c 00 17 0e stvlxl v0,0,r2 + 30: 7c 01 15 4e stvrx v0,r1,r2 + 34: 7c 00 15 4e stvrx v0,0,r2 + 38: 7c 01 17 4e stvrxl v0,r1,r2 + 3c: 7c 00 17 4e stvrxl v0,0,r2 + 40: 7c 00 0c 28 ldbrx r0,0,r1 + 44: 7c 01 14 28 ldbrx r0,r1,r2 + 48: 7c 00 0d 28 stdbrx r0,0,r1 + 4c: 7c 01 15 28 stdbrx r0,r1,r2 diff --git a/gas/testsuite/gas/ppc/cell.s b/gas/testsuite/gas/ppc/cell.s new file mode 100644 index 000000000000..29853866147e --- /dev/null +++ b/gas/testsuite/gas/ppc/cell.s @@ -0,0 +1,24 @@ + .section ".text" + lvlx %r0, %r1, %r2 + lvlx %r0, 0, %r2 + lvlxl %r0, %r1, %r2 + lvlxl %r0, 0, %r2 + lvrx %r0, %r1, %r2 + lvrx %r0, 0, %r2 + lvrxl %r0, %r1, %r2 + lvrxl %r0, 0, %r2 + + stvlx %r0, %r1, %r2 + stvlx %r0, 0, %r2 + stvlxl %r0, %r1, %r2 + stvlxl %r0, 0, %r2 + stvrx %r0, %r1, %r2 + stvrx %r0, 0, %r2 + stvrxl %r0, %r1, %r2 + stvrxl %r0, 0, %r2 + + ldbrx %r0, 0, %r1 + ldbrx %r0, %r1, %r2 + + stdbrx %r0, 0, %r1 + stdbrx %r0, %r1, %r2 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 0dd4648f021d..0e2db22c66ee 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -11,6 +11,8 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then { run_dump_test "astest2_64" run_dump_test "test1elf64" run_dump_test "power4" + run_dump_test "cell" + run_list_test "range64" "-a64" } elseif { [istarget powerpc*-*aix*] } then { run_dump_test "test1xcoff32" } elseif { [istarget powerpc*-*-*bsd*] \ @@ -38,5 +40,6 @@ if { [istarget powerpc*-*-*] } then { run_dump_test "altivec" run_dump_test "booke" run_dump_test "e500" + run_list_test "range" "-a32" } } diff --git a/gas/testsuite/gas/ppc/range.l b/gas/testsuite/gas/ppc/range.l new file mode 100644 index 000000000000..9a71ca4f88f3 --- /dev/null +++ b/gas/testsuite/gas/ppc/range.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:6: Error: operand out of range.* +.*:7: Error: operand out of range.* diff --git a/gas/testsuite/gas/ppc/range.s b/gas/testsuite/gas/ppc/range.s new file mode 100644 index 000000000000..04251e5e93bf --- /dev/null +++ b/gas/testsuite/gas/ppc/range.s @@ -0,0 +1,7 @@ + .text + lbz 4,-32768(3) + lbz 5,-1(3) + lbz 6,2(3) + lbz 7,32767(3) + lbz 8,32768(3) + lbz 9,-32769(3) diff --git a/gas/testsuite/gas/ppc/range64.l b/gas/testsuite/gas/ppc/range64.l new file mode 100644 index 000000000000..6e28b7c7e9fc --- /dev/null +++ b/gas/testsuite/gas/ppc/range64.l @@ -0,0 +1,6 @@ +.*: Assembler messages: +.*:3: Error: operand out of domain \(-1 is not a multiple of 4\) +.*:4: Error: operand out of domain \(2 is not a multiple of 4\) +.*:5: Error: operand out of range.* +.*:6: Error: operand out of range.* +.*:7: Error: operand out of range.* diff --git a/gas/testsuite/gas/ppc/range64.s b/gas/testsuite/gas/ppc/range64.s new file mode 100644 index 000000000000..b4a04cf76314 --- /dev/null +++ b/gas/testsuite/gas/ppc/range64.s @@ -0,0 +1,7 @@ + .text + ld 4,-32768(3) + ld 5,-1(3) + ld 6,2(3) + ld 7,32767(3) + ld 8,32768(3) + ld 9,-32769(3) diff --git a/gas/testsuite/gas/ppc/reloc.d b/gas/testsuite/gas/ppc/reloc.d new file mode 100644 index 000000000000..006604b12b9c --- /dev/null +++ b/gas/testsuite/gas/ppc/reloc.d @@ -0,0 +1,12 @@ +#readelf: -r --wide +#name: reloc + +Relocation section '\.rela\.data' at .* contains 2 entries: + Offset Info Type Sym\. Value Symbol's Name \+ Addend +0+08 .* R_PPC_ADDR32 .* y \+ f+fc +0+0c .* R_PPC_ADDR32 .* y \+ 0 + +Relocation section '\.rela\.data\.other' at .* contains 2 entries: + Offset Info Type Sym\. Value Symbol's Name \+ Addend +0+00 .* R_PPC_ADDR32 .* x \+ 0 +0+04 .* R_PPC_ADDR32 .* x \+ f+fc diff --git a/gas/testsuite/gas/ppc/reloc.s b/gas/testsuite/gas/ppc/reloc.s new file mode 100644 index 000000000000..19e4355eb71f --- /dev/null +++ b/gas/testsuite/gas/ppc/reloc.s @@ -0,0 +1,13 @@ + .reloc x+8, R_PPC_ADDR32, y-4 + + .data +x: + .long 0,0,0,0 + + .section .data.other,"aw",@progbits +y: + .long 0,0,0,0 + + .reloc 0, R_PPC_ADDR32, x + .reloc y+4, R_PPC_ADDR32, x-4 + .reloc x+12, R_PPC_ADDR32, y diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d index 0c38e419b82b..16021f6e93ef 100644 --- a/gas/testsuite/gas/s390/esa-g5.d +++ b/gas/testsuite/gas/s390/esa-g5.d @@ -104,9 +104,9 @@ Disassembly of section .text: .*: b3 b4 00 69 [ ]*cefr %r6,%f9 .*: 39 69 [ ]*cer %f6,%f9 .*: b2 1a 5f ff [ ]*cfc 4095\(%r5\) -.*: b3 99 50 69 [ ]*cfdbr %f6,5,%r9 -.*: b3 98 50 69 [ ]*cfebr %f6,5,%r9 -.*: b3 9a 50 69 [ ]*cfxbr %f6,5,%r9 +.*: b3 99 50 69 [ ]*cfdbr %r6,5,%f9 +.*: b3 98 50 69 [ ]*cfebr %r6,5,%f9 +.*: b3 9a 50 69 [ ]*cfxbr %r6,5,%f9 .*: 49 65 af ff [ ]*ch %r6,4095\(%r5,%r10\) .*: a7 6e 80 01 [ ]*chi %r6,-32767 .*: b2 41 00 69 [ ]*cksm %r6,%r9 @@ -341,7 +341,7 @@ Disassembly of section .text: .*: b2 18 5f ff [ ]*pc 4095\(%r5\) .*: b2 2e 00 69 [ ]*pgin %r6,%r9 .*: b2 2f 00 69 [ ]*pgout %r6,%r9 -.*: e9 ff 5f ff af ff [ ]*pka 4095\(256,%r5\),4095\(%r10\) +.*: e9 1f 5f ff af ff [ ]*pka 4095\(%r5\),4095\(32,%r10\) .*: e1 ff 5f ff af ff [ ]*pku 4095\(256,%r5\),4095\(%r10\) .*: ee 69 5f ff af ff [ ]*plo %r6,4095\(%r5\),%r9,4095\(%r10\) .*: 01 01 [ ]*pr diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s index 314cbbb09640..3ff0b5343600 100644 --- a/gas/testsuite/gas/s390/esa-g5.s +++ b/gas/testsuite/gas/s390/esa-g5.s @@ -98,9 +98,9 @@ foo: cefr %r6,%f9 cer %f6,%f9 cfc 4095(%r5) - cfdbr %r6,5,%r9 - cfebr %r6,5,%r9 - cfxbr %r6,5,%r9 + cfdbr %r6,5,%f9 + cfebr %r6,5,%f9 + cfxbr %r6,5,%f9 ch %r6,4095(%r5,%r10) chi %r6,-32767 cksm %r6,%r9 @@ -335,7 +335,7 @@ foo: pc 4095(%r5) pgin %r6,%r9 pgout %r6,%r9 - pka 4095(256,%r5),4095(%r10) + pka 4095(%r5),4095(32,%r10) pku 4095(256,%r5),4095(%r10) plo %r6,4095(%r5),%r9,4095(%r10) pr diff --git a/gas/testsuite/gas/s390/operands.d b/gas/testsuite/gas/s390/operands.d deleted file mode 100644 index d1744086ba26..000000000000 --- a/gas/testsuite/gas/s390/operands.d +++ /dev/null @@ -1,23 +0,0 @@ -#name: s390 operands -#objdump: -dr - -.*: +file format .* - -Disassembly of section .text: - -.* <foo>: - 0: 01 01 [ ]*pr - 2: a7 1a 80 01 [ ]*ahi %r1,-32767 - 6: 18 12 [ ]*lr %r1,%r2 - 8: b2 5e 00 12 [ ]*srst %r1,%r2 - c: b3 5b 93 12 [ ]*didbr %f1,%f9,%f2,3 - 10: ba 12 40 03 [ ]*cs %r1,%r2,3\(%r4\) - 14: 84 12 00 00 [ ]*brxh %r1,%r2,14 <foo\+0x14> -[ ]*16: R_390_PC16DBL test_rsi\+0x2 - 18: 58 13 40 02 [ ]*l %r1,2\(%r3,%r4\) - 1c: ed 10 30 02 00 1a [ ]*adb %f1,2\(%r3\) - 22: ed 24 50 03 10 1e [ ]*madb %f1,%f2,3\(%r4,%r5\) - 28: b2 33 20 01 [ ]*ssch 1\(%r2\) - 2c: 92 03 20 01 [ ]*mvi 1\(%r2\),3 - 30: d2 26 30 01 50 04 [ ]*mvc 1\(39,%r3\),4\(%r5\) - 36: e5 01 20 01 40 03 [ ]*tprot 1\(%r2\),3\(%r4\) diff --git a/gas/testsuite/gas/s390/operands.s b/gas/testsuite/gas/s390/operands.s deleted file mode 100644 index 9f030e835f75..000000000000 --- a/gas/testsuite/gas/s390/operands.s +++ /dev/null @@ -1,16 +0,0 @@ -.text -foo: - .insn e,0x0101 - .insn ri,0xa70a0000,%r1,-32767 - .insn rr,0x1800,%r1,%r2 - .insn rre,0xb25e0000,%r1,%r2 - .insn rrf,0xb35b0000,%f1,%f2,9,%f3 - .insn rs,0xba000000,%r1,%r2,3(%r4) - .insn rsi,0x84000000,%r1,%r2,test_rsi - .insn rx,0x58000000,%r1,2(%r3,%r4) - .insn rxe,0xed000000001a,%f1,2(%r3) - .insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5) - .insn s,0xb2330000,1(%r2) - .insn si,0x92000000,1(%r2),3 - .insn ss,0xd20000000000,1(2,%r3),4(%r5),6 - .insn sse,0xe50100000000,1(%r2),3(%r4) diff --git a/gas/testsuite/gas/s390/operands64.d b/gas/testsuite/gas/s390/operands64.d deleted file mode 100644 index 5cae0553e146..000000000000 --- a/gas/testsuite/gas/s390/operands64.d +++ /dev/null @@ -1,14 +0,0 @@ -#name: s390x operands -#objdump: -dr - -.*: +file format .* - -Disassembly of section .text: - -.* <foo>: - 0: ec 12 00 00 00 45 [ ]*brxlg %r1,%r2,0 <foo> -[ ]*2: R_390_PC16DBL test_rie\+0x2 - 6: c0 e5 00 00 00 00 [ ]*brasl %r14,6 <foo\+0x6> -[ ]*8: R_390_PC32DBL test_ril\+0x2 - c: eb 12 40 03 00 0d [ ]*sllg %r1,%r2,3\(%r4\) - 12: 07 07 [ ]*bcr 0,%r7 diff --git a/gas/testsuite/gas/s390/operands64.s b/gas/testsuite/gas/s390/operands64.s deleted file mode 100644 index 6313cb275a00..000000000000 --- a/gas/testsuite/gas/s390/operands64.s +++ /dev/null @@ -1,6 +0,0 @@ -.text -foo: - .insn rie,0xec0000000045,%r1,%r2,test_rie - .insn ril,0xc00500000000,%r14,test_ril - .insn rse,0xeb000000000d,%r1,%r2,3(%r4) - diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 3d9a4a135c80..8739bdd93272 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -1,19 +1,6 @@ # # s390/s390x tests # -proc run_list_test { name opts } { - global srcdir subdir - set testname "s390 $name" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&dump.out" - if { [regexp_diff "dump.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "dump.out"]" 2 - exit - return - } - pass $testname -} if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { @@ -32,6 +19,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "zarch-z900" "{as -m64}" run_dump_test "zarch-z990" "{as -m64} {as -march=z990}" run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}" + run_dump_test "zarch-z9-ec" "{as -m64} {as -march=z9-ec}" run_dump_test "zarch-reloc" "{as -m64}" run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}" } diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.d b/gas/testsuite/gas/s390/zarch-z9-ec.d new file mode 100644 index 000000000000..142ec0db7506 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-z9-ec.d @@ -0,0 +1,76 @@ +#name: s390x opcode +#objdump: -drw + +.*: +file format .* + +Disassembly of section .text: + +.* <foo>: +.*: b3 70 00 62 [ ]*lpdfr %f6,%f2 +.*: b3 71 00 62 [ ]*lndfr %f6,%f2 +.*: b3 72 10 62 [ ]*cpsdr %f6,%f1,%f2 +.*: b3 73 00 62 [ ]*lcdfr %f6,%f2 +.*: b3 c1 00 62 [ ]*ldgr %f6,%r2 +.*: b3 cd 00 26 [ ]*lgdr %r2,%f6 +.*: b3 d2 40 62 [ ]*adtr %f6,%f2,%f4 +.*: b3 da 40 62 [ ]*axtr %f6,%f2,%f4 +.*: b3 e4 00 62 [ ]*cdtr %f6,%f2 +.*: b3 ec 00 62 [ ]*cxtr %f6,%f2 +.*: b3 e0 00 62 [ ]*kdtr %f6,%f2 +.*: b3 e8 00 62 [ ]*kxtr %f6,%f2 +.*: b3 f4 00 62 [ ]*cedtr %f6,%f2 +.*: b3 fc 00 62 [ ]*cextr %f6,%f2 +.*: b3 f1 00 62 [ ]*cdgtr %f6,%r2 +.*: b3 f9 00 62 [ ]*cxgtr %f6,%r2 +.*: b3 f3 00 62 [ ]*cdstr %f6,%r2 +.*: b3 fb 00 62 [ ]*cxstr %f6,%r2 +.*: b3 f2 00 62 [ ]*cdutr %f6,%r2 +.*: b3 fa 00 62 [ ]*cxutr %f6,%r2 +.*: b3 e1 10 26 [ ]*cgdtr %r2,1,%f6 +.*: b3 e9 10 26 [ ]*cgxtr %r2,1,%f6 +.*: b3 e3 00 26 [ ]*csdtr %r2,%f6 +.*: b3 eb 00 26 [ ]*csxtr %r2,%f6 +.*: b3 e2 00 26 [ ]*cudtr %r2,%f6 +.*: b3 ea 00 26 [ ]*cuxtr %r2,%f6 +.*: b3 d1 40 62 [ ]*ddtr %f6,%f2,%f4 +.*: b3 d9 40 62 [ ]*dxtr %f6,%f2,%f4 +.*: b3 e5 00 26 [ ]*eedtr %r2,%f6 +.*: b3 ed 00 26 [ ]*eextr %r2,%f6 +.*: b3 e7 00 26 [ ]*esdtr %r2,%f6 +.*: b3 ef 00 26 [ ]*esxtr %r2,%f6 +.*: b3 f6 20 64 [ ]*iedtr %f6,%f2,%r4 +.*: b3 fe 20 64 [ ]*iextr %f6,%f2,%r4 +.*: b3 d6 00 62 [ ]*ltdtr %f6,%f2 +.*: b3 de 00 62 [ ]*ltxtr %f6,%f2 +.*: b3 d7 13 62 [ ]*fidtr %f6,1,%f2,3 +.*: b3 df 13 62 [ ]*fixtr %f6,1,%f2,3 +.*: b2 bd 10 03 [ ]*lfas 3\(%r1\) +.*: b3 d4 01 62 [ ]*ldetr %f6,%f2,1 +.*: b3 dc 01 62 [ ]*lxdtr %f6,%f2,1 +.*: b3 d5 13 62 [ ]*ledtr %f6,1,%f2,3 +.*: b3 dd 13 62 [ ]*ldxtr %f6,1,%f2,3 +.*: b3 d0 40 62 [ ]*mdtr %f6,%f2,%f4 +.*: b3 d8 40 62 [ ]*mxtr %f6,%f2,%f4 +.*: b3 f5 21 64 [ ]*qadtr %f6,%f2,%f4,1 +.*: b3 fd 21 64 [ ]*qaxtr %f6,%f2,%f4,1 +.*: b3 f7 21 64 [ ]*rrdtr %f6,%f2,%f4,1 +.*: b3 ff 21 64 [ ]*rrxtr %f6,%f2,%f4,1 +.*: b2 b9 10 03 [ ]*srnmt 3\(%r1\) +.*: b3 85 00 20 [ ]*sfasr %r2 +.*: ed 21 40 03 60 40 [ ]*sldt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 48 [ ]*slxt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 41 [ ]*srdt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 49 [ ]*srxt %f6,%f2,3\(%r1,%r4\) +.*: b3 d3 40 62 [ ]*sdtr %f6,%f2,%f4 +.*: b3 db 40 62 [ ]*sxtr %f6,%f2,%f4 +.*: ed 61 20 03 00 50 [ ]*tcet %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 54 [ ]*tcdt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 58 [ ]*tcxt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 51 [ ]*tget %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 55 [ ]*tgdt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 59 [ ]*tgxt %f6,3\(%r1,%r2\) +.*: 01 0a [ ]*pfpo +.*: c8 31 10 0a 20 14 [ ]*ectg 10\(%r1\),20\(%r2\),%r3 +.*: c8 32 10 0a 20 14 [ ]*csst 10\(%r1\),20\(%r2\),%r3 +# Expect 2 bytes of padding. +.*: 07 07 [ ]*bcr 0,%r7 diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.s b/gas/testsuite/gas/s390/zarch-z9-ec.s new file mode 100644 index 000000000000..9139b7543a8a --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-z9-ec.s @@ -0,0 +1,72 @@ +.text +foo: + lpdfr %f6,%f2 + lndfr %f6,%f2 + cpsdr %f6,%f1,%f2 + lcdfr %f6,%f2 + ldgr %f6,%r2 + lgdr %r2,%f6 + adtr %f6,%f2,%f4 + axtr %f6,%f2,%f4 + cdtr %f6,%f2 + cxtr %f6,%f2 + kdtr %f6,%f2 + kxtr %f6,%f2 + cedtr %f6,%f2 + cextr %f6,%f2 + cdgtr %f6,%r2 + cxgtr %f6,%r2 + cdstr %f6,%r2 + cxstr %f6,%r2 + cdutr %f6,%r2 + cxutr %f6,%r2 + cgdtr %r2,1,%f6 + cgxtr %r2,1,%f6 + csdtr %r2,%f6 + csxtr %r2,%f6 + cudtr %r2,%f6 + cuxtr %r2,%f6 + ddtr %f6,%f2,%f4 + dxtr %f6,%f2,%f4 + eedtr %r2,%f6 + eextr %r2,%f6 + esdtr %r2,%f6 + esxtr %r2,%f6 + iedtr %f6,%f2,%r4 + iextr %f6,%f2,%r4 + ltdtr %f6,%f2 + ltxtr %f6,%f2 + fidtr %f6,1,%f2,3 + fixtr %f6,1,%f2,3 + lfas 3(%r1) + ldetr %f6,%f2,1 + lxdtr %f6,%f2,1 + ledtr %f6,1,%f2,3 + ldxtr %f6,1,%f2,3 + mdtr %f6,%f2,%f4 + mxtr %f6,%f2,%f4 + qadtr %f6,%f2,%f4,1 + qaxtr %f6,%f2,%f4,1 + rrdtr %f6,%f2,%f4,1 + rrxtr %f6,%f2,%f4,1 + srnmt 3(%r1) + sfasr %r2 + sldt %f6,%f2,3(%r1,%r4) + slxt %f6,%f2,3(%r1,%r4) + srdt %f6,%f2,3(%r1,%r4) + srxt %f6,%f2,3(%r1,%r4) + sdtr %f6,%f2,%f4 + sxtr %f6,%f2,%f4 + tcet %f6,3(%r1,%r2) + tcdt %f6,3(%r1,%r2) + tcxt %f6,3(%r1,%r2) + tget %f6,3(%r1,%r2) + tgdt %f6,3(%r1,%r2) + tgxt %f6,3(%r1,%r2) + pfpo + ectg 10(%r1),20(%r2),%r3 + csst 10(%r1),20(%r2),%r3 + /* The following .data section is 4 byte aligned. + So we get 2 additional bytes of 07 07 wherefor + we have to provide an instruction. */ + bcr 0,%r7 diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d index 0f701282acf9..dc21077dedfd 100644 --- a/gas/testsuite/gas/s390/zarch-z900.d +++ b/gas/testsuite/gas/s390/zarch-z900.d @@ -29,20 +29,20 @@ Disassembly of section .text: .*: eb 96 5f ff 00 3e [ ]*cdsg %r9,%r6,4095\(%r5\) .*: b3 a4 00 96 [ ]*cegbr %r9,%r6 .*: b3 c4 00 96 [ ]*cegr %r9,%r6 -.*: b3 b9 90 65 [ ]*cfdr %f6,9,%r5 -.*: b3 b8 90 65 [ ]*cfer %f6,9,%r5 -.*: b3 ba 90 65 [ ]*cfxr %f6,9,%r5 +.*: b3 b9 90 65 [ ]*cfdr %r6,9,%f5 +.*: b3 b8 90 65 [ ]*cfer %r6,9,%f5 +.*: b3 ba 90 65 [ ]*cfxr %r6,9,%f5 .*: e3 95 af ff 00 20 [ ]*cg %r9,4095\(%r5,%r10\) -.*: b3 a9 f0 65 [ ]*cgdbr %f6,15,%r5 -.*: b3 c9 f0 65 [ ]*cgdr %f6,15,%r5 -.*: b3 a8 f0 65 [ ]*cgebr %f6,15,%r5 -.*: b3 c8 f0 65 [ ]*cger %f6,15,%r5 +.*: b3 a9 f0 65 [ ]*cgdbr %r6,15,%f5 +.*: b3 c9 f0 65 [ ]*cgdr %r6,15,%f5 +.*: b3 a8 f0 65 [ ]*cgebr %r6,15,%f5 +.*: b3 c8 f0 65 [ ]*cger %r6,15,%f5 .*: e3 95 af ff 00 30 [ ]*cgf %r9,4095\(%r5,%r10\) .*: b9 30 00 96 [ ]*cgfr %r9,%r6 .*: a7 9f 80 01 [ ]*cghi %r9,-32767 .*: b9 20 00 96 [ ]*cgr %r9,%r6 -.*: b3 aa f0 65 [ ]*cgxbr %f6,15,%r5 -.*: b3 ca f0 65 [ ]*cgxr %f6,15,%r5 +.*: b3 aa f0 65 [ ]*cgxbr %r6,15,%f5 +.*: b3 ca f0 65 [ ]*cgxr %r6,15,%f5 .*: e3 95 af ff 00 21 [ ]*clg %r9,4095\(%r5,%r10\) .*: e3 95 af ff 00 31 [ ]*clgf %r9,4095\(%r5,%r10\) .*: b9 31 00 96 [ ]*clgfr %r9,%r6 diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s index f5e737113c5e..688033a32e91 100644 --- a/gas/testsuite/gas/s390/zarch-z900.s +++ b/gas/testsuite/gas/s390/zarch-z900.s @@ -23,20 +23,20 @@ foo: cdsg %r9,%r6,4095(%r5) cegbr %r9,%r6 cegr %r9,%r6 - cfdr %f6,9,%r5 - cfer %f6,9,%r5 - cfxr %f6,9,%r5 + cfdr %r6,9,%f5 + cfer %r6,9,%f5 + cfxr %r6,9,%f5 cg %r9,4095(%r5,%r10) - cgdbr %f6,15,%r5 - cgdr %f6,15,%r5 - cgebr %f6,15,%r5 - cger %f6,15,%r5 + cgdbr %r6,15,%f5 + cgdr %r6,15,%f5 + cgebr %r6,15,%f5 + cger %r6,15,%f5 cgf %r9,4095(%r5,%r10) cgfr %r9,%r6 cghi %r9,-32767 cgr %r9,%r6 - cgxbr %f6,15,%r5 - cgxr %f6,15,%r5 + cgxbr %r6,15,%f5 + cgxr %r6,15,%f5 clg %r9,4095(%r5,%r10) clgf %r9,4095(%r5,%r10) clgfr %r9,%r6 diff --git a/gas/testsuite/gas/score/addi.d b/gas/testsuite/gas/score/addi.d new file mode 100644 index 000000000000..148ecd714339 --- /dev/null +++ b/gas/testsuite/gas/score/addi.d @@ -0,0 +1,33 @@ +#as: +#objdump: -d +#source: addi.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + 0: 84008003 addi.c r0, 1 + 4: 84008003 addi.c r0, 1 + 8: 85e08021 addi.c r15, 16 + c: 85e08021 addi.c r15, 16 + 10: 85e18001 addi.c r15, 16384 + 14: 85e18001 addi.c r15, 16384 + 18: 6818 addei! r8, 3 + 1a: 6818 addei! r8, 3 + 1c: 6f78 addei! r15, 15 + 1e: 0000 nop! + 20: 85e1ffff addi.c r15, 32767 + ... + 30: 8403ffff addi.c r0, -1 + 34: 8403ffff addi.c r0, -1 + 38: 85e3ffe1 addi.c r15, -16 + 3c: 85e3ffe1 addi.c r15, -16 + 40: 85e38001 addi.c r15, -16384 + 44: 85e38001 addi.c r15, -16384 + 48: 6898 subei! r8, 3 + 4a: 6898 subei! r8, 3 + 4c: 6ff8 subei! r15, 15 + 4e: 0000 nop! + 50: 85e1ffff addi.c r15, 32767 +#pass diff --git a/gas/testsuite/gas/score/addi.s b/gas/testsuite/gas/score/addi.s new file mode 100644 index 000000000000..e87620e5c590 --- /dev/null +++ b/gas/testsuite/gas/score/addi.s @@ -0,0 +1,37 @@ +/* + * test relax + * addi <-> addei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b + * (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767 + * (2)addei! rD, imm4 : rD = rD + 2**imm4 + * addi <-> subei! : for addei : register number must be in 0-15, offset : 4b, only 16b -> 32b + * (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767 + * (2)subei! rD, imm4 : rD = rD + 2**imm4 + + * Author: ligang + */ + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16, sign +.align 4 + + \insn16 r0, 0 #16b -> 32b + \insn32 r0, \sign * 1 + + \insn16 r15, 4 #16b -> 32b + \insn32 r15, \sign * 16 + + \insn16 r15, 14 #16b -> 32b + \insn32 r15, \sign * 1024 * 16 + + \insn16 r8, 3 #No transform + \insn16 r8, 3 #No transform + + \insn16 r15, 15 #No transform. Because 2**15 = 32768, extend range of addi + \insn32 r15, 0x7FFF + +.endm + +.text + + tran1632 "addi.c", "addei!", 1 + tran1632 "addi.c", "subei!", -1 diff --git a/gas/testsuite/gas/score/b.d b/gas/testsuite/gas/score/b.d new file mode 100644 index 000000000000..133540e4673d --- /dev/null +++ b/gas/testsuite/gas/score/b.d @@ -0,0 +1,18 @@ +#as: +#objdump: -d +#source: b.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <L1>: + 0: 4f00 b! 0 <L1> + 2: 4fff b! 0 <L1> + 4: 4ffe b! 0 <L1> + 6: 4ffd b! 0 <L1> + 8: 4ffc b! 0 <L1> + a: 4ffb b! 0 <L1> + c: 93ffbff4 b 0 <L1> + 10: 8254e010 add r18, r20, r24 +#pass diff --git a/gas/testsuite/gas/score/b.s b/gas/testsuite/gas/score/b.s new file mode 100644 index 000000000000..002347c04f38 --- /dev/null +++ b/gas/testsuite/gas/score/b.s @@ -0,0 +1,30 @@ +/* + * test relax + * b <-> b! : jump range must be in 8 bit, only 32b -> 16b + + * Author: ligang + */ + +.macro tran insn32, insn16 +/* This block transform 32b instruction to 16b. */ +.align 4 + + \insn32 #32b -> 16b + \insn16 + + \insn32 #32b -> 16b + \insn32 #32b -> 16b + + \insn16 + \insn32 #32b -> 16b + + \insn32 #No transform + add r18, r20, r24 + +.endm + +L1: + + tran "b L1", "b! L1" + #tran "b 0x8", "b! 0x8" + diff --git a/gas/testsuite/gas/score/bittst.d b/gas/testsuite/gas/score/bittst.d new file mode 100644 index 000000000000..0bb6651b30a3 --- /dev/null +++ b/gas/testsuite/gas/score/bittst.d @@ -0,0 +1,36 @@ +#as: +#objdump: -d +#source: bittst.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6016 bittst! r0, 0x2 + 2: 6016 bittst! r0, 0x2 + 4: 6f26 bittst! r15, 0x4 + 6: 6f26 bittst! r15, 0x4 + 8: 6f0e bittst! r15, 0x1 + a: 6f0e bittst! r15, 0x1 + c: 6f1e bittst! r15, 0x3 + e: 6f1e bittst! r15, 0x3 + 10: 6816 bittst! r8, 0x2 + 12: 6816 bittst! r8, 0x2 + 14: 800f842d bittst.c r15, 0x1 + 18: 801a902d bittst.c r26, 0x4 + 1c: 0000 nop! + 1e: 0000 nop! + 20: 8000882d bittst.c r0, 0x2 + 24: 8014882d bittst.c r20, 0x2 + 28: 81ef902d bittst.c r15, 0x4 + 2c: 8019902d bittst.c r25, 0x4 + 30: 81ef842d bittst.c r15, 0x1 + 34: 8019842d bittst.c r25, 0x1 + 38: 680e bittst! r8, 0x1 + 3a: 680e bittst! r8, 0x1 + 3c: 6626 bittst! r6, 0x4 + 3e: 6626 bittst! r6, 0x4 + 40: 671e bittst! r7, 0x3 + 42: 671e bittst! r7, 0x3 +#pass diff --git a/gas/testsuite/gas/score/bittst.s b/gas/testsuite/gas/score/bittst.s new file mode 100644 index 000000000000..b6657b9a5d5d --- /dev/null +++ b/gas/testsuite/gas/score/bittst.s @@ -0,0 +1,59 @@ +/* + * test relax + * bittst.c <-> bittst! : register number must be in 0-15 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 + + \insn32 r0, 2 #32b -> 16b + \insn16 r0, 2 + + \insn32 r15, 4 #32b -> 16b + \insn16 r15, 4 + + \insn32 r15, 1 #32b -> 16b + \insn16 r15, 1 + + \insn16 r15, 3 + \insn32 r15, 3 #32b -> 16b + + \insn32 r8, 2 #32b -> 16b + \insn32 r8, 2 #32b -> 16b + + \insn32 r15, 1 #No transform + \insn32 r26, 4 + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, 2 #16b -> 32b + \insn32 r20, 2 + + \insn16 r15, 4 #16b -> 32b + \insn32 r25, 4 + + \insn16 r15, 1 #16b -> 32b + \insn32 r25, 1 + + \insn16 r8, 1 #No transform + \insn16 r8, 1 #No transform + + \insn16 r6, 4 #No transform + \insn32 r6, 4 #32b -> 16b + + \insn32 r7, 3 #32b -> 16b + \insn16 r7, 3 #No transform + +.endm + +.text + + tran3216 "bittst.c", "bittst!" + tran1632 "bittst.c", "bittst!" + diff --git a/gas/testsuite/gas/score/br.d b/gas/testsuite/gas/score/br.d new file mode 100644 index 000000000000..273632fbd03f --- /dev/null +++ b/gas/testsuite/gas/score/br.d @@ -0,0 +1,49 @@ +#as: +#objdump: -d +#source: br.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + 0: 0f04 br! r0 + 2: 0f04 br! r0 + 4: 0ff4 br! r15 + 6: 0ff4 br! r15 + 8: 0f34 br! r3 + a: 0f34 br! r3 + c: 0f54 br! r5 + e: 0f54 br! r5 + 10: 8003bc08 br r3 + 14: 801fbc08 br r31 + ... + 20: 0f0c brl! r0 + 22: 0f0c brl! r0 + 24: 0ffc brl! r15 + 26: 0ffc brl! r15 + 28: 0f3c brl! r3 + 2a: 0f3c brl! r3 + 2c: 0f5c brl! r5 + 2e: 0f5c brl! r5 + 30: 8003bc09 brl r3 + 34: 801fbc09 brl r31 + ... + 40: 8000bc08 br r0 + 44: 8017bc08 br r23 + 48: 800fbc08 br r15 + 4c: 801bbc08 br r27 + 50: 0f64 br! r6 + 52: 0f64 br! r6 + 54: 0f34 br! r3 + 56: 0f34 br! r3 + ... + 60: 8000bc09 brl r0 + 64: 8017bc09 brl r23 + 68: 800fbc09 brl r15 + 6c: 801bbc09 brl r27 + 70: 0f6c brl! r6 + 72: 0f6c brl! r6 + 74: 0f3c brl! r3 + 76: 0f3c brl! r3 +#pass diff --git a/gas/testsuite/gas/score/br.s b/gas/testsuite/gas/score/br.s new file mode 100644 index 000000000000..e60e058d8190 --- /dev/null +++ b/gas/testsuite/gas/score/br.s @@ -0,0 +1,53 @@ +/* + * test relax + * br <-> br! : register number must be in 0-15 + * brl <-> brl! : register number must be in 0-15 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0 #32b -> 16b + \insn16 r0 + + \insn32 r15 #32b -> 16b + \insn16 r15 + + \insn32 r3 #32b -> 16b + \insn32 r3 #32b -> 16b + + \insn16 r5 + \insn32 r5 #32b -> 16b + + \insn32 r3 #No transform + \insn32 r31 #No transform + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0 #16b -> 32b + \insn32 r23 + + \insn16 r15 #16b -> 32b + \insn32 r27 + + \insn16 r6 #No transform + \insn32 r6 + + \insn16 r3 #No transform + \insn16 r3 + +.endm + + tran3216 "br", "br!" + tran3216 "brl", "brl!" + + tran1632 "br", "br!" + tran1632 "brl", "brl!" + diff --git a/gas/testsuite/gas/score/ldi.d b/gas/testsuite/gas/score/ldi.d new file mode 100644 index 000000000000..edd806d7b40c --- /dev/null +++ b/gas/testsuite/gas/score/ldi.d @@ -0,0 +1,29 @@ +#as: +#objdump: -d +#source: ldi.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 5200 ldiu! r2, 0 + 2: 5200 ldiu! r2, 0 + 4: 53ff ldiu! r3, 255 + 6: 53ff ldiu! r3, 255 + 8: 5409 ldiu! r4, 9 + a: 5409 ldiu! r4, 9 + c: 53ff ldiu! r3, 255 + e: 53ff ldiu! r3, 255 + 10: 85188006 ldi r8, 0x3\(3\) + 14: 87388006 ldi r25, 0x3\(3\) + ... + 20: 84588000 ldi r2, 0x0\(0\) + 24: 87388000 ldi r25, 0x0\(0\) + 28: 847881fe ldi r3, 0xff\(255\) + 2c: 86f88002 ldi r23, 0x1\(1\) + 30: 5fff ldiu! r15, 255 + 32: 5fff ldiu! r15, 255 + 34: 5803 ldiu! r8, 3 + 36: 5803 ldiu! r8, 3 +#pass diff --git a/gas/testsuite/gas/score/ldi.s b/gas/testsuite/gas/score/ldi.s new file mode 100644 index 000000000000..d180da34d56d --- /dev/null +++ b/gas/testsuite/gas/score/ldi.s @@ -0,0 +1,53 @@ +/* + * test relax + * ldi <-> ldiu! : for ldiu! : register number must be in 0-15, simm16: [0-255] + * (1)ldi rD, simm16 : rD = simm16 + * (2)ldiu! rD, imm8 : rD = ZE(imm8) + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r2, 0 #32b -> 16b + \insn16 r2, 0 + + \insn32 r3, 255 #32b -> 16b + \insn16 r3, 255 + + \insn32 r4, 9 #32b -> 16b + \insn32 r4, 9 #32b -> 16b + + \insn16 r3, 255 + \insn32 r3, 255 #32b -> 16b + + \insn32 r8, 3 #No transform + \insn32 r25, 3 #No transform + + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r2, 0 #16b -> 32b + \insn32 r25, 0 + + \insn16 r3, 255 #16b -> 32b + \insn32 r23, 1 + + \insn16 r15, 255 #No transform + \insn32 r15, 255 + + \insn16 r8, 3 #No transform + \insn16 r8, 3 #No transform + +.endm + +.text + + tran3216 "ldi", "ldiu!" + tran1632 "ldi", "ldiu!" diff --git a/gas/testsuite/gas/score/ls32ls16.d b/gas/testsuite/gas/score/ls32ls16.d new file mode 100644 index 000000000000..a6ddfa60e1f8 --- /dev/null +++ b/gas/testsuite/gas/score/ls32ls16.d @@ -0,0 +1,145 @@ +#as: +#objdump: -d +#source: ls32ls16.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + ... + 10: 2038 lw! r0, \[r3\] + 12: 2038 lw! r0, \[r3\] + 14: 23f8 lw! r3, \[r15\] + 16: 23f8 lw! r3, \[r15\] + 18: 2f88 lw! r15, \[r8\] + 1a: 2f88 lw! r15, \[r8\] + 1c: c0888000 lw r4, \[r8, 0\] + 20: c3338000 lw r25, \[r19, 0\] + 24: 2578 lw! r5, \[r7\] + 26: 2578 lw! r5, \[r7\] + 28: 2238 lw! r2, \[r3\] + 2a: 2238 lw! r2, \[r3\] + ... + 40: 2039 lh! r0, \[r3\] + 42: 2039 lh! r0, \[r3\] + 44: 23f9 lh! r3, \[r15\] + 46: 23f9 lh! r3, \[r15\] + 48: 2f89 lh! r15, \[r8\] + 4a: 2f89 lh! r15, \[r8\] + 4c: c4888000 lh r4, \[r8, 0\] + 50: c7338000 lh r25, \[r19, 0\] + 54: 2579 lh! r5, \[r7\] + 56: 2579 lh! r5, \[r7\] + 58: 2239 lh! r2, \[r3\] + 5a: 2239 lh! r2, \[r3\] + ... + 110: 203b lbu! r0, \[r3\] + 112: 203b lbu! r0, \[r3\] + 114: 23fb lbu! r3, \[r15\] + 116: 23fb lbu! r3, \[r15\] + 118: 2f8b lbu! r15, \[r8\] + 11a: 2f8b lbu! r15, \[r8\] + 11c: d8888000 lbu r4, \[r8, 0\] + 120: db338000 lbu r25, \[r19, 0\] + 124: 257b lbu! r5, \[r7\] + 126: 257b lbu! r5, \[r7\] + 128: 223b lbu! r2, \[r3\] + 12a: 223b lbu! r2, \[r3\] + ... + 210: 203c sw! r0, \[r3\] + 212: 203c sw! r0, \[r3\] + 214: 23fc sw! r3, \[r15\] + 216: 23fc sw! r3, \[r15\] + 218: 2f8c sw! r15, \[r8\] + 21a: 2f8c sw! r15, \[r8\] + 21c: d0888000 sw r4, \[r8, 0\] + 220: d3338000 sw r25, \[r19, 0\] + 224: 257c sw! r5, \[r7\] + 226: 257c sw! r5, \[r7\] + 228: 223c sw! r2, \[r3\] + 22a: 223c sw! r2, \[r3\] + 22c: 0000 nop! + 22e: 0000 nop! + 230: 203d sh! r0, \[r3\] + 232: 203d sh! r0, \[r3\] + 234: 23fd sh! r3, \[r15\] + 236: 23fd sh! r3, \[r15\] + 238: 2f8d sh! r15, \[r8\] + 23a: 2f8d sh! r15, \[r8\] + 23c: d4888000 sh r4, \[r8, 0\] + 240: d7338000 sh r25, \[r19, 0\] + 244: 257d sh! r5, \[r7\] + 246: 257d sh! r5, \[r7\] + 248: 223d sh! r2, \[r3\] + 24a: 223d sh! r2, \[r3\] + 24c: 0000 nop! + 24e: 0000 nop! + 250: 203f sb! r0, \[r3\] + 252: 203f sb! r0, \[r3\] + 254: 23ff sb! r3, \[r15\] + 256: 23ff sb! r3, \[r15\] + 258: 2f8f sb! r15, \[r8\] + 25a: 2f8f sb! r15, \[r8\] + 25c: dc888000 sb r4, \[r8, 0\] + 260: df338000 sb r25, \[r19, 0\] + 264: 257f sb! r5, \[r7\] + 266: 257f sb! r5, \[r7\] + 268: 223f sb! r2, \[r3\] + 26a: 223f sb! r2, \[r3\] + 26c: 0000 nop! + 26e: 0000 nop! + 270: c0038000 lw r0, \[r3, 0\] + 274: c257800a lw r18, \[r23, 10\] + 278: c1e08000 lw r15, \[r0, 0\] + 27c: c23a800a lw r17, \[r26, 10\] + 280: 2688 lw! r6, \[r8\] + 282: 2688 lw! r6, \[r8\] + 284: 2378 lw! r3, \[r7\] + 286: 2378 lw! r3, \[r7\] + ... + 290: c4038000 lh r0, \[r3, 0\] + 294: c657800a lh r18, \[r23, 10\] + 298: c5e08000 lh r15, \[r0, 0\] + 29c: c63a800a lh r17, \[r26, 10\] + 2a0: 2689 lh! r6, \[r8\] + 2a2: 2689 lh! r6, \[r8\] + 2a4: 2379 lh! r3, \[r7\] + 2a6: 2379 lh! r3, \[r7\] + ... + 2b0: d8038000 lbu r0, \[r3, 0\] + 2b4: da57800a lbu r18, \[r23, 10\] + 2b8: d9e08000 lbu r15, \[r0, 0\] + 2bc: da3a800a lbu r17, \[r26, 10\] + 2c0: 268b lbu! r6, \[r8\] + 2c2: 268b lbu! r6, \[r8\] + 2c4: 237b lbu! r3, \[r7\] + 2c6: 237b lbu! r3, \[r7\] + ... + 2d0: d0038000 sw r0, \[r3, 0\] + 2d4: d257800a sw r18, \[r23, 10\] + 2d8: d1e08000 sw r15, \[r0, 0\] + 2dc: d23a800a sw r17, \[r26, 10\] + 2e0: 268c sw! r6, \[r8\] + 2e2: 268c sw! r6, \[r8\] + 2e4: 237c sw! r3, \[r7\] + 2e6: 237c sw! r3, \[r7\] + ... + 2f0: d4038000 sh r0, \[r3, 0\] + 2f4: d657800a sh r18, \[r23, 10\] + 2f8: d5e08000 sh r15, \[r0, 0\] + 2fc: d63a800a sh r17, \[r26, 10\] + 300: 268d sh! r6, \[r8\] + 302: 268d sh! r6, \[r8\] + 304: 237d sh! r3, \[r7\] + 306: 237d sh! r3, \[r7\] + ... + 310: dc038000 sb r0, \[r3, 0\] + 314: de57800a sb r18, \[r23, 10\] + 318: dde08000 sb r15, \[r0, 0\] + 31c: de3a800a sb r17, \[r26, 10\] + 320: 268f sb! r6, \[r8\] + 322: 268f sb! r6, \[r8\] + 324: 237f sb! r3, \[r7\] + 326: 237f sb! r3, \[r7\] +#pass diff --git a/gas/testsuite/gas/score/ls32ls16.s b/gas/testsuite/gas/score/ls32ls16.s new file mode 100644 index 000000000000..387d41dab9e9 --- /dev/null +++ b/gas/testsuite/gas/score/ls32ls16.s @@ -0,0 +1,70 @@ +/* + * test relax + * lw <-> lw! : register number must be in 0-15, offset == 0 + * lh <-> lh! : register number must be in 0-15, offset == 0 + * lbu <-> lbu! : register number must be in 0-15, offset == 0 + * sw <-> sw! : register number must be in 0-15, offset == 0 + * sh <-> sh! : register number must be in 0-15, offset == 0 + * sb <-> sb! : register number must be in 0-15, offset == 0 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0, [r3, 0] #32b -> 16b + \insn16 r0, [r3] + + \insn32 r3, [r15, 0] #32b -> 16b + \insn16 r3, [r15] + + \insn32 r15, [r8, 0] #32b -> 16b + \insn16 r15, [r8] + + \insn32 r4, [r8, 0] #No transform + \insn32 r25, [r19, 0] + + \insn32 r5, [r7, 0] #32b -> 16b + \insn32 r5, [r7, 0] #32b -> 16b + + \insn16 r2, [r3] + \insn32 r2, [r3, 0] #32b -> 16b + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, [r3] #16b -> 32b + \insn32 r18, [r23, 10] + + \insn16 r15, [r0] #16b -> 32b + \insn32 r17, [r26, 10] + + \insn16 r6, [r8] #No transform + \insn16 r6, [r8] #No transform + + \insn16 r3, [r7] #No transform + \insn32 r3, [r7, 0] + +.endm +.space 1 + tran3216 "lw", "lw!" +.fill 10, 1 + tran3216 "lh", "lh!" +.org 0x101 + tran3216 "lbu", "lbu!" +.org 0x203 + tran3216 "sw", "sw!" + tran3216 "sh", "sh!" + tran3216 "sb", "sb!" + + tran1632 "lw", "lw!" + tran1632 "lh", "lh!" + tran1632 "lbu", "lbu!" + tran1632 "sw", "sw!" + tran1632 "sh", "sh!" + tran1632 "sb", "sb!" diff --git a/gas/testsuite/gas/score/ls32ls16p.d b/gas/testsuite/gas/score/ls32ls16p.d new file mode 100644 index 000000000000..aa1d3a64de66 --- /dev/null +++ b/gas/testsuite/gas/score/ls32ls16p.d @@ -0,0 +1,135 @@ +#as: +#objdump: -d +#source: ls32ls16p.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + 0: 7320 lwp! r3, 16 + 2: 7320 lwp! r3, 16 + 4: 7460 lwp! r4, 48 + 6: 7460 lwp! r4, 48 + 8: 7790 lwp! r7, 72 + a: 7790 lwp! r7, 72 + c: 7840 lwp! r8, 32 + e: 7840 lwp! r8, 32 + 10: c0a28080 lw r5, \[r2, 128\] + 14: c0a28080 lw r5, \[r2, 128\] + 18: c0c68020 lw r6, \[r6, 32\] + 1c: c0c68020 lw r6, \[r6, 32\] + 20: 7321 lhp! r3, 8 + 22: 7321 lhp! r3, 8 + 24: 7461 lhp! r4, 24 + 26: 7461 lhp! r4, 24 + 28: 7791 lhp! r7, 36 + 2a: 7791 lhp! r7, 36 + 2c: 7841 lhp! r8, 16 + 2e: 7841 lhp! r8, 16 + 30: c4a28040 lh r5, \[r2, 64\] + 34: c4a28040 lh r5, \[r2, 64\] + 38: c4c68010 lh r6, \[r6, 16\] + 3c: c4c68010 lh r6, \[r6, 16\] + 40: 7323 lbup! r3, 4 + 42: 7323 lbup! r3, 4 + 44: 7463 lbup! r4, 12 + 46: 7463 lbup! r4, 12 + 48: 7793 lbup! r7, 18 + 4a: 7793 lbup! r7, 18 + 4c: 7843 lbup! r8, 8 + 4e: 7843 lbup! r8, 8 + 50: d8a28020 lbu r5, \[r2, 32\] + 54: d8a28020 lbu r5, \[r2, 32\] + 58: d8c68008 lbu r6, \[r6, 8\] + 5c: d8c68008 lbu r6, \[r6, 8\] + 60: 7324 swp! r3, 16 + 62: 7324 swp! r3, 16 + 64: 7464 swp! r4, 48 + 66: 7464 swp! r4, 48 + 68: 7794 swp! r7, 72 + 6a: 7794 swp! r7, 72 + 6c: 7844 swp! r8, 32 + 6e: 7844 swp! r8, 32 + 70: d0a28080 sw r5, \[r2, 128\] + 74: d0a28080 sw r5, \[r2, 128\] + 78: d0c68020 sw r6, \[r6, 32\] + 7c: d0c68020 sw r6, \[r6, 32\] + 80: 7325 shp! r3, 8 + 82: 7325 shp! r3, 8 + 84: 7465 shp! r4, 24 + 86: 7465 shp! r4, 24 + 88: 7795 shp! r7, 36 + 8a: 7795 shp! r7, 36 + 8c: 7845 shp! r8, 16 + 8e: 7845 shp! r8, 16 + 90: d4a28040 sh r5, \[r2, 64\] + 94: d4a28040 sh r5, \[r2, 64\] + 98: d4c68010 sh r6, \[r6, 16\] + 9c: d4c68010 sh r6, \[r6, 16\] + a0: 7327 sbp! r3, 4 + a2: 7327 sbp! r3, 4 + a4: 7467 sbp! r4, 12 + a6: 7467 sbp! r4, 12 + a8: 7797 sbp! r7, 18 + aa: 7797 sbp! r7, 18 + ac: 7847 sbp! r8, 8 + ae: 7847 sbp! r8, 8 + b0: dca28020 sb r5, \[r2, 32\] + b4: dca28020 sb r5, \[r2, 32\] + b8: dcc68008 sb r6, \[r6, 8\] + bc: dcc68008 sb r6, \[r6, 8\] + c0: c002800c lw r0, \[r2, 12\] + c4: c00580ff lw r0, \[r5, 255\] + c8: c1e28000 lw r15, \[r2, 0\] + cc: c1e480ff lw r15, \[r4, 255\] + d0: 7410 lwp! r4, 8 + d2: 7410 lwp! r4, 8 + d4: 7710 lwp! r7, 8 + d6: 7740 lwp! r7, 32 + ... + e0: c402800c lh r0, \[r2, 12\] + e4: c40580ff lh r0, \[r5, 255\] + e8: c5e28000 lh r15, \[r2, 0\] + ec: c5e480ff lh r15, \[r4, 255\] + f0: 7421 lhp! r4, 8 + f2: 7421 lhp! r4, 8 + f4: 7721 lhp! r7, 8 + f6: 7741 lhp! r7, 16 + ... + 100: d802800c lbu r0, \[r2, 12\] + 104: d80580ff lbu r0, \[r5, 255\] + 108: d9e28000 lbu r15, \[r2, 0\] + 10c: d9e480ff lbu r15, \[r4, 255\] + 110: 7443 lbup! r4, 8 + 112: 7443 lbup! r4, 8 + 114: 7743 lbup! r7, 8 + 116: 7743 lbup! r7, 8 + ... + 120: d002800c sw r0, \[r2, 12\] + 124: d00580ff sw r0, \[r5, 255\] + 128: d1e28000 sw r15, \[r2, 0\] + 12c: d1e480ff sw r15, \[r4, 255\] + 130: 7414 swp! r4, 8 + 132: 7414 swp! r4, 8 + 134: 7714 swp! r7, 8 + 136: 7744 swp! r7, 32 + ... + 140: d402800c sh r0, \[r2, 12\] + 144: d40580ff sh r0, \[r5, 255\] + 148: d5e28000 sh r15, \[r2, 0\] + 14c: d5e480ff sh r15, \[r4, 255\] + 150: 7425 shp! r4, 8 + 152: 7425 shp! r4, 8 + 154: 7725 shp! r7, 8 + 156: 7745 shp! r7, 16 + ... + 160: dc02800c sb r0, \[r2, 12\] + 164: dc0580ff sb r0, \[r5, 255\] + 168: dde28000 sb r15, \[r2, 0\] + 16c: dde480ff sb r15, \[r4, 255\] + 170: 7447 sbp! r4, 8 + 172: 7447 sbp! r4, 8 + 174: 7747 sbp! r7, 8 + 176: 7747 sbp! r7, 8 +#pass diff --git a/gas/testsuite/gas/score/ls32ls16p.s b/gas/testsuite/gas/score/ls32ls16p.s new file mode 100644 index 000000000000..72aa6125c769 --- /dev/null +++ b/gas/testsuite/gas/score/ls32ls16p.s @@ -0,0 +1,68 @@ +/* + * test relax + * lw <-> lwp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b + * lh <-> lhp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b + * lbu <-> lbu! : rs = r2, offset != 0, offset : 5b + * sw <-> swp! : rs = r2, offset & 0x3 == 0, offset >> 2 : 5b + * sh <-> shp! : rs = r2, offset & 0x1 == 0, offset >> 1 : 5b + * sb <-> sb! : rs = r2, offset != 0, offset : 5b + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16, shift +.align 4 + + \insn32 r3, [r2, 0x4 << \shift] #32b -> 16b + \insn16 r3, 0x4 << \shift + + \insn32 r4, [r2, 0xC << \shift] #32b -> 16b + \insn16 r4, 0xC << \shift + + \insn32 r7, [r2, 0x12 << \shift] #32b -> 16b + \insn32 r7, [r2, 0x12 << \shift] #32b -> 16b + + \insn16 r8, 0x8 << \shift + \insn32 r8, [r2, 0x8 << \shift] #32b -> 16b + + \insn32 r5, [r2, 0x20 << \shift] #No transform + \insn32 r5, [r2, 0x20 << \shift] #No transform + + \insn32 r6, [r6, 0x8 << \shift] #No transform + \insn32 r6, [r6, 0x8 << \shift] #No transform + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16, shift +.align 4 + + \insn16 r0, 0xC #16b -> 32b + \insn32 r0, [r5, 0xFF] + + \insn16 r15, 0x0 #16b -> 32b + \insn32 r15, [r4, 0xFF] + + \insn16 r4, 0x8 #No transform + \insn16 r4, 0x8 #No transform + + \insn16 r7, 0x8 #No transform + \insn32 r7, [r2, 0x8 << \shift] + +.endm + + tran3216 "lw", "lwp!", 2 + tran3216 "lh", "lhp!", 1 + tran3216 "lbu", "lbup!", 0 + tran3216 "sw", "swp!", 2 + tran3216 "sh", "shp!", 1 + tran3216 "sb", "sbp!", 0 + + tran1632 "lw", "lwp!", 2 + tran1632 "lh", "lhp!", 1 + tran1632 "lbu", "lbup!", 0 + tran1632 "sw", "swp!", 2 + tran1632 "sh", "shp!", 1 + tran1632 "sb", "sbp!", 0 + diff --git a/gas/testsuite/gas/score/move.d b/gas/testsuite/gas/score/move.d new file mode 100644 index 000000000000..0bec506ec8eb --- /dev/null +++ b/gas/testsuite/gas/score/move.d @@ -0,0 +1,60 @@ +#as: +#objdump: -d +#source: move.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + 0: 00f3 mv! r0, r15 + 2: 00f3 mv! r0, r15 + 4: 0ff3 mv! r15, r15 + 6: 0ff3 mv! r15, r15 + 8: 0353 mv! r3, r5 + a: 0353 mv! r3, r5 + c: 0673 mv! r6, r7 + e: 0673 mv! r6, r7 + 10: 810abc56 mv r8, r10 + 14: 82b7bc56 mv r21, r23 + ... + 20: 800fbc56 mv r0, r15 + 24: 82fbbc56 mv r23, r27 + 28: 0283 mv! r2, r8 + 2a: 0283 mv! r2, r8 + 2c: 0283 mv! r2, r8 + 2e: 0283 mv! r2, r8 + 30: 0f02 mhfl! r31, r0 + 32: 0f02 mhfl! r31, r0 + 34: 00f2 mhfl! r16, r15 + 36: 00f2 mhfl! r16, r15 + 38: 0752 mhfl! r23, r5 + 3a: 0752 mhfl! r23, r5 + 3c: 0a72 mhfl! r26, r7 + 3e: 0a72 mhfl! r26, r7 + 40: 838abc56 mv gp, r10 + 44: 82b7bc56 mv r21, r23 + ... + 50: 83e0bc56 mv r31, r0 + 54: 82fbbc56 mv r23, r27 + 58: 0682 mhfl! r22, r8 + 5a: 0682 mhfl! r22, r8 + 5c: 07f2 mhfl! r23, r15 + 5e: 07f2 mhfl! r23, r15 + 60: 00f1 mlfh! r0, r31 + 62: 00f1 mlfh! r0, r31 + 64: 0f01 mlfh! r15, r16 + 66: 0f01 mlfh! r15, r16 + 68: 0571 mlfh! r5, r23 + 6a: 0571 mlfh! r5, r23 + 6c: 07a1 mlfh! r7, r26 + 6e: 07a1 mlfh! r7, r26 + 70: 815cbc56 mv r10, gp + 74: 82b7bc56 mv r21, r23 + ... + 80: 801fbc56 mv r0, r31 + 84: 82fbbc56 mv r23, r27 + 88: 0861 mlfh! r8, r22 + 8a: 0861 mlfh! r8, r22 + 8c: 0f71 mlfh! r15, r23 + 8e: 0f71 mlfh! r15, r23 diff --git a/gas/testsuite/gas/score/move.s b/gas/testsuite/gas/score/move.s new file mode 100644 index 000000000000..3a4623eda45e --- /dev/null +++ b/gas/testsuite/gas/score/move.s @@ -0,0 +1,98 @@ +/* + * test relax + * mv <-> mv! : for mv! : register number must be in 0-15 + * mv <-> mhfl! : for mhfl! : rD must be in 16-31, rS must be in 0-15 + * mv <-> mlfh! : for mhfl! : rD must be in 0-15, rS must be in 16-31 + + * Author: ligang + */ + +/* This block test mv -> mv! */ +.align 4 + + mv r0, r15 #32b -> 16b + mv! r0, r15 + + mv r15, r15 #32b -> 16b + mv! r15, r15 + + mv r3, r5 #32b -> 16b + mv r3, r5 #32b -> 16b + + mv! r6, r7 + mv r6, r7 #32b -> 16b + + mv r8, r10 #No transform + mv r21, r23 + +/* This block test mv! -> mv */ +.align 4 + + mv! r0, r15 #16b -> 32b + mv r23, r27 + + mv! r2, r8 #No transform + mv! r2, r8 #No transform + + mv! r2, r8 #No transform + mv r2, r8 + +/* This block test mv -> mhfl! */ +.align 4 + + mv r31, r0 #32b -> 16b + mhfl! r31, r0 + + mv r16, r15 #32b -> 16b + mv! r16, r15 + + mv r23, r5 #32b -> 16b + mv r23, r5 #32b -> 16b + + mhfl! r26, r7 + mv r26, r7 #32b -> 16b + + mv r28, r10 #No transform + mv r21, r23 + +/* This block test mhfl! -> mv */ +.align 4 + + mhfl! r31, r0 #16b -> 32b + mv r23, r27 + + mhfl! r22, r8 #No transform + mhfl! r22, r8 #No transform + + mhfl! r23, r15 #No transform + mv r23, r15 + +/* This block test mv -> mlfh! */ +.align 4 + + mv r0, r31 #32b -> 16b + mlfh! r0, r31 + + mv r15, r16 #32b -> 16b + mv! r15, r16 + + mv r5, r23 #32b -> 16b + mv r5, r23 #32b -> 16b + + mlfh! r7, r26 + mv r7, r26 #32b -> 16b + + mv r10, r28 #No transform + mv r21, r23 + +/* This block test mhfl! -> mv */ +.align 4 + + mlfh! r0, r31 #16b -> 32b + mv r23, r27 + + mlfh! r8, r22 #No transform + mlfh! r8, r22 #No transform + + mlfh! r15, r23 #No transform + mv r15, r23 diff --git a/gas/testsuite/gas/score/nop.d b/gas/testsuite/gas/score/nop.d new file mode 100644 index 000000000000..83e98b7faa03 --- /dev/null +++ b/gas/testsuite/gas/score/nop.d @@ -0,0 +1,15 @@ +#as: +#objdump: -d +#source: nop.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + ... + c: 80008000 nop + 10: 8254e010 add r18, r20, r24 + ... + 28: 80008000 nop + 2c: 8254e026 xor r18, r20, r24 diff --git a/gas/testsuite/gas/score/nop.s b/gas/testsuite/gas/score/nop.s new file mode 100644 index 000000000000..26955528ae12 --- /dev/null +++ b/gas/testsuite/gas/score/nop.s @@ -0,0 +1,38 @@ +/* + * test relax + * nop <-> nop! + + * Author: ligang + */ + +.macro tran insn32, insn16 +/* This block transform 32b instruction to 16b. */ +.align 4 + + \insn32 #32b -> 16b + \insn16 + + \insn32 #32b -> 16b + \insn32 #32b -> 16b + + \insn16 + \insn32 #32b -> 16b + + \insn32 #No transform + add r18, r20, r24 + +/* This block transform 16b instruction to 32b. */ +.align 4 + + \insn16 #No transform + \insn32 + + \insn16 #No transform + \insn16 + + \insn16 #16b -> 32b + xor r18, r20, r24 + +.endm + + tran "nop", "nop!" diff --git a/gas/testsuite/gas/score/postlw.d b/gas/testsuite/gas/score/postlw.d new file mode 100644 index 000000000000..25867f4edc34 --- /dev/null +++ b/gas/testsuite/gas/score/postlw.d @@ -0,0 +1,32 @@ +#as: +#objdump: -d +#source: postlw.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 27fa pop! r23, \[r7\] + 2: 27fa pop! r23, \[r7\] + 4: 202a pop! r0, \[r2\] + 6: 202a pop! r0, \[r2\] + 8: 2f0a pop! r15, \[r0\] + a: 2f0a pop! r15, \[r0\] + c: 2f7a pop! r15, \[r7\] + e: 2f7a pop! r15, \[r7\] + 10: 29ba pop! r25, \[r3\] + 12: 29ba pop! r25, \[r3\] + 14: 9f0d8020 lw r24, \[r13\]\+, 4 + 18: 9ee78028 lw r23, \[r7\]\+, 5 + 1c: 0000 nop! + 1e: 0000 nop! + 20: 9c078020 lw r0, \[r7\]\+, 4 + 24: 9f2d8020 lw r25, \[r13\]\+, 4 + 28: 9f208020 lw r25, \[r0\]\+, 4 + 2c: 9e578020 lw r18, \[r23\]\+, 4 + 30: 263a pop! r6, \[r3\] + 32: 263a pop! r6, \[r3\] + 34: 237a pop! r3, \[r7\] + 36: 237a pop! r3, \[r7\] +#pass diff --git a/gas/testsuite/gas/score/postlw.s b/gas/testsuite/gas/score/postlw.s new file mode 100644 index 000000000000..499ea94a5956 --- /dev/null +++ b/gas/testsuite/gas/score/postlw.s @@ -0,0 +1,54 @@ +/* + * test relax + * post lw <-> pop! : offset == 4 + * syntax: + lw rD, [rA]+, simm12 : rD and rA can be 0-31 + pop! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r23, [r7]+, 4 #32b -> 16b + \insn16 r23, [r7] + + \insn32 r0, [r2]+, 4 #32b -> 16b + \insn16 r0, [r2] + + \insn32 r15, [r0]+, 4 #32b -> 16b + \insn16 r15, [r0] + + \insn16 r15, [r7] + \insn32 r15, [r7]+, 4 #32b -> 16b + + \insn32 r25, [r3]+, 4 #32b -> 16b + \insn32 r25, [r3]+, 4 #32b -> 16b + + \insn32 r24, [r13]+, 4 #No transform + \insn32 r23, [r7]+, 5 #No transform + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, [r7] #16b -> 32b + \insn32 r25, [r13]+, 4 + + \insn16 r25, [r0] #16b -> 32b + \insn32 r18, [r23]+, 4 + + \insn16 r6, [r3] #No transform + \insn16 r6, [r3] #No transform + + \insn16 r3, [r7] #No transform + \insn32 r3, [r7]+, 4 + +.endm + + tran3216 "lw", "pop!" + tran1632 "lw", "pop!" diff --git a/gas/testsuite/gas/score/presw.d b/gas/testsuite/gas/score/presw.d new file mode 100644 index 000000000000..cc4092fdcc82 --- /dev/null +++ b/gas/testsuite/gas/score/presw.d @@ -0,0 +1,32 @@ +#as: +#objdump: -d +#source: presw.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <.text>: + 0: 202e push! r0, \[r2\] + 2: 202e push! r0, \[r2\] + 4: 27fe push! r23, \[r7\] + 6: 27fe push! r23, \[r7\] + 8: 2f0e push! r15, \[r0\] + a: 2f0e push! r15, \[r0\] + c: 2f7e push! r15, \[r7\] + e: 2f7e push! r15, \[r7\] + 10: 29be push! r25, \[r3\] + 12: 29be push! r25, \[r3\] + 14: 8f0dffe4 sw r24, \[r13, -4\]\+ + 18: 8ee7ffdc sw r23, \[r7, -5\]\+ + 1c: 0000 nop! + 1e: 0000 nop! + 20: 8c07ffe4 sw r0, \[r7, -4\]\+ + 24: 8f2dffe4 sw r25, \[r13, -4\]\+ + 28: 8f20ffe4 sw r25, \[r0, -4\]\+ + 2c: 8e57ffe4 sw r18, \[r23, -4\]\+ + 30: 263e push! r6, \[r3\] + 32: 263e push! r6, \[r3\] + 34: 237e push! r3, \[r7\] + 36: 237e push! r3, \[r7\] +#pass diff --git a/gas/testsuite/gas/score/presw.s b/gas/testsuite/gas/score/presw.s new file mode 100644 index 000000000000..bcc11d102c89 --- /dev/null +++ b/gas/testsuite/gas/score/presw.s @@ -0,0 +1,54 @@ +/* + * test relax + * pre sw <-> push! : offset == -4 + * syntax: + sw rD, [rA, simm12]+ : rD and rA can be 0-31 + push! rD, [rAg0] : rAg0 must be in 0-7, rD can be 0-31 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0, [r2, -4]+ #32b -> 16b + \insn16 r0, [r2] + + \insn32 r23, [r7, -4]+ #32b -> 16b + \insn16 r23, [r7] + + \insn32 r15, [r0, -4]+ #32b -> 16b + \insn16 r15, [r0] + + \insn16 r15, [r7] + \insn32 r15, [r7, -4]+ #32b -> 16b + + \insn32 r25, [r3, -4]+ #32b -> 16b + \insn32 r25, [r3, -4]+ #32b -> 16b + + \insn32 r24, [r13, -4]+ #No transform + \insn32 r23, [r7, -5]+ #No transform + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, [r7] #16b -> 32b + \insn32 r25, [r13, -4]+ + + \insn16 r25, [r0] #16b -> 32b + \insn32 r18, [r23, -4]+ + + \insn16 r6, [r3] #No transform + \insn16 r6, [r3] #No transform + + \insn16 r3, [r7] #No transform + \insn32 r3, [r7, -4]+ + +.endm + + tran3216 "sw", "push!" + tran1632 "sw", "push!" diff --git a/gas/testsuite/gas/score/rD_rA.d b/gas/testsuite/gas/score/rD_rA.d new file mode 100644 index 000000000000..36f29f65c101 --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA.d @@ -0,0 +1,90 @@ +#as: +#objdump: -d +#source: rD_rA.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 2076 not! r0, r7 + 2: 2076 not! r0, r7 + 4: 2f46 not! r15, r4 + 6: 2f46 not! r15, r4 + 8: 2ff6 not! r15, r15 + a: 2ff6 not! r15, r15 + c: 2f36 not! r15, r3 + e: 2f36 not! r15, r3 + 10: 2826 not! r8, r2 + 12: 2826 not! r8, r2 + 14: 81e58025 not.c r15, r5 + 18: 83578025 not.c r26, r23 + 1c: 0000 nop! + 1e: 0000 nop! + 20: 2072 neg! r0, r7 + 22: 2072 neg! r0, r7 + 24: 2f42 neg! r15, r4 + 26: 2f42 neg! r15, r4 + 28: 2ff2 neg! r15, r15 + 2a: 2ff2 neg! r15, r15 + 2c: 2f32 neg! r15, r3 + 2e: 2f32 neg! r15, r3 + 30: 2822 neg! r8, r2 + 32: 2822 neg! r8, r2 + 34: 81e0941f neg.c r15, r5 + 38: 8340dc1f neg.c r26, r23 + 3c: 0000 nop! + 3e: 0000 nop! + 40: 2073 cmp! r0, r7 + 42: 2073 cmp! r0, r7 + 44: 2f43 cmp! r15, r4 + 46: 2f43 cmp! r15, r4 + 48: 2ff3 cmp! r15, r15 + 4a: 2ff3 cmp! r15, r15 + 4c: 2f33 cmp! r15, r3 + 4e: 2f33 cmp! r15, r3 + 50: 2823 cmp! r8, r2 + 52: 2823 cmp! r8, r2 + 54: 806f9419 cmp.c r15, r5 + 58: 807adc19 cmp.c r26, r23 + 5c: 0000 nop! + 5e: 0000 nop! + 60: 80028025 not.c r0, r2 + 64: 82958025 not.c r20, r21 + 68: 81e48025 not.c r15, r4 + 6c: 83358025 not.c r25, r21 + 70: 81e38025 not.c r15, r3 + 74: 83368025 not.c r25, r22 + 78: 2836 not! r8, r3 + 7a: 2836 not! r8, r3 + 7c: 2626 not! r6, r2 + 7e: 2626 not! r6, r2 + 80: 2746 not! r7, r4 + 82: 2746 not! r7, r4 + ... + 90: 8000881f neg.c r0, r2 + 94: 8280d41f neg.c r20, r21 + 98: 81ef901f neg.c r15, r4 + 9c: 8320d41f neg.c r25, r21 + a0: 81ef8c1f neg.c r15, r3 + a4: 8320d81f neg.c r25, r22 + a8: 2832 neg! r8, r3 + aa: 2832 neg! r8, r3 + ac: 2622 neg! r6, r2 + ae: 2622 neg! r6, r2 + b0: 2742 neg! r7, r4 + b2: 2742 neg! r7, r4 + ... + c0: 80608819 cmp.c r0, r2 + c4: 8074d419 cmp.c r20, r21 + c8: 806f9019 cmp.c r15, r4 + cc: 8079d419 cmp.c r25, r21 + d0: 806f8c19 cmp.c r15, r3 + d4: 8079d819 cmp.c r25, r22 + d8: 2833 cmp! r8, r3 + da: 2833 cmp! r8, r3 + dc: 2623 cmp! r6, r2 + de: 2623 cmp! r6, r2 + e0: 2743 cmp! r7, r4 + e2: 2743 cmp! r7, r4 +#pass diff --git a/gas/testsuite/gas/score/rD_rA.s b/gas/testsuite/gas/score/rD_rA.s new file mode 100644 index 000000000000..0f1c0d43ae01 --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA.s @@ -0,0 +1,66 @@ +/* + * test relax + * not.c <-> not! : register number must be in 0-15 + * neg.c <-> neg! : register number must be in 0-15 + * cmp.c <-> cmp! : register number must be in 0-15 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0, r7 #32b -> 16b + \insn16 r0, r7 + + \insn32 r15, r4 #32b -> 16b + \insn16 r15, r4 + + \insn32 r15, r15 #32b -> 16b + \insn16 r15, r15 + + \insn16 r15, r3 + \insn32 r15, r3 #32b -> 16b + + \insn32 r8, r2 #32b -> 16b + \insn32 r8, r2 #32b -> 16b + + \insn32 r15, r5 #No transform + \insn32 r26, r23 + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, r2 #16b -> 32b + \insn32 r20, r21 + + \insn16 r15, r4 #16b -> 32b + \insn32 r25, r21 + + \insn16 r15, r3 #16b -> 32b + \insn32 r25, r22 + + \insn16 r8, r3 #No transform + \insn16 r8, r3 #No transform + + \insn16 r6, r2 #No transform + \insn32 r6, r2 #32b -> 16b + + \insn32 r7, r4 #32b -> 16b + \insn16 r7, r4 #No transform + +.endm + +.text + + tran3216 "not.c", "not!" + tran3216 "neg.c", "neg!" + tran3216 "cmp.c", "cmp!" + + tran1632 "not.c", "not!" + tran1632 "neg.c", "neg!" + tran1632 "cmp.c", "cmp!" diff --git a/gas/testsuite/gas/score/rD_rA_BN.d b/gas/testsuite/gas/score/rD_rA_BN.d new file mode 100644 index 000000000000..505e458fd55e --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA_BN.d @@ -0,0 +1,144 @@ +#as: +#objdump: -d +#source: rD_rA_BN.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 6014 bitclr! r0, 0x2 + 2: 6014 bitclr! r0, 0x2 + 4: 6f24 bitclr! r15, 0x4 + 6: 6f24 bitclr! r15, 0x4 + 8: 6f0c bitclr! r15, 0x1 + a: 6f0c bitclr! r15, 0x1 + c: 6f1c bitclr! r15, 0x3 + e: 6f1c bitclr! r15, 0x3 + 10: 681c bitclr! r8, 0x3 + 12: 681c bitclr! r8, 0x3 + 14: 81ef8429 bitclr.c r15, r15, 0x1 + 18: 83579029 bitclr.c r26, r23, 0x4 + 1c: 0000 nop! + 1e: 0000 nop! + 20: 6015 bitset! r0, 0x2 + 22: 6015 bitset! r0, 0x2 + 24: 6f25 bitset! r15, 0x4 + 26: 6f25 bitset! r15, 0x4 + 28: 6f0d bitset! r15, 0x1 + 2a: 6f0d bitset! r15, 0x1 + 2c: 6f1d bitset! r15, 0x3 + 2e: 6f1d bitset! r15, 0x3 + 30: 681d bitset! r8, 0x3 + 32: 681d bitset! r8, 0x3 + 34: 81ef842b bitset.c r15, r15, 0x1 + 38: 8357902b bitset.c r26, r23, 0x4 + 3c: 0000 nop! + 3e: 0000 nop! + 40: 6017 bittgl! r0, 0x2 + 42: 6017 bittgl! r0, 0x2 + 44: 6f27 bittgl! r15, 0x4 + 46: 6f27 bittgl! r15, 0x4 + 48: 6f0f bittgl! r15, 0x1 + 4a: 6f0f bittgl! r15, 0x1 + 4c: 6f1f bittgl! r15, 0x3 + 4e: 6f1f bittgl! r15, 0x3 + 50: 681f bittgl! r8, 0x3 + 52: 681f bittgl! r8, 0x3 + 54: 81ef842f bittgl.c r15, r15, 0x1 + 58: 8357902f bittgl.c r26, r23, 0x4 + 5c: 0000 nop! + 5e: 0000 nop! + 60: 6011 slli! r0, 2 + 62: 6011 slli! r0, 2 + 64: 6f21 slli! r15, 4 + 66: 6f21 slli! r15, 4 + 68: 6f09 slli! r15, 1 + 6a: 6f09 slli! r15, 1 + 6c: 6f19 slli! r15, 3 + 6e: 6f19 slli! r15, 3 + 70: 6819 slli! r8, 3 + 72: 6819 slli! r8, 3 + 74: 81ef8471 slli.c r15, r15, 1 + 78: 83579071 slli.c r26, r23, 4 + 7c: 0000 nop! + 7e: 0000 nop! + 80: 6013 srli! r0, 2 + 82: 6013 srli! r0, 2 + 84: 6f23 srli! r15, 4 + 86: 6f23 srli! r15, 4 + 88: 6f0b srli! r15, 1 + 8a: 6f0b srli! r15, 1 + 8c: 6f1b srli! r15, 3 + 8e: 6f1b srli! r15, 3 + 90: 681b srli! r8, 3 + 92: 681b srli! r8, 3 + 94: 81ef8475 srli.c r15, r15, 1 + 98: 83579075 srli.c r26, r23, 4 + 9c: 0000 nop! + 9e: 0000 nop! + a0: 80008829 bitclr.c r0, r0, 0x2 + a4: 82958829 bitclr.c r20, r21, 0x2 + a8: 81ef9029 bitclr.c r15, r15, 0x4 + ac: 83359029 bitclr.c r25, r21, 0x4 + b0: 81ef8429 bitclr.c r15, r15, 0x1 + b4: 83368429 bitclr.c r25, r22, 0x1 + b8: 681c bitclr! r8, 0x3 + ba: 681c bitclr! r8, 0x3 + bc: 6624 bitclr! r6, 0x4 + be: 6624 bitclr! r6, 0x4 + c0: 6914 bitclr! r9, 0x2 + c2: 6914 bitclr! r9, 0x2 + ... + d0: 8000882b bitset.c r0, r0, 0x2 + d4: 8295882b bitset.c r20, r21, 0x2 + d8: 81ef902b bitset.c r15, r15, 0x4 + dc: 8335902b bitset.c r25, r21, 0x4 + e0: 81ef842b bitset.c r15, r15, 0x1 + e4: 8336842b bitset.c r25, r22, 0x1 + e8: 681d bitset! r8, 0x3 + ea: 681d bitset! r8, 0x3 + ec: 6625 bitset! r6, 0x4 + ee: 6625 bitset! r6, 0x4 + f0: 6915 bitset! r9, 0x2 + f2: 6915 bitset! r9, 0x2 + ... + 100: 8000882f bittgl.c r0, r0, 0x2 + 104: 8295882f bittgl.c r20, r21, 0x2 + 108: 81ef902f bittgl.c r15, r15, 0x4 + 10c: 8335902f bittgl.c r25, r21, 0x4 + 110: 81ef842f bittgl.c r15, r15, 0x1 + 114: 8336842f bittgl.c r25, r22, 0x1 + 118: 681f bittgl! r8, 0x3 + 11a: 681f bittgl! r8, 0x3 + 11c: 6627 bittgl! r6, 0x4 + 11e: 6627 bittgl! r6, 0x4 + 120: 6917 bittgl! r9, 0x2 + 122: 6917 bittgl! r9, 0x2 + ... + 130: 80008871 slli.c r0, r0, 2 + 134: 82958871 slli.c r20, r21, 2 + 138: 81ef9071 slli.c r15, r15, 4 + 13c: 83359071 slli.c r25, r21, 4 + 140: 81ef8471 slli.c r15, r15, 1 + 144: 83368471 slli.c r25, r22, 1 + 148: 6819 slli! r8, 3 + 14a: 6819 slli! r8, 3 + 14c: 6621 slli! r6, 4 + 14e: 6621 slli! r6, 4 + 150: 6911 slli! r9, 2 + 152: 6911 slli! r9, 2 + ... + 160: 80008875 srli.c r0, r0, 2 + 164: 82958875 srli.c r20, r21, 2 + 168: 81ef9075 srli.c r15, r15, 4 + 16c: 83359075 srli.c r25, r21, 4 + 170: 81ef8475 srli.c r15, r15, 1 + 174: 83368475 srli.c r25, r22, 1 + 178: 681b srli! r8, 3 + 17a: 681b srli! r8, 3 + 17c: 6623 srli! r6, 4 + 17e: 6623 srli! r6, 4 + 180: 6913 srli! r9, 2 + 182: 6913 srli! r9, 2 +#pass diff --git a/gas/testsuite/gas/score/rD_rA_BN.s b/gas/testsuite/gas/score/rD_rA_BN.s new file mode 100644 index 000000000000..224438f85b23 --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA_BN.s @@ -0,0 +1,73 @@ +/* + * test relax + * bitclr.c <-> bitclr! : register number must be in 0-15 + * bitset.c <-> bitset! : register number must be in 0-15 + * bittgl.c <-> bittgl! : register number must be in 0-15 + * slli.c <-> slli! : register number must be in 0-15 + * srli.c <-> srli! : register number must be in 0-15 + + * Author: ligang + */ + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0, r0, 2 #32b -> 16b + \insn16 r0, 2 + + \insn32 r15, r15, 4 #32b -> 16b + \insn16 r15, 4 + + \insn32 r15, r15, 1 #32b -> 16b + \insn16 r15, 1 + + \insn16 r15, 3 + \insn32 r15, r15, 3 #32b -> 16b + + \insn32 r8, r8, 3 #32b -> 16b + \insn32 r8, r8, 3 #32b -> 16b + + \insn32 r15, r15, 1 #No transform + \insn32 r26, r23, 4 + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, 2 #16b -> 32b + \insn32 r20, r21, 2 + + \insn16 r15, 4 #16b -> 32b + \insn32 r25, r21, 4 + + \insn16 r15, 1 #16b -> 32b + \insn32 r25, r22, 1 + + \insn16 r8, 3 #No transform + \insn16 r8, 3 #No transform + + \insn16 r6, 4 #No transform + \insn32 r6, r6, 4 #32b -> 16b + + \insn32 r9, r9, 2 #32b -> 16b + \insn16 r9, 2 #No transform + +.endm + +.text + + tran3216 "bitclr.c", "bitclr!" + tran3216 "bitset.c", "bitset!" + tran3216 "bittgl.c", "bittgl!" + tran3216 "slli.c", "slli!" + tran3216 "srli.c", "srli!" + + tran1632 "bitclr.c", "bitclr!" + tran1632 "bitset.c", "bitset!" + tran1632 "bittgl.c", "bittgl!" + tran1632 "slli.c", "slli!" + tran1632 "srli.c", "srli!" + diff --git a/gas/testsuite/gas/score/rD_rA_rB.d b/gas/testsuite/gas/score/rD_rA_rB.d new file mode 100644 index 000000000000..d897ebc7391b --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA_rB.d @@ -0,0 +1,252 @@ +#as: +#objdump: -d +#source: rD_rA_rB.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 2020 add! r0, r2 + 2: 2020 add! r0, r2 + 4: 2540 add! r5, r4 + 6: 2540 add! r5, r4 + 8: 2f40 add! r15, r4 + a: 2f40 add! r15, r4 + c: 2f30 add! r15, r3 + e: 2f30 add! r15, r3 + 10: 2830 add! r8, r3 + 12: 2830 add! r8, r3 + 14: 81ef9811 add.c r15, r15, r6 + 18: 83579011 add.c r26, r23, r4 + 1c: 0000 nop! + 1e: 0000 nop! + 20: 0029 addc! r0, r2 + 22: 0029 addc! r0, r2 + 24: 0549 addc! r5, r4 + 26: 0549 addc! r5, r4 + 28: 0f49 addc! r15, r4 + 2a: 0f49 addc! r15, r4 + 2c: 0f39 addc! r15, r3 + 2e: 0f39 addc! r15, r3 + 30: 0839 addc! r8, r3 + 32: 0839 addc! r8, r3 + 34: 81ef9813 addc.c r15, r15, r6 + 38: 83579013 addc.c r26, r23, r4 + 3c: 0000 nop! + 3e: 0000 nop! + 40: 2021 sub! r0, r2 + 42: 2021 sub! r0, r2 + 44: 2541 sub! r5, r4 + 46: 2541 sub! r5, r4 + 48: 2f41 sub! r15, r4 + 4a: 2f41 sub! r15, r4 + 4c: 2f31 sub! r15, r3 + 4e: 2f31 sub! r15, r3 + 50: 2831 sub! r8, r3 + 52: 2831 sub! r8, r3 + 54: 81ef9815 sub.c r15, r15, r6 + 58: 83579015 sub.c r26, r23, r4 + 5c: 0000 nop! + 5e: 0000 nop! + 60: 2024 and! r0, r2 + 62: 2024 and! r0, r2 + 64: 2544 and! r5, r4 + 66: 2544 and! r5, r4 + 68: 2f44 and! r15, r4 + 6a: 2f44 and! r15, r4 + 6c: 2f34 and! r15, r3 + 6e: 2f34 and! r15, r3 + 70: 2834 and! r8, r3 + 72: 2834 and! r8, r3 + 74: 81ef9821 and.c r15, r15, r6 + 78: 83579021 and.c r26, r23, r4 + 7c: 0000 nop! + 7e: 0000 nop! + 80: 2025 or! r0, r2 + 82: 2025 or! r0, r2 + 84: 2545 or! r5, r4 + 86: 2545 or! r5, r4 + 88: 2f45 or! r15, r4 + 8a: 2f45 or! r15, r4 + 8c: 2f35 or! r15, r3 + 8e: 2f35 or! r15, r3 + 90: 2835 or! r8, r3 + 92: 2835 or! r8, r3 + 94: 81ef9823 or.c r15, r15, r6 + 98: 83579023 or.c r26, r23, r4 + 9c: 0000 nop! + 9e: 0000 nop! + a0: 2027 xor! r0, r2 + a2: 2027 xor! r0, r2 + a4: 2547 xor! r5, r4 + a6: 2547 xor! r5, r4 + a8: 2f47 xor! r15, r4 + aa: 2f47 xor! r15, r4 + ac: 2f37 xor! r15, r3 + ae: 2f37 xor! r15, r3 + b0: 2837 xor! r8, r3 + b2: 2837 xor! r8, r3 + b4: 81ef9827 xor.c r15, r15, r6 + b8: 83579027 xor.c r26, r23, r4 + bc: 0000 nop! + be: 0000 nop! + c0: 002b sra! r0, r2 + c2: 002b sra! r0, r2 + c4: 054b sra! r5, r4 + c6: 054b sra! r5, r4 + c8: 0f4b sra! r15, r4 + ca: 0f4b sra! r15, r4 + cc: 0f3b sra! r15, r3 + ce: 0f3b sra! r15, r3 + d0: 083b sra! r8, r3 + d2: 083b sra! r8, r3 + d4: 81ef9837 sra.c r15, r15, r6 + d8: 83579037 sra.c r26, r23, r4 + dc: 0000 nop! + de: 0000 nop! + e0: 002a srl! r0, r2 + e2: 002a srl! r0, r2 + e4: 054a srl! r5, r4 + e6: 054a srl! r5, r4 + e8: 0f4a srl! r15, r4 + ea: 0f4a srl! r15, r4 + ec: 0f3a srl! r15, r3 + ee: 0f3a srl! r15, r3 + f0: 083a srl! r8, r3 + f2: 083a srl! r8, r3 + f4: 81ef9835 srl.c r15, r15, r6 + f8: 83579035 srl.c r26, r23, r4 + fc: 0000 nop! + fe: 0000 nop! + 100: 0028 sll! r0, r2 + 102: 0028 sll! r0, r2 + 104: 0548 sll! r5, r4 + 106: 0548 sll! r5, r4 + 108: 0f48 sll! r15, r4 + 10a: 0f48 sll! r15, r4 + 10c: 0f38 sll! r15, r3 + 10e: 0f38 sll! r15, r3 + 110: 0838 sll! r8, r3 + 112: 0838 sll! r8, r3 + 114: 81ef9831 sll.c r15, r15, r6 + 118: 83579031 sll.c r26, r23, r4 + 11c: 0000 nop! + 11e: 0000 nop! + 120: 80008811 add.c r0, r0, r2 + 124: 82958811 add.c r20, r21, r2 + 128: 81ef9011 add.c r15, r15, r4 + 12c: 83359011 add.c r25, r21, r4 + 130: 81ef8c11 add.c r15, r15, r3 + 134: 83368c11 add.c r25, r22, r3 + 138: 2870 add! r8, r7 + 13a: 2870 add! r8, r7 + 13c: 2640 add! r6, r4 + 13e: 2640 add! r6, r4 + 140: 2740 add! r7, r4 + 142: 2740 add! r7, r4 + ... + 150: 80008813 addc.c r0, r0, r2 + 154: 82958813 addc.c r20, r21, r2 + 158: 81ef9013 addc.c r15, r15, r4 + 15c: 83359013 addc.c r25, r21, r4 + 160: 81ef8c13 addc.c r15, r15, r3 + 164: 83368c13 addc.c r25, r22, r3 + 168: 0879 addc! r8, r7 + 16a: 0879 addc! r8, r7 + 16c: 0649 addc! r6, r4 + 16e: 0649 addc! r6, r4 + 170: 0749 addc! r7, r4 + 172: 0749 addc! r7, r4 + ... + 180: 80008815 sub.c r0, r0, r2 + 184: 82958815 sub.c r20, r21, r2 + 188: 81ef9015 sub.c r15, r15, r4 + 18c: 83359015 sub.c r25, r21, r4 + 190: 81ef8c15 sub.c r15, r15, r3 + 194: 83368c15 sub.c r25, r22, r3 + 198: 2871 sub! r8, r7 + 19a: 2871 sub! r8, r7 + 19c: 2641 sub! r6, r4 + 19e: 2641 sub! r6, r4 + 1a0: 2741 sub! r7, r4 + 1a2: 2741 sub! r7, r4 + ... + 1b0: 80008821 and.c r0, r0, r2 + 1b4: 82958821 and.c r20, r21, r2 + 1b8: 81ef9021 and.c r15, r15, r4 + 1bc: 83359021 and.c r25, r21, r4 + 1c0: 81ef8c21 and.c r15, r15, r3 + 1c4: 83368c21 and.c r25, r22, r3 + 1c8: 2874 and! r8, r7 + 1ca: 2874 and! r8, r7 + 1cc: 2644 and! r6, r4 + 1ce: 2644 and! r6, r4 + 1d0: 2744 and! r7, r4 + 1d2: 2744 and! r7, r4 + ... + 1e0: 80008823 or.c r0, r0, r2 + 1e4: 82958823 or.c r20, r21, r2 + 1e8: 81ef9023 or.c r15, r15, r4 + 1ec: 83359023 or.c r25, r21, r4 + 1f0: 81ef8c23 or.c r15, r15, r3 + 1f4: 83368c23 or.c r25, r22, r3 + 1f8: 2875 or! r8, r7 + 1fa: 2875 or! r8, r7 + 1fc: 2645 or! r6, r4 + 1fe: 2645 or! r6, r4 + 200: 2745 or! r7, r4 + 202: 2745 or! r7, r4 + ... + 210: 80008827 xor.c r0, r0, r2 + 214: 82958827 xor.c r20, r21, r2 + 218: 81ef9027 xor.c r15, r15, r4 + 21c: 83359027 xor.c r25, r21, r4 + 220: 81ef8c27 xor.c r15, r15, r3 + 224: 83368c27 xor.c r25, r22, r3 + 228: 2877 xor! r8, r7 + 22a: 2877 xor! r8, r7 + 22c: 2647 xor! r6, r4 + 22e: 2647 xor! r6, r4 + 230: 2747 xor! r7, r4 + 232: 2747 xor! r7, r4 + ... + 240: 80008837 sra.c r0, r0, r2 + 244: 82958837 sra.c r20, r21, r2 + 248: 81ef9037 sra.c r15, r15, r4 + 24c: 83359037 sra.c r25, r21, r4 + 250: 81ef8c37 sra.c r15, r15, r3 + 254: 83368c37 sra.c r25, r22, r3 + 258: 087b sra! r8, r7 + 25a: 087b sra! r8, r7 + 25c: 064b sra! r6, r4 + 25e: 064b sra! r6, r4 + 260: 074b sra! r7, r4 + 262: 074b sra! r7, r4 + ... + 270: 80008835 srl.c r0, r0, r2 + 274: 82958835 srl.c r20, r21, r2 + 278: 81ef9035 srl.c r15, r15, r4 + 27c: 83359035 srl.c r25, r21, r4 + 280: 81ef8c35 srl.c r15, r15, r3 + 284: 83368c35 srl.c r25, r22, r3 + 288: 087a srl! r8, r7 + 28a: 087a srl! r8, r7 + 28c: 064a srl! r6, r4 + 28e: 064a srl! r6, r4 + 290: 074a srl! r7, r4 + 292: 074a srl! r7, r4 + ... + 2a0: 80008831 sll.c r0, r0, r2 + 2a4: 82958831 sll.c r20, r21, r2 + 2a8: 81ef9031 sll.c r15, r15, r4 + 2ac: 83359031 sll.c r25, r21, r4 + 2b0: 81ef8c31 sll.c r15, r15, r3 + 2b4: 83368c31 sll.c r25, r22, r3 + 2b8: 0878 sll! r8, r7 + 2ba: 0878 sll! r8, r7 + 2bc: 0648 sll! r6, r4 + 2be: 0648 sll! r6, r4 + 2c0: 0748 sll! r7, r4 + 2c2: 0748 sll! r7, r4 +#pass diff --git a/gas/testsuite/gas/score/rD_rA_rB.s b/gas/testsuite/gas/score/rD_rA_rB.s new file mode 100644 index 000000000000..1a72b131109c --- /dev/null +++ b/gas/testsuite/gas/score/rD_rA_rB.s @@ -0,0 +1,86 @@ +/* + * test relax + * add.c <-> add! : register number must be in 0-15 + * addc.c <-> addc! : register number must be in 0-15 + * sub.c <-> sub! : register number must be in 0-15 + * and.c <-> and! : register number must be in 0-15 + * or.c <-> or! : register number must be in 0-15 + * xor.c <-> xor! : register number must be in 0-15 + * sra.c <-> sra! : register number must be in 0-15 + * srl.c <-> srl! : register number must be in 0-15 + * sll.c <-> sll! : register number must be in 0-15 + + * Author: ligang + */ + + +/* This macro transform 32b instruction to 16b. */ +.macro tran3216 insn32, insn16 +.align 4 + + \insn32 r0, r0, r2 #32b -> 16b + \insn16 r0, r2 + + \insn32 r5, r5, r4 #32b -> 16b + \insn16 r5, r4 + + \insn32 r15, r15, r4 #32b -> 16b + \insn16 r15, r4 + + \insn16 r15, r3 + \insn32 r15, r15, r3 #32b -> 16b + + \insn32 r8, r8, r3 #32b -> 16b + \insn32 r8, r8, r3 #32b -> 16b + + \insn32 r15, r15, r6 #No transform + \insn32 r26, r23, r4 + +.endm + +/* This macro transform 16b instruction to 32b. */ +.macro tran1632 insn32, insn16 +.align 4 + + \insn16 r0, r2 #16b -> 32b + \insn32 r20, r21, r2 + + \insn16 r15, r4 #16b -> 32b + \insn32 r25, r21, r4 + + \insn16 r15, r3 #16b -> 32b + \insn32 r25, r22, r3 + + \insn16 r8, r7 #No transform + \insn16 r8, r7 #No transform + + \insn16 r6, r4 #No transform + \insn32 r6, r6, r4 + + \insn32 r7, r7, r4 #32b -> 16b + \insn16 r7, r4 #No transform + +.endm + +.text + + tran3216 "add.c", "add!" + tran3216 "addc.c", "addc!" + tran3216 "sub.c", "sub!" + tran3216 "and.c", "and!" + tran3216 "or.c", "or!" + tran3216 "xor.c", "xor!" + tran3216 "sra.c", "sra!" + tran3216 "srl.c", "srl!" + tran3216 "sll.c", "sll!" + + tran1632 "add.c", "add!" + tran1632 "addc.c", "addc!" + tran1632 "sub.c", "sub!" + tran1632 "and.c", "and!" + tran1632 "or.c", "or!" + tran1632 "xor.c", "xor!" + tran1632 "sra.c", "sra!" + tran1632 "srl.c", "srl!" + tran1632 "sll.c", "sll!" + diff --git a/gas/testsuite/gas/score/relax.exp b/gas/testsuite/gas/score/relax.exp new file mode 100644 index 000000000000..6a8f2b838bcb --- /dev/null +++ b/gas/testsuite/gas/score/relax.exp @@ -0,0 +1,20 @@ +# test relax + +if [istarget score-*-*] then { + run_dump_test "ldi" + run_dump_test "nop" + run_dump_test "tcond" + run_dump_test "ls32ls16" + run_dump_test "ls32ls16p" + run_dump_test "postlw" + run_dump_test "presw" + run_dump_test "rD_rA_rB" + run_dump_test "bittst" + run_dump_test "addi" + run_dump_test "br" + run_dump_test "b" + run_dump_test "move" + run_dump_test "rD_rA_BN" + run_dump_test "rD_rA" +} + diff --git a/gas/testsuite/gas/score/tcond.d b/gas/testsuite/gas/score/tcond.d new file mode 100644 index 000000000000..04460cfcb0a1 --- /dev/null +++ b/gas/testsuite/gas/score/tcond.d @@ -0,0 +1,264 @@ +#as: +#objdump: -d +#source: tcond.s + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 0f05 tset! + 2: 0f05 tset! + 4: 0f05 tset! + 6: 0f05 tset! + 8: 0f05 tset! + a: 0f05 tset! + c: 8000bc54 tset + 10: 8254e010 add r18, r20, r24 + ... + 20: 0f05 tset! + 22: 0f05 tset! + 24: 0f05 tset! + 26: 0f05 tset! + 28: 8000bc54 tset + 2c: 8254e026 xor r18, r20, r24 + 30: 0005 tcs! + 32: 0005 tcs! + 34: 0005 tcs! + 36: 0005 tcs! + 38: 0005 tcs! + 3a: 0005 tcs! + 3c: 80008054 tcs + 40: 8254e010 add r18, r20, r24 + ... + 50: 0005 tcs! + 52: 0005 tcs! + 54: 0005 tcs! + 56: 0005 tcs! + 58: 80008054 tcs + 5c: 8254e026 xor r18, r20, r24 + 60: 0105 tcc! + 62: 0105 tcc! + 64: 0105 tcc! + 66: 0105 tcc! + 68: 0105 tcc! + 6a: 0105 tcc! + 6c: 80008454 tcc + 70: 8254e010 add r18, r20, r24 + ... + 80: 0105 tcc! + 82: 0105 tcc! + 84: 0105 tcc! + 86: 0105 tcc! + 88: 80008454 tcc + 8c: 8254e026 xor r18, r20, r24 + 90: 0205 tgtu! + 92: 0205 tgtu! + 94: 0205 tgtu! + 96: 0205 tgtu! + 98: 0205 tgtu! + 9a: 0205 tgtu! + 9c: 80008854 tgtu + a0: 8254e010 add r18, r20, r24 + ... + b0: 0205 tgtu! + b2: 0205 tgtu! + b4: 0205 tgtu! + b6: 0205 tgtu! + b8: 80008854 tgtu + bc: 8254e026 xor r18, r20, r24 + c0: 0305 tleu! + c2: 0305 tleu! + c4: 0305 tleu! + c6: 0305 tleu! + c8: 0305 tleu! + ca: 0305 tleu! + cc: 80008c54 tleu + d0: 8254e010 add r18, r20, r24 + ... + e0: 0305 tleu! + e2: 0305 tleu! + e4: 0305 tleu! + e6: 0305 tleu! + e8: 80008c54 tleu + ec: 8254e026 xor r18, r20, r24 + f0: 0405 teq! + f2: 0405 teq! + f4: 0405 teq! + f6: 0405 teq! + f8: 0405 teq! + fa: 0405 teq! + fc: 80009054 teq + 100: 8254e010 add r18, r20, r24 + ... + 110: 0405 teq! + 112: 0405 teq! + 114: 0405 teq! + 116: 0405 teq! + 118: 80009054 teq + 11c: 8254e026 xor r18, r20, r24 + 120: 0505 tne! + 122: 0505 tne! + 124: 0505 tne! + 126: 0505 tne! + 128: 0505 tne! + 12a: 0505 tne! + 12c: 80009454 tne + 130: 8254e010 add r18, r20, r24 + ... + 140: 0505 tne! + 142: 0505 tne! + 144: 0505 tne! + 146: 0505 tne! + 148: 80009454 tne + 14c: 8254e026 xor r18, r20, r24 + 150: 0605 tgt! + 152: 0605 tgt! + 154: 0605 tgt! + 156: 0605 tgt! + 158: 0605 tgt! + 15a: 0605 tgt! + 15c: 80009854 tgt + 160: 8254e010 add r18, r20, r24 + ... + 170: 0605 tgt! + 172: 0605 tgt! + 174: 0605 tgt! + 176: 0605 tgt! + 178: 80009854 tgt + 17c: 8254e026 xor r18, r20, r24 + 180: 0705 tle! + 182: 0705 tle! + 184: 0705 tle! + 186: 0705 tle! + 188: 0705 tle! + 18a: 0705 tle! + 18c: 80009c54 tle + 190: 8254e010 add r18, r20, r24 + ... + 1a0: 0705 tle! + 1a2: 0705 tle! + 1a4: 0705 tle! + 1a6: 0705 tle! + 1a8: 80009c54 tle + 1ac: 8254e026 xor r18, r20, r24 + 1b0: 0805 tge! + 1b2: 0805 tge! + 1b4: 0805 tge! + 1b6: 0805 tge! + 1b8: 0805 tge! + 1ba: 0805 tge! + 1bc: 8000a054 tge + 1c0: 8254e010 add r18, r20, r24 + ... + 1d0: 0805 tge! + 1d2: 0805 tge! + 1d4: 0805 tge! + 1d6: 0805 tge! + 1d8: 8000a054 tge + 1dc: 8254e026 xor r18, r20, r24 + 1e0: 0905 tlt! + 1e2: 0905 tlt! + 1e4: 0905 tlt! + 1e6: 0905 tlt! + 1e8: 0905 tlt! + 1ea: 0905 tlt! + 1ec: 8000a454 tlt + 1f0: 8254e010 add r18, r20, r24 + ... + 200: 0905 tlt! + 202: 0905 tlt! + 204: 0905 tlt! + 206: 0905 tlt! + 208: 8000a454 tlt + 20c: 8254e026 xor r18, r20, r24 + 210: 0a05 tmi! + 212: 0a05 tmi! + 214: 0a05 tmi! + 216: 0a05 tmi! + 218: 0a05 tmi! + 21a: 0a05 tmi! + 21c: 8000a854 tmi + 220: 8254e010 add r18, r20, r24 + ... + 230: 0a05 tmi! + 232: 0a05 tmi! + 234: 0a05 tmi! + 236: 0a05 tmi! + 238: 8000a854 tmi + 23c: 8254e026 xor r18, r20, r24 + 240: 0b05 tpl! + 242: 0b05 tpl! + 244: 0b05 tpl! + 246: 0b05 tpl! + 248: 0b05 tpl! + 24a: 0b05 tpl! + 24c: 8000ac54 tpl + 250: 8254e010 add r18, r20, r24 + ... + 260: 0b05 tpl! + 262: 0b05 tpl! + 264: 0b05 tpl! + 266: 0b05 tpl! + 268: 8000ac54 tpl + 26c: 8254e026 xor r18, r20, r24 + 270: 0c05 tvs! + 272: 0c05 tvs! + 274: 0c05 tvs! + 276: 0c05 tvs! + 278: 0c05 tvs! + 27a: 0c05 tvs! + 27c: 8000b054 tvs + 280: 8254e010 add r18, r20, r24 + ... + 290: 0c05 tvs! + 292: 0c05 tvs! + 294: 0c05 tvs! + 296: 0c05 tvs! + 298: 8000b054 tvs + 29c: 8254e026 xor r18, r20, r24 + 2a0: 0d05 tvc! + 2a2: 0d05 tvc! + 2a4: 0d05 tvc! + 2a6: 0d05 tvc! + 2a8: 0d05 tvc! + 2aa: 0d05 tvc! + 2ac: 8000b454 tvc + 2b0: 8254e010 add r18, r20, r24 + ... + 2c0: 0d05 tvc! + 2c2: 0d05 tvc! + 2c4: 0d05 tvc! + 2c6: 0d05 tvc! + 2c8: 8000b454 tvc + 2cc: 8254e026 xor r18, r20, r24 + 2d0: 0e05 tcnz! + 2d2: 0e05 tcnz! + 2d4: 0e05 tcnz! + 2d6: 0e05 tcnz! + 2d8: 0e05 tcnz! + 2da: 0e05 tcnz! + 2dc: 8000b854 tcnz + 2e0: 8254e010 add r18, r20, r24 + ... + 2f0: 0e05 tcnz! + 2f2: 0e05 tcnz! + 2f4: 0e05 tcnz! + 2f6: 0e05 tcnz! + 2f8: 8000b854 tcnz + 2fc: 8254e026 xor r18, r20, r24 + 300: 6062 sdbbp! 12 + 302: 6062 sdbbp! 12 + 304: 6062 sdbbp! 12 + 306: 6062 sdbbp! 12 + 308: 6062 sdbbp! 12 + 30a: 6062 sdbbp! 12 + 30c: 800c8006 sdbbp 12 + 310: 8254e010 add r18, r20, r24 + ... + 320: 6062 sdbbp! 12 + 322: 6062 sdbbp! 12 + 324: 6062 sdbbp! 12 + 326: 6062 sdbbp! 12 + 328: 800c8006 sdbbp 12 + 32c: 8254e026 xor r18, r20, r24 diff --git a/gas/testsuite/gas/score/tcond.s b/gas/testsuite/gas/score/tcond.s new file mode 100644 index 000000000000..fe89bad3a1d7 --- /dev/null +++ b/gas/testsuite/gas/score/tcond.s @@ -0,0 +1,55 @@ +/* + * test relax + * Tcond <-> Tcond! + * sdbbp <-> sdbbp! + + * Author: ligang + */ + +.macro tran insn32, insn16 +/* This block transform 32b instruction to 16b. */ +.align 4 + + \insn32 #32b -> 16b + \insn16 + + \insn32 #32b -> 16b + \insn32 #32b -> 16b + + \insn16 + \insn32 #32b -> 16b + + \insn32 #No transform + add r18, r20, r24 + +/* This block transform 16b instruction to 32b. */ +.align 4 + + \insn16 #No transform + \insn32 + + \insn16 #No transform + \insn16 + + \insn16 #16b -> 32b + xor r18, r20, r24 + +.endm + + tran "tset", "tset!" + tran "tcs", "tcs!" + tran "tcc", "tcc!" + tran "tgtu", "tgtu!" + tran "tleu", "tleu!" + tran "teq", "teq!" + tran "tne", "tne!" + tran "tgt", "tgt!" + tran "tle", "tle!" + tran "tge", "tge!" + tran "tlt", "tlt!" + tran "tmi", "tmi!" + tran "tpl", "tpl!" + tran "tvs", "tvs!" + tran "tvc", "tvc!" + tran "tcnz", "tcnz!" + tran "sdbbp 12", "sdbbp! 12" diff --git a/gas/testsuite/gas/sh/basic.exp b/gas/testsuite/gas/sh/basic.exp index 093048b87dc9..2f9424d98e6f 100644 --- a/gas/testsuite/gas/sh/basic.exp +++ b/gas/testsuite/gas/sh/basic.exp @@ -167,6 +167,8 @@ if [istarget sh*-*-*] then { # Test --allow-reg-prefix. run_dump_test "reg-prefix" + + run_dump_test "too_large" } } diff --git a/gas/testsuite/gas/sh/pcrel-coff.d b/gas/testsuite/gas/sh/pcrel-coff.d index eaca1fd7cea2..9946bf51e151 100644 --- a/gas/testsuite/gas/sh/pcrel-coff.d +++ b/gas/testsuite/gas/sh/pcrel-coff.d @@ -7,11 +7,11 @@ Disassembly of section .text: 00000000 <code>: - 0: d1 03 mov\.l 10 <litpool>,r1 ! 0xfffffff0 - 2: d1 03 mov\.l 10 <litpool>,r1 ! 0xfffffff0 + 0: d1 03 mov\.l 10 <litpool>,r1 ! fffffff0 + 2: d1 03 mov\.l 10 <litpool>,r1 ! fffffff0 4: c7 02 mova 10 <litpool>,r0 6: 61 02 mov\.l @r0,r1 - 8: d1 01 mov\.l 10 <litpool>,r1 ! 0xfffffff0 + 8: d1 01 mov\.l 10 <litpool>,r1 ! fffffff0 a: 01 03 bsrf r1 c: 00 09 nop e: 00 09 nop diff --git a/gas/testsuite/gas/sh/pcrel-hms.d b/gas/testsuite/gas/sh/pcrel-hms.d index 12df66771932..233886d88568 100644 --- a/gas/testsuite/gas/sh/pcrel-hms.d +++ b/gas/testsuite/gas/sh/pcrel-hms.d @@ -9,13 +9,13 @@ Disassembly of section .text: 00000000 <code>: - 0: d0 04 mov\.l 14 <litpool>,r0 ! 0xffffffec - 2: d1 05 mov\.l 18 <litpool\+0x4>,r1 ! 0x90009 - 4: d1 03 mov\.l 14 <litpool>,r1 ! 0xffffffec - 6: d1 03 mov\.l 14 <litpool>,r1 ! 0xffffffec + 0: d0 04 mov\.l 14 <litpool>,r0 ! ffffffec + 2: d1 05 mov\.l 18 <litpool\+0x4>,r1 ! 90009 + 4: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec + 6: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec 8: c7 02 mova 14 <litpool>,r0 a: 61 02 mov\.l @r0,r1 - c: d1 01 mov\.l 14 <litpool>,r1 ! 0xffffffec + c: d1 01 mov\.l 14 <litpool>,r1 ! ffffffec e: 01 03 bsrf r1 10: 00 09 nop 12: 00 09 nop diff --git a/gas/testsuite/gas/sh/pcrel.d b/gas/testsuite/gas/sh/pcrel.d index 9e81b60cdf8f..b9f8fcd5560c 100644 --- a/gas/testsuite/gas/sh/pcrel.d +++ b/gas/testsuite/gas/sh/pcrel.d @@ -8,13 +8,13 @@ Disassembly of section .text: 00000000 <code>: - 0: d0 04 mov\.l 14 <litpool>,r0 ! 0xffffffec + 0: d0 04 mov\.l 14 <litpool>,r0 ! ffffffec 2: d1 05 mov\.l 18 <litpool\+0x4>,r1 - 4: d1 03 mov\.l 14 <litpool>,r1 ! 0xffffffec - 6: d1 03 mov\.l 14 <litpool>,r1 ! 0xffffffec + 4: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec + 6: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec 8: c7 02 mova 14 <litpool>,r0 a: 61 02 mov\.l @r0,r1 - c: d1 01 mov\.l 14 <litpool>,r1 ! 0xffffffec + c: d1 01 mov\.l 14 <litpool>,r1 ! ffffffec e: 01 03 bsrf r1 10: 00 09 nop 12: 00 09 nop diff --git a/gas/testsuite/gas/sh/pcrel2.d b/gas/testsuite/gas/sh/pcrel2.d index 21df0aa7d2f2..519214a45c64 100644 --- a/gas/testsuite/gas/sh/pcrel2.d +++ b/gas/testsuite/gas/sh/pcrel2.d @@ -8,8 +8,8 @@ Disassembly of section \.text: 00000000 <code>: 0: 8b 01 bf 6 <foo> - 2: d0 02 mov\.l c <bar>,r0 ! 0x6 .* - 4: 90 02 mov\.w c <bar>,r0 ! 0x0 .* + 2: d0 02 mov\.l c <bar>,r0 ! 6 .* + 4: 90 02 mov\.w c <bar>,r0 ! 0 .* 00000006 <foo>: 6: af fe bra 6 <foo> diff --git a/gas/testsuite/gas/sh/pic.d b/gas/testsuite/gas/sh/pic.d index 9a2d0cecdde6..8d3e69fa69df 100644 --- a/gas/testsuite/gas/sh/pic.d +++ b/gas/testsuite/gas/sh/pic.d @@ -6,25 +6,25 @@ Disassembly of section \.text: 0x00000000 c7 0a mova 0x0000002c,r0 -0x00000002 dc 0a mov\.l 0x0000002c,r12 ! 0x0 +0x00000002 dc 0a mov\.l 0x0000002c,r12 ! 0 0x00000004 3c 0c add r0,r12 -0x00000006 d0 0a mov\.l 0x00000030,r0 ! 0x0 +0x00000006 d0 0a mov\.l 0x00000030,r0 ! 0 0x00000008 00 ce mov\.l @\(r0,r12\),r0 0x0000000a 40 0b jsr @r0 0x0000000c 00 09 nop -0x0000000e d0 09 mov\.l 0x00000034,r0 ! 0x0 +0x0000000e d0 09 mov\.l 0x00000034,r0 ! 0 0x00000010 30 cc add r12,r0 0x00000012 40 0b jsr @r0 0x00000014 00 09 nop -0x00000016 d1 08 mov\.l 0x00000038,r1 ! 0x0 +0x00000016 d1 08 mov\.l 0x00000038,r1 ! 0 0x00000018 c7 07 mova 0x00000038,r0 0x0000001a 30 1c add r1,r0 0x0000001c 40 0b jsr @r0 0x0000001e 00 09 nop -0x00000020 d0 06 mov\.l 0x0000003c,r0 ! 0x16 +0x00000020 d0 06 mov\.l 0x0000003c,r0 ! 16 0x00000022 40 0b jsr @r0 0x00000024 00 09 nop -0x00000026 d0 06 mov\.l 0x00000040,r0 ! 0x14 +0x00000026 d0 06 mov\.l 0x00000040,r0 ! 14 0x00000028 40 0b jsr @r0 0x0000002a 00 09 nop \.\.\. diff --git a/gas/testsuite/gas/sh/sh64/syntax-1.d b/gas/testsuite/gas/sh/sh64/syntax-1.d index 84a9c2552102..b48329324ad6 100644 --- a/gas/testsuite/gas/sh/sh64/syntax-1.d +++ b/gas/testsuite/gas/sh/sh64/syntax-1.d @@ -85,7 +85,7 @@ Disassembly of section .text: 104: e00107f0 prefi r0,32 0000000000000108 <.*>: - 108: 90 01 mov.w 10e <.*>,r0 ! 0x8101 + 108: 90 01 mov.w 10e <.*>,r0 ! 8101 10a: 85 01 mov.w @\(2,r0\),r0 10c: c5 01 mov.w @\(2,gbr\),r0 10e: 81 01 mov.w r0,@\(2,r0\) @@ -94,7 +94,7 @@ Disassembly of section .text: 114: 89 01 bt 11a <.*> 116: a0 01 bra 11c <.*> 118: b0 01 bsr 11e <.*> - 11a: d0 00 mov.l 11c <.*>,r0 ! 0x5001c601 + 11a: d0 00 mov.l 11c <.*>,r0 ! 5001c601 11c: 50 01 mov.l @\(4,r0\),r0 11e: c6 01 mov.l @\(4,gbr\),r0 120: c7 01 mova 128 <.*>,r0 diff --git a/gas/testsuite/gas/sh/tlsd.d b/gas/testsuite/gas/sh/tlsd.d index b4d75974c85e..055b5a7c6ece 100644 --- a/gas/testsuite/gas/sh/tlsd.d +++ b/gas/testsuite/gas/sh/tlsd.d @@ -11,12 +11,12 @@ Disassembly of section .text: 2: 2f e6 [ ]*mov\.l r14,@-r15 4: 4f 22 [ ]*sts\.l pr,@-r15 6: c7 14 [ ]*mova 58 <fn\+0x58>,r0 - 8: dc 13 [ ]*mov\.l 58 <fn\+0x58>,r12[ ]+! 0x0 .* + 8: dc 13 [ ]*mov\.l 58 <fn\+0x58>,r12[ ]+! 0 .* a: 3c 0c [ ]*add r0,r12 c: 6e f3 [ ]*mov r15,r14 - e: d4 04 [ ]*mov\.l 20 <fn\+0x20>,r4[ ]+! 0x0 .* + e: d4 04 [ ]*mov\.l 20 <fn\+0x20>,r4[ ]+! 0 .* 10: c7 04 [ ]*mova 24 <fn\+0x24>,r0 - 12: d1 04 [ ]*mov\.l 24 <fn\+0x24>,r1[ ]+! 0x0 .* + 12: d1 04 [ ]*mov\.l 24 <fn\+0x24>,r1[ ]+! 0 .* 14: 31 0c [ ]*add r0,r1 16: 41 0b [ ]*jsr @r1 18: 34 cc [ ]*add r12,r4 @@ -26,9 +26,9 @@ Disassembly of section .text: \.\.\. [ ]+20: R_SH_TLS_GD_32 foo [ ]+24: R_SH_PLT32 __tls_get_addr - 28: d4 03 [ ]*mov\.l 38 <fn\+0x38>,r4[ ]+! 0x0 .* + 28: d4 03 [ ]*mov\.l 38 <fn\+0x38>,r4[ ]+! 0 .* 2a: c7 04 [ ]*mova 3c <fn\+0x3c>,r0 - 2c: d1 03 [ ]*mov\.l 3c <fn\+0x3c>,r1[ ]+! 0x0 .* + 2c: d1 03 [ ]*mov\.l 3c <fn\+0x3c>,r1[ ]+! 0 .* 2e: 31 0c [ ]*add r0,r1 30: 41 0b [ ]*jsr @r1 32: 34 cc [ ]*add r12,r4 @@ -38,10 +38,10 @@ Disassembly of section .text: [ ]+38: R_SH_TLS_LD_32 bar [ ]+3c: R_SH_PLT32 __tls_get_addr 40: e2 01 [ ]*mov #1,r2 - 42: d1 06 [ ]*mov\.l 5c <fn\+0x5c>,r1[ ]+! 0x0 .* + 42: d1 06 [ ]*mov\.l 5c <fn\+0x5c>,r1[ ]+! 0 .* 44: 30 1c [ ]*add r1,r0 46: 20 22 [ ]*mov\.l r2,@r0 - 48: d1 05 [ ]*mov\.l 60 <fn\+0x60>,r1[ ]+! 0x0 .* + 48: d1 05 [ ]*mov\.l 60 <fn\+0x60>,r1[ ]+! 0 .* 4a: 30 1c [ ]*add r1,r0 4c: 6f e3 [ ]*mov r14,r15 4e: 4f 26 [ ]*lds\.l @r15\+,pr diff --git a/gas/testsuite/gas/sh/tlsnopic.d b/gas/testsuite/gas/sh/tlsnopic.d index 69131276ccee..739f48de879c 100644 --- a/gas/testsuite/gas/sh/tlsnopic.d +++ b/gas/testsuite/gas/sh/tlsnopic.d @@ -10,7 +10,7 @@ Disassembly of section .text: 0: 2f e6 [ ]*mov\.l r14,@-r15 2: 6e f3 [ ]*mov r15,r14 4: 01 12 [ ]*stc gbr,r1 - 6: d0 02 [ ]*mov\.l 10 <fn\+0x10>,r0[ ]+! 0x0 .* + 6: d0 02 [ ]*mov\.l 10 <fn\+0x10>,r0[ ]+! 0 .* 8: 30 1c [ ]*add r1,r0 a: 6f e3 [ ]*mov r14,r15 c: 00 0b [ ]*rts diff --git a/gas/testsuite/gas/sh/tlspic.d b/gas/testsuite/gas/sh/tlspic.d index 207ab1a2f4b2..66043ba1839e 100644 --- a/gas/testsuite/gas/sh/tlspic.d +++ b/gas/testsuite/gas/sh/tlspic.d @@ -11,9 +11,9 @@ Disassembly of section .text: 2: 2f e6 [ ]*mov\.l r14,@-r15 4: 6e f3 [ ]*mov r15,r14 6: c7 08 [ ]*mova 28 <fn\+0x28>,r0 - 8: dc 07 [ ]*mov\.l 28 <fn\+0x28>,r12[ ]+! 0x0 .* + 8: dc 07 [ ]*mov\.l 28 <fn\+0x28>,r12[ ]+! 0 .* a: 3c 0c [ ]*add r0,r12 - c: d0 02 [ ]*mov\.l 18 <fn\+0x18>,r0[ ]+! 0x0 .* + c: d0 02 [ ]*mov\.l 18 <fn\+0x18>,r0[ ]+! 0 .* e: 01 12 [ ]*stc gbr,r1 10: 00 ce [ ]*mov\.l @\(r0,r12\),r0 12: a0 03 [ ]*bra 1c <fn\+0x1c> diff --git a/gas/testsuite/gas/sh/too_large.d b/gas/testsuite/gas/sh/too_large.d new file mode 100644 index 000000000000..597e74516e01 --- /dev/null +++ b/gas/testsuite/gas/sh/too_large.d @@ -0,0 +1,9 @@ +#name: Check for bogus overflow errors in .byte directives +#as: -big -relax -isa=sh4a +#nm: -n + +[ ]*U \.L318 +[ ]*U \.L319 +[ ]*U \.L320 +[ ]*U \.L321 +0+00100 t \.L307 diff --git a/gas/testsuite/gas/sh/too_large.s b/gas/testsuite/gas/sh/too_large.s new file mode 100644 index 000000000000..b67b8f716d07 --- /dev/null +++ b/gas/testsuite/gas/sh/too_large.s @@ -0,0 +1,39 @@ + .file "too_large.c" + .text + nop + .align 8 +.L307: + .byte .L302-.L307 + .byte .L303-.L307 + .byte .L304-.L307 + .byte .L305-.L307 +.L304: + mov.l .L318,r1 + jsr @r1 + mov r8,r4 + lds r0,fpul + fsts fpul,fr1 + flds fr1,fpul + sts fpul,r0 + mov r14,r15 + lds.l @r15+,pr + mov.l @r15+,r14 + mov.l @r15+,r8 + rts + nop +.L305: + mov.l .L319,r7 + jsr @r7 + mov r8,r4 + lds r0,fpul + bra .L307 + fsts fpul,fr1 +.L303: + mov.l .L320,r6 + jsr @r6 + mov r8,r4 + lds r0,fpul + bra .L307 + fsts fpul,fr1 +.L302: + mov.l .L321,r5 diff --git a/gas/testsuite/gas/sparc/pr4587.l b/gas/testsuite/gas/sparc/pr4587.l new file mode 100644 index 000000000000..fd05091b1e27 --- /dev/null +++ b/gas/testsuite/gas/sparc/pr4587.l @@ -0,0 +1,2 @@ +.*pr4587.s: Assembler messages: +.*pr4587.s:18: Error: Illegal operands diff --git a/gas/testsuite/gas/sparc/pr4587.s b/gas/testsuite/gas/sparc/pr4587.s new file mode 100644 index 000000000000..a058c1d07a38 --- /dev/null +++ b/gas/testsuite/gas/sparc/pr4587.s @@ -0,0 +1,22 @@ + .section .data + .align 4 +zero: .single 0.0 + + .section .text + .align 4 + .global main +main: + save %sp, -96, %sp + + ! Zero-out the first FP register + set zero, %l0 + ld [%l0], %f0 + + ! Compare it to itself + ! The third reg (%f0) will cause a segfault in as + ! fcmps only takes two regs... this should be illegal operand error + fcmps %f0, %f0, %f0 + + ! Return 0 + ret + restore %g0, %g0, %o0 diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp index a2e362dbba11..876f9acf8011 100644 --- a/gas/testsuite/gas/sparc/sparc.exp +++ b/gas/testsuite/gas/sparc/sparc.exp @@ -48,6 +48,13 @@ if [istarget sparc*-*-*] { run_dump_test "pcrel64" run_dump_test "plt64" } + run_dump_test "v9branch1" + run_dump_test "v9branch2" + run_dump_test "v9branch3" + run_dump_test "v9branch4" + run_dump_test "v9branch5" + + run_list_test "pr4587" "" } if [istarget sparc-*-vxworks*] { diff --git a/gas/testsuite/gas/sparc/v9branch1.d b/gas/testsuite/gas/sparc/v9branch1.d new file mode 100644 index 000000000000..c2c05e4d88b4 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch1.d @@ -0,0 +1,23 @@ +#as: -Av9 +#objdump: -dr --prefix-addresses +#name: v9branch1 + +.*: +file format .*sparc.* + +Disassembly of section .text: +0x0+000000 brz %o0, 0x0+01fffc +0x0+000004 nop + ... +0x0+01fff8 nop +0x0+01fffc nop + ... +0x0+03fffc brz %o0, 0x0+01fffc +0x0+040000 nop +0x0+040004 bne %icc, 0x0+140000 +0x0+040008 nop + ... +0x0+13fffc nop +0x0+140000 nop + ... +0x0+240000 bne %icc, 0x0+140000 +0x0+240004 nop diff --git a/gas/testsuite/gas/sparc/v9branch1.s b/gas/testsuite/gas/sparc/v9branch1.s new file mode 100644 index 000000000000..15c4a6aecd60 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch1.s @@ -0,0 +1,18 @@ + # Check if maximum possible branch distances for v9 branches are accepted + .text + brz,pt %o0, 1f + nop + .skip (128 * 1024 - 16) + nop +1: nop + .skip (128 * 1024 - 4) + brz,pt %o0, 1b + nop + bne,pt %icc, 2f + nop + .skip (1024 * 1024 - 16) + nop +2: nop + .skip (1024 * 1024 - 4) + bne,pt %icc, 2b + nop diff --git a/gas/testsuite/gas/sparc/v9branch2.d b/gas/testsuite/gas/sparc/v9branch2.d new file mode 100644 index 000000000000..dcad03b336f5 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch2.d @@ -0,0 +1,3 @@ +#as: -Av9 +#name: v9branch2 +#error: :3:.*relocation.*overflow diff --git a/gas/testsuite/gas/sparc/v9branch2.s b/gas/testsuite/gas/sparc/v9branch2.s new file mode 100644 index 000000000000..6048a82d7b8d --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch2.s @@ -0,0 +1,7 @@ + # Text for relocation overflow diagnostic + .text + brz,pt %o0, 1f + nop + .skip (128 * 1024 - 12) + nop +1: nop diff --git a/gas/testsuite/gas/sparc/v9branch3.d b/gas/testsuite/gas/sparc/v9branch3.d new file mode 100644 index 000000000000..f8105fd70399 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch3.d @@ -0,0 +1,3 @@ +#as: -Av9 +#name: v9branch3 +#error: :5:.*relocation.*overflow diff --git a/gas/testsuite/gas/sparc/v9branch3.s b/gas/testsuite/gas/sparc/v9branch3.s new file mode 100644 index 000000000000..6bcfea08313b --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch3.s @@ -0,0 +1,6 @@ + # Text for relocation overflow diagnostic + .text +1: nop + .skip (128 * 1024) + brz,pt %o0, 1b + nop diff --git a/gas/testsuite/gas/sparc/v9branch4.d b/gas/testsuite/gas/sparc/v9branch4.d new file mode 100644 index 000000000000..4379388eb576 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch4.d @@ -0,0 +1,3 @@ +#as: -Av9 +#name: v9branch4 +#error: :3:.*relocation.*overflow diff --git a/gas/testsuite/gas/sparc/v9branch4.s b/gas/testsuite/gas/sparc/v9branch4.s new file mode 100644 index 000000000000..bf2306f34f01 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch4.s @@ -0,0 +1,7 @@ + # Text for relocation overflow diagnostic + .text + bne,pt %icc, 1f + nop + .skip (1024 * 1024 - 12) + nop +1: nop diff --git a/gas/testsuite/gas/sparc/v9branch5.d b/gas/testsuite/gas/sparc/v9branch5.d new file mode 100644 index 000000000000..937a3eacb7ec --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch5.d @@ -0,0 +1,3 @@ +#as: -Av9 +#name: v9branch5 +#error: :5:.*relocation.*overflow diff --git a/gas/testsuite/gas/sparc/v9branch5.s b/gas/testsuite/gas/sparc/v9branch5.s new file mode 100644 index 000000000000..733aa2a3ed28 --- /dev/null +++ b/gas/testsuite/gas/sparc/v9branch5.s @@ -0,0 +1,6 @@ + # Text for relocation overflow diagnostic + .text +1: nop + .skip (1024 * 1024) + bne,pt %icc, 1b + nop diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d index 3f176d13c3bd..9fb689b5d3c7 100644 --- a/gas/testsuite/gas/v850/v850e1.d +++ b/gas/testsuite/gas/v850/v850e1.d @@ -11,7 +11,7 @@ Disassembly of section .text: 0x0+04 e0 1f 40 23 [ ]*bsw sp, gp 0x0+08 05 02 [ ]*callt 5 0x0+0a e8 3f e4 00 [ ]*clr1 r7, r8 -0x0+0e f6 17 14 1b [ ]*cmov nz, 22, r2, sp +0x0+0e f6 17 14 1b [ ]*cmov nz, -10, r2, sp 0x0+12 e1 17 34 1b [ ]*cmov nz, r1, r2, sp 0x0+16 e0 07 44 01 [ ]*ctret 0x0+1a e0 07 46 01 [ ]*dbret diff --git a/gas/testsuite/gas/z8k/calr.d b/gas/testsuite/gas/z8k/calr.d index fd6f7d8293db..5ba3db904b4f 100644 --- a/gas/testsuite/gas/z8k/calr.d +++ b/gas/testsuite/gas/z8k/calr.d @@ -6,16 +6,16 @@ Disassembly of section \.text: -00000000 <label1>: +0*00000000 <label1>: 0: d803 calr 0xffc 2: d800 calr 0x1004 \.\.\. -00000ffc <label2>: +0*00000ffc <label2>: ffc: d7ff calr 0x0 ffe: 8d07 nop 1000: 8d07 nop 1002: 8d07 nop -00001004 <label3>: +0*00001004 <label3>: 1004: 8d07 nop diff --git a/gas/testsuite/gas/z8k/ctrl-names.d b/gas/testsuite/gas/z8k/ctrl-names.d index ecf004fa89bb..ae69e97749b4 100644 --- a/gas/testsuite/gas/z8k/ctrl-names.d +++ b/gas/testsuite/gas/z8k/ctrl-names.d @@ -1,12 +1,12 @@ #as: #objdump: -d -#name: jmp cc +#name: control register names .*: +file format coff-z8k Disassembly of section \.text: -00000000 <\.text>: +0*00000000 <\.text>: 0: 7d02 ldctl r0,fcw 2: 7d0a ldctl fcw,r0 4: 7d03 ldctl r0,refresh diff --git a/gas/testsuite/gas/z8k/djnz.d b/gas/testsuite/gas/z8k/djnz.d index 5b6eca73cafc..053a7d03fc28 100644 --- a/gas/testsuite/gas/z8k/djnz.d +++ b/gas/testsuite/gas/z8k/djnz.d @@ -6,14 +6,14 @@ Disassembly of section \.text: -00000000 <label1>: +0*00000000 <label1>: 0: 8d07 nop \.\.\. fa: f0fe djnz r0,0x0 fc: f87f dbjnz rl0,0x0 fe: 8d07 nop -00000100 <label2>: +0*00000100 <label2>: 100: 8d07 nop \.\.\. 1fa: f87e dbjnz rl0,0x100 diff --git a/gas/testsuite/gas/z8k/inout.d b/gas/testsuite/gas/z8k/inout.d index 0f0f772940b7..7b9696bb0290 100644 --- a/gas/testsuite/gas/z8k/inout.d +++ b/gas/testsuite/gas/z8k/inout.d @@ -6,7 +6,7 @@ Disassembly of section \.text: -00000000 <\.text>: +0*00000000 <\.text>: 0: 3b14 4444 in r1,#0x4444 4: 3a34 0123 inb rh3,#0x123 8: 3d08 in r8,@r0 diff --git a/gas/testsuite/gas/z8k/jmp-cc.d b/gas/testsuite/gas/z8k/jmp-cc.d index 012e97f7b14b..11940500ed89 100644 --- a/gas/testsuite/gas/z8k/jmp-cc.d +++ b/gas/testsuite/gas/z8k/jmp-cc.d @@ -6,7 +6,7 @@ Disassembly of section \.text: -00000000 <\.text>: +0*00000000 <\.text>: 0: e01f jr f,0x40 2: e11e jr lt,0x40 4: e21d jr le,0x40 @@ -37,7 +37,7 @@ Disassembly of section \.text: 3c: e801 jr t,0x40 3e: e800 jr t,0x40 -00000040 <dd>: +0*00000040 <dd>: 40: e8ff jr t,0x40 42: e8fe jr t,0x40 44: 8d07 nop diff --git a/gas/testsuite/gas/z8k/jr-back.d b/gas/testsuite/gas/z8k/jr-back.d index 0b80140380f6..bc244332a543 100644 --- a/gas/testsuite/gas/z8k/jr-back.d +++ b/gas/testsuite/gas/z8k/jr-back.d @@ -6,7 +6,7 @@ Disassembly of section \.text: -00000000 <start>: +0*00000000 <start>: 0: 8d07 nop \.\.\. fa: e882 jr t,0x0 diff --git a/gas/testsuite/gas/z8k/jr-forw.d b/gas/testsuite/gas/z8k/jr-forw.d index 6d2f4680f006..a0de55c96311 100644 --- a/gas/testsuite/gas/z8k/jr-forw.d +++ b/gas/testsuite/gas/z8k/jr-forw.d @@ -6,11 +6,11 @@ Disassembly of section \.text: -00000000 <.text>: +0*00000000 <.text>: 0: e87f jr t,0x100 2: e87e jr t,0x100 4: e87d jr t,0x100 \.\.\. -00000100 <dest>: +0*00000100 <dest>: 100: 8d07 nop diff --git a/gas/testsuite/gas/z8k/reglabel.d b/gas/testsuite/gas/z8k/reglabel.d new file mode 100644 index 000000000000..a16cad502eca --- /dev/null +++ b/gas/testsuite/gas/z8k/reglabel.d @@ -0,0 +1,268 @@ +#as: +#objdump: -d +#name: reglabel + +.*: +file format coff-z8k + +Disassembly of section \.text: + +0*00000000 <sp_label>: + 0: 7600 0000 lda r0,0x0 + +0*00000004 <r0_label>: + 4: 7600 0004 lda r0,0x4 + +0*00000008 <r1_label>: + 8: 7600 0008 lda r0,0x8 + +0*0000000c <r2_label>: + c: 7600 000c lda r0,0xc + +0*00000010 <r3_label>: + 10: 7600 0010 lda r0,0x10 + +0*00000014 <r4_label>: + 14: 7600 0014 lda r0,0x14 + +0*00000018 <r5_label>: + 18: 7600 0018 lda r0,0x18 + +0*0000001c <r6_label>: + 1c: 7600 001c lda r0,0x1c + +0*00000020 <r7_label>: + 20: 7600 0020 lda r0,0x20 + +0*00000024 <r8_label>: + 24: 7600 0024 lda r0,0x24 + +0*00000028 <r9_label>: + 28: 7600 0028 lda r0,0x28 + +0*0000002c <r10_label>: + 2c: 7600 002c lda r0,0x2c + +0*00000030 <r11_label>: + 30: 7600 0030 lda r0,0x30 + +0*00000034 <r12_label>: + 34: 7600 0034 lda r0,0x34 + +0*00000038 <r13_label>: + 38: 7600 0038 lda r0,0x38 + +0*0000003c <r14_label>: + 3c: 7600 003c lda r0,0x3c + +0*00000040 <r15_label>: + 40: 7600 0040 lda r0,0x40 + +0*00000044 <r16_label>: + 44: 7600 0044 lda r0,0x44 + +0*00000048 <rr0_label>: + 48: 7600 0048 lda r0,0x48 + +0*0000004c <rr1_label>: + 4c: 7600 004c lda r0,0x4c + +0*00000050 <rr2_label>: + 50: 7600 0050 lda r0,0x50 + +0*00000054 <rr3_label>: + 54: 7600 0054 lda r0,0x54 + +0*00000058 <rr4_label>: + 58: 7600 0058 lda r0,0x58 + +0*0000005c <rr5_label>: + 5c: 7600 005c lda r0,0x5c + +0*00000060 <rr6_label>: + 60: 7600 0060 lda r0,0x60 + +0*00000064 <rr7_label>: + 64: 7600 0064 lda r0,0x64 + +0*00000068 <rr8_label>: + 68: 7600 0068 lda r0,0x68 + +0*0000006c <rr9_label>: + 6c: 7600 006c lda r0,0x6c + +0*00000070 <rr10_label>: + 70: 7600 0070 lda r0,0x70 + +0*00000074 <rr11_label>: + 74: 7600 0074 lda r0,0x74 + +0*00000078 <rr12_label>: + 78: 7600 0078 lda r0,0x78 + +0*0000007c <rr13_label>: + 7c: 7600 007c lda r0,0x7c + +0*00000080 <rr14_label>: + 80: 7600 0080 lda r0,0x80 + +0*00000084 <rr15_label>: + 84: 7600 0084 lda r0,0x84 + +0*00000088 <rr16_label>: + 88: 7600 0088 lda r0,0x88 + +0*0000008c <rq0_label>: + 8c: 7600 008c lda r0,0x8c + +0*00000090 <rq1_label>: + 90: 7600 0090 lda r0,0x90 + +0*00000094 <rq2_label>: + 94: 7600 0094 lda r0,0x94 + +0*00000098 <rq3_label>: + 98: 7600 0098 lda r0,0x98 + +0*0000009c <rq4_label>: + 9c: 7600 009c lda r0,0x9c + +0*000000a0 <rq5_label>: + a0: 7600 00a0 lda r0,0xa0 + +0*000000a4 <rq6_label>: + a4: 7600 00a4 lda r0,0xa4 + +0*000000a8 <rq7_label>: + a8: 7600 00a8 lda r0,0xa8 + +0*000000ac <rq8_label>: + ac: 7600 00ac lda r0,0xac + +0*000000b0 <rq9_label>: + b0: 7600 00b0 lda r0,0xb0 + +0*000000b4 <rq10_label>: + b4: 7600 00b4 lda r0,0xb4 + +0*000000b8 <rq11_label>: + b8: 7600 00b8 lda r0,0xb8 + +0*000000bc <rq12_label>: + bc: 7600 00bc lda r0,0xbc + +0*000000c0 <rq13_label>: + c0: 7600 00c0 lda r0,0xc0 + +0*000000c4 <rq14_label>: + c4: 7600 00c4 lda r0,0xc4 + +0*000000c8 <rq15_label>: + c8: 7600 00c8 lda r0,0xc8 + +0*000000cc <rq16_label>: + cc: 7600 00cc lda r0,0xcc + +0*000000d0 <rh0_label>: + d0: 7600 00d0 lda r0,0xd0 + +0*000000d4 <rh1_label>: + d4: 7600 00d4 lda r0,0xd4 + +0*000000d8 <rh2_label>: + d8: 7600 00d8 lda r0,0xd8 + +0*000000dc <rh3_label>: + dc: 7600 00dc lda r0,0xdc + +0*000000e0 <rh4_label>: + e0: 7600 00e0 lda r0,0xe0 + +0*000000e4 <rh5_label>: + e4: 7600 00e4 lda r0,0xe4 + +0*000000e8 <rh6_label>: + e8: 7600 00e8 lda r0,0xe8 + +0*000000ec <rh7_label>: + ec: 7600 00ec lda r0,0xec + +0*000000f0 <rh8_label>: + f0: 7600 00f0 lda r0,0xf0 + +0*000000f4 <rh9_label>: + f4: 7600 00f4 lda r0,0xf4 + +0*000000f8 <rh10_label>: + f8: 7600 00f8 lda r0,0xf8 + +0*000000fc <rh11_label>: + fc: 7600 00fc lda r0,0xfc + +0*00000100 <rh12_label>: + 100: 7600 0100 lda r0,0x100 + +0*00000104 <rh13_label>: + 104: 7600 0104 lda r0,0x104 + +0*00000108 <rh14_label>: + 108: 7600 0108 lda r0,0x108 + +0*0000010c <rh15_label>: + 10c: 7600 010c lda r0,0x10c + +0*00000110 <rh16_label>: + 110: 7600 0110 lda r0,0x110 + +0*00000114 <rl0_label>: + 114: 7600 0114 lda r0,0x114 + +0*00000118 <rl1_label>: + 118: 7600 0118 lda r0,0x118 + +0*0000011c <rl2_label>: + 11c: 7600 011c lda r0,0x11c + +0*00000120 <rl3_label>: + 120: 7600 0120 lda r0,0x120 + +0*00000124 <rl4_label>: + 124: 7600 0124 lda r0,0x124 + +0*00000128 <rl5_label>: + 128: 7600 0128 lda r0,0x128 + +0*0000012c <rl6_label>: + 12c: 7600 012c lda r0,0x12c + +0*00000130 <rl7_label>: + 130: 7600 0130 lda r0,0x130 + +0*00000134 <rl8_label>: + 134: 7600 0134 lda r0,0x134 + +0*00000138 <rl9_label>: + 138: 7600 0138 lda r0,0x138 + +0*0000013c <rl10_label>: + 13c: 7600 013c lda r0,0x13c + +0*00000140 <rl11_label>: + 140: 7600 0140 lda r0,0x140 + +0*00000144 <rl12_label>: + 144: 7600 0144 lda r0,0x144 + +0*00000148 <rl13_label>: + 148: 7600 0148 lda r0,0x148 + +0*0000014c <rl14_label>: + 14c: 7600 014c lda r0,0x14c + +0*00000150 <rl15_label>: + 150: 7600 0150 lda r0,0x150 + +0*00000154 <rl16_label>: + 154: 7600 0154 lda r0,0x154 + +0*00000158 <r00_label>: + 158: 7600 0158 lda r0,0x158 diff --git a/gas/testsuite/gas/z8k/reglabel.s b/gas/testsuite/gas/z8k/reglabel.s new file mode 100644 index 000000000000..b722b14b9b6e --- /dev/null +++ b/gas/testsuite/gas/z8k/reglabel.s @@ -0,0 +1,99 @@ +! labels starting with a valid register name + +.text + +sp_label: lda r0,sp_label + +r0_label: lda r0,r0_label +r1_label: lda r0,r1_label +r2_label: lda r0,r2_label +r3_label: lda r0,r3_label +r4_label: lda r0,r4_label +r5_label: lda r0,r5_label +r6_label: lda r0,r6_label +r7_label: lda r0,r7_label +r8_label: lda r0,r8_label +r9_label: lda r0,r9_label +r10_label: lda r0,r10_label +r11_label: lda r0,r11_label +r12_label: lda r0,r12_label +r13_label: lda r0,r13_label +r14_label: lda r0,r14_label +r15_label: lda r0,r15_label +r16_label: lda r0,r16_label ! not a valid register name anyway + +rr0_label: lda r0,rr0_label +rr1_label: lda r0,rr1_label ! not a valid register name anyway +rr2_label: lda r0,rr2_label +rr3_label: lda r0,rr3_label ! not a valid register name anyway +rr4_label: lda r0,rr4_label +rr5_label: lda r0,rr5_label ! not a valid register name anyway +rr6_label: lda r0,rr6_label +rr7_label: lda r0,rr7_label ! not a valid register name anyway +rr8_label: lda r0,rr8_label +rr9_label: lda r0,rr9_label ! not a valid register name anyway +rr10_label: lda r0,rr10_label +rr11_label: lda r0,rr11_label ! not a valid register name anyway +rr12_label: lda r0,rr12_label +rr13_label: lda r0,rr13_label ! not a valid register name anyway +rr14_label: lda r0,rr14_label +rr15_label: lda r0,rr15_label ! not a valid register name anyway +rr16_label: lda r0,rr16_label ! not a valid register name anyway + +rq0_label: lda r0,rq0_label +rq1_label: lda r0,rq1_label ! not a valid register name anyway +rq2_label: lda r0,rq2_label ! not a valid register name anyway +rq3_label: lda r0,rq3_label ! not a valid register name anyway +rq4_label: lda r0,rq4_label +rq5_label: lda r0,rq5_label ! not a valid register name anyway +rq6_label: lda r0,rq6_label ! not a valid register name anyway +rq7_label: lda r0,rq7_label ! not a valid register name anyway +rq8_label: lda r0,rq8_label +rq9_label: lda r0,rq9_label ! not a valid register name anyway +rq10_label: lda r0,rq10_label ! not a valid register name anyway +rq11_label: lda r0,rq11_label ! not a valid register name anyway +rq12_label: lda r0,rq12_label +rq13_label: lda r0,rq13_label ! not a valid register name anyway +rq14_label: lda r0,rq14_label ! not a valid register name anyway +rq15_label: lda r0,rq15_label ! not a valid register name anyway +rq16_label: lda r0,rq16_label ! not a valid register name anyway + + +rh0_label: lda r0,rh0_label +rh1_label: lda r0,rh1_label +rh2_label: lda r0,rh2_label +rh3_label: lda r0,rh3_label +rh4_label: lda r0,rh4_label +rh5_label: lda r0,rh5_label +rh6_label: lda r0,rh6_label +rh7_label: lda r0,rh7_label +rh8_label: lda r0,rh8_label ! not a valid register name anyway +rh9_label: lda r0,rh9_label ! not a valid register name anyway +rh10_label: lda r0,rh10_label ! not a valid register name anyway +rh11_label: lda r0,rh11_label ! not a valid register name anyway +rh12_label: lda r0,rh12_label ! not a valid register name anyway +rh13_label: lda r0,rh13_label ! not a valid register name anyway +rh14_label: lda r0,rh14_label ! not a valid register name anyway +rh15_label: lda r0,rh15_label ! not a valid register name anyway +rh16_label: lda r0,rh16_label ! not a valid register name anyway + +rl0_label: lda r0,rl0_label +rl1_label: lda r0,rl1_label +rl2_label: lda r0,rl2_label +rl3_label: lda r0,rl3_label +rl4_label: lda r0,rl4_label +rl5_label: lda r0,rl5_label +rl6_label: lda r0,rl6_label +rl7_label: lda r0,rl7_label +rl8_label: lda r0,rl8_label ! not a valid register name anyway +rl9_label: lda r0,rl9_label ! not a valid register name anyway +rl10_label: lda r0,rl10_label ! not a valid register name anyway +rl11_label: lda r0,rl11_label ! not a valid register name anyway +rl12_label: lda r0,rl12_label ! not a valid register name anyway +rl13_label: lda r0,rl13_label ! not a valid register name anyway +rl14_label: lda r0,rl14_label ! not a valid register name anyway +rl15_label: lda r0,rl15_label ! not a valid register name anyway +rl16_label: lda r0,rl16_label ! not a valid register name anyway + +r00_label: lda r0,r00_label ! not a valid register name anyway + diff --git a/gas/testsuite/gas/z8k/ret-cc.d b/gas/testsuite/gas/z8k/ret-cc.d index 86ccc1e68f95..6b8d0c317713 100644 --- a/gas/testsuite/gas/z8k/ret-cc.d +++ b/gas/testsuite/gas/z8k/ret-cc.d @@ -1,12 +1,12 @@ #as: #objdump: -d -#name: jmp cc +#name: return on condition code .*: +file format coff-z8k Disassembly of section \.text: -00000000 <\.text>: +0*00000000 <\.text>: 0: 9e00 ret f 2: 9e01 ret lt 4: 9e02 ret le @@ -37,7 +37,7 @@ Disassembly of section \.text: 36: 9e08 ret t 38: 9e08 ret t -0000003a <dd>: +0*0000003a <dd>: 3a: e8ff jr t,0x3a 3c: e8fe jr t,0x3a 3e: 8d07 nop diff --git a/gas/testsuite/gas/z8k/z8k.exp b/gas/testsuite/gas/z8k/z8k.exp index 60cbca5776ac..3f966328faef 100644 --- a/gas/testsuite/gas/z8k/z8k.exp +++ b/gas/testsuite/gas/z8k/z8k.exp @@ -45,4 +45,8 @@ if [istarget z8k-*-*] then { # ctrl names test run_dump_test "ctrl-names" + +# labels starting with register names test + + run_dump_test "reglabel" } |